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tg3: Make tg3_alloc_rx_skb() a dst-only operation
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
123b43e9
MC		 71#define DRV_MODULE_VERSION "3.103"
72#define DRV_MODULE_RELDATE "November 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
c73430d0 943 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
a9daf367 956 return;
fcb389df
MC		 957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
a9daf367 980
bb85fbb6
MC		 981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
bb85fbb6
MC		 990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
a9daf367 993
a9daf367
MC		 994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
fcb389df 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014}
1015
158d7abd
MC		 1016static void tg3_mdio_start(struct tg3 *tp)
1017{
158d7abd
MC		 1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
a9daf367 1021
882e9793
MC		 1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
3f0e3ad7 1035 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1036
9c61d6bc
MC		 1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
158d7abd
MC		 1040}
1041
158d7abd
MC		 1042static int tg3_mdio_init(struct tg3 *tp)
1043{
1044 int i;
1045 u32 reg;
a9daf367 1046 struct phy_device *phydev;
158d7abd
MC		 1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
298cf9be
LB		 1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
158d7abd 1057
298cf9be
LB		 1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1070 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
298cf9be 1080 i = mdiobus_register(tp->mdio_bus);
a9daf367 1081 if (i) {
158d7abd
MC		 1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
9c61d6bc 1084 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1085 return i;
1086 }
158d7abd 1087
3f0e3ad7 1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1089
9c61d6bc
MC		 1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1100 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1101 break;
a9daf367 1102 case TG3_PHY_ID_BCM50610:
c73430d0 1103 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1104 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1105 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1106 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1107 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1108 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1114 /* fallthru */
1115 case TG3_PHY_ID_RTL8211C:
1116 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1117 break;
fcb389df 1118 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1119 case TG3_PHY_ID_BCMAC131:
1120 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1121 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1122 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1123 break;
1124 }
1125
9c61d6bc
MC		 1126 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129 tg3_mdio_config_5785(tp);
a9daf367
MC		 1130
1131 return 0;
158d7abd
MC		 1132}
1133
1134static void tg3_mdio_fini(struct tg3 *tp)
1135{
1136 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1138 mdiobus_unregister(tp->mdio_bus);
1139 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1140 }
1141}
1142
4ba526ce
MC		 1143/* tp->lock is held. */
1144static inline void tg3_generate_fw_event(struct tg3 *tp)
1145{
1146 u32 val;
1147
1148 val = tr32(GRC_RX_CPU_EVENT);
1149 val |= GRC_RX_CPU_DRIVER_EVENT;
1150 tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152 tp->last_event_jiffies = jiffies;
1153}
1154
1155#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
95e2869a
MC		 1157/* tp->lock is held. */
1158static void tg3_wait_for_event_ack(struct tg3 *tp)
1159{
1160 int i;
4ba526ce
MC		 1161 unsigned int delay_cnt;
1162 long time_remain;
1163
1164 /* If enough time has passed, no wait is necessary. */
1165 time_remain = (long)(tp->last_event_jiffies + 1 +
1166 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167 (long)jiffies;
1168 if (time_remain < 0)
1169 return;
1170
1171 /* Check if we can shorten the wait time. */
1172 delay_cnt = jiffies_to_usecs(time_remain);
1173 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1176
4ba526ce 1177 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1178 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179 break;
4ba526ce 1180 udelay(8);
95e2869a
MC		 1181 }
1182}
1183
1184/* tp->lock is held. */
1185static void tg3_ump_link_report(struct tg3 *tp)
1186{
1187 u32 reg;
1188 u32 val;
1189
1190 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1192 return;
1193
1194 tg3_wait_for_event_ack(tp);
1195
1196 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200 val = 0;
1201 if (!tg3_readphy(tp, MII_BMCR, &reg))
1202 val = reg << 16;
1203 if (!tg3_readphy(tp, MII_BMSR, &reg))
1204 val |= (reg & 0xffff);
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207 val = 0;
1208 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_LPA, &reg))
1211 val |= (reg & 0xffff);
1212 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214 val = 0;
1215 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217 val = reg << 16;
1218 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219 val |= (reg & 0xffff);
1220 }
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224 val = reg << 16;
1225 else
1226 val = 0;
1227 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
4ba526ce 1229 tg3_generate_fw_event(tp);
95e2869a
MC		 1230}
1231
1232static void tg3_link_report(struct tg3 *tp)
1233{
1234 if (!netif_carrier_ok(tp->dev)) {
1235 if (netif_msg_link(tp))
1236 printk(KERN_INFO PFX "%s: Link is down.\n",
1237 tp->dev->name);
1238 tg3_ump_link_report(tp);
1239 } else if (netif_msg_link(tp)) {
1240 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241 tp->dev->name,
1242 (tp->link_config.active_speed == SPEED_1000 ?
1243 1000 :
1244 (tp->link_config.active_speed == SPEED_100 ?
1245 100 : 10)),
1246 (tp->link_config.active_duplex == DUPLEX_FULL ?
1247 "full" : "half"));
1248
1249 printk(KERN_INFO PFX
1250 "%s: Flow control is %s for TX and %s for RX.\n",
1251 tp->dev->name,
e18ce346 1252 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1253 "on" : "off",
e18ce346 1254 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1255 "on" : "off");
1256 tg3_ump_link_report(tp);
1257 }
1258}
1259
1260static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261{
1262 u16 miireg;
1263
e18ce346 1264 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1265 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1266 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1267 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1268 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1269 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270 else
1271 miireg = 0;
1272
1273 return miireg;
1274}
1275
1276static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277{
1278 u16 miireg;
1279
e18ce346 1280 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1281 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1282 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1283 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1284 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1285 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286 else
1287 miireg = 0;
1288
1289 return miireg;
1290}
1291
95e2869a
MC		 1292static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293{
1294 u8 cap = 0;
1295
1296 if (lcladv & ADVERTISE_1000XPAUSE) {
1297 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1299 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1300 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1301 cap = FLOW_CTRL_RX;
95e2869a
MC		 1302 } else {
1303 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1304 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1305 }
1306 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1308 cap = FLOW_CTRL_TX;
95e2869a
MC		 1309 }
1310
1311 return cap;
1312}
1313
f51f3562 1314static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1315{
b02fd9e3 1316 u8 autoneg;
f51f3562 1317 u8 flowctrl = 0;
95e2869a
MC		 1318 u32 old_rx_mode = tp->rx_mode;
1319 u32 old_tx_mode = tp->tx_mode;
1320
b02fd9e3 1321 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1322 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1323 else
1324 autoneg = tp->link_config.autoneg;
1325
1326 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1327 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1329 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1330 else
bc02ff95 1331 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1332 } else
1333 flowctrl = tp->link_config.flowctrl;
95e2869a 1334
f51f3562 1335 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1336
e18ce346 1337 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1338 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
f51f3562 1342 if (old_rx_mode != tp->rx_mode)
95e2869a 1343 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1344
e18ce346 1345 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1346 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347 else
1348 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
f51f3562 1350 if (old_tx_mode != tp->tx_mode)
95e2869a 1351 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1352}
1353
b02fd9e3
MC		 1354static void tg3_adjust_link(struct net_device *dev)
1355{
1356 u8 oldflowctrl, linkmesg = 0;
1357 u32 mac_mode, lcl_adv, rmt_adv;
1358 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1359 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1360
24bb4fb6 1361 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1362
1363 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364 MAC_MODE_HALF_DUPLEX);
1365
1366 oldflowctrl = tp->link_config.active_flowctrl;
1367
1368 if (phydev->link) {
1369 lcl_adv = 0;
1370 rmt_adv = 0;
1371
1372 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1374 else if (phydev->speed == SPEED_1000 ||
1375 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1376 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1377 else
1378 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1379
1380 if (phydev->duplex == DUPLEX_HALF)
1381 mac_mode |= MAC_MODE_HALF_DUPLEX;
1382 else {
1383 lcl_adv = tg3_advert_flowctrl_1000T(
1384 tp->link_config.flowctrl);
1385
1386 if (phydev->pause)
1387 rmt_adv = LPA_PAUSE_CAP;
1388 if (phydev->asym_pause)
1389 rmt_adv |= LPA_PAUSE_ASYM;
1390 }
1391
1392 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393 } else
1394 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396 if (mac_mode != tp->mac_mode) {
1397 tp->mac_mode = mac_mode;
1398 tw32_f(MAC_MODE, tp->mac_mode);
1399 udelay(40);
1400 }
1401
fcb389df
MC		 1402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403 if (phydev->speed == SPEED_10)
1404 tw32(MAC_MI_STAT,
1405 MAC_MI_STAT_10MBPS_MODE |
1406 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407 else
1408 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409 }
1410
b02fd9e3
MC		 1411 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412 tw32(MAC_TX_LENGTHS,
1413 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414 (6 << TX_LENGTHS_IPG_SHIFT) |
1415 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416 else
1417 tw32(MAC_TX_LENGTHS,
1418 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419 (6 << TX_LENGTHS_IPG_SHIFT) |
1420 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424 phydev->speed != tp->link_config.active_speed ||
1425 phydev->duplex != tp->link_config.active_duplex ||
1426 oldflowctrl != tp->link_config.active_flowctrl)
1427 linkmesg = 1;
1428
1429 tp->link_config.active_speed = phydev->speed;
1430 tp->link_config.active_duplex = phydev->duplex;
1431
24bb4fb6 1432 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1433
1434 if (linkmesg)
1435 tg3_link_report(tp);
1436}
1437
1438static int tg3_phy_init(struct tg3 *tp)
1439{
1440 struct phy_device *phydev;
1441
1442 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443 return 0;
1444
1445 /* Bring the PHY back to a known state. */
1446 tg3_bmcr_reset(tp);
1447
3f0e3ad7 1448 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1449
1450 /* Attach the MAC to the PHY. */
fb28ad35 1451 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1452 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1453 if (IS_ERR(phydev)) {
1454 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455 return PTR_ERR(phydev);
1456 }
1457
b02fd9e3 1458 /* Mask with MAC supported features. */
9c61d6bc
MC		 1459 switch (phydev->interface) {
1460 case PHY_INTERFACE_MODE_GMII:
1461 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1462 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463 phydev->supported &= (PHY_GBIT_FEATURES |
1464 SUPPORTED_Pause |
1465 SUPPORTED_Asym_Pause);
1466 break;
1467 }
1468 /* fallthru */
9c61d6bc
MC		 1469 case PHY_INTERFACE_MODE_MII:
1470 phydev->supported &= (PHY_BASIC_FEATURES |
1471 SUPPORTED_Pause |
1472 SUPPORTED_Asym_Pause);
1473 break;
1474 default:
3f0e3ad7 1475 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1476 return -EINVAL;
1477 }
1478
1479 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1480
1481 phydev->advertising = phydev->supported;
1482
b02fd9e3
MC		 1483 return 0;
1484}
1485
1486static void tg3_phy_start(struct tg3 *tp)
1487{
1488 struct phy_device *phydev;
1489
1490 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491 return;
1492
3f0e3ad7 1493 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1494
1495 if (tp->link_config.phy_is_low_power) {
1496 tp->link_config.phy_is_low_power = 0;
1497 phydev->speed = tp->link_config.orig_speed;
1498 phydev->duplex = tp->link_config.orig_duplex;
1499 phydev->autoneg = tp->link_config.orig_autoneg;
1500 phydev->advertising = tp->link_config.orig_advertising;
1501 }
1502
1503 phy_start(phydev);
1504
1505 phy_start_aneg(phydev);
1506}
1507
1508static void tg3_phy_stop(struct tg3 *tp)
1509{
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511 return;
1512
3f0e3ad7 1513 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1514}
1515
1516static void tg3_phy_fini(struct tg3 *tp)
1517{
1518 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1519 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1520 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521 }
1522}
1523
b2a5c19c
MC		 1524static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525{
1526 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528}
1529
7f97a4bd
MC		 1530static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531{
1532 u32 phytest;
1533
1534 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535 u32 phy;
1536
1537 tg3_writephy(tp, MII_TG3_FET_TEST,
1538 phytest | MII_TG3_FET_SHADOW_EN);
1539 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540 if (enable)
1541 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542 else
1543 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545 }
1546 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547 }
1548}
1549
6833c043
MC		 1550static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551{
1552 u32 reg;
1553
7f97a4bd 1554 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1555 return;
1556
7f97a4bd
MC		 1557 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558 tg3_phy_fet_toggle_apd(tp, enable);
1559 return;
1560 }
1561
6833c043
MC		 1562 reg = MII_TG3_MISC_SHDW_WREN |
1563 MII_TG3_MISC_SHDW_SCR5_SEL |
1564 MII_TG3_MISC_SHDW_SCR5_LPED |
1565 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566 MII_TG3_MISC_SHDW_SCR5_SDTL |
1567 MII_TG3_MISC_SHDW_SCR5_C125OE;
1568 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574 reg = MII_TG3_MISC_SHDW_WREN |
1575 MII_TG3_MISC_SHDW_APD_SEL |
1576 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577 if (enable)
1578 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581}
1582
9ef8ca99
MC		 1583static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584{
1585 u32 phy;
1586
1587 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589 return;
1590
7f97a4bd 1591 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1592 u32 ephy;
1593
535ef6e1
MC		 1594 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597 tg3_writephy(tp, MII_TG3_FET_TEST,
1598 ephy | MII_TG3_FET_SHADOW_EN);
1599 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1600 if (enable)
535ef6e1 1601 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1602 else
535ef6e1
MC		 1603 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604 tg3_writephy(tp, reg, phy);
9ef8ca99 1605 }
535ef6e1 1606 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1607 }
1608 } else {
1609 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610 MII_TG3_AUXCTL_SHDWSEL_MISC;
1611 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613 if (enable)
1614 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615 else
1616 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617 phy |= MII_TG3_AUXCTL_MISC_WREN;
1618 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619 }
1620 }
1621}
1622
1da177e4
LT		 1623static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624{
1625 u32 val;
1626
1627 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628 return;
1629
1630 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633 (val | (1 << 15) | (1 << 4)));
1634}
1635
b2a5c19c
MC		 1636static void tg3_phy_apply_otp(struct tg3 *tp)
1637{
1638 u32 otp, phy;
1639
1640 if (!tp->phy_otp)
1641 return;
1642
1643 otp = tp->phy_otp;
1644
1645 /* Enable SM_DSP clock and tx 6dB coding. */
1646 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648 MII_TG3_AUXCTL_ACTL_TX_6DB;
1649 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673 /* Turn off SM_DSP clock. */
1674 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675 MII_TG3_AUXCTL_ACTL_TX_6DB;
1676 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677}
1678
1da177e4
LT		 1679static int tg3_wait_macro_done(struct tg3 *tp)
1680{
1681 int limit = 100;
1682
1683 while (limit--) {
1684 u32 tmp32;
1685
1686 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687 if ((tmp32 & 0x1000) == 0)
1688 break;
1689 }
1690 }
d4675b52 1691 if (limit < 0)
1da177e4
LT		 1692 return -EBUSY;
1693
1694 return 0;
1695}
1696
1697static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698{
1699 static const u32 test_pat[4][6] = {
1700 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704 };
1705 int chan;
1706
1707 for (chan = 0; chan < 4; chan++) {
1708 int i;
1709
1710 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711 (chan * 0x2000) | 0x0200);
1712 tg3_writephy(tp, 0x16, 0x0002);
1713
1714 for (i = 0; i < 6; i++)
1715 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716 test_pat[chan][i]);
1717
1718 tg3_writephy(tp, 0x16, 0x0202);
1719 if (tg3_wait_macro_done(tp)) {
1720 *resetp = 1;
1721 return -EBUSY;
1722 }
1723
1724 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725 (chan * 0x2000) | 0x0200);
1726 tg3_writephy(tp, 0x16, 0x0082);
1727 if (tg3_wait_macro_done(tp)) {
1728 *resetp = 1;
1729 return -EBUSY;
1730 }
1731
1732 tg3_writephy(tp, 0x16, 0x0802);
1733 if (tg3_wait_macro_done(tp)) {
1734 *resetp = 1;
1735 return -EBUSY;
1736 }
1737
1738 for (i = 0; i < 6; i += 2) {
1739 u32 low, high;
1740
1741 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743 tg3_wait_macro_done(tp)) {
1744 *resetp = 1;
1745 return -EBUSY;
1746 }
1747 low &= 0x7fff;
1748 high &= 0x000f;
1749 if (low != test_pat[chan][i] ||
1750 high != test_pat[chan][i+1]) {
1751 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755 return -EBUSY;
1756 }
1757 }
1758 }
1759
1760 return 0;
1761}
1762
1763static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764{
1765 int chan;
1766
1767 for (chan = 0; chan < 4; chan++) {
1768 int i;
1769
1770 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771 (chan * 0x2000) | 0x0200);
1772 tg3_writephy(tp, 0x16, 0x0002);
1773 for (i = 0; i < 6; i++)
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775 tg3_writephy(tp, 0x16, 0x0202);
1776 if (tg3_wait_macro_done(tp))
1777 return -EBUSY;
1778 }
1779
1780 return 0;
1781}
1782
1783static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784{
1785 u32 reg32, phy9_orig;
1786 int retries, do_phy_reset, err;
1787
1788 retries = 10;
1789 do_phy_reset = 1;
1790 do {
1791 if (do_phy_reset) {
1792 err = tg3_bmcr_reset(tp);
1793 if (err)
1794 return err;
1795 do_phy_reset = 0;
1796 }
1797
1798 /* Disable transmitter and interrupt. */
1799 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800 continue;
1801
1802 reg32 |= 0x3000;
1803 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805 /* Set full-duplex, 1000 mbps. */
1806 tg3_writephy(tp, MII_BMCR,
1807 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809 /* Set to master mode. */
1810 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811 continue;
1812
1813 tg3_writephy(tp, MII_TG3_CTRL,
1814 (MII_TG3_CTRL_AS_MASTER |
1815 MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817 /* Enable SM_DSP_CLOCK and 6dB. */
1818 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820 /* Block the PHY control access. */
1821 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825 if (!err)
1826 break;
1827 } while (--retries);
1828
1829 err = tg3_phy_reset_chanpat(tp);
1830 if (err)
1831 return err;
1832
1833 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837 tg3_writephy(tp, 0x16, 0x0000);
1838
1839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841 /* Set Extended packet length bit for jumbo frames */
1842 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843 }
1844 else {
1845 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846 }
1847
1848 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851 reg32 &= ~0x3000;
1852 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853 } else if (!err)
1854 err = -EBUSY;
1855
1856 return err;
1857}
1858
1859/* This will reset the tigon3 PHY if there is no valid
1860 * link unless the FORCE argument is non-zero.
1861 */
1862static int tg3_phy_reset(struct tg3 *tp)
1863{
b2a5c19c 1864 u32 cpmuctrl;
1da177e4
LT		 1865 u32 phy_status;
1866 int err;
1867
60189ddf
MC		 1868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869 u32 val;
1870
1871 val = tr32(GRC_MISC_CFG);
1872 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873 udelay(40);
1874 }
1da177e4
LT		 1875 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1876 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877 if (err != 0)
1878 return -EBUSY;
1879
c8e1e82b
MC		 1880 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881 netif_carrier_off(tp->dev);
1882 tg3_link_report(tp);
1883 }
1884
1da177e4
LT		 1885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888 err = tg3_phy_reset_5703_4_5(tp);
1889 if (err)
1890 return err;
1891 goto out;
1892 }
1893
b2a5c19c
MC		 1894 cpmuctrl = 0;
1895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899 tw32(TG3_CPMU_CTRL,
1900 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901 }
1902
1da177e4
LT		 1903 err = tg3_bmcr_reset(tp);
1904 if (err)
1905 return err;
1906
b2a5c19c
MC		 1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908 u32 phy;
1909
1910 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914 }
1915
bcb37f6c
MC		 1916 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1918 u32 val;
1919
1920 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922 CPMU_LSPD_1000MB_MACCLK_12_5) {
1923 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924 udelay(40);
1925 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926 }
1927 }
1928
b2a5c19c
MC		 1929 tg3_phy_apply_otp(tp);
1930
6833c043
MC		 1931 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932 tg3_phy_toggle_apd(tp, true);
1933 else
1934 tg3_phy_toggle_apd(tp, false);
1935
1da177e4
LT		 1936out:
1937 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944 }
1945 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946 tg3_writephy(tp, 0x1c, 0x8d68);
1947 tg3_writephy(tp, 0x1c, 0x8d68);
1948 }
1949 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
c424cb24
MC		 1959 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1962 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964 tg3_writephy(tp, MII_TG3_TEST1,
1965 MII_TG3_TEST1_TRIM_EN | 0x4);
1966 } else
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969 }
1da177e4
LT		 1970 /* Set Extended packet length bit (bit 14) on all chips that */
1971 /* support jumbo frames */
1972 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973 /* Cannot do read-modify-write on 5401 */
1974 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1975 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1976 u32 phy_reg;
1977
1978 /* Set bit 14 with read-modify-write to preserve other bits */
1979 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982 }
1983
1984 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985 * jumbo frames transmission.
1986 */
8f666b07 1987 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1988 u32 phy_reg;
1989
1990 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993 }
1994
715116a1 1995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1996 /* adjust output voltage */
535ef6e1 1997 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1998 }
1999
9ef8ca99 2000 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2001 tg3_phy_set_wirespeed(tp);
2002 return 0;
2003}
2004
2005static void tg3_frob_aux_power(struct tg3 *tp)
2006{
2007 struct tg3 *tp_peer = tp;
2008
9d26e213 2009 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2010 return;
2011
f6eb9b1f
MC		 2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2015 struct net_device *dev_peer;
2016
2017 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2018 /* remove_one() may have been run on the peer. */
8c2dc7e1 2019 if (!dev_peer)
bc1c7567
MC		 2020 tp_peer = tp;
2021 else
2022 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2023 }
2024
1da177e4 2025 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2026 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2031 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032 (GRC_LCLCTRL_GPIO_OE0 |
2033 GRC_LCLCTRL_GPIO_OE1 |
2034 GRC_LCLCTRL_GPIO_OE2 |
2035 GRC_LCLCTRL_GPIO_OUTPUT0 |
2036 GRC_LCLCTRL_GPIO_OUTPUT1),
2037 100);
8d519ab2
MC		 2038 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2040 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1 |
2046 tp->grc_local_ctrl;
2047 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2054 } else {
2055 u32 no_gpio2;
dc56b7d4 2056 u32 grc_local_ctrl = 0;
1da177e4
LT		 2057
2058 if (tp_peer != tp &&
2059 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060 return;
2061
dc56b7d4
MC		 2062 /* Workaround to prevent overdrawing Amps. */
2063 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064 ASIC_REV_5714) {
2065 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 grc_local_ctrl, 100);
dc56b7d4
MC		 2068 }
2069
1da177e4
LT		 2070 /* On 5753 and variants, GPIO2 cannot be used. */
2071 no_gpio2 = tp->nic_sram_data_cfg &
2072 NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
dc56b7d4 2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2075 GRC_LCLCTRL_GPIO_OE1 |
2076 GRC_LCLCTRL_GPIO_OE2 |
2077 GRC_LCLCTRL_GPIO_OUTPUT1 |
2078 GRC_LCLCTRL_GPIO_OUTPUT2;
2079 if (no_gpio2) {
2080 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081 GRC_LCLCTRL_GPIO_OUTPUT2);
2082 }
b401e9e2
MC		 2083 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084 grc_local_ctrl, 100);
1da177e4
LT		 2085
2086 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
b401e9e2
MC		 2088 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089 grc_local_ctrl, 100);
1da177e4
LT		 2090
2091 if (!no_gpio2) {
2092 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 grc_local_ctrl, 100);
1da177e4
LT		 2095 }
2096 }
2097 } else {
2098 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100 if (tp_peer != tp &&
2101 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102 return;
2103
b401e9e2
MC		 2104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105 (GRC_LCLCTRL_GPIO_OE1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2107
b401e9e2
MC		 2108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2110
b401e9e2
MC		 2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 (GRC_LCLCTRL_GPIO_OE1 |
2113 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2114 }
2115 }
2116}
2117
e8f3f6ca
MC		 2118static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119{
2120 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121 return 1;
2122 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123 if (speed != SPEED_10)
2124 return 1;
2125 } else if (speed == SPEED_10)
2126 return 1;
2127
2128 return 0;
2129}
2130
1da177e4
LT		 2131static int tg3_setup_phy(struct tg3 *, int);
2132
2133#define RESET_KIND_SHUTDOWN 0
2134#define RESET_KIND_INIT 1
2135#define RESET_KIND_SUSPEND 2
2136
2137static void tg3_write_sig_post_reset(struct tg3 *, int);
2138static int tg3_halt_cpu(struct tg3 *, u32);
2139
0a459aac 2140static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2141{
ce057f01
MC		 2142 u32 val;
2143
5129724a
MC		 2144 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149 sg_dig_ctrl |=
2150 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153 }
3f7045c1 2154 return;
5129724a 2155 }
3f7045c1 2156
60189ddf 2157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2158 tg3_bmcr_reset(tp);
2159 val = tr32(GRC_MISC_CFG);
2160 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161 udelay(40);
2162 return;
0e5f784c
MC		 2163 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164 u32 phytest;
2165 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166 u32 phy;
2167
2168 tg3_writephy(tp, MII_ADVERTISE, 0);
2169 tg3_writephy(tp, MII_BMCR,
2170 BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172 tg3_writephy(tp, MII_TG3_FET_TEST,
2173 phytest | MII_TG3_FET_SHADOW_EN);
2174 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176 tg3_writephy(tp,
2177 MII_TG3_FET_SHDW_AUXMODE4,
2178 phy);
2179 }
2180 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181 }
2182 return;
0a459aac 2183 } else if (do_low_power) {
715116a1
MC		 2184 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2186
2187 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2192 }
3f7045c1 2193
15c3b696
MC		 2194 /* The PHY should not be powered down on some chips because
2195 * of bugs.
2196 */
2197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201 return;
ce057f01 2202
bcb37f6c
MC		 2203 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2205 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209 }
2210
15c3b696
MC		 2211 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212}
2213
ffbcfed4
MC		 2214/* tp->lock is held. */
2215static int tg3_nvram_lock(struct tg3 *tp)
2216{
2217 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218 int i;
2219
2220 if (tp->nvram_lock_cnt == 0) {
2221 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222 for (i = 0; i < 8000; i++) {
2223 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224 break;
2225 udelay(20);
2226 }
2227 if (i == 8000) {
2228 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229 return -ENODEV;
2230 }
2231 }
2232 tp->nvram_lock_cnt++;
2233 }
2234 return 0;
2235}
2236
2237/* tp->lock is held. */
2238static void tg3_nvram_unlock(struct tg3 *tp)
2239{
2240 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241 if (tp->nvram_lock_cnt > 0)
2242 tp->nvram_lock_cnt--;
2243 if (tp->nvram_lock_cnt == 0)
2244 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245 }
2246}
2247
2248/* tp->lock is held. */
2249static void tg3_enable_nvram_access(struct tg3 *tp)
2250{
2251 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2252 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2253 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256 }
2257}
2258
2259/* tp->lock is held. */
2260static void tg3_disable_nvram_access(struct tg3 *tp)
2261{
2262 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2263 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2264 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267 }
2268}
2269
2270static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271 u32 offset, u32 *val)
2272{
2273 u32 tmp;
2274 int i;
2275
2276 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277 return -EINVAL;
2278
2279 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280 EEPROM_ADDR_DEVID_MASK |
2281 EEPROM_ADDR_READ);
2282 tw32(GRC_EEPROM_ADDR,
2283 tmp |
2284 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286 EEPROM_ADDR_ADDR_MASK) |
2287 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289 for (i = 0; i < 1000; i++) {
2290 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292 if (tmp & EEPROM_ADDR_COMPLETE)
2293 break;
2294 msleep(1);
2295 }
2296 if (!(tmp & EEPROM_ADDR_COMPLETE))
2297 return -EBUSY;
2298
62cedd11
MC		 2299 tmp = tr32(GRC_EEPROM_DATA);
2300
2301 /*
2302 * The data will always be opposite the native endian
2303 * format. Perform a blind byteswap to compensate.
2304 */
2305 *val = swab32(tmp);
2306
ffbcfed4
MC		 2307 return 0;
2308}
2309
2310#define NVRAM_CMD_TIMEOUT 10000
2311
2312static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313{
2314 int i;
2315
2316 tw32(NVRAM_CMD, nvram_cmd);
2317 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318 udelay(10);
2319 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320 udelay(10);
2321 break;
2322 }
2323 }
2324
2325 if (i == NVRAM_CMD_TIMEOUT)
2326 return -EBUSY;
2327
2328 return 0;
2329}
2330
2331static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332{
2333 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337 (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339 addr = ((addr / tp->nvram_pagesize) <<
2340 ATMEL_AT45DB0X1B_PAGE_POS) +
2341 (addr % tp->nvram_pagesize);
2342
2343 return addr;
2344}
2345
2346static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347{
2348 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352 (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355 tp->nvram_pagesize) +
2356 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358 return addr;
2359}
2360
e4f34110
MC		 2361/* NOTE: Data read in from NVRAM is byteswapped according to
2362 * the byteswapping settings for all other register accesses.
2363 * tg3 devices are BE devices, so on a BE machine, the data
2364 * returned will be exactly as it is seen in NVRAM. On a LE
2365 * machine, the 32-bit value will be byteswapped.
2366 */
ffbcfed4
MC		 2367static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368{
2369 int ret;
2370
2371 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374 offset = tg3_nvram_phys_addr(tp, offset);
2375
2376 if (offset > NVRAM_ADDR_MSK)
2377 return -EINVAL;
2378
2379 ret = tg3_nvram_lock(tp);
2380 if (ret)
2381 return ret;
2382
2383 tg3_enable_nvram_access(tp);
2384
2385 tw32(NVRAM_ADDR, offset);
2386 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389 if (ret == 0)
e4f34110 2390 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2391
2392 tg3_disable_nvram_access(tp);
2393
2394 tg3_nvram_unlock(tp);
2395
2396 return ret;
2397}
2398
a9dc529d
MC		 2399/* Ensures NVRAM data is in bytestream format. */
2400static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2401{
2402 u32 v;
a9dc529d 2403 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2404 if (!res)
a9dc529d 2405 *val = cpu_to_be32(v);
ffbcfed4
MC		 2406 return res;
2407}
2408
3f007891
MC		 2409/* tp->lock is held. */
2410static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411{
2412 u32 addr_high, addr_low;
2413 int i;
2414
2415 addr_high = ((tp->dev->dev_addr[0] << 8) |
2416 tp->dev->dev_addr[1]);
2417 addr_low = ((tp->dev->dev_addr[2] << 24) |
2418 (tp->dev->dev_addr[3] << 16) |
2419 (tp->dev->dev_addr[4] << 8) |
2420 (tp->dev->dev_addr[5] << 0));
2421 for (i = 0; i < 4; i++) {
2422 if (i == 1 && skip_mac_1)
2423 continue;
2424 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426 }
2427
2428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430 for (i = 0; i < 12; i++) {
2431 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433 }
2434 }
2435
2436 addr_high = (tp->dev->dev_addr[0] +
2437 tp->dev->dev_addr[1] +
2438 tp->dev->dev_addr[2] +
2439 tp->dev->dev_addr[3] +
2440 tp->dev->dev_addr[4] +
2441 tp->dev->dev_addr[5]) &
2442 TX_BACKOFF_SEED_MASK;
2443 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444}
2445
bc1c7567 2446static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2447{
2448 u32 misc_host_ctrl;
0a459aac 2449 bool device_should_wake, do_low_power;
1da177e4
LT		 2450
2451 /* Make sure register accesses (indirect or otherwise)
2452 * will function correctly.
2453 */
2454 pci_write_config_dword(tp->pdev,
2455 TG3PCI_MISC_HOST_CTRL,
2456 tp->misc_host_ctrl);
2457
1da177e4 2458 switch (state) {
bc1c7567 2459 case PCI_D0:
12dac075
RW		 2460 pci_enable_wake(tp->pdev, state, false);
2461 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2462
9d26e213
MC		 2463 /* Switch out of Vaux if it is a NIC */
2464 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2465 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2466
2467 return 0;
2468
bc1c7567 2469 case PCI_D1:
bc1c7567 2470 case PCI_D2:
bc1c7567 2471 case PCI_D3hot:
1da177e4
LT		 2472 break;
2473
2474 default:
12dac075
RW		 2475 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476 tp->dev->name, state);
1da177e4 2477 return -EINVAL;
855e1111 2478 }
5e7dfd0f
MC		 2479
2480 /* Restore the CLKREQ setting. */
2481 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482 u16 lnkctl;
2483
2484 pci_read_config_word(tp->pdev,
2485 tp->pcie_cap + PCI_EXP_LNKCTL,
2486 &lnkctl);
2487 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488 pci_write_config_word(tp->pdev,
2489 tp->pcie_cap + PCI_EXP_LNKCTL,
2490 lnkctl);
2491 }
2492
1da177e4
LT		 2493 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494 tw32(TG3PCI_MISC_HOST_CTRL,
2495 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
05ac4cb7
MC		 2497 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498 device_may_wakeup(&tp->pdev->dev) &&
2499 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
dd477003 2501 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2502 do_low_power = false;
b02fd9e3
MC		 2503 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504 !tp->link_config.phy_is_low_power) {
2505 struct phy_device *phydev;
0a459aac 2506 u32 phyid, advertising;
b02fd9e3 2507
3f0e3ad7 2508 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2509
2510 tp->link_config.phy_is_low_power = 1;
2511
2512 tp->link_config.orig_speed = phydev->speed;
2513 tp->link_config.orig_duplex = phydev->duplex;
2514 tp->link_config.orig_autoneg = phydev->autoneg;
2515 tp->link_config.orig_advertising = phydev->advertising;
2516
2517 advertising = ADVERTISED_TP |
2518 ADVERTISED_Pause |
2519 ADVERTISED_Autoneg |
2520 ADVERTISED_10baseT_Half;
2521
2522 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2523 device_should_wake) {
b02fd9e3
MC		 2524 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525 advertising |=
2526 ADVERTISED_100baseT_Half |
2527 ADVERTISED_100baseT_Full |
2528 ADVERTISED_10baseT_Full;
2529 else
2530 advertising |= ADVERTISED_10baseT_Full;
2531 }
2532
2533 phydev->advertising = advertising;
2534
2535 phy_start_aneg(phydev);
0a459aac
MC		 2536
2537 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538 if (phyid != TG3_PHY_ID_BCMAC131) {
2539 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2540 if (phyid == TG3_PHY_OUI_1 ||
2541 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2542 phyid == TG3_PHY_OUI_3)
2543 do_low_power = true;
2544 }
b02fd9e3 2545 }
dd477003 2546 } else {
2023276e 2547 do_low_power = true;
0a459aac 2548
dd477003
MC		 2549 if (tp->link_config.phy_is_low_power == 0) {
2550 tp->link_config.phy_is_low_power = 1;
2551 tp->link_config.orig_speed = tp->link_config.speed;
2552 tp->link_config.orig_duplex = tp->link_config.duplex;
2553 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554 }
1da177e4 2555
dd477003
MC		 2556 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557 tp->link_config.speed = SPEED_10;
2558 tp->link_config.duplex = DUPLEX_HALF;
2559 tp->link_config.autoneg = AUTONEG_ENABLE;
2560 tg3_setup_phy(tp, 0);
2561 }
1da177e4
LT		 2562 }
2563
b5d3772c
MC		 2564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565 u32 val;
2566
2567 val = tr32(GRC_VCPU_EXT_CTRL);
2568 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2570 int i;
2571 u32 val;
2572
2573 for (i = 0; i < 200; i++) {
2574 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576 break;
2577 msleep(1);
2578 }
2579 }
a85feb8c
GZ		 2580 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582 WOL_DRV_STATE_SHUTDOWN |
2583 WOL_DRV_WOL |
2584 WOL_SET_MAGIC_PKT);
6921d201 2585
05ac4cb7 2586 if (device_should_wake) {
1da177e4
LT		 2587 u32 mac_mode;
2588
2589 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2590 if (do_low_power) {
dd477003
MC		 2591 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592 udelay(40);
2593 }
1da177e4 2594
3f7045c1
MC		 2595 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597 else
2598 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2599
e8f3f6ca
MC		 2600 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602 ASIC_REV_5700) {
2603 u32 speed = (tp->tg3_flags &
2604 TG3_FLAG_WOL_SPEED_100MB) ?
2605 SPEED_100 : SPEED_10;
2606 if (tg3_5700_link_polarity(tp, speed))
2607 mac_mode |= MAC_MODE_LINK_POLARITY;
2608 else
2609 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610 }
1da177e4
LT		 2611 } else {
2612 mac_mode = MAC_MODE_PORT_MODE_TBI;
2613 }
2614
cbf46853 2615 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2616 tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
05ac4cb7
MC		 2618 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2624
3bda1258
MC		 2625 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626 mac_mode |= tp->mac_mode &
2627 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628 if (mac_mode & MAC_MODE_APE_TX_EN)
2629 mac_mode |= MAC_MODE_TDE_ENABLE;
2630 }
2631
1da177e4
LT		 2632 tw32_f(MAC_MODE, mac_mode);
2633 udelay(100);
2634
2635 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636 udelay(10);
2637 }
2638
2639 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642 u32 base_val;
2643
2644 base_val = tp->pci_clock_ctrl;
2645 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646 CLOCK_CTRL_TXCLK_DISABLE);
2647
b401e9e2
MC		 2648 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2650 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2651 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2652 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2653 /* do nothing */
85e94ced 2654 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2655 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656 u32 newbits1, newbits2;
2657
2658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661 CLOCK_CTRL_TXCLK_DISABLE |
2662 CLOCK_CTRL_ALTCLK);
2663 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665 newbits1 = CLOCK_CTRL_625_CORE;
2666 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667 } else {
2668 newbits1 = CLOCK_CTRL_ALTCLK;
2669 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670 }
2671
b401e9e2
MC		 2672 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673 40);
1da177e4 2674
b401e9e2
MC		 2675 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676 40);
1da177e4
LT		 2677
2678 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679 u32 newbits3;
2680
2681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684 CLOCK_CTRL_TXCLK_DISABLE |
2685 CLOCK_CTRL_44MHZ_CORE);
2686 } else {
2687 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688 }
2689
b401e9e2
MC		 2690 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2692 }
2693 }
2694
05ac4cb7 2695 if (!(device_should_wake) &&
22435849 2696 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2697 tg3_power_down_phy(tp, do_low_power);
6921d201 2698
1da177e4
LT		 2699 tg3_frob_aux_power(tp);
2700
2701 /* Workaround for unstable PLL clock */
2702 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704 u32 val = tr32(0x7d00);
2705
2706 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707 tw32(0x7d00, val);
6921d201 2708 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2709 int err;
2710
2711 err = tg3_nvram_lock(tp);
1da177e4 2712 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2713 if (!err)
2714 tg3_nvram_unlock(tp);
6921d201 2715 }
1da177e4
LT		 2716 }
2717
bbadf503
MC		 2718 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
05ac4cb7 2720 if (device_should_wake)
12dac075
RW		 2721 pci_enable_wake(tp->pdev, state, true);
2722
1da177e4 2723 /* Finally, set the new power state. */
12dac075 2724 pci_set_power_state(tp->pdev, state);
1da177e4 2725
1da177e4
LT		 2726 return 0;
2727}
2728
1da177e4
LT		 2729static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730{
2731 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732 case MII_TG3_AUX_STAT_10HALF:
2733 *speed = SPEED_10;
2734 *duplex = DUPLEX_HALF;
2735 break;
2736
2737 case MII_TG3_AUX_STAT_10FULL:
2738 *speed = SPEED_10;
2739 *duplex = DUPLEX_FULL;
2740 break;
2741
2742 case MII_TG3_AUX_STAT_100HALF:
2743 *speed = SPEED_100;
2744 *duplex = DUPLEX_HALF;
2745 break;
2746
2747 case MII_TG3_AUX_STAT_100FULL:
2748 *speed = SPEED_100;
2749 *duplex = DUPLEX_FULL;
2750 break;
2751
2752 case MII_TG3_AUX_STAT_1000HALF:
2753 *speed = SPEED_1000;
2754 *duplex = DUPLEX_HALF;
2755 break;
2756
2757 case MII_TG3_AUX_STAT_1000FULL:
2758 *speed = SPEED_1000;
2759 *duplex = DUPLEX_FULL;
2760 break;
2761
2762 default:
7f97a4bd 2763 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2764 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765 SPEED_10;
2766 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767 DUPLEX_HALF;
2768 break;
2769 }
1da177e4
LT		 2770 *speed = SPEED_INVALID;
2771 *duplex = DUPLEX_INVALID;
2772 break;
855e1111 2773 }
1da177e4
LT		 2774}
2775
2776static void tg3_phy_copper_begin(struct tg3 *tp)
2777{
2778 u32 new_adv;
2779 int i;
2780
2781 if (tp->link_config.phy_is_low_power) {
2782 /* Entering low power mode. Disable gigabit and
2783 * 100baseT advertisements.
2784 */
2785 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2794 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795 tp->link_config.advertising &=
2796 ~(ADVERTISED_1000baseT_Half |
2797 ADVERTISED_1000baseT_Full);
2798
ba4d07a8 2799 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2800 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801 new_adv |= ADVERTISE_10HALF;
2802 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803 new_adv |= ADVERTISE_10FULL;
2804 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805 new_adv |= ADVERTISE_100HALF;
2806 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2808
2809 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
1da177e4
LT		 2811 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813 if (tp->link_config.advertising &
2814 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815 new_adv = 0;
2816 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824 MII_TG3_CTRL_ENABLE_AS_MASTER);
2825 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826 } else {
2827 tg3_writephy(tp, MII_TG3_CTRL, 0);
2828 }
2829 } else {
ba4d07a8
MC		 2830 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831 new_adv |= ADVERTISE_CSMA;
2832
1da177e4
LT		 2833 /* Asking for a specific link mode. */
2834 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2835 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837 if (tp->link_config.duplex == DUPLEX_FULL)
2838 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839 else
2840 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2845 } else {
1da177e4
LT		 2846 if (tp->link_config.speed == SPEED_100) {
2847 if (tp->link_config.duplex == DUPLEX_FULL)
2848 new_adv |= ADVERTISE_100FULL;
2849 else
2850 new_adv |= ADVERTISE_100HALF;
2851 } else {
2852 if (tp->link_config.duplex == DUPLEX_FULL)
2853 new_adv |= ADVERTISE_10FULL;
2854 else
2855 new_adv |= ADVERTISE_10HALF;
2856 }
2857 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2858
2859 new_adv = 0;
1da177e4 2860 }
ba4d07a8
MC		 2861
2862 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2863 }
2864
2865 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866 tp->link_config.speed != SPEED_INVALID) {
2867 u32 bmcr, orig_bmcr;
2868
2869 tp->link_config.active_speed = tp->link_config.speed;
2870 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872 bmcr = 0;
2873 switch (tp->link_config.speed) {
2874 default:
2875 case SPEED_10:
2876 break;
2877
2878 case SPEED_100:
2879 bmcr |= BMCR_SPEED100;
2880 break;
2881
2882 case SPEED_1000:
2883 bmcr |= TG3_BMCR_SPEED1000;
2884 break;
855e1111 2885 }
1da177e4
LT		 2886
2887 if (tp->link_config.duplex == DUPLEX_FULL)
2888 bmcr |= BMCR_FULLDPLX;
2889
2890 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891 (bmcr != orig_bmcr)) {
2892 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893 for (i = 0; i < 1500; i++) {
2894 u32 tmp;
2895
2896 udelay(10);
2897 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898 tg3_readphy(tp, MII_BMSR, &tmp))
2899 continue;
2900 if (!(tmp & BMSR_LSTATUS)) {
2901 udelay(40);
2902 break;
2903 }
2904 }
2905 tg3_writephy(tp, MII_BMCR, bmcr);
2906 udelay(40);
2907 }
2908 } else {
2909 tg3_writephy(tp, MII_BMCR,
2910 BMCR_ANENABLE | BMCR_ANRESTART);
2911 }
2912}
2913
2914static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915{
2916 int err;
2917
2918 /* Turn off tap power management. */
2919 /* Set Extended packet length bit */
2920 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937 udelay(40);
2938
2939 return err;
2940}
2941
3600d918 2942static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2943{
3600d918
MC		 2944 u32 adv_reg, all_mask = 0;
2945
2946 if (mask & ADVERTISED_10baseT_Half)
2947 all_mask |= ADVERTISE_10HALF;
2948 if (mask & ADVERTISED_10baseT_Full)
2949 all_mask |= ADVERTISE_10FULL;
2950 if (mask & ADVERTISED_100baseT_Half)
2951 all_mask |= ADVERTISE_100HALF;
2952 if (mask & ADVERTISED_100baseT_Full)
2953 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2954
2955 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956 return 0;
2957
1da177e4
LT		 2958 if ((adv_reg & all_mask) != all_mask)
2959 return 0;
2960 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961 u32 tg3_ctrl;
2962
3600d918
MC		 2963 all_mask = 0;
2964 if (mask & ADVERTISED_1000baseT_Half)
2965 all_mask |= ADVERTISE_1000HALF;
2966 if (mask & ADVERTISED_1000baseT_Full)
2967 all_mask |= ADVERTISE_1000FULL;
2968
1da177e4
LT		 2969 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970 return 0;
2971
1da177e4
LT		 2972 if ((tg3_ctrl & all_mask) != all_mask)
2973 return 0;
2974 }
2975 return 1;
2976}
2977
ef167e27
MC		 2978static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979{
2980 u32 curadv, reqadv;
2981
2982 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983 return 1;
2984
2985 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989 if (curadv != reqadv)
2990 return 0;
2991
2992 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993 tg3_readphy(tp, MII_LPA, rmtadv);
2994 } else {
2995 /* Reprogram the advertisement register, even if it
2996 * does not affect the current link. If the link
2997 * gets renegotiated in the future, we can save an
2998 * additional renegotiation cycle by advertising
2999 * it correctly in the first place.
3000 */
3001 if (curadv != reqadv) {
3002 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003 ADVERTISE_PAUSE_ASYM);
3004 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005 }
3006 }
3007
3008 return 1;
3009}
3010
1da177e4
LT		 3011static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012{
3013 int current_link_up;
3014 u32 bmsr, dummy;
ef167e27 3015 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3016 u16 current_speed;
3017 u8 current_duplex;
3018 int i, err;
3019
3020 tw32(MAC_EVENT, 0);
3021
3022 tw32_f(MAC_STATUS,
3023 (MAC_STATUS_SYNC_CHANGED |
3024 MAC_STATUS_CFG_CHANGED |
3025 MAC_STATUS_MI_COMPLETION |
3026 MAC_STATUS_LNKSTATE_CHANGED));
3027 udelay(40);
3028
8ef21428
MC		 3029 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030 tw32_f(MAC_MI_MODE,
3031 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032 udelay(80);
3033 }
1da177e4
LT		 3034
3035 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037 /* Some third-party PHYs need to be reset on link going
3038 * down.
3039 */
3040 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043 netif_carrier_ok(tp->dev)) {
3044 tg3_readphy(tp, MII_BMSR, &bmsr);
3045 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046 !(bmsr & BMSR_LSTATUS))
3047 force_reset = 1;
3048 }
3049 if (force_reset)
3050 tg3_phy_reset(tp);
3051
3052 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056 bmsr = 0;
3057
3058 if (!(bmsr & BMSR_LSTATUS)) {
3059 err = tg3_init_5401phy_dsp(tp);
3060 if (err)
3061 return err;
3062
3063 tg3_readphy(tp, MII_BMSR, &bmsr);
3064 for (i = 0; i < 1000; i++) {
3065 udelay(10);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS)) {
3068 udelay(40);
3069 break;
3070 }
3071 }
3072
3073 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074 !(bmsr & BMSR_LSTATUS) &&
3075 tp->link_config.active_speed == SPEED_1000) {
3076 err = tg3_phy_reset(tp);
3077 if (!err)
3078 err = tg3_init_5401phy_dsp(tp);
3079 if (err)
3080 return err;
3081 }
3082 }
3083 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085 /* 5701 {A0,B0} CRC bug workaround */
3086 tg3_writephy(tp, 0x15, 0x0a75);
3087 tg3_writephy(tp, 0x1c, 0x8c68);
3088 tg3_writephy(tp, 0x1c, 0x8d68);
3089 tg3_writephy(tp, 0x1c, 0x8c68);
3090 }
3091
3092 /* Clear pending interrupts... */
3093 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3098 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3099 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106 else
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108 }
3109
3110 current_link_up = 0;
3111 current_speed = SPEED_INVALID;
3112 current_duplex = DUPLEX_INVALID;
3113
3114 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115 u32 val;
3116
3117 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119 if (!(val & (1 << 10))) {
3120 val |= (1 << 10);
3121 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122 goto relink;
3123 }
3124 }
3125
3126 bmsr = 0;
3127 for (i = 0; i < 100; i++) {
3128 tg3_readphy(tp, MII_BMSR, &bmsr);
3129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130 (bmsr & BMSR_LSTATUS))
3131 break;
3132 udelay(40);
3133 }
3134
3135 if (bmsr & BMSR_LSTATUS) {
3136 u32 aux_stat, bmcr;
3137
3138 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139 for (i = 0; i < 2000; i++) {
3140 udelay(10);
3141 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142 aux_stat)
3143 break;
3144 }
3145
3146 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147 &current_speed,
3148 &current_duplex);
3149
3150 bmcr = 0;
3151 for (i = 0; i < 200; i++) {
3152 tg3_readphy(tp, MII_BMCR, &bmcr);
3153 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154 continue;
3155 if (bmcr && bmcr != 0x7fff)
3156 break;
3157 udelay(10);
3158 }
3159
ef167e27
MC		 3160 lcl_adv = 0;
3161 rmt_adv = 0;
1da177e4 3162
ef167e27
MC		 3163 tp->link_config.active_speed = current_speed;
3164 tp->link_config.active_duplex = current_duplex;
3165
3166 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167 if ((bmcr & BMCR_ANENABLE) &&
3168 tg3_copper_is_advertising_all(tp,
3169 tp->link_config.advertising)) {
3170 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171 &rmt_adv))
3172 current_link_up = 1;
1da177e4
LT		 3173 }
3174 } else {
3175 if (!(bmcr & BMCR_ANENABLE) &&
3176 tp->link_config.speed == current_speed &&
ef167e27
MC		 3177 tp->link_config.duplex == current_duplex &&
3178 tp->link_config.flowctrl ==
3179 tp->link_config.active_flowctrl) {
1da177e4 3180 current_link_up = 1;
1da177e4
LT		 3181 }
3182 }
3183
ef167e27
MC		 3184 if (current_link_up == 1 &&
3185 tp->link_config.active_duplex == DUPLEX_FULL)
3186 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3187 }
3188
1da177e4 3189relink:
6921d201 3190 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3191 u32 tmp;
3192
3193 tg3_phy_copper_begin(tp);
3194
3195 tg3_readphy(tp, MII_BMSR, &tmp);
3196 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197 (tmp & BMSR_LSTATUS))
3198 current_link_up = 1;
3199 }
3200
3201 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202 if (current_link_up == 1) {
3203 if (tp->link_config.active_speed == SPEED_100 ||
3204 tp->link_config.active_speed == SPEED_10)
3205 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206 else
3207 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3208 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210 else
1da177e4
LT		 3211 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214 if (tp->link_config.active_duplex == DUPLEX_HALF)
3215 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
1da177e4 3217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3218 if (current_link_up == 1 &&
3219 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3220 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3221 else
3222 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3223 }
3224
3225 /* ??? Without this setting Netgear GA302T PHY does not
3226 * ??? send/receive packets...
3227 */
3228 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232 udelay(80);
3233 }
3234
3235 tw32_f(MAC_MODE, tp->mac_mode);
3236 udelay(40);
3237
3238 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239 /* Polled via timer. */
3240 tw32_f(MAC_EVENT, 0);
3241 } else {
3242 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243 }
3244 udelay(40);
3245
3246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247 current_link_up == 1 &&
3248 tp->link_config.active_speed == SPEED_1000 &&
3249 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251 udelay(120);
3252 tw32_f(MAC_STATUS,
3253 (MAC_STATUS_SYNC_CHANGED |
3254 MAC_STATUS_CFG_CHANGED));
3255 udelay(40);
3256 tg3_write_mem(tp,
3257 NIC_SRAM_FIRMWARE_MBOX,
3258 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259 }
3260
5e7dfd0f
MC		 3261 /* Prevent send BD corruption. */
3262 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263 u16 oldlnkctl, newlnkctl;
3264
3265 pci_read_config_word(tp->pdev,
3266 tp->pcie_cap + PCI_EXP_LNKCTL,
3267 &oldlnkctl);
3268 if (tp->link_config.active_speed == SPEED_100 ||
3269 tp->link_config.active_speed == SPEED_10)
3270 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271 else
3272 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273 if (newlnkctl != oldlnkctl)
3274 pci_write_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3276 newlnkctl);
3277 }
3278
1da177e4
LT		 3279 if (current_link_up != netif_carrier_ok(tp->dev)) {
3280 if (current_link_up)
3281 netif_carrier_on(tp->dev);
3282 else
3283 netif_carrier_off(tp->dev);
3284 tg3_link_report(tp);
3285 }
3286
3287 return 0;
3288}
3289
3290struct tg3_fiber_aneginfo {
3291 int state;
3292#define ANEG_STATE_UNKNOWN 0
3293#define ANEG_STATE_AN_ENABLE 1
3294#define ANEG_STATE_RESTART_INIT 2
3295#define ANEG_STATE_RESTART 3
3296#define ANEG_STATE_DISABLE_LINK_OK 4
3297#define ANEG_STATE_ABILITY_DETECT_INIT 5
3298#define ANEG_STATE_ABILITY_DETECT 6
3299#define ANEG_STATE_ACK_DETECT_INIT 7
3300#define ANEG_STATE_ACK_DETECT 8
3301#define ANEG_STATE_COMPLETE_ACK_INIT 9
3302#define ANEG_STATE_COMPLETE_ACK 10
3303#define ANEG_STATE_IDLE_DETECT_INIT 11
3304#define ANEG_STATE_IDLE_DETECT 12
3305#define ANEG_STATE_LINK_OK 13
3306#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3307#define ANEG_STATE_NEXT_PAGE_WAIT 15
3308
3309 u32 flags;
3310#define MR_AN_ENABLE 0x00000001
3311#define MR_RESTART_AN 0x00000002
3312#define MR_AN_COMPLETE 0x00000004
3313#define MR_PAGE_RX 0x00000008
3314#define MR_NP_LOADED 0x00000010
3315#define MR_TOGGLE_TX 0x00000020
3316#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3317#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3318#define MR_LP_ADV_SYM_PAUSE 0x00000100
3319#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3320#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322#define MR_LP_ADV_NEXT_PAGE 0x00001000
3323#define MR_TOGGLE_RX 0x00002000
3324#define MR_NP_RX 0x00004000
3325
3326#define MR_LINK_OK 0x80000000
3327
3328 unsigned long link_time, cur_time;
3329
3330 u32 ability_match_cfg;
3331 int ability_match_count;
3332
3333 char ability_match, idle_match, ack_match;
3334
3335 u32 txconfig, rxconfig;
3336#define ANEG_CFG_NP 0x00000080
3337#define ANEG_CFG_ACK 0x00000040
3338#define ANEG_CFG_RF2 0x00000020
3339#define ANEG_CFG_RF1 0x00000010
3340#define ANEG_CFG_PS2 0x00000001
3341#define ANEG_CFG_PS1 0x00008000
3342#define ANEG_CFG_HD 0x00004000
3343#define ANEG_CFG_FD 0x00002000
3344#define ANEG_CFG_INVAL 0x00001f06
3345
3346};
3347#define ANEG_OK 0
3348#define ANEG_DONE 1
3349#define ANEG_TIMER_ENAB 2
3350#define ANEG_FAILED -1
3351
3352#define ANEG_STATE_SETTLE_TIME 10000
3353
3354static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355 struct tg3_fiber_aneginfo *ap)
3356{
5be73b47 3357 u16 flowctrl;
1da177e4
LT		 3358 unsigned long delta;
3359 u32 rx_cfg_reg;
3360 int ret;
3361
3362 if (ap->state == ANEG_STATE_UNKNOWN) {
3363 ap->rxconfig = 0;
3364 ap->link_time = 0;
3365 ap->cur_time = 0;
3366 ap->ability_match_cfg = 0;
3367 ap->ability_match_count = 0;
3368 ap->ability_match = 0;
3369 ap->idle_match = 0;
3370 ap->ack_match = 0;
3371 }
3372 ap->cur_time++;
3373
3374 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377 if (rx_cfg_reg != ap->ability_match_cfg) {
3378 ap->ability_match_cfg = rx_cfg_reg;
3379 ap->ability_match = 0;
3380 ap->ability_match_count = 0;
3381 } else {
3382 if (++ap->ability_match_count > 1) {
3383 ap->ability_match = 1;
3384 ap->ability_match_cfg = rx_cfg_reg;
3385 }
3386 }
3387 if (rx_cfg_reg & ANEG_CFG_ACK)
3388 ap->ack_match = 1;
3389 else
3390 ap->ack_match = 0;
3391
3392 ap->idle_match = 0;
3393 } else {
3394 ap->idle_match = 1;
3395 ap->ability_match_cfg = 0;
3396 ap->ability_match_count = 0;
3397 ap->ability_match = 0;
3398 ap->ack_match = 0;
3399
3400 rx_cfg_reg = 0;
3401 }
3402
3403 ap->rxconfig = rx_cfg_reg;
3404 ret = ANEG_OK;
3405
3406 switch(ap->state) {
3407 case ANEG_STATE_UNKNOWN:
3408 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409 ap->state = ANEG_STATE_AN_ENABLE;
3410
3411 /* fallthru */
3412 case ANEG_STATE_AN_ENABLE:
3413 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414 if (ap->flags & MR_AN_ENABLE) {
3415 ap->link_time = 0;
3416 ap->cur_time = 0;
3417 ap->ability_match_cfg = 0;
3418 ap->ability_match_count = 0;
3419 ap->ability_match = 0;
3420 ap->idle_match = 0;
3421 ap->ack_match = 0;
3422
3423 ap->state = ANEG_STATE_RESTART_INIT;
3424 } else {
3425 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426 }
3427 break;
3428
3429 case ANEG_STATE_RESTART_INIT:
3430 ap->link_time = ap->cur_time;
3431 ap->flags &= ~(MR_NP_LOADED);
3432 ap->txconfig = 0;
3433 tw32(MAC_TX_AUTO_NEG, 0);
3434 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435 tw32_f(MAC_MODE, tp->mac_mode);
3436 udelay(40);
3437
3438 ret = ANEG_TIMER_ENAB;
3439 ap->state = ANEG_STATE_RESTART;
3440
3441 /* fallthru */
3442 case ANEG_STATE_RESTART:
3443 delta = ap->cur_time - ap->link_time;
3444 if (delta > ANEG_STATE_SETTLE_TIME) {
3445 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446 } else {
3447 ret = ANEG_TIMER_ENAB;
3448 }
3449 break;
3450
3451 case ANEG_STATE_DISABLE_LINK_OK:
3452 ret = ANEG_DONE;
3453 break;
3454
3455 case ANEG_STATE_ABILITY_DETECT_INIT:
3456 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3457 ap->txconfig = ANEG_CFG_FD;
3458 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459 if (flowctrl & ADVERTISE_1000XPAUSE)
3460 ap->txconfig |= ANEG_CFG_PS1;
3461 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3463 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465 tw32_f(MAC_MODE, tp->mac_mode);
3466 udelay(40);
3467
3468 ap->state = ANEG_STATE_ABILITY_DETECT;
3469 break;
3470
3471 case ANEG_STATE_ABILITY_DETECT:
3472 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474 }
3475 break;
3476
3477 case ANEG_STATE_ACK_DETECT_INIT:
3478 ap->txconfig |= ANEG_CFG_ACK;
3479 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481 tw32_f(MAC_MODE, tp->mac_mode);
3482 udelay(40);
3483
3484 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486 /* fallthru */
3487 case ANEG_STATE_ACK_DETECT:
3488 if (ap->ack_match != 0) {
3489 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492 } else {
3493 ap->state = ANEG_STATE_AN_ENABLE;
3494 }
3495 } else if (ap->ability_match != 0 &&
3496 ap->rxconfig == 0) {
3497 ap->state = ANEG_STATE_AN_ENABLE;
3498 }
3499 break;
3500
3501 case ANEG_STATE_COMPLETE_ACK_INIT:
3502 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503 ret = ANEG_FAILED;
3504 break;
3505 }
3506 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507 MR_LP_ADV_HALF_DUPLEX |
3508 MR_LP_ADV_SYM_PAUSE |
3509 MR_LP_ADV_ASYM_PAUSE |
3510 MR_LP_ADV_REMOTE_FAULT1 |
3511 MR_LP_ADV_REMOTE_FAULT2 |
3512 MR_LP_ADV_NEXT_PAGE |
3513 MR_TOGGLE_RX |
3514 MR_NP_RX);
3515 if (ap->rxconfig & ANEG_CFG_FD)
3516 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517 if (ap->rxconfig & ANEG_CFG_HD)
3518 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519 if (ap->rxconfig & ANEG_CFG_PS1)
3520 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521 if (ap->rxconfig & ANEG_CFG_PS2)
3522 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523 if (ap->rxconfig & ANEG_CFG_RF1)
3524 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525 if (ap->rxconfig & ANEG_CFG_RF2)
3526 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527 if (ap->rxconfig & ANEG_CFG_NP)
3528 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530 ap->link_time = ap->cur_time;
3531
3532 ap->flags ^= (MR_TOGGLE_TX);
3533 if (ap->rxconfig & 0x0008)
3534 ap->flags |= MR_TOGGLE_RX;
3535 if (ap->rxconfig & ANEG_CFG_NP)
3536 ap->flags |= MR_NP_RX;
3537 ap->flags |= MR_PAGE_RX;
3538
3539 ap->state = ANEG_STATE_COMPLETE_ACK;
3540 ret = ANEG_TIMER_ENAB;
3541 break;
3542
3543 case ANEG_STATE_COMPLETE_ACK:
3544 if (ap->ability_match != 0 &&
3545 ap->rxconfig == 0) {
3546 ap->state = ANEG_STATE_AN_ENABLE;
3547 break;
3548 }
3549 delta = ap->cur_time - ap->link_time;
3550 if (delta > ANEG_STATE_SETTLE_TIME) {
3551 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553 } else {
3554 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555 !(ap->flags & MR_NP_RX)) {
3556 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557 } else {
3558 ret = ANEG_FAILED;
3559 }
3560 }
3561 }
3562 break;
3563
3564 case ANEG_STATE_IDLE_DETECT_INIT:
3565 ap->link_time = ap->cur_time;
3566 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567 tw32_f(MAC_MODE, tp->mac_mode);
3568 udelay(40);
3569
3570 ap->state = ANEG_STATE_IDLE_DETECT;
3571 ret = ANEG_TIMER_ENAB;
3572 break;
3573
3574 case ANEG_STATE_IDLE_DETECT:
3575 if (ap->ability_match != 0 &&
3576 ap->rxconfig == 0) {
3577 ap->state = ANEG_STATE_AN_ENABLE;
3578 break;
3579 }
3580 delta = ap->cur_time - ap->link_time;
3581 if (delta > ANEG_STATE_SETTLE_TIME) {
3582 /* XXX another gem from the Broadcom driver :( */
3583 ap->state = ANEG_STATE_LINK_OK;
3584 }
3585 break;
3586
3587 case ANEG_STATE_LINK_OK:
3588 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589 ret = ANEG_DONE;
3590 break;
3591
3592 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593 /* ??? unimplemented */
3594 break;
3595
3596 case ANEG_STATE_NEXT_PAGE_WAIT:
3597 /* ??? unimplemented */
3598 break;
3599
3600 default:
3601 ret = ANEG_FAILED;
3602 break;
855e1111 3603 }
1da177e4
LT		 3604
3605 return ret;
3606}
3607
5be73b47 3608static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3609{
3610 int res = 0;
3611 struct tg3_fiber_aneginfo aninfo;
3612 int status = ANEG_FAILED;
3613 unsigned int tick;
3614 u32 tmp;
3615
3616 tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620 udelay(40);
3621
3622 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623 udelay(40);
3624
3625 memset(&aninfo, 0, sizeof(aninfo));
3626 aninfo.flags |= MR_AN_ENABLE;
3627 aninfo.state = ANEG_STATE_UNKNOWN;
3628 aninfo.cur_time = 0;
3629 tick = 0;
3630 while (++tick < 195000) {
3631 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632 if (status == ANEG_DONE || status == ANEG_FAILED)
3633 break;
3634
3635 udelay(1);
3636 }
3637
3638 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639 tw32_f(MAC_MODE, tp->mac_mode);
3640 udelay(40);
3641
5be73b47
MC		 3642 *txflags = aninfo.txconfig;
3643 *rxflags = aninfo.flags;
1da177e4
LT		 3644
3645 if (status == ANEG_DONE &&
3646 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647 MR_LP_ADV_FULL_DUPLEX)))
3648 res = 1;
3649
3650 return res;
3651}
3652
3653static void tg3_init_bcm8002(struct tg3 *tp)
3654{
3655 u32 mac_status = tr32(MAC_STATUS);
3656 int i;
3657
3658 /* Reset when initting first time or we have a link. */
3659 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660 !(mac_status & MAC_STATUS_PCS_SYNCED))
3661 return;
3662
3663 /* Set PLL lock range. */
3664 tg3_writephy(tp, 0x16, 0x8007);
3665
3666 /* SW reset */
3667 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669 /* Wait for reset to complete. */
3670 /* XXX schedule_timeout() ... */
3671 for (i = 0; i < 500; i++)
3672 udelay(10);
3673
3674 /* Config mode; select PMA/Ch 1 regs. */
3675 tg3_writephy(tp, 0x10, 0x8411);
3676
3677 /* Enable auto-lock and comdet, select txclk for tx. */
3678 tg3_writephy(tp, 0x11, 0x0a10);
3679
3680 tg3_writephy(tp, 0x18, 0x00a0);
3681 tg3_writephy(tp, 0x16, 0x41ff);
3682
3683 /* Assert and deassert POR. */
3684 tg3_writephy(tp, 0x13, 0x0400);
3685 udelay(40);
3686 tg3_writephy(tp, 0x13, 0x0000);
3687
3688 tg3_writephy(tp, 0x11, 0x0a50);
3689 udelay(40);
3690 tg3_writephy(tp, 0x11, 0x0a10);
3691
3692 /* Wait for signal to stabilize */
3693 /* XXX schedule_timeout() ... */
3694 for (i = 0; i < 15000; i++)
3695 udelay(10);
3696
3697 /* Deselect the channel register so we can read the PHYID
3698 * later.
3699 */
3700 tg3_writephy(tp, 0x10, 0x8011);
3701}
3702
3703static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704{
82cd3d11 3705 u16 flowctrl;
1da177e4
LT		 3706 u32 sg_dig_ctrl, sg_dig_status;
3707 u32 serdes_cfg, expected_sg_dig_ctrl;
3708 int workaround, port_a;
3709 int current_link_up;
3710
3711 serdes_cfg = 0;
3712 expected_sg_dig_ctrl = 0;
3713 workaround = 0;
3714 port_a = 1;
3715 current_link_up = 0;
3716
3717 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719 workaround = 1;
3720 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721 port_a = 0;
3722
3723 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724 /* preserve bits 20-23 for voltage regulator */
3725 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726 }
3727
3728 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3731 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3732 if (workaround) {
3733 u32 val = serdes_cfg;
3734
3735 if (port_a)
3736 val |= 0xc010000;
3737 else
3738 val |= 0x4010000;
3739 tw32_f(MAC_SERDES_CFG, val);
3740 }
c98f6e3b
MC		 3741
3742 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3743 }
3744 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745 tg3_setup_flow_control(tp, 0, 0);
3746 current_link_up = 1;
3747 }
3748 goto out;
3749 }
3750
3751 /* Want auto-negotiation. */
c98f6e3b 3752 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3753
82cd3d11
MC		 3754 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755 if (flowctrl & ADVERTISE_1000XPAUSE)
3756 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3759
3760 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3761 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762 tp->serdes_counter &&
3763 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764 MAC_STATUS_RCVD_CFG)) ==
3765 MAC_STATUS_PCS_SYNCED)) {
3766 tp->serdes_counter--;
3767 current_link_up = 1;
3768 goto out;
3769 }
3770restart_autoneg:
1da177e4
LT		 3771 if (workaround)
3772 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3773 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3774 udelay(5);
3775 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3d3ebe74
MC		 3777 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3779 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3781 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3782 mac_status = tr32(MAC_STATUS);
3783
c98f6e3b 3784 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3785 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3786 u32 local_adv = 0, remote_adv = 0;
3787
3788 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789 local_adv |= ADVERTISE_1000XPAUSE;
3790 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3792
c98f6e3b 3793 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3794 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3795 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3796 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3797
3798 tg3_setup_flow_control(tp, local_adv, remote_adv);
3799 current_link_up = 1;
3d3ebe74
MC		 3800 tp->serdes_counter = 0;
3801 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3802 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3803 if (tp->serdes_counter)
3804 tp->serdes_counter--;
1da177e4
LT		 3805 else {
3806 if (workaround) {
3807 u32 val = serdes_cfg;
3808
3809 if (port_a)
3810 val |= 0xc010000;
3811 else
3812 val |= 0x4010000;
3813
3814 tw32_f(MAC_SERDES_CFG, val);
3815 }
3816
c98f6e3b 3817 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3818 udelay(40);
3819
3820 /* Link parallel detection - link is up */
3821 /* only if we have PCS_SYNC and not */
3822 /* receiving config code words */
3823 mac_status = tr32(MAC_STATUS);
3824 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826 tg3_setup_flow_control(tp, 0, 0);
3827 current_link_up = 1;
3d3ebe74
MC		 3828 tp->tg3_flags2 |=
3829 TG3_FLG2_PARALLEL_DETECT;
3830 tp->serdes_counter =
3831 SERDES_PARALLEL_DET_TIMEOUT;
3832 } else
3833 goto restart_autoneg;
1da177e4
LT		 3834 }
3835 }
3d3ebe74
MC		 3836 } else {
3837 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3839 }
3840
3841out:
3842 return current_link_up;
3843}
3844
3845static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846{
3847 int current_link_up = 0;
3848
5cf64b8a 3849 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3850 goto out;
1da177e4
LT		 3851
3852 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3853 u32 txflags, rxflags;
1da177e4 3854 int i;
6aa20a22 3855
5be73b47
MC		 3856 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857 u32 local_adv = 0, remote_adv = 0;
1da177e4 3858
5be73b47
MC		 3859 if (txflags & ANEG_CFG_PS1)
3860 local_adv |= ADVERTISE_1000XPAUSE;
3861 if (txflags & ANEG_CFG_PS2)
3862 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865 remote_adv |= LPA_1000XPAUSE;
3866 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3868
3869 tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
1da177e4
LT		 3871 current_link_up = 1;
3872 }
3873 for (i = 0; i < 30; i++) {
3874 udelay(20);
3875 tw32_f(MAC_STATUS,
3876 (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 udelay(40);
3879 if ((tr32(MAC_STATUS) &
3880 (MAC_STATUS_SYNC_CHANGED |
3881 MAC_STATUS_CFG_CHANGED)) == 0)
3882 break;
3883 }
3884
3885 mac_status = tr32(MAC_STATUS);
3886 if (current_link_up == 0 &&
3887 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888 !(mac_status & MAC_STATUS_RCVD_CFG))
3889 current_link_up = 1;
3890 } else {
5be73b47
MC		 3891 tg3_setup_flow_control(tp, 0, 0);
3892
1da177e4
LT		 3893 /* Forcing 1000FD link up. */
3894 current_link_up = 1;
1da177e4
LT		 3895
3896 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897 udelay(40);
e8f3f6ca
MC		 3898
3899 tw32_f(MAC_MODE, tp->mac_mode);
3900 udelay(40);
1da177e4
LT		 3901 }
3902
3903out:
3904 return current_link_up;
3905}
3906
3907static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908{
3909 u32 orig_pause_cfg;
3910 u16 orig_active_speed;
3911 u8 orig_active_duplex;
3912 u32 mac_status;
3913 int current_link_up;
3914 int i;
3915
8d018621 3916 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3917 orig_active_speed = tp->link_config.active_speed;
3918 orig_active_duplex = tp->link_config.active_duplex;
3919
3920 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921 netif_carrier_ok(tp->dev) &&
3922 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923 mac_status = tr32(MAC_STATUS);
3924 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925 MAC_STATUS_SIGNAL_DET |
3926 MAC_STATUS_CFG_CHANGED |
3927 MAC_STATUS_RCVD_CFG);
3928 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929 MAC_STATUS_SIGNAL_DET)) {
3930 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931 MAC_STATUS_CFG_CHANGED));
3932 return 0;
3933 }
3934 }
3935
3936 tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940 tw32_f(MAC_MODE, tp->mac_mode);
3941 udelay(40);
3942
3943 if (tp->phy_id == PHY_ID_BCM8002)
3944 tg3_init_bcm8002(tp);
3945
3946 /* Enable link change event even when serdes polling. */
3947 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948 udelay(40);
3949
3950 current_link_up = 0;
3951 mac_status = tr32(MAC_STATUS);
3952
3953 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955 else
3956 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
898a56f8 3958 tp->napi[0].hw_status->status =
1da177e4 3959 (SD_STATUS_UPDATED |
898a56f8 3960 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3961
3962 for (i = 0; i < 100; i++) {
3963 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964 MAC_STATUS_CFG_CHANGED));
3965 udelay(5);
3966 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3967 MAC_STATUS_CFG_CHANGED |
3968 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3969 break;
3970 }
3971
3972 mac_status = tr32(MAC_STATUS);
3973 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974 current_link_up = 0;
3d3ebe74
MC		 3975 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976 tp->serdes_counter == 0) {
1da177e4
LT		 3977 tw32_f(MAC_MODE, (tp->mac_mode |
3978 MAC_MODE_SEND_CONFIGS));
3979 udelay(1);
3980 tw32_f(MAC_MODE, tp->mac_mode);
3981 }
3982 }
3983
3984 if (current_link_up == 1) {
3985 tp->link_config.active_speed = SPEED_1000;
3986 tp->link_config.active_duplex = DUPLEX_FULL;
3987 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988 LED_CTRL_LNKLED_OVERRIDE |
3989 LED_CTRL_1000MBPS_ON));
3990 } else {
3991 tp->link_config.active_speed = SPEED_INVALID;
3992 tp->link_config.active_duplex = DUPLEX_INVALID;
3993 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994 LED_CTRL_LNKLED_OVERRIDE |
3995 LED_CTRL_TRAFFIC_OVERRIDE));
3996 }
3997
3998 if (current_link_up != netif_carrier_ok(tp->dev)) {
3999 if (current_link_up)
4000 netif_carrier_on(tp->dev);
4001 else
4002 netif_carrier_off(tp->dev);
4003 tg3_link_report(tp);
4004 } else {
8d018621 4005 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4006 if (orig_pause_cfg != now_pause_cfg ||
4007 orig_active_speed != tp->link_config.active_speed ||
4008 orig_active_duplex != tp->link_config.active_duplex)
4009 tg3_link_report(tp);
4010 }
4011
4012 return 0;
4013}
4014
747e8f8b
MC		 4015static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016{
4017 int current_link_up, err = 0;
4018 u32 bmsr, bmcr;
4019 u16 current_speed;
4020 u8 current_duplex;
ef167e27 4021 u32 local_adv, remote_adv;
747e8f8b
MC		 4022
4023 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024 tw32_f(MAC_MODE, tp->mac_mode);
4025 udelay(40);
4026
4027 tw32(MAC_EVENT, 0);
4028
4029 tw32_f(MAC_STATUS,
4030 (MAC_STATUS_SYNC_CHANGED |
4031 MAC_STATUS_CFG_CHANGED |
4032 MAC_STATUS_MI_COMPLETION |
4033 MAC_STATUS_LNKSTATE_CHANGED));
4034 udelay(40);
4035
4036 if (force_reset)
4037 tg3_phy_reset(tp);
4038
4039 current_link_up = 0;
4040 current_speed = SPEED_INVALID;
4041 current_duplex = DUPLEX_INVALID;
4042
4043 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047 bmsr |= BMSR_LSTATUS;
4048 else
4049 bmsr &= ~BMSR_LSTATUS;
4050 }
747e8f8b
MC		 4051
4052 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4055 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4056 /* do nothing, just check for link up at the end */
4057 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058 u32 adv, new_adv;
4059
4060 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062 ADVERTISE_1000XPAUSE |
4063 ADVERTISE_1000XPSE_ASYM |
4064 ADVERTISE_SLCT);
4065
ba4d07a8 4066 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4067
4068 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069 new_adv |= ADVERTISE_1000XHALF;
4070 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071 new_adv |= ADVERTISE_1000XFULL;
4072
4073 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076 tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4079 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4080 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082 return err;
4083 }
4084 } else {
4085 u32 new_bmcr;
4086
4087 bmcr &= ~BMCR_SPEED1000;
4088 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090 if (tp->link_config.duplex == DUPLEX_FULL)
4091 new_bmcr |= BMCR_FULLDPLX;
4092
4093 if (new_bmcr != bmcr) {
4094 /* BMCR_SPEED1000 is a reserved bit that needs
4095 * to be set on write.
4096 */
4097 new_bmcr |= BMCR_SPEED1000;
4098
4099 /* Force a linkdown */
4100 if (netif_carrier_ok(tp->dev)) {
4101 u32 adv;
4102
4103 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104 adv &= ~(ADVERTISE_1000XFULL |
4105 ADVERTISE_1000XHALF |
4106 ADVERTISE_SLCT);
4107 tg3_writephy(tp, MII_ADVERTISE, adv);
4108 tg3_writephy(tp, MII_BMCR, bmcr |
4109 BMCR_ANRESTART |
4110 BMCR_ANENABLE);
4111 udelay(10);
4112 netif_carrier_off(tp->dev);
4113 }
4114 tg3_writephy(tp, MII_BMCR, new_bmcr);
4115 bmcr = new_bmcr;
4116 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4118 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119 ASIC_REV_5714) {
4120 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121 bmsr |= BMSR_LSTATUS;
4122 else
4123 bmsr &= ~BMSR_LSTATUS;
4124 }
747e8f8b
MC		 4125 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126 }
4127 }
4128
4129 if (bmsr & BMSR_LSTATUS) {
4130 current_speed = SPEED_1000;
4131 current_link_up = 1;
4132 if (bmcr & BMCR_FULLDPLX)
4133 current_duplex = DUPLEX_FULL;
4134 else
4135 current_duplex = DUPLEX_HALF;
4136
ef167e27
MC		 4137 local_adv = 0;
4138 remote_adv = 0;
4139
747e8f8b 4140 if (bmcr & BMCR_ANENABLE) {
ef167e27 4141 u32 common;
747e8f8b
MC		 4142
4143 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145 common = local_adv & remote_adv;
4146 if (common & (ADVERTISE_1000XHALF |
4147 ADVERTISE_1000XFULL)) {
4148 if (common & ADVERTISE_1000XFULL)
4149 current_duplex = DUPLEX_FULL;
4150 else
4151 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4152 }
4153 else
4154 current_link_up = 0;
4155 }
4156 }
4157
ef167e27
MC		 4158 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
747e8f8b
MC		 4161 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162 if (tp->link_config.active_duplex == DUPLEX_HALF)
4163 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165 tw32_f(MAC_MODE, tp->mac_mode);
4166 udelay(40);
4167
4168 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170 tp->link_config.active_speed = current_speed;
4171 tp->link_config.active_duplex = current_duplex;
4172
4173 if (current_link_up != netif_carrier_ok(tp->dev)) {
4174 if (current_link_up)
4175 netif_carrier_on(tp->dev);
4176 else {
4177 netif_carrier_off(tp->dev);
4178 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179 }
4180 tg3_link_report(tp);
4181 }
4182 return err;
4183}
4184
4185static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186{
3d3ebe74 4187 if (tp->serdes_counter) {
747e8f8b 4188 /* Give autoneg time to complete. */
3d3ebe74 4189 tp->serdes_counter--;
747e8f8b
MC		 4190 return;
4191 }
4192 if (!netif_carrier_ok(tp->dev) &&
4193 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194 u32 bmcr;
4195
4196 tg3_readphy(tp, MII_BMCR, &bmcr);
4197 if (bmcr & BMCR_ANENABLE) {
4198 u32 phy1, phy2;
4199
4200 /* Select shadow register 0x1f */
4201 tg3_writephy(tp, 0x1c, 0x7c00);
4202 tg3_readphy(tp, 0x1c, &phy1);
4203
4204 /* Select expansion interrupt status register */
4205 tg3_writephy(tp, 0x17, 0x0f01);
4206 tg3_readphy(tp, 0x15, &phy2);
4207 tg3_readphy(tp, 0x15, &phy2);
4208
4209 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210 /* We have signal detect and not receiving
4211 * config code words, link is up by parallel
4212 * detection.
4213 */
4214
4215 bmcr &= ~BMCR_ANENABLE;
4216 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217 tg3_writephy(tp, MII_BMCR, bmcr);
4218 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219 }
4220 }
4221 }
4222 else if (netif_carrier_ok(tp->dev) &&
4223 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225 u32 phy2;
4226
4227 /* Select expansion interrupt status register */
4228 tg3_writephy(tp, 0x17, 0x0f01);
4229 tg3_readphy(tp, 0x15, &phy2);
4230 if (phy2 & 0x20) {
4231 u32 bmcr;
4232
4233 /* Config code words received, turn on autoneg. */
4234 tg3_readphy(tp, MII_BMCR, &bmcr);
4235 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239 }
4240 }
4241}
4242
1da177e4
LT		 4243static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244{
4245 int err;
4246
4247 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4249 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4251 } else {
4252 err = tg3_setup_copper_phy(tp, force_reset);
4253 }
4254
bcb37f6c 4255 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4256 u32 val, scale;
4257
4258 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260 scale = 65;
4261 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262 scale = 6;
4263 else
4264 scale = 12;
4265
4266 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268 tw32(GRC_MISC_CFG, val);
4269 }
4270
1da177e4
LT		 4271 if (tp->link_config.active_speed == SPEED_1000 &&
4272 tp->link_config.active_duplex == DUPLEX_HALF)
4273 tw32(MAC_TX_LENGTHS,
4274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275 (6 << TX_LENGTHS_IPG_SHIFT) |
4276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277 else
4278 tw32(MAC_TX_LENGTHS,
4279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280 (6 << TX_LENGTHS_IPG_SHIFT) |
4281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284 if (netif_carrier_ok(tp->dev)) {
4285 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4286 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4287 } else {
4288 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289 }
4290 }
4291
8ed5d97e
MC		 4292 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294 if (!netif_carrier_ok(tp->dev))
4295 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296 tp->pwrmgmt_thresh;
4297 else
4298 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299 tw32(PCIE_PWR_MGMT_THRESH, val);
4300 }
4301
1da177e4
LT		 4302 return err;
4303}
4304
df3e6548
MC		 4305/* This is called whenever we suspect that the system chipset is re-
4306 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307 * is bogus tx completions. We try to recover by setting the
4308 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309 * in the workqueue.
4310 */
4311static void tg3_tx_recover(struct tg3 *tp)
4312{
4313 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317 "mapped I/O cycles to the network device, attempting to "
4318 "recover. Please report the problem to the driver maintainer "
4319 "and include system chipset information.\n", tp->dev->name);
4320
4321 spin_lock(&tp->lock);
df3e6548 4322 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4323 spin_unlock(&tp->lock);
4324}
4325
f3f3f27e 4326static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4327{
4328 smp_mb();
f3f3f27e
MC		 4329 return tnapi->tx_pending -
4330 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4331}
4332
1da177e4
LT		 4333/* Tigon3 never reports partial packet sends. So we do not
4334 * need special logic to handle SKBs that have not had all
4335 * of their frags sent yet, like SunGEM does.
4336 */
17375d25 4337static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4338{
17375d25 4339 struct tg3 *tp = tnapi->tp;
898a56f8 4340 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4341 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4342 struct netdev_queue *txq;
4343 int index = tnapi - tp->napi;
4344
4345 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346 index--;
4347
4348 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4349
4350 while (sw_idx != hw_idx) {
f3f3f27e 4351 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4352 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4353 int i, tx_bug = 0;
4354
4355 if (unlikely(skb == NULL)) {
4356 tg3_tx_recover(tp);
4357 return;
4358 }
1da177e4 4359
90079ce8 4360 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4361
4362 ri->skb = NULL;
4363
4364 sw_idx = NEXT_TX(sw_idx);
4365
4366 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4367 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4368 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369 tx_bug = 1;
1da177e4
LT		 4370 sw_idx = NEXT_TX(sw_idx);
4371 }
4372
f47c11ee 4373 dev_kfree_skb(skb);
df3e6548
MC		 4374
4375 if (unlikely(tx_bug)) {
4376 tg3_tx_recover(tp);
4377 return;
4378 }
1da177e4
LT		 4379 }
4380
f3f3f27e 4381 tnapi->tx_cons = sw_idx;
1da177e4 4382
1b2a7205
MC		 4383 /* Need to make the tx_cons update visible to tg3_start_xmit()
4384 * before checking for netif_queue_stopped(). Without the
4385 * memory barrier, there is a small possibility that tg3_start_xmit()
4386 * will miss it and cause the queue to be stopped forever.
4387 */
4388 smp_mb();
4389
fe5f5787 4390 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4392 __netif_tx_lock(txq, smp_processor_id());
4393 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4394 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4395 netif_tx_wake_queue(txq);
4396 __netif_tx_unlock(txq);
51b91468 4397 }
1da177e4
LT		 4398}
4399
4400/* Returns size of skb allocated or < 0 on error.
4401 *
4402 * We only need to fill in the address because the other members
4403 * of the RX descriptor are invariant, see tg3_init_rings.
4404 *
4405 * Note the purposeful assymetry of cpu vs. chip accesses. For
4406 * posting buffers we only dirty the first cache line of the RX
4407 * descriptor (containing the address). Whereas for the RX status
4408 * buffers the cpu only reads the last cacheline of the RX descriptor
4409 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410 */
17375d25 4411static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
afc081f8 4412 u32 dest_idx_unmasked)
1da177e4 4413{
17375d25 4414 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4415 struct tg3_rx_buffer_desc *desc;
4416 struct ring_info *map, *src_map;
4417 struct sk_buff *skb;
4418 dma_addr_t mapping;
4419 int skb_size, dest_idx;
21f581a5 4420 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4421
4422 src_map = NULL;
4423 switch (opaque_key) {
4424 case RXD_OPAQUE_RING_STD:
4425 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4426 desc = &tpr->rx_std[dest_idx];
4427 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4428 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4429 break;
4430
4431 case RXD_OPAQUE_RING_JUMBO:
4432 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4433 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4434 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4435 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4436 break;
4437
4438 default:
4439 return -EINVAL;
855e1111 4440 }
1da177e4
LT		 4441
4442 /* Do not overwrite any of the map or rp information
4443 * until we are sure we can commit to a new buffer.
4444 *
4445 * Callers depend upon this behavior and assume that
4446 * we leave everything unchanged if we fail.
4447 */
287be12e 4448 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4449 if (skb == NULL)
4450 return -ENOMEM;
4451
1da177e4
LT		 4452 skb_reserve(skb, tp->rx_offset);
4453
287be12e 4454 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4455 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4456 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4457 dev_kfree_skb(skb);
4458 return -EIO;
4459 }
1da177e4
LT		 4460
4461 map->skb = skb;
4462 pci_unmap_addr_set(map, mapping, mapping);
4463
1da177e4
LT		 4464 desc->addr_hi = ((u64)mapping >> 32);
4465 desc->addr_lo = ((u64)mapping & 0xffffffff);
4466
4467 return skb_size;
4468}
4469
4470/* We only need to move over in the address because the other
4471 * members of the RX descriptor are invariant. See notes above
4472 * tg3_alloc_rx_skb for full details.
4473 */
17375d25 4474static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4475 int src_idx, u32 dest_idx_unmasked)
4476{
17375d25 4477 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4478 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4479 struct ring_info *src_map, *dest_map;
4480 int dest_idx;
21f581a5 4481 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4482
4483 switch (opaque_key) {
4484 case RXD_OPAQUE_RING_STD:
4485 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4486 dest_desc = &tpr->rx_std[dest_idx];
4487 dest_map = &tpr->rx_std_buffers[dest_idx];
4488 src_desc = &tpr->rx_std[src_idx];
4489 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4490 break;
4491
4492 case RXD_OPAQUE_RING_JUMBO:
4493 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4494 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4495 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4496 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4497 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4498 break;
4499
4500 default:
4501 return;
855e1111 4502 }
1da177e4
LT		 4503
4504 dest_map->skb = src_map->skb;
4505 pci_unmap_addr_set(dest_map, mapping,
4506 pci_unmap_addr(src_map, mapping));
4507 dest_desc->addr_hi = src_desc->addr_hi;
4508 dest_desc->addr_lo = src_desc->addr_lo;
4509
4510 src_map->skb = NULL;
4511}
4512
1da177e4
LT		 4513/* The RX ring scheme is composed of multiple rings which post fresh
4514 * buffers to the chip, and one special ring the chip uses to report
4515 * status back to the host.
4516 *
4517 * The special ring reports the status of received packets to the
4518 * host. The chip does not write into the original descriptor the
4519 * RX buffer was obtained from. The chip simply takes the original
4520 * descriptor as provided by the host, updates the status and length
4521 * field, then writes this into the next status ring entry.
4522 *
4523 * Each ring the host uses to post buffers to the chip is described
4524 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4525 * it is first placed into the on-chip ram. When the packet's length
4526 * is known, it walks down the TG3_BDINFO entries to select the ring.
4527 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4528 * which is within the range of the new packet's length is chosen.
4529 *
4530 * The "separate ring for rx status" scheme may sound queer, but it makes
4531 * sense from a cache coherency perspective. If only the host writes
4532 * to the buffer post rings, and only the chip writes to the rx status
4533 * rings, then cache lines never move beyond shared-modified state.
4534 * If both the host and chip were to write into the same ring, cache line
4535 * eviction could occur since both entities want it in an exclusive state.
4536 */
17375d25 4537static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4538{
17375d25 4539 struct tg3 *tp = tnapi->tp;
f92905de 4540 u32 work_mask, rx_std_posted = 0;
72334482 4541 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4542 u16 hw_idx;
1da177e4 4543 int received;
21f581a5 4544 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4545
8d9d7cfc 4546 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4547 /*
4548 * We need to order the read of hw_idx and the read of
4549 * the opaque cookie.
4550 */
4551 rmb();
1da177e4
LT		 4552 work_mask = 0;
4553 received = 0;
4554 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4555 struct ring_info *ri;
72334482 4556 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4557 unsigned int len;
4558 struct sk_buff *skb;
4559 dma_addr_t dma_addr;
4560 u32 opaque_key, desc_idx, *post_ptr;
4561
4562 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4563 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4564 if (opaque_key == RXD_OPAQUE_RING_STD) {
afc081f8 4565 ri = &tpr->rx_std_buffers[desc_idx];
21f581a5
MC		 4566 dma_addr = pci_unmap_addr(ri, mapping);
4567 skb = ri->skb;
4568 post_ptr = &tpr->rx_std_ptr;
f92905de 4569 rx_std_posted++;
1da177e4 4570 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
afc081f8 4571 ri = &tpr->rx_jmb_buffers[desc_idx];
21f581a5
MC		 4572 dma_addr = pci_unmap_addr(ri, mapping);
4573 skb = ri->skb;
4574 post_ptr = &tpr->rx_jmb_ptr;
4575 } else
1da177e4 4576 goto next_pkt_nopost;
1da177e4
LT		 4577
4578 work_mask |= opaque_key;
4579
4580 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4581 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4582 drop_it:
17375d25 4583 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4584 desc_idx, *post_ptr);
4585 drop_it_no_recycle:
4586 /* Other statistics kept track of by card. */
4587 tp->net_stats.rx_dropped++;
4588 goto next_pkt;
4589 }
4590
ad829268
MC		 4591 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4592 ETH_FCS_LEN;
1da177e4 4593
6aa20a22 4594 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4595 && tp->rx_offset == NET_IP_ALIGN
4596 /* rx_offset will likely not equal NET_IP_ALIGN
4597 * if this is a 5701 card running in PCI-X mode
4598 * [see tg3_get_invariants()]
4599 */
1da177e4
LT		 4600 ) {
4601 int skb_size;
4602
17375d25 4603 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
afc081f8 4604 *post_ptr);
1da177e4
LT		 4605 if (skb_size < 0)
4606 goto drop_it;
4607
afc081f8
MC		 4608 ri->skb = NULL;
4609
287be12e 4610 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4611 PCI_DMA_FROMDEVICE);
4612
4613 skb_put(skb, len);
4614 } else {
4615 struct sk_buff *copy_skb;
4616
17375d25 4617 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4618 desc_idx, *post_ptr);
4619
ad829268
MC		 4620 copy_skb = netdev_alloc_skb(tp->dev,
4621 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4622 if (copy_skb == NULL)
4623 goto drop_it_no_recycle;
4624
ad829268 4625 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4626 skb_put(copy_skb, len);
4627 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4628 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4629 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4630
4631 /* We'll reuse the original ring buffer. */
4632 skb = copy_skb;
4633 }
4634
4635 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4636 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4637 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4638 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4639 skb->ip_summed = CHECKSUM_UNNECESSARY;
4640 else
4641 skb->ip_summed = CHECKSUM_NONE;
4642
4643 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4644
4645 if (len > (tp->dev->mtu + ETH_HLEN) &&
4646 skb->protocol != htons(ETH_P_8021Q)) {
4647 dev_kfree_skb(skb);
4648 goto next_pkt;
4649 }
4650
1da177e4
LT		 4651#if TG3_VLAN_TAG_USED
4652 if (tp->vlgrp != NULL &&
4653 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4654 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4655 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4656 } else
4657#endif
17375d25 4658 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4659
1da177e4
LT		 4660 received++;
4661 budget--;
4662
4663next_pkt:
4664 (*post_ptr)++;
f92905de
MC		 4665
4666 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4667 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4668
4669 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4670 TG3_64BIT_REG_LOW, idx);
4671 work_mask &= ~RXD_OPAQUE_RING_STD;
4672 rx_std_posted = 0;
4673 }
1da177e4 4674next_pkt_nopost:
483ba50b 4675 sw_idx++;
6b31a515 4676 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4677
4678 /* Refresh hw_idx to see if there is new work */
4679 if (sw_idx == hw_idx) {
8d9d7cfc 4680 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4681 rmb();
4682 }
1da177e4
LT		 4683 }
4684
4685 /* ACK the status ring. */
72334482
MC		 4686 tnapi->rx_rcb_ptr = sw_idx;
4687 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4688
4689 /* Refill RX ring(s). */
4690 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4691 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4692 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4693 sw_idx);
4694 }
4695 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4696 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4697 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4698 sw_idx);
4699 }
4700 mmiowb();
4701
4702 return received;
4703}
4704
35f2d7d0 4705static void tg3_poll_link(struct tg3 *tp)
1da177e4 4706{
1da177e4
LT		 4707 /* handle link change and other phy events */
4708 if (!(tp->tg3_flags &
4709 (TG3_FLAG_USE_LINKCHG_REG |
4710 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4711 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4712
1da177e4
LT		 4713 if (sblk->status & SD_STATUS_LINK_CHG) {
4714 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4715 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4716 spin_lock(&tp->lock);
dd477003
MC		 4717 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4718 tw32_f(MAC_STATUS,
4719 (MAC_STATUS_SYNC_CHANGED |
4720 MAC_STATUS_CFG_CHANGED |
4721 MAC_STATUS_MI_COMPLETION |
4722 MAC_STATUS_LNKSTATE_CHANGED));
4723 udelay(40);
4724 } else
4725 tg3_setup_phy(tp, 0);
f47c11ee 4726 spin_unlock(&tp->lock);
1da177e4
LT		 4727 }
4728 }
35f2d7d0
MC		 4729}
4730
4731static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4732{
4733 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4734
4735 /* run TX completion thread */
f3f3f27e 4736 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4737 tg3_tx(tnapi);
6f535763 4738 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4739 return work_done;
1da177e4
LT		 4740 }
4741
1da177e4
LT		 4742 /* run RX thread, within the bounds set by NAPI.
4743 * All RX "locking" is done by ensuring outside
bea3348e 4744 * code synchronizes with tg3->napi.poll()
1da177e4 4745 */
8d9d7cfc 4746 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4747 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4748
6f535763
DM		 4749 return work_done;
4750}
4751
35f2d7d0
MC		 4752static int tg3_poll_msix(struct napi_struct *napi, int budget)
4753{
4754 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4755 struct tg3 *tp = tnapi->tp;
4756 int work_done = 0;
4757 struct tg3_hw_status *sblk = tnapi->hw_status;
4758
4759 while (1) {
4760 work_done = tg3_poll_work(tnapi, work_done, budget);
4761
4762 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4763 goto tx_recovery;
4764
4765 if (unlikely(work_done >= budget))
4766 break;
4767
4768 /* tp->last_tag is used in tg3_restart_ints() below
4769 * to tell the hw how much work has been processed,
4770 * so we must read it before checking for more work.
4771 */
4772 tnapi->last_tag = sblk->status_tag;
4773 tnapi->last_irq_tag = tnapi->last_tag;
4774 rmb();
4775
4776 /* check for RX/TX work to do */
4777 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4778 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4779 napi_complete(napi);
4780 /* Reenable interrupts. */
4781 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4782 mmiowb();
4783 break;
4784 }
4785 }
4786
4787 return work_done;
4788
4789tx_recovery:
4790 /* work_done is guaranteed to be less than budget. */
4791 napi_complete(napi);
4792 schedule_work(&tp->reset_task);
4793 return work_done;
4794}
4795
6f535763
DM		 4796static int tg3_poll(struct napi_struct *napi, int budget)
4797{
8ef0442f
MC		 4798 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4799 struct tg3 *tp = tnapi->tp;
6f535763 4800 int work_done = 0;
898a56f8 4801 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4802
4803 while (1) {
35f2d7d0
MC		 4804 tg3_poll_link(tp);
4805
17375d25 4806 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4807
4808 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4809 goto tx_recovery;
4810
4811 if (unlikely(work_done >= budget))
4812 break;
4813
4fd7ab59 4814 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4815 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4816 * to tell the hw how much work has been processed,
4817 * so we must read it before checking for more work.
4818 */
898a56f8
MC		 4819 tnapi->last_tag = sblk->status_tag;
4820 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4821 rmb();
4822 } else
4823 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4824
17375d25 4825 if (likely(!tg3_has_work(tnapi))) {
288379f0 4826 napi_complete(napi);
17375d25 4827 tg3_int_reenable(tnapi);
6f535763
DM		 4828 break;
4829 }
1da177e4
LT		 4830 }
4831
bea3348e 4832 return work_done;
6f535763
DM		 4833
4834tx_recovery:
4fd7ab59 4835 /* work_done is guaranteed to be less than budget. */
288379f0 4836 napi_complete(napi);
6f535763 4837 schedule_work(&tp->reset_task);
4fd7ab59 4838 return work_done;
1da177e4
LT		 4839}
4840
f47c11ee
DM		 4841static void tg3_irq_quiesce(struct tg3 *tp)
4842{
4f125f42
MC		 4843 int i;
4844
f47c11ee
DM		 4845 BUG_ON(tp->irq_sync);
4846
4847 tp->irq_sync = 1;
4848 smp_mb();
4849
4f125f42
MC		 4850 for (i = 0; i < tp->irq_cnt; i++)
4851 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4852}
4853
4854static inline int tg3_irq_sync(struct tg3 *tp)
4855{
4856 return tp->irq_sync;
4857}
4858
4859/* Fully shutdown all tg3 driver activity elsewhere in the system.
4860 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4861 * with as well. Most of the time, this is not necessary except when
4862 * shutting down the device.
4863 */
4864static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4865{
46966545 4866 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4867 if (irq_sync)
4868 tg3_irq_quiesce(tp);
f47c11ee
DM		 4869}
4870
4871static inline void tg3_full_unlock(struct tg3 *tp)
4872{
f47c11ee
DM		 4873 spin_unlock_bh(&tp->lock);
4874}
4875
fcfa0a32
MC		 4876/* One-shot MSI handler - Chip automatically disables interrupt
4877 * after sending MSI so driver doesn't have to do it.
4878 */
7d12e780 4879static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4880{
09943a18
MC		 4881 struct tg3_napi *tnapi = dev_id;
4882 struct tg3 *tp = tnapi->tp;
fcfa0a32 4883
898a56f8 4884 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4885 if (tnapi->rx_rcb)
4886 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4887
4888 if (likely(!tg3_irq_sync(tp)))
09943a18 4889 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4890
4891 return IRQ_HANDLED;
4892}
4893
88b06bc2
MC		 4894/* MSI ISR - No need to check for interrupt sharing and no need to
4895 * flush status block and interrupt mailbox. PCI ordering rules
4896 * guarantee that MSI will arrive after the status block.
4897 */
7d12e780 4898static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4899{
09943a18
MC		 4900 struct tg3_napi *tnapi = dev_id;
4901 struct tg3 *tp = tnapi->tp;
88b06bc2 4902
898a56f8 4903 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4904 if (tnapi->rx_rcb)
4905 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4906 /*
fac9b83e 4907 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4908 * chip-internal interrupt pending events.
fac9b83e 4909 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4910 * NIC to stop sending us irqs, engaging "in-intr-handler"
4911 * event coalescing.
4912 */
4913 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4914 if (likely(!tg3_irq_sync(tp)))
09943a18 4915 napi_schedule(&tnapi->napi);
61487480 4916
88b06bc2
MC		 4917 return IRQ_RETVAL(1);
4918}
4919
7d12e780 4920static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4921{
09943a18
MC		 4922 struct tg3_napi *tnapi = dev_id;
4923 struct tg3 *tp = tnapi->tp;
898a56f8 4924 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4925 unsigned int handled = 1;
4926
1da177e4
LT		 4927 /* In INTx mode, it is possible for the interrupt to arrive at
4928 * the CPU before the status block posted prior to the interrupt.
4929 * Reading the PCI State register will confirm whether the
4930 * interrupt is ours and will flush the status block.
4931 */
d18edcb2
MC		 4932 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4933 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4934 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4935 handled = 0;
f47c11ee 4936 goto out;
fac9b83e 4937 }
d18edcb2
MC		 4938 }
4939
4940 /*
4941 * Writing any value to intr-mbox-0 clears PCI INTA# and
4942 * chip-internal interrupt pending events.
4943 * Writing non-zero to intr-mbox-0 additional tells the
4944 * NIC to stop sending us irqs, engaging "in-intr-handler"
4945 * event coalescing.
c04cb347
MC		 4946 *
4947 * Flush the mailbox to de-assert the IRQ immediately to prevent
4948 * spurious interrupts. The flush impacts performance but
4949 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4950 */
c04cb347 4951 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4952 if (tg3_irq_sync(tp))
4953 goto out;
4954 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4955 if (likely(tg3_has_work(tnapi))) {
72334482 4956 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4957 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4958 } else {
4959 /* No work, shared interrupt perhaps? re-enable
4960 * interrupts, and flush that PCI write
4961 */
4962 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4963 0x00000000);
fac9b83e 4964 }
f47c11ee 4965out:
fac9b83e
DM		 4966 return IRQ_RETVAL(handled);
4967}
4968
7d12e780 4969static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4970{
09943a18
MC		 4971 struct tg3_napi *tnapi = dev_id;
4972 struct tg3 *tp = tnapi->tp;
898a56f8 4973 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4974 unsigned int handled = 1;
4975
fac9b83e
DM		 4976 /* In INTx mode, it is possible for the interrupt to arrive at
4977 * the CPU before the status block posted prior to the interrupt.
4978 * Reading the PCI State register will confirm whether the
4979 * interrupt is ours and will flush the status block.
4980 */
898a56f8 4981 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4982 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4983 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4984 handled = 0;
f47c11ee 4985 goto out;
1da177e4 4986 }
d18edcb2
MC		 4987 }
4988
4989 /*
4990 * writing any value to intr-mbox-0 clears PCI INTA# and
4991 * chip-internal interrupt pending events.
4992 * writing non-zero to intr-mbox-0 additional tells the
4993 * NIC to stop sending us irqs, engaging "in-intr-handler"
4994 * event coalescing.
c04cb347
MC		 4995 *
4996 * Flush the mailbox to de-assert the IRQ immediately to prevent
4997 * spurious interrupts. The flush impacts performance but
4998 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4999 */
c04cb347 5000 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5001
5002 /*
5003 * In a shared interrupt configuration, sometimes other devices'
5004 * interrupts will scream. We record the current status tag here
5005 * so that the above check can report that the screaming interrupts
5006 * are unhandled. Eventually they will be silenced.
5007 */
898a56f8 5008 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5009
d18edcb2
MC		 5010 if (tg3_irq_sync(tp))
5011 goto out;
624f8e50 5012
72334482 5013 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5014
09943a18 5015 napi_schedule(&tnapi->napi);
624f8e50 5016
f47c11ee 5017out:
1da177e4
LT		 5018 return IRQ_RETVAL(handled);
5019}
5020
7938109f 5021/* ISR for interrupt test */
7d12e780 5022static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5023{
09943a18
MC		 5024 struct tg3_napi *tnapi = dev_id;
5025 struct tg3 *tp = tnapi->tp;
898a56f8 5026 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5027
f9804ddb
MC		 5028 if ((sblk->status & SD_STATUS_UPDATED) ||
5029 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5030 tg3_disable_ints(tp);
7938109f
MC		 5031 return IRQ_RETVAL(1);
5032 }
5033 return IRQ_RETVAL(0);
5034}
5035
8e7a22e3 5036static int tg3_init_hw(struct tg3 *, int);
944d980e 5037static int tg3_halt(struct tg3 *, int, int);
1da177e4 5038
b9ec6c1b
MC		 5039/* Restart hardware after configuration changes, self-test, etc.
5040 * Invoked with tp->lock held.
5041 */
5042static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5043 __releases(tp->lock)
5044 __acquires(tp->lock)
b9ec6c1b
MC		 5045{
5046 int err;
5047
5048 err = tg3_init_hw(tp, reset_phy);
5049 if (err) {
5050 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5051 "aborting.\n", tp->dev->name);
5052 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5053 tg3_full_unlock(tp);
5054 del_timer_sync(&tp->timer);
5055 tp->irq_sync = 0;
fed97810 5056 tg3_napi_enable(tp);
b9ec6c1b
MC		 5057 dev_close(tp->dev);
5058 tg3_full_lock(tp, 0);
5059 }
5060 return err;
5061}
5062
1da177e4
LT		 5063#ifdef CONFIG_NET_POLL_CONTROLLER
5064static void tg3_poll_controller(struct net_device *dev)
5065{
4f125f42 5066 int i;
88b06bc2
MC		 5067 struct tg3 *tp = netdev_priv(dev);
5068
4f125f42
MC		 5069 for (i = 0; i < tp->irq_cnt; i++)
5070 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5071}
5072#endif
5073
c4028958 5074static void tg3_reset_task(struct work_struct *work)
1da177e4 5075{
c4028958 5076 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5077 int err;
1da177e4
LT		 5078 unsigned int restart_timer;
5079
7faa006f 5080 tg3_full_lock(tp, 0);
7faa006f
MC		 5081
5082 if (!netif_running(tp->dev)) {
7faa006f
MC		 5083 tg3_full_unlock(tp);
5084 return;
5085 }
5086
5087 tg3_full_unlock(tp);
5088
b02fd9e3
MC		 5089 tg3_phy_stop(tp);
5090
1da177e4
LT		 5091 tg3_netif_stop(tp);
5092
f47c11ee 5093 tg3_full_lock(tp, 1);
1da177e4
LT		 5094
5095 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5096 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5097
df3e6548
MC		 5098 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5099 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5100 tp->write32_rx_mbox = tg3_write_flush_reg32;
5101 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5102 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5103 }
5104
944d980e 5105 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5106 err = tg3_init_hw(tp, 1);
5107 if (err)
b9ec6c1b 5108 goto out;
1da177e4
LT		 5109
5110 tg3_netif_start(tp);
5111
1da177e4
LT		 5112 if (restart_timer)
5113 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5114
b9ec6c1b 5115out:
7faa006f 5116 tg3_full_unlock(tp);
b02fd9e3
MC		 5117
5118 if (!err)
5119 tg3_phy_start(tp);
1da177e4
LT		 5120}
5121
b0408751
MC		 5122static void tg3_dump_short_state(struct tg3 *tp)
5123{
5124 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5125 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5126 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5127 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5128}
5129
1da177e4
LT		 5130static void tg3_tx_timeout(struct net_device *dev)
5131{
5132 struct tg3 *tp = netdev_priv(dev);
5133
b0408751 5134 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5135 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5136 dev->name);
b0408751
MC		 5137 tg3_dump_short_state(tp);
5138 }
1da177e4
LT		 5139
5140 schedule_work(&tp->reset_task);
5141}
5142
c58ec932
MC		 5143/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5144static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5145{
5146 u32 base = (u32) mapping & 0xffffffff;
5147
5148 return ((base > 0xffffdcc0) &&
5149 (base + len + 8 < base));
5150}
5151
72f2afb8
MC		 5152/* Test for DMA addresses > 40-bit */
5153static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5154 int len)
5155{
5156#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5157 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5158 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5159 return 0;
5160#else
5161 return 0;
5162#endif
5163}
5164
f3f3f27e 5165static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5166
72f2afb8 5167/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5168static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5169 struct sk_buff *skb, u32 last_plus_one,
5170 u32 *start, u32 base_flags, u32 mss)
1da177e4 5171{
24f4efd4 5172 struct tg3 *tp = tnapi->tp;
41588ba1 5173 struct sk_buff *new_skb;
c58ec932 5174 dma_addr_t new_addr = 0;
1da177e4 5175 u32 entry = *start;
c58ec932 5176 int i, ret = 0;
1da177e4 5177
41588ba1
MC		 5178 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5179 new_skb = skb_copy(skb, GFP_ATOMIC);
5180 else {
5181 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5182
5183 new_skb = skb_copy_expand(skb,
5184 skb_headroom(skb) + more_headroom,
5185 skb_tailroom(skb), GFP_ATOMIC);
5186 }
5187
1da177e4 5188 if (!new_skb) {
c58ec932
MC		 5189 ret = -1;
5190 } else {
5191 /* New SKB is guaranteed to be linear. */
5192 entry = *start;
90079ce8 5193 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5194 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5195
c58ec932
MC		 5196 /* Make sure new skb does not cross any 4G boundaries.
5197 * Drop the packet if it does.
5198 */
0e1406dd
MC		 5199 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5200 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5201 if (!ret)
5202 skb_dma_unmap(&tp->pdev->dev, new_skb,
5203 DMA_TO_DEVICE);
c58ec932
MC		 5204 ret = -1;
5205 dev_kfree_skb(new_skb);
5206 new_skb = NULL;
5207 } else {
f3f3f27e 5208 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5209 base_flags, 1 | (mss << 1));
5210 *start = NEXT_TX(entry);
5211 }
1da177e4
LT		 5212 }
5213
1da177e4
LT		 5214 /* Now clean up the sw ring entries. */
5215 i = 0;
5216 while (entry != last_plus_one) {
f3f3f27e
MC		 5217 if (i == 0)
5218 tnapi->tx_buffers[entry].skb = new_skb;
5219 else
5220 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5221 entry = NEXT_TX(entry);
5222 i++;
5223 }
5224
90079ce8 5225 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5226 dev_kfree_skb(skb);
5227
c58ec932 5228 return ret;
1da177e4
LT		 5229}
5230
f3f3f27e 5231static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5232 dma_addr_t mapping, int len, u32 flags,
5233 u32 mss_and_is_end)
5234{
f3f3f27e 5235 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5236 int is_end = (mss_and_is_end & 0x1);
5237 u32 mss = (mss_and_is_end >> 1);
5238 u32 vlan_tag = 0;
5239
5240 if (is_end)
5241 flags |= TXD_FLAG_END;
5242 if (flags & TXD_FLAG_VLAN) {
5243 vlan_tag = flags >> 16;
5244 flags &= 0xffff;
5245 }
5246 vlan_tag |= (mss << TXD_MSS_SHIFT);
5247
5248 txd->addr_hi = ((u64) mapping >> 32);
5249 txd->addr_lo = ((u64) mapping & 0xffffffff);
5250 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5251 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5252}
5253
5a6f3074 5254/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5255 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5256 */
61357325
SH		 5257static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5258 struct net_device *dev)
5a6f3074
MC		 5259{
5260 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5261 u32 len, entry, base_flags, mss;
90079ce8
DM		 5262 struct skb_shared_info *sp;
5263 dma_addr_t mapping;
fe5f5787
MC		 5264 struct tg3_napi *tnapi;
5265 struct netdev_queue *txq;
5a6f3074 5266
fe5f5787
MC		 5267 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5268 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5269 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5270 tnapi++;
5a6f3074 5271
00b70504 5272 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5273 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5274 * interrupt. Furthermore, IRQ processing runs lockless so we have
5275 * no IRQ context deadlocks to worry about either. Rejoice!
5276 */
f3f3f27e 5277 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5278 if (!netif_tx_queue_stopped(txq)) {
5279 netif_tx_stop_queue(txq);
5a6f3074
MC		 5280
5281 /* This is a hard error, log it. */
5282 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5283 "queue awake!\n", dev->name);
5284 }
5a6f3074
MC		 5285 return NETDEV_TX_BUSY;
5286 }
5287
f3f3f27e 5288 entry = tnapi->tx_prod;
5a6f3074 5289 base_flags = 0;
5a6f3074 5290 mss = 0;
c13e3713 5291 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5292 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5293 u32 hdrlen;
5a6f3074
MC		 5294
5295 if (skb_header_cloned(skb) &&
5296 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5297 dev_kfree_skb(skb);
5298 goto out_unlock;
5299 }
5300
b0026624 5301 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5302 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5303 else {
eddc9ec5
ACM		 5304 struct iphdr *iph = ip_hdr(skb);
5305
ab6a5bb6 5306 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5307 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5308
eddc9ec5
ACM		 5309 iph->check = 0;
5310 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5311 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5312 }
5a6f3074 5313
e849cdc3 5314 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5315 mss |= (hdrlen & 0xc) << 12;
5316 if (hdrlen & 0x10)
5317 base_flags |= 0x00000010;
5318 base_flags |= (hdrlen & 0x3e0) << 5;
5319 } else
5320 mss |= hdrlen << 9;
5321
5a6f3074
MC		 5322 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5323 TXD_FLAG_CPU_POST_DMA);
5324
aa8223c7 5325 tcp_hdr(skb)->check = 0;
5a6f3074 5326
5a6f3074 5327 }
84fa7933 5328 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5329 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5330#if TG3_VLAN_TAG_USED
5331 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5332 base_flags |= (TXD_FLAG_VLAN |
5333 (vlan_tx_tag_get(skb) << 16));
5334#endif
5335
90079ce8
DM		 5336 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5337 dev_kfree_skb(skb);
5338 goto out_unlock;
5339 }
5340
5341 sp = skb_shinfo(skb);
5342
042a53a9 5343 mapping = sp->dma_head;
5a6f3074 5344
f3f3f27e 5345 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5346
fe5f5787
MC		 5347 len = skb_headlen(skb);
5348
f6eb9b1f
MC		 5349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5350 !mss && skb->len > ETH_DATA_LEN)
5351 base_flags |= TXD_FLAG_JMB_PKT;
5352
f3f3f27e 5353 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5354 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5355
5356 entry = NEXT_TX(entry);
5357
5358 /* Now loop through additional data fragments, and queue them. */
5359 if (skb_shinfo(skb)->nr_frags > 0) {
5360 unsigned int i, last;
5361
5362 last = skb_shinfo(skb)->nr_frags - 1;
5363 for (i = 0; i <= last; i++) {
5364 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5365
5366 len = frag->size;
042a53a9 5367 mapping = sp->dma_maps[i];
f3f3f27e 5368 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5369
f3f3f27e 5370 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5371 base_flags, (i == last) | (mss << 1));
5372
5373 entry = NEXT_TX(entry);
5374 }
5375 }
5376
5377 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5378 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5379
f3f3f27e
MC		 5380 tnapi->tx_prod = entry;
5381 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5382 netif_tx_stop_queue(txq);
f3f3f27e 5383 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5384 netif_tx_wake_queue(txq);
5a6f3074
MC		 5385 }
5386
5387out_unlock:
cdd0db05 5388 mmiowb();
5a6f3074
MC		 5389
5390 return NETDEV_TX_OK;
5391}
5392
61357325
SH		 5393static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5394 struct net_device *);
52c0fd83
MC		 5395
5396/* Use GSO to workaround a rare TSO bug that may be triggered when the
5397 * TSO header is greater than 80 bytes.
5398 */
5399static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5400{
5401 struct sk_buff *segs, *nskb;
f3f3f27e 5402 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5403
5404 /* Estimate the number of fragments in the worst case */
f3f3f27e 5405 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5406 netif_stop_queue(tp->dev);
f3f3f27e 5407 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5408 return NETDEV_TX_BUSY;
5409
5410 netif_wake_queue(tp->dev);
52c0fd83
MC		 5411 }
5412
5413 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5414 if (IS_ERR(segs))
52c0fd83
MC		 5415 goto tg3_tso_bug_end;
5416
5417 do {
5418 nskb = segs;
5419 segs = segs->next;
5420 nskb->next = NULL;
5421 tg3_start_xmit_dma_bug(nskb, tp->dev);
5422 } while (segs);
5423
5424tg3_tso_bug_end:
5425 dev_kfree_skb(skb);
5426
5427 return NETDEV_TX_OK;
5428}
52c0fd83 5429
5a6f3074
MC		 5430/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5431 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5432 */
61357325
SH		 5433static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5434 struct net_device *dev)
1da177e4
LT		 5435{
5436 struct tg3 *tp = netdev_priv(dev);
1da177e4 5437 u32 len, entry, base_flags, mss;
90079ce8 5438 struct skb_shared_info *sp;
1da177e4 5439 int would_hit_hwbug;
90079ce8 5440 dma_addr_t mapping;
24f4efd4
MC		 5441 struct tg3_napi *tnapi;
5442 struct netdev_queue *txq;
1da177e4 5443
24f4efd4
MC		 5444 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5445 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5446 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5447 tnapi++;
1da177e4 5448
00b70504 5449 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5450 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5451 * interrupt. Furthermore, IRQ processing runs lockless so we have
5452 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5453 */
f3f3f27e 5454 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5455 if (!netif_tx_queue_stopped(txq)) {
5456 netif_tx_stop_queue(txq);
1f064a87
SH		 5457
5458 /* This is a hard error, log it. */
5459 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5460 "queue awake!\n", dev->name);
5461 }
1da177e4
LT		 5462 return NETDEV_TX_BUSY;
5463 }
5464
f3f3f27e 5465 entry = tnapi->tx_prod;
1da177e4 5466 base_flags = 0;
84fa7933 5467 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5468 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5469
c13e3713 5470 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5471 struct iphdr *iph;
92c6b8d1 5472 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5473
5474 if (skb_header_cloned(skb) &&
5475 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5476 dev_kfree_skb(skb);
5477 goto out_unlock;
5478 }
5479
ab6a5bb6 5480 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5481 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5482
52c0fd83
MC		 5483 hdr_len = ip_tcp_len + tcp_opt_len;
5484 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5485 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5486 return (tg3_tso_bug(tp, skb));
5487
1da177e4
LT		 5488 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5489 TXD_FLAG_CPU_POST_DMA);
5490
eddc9ec5
ACM		 5491 iph = ip_hdr(skb);
5492 iph->check = 0;
5493 iph->tot_len = htons(mss + hdr_len);
1da177e4 5494 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5495 tcp_hdr(skb)->check = 0;
1da177e4 5496 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5497 } else
5498 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5499 iph->daddr, 0,
5500 IPPROTO_TCP,
5501 0);
1da177e4 5502
615774fe
MC		 5503 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5504 mss |= (hdr_len & 0xc) << 12;
5505 if (hdr_len & 0x10)
5506 base_flags |= 0x00000010;
5507 base_flags |= (hdr_len & 0x3e0) << 5;
5508 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5509 mss |= hdr_len << 9;
5510 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5512 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5513 int tsflags;
5514
eddc9ec5 5515 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5516 mss |= (tsflags << 11);
5517 }
5518 } else {
eddc9ec5 5519 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5520 int tsflags;
5521
eddc9ec5 5522 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5523 base_flags |= tsflags << 12;
5524 }
5525 }
5526 }
1da177e4
LT		 5527#if TG3_VLAN_TAG_USED
5528 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5529 base_flags |= (TXD_FLAG_VLAN |
5530 (vlan_tx_tag_get(skb) << 16));
5531#endif
5532
615774fe
MC		 5533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5534 !mss && skb->len > ETH_DATA_LEN)
5535 base_flags |= TXD_FLAG_JMB_PKT;
5536
90079ce8
DM		 5537 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5538 dev_kfree_skb(skb);
5539 goto out_unlock;
5540 }
5541
5542 sp = skb_shinfo(skb);
5543
042a53a9 5544 mapping = sp->dma_head;
1da177e4 5545
f3f3f27e 5546 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5547
5548 would_hit_hwbug = 0;
5549
24f4efd4
MC		 5550 len = skb_headlen(skb);
5551
92c6b8d1
MC		 5552 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5553 would_hit_hwbug = 1;
5554
0e1406dd
MC		 5555 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5556 tg3_4g_overflow_test(mapping, len))
5557 would_hit_hwbug = 1;
5558
5559 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5560 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5561 would_hit_hwbug = 1;
0e1406dd
MC		 5562
5563 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5564 would_hit_hwbug = 1;
1da177e4 5565
f3f3f27e 5566 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5567 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5568
5569 entry = NEXT_TX(entry);
5570
5571 /* Now loop through additional data fragments, and queue them. */
5572 if (skb_shinfo(skb)->nr_frags > 0) {
5573 unsigned int i, last;
5574
5575 last = skb_shinfo(skb)->nr_frags - 1;
5576 for (i = 0; i <= last; i++) {
5577 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5578
5579 len = frag->size;
042a53a9 5580 mapping = sp->dma_maps[i];
1da177e4 5581
f3f3f27e 5582 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5583
92c6b8d1
MC		 5584 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5585 len <= 8)
5586 would_hit_hwbug = 1;
5587
0e1406dd
MC		 5588 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5589 tg3_4g_overflow_test(mapping, len))
c58ec932 5590 would_hit_hwbug = 1;
1da177e4 5591
0e1406dd
MC		 5592 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5593 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5594 would_hit_hwbug = 1;
5595
1da177e4 5596 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5597 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5598 base_flags, (i == last)|(mss << 1));
5599 else
f3f3f27e 5600 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5601 base_flags, (i == last));
5602
5603 entry = NEXT_TX(entry);
5604 }
5605 }
5606
5607 if (would_hit_hwbug) {
5608 u32 last_plus_one = entry;
5609 u32 start;
1da177e4 5610
c58ec932
MC		 5611 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5612 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5613
5614 /* If the workaround fails due to memory/mapping
5615 * failure, silently drop this packet.
5616 */
24f4efd4 5617 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5618 &start, base_flags, mss))
1da177e4
LT		 5619 goto out_unlock;
5620
5621 entry = start;
5622 }
5623
5624 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5625 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5626
f3f3f27e
MC		 5627 tnapi->tx_prod = entry;
5628 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5629 netif_tx_stop_queue(txq);
f3f3f27e 5630 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5631 netif_tx_wake_queue(txq);
51b91468 5632 }
1da177e4
LT		 5633
5634out_unlock:
cdd0db05 5635 mmiowb();
1da177e4
LT		 5636
5637 return NETDEV_TX_OK;
5638}
5639
5640static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5641 int new_mtu)
5642{
5643 dev->mtu = new_mtu;
5644
ef7f5ec0 5645 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5646 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5647 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5648 ethtool_op_set_tso(dev, 0);
5649 }
5650 else
5651 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5652 } else {
a4e2b347 5653 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5654 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5655 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5656 }
1da177e4
LT		 5657}
5658
5659static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5660{
5661 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5662 int err;
1da177e4
LT		 5663
5664 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5665 return -EINVAL;
5666
5667 if (!netif_running(dev)) {
5668 /* We'll just catch it later when the
5669 * device is up'd.
5670 */
5671 tg3_set_mtu(dev, tp, new_mtu);
5672 return 0;
5673 }
5674
b02fd9e3
MC		 5675 tg3_phy_stop(tp);
5676
1da177e4 5677 tg3_netif_stop(tp);
f47c11ee
DM		 5678
5679 tg3_full_lock(tp, 1);
1da177e4 5680
944d980e 5681 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5682
5683 tg3_set_mtu(dev, tp, new_mtu);
5684
b9ec6c1b 5685 err = tg3_restart_hw(tp, 0);
1da177e4 5686
b9ec6c1b
MC		 5687 if (!err)
5688 tg3_netif_start(tp);
1da177e4 5689
f47c11ee 5690 tg3_full_unlock(tp);
1da177e4 5691
b02fd9e3
MC		 5692 if (!err)
5693 tg3_phy_start(tp);
5694
b9ec6c1b 5695 return err;
1da177e4
LT		 5696}
5697
21f581a5
MC		 5698static void tg3_rx_prodring_free(struct tg3 *tp,
5699 struct tg3_rx_prodring_set *tpr)
1da177e4 5700{
1da177e4 5701 int i;
f3f3f27e 5702 struct ring_info *rxp;
1da177e4
LT		 5703
5704 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5705 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5706
5707 if (rxp->skb == NULL)
5708 continue;
1da177e4 5709
1da177e4
LT		 5710 pci_unmap_single(tp->pdev,
5711 pci_unmap_addr(rxp, mapping),
cf7a7298 5712 tp->rx_pkt_map_sz,
1da177e4
LT		 5713 PCI_DMA_FROMDEVICE);
5714 dev_kfree_skb_any(rxp->skb);
5715 rxp->skb = NULL;
5716 }
5717
cf7a7298
MC		 5718 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5719 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5720 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5721
cf7a7298
MC		 5722 if (rxp->skb == NULL)
5723 continue;
1da177e4 5724
cf7a7298
MC		 5725 pci_unmap_single(tp->pdev,
5726 pci_unmap_addr(rxp, mapping),
5727 TG3_RX_JMB_MAP_SZ,
5728 PCI_DMA_FROMDEVICE);
5729 dev_kfree_skb_any(rxp->skb);
5730 rxp->skb = NULL;
1da177e4 5731 }
1da177e4
LT		 5732 }
5733}
5734
5735/* Initialize tx/rx rings for packet processing.
5736 *
5737 * The chip has been shut down and the driver detached from
5738 * the networking, so no interrupts or new tx packets will
5739 * end up in the driver. tp->{tx,}lock are held and thus
5740 * we may not sleep.
5741 */
21f581a5
MC		 5742static int tg3_rx_prodring_alloc(struct tg3 *tp,
5743 struct tg3_rx_prodring_set *tpr)
1da177e4 5744{
287be12e 5745 u32 i, rx_pkt_dma_sz;
17375d25 5746 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5747
1da177e4 5748 /* Zero out all descriptors. */
21f581a5 5749 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5750
287be12e 5751 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5752 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5753 tp->dev->mtu > ETH_DATA_LEN)
5754 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5755 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5756
1da177e4
LT		 5757 /* Initialize invariants of the rings, we only set this
5758 * stuff once. This works because the card does not
5759 * write into the rx buffer posting rings.
5760 */
5761 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5762 struct tg3_rx_buffer_desc *rxd;
5763
21f581a5 5764 rxd = &tpr->rx_std[i];
287be12e 5765 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5766 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5767 rxd->opaque = (RXD_OPAQUE_RING_STD |
5768 (i << RXD_OPAQUE_INDEX_SHIFT));
5769 }
5770
1da177e4
LT		 5771 /* Now allocate fresh SKBs for each rx ring. */
5772 for (i = 0; i < tp->rx_pending; i++) {
afc081f8 5773 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 5774 printk(KERN_WARNING PFX
5775 "%s: Using a smaller RX standard ring, "
5776 "only %d out of %d buffers were allocated "
5777 "successfully.\n",
5778 tp->dev->name, i, tp->rx_pending);
5779 if (i == 0)
cf7a7298 5780 goto initfail;
32d8c572 5781 tp->rx_pending = i;
1da177e4 5782 break;
32d8c572 5783 }
1da177e4
LT		 5784 }
5785
cf7a7298
MC		 5786 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5787 goto done;
5788
21f581a5 5789 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5790
0f893dc6 5791 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5792 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5793 struct tg3_rx_buffer_desc *rxd;
5794
79ed5ac7 5795 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5796 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5797 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5798 RXD_FLAG_JUMBO;
5799 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5800 (i << RXD_OPAQUE_INDEX_SHIFT));
5801 }
5802
1da177e4 5803 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5804 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
afc081f8 5805 i) < 0) {
32d8c572
MC		 5806 printk(KERN_WARNING PFX
5807 "%s: Using a smaller RX jumbo ring, "
5808 "only %d out of %d buffers were "
5809 "allocated successfully.\n",
5810 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5811 if (i == 0)
5812 goto initfail;
32d8c572 5813 tp->rx_jumbo_pending = i;
1da177e4 5814 break;
32d8c572 5815 }
1da177e4
LT		 5816 }
5817 }
cf7a7298
MC		 5818
5819done:
32d8c572 5820 return 0;
cf7a7298
MC		 5821
5822initfail:
21f581a5 5823 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5824 return -ENOMEM;
1da177e4
LT		 5825}
5826
21f581a5
MC		 5827static void tg3_rx_prodring_fini(struct tg3 *tp,
5828 struct tg3_rx_prodring_set *tpr)
1da177e4 5829{
21f581a5
MC		 5830 kfree(tpr->rx_std_buffers);
5831 tpr->rx_std_buffers = NULL;
5832 kfree(tpr->rx_jmb_buffers);
5833 tpr->rx_jmb_buffers = NULL;
5834 if (tpr->rx_std) {
1da177e4 5835 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5836 tpr->rx_std, tpr->rx_std_mapping);
5837 tpr->rx_std = NULL;
1da177e4 5838 }
21f581a5 5839 if (tpr->rx_jmb) {
1da177e4 5840 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5841 tpr->rx_jmb, tpr->rx_jmb_mapping);
5842 tpr->rx_jmb = NULL;
1da177e4 5843 }
cf7a7298
MC		 5844}
5845
21f581a5
MC		 5846static int tg3_rx_prodring_init(struct tg3 *tp,
5847 struct tg3_rx_prodring_set *tpr)
cf7a7298 5848{
21f581a5
MC		 5849 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5850 TG3_RX_RING_SIZE, GFP_KERNEL);
5851 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5852 return -ENOMEM;
5853
21f581a5
MC		 5854 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5855 &tpr->rx_std_mapping);
5856 if (!tpr->rx_std)
cf7a7298
MC		 5857 goto err_out;
5858
5859 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5860 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5861 TG3_RX_JUMBO_RING_SIZE,
5862 GFP_KERNEL);
5863 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5864 goto err_out;
5865
21f581a5
MC		 5866 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5867 TG3_RX_JUMBO_RING_BYTES,
5868 &tpr->rx_jmb_mapping);
5869 if (!tpr->rx_jmb)
cf7a7298
MC		 5870 goto err_out;
5871 }
5872
5873 return 0;
5874
5875err_out:
21f581a5 5876 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5877 return -ENOMEM;
5878}
5879
5880/* Free up pending packets in all rx/tx rings.
5881 *
5882 * The chip has been shut down and the driver detached from
5883 * the networking, so no interrupts or new tx packets will
5884 * end up in the driver. tp->{tx,}lock is not held and we are not
5885 * in an interrupt context and thus may sleep.
5886 */
5887static void tg3_free_rings(struct tg3 *tp)
5888{
f77a6a8e 5889 int i, j;
cf7a7298 5890
f77a6a8e
MC		 5891 for (j = 0; j < tp->irq_cnt; j++) {
5892 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5893
0c1d0e2b
MC		 5894 if (!tnapi->tx_buffers)
5895 continue;
5896
f77a6a8e
MC		 5897 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5898 struct tx_ring_info *txp;
5899 struct sk_buff *skb;
cf7a7298 5900
f77a6a8e
MC		 5901 txp = &tnapi->tx_buffers[i];
5902 skb = txp->skb;
cf7a7298 5903
f77a6a8e
MC		 5904 if (skb == NULL) {
5905 i++;
5906 continue;
5907 }
cf7a7298 5908
f77a6a8e 5909 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5910
f77a6a8e 5911 txp->skb = NULL;
cf7a7298 5912
f77a6a8e
MC		 5913 i += skb_shinfo(skb)->nr_frags + 1;
5914
5915 dev_kfree_skb_any(skb);
5916 }
cf7a7298
MC		 5917 }
5918
21f581a5 5919 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5920}
5921
5922/* Initialize tx/rx rings for packet processing.
5923 *
5924 * The chip has been shut down and the driver detached from
5925 * the networking, so no interrupts or new tx packets will
5926 * end up in the driver. tp->{tx,}lock are held and thus
5927 * we may not sleep.
5928 */
5929static int tg3_init_rings(struct tg3 *tp)
5930{
f77a6a8e 5931 int i;
72334482 5932
cf7a7298
MC		 5933 /* Free up all the SKBs. */
5934 tg3_free_rings(tp);
5935
f77a6a8e
MC		 5936 for (i = 0; i < tp->irq_cnt; i++) {
5937 struct tg3_napi *tnapi = &tp->napi[i];
5938
5939 tnapi->last_tag = 0;
5940 tnapi->last_irq_tag = 0;
5941 tnapi->hw_status->status = 0;
5942 tnapi->hw_status->status_tag = 0;
5943 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5944
f77a6a8e
MC		 5945 tnapi->tx_prod = 0;
5946 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5947 if (tnapi->tx_ring)
5948 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5949
5950 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5951 if (tnapi->rx_rcb)
5952 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5953 }
72334482 5954
21f581a5 5955 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5956}
5957
5958/*
5959 * Must not be invoked with interrupt sources disabled and
5960 * the hardware shutdown down.
5961 */
5962static void tg3_free_consistent(struct tg3 *tp)
5963{
f77a6a8e 5964 int i;
898a56f8 5965
f77a6a8e
MC		 5966 for (i = 0; i < tp->irq_cnt; i++) {
5967 struct tg3_napi *tnapi = &tp->napi[i];
5968
5969 if (tnapi->tx_ring) {
5970 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5971 tnapi->tx_ring, tnapi->tx_desc_mapping);
5972 tnapi->tx_ring = NULL;
5973 }
5974
5975 kfree(tnapi->tx_buffers);
5976 tnapi->tx_buffers = NULL;
5977
5978 if (tnapi->rx_rcb) {
5979 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5980 tnapi->rx_rcb,
5981 tnapi->rx_rcb_mapping);
5982 tnapi->rx_rcb = NULL;
5983 }
5984
5985 if (tnapi->hw_status) {
5986 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5987 tnapi->hw_status,
5988 tnapi->status_mapping);
5989 tnapi->hw_status = NULL;
5990 }
1da177e4 5991 }
f77a6a8e 5992
1da177e4
LT		 5993 if (tp->hw_stats) {
5994 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5995 tp->hw_stats, tp->stats_mapping);
5996 tp->hw_stats = NULL;
5997 }
f77a6a8e 5998
21f581a5 5999 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 6000}
6001
6002/*
6003 * Must not be invoked with interrupt sources disabled and
6004 * the hardware shutdown down. Can sleep.
6005 */
6006static int tg3_alloc_consistent(struct tg3 *tp)
6007{
f77a6a8e 6008 int i;
898a56f8 6009
21f581a5 6010 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 6011 return -ENOMEM;
6012
f77a6a8e
MC		 6013 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6014 sizeof(struct tg3_hw_stats),
6015 &tp->stats_mapping);
6016 if (!tp->hw_stats)
1da177e4
LT		 6017 goto err_out;
6018
f77a6a8e 6019 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6020
f77a6a8e
MC		 6021 for (i = 0; i < tp->irq_cnt; i++) {
6022 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6023 struct tg3_hw_status *sblk;
1da177e4 6024
f77a6a8e
MC		 6025 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6026 TG3_HW_STATUS_SIZE,
6027 &tnapi->status_mapping);
6028 if (!tnapi->hw_status)
6029 goto err_out;
898a56f8 6030
f77a6a8e 6031 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6032 sblk = tnapi->hw_status;
6033
6034 /*
6035 * When RSS is enabled, the status block format changes
6036 * slightly. The "rx_jumbo_consumer", "reserved",
6037 * and "rx_mini_consumer" members get mapped to the
6038 * other three rx return ring producer indexes.
6039 */
6040 switch (i) {
6041 default:
6042 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6043 break;
6044 case 2:
6045 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6046 break;
6047 case 3:
6048 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6049 break;
6050 case 4:
6051 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6052 break;
6053 }
72334482 6054
0c1d0e2b
MC		 6055 /*
6056 * If multivector RSS is enabled, vector 0 does not handle
6057 * rx or tx interrupts. Don't allocate any resources for it.
6058 */
6059 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6060 continue;
6061
f77a6a8e
MC		 6062 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6063 TG3_RX_RCB_RING_BYTES(tp),
6064 &tnapi->rx_rcb_mapping);
6065 if (!tnapi->rx_rcb)
6066 goto err_out;
72334482 6067
f77a6a8e 6068 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6069
f77a6a8e
MC		 6070 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6071 TG3_TX_RING_SIZE, GFP_KERNEL);
6072 if (!tnapi->tx_buffers)
6073 goto err_out;
6074
6075 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6076 TG3_TX_RING_BYTES,
6077 &tnapi->tx_desc_mapping);
6078 if (!tnapi->tx_ring)
6079 goto err_out;
6080 }
1da177e4
LT		 6081
6082 return 0;
6083
6084err_out:
6085 tg3_free_consistent(tp);
6086 return -ENOMEM;
6087}
6088
6089#define MAX_WAIT_CNT 1000
6090
6091/* To stop a block, clear the enable bit and poll till it
6092 * clears. tp->lock is held.
6093 */
b3b7d6be 6094static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6095{
6096 unsigned int i;
6097 u32 val;
6098
6099 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6100 switch (ofs) {
6101 case RCVLSC_MODE:
6102 case DMAC_MODE:
6103 case MBFREE_MODE:
6104 case BUFMGR_MODE:
6105 case MEMARB_MODE:
6106 /* We can't enable/disable these bits of the
6107 * 5705/5750, just say success.
6108 */
6109 return 0;
6110
6111 default:
6112 break;
855e1111 6113 }
1da177e4
LT		 6114 }
6115
6116 val = tr32(ofs);
6117 val &= ~enable_bit;
6118 tw32_f(ofs, val);
6119
6120 for (i = 0; i < MAX_WAIT_CNT; i++) {
6121 udelay(100);
6122 val = tr32(ofs);
6123 if ((val & enable_bit) == 0)
6124 break;
6125 }
6126
b3b7d6be 6127 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6128 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6129 "ofs=%lx enable_bit=%x\n",
6130 ofs, enable_bit);
6131 return -ENODEV;
6132 }
6133
6134 return 0;
6135}
6136
6137/* tp->lock is held. */
b3b7d6be 6138static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6139{
6140 int i, err;
6141
6142 tg3_disable_ints(tp);
6143
6144 tp->rx_mode &= ~RX_MODE_ENABLE;
6145 tw32_f(MAC_RX_MODE, tp->rx_mode);
6146 udelay(10);
6147
b3b7d6be
DM		 6148 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6149 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6150 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6151 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6152 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6153 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6154
6155 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6156 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6157 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6158 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6159 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6160 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6161 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6162
6163 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6164 tw32_f(MAC_MODE, tp->mac_mode);
6165 udelay(40);
6166
6167 tp->tx_mode &= ~TX_MODE_ENABLE;
6168 tw32_f(MAC_TX_MODE, tp->tx_mode);
6169
6170 for (i = 0; i < MAX_WAIT_CNT; i++) {
6171 udelay(100);
6172 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6173 break;
6174 }
6175 if (i >= MAX_WAIT_CNT) {
6176 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6177 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6178 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6179 err |= -ENODEV;
1da177e4
LT		 6180 }
6181
e6de8ad1 6182 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6183 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6184 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6185
6186 tw32(FTQ_RESET, 0xffffffff);
6187 tw32(FTQ_RESET, 0x00000000);
6188
b3b7d6be
DM		 6189 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6190 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6191
f77a6a8e
MC		 6192 for (i = 0; i < tp->irq_cnt; i++) {
6193 struct tg3_napi *tnapi = &tp->napi[i];
6194 if (tnapi->hw_status)
6195 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6196 }
1da177e4
LT		 6197 if (tp->hw_stats)
6198 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6199
1da177e4
LT		 6200 return err;
6201}
6202
0d3031d9
MC		 6203static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6204{
6205 int i;
6206 u32 apedata;
6207
6208 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6209 if (apedata != APE_SEG_SIG_MAGIC)
6210 return;
6211
6212 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6213 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6214 return;
6215
6216 /* Wait for up to 1 millisecond for APE to service previous event. */
6217 for (i = 0; i < 10; i++) {
6218 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6219 return;
6220
6221 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6222
6223 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6224 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6225 event | APE_EVENT_STATUS_EVENT_PENDING);
6226
6227 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6228
6229 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6230 break;
6231
6232 udelay(100);
6233 }
6234
6235 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6236 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6237}
6238
6239static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6240{
6241 u32 event;
6242 u32 apedata;
6243
6244 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6245 return;
6246
6247 switch (kind) {
6248 case RESET_KIND_INIT:
6249 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6250 APE_HOST_SEG_SIG_MAGIC);
6251 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6252 APE_HOST_SEG_LEN_MAGIC);
6253 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6254 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6255 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6256 APE_HOST_DRIVER_ID_MAGIC);
6257 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6258 APE_HOST_BEHAV_NO_PHYLOCK);
6259
6260 event = APE_EVENT_STATUS_STATE_START;
6261 break;
6262 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6263 /* With the interface we are currently using,
6264 * APE does not track driver state. Wiping
6265 * out the HOST SEGMENT SIGNATURE forces
6266 * the APE to assume OS absent status.
6267 */
6268 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6269
0d3031d9
MC		 6270 event = APE_EVENT_STATUS_STATE_UNLOAD;
6271 break;
6272 case RESET_KIND_SUSPEND:
6273 event = APE_EVENT_STATUS_STATE_SUSPEND;
6274 break;
6275 default:
6276 return;
6277 }
6278
6279 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6280
6281 tg3_ape_send_event(tp, event);
6282}
6283
1da177e4
LT		 6284/* tp->lock is held. */
6285static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6286{
f49639e6
DM		 6287 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6288 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6289
6290 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6291 switch (kind) {
6292 case RESET_KIND_INIT:
6293 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6294 DRV_STATE_START);
6295 break;
6296
6297 case RESET_KIND_SHUTDOWN:
6298 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6299 DRV_STATE_UNLOAD);
6300 break;
6301
6302 case RESET_KIND_SUSPEND:
6303 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6304 DRV_STATE_SUSPEND);
6305 break;
6306
6307 default:
6308 break;
855e1111 6309 }
1da177e4 6310 }
0d3031d9
MC		 6311
6312 if (kind == RESET_KIND_INIT ||
6313 kind == RESET_KIND_SUSPEND)
6314 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6315}
6316
6317/* tp->lock is held. */
6318static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6319{
6320 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6321 switch (kind) {
6322 case RESET_KIND_INIT:
6323 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6324 DRV_STATE_START_DONE);
6325 break;
6326
6327 case RESET_KIND_SHUTDOWN:
6328 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6329 DRV_STATE_UNLOAD_DONE);
6330 break;
6331
6332 default:
6333 break;
855e1111 6334 }
1da177e4 6335 }
0d3031d9
MC		 6336
6337 if (kind == RESET_KIND_SHUTDOWN)
6338 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6339}
6340
6341/* tp->lock is held. */
6342static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6343{
6344 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6345 switch (kind) {
6346 case RESET_KIND_INIT:
6347 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6348 DRV_STATE_START);
6349 break;
6350
6351 case RESET_KIND_SHUTDOWN:
6352 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6353 DRV_STATE_UNLOAD);
6354 break;
6355
6356 case RESET_KIND_SUSPEND:
6357 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6358 DRV_STATE_SUSPEND);
6359 break;
6360
6361 default:
6362 break;
855e1111 6363 }
1da177e4
LT		 6364 }
6365}
6366
7a6f4369
MC		 6367static int tg3_poll_fw(struct tg3 *tp)
6368{
6369 int i;
6370 u32 val;
6371
b5d3772c 6372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6373 /* Wait up to 20ms for init done. */
6374 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6375 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6376 return 0;
0ccead18 6377 udelay(100);
b5d3772c
MC		 6378 }
6379 return -ENODEV;
6380 }
6381
7a6f4369
MC		 6382 /* Wait for firmware initialization to complete. */
6383 for (i = 0; i < 100000; i++) {
6384 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6385 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6386 break;
6387 udelay(10);
6388 }
6389
6390 /* Chip might not be fitted with firmware. Some Sun onboard
6391 * parts are configured like that. So don't signal the timeout
6392 * of the above loop as an error, but do report the lack of
6393 * running firmware once.
6394 */
6395 if (i >= 100000 &&
6396 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6397 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6398
6399 printk(KERN_INFO PFX "%s: No firmware running.\n",
6400 tp->dev->name);
6401 }
6402
6403 return 0;
6404}
6405
ee6a99b5
MC		 6406/* Save PCI command register before chip reset */
6407static void tg3_save_pci_state(struct tg3 *tp)
6408{
8a6eac90 6409 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6410}
6411
6412/* Restore PCI state after chip reset */
6413static void tg3_restore_pci_state(struct tg3 *tp)
6414{
6415 u32 val;
6416
6417 /* Re-enable indirect register accesses. */
6418 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6419 tp->misc_host_ctrl);
6420
6421 /* Set MAX PCI retry to zero. */
6422 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6423 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6424 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6425 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6426 /* Allow reads and writes to the APE register and memory space. */
6427 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6428 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6429 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6430 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6431
8a6eac90 6432 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6433
fcb389df
MC		 6434 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6435 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6436 pcie_set_readrq(tp->pdev, 4096);
6437 else {
6438 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6439 tp->pci_cacheline_sz);
6440 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6441 tp->pci_lat_timer);
6442 }
114342f2 6443 }
5f5c51e3 6444
ee6a99b5 6445 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6446 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6447 u16 pcix_cmd;
6448
6449 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6450 &pcix_cmd);
6451 pcix_cmd &= ~PCI_X_CMD_ERO;
6452 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6453 pcix_cmd);
6454 }
ee6a99b5
MC		 6455
6456 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6457
6458 /* Chip reset on 5780 will reset MSI enable bit,
6459 * so need to restore it.
6460 */
6461 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6462 u16 ctrl;
6463
6464 pci_read_config_word(tp->pdev,
6465 tp->msi_cap + PCI_MSI_FLAGS,
6466 &ctrl);
6467 pci_write_config_word(tp->pdev,
6468 tp->msi_cap + PCI_MSI_FLAGS,
6469 ctrl | PCI_MSI_FLAGS_ENABLE);
6470 val = tr32(MSGINT_MODE);
6471 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6472 }
6473 }
6474}
6475
1da177e4
LT		 6476static void tg3_stop_fw(struct tg3 *);
6477
6478/* tp->lock is held. */
6479static int tg3_chip_reset(struct tg3 *tp)
6480{
6481 u32 val;
1ee582d8 6482 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6483 int i, err;
1da177e4 6484
f49639e6
DM		 6485 tg3_nvram_lock(tp);
6486
77b483f1
MC		 6487 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6488
f49639e6
DM		 6489 /* No matching tg3_nvram_unlock() after this because
6490 * chip reset below will undo the nvram lock.
6491 */
6492 tp->nvram_lock_cnt = 0;
1da177e4 6493
ee6a99b5
MC		 6494 /* GRC_MISC_CFG core clock reset will clear the memory
6495 * enable bit in PCI register 4 and the MSI enable bit
6496 * on some chips, so we save relevant registers here.
6497 */
6498 tg3_save_pci_state(tp);
6499
d9ab5ad1 6500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6501 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6502 tw32(GRC_FASTBOOT_PC, 0);
6503
1da177e4
LT		 6504 /*
6505 * We must avoid the readl() that normally takes place.
6506 * It locks machines, causes machine checks, and other
6507 * fun things. So, temporarily disable the 5701
6508 * hardware workaround, while we do the reset.
6509 */
1ee582d8
MC		 6510 write_op = tp->write32;
6511 if (write_op == tg3_write_flush_reg32)
6512 tp->write32 = tg3_write32;
1da177e4 6513
d18edcb2
MC		 6514 /* Prevent the irq handler from reading or writing PCI registers
6515 * during chip reset when the memory enable bit in the PCI command
6516 * register may be cleared. The chip does not generate interrupt
6517 * at this time, but the irq handler may still be called due to irq
6518 * sharing or irqpoll.
6519 */
6520 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6521 for (i = 0; i < tp->irq_cnt; i++) {
6522 struct tg3_napi *tnapi = &tp->napi[i];
6523 if (tnapi->hw_status) {
6524 tnapi->hw_status->status = 0;
6525 tnapi->hw_status->status_tag = 0;
6526 }
6527 tnapi->last_tag = 0;
6528 tnapi->last_irq_tag = 0;
b8fa2f3a 6529 }
d18edcb2 6530 smp_mb();
4f125f42
MC		 6531
6532 for (i = 0; i < tp->irq_cnt; i++)
6533 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6534
255ca311
MC		 6535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6536 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6537 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6538 }
6539
1da177e4
LT		 6540 /* do the reset */
6541 val = GRC_MISC_CFG_CORECLK_RESET;
6542
6543 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6544 if (tr32(0x7e2c) == 0x60) {
6545 tw32(0x7e2c, 0x20);
6546 }
6547 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6548 tw32(GRC_MISC_CFG, (1 << 29));
6549 val |= (1 << 29);
6550 }
6551 }
6552
b5d3772c
MC		 6553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6554 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6555 tw32(GRC_VCPU_EXT_CTRL,
6556 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6557 }
6558
1da177e4
LT		 6559 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6560 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6561 tw32(GRC_MISC_CFG, val);
6562
1ee582d8
MC		 6563 /* restore 5701 hardware bug workaround write method */
6564 tp->write32 = write_op;
1da177e4
LT		 6565
6566 /* Unfortunately, we have to delay before the PCI read back.
6567 * Some 575X chips even will not respond to a PCI cfg access
6568 * when the reset command is given to the chip.
6569 *
6570 * How do these hardware designers expect things to work
6571 * properly if the PCI write is posted for a long period
6572 * of time? It is always necessary to have some method by
6573 * which a register read back can occur to push the write
6574 * out which does the reset.
6575 *
6576 * For most tg3 variants the trick below was working.
6577 * Ho hum...
6578 */
6579 udelay(120);
6580
6581 /* Flush PCI posted writes. The normal MMIO registers
6582 * are inaccessible at this time so this is the only
6583 * way to make this reliably (actually, this is no longer
6584 * the case, see above). I tried to use indirect
6585 * register read/write but this upset some 5701 variants.
6586 */
6587 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6588
6589 udelay(120);
6590
5e7dfd0f 6591 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6592 u16 val16;
6593
1da177e4
LT		 6594 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6595 int i;
6596 u32 cfg_val;
6597
6598 /* Wait for link training to complete. */
6599 for (i = 0; i < 5000; i++)
6600 udelay(100);
6601
6602 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6603 pci_write_config_dword(tp->pdev, 0xc4,
6604 cfg_val | (1 << 15));
6605 }
5e7dfd0f 6606
e7126997
MC		 6607 /* Clear the "no snoop" and "relaxed ordering" bits. */
6608 pci_read_config_word(tp->pdev,
6609 tp->pcie_cap + PCI_EXP_DEVCTL,
6610 &val16);
6611 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6612 PCI_EXP_DEVCTL_NOSNOOP_EN);
6613 /*
6614 * Older PCIe devices only support the 128 byte
6615 * MPS setting. Enforce the restriction.
5e7dfd0f 6616 */
e7126997
MC		 6617 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6618 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6619 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6620 pci_write_config_word(tp->pdev,
6621 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6622 val16);
5e7dfd0f
MC		 6623
6624 pcie_set_readrq(tp->pdev, 4096);
6625
6626 /* Clear error status */
6627 pci_write_config_word(tp->pdev,
6628 tp->pcie_cap + PCI_EXP_DEVSTA,
6629 PCI_EXP_DEVSTA_CED |
6630 PCI_EXP_DEVSTA_NFED |
6631 PCI_EXP_DEVSTA_FED |
6632 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6633 }
6634
ee6a99b5 6635 tg3_restore_pci_state(tp);
1da177e4 6636
d18edcb2
MC		 6637 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6638
ee6a99b5
MC		 6639 val = 0;
6640 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6641 val = tr32(MEMARB_MODE);
ee6a99b5 6642 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6643
6644 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6645 tg3_stop_fw(tp);
6646 tw32(0x5000, 0x400);
6647 }
6648
6649 tw32(GRC_MODE, tp->grc_mode);
6650
6651 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6652 val = tr32(0xc4);
1da177e4
LT		 6653
6654 tw32(0xc4, val | (1 << 15));
6655 }
6656
6657 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6659 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6660 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6661 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6662 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6663 }
6664
6665 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6666 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6667 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6668 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6669 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6670 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6671 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6672 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6673 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6674 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6675 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6676 } else
6677 tw32_f(MAC_MODE, 0);
6678 udelay(40);
6679
77b483f1
MC		 6680 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6681
7a6f4369
MC		 6682 err = tg3_poll_fw(tp);
6683 if (err)
6684 return err;
1da177e4 6685
0a9140cf
MC		 6686 tg3_mdio_start(tp);
6687
52cdf852
MC		 6688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6689 u8 phy_addr;
6690
6691 phy_addr = tp->phy_addr;
6692 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6693
6694 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6695 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6696 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6697 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6698 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6699 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6700 udelay(10);
6701
6702 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6703 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6704 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6705 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6706 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6707 udelay(10);
6708
6709 tp->phy_addr = phy_addr;
6710 }
6711
1da177e4 6712 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6713 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6714 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6715 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6716 val = tr32(0x7c00);
1da177e4
LT		 6717
6718 tw32(0x7c00, val | (1 << 25));
6719 }
6720
6721 /* Reprobe ASF enable state. */
6722 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6723 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6724 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6725 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6726 u32 nic_cfg;
6727
6728 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6729 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6730 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6731 tp->last_event_jiffies = jiffies;
cbf46853 6732 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6733 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6734 }
6735 }
6736
6737 return 0;
6738}
6739
6740/* tp->lock is held. */
6741static void tg3_stop_fw(struct tg3 *tp)
6742{
0d3031d9
MC		 6743 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6744 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6745 /* Wait for RX cpu to ACK the previous event. */
6746 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6747
6748 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6749
6750 tg3_generate_fw_event(tp);
1da177e4 6751
7c5026aa
MC		 6752 /* Wait for RX cpu to ACK this event. */
6753 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6754 }
6755}
6756
6757/* tp->lock is held. */
944d980e 6758static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6759{
6760 int err;
6761
6762 tg3_stop_fw(tp);
6763
944d980e 6764 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6765
b3b7d6be 6766 tg3_abort_hw(tp, silent);
1da177e4
LT		 6767 err = tg3_chip_reset(tp);
6768
daba2a63
MC		 6769 __tg3_set_mac_addr(tp, 0);
6770
944d980e
MC		 6771 tg3_write_sig_legacy(tp, kind);
6772 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6773
6774 if (err)
6775 return err;
6776
6777 return 0;
6778}
6779
1da177e4
LT		 6780#define RX_CPU_SCRATCH_BASE 0x30000
6781#define RX_CPU_SCRATCH_SIZE 0x04000
6782#define TX_CPU_SCRATCH_BASE 0x34000
6783#define TX_CPU_SCRATCH_SIZE 0x04000
6784
6785/* tp->lock is held. */
6786static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6787{
6788 int i;
6789
5d9428de
ES		 6790 BUG_ON(offset == TX_CPU_BASE &&
6791 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6792
b5d3772c
MC		 6793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6794 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6795
6796 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6797 return 0;
6798 }
1da177e4
LT		 6799 if (offset == RX_CPU_BASE) {
6800 for (i = 0; i < 10000; i++) {
6801 tw32(offset + CPU_STATE, 0xffffffff);
6802 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6803 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6804 break;
6805 }
6806
6807 tw32(offset + CPU_STATE, 0xffffffff);
6808 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6809 udelay(10);
6810 } else {
6811 for (i = 0; i < 10000; i++) {
6812 tw32(offset + CPU_STATE, 0xffffffff);
6813 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6814 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6815 break;
6816 }
6817 }
6818
6819 if (i >= 10000) {
6820 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6821 "and %s CPU\n",
6822 tp->dev->name,
6823 (offset == RX_CPU_BASE ? "RX" : "TX"));
6824 return -ENODEV;
6825 }
ec41c7df
MC		 6826
6827 /* Clear firmware's nvram arbitration. */
6828 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6829 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6830 return 0;
6831}
6832
6833struct fw_info {
077f849d
JSR		 6834 unsigned int fw_base;
6835 unsigned int fw_len;
6836 const __be32 *fw_data;
1da177e4
LT		 6837};
6838
6839/* tp->lock is held. */
6840static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6841 int cpu_scratch_size, struct fw_info *info)
6842{
ec41c7df 6843 int err, lock_err, i;
1da177e4
LT		 6844 void (*write_op)(struct tg3 *, u32, u32);
6845
6846 if (cpu_base == TX_CPU_BASE &&
6847 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6848 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6849 "TX cpu firmware on %s which is 5705.\n",
6850 tp->dev->name);
6851 return -EINVAL;
6852 }
6853
6854 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6855 write_op = tg3_write_mem;
6856 else
6857 write_op = tg3_write_indirect_reg32;
6858
1b628151
MC		 6859 /* It is possible that bootcode is still loading at this point.
6860 * Get the nvram lock first before halting the cpu.
6861 */
ec41c7df 6862 lock_err = tg3_nvram_lock(tp);
1da177e4 6863 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6864 if (!lock_err)
6865 tg3_nvram_unlock(tp);
1da177e4
LT		 6866 if (err)
6867 goto out;
6868
6869 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6870 write_op(tp, cpu_scratch_base + i, 0);
6871 tw32(cpu_base + CPU_STATE, 0xffffffff);
6872 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6873 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6874 write_op(tp, (cpu_scratch_base +
077f849d 6875 (info->fw_base & 0xffff) +
1da177e4 6876 (i * sizeof(u32))),
077f849d 6877 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6878
6879 err = 0;
6880
6881out:
1da177e4
LT		 6882 return err;
6883}
6884
6885/* tp->lock is held. */
6886static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6887{
6888 struct fw_info info;
077f849d 6889 const __be32 *fw_data;
1da177e4
LT		 6890 int err, i;
6891
077f849d
JSR		 6892 fw_data = (void *)tp->fw->data;
6893
6894 /* Firmware blob starts with version numbers, followed by
6895 start address and length. We are setting complete length.
6896 length = end_address_of_bss - start_address_of_text.
6897 Remainder is the blob to be loaded contiguously
6898 from start address. */
6899
6900 info.fw_base = be32_to_cpu(fw_data[1]);
6901 info.fw_len = tp->fw->size - 12;
6902 info.fw_data = &fw_data[3];
1da177e4
LT		 6903
6904 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6905 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6906 &info);
6907 if (err)
6908 return err;
6909
6910 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6911 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6912 &info);
6913 if (err)
6914 return err;
6915
6916 /* Now startup only the RX cpu. */
6917 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6918 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6919
6920 for (i = 0; i < 5; i++) {
077f849d 6921 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6922 break;
6923 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6924 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6925 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6926 udelay(1000);
6927 }
6928 if (i >= 5) {
6929 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6930 "to set RX CPU PC, is %08x should be %08x\n",
6931 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6932 info.fw_base);
1da177e4
LT		 6933 return -ENODEV;
6934 }
6935 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6936 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6937
6938 return 0;
6939}
6940
1da177e4 6941/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6942
6943/* tp->lock is held. */
6944static int tg3_load_tso_firmware(struct tg3 *tp)
6945{
6946 struct fw_info info;
077f849d 6947 const __be32 *fw_data;
1da177e4
LT		 6948 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6949 int err, i;
6950
6951 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6952 return 0;
6953
077f849d
JSR		 6954 fw_data = (void *)tp->fw->data;
6955
6956 /* Firmware blob starts with version numbers, followed by
6957 start address and length. We are setting complete length.
6958 length = end_address_of_bss - start_address_of_text.
6959 Remainder is the blob to be loaded contiguously
6960 from start address. */
6961
6962 info.fw_base = be32_to_cpu(fw_data[1]);
6963 cpu_scratch_size = tp->fw_len;
6964 info.fw_len = tp->fw->size - 12;
6965 info.fw_data = &fw_data[3];
6966
1da177e4 6967 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6968 cpu_base = RX_CPU_BASE;
6969 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6970 } else {
1da177e4
LT		 6971 cpu_base = TX_CPU_BASE;
6972 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6973 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6974 }
6975
6976 err = tg3_load_firmware_cpu(tp, cpu_base,
6977 cpu_scratch_base, cpu_scratch_size,
6978 &info);
6979 if (err)
6980 return err;
6981
6982 /* Now startup the cpu. */
6983 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6984 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6985
6986 for (i = 0; i < 5; i++) {
077f849d 6987 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6988 break;
6989 tw32(cpu_base + CPU_STATE, 0xffffffff);
6990 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6991 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6992 udelay(1000);
6993 }
6994 if (i >= 5) {
6995 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6996 "to set CPU PC, is %08x should be %08x\n",
6997 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6998 info.fw_base);
1da177e4
LT		 6999 return -ENODEV;
7000 }
7001 tw32(cpu_base + CPU_STATE, 0xffffffff);
7002 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7003 return 0;
7004}
7005
1da177e4 7006
1da177e4
LT		 7007static int tg3_set_mac_addr(struct net_device *dev, void *p)
7008{
7009 struct tg3 *tp = netdev_priv(dev);
7010 struct sockaddr *addr = p;
986e0aeb 7011 int err = 0, skip_mac_1 = 0;
1da177e4 7012
f9804ddb
MC		 7013 if (!is_valid_ether_addr(addr->sa_data))
7014 return -EINVAL;
7015
1da177e4
LT		 7016 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7017
e75f7c90
MC		 7018 if (!netif_running(dev))
7019 return 0;
7020
58712ef9 7021 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7022 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7023
986e0aeb
MC		 7024 addr0_high = tr32(MAC_ADDR_0_HIGH);
7025 addr0_low = tr32(MAC_ADDR_0_LOW);
7026 addr1_high = tr32(MAC_ADDR_1_HIGH);
7027 addr1_low = tr32(MAC_ADDR_1_LOW);
7028
7029 /* Skip MAC addr 1 if ASF is using it. */
7030 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7031 !(addr1_high == 0 && addr1_low == 0))
7032 skip_mac_1 = 1;
58712ef9 7033 }
986e0aeb
MC		 7034 spin_lock_bh(&tp->lock);
7035 __tg3_set_mac_addr(tp, skip_mac_1);
7036 spin_unlock_bh(&tp->lock);
1da177e4 7037
b9ec6c1b 7038 return err;
1da177e4
LT		 7039}
7040
7041/* tp->lock is held. */
7042static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7043 dma_addr_t mapping, u32 maxlen_flags,
7044 u32 nic_addr)
7045{
7046 tg3_write_mem(tp,
7047 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7048 ((u64) mapping >> 32));
7049 tg3_write_mem(tp,
7050 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7051 ((u64) mapping & 0xffffffff));
7052 tg3_write_mem(tp,
7053 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7054 maxlen_flags);
7055
7056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7057 tg3_write_mem(tp,
7058 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7059 nic_addr);
7060}
7061
7062static void __tg3_set_rx_mode(struct net_device *);
d244c892 7063static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7064{
b6080e12
MC		 7065 int i;
7066
7067 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7068 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7069 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7070 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7071
7072 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7073 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7074 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7075 } else {
7076 tw32(HOSTCC_TXCOL_TICKS, 0);
7077 tw32(HOSTCC_TXMAX_FRAMES, 0);
7078 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7079
7080 tw32(HOSTCC_RXCOL_TICKS, 0);
7081 tw32(HOSTCC_RXMAX_FRAMES, 0);
7082 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7083 }
b6080e12 7084
15f9850d
DM		 7085 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7086 u32 val = ec->stats_block_coalesce_usecs;
7087
b6080e12
MC		 7088 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7089 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7090
15f9850d
DM		 7091 if (!netif_carrier_ok(tp->dev))
7092 val = 0;
7093
7094 tw32(HOSTCC_STAT_COAL_TICKS, val);
7095 }
b6080e12
MC		 7096
7097 for (i = 0; i < tp->irq_cnt - 1; i++) {
7098 u32 reg;
7099
7100 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7101 tw32(reg, ec->rx_coalesce_usecs);
7102 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7103 tw32(reg, ec->tx_coalesce_usecs);
7104 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7105 tw32(reg, ec->rx_max_coalesced_frames);
7106 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7107 tw32(reg, ec->tx_max_coalesced_frames);
7108 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7109 tw32(reg, ec->rx_max_coalesced_frames_irq);
7110 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7111 tw32(reg, ec->tx_max_coalesced_frames_irq);
7112 }
7113
7114 for (; i < tp->irq_max - 1; i++) {
7115 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7116 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7117 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7118 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7119 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7120 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7121 }
15f9850d 7122}
1da177e4 7123
2d31ecaf
MC		 7124/* tp->lock is held. */
7125static void tg3_rings_reset(struct tg3 *tp)
7126{
7127 int i;
f77a6a8e 7128 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7129 struct tg3_napi *tnapi = &tp->napi[0];
7130
7131 /* Disable all transmit rings but the first. */
7132 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7133 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7134 else
7135 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7136
7137 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7138 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7139 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7140 BDINFO_FLAGS_DISABLED);
7141
7142
7143 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7145 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7146 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7147 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7148 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7149 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7150 else
7151 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7152
7153 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7154 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7155 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7156 BDINFO_FLAGS_DISABLED);
7157
7158 /* Disable interrupts */
7159 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7160
7161 /* Zero mailbox registers. */
f77a6a8e
MC		 7162 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7163 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7164 tp->napi[i].tx_prod = 0;
7165 tp->napi[i].tx_cons = 0;
7166 tw32_mailbox(tp->napi[i].prodmbox, 0);
7167 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7168 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7169 }
7170 } else {
7171 tp->napi[0].tx_prod = 0;
7172 tp->napi[0].tx_cons = 0;
7173 tw32_mailbox(tp->napi[0].prodmbox, 0);
7174 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7175 }
2d31ecaf
MC		 7176
7177 /* Make sure the NIC-based send BD rings are disabled. */
7178 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7179 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7180 for (i = 0; i < 16; i++)
7181 tw32_tx_mbox(mbox + i * 8, 0);
7182 }
7183
7184 txrcb = NIC_SRAM_SEND_RCB;
7185 rxrcb = NIC_SRAM_RCV_RET_RCB;
7186
7187 /* Clear status block in ram. */
7188 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7189
7190 /* Set status block DMA address */
7191 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7192 ((u64) tnapi->status_mapping >> 32));
7193 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7194 ((u64) tnapi->status_mapping & 0xffffffff));
7195
f77a6a8e
MC		 7196 if (tnapi->tx_ring) {
7197 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7198 (TG3_TX_RING_SIZE <<
7199 BDINFO_FLAGS_MAXLEN_SHIFT),
7200 NIC_SRAM_TX_BUFFER_DESC);
7201 txrcb += TG3_BDINFO_SIZE;
7202 }
7203
7204 if (tnapi->rx_rcb) {
7205 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7206 (TG3_RX_RCB_RING_SIZE(tp) <<
7207 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7208 rxrcb += TG3_BDINFO_SIZE;
7209 }
7210
7211 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7212
f77a6a8e
MC		 7213 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7214 u64 mapping = (u64)tnapi->status_mapping;
7215 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7216 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7217
7218 /* Clear status block in ram. */
7219 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7220
7221 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7222 (TG3_TX_RING_SIZE <<
7223 BDINFO_FLAGS_MAXLEN_SHIFT),
7224 NIC_SRAM_TX_BUFFER_DESC);
7225
7226 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7227 (TG3_RX_RCB_RING_SIZE(tp) <<
7228 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7229
7230 stblk += 8;
7231 txrcb += TG3_BDINFO_SIZE;
7232 rxrcb += TG3_BDINFO_SIZE;
7233 }
2d31ecaf
MC		 7234}
7235
1da177e4 7236/* tp->lock is held. */
8e7a22e3 7237static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7238{
7239 u32 val, rdmac_mode;
7240 int i, err, limit;
21f581a5 7241 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7242
7243 tg3_disable_ints(tp);
7244
7245 tg3_stop_fw(tp);
7246
7247 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7248
7249 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7250 tg3_abort_hw(tp, 1);
1da177e4
LT		 7251 }
7252
dd477003
MC		 7253 if (reset_phy &&
7254 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7255 tg3_phy_reset(tp);
7256
1da177e4
LT		 7257 err = tg3_chip_reset(tp);
7258 if (err)
7259 return err;
7260
7261 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7262
bcb37f6c 7263 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7264 val = tr32(TG3_CPMU_CTRL);
7265 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7266 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7267
7268 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7269 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7270 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7271 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7272
7273 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7274 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7275 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7276 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7277
7278 val = tr32(TG3_CPMU_HST_ACC);
7279 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7280 val |= CPMU_HST_ACC_MACCLK_6_25;
7281 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7282 }
7283
33466d93
MC		 7284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7285 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7286 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7287 PCIE_PWR_MGMT_L1_THRESH_4MS;
7288 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7289
7290 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7291 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7292
7293 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7294
f40386c8
MC		 7295 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7296 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7297 }
7298
1da177e4
LT		 7299 /* This works around an issue with Athlon chipsets on
7300 * B3 tigon3 silicon. This bit has no effect on any
7301 * other revision. But do not set this on PCI Express
795d01c5 7302 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7303 */
795d01c5
MC		 7304 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7305 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7306 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7307 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7308 }
1da177e4
LT		 7309
7310 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7311 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7312 val = tr32(TG3PCI_PCISTATE);
7313 val |= PCISTATE_RETRY_SAME_DMA;
7314 tw32(TG3PCI_PCISTATE, val);
7315 }
7316
0d3031d9
MC		 7317 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7318 /* Allow reads and writes to the
7319 * APE register and memory space.
7320 */
7321 val = tr32(TG3PCI_PCISTATE);
7322 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7323 PCISTATE_ALLOW_APE_SHMEM_WR;
7324 tw32(TG3PCI_PCISTATE, val);
7325 }
7326
1da177e4
LT		 7327 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7328 /* Enable some hw fixes. */
7329 val = tr32(TG3PCI_MSI_DATA);
7330 val |= (1 << 26) | (1 << 28) | (1 << 29);
7331 tw32(TG3PCI_MSI_DATA, val);
7332 }
7333
7334 /* Descriptor ring init may make accesses to the
7335 * NIC SRAM area to setup the TX descriptors, so we
7336 * can only do this after the hardware has been
7337 * successfully reset.
7338 */
32d8c572
MC		 7339 err = tg3_init_rings(tp);
7340 if (err)
7341 return err;
1da177e4 7342
cbf9ca6c
MC		 7343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7344 val = tr32(TG3PCI_DMA_RW_CTRL) &
7345 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7346 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7347 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7348 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7349 /* This value is determined during the probe time DMA
7350 * engine test, tg3_test_dma.
7351 */
7352 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7353 }
1da177e4
LT		 7354
7355 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7356 GRC_MODE_4X_NIC_SEND_RINGS |
7357 GRC_MODE_NO_TX_PHDR_CSUM |
7358 GRC_MODE_NO_RX_PHDR_CSUM);
7359 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7360
7361 /* Pseudo-header checksum is done by hardware logic and not
7362 * the offload processers, so make the chip do the pseudo-
7363 * header checksums on receive. For transmit it is more
7364 * convenient to do the pseudo-header checksum in software
7365 * as Linux does that on transmit for us in all cases.
7366 */
7367 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7368
7369 tw32(GRC_MODE,
7370 tp->grc_mode |
7371 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7372
7373 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7374 val = tr32(GRC_MISC_CFG);
7375 val &= ~0xff;
7376 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7377 tw32(GRC_MISC_CFG, val);
7378
7379 /* Initialize MBUF/DESC pool. */
cbf46853 7380 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7381 /* Do nothing. */
7382 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7383 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7385 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7386 else
7387 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7388 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7389 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7390 }
1da177e4
LT		 7391 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7392 int fw_len;
7393
077f849d 7394 fw_len = tp->fw_len;
1da177e4
LT		 7395 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7396 tw32(BUFMGR_MB_POOL_ADDR,
7397 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7398 tw32(BUFMGR_MB_POOL_SIZE,
7399 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7400 }
1da177e4 7401
0f893dc6 7402 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7403 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7404 tp->bufmgr_config.mbuf_read_dma_low_water);
7405 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7406 tp->bufmgr_config.mbuf_mac_rx_low_water);
7407 tw32(BUFMGR_MB_HIGH_WATER,
7408 tp->bufmgr_config.mbuf_high_water);
7409 } else {
7410 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7411 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7412 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7413 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7414 tw32(BUFMGR_MB_HIGH_WATER,
7415 tp->bufmgr_config.mbuf_high_water_jumbo);
7416 }
7417 tw32(BUFMGR_DMA_LOW_WATER,
7418 tp->bufmgr_config.dma_low_water);
7419 tw32(BUFMGR_DMA_HIGH_WATER,
7420 tp->bufmgr_config.dma_high_water);
7421
7422 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7423 for (i = 0; i < 2000; i++) {
7424 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7425 break;
7426 udelay(10);
7427 }
7428 if (i >= 2000) {
7429 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7430 tp->dev->name);
7431 return -ENODEV;
7432 }
7433
7434 /* Setup replenish threshold. */
f92905de
MC		 7435 val = tp->rx_pending / 8;
7436 if (val == 0)
7437 val = 1;
7438 else if (val > tp->rx_std_max_post)
7439 val = tp->rx_std_max_post;
b5d3772c
MC		 7440 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7441 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7442 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7443
7444 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7445 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7446 }
f92905de
MC		 7447
7448 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7449
7450 /* Initialize TG3_BDINFO's at:
7451 * RCVDBDI_STD_BD: standard eth size rx ring
7452 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7453 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7454 *
7455 * like so:
7456 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7457 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7458 * ring attribute flags
7459 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7460 *
7461 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7462 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7463 *
7464 * The size of each ring is fixed in the firmware, but the location is
7465 * configurable.
7466 */
7467 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7468 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7469 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7470 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7471 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7472 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7473 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7474
fdb72b38
MC		 7475 /* Disable the mini ring */
7476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7477 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7478 BDINFO_FLAGS_DISABLED);
7479
fdb72b38
MC		 7480 /* Program the jumbo buffer descriptor ring control
7481 * blocks on those devices that have them.
7482 */
8f666b07 7483 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7484 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7485 /* Setup replenish threshold. */
7486 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7487
0f893dc6 7488 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7489 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7490 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7491 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7492 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7493 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7494 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7495 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7496 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7497 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7498 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7499 } else {
7500 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7501 BDINFO_FLAGS_DISABLED);
7502 }
7503
f6eb9b1f
MC		 7504 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7505 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7506 (RX_STD_MAX_SIZE << 2);
7507 else
7508 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7509 } else
7510 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7511
7512 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7513
21f581a5 7514 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7515 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7516 tpr->rx_std_ptr);
1da177e4 7517
21f581a5
MC		 7518 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7519 tp->rx_jumbo_pending : 0;
1da177e4 7520 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7521 tpr->rx_jmb_ptr);
1da177e4 7522
f6eb9b1f
MC		 7523 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7524 tw32(STD_REPLENISH_LWM, 32);
7525 tw32(JMB_REPLENISH_LWM, 16);
7526 }
7527
2d31ecaf
MC		 7528 tg3_rings_reset(tp);
7529
1da177e4 7530 /* Initialize MAC address and backoff seed. */
986e0aeb 7531 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7532
7533 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7534 tw32(MAC_RX_MTU_SIZE,
7535 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7536
7537 /* The slot time is changed by tg3_setup_phy if we
7538 * run at gigabit with half duplex.
7539 */
7540 tw32(MAC_TX_LENGTHS,
7541 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7542 (6 << TX_LENGTHS_IPG_SHIFT) |
7543 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7544
7545 /* Receive rules. */
7546 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7547 tw32(RCVLPC_CONFIG, 0x0181);
7548
7549 /* Calculate RDMAC_MODE setting early, we need it to determine
7550 * the RCVLPC_STATE_ENABLE mask.
7551 */
7552 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7553 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7554 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7555 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7556 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7557
57e6983c 7558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7560 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7561 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7562 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7563 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7564
85e94ced
MC		 7565 /* If statement applies to 5705 and 5750 PCI devices only */
7566 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7567 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7568 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7569 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7571 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7572 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7573 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7574 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7575 }
7576 }
7577
85e94ced
MC		 7578 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7579 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7580
1da177e4 7581 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7582 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7583
e849cdc3
MC		 7584 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7585 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7587 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7588
7589 /* Receive/send statistics. */
1661394e
MC		 7590 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7591 val = tr32(RCVLPC_STATS_ENABLE);
7592 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7593 tw32(RCVLPC_STATS_ENABLE, val);
7594 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7595 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7596 val = tr32(RCVLPC_STATS_ENABLE);
7597 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7598 tw32(RCVLPC_STATS_ENABLE, val);
7599 } else {
7600 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7601 }
7602 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7603 tw32(SNDDATAI_STATSENAB, 0xffffff);
7604 tw32(SNDDATAI_STATSCTRL,
7605 (SNDDATAI_SCTRL_ENABLE |
7606 SNDDATAI_SCTRL_FASTUPD));
7607
7608 /* Setup host coalescing engine. */
7609 tw32(HOSTCC_MODE, 0);
7610 for (i = 0; i < 2000; i++) {
7611 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7612 break;
7613 udelay(10);
7614 }
7615
d244c892 7616 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7617
1da177e4
LT		 7618 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7619 /* Status/statistics block address. See tg3_timer,
7620 * the tg3_periodic_fetch_stats call there, and
7621 * tg3_get_stats to see how this works for 5705/5750 chips.
7622 */
1da177e4
LT		 7623 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7624 ((u64) tp->stats_mapping >> 32));
7625 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7626 ((u64) tp->stats_mapping & 0xffffffff));
7627 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7628
1da177e4 7629 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7630
7631 /* Clear statistics and status block memory areas */
7632 for (i = NIC_SRAM_STATS_BLK;
7633 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7634 i += sizeof(u32)) {
7635 tg3_write_mem(tp, i, 0);
7636 udelay(40);
7637 }
1da177e4
LT		 7638 }
7639
7640 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7641
7642 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7643 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7644 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7645 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7646
c94e3941
MC		 7647 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7648 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7649 /* reset to prevent losing 1st rx packet intermittently */
7650 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7651 udelay(10);
7652 }
7653
3bda1258
MC		 7654 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7655 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7656 else
7657 tp->mac_mode = 0;
7658 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7659 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7660 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7661 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7662 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7663 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7664 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7665 udelay(40);
7666
314fba34 7667 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7668 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7669 * register to preserve the GPIO settings for LOMs. The GPIOs,
7670 * whether used as inputs or outputs, are set by boot code after
7671 * reset.
7672 */
9d26e213 7673 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7674 u32 gpio_mask;
7675
9d26e213
MC		 7676 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7677 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7678 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7679
7680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7681 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7682 GRC_LCLCTRL_GPIO_OUTPUT3;
7683
af36e6b6
MC		 7684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7685 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7686
aaf84465 7687 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7688 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7689
7690 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7691 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7692 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7693 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7694 }
1da177e4
LT		 7695 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7696 udelay(100);
7697
baf8a94a
MC		 7698 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7699 val = tr32(MSGINT_MODE);
7700 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7701 tw32(MSGINT_MODE, val);
7702 }
7703
1da177e4
LT		 7704 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7705 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7706 udelay(40);
7707 }
7708
7709 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7710 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7711 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7712 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7713 WDMAC_MODE_LNGREAD_ENAB);
7714
85e94ced
MC		 7715 /* If statement applies to 5705 and 5750 PCI devices only */
7716 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7717 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7719 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7720 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7721 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7722 /* nothing */
7723 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7724 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7725 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7726 val |= WDMAC_MODE_RX_ACCEL;
7727 }
7728 }
7729
d9ab5ad1 7730 /* Enable host coalescing bug fix */
321d32a0 7731 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7732 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7733
788a035e
MC		 7734 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7735 val |= WDMAC_MODE_BURST_ALL_DATA;
7736
1da177e4
LT		 7737 tw32_f(WDMAC_MODE, val);
7738 udelay(40);
7739
9974a356
MC		 7740 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7741 u16 pcix_cmd;
7742
7743 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7744 &pcix_cmd);
1da177e4 7745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7746 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7747 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7748 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7749 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7750 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7751 }
9974a356
MC		 7752 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7753 pcix_cmd);
1da177e4
LT		 7754 }
7755
7756 tw32_f(RDMAC_MODE, rdmac_mode);
7757 udelay(40);
7758
7759 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7760 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7761 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7762
7763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7764 tw32(SNDDATAC_MODE,
7765 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7766 else
7767 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7768
1da177e4
LT		 7769 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7770 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7771 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7772 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7773 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7774 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7775 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7776 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7777 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7778 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7779 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7780
7781 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7782 err = tg3_load_5701_a0_firmware_fix(tp);
7783 if (err)
7784 return err;
7785 }
7786
1da177e4
LT		 7787 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7788 err = tg3_load_tso_firmware(tp);
7789 if (err)
7790 return err;
7791 }
1da177e4
LT		 7792
7793 tp->tx_mode = TX_MODE_ENABLE;
7794 tw32_f(MAC_TX_MODE, tp->tx_mode);
7795 udelay(100);
7796
baf8a94a
MC		 7797 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7798 u32 reg = MAC_RSS_INDIR_TBL_0;
7799 u8 *ent = (u8 *)&val;
7800
7801 /* Setup the indirection table */
7802 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7803 int idx = i % sizeof(val);
7804
7805 ent[idx] = i % (tp->irq_cnt - 1);
7806 if (idx == sizeof(val) - 1) {
7807 tw32(reg, val);
7808 reg += 4;
7809 }
7810 }
7811
7812 /* Setup the "secret" hash key. */
7813 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7814 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7815 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7816 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7817 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7818 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7819 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7820 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7821 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7822 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7823 }
7824
1da177e4 7825 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7826 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7827 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7828
baf8a94a
MC		 7829 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7830 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7831 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7832 RX_MODE_RSS_IPV6_HASH_EN |
7833 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7834 RX_MODE_RSS_IPV4_HASH_EN |
7835 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7836
1da177e4
LT		 7837 tw32_f(MAC_RX_MODE, tp->rx_mode);
7838 udelay(10);
7839
1da177e4
LT		 7840 tw32(MAC_LED_CTRL, tp->led_ctrl);
7841
7842 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7843 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7844 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7845 udelay(10);
7846 }
7847 tw32_f(MAC_RX_MODE, tp->rx_mode);
7848 udelay(10);
7849
7850 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7851 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7852 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7853 /* Set drive transmission level to 1.2V */
7854 /* only if the signal pre-emphasis bit is not set */
7855 val = tr32(MAC_SERDES_CFG);
7856 val &= 0xfffff000;
7857 val |= 0x880;
7858 tw32(MAC_SERDES_CFG, val);
7859 }
7860 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7861 tw32(MAC_SERDES_CFG, 0x616000);
7862 }
7863
7864 /* Prevent chip from dropping frames when flow control
7865 * is enabled.
7866 */
7867 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7868
7869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7870 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7871 /* Use hardware link auto-negotiation */
7872 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7873 }
7874
d4d2c558
MC		 7875 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7876 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7877 u32 tmp;
7878
7879 tmp = tr32(SERDES_RX_CTRL);
7880 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7881 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7882 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7883 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7884 }
7885
dd477003
MC		 7886 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7887 if (tp->link_config.phy_is_low_power) {
7888 tp->link_config.phy_is_low_power = 0;
7889 tp->link_config.speed = tp->link_config.orig_speed;
7890 tp->link_config.duplex = tp->link_config.orig_duplex;
7891 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7892 }
1da177e4 7893
dd477003
MC		 7894 err = tg3_setup_phy(tp, 0);
7895 if (err)
7896 return err;
1da177e4 7897
dd477003 7898 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7899 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7900 u32 tmp;
7901
7902 /* Clear CRC stats. */
7903 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7904 tg3_writephy(tp, MII_TG3_TEST1,
7905 tmp | MII_TG3_TEST1_CRC_EN);
7906 tg3_readphy(tp, 0x14, &tmp);
7907 }
1da177e4
LT		 7908 }
7909 }
7910
7911 __tg3_set_rx_mode(tp->dev);
7912
7913 /* Initialize receive rules. */
7914 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7915 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7916 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7917 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7918
4cf78e4f 7919 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7920 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7921 limit = 8;
7922 else
7923 limit = 16;
7924 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7925 limit -= 4;
7926 switch (limit) {
7927 case 16:
7928 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7929 case 15:
7930 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7931 case 14:
7932 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7933 case 13:
7934 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7935 case 12:
7936 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7937 case 11:
7938 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7939 case 10:
7940 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7941 case 9:
7942 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7943 case 8:
7944 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7945 case 7:
7946 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7947 case 6:
7948 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7949 case 5:
7950 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7951 case 4:
7952 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7953 case 3:
7954 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7955 case 2:
7956 case 1:
7957
7958 default:
7959 break;
855e1111 7960 }
1da177e4 7961
9ce768ea
MC		 7962 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7963 /* Write our heartbeat update interval to APE. */
7964 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7965 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7966
1da177e4
LT		 7967 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7968
1da177e4
LT		 7969 return 0;
7970}
7971
7972/* Called at device open time to get the chip ready for
7973 * packet processing. Invoked with tp->lock held.
7974 */
8e7a22e3 7975static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7976{
1da177e4
LT		 7977 tg3_switch_clocks(tp);
7978
7979 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7980
2f751b67 7981 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7982}
7983
7984#define TG3_STAT_ADD32(PSTAT, REG) \
7985do { u32 __val = tr32(REG); \
7986 (PSTAT)->low += __val; \
7987 if ((PSTAT)->low < __val) \
7988 (PSTAT)->high += 1; \
7989} while (0)
7990
7991static void tg3_periodic_fetch_stats(struct tg3 *tp)
7992{
7993 struct tg3_hw_stats *sp = tp->hw_stats;
7994
7995 if (!netif_carrier_ok(tp->dev))
7996 return;
7997
7998 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7999 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8000 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8001 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8002 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8003 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8004 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8005 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8006 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8007 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8008 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8009 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8010 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8011
8012 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8013 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8014 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8015 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8016 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8017 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8018 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8019 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8020 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8021 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8022 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8023 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8024 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8025 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8026
8027 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8028 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8029 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8030}
8031
8032static void tg3_timer(unsigned long __opaque)
8033{
8034 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8035
f475f163
MC		 8036 if (tp->irq_sync)
8037 goto restart_timer;
8038
f47c11ee 8039 spin_lock(&tp->lock);
1da177e4 8040
fac9b83e
DM		 8041 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8042 /* All of this garbage is because when using non-tagged
8043 * IRQ status the mailbox/status_block protocol the chip
8044 * uses with the cpu is race prone.
8045 */
898a56f8 8046 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8047 tw32(GRC_LOCAL_CTRL,
8048 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8049 } else {
8050 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8051 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8052 }
1da177e4 8053
fac9b83e
DM		 8054 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8055 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8056 spin_unlock(&tp->lock);
fac9b83e
DM		 8057 schedule_work(&tp->reset_task);
8058 return;
8059 }
1da177e4
LT		 8060 }
8061
1da177e4
LT		 8062 /* This part only runs once per second. */
8063 if (!--tp->timer_counter) {
fac9b83e
DM		 8064 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8065 tg3_periodic_fetch_stats(tp);
8066
1da177e4
LT		 8067 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8068 u32 mac_stat;
8069 int phy_event;
8070
8071 mac_stat = tr32(MAC_STATUS);
8072
8073 phy_event = 0;
8074 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8075 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8076 phy_event = 1;
8077 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8078 phy_event = 1;
8079
8080 if (phy_event)
8081 tg3_setup_phy(tp, 0);
8082 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8083 u32 mac_stat = tr32(MAC_STATUS);
8084 int need_setup = 0;
8085
8086 if (netif_carrier_ok(tp->dev) &&
8087 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8088 need_setup = 1;
8089 }
8090 if (! netif_carrier_ok(tp->dev) &&
8091 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8092 MAC_STATUS_SIGNAL_DET))) {
8093 need_setup = 1;
8094 }
8095 if (need_setup) {
3d3ebe74
MC		 8096 if (!tp->serdes_counter) {
8097 tw32_f(MAC_MODE,
8098 (tp->mac_mode &
8099 ~MAC_MODE_PORT_MODE_MASK));
8100 udelay(40);
8101 tw32_f(MAC_MODE, tp->mac_mode);
8102 udelay(40);
8103 }
1da177e4
LT		 8104 tg3_setup_phy(tp, 0);
8105 }
747e8f8b
MC		 8106 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8107 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8108
8109 tp->timer_counter = tp->timer_multiplier;
8110 }
8111
130b8e4d
MC		 8112 /* Heartbeat is only sent once every 2 seconds.
8113 *
8114 * The heartbeat is to tell the ASF firmware that the host
8115 * driver is still alive. In the event that the OS crashes,
8116 * ASF needs to reset the hardware to free up the FIFO space
8117 * that may be filled with rx packets destined for the host.
8118 * If the FIFO is full, ASF will no longer function properly.
8119 *
8120 * Unintended resets have been reported on real time kernels
8121 * where the timer doesn't run on time. Netpoll will also have
8122 * same problem.
8123 *
8124 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8125 * to check the ring condition when the heartbeat is expiring
8126 * before doing the reset. This will prevent most unintended
8127 * resets.
8128 */
1da177e4 8129 if (!--tp->asf_counter) {
bc7959b2
MC		 8130 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8131 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8132 tg3_wait_for_event_ack(tp);
8133
bbadf503 8134 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8135 FWCMD_NICDRV_ALIVE3);
bbadf503 8136 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8137 /* 5 seconds timeout */
bbadf503 8138 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8139
8140 tg3_generate_fw_event(tp);
1da177e4
LT		 8141 }
8142 tp->asf_counter = tp->asf_multiplier;
8143 }
8144
f47c11ee 8145 spin_unlock(&tp->lock);
1da177e4 8146
f475f163 8147restart_timer:
1da177e4
LT		 8148 tp->timer.expires = jiffies + tp->timer_offset;
8149 add_timer(&tp->timer);
8150}
8151
4f125f42 8152static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8153{
7d12e780 8154 irq_handler_t fn;
fcfa0a32 8155 unsigned long flags;
4f125f42
MC		 8156 char *name;
8157 struct tg3_napi *tnapi = &tp->napi[irq_num];
8158
8159 if (tp->irq_cnt == 1)
8160 name = tp->dev->name;
8161 else {
8162 name = &tnapi->irq_lbl[0];
8163 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8164 name[IFNAMSIZ-1] = 0;
8165 }
fcfa0a32 8166
679563f4 8167 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8168 fn = tg3_msi;
8169 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8170 fn = tg3_msi_1shot;
1fb9df5d 8171 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8172 } else {
8173 fn = tg3_interrupt;
8174 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8175 fn = tg3_interrupt_tagged;
1fb9df5d 8176 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8177 }
4f125f42
MC		 8178
8179 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8180}
8181
7938109f
MC		 8182static int tg3_test_interrupt(struct tg3 *tp)
8183{
09943a18 8184 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8185 struct net_device *dev = tp->dev;
b16250e3 8186 int err, i, intr_ok = 0;
f6eb9b1f 8187 u32 val;
7938109f 8188
d4bc3927
MC		 8189 if (!netif_running(dev))
8190 return -ENODEV;
8191
7938109f
MC		 8192 tg3_disable_ints(tp);
8193
4f125f42 8194 free_irq(tnapi->irq_vec, tnapi);
7938109f 8195
f6eb9b1f
MC		 8196 /*
8197 * Turn off MSI one shot mode. Otherwise this test has no
8198 * observable way to know whether the interrupt was delivered.
8199 */
8200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8201 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8202 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8203 tw32(MSGINT_MODE, val);
8204 }
8205
4f125f42 8206 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8207 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8208 if (err)
8209 return err;
8210
898a56f8 8211 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8212 tg3_enable_ints(tp);
8213
8214 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8215 tnapi->coal_now);
7938109f
MC		 8216
8217 for (i = 0; i < 5; i++) {
b16250e3
MC		 8218 u32 int_mbox, misc_host_ctrl;
8219
898a56f8 8220 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8221 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8222
8223 if ((int_mbox != 0) ||
8224 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8225 intr_ok = 1;
7938109f 8226 break;
b16250e3
MC		 8227 }
8228
7938109f
MC		 8229 msleep(10);
8230 }
8231
8232 tg3_disable_ints(tp);
8233
4f125f42 8234 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8235
4f125f42 8236 err = tg3_request_irq(tp, 0);
7938109f
MC		 8237
8238 if (err)
8239 return err;
8240
f6eb9b1f
MC		 8241 if (intr_ok) {
8242 /* Reenable MSI one shot mode. */
8243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8244 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8245 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8246 tw32(MSGINT_MODE, val);
8247 }
7938109f 8248 return 0;
f6eb9b1f 8249 }
7938109f
MC		 8250
8251 return -EIO;
8252}
8253
8254/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8255 * successfully restored
8256 */
8257static int tg3_test_msi(struct tg3 *tp)
8258{
7938109f
MC		 8259 int err;
8260 u16 pci_cmd;
8261
8262 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8263 return 0;
8264
8265 /* Turn off SERR reporting in case MSI terminates with Master
8266 * Abort.
8267 */
8268 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8269 pci_write_config_word(tp->pdev, PCI_COMMAND,
8270 pci_cmd & ~PCI_COMMAND_SERR);
8271
8272 err = tg3_test_interrupt(tp);
8273
8274 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8275
8276 if (!err)
8277 return 0;
8278
8279 /* other failures */
8280 if (err != -EIO)
8281 return err;
8282
8283 /* MSI test failed, go back to INTx mode */
8284 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8285 "switching to INTx mode. Please report this failure to "
8286 "the PCI maintainer and include system chipset information.\n",
8287 tp->dev->name);
8288
4f125f42 8289 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8290
7938109f
MC		 8291 pci_disable_msi(tp->pdev);
8292
8293 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8294
4f125f42 8295 err = tg3_request_irq(tp, 0);
7938109f
MC		 8296 if (err)
8297 return err;
8298
8299 /* Need to reset the chip because the MSI cycle may have terminated
8300 * with Master Abort.
8301 */
f47c11ee 8302 tg3_full_lock(tp, 1);
7938109f 8303
944d980e 8304 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8305 err = tg3_init_hw(tp, 1);
7938109f 8306
f47c11ee 8307 tg3_full_unlock(tp);
7938109f
MC		 8308
8309 if (err)
4f125f42 8310 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8311
8312 return err;
8313}
8314
9e9fd12d
MC		 8315static int tg3_request_firmware(struct tg3 *tp)
8316{
8317 const __be32 *fw_data;
8318
8319 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8320 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8321 tp->dev->name, tp->fw_needed);
8322 return -ENOENT;
8323 }
8324
8325 fw_data = (void *)tp->fw->data;
8326
8327 /* Firmware blob starts with version numbers, followed by
8328 * start address and _full_ length including BSS sections
8329 * (which must be longer than the actual data, of course
8330 */
8331
8332 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8333 if (tp->fw_len < (tp->fw->size - 12)) {
8334 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8335 tp->dev->name, tp->fw_len, tp->fw_needed);
8336 release_firmware(tp->fw);
8337 tp->fw = NULL;
8338 return -EINVAL;
8339 }
8340
8341 /* We no longer need firmware; we have it. */
8342 tp->fw_needed = NULL;
8343 return 0;
8344}
8345
679563f4
MC		 8346static bool tg3_enable_msix(struct tg3 *tp)
8347{
8348 int i, rc, cpus = num_online_cpus();
8349 struct msix_entry msix_ent[tp->irq_max];
8350
8351 if (cpus == 1)
8352 /* Just fallback to the simpler MSI mode. */
8353 return false;
8354
8355 /*
8356 * We want as many rx rings enabled as there are cpus.
8357 * The first MSIX vector only deals with link interrupts, etc,
8358 * so we add one to the number of vectors we are requesting.
8359 */
8360 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8361
8362 for (i = 0; i < tp->irq_max; i++) {
8363 msix_ent[i].entry = i;
8364 msix_ent[i].vector = 0;
8365 }
8366
8367 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8368 if (rc != 0) {
8369 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8370 return false;
8371 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8372 return false;
8373 printk(KERN_NOTICE
8374 "%s: Requested %d MSI-X vectors, received %d\n",
8375 tp->dev->name, tp->irq_cnt, rc);
8376 tp->irq_cnt = rc;
8377 }
8378
baf8a94a
MC		 8379 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8380
679563f4
MC		 8381 for (i = 0; i < tp->irq_max; i++)
8382 tp->napi[i].irq_vec = msix_ent[i].vector;
8383
fe5f5787
MC		 8384 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8385
679563f4
MC		 8386 return true;
8387}
8388
07b0173c
MC		 8389static void tg3_ints_init(struct tg3 *tp)
8390{
679563f4
MC		 8391 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8392 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8393 /* All MSI supporting chips should support tagged
8394 * status. Assert that this is the case.
8395 */
679563f4
MC		 8396 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8397 "Not using MSI.\n", tp->dev->name);
8398 goto defcfg;
07b0173c 8399 }
4f125f42 8400
679563f4
MC		 8401 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8402 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8403 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8404 pci_enable_msi(tp->pdev) == 0)
8405 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8406
8407 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8408 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8409 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8410 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8411 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8412 }
8413defcfg:
8414 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8415 tp->irq_cnt = 1;
8416 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8417 tp->dev->real_num_tx_queues = 1;
679563f4 8418 }
07b0173c
MC		 8419}
8420
8421static void tg3_ints_fini(struct tg3 *tp)
8422{
679563f4
MC		 8423 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8424 pci_disable_msix(tp->pdev);
8425 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8426 pci_disable_msi(tp->pdev);
8427 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8428 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8429}
8430
1da177e4
LT		 8431static int tg3_open(struct net_device *dev)
8432{
8433 struct tg3 *tp = netdev_priv(dev);
4f125f42 8434 int i, err;
1da177e4 8435
9e9fd12d
MC		 8436 if (tp->fw_needed) {
8437 err = tg3_request_firmware(tp);
8438 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8439 if (err)
8440 return err;
8441 } else if (err) {
8442 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8443 tp->dev->name);
8444 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8445 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8446 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8447 tp->dev->name);
8448 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8449 }
8450 }
8451
c49a1561
MC		 8452 netif_carrier_off(tp->dev);
8453
bc1c7567 8454 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8455 if (err)
bc1c7567 8456 return err;
2f751b67
MC		 8457
8458 tg3_full_lock(tp, 0);
bc1c7567 8459
1da177e4
LT		 8460 tg3_disable_ints(tp);
8461 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8462
f47c11ee 8463 tg3_full_unlock(tp);
1da177e4 8464
679563f4
MC		 8465 /*
8466 * Setup interrupts first so we know how
8467 * many NAPI resources to allocate
8468 */
8469 tg3_ints_init(tp);
8470
1da177e4
LT		 8471 /* The placement of this call is tied
8472 * to the setup and use of Host TX descriptors.
8473 */
8474 err = tg3_alloc_consistent(tp);
8475 if (err)
679563f4 8476 goto err_out1;
88b06bc2 8477
fed97810 8478 tg3_napi_enable(tp);
1da177e4 8479
4f125f42
MC		 8480 for (i = 0; i < tp->irq_cnt; i++) {
8481 struct tg3_napi *tnapi = &tp->napi[i];
8482 err = tg3_request_irq(tp, i);
8483 if (err) {
8484 for (i--; i >= 0; i--)
8485 free_irq(tnapi->irq_vec, tnapi);
8486 break;
8487 }
8488 }
1da177e4 8489
07b0173c 8490 if (err)
679563f4 8491 goto err_out2;
bea3348e 8492
f47c11ee 8493 tg3_full_lock(tp, 0);
1da177e4 8494
8e7a22e3 8495 err = tg3_init_hw(tp, 1);
1da177e4 8496 if (err) {
944d980e 8497 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8498 tg3_free_rings(tp);
8499 } else {
fac9b83e
DM		 8500 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8501 tp->timer_offset = HZ;
8502 else
8503 tp->timer_offset = HZ / 10;
8504
8505 BUG_ON(tp->timer_offset > HZ);
8506 tp->timer_counter = tp->timer_multiplier =
8507 (HZ / tp->timer_offset);
8508 tp->asf_counter = tp->asf_multiplier =
28fbef78 8509 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8510
8511 init_timer(&tp->timer);
8512 tp->timer.expires = jiffies + tp->timer_offset;
8513 tp->timer.data = (unsigned long) tp;
8514 tp->timer.function = tg3_timer;
1da177e4
LT		 8515 }
8516
f47c11ee 8517 tg3_full_unlock(tp);
1da177e4 8518
07b0173c 8519 if (err)
679563f4 8520 goto err_out3;
1da177e4 8521
7938109f
MC		 8522 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8523 err = tg3_test_msi(tp);
fac9b83e 8524
7938109f 8525 if (err) {
f47c11ee 8526 tg3_full_lock(tp, 0);
944d980e 8527 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8528 tg3_free_rings(tp);
f47c11ee 8529 tg3_full_unlock(tp);
7938109f 8530
679563f4 8531 goto err_out2;
7938109f 8532 }
fcfa0a32 8533
f6eb9b1f
MC		 8534 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8535 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8536 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8537 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8538
f6eb9b1f
MC		 8539 tw32(PCIE_TRANSACTION_CFG,
8540 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8541 }
7938109f
MC		 8542 }
8543
b02fd9e3
MC		 8544 tg3_phy_start(tp);
8545
f47c11ee 8546 tg3_full_lock(tp, 0);
1da177e4 8547
7938109f
MC		 8548 add_timer(&tp->timer);
8549 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8550 tg3_enable_ints(tp);
8551
f47c11ee 8552 tg3_full_unlock(tp);
1da177e4 8553
fe5f5787 8554 netif_tx_start_all_queues(dev);
1da177e4
LT		 8555
8556 return 0;
07b0173c 8557
679563f4 8558err_out3:
4f125f42
MC		 8559 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8560 struct tg3_napi *tnapi = &tp->napi[i];
8561 free_irq(tnapi->irq_vec, tnapi);
8562 }
07b0173c 8563
679563f4 8564err_out2:
fed97810 8565 tg3_napi_disable(tp);
07b0173c 8566 tg3_free_consistent(tp);
679563f4
MC		 8567
8568err_out1:
8569 tg3_ints_fini(tp);
07b0173c 8570 return err;
1da177e4
LT		 8571}
8572
8573#if 0
8574/*static*/ void tg3_dump_state(struct tg3 *tp)
8575{
8576 u32 val32, val32_2, val32_3, val32_4, val32_5;
8577 u16 val16;
8578 int i;
898a56f8 8579 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8580
8581 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8582 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8583 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8584 val16, val32);
8585
8586 /* MAC block */
8587 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8588 tr32(MAC_MODE), tr32(MAC_STATUS));
8589 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8590 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8591 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8592 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8593 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8594 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8595
8596 /* Send data initiator control block */
8597 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8598 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8599 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8600 tr32(SNDDATAI_STATSCTRL));
8601
8602 /* Send data completion control block */
8603 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8604
8605 /* Send BD ring selector block */
8606 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8607 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8608
8609 /* Send BD initiator control block */
8610 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8611 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8612
8613 /* Send BD completion control block */
8614 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8615
8616 /* Receive list placement control block */
8617 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8618 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8619 printk(" RCVLPC_STATSCTRL[%08x]\n",
8620 tr32(RCVLPC_STATSCTRL));
8621
8622 /* Receive data and receive BD initiator control block */
8623 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8624 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8625
8626 /* Receive data completion control block */
8627 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8628 tr32(RCVDCC_MODE));
8629
8630 /* Receive BD initiator control block */
8631 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8632 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8633
8634 /* Receive BD completion control block */
8635 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8636 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8637
8638 /* Receive list selector control block */
8639 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8640 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8641
8642 /* Mbuf cluster free block */
8643 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8644 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8645
8646 /* Host coalescing control block */
8647 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8648 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8649 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8650 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8651 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8652 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8653 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8654 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8655 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8656 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8657 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8658 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8659
8660 /* Memory arbiter control block */
8661 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8662 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8663
8664 /* Buffer manager control block */
8665 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8666 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8667 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8668 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8669 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8670 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8671 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8672 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8673
8674 /* Read DMA control block */
8675 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8676 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8677
8678 /* Write DMA control block */
8679 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8680 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8681
8682 /* DMA completion block */
8683 printk("DEBUG: DMAC_MODE[%08x]\n",
8684 tr32(DMAC_MODE));
8685
8686 /* GRC block */
8687 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8688 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8689 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8690 tr32(GRC_LOCAL_CTRL));
8691
8692 /* TG3_BDINFOs */
8693 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8694 tr32(RCVDBDI_JUMBO_BD + 0x0),
8695 tr32(RCVDBDI_JUMBO_BD + 0x4),
8696 tr32(RCVDBDI_JUMBO_BD + 0x8),
8697 tr32(RCVDBDI_JUMBO_BD + 0xc));
8698 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8699 tr32(RCVDBDI_STD_BD + 0x0),
8700 tr32(RCVDBDI_STD_BD + 0x4),
8701 tr32(RCVDBDI_STD_BD + 0x8),
8702 tr32(RCVDBDI_STD_BD + 0xc));
8703 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8704 tr32(RCVDBDI_MINI_BD + 0x0),
8705 tr32(RCVDBDI_MINI_BD + 0x4),
8706 tr32(RCVDBDI_MINI_BD + 0x8),
8707 tr32(RCVDBDI_MINI_BD + 0xc));
8708
8709 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8710 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8711 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8712 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8713 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8714 val32, val32_2, val32_3, val32_4);
8715
8716 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8717 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8718 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8719 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8720 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8721 val32, val32_2, val32_3, val32_4);
8722
8723 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8724 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8725 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8726 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8727 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8728 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8729 val32, val32_2, val32_3, val32_4, val32_5);
8730
8731 /* SW status block */
898a56f8
MC		 8732 printk(KERN_DEBUG
8733 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8734 sblk->status,
8735 sblk->status_tag,
8736 sblk->rx_jumbo_consumer,
8737 sblk->rx_consumer,
8738 sblk->rx_mini_consumer,
8739 sblk->idx[0].rx_producer,
8740 sblk->idx[0].tx_consumer);
1da177e4
LT		 8741
8742 /* SW statistics block */
8743 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8744 ((u32 *)tp->hw_stats)[0],
8745 ((u32 *)tp->hw_stats)[1],
8746 ((u32 *)tp->hw_stats)[2],
8747 ((u32 *)tp->hw_stats)[3]);
8748
8749 /* Mailboxes */
8750 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8751 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8752 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8753 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8754 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8755
8756 /* NIC side send descriptors. */
8757 for (i = 0; i < 6; i++) {
8758 unsigned long txd;
8759
8760 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8761 + (i * sizeof(struct tg3_tx_buffer_desc));
8762 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8763 i,
8764 readl(txd + 0x0), readl(txd + 0x4),
8765 readl(txd + 0x8), readl(txd + 0xc));
8766 }
8767
8768 /* NIC side RX descriptors. */
8769 for (i = 0; i < 6; i++) {
8770 unsigned long rxd;
8771
8772 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8773 + (i * sizeof(struct tg3_rx_buffer_desc));
8774 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8775 i,
8776 readl(rxd + 0x0), readl(rxd + 0x4),
8777 readl(rxd + 0x8), readl(rxd + 0xc));
8778 rxd += (4 * sizeof(u32));
8779 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8780 i,
8781 readl(rxd + 0x0), readl(rxd + 0x4),
8782 readl(rxd + 0x8), readl(rxd + 0xc));
8783 }
8784
8785 for (i = 0; i < 6; i++) {
8786 unsigned long rxd;
8787
8788 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8789 + (i * sizeof(struct tg3_rx_buffer_desc));
8790 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8791 i,
8792 readl(rxd + 0x0), readl(rxd + 0x4),
8793 readl(rxd + 0x8), readl(rxd + 0xc));
8794 rxd += (4 * sizeof(u32));
8795 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8796 i,
8797 readl(rxd + 0x0), readl(rxd + 0x4),
8798 readl(rxd + 0x8), readl(rxd + 0xc));
8799 }
8800}
8801#endif
8802
8803static struct net_device_stats *tg3_get_stats(struct net_device *);
8804static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8805
8806static int tg3_close(struct net_device *dev)
8807{
4f125f42 8808 int i;
1da177e4
LT		 8809 struct tg3 *tp = netdev_priv(dev);
8810
fed97810 8811 tg3_napi_disable(tp);
28e53bdd 8812 cancel_work_sync(&tp->reset_task);
7faa006f 8813
fe5f5787 8814 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8815
8816 del_timer_sync(&tp->timer);
8817
24bb4fb6
MC		 8818 tg3_phy_stop(tp);
8819
f47c11ee 8820 tg3_full_lock(tp, 1);
1da177e4
LT		 8821#if 0
8822 tg3_dump_state(tp);
8823#endif
8824
8825 tg3_disable_ints(tp);
8826
944d980e 8827 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8828 tg3_free_rings(tp);
5cf64b8a 8829 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8830
f47c11ee 8831 tg3_full_unlock(tp);
1da177e4 8832
4f125f42
MC		 8833 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8834 struct tg3_napi *tnapi = &tp->napi[i];
8835 free_irq(tnapi->irq_vec, tnapi);
8836 }
07b0173c
MC		 8837
8838 tg3_ints_fini(tp);
1da177e4
LT		 8839
8840 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8841 sizeof(tp->net_stats_prev));
8842 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8843 sizeof(tp->estats_prev));
8844
8845 tg3_free_consistent(tp);
8846
bc1c7567
MC		 8847 tg3_set_power_state(tp, PCI_D3hot);
8848
8849 netif_carrier_off(tp->dev);
8850
1da177e4
LT		 8851 return 0;
8852}
8853
8854static inline unsigned long get_stat64(tg3_stat64_t *val)
8855{
8856 unsigned long ret;
8857
8858#if (BITS_PER_LONG == 32)
8859 ret = val->low;
8860#else
8861 ret = ((u64)val->high << 32) | ((u64)val->low);
8862#endif
8863 return ret;
8864}
8865
816f8b86
SB		 8866static inline u64 get_estat64(tg3_stat64_t *val)
8867{
8868 return ((u64)val->high << 32) | ((u64)val->low);
8869}
8870
1da177e4
LT		 8871static unsigned long calc_crc_errors(struct tg3 *tp)
8872{
8873 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8874
8875 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8876 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8877 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8878 u32 val;
8879
f47c11ee 8880 spin_lock_bh(&tp->lock);
569a5df8
MC		 8881 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8882 tg3_writephy(tp, MII_TG3_TEST1,
8883 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8884 tg3_readphy(tp, 0x14, &val);
8885 } else
8886 val = 0;
f47c11ee 8887 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8888
8889 tp->phy_crc_errors += val;
8890
8891 return tp->phy_crc_errors;
8892 }
8893
8894 return get_stat64(&hw_stats->rx_fcs_errors);
8895}
8896
8897#define ESTAT_ADD(member) \
8898 estats->member = old_estats->member + \
816f8b86 8899 get_estat64(&hw_stats->member)
1da177e4
LT		 8900
8901static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8902{
8903 struct tg3_ethtool_stats *estats = &tp->estats;
8904 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8905 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8906
8907 if (!hw_stats)
8908 return old_estats;
8909
8910 ESTAT_ADD(rx_octets);
8911 ESTAT_ADD(rx_fragments);
8912 ESTAT_ADD(rx_ucast_packets);
8913 ESTAT_ADD(rx_mcast_packets);
8914 ESTAT_ADD(rx_bcast_packets);
8915 ESTAT_ADD(rx_fcs_errors);
8916 ESTAT_ADD(rx_align_errors);
8917 ESTAT_ADD(rx_xon_pause_rcvd);
8918 ESTAT_ADD(rx_xoff_pause_rcvd);
8919 ESTAT_ADD(rx_mac_ctrl_rcvd);
8920 ESTAT_ADD(rx_xoff_entered);
8921 ESTAT_ADD(rx_frame_too_long_errors);
8922 ESTAT_ADD(rx_jabbers);
8923 ESTAT_ADD(rx_undersize_packets);
8924 ESTAT_ADD(rx_in_length_errors);
8925 ESTAT_ADD(rx_out_length_errors);
8926 ESTAT_ADD(rx_64_or_less_octet_packets);
8927 ESTAT_ADD(rx_65_to_127_octet_packets);
8928 ESTAT_ADD(rx_128_to_255_octet_packets);
8929 ESTAT_ADD(rx_256_to_511_octet_packets);
8930 ESTAT_ADD(rx_512_to_1023_octet_packets);
8931 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8932 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8933 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8934 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8935 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8936
8937 ESTAT_ADD(tx_octets);
8938 ESTAT_ADD(tx_collisions);
8939 ESTAT_ADD(tx_xon_sent);
8940 ESTAT_ADD(tx_xoff_sent);
8941 ESTAT_ADD(tx_flow_control);
8942 ESTAT_ADD(tx_mac_errors);
8943 ESTAT_ADD(tx_single_collisions);
8944 ESTAT_ADD(tx_mult_collisions);
8945 ESTAT_ADD(tx_deferred);
8946 ESTAT_ADD(tx_excessive_collisions);
8947 ESTAT_ADD(tx_late_collisions);
8948 ESTAT_ADD(tx_collide_2times);
8949 ESTAT_ADD(tx_collide_3times);
8950 ESTAT_ADD(tx_collide_4times);
8951 ESTAT_ADD(tx_collide_5times);
8952 ESTAT_ADD(tx_collide_6times);
8953 ESTAT_ADD(tx_collide_7times);
8954 ESTAT_ADD(tx_collide_8times);
8955 ESTAT_ADD(tx_collide_9times);
8956 ESTAT_ADD(tx_collide_10times);
8957 ESTAT_ADD(tx_collide_11times);
8958 ESTAT_ADD(tx_collide_12times);
8959 ESTAT_ADD(tx_collide_13times);
8960 ESTAT_ADD(tx_collide_14times);
8961 ESTAT_ADD(tx_collide_15times);
8962 ESTAT_ADD(tx_ucast_packets);
8963 ESTAT_ADD(tx_mcast_packets);
8964 ESTAT_ADD(tx_bcast_packets);
8965 ESTAT_ADD(tx_carrier_sense_errors);
8966 ESTAT_ADD(tx_discards);
8967 ESTAT_ADD(tx_errors);
8968
8969 ESTAT_ADD(dma_writeq_full);
8970 ESTAT_ADD(dma_write_prioq_full);
8971 ESTAT_ADD(rxbds_empty);
8972 ESTAT_ADD(rx_discards);
8973 ESTAT_ADD(rx_errors);
8974 ESTAT_ADD(rx_threshold_hit);
8975
8976 ESTAT_ADD(dma_readq_full);
8977 ESTAT_ADD(dma_read_prioq_full);
8978 ESTAT_ADD(tx_comp_queue_full);
8979
8980 ESTAT_ADD(ring_set_send_prod_index);
8981 ESTAT_ADD(ring_status_update);
8982 ESTAT_ADD(nic_irqs);
8983 ESTAT_ADD(nic_avoided_irqs);
8984 ESTAT_ADD(nic_tx_threshold_hit);
8985
8986 return estats;
8987}
8988
8989static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8990{
8991 struct tg3 *tp = netdev_priv(dev);
8992 struct net_device_stats *stats = &tp->net_stats;
8993 struct net_device_stats *old_stats = &tp->net_stats_prev;
8994 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8995
8996 if (!hw_stats)
8997 return old_stats;
8998
8999 stats->rx_packets = old_stats->rx_packets +
9000 get_stat64(&hw_stats->rx_ucast_packets) +
9001 get_stat64(&hw_stats->rx_mcast_packets) +
9002 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9003
1da177e4
LT		 9004 stats->tx_packets = old_stats->tx_packets +
9005 get_stat64(&hw_stats->tx_ucast_packets) +
9006 get_stat64(&hw_stats->tx_mcast_packets) +
9007 get_stat64(&hw_stats->tx_bcast_packets);
9008
9009 stats->rx_bytes = old_stats->rx_bytes +
9010 get_stat64(&hw_stats->rx_octets);
9011 stats->tx_bytes = old_stats->tx_bytes +
9012 get_stat64(&hw_stats->tx_octets);
9013
9014 stats->rx_errors = old_stats->rx_errors +
4f63b877 9015 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9016 stats->tx_errors = old_stats->tx_errors +
9017 get_stat64(&hw_stats->tx_errors) +
9018 get_stat64(&hw_stats->tx_mac_errors) +
9019 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9020 get_stat64(&hw_stats->tx_discards);
9021
9022 stats->multicast = old_stats->multicast +
9023 get_stat64(&hw_stats->rx_mcast_packets);
9024 stats->collisions = old_stats->collisions +
9025 get_stat64(&hw_stats->tx_collisions);
9026
9027 stats->rx_length_errors = old_stats->rx_length_errors +
9028 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9029 get_stat64(&hw_stats->rx_undersize_packets);
9030
9031 stats->rx_over_errors = old_stats->rx_over_errors +
9032 get_stat64(&hw_stats->rxbds_empty);
9033 stats->rx_frame_errors = old_stats->rx_frame_errors +
9034 get_stat64(&hw_stats->rx_align_errors);
9035 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9036 get_stat64(&hw_stats->tx_discards);
9037 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9038 get_stat64(&hw_stats->tx_carrier_sense_errors);
9039
9040 stats->rx_crc_errors = old_stats->rx_crc_errors +
9041 calc_crc_errors(tp);
9042
4f63b877
JL		 9043 stats->rx_missed_errors = old_stats->rx_missed_errors +
9044 get_stat64(&hw_stats->rx_discards);
9045
1da177e4
LT		 9046 return stats;
9047}
9048
9049static inline u32 calc_crc(unsigned char *buf, int len)
9050{
9051 u32 reg;
9052 u32 tmp;
9053 int j, k;
9054
9055 reg = 0xffffffff;
9056
9057 for (j = 0; j < len; j++) {
9058 reg ^= buf[j];
9059
9060 for (k = 0; k < 8; k++) {
9061 tmp = reg & 0x01;
9062
9063 reg >>= 1;
9064
9065 if (tmp) {
9066 reg ^= 0xedb88320;
9067 }
9068 }
9069 }
9070
9071 return ~reg;
9072}
9073
9074static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9075{
9076 /* accept or reject all multicast frames */
9077 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9078 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9079 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9080 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9081}
9082
9083static void __tg3_set_rx_mode(struct net_device *dev)
9084{
9085 struct tg3 *tp = netdev_priv(dev);
9086 u32 rx_mode;
9087
9088 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9089 RX_MODE_KEEP_VLAN_TAG);
9090
9091 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9092 * flag clear.
9093 */
9094#if TG3_VLAN_TAG_USED
9095 if (!tp->vlgrp &&
9096 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9097 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9098#else
9099 /* By definition, VLAN is disabled always in this
9100 * case.
9101 */
9102 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9103 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9104#endif
9105
9106 if (dev->flags & IFF_PROMISC) {
9107 /* Promiscuous mode. */
9108 rx_mode |= RX_MODE_PROMISC;
9109 } else if (dev->flags & IFF_ALLMULTI) {
9110 /* Accept all multicast. */
9111 tg3_set_multi (tp, 1);
9112 } else if (dev->mc_count < 1) {
9113 /* Reject all multicast. */
9114 tg3_set_multi (tp, 0);
9115 } else {
9116 /* Accept one or more multicast(s). */
9117 struct dev_mc_list *mclist;
9118 unsigned int i;
9119 u32 mc_filter[4] = { 0, };
9120 u32 regidx;
9121 u32 bit;
9122 u32 crc;
9123
9124 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9125 i++, mclist = mclist->next) {
9126
9127 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9128 bit = ~crc & 0x7f;
9129 regidx = (bit & 0x60) >> 5;
9130 bit &= 0x1f;
9131 mc_filter[regidx] |= (1 << bit);
9132 }
9133
9134 tw32(MAC_HASH_REG_0, mc_filter[0]);
9135 tw32(MAC_HASH_REG_1, mc_filter[1]);
9136 tw32(MAC_HASH_REG_2, mc_filter[2]);
9137 tw32(MAC_HASH_REG_3, mc_filter[3]);
9138 }
9139
9140 if (rx_mode != tp->rx_mode) {
9141 tp->rx_mode = rx_mode;
9142 tw32_f(MAC_RX_MODE, rx_mode);
9143 udelay(10);
9144 }
9145}
9146
9147static void tg3_set_rx_mode(struct net_device *dev)
9148{
9149 struct tg3 *tp = netdev_priv(dev);
9150
e75f7c90
MC		 9151 if (!netif_running(dev))
9152 return;
9153
f47c11ee 9154 tg3_full_lock(tp, 0);
1da177e4 9155 __tg3_set_rx_mode(dev);
f47c11ee 9156 tg3_full_unlock(tp);
1da177e4
LT		 9157}
9158
9159#define TG3_REGDUMP_LEN (32 * 1024)
9160
9161static int tg3_get_regs_len(struct net_device *dev)
9162{
9163 return TG3_REGDUMP_LEN;
9164}
9165
9166static void tg3_get_regs(struct net_device *dev,
9167 struct ethtool_regs *regs, void *_p)
9168{
9169 u32 *p = _p;
9170 struct tg3 *tp = netdev_priv(dev);
9171 u8 *orig_p = _p;
9172 int i;
9173
9174 regs->version = 0;
9175
9176 memset(p, 0, TG3_REGDUMP_LEN);
9177
bc1c7567
MC		 9178 if (tp->link_config.phy_is_low_power)
9179 return;
9180
f47c11ee 9181 tg3_full_lock(tp, 0);
1da177e4
LT		 9182
9183#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9184#define GET_REG32_LOOP(base,len) \
9185do { p = (u32 *)(orig_p + (base)); \
9186 for (i = 0; i < len; i += 4) \
9187 __GET_REG32((base) + i); \
9188} while (0)
9189#define GET_REG32_1(reg) \
9190do { p = (u32 *)(orig_p + (reg)); \
9191 __GET_REG32((reg)); \
9192} while (0)
9193
9194 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9195 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9196 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9197 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9198 GET_REG32_1(SNDDATAC_MODE);
9199 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9200 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9201 GET_REG32_1(SNDBDC_MODE);
9202 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9203 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9204 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9205 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9206 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9207 GET_REG32_1(RCVDCC_MODE);
9208 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9209 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9210 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9211 GET_REG32_1(MBFREE_MODE);
9212 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9213 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9214 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9215 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9216 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9217 GET_REG32_1(RX_CPU_MODE);
9218 GET_REG32_1(RX_CPU_STATE);
9219 GET_REG32_1(RX_CPU_PGMCTR);
9220 GET_REG32_1(RX_CPU_HWBKPT);
9221 GET_REG32_1(TX_CPU_MODE);
9222 GET_REG32_1(TX_CPU_STATE);
9223 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9224 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9225 GET_REG32_LOOP(FTQ_RESET, 0x120);
9226 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9227 GET_REG32_1(DMAC_MODE);
9228 GET_REG32_LOOP(GRC_MODE, 0x4c);
9229 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9230 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9231
9232#undef __GET_REG32
9233#undef GET_REG32_LOOP
9234#undef GET_REG32_1
9235
f47c11ee 9236 tg3_full_unlock(tp);
1da177e4
LT		 9237}
9238
9239static int tg3_get_eeprom_len(struct net_device *dev)
9240{
9241 struct tg3 *tp = netdev_priv(dev);
9242
9243 return tp->nvram_size;
9244}
9245
1da177e4
LT		 9246static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9247{
9248 struct tg3 *tp = netdev_priv(dev);
9249 int ret;
9250 u8 *pd;
b9fc7dc5 9251 u32 i, offset, len, b_offset, b_count;
a9dc529d 9252 __be32 val;
1da177e4 9253
df259d8c
MC		 9254 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9255 return -EINVAL;
9256
bc1c7567
MC		 9257 if (tp->link_config.phy_is_low_power)
9258 return -EAGAIN;
9259
1da177e4
LT		 9260 offset = eeprom->offset;
9261 len = eeprom->len;
9262 eeprom->len = 0;
9263
9264 eeprom->magic = TG3_EEPROM_MAGIC;
9265
9266 if (offset & 3) {
9267 /* adjustments to start on required 4 byte boundary */
9268 b_offset = offset & 3;
9269 b_count = 4 - b_offset;
9270 if (b_count > len) {
9271 /* i.e. offset=1 len=2 */
9272 b_count = len;
9273 }
a9dc529d 9274 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9275 if (ret)
9276 return ret;
1da177e4
LT		 9277 memcpy(data, ((char*)&val) + b_offset, b_count);
9278 len -= b_count;
9279 offset += b_count;
9280 eeprom->len += b_count;
9281 }
9282
9283 /* read bytes upto the last 4 byte boundary */
9284 pd = &data[eeprom->len];
9285 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9286 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9287 if (ret) {
9288 eeprom->len += i;
9289 return ret;
9290 }
1da177e4
LT		 9291 memcpy(pd + i, &val, 4);
9292 }
9293 eeprom->len += i;
9294
9295 if (len & 3) {
9296 /* read last bytes not ending on 4 byte boundary */
9297 pd = &data[eeprom->len];
9298 b_count = len & 3;
9299 b_offset = offset + len - b_count;
a9dc529d 9300 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9301 if (ret)
9302 return ret;
b9fc7dc5 9303 memcpy(pd, &val, b_count);
1da177e4
LT		 9304 eeprom->len += b_count;
9305 }
9306 return 0;
9307}
9308
6aa20a22 9309static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9310
9311static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9312{
9313 struct tg3 *tp = netdev_priv(dev);
9314 int ret;
b9fc7dc5 9315 u32 offset, len, b_offset, odd_len;
1da177e4 9316 u8 *buf;
a9dc529d 9317 __be32 start, end;
1da177e4 9318
bc1c7567
MC		 9319 if (tp->link_config.phy_is_low_power)
9320 return -EAGAIN;
9321
df259d8c
MC		 9322 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9323 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9324 return -EINVAL;
9325
9326 offset = eeprom->offset;
9327 len = eeprom->len;
9328
9329 if ((b_offset = (offset & 3))) {
9330 /* adjustments to start on required 4 byte boundary */
a9dc529d 9331 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9332 if (ret)
9333 return ret;
1da177e4
LT		 9334 len += b_offset;
9335 offset &= ~3;
1c8594b4
MC		 9336 if (len < 4)
9337 len = 4;
1da177e4
LT		 9338 }
9339
9340 odd_len = 0;
1c8594b4 9341 if (len & 3) {
1da177e4
LT		 9342 /* adjustments to end on required 4 byte boundary */
9343 odd_len = 1;
9344 len = (len + 3) & ~3;
a9dc529d 9345 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9346 if (ret)
9347 return ret;
1da177e4
LT		 9348 }
9349
9350 buf = data;
9351 if (b_offset || odd_len) {
9352 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9353 if (!buf)
1da177e4
LT		 9354 return -ENOMEM;
9355 if (b_offset)
9356 memcpy(buf, &start, 4);
9357 if (odd_len)
9358 memcpy(buf+len-4, &end, 4);
9359 memcpy(buf + b_offset, data, eeprom->len);
9360 }
9361
9362 ret = tg3_nvram_write_block(tp, offset, len, buf);
9363
9364 if (buf != data)
9365 kfree(buf);
9366
9367 return ret;
9368}
9369
9370static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9371{
b02fd9e3
MC		 9372 struct tg3 *tp = netdev_priv(dev);
9373
9374 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9375 struct phy_device *phydev;
b02fd9e3
MC		 9376 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9377 return -EAGAIN;
3f0e3ad7
MC		 9378 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9379 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9380 }
6aa20a22 9381
1da177e4
LT		 9382 cmd->supported = (SUPPORTED_Autoneg);
9383
9384 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9385 cmd->supported |= (SUPPORTED_1000baseT_Half |
9386 SUPPORTED_1000baseT_Full);
9387
ef348144 9388 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9389 cmd->supported |= (SUPPORTED_100baseT_Half |
9390 SUPPORTED_100baseT_Full |
9391 SUPPORTED_10baseT_Half |
9392 SUPPORTED_10baseT_Full |
3bebab59 9393 SUPPORTED_TP);
ef348144
KK		 9394 cmd->port = PORT_TP;
9395 } else {
1da177e4 9396 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9397 cmd->port = PORT_FIBRE;
9398 }
6aa20a22 9399
1da177e4
LT		 9400 cmd->advertising = tp->link_config.advertising;
9401 if (netif_running(dev)) {
9402 cmd->speed = tp->link_config.active_speed;
9403 cmd->duplex = tp->link_config.active_duplex;
9404 }
882e9793 9405 cmd->phy_address = tp->phy_addr;
7e5856bd 9406 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9407 cmd->autoneg = tp->link_config.autoneg;
9408 cmd->maxtxpkt = 0;
9409 cmd->maxrxpkt = 0;
9410 return 0;
9411}
6aa20a22 9412
1da177e4
LT		 9413static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9414{
9415 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9416
b02fd9e3 9417 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9418 struct phy_device *phydev;
b02fd9e3
MC		 9419 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9420 return -EAGAIN;
3f0e3ad7
MC		 9421 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9422 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9423 }
9424
7e5856bd
MC		 9425 if (cmd->autoneg != AUTONEG_ENABLE &&
9426 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9427 return -EINVAL;
7e5856bd
MC		 9428
9429 if (cmd->autoneg == AUTONEG_DISABLE &&
9430 cmd->duplex != DUPLEX_FULL &&
9431 cmd->duplex != DUPLEX_HALF)
37ff238d 9432 return -EINVAL;
1da177e4 9433
7e5856bd
MC		 9434 if (cmd->autoneg == AUTONEG_ENABLE) {
9435 u32 mask = ADVERTISED_Autoneg |
9436 ADVERTISED_Pause |
9437 ADVERTISED_Asym_Pause;
9438
9439 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9440 mask |= ADVERTISED_1000baseT_Half |
9441 ADVERTISED_1000baseT_Full;
9442
9443 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9444 mask |= ADVERTISED_100baseT_Half |
9445 ADVERTISED_100baseT_Full |
9446 ADVERTISED_10baseT_Half |
9447 ADVERTISED_10baseT_Full |
9448 ADVERTISED_TP;
9449 else
9450 mask |= ADVERTISED_FIBRE;
9451
9452 if (cmd->advertising & ~mask)
9453 return -EINVAL;
9454
9455 mask &= (ADVERTISED_1000baseT_Half |
9456 ADVERTISED_1000baseT_Full |
9457 ADVERTISED_100baseT_Half |
9458 ADVERTISED_100baseT_Full |
9459 ADVERTISED_10baseT_Half |
9460 ADVERTISED_10baseT_Full);
9461
9462 cmd->advertising &= mask;
9463 } else {
9464 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9465 if (cmd->speed != SPEED_1000)
9466 return -EINVAL;
9467
9468 if (cmd->duplex != DUPLEX_FULL)
9469 return -EINVAL;
9470 } else {
9471 if (cmd->speed != SPEED_100 &&
9472 cmd->speed != SPEED_10)
9473 return -EINVAL;
9474 }
9475 }
9476
f47c11ee 9477 tg3_full_lock(tp, 0);
1da177e4
LT		 9478
9479 tp->link_config.autoneg = cmd->autoneg;
9480 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9481 tp->link_config.advertising = (cmd->advertising |
9482 ADVERTISED_Autoneg);
1da177e4
LT		 9483 tp->link_config.speed = SPEED_INVALID;
9484 tp->link_config.duplex = DUPLEX_INVALID;
9485 } else {
9486 tp->link_config.advertising = 0;
9487 tp->link_config.speed = cmd->speed;
9488 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9489 }
6aa20a22 9490
24fcad6b
MC		 9491 tp->link_config.orig_speed = tp->link_config.speed;
9492 tp->link_config.orig_duplex = tp->link_config.duplex;
9493 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9494
1da177e4
LT		 9495 if (netif_running(dev))
9496 tg3_setup_phy(tp, 1);
9497
f47c11ee 9498 tg3_full_unlock(tp);
6aa20a22 9499
1da177e4
LT		 9500 return 0;
9501}
6aa20a22 9502
1da177e4
LT		 9503static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9504{
9505 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9506
1da177e4
LT		 9507 strcpy(info->driver, DRV_MODULE_NAME);
9508 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9509 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9510 strcpy(info->bus_info, pci_name(tp->pdev));
9511}
6aa20a22 9512
1da177e4
LT		 9513static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9514{
9515 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9516
12dac075
RW		 9517 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9518 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9519 wol->supported = WAKE_MAGIC;
9520 else
9521 wol->supported = 0;
1da177e4 9522 wol->wolopts = 0;
05ac4cb7
MC		 9523 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9524 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9525 wol->wolopts = WAKE_MAGIC;
9526 memset(&wol->sopass, 0, sizeof(wol->sopass));
9527}
6aa20a22 9528
1da177e4
LT		 9529static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9530{
9531 struct tg3 *tp = netdev_priv(dev);
12dac075 9532 struct device *dp = &tp->pdev->dev;
6aa20a22 9533
1da177e4
LT		 9534 if (wol->wolopts & ~WAKE_MAGIC)
9535 return -EINVAL;
9536 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9537 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9538 return -EINVAL;
6aa20a22 9539
f47c11ee 9540 spin_lock_bh(&tp->lock);
12dac075 9541 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9542 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9543 device_set_wakeup_enable(dp, true);
9544 } else {
1da177e4 9545 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9546 device_set_wakeup_enable(dp, false);
9547 }
f47c11ee 9548 spin_unlock_bh(&tp->lock);
6aa20a22 9549
1da177e4
LT		 9550 return 0;
9551}
6aa20a22 9552
1da177e4
LT		 9553static u32 tg3_get_msglevel(struct net_device *dev)
9554{
9555 struct tg3 *tp = netdev_priv(dev);
9556 return tp->msg_enable;
9557}
6aa20a22 9558
1da177e4
LT		 9559static void tg3_set_msglevel(struct net_device *dev, u32 value)
9560{
9561 struct tg3 *tp = netdev_priv(dev);
9562 tp->msg_enable = value;
9563}
6aa20a22 9564
1da177e4
LT		 9565static int tg3_set_tso(struct net_device *dev, u32 value)
9566{
9567 struct tg3 *tp = netdev_priv(dev);
9568
9569 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9570 if (value)
9571 return -EINVAL;
9572 return 0;
9573 }
027455ad 9574 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9575 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9576 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9577 if (value) {
b0026624 9578 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9579 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9581 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9582 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9583 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9584 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9585 dev->features |= NETIF_F_TSO_ECN;
9586 } else
9587 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9588 }
1da177e4
LT		 9589 return ethtool_op_set_tso(dev, value);
9590}
6aa20a22 9591
1da177e4
LT		 9592static int tg3_nway_reset(struct net_device *dev)
9593{
9594 struct tg3 *tp = netdev_priv(dev);
1da177e4 9595 int r;
6aa20a22 9596
1da177e4
LT		 9597 if (!netif_running(dev))
9598 return -EAGAIN;
9599
c94e3941
MC		 9600 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9601 return -EINVAL;
9602
b02fd9e3
MC		 9603 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9604 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9605 return -EAGAIN;
3f0e3ad7 9606 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9607 } else {
9608 u32 bmcr;
9609
9610 spin_lock_bh(&tp->lock);
9611 r = -EINVAL;
9612 tg3_readphy(tp, MII_BMCR, &bmcr);
9613 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9614 ((bmcr & BMCR_ANENABLE) ||
9615 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9616 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9617 BMCR_ANENABLE);
9618 r = 0;
9619 }
9620 spin_unlock_bh(&tp->lock);
1da177e4 9621 }
6aa20a22 9622
1da177e4
LT		 9623 return r;
9624}
6aa20a22 9625
1da177e4
LT		 9626static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9627{
9628 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9629
1da177e4
LT		 9630 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9631 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9632 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9633 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9634 else
9635 ering->rx_jumbo_max_pending = 0;
9636
9637 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9638
9639 ering->rx_pending = tp->rx_pending;
9640 ering->rx_mini_pending = 0;
4f81c32b
MC		 9641 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9642 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9643 else
9644 ering->rx_jumbo_pending = 0;
9645
f3f3f27e 9646 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9647}
6aa20a22 9648
1da177e4
LT		 9649static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9650{
9651 struct tg3 *tp = netdev_priv(dev);
646c9edd 9652 int i, irq_sync = 0, err = 0;
6aa20a22 9653
1da177e4
LT		 9654 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9655 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9656 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9657 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9658 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9659 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9660 return -EINVAL;
6aa20a22 9661
bbe832c0 9662 if (netif_running(dev)) {
b02fd9e3 9663 tg3_phy_stop(tp);
1da177e4 9664 tg3_netif_stop(tp);
bbe832c0
MC		 9665 irq_sync = 1;
9666 }
1da177e4 9667
bbe832c0 9668 tg3_full_lock(tp, irq_sync);
6aa20a22 9669
1da177e4
LT		 9670 tp->rx_pending = ering->rx_pending;
9671
9672 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9673 tp->rx_pending > 63)
9674 tp->rx_pending = 63;
9675 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9676
9677 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9678 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9679
9680 if (netif_running(dev)) {
944d980e 9681 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9682 err = tg3_restart_hw(tp, 1);
9683 if (!err)
9684 tg3_netif_start(tp);
1da177e4
LT		 9685 }
9686
f47c11ee 9687 tg3_full_unlock(tp);
6aa20a22 9688
b02fd9e3
MC		 9689 if (irq_sync && !err)
9690 tg3_phy_start(tp);
9691
b9ec6c1b 9692 return err;
1da177e4 9693}
6aa20a22 9694
1da177e4
LT		 9695static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9696{
9697 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9698
1da177e4 9699 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9700
e18ce346 9701 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9702 epause->rx_pause = 1;
9703 else
9704 epause->rx_pause = 0;
9705
e18ce346 9706 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9707 epause->tx_pause = 1;
9708 else
9709 epause->tx_pause = 0;
1da177e4 9710}
6aa20a22 9711
1da177e4
LT		 9712static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9713{
9714 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9715 int err = 0;
6aa20a22 9716
b02fd9e3
MC		 9717 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9718 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9719 return -EAGAIN;
1da177e4 9720
b02fd9e3
MC		 9721 if (epause->autoneg) {
9722 u32 newadv;
9723 struct phy_device *phydev;
f47c11ee 9724
3f0e3ad7 9725 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9726
b02fd9e3
MC		 9727 if (epause->rx_pause) {
9728 if (epause->tx_pause)
9729 newadv = ADVERTISED_Pause;
9730 else
9731 newadv = ADVERTISED_Pause |
9732 ADVERTISED_Asym_Pause;
9733 } else if (epause->tx_pause) {
9734 newadv = ADVERTISED_Asym_Pause;
9735 } else
9736 newadv = 0;
9737
9738 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9739 u32 oldadv = phydev->advertising &
9740 (ADVERTISED_Pause |
9741 ADVERTISED_Asym_Pause);
9742 if (oldadv != newadv) {
9743 phydev->advertising &=
9744 ~(ADVERTISED_Pause |
9745 ADVERTISED_Asym_Pause);
9746 phydev->advertising |= newadv;
9747 err = phy_start_aneg(phydev);
9748 }
9749 } else {
9750 tp->link_config.advertising &=
9751 ~(ADVERTISED_Pause |
9752 ADVERTISED_Asym_Pause);
9753 tp->link_config.advertising |= newadv;
9754 }
9755 } else {
9756 if (epause->rx_pause)
e18ce346 9757 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9758 else
e18ce346 9759 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9760
b02fd9e3 9761 if (epause->tx_pause)
e18ce346 9762 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9763 else
e18ce346 9764 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9765
9766 if (netif_running(dev))
9767 tg3_setup_flow_control(tp, 0, 0);
9768 }
9769 } else {
9770 int irq_sync = 0;
9771
9772 if (netif_running(dev)) {
9773 tg3_netif_stop(tp);
9774 irq_sync = 1;
9775 }
9776
9777 tg3_full_lock(tp, irq_sync);
9778
9779 if (epause->autoneg)
9780 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9781 else
9782 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9783 if (epause->rx_pause)
e18ce346 9784 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9785 else
e18ce346 9786 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9787 if (epause->tx_pause)
e18ce346 9788 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9789 else
e18ce346 9790 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9791
9792 if (netif_running(dev)) {
9793 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9794 err = tg3_restart_hw(tp, 1);
9795 if (!err)
9796 tg3_netif_start(tp);
9797 }
9798
9799 tg3_full_unlock(tp);
9800 }
6aa20a22 9801
b9ec6c1b 9802 return err;
1da177e4 9803}
6aa20a22 9804
1da177e4
LT		 9805static u32 tg3_get_rx_csum(struct net_device *dev)
9806{
9807 struct tg3 *tp = netdev_priv(dev);
9808 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9809}
6aa20a22 9810
1da177e4
LT		 9811static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9812{
9813 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9814
1da177e4
LT		 9815 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9816 if (data != 0)
9817 return -EINVAL;
9818 return 0;
9819 }
6aa20a22 9820
f47c11ee 9821 spin_lock_bh(&tp->lock);
1da177e4
LT		 9822 if (data)
9823 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9824 else
9825 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9826 spin_unlock_bh(&tp->lock);
6aa20a22 9827
1da177e4
LT		 9828 return 0;
9829}
6aa20a22 9830
1da177e4
LT		 9831static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9832{
9833 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9834
1da177e4
LT		 9835 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9836 if (data != 0)
9837 return -EINVAL;
9838 return 0;
9839 }
6aa20a22 9840
321d32a0 9841 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9842 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9843 else
9c27dbdf 9844 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9845
9846 return 0;
9847}
9848
b9f2c044 9849static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9850{
b9f2c044
JG		 9851 switch (sset) {
9852 case ETH_SS_TEST:
9853 return TG3_NUM_TEST;
9854 case ETH_SS_STATS:
9855 return TG3_NUM_STATS;
9856 default:
9857 return -EOPNOTSUPP;
9858 }
4cafd3f5
MC		 9859}
9860
1da177e4
LT		 9861static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9862{
9863 switch (stringset) {
9864 case ETH_SS_STATS:
9865 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9866 break;
4cafd3f5
MC		 9867 case ETH_SS_TEST:
9868 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9869 break;
1da177e4
LT		 9870 default:
9871 WARN_ON(1); /* we need a WARN() */
9872 break;
9873 }
9874}
9875
4009a93d
MC		 9876static int tg3_phys_id(struct net_device *dev, u32 data)
9877{
9878 struct tg3 *tp = netdev_priv(dev);
9879 int i;
9880
9881 if (!netif_running(tp->dev))
9882 return -EAGAIN;
9883
9884 if (data == 0)
759afc31 9885 data = UINT_MAX / 2;
4009a93d
MC		 9886
9887 for (i = 0; i < (data * 2); i++) {
9888 if ((i % 2) == 0)
9889 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9890 LED_CTRL_1000MBPS_ON |
9891 LED_CTRL_100MBPS_ON |
9892 LED_CTRL_10MBPS_ON |
9893 LED_CTRL_TRAFFIC_OVERRIDE |
9894 LED_CTRL_TRAFFIC_BLINK |
9895 LED_CTRL_TRAFFIC_LED);
6aa20a22 9896
4009a93d
MC		 9897 else
9898 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9899 LED_CTRL_TRAFFIC_OVERRIDE);
9900
9901 if (msleep_interruptible(500))
9902 break;
9903 }
9904 tw32(MAC_LED_CTRL, tp->led_ctrl);
9905 return 0;
9906}
9907
1da177e4
LT		 9908static void tg3_get_ethtool_stats (struct net_device *dev,
9909 struct ethtool_stats *estats, u64 *tmp_stats)
9910{
9911 struct tg3 *tp = netdev_priv(dev);
9912 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9913}
9914
566f86ad 9915#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9916#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9917#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9918#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9919#define NVRAM_SELFBOOT_HW_SIZE 0x20
9920#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9921
9922static int tg3_test_nvram(struct tg3 *tp)
9923{
b9fc7dc5 9924 u32 csum, magic;
a9dc529d 9925 __be32 *buf;
ab0049b4 9926 int i, j, k, err = 0, size;
566f86ad 9927
df259d8c
MC		 9928 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9929 return 0;
9930
e4f34110 9931 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9932 return -EIO;
9933
1b27777a
MC		 9934 if (magic == TG3_EEPROM_MAGIC)
9935 size = NVRAM_TEST_SIZE;
b16250e3 9936 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9937 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9938 TG3_EEPROM_SB_FORMAT_1) {
9939 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9940 case TG3_EEPROM_SB_REVISION_0:
9941 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9942 break;
9943 case TG3_EEPROM_SB_REVISION_2:
9944 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9945 break;
9946 case TG3_EEPROM_SB_REVISION_3:
9947 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9948 break;
9949 default:
9950 return 0;
9951 }
9952 } else
1b27777a 9953 return 0;
b16250e3
MC		 9954 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9955 size = NVRAM_SELFBOOT_HW_SIZE;
9956 else
1b27777a
MC		 9957 return -EIO;
9958
9959 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9960 if (buf == NULL)
9961 return -ENOMEM;
9962
1b27777a
MC		 9963 err = -EIO;
9964 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9965 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9966 if (err)
566f86ad 9967 break;
566f86ad 9968 }
1b27777a 9969 if (i < size)
566f86ad
MC		 9970 goto out;
9971
1b27777a 9972 /* Selfboot format */
a9dc529d 9973 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9974 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9975 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9976 u8 *buf8 = (u8 *) buf, csum8 = 0;
9977
b9fc7dc5 9978 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9979 TG3_EEPROM_SB_REVISION_2) {
9980 /* For rev 2, the csum doesn't include the MBA. */
9981 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9982 csum8 += buf8[i];
9983 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9984 csum8 += buf8[i];
9985 } else {
9986 for (i = 0; i < size; i++)
9987 csum8 += buf8[i];
9988 }
1b27777a 9989
ad96b485
AB		 9990 if (csum8 == 0) {
9991 err = 0;
9992 goto out;
9993 }
9994
9995 err = -EIO;
9996 goto out;
1b27777a 9997 }
566f86ad 9998
b9fc7dc5 9999 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10000 TG3_EEPROM_MAGIC_HW) {
10001 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10002 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10003 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10004
10005 /* Separate the parity bits and the data bytes. */
10006 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10007 if ((i == 0) || (i == 8)) {
10008 int l;
10009 u8 msk;
10010
10011 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10012 parity[k++] = buf8[i] & msk;
10013 i++;
10014 }
10015 else if (i == 16) {
10016 int l;
10017 u8 msk;
10018
10019 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10020 parity[k++] = buf8[i] & msk;
10021 i++;
10022
10023 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10024 parity[k++] = buf8[i] & msk;
10025 i++;
10026 }
10027 data[j++] = buf8[i];
10028 }
10029
10030 err = -EIO;
10031 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10032 u8 hw8 = hweight8(data[i]);
10033
10034 if ((hw8 & 0x1) && parity[i])
10035 goto out;
10036 else if (!(hw8 & 0x1) && !parity[i])
10037 goto out;
10038 }
10039 err = 0;
10040 goto out;
10041 }
10042
566f86ad
MC		 10043 /* Bootstrap checksum at offset 0x10 */
10044 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10045 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10046 goto out;
10047
10048 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10049 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10050 if (csum != be32_to_cpu(buf[0xfc/4]))
10051 goto out;
566f86ad
MC		 10052
10053 err = 0;
10054
10055out:
10056 kfree(buf);
10057 return err;
10058}
10059
ca43007a
MC		 10060#define TG3_SERDES_TIMEOUT_SEC 2
10061#define TG3_COPPER_TIMEOUT_SEC 6
10062
10063static int tg3_test_link(struct tg3 *tp)
10064{
10065 int i, max;
10066
10067 if (!netif_running(tp->dev))
10068 return -ENODEV;
10069
4c987487 10070 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10071 max = TG3_SERDES_TIMEOUT_SEC;
10072 else
10073 max = TG3_COPPER_TIMEOUT_SEC;
10074
10075 for (i = 0; i < max; i++) {
10076 if (netif_carrier_ok(tp->dev))
10077 return 0;
10078
10079 if (msleep_interruptible(1000))
10080 break;
10081 }
10082
10083 return -EIO;
10084}
10085
a71116d1 10086/* Only test the commonly used registers */
30ca3e37 10087static int tg3_test_registers(struct tg3 *tp)
a71116d1 10088{
b16250e3 10089 int i, is_5705, is_5750;
a71116d1
MC		 10090 u32 offset, read_mask, write_mask, val, save_val, read_val;
10091 static struct {
10092 u16 offset;
10093 u16 flags;
10094#define TG3_FL_5705 0x1
10095#define TG3_FL_NOT_5705 0x2
10096#define TG3_FL_NOT_5788 0x4
b16250e3 10097#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10098 u32 read_mask;
10099 u32 write_mask;
10100 } reg_tbl[] = {
10101 /* MAC Control Registers */
10102 { MAC_MODE, TG3_FL_NOT_5705,
10103 0x00000000, 0x00ef6f8c },
10104 { MAC_MODE, TG3_FL_5705,
10105 0x00000000, 0x01ef6b8c },
10106 { MAC_STATUS, TG3_FL_NOT_5705,
10107 0x03800107, 0x00000000 },
10108 { MAC_STATUS, TG3_FL_5705,
10109 0x03800100, 0x00000000 },
10110 { MAC_ADDR_0_HIGH, 0x0000,
10111 0x00000000, 0x0000ffff },
10112 { MAC_ADDR_0_LOW, 0x0000,
10113 0x00000000, 0xffffffff },
10114 { MAC_RX_MTU_SIZE, 0x0000,
10115 0x00000000, 0x0000ffff },
10116 { MAC_TX_MODE, 0x0000,
10117 0x00000000, 0x00000070 },
10118 { MAC_TX_LENGTHS, 0x0000,
10119 0x00000000, 0x00003fff },
10120 { MAC_RX_MODE, TG3_FL_NOT_5705,
10121 0x00000000, 0x000007fc },
10122 { MAC_RX_MODE, TG3_FL_5705,
10123 0x00000000, 0x000007dc },
10124 { MAC_HASH_REG_0, 0x0000,
10125 0x00000000, 0xffffffff },
10126 { MAC_HASH_REG_1, 0x0000,
10127 0x00000000, 0xffffffff },
10128 { MAC_HASH_REG_2, 0x0000,
10129 0x00000000, 0xffffffff },
10130 { MAC_HASH_REG_3, 0x0000,
10131 0x00000000, 0xffffffff },
10132
10133 /* Receive Data and Receive BD Initiator Control Registers. */
10134 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10135 0x00000000, 0xffffffff },
10136 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10137 0x00000000, 0xffffffff },
10138 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10139 0x00000000, 0x00000003 },
10140 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10141 0x00000000, 0xffffffff },
10142 { RCVDBDI_STD_BD+0, 0x0000,
10143 0x00000000, 0xffffffff },
10144 { RCVDBDI_STD_BD+4, 0x0000,
10145 0x00000000, 0xffffffff },
10146 { RCVDBDI_STD_BD+8, 0x0000,
10147 0x00000000, 0xffff0002 },
10148 { RCVDBDI_STD_BD+0xc, 0x0000,
10149 0x00000000, 0xffffffff },
6aa20a22 10150
a71116d1
MC		 10151 /* Receive BD Initiator Control Registers. */
10152 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10153 0x00000000, 0xffffffff },
10154 { RCVBDI_STD_THRESH, TG3_FL_5705,
10155 0x00000000, 0x000003ff },
10156 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10157 0x00000000, 0xffffffff },
6aa20a22 10158
a71116d1
MC		 10159 /* Host Coalescing Control Registers. */
10160 { HOSTCC_MODE, TG3_FL_NOT_5705,
10161 0x00000000, 0x00000004 },
10162 { HOSTCC_MODE, TG3_FL_5705,
10163 0x00000000, 0x000000f6 },
10164 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10165 0x00000000, 0xffffffff },
10166 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10167 0x00000000, 0x000003ff },
10168 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10169 0x00000000, 0xffffffff },
10170 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10171 0x00000000, 0x000003ff },
10172 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10173 0x00000000, 0xffffffff },
10174 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10175 0x00000000, 0x000000ff },
10176 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10177 0x00000000, 0xffffffff },
10178 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10179 0x00000000, 0x000000ff },
10180 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10181 0x00000000, 0xffffffff },
10182 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10183 0x00000000, 0xffffffff },
10184 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10185 0x00000000, 0xffffffff },
10186 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10187 0x00000000, 0x000000ff },
10188 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10189 0x00000000, 0xffffffff },
10190 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10191 0x00000000, 0x000000ff },
10192 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10193 0x00000000, 0xffffffff },
10194 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10195 0x00000000, 0xffffffff },
10196 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10197 0x00000000, 0xffffffff },
10198 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10199 0x00000000, 0xffffffff },
10200 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10201 0x00000000, 0xffffffff },
10202 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10203 0xffffffff, 0x00000000 },
10204 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10205 0xffffffff, 0x00000000 },
10206
10207 /* Buffer Manager Control Registers. */
b16250e3 10208 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10209 0x00000000, 0x007fff80 },
b16250e3 10210 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10211 0x00000000, 0x007fffff },
10212 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10213 0x00000000, 0x0000003f },
10214 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10215 0x00000000, 0x000001ff },
10216 { BUFMGR_MB_HIGH_WATER, 0x0000,
10217 0x00000000, 0x000001ff },
10218 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10219 0xffffffff, 0x00000000 },
10220 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10221 0xffffffff, 0x00000000 },
6aa20a22 10222
a71116d1
MC		 10223 /* Mailbox Registers */
10224 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10225 0x00000000, 0x000001ff },
10226 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10227 0x00000000, 0x000001ff },
10228 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10229 0x00000000, 0x000007ff },
10230 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10231 0x00000000, 0x000001ff },
10232
10233 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10234 };
10235
b16250e3
MC		 10236 is_5705 = is_5750 = 0;
10237 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10238 is_5705 = 1;
b16250e3
MC		 10239 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10240 is_5750 = 1;
10241 }
a71116d1
MC		 10242
10243 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10244 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10245 continue;
10246
10247 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10248 continue;
10249
10250 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10251 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10252 continue;
10253
b16250e3
MC		 10254 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10255 continue;
10256
a71116d1
MC		 10257 offset = (u32) reg_tbl[i].offset;
10258 read_mask = reg_tbl[i].read_mask;
10259 write_mask = reg_tbl[i].write_mask;
10260
10261 /* Save the original register content */
10262 save_val = tr32(offset);
10263
10264 /* Determine the read-only value. */
10265 read_val = save_val & read_mask;
10266
10267 /* Write zero to the register, then make sure the read-only bits
10268 * are not changed and the read/write bits are all zeros.
10269 */
10270 tw32(offset, 0);
10271
10272 val = tr32(offset);
10273
10274 /* Test the read-only and read/write bits. */
10275 if (((val & read_mask) != read_val) || (val & write_mask))
10276 goto out;
10277
10278 /* Write ones to all the bits defined by RdMask and WrMask, then
10279 * make sure the read-only bits are not changed and the
10280 * read/write bits are all ones.
10281 */
10282 tw32(offset, read_mask | write_mask);
10283
10284 val = tr32(offset);
10285
10286 /* Test the read-only bits. */
10287 if ((val & read_mask) != read_val)
10288 goto out;
10289
10290 /* Test the read/write bits. */
10291 if ((val & write_mask) != write_mask)
10292 goto out;
10293
10294 tw32(offset, save_val);
10295 }
10296
10297 return 0;
10298
10299out:
9f88f29f
MC		 10300 if (netif_msg_hw(tp))
10301 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10302 offset);
a71116d1
MC		 10303 tw32(offset, save_val);
10304 return -EIO;
10305}
10306
7942e1db
MC		 10307static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10308{
f71e1309 10309 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10310 int i;
10311 u32 j;
10312
e9edda69 10313 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10314 for (j = 0; j < len; j += 4) {
10315 u32 val;
10316
10317 tg3_write_mem(tp, offset + j, test_pattern[i]);
10318 tg3_read_mem(tp, offset + j, &val);
10319 if (val != test_pattern[i])
10320 return -EIO;
10321 }
10322 }
10323 return 0;
10324}
10325
10326static int tg3_test_memory(struct tg3 *tp)
10327{
10328 static struct mem_entry {
10329 u32 offset;
10330 u32 len;
10331 } mem_tbl_570x[] = {
38690194 10332 { 0x00000000, 0x00b50},
7942e1db
MC		 10333 { 0x00002000, 0x1c000},
10334 { 0xffffffff, 0x00000}
10335 }, mem_tbl_5705[] = {
10336 { 0x00000100, 0x0000c},
10337 { 0x00000200, 0x00008},
7942e1db
MC		 10338 { 0x00004000, 0x00800},
10339 { 0x00006000, 0x01000},
10340 { 0x00008000, 0x02000},
10341 { 0x00010000, 0x0e000},
10342 { 0xffffffff, 0x00000}
79f4d13a
MC		 10343 }, mem_tbl_5755[] = {
10344 { 0x00000200, 0x00008},
10345 { 0x00004000, 0x00800},
10346 { 0x00006000, 0x00800},
10347 { 0x00008000, 0x02000},
10348 { 0x00010000, 0x0c000},
10349 { 0xffffffff, 0x00000}
b16250e3
MC		 10350 }, mem_tbl_5906[] = {
10351 { 0x00000200, 0x00008},
10352 { 0x00004000, 0x00400},
10353 { 0x00006000, 0x00400},
10354 { 0x00008000, 0x01000},
10355 { 0x00010000, 0x01000},
10356 { 0xffffffff, 0x00000}
7942e1db
MC		 10357 };
10358 struct mem_entry *mem_tbl;
10359 int err = 0;
10360 int i;
10361
321d32a0
MC		 10362 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10363 mem_tbl = mem_tbl_5755;
10364 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10365 mem_tbl = mem_tbl_5906;
10366 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10367 mem_tbl = mem_tbl_5705;
10368 else
7942e1db
MC		 10369 mem_tbl = mem_tbl_570x;
10370
10371 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10372 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10373 mem_tbl[i].len)) != 0)
10374 break;
10375 }
6aa20a22 10376
7942e1db
MC		 10377 return err;
10378}
10379
9f40dead
MC		 10380#define TG3_MAC_LOOPBACK 0
10381#define TG3_PHY_LOOPBACK 1
10382
10383static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10384{
9f40dead 10385 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10386 u32 desc_idx, coal_now;
c76949a6
MC		 10387 struct sk_buff *skb, *rx_skb;
10388 u8 *tx_data;
10389 dma_addr_t map;
10390 int num_pkts, tx_len, rx_len, i, err;
10391 struct tg3_rx_buffer_desc *desc;
898a56f8 10392 struct tg3_napi *tnapi, *rnapi;
21f581a5 10393 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10394
0c1d0e2b
MC		 10395 if (tp->irq_cnt > 1) {
10396 tnapi = &tp->napi[1];
10397 rnapi = &tp->napi[1];
10398 } else {
10399 tnapi = &tp->napi[0];
10400 rnapi = &tp->napi[0];
10401 }
fd2ce37f 10402 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10403
9f40dead 10404 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10405 /* HW errata - mac loopback fails in some cases on 5780.
10406 * Normal traffic and PHY loopback are not affected by
10407 * errata.
10408 */
10409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10410 return 0;
10411
9f40dead 10412 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10413 MAC_MODE_PORT_INT_LPBACK;
10414 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10415 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10416 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10417 mac_mode |= MAC_MODE_PORT_MODE_MII;
10418 else
10419 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10420 tw32(MAC_MODE, mac_mode);
10421 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10422 u32 val;
10423
7f97a4bd
MC		 10424 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10425 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10426 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10427 } else
10428 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10429
9ef8ca99
MC		 10430 tg3_phy_toggle_automdix(tp, 0);
10431
3f7045c1 10432 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10433 udelay(40);
5d64ad34 10434
e8f3f6ca 10435 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10436 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10438 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10439 mac_mode |= MAC_MODE_PORT_MODE_MII;
10440 } else
10441 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10442
c94e3941
MC		 10443 /* reset to prevent losing 1st rx packet intermittently */
10444 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10445 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10446 udelay(10);
10447 tw32_f(MAC_RX_MODE, tp->rx_mode);
10448 }
e8f3f6ca
MC		 10449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10450 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10451 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10452 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10453 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10454 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10455 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10456 }
9f40dead 10457 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10458 }
10459 else
10460 return -EINVAL;
c76949a6
MC		 10461
10462 err = -EIO;
10463
c76949a6 10464 tx_len = 1514;
a20e9c62 10465 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10466 if (!skb)
10467 return -ENOMEM;
10468
c76949a6
MC		 10469 tx_data = skb_put(skb, tx_len);
10470 memcpy(tx_data, tp->dev->dev_addr, 6);
10471 memset(tx_data + 6, 0x0, 8);
10472
10473 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10474
10475 for (i = 14; i < tx_len; i++)
10476 tx_data[i] = (u8) (i & 0xff);
10477
a21771dd
MC		 10478 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10479 dev_kfree_skb(skb);
10480 return -EIO;
10481 }
c76949a6
MC		 10482
10483 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10484 rnapi->coal_now);
c76949a6
MC		 10485
10486 udelay(10);
10487
898a56f8 10488 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10489
c76949a6
MC		 10490 num_pkts = 0;
10491
a21771dd
MC		 10492 tg3_set_txd(tnapi, tnapi->tx_prod,
10493 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10494
f3f3f27e 10495 tnapi->tx_prod++;
c76949a6
MC		 10496 num_pkts++;
10497
f3f3f27e
MC		 10498 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10499 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10500
10501 udelay(10);
10502
303fc921
MC		 10503 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10504 for (i = 0; i < 35; i++) {
c76949a6 10505 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10506 coal_now);
c76949a6
MC		 10507
10508 udelay(10);
10509
898a56f8
MC		 10510 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10511 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10512 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10513 (rx_idx == (rx_start_idx + num_pkts)))
10514 break;
10515 }
10516
a21771dd 10517 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10518 dev_kfree_skb(skb);
10519
f3f3f27e 10520 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10521 goto out;
10522
10523 if (rx_idx != rx_start_idx + num_pkts)
10524 goto out;
10525
72334482 10526 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10527 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10528 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10529 if (opaque_key != RXD_OPAQUE_RING_STD)
10530 goto out;
10531
10532 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10533 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10534 goto out;
10535
10536 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10537 if (rx_len != tx_len)
10538 goto out;
10539
21f581a5 10540 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10541
21f581a5 10542 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10543 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10544
10545 for (i = 14; i < tx_len; i++) {
10546 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10547 goto out;
10548 }
10549 err = 0;
6aa20a22 10550
c76949a6
MC		 10551 /* tg3_free_rings will unmap and free the rx_skb */
10552out:
10553 return err;
10554}
10555
9f40dead
MC		 10556#define TG3_MAC_LOOPBACK_FAILED 1
10557#define TG3_PHY_LOOPBACK_FAILED 2
10558#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10559 TG3_PHY_LOOPBACK_FAILED)
10560
10561static int tg3_test_loopback(struct tg3 *tp)
10562{
10563 int err = 0;
9936bcf6 10564 u32 cpmuctrl = 0;
9f40dead
MC		 10565
10566 if (!netif_running(tp->dev))
10567 return TG3_LOOPBACK_FAILED;
10568
b9ec6c1b
MC		 10569 err = tg3_reset_hw(tp, 1);
10570 if (err)
10571 return TG3_LOOPBACK_FAILED;
9f40dead 10572
6833c043
MC		 10573 /* Turn off gphy autopowerdown. */
10574 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10575 tg3_phy_toggle_apd(tp, false);
10576
321d32a0 10577 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10578 int i;
10579 u32 status;
10580
10581 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10582
10583 /* Wait for up to 40 microseconds to acquire lock. */
10584 for (i = 0; i < 4; i++) {
10585 status = tr32(TG3_CPMU_MUTEX_GNT);
10586 if (status == CPMU_MUTEX_GNT_DRIVER)
10587 break;
10588 udelay(10);
10589 }
10590
10591 if (status != CPMU_MUTEX_GNT_DRIVER)
10592 return TG3_LOOPBACK_FAILED;
10593
b2a5c19c 10594 /* Turn off link-based power management. */
e875093c 10595 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10596 tw32(TG3_CPMU_CTRL,
10597 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10598 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10599 }
10600
9f40dead
MC		 10601 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10602 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10603
321d32a0 10604 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10605 tw32(TG3_CPMU_CTRL, cpmuctrl);
10606
10607 /* Release the mutex */
10608 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10609 }
10610
dd477003
MC		 10611 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10612 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10613 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10614 err |= TG3_PHY_LOOPBACK_FAILED;
10615 }
10616
6833c043
MC		 10617 /* Re-enable gphy autopowerdown. */
10618 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10619 tg3_phy_toggle_apd(tp, true);
10620
9f40dead
MC		 10621 return err;
10622}
10623
4cafd3f5
MC		 10624static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10625 u64 *data)
10626{
566f86ad
MC		 10627 struct tg3 *tp = netdev_priv(dev);
10628
bc1c7567
MC		 10629 if (tp->link_config.phy_is_low_power)
10630 tg3_set_power_state(tp, PCI_D0);
10631
566f86ad
MC		 10632 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10633
10634 if (tg3_test_nvram(tp) != 0) {
10635 etest->flags |= ETH_TEST_FL_FAILED;
10636 data[0] = 1;
10637 }
ca43007a
MC		 10638 if (tg3_test_link(tp) != 0) {
10639 etest->flags |= ETH_TEST_FL_FAILED;
10640 data[1] = 1;
10641 }
a71116d1 10642 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10643 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10644
10645 if (netif_running(dev)) {
b02fd9e3 10646 tg3_phy_stop(tp);
a71116d1 10647 tg3_netif_stop(tp);
bbe832c0
MC		 10648 irq_sync = 1;
10649 }
a71116d1 10650
bbe832c0 10651 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10652
10653 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10654 err = tg3_nvram_lock(tp);
a71116d1
MC		 10655 tg3_halt_cpu(tp, RX_CPU_BASE);
10656 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10657 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10658 if (!err)
10659 tg3_nvram_unlock(tp);
a71116d1 10660
d9ab5ad1
MC		 10661 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10662 tg3_phy_reset(tp);
10663
a71116d1
MC		 10664 if (tg3_test_registers(tp) != 0) {
10665 etest->flags |= ETH_TEST_FL_FAILED;
10666 data[2] = 1;
10667 }
7942e1db
MC		 10668 if (tg3_test_memory(tp) != 0) {
10669 etest->flags |= ETH_TEST_FL_FAILED;
10670 data[3] = 1;
10671 }
9f40dead 10672 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10673 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10674
f47c11ee
DM		 10675 tg3_full_unlock(tp);
10676
d4bc3927
MC		 10677 if (tg3_test_interrupt(tp) != 0) {
10678 etest->flags |= ETH_TEST_FL_FAILED;
10679 data[5] = 1;
10680 }
f47c11ee
DM		 10681
10682 tg3_full_lock(tp, 0);
d4bc3927 10683
a71116d1
MC		 10684 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10685 if (netif_running(dev)) {
10686 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10687 err2 = tg3_restart_hw(tp, 1);
10688 if (!err2)
b9ec6c1b 10689 tg3_netif_start(tp);
a71116d1 10690 }
f47c11ee
DM		 10691
10692 tg3_full_unlock(tp);
b02fd9e3
MC		 10693
10694 if (irq_sync && !err2)
10695 tg3_phy_start(tp);
a71116d1 10696 }
bc1c7567
MC		 10697 if (tp->link_config.phy_is_low_power)
10698 tg3_set_power_state(tp, PCI_D3hot);
10699
4cafd3f5
MC		 10700}
10701
1da177e4
LT		 10702static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10703{
10704 struct mii_ioctl_data *data = if_mii(ifr);
10705 struct tg3 *tp = netdev_priv(dev);
10706 int err;
10707
b02fd9e3 10708 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10709 struct phy_device *phydev;
b02fd9e3
MC		 10710 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10711 return -EAGAIN;
3f0e3ad7
MC		 10712 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10713 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10714 }
10715
1da177e4
LT		 10716 switch(cmd) {
10717 case SIOCGMIIPHY:
882e9793 10718 data->phy_id = tp->phy_addr;
1da177e4
LT		 10719
10720 /* fallthru */
10721 case SIOCGMIIREG: {
10722 u32 mii_regval;
10723
10724 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10725 break; /* We have no PHY */
10726
bc1c7567
MC		 10727 if (tp->link_config.phy_is_low_power)
10728 return -EAGAIN;
10729
f47c11ee 10730 spin_lock_bh(&tp->lock);
1da177e4 10731 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10732 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10733
10734 data->val_out = mii_regval;
10735
10736 return err;
10737 }
10738
10739 case SIOCSMIIREG:
10740 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10741 break; /* We have no PHY */
10742
bc1c7567
MC		 10743 if (tp->link_config.phy_is_low_power)
10744 return -EAGAIN;
10745
f47c11ee 10746 spin_lock_bh(&tp->lock);
1da177e4 10747 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10748 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10749
10750 return err;
10751
10752 default:
10753 /* do nothing */
10754 break;
10755 }
10756 return -EOPNOTSUPP;
10757}
10758
10759#if TG3_VLAN_TAG_USED
10760static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10761{
10762 struct tg3 *tp = netdev_priv(dev);
10763
844b3eed
MC		 10764 if (!netif_running(dev)) {
10765 tp->vlgrp = grp;
10766 return;
10767 }
10768
10769 tg3_netif_stop(tp);
29315e87 10770
f47c11ee 10771 tg3_full_lock(tp, 0);
1da177e4
LT		 10772
10773 tp->vlgrp = grp;
10774
10775 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10776 __tg3_set_rx_mode(dev);
10777
844b3eed 10778 tg3_netif_start(tp);
46966545
MC		 10779
10780 tg3_full_unlock(tp);
1da177e4 10781}
1da177e4
LT		 10782#endif
10783
15f9850d
DM		 10784static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10785{
10786 struct tg3 *tp = netdev_priv(dev);
10787
10788 memcpy(ec, &tp->coal, sizeof(*ec));
10789 return 0;
10790}
10791
d244c892
MC		 10792static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10793{
10794 struct tg3 *tp = netdev_priv(dev);
10795 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10796 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10797
10798 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10799 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10800 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10801 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10802 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10803 }
10804
10805 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10806 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10807 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10808 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10809 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10810 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10811 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10812 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10813 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10814 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10815 return -EINVAL;
10816
10817 /* No rx interrupts will be generated if both are zero */
10818 if ((ec->rx_coalesce_usecs == 0) &&
10819 (ec->rx_max_coalesced_frames == 0))
10820 return -EINVAL;
10821
10822 /* No tx interrupts will be generated if both are zero */
10823 if ((ec->tx_coalesce_usecs == 0) &&
10824 (ec->tx_max_coalesced_frames == 0))
10825 return -EINVAL;
10826
10827 /* Only copy relevant parameters, ignore all others. */
10828 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10829 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10830 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10831 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10832 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10833 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10834 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10835 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10836 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10837
10838 if (netif_running(dev)) {
10839 tg3_full_lock(tp, 0);
10840 __tg3_set_coalesce(tp, &tp->coal);
10841 tg3_full_unlock(tp);
10842 }
10843 return 0;
10844}
10845
7282d491 10846static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10847 .get_settings = tg3_get_settings,
10848 .set_settings = tg3_set_settings,
10849 .get_drvinfo = tg3_get_drvinfo,
10850 .get_regs_len = tg3_get_regs_len,
10851 .get_regs = tg3_get_regs,
10852 .get_wol = tg3_get_wol,
10853 .set_wol = tg3_set_wol,
10854 .get_msglevel = tg3_get_msglevel,
10855 .set_msglevel = tg3_set_msglevel,
10856 .nway_reset = tg3_nway_reset,
10857 .get_link = ethtool_op_get_link,
10858 .get_eeprom_len = tg3_get_eeprom_len,
10859 .get_eeprom = tg3_get_eeprom,
10860 .set_eeprom = tg3_set_eeprom,
10861 .get_ringparam = tg3_get_ringparam,
10862 .set_ringparam = tg3_set_ringparam,
10863 .get_pauseparam = tg3_get_pauseparam,
10864 .set_pauseparam = tg3_set_pauseparam,
10865 .get_rx_csum = tg3_get_rx_csum,
10866 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10867 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10868 .set_sg = ethtool_op_set_sg,
1da177e4 10869 .set_tso = tg3_set_tso,
4cafd3f5 10870 .self_test = tg3_self_test,
1da177e4 10871 .get_strings = tg3_get_strings,
4009a93d 10872 .phys_id = tg3_phys_id,
1da177e4 10873 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10874 .get_coalesce = tg3_get_coalesce,
d244c892 10875 .set_coalesce = tg3_set_coalesce,
b9f2c044 10876 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10877};
10878
10879static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10880{
1b27777a 10881 u32 cursize, val, magic;
1da177e4
LT		 10882
10883 tp->nvram_size = EEPROM_CHIP_SIZE;
10884
e4f34110 10885 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10886 return;
10887
b16250e3
MC		 10888 if ((magic != TG3_EEPROM_MAGIC) &&
10889 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10890 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10891 return;
10892
10893 /*
10894 * Size the chip by reading offsets at increasing powers of two.
10895 * When we encounter our validation signature, we know the addressing
10896 * has wrapped around, and thus have our chip size.
10897 */
1b27777a 10898 cursize = 0x10;
1da177e4
LT		 10899
10900 while (cursize < tp->nvram_size) {
e4f34110 10901 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10902 return;
10903
1820180b 10904 if (val == magic)
1da177e4
LT		 10905 break;
10906
10907 cursize <<= 1;
10908 }
10909
10910 tp->nvram_size = cursize;
10911}
6aa20a22 10912
1da177e4
LT		 10913static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10914{
10915 u32 val;
10916
df259d8c
MC		 10917 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10918 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10919 return;
10920
10921 /* Selfboot format */
1820180b 10922 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10923 tg3_get_eeprom_size(tp);
10924 return;
10925 }
10926
6d348f2c 10927 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10928 if (val != 0) {
6d348f2c
MC		 10929 /* This is confusing. We want to operate on the
10930 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10931 * call will read from NVRAM and byteswap the data
10932 * according to the byteswapping settings for all
10933 * other register accesses. This ensures the data we
10934 * want will always reside in the lower 16-bits.
10935 * However, the data in NVRAM is in LE format, which
10936 * means the data from the NVRAM read will always be
10937 * opposite the endianness of the CPU. The 16-bit
10938 * byteswap then brings the data to CPU endianness.
10939 */
10940 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10941 return;
10942 }
10943 }
fd1122a2 10944 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10945}
10946
10947static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10948{
10949 u32 nvcfg1;
10950
10951 nvcfg1 = tr32(NVRAM_CFG1);
10952 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10953 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10954 } else {
1da177e4
LT		 10955 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10956 tw32(NVRAM_CFG1, nvcfg1);
10957 }
10958
4c987487 10959 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10960 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10961 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10962 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10963 tp->nvram_jedecnum = JEDEC_ATMEL;
10964 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10965 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10966 break;
10967 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10968 tp->nvram_jedecnum = JEDEC_ATMEL;
10969 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10970 break;
10971 case FLASH_VENDOR_ATMEL_EEPROM:
10972 tp->nvram_jedecnum = JEDEC_ATMEL;
10973 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10974 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10975 break;
10976 case FLASH_VENDOR_ST:
10977 tp->nvram_jedecnum = JEDEC_ST;
10978 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10979 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10980 break;
10981 case FLASH_VENDOR_SAIFUN:
10982 tp->nvram_jedecnum = JEDEC_SAIFUN;
10983 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10984 break;
10985 case FLASH_VENDOR_SST_SMALL:
10986 case FLASH_VENDOR_SST_LARGE:
10987 tp->nvram_jedecnum = JEDEC_SST;
10988 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10989 break;
1da177e4 10990 }
8590a603 10991 } else {
1da177e4
LT		 10992 tp->nvram_jedecnum = JEDEC_ATMEL;
10993 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10994 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10995 }
10996}
10997
a1b950d5
MC		 10998static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10999{
11000 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11001 case FLASH_5752PAGE_SIZE_256:
11002 tp->nvram_pagesize = 256;
11003 break;
11004 case FLASH_5752PAGE_SIZE_512:
11005 tp->nvram_pagesize = 512;
11006 break;
11007 case FLASH_5752PAGE_SIZE_1K:
11008 tp->nvram_pagesize = 1024;
11009 break;
11010 case FLASH_5752PAGE_SIZE_2K:
11011 tp->nvram_pagesize = 2048;
11012 break;
11013 case FLASH_5752PAGE_SIZE_4K:
11014 tp->nvram_pagesize = 4096;
11015 break;
11016 case FLASH_5752PAGE_SIZE_264:
11017 tp->nvram_pagesize = 264;
11018 break;
11019 case FLASH_5752PAGE_SIZE_528:
11020 tp->nvram_pagesize = 528;
11021 break;
11022 }
11023}
11024
361b4ac2
MC		 11025static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11026{
11027 u32 nvcfg1;
11028
11029 nvcfg1 = tr32(NVRAM_CFG1);
11030
e6af301b
MC		 11031 /* NVRAM protection for TPM */
11032 if (nvcfg1 & (1 << 27))
f66a29b0 11033 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11034
361b4ac2 11035 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11036 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11037 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11038 tp->nvram_jedecnum = JEDEC_ATMEL;
11039 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11040 break;
11041 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11042 tp->nvram_jedecnum = JEDEC_ATMEL;
11043 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11044 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11045 break;
11046 case FLASH_5752VENDOR_ST_M45PE10:
11047 case FLASH_5752VENDOR_ST_M45PE20:
11048 case FLASH_5752VENDOR_ST_M45PE40:
11049 tp->nvram_jedecnum = JEDEC_ST;
11050 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11051 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11052 break;
361b4ac2
MC		 11053 }
11054
11055 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11056 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11057 } else {
361b4ac2
MC		 11058 /* For eeprom, set pagesize to maximum eeprom size */
11059 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11060
11061 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11062 tw32(NVRAM_CFG1, nvcfg1);
11063 }
11064}
11065
d3c7b886
MC		 11066static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11067{
989a9d23 11068 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11069
11070 nvcfg1 = tr32(NVRAM_CFG1);
11071
11072 /* NVRAM protection for TPM */
989a9d23 11073 if (nvcfg1 & (1 << 27)) {
f66a29b0 11074 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11075 protect = 1;
11076 }
d3c7b886 11077
989a9d23
MC		 11078 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11079 switch (nvcfg1) {
8590a603
MC		 11080 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11081 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11082 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11083 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11084 tp->nvram_jedecnum = JEDEC_ATMEL;
11085 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11086 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11087 tp->nvram_pagesize = 264;
11088 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11089 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11090 tp->nvram_size = (protect ? 0x3e200 :
11091 TG3_NVRAM_SIZE_512KB);
11092 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11093 tp->nvram_size = (protect ? 0x1f200 :
11094 TG3_NVRAM_SIZE_256KB);
11095 else
11096 tp->nvram_size = (protect ? 0x1f200 :
11097 TG3_NVRAM_SIZE_128KB);
11098 break;
11099 case FLASH_5752VENDOR_ST_M45PE10:
11100 case FLASH_5752VENDOR_ST_M45PE20:
11101 case FLASH_5752VENDOR_ST_M45PE40:
11102 tp->nvram_jedecnum = JEDEC_ST;
11103 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11104 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11105 tp->nvram_pagesize = 256;
11106 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11107 tp->nvram_size = (protect ?
11108 TG3_NVRAM_SIZE_64KB :
11109 TG3_NVRAM_SIZE_128KB);
11110 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11111 tp->nvram_size = (protect ?
11112 TG3_NVRAM_SIZE_64KB :
11113 TG3_NVRAM_SIZE_256KB);
11114 else
11115 tp->nvram_size = (protect ?
11116 TG3_NVRAM_SIZE_128KB :
11117 TG3_NVRAM_SIZE_512KB);
11118 break;
d3c7b886
MC		 11119 }
11120}
11121
1b27777a
MC		 11122static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11123{
11124 u32 nvcfg1;
11125
11126 nvcfg1 = tr32(NVRAM_CFG1);
11127
11128 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11129 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11130 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11131 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11132 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11133 tp->nvram_jedecnum = JEDEC_ATMEL;
11134 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11135 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11136
8590a603
MC		 11137 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11138 tw32(NVRAM_CFG1, nvcfg1);
11139 break;
11140 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11141 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11142 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11143 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11144 tp->nvram_jedecnum = JEDEC_ATMEL;
11145 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11146 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11147 tp->nvram_pagesize = 264;
11148 break;
11149 case FLASH_5752VENDOR_ST_M45PE10:
11150 case FLASH_5752VENDOR_ST_M45PE20:
11151 case FLASH_5752VENDOR_ST_M45PE40:
11152 tp->nvram_jedecnum = JEDEC_ST;
11153 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11154 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11155 tp->nvram_pagesize = 256;
11156 break;
1b27777a
MC		 11157 }
11158}
11159
6b91fa02
MC		 11160static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11161{
11162 u32 nvcfg1, protect = 0;
11163
11164 nvcfg1 = tr32(NVRAM_CFG1);
11165
11166 /* NVRAM protection for TPM */
11167 if (nvcfg1 & (1 << 27)) {
f66a29b0 11168 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11169 protect = 1;
11170 }
11171
11172 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11173 switch (nvcfg1) {
8590a603
MC		 11174 case FLASH_5761VENDOR_ATMEL_ADB021D:
11175 case FLASH_5761VENDOR_ATMEL_ADB041D:
11176 case FLASH_5761VENDOR_ATMEL_ADB081D:
11177 case FLASH_5761VENDOR_ATMEL_ADB161D:
11178 case FLASH_5761VENDOR_ATMEL_MDB021D:
11179 case FLASH_5761VENDOR_ATMEL_MDB041D:
11180 case FLASH_5761VENDOR_ATMEL_MDB081D:
11181 case FLASH_5761VENDOR_ATMEL_MDB161D:
11182 tp->nvram_jedecnum = JEDEC_ATMEL;
11183 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11184 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11185 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11186 tp->nvram_pagesize = 256;
11187 break;
11188 case FLASH_5761VENDOR_ST_A_M45PE20:
11189 case FLASH_5761VENDOR_ST_A_M45PE40:
11190 case FLASH_5761VENDOR_ST_A_M45PE80:
11191 case FLASH_5761VENDOR_ST_A_M45PE16:
11192 case FLASH_5761VENDOR_ST_M_M45PE20:
11193 case FLASH_5761VENDOR_ST_M_M45PE40:
11194 case FLASH_5761VENDOR_ST_M_M45PE80:
11195 case FLASH_5761VENDOR_ST_M_M45PE16:
11196 tp->nvram_jedecnum = JEDEC_ST;
11197 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11198 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11199 tp->nvram_pagesize = 256;
11200 break;
6b91fa02
MC		 11201 }
11202
11203 if (protect) {
11204 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11205 } else {
11206 switch (nvcfg1) {
8590a603
MC		 11207 case FLASH_5761VENDOR_ATMEL_ADB161D:
11208 case FLASH_5761VENDOR_ATMEL_MDB161D:
11209 case FLASH_5761VENDOR_ST_A_M45PE16:
11210 case FLASH_5761VENDOR_ST_M_M45PE16:
11211 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11212 break;
11213 case FLASH_5761VENDOR_ATMEL_ADB081D:
11214 case FLASH_5761VENDOR_ATMEL_MDB081D:
11215 case FLASH_5761VENDOR_ST_A_M45PE80:
11216 case FLASH_5761VENDOR_ST_M_M45PE80:
11217 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11218 break;
11219 case FLASH_5761VENDOR_ATMEL_ADB041D:
11220 case FLASH_5761VENDOR_ATMEL_MDB041D:
11221 case FLASH_5761VENDOR_ST_A_M45PE40:
11222 case FLASH_5761VENDOR_ST_M_M45PE40:
11223 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11224 break;
11225 case FLASH_5761VENDOR_ATMEL_ADB021D:
11226 case FLASH_5761VENDOR_ATMEL_MDB021D:
11227 case FLASH_5761VENDOR_ST_A_M45PE20:
11228 case FLASH_5761VENDOR_ST_M_M45PE20:
11229 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11230 break;
6b91fa02
MC		 11231 }
11232 }
11233}
11234
b5d3772c
MC		 11235static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11236{
11237 tp->nvram_jedecnum = JEDEC_ATMEL;
11238 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11239 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11240}
11241
321d32a0
MC		 11242static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11243{
11244 u32 nvcfg1;
11245
11246 nvcfg1 = tr32(NVRAM_CFG1);
11247
11248 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11249 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11250 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11251 tp->nvram_jedecnum = JEDEC_ATMEL;
11252 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11253 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11254
11255 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11256 tw32(NVRAM_CFG1, nvcfg1);
11257 return;
11258 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11259 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11260 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11261 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11262 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11263 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11264 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11265 tp->nvram_jedecnum = JEDEC_ATMEL;
11266 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11267 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11268
11269 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11270 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11271 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11272 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11273 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11274 break;
11275 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11276 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11277 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11278 break;
11279 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11280 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11281 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11282 break;
11283 }
11284 break;
11285 case FLASH_5752VENDOR_ST_M45PE10:
11286 case FLASH_5752VENDOR_ST_M45PE20:
11287 case FLASH_5752VENDOR_ST_M45PE40:
11288 tp->nvram_jedecnum = JEDEC_ST;
11289 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11290 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11291
11292 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11293 case FLASH_5752VENDOR_ST_M45PE10:
11294 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11295 break;
11296 case FLASH_5752VENDOR_ST_M45PE20:
11297 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11298 break;
11299 case FLASH_5752VENDOR_ST_M45PE40:
11300 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11301 break;
11302 }
11303 break;
11304 default:
df259d8c 11305 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11306 return;
11307 }
11308
a1b950d5
MC		 11309 tg3_nvram_get_pagesize(tp, nvcfg1);
11310 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11311 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11312}
11313
11314
11315static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11316{
11317 u32 nvcfg1;
11318
11319 nvcfg1 = tr32(NVRAM_CFG1);
11320
11321 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11322 case FLASH_5717VENDOR_ATMEL_EEPROM:
11323 case FLASH_5717VENDOR_MICRO_EEPROM:
11324 tp->nvram_jedecnum = JEDEC_ATMEL;
11325 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11326 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11327
11328 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11329 tw32(NVRAM_CFG1, nvcfg1);
11330 return;
11331 case FLASH_5717VENDOR_ATMEL_MDB011D:
11332 case FLASH_5717VENDOR_ATMEL_ADB011B:
11333 case FLASH_5717VENDOR_ATMEL_ADB011D:
11334 case FLASH_5717VENDOR_ATMEL_MDB021D:
11335 case FLASH_5717VENDOR_ATMEL_ADB021B:
11336 case FLASH_5717VENDOR_ATMEL_ADB021D:
11337 case FLASH_5717VENDOR_ATMEL_45USPT:
11338 tp->nvram_jedecnum = JEDEC_ATMEL;
11339 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11340 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11341
11342 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11343 case FLASH_5717VENDOR_ATMEL_MDB021D:
11344 case FLASH_5717VENDOR_ATMEL_ADB021B:
11345 case FLASH_5717VENDOR_ATMEL_ADB021D:
11346 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11347 break;
11348 default:
11349 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11350 break;
11351 }
321d32a0 11352 break;
a1b950d5
MC		 11353 case FLASH_5717VENDOR_ST_M_M25PE10:
11354 case FLASH_5717VENDOR_ST_A_M25PE10:
11355 case FLASH_5717VENDOR_ST_M_M45PE10:
11356 case FLASH_5717VENDOR_ST_A_M45PE10:
11357 case FLASH_5717VENDOR_ST_M_M25PE20:
11358 case FLASH_5717VENDOR_ST_A_M25PE20:
11359 case FLASH_5717VENDOR_ST_M_M45PE20:
11360 case FLASH_5717VENDOR_ST_A_M45PE20:
11361 case FLASH_5717VENDOR_ST_25USPT:
11362 case FLASH_5717VENDOR_ST_45USPT:
11363 tp->nvram_jedecnum = JEDEC_ST;
11364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11366
11367 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11368 case FLASH_5717VENDOR_ST_M_M25PE20:
11369 case FLASH_5717VENDOR_ST_A_M25PE20:
11370 case FLASH_5717VENDOR_ST_M_M45PE20:
11371 case FLASH_5717VENDOR_ST_A_M45PE20:
11372 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11373 break;
11374 default:
11375 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11376 break;
11377 }
321d32a0 11378 break;
a1b950d5
MC		 11379 default:
11380 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11381 return;
321d32a0 11382 }
a1b950d5
MC		 11383
11384 tg3_nvram_get_pagesize(tp, nvcfg1);
11385 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11386 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11387}
11388
1da177e4
LT		 11389/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11390static void __devinit tg3_nvram_init(struct tg3 *tp)
11391{
1da177e4
LT		 11392 tw32_f(GRC_EEPROM_ADDR,
11393 (EEPROM_ADDR_FSM_RESET |
11394 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11395 EEPROM_ADDR_CLKPERD_SHIFT)));
11396
9d57f01c 11397 msleep(1);
1da177e4
LT		 11398
11399 /* Enable seeprom accesses. */
11400 tw32_f(GRC_LOCAL_CTRL,
11401 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11402 udelay(100);
11403
11404 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11405 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11406 tp->tg3_flags |= TG3_FLAG_NVRAM;
11407
ec41c7df
MC		 11408 if (tg3_nvram_lock(tp)) {
11409 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11410 "tg3_nvram_init failed.\n", tp->dev->name);
11411 return;
11412 }
e6af301b 11413 tg3_enable_nvram_access(tp);
1da177e4 11414
989a9d23
MC		 11415 tp->nvram_size = 0;
11416
361b4ac2
MC		 11417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11418 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11419 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11420 tg3_get_5755_nvram_info(tp);
d30cdd28 11421 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11423 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11424 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11425 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11426 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11427 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11428 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11429 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11430 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11431 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11432 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11433 else
11434 tg3_get_nvram_info(tp);
11435
989a9d23
MC		 11436 if (tp->nvram_size == 0)
11437 tg3_get_nvram_size(tp);
1da177e4 11438
e6af301b 11439 tg3_disable_nvram_access(tp);
381291b7 11440 tg3_nvram_unlock(tp);
1da177e4
LT		 11441
11442 } else {
11443 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11444
11445 tg3_get_eeprom_size(tp);
11446 }
11447}
11448
1da177e4
LT		 11449static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11450 u32 offset, u32 len, u8 *buf)
11451{
11452 int i, j, rc = 0;
11453 u32 val;
11454
11455 for (i = 0; i < len; i += 4) {
b9fc7dc5 11456 u32 addr;
a9dc529d 11457 __be32 data;
1da177e4
LT		 11458
11459 addr = offset + i;
11460
11461 memcpy(&data, buf + i, 4);
11462
62cedd11
MC		 11463 /*
11464 * The SEEPROM interface expects the data to always be opposite
11465 * the native endian format. We accomplish this by reversing
11466 * all the operations that would have been performed on the
11467 * data from a call to tg3_nvram_read_be32().
11468 */
11469 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11470
11471 val = tr32(GRC_EEPROM_ADDR);
11472 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11473
11474 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11475 EEPROM_ADDR_READ);
11476 tw32(GRC_EEPROM_ADDR, val |
11477 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11478 (addr & EEPROM_ADDR_ADDR_MASK) |
11479 EEPROM_ADDR_START |
11480 EEPROM_ADDR_WRITE);
6aa20a22 11481
9d57f01c 11482 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11483 val = tr32(GRC_EEPROM_ADDR);
11484
11485 if (val & EEPROM_ADDR_COMPLETE)
11486 break;
9d57f01c 11487 msleep(1);
1da177e4
LT		 11488 }
11489 if (!(val & EEPROM_ADDR_COMPLETE)) {
11490 rc = -EBUSY;
11491 break;
11492 }
11493 }
11494
11495 return rc;
11496}
11497
11498/* offset and length are dword aligned */
11499static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11500 u8 *buf)
11501{
11502 int ret = 0;
11503 u32 pagesize = tp->nvram_pagesize;
11504 u32 pagemask = pagesize - 1;
11505 u32 nvram_cmd;
11506 u8 *tmp;
11507
11508 tmp = kmalloc(pagesize, GFP_KERNEL);
11509 if (tmp == NULL)
11510 return -ENOMEM;
11511
11512 while (len) {
11513 int j;
e6af301b 11514 u32 phy_addr, page_off, size;
1da177e4
LT		 11515
11516 phy_addr = offset & ~pagemask;
6aa20a22 11517
1da177e4 11518 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11519 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11520 (__be32 *) (tmp + j));
11521 if (ret)
1da177e4
LT		 11522 break;
11523 }
11524 if (ret)
11525 break;
11526
11527 page_off = offset & pagemask;
11528 size = pagesize;
11529 if (len < size)
11530 size = len;
11531
11532 len -= size;
11533
11534 memcpy(tmp + page_off, buf, size);
11535
11536 offset = offset + (pagesize - page_off);
11537
e6af301b 11538 tg3_enable_nvram_access(tp);
1da177e4
LT		 11539
11540 /*
11541 * Before we can erase the flash page, we need
11542 * to issue a special "write enable" command.
11543 */
11544 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11545
11546 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11547 break;
11548
11549 /* Erase the target page */
11550 tw32(NVRAM_ADDR, phy_addr);
11551
11552 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11553 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11554
11555 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11556 break;
11557
11558 /* Issue another write enable to start the write. */
11559 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11560
11561 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11562 break;
11563
11564 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11565 __be32 data;
1da177e4 11566
b9fc7dc5 11567 data = *((__be32 *) (tmp + j));
a9dc529d 11568
b9fc7dc5 11569 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11570
11571 tw32(NVRAM_ADDR, phy_addr + j);
11572
11573 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11574 NVRAM_CMD_WR;
11575
11576 if (j == 0)
11577 nvram_cmd |= NVRAM_CMD_FIRST;
11578 else if (j == (pagesize - 4))
11579 nvram_cmd |= NVRAM_CMD_LAST;
11580
11581 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11582 break;
11583 }
11584 if (ret)
11585 break;
11586 }
11587
11588 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11589 tg3_nvram_exec_cmd(tp, nvram_cmd);
11590
11591 kfree(tmp);
11592
11593 return ret;
11594}
11595
11596/* offset and length are dword aligned */
11597static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11598 u8 *buf)
11599{
11600 int i, ret = 0;
11601
11602 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11603 u32 page_off, phy_addr, nvram_cmd;
11604 __be32 data;
1da177e4
LT		 11605
11606 memcpy(&data, buf + i, 4);
b9fc7dc5 11607 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11608
11609 page_off = offset % tp->nvram_pagesize;
11610
1820180b 11611 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11612
11613 tw32(NVRAM_ADDR, phy_addr);
11614
11615 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11616
11617 if ((page_off == 0) || (i == 0))
11618 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11619 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11620 nvram_cmd |= NVRAM_CMD_LAST;
11621
11622 if (i == (len - 4))
11623 nvram_cmd |= NVRAM_CMD_LAST;
11624
321d32a0
MC		 11625 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11626 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11627 (tp->nvram_jedecnum == JEDEC_ST) &&
11628 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11629
11630 if ((ret = tg3_nvram_exec_cmd(tp,
11631 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11632 NVRAM_CMD_DONE)))
11633
11634 break;
11635 }
11636 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11637 /* We always do complete word writes to eeprom. */
11638 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11639 }
11640
11641 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11642 break;
11643 }
11644 return ret;
11645}
11646
11647/* offset and length are dword aligned */
11648static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11649{
11650 int ret;
11651
1da177e4 11652 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11653 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11654 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11655 udelay(40);
11656 }
11657
11658 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11659 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11660 }
11661 else {
11662 u32 grc_mode;
11663
ec41c7df
MC		 11664 ret = tg3_nvram_lock(tp);
11665 if (ret)
11666 return ret;
1da177e4 11667
e6af301b
MC		 11668 tg3_enable_nvram_access(tp);
11669 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11670 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11671 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11672
11673 grc_mode = tr32(GRC_MODE);
11674 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11675
11676 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11677 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11678
11679 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11680 buf);
11681 }
11682 else {
11683 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11684 buf);
11685 }
11686
11687 grc_mode = tr32(GRC_MODE);
11688 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11689
e6af301b 11690 tg3_disable_nvram_access(tp);
1da177e4
LT		 11691 tg3_nvram_unlock(tp);
11692 }
11693
11694 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11695 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11696 udelay(40);
11697 }
11698
11699 return ret;
11700}
11701
11702struct subsys_tbl_ent {
11703 u16 subsys_vendor, subsys_devid;
11704 u32 phy_id;
11705};
11706
11707static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11708 /* Broadcom boards. */
11709 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11710 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11711 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11712 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11713 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11714 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11715 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11716 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11717 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11718 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11719 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11720
11721 /* 3com boards. */
11722 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11723 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11724 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11725 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11726 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11727
11728 /* DELL boards. */
11729 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11730 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11731 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11732 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11733
11734 /* Compaq boards. */
11735 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11736 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11737 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11738 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11739 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11740
11741 /* IBM boards. */
11742 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11743};
11744
11745static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11746{
11747 int i;
11748
11749 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11750 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11751 tp->pdev->subsystem_vendor) &&
11752 (subsys_id_to_phy_id[i].subsys_devid ==
11753 tp->pdev->subsystem_device))
11754 return &subsys_id_to_phy_id[i];
11755 }
11756 return NULL;
11757}
11758
7d0c41ef 11759static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11760{
1da177e4 11761 u32 val;
caf636c7
MC		 11762 u16 pmcsr;
11763
11764 /* On some early chips the SRAM cannot be accessed in D3hot state,
11765 * so need make sure we're in D0.
11766 */
11767 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11768 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11769 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11770 msleep(1);
7d0c41ef
MC		 11771
11772 /* Make sure register accesses (indirect or otherwise)
11773 * will function correctly.
11774 */
11775 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11776 tp->misc_host_ctrl);
1da177e4 11777
f49639e6
DM		 11778 /* The memory arbiter has to be enabled in order for SRAM accesses
11779 * to succeed. Normally on powerup the tg3 chip firmware will make
11780 * sure it is enabled, but other entities such as system netboot
11781 * code might disable it.
11782 */
11783 val = tr32(MEMARB_MODE);
11784 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11785
1da177e4 11786 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11787 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11788
a85feb8c
GZ		 11789 /* Assume an onboard device and WOL capable by default. */
11790 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11791
b5d3772c 11792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11793 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11794 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11795 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11796 }
0527ba35
MC		 11797 val = tr32(VCPU_CFGSHDW);
11798 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11799 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11800 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11801 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11802 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11803 goto done;
b5d3772c
MC		 11804 }
11805
1da177e4
LT		 11806 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11807 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11808 u32 nic_cfg, led_cfg;
a9daf367 11809 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11810 int eeprom_phy_serdes = 0;
1da177e4
LT		 11811
11812 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11813 tp->nic_sram_data_cfg = nic_cfg;
11814
11815 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11816 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11817 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11818 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11819 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11820 (ver > 0) && (ver < 0x100))
11821 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11822
a9daf367
MC		 11823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11824 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11825
1da177e4
LT		 11826 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11827 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11828 eeprom_phy_serdes = 1;
11829
11830 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11831 if (nic_phy_id != 0) {
11832 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11833 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11834
11835 eeprom_phy_id = (id1 >> 16) << 10;
11836 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11837 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11838 } else
11839 eeprom_phy_id = 0;
11840
7d0c41ef 11841 tp->phy_id = eeprom_phy_id;
747e8f8b 11842 if (eeprom_phy_serdes) {
a4e2b347 11843 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11844 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11845 else
11846 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11847 }
7d0c41ef 11848
cbf46853 11849 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11850 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11851 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11852 else
1da177e4
LT		 11853 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11854
11855 switch (led_cfg) {
11856 default:
11857 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11858 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11859 break;
11860
11861 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11862 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11863 break;
11864
11865 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11866 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11867
11868 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11869 * read on some older 5700/5701 bootcode.
11870 */
11871 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11872 ASIC_REV_5700 ||
11873 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11874 ASIC_REV_5701)
11875 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11876
1da177e4
LT		 11877 break;
11878
11879 case SHASTA_EXT_LED_SHARED:
11880 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11881 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11882 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11883 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11884 LED_CTRL_MODE_PHY_2);
11885 break;
11886
11887 case SHASTA_EXT_LED_MAC:
11888 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11889 break;
11890
11891 case SHASTA_EXT_LED_COMBO:
11892 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11893 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11894 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11895 LED_CTRL_MODE_PHY_2);
11896 break;
11897
855e1111 11898 }
1da177e4
LT		 11899
11900 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11901 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11902 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11903 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11904
b2a5c19c
MC		 11905 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11906 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11907
9d26e213 11908 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11909 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11910 if ((tp->pdev->subsystem_vendor ==
11911 PCI_VENDOR_ID_ARIMA) &&
11912 (tp->pdev->subsystem_device == 0x205a ||
11913 tp->pdev->subsystem_device == 0x2063))
11914 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11915 } else {
f49639e6 11916 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11917 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11918 }
1da177e4
LT		 11919
11920 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11921 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11922 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11923 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11924 }
b2b98d4a
MC		 11925
11926 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11927 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11928 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11929
a85feb8c
GZ		 11930 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11931 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11932 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11933
12dac075 11934 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11935 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11936 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11937
1da177e4
LT		 11938 if (cfg2 & (1 << 17))
11939 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11940
11941 /* serdes signal pre-emphasis in register 0x590 set by */
11942 /* bootcode if bit 18 is set */
11943 if (cfg2 & (1 << 18))
11944 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11945
321d32a0
MC		 11946 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11947 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11948 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11949 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11950
8ed5d97e
MC		 11951 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11952 u32 cfg3;
11953
11954 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11955 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11956 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11957 }
a9daf367
MC		 11958
11959 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11960 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11961 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11962 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11963 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11964 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11965 }
05ac4cb7
MC		 11966done:
11967 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11968 device_set_wakeup_enable(&tp->pdev->dev,
11969 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11970}
11971
b2a5c19c
MC		 11972static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11973{
11974 int i;
11975 u32 val;
11976
11977 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11978 tw32(OTP_CTRL, cmd);
11979
11980 /* Wait for up to 1 ms for command to execute. */
11981 for (i = 0; i < 100; i++) {
11982 val = tr32(OTP_STATUS);
11983 if (val & OTP_STATUS_CMD_DONE)
11984 break;
11985 udelay(10);
11986 }
11987
11988 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11989}
11990
11991/* Read the gphy configuration from the OTP region of the chip. The gphy
11992 * configuration is a 32-bit value that straddles the alignment boundary.
11993 * We do two 32-bit reads and then shift and merge the results.
11994 */
11995static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11996{
11997 u32 bhalf_otp, thalf_otp;
11998
11999 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12000
12001 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12002 return 0;
12003
12004 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12005
12006 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12007 return 0;
12008
12009 thalf_otp = tr32(OTP_READ_DATA);
12010
12011 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12012
12013 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12014 return 0;
12015
12016 bhalf_otp = tr32(OTP_READ_DATA);
12017
12018 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12019}
12020
7d0c41ef
MC		 12021static int __devinit tg3_phy_probe(struct tg3 *tp)
12022{
12023 u32 hw_phy_id_1, hw_phy_id_2;
12024 u32 hw_phy_id, hw_phy_id_masked;
12025 int err;
1da177e4 12026
b02fd9e3
MC		 12027 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12028 return tg3_phy_init(tp);
12029
1da177e4 12030 /* Reading the PHY ID register can conflict with ASF
877d0310 12031 * firmware access to the PHY hardware.
1da177e4
LT		 12032 */
12033 err = 0;
0d3031d9
MC		 12034 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12035 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12036 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12037 } else {
12038 /* Now read the physical PHY_ID from the chip and verify
12039 * that it is sane. If it doesn't look good, we fall back
12040 * to either the hard-coded table based PHY_ID and failing
12041 * that the value found in the eeprom area.
12042 */
12043 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12044 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12045
12046 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12047 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12048 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12049
12050 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12051 }
12052
12053 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12054 tp->phy_id = hw_phy_id;
12055 if (hw_phy_id_masked == PHY_ID_BCM8002)
12056 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12057 else
12058 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12059 } else {
7d0c41ef
MC		 12060 if (tp->phy_id != PHY_ID_INVALID) {
12061 /* Do nothing, phy ID already set up in
12062 * tg3_get_eeprom_hw_cfg().
12063 */
1da177e4
LT		 12064 } else {
12065 struct subsys_tbl_ent *p;
12066
12067 /* No eeprom signature? Try the hardcoded
12068 * subsys device table.
12069 */
12070 p = lookup_by_subsys(tp);
12071 if (!p)
12072 return -ENODEV;
12073
12074 tp->phy_id = p->phy_id;
12075 if (!tp->phy_id ||
12076 tp->phy_id == PHY_ID_BCM8002)
12077 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12078 }
12079 }
12080
747e8f8b 12081 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12082 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12083 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12084 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12085
12086 tg3_readphy(tp, MII_BMSR, &bmsr);
12087 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12088 (bmsr & BMSR_LSTATUS))
12089 goto skip_phy_reset;
6aa20a22 12090
1da177e4
LT		 12091 err = tg3_phy_reset(tp);
12092 if (err)
12093 return err;
12094
12095 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12096 ADVERTISE_100HALF | ADVERTISE_100FULL |
12097 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12098 tg3_ctrl = 0;
12099 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12100 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12101 MII_TG3_CTRL_ADV_1000_FULL);
12102 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12103 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12104 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12105 MII_TG3_CTRL_ENABLE_AS_MASTER);
12106 }
12107
3600d918
MC		 12108 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12109 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12110 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12111 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12112 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12113
12114 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12115 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12116
12117 tg3_writephy(tp, MII_BMCR,
12118 BMCR_ANENABLE | BMCR_ANRESTART);
12119 }
12120 tg3_phy_set_wirespeed(tp);
12121
12122 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12123 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12124 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12125 }
12126
12127skip_phy_reset:
12128 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12129 err = tg3_init_5401phy_dsp(tp);
12130 if (err)
12131 return err;
12132 }
12133
12134 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12135 err = tg3_init_5401phy_dsp(tp);
12136 }
12137
747e8f8b 12138 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12139 tp->link_config.advertising =
12140 (ADVERTISED_1000baseT_Half |
12141 ADVERTISED_1000baseT_Full |
12142 ADVERTISED_Autoneg |
12143 ADVERTISED_FIBRE);
12144 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12145 tp->link_config.advertising &=
12146 ~(ADVERTISED_1000baseT_Half |
12147 ADVERTISED_1000baseT_Full);
12148
12149 return err;
12150}
12151
12152static void __devinit tg3_read_partno(struct tg3 *tp)
12153{
6d348f2c 12154 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12155 unsigned int i;
1b27777a 12156 u32 magic;
1da177e4 12157
df259d8c
MC		 12158 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12159 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12160 goto out_not_found;
1da177e4 12161
1820180b 12162 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12163 for (i = 0; i < 256; i += 4) {
12164 u32 tmp;
1da177e4 12165
6d348f2c
MC		 12166 /* The data is in little-endian format in NVRAM.
12167 * Use the big-endian read routines to preserve
12168 * the byte order as it exists in NVRAM.
12169 */
12170 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12171 goto out_not_found;
12172
6d348f2c 12173 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12174 }
12175 } else {
12176 int vpd_cap;
12177
12178 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12179 for (i = 0; i < 256; i += 4) {
12180 u32 tmp, j = 0;
b9fc7dc5 12181 __le32 v;
1b27777a
MC		 12182 u16 tmp16;
12183
12184 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12185 i);
12186 while (j++ < 100) {
12187 pci_read_config_word(tp->pdev, vpd_cap +
12188 PCI_VPD_ADDR, &tmp16);
12189 if (tmp16 & 0x8000)
12190 break;
12191 msleep(1);
12192 }
f49639e6
DM		 12193 if (!(tmp16 & 0x8000))
12194 goto out_not_found;
12195
1b27777a
MC		 12196 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12197 &tmp);
b9fc7dc5 12198 v = cpu_to_le32(tmp);
6d348f2c 12199 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12200 }
1da177e4
LT		 12201 }
12202
12203 /* Now parse and find the part number. */
af2c6a4a 12204 for (i = 0; i < 254; ) {
1da177e4 12205 unsigned char val = vpd_data[i];
af2c6a4a 12206 unsigned int block_end;
1da177e4
LT		 12207
12208 if (val == 0x82 || val == 0x91) {
12209 i = (i + 3 +
12210 (vpd_data[i + 1] +
12211 (vpd_data[i + 2] << 8)));
12212 continue;
12213 }
12214
12215 if (val != 0x90)
12216 goto out_not_found;
12217
12218 block_end = (i + 3 +
12219 (vpd_data[i + 1] +
12220 (vpd_data[i + 2] << 8)));
12221 i += 3;
af2c6a4a
MC		 12222
12223 if (block_end > 256)
12224 goto out_not_found;
12225
12226 while (i < (block_end - 2)) {
1da177e4
LT		 12227 if (vpd_data[i + 0] == 'P' &&
12228 vpd_data[i + 1] == 'N') {
12229 int partno_len = vpd_data[i + 2];
12230
af2c6a4a
MC		 12231 i += 3;
12232 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12233 goto out_not_found;
12234
12235 memcpy(tp->board_part_number,
af2c6a4a 12236 &vpd_data[i], partno_len);
1da177e4
LT		 12237
12238 /* Success. */
12239 return;
12240 }
af2c6a4a 12241 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12242 }
12243
12244 /* Part number not found. */
12245 goto out_not_found;
12246 }
12247
12248out_not_found:
b5d3772c
MC		 12249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12250 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12251 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12252 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12253 strcpy(tp->board_part_number, "BCM57780");
12254 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12255 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12256 strcpy(tp->board_part_number, "BCM57760");
12257 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12258 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12259 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12260 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12261 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12262 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12263 else
12264 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12265}
12266
9c8a620e
MC		 12267static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12268{
12269 u32 val;
12270
e4f34110 12271 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12272 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12273 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12274 val != 0)
12275 return 0;
12276
12277 return 1;
12278}
12279
acd9c119
MC		 12280static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12281{
ff3a7cb2 12282 u32 val, offset, start, ver_offset;
acd9c119 12283 int i;
ff3a7cb2 12284 bool newver = false;
acd9c119
MC		 12285
12286 if (tg3_nvram_read(tp, 0xc, &offset) ||
12287 tg3_nvram_read(tp, 0x4, &start))
12288 return;
12289
12290 offset = tg3_nvram_logical_addr(tp, offset);
12291
ff3a7cb2 12292 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12293 return;
12294
ff3a7cb2
MC		 12295 if ((val & 0xfc000000) == 0x0c000000) {
12296 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12297 return;
12298
ff3a7cb2
MC		 12299 if (val == 0)
12300 newver = true;
12301 }
12302
12303 if (newver) {
12304 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12305 return;
12306
12307 offset = offset + ver_offset - start;
12308 for (i = 0; i < 16; i += 4) {
12309 __be32 v;
12310 if (tg3_nvram_read_be32(tp, offset + i, &v))
12311 return;
12312
12313 memcpy(tp->fw_ver + i, &v, sizeof(v));
12314 }
12315 } else {
12316 u32 major, minor;
12317
12318 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12319 return;
12320
12321 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12322 TG3_NVM_BCVER_MAJSFT;
12323 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12324 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12325 }
12326}
12327
a6f6cb1c
MC		 12328static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12329{
12330 u32 val, major, minor;
12331
12332 /* Use native endian representation */
12333 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12334 return;
12335
12336 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12337 TG3_NVM_HWSB_CFG1_MAJSFT;
12338 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12339 TG3_NVM_HWSB_CFG1_MINSFT;
12340
12341 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12342}
12343
dfe00d7d
MC		 12344static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12345{
12346 u32 offset, major, minor, build;
12347
12348 tp->fw_ver[0] = 's';
12349 tp->fw_ver[1] = 'b';
12350 tp->fw_ver[2] = '\0';
12351
12352 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12353 return;
12354
12355 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12356 case TG3_EEPROM_SB_REVISION_0:
12357 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12358 break;
12359 case TG3_EEPROM_SB_REVISION_2:
12360 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12361 break;
12362 case TG3_EEPROM_SB_REVISION_3:
12363 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12364 break;
12365 default:
12366 return;
12367 }
12368
e4f34110 12369 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12370 return;
12371
12372 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12373 TG3_EEPROM_SB_EDH_BLD_SHFT;
12374 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12375 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12376 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12377
12378 if (minor > 99 || build > 26)
12379 return;
12380
12381 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12382
12383 if (build > 0) {
12384 tp->fw_ver[8] = 'a' + build - 1;
12385 tp->fw_ver[9] = '\0';
12386 }
12387}
12388
acd9c119 12389static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12390{
12391 u32 val, offset, start;
acd9c119 12392 int i, vlen;
9c8a620e
MC		 12393
12394 for (offset = TG3_NVM_DIR_START;
12395 offset < TG3_NVM_DIR_END;
12396 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12397 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12398 return;
12399
9c8a620e
MC		 12400 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12401 break;
12402 }
12403
12404 if (offset == TG3_NVM_DIR_END)
12405 return;
12406
12407 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12408 start = 0x08000000;
e4f34110 12409 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12410 return;
12411
e4f34110 12412 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12413 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12414 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12415 return;
12416
12417 offset += val - start;
12418
acd9c119 12419 vlen = strlen(tp->fw_ver);
9c8a620e 12420
acd9c119
MC		 12421 tp->fw_ver[vlen++] = ',';
12422 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12423
12424 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12425 __be32 v;
12426 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12427 return;
12428
b9fc7dc5 12429 offset += sizeof(v);
c4e6575c 12430
acd9c119
MC		 12431 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12432 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12433 break;
c4e6575c 12434 }
9c8a620e 12435
acd9c119
MC		 12436 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12437 vlen += sizeof(v);
c4e6575c 12438 }
acd9c119
MC		 12439}
12440
7fd76445
MC		 12441static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12442{
12443 int vlen;
12444 u32 apedata;
12445
12446 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12447 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12448 return;
12449
12450 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12451 if (apedata != APE_SEG_SIG_MAGIC)
12452 return;
12453
12454 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12455 if (!(apedata & APE_FW_STATUS_READY))
12456 return;
12457
12458 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12459
12460 vlen = strlen(tp->fw_ver);
12461
12462 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12463 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12464 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12465 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12466 (apedata & APE_FW_VERSION_BLDMSK));
12467}
12468
acd9c119
MC		 12469static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12470{
12471 u32 val;
12472
df259d8c
MC		 12473 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12474 tp->fw_ver[0] = 's';
12475 tp->fw_ver[1] = 'b';
12476 tp->fw_ver[2] = '\0';
12477
12478 return;
12479 }
12480
acd9c119
MC		 12481 if (tg3_nvram_read(tp, 0, &val))
12482 return;
12483
12484 if (val == TG3_EEPROM_MAGIC)
12485 tg3_read_bc_ver(tp);
12486 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12487 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12488 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12489 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12490 else
12491 return;
12492
12493 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12494 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12495 return;
12496
12497 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12498
12499 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12500}
12501
7544b097
MC		 12502static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12503
1da177e4
LT		 12504static int __devinit tg3_get_invariants(struct tg3 *tp)
12505{
12506 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12507 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12508 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12509 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12510 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12511 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12512 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12513 { },
12514 };
12515 u32 misc_ctrl_reg;
1da177e4
LT		 12516 u32 pci_state_reg, grc_misc_cfg;
12517 u32 val;
12518 u16 pci_cmd;
5e7dfd0f 12519 int err;
1da177e4 12520
1da177e4
LT		 12521 /* Force memory write invalidate off. If we leave it on,
12522 * then on 5700_BX chips we have to enable a workaround.
12523 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12524 * to match the cacheline size. The Broadcom driver have this
12525 * workaround but turns MWI off all the times so never uses
12526 * it. This seems to suggest that the workaround is insufficient.
12527 */
12528 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12529 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12530 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12531
12532 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12533 * has the register indirect write enable bit set before
12534 * we try to access any of the MMIO registers. It is also
12535 * critical that the PCI-X hw workaround situation is decided
12536 * before that as well.
12537 */
12538 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12539 &misc_ctrl_reg);
12540
12541 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12542 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12544 u32 prod_id_asic_rev;
12545
f6eb9b1f
MC		 12546 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12547 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12548 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12549 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12550 pci_read_config_dword(tp->pdev,
12551 TG3PCI_GEN2_PRODID_ASICREV,
12552 &prod_id_asic_rev);
12553 else
12554 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12555 &prod_id_asic_rev);
12556
321d32a0 12557 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12558 }
1da177e4 12559
ff645bec
MC		 12560 /* Wrong chip ID in 5752 A0. This code can be removed later
12561 * as A0 is not in production.
12562 */
12563 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12564 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12565
6892914f
MC		 12566 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12567 * we need to disable memory and use config. cycles
12568 * only to access all registers. The 5702/03 chips
12569 * can mistakenly decode the special cycles from the
12570 * ICH chipsets as memory write cycles, causing corruption
12571 * of register and memory space. Only certain ICH bridges
12572 * will drive special cycles with non-zero data during the
12573 * address phase which can fall within the 5703's address
12574 * range. This is not an ICH bug as the PCI spec allows
12575 * non-zero address during special cycles. However, only
12576 * these ICH bridges are known to drive non-zero addresses
12577 * during special cycles.
12578 *
12579 * Since special cycles do not cross PCI bridges, we only
12580 * enable this workaround if the 5703 is on the secondary
12581 * bus of these ICH bridges.
12582 */
12583 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12584 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12585 static struct tg3_dev_id {
12586 u32 vendor;
12587 u32 device;
12588 u32 rev;
12589 } ich_chipsets[] = {
12590 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12591 PCI_ANY_ID },
12592 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12593 PCI_ANY_ID },
12594 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12595 0xa },
12596 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12597 PCI_ANY_ID },
12598 { },
12599 };
12600 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12601 struct pci_dev *bridge = NULL;
12602
12603 while (pci_id->vendor != 0) {
12604 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12605 bridge);
12606 if (!bridge) {
12607 pci_id++;
12608 continue;
12609 }
12610 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12611 if (bridge->revision > pci_id->rev)
6892914f
MC		 12612 continue;
12613 }
12614 if (bridge->subordinate &&
12615 (bridge->subordinate->number ==
12616 tp->pdev->bus->number)) {
12617
12618 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12619 pci_dev_put(bridge);
12620 break;
12621 }
12622 }
12623 }
12624
41588ba1
MC		 12625 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12626 static struct tg3_dev_id {
12627 u32 vendor;
12628 u32 device;
12629 } bridge_chipsets[] = {
12630 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12631 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12632 { },
12633 };
12634 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12635 struct pci_dev *bridge = NULL;
12636
12637 while (pci_id->vendor != 0) {
12638 bridge = pci_get_device(pci_id->vendor,
12639 pci_id->device,
12640 bridge);
12641 if (!bridge) {
12642 pci_id++;
12643 continue;
12644 }
12645 if (bridge->subordinate &&
12646 (bridge->subordinate->number <=
12647 tp->pdev->bus->number) &&
12648 (bridge->subordinate->subordinate >=
12649 tp->pdev->bus->number)) {
12650 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12651 pci_dev_put(bridge);
12652 break;
12653 }
12654 }
12655 }
12656
4a29cc2e
MC		 12657 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12658 * DMA addresses > 40-bit. This bridge may have other additional
12659 * 57xx devices behind it in some 4-port NIC designs for example.
12660 * Any tg3 device found behind the bridge will also need the 40-bit
12661 * DMA workaround.
12662 */
a4e2b347
MC		 12663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12664 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12665 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12666 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12667 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12668 }
4a29cc2e
MC		 12669 else {
12670 struct pci_dev *bridge = NULL;
12671
12672 do {
12673 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12674 PCI_DEVICE_ID_SERVERWORKS_EPB,
12675 bridge);
12676 if (bridge && bridge->subordinate &&
12677 (bridge->subordinate->number <=
12678 tp->pdev->bus->number) &&
12679 (bridge->subordinate->subordinate >=
12680 tp->pdev->bus->number)) {
12681 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12682 pci_dev_put(bridge);
12683 break;
12684 }
12685 } while (bridge);
12686 }
4cf78e4f 12687
1da177e4
LT		 12688 /* Initialize misc host control in PCI block. */
12689 tp->misc_host_ctrl |= (misc_ctrl_reg &
12690 MISC_HOST_CTRL_CHIPREV);
12691 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12692 tp->misc_host_ctrl);
12693
f6eb9b1f
MC		 12694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12697 tp->pdev_peer = tg3_find_peer(tp);
12698
321d32a0
MC		 12699 /* Intentionally exclude ASIC_REV_5906 */
12700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12707 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12708
12709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12710 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12711 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12712 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12713 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12714 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12715
1b440c56
JL		 12716 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12717 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12718 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12719
027455ad
MC		 12720 /* 5700 B0 chips do not support checksumming correctly due
12721 * to hardware bugs.
12722 */
12723 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12724 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12725 else {
12726 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12727 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12728 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12729 tp->dev->features |= NETIF_F_IPV6_CSUM;
12730 }
12731
507399f1 12732 /* Determine TSO capabilities */
e849cdc3
MC		 12733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12734 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12735 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12736 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 12737 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12738 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12739 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12741 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12742 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12743 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12744 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12745 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12746 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12748 tp->fw_needed = FIRMWARE_TG3TSO5;
12749 else
12750 tp->fw_needed = FIRMWARE_TG3TSO;
12751 }
12752
12753 tp->irq_max = 1;
12754
5a6f3074 12755 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12756 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12757 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12758 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12759 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12760 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12761 tp->pdev_peer == tp->pdev))
12762 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12763
321d32a0 12764 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 12766 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12767 }
4f125f42 12768
507399f1
MC		 12769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12770 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12771 tp->irq_max = TG3_IRQ_MAX_VECS;
12772 }
f6eb9b1f 12773 }
0e1406dd 12774
615774fe
MC		 12775 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12777 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12778 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12779 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12780 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 12781 }
f6eb9b1f 12782
f51f3562 12783 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12784 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12785 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12786 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12787
52f4490c
MC		 12788 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12789 &pci_state_reg);
12790
5e7dfd0f
MC		 12791 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12792 if (tp->pcie_cap != 0) {
12793 u16 lnkctl;
12794
1da177e4 12795 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12796
12797 pcie_set_readrq(tp->pdev, 4096);
12798
5e7dfd0f
MC		 12799 pci_read_config_word(tp->pdev,
12800 tp->pcie_cap + PCI_EXP_LNKCTL,
12801 &lnkctl);
12802 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12804 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12807 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12808 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12809 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12810 }
52f4490c 12811 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12812 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12813 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12814 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12815 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12816 if (!tp->pcix_cap) {
12817 printk(KERN_ERR PFX "Cannot find PCI-X "
12818 "capability, aborting.\n");
12819 return -EIO;
12820 }
12821
12822 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12823 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12824 }
1da177e4 12825
399de50b
MC		 12826 /* If we have an AMD 762 or VIA K8T800 chipset, write
12827 * reordering to the mailbox registers done by the host
12828 * controller can cause major troubles. We read back from
12829 * every mailbox register write to force the writes to be
12830 * posted to the chip in order.
12831 */
12832 if (pci_dev_present(write_reorder_chipsets) &&
12833 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12834 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12835
69fc4053
MC		 12836 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12837 &tp->pci_cacheline_sz);
12838 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12839 &tp->pci_lat_timer);
1da177e4
LT		 12840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12841 tp->pci_lat_timer < 64) {
12842 tp->pci_lat_timer = 64;
69fc4053
MC		 12843 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12844 tp->pci_lat_timer);
1da177e4
LT		 12845 }
12846
52f4490c
MC		 12847 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12848 /* 5700 BX chips need to have their TX producer index
12849 * mailboxes written twice to workaround a bug.
12850 */
12851 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12852
52f4490c 12853 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12854 *
12855 * The workaround is to use indirect register accesses
12856 * for all chip writes not to mailbox registers.
12857 */
52f4490c 12858 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12859 u32 pm_reg;
1da177e4
LT		 12860
12861 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12862
12863 /* The chip can have it's power management PCI config
12864 * space registers clobbered due to this bug.
12865 * So explicitly force the chip into D0 here.
12866 */
9974a356
MC		 12867 pci_read_config_dword(tp->pdev,
12868 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12869 &pm_reg);
12870 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12871 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12872 pci_write_config_dword(tp->pdev,
12873 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12874 pm_reg);
12875
12876 /* Also, force SERR#/PERR# in PCI command. */
12877 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12878 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12879 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12880 }
12881 }
12882
1da177e4
LT		 12883 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12884 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12885 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12886 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12887
12888 /* Chip-specific fixup from Broadcom driver */
12889 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12890 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12891 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12892 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12893 }
12894
1ee582d8 12895 /* Default fast path register access methods */
20094930 12896 tp->read32 = tg3_read32;
1ee582d8 12897 tp->write32 = tg3_write32;
09ee929c 12898 tp->read32_mbox = tg3_read32;
20094930 12899 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12900 tp->write32_tx_mbox = tg3_write32;
12901 tp->write32_rx_mbox = tg3_write32;
12902
12903 /* Various workaround register access methods */
12904 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12905 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12906 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12907 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12908 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12909 /*
12910 * Back to back register writes can cause problems on these
12911 * chips, the workaround is to read back all reg writes
12912 * except those to mailbox regs.
12913 *
12914 * See tg3_write_indirect_reg32().
12915 */
1ee582d8 12916 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12917 }
12918
1ee582d8
MC		 12919 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12920 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12921 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12922 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12923 tp->write32_rx_mbox = tg3_write_flush_reg32;
12924 }
20094930 12925
6892914f
MC		 12926 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12927 tp->read32 = tg3_read_indirect_reg32;
12928 tp->write32 = tg3_write_indirect_reg32;
12929 tp->read32_mbox = tg3_read_indirect_mbox;
12930 tp->write32_mbox = tg3_write_indirect_mbox;
12931 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12932 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12933
12934 iounmap(tp->regs);
22abe310 12935 tp->regs = NULL;
6892914f
MC		 12936
12937 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12938 pci_cmd &= ~PCI_COMMAND_MEMORY;
12939 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12940 }
b5d3772c
MC		 12941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12942 tp->read32_mbox = tg3_read32_mbox_5906;
12943 tp->write32_mbox = tg3_write32_mbox_5906;
12944 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12945 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12946 }
6892914f 12947
bbadf503
MC		 12948 if (tp->write32 == tg3_write_indirect_reg32 ||
12949 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12950 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12952 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12953
7d0c41ef 12954 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12955 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12956 * determined before calling tg3_set_power_state() so that
12957 * we know whether or not to switch out of Vaux power.
12958 * When the flag is set, it means that GPIO1 is used for eeprom
12959 * write protect and also implies that it is a LOM where GPIOs
12960 * are not used to switch power.
6aa20a22 12961 */
7d0c41ef
MC		 12962 tg3_get_eeprom_hw_cfg(tp);
12963
0d3031d9
MC		 12964 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12965 /* Allow reads and writes to the
12966 * APE register and memory space.
12967 */
12968 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12969 PCISTATE_ALLOW_APE_SHMEM_WR;
12970 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12971 pci_state_reg);
12972 }
12973
9936bcf6 12974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12979 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12980
314fba34
MC		 12981 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12982 * GPIO1 driven high will bring 5700's external PHY out of reset.
12983 * It is also used as eeprom write protect on LOMs.
12984 */
12985 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12986 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12987 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12988 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12989 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12990 /* Unused GPIO3 must be driven as output on 5752 because there
12991 * are no pull-up resistors on unused GPIO pins.
12992 */
12993 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12994 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12995
321d32a0
MC		 12996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12998 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12999
8d519ab2
MC		 13000 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13001 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13002 /* Turn off the debug UART. */
13003 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13004 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13005 /* Keep VMain power. */
13006 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13007 GRC_LCLCTRL_GPIO_OUTPUT0;
13008 }
13009
1da177e4 13010 /* Force the chip into D0. */
bc1c7567 13011 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13012 if (err) {
13013 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13014 pci_name(tp->pdev));
13015 return err;
13016 }
13017
1da177e4
LT		 13018 /* Derive initial jumbo mode from MTU assigned in
13019 * ether_setup() via the alloc_etherdev() call
13020 */
0f893dc6 13021 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13022 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13023 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13024
13025 /* Determine WakeOnLan speed to use. */
13026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13027 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13028 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13029 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13030 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13031 } else {
13032 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13033 }
13034
7f97a4bd
MC		 13035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13036 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13037
1da177e4
LT		 13038 /* A few boards don't want Ethernet@WireSpeed phy feature */
13039 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13040 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13041 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13042 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13043 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13044 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13045 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13046
13047 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13048 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13049 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13050 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13051 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13052
321d32a0 13053 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13054 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13055 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 13056 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13057 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 13058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13062 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13063 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13064 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13065 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13066 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13067 } else
c424cb24
MC		 13068 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13069 }
1da177e4 13070
b2a5c19c
MC		 13071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13072 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13073 tp->phy_otp = tg3_read_otp_phycfg(tp);
13074 if (tp->phy_otp == 0)
13075 tp->phy_otp = TG3_OTP_DEFAULT;
13076 }
13077
f51f3562 13078 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13079 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13080 else
13081 tp->mi_mode = MAC_MI_MODE_BASE;
13082
1da177e4 13083 tp->coalesce_mode = 0;
1da177e4
LT		 13084 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13085 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13086 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13087
321d32a0
MC		 13088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13090 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13091
158d7abd
MC		 13092 err = tg3_mdio_init(tp);
13093 if (err)
13094 return err;
1da177e4
LT		 13095
13096 /* Initialize data/descriptor byte/word swapping. */
13097 val = tr32(GRC_MODE);
13098 val &= GRC_MODE_HOST_STACKUP;
13099 tw32(GRC_MODE, val | tp->grc_mode);
13100
13101 tg3_switch_clocks(tp);
13102
13103 /* Clear this out for sanity. */
13104 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13105
13106 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13107 &pci_state_reg);
13108 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13109 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13110 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13111
13112 if (chiprevid == CHIPREV_ID_5701_A0 ||
13113 chiprevid == CHIPREV_ID_5701_B0 ||
13114 chiprevid == CHIPREV_ID_5701_B2 ||
13115 chiprevid == CHIPREV_ID_5701_B5) {
13116 void __iomem *sram_base;
13117
13118 /* Write some dummy words into the SRAM status block
13119 * area, see if it reads back correctly. If the return
13120 * value is bad, force enable the PCIX workaround.
13121 */
13122 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13123
13124 writel(0x00000000, sram_base);
13125 writel(0x00000000, sram_base + 4);
13126 writel(0xffffffff, sram_base + 4);
13127 if (readl(sram_base) != 0x00000000)
13128 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13129 }
13130 }
13131
13132 udelay(50);
13133 tg3_nvram_init(tp);
13134
13135 grc_misc_cfg = tr32(GRC_MISC_CFG);
13136 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13137
1da177e4
LT		 13138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13139 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13140 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13141 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13142
fac9b83e
DM		 13143 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13144 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13145 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13146 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13147 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13148 HOSTCC_MODE_CLRTICK_TXBD);
13149
13150 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13151 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13152 tp->misc_host_ctrl);
13153 }
13154
3bda1258
MC		 13155 /* Preserve the APE MAC_MODE bits */
13156 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13157 tp->mac_mode = tr32(MAC_MODE) |
13158 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13159 else
13160 tp->mac_mode = TG3_DEF_MAC_MODE;
13161
1da177e4
LT		 13162 /* these are limited to 10/100 only */
13163 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13164 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13165 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13166 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13167 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13168 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13169 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13170 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13171 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13172 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13173 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13174 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13175 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13176 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13177
13178 err = tg3_phy_probe(tp);
13179 if (err) {
13180 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13181 pci_name(tp->pdev), err);
13182 /* ... but do not return immediately ... */
b02fd9e3 13183 tg3_mdio_fini(tp);
1da177e4
LT		 13184 }
13185
13186 tg3_read_partno(tp);
c4e6575c 13187 tg3_read_fw_ver(tp);
1da177e4
LT		 13188
13189 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13190 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13191 } else {
13192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13193 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13194 else
13195 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13196 }
13197
13198 /* 5700 {AX,BX} chips have a broken status block link
13199 * change bit implementation, so we must use the
13200 * status register in those cases.
13201 */
13202 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13203 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13204 else
13205 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13206
13207 /* The led_ctrl is set during tg3_phy_probe, here we might
13208 * have to force the link status polling mechanism based
13209 * upon subsystem IDs.
13210 */
13211 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13213 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13214 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13215 TG3_FLAG_USE_LINKCHG_REG);
13216 }
13217
13218 /* For all SERDES we poll the MAC status register. */
13219 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13220 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13221 else
13222 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13223
ad829268 13224 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13226 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13227 tp->rx_offset = 0;
13228
f92905de
MC		 13229 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13230
13231 /* Increment the rx prod index on the rx std ring by at most
13232 * 8 for these chips to workaround hw errata.
13233 */
13234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13235 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13237 tp->rx_std_max_post = 8;
13238
8ed5d97e
MC		 13239 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13240 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13241 PCIE_PWR_MGMT_L1_THRESH_MSK;
13242
1da177e4
LT		 13243 return err;
13244}
13245
49b6e95f 13246#ifdef CONFIG_SPARC
1da177e4
LT		 13247static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13248{
13249 struct net_device *dev = tp->dev;
13250 struct pci_dev *pdev = tp->pdev;
49b6e95f 13251 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13252 const unsigned char *addr;
49b6e95f
DM		 13253 int len;
13254
13255 addr = of_get_property(dp, "local-mac-address", &len);
13256 if (addr && len == 6) {
13257 memcpy(dev->dev_addr, addr, 6);
13258 memcpy(dev->perm_addr, dev->dev_addr, 6);
13259 return 0;
1da177e4
LT		 13260 }
13261 return -ENODEV;
13262}
13263
13264static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13265{
13266 struct net_device *dev = tp->dev;
13267
13268 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13269 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13270 return 0;
13271}
13272#endif
13273
13274static int __devinit tg3_get_device_address(struct tg3 *tp)
13275{
13276 struct net_device *dev = tp->dev;
13277 u32 hi, lo, mac_offset;
008652b3 13278 int addr_ok = 0;
1da177e4 13279
49b6e95f 13280#ifdef CONFIG_SPARC
1da177e4
LT		 13281 if (!tg3_get_macaddr_sparc(tp))
13282 return 0;
13283#endif
13284
13285 mac_offset = 0x7c;
f49639e6 13286 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13287 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13288 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13289 mac_offset = 0xcc;
13290 if (tg3_nvram_lock(tp))
13291 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13292 else
13293 tg3_nvram_unlock(tp);
a1b950d5
MC		 13294 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13295 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13296 mac_offset = 0xcc;
13297 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13298 mac_offset = 0x10;
1da177e4
LT		 13299
13300 /* First try to get it from MAC address mailbox. */
13301 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13302 if ((hi >> 16) == 0x484b) {
13303 dev->dev_addr[0] = (hi >> 8) & 0xff;
13304 dev->dev_addr[1] = (hi >> 0) & 0xff;
13305
13306 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13307 dev->dev_addr[2] = (lo >> 24) & 0xff;
13308 dev->dev_addr[3] = (lo >> 16) & 0xff;
13309 dev->dev_addr[4] = (lo >> 8) & 0xff;
13310 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13311
008652b3
MC		 13312 /* Some old bootcode may report a 0 MAC address in SRAM */
13313 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13314 }
13315 if (!addr_ok) {
13316 /* Next, try NVRAM. */
df259d8c
MC		 13317 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13318 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13319 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13320 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13321 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13322 }
13323 /* Finally just fetch it out of the MAC control regs. */
13324 else {
13325 hi = tr32(MAC_ADDR_0_HIGH);
13326 lo = tr32(MAC_ADDR_0_LOW);
13327
13328 dev->dev_addr[5] = lo & 0xff;
13329 dev->dev_addr[4] = (lo >> 8) & 0xff;
13330 dev->dev_addr[3] = (lo >> 16) & 0xff;
13331 dev->dev_addr[2] = (lo >> 24) & 0xff;
13332 dev->dev_addr[1] = hi & 0xff;
13333 dev->dev_addr[0] = (hi >> 8) & 0xff;
13334 }
1da177e4
LT		 13335 }
13336
13337 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13338#ifdef CONFIG_SPARC
1da177e4
LT		 13339 if (!tg3_get_default_macaddr_sparc(tp))
13340 return 0;
13341#endif
13342 return -EINVAL;
13343 }
2ff43697 13344 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13345 return 0;
13346}
13347
59e6b434
DM		 13348#define BOUNDARY_SINGLE_CACHELINE 1
13349#define BOUNDARY_MULTI_CACHELINE 2
13350
13351static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13352{
13353 int cacheline_size;
13354 u8 byte;
13355 int goal;
13356
13357 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13358 if (byte == 0)
13359 cacheline_size = 1024;
13360 else
13361 cacheline_size = (int) byte * 4;
13362
13363 /* On 5703 and later chips, the boundary bits have no
13364 * effect.
13365 */
13366 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13367 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13368 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13369 goto out;
13370
13371#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13372 goal = BOUNDARY_MULTI_CACHELINE;
13373#else
13374#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13375 goal = BOUNDARY_SINGLE_CACHELINE;
13376#else
13377 goal = 0;
13378#endif
13379#endif
13380
cbf9ca6c
MC		 13381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13382 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13383 goto out;
13384 }
13385
59e6b434
DM		 13386 if (!goal)
13387 goto out;
13388
13389 /* PCI controllers on most RISC systems tend to disconnect
13390 * when a device tries to burst across a cache-line boundary.
13391 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13392 *
13393 * Unfortunately, for PCI-E there are only limited
13394 * write-side controls for this, and thus for reads
13395 * we will still get the disconnects. We'll also waste
13396 * these PCI cycles for both read and write for chips
13397 * other than 5700 and 5701 which do not implement the
13398 * boundary bits.
13399 */
13400 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13401 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13402 switch (cacheline_size) {
13403 case 16:
13404 case 32:
13405 case 64:
13406 case 128:
13407 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13408 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13409 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13410 } else {
13411 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13412 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13413 }
13414 break;
13415
13416 case 256:
13417 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13418 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13419 break;
13420
13421 default:
13422 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13423 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13424 break;
855e1111 13425 }
59e6b434
DM		 13426 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13427 switch (cacheline_size) {
13428 case 16:
13429 case 32:
13430 case 64:
13431 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13432 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13433 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13434 break;
13435 }
13436 /* fallthrough */
13437 case 128:
13438 default:
13439 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13440 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13441 break;
855e1111 13442 }
59e6b434
DM		 13443 } else {
13444 switch (cacheline_size) {
13445 case 16:
13446 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13447 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13448 DMA_RWCTRL_WRITE_BNDRY_16);
13449 break;
13450 }
13451 /* fallthrough */
13452 case 32:
13453 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13454 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13455 DMA_RWCTRL_WRITE_BNDRY_32);
13456 break;
13457 }
13458 /* fallthrough */
13459 case 64:
13460 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13461 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13462 DMA_RWCTRL_WRITE_BNDRY_64);
13463 break;
13464 }
13465 /* fallthrough */
13466 case 128:
13467 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13468 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13469 DMA_RWCTRL_WRITE_BNDRY_128);
13470 break;
13471 }
13472 /* fallthrough */
13473 case 256:
13474 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13475 DMA_RWCTRL_WRITE_BNDRY_256);
13476 break;
13477 case 512:
13478 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13479 DMA_RWCTRL_WRITE_BNDRY_512);
13480 break;
13481 case 1024:
13482 default:
13483 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13484 DMA_RWCTRL_WRITE_BNDRY_1024);
13485 break;
855e1111 13486 }
59e6b434
DM		 13487 }
13488
13489out:
13490 return val;
13491}
13492
1da177e4
LT		 13493static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13494{
13495 struct tg3_internal_buffer_desc test_desc;
13496 u32 sram_dma_descs;
13497 int i, ret;
13498
13499 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13500
13501 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13502 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13503 tw32(RDMAC_STATUS, 0);
13504 tw32(WDMAC_STATUS, 0);
13505
13506 tw32(BUFMGR_MODE, 0);
13507 tw32(FTQ_RESET, 0);
13508
13509 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13510 test_desc.addr_lo = buf_dma & 0xffffffff;
13511 test_desc.nic_mbuf = 0x00002100;
13512 test_desc.len = size;
13513
13514 /*
13515 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13516 * the *second* time the tg3 driver was getting loaded after an
13517 * initial scan.
13518 *
13519 * Broadcom tells me:
13520 * ...the DMA engine is connected to the GRC block and a DMA
13521 * reset may affect the GRC block in some unpredictable way...
13522 * The behavior of resets to individual blocks has not been tested.
13523 *
13524 * Broadcom noted the GRC reset will also reset all sub-components.
13525 */
13526 if (to_device) {
13527 test_desc.cqid_sqid = (13 << 8) | 2;
13528
13529 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13530 udelay(40);
13531 } else {
13532 test_desc.cqid_sqid = (16 << 8) | 7;
13533
13534 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13535 udelay(40);
13536 }
13537 test_desc.flags = 0x00000005;
13538
13539 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13540 u32 val;
13541
13542 val = *(((u32 *)&test_desc) + i);
13543 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13544 sram_dma_descs + (i * sizeof(u32)));
13545 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13546 }
13547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13548
13549 if (to_device) {
13550 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13551 } else {
13552 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13553 }
13554
13555 ret = -ENODEV;
13556 for (i = 0; i < 40; i++) {
13557 u32 val;
13558
13559 if (to_device)
13560 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13561 else
13562 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13563 if ((val & 0xffff) == sram_dma_descs) {
13564 ret = 0;
13565 break;
13566 }
13567
13568 udelay(100);
13569 }
13570
13571 return ret;
13572}
13573
ded7340d 13574#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13575
13576static int __devinit tg3_test_dma(struct tg3 *tp)
13577{
13578 dma_addr_t buf_dma;
59e6b434 13579 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13580 int ret = 0;
1da177e4
LT		 13581
13582 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13583 if (!buf) {
13584 ret = -ENOMEM;
13585 goto out_nofree;
13586 }
13587
13588 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13589 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13590
59e6b434 13591 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13592
cbf9ca6c
MC		 13593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13594 goto out;
13595
1da177e4
LT		 13596 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13597 /* DMA read watermark not used on PCIE */
13598 tp->dma_rwctrl |= 0x00180000;
13599 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13600 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13602 tp->dma_rwctrl |= 0x003f0000;
13603 else
13604 tp->dma_rwctrl |= 0x003f000f;
13605 } else {
13606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13608 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13609 u32 read_water = 0x7;
1da177e4 13610
4a29cc2e
MC		 13611 /* If the 5704 is behind the EPB bridge, we can
13612 * do the less restrictive ONE_DMA workaround for
13613 * better performance.
13614 */
13615 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13617 tp->dma_rwctrl |= 0x8000;
13618 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13619 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13620
49afdeb6
MC		 13621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13622 read_water = 4;
59e6b434 13623 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13624 tp->dma_rwctrl |=
13625 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13626 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13627 (1 << 23);
4cf78e4f
MC		 13628 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13629 /* 5780 always in PCIX mode */
13630 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13631 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13632 /* 5714 always in PCIX mode */
13633 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13634 } else {
13635 tp->dma_rwctrl |= 0x001b000f;
13636 }
13637 }
13638
13639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13641 tp->dma_rwctrl &= 0xfffffff0;
13642
13643 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13645 /* Remove this if it causes problems for some boards. */
13646 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13647
13648 /* On 5700/5701 chips, we need to set this bit.
13649 * Otherwise the chip will issue cacheline transactions
13650 * to streamable DMA memory with not all the byte
13651 * enables turned on. This is an error on several
13652 * RISC PCI controllers, in particular sparc64.
13653 *
13654 * On 5703/5704 chips, this bit has been reassigned
13655 * a different meaning. In particular, it is used
13656 * on those chips to enable a PCI-X workaround.
13657 */
13658 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13659 }
13660
13661 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13662
13663#if 0
13664 /* Unneeded, already done by tg3_get_invariants. */
13665 tg3_switch_clocks(tp);
13666#endif
13667
1da177e4
LT		 13668 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13669 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13670 goto out;
13671
59e6b434
DM		 13672 /* It is best to perform DMA test with maximum write burst size
13673 * to expose the 5700/5701 write DMA bug.
13674 */
13675 saved_dma_rwctrl = tp->dma_rwctrl;
13676 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13677 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13678
1da177e4
LT		 13679 while (1) {
13680 u32 *p = buf, i;
13681
13682 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13683 p[i] = i;
13684
13685 /* Send the buffer to the chip. */
13686 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13687 if (ret) {
13688 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13689 break;
13690 }
13691
13692#if 0
13693 /* validate data reached card RAM correctly. */
13694 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13695 u32 val;
13696 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13697 if (le32_to_cpu(val) != p[i]) {
13698 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13699 /* ret = -ENODEV here? */
13700 }
13701 p[i] = 0;
13702 }
13703#endif
13704 /* Now read it back. */
13705 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13706 if (ret) {
13707 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13708
13709 break;
13710 }
13711
13712 /* Verify it. */
13713 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13714 if (p[i] == i)
13715 continue;
13716
59e6b434
DM		 13717 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13718 DMA_RWCTRL_WRITE_BNDRY_16) {
13719 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13720 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13721 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13722 break;
13723 } else {
13724 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13725 ret = -ENODEV;
13726 goto out;
13727 }
13728 }
13729
13730 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13731 /* Success. */
13732 ret = 0;
13733 break;
13734 }
13735 }
59e6b434
DM		 13736 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13737 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13738 static struct pci_device_id dma_wait_state_chipsets[] = {
13739 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13740 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13741 { },
13742 };
13743
59e6b434 13744 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13745 * now look for chipsets that are known to expose the
13746 * DMA bug without failing the test.
59e6b434 13747 */
6d1cfbab
MC		 13748 if (pci_dev_present(dma_wait_state_chipsets)) {
13749 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13750 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13751 }
13752 else
13753 /* Safe to use the calculated DMA boundary. */
13754 tp->dma_rwctrl = saved_dma_rwctrl;
13755
59e6b434
DM		 13756 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13757 }
1da177e4
LT		 13758
13759out:
13760 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13761out_nofree:
13762 return ret;
13763}
13764
13765static void __devinit tg3_init_link_config(struct tg3 *tp)
13766{
13767 tp->link_config.advertising =
13768 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13769 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13770 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13771 ADVERTISED_Autoneg | ADVERTISED_MII);
13772 tp->link_config.speed = SPEED_INVALID;
13773 tp->link_config.duplex = DUPLEX_INVALID;
13774 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13775 tp->link_config.active_speed = SPEED_INVALID;
13776 tp->link_config.active_duplex = DUPLEX_INVALID;
13777 tp->link_config.phy_is_low_power = 0;
13778 tp->link_config.orig_speed = SPEED_INVALID;
13779 tp->link_config.orig_duplex = DUPLEX_INVALID;
13780 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13781}
13782
13783static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13784{
f6eb9b1f
MC		 13785 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13786 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13787 tp->bufmgr_config.mbuf_read_dma_low_water =
13788 DEFAULT_MB_RDMA_LOW_WATER_5705;
13789 tp->bufmgr_config.mbuf_mac_rx_low_water =
13790 DEFAULT_MB_MACRX_LOW_WATER_5705;
13791 tp->bufmgr_config.mbuf_high_water =
13792 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13794 tp->bufmgr_config.mbuf_mac_rx_low_water =
13795 DEFAULT_MB_MACRX_LOW_WATER_5906;
13796 tp->bufmgr_config.mbuf_high_water =
13797 DEFAULT_MB_HIGH_WATER_5906;
13798 }
fdfec172
MC		 13799
13800 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13801 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13802 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13803 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13804 tp->bufmgr_config.mbuf_high_water_jumbo =
13805 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13806 } else {
13807 tp->bufmgr_config.mbuf_read_dma_low_water =
13808 DEFAULT_MB_RDMA_LOW_WATER;
13809 tp->bufmgr_config.mbuf_mac_rx_low_water =
13810 DEFAULT_MB_MACRX_LOW_WATER;
13811 tp->bufmgr_config.mbuf_high_water =
13812 DEFAULT_MB_HIGH_WATER;
13813
13814 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13815 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13816 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13817 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13818 tp->bufmgr_config.mbuf_high_water_jumbo =
13819 DEFAULT_MB_HIGH_WATER_JUMBO;
13820 }
1da177e4
LT		 13821
13822 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13823 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13824}
13825
13826static char * __devinit tg3_phy_string(struct tg3 *tp)
13827{
13828 switch (tp->phy_id & PHY_ID_MASK) {
13829 case PHY_ID_BCM5400: return "5400";
13830 case PHY_ID_BCM5401: return "5401";
13831 case PHY_ID_BCM5411: return "5411";
13832 case PHY_ID_BCM5701: return "5701";
13833 case PHY_ID_BCM5703: return "5703";
13834 case PHY_ID_BCM5704: return "5704";
13835 case PHY_ID_BCM5705: return "5705";
13836 case PHY_ID_BCM5750: return "5750";
85e94ced 13837 case PHY_ID_BCM5752: return "5752";
a4e2b347 13838 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13839 case PHY_ID_BCM5780: return "5780";
af36e6b6 13840 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13841 case PHY_ID_BCM5787: return "5787";
d30cdd28 13842 case PHY_ID_BCM5784: return "5784";
126a3368 13843 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13844 case PHY_ID_BCM5906: return "5906";
9936bcf6 13845 case PHY_ID_BCM5761: return "5761";
c2060fe1 13846 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 13847 case PHY_ID_BCM8002: return "8002/serdes";
13848 case 0: return "serdes";
13849 default: return "unknown";
855e1111 13850 }
1da177e4
LT		 13851}
13852
f9804ddb
MC		 13853static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13854{
13855 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13856 strcpy(str, "PCI Express");
13857 return str;
13858 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13859 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13860
13861 strcpy(str, "PCIX:");
13862
13863 if ((clock_ctrl == 7) ||
13864 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13865 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13866 strcat(str, "133MHz");
13867 else if (clock_ctrl == 0)
13868 strcat(str, "33MHz");
13869 else if (clock_ctrl == 2)
13870 strcat(str, "50MHz");
13871 else if (clock_ctrl == 4)
13872 strcat(str, "66MHz");
13873 else if (clock_ctrl == 6)
13874 strcat(str, "100MHz");
f9804ddb
MC		 13875 } else {
13876 strcpy(str, "PCI:");
13877 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13878 strcat(str, "66MHz");
13879 else
13880 strcat(str, "33MHz");
13881 }
13882 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13883 strcat(str, ":32-bit");
13884 else
13885 strcat(str, ":64-bit");
13886 return str;
13887}
13888
8c2dc7e1 13889static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13890{
13891 struct pci_dev *peer;
13892 unsigned int func, devnr = tp->pdev->devfn & ~7;
13893
13894 for (func = 0; func < 8; func++) {
13895 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13896 if (peer && peer != tp->pdev)
13897 break;
13898 pci_dev_put(peer);
13899 }
16fe9d74
MC		 13900 /* 5704 can be configured in single-port mode, set peer to
13901 * tp->pdev in that case.
13902 */
13903 if (!peer) {
13904 peer = tp->pdev;
13905 return peer;
13906 }
1da177e4
LT		 13907
13908 /*
13909 * We don't need to keep the refcount elevated; there's no way
13910 * to remove one half of this device without removing the other
13911 */
13912 pci_dev_put(peer);
13913
13914 return peer;
13915}
13916
15f9850d
DM		 13917static void __devinit tg3_init_coal(struct tg3 *tp)
13918{
13919 struct ethtool_coalesce *ec = &tp->coal;
13920
13921 memset(ec, 0, sizeof(*ec));
13922 ec->cmd = ETHTOOL_GCOALESCE;
13923 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13924 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13925 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13926 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13927 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13928 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13929 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13930 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13931 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13932
13933 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13934 HOSTCC_MODE_CLRTICK_TXBD)) {
13935 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13936 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13937 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13938 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13939 }
d244c892
MC		 13940
13941 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13942 ec->rx_coalesce_usecs_irq = 0;
13943 ec->tx_coalesce_usecs_irq = 0;
13944 ec->stats_block_coalesce_usecs = 0;
13945 }
15f9850d
DM		 13946}
13947
7c7d64b8
SH		 13948static const struct net_device_ops tg3_netdev_ops = {
13949 .ndo_open = tg3_open,
13950 .ndo_stop = tg3_close,
00829823
SH		 13951 .ndo_start_xmit = tg3_start_xmit,
13952 .ndo_get_stats = tg3_get_stats,
13953 .ndo_validate_addr = eth_validate_addr,
13954 .ndo_set_multicast_list = tg3_set_rx_mode,
13955 .ndo_set_mac_address = tg3_set_mac_addr,
13956 .ndo_do_ioctl = tg3_ioctl,
13957 .ndo_tx_timeout = tg3_tx_timeout,
13958 .ndo_change_mtu = tg3_change_mtu,
13959#if TG3_VLAN_TAG_USED
13960 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13961#endif
13962#ifdef CONFIG_NET_POLL_CONTROLLER
13963 .ndo_poll_controller = tg3_poll_controller,
13964#endif
13965};
13966
13967static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13968 .ndo_open = tg3_open,
13969 .ndo_stop = tg3_close,
13970 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13971 .ndo_get_stats = tg3_get_stats,
13972 .ndo_validate_addr = eth_validate_addr,
13973 .ndo_set_multicast_list = tg3_set_rx_mode,
13974 .ndo_set_mac_address = tg3_set_mac_addr,
13975 .ndo_do_ioctl = tg3_ioctl,
13976 .ndo_tx_timeout = tg3_tx_timeout,
13977 .ndo_change_mtu = tg3_change_mtu,
13978#if TG3_VLAN_TAG_USED
13979 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13980#endif
13981#ifdef CONFIG_NET_POLL_CONTROLLER
13982 .ndo_poll_controller = tg3_poll_controller,
13983#endif
13984};
13985
1da177e4
LT		 13986static int __devinit tg3_init_one(struct pci_dev *pdev,
13987 const struct pci_device_id *ent)
13988{
13989 static int tg3_version_printed = 0;
1da177e4
LT		 13990 struct net_device *dev;
13991 struct tg3 *tp;
646c9edd
MC		 13992 int i, err, pm_cap;
13993 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13994 char str[40];
72f2afb8 13995 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13996
13997 if (tg3_version_printed++ == 0)
13998 printk(KERN_INFO "%s", version);
13999
14000 err = pci_enable_device(pdev);
14001 if (err) {
14002 printk(KERN_ERR PFX "Cannot enable PCI device, "
14003 "aborting.\n");
14004 return err;
14005 }
14006
1da177e4
LT		 14007 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14008 if (err) {
14009 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14010 "aborting.\n");
14011 goto err_out_disable_pdev;
14012 }
14013
14014 pci_set_master(pdev);
14015
14016 /* Find power-management capability. */
14017 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14018 if (pm_cap == 0) {
14019 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14020 "aborting.\n");
14021 err = -EIO;
14022 goto err_out_free_res;
14023 }
14024
fe5f5787 14025 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14026 if (!dev) {
14027 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14028 err = -ENOMEM;
14029 goto err_out_free_res;
14030 }
14031
1da177e4
LT		 14032 SET_NETDEV_DEV(dev, &pdev->dev);
14033
1da177e4
LT		 14034#if TG3_VLAN_TAG_USED
14035 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14036#endif
14037
14038 tp = netdev_priv(dev);
14039 tp->pdev = pdev;
14040 tp->dev = dev;
14041 tp->pm_cap = pm_cap;
1da177e4
LT		 14042 tp->rx_mode = TG3_DEF_RX_MODE;
14043 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14044
1da177e4
LT		 14045 if (tg3_debug > 0)
14046 tp->msg_enable = tg3_debug;
14047 else
14048 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14049
14050 /* The word/byte swap controls here control register access byte
14051 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14052 * setting below.
14053 */
14054 tp->misc_host_ctrl =
14055 MISC_HOST_CTRL_MASK_PCI_INT |
14056 MISC_HOST_CTRL_WORD_SWAP |
14057 MISC_HOST_CTRL_INDIR_ACCESS |
14058 MISC_HOST_CTRL_PCISTATE_RW;
14059
14060 /* The NONFRM (non-frame) byte/word swap controls take effect
14061 * on descriptor entries, anything which isn't packet data.
14062 *
14063 * The StrongARM chips on the board (one for tx, one for rx)
14064 * are running in big-endian mode.
14065 */
14066 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14067 GRC_MODE_WSWAP_NONFRM_DATA);
14068#ifdef __BIG_ENDIAN
14069 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14070#endif
14071 spin_lock_init(&tp->lock);
1da177e4 14072 spin_lock_init(&tp->indirect_lock);
c4028958 14073 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14074
d5fe488a 14075 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14076 if (!tp->regs) {
1da177e4
LT		 14077 printk(KERN_ERR PFX "Cannot map device registers, "
14078 "aborting.\n");
14079 err = -ENOMEM;
14080 goto err_out_free_dev;
14081 }
14082
14083 tg3_init_link_config(tp);
14084
1da177e4
LT		 14085 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14086 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14087
1da177e4 14088 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14089 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14090 dev->irq = pdev->irq;
1da177e4
LT		 14091
14092 err = tg3_get_invariants(tp);
14093 if (err) {
14094 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14095 "aborting.\n");
14096 goto err_out_iounmap;
14097 }
14098
615774fe
MC		 14099 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14100 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14101 dev->netdev_ops = &tg3_netdev_ops;
14102 else
14103 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14104
14105
4a29cc2e
MC		 14106 /* The EPB bridge inside 5714, 5715, and 5780 and any
14107 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14108 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14109 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14110 * do DMA address check in tg3_start_xmit().
14111 */
4a29cc2e 14112 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14113 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14114 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14115 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14116#ifdef CONFIG_HIGHMEM
6a35528a 14117 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14118#endif
4a29cc2e 14119 } else
6a35528a 14120 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14121
14122 /* Configure DMA attributes. */
284901a9 14123 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14124 err = pci_set_dma_mask(pdev, dma_mask);
14125 if (!err) {
14126 dev->features |= NETIF_F_HIGHDMA;
14127 err = pci_set_consistent_dma_mask(pdev,
14128 persist_dma_mask);
14129 if (err < 0) {
14130 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14131 "DMA for consistent allocations\n");
14132 goto err_out_iounmap;
14133 }
14134 }
14135 }
284901a9
YH		 14136 if (err || dma_mask == DMA_BIT_MASK(32)) {
14137 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14138 if (err) {
14139 printk(KERN_ERR PFX "No usable DMA configuration, "
14140 "aborting.\n");
14141 goto err_out_iounmap;
14142 }
14143 }
14144
fdfec172 14145 tg3_init_bufmgr_config(tp);
1da177e4 14146
507399f1
MC		 14147 /* Selectively allow TSO based on operating conditions */
14148 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14149 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14150 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14151 else {
14152 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14153 tp->fw_needed = NULL;
1da177e4 14154 }
507399f1
MC		 14155
14156 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14157 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14158
4e3a7aaa
MC		 14159 /* TSO is on by default on chips that support hardware TSO.
14160 * Firmware TSO on older chips gives lower performance, so it
14161 * is off by default, but can be enabled using ethtool.
14162 */
e849cdc3
MC		 14163 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14164 (dev->features & NETIF_F_IP_CSUM))
14165 dev->features |= NETIF_F_TSO;
14166
14167 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14168 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14169 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14170 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14171 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14173 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14174 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14175 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14177 dev->features |= NETIF_F_TSO_ECN;
b0026624 14178 }
1da177e4 14179
1da177e4
LT		 14180 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14181 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14182 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14183 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14184 tp->rx_pending = 63;
14185 }
14186
1da177e4
LT		 14187 err = tg3_get_device_address(tp);
14188 if (err) {
14189 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14190 "aborting.\n");
077f849d 14191 goto err_out_fw;
1da177e4
LT		 14192 }
14193
c88864df 14194 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14195 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14196 if (!tp->aperegs) {
c88864df
MC		 14197 printk(KERN_ERR PFX "Cannot map APE registers, "
14198 "aborting.\n");
14199 err = -ENOMEM;
077f849d 14200 goto err_out_fw;
c88864df
MC		 14201 }
14202
14203 tg3_ape_lock_init(tp);
7fd76445
MC		 14204
14205 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14206 tg3_read_dash_ver(tp);
c88864df
MC		 14207 }
14208
1da177e4
LT		 14209 /*
14210 * Reset chip in case UNDI or EFI driver did not shutdown
14211 * DMA self test will enable WDMAC and we'll see (spurious)
14212 * pending DMA on the PCI bus at that point.
14213 */
14214 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14215 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14216 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14217 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14218 }
14219
14220 err = tg3_test_dma(tp);
14221 if (err) {
14222 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14223 goto err_out_apeunmap;
1da177e4
LT		 14224 }
14225
1da177e4
LT		 14226 /* flow control autonegotiation is default behavior */
14227 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14228 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14229
78f90dcf
MC		 14230 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14231 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14232 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14233 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14234 struct tg3_napi *tnapi = &tp->napi[i];
14235
14236 tnapi->tp = tp;
14237 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14238
14239 tnapi->int_mbox = intmbx;
14240 if (i < 4)
14241 intmbx += 0x8;
14242 else
14243 intmbx += 0x4;
14244
14245 tnapi->consmbox = rcvmbx;
14246 tnapi->prodmbox = sndmbx;
14247
14248 if (i) {
14249 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14250 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14251 } else {
14252 tnapi->coal_now = HOSTCC_MODE_NOW;
14253 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14254 }
14255
14256 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14257 break;
14258
14259 /*
14260 * If we support MSIX, we'll be using RSS. If we're using
14261 * RSS, the first vector only handles link interrupts and the
14262 * remaining vectors handle rx and tx interrupts. Reuse the
14263 * mailbox values for the next iteration. The values we setup
14264 * above are still useful for the single vectored mode.
14265 */
14266 if (!i)
14267 continue;
14268
14269 rcvmbx += 0x8;
14270
14271 if (sndmbx & 0x4)
14272 sndmbx -= 0x4;
14273 else
14274 sndmbx += 0xc;
14275 }
14276
15f9850d
DM		 14277 tg3_init_coal(tp);
14278
c49a1561
MC		 14279 pci_set_drvdata(pdev, dev);
14280
1da177e4
LT		 14281 err = register_netdev(dev);
14282 if (err) {
14283 printk(KERN_ERR PFX "Cannot register net device, "
14284 "aborting.\n");
0d3031d9 14285 goto err_out_apeunmap;
1da177e4
LT		 14286 }
14287
df59c940 14288 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14289 dev->name,
14290 tp->board_part_number,
14291 tp->pci_chip_rev_id,
f9804ddb 14292 tg3_bus_string(tp, str),
e174961c 14293 dev->dev_addr);
1da177e4 14294
3f0e3ad7
MC		 14295 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14296 struct phy_device *phydev;
14297 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14298 printk(KERN_INFO
14299 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14300 tp->dev->name, phydev->drv->name,
14301 dev_name(&phydev->dev));
14302 } else
df59c940
MC		 14303 printk(KERN_INFO
14304 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14305 tp->dev->name, tg3_phy_string(tp),
14306 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14307 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14308 "10/100/1000Base-T")),
14309 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14310
14311 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14312 dev->name,
14313 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14314 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14315 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14316 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14317 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14318 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14319 dev->name, tp->dma_rwctrl,
284901a9 14320 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14321 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14322
14323 return 0;
14324
0d3031d9
MC		 14325err_out_apeunmap:
14326 if (tp->aperegs) {
14327 iounmap(tp->aperegs);
14328 tp->aperegs = NULL;
14329 }
14330
077f849d
JSR		 14331err_out_fw:
14332 if (tp->fw)
14333 release_firmware(tp->fw);
14334
1da177e4 14335err_out_iounmap:
6892914f
MC		 14336 if (tp->regs) {
14337 iounmap(tp->regs);
22abe310 14338 tp->regs = NULL;
6892914f 14339 }
1da177e4
LT		 14340
14341err_out_free_dev:
14342 free_netdev(dev);
14343
14344err_out_free_res:
14345 pci_release_regions(pdev);
14346
14347err_out_disable_pdev:
14348 pci_disable_device(pdev);
14349 pci_set_drvdata(pdev, NULL);
14350 return err;
14351}
14352
14353static void __devexit tg3_remove_one(struct pci_dev *pdev)
14354{
14355 struct net_device *dev = pci_get_drvdata(pdev);
14356
14357 if (dev) {
14358 struct tg3 *tp = netdev_priv(dev);
14359
077f849d
JSR		 14360 if (tp->fw)
14361 release_firmware(tp->fw);
14362
7faa006f 14363 flush_scheduled_work();
158d7abd 14364
b02fd9e3
MC		 14365 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14366 tg3_phy_fini(tp);
158d7abd 14367 tg3_mdio_fini(tp);
b02fd9e3 14368 }
158d7abd 14369
1da177e4 14370 unregister_netdev(dev);
0d3031d9
MC		 14371 if (tp->aperegs) {
14372 iounmap(tp->aperegs);
14373 tp->aperegs = NULL;
14374 }
6892914f
MC		 14375 if (tp->regs) {
14376 iounmap(tp->regs);
22abe310 14377 tp->regs = NULL;
6892914f 14378 }
1da177e4
LT		 14379 free_netdev(dev);
14380 pci_release_regions(pdev);
14381 pci_disable_device(pdev);
14382 pci_set_drvdata(pdev, NULL);
14383 }
14384}
14385
14386static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14387{
14388 struct net_device *dev = pci_get_drvdata(pdev);
14389 struct tg3 *tp = netdev_priv(dev);
12dac075 14390 pci_power_t target_state;
1da177e4
LT		 14391 int err;
14392
3e0c95fd
MC		 14393 /* PCI register 4 needs to be saved whether netif_running() or not.
14394 * MSI address and data need to be saved if using MSI and
14395 * netif_running().
14396 */
14397 pci_save_state(pdev);
14398
1da177e4
LT		 14399 if (!netif_running(dev))
14400 return 0;
14401
7faa006f 14402 flush_scheduled_work();
b02fd9e3 14403 tg3_phy_stop(tp);
1da177e4
LT		 14404 tg3_netif_stop(tp);
14405
14406 del_timer_sync(&tp->timer);
14407
f47c11ee 14408 tg3_full_lock(tp, 1);
1da177e4 14409 tg3_disable_ints(tp);
f47c11ee 14410 tg3_full_unlock(tp);
1da177e4
LT		 14411
14412 netif_device_detach(dev);
14413
f47c11ee 14414 tg3_full_lock(tp, 0);
944d980e 14415 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14416 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14417 tg3_full_unlock(tp);
1da177e4 14418
12dac075
RW		 14419 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14420
14421 err = tg3_set_power_state(tp, target_state);
1da177e4 14422 if (err) {
b02fd9e3
MC		 14423 int err2;
14424
f47c11ee 14425 tg3_full_lock(tp, 0);
1da177e4 14426
6a9eba15 14427 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14428 err2 = tg3_restart_hw(tp, 1);
14429 if (err2)
b9ec6c1b 14430 goto out;
1da177e4
LT		 14431
14432 tp->timer.expires = jiffies + tp->timer_offset;
14433 add_timer(&tp->timer);
14434
14435 netif_device_attach(dev);
14436 tg3_netif_start(tp);
14437
b9ec6c1b 14438out:
f47c11ee 14439 tg3_full_unlock(tp);
b02fd9e3
MC		 14440
14441 if (!err2)
14442 tg3_phy_start(tp);
1da177e4
LT		 14443 }
14444
14445 return err;
14446}
14447
14448static int tg3_resume(struct pci_dev *pdev)
14449{
14450 struct net_device *dev = pci_get_drvdata(pdev);
14451 struct tg3 *tp = netdev_priv(dev);
14452 int err;
14453
3e0c95fd
MC		 14454 pci_restore_state(tp->pdev);
14455
1da177e4
LT		 14456 if (!netif_running(dev))
14457 return 0;
14458
bc1c7567 14459 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14460 if (err)
14461 return err;
14462
14463 netif_device_attach(dev);
14464
f47c11ee 14465 tg3_full_lock(tp, 0);
1da177e4 14466
6a9eba15 14467 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14468 err = tg3_restart_hw(tp, 1);
14469 if (err)
14470 goto out;
1da177e4
LT		 14471
14472 tp->timer.expires = jiffies + tp->timer_offset;
14473 add_timer(&tp->timer);
14474
1da177e4
LT		 14475 tg3_netif_start(tp);
14476
b9ec6c1b 14477out:
f47c11ee 14478 tg3_full_unlock(tp);
1da177e4 14479
b02fd9e3
MC		 14480 if (!err)
14481 tg3_phy_start(tp);
14482
b9ec6c1b 14483 return err;
1da177e4
LT		 14484}
14485
14486static struct pci_driver tg3_driver = {
14487 .name = DRV_MODULE_NAME,
14488 .id_table = tg3_pci_tbl,
14489 .probe = tg3_init_one,
14490 .remove = __devexit_p(tg3_remove_one),
14491 .suspend = tg3_suspend,
14492 .resume = tg3_resume
14493};
14494
14495static int __init tg3_init(void)
14496{
29917620 14497 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14498}
14499
14500static void __exit tg3_cleanup(void)
14501{
14502 pci_unregister_driver(&tg3_driver);
14503}
14504
14505module_init(tg3_init);
14506module_exit(tg3_cleanup);
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