]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tg3: Turn off the debug UART for 57765
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
cceea982
MC		 71#define DRV_MODULE_VERSION "3.105"
72#define DRV_MODULE_RELDATE "December 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
13185217
HK		 247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254 {}
1da177e4
LT		 255};
256
257MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
50da859d 259static const struct {
1da177e4
LT		 260 const char string[ETH_GSTRING_LEN];
261} ethtool_stats_keys[TG3_NUM_STATS] = {
262 { "rx_octets" },
263 { "rx_fragments" },
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
267 { "rx_fcs_errors" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
274 { "rx_jabbers" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
288
289 { "tx_octets" },
290 { "tx_collisions" },
291
292 { "tx_xon_sent" },
293 { "tx_xoff_sent" },
294 { "tx_flow_control" },
295 { "tx_mac_errors" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
298 { "tx_deferred" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
319 { "tx_discards" },
320 { "tx_errors" },
321
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
324 { "rxbds_empty" },
325 { "rx_discards" },
326 { "rx_errors" },
327 { "rx_threshold_hit" },
328
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
332
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
335 { "nic_irqs" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
338};
339
50da859d 340static const struct {
4cafd3f5
MC		 341 const char string[ETH_GSTRING_LEN];
342} ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
349};
350
b401e9e2
MC		 351static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354}
355
356static u32 tg3_read32(struct tg3 *tp, u32 off)
357{
6aa20a22 358 return (readl(tp->regs + off));
b401e9e2
MC		 359}
360
0d3031d9
MC		 361static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->aperegs + off);
364}
365
366static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367{
368 return (readl(tp->aperegs + off));
369}
370
1da177e4
LT		 371static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372{
6892914f
MC		 373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 379}
380
381static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382{
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
1da177e4
LT		 385}
386
6892914f 387static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 388{
6892914f
MC		 389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
399static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
66711e66 408 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
1da177e4 412 }
6892914f
MC		 413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427}
428
429static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430{
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439}
440
b401e9e2
MC		 441/* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 447{
b401e9e2
MC		 448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
1da177e4
LT		 464}
465
09ee929c
MC		 466static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467{
468 tp->write32_mbox(tp, off, val);
6892914f
MC		 469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
09ee929c
MC		 472}
473
20094930 474static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 475{
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482}
483
b5d3772c
MC		 484static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485{
486 return (readl(tp->regs + off + GRCMBOX_BASE));
487}
488
489static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off + GRCMBOX_BASE);
492}
493
20094930 494#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 495#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 496#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 498#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 499
500#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 501#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 503#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 504
505static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506{
6892914f
MC		 507 unsigned long flags;
508
b5d3772c
MC		 509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511 return;
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 528}
529
1da177e4
LT		 530static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536 *val = 0;
537 return;
538 }
539
6892914f 540 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 544
bbadf503
MC		 545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 } else {
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 }
6892914f 554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 555}
556
0d3031d9
MC		 557static void tg3_ape_lock_init(struct tg3 *tp)
558{
559 int i;
560
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
565}
566
567static int tg3_ape_lock(struct tg3 *tp, int locknum)
568{
569 int i, off;
570 int ret = 0;
571 u32 status;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return 0;
575
576 switch (locknum) {
77b483f1 577 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 off = 4 * locknum;
585
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
592 break;
593 udelay(10);
594 }
595
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
600
601 ret = -EBUSY;
602 }
603
604 return ret;
605}
606
607static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608{
609 int off;
610
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612 return;
613
614 switch (locknum) {
77b483f1 615 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 616 case TG3_APE_LOCK_MEM:
617 break;
618 default:
619 return;
620 }
621
622 off = 4 * locknum;
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624}
625
1da177e4
LT		 626static void tg3_disable_ints(struct tg3 *tp)
627{
89aeb3bc
MC		 628 int i;
629
1da177e4
LT		 630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 634}
635
1da177e4
LT		 636static void tg3_enable_ints(struct tg3 *tp)
637{
89aeb3bc
MC		 638 int i;
639 u32 coal_now = 0;
640
bbe832c0
MC		 641 tp->irq_sync = 0;
642 wmb();
643
1da177e4
LT		 644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 646
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 652
89aeb3bc
MC		 653 coal_now |= tnapi->coal_now;
654 }
f19af9c2
MC		 655
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660 else
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 663}
664
17375d25 665static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 666{
17375d25 667 struct tg3 *tp = tnapi->tp;
898a56f8 668 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 669 unsigned int work_exists = 0;
670
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
676 work_exists = 1;
677 }
678 /* check for RX/TX work to do */
f3f3f27e 679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 681 work_exists = 1;
682
683 return work_exists;
684}
685
17375d25 686/* tg3_int_reenable
04237ddd
MC		 687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
6aa20a22 689 * which reenables interrupts
1da177e4 690 */
17375d25 691static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 692{
17375d25
MC		 693 struct tg3 *tp = tnapi->tp;
694
898a56f8 695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 696 mmiowb();
697
fac9b83e
DM		 698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
701 */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 703 tg3_has_work(tnapi))
04237ddd 704 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 706}
707
fed97810
MC		 708static void tg3_napi_disable(struct tg3 *tp)
709{
710 int i;
711
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
714}
715
716static void tg3_napi_enable(struct tg3 *tp)
717{
718 int i;
719
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
722}
723
1da177e4
LT		 724static inline void tg3_netif_stop(struct tg3 *tp)
725{
bbe832c0 726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 727 tg3_napi_disable(tp);
1da177e4
LT		 728 netif_tx_disable(tp->dev);
729}
730
731static inline void tg3_netif_start(struct tg3 *tp)
732{
fe5f5787
MC		 733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
1da177e4 736 */
fe5f5787
MC		 737 netif_tx_wake_all_queues(tp->dev);
738
fed97810
MC		 739 tg3_napi_enable(tp);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 741 tg3_enable_ints(tp);
1da177e4
LT		 742}
743
744static void tg3_switch_clocks(struct tg3 *tp)
745{
f6eb9b1f 746 u32 clock_ctrl;
1da177e4
LT		 747 u32 orig_clock_ctrl;
748
795d01c5
MC		 749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 751 return;
752
f6eb9b1f
MC		 753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
1da177e4
LT		 755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
758 0x1f);
759 tp->pci_clock_ctrl = clock_ctrl;
760
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 765 }
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl |
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770 40);
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
773 40);
1da177e4 774 }
b401e9e2 775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 776}
777
778#define PHY_BUSY_LOOPS 5000
779
780static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781{
782 u32 frame_val;
783 unsigned int loops;
784 int ret;
785
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787 tw32_f(MAC_MI_MODE,
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789 udelay(80);
790 }
791
792 *val = 0x0;
793
882e9793 794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 799
1da177e4
LT		 800 tw32_f(MAC_MI_COM, frame_val);
801
802 loops = PHY_BUSY_LOOPS;
803 while (loops != 0) {
804 udelay(10);
805 frame_val = tr32(MAC_MI_COM);
806
807 if ((frame_val & MI_COM_BUSY) == 0) {
808 udelay(5);
809 frame_val = tr32(MAC_MI_COM);
810 break;
811 }
812 loops -= 1;
813 }
814
815 ret = -EBUSY;
816 if (loops != 0) {
817 *val = frame_val & MI_COM_DATA_MASK;
818 ret = 0;
819 }
820
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
823 udelay(80);
824 }
825
826 return ret;
827}
828
829static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830{
831 u32 frame_val;
832 unsigned int loops;
833 int ret;
834
7f97a4bd 835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837 return 0;
838
1da177e4
LT		 839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840 tw32_f(MAC_MI_MODE,
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842 udelay(80);
843 }
844
882e9793 845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 851
1da177e4
LT		 852 tw32_f(MAC_MI_COM, frame_val);
853
854 loops = PHY_BUSY_LOOPS;
855 while (loops != 0) {
856 udelay(10);
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
859 udelay(5);
860 frame_val = tr32(MAC_MI_COM);
861 break;
862 }
863 loops -= 1;
864 }
865
866 ret = -EBUSY;
867 if (loops != 0)
868 ret = 0;
869
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
872 udelay(80);
873 }
874
875 return ret;
876}
877
95e2869a
MC		 878static int tg3_bmcr_reset(struct tg3 *tp)
879{
880 u32 phy_control;
881 int limit, err;
882
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
885 */
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
888 if (err != 0)
889 return -EBUSY;
890
891 limit = 5000;
892 while (limit--) {
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 if ((phy_control & BMCR_RESET) == 0) {
898 udelay(40);
899 break;
900 }
901 udelay(10);
902 }
d4675b52 903 if (limit < 0)
95e2869a
MC		 904 return -EBUSY;
905
906 return 0;
907}
908
158d7abd
MC		 909static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910{
3d16543d 911 struct tg3 *tp = bp->priv;
158d7abd
MC		 912 u32 val;
913
24bb4fb6 914 spin_lock_bh(&tp->lock);
158d7abd
MC		 915
916 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 917 val = -EIO;
918
919 spin_unlock_bh(&tp->lock);
158d7abd
MC		 920
921 return val;
922}
923
924static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925{
3d16543d 926 struct tg3 *tp = bp->priv;
24bb4fb6 927 u32 ret = 0;
158d7abd 928
24bb4fb6 929 spin_lock_bh(&tp->lock);
158d7abd
MC		 930
931 if (tg3_writephy(tp, reg, val))
24bb4fb6 932 ret = -EIO;
158d7abd 933
24bb4fb6
MC		 934 spin_unlock_bh(&tp->lock);
935
936 return ret;
158d7abd
MC		 937}
938
939static int tg3_mdio_reset(struct mii_bus *bp)
940{
941 return 0;
942}
943
9c61d6bc 944static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 945{
946 u32 val;
fcb389df 947 struct phy_device *phydev;
a9daf367 948
3f0e3ad7 949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
c73430d0 952 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 953 val = MAC_PHYCFG2_50610_LED_MODES;
954 break;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960 break;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963 break;
964 default:
a9daf367 965 return;
fcb389df
MC		 966 }
967
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
970
971 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 975 tw32(MAC_PHYCFG1, val);
976
977 return;
978 }
979
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
987
988 tw32(MAC_PHYCFG2, val);
a9daf367 989
bb85fbb6
MC		 990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998 }
bb85fbb6
MC		 999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
a9daf367 1002
a9daf367
MC		 1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
fcb389df 1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1021 }
1022 tw32(MAC_EXT_RGMII_MODE, val);
1023}
1024
158d7abd
MC		 1025static void tg3_mdio_start(struct tg3 *tp)
1026{
158d7abd
MC		 1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1029 udelay(80);
a9daf367 1030
882e9793
MC		 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1033
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035 if (funcnum)
1036 tp->phy_addr = 2;
1037 else
1038 tp->phy_addr = 1;
1039
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041 if (is_serdes)
1042 tp->phy_addr += 7;
1043 } else
3f0e3ad7 1044 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1045
9c61d6bc
MC		 1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
158d7abd
MC		 1049}
1050
158d7abd
MC		 1051static int tg3_mdio_init(struct tg3 *tp)
1052{
1053 int i;
1054 u32 reg;
a9daf367 1055 struct phy_device *phydev;
158d7abd
MC		 1056
1057 tg3_mdio_start(tp);
1058
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061 return 0;
1062
298cf9be
LB		 1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1065 return -ENOMEM;
158d7abd 1066
298cf9be
LB		 1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1077
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1079 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1080
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1085 */
1086 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087 tg3_bmcr_reset(tp);
1088
298cf9be 1089 i = mdiobus_register(tp->mdio_bus);
a9daf367 1090 if (i) {
158d7abd
MC		 1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092 tp->dev->name, i);
9c61d6bc 1093 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1094 return i;
1095 }
158d7abd 1096
3f0e3ad7 1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1098
9c61d6bc
MC		 1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1103 return -ENODEV;
1104 }
1105
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1110 break;
a9daf367 1111 case TG3_PHY_ID_BCM50610:
c73430d0 1112 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1114 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1123 /* fallthru */
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1126 break;
fcb389df 1127 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1132 break;
1133 }
1134
9c61d6bc
MC		 1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
a9daf367
MC		 1139
1140 return 0;
158d7abd
MC		 1141}
1142
1143static void tg3_mdio_fini(struct tg3 *tp)
1144{
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1149 }
1150}
1151
4ba526ce
MC		 1152/* tp->lock is held. */
1153static inline void tg3_generate_fw_event(struct tg3 *tp)
1154{
1155 u32 val;
1156
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161 tp->last_event_jiffies = jiffies;
1162}
1163
1164#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
95e2869a
MC		 1166/* tp->lock is held. */
1167static void tg3_wait_for_event_ack(struct tg3 *tp)
1168{
1169 int i;
4ba526ce
MC		 1170 unsigned int delay_cnt;
1171 long time_remain;
1172
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176 (long)jiffies;
1177 if (time_remain < 0)
1178 return;
1179
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1185
4ba526ce 1186 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188 break;
4ba526ce 1189 udelay(8);
95e2869a
MC		 1190 }
1191}
1192
1193/* tp->lock is held. */
1194static void tg3_ump_link_report(struct tg3 *tp)
1195{
1196 u32 reg;
1197 u32 val;
1198
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1201 return;
1202
1203 tg3_wait_for_event_ack(tp);
1204
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209 val = 0;
1210 if (!tg3_readphy(tp, MII_BMCR, &reg))
1211 val = reg << 16;
1212 if (!tg3_readphy(tp, MII_BMSR, &reg))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216 val = 0;
1217 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218 val = reg << 16;
1219 if (!tg3_readphy(tp, MII_LPA, &reg))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223 val = 0;
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226 val = reg << 16;
1227 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228 val |= (reg & 0xffff);
1229 }
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233 val = reg << 16;
1234 else
1235 val = 0;
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
4ba526ce 1238 tg3_generate_fw_event(tp);
95e2869a
MC		 1239}
1240
1241static void tg3_link_report(struct tg3 *tp)
1242{
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1246 tp->dev->name);
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250 tp->dev->name,
1251 (tp->link_config.active_speed == SPEED_1000 ?
1252 1000 :
1253 (tp->link_config.active_speed == SPEED_100 ?
1254 100 : 10)),
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1256 "full" : "half"));
1257
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1260 tp->dev->name,
e18ce346 1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1262 "on" : "off",
e18ce346 1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1264 "on" : "off");
1265 tg3_ump_link_report(tp);
1266 }
1267}
1268
1269static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270{
1271 u16 miireg;
1272
e18ce346 1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1274 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1275 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1276 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1277 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279 else
1280 miireg = 0;
1281
1282 return miireg;
1283}
1284
1285static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286{
1287 u16 miireg;
1288
e18ce346 1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1290 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1291 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1292 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1293 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295 else
1296 miireg = 0;
1297
1298 return miireg;
1299}
1300
95e2869a
MC		 1301static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302{
1303 u8 cap = 0;
1304
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1310 cap = FLOW_CTRL_RX;
95e2869a
MC		 1311 } else {
1312 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1314 }
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1317 cap = FLOW_CTRL_TX;
95e2869a
MC		 1318 }
1319
1320 return cap;
1321}
1322
f51f3562 1323static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1324{
b02fd9e3 1325 u8 autoneg;
f51f3562 1326 u8 flowctrl = 0;
95e2869a
MC		 1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1329
b02fd9e3 1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1332 else
1333 autoneg = tp->link_config.autoneg;
1334
1335 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1339 else
bc02ff95 1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1341 } else
1342 flowctrl = tp->link_config.flowctrl;
95e2869a 1343
f51f3562 1344 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1345
e18ce346 1346 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348 else
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
f51f3562 1351 if (old_rx_mode != tp->rx_mode)
95e2869a 1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1353
e18ce346 1354 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356 else
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
f51f3562 1359 if (old_tx_mode != tp->tx_mode)
95e2869a 1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1361}
1362
b02fd9e3
MC		 1363static void tg3_adjust_link(struct net_device *dev)
1364{
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1369
24bb4fb6 1370 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1371
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1374
1375 oldflowctrl = tp->link_config.active_flowctrl;
1376
1377 if (phydev->link) {
1378 lcl_adv = 0;
1379 rmt_adv = 0;
1380
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1386 else
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1388
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1391 else {
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1394
1395 if (phydev->pause)
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1399 }
1400
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402 } else
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1408 udelay(40);
1409 }
1410
fcb389df
MC		 1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1413 tw32(MAC_MI_STAT,
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416 else
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418 }
1419
b02fd9e3
MC		 1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425 else
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1436 linkmesg = 1;
1437
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1440
24bb4fb6 1441 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1442
1443 if (linkmesg)
1444 tg3_link_report(tp);
1445}
1446
1447static int tg3_phy_init(struct tg3 *tp)
1448{
1449 struct phy_device *phydev;
1450
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452 return 0;
1453
1454 /* Bring the PHY back to a known state. */
1455 tg3_bmcr_reset(tp);
1456
3f0e3ad7 1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1458
1459 /* Attach the MAC to the PHY. */
fb28ad35 1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1461 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1465 }
1466
b02fd9e3 1467 /* Mask with MAC supported features. */
9c61d6bc
MC		 1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1473 SUPPORTED_Pause |
1474 SUPPORTED_Asym_Pause);
1475 break;
1476 }
1477 /* fallthru */
9c61d6bc
MC		 1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 default:
3f0e3ad7 1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1485 return -EINVAL;
1486 }
1487
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1489
1490 phydev->advertising = phydev->supported;
1491
b02fd9e3
MC		 1492 return 0;
1493}
1494
1495static void tg3_phy_start(struct tg3 *tp)
1496{
1497 struct phy_device *phydev;
1498
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1503
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1510 }
1511
1512 phy_start(phydev);
1513
1514 phy_start_aneg(phydev);
1515}
1516
1517static void tg3_phy_stop(struct tg3 *tp)
1518{
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520 return;
1521
3f0e3ad7 1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1523}
1524
1525static void tg3_phy_fini(struct tg3 *tp)
1526{
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530 }
1531}
1532
b2a5c19c
MC		 1533static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534{
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537}
1538
7f97a4bd
MC		 1539static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 phytest;
1542
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544 u32 phy;
1545
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549 if (enable)
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551 else
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554 }
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556 }
1557}
1558
6833c043
MC		 1559static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560{
1561 u32 reg;
1562
ecf1410b
MC		 1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1564 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1565 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1566 return;
1567
7f97a4bd
MC		 1568 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1569 tg3_phy_fet_toggle_apd(tp, enable);
1570 return;
1571 }
1572
6833c043
MC		 1573 reg = MII_TG3_MISC_SHDW_WREN |
1574 MII_TG3_MISC_SHDW_SCR5_SEL |
1575 MII_TG3_MISC_SHDW_SCR5_LPED |
1576 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1577 MII_TG3_MISC_SHDW_SCR5_SDTL |
1578 MII_TG3_MISC_SHDW_SCR5_C125OE;
1579 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1580 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1581
1582 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1583
1584
1585 reg = MII_TG3_MISC_SHDW_WREN |
1586 MII_TG3_MISC_SHDW_APD_SEL |
1587 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1588 if (enable)
1589 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1590
1591 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592}
1593
9ef8ca99
MC		 1594static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1595{
1596 u32 phy;
1597
1598 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1599 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1600 return;
1601
7f97a4bd 1602 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1603 u32 ephy;
1604
535ef6e1
MC		 1605 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1606 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1607
1608 tg3_writephy(tp, MII_TG3_FET_TEST,
1609 ephy | MII_TG3_FET_SHADOW_EN);
1610 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1611 if (enable)
535ef6e1 1612 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1613 else
535ef6e1
MC		 1614 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1615 tg3_writephy(tp, reg, phy);
9ef8ca99 1616 }
535ef6e1 1617 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1618 }
1619 } else {
1620 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1621 MII_TG3_AUXCTL_SHDWSEL_MISC;
1622 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1623 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1624 if (enable)
1625 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 else
1627 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1628 phy |= MII_TG3_AUXCTL_MISC_WREN;
1629 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1630 }
1631 }
1632}
1633
1da177e4
LT		 1634static void tg3_phy_set_wirespeed(struct tg3 *tp)
1635{
1636 u32 val;
1637
1638 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1639 return;
1640
1641 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1642 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1643 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1644 (val | (1 << 15) | (1 << 4)));
1645}
1646
b2a5c19c
MC		 1647static void tg3_phy_apply_otp(struct tg3 *tp)
1648{
1649 u32 otp, phy;
1650
1651 if (!tp->phy_otp)
1652 return;
1653
1654 otp = tp->phy_otp;
1655
1656 /* Enable SM_DSP clock and tx 6dB coding. */
1657 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1658 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1659 MII_TG3_AUXCTL_ACTL_TX_6DB;
1660 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1661
1662 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1663 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1664 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1665
1666 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1667 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1668 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1669
1670 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1671 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1672 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1673
1674 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1675 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1676
1677 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1678 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1679
1680 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1681 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1683
1684 /* Turn off SM_DSP clock. */
1685 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1686 MII_TG3_AUXCTL_ACTL_TX_6DB;
1687 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1688}
1689
1da177e4
LT		 1690static int tg3_wait_macro_done(struct tg3 *tp)
1691{
1692 int limit = 100;
1693
1694 while (limit--) {
1695 u32 tmp32;
1696
1697 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1698 if ((tmp32 & 0x1000) == 0)
1699 break;
1700 }
1701 }
d4675b52 1702 if (limit < 0)
1da177e4
LT		 1703 return -EBUSY;
1704
1705 return 0;
1706}
1707
1708static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1709{
1710 static const u32 test_pat[4][6] = {
1711 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1712 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1713 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1714 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1715 };
1716 int chan;
1717
1718 for (chan = 0; chan < 4; chan++) {
1719 int i;
1720
1721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1722 (chan * 0x2000) | 0x0200);
1723 tg3_writephy(tp, 0x16, 0x0002);
1724
1725 for (i = 0; i < 6; i++)
1726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1727 test_pat[chan][i]);
1728
1729 tg3_writephy(tp, 0x16, 0x0202);
1730 if (tg3_wait_macro_done(tp)) {
1731 *resetp = 1;
1732 return -EBUSY;
1733 }
1734
1735 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1736 (chan * 0x2000) | 0x0200);
1737 tg3_writephy(tp, 0x16, 0x0082);
1738 if (tg3_wait_macro_done(tp)) {
1739 *resetp = 1;
1740 return -EBUSY;
1741 }
1742
1743 tg3_writephy(tp, 0x16, 0x0802);
1744 if (tg3_wait_macro_done(tp)) {
1745 *resetp = 1;
1746 return -EBUSY;
1747 }
1748
1749 for (i = 0; i < 6; i += 2) {
1750 u32 low, high;
1751
1752 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1753 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1754 tg3_wait_macro_done(tp)) {
1755 *resetp = 1;
1756 return -EBUSY;
1757 }
1758 low &= 0x7fff;
1759 high &= 0x000f;
1760 if (low != test_pat[chan][i] ||
1761 high != test_pat[chan][i+1]) {
1762 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1764 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1765
1766 return -EBUSY;
1767 }
1768 }
1769 }
1770
1771 return 0;
1772}
1773
1774static int tg3_phy_reset_chanpat(struct tg3 *tp)
1775{
1776 int chan;
1777
1778 for (chan = 0; chan < 4; chan++) {
1779 int i;
1780
1781 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782 (chan * 0x2000) | 0x0200);
1783 tg3_writephy(tp, 0x16, 0x0002);
1784 for (i = 0; i < 6; i++)
1785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1786 tg3_writephy(tp, 0x16, 0x0202);
1787 if (tg3_wait_macro_done(tp))
1788 return -EBUSY;
1789 }
1790
1791 return 0;
1792}
1793
1794static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1795{
1796 u32 reg32, phy9_orig;
1797 int retries, do_phy_reset, err;
1798
1799 retries = 10;
1800 do_phy_reset = 1;
1801 do {
1802 if (do_phy_reset) {
1803 err = tg3_bmcr_reset(tp);
1804 if (err)
1805 return err;
1806 do_phy_reset = 0;
1807 }
1808
1809 /* Disable transmitter and interrupt. */
1810 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1811 continue;
1812
1813 reg32 |= 0x3000;
1814 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1815
1816 /* Set full-duplex, 1000 mbps. */
1817 tg3_writephy(tp, MII_BMCR,
1818 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1819
1820 /* Set to master mode. */
1821 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1822 continue;
1823
1824 tg3_writephy(tp, MII_TG3_CTRL,
1825 (MII_TG3_CTRL_AS_MASTER |
1826 MII_TG3_CTRL_ENABLE_AS_MASTER));
1827
1828 /* Enable SM_DSP_CLOCK and 6dB. */
1829 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1830
1831 /* Block the PHY control access. */
1832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1834
1835 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1836 if (!err)
1837 break;
1838 } while (--retries);
1839
1840 err = tg3_phy_reset_chanpat(tp);
1841 if (err)
1842 return err;
1843
1844 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1845 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1846
1847 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1848 tg3_writephy(tp, 0x16, 0x0000);
1849
1850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1852 /* Set Extended packet length bit for jumbo frames */
1853 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1854 }
1855 else {
1856 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1857 }
1858
1859 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1860
1861 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1862 reg32 &= ~0x3000;
1863 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1864 } else if (!err)
1865 err = -EBUSY;
1866
1867 return err;
1868}
1869
1870/* This will reset the tigon3 PHY if there is no valid
1871 * link unless the FORCE argument is non-zero.
1872 */
1873static int tg3_phy_reset(struct tg3 *tp)
1874{
b2a5c19c 1875 u32 cpmuctrl;
1da177e4
LT		 1876 u32 phy_status;
1877 int err;
1878
60189ddf
MC		 1879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1880 u32 val;
1881
1882 val = tr32(GRC_MISC_CFG);
1883 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1884 udelay(40);
1885 }
1da177e4
LT		 1886 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1887 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1888 if (err != 0)
1889 return -EBUSY;
1890
c8e1e82b
MC		 1891 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1892 netif_carrier_off(tp->dev);
1893 tg3_link_report(tp);
1894 }
1895
1da177e4
LT		 1896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1899 err = tg3_phy_reset_5703_4_5(tp);
1900 if (err)
1901 return err;
1902 goto out;
1903 }
1904
b2a5c19c
MC		 1905 cpmuctrl = 0;
1906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1907 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1908 cpmuctrl = tr32(TG3_CPMU_CTRL);
1909 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1910 tw32(TG3_CPMU_CTRL,
1911 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1912 }
1913
1da177e4
LT		 1914 err = tg3_bmcr_reset(tp);
1915 if (err)
1916 return err;
1917
b2a5c19c
MC		 1918 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1919 u32 phy;
1920
1921 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1922 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1923
1924 tw32(TG3_CPMU_CTRL, cpmuctrl);
1925 }
1926
bcb37f6c
MC		 1927 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1928 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1929 u32 val;
1930
1931 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1932 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1933 CPMU_LSPD_1000MB_MACCLK_12_5) {
1934 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1935 udelay(40);
1936 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1937 }
1938 }
1939
ecf1410b
MC		 1940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1941 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1942 return 0;
1943
b2a5c19c
MC		 1944 tg3_phy_apply_otp(tp);
1945
6833c043
MC		 1946 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1947 tg3_phy_toggle_apd(tp, true);
1948 else
1949 tg3_phy_toggle_apd(tp, false);
1950
1da177e4
LT		 1951out:
1952 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1953 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1955 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1956 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1958 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959 }
1960 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1961 tg3_writephy(tp, 0x1c, 0x8d68);
1962 tg3_writephy(tp, 0x1c, 0x8d68);
1963 }
1964 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1965 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1968 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1969 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1971 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1973 }
c424cb24
MC		 1974 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1975 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1977 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1979 tg3_writephy(tp, MII_TG3_TEST1,
1980 MII_TG3_TEST1_TRIM_EN | 0x4);
1981 } else
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984 }
1da177e4
LT		 1985 /* Set Extended packet length bit (bit 14) on all chips that */
1986 /* support jumbo frames */
1987 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1988 /* Cannot do read-modify-write on 5401 */
1989 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1990 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1991 u32 phy_reg;
1992
1993 /* Set bit 14 with read-modify-write to preserve other bits */
1994 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1995 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1996 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1997 }
1998
1999 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2000 * jumbo frames transmission.
2001 */
8f666b07 2002 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2003 u32 phy_reg;
2004
2005 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2006 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2007 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2008 }
2009
715116a1 2010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2011 /* adjust output voltage */
535ef6e1 2012 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2013 }
2014
9ef8ca99 2015 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2016 tg3_phy_set_wirespeed(tp);
2017 return 0;
2018}
2019
2020static void tg3_frob_aux_power(struct tg3 *tp)
2021{
2022 struct tg3 *tp_peer = tp;
2023
9d26e213 2024 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2025 return;
2026
f6eb9b1f
MC		 2027 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2030 struct net_device *dev_peer;
2031
2032 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2033 /* remove_one() may have been run on the peer. */
8c2dc7e1 2034 if (!dev_peer)
bc1c7567
MC		 2035 tp_peer = tp;
2036 else
2037 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2038 }
2039
1da177e4 2040 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2041 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2042 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2043 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2046 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2047 (GRC_LCLCTRL_GPIO_OE0 |
2048 GRC_LCLCTRL_GPIO_OE1 |
2049 GRC_LCLCTRL_GPIO_OE2 |
2050 GRC_LCLCTRL_GPIO_OUTPUT0 |
2051 GRC_LCLCTRL_GPIO_OUTPUT1),
2052 100);
8d519ab2
MC		 2053 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2054 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2055 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2056 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2057 GRC_LCLCTRL_GPIO_OE1 |
2058 GRC_LCLCTRL_GPIO_OE2 |
2059 GRC_LCLCTRL_GPIO_OUTPUT0 |
2060 GRC_LCLCTRL_GPIO_OUTPUT1 |
2061 tp->grc_local_ctrl;
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2063
2064 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2065 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2066
2067 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2068 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2069 } else {
2070 u32 no_gpio2;
dc56b7d4 2071 u32 grc_local_ctrl = 0;
1da177e4
LT		 2072
2073 if (tp_peer != tp &&
2074 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2075 return;
2076
dc56b7d4
MC		 2077 /* Workaround to prevent overdrawing Amps. */
2078 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2079 ASIC_REV_5714) {
2080 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2081 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2082 grc_local_ctrl, 100);
dc56b7d4
MC		 2083 }
2084
1da177e4
LT		 2085 /* On 5753 and variants, GPIO2 cannot be used. */
2086 no_gpio2 = tp->nic_sram_data_cfg &
2087 NIC_SRAM_DATA_CFG_NO_GPIO2;
2088
dc56b7d4 2089 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2090 GRC_LCLCTRL_GPIO_OE1 |
2091 GRC_LCLCTRL_GPIO_OE2 |
2092 GRC_LCLCTRL_GPIO_OUTPUT1 |
2093 GRC_LCLCTRL_GPIO_OUTPUT2;
2094 if (no_gpio2) {
2095 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2096 GRC_LCLCTRL_GPIO_OUTPUT2);
2097 }
b401e9e2
MC		 2098 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099 grc_local_ctrl, 100);
1da177e4
LT		 2100
2101 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2102
b401e9e2
MC		 2103 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104 grc_local_ctrl, 100);
1da177e4
LT		 2105
2106 if (!no_gpio2) {
2107 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109 grc_local_ctrl, 100);
1da177e4
LT		 2110 }
2111 }
2112 } else {
2113 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2114 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2115 if (tp_peer != tp &&
2116 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2117 return;
2118
b401e9e2
MC		 2119 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2120 (GRC_LCLCTRL_GPIO_OE1 |
2121 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2122
b401e9e2
MC		 2123 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2124 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2125
b401e9e2
MC		 2126 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127 (GRC_LCLCTRL_GPIO_OE1 |
2128 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2129 }
2130 }
2131}
2132
e8f3f6ca
MC		 2133static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2134{
2135 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2136 return 1;
2137 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2138 if (speed != SPEED_10)
2139 return 1;
2140 } else if (speed == SPEED_10)
2141 return 1;
2142
2143 return 0;
2144}
2145
1da177e4
LT		 2146static int tg3_setup_phy(struct tg3 *, int);
2147
2148#define RESET_KIND_SHUTDOWN 0
2149#define RESET_KIND_INIT 1
2150#define RESET_KIND_SUSPEND 2
2151
2152static void tg3_write_sig_post_reset(struct tg3 *, int);
2153static int tg3_halt_cpu(struct tg3 *, u32);
2154
0a459aac 2155static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2156{
ce057f01
MC		 2157 u32 val;
2158
5129724a
MC		 2159 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2160 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2161 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2162 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2163
2164 sg_dig_ctrl |=
2165 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2166 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2167 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2168 }
3f7045c1 2169 return;
5129724a 2170 }
3f7045c1 2171
60189ddf 2172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2173 tg3_bmcr_reset(tp);
2174 val = tr32(GRC_MISC_CFG);
2175 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2176 udelay(40);
2177 return;
0e5f784c
MC		 2178 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2179 u32 phytest;
2180 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2181 u32 phy;
2182
2183 tg3_writephy(tp, MII_ADVERTISE, 0);
2184 tg3_writephy(tp, MII_BMCR,
2185 BMCR_ANENABLE | BMCR_ANRESTART);
2186
2187 tg3_writephy(tp, MII_TG3_FET_TEST,
2188 phytest | MII_TG3_FET_SHADOW_EN);
2189 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2190 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2191 tg3_writephy(tp,
2192 MII_TG3_FET_SHDW_AUXMODE4,
2193 phy);
2194 }
2195 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2196 }
2197 return;
0a459aac 2198 } else if (do_low_power) {
715116a1
MC		 2199 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2200 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2201
2202 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2203 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2204 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2205 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2206 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2207 }
3f7045c1 2208
15c3b696
MC		 2209 /* The PHY should not be powered down on some chips because
2210 * of bugs.
2211 */
2212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2214 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2215 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2216 return;
ce057f01 2217
bcb37f6c
MC		 2218 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2219 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2220 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2221 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2222 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2223 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2224 }
2225
15c3b696
MC		 2226 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2227}
2228
ffbcfed4
MC		 2229/* tp->lock is held. */
2230static int tg3_nvram_lock(struct tg3 *tp)
2231{
2232 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2233 int i;
2234
2235 if (tp->nvram_lock_cnt == 0) {
2236 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2237 for (i = 0; i < 8000; i++) {
2238 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2239 break;
2240 udelay(20);
2241 }
2242 if (i == 8000) {
2243 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2244 return -ENODEV;
2245 }
2246 }
2247 tp->nvram_lock_cnt++;
2248 }
2249 return 0;
2250}
2251
2252/* tp->lock is held. */
2253static void tg3_nvram_unlock(struct tg3 *tp)
2254{
2255 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2256 if (tp->nvram_lock_cnt > 0)
2257 tp->nvram_lock_cnt--;
2258 if (tp->nvram_lock_cnt == 0)
2259 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2260 }
2261}
2262
2263/* tp->lock is held. */
2264static void tg3_enable_nvram_access(struct tg3 *tp)
2265{
2266 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2267 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2268 u32 nvaccess = tr32(NVRAM_ACCESS);
2269
2270 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2271 }
2272}
2273
2274/* tp->lock is held. */
2275static void tg3_disable_nvram_access(struct tg3 *tp)
2276{
2277 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2278 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2279 u32 nvaccess = tr32(NVRAM_ACCESS);
2280
2281 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2282 }
2283}
2284
2285static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2286 u32 offset, u32 *val)
2287{
2288 u32 tmp;
2289 int i;
2290
2291 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2292 return -EINVAL;
2293
2294 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2295 EEPROM_ADDR_DEVID_MASK |
2296 EEPROM_ADDR_READ);
2297 tw32(GRC_EEPROM_ADDR,
2298 tmp |
2299 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2300 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2301 EEPROM_ADDR_ADDR_MASK) |
2302 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2303
2304 for (i = 0; i < 1000; i++) {
2305 tmp = tr32(GRC_EEPROM_ADDR);
2306
2307 if (tmp & EEPROM_ADDR_COMPLETE)
2308 break;
2309 msleep(1);
2310 }
2311 if (!(tmp & EEPROM_ADDR_COMPLETE))
2312 return -EBUSY;
2313
62cedd11
MC		 2314 tmp = tr32(GRC_EEPROM_DATA);
2315
2316 /*
2317 * The data will always be opposite the native endian
2318 * format. Perform a blind byteswap to compensate.
2319 */
2320 *val = swab32(tmp);
2321
ffbcfed4
MC		 2322 return 0;
2323}
2324
2325#define NVRAM_CMD_TIMEOUT 10000
2326
2327static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2328{
2329 int i;
2330
2331 tw32(NVRAM_CMD, nvram_cmd);
2332 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2333 udelay(10);
2334 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2335 udelay(10);
2336 break;
2337 }
2338 }
2339
2340 if (i == NVRAM_CMD_TIMEOUT)
2341 return -EBUSY;
2342
2343 return 0;
2344}
2345
2346static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2347{
2348 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352 (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354 addr = ((addr / tp->nvram_pagesize) <<
2355 ATMEL_AT45DB0X1B_PAGE_POS) +
2356 (addr % tp->nvram_pagesize);
2357
2358 return addr;
2359}
2360
2361static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2362{
2363 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2364 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2365 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2366 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2367 (tp->nvram_jedecnum == JEDEC_ATMEL))
2368
2369 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2370 tp->nvram_pagesize) +
2371 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2372
2373 return addr;
2374}
2375
e4f34110
MC		 2376/* NOTE: Data read in from NVRAM is byteswapped according to
2377 * the byteswapping settings for all other register accesses.
2378 * tg3 devices are BE devices, so on a BE machine, the data
2379 * returned will be exactly as it is seen in NVRAM. On a LE
2380 * machine, the 32-bit value will be byteswapped.
2381 */
ffbcfed4
MC		 2382static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2383{
2384 int ret;
2385
2386 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2387 return tg3_nvram_read_using_eeprom(tp, offset, val);
2388
2389 offset = tg3_nvram_phys_addr(tp, offset);
2390
2391 if (offset > NVRAM_ADDR_MSK)
2392 return -EINVAL;
2393
2394 ret = tg3_nvram_lock(tp);
2395 if (ret)
2396 return ret;
2397
2398 tg3_enable_nvram_access(tp);
2399
2400 tw32(NVRAM_ADDR, offset);
2401 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2402 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2403
2404 if (ret == 0)
e4f34110 2405 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2406
2407 tg3_disable_nvram_access(tp);
2408
2409 tg3_nvram_unlock(tp);
2410
2411 return ret;
2412}
2413
a9dc529d
MC		 2414/* Ensures NVRAM data is in bytestream format. */
2415static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2416{
2417 u32 v;
a9dc529d 2418 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2419 if (!res)
a9dc529d 2420 *val = cpu_to_be32(v);
ffbcfed4
MC		 2421 return res;
2422}
2423
3f007891
MC		 2424/* tp->lock is held. */
2425static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2426{
2427 u32 addr_high, addr_low;
2428 int i;
2429
2430 addr_high = ((tp->dev->dev_addr[0] << 8) |
2431 tp->dev->dev_addr[1]);
2432 addr_low = ((tp->dev->dev_addr[2] << 24) |
2433 (tp->dev->dev_addr[3] << 16) |
2434 (tp->dev->dev_addr[4] << 8) |
2435 (tp->dev->dev_addr[5] << 0));
2436 for (i = 0; i < 4; i++) {
2437 if (i == 1 && skip_mac_1)
2438 continue;
2439 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2440 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2441 }
2442
2443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2445 for (i = 0; i < 12; i++) {
2446 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2447 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2448 }
2449 }
2450
2451 addr_high = (tp->dev->dev_addr[0] +
2452 tp->dev->dev_addr[1] +
2453 tp->dev->dev_addr[2] +
2454 tp->dev->dev_addr[3] +
2455 tp->dev->dev_addr[4] +
2456 tp->dev->dev_addr[5]) &
2457 TX_BACKOFF_SEED_MASK;
2458 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2459}
2460
bc1c7567 2461static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2462{
2463 u32 misc_host_ctrl;
0a459aac 2464 bool device_should_wake, do_low_power;
1da177e4
LT		 2465
2466 /* Make sure register accesses (indirect or otherwise)
2467 * will function correctly.
2468 */
2469 pci_write_config_dword(tp->pdev,
2470 TG3PCI_MISC_HOST_CTRL,
2471 tp->misc_host_ctrl);
2472
1da177e4 2473 switch (state) {
bc1c7567 2474 case PCI_D0:
12dac075
RW		 2475 pci_enable_wake(tp->pdev, state, false);
2476 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2477
9d26e213
MC		 2478 /* Switch out of Vaux if it is a NIC */
2479 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2480 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2481
2482 return 0;
2483
bc1c7567 2484 case PCI_D1:
bc1c7567 2485 case PCI_D2:
bc1c7567 2486 case PCI_D3hot:
1da177e4
LT		 2487 break;
2488
2489 default:
12dac075
RW		 2490 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2491 tp->dev->name, state);
1da177e4 2492 return -EINVAL;
855e1111 2493 }
5e7dfd0f
MC		 2494
2495 /* Restore the CLKREQ setting. */
2496 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2497 u16 lnkctl;
2498
2499 pci_read_config_word(tp->pdev,
2500 tp->pcie_cap + PCI_EXP_LNKCTL,
2501 &lnkctl);
2502 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2503 pci_write_config_word(tp->pdev,
2504 tp->pcie_cap + PCI_EXP_LNKCTL,
2505 lnkctl);
2506 }
2507
1da177e4
LT		 2508 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2509 tw32(TG3PCI_MISC_HOST_CTRL,
2510 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2511
05ac4cb7
MC		 2512 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2513 device_may_wakeup(&tp->pdev->dev) &&
2514 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2515
dd477003 2516 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2517 do_low_power = false;
b02fd9e3
MC		 2518 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2519 !tp->link_config.phy_is_low_power) {
2520 struct phy_device *phydev;
0a459aac 2521 u32 phyid, advertising;
b02fd9e3 2522
3f0e3ad7 2523 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2524
2525 tp->link_config.phy_is_low_power = 1;
2526
2527 tp->link_config.orig_speed = phydev->speed;
2528 tp->link_config.orig_duplex = phydev->duplex;
2529 tp->link_config.orig_autoneg = phydev->autoneg;
2530 tp->link_config.orig_advertising = phydev->advertising;
2531
2532 advertising = ADVERTISED_TP |
2533 ADVERTISED_Pause |
2534 ADVERTISED_Autoneg |
2535 ADVERTISED_10baseT_Half;
2536
2537 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2538 device_should_wake) {
b02fd9e3
MC		 2539 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2540 advertising |=
2541 ADVERTISED_100baseT_Half |
2542 ADVERTISED_100baseT_Full |
2543 ADVERTISED_10baseT_Full;
2544 else
2545 advertising |= ADVERTISED_10baseT_Full;
2546 }
2547
2548 phydev->advertising = advertising;
2549
2550 phy_start_aneg(phydev);
0a459aac
MC		 2551
2552 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2553 if (phyid != TG3_PHY_ID_BCMAC131) {
2554 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2555 if (phyid == TG3_PHY_OUI_1 ||
2556 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2557 phyid == TG3_PHY_OUI_3)
2558 do_low_power = true;
2559 }
b02fd9e3 2560 }
dd477003 2561 } else {
2023276e 2562 do_low_power = true;
0a459aac 2563
dd477003
MC		 2564 if (tp->link_config.phy_is_low_power == 0) {
2565 tp->link_config.phy_is_low_power = 1;
2566 tp->link_config.orig_speed = tp->link_config.speed;
2567 tp->link_config.orig_duplex = tp->link_config.duplex;
2568 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2569 }
1da177e4 2570
dd477003
MC		 2571 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2572 tp->link_config.speed = SPEED_10;
2573 tp->link_config.duplex = DUPLEX_HALF;
2574 tp->link_config.autoneg = AUTONEG_ENABLE;
2575 tg3_setup_phy(tp, 0);
2576 }
1da177e4
LT		 2577 }
2578
b5d3772c
MC		 2579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2580 u32 val;
2581
2582 val = tr32(GRC_VCPU_EXT_CTRL);
2583 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2584 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2585 int i;
2586 u32 val;
2587
2588 for (i = 0; i < 200; i++) {
2589 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2590 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2591 break;
2592 msleep(1);
2593 }
2594 }
a85feb8c
GZ		 2595 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2596 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2597 WOL_DRV_STATE_SHUTDOWN |
2598 WOL_DRV_WOL |
2599 WOL_SET_MAGIC_PKT);
6921d201 2600
05ac4cb7 2601 if (device_should_wake) {
1da177e4
LT		 2602 u32 mac_mode;
2603
2604 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2605 if (do_low_power) {
dd477003
MC		 2606 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2607 udelay(40);
2608 }
1da177e4 2609
3f7045c1
MC		 2610 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2611 mac_mode = MAC_MODE_PORT_MODE_GMII;
2612 else
2613 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2614
e8f3f6ca
MC		 2615 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2616 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2617 ASIC_REV_5700) {
2618 u32 speed = (tp->tg3_flags &
2619 TG3_FLAG_WOL_SPEED_100MB) ?
2620 SPEED_100 : SPEED_10;
2621 if (tg3_5700_link_polarity(tp, speed))
2622 mac_mode |= MAC_MODE_LINK_POLARITY;
2623 else
2624 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2625 }
1da177e4
LT		 2626 } else {
2627 mac_mode = MAC_MODE_PORT_MODE_TBI;
2628 }
2629
cbf46853 2630 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2631 tw32(MAC_LED_CTRL, tp->led_ctrl);
2632
05ac4cb7
MC		 2633 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2634 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2635 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2636 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2637 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2638 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2639
3bda1258
MC		 2640 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2641 mac_mode |= tp->mac_mode &
2642 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2643 if (mac_mode & MAC_MODE_APE_TX_EN)
2644 mac_mode |= MAC_MODE_TDE_ENABLE;
2645 }
2646
1da177e4
LT		 2647 tw32_f(MAC_MODE, mac_mode);
2648 udelay(100);
2649
2650 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2651 udelay(10);
2652 }
2653
2654 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2655 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2657 u32 base_val;
2658
2659 base_val = tp->pci_clock_ctrl;
2660 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2661 CLOCK_CTRL_TXCLK_DISABLE);
2662
b401e9e2
MC		 2663 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2664 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2665 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2666 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2667 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2668 /* do nothing */
85e94ced 2669 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2670 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2671 u32 newbits1, newbits2;
2672
2673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2675 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2676 CLOCK_CTRL_TXCLK_DISABLE |
2677 CLOCK_CTRL_ALTCLK);
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2680 newbits1 = CLOCK_CTRL_625_CORE;
2681 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2682 } else {
2683 newbits1 = CLOCK_CTRL_ALTCLK;
2684 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2685 }
2686
b401e9e2
MC		 2687 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2688 40);
1da177e4 2689
b401e9e2
MC		 2690 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2691 40);
1da177e4
LT		 2692
2693 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2694 u32 newbits3;
2695
2696 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2697 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2698 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2699 CLOCK_CTRL_TXCLK_DISABLE |
2700 CLOCK_CTRL_44MHZ_CORE);
2701 } else {
2702 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2703 }
2704
b401e9e2
MC		 2705 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2706 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2707 }
2708 }
2709
05ac4cb7 2710 if (!(device_should_wake) &&
22435849 2711 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2712 tg3_power_down_phy(tp, do_low_power);
6921d201 2713
1da177e4
LT		 2714 tg3_frob_aux_power(tp);
2715
2716 /* Workaround for unstable PLL clock */
2717 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2718 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2719 u32 val = tr32(0x7d00);
2720
2721 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2722 tw32(0x7d00, val);
6921d201 2723 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2724 int err;
2725
2726 err = tg3_nvram_lock(tp);
1da177e4 2727 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2728 if (!err)
2729 tg3_nvram_unlock(tp);
6921d201 2730 }
1da177e4
LT		 2731 }
2732
bbadf503
MC		 2733 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2734
05ac4cb7 2735 if (device_should_wake)
12dac075
RW		 2736 pci_enable_wake(tp->pdev, state, true);
2737
1da177e4 2738 /* Finally, set the new power state. */
12dac075 2739 pci_set_power_state(tp->pdev, state);
1da177e4 2740
1da177e4
LT		 2741 return 0;
2742}
2743
1da177e4
LT		 2744static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2745{
2746 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2747 case MII_TG3_AUX_STAT_10HALF:
2748 *speed = SPEED_10;
2749 *duplex = DUPLEX_HALF;
2750 break;
2751
2752 case MII_TG3_AUX_STAT_10FULL:
2753 *speed = SPEED_10;
2754 *duplex = DUPLEX_FULL;
2755 break;
2756
2757 case MII_TG3_AUX_STAT_100HALF:
2758 *speed = SPEED_100;
2759 *duplex = DUPLEX_HALF;
2760 break;
2761
2762 case MII_TG3_AUX_STAT_100FULL:
2763 *speed = SPEED_100;
2764 *duplex = DUPLEX_FULL;
2765 break;
2766
2767 case MII_TG3_AUX_STAT_1000HALF:
2768 *speed = SPEED_1000;
2769 *duplex = DUPLEX_HALF;
2770 break;
2771
2772 case MII_TG3_AUX_STAT_1000FULL:
2773 *speed = SPEED_1000;
2774 *duplex = DUPLEX_FULL;
2775 break;
2776
2777 default:
7f97a4bd 2778 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2779 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2780 SPEED_10;
2781 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2782 DUPLEX_HALF;
2783 break;
2784 }
1da177e4
LT		 2785 *speed = SPEED_INVALID;
2786 *duplex = DUPLEX_INVALID;
2787 break;
855e1111 2788 }
1da177e4
LT		 2789}
2790
2791static void tg3_phy_copper_begin(struct tg3 *tp)
2792{
2793 u32 new_adv;
2794 int i;
2795
2796 if (tp->link_config.phy_is_low_power) {
2797 /* Entering low power mode. Disable gigabit and
2798 * 100baseT advertisements.
2799 */
2800 tg3_writephy(tp, MII_TG3_CTRL, 0);
2801
2802 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2803 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2804 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2805 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2806
2807 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2808 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2809 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2810 tp->link_config.advertising &=
2811 ~(ADVERTISED_1000baseT_Half |
2812 ADVERTISED_1000baseT_Full);
2813
ba4d07a8 2814 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2815 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2816 new_adv |= ADVERTISE_10HALF;
2817 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2818 new_adv |= ADVERTISE_10FULL;
2819 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2820 new_adv |= ADVERTISE_100HALF;
2821 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2822 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2823
2824 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2825
1da177e4
LT		 2826 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827
2828 if (tp->link_config.advertising &
2829 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2830 new_adv = 0;
2831 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2832 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2833 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2834 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2835 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2836 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2837 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2838 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2839 MII_TG3_CTRL_ENABLE_AS_MASTER);
2840 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2841 } else {
2842 tg3_writephy(tp, MII_TG3_CTRL, 0);
2843 }
2844 } else {
ba4d07a8
MC		 2845 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2846 new_adv |= ADVERTISE_CSMA;
2847
1da177e4
LT		 2848 /* Asking for a specific link mode. */
2849 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2850 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851
2852 if (tp->link_config.duplex == DUPLEX_FULL)
2853 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2854 else
2855 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2856 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2857 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2858 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2859 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2860 } else {
1da177e4
LT		 2861 if (tp->link_config.speed == SPEED_100) {
2862 if (tp->link_config.duplex == DUPLEX_FULL)
2863 new_adv |= ADVERTISE_100FULL;
2864 else
2865 new_adv |= ADVERTISE_100HALF;
2866 } else {
2867 if (tp->link_config.duplex == DUPLEX_FULL)
2868 new_adv |= ADVERTISE_10FULL;
2869 else
2870 new_adv |= ADVERTISE_10HALF;
2871 }
2872 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2873
2874 new_adv = 0;
1da177e4 2875 }
ba4d07a8
MC		 2876
2877 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2878 }
2879
2880 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2881 tp->link_config.speed != SPEED_INVALID) {
2882 u32 bmcr, orig_bmcr;
2883
2884 tp->link_config.active_speed = tp->link_config.speed;
2885 tp->link_config.active_duplex = tp->link_config.duplex;
2886
2887 bmcr = 0;
2888 switch (tp->link_config.speed) {
2889 default:
2890 case SPEED_10:
2891 break;
2892
2893 case SPEED_100:
2894 bmcr |= BMCR_SPEED100;
2895 break;
2896
2897 case SPEED_1000:
2898 bmcr |= TG3_BMCR_SPEED1000;
2899 break;
855e1111 2900 }
1da177e4
LT		 2901
2902 if (tp->link_config.duplex == DUPLEX_FULL)
2903 bmcr |= BMCR_FULLDPLX;
2904
2905 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2906 (bmcr != orig_bmcr)) {
2907 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2908 for (i = 0; i < 1500; i++) {
2909 u32 tmp;
2910
2911 udelay(10);
2912 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2913 tg3_readphy(tp, MII_BMSR, &tmp))
2914 continue;
2915 if (!(tmp & BMSR_LSTATUS)) {
2916 udelay(40);
2917 break;
2918 }
2919 }
2920 tg3_writephy(tp, MII_BMCR, bmcr);
2921 udelay(40);
2922 }
2923 } else {
2924 tg3_writephy(tp, MII_BMCR,
2925 BMCR_ANENABLE | BMCR_ANRESTART);
2926 }
2927}
2928
2929static int tg3_init_5401phy_dsp(struct tg3 *tp)
2930{
2931 int err;
2932
2933 /* Turn off tap power management. */
2934 /* Set Extended packet length bit */
2935 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2936
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2939
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2942
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2945
2946 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2947 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2948
2949 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2951
2952 udelay(40);
2953
2954 return err;
2955}
2956
3600d918 2957static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2958{
3600d918
MC		 2959 u32 adv_reg, all_mask = 0;
2960
2961 if (mask & ADVERTISED_10baseT_Half)
2962 all_mask |= ADVERTISE_10HALF;
2963 if (mask & ADVERTISED_10baseT_Full)
2964 all_mask |= ADVERTISE_10FULL;
2965 if (mask & ADVERTISED_100baseT_Half)
2966 all_mask |= ADVERTISE_100HALF;
2967 if (mask & ADVERTISED_100baseT_Full)
2968 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2969
2970 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2971 return 0;
2972
1da177e4
LT		 2973 if ((adv_reg & all_mask) != all_mask)
2974 return 0;
2975 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2976 u32 tg3_ctrl;
2977
3600d918
MC		 2978 all_mask = 0;
2979 if (mask & ADVERTISED_1000baseT_Half)
2980 all_mask |= ADVERTISE_1000HALF;
2981 if (mask & ADVERTISED_1000baseT_Full)
2982 all_mask |= ADVERTISE_1000FULL;
2983
1da177e4
LT		 2984 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2985 return 0;
2986
1da177e4
LT		 2987 if ((tg3_ctrl & all_mask) != all_mask)
2988 return 0;
2989 }
2990 return 1;
2991}
2992
ef167e27
MC		 2993static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2994{
2995 u32 curadv, reqadv;
2996
2997 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2998 return 1;
2999
3000 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3001 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3002
3003 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3004 if (curadv != reqadv)
3005 return 0;
3006
3007 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3008 tg3_readphy(tp, MII_LPA, rmtadv);
3009 } else {
3010 /* Reprogram the advertisement register, even if it
3011 * does not affect the current link. If the link
3012 * gets renegotiated in the future, we can save an
3013 * additional renegotiation cycle by advertising
3014 * it correctly in the first place.
3015 */
3016 if (curadv != reqadv) {
3017 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3018 ADVERTISE_PAUSE_ASYM);
3019 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3020 }
3021 }
3022
3023 return 1;
3024}
3025
1da177e4
LT		 3026static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3027{
3028 int current_link_up;
3029 u32 bmsr, dummy;
ef167e27 3030 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3031 u16 current_speed;
3032 u8 current_duplex;
3033 int i, err;
3034
3035 tw32(MAC_EVENT, 0);
3036
3037 tw32_f(MAC_STATUS,
3038 (MAC_STATUS_SYNC_CHANGED |
3039 MAC_STATUS_CFG_CHANGED |
3040 MAC_STATUS_MI_COMPLETION |
3041 MAC_STATUS_LNKSTATE_CHANGED));
3042 udelay(40);
3043
8ef21428
MC		 3044 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3045 tw32_f(MAC_MI_MODE,
3046 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3047 udelay(80);
3048 }
1da177e4
LT		 3049
3050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3051
3052 /* Some third-party PHYs need to be reset on link going
3053 * down.
3054 */
3055 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3058 netif_carrier_ok(tp->dev)) {
3059 tg3_readphy(tp, MII_BMSR, &bmsr);
3060 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3061 !(bmsr & BMSR_LSTATUS))
3062 force_reset = 1;
3063 }
3064 if (force_reset)
3065 tg3_phy_reset(tp);
3066
3067 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3068 tg3_readphy(tp, MII_BMSR, &bmsr);
3069 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3070 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3071 bmsr = 0;
3072
3073 if (!(bmsr & BMSR_LSTATUS)) {
3074 err = tg3_init_5401phy_dsp(tp);
3075 if (err)
3076 return err;
3077
3078 tg3_readphy(tp, MII_BMSR, &bmsr);
3079 for (i = 0; i < 1000; i++) {
3080 udelay(10);
3081 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3082 (bmsr & BMSR_LSTATUS)) {
3083 udelay(40);
3084 break;
3085 }
3086 }
3087
3088 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3089 !(bmsr & BMSR_LSTATUS) &&
3090 tp->link_config.active_speed == SPEED_1000) {
3091 err = tg3_phy_reset(tp);
3092 if (!err)
3093 err = tg3_init_5401phy_dsp(tp);
3094 if (err)
3095 return err;
3096 }
3097 }
3098 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3099 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3100 /* 5701 {A0,B0} CRC bug workaround */
3101 tg3_writephy(tp, 0x15, 0x0a75);
3102 tg3_writephy(tp, 0x1c, 0x8c68);
3103 tg3_writephy(tp, 0x1c, 0x8d68);
3104 tg3_writephy(tp, 0x1c, 0x8c68);
3105 }
3106
3107 /* Clear pending interrupts... */
3108 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3109 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3110
3111 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3112 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3113 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3114 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3115
3116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3118 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3119 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3120 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3121 else
3122 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3123 }
3124
3125 current_link_up = 0;
3126 current_speed = SPEED_INVALID;
3127 current_duplex = DUPLEX_INVALID;
3128
3129 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3130 u32 val;
3131
3132 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3133 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3134 if (!(val & (1 << 10))) {
3135 val |= (1 << 10);
3136 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3137 goto relink;
3138 }
3139 }
3140
3141 bmsr = 0;
3142 for (i = 0; i < 100; i++) {
3143 tg3_readphy(tp, MII_BMSR, &bmsr);
3144 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3145 (bmsr & BMSR_LSTATUS))
3146 break;
3147 udelay(40);
3148 }
3149
3150 if (bmsr & BMSR_LSTATUS) {
3151 u32 aux_stat, bmcr;
3152
3153 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3154 for (i = 0; i < 2000; i++) {
3155 udelay(10);
3156 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3157 aux_stat)
3158 break;
3159 }
3160
3161 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3162 &current_speed,
3163 &current_duplex);
3164
3165 bmcr = 0;
3166 for (i = 0; i < 200; i++) {
3167 tg3_readphy(tp, MII_BMCR, &bmcr);
3168 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3169 continue;
3170 if (bmcr && bmcr != 0x7fff)
3171 break;
3172 udelay(10);
3173 }
3174
ef167e27
MC		 3175 lcl_adv = 0;
3176 rmt_adv = 0;
1da177e4 3177
ef167e27
MC		 3178 tp->link_config.active_speed = current_speed;
3179 tp->link_config.active_duplex = current_duplex;
3180
3181 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3182 if ((bmcr & BMCR_ANENABLE) &&
3183 tg3_copper_is_advertising_all(tp,
3184 tp->link_config.advertising)) {
3185 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3186 &rmt_adv))
3187 current_link_up = 1;
1da177e4
LT		 3188 }
3189 } else {
3190 if (!(bmcr & BMCR_ANENABLE) &&
3191 tp->link_config.speed == current_speed &&
ef167e27
MC		 3192 tp->link_config.duplex == current_duplex &&
3193 tp->link_config.flowctrl ==
3194 tp->link_config.active_flowctrl) {
1da177e4 3195 current_link_up = 1;
1da177e4
LT		 3196 }
3197 }
3198
ef167e27
MC		 3199 if (current_link_up == 1 &&
3200 tp->link_config.active_duplex == DUPLEX_FULL)
3201 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3202 }
3203
1da177e4 3204relink:
6921d201 3205 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3206 u32 tmp;
3207
3208 tg3_phy_copper_begin(tp);
3209
3210 tg3_readphy(tp, MII_BMSR, &tmp);
3211 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3212 (tmp & BMSR_LSTATUS))
3213 current_link_up = 1;
3214 }
3215
3216 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3217 if (current_link_up == 1) {
3218 if (tp->link_config.active_speed == SPEED_100 ||
3219 tp->link_config.active_speed == SPEED_10)
3220 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3221 else
3222 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3223 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3224 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3225 else
1da177e4
LT		 3226 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3227
3228 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3229 if (tp->link_config.active_duplex == DUPLEX_HALF)
3230 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3231
1da177e4 3232 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3233 if (current_link_up == 1 &&
3234 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3235 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3236 else
3237 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3238 }
3239
3240 /* ??? Without this setting Netgear GA302T PHY does not
3241 * ??? send/receive packets...
3242 */
3243 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3244 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3245 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3246 tw32_f(MAC_MI_MODE, tp->mi_mode);
3247 udelay(80);
3248 }
3249
3250 tw32_f(MAC_MODE, tp->mac_mode);
3251 udelay(40);
3252
3253 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3254 /* Polled via timer. */
3255 tw32_f(MAC_EVENT, 0);
3256 } else {
3257 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3258 }
3259 udelay(40);
3260
3261 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3262 current_link_up == 1 &&
3263 tp->link_config.active_speed == SPEED_1000 &&
3264 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3265 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3266 udelay(120);
3267 tw32_f(MAC_STATUS,
3268 (MAC_STATUS_SYNC_CHANGED |
3269 MAC_STATUS_CFG_CHANGED));
3270 udelay(40);
3271 tg3_write_mem(tp,
3272 NIC_SRAM_FIRMWARE_MBOX,
3273 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3274 }
3275
5e7dfd0f
MC		 3276 /* Prevent send BD corruption. */
3277 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3278 u16 oldlnkctl, newlnkctl;
3279
3280 pci_read_config_word(tp->pdev,
3281 tp->pcie_cap + PCI_EXP_LNKCTL,
3282 &oldlnkctl);
3283 if (tp->link_config.active_speed == SPEED_100 ||
3284 tp->link_config.active_speed == SPEED_10)
3285 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3286 else
3287 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3288 if (newlnkctl != oldlnkctl)
3289 pci_write_config_word(tp->pdev,
3290 tp->pcie_cap + PCI_EXP_LNKCTL,
3291 newlnkctl);
3292 }
3293
1da177e4
LT		 3294 if (current_link_up != netif_carrier_ok(tp->dev)) {
3295 if (current_link_up)
3296 netif_carrier_on(tp->dev);
3297 else
3298 netif_carrier_off(tp->dev);
3299 tg3_link_report(tp);
3300 }
3301
3302 return 0;
3303}
3304
3305struct tg3_fiber_aneginfo {
3306 int state;
3307#define ANEG_STATE_UNKNOWN 0
3308#define ANEG_STATE_AN_ENABLE 1
3309#define ANEG_STATE_RESTART_INIT 2
3310#define ANEG_STATE_RESTART 3
3311#define ANEG_STATE_DISABLE_LINK_OK 4
3312#define ANEG_STATE_ABILITY_DETECT_INIT 5
3313#define ANEG_STATE_ABILITY_DETECT 6
3314#define ANEG_STATE_ACK_DETECT_INIT 7
3315#define ANEG_STATE_ACK_DETECT 8
3316#define ANEG_STATE_COMPLETE_ACK_INIT 9
3317#define ANEG_STATE_COMPLETE_ACK 10
3318#define ANEG_STATE_IDLE_DETECT_INIT 11
3319#define ANEG_STATE_IDLE_DETECT 12
3320#define ANEG_STATE_LINK_OK 13
3321#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3322#define ANEG_STATE_NEXT_PAGE_WAIT 15
3323
3324 u32 flags;
3325#define MR_AN_ENABLE 0x00000001
3326#define MR_RESTART_AN 0x00000002
3327#define MR_AN_COMPLETE 0x00000004
3328#define MR_PAGE_RX 0x00000008
3329#define MR_NP_LOADED 0x00000010
3330#define MR_TOGGLE_TX 0x00000020
3331#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3332#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3333#define MR_LP_ADV_SYM_PAUSE 0x00000100
3334#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3335#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3336#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3337#define MR_LP_ADV_NEXT_PAGE 0x00001000
3338#define MR_TOGGLE_RX 0x00002000
3339#define MR_NP_RX 0x00004000
3340
3341#define MR_LINK_OK 0x80000000
3342
3343 unsigned long link_time, cur_time;
3344
3345 u32 ability_match_cfg;
3346 int ability_match_count;
3347
3348 char ability_match, idle_match, ack_match;
3349
3350 u32 txconfig, rxconfig;
3351#define ANEG_CFG_NP 0x00000080
3352#define ANEG_CFG_ACK 0x00000040
3353#define ANEG_CFG_RF2 0x00000020
3354#define ANEG_CFG_RF1 0x00000010
3355#define ANEG_CFG_PS2 0x00000001
3356#define ANEG_CFG_PS1 0x00008000
3357#define ANEG_CFG_HD 0x00004000
3358#define ANEG_CFG_FD 0x00002000
3359#define ANEG_CFG_INVAL 0x00001f06
3360
3361};
3362#define ANEG_OK 0
3363#define ANEG_DONE 1
3364#define ANEG_TIMER_ENAB 2
3365#define ANEG_FAILED -1
3366
3367#define ANEG_STATE_SETTLE_TIME 10000
3368
3369static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3370 struct tg3_fiber_aneginfo *ap)
3371{
5be73b47 3372 u16 flowctrl;
1da177e4
LT		 3373 unsigned long delta;
3374 u32 rx_cfg_reg;
3375 int ret;
3376
3377 if (ap->state == ANEG_STATE_UNKNOWN) {
3378 ap->rxconfig = 0;
3379 ap->link_time = 0;
3380 ap->cur_time = 0;
3381 ap->ability_match_cfg = 0;
3382 ap->ability_match_count = 0;
3383 ap->ability_match = 0;
3384 ap->idle_match = 0;
3385 ap->ack_match = 0;
3386 }
3387 ap->cur_time++;
3388
3389 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3390 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3391
3392 if (rx_cfg_reg != ap->ability_match_cfg) {
3393 ap->ability_match_cfg = rx_cfg_reg;
3394 ap->ability_match = 0;
3395 ap->ability_match_count = 0;
3396 } else {
3397 if (++ap->ability_match_count > 1) {
3398 ap->ability_match = 1;
3399 ap->ability_match_cfg = rx_cfg_reg;
3400 }
3401 }
3402 if (rx_cfg_reg & ANEG_CFG_ACK)
3403 ap->ack_match = 1;
3404 else
3405 ap->ack_match = 0;
3406
3407 ap->idle_match = 0;
3408 } else {
3409 ap->idle_match = 1;
3410 ap->ability_match_cfg = 0;
3411 ap->ability_match_count = 0;
3412 ap->ability_match = 0;
3413 ap->ack_match = 0;
3414
3415 rx_cfg_reg = 0;
3416 }
3417
3418 ap->rxconfig = rx_cfg_reg;
3419 ret = ANEG_OK;
3420
3421 switch(ap->state) {
3422 case ANEG_STATE_UNKNOWN:
3423 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3424 ap->state = ANEG_STATE_AN_ENABLE;
3425
3426 /* fallthru */
3427 case ANEG_STATE_AN_ENABLE:
3428 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3429 if (ap->flags & MR_AN_ENABLE) {
3430 ap->link_time = 0;
3431 ap->cur_time = 0;
3432 ap->ability_match_cfg = 0;
3433 ap->ability_match_count = 0;
3434 ap->ability_match = 0;
3435 ap->idle_match = 0;
3436 ap->ack_match = 0;
3437
3438 ap->state = ANEG_STATE_RESTART_INIT;
3439 } else {
3440 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3441 }
3442 break;
3443
3444 case ANEG_STATE_RESTART_INIT:
3445 ap->link_time = ap->cur_time;
3446 ap->flags &= ~(MR_NP_LOADED);
3447 ap->txconfig = 0;
3448 tw32(MAC_TX_AUTO_NEG, 0);
3449 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3450 tw32_f(MAC_MODE, tp->mac_mode);
3451 udelay(40);
3452
3453 ret = ANEG_TIMER_ENAB;
3454 ap->state = ANEG_STATE_RESTART;
3455
3456 /* fallthru */
3457 case ANEG_STATE_RESTART:
3458 delta = ap->cur_time - ap->link_time;
3459 if (delta > ANEG_STATE_SETTLE_TIME) {
3460 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3461 } else {
3462 ret = ANEG_TIMER_ENAB;
3463 }
3464 break;
3465
3466 case ANEG_STATE_DISABLE_LINK_OK:
3467 ret = ANEG_DONE;
3468 break;
3469
3470 case ANEG_STATE_ABILITY_DETECT_INIT:
3471 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3472 ap->txconfig = ANEG_CFG_FD;
3473 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3474 if (flowctrl & ADVERTISE_1000XPAUSE)
3475 ap->txconfig |= ANEG_CFG_PS1;
3476 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3477 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3478 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3479 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3480 tw32_f(MAC_MODE, tp->mac_mode);
3481 udelay(40);
3482
3483 ap->state = ANEG_STATE_ABILITY_DETECT;
3484 break;
3485
3486 case ANEG_STATE_ABILITY_DETECT:
3487 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3488 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3489 }
3490 break;
3491
3492 case ANEG_STATE_ACK_DETECT_INIT:
3493 ap->txconfig |= ANEG_CFG_ACK;
3494 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3495 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3496 tw32_f(MAC_MODE, tp->mac_mode);
3497 udelay(40);
3498
3499 ap->state = ANEG_STATE_ACK_DETECT;
3500
3501 /* fallthru */
3502 case ANEG_STATE_ACK_DETECT:
3503 if (ap->ack_match != 0) {
3504 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3505 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3506 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3507 } else {
3508 ap->state = ANEG_STATE_AN_ENABLE;
3509 }
3510 } else if (ap->ability_match != 0 &&
3511 ap->rxconfig == 0) {
3512 ap->state = ANEG_STATE_AN_ENABLE;
3513 }
3514 break;
3515
3516 case ANEG_STATE_COMPLETE_ACK_INIT:
3517 if (ap->rxconfig & ANEG_CFG_INVAL) {
3518 ret = ANEG_FAILED;
3519 break;
3520 }
3521 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3522 MR_LP_ADV_HALF_DUPLEX |
3523 MR_LP_ADV_SYM_PAUSE |
3524 MR_LP_ADV_ASYM_PAUSE |
3525 MR_LP_ADV_REMOTE_FAULT1 |
3526 MR_LP_ADV_REMOTE_FAULT2 |
3527 MR_LP_ADV_NEXT_PAGE |
3528 MR_TOGGLE_RX |
3529 MR_NP_RX);
3530 if (ap->rxconfig & ANEG_CFG_FD)
3531 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3532 if (ap->rxconfig & ANEG_CFG_HD)
3533 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3534 if (ap->rxconfig & ANEG_CFG_PS1)
3535 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3536 if (ap->rxconfig & ANEG_CFG_PS2)
3537 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3538 if (ap->rxconfig & ANEG_CFG_RF1)
3539 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3540 if (ap->rxconfig & ANEG_CFG_RF2)
3541 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3542 if (ap->rxconfig & ANEG_CFG_NP)
3543 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3544
3545 ap->link_time = ap->cur_time;
3546
3547 ap->flags ^= (MR_TOGGLE_TX);
3548 if (ap->rxconfig & 0x0008)
3549 ap->flags |= MR_TOGGLE_RX;
3550 if (ap->rxconfig & ANEG_CFG_NP)
3551 ap->flags |= MR_NP_RX;
3552 ap->flags |= MR_PAGE_RX;
3553
3554 ap->state = ANEG_STATE_COMPLETE_ACK;
3555 ret = ANEG_TIMER_ENAB;
3556 break;
3557
3558 case ANEG_STATE_COMPLETE_ACK:
3559 if (ap->ability_match != 0 &&
3560 ap->rxconfig == 0) {
3561 ap->state = ANEG_STATE_AN_ENABLE;
3562 break;
3563 }
3564 delta = ap->cur_time - ap->link_time;
3565 if (delta > ANEG_STATE_SETTLE_TIME) {
3566 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3567 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3568 } else {
3569 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3570 !(ap->flags & MR_NP_RX)) {
3571 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3572 } else {
3573 ret = ANEG_FAILED;
3574 }
3575 }
3576 }
3577 break;
3578
3579 case ANEG_STATE_IDLE_DETECT_INIT:
3580 ap->link_time = ap->cur_time;
3581 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3582 tw32_f(MAC_MODE, tp->mac_mode);
3583 udelay(40);
3584
3585 ap->state = ANEG_STATE_IDLE_DETECT;
3586 ret = ANEG_TIMER_ENAB;
3587 break;
3588
3589 case ANEG_STATE_IDLE_DETECT:
3590 if (ap->ability_match != 0 &&
3591 ap->rxconfig == 0) {
3592 ap->state = ANEG_STATE_AN_ENABLE;
3593 break;
3594 }
3595 delta = ap->cur_time - ap->link_time;
3596 if (delta > ANEG_STATE_SETTLE_TIME) {
3597 /* XXX another gem from the Broadcom driver :( */
3598 ap->state = ANEG_STATE_LINK_OK;
3599 }
3600 break;
3601
3602 case ANEG_STATE_LINK_OK:
3603 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3604 ret = ANEG_DONE;
3605 break;
3606
3607 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3608 /* ??? unimplemented */
3609 break;
3610
3611 case ANEG_STATE_NEXT_PAGE_WAIT:
3612 /* ??? unimplemented */
3613 break;
3614
3615 default:
3616 ret = ANEG_FAILED;
3617 break;
855e1111 3618 }
1da177e4
LT		 3619
3620 return ret;
3621}
3622
5be73b47 3623static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3624{
3625 int res = 0;
3626 struct tg3_fiber_aneginfo aninfo;
3627 int status = ANEG_FAILED;
3628 unsigned int tick;
3629 u32 tmp;
3630
3631 tw32_f(MAC_TX_AUTO_NEG, 0);
3632
3633 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3634 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3635 udelay(40);
3636
3637 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3638 udelay(40);
3639
3640 memset(&aninfo, 0, sizeof(aninfo));
3641 aninfo.flags |= MR_AN_ENABLE;
3642 aninfo.state = ANEG_STATE_UNKNOWN;
3643 aninfo.cur_time = 0;
3644 tick = 0;
3645 while (++tick < 195000) {
3646 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3647 if (status == ANEG_DONE || status == ANEG_FAILED)
3648 break;
3649
3650 udelay(1);
3651 }
3652
3653 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3654 tw32_f(MAC_MODE, tp->mac_mode);
3655 udelay(40);
3656
5be73b47
MC		 3657 *txflags = aninfo.txconfig;
3658 *rxflags = aninfo.flags;
1da177e4
LT		 3659
3660 if (status == ANEG_DONE &&
3661 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3662 MR_LP_ADV_FULL_DUPLEX)))
3663 res = 1;
3664
3665 return res;
3666}
3667
3668static void tg3_init_bcm8002(struct tg3 *tp)
3669{
3670 u32 mac_status = tr32(MAC_STATUS);
3671 int i;
3672
3673 /* Reset when initting first time or we have a link. */
3674 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3675 !(mac_status & MAC_STATUS_PCS_SYNCED))
3676 return;
3677
3678 /* Set PLL lock range. */
3679 tg3_writephy(tp, 0x16, 0x8007);
3680
3681 /* SW reset */
3682 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3683
3684 /* Wait for reset to complete. */
3685 /* XXX schedule_timeout() ... */
3686 for (i = 0; i < 500; i++)
3687 udelay(10);
3688
3689 /* Config mode; select PMA/Ch 1 regs. */
3690 tg3_writephy(tp, 0x10, 0x8411);
3691
3692 /* Enable auto-lock and comdet, select txclk for tx. */
3693 tg3_writephy(tp, 0x11, 0x0a10);
3694
3695 tg3_writephy(tp, 0x18, 0x00a0);
3696 tg3_writephy(tp, 0x16, 0x41ff);
3697
3698 /* Assert and deassert POR. */
3699 tg3_writephy(tp, 0x13, 0x0400);
3700 udelay(40);
3701 tg3_writephy(tp, 0x13, 0x0000);
3702
3703 tg3_writephy(tp, 0x11, 0x0a50);
3704 udelay(40);
3705 tg3_writephy(tp, 0x11, 0x0a10);
3706
3707 /* Wait for signal to stabilize */
3708 /* XXX schedule_timeout() ... */
3709 for (i = 0; i < 15000; i++)
3710 udelay(10);
3711
3712 /* Deselect the channel register so we can read the PHYID
3713 * later.
3714 */
3715 tg3_writephy(tp, 0x10, 0x8011);
3716}
3717
3718static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3719{
82cd3d11 3720 u16 flowctrl;
1da177e4
LT		 3721 u32 sg_dig_ctrl, sg_dig_status;
3722 u32 serdes_cfg, expected_sg_dig_ctrl;
3723 int workaround, port_a;
3724 int current_link_up;
3725
3726 serdes_cfg = 0;
3727 expected_sg_dig_ctrl = 0;
3728 workaround = 0;
3729 port_a = 1;
3730 current_link_up = 0;
3731
3732 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3733 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3734 workaround = 1;
3735 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3736 port_a = 0;
3737
3738 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3739 /* preserve bits 20-23 for voltage regulator */
3740 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3741 }
3742
3743 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3744
3745 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3746 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3747 if (workaround) {
3748 u32 val = serdes_cfg;
3749
3750 if (port_a)
3751 val |= 0xc010000;
3752 else
3753 val |= 0x4010000;
3754 tw32_f(MAC_SERDES_CFG, val);
3755 }
c98f6e3b
MC		 3756
3757 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3758 }
3759 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3760 tg3_setup_flow_control(tp, 0, 0);
3761 current_link_up = 1;
3762 }
3763 goto out;
3764 }
3765
3766 /* Want auto-negotiation. */
c98f6e3b 3767 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3768
82cd3d11
MC		 3769 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3770 if (flowctrl & ADVERTISE_1000XPAUSE)
3771 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3772 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3773 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3774
3775 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3776 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3777 tp->serdes_counter &&
3778 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3779 MAC_STATUS_RCVD_CFG)) ==
3780 MAC_STATUS_PCS_SYNCED)) {
3781 tp->serdes_counter--;
3782 current_link_up = 1;
3783 goto out;
3784 }
3785restart_autoneg:
1da177e4
LT		 3786 if (workaround)
3787 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3788 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3789 udelay(5);
3790 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3791
3d3ebe74
MC		 3792 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3793 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3794 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3795 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3796 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3797 mac_status = tr32(MAC_STATUS);
3798
c98f6e3b 3799 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3800 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3801 u32 local_adv = 0, remote_adv = 0;
3802
3803 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3804 local_adv |= ADVERTISE_1000XPAUSE;
3805 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3806 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3807
c98f6e3b 3808 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3809 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3810 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3811 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3812
3813 tg3_setup_flow_control(tp, local_adv, remote_adv);
3814 current_link_up = 1;
3d3ebe74
MC		 3815 tp->serdes_counter = 0;
3816 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3817 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3818 if (tp->serdes_counter)
3819 tp->serdes_counter--;
1da177e4
LT		 3820 else {
3821 if (workaround) {
3822 u32 val = serdes_cfg;
3823
3824 if (port_a)
3825 val |= 0xc010000;
3826 else
3827 val |= 0x4010000;
3828
3829 tw32_f(MAC_SERDES_CFG, val);
3830 }
3831
c98f6e3b 3832 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3833 udelay(40);
3834
3835 /* Link parallel detection - link is up */
3836 /* only if we have PCS_SYNC and not */
3837 /* receiving config code words */
3838 mac_status = tr32(MAC_STATUS);
3839 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3840 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3841 tg3_setup_flow_control(tp, 0, 0);
3842 current_link_up = 1;
3d3ebe74
MC		 3843 tp->tg3_flags2 |=
3844 TG3_FLG2_PARALLEL_DETECT;
3845 tp->serdes_counter =
3846 SERDES_PARALLEL_DET_TIMEOUT;
3847 } else
3848 goto restart_autoneg;
1da177e4
LT		 3849 }
3850 }
3d3ebe74
MC		 3851 } else {
3852 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3853 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3854 }
3855
3856out:
3857 return current_link_up;
3858}
3859
3860static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3861{
3862 int current_link_up = 0;
3863
5cf64b8a 3864 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3865 goto out;
1da177e4
LT		 3866
3867 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3868 u32 txflags, rxflags;
1da177e4 3869 int i;
6aa20a22 3870
5be73b47
MC		 3871 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3872 u32 local_adv = 0, remote_adv = 0;
1da177e4 3873
5be73b47
MC		 3874 if (txflags & ANEG_CFG_PS1)
3875 local_adv |= ADVERTISE_1000XPAUSE;
3876 if (txflags & ANEG_CFG_PS2)
3877 local_adv |= ADVERTISE_1000XPSE_ASYM;
3878
3879 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3880 remote_adv |= LPA_1000XPAUSE;
3881 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3882 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3883
3884 tg3_setup_flow_control(tp, local_adv, remote_adv);
3885
1da177e4
LT		 3886 current_link_up = 1;
3887 }
3888 for (i = 0; i < 30; i++) {
3889 udelay(20);
3890 tw32_f(MAC_STATUS,
3891 (MAC_STATUS_SYNC_CHANGED |
3892 MAC_STATUS_CFG_CHANGED));
3893 udelay(40);
3894 if ((tr32(MAC_STATUS) &
3895 (MAC_STATUS_SYNC_CHANGED |
3896 MAC_STATUS_CFG_CHANGED)) == 0)
3897 break;
3898 }
3899
3900 mac_status = tr32(MAC_STATUS);
3901 if (current_link_up == 0 &&
3902 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3903 !(mac_status & MAC_STATUS_RCVD_CFG))
3904 current_link_up = 1;
3905 } else {
5be73b47
MC		 3906 tg3_setup_flow_control(tp, 0, 0);
3907
1da177e4
LT		 3908 /* Forcing 1000FD link up. */
3909 current_link_up = 1;
1da177e4
LT		 3910
3911 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3912 udelay(40);
e8f3f6ca
MC		 3913
3914 tw32_f(MAC_MODE, tp->mac_mode);
3915 udelay(40);
1da177e4
LT		 3916 }
3917
3918out:
3919 return current_link_up;
3920}
3921
3922static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3923{
3924 u32 orig_pause_cfg;
3925 u16 orig_active_speed;
3926 u8 orig_active_duplex;
3927 u32 mac_status;
3928 int current_link_up;
3929 int i;
3930
8d018621 3931 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3932 orig_active_speed = tp->link_config.active_speed;
3933 orig_active_duplex = tp->link_config.active_duplex;
3934
3935 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3936 netif_carrier_ok(tp->dev) &&
3937 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3938 mac_status = tr32(MAC_STATUS);
3939 mac_status &= (MAC_STATUS_PCS_SYNCED |
3940 MAC_STATUS_SIGNAL_DET |
3941 MAC_STATUS_CFG_CHANGED |
3942 MAC_STATUS_RCVD_CFG);
3943 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3944 MAC_STATUS_SIGNAL_DET)) {
3945 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3946 MAC_STATUS_CFG_CHANGED));
3947 return 0;
3948 }
3949 }
3950
3951 tw32_f(MAC_TX_AUTO_NEG, 0);
3952
3953 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3954 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3955 tw32_f(MAC_MODE, tp->mac_mode);
3956 udelay(40);
3957
3958 if (tp->phy_id == PHY_ID_BCM8002)
3959 tg3_init_bcm8002(tp);
3960
3961 /* Enable link change event even when serdes polling. */
3962 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3963 udelay(40);
3964
3965 current_link_up = 0;
3966 mac_status = tr32(MAC_STATUS);
3967
3968 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3969 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3970 else
3971 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3972
898a56f8 3973 tp->napi[0].hw_status->status =
1da177e4 3974 (SD_STATUS_UPDATED |
898a56f8 3975 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3976
3977 for (i = 0; i < 100; i++) {
3978 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979 MAC_STATUS_CFG_CHANGED));
3980 udelay(5);
3981 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3982 MAC_STATUS_CFG_CHANGED |
3983 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3984 break;
3985 }
3986
3987 mac_status = tr32(MAC_STATUS);
3988 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3989 current_link_up = 0;
3d3ebe74
MC		 3990 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3991 tp->serdes_counter == 0) {
1da177e4
LT		 3992 tw32_f(MAC_MODE, (tp->mac_mode |
3993 MAC_MODE_SEND_CONFIGS));
3994 udelay(1);
3995 tw32_f(MAC_MODE, tp->mac_mode);
3996 }
3997 }
3998
3999 if (current_link_up == 1) {
4000 tp->link_config.active_speed = SPEED_1000;
4001 tp->link_config.active_duplex = DUPLEX_FULL;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_1000MBPS_ON));
4005 } else {
4006 tp->link_config.active_speed = SPEED_INVALID;
4007 tp->link_config.active_duplex = DUPLEX_INVALID;
4008 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4009 LED_CTRL_LNKLED_OVERRIDE |
4010 LED_CTRL_TRAFFIC_OVERRIDE));
4011 }
4012
4013 if (current_link_up != netif_carrier_ok(tp->dev)) {
4014 if (current_link_up)
4015 netif_carrier_on(tp->dev);
4016 else
4017 netif_carrier_off(tp->dev);
4018 tg3_link_report(tp);
4019 } else {
8d018621 4020 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4021 if (orig_pause_cfg != now_pause_cfg ||
4022 orig_active_speed != tp->link_config.active_speed ||
4023 orig_active_duplex != tp->link_config.active_duplex)
4024 tg3_link_report(tp);
4025 }
4026
4027 return 0;
4028}
4029
747e8f8b
MC		 4030static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4031{
4032 int current_link_up, err = 0;
4033 u32 bmsr, bmcr;
4034 u16 current_speed;
4035 u8 current_duplex;
ef167e27 4036 u32 local_adv, remote_adv;
747e8f8b
MC		 4037
4038 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4039 tw32_f(MAC_MODE, tp->mac_mode);
4040 udelay(40);
4041
4042 tw32(MAC_EVENT, 0);
4043
4044 tw32_f(MAC_STATUS,
4045 (MAC_STATUS_SYNC_CHANGED |
4046 MAC_STATUS_CFG_CHANGED |
4047 MAC_STATUS_MI_COMPLETION |
4048 MAC_STATUS_LNKSTATE_CHANGED));
4049 udelay(40);
4050
4051 if (force_reset)
4052 tg3_phy_reset(tp);
4053
4054 current_link_up = 0;
4055 current_speed = SPEED_INVALID;
4056 current_duplex = DUPLEX_INVALID;
4057
4058 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4059 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4061 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4062 bmsr |= BMSR_LSTATUS;
4063 else
4064 bmsr &= ~BMSR_LSTATUS;
4065 }
747e8f8b
MC		 4066
4067 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4068
4069 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4070 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4071 /* do nothing, just check for link up at the end */
4072 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4073 u32 adv, new_adv;
4074
4075 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4076 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4077 ADVERTISE_1000XPAUSE |
4078 ADVERTISE_1000XPSE_ASYM |
4079 ADVERTISE_SLCT);
4080
ba4d07a8 4081 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4082
4083 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4084 new_adv |= ADVERTISE_1000XHALF;
4085 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4086 new_adv |= ADVERTISE_1000XFULL;
4087
4088 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4089 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4090 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4091 tg3_writephy(tp, MII_BMCR, bmcr);
4092
4093 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4094 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4095 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4096
4097 return err;
4098 }
4099 } else {
4100 u32 new_bmcr;
4101
4102 bmcr &= ~BMCR_SPEED1000;
4103 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4104
4105 if (tp->link_config.duplex == DUPLEX_FULL)
4106 new_bmcr |= BMCR_FULLDPLX;
4107
4108 if (new_bmcr != bmcr) {
4109 /* BMCR_SPEED1000 is a reserved bit that needs
4110 * to be set on write.
4111 */
4112 new_bmcr |= BMCR_SPEED1000;
4113
4114 /* Force a linkdown */
4115 if (netif_carrier_ok(tp->dev)) {
4116 u32 adv;
4117
4118 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4119 adv &= ~(ADVERTISE_1000XFULL |
4120 ADVERTISE_1000XHALF |
4121 ADVERTISE_SLCT);
4122 tg3_writephy(tp, MII_ADVERTISE, adv);
4123 tg3_writephy(tp, MII_BMCR, bmcr |
4124 BMCR_ANRESTART |
4125 BMCR_ANENABLE);
4126 udelay(10);
4127 netif_carrier_off(tp->dev);
4128 }
4129 tg3_writephy(tp, MII_BMCR, new_bmcr);
4130 bmcr = new_bmcr;
4131 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4132 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4133 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4134 ASIC_REV_5714) {
4135 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4136 bmsr |= BMSR_LSTATUS;
4137 else
4138 bmsr &= ~BMSR_LSTATUS;
4139 }
747e8f8b
MC		 4140 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4141 }
4142 }
4143
4144 if (bmsr & BMSR_LSTATUS) {
4145 current_speed = SPEED_1000;
4146 current_link_up = 1;
4147 if (bmcr & BMCR_FULLDPLX)
4148 current_duplex = DUPLEX_FULL;
4149 else
4150 current_duplex = DUPLEX_HALF;
4151
ef167e27
MC		 4152 local_adv = 0;
4153 remote_adv = 0;
4154
747e8f8b 4155 if (bmcr & BMCR_ANENABLE) {
ef167e27 4156 u32 common;
747e8f8b
MC		 4157
4158 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4159 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4160 common = local_adv & remote_adv;
4161 if (common & (ADVERTISE_1000XHALF |
4162 ADVERTISE_1000XFULL)) {
4163 if (common & ADVERTISE_1000XFULL)
4164 current_duplex = DUPLEX_FULL;
4165 else
4166 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4167 }
4168 else
4169 current_link_up = 0;
4170 }
4171 }
4172
ef167e27
MC		 4173 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4174 tg3_setup_flow_control(tp, local_adv, remote_adv);
4175
747e8f8b
MC		 4176 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4177 if (tp->link_config.active_duplex == DUPLEX_HALF)
4178 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4179
4180 tw32_f(MAC_MODE, tp->mac_mode);
4181 udelay(40);
4182
4183 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4184
4185 tp->link_config.active_speed = current_speed;
4186 tp->link_config.active_duplex = current_duplex;
4187
4188 if (current_link_up != netif_carrier_ok(tp->dev)) {
4189 if (current_link_up)
4190 netif_carrier_on(tp->dev);
4191 else {
4192 netif_carrier_off(tp->dev);
4193 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4194 }
4195 tg3_link_report(tp);
4196 }
4197 return err;
4198}
4199
4200static void tg3_serdes_parallel_detect(struct tg3 *tp)
4201{
3d3ebe74 4202 if (tp->serdes_counter) {
747e8f8b 4203 /* Give autoneg time to complete. */
3d3ebe74 4204 tp->serdes_counter--;
747e8f8b
MC		 4205 return;
4206 }
4207 if (!netif_carrier_ok(tp->dev) &&
4208 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4209 u32 bmcr;
4210
4211 tg3_readphy(tp, MII_BMCR, &bmcr);
4212 if (bmcr & BMCR_ANENABLE) {
4213 u32 phy1, phy2;
4214
4215 /* Select shadow register 0x1f */
4216 tg3_writephy(tp, 0x1c, 0x7c00);
4217 tg3_readphy(tp, 0x1c, &phy1);
4218
4219 /* Select expansion interrupt status register */
4220 tg3_writephy(tp, 0x17, 0x0f01);
4221 tg3_readphy(tp, 0x15, &phy2);
4222 tg3_readphy(tp, 0x15, &phy2);
4223
4224 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4225 /* We have signal detect and not receiving
4226 * config code words, link is up by parallel
4227 * detection.
4228 */
4229
4230 bmcr &= ~BMCR_ANENABLE;
4231 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4232 tg3_writephy(tp, MII_BMCR, bmcr);
4233 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4234 }
4235 }
4236 }
4237 else if (netif_carrier_ok(tp->dev) &&
4238 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4239 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4240 u32 phy2;
4241
4242 /* Select expansion interrupt status register */
4243 tg3_writephy(tp, 0x17, 0x0f01);
4244 tg3_readphy(tp, 0x15, &phy2);
4245 if (phy2 & 0x20) {
4246 u32 bmcr;
4247
4248 /* Config code words received, turn on autoneg. */
4249 tg3_readphy(tp, MII_BMCR, &bmcr);
4250 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4251
4252 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4253
4254 }
4255 }
4256}
4257
1da177e4
LT		 4258static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4259{
4260 int err;
4261
4262 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4263 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4264 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4265 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4266 } else {
4267 err = tg3_setup_copper_phy(tp, force_reset);
4268 }
4269
bcb37f6c 4270 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4271 u32 val, scale;
4272
4273 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4274 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4275 scale = 65;
4276 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4277 scale = 6;
4278 else
4279 scale = 12;
4280
4281 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4282 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4283 tw32(GRC_MISC_CFG, val);
4284 }
4285
1da177e4
LT		 4286 if (tp->link_config.active_speed == SPEED_1000 &&
4287 tp->link_config.active_duplex == DUPLEX_HALF)
4288 tw32(MAC_TX_LENGTHS,
4289 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4290 (6 << TX_LENGTHS_IPG_SHIFT) |
4291 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4292 else
4293 tw32(MAC_TX_LENGTHS,
4294 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4295 (6 << TX_LENGTHS_IPG_SHIFT) |
4296 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4297
4298 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4299 if (netif_carrier_ok(tp->dev)) {
4300 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4301 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4302 } else {
4303 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4304 }
4305 }
4306
8ed5d97e
MC		 4307 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4308 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4309 if (!netif_carrier_ok(tp->dev))
4310 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4311 tp->pwrmgmt_thresh;
4312 else
4313 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4314 tw32(PCIE_PWR_MGMT_THRESH, val);
4315 }
4316
1da177e4
LT		 4317 return err;
4318}
4319
df3e6548
MC		 4320/* This is called whenever we suspect that the system chipset is re-
4321 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4322 * is bogus tx completions. We try to recover by setting the
4323 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4324 * in the workqueue.
4325 */
4326static void tg3_tx_recover(struct tg3 *tp)
4327{
4328 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4329 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4330
4331 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4332 "mapped I/O cycles to the network device, attempting to "
4333 "recover. Please report the problem to the driver maintainer "
4334 "and include system chipset information.\n", tp->dev->name);
4335
4336 spin_lock(&tp->lock);
df3e6548 4337 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4338 spin_unlock(&tp->lock);
4339}
4340
f3f3f27e 4341static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4342{
4343 smp_mb();
f3f3f27e
MC		 4344 return tnapi->tx_pending -
4345 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4346}
4347
1da177e4
LT		 4348/* Tigon3 never reports partial packet sends. So we do not
4349 * need special logic to handle SKBs that have not had all
4350 * of their frags sent yet, like SunGEM does.
4351 */
17375d25 4352static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4353{
17375d25 4354 struct tg3 *tp = tnapi->tp;
898a56f8 4355 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4356 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4357 struct netdev_queue *txq;
4358 int index = tnapi - tp->napi;
4359
19cfaecc 4360 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4361 index--;
4362
4363 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4364
4365 while (sw_idx != hw_idx) {
f4188d8a 4366 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4367 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4368 int i, tx_bug = 0;
4369
4370 if (unlikely(skb == NULL)) {
4371 tg3_tx_recover(tp);
4372 return;
4373 }
1da177e4 4374
f4188d8a
AD		 4375 pci_unmap_single(tp->pdev,
4376 pci_unmap_addr(ri, mapping),
4377 skb_headlen(skb),
4378 PCI_DMA_TODEVICE);
1da177e4
LT		 4379
4380 ri->skb = NULL;
4381
4382 sw_idx = NEXT_TX(sw_idx);
4383
4384 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4385 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4386 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4387 tx_bug = 1;
f4188d8a
AD		 4388
4389 pci_unmap_page(tp->pdev,
4390 pci_unmap_addr(ri, mapping),
4391 skb_shinfo(skb)->frags[i].size,
4392 PCI_DMA_TODEVICE);
1da177e4
LT		 4393 sw_idx = NEXT_TX(sw_idx);
4394 }
4395
f47c11ee 4396 dev_kfree_skb(skb);
df3e6548
MC		 4397
4398 if (unlikely(tx_bug)) {
4399 tg3_tx_recover(tp);
4400 return;
4401 }
1da177e4
LT		 4402 }
4403
f3f3f27e 4404 tnapi->tx_cons = sw_idx;
1da177e4 4405
1b2a7205
MC		 4406 /* Need to make the tx_cons update visible to tg3_start_xmit()
4407 * before checking for netif_queue_stopped(). Without the
4408 * memory barrier, there is a small possibility that tg3_start_xmit()
4409 * will miss it and cause the queue to be stopped forever.
4410 */
4411 smp_mb();
4412
fe5f5787 4413 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4414 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4415 __netif_tx_lock(txq, smp_processor_id());
4416 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4417 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4418 netif_tx_wake_queue(txq);
4419 __netif_tx_unlock(txq);
51b91468 4420 }
1da177e4
LT		 4421}
4422
2b2cdb65
MC		 4423static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4424{
4425 if (!ri->skb)
4426 return;
4427
4428 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4429 map_sz, PCI_DMA_FROMDEVICE);
4430 dev_kfree_skb_any(ri->skb);
4431 ri->skb = NULL;
4432}
4433
1da177e4
LT		 4434/* Returns size of skb allocated or < 0 on error.
4435 *
4436 * We only need to fill in the address because the other members
4437 * of the RX descriptor are invariant, see tg3_init_rings.
4438 *
4439 * Note the purposeful assymetry of cpu vs. chip accesses. For
4440 * posting buffers we only dirty the first cache line of the RX
4441 * descriptor (containing the address). Whereas for the RX status
4442 * buffers the cpu only reads the last cacheline of the RX descriptor
4443 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4444 */
86b21e59 4445static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4446 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4447{
4448 struct tg3_rx_buffer_desc *desc;
4449 struct ring_info *map, *src_map;
4450 struct sk_buff *skb;
4451 dma_addr_t mapping;
4452 int skb_size, dest_idx;
4453
4454 src_map = NULL;
4455 switch (opaque_key) {
4456 case RXD_OPAQUE_RING_STD:
4457 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4458 desc = &tpr->rx_std[dest_idx];
4459 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4460 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4461 break;
4462
4463 case RXD_OPAQUE_RING_JUMBO:
4464 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4465 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4466 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4467 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4468 break;
4469
4470 default:
4471 return -EINVAL;
855e1111 4472 }
1da177e4
LT		 4473
4474 /* Do not overwrite any of the map or rp information
4475 * until we are sure we can commit to a new buffer.
4476 *
4477 * Callers depend upon this behavior and assume that
4478 * we leave everything unchanged if we fail.
4479 */
287be12e 4480 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4481 if (skb == NULL)
4482 return -ENOMEM;
4483
1da177e4
LT		 4484 skb_reserve(skb, tp->rx_offset);
4485
287be12e 4486 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4487 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4488 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4489 dev_kfree_skb(skb);
4490 return -EIO;
4491 }
1da177e4
LT		 4492
4493 map->skb = skb;
4494 pci_unmap_addr_set(map, mapping, mapping);
4495
1da177e4
LT		 4496 desc->addr_hi = ((u64)mapping >> 32);
4497 desc->addr_lo = ((u64)mapping & 0xffffffff);
4498
4499 return skb_size;
4500}
4501
4502/* We only need to move over in the address because the other
4503 * members of the RX descriptor are invariant. See notes above
4504 * tg3_alloc_rx_skb for full details.
4505 */
a3896167
MC		 4506static void tg3_recycle_rx(struct tg3_napi *tnapi,
4507 struct tg3_rx_prodring_set *dpr,
4508 u32 opaque_key, int src_idx,
4509 u32 dest_idx_unmasked)
1da177e4 4510{
17375d25 4511 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4512 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4513 struct ring_info *src_map, *dest_map;
4514 int dest_idx;
a3896167 4515 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4516
4517 switch (opaque_key) {
4518 case RXD_OPAQUE_RING_STD:
4519 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4520 dest_desc = &dpr->rx_std[dest_idx];
4521 dest_map = &dpr->rx_std_buffers[dest_idx];
4522 src_desc = &spr->rx_std[src_idx];
4523 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4524 break;
4525
4526 case RXD_OPAQUE_RING_JUMBO:
4527 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4528 dest_desc = &dpr->rx_jmb[dest_idx].std;
4529 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4530 src_desc = &spr->rx_jmb[src_idx].std;
4531 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4532 break;
4533
4534 default:
4535 return;
855e1111 4536 }
1da177e4
LT		 4537
4538 dest_map->skb = src_map->skb;
4539 pci_unmap_addr_set(dest_map, mapping,
4540 pci_unmap_addr(src_map, mapping));
4541 dest_desc->addr_hi = src_desc->addr_hi;
4542 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4543 src_map->skb = NULL;
4544}
4545
1da177e4
LT		 4546/* The RX ring scheme is composed of multiple rings which post fresh
4547 * buffers to the chip, and one special ring the chip uses to report
4548 * status back to the host.
4549 *
4550 * The special ring reports the status of received packets to the
4551 * host. The chip does not write into the original descriptor the
4552 * RX buffer was obtained from. The chip simply takes the original
4553 * descriptor as provided by the host, updates the status and length
4554 * field, then writes this into the next status ring entry.
4555 *
4556 * Each ring the host uses to post buffers to the chip is described
4557 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4558 * it is first placed into the on-chip ram. When the packet's length
4559 * is known, it walks down the TG3_BDINFO entries to select the ring.
4560 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4561 * which is within the range of the new packet's length is chosen.
4562 *
4563 * The "separate ring for rx status" scheme may sound queer, but it makes
4564 * sense from a cache coherency perspective. If only the host writes
4565 * to the buffer post rings, and only the chip writes to the rx status
4566 * rings, then cache lines never move beyond shared-modified state.
4567 * If both the host and chip were to write into the same ring, cache line
4568 * eviction could occur since both entities want it in an exclusive state.
4569 */
17375d25 4570static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4571{
17375d25 4572 struct tg3 *tp = tnapi->tp;
f92905de 4573 u32 work_mask, rx_std_posted = 0;
4361935a 4574 u32 std_prod_idx, jmb_prod_idx;
72334482 4575 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4576 u16 hw_idx;
1da177e4 4577 int received;
b196c7e4 4578 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4579
8d9d7cfc 4580 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4581 /*
4582 * We need to order the read of hw_idx and the read of
4583 * the opaque cookie.
4584 */
4585 rmb();
1da177e4
LT		 4586 work_mask = 0;
4587 received = 0;
4361935a
MC		 4588 std_prod_idx = tpr->rx_std_prod_idx;
4589 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4590 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4591 struct ring_info *ri;
72334482 4592 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4593 unsigned int len;
4594 struct sk_buff *skb;
4595 dma_addr_t dma_addr;
4596 u32 opaque_key, desc_idx, *post_ptr;
4597
4598 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4599 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4600 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4601 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4602 dma_addr = pci_unmap_addr(ri, mapping);
4603 skb = ri->skb;
4361935a 4604 post_ptr = &std_prod_idx;
f92905de 4605 rx_std_posted++;
1da177e4 4606 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4607 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4608 dma_addr = pci_unmap_addr(ri, mapping);
4609 skb = ri->skb;
4361935a 4610 post_ptr = &jmb_prod_idx;
21f581a5 4611 } else
1da177e4 4612 goto next_pkt_nopost;
1da177e4
LT		 4613
4614 work_mask |= opaque_key;
4615
4616 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4617 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4618 drop_it:
a3896167 4619 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4620 desc_idx, *post_ptr);
4621 drop_it_no_recycle:
4622 /* Other statistics kept track of by card. */
4623 tp->net_stats.rx_dropped++;
4624 goto next_pkt;
4625 }
4626
ad829268
MC		 4627 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4628 ETH_FCS_LEN;
1da177e4 4629
8e95a202
JP		 4630 if (len > RX_COPY_THRESHOLD &&
4631 tp->rx_offset == NET_IP_ALIGN) {
4632 /* rx_offset will likely not equal NET_IP_ALIGN
4633 * if this is a 5701 card running in PCI-X mode
4634 * [see tg3_get_invariants()]
4635 */
1da177e4
LT		 4636 int skb_size;
4637
86b21e59 4638 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4639 *post_ptr);
1da177e4
LT		 4640 if (skb_size < 0)
4641 goto drop_it;
4642
afc081f8
MC		 4643 ri->skb = NULL;
4644
287be12e 4645 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4646 PCI_DMA_FROMDEVICE);
4647
4648 skb_put(skb, len);
4649 } else {
4650 struct sk_buff *copy_skb;
4651
a3896167 4652 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4653 desc_idx, *post_ptr);
4654
ad829268
MC		 4655 copy_skb = netdev_alloc_skb(tp->dev,
4656 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4657 if (copy_skb == NULL)
4658 goto drop_it_no_recycle;
4659
ad829268 4660 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4661 skb_put(copy_skb, len);
4662 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4663 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4664 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665
4666 /* We'll reuse the original ring buffer. */
4667 skb = copy_skb;
4668 }
4669
4670 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4671 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4672 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4673 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4674 skb->ip_summed = CHECKSUM_UNNECESSARY;
4675 else
4676 skb->ip_summed = CHECKSUM_NONE;
4677
4678 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4679
4680 if (len > (tp->dev->mtu + ETH_HLEN) &&
4681 skb->protocol != htons(ETH_P_8021Q)) {
4682 dev_kfree_skb(skb);
4683 goto next_pkt;
4684 }
4685
1da177e4
LT		 4686#if TG3_VLAN_TAG_USED
4687 if (tp->vlgrp != NULL &&
4688 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4689 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4690 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4691 } else
4692#endif
17375d25 4693 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4694
1da177e4
LT		 4695 received++;
4696 budget--;
4697
4698next_pkt:
4699 (*post_ptr)++;
f92905de
MC		 4700
4701 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4702 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
66711e66 4703 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
f92905de
MC		 4704 work_mask &= ~RXD_OPAQUE_RING_STD;
4705 rx_std_posted = 0;
4706 }
1da177e4 4707next_pkt_nopost:
483ba50b 4708 sw_idx++;
6b31a515 4709 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4710
4711 /* Refresh hw_idx to see if there is new work */
4712 if (sw_idx == hw_idx) {
8d9d7cfc 4713 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4714 rmb();
4715 }
1da177e4
LT		 4716 }
4717
4718 /* ACK the status ring. */
72334482
MC		 4719 tnapi->rx_rcb_ptr = sw_idx;
4720 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4721
4722 /* Refill RX ring(s). */
b196c7e4
MC		 4723 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4724 if (work_mask & RXD_OPAQUE_RING_STD) {
4725 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4726 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4727 tpr->rx_std_prod_idx);
4728 }
4729 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4730 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4731 TG3_RX_JUMBO_RING_SIZE;
4732 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4733 tpr->rx_jmb_prod_idx);
4734 }
4735 mmiowb();
4736 } else if (work_mask) {
4737 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4738 * updated before the producer indices can be updated.
4739 */
4740 smp_wmb();
4741
4361935a 4742 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4743 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4
MC		 4744
4745 napi_schedule(&tp->napi[1].napi);
1da177e4 4746 }
1da177e4
LT		 4747
4748 return received;
4749}
4750
35f2d7d0 4751static void tg3_poll_link(struct tg3 *tp)
1da177e4 4752{
1da177e4
LT		 4753 /* handle link change and other phy events */
4754 if (!(tp->tg3_flags &
4755 (TG3_FLAG_USE_LINKCHG_REG |
4756 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4757 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4758
1da177e4
LT		 4759 if (sblk->status & SD_STATUS_LINK_CHG) {
4760 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4761 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4762 spin_lock(&tp->lock);
dd477003
MC		 4763 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4764 tw32_f(MAC_STATUS,
4765 (MAC_STATUS_SYNC_CHANGED |
4766 MAC_STATUS_CFG_CHANGED |
4767 MAC_STATUS_MI_COMPLETION |
4768 MAC_STATUS_LNKSTATE_CHANGED));
4769 udelay(40);
4770 } else
4771 tg3_setup_phy(tp, 0);
f47c11ee 4772 spin_unlock(&tp->lock);
1da177e4
LT		 4773 }
4774 }
35f2d7d0
MC		 4775}
4776
b196c7e4
MC		 4777static void tg3_rx_prodring_xfer(struct tg3 *tp,
4778 struct tg3_rx_prodring_set *dpr,
4779 struct tg3_rx_prodring_set *spr)
4780{
4781 u32 si, di, cpycnt, src_prod_idx;
4782 int i;
4783
4784 while (1) {
4785 src_prod_idx = spr->rx_std_prod_idx;
4786
4787 /* Make sure updates to the rx_std_buffers[] entries and the
4788 * standard producer index are seen in the correct order.
4789 */
4790 smp_rmb();
4791
4792 if (spr->rx_std_cons_idx == src_prod_idx)
4793 break;
4794
4795 if (spr->rx_std_cons_idx < src_prod_idx)
4796 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4797 else
4798 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4799
4800 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4801
4802 si = spr->rx_std_cons_idx;
4803 di = dpr->rx_std_prod_idx;
4804
4805 memcpy(&dpr->rx_std_buffers[di],
4806 &spr->rx_std_buffers[si],
4807 cpycnt * sizeof(struct ring_info));
4808
4809 for (i = 0; i < cpycnt; i++, di++, si++) {
4810 struct tg3_rx_buffer_desc *sbd, *dbd;
4811 sbd = &spr->rx_std[si];
4812 dbd = &dpr->rx_std[di];
4813 dbd->addr_hi = sbd->addr_hi;
4814 dbd->addr_lo = sbd->addr_lo;
4815 }
4816
4817 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4818 TG3_RX_RING_SIZE;
4819 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4820 TG3_RX_RING_SIZE;
4821 }
4822
4823 while (1) {
4824 src_prod_idx = spr->rx_jmb_prod_idx;
4825
4826 /* Make sure updates to the rx_jmb_buffers[] entries and
4827 * the jumbo producer index are seen in the correct order.
4828 */
4829 smp_rmb();
4830
4831 if (spr->rx_jmb_cons_idx == src_prod_idx)
4832 break;
4833
4834 if (spr->rx_jmb_cons_idx < src_prod_idx)
4835 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4836 else
4837 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4838
4839 cpycnt = min(cpycnt,
4840 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4841
4842 si = spr->rx_jmb_cons_idx;
4843 di = dpr->rx_jmb_prod_idx;
4844
4845 memcpy(&dpr->rx_jmb_buffers[di],
4846 &spr->rx_jmb_buffers[si],
4847 cpycnt * sizeof(struct ring_info));
4848
4849 for (i = 0; i < cpycnt; i++, di++, si++) {
4850 struct tg3_rx_buffer_desc *sbd, *dbd;
4851 sbd = &spr->rx_jmb[si].std;
4852 dbd = &dpr->rx_jmb[di].std;
4853 dbd->addr_hi = sbd->addr_hi;
4854 dbd->addr_lo = sbd->addr_lo;
4855 }
4856
4857 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4858 TG3_RX_JUMBO_RING_SIZE;
4859 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4860 TG3_RX_JUMBO_RING_SIZE;
4861 }
4862}
4863
35f2d7d0
MC		 4864static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4865{
4866 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4867
4868 /* run TX completion thread */
f3f3f27e 4869 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4870 tg3_tx(tnapi);
6f535763 4871 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4872 return work_done;
1da177e4
LT		 4873 }
4874
1da177e4
LT		 4875 /* run RX thread, within the bounds set by NAPI.
4876 * All RX "locking" is done by ensuring outside
bea3348e 4877 * code synchronizes with tg3->napi.poll()
1da177e4 4878 */
8d9d7cfc 4879 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4880 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4881
b196c7e4
MC		 4882 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4883 int i;
4884 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4885 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4886
4887 for (i = 2; i < tp->irq_cnt; i++)
4888 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4889 tp->napi[i].prodring);
4890
4891 wmb();
4892
4893 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4894 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4895 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4896 }
4897
4898 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4899 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4900 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4901 }
4902
4903 mmiowb();
4904 }
4905
6f535763
DM		 4906 return work_done;
4907}
4908
35f2d7d0
MC		 4909static int tg3_poll_msix(struct napi_struct *napi, int budget)
4910{
4911 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4912 struct tg3 *tp = tnapi->tp;
4913 int work_done = 0;
4914 struct tg3_hw_status *sblk = tnapi->hw_status;
4915
4916 while (1) {
4917 work_done = tg3_poll_work(tnapi, work_done, budget);
4918
4919 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4920 goto tx_recovery;
4921
4922 if (unlikely(work_done >= budget))
4923 break;
4924
4925 /* tp->last_tag is used in tg3_restart_ints() below
4926 * to tell the hw how much work has been processed,
4927 * so we must read it before checking for more work.
4928 */
4929 tnapi->last_tag = sblk->status_tag;
4930 tnapi->last_irq_tag = tnapi->last_tag;
4931 rmb();
4932
4933 /* check for RX/TX work to do */
4934 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4935 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4936 napi_complete(napi);
4937 /* Reenable interrupts. */
4938 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4939 mmiowb();
4940 break;
4941 }
4942 }
4943
4944 return work_done;
4945
4946tx_recovery:
4947 /* work_done is guaranteed to be less than budget. */
4948 napi_complete(napi);
4949 schedule_work(&tp->reset_task);
4950 return work_done;
4951}
4952
6f535763
DM		 4953static int tg3_poll(struct napi_struct *napi, int budget)
4954{
8ef0442f
MC		 4955 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4956 struct tg3 *tp = tnapi->tp;
6f535763 4957 int work_done = 0;
898a56f8 4958 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4959
4960 while (1) {
35f2d7d0
MC		 4961 tg3_poll_link(tp);
4962
17375d25 4963 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4964
4965 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4966 goto tx_recovery;
4967
4968 if (unlikely(work_done >= budget))
4969 break;
4970
4fd7ab59 4971 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4972 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4973 * to tell the hw how much work has been processed,
4974 * so we must read it before checking for more work.
4975 */
898a56f8
MC		 4976 tnapi->last_tag = sblk->status_tag;
4977 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4978 rmb();
4979 } else
4980 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4981
17375d25 4982 if (likely(!tg3_has_work(tnapi))) {
288379f0 4983 napi_complete(napi);
17375d25 4984 tg3_int_reenable(tnapi);
6f535763
DM		 4985 break;
4986 }
1da177e4
LT		 4987 }
4988
bea3348e 4989 return work_done;
6f535763
DM		 4990
4991tx_recovery:
4fd7ab59 4992 /* work_done is guaranteed to be less than budget. */
288379f0 4993 napi_complete(napi);
6f535763 4994 schedule_work(&tp->reset_task);
4fd7ab59 4995 return work_done;
1da177e4
LT		 4996}
4997
f47c11ee
DM		 4998static void tg3_irq_quiesce(struct tg3 *tp)
4999{
4f125f42
MC		 5000 int i;
5001
f47c11ee
DM		 5002 BUG_ON(tp->irq_sync);
5003
5004 tp->irq_sync = 1;
5005 smp_mb();
5006
4f125f42
MC		 5007 for (i = 0; i < tp->irq_cnt; i++)
5008 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5009}
5010
5011static inline int tg3_irq_sync(struct tg3 *tp)
5012{
5013 return tp->irq_sync;
5014}
5015
5016/* Fully shutdown all tg3 driver activity elsewhere in the system.
5017 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5018 * with as well. Most of the time, this is not necessary except when
5019 * shutting down the device.
5020 */
5021static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5022{
46966545 5023 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5024 if (irq_sync)
5025 tg3_irq_quiesce(tp);
f47c11ee
DM		 5026}
5027
5028static inline void tg3_full_unlock(struct tg3 *tp)
5029{
f47c11ee
DM		 5030 spin_unlock_bh(&tp->lock);
5031}
5032
fcfa0a32
MC		 5033/* One-shot MSI handler - Chip automatically disables interrupt
5034 * after sending MSI so driver doesn't have to do it.
5035 */
7d12e780 5036static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5037{
09943a18
MC		 5038 struct tg3_napi *tnapi = dev_id;
5039 struct tg3 *tp = tnapi->tp;
fcfa0a32 5040
898a56f8 5041 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5042 if (tnapi->rx_rcb)
5043 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5044
5045 if (likely(!tg3_irq_sync(tp)))
09943a18 5046 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5047
5048 return IRQ_HANDLED;
5049}
5050
88b06bc2
MC		 5051/* MSI ISR - No need to check for interrupt sharing and no need to
5052 * flush status block and interrupt mailbox. PCI ordering rules
5053 * guarantee that MSI will arrive after the status block.
5054 */
7d12e780 5055static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5056{
09943a18
MC		 5057 struct tg3_napi *tnapi = dev_id;
5058 struct tg3 *tp = tnapi->tp;
88b06bc2 5059
898a56f8 5060 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5061 if (tnapi->rx_rcb)
5062 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5063 /*
fac9b83e 5064 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5065 * chip-internal interrupt pending events.
fac9b83e 5066 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5067 * NIC to stop sending us irqs, engaging "in-intr-handler"
5068 * event coalescing.
5069 */
5070 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5071 if (likely(!tg3_irq_sync(tp)))
09943a18 5072 napi_schedule(&tnapi->napi);
61487480 5073
88b06bc2
MC		 5074 return IRQ_RETVAL(1);
5075}
5076
7d12e780 5077static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5078{
09943a18
MC		 5079 struct tg3_napi *tnapi = dev_id;
5080 struct tg3 *tp = tnapi->tp;
898a56f8 5081 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5082 unsigned int handled = 1;
5083
1da177e4
LT		 5084 /* In INTx mode, it is possible for the interrupt to arrive at
5085 * the CPU before the status block posted prior to the interrupt.
5086 * Reading the PCI State register will confirm whether the
5087 * interrupt is ours and will flush the status block.
5088 */
d18edcb2
MC		 5089 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5090 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5091 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5092 handled = 0;
f47c11ee 5093 goto out;
fac9b83e 5094 }
d18edcb2
MC		 5095 }
5096
5097 /*
5098 * Writing any value to intr-mbox-0 clears PCI INTA# and
5099 * chip-internal interrupt pending events.
5100 * Writing non-zero to intr-mbox-0 additional tells the
5101 * NIC to stop sending us irqs, engaging "in-intr-handler"
5102 * event coalescing.
c04cb347
MC		 5103 *
5104 * Flush the mailbox to de-assert the IRQ immediately to prevent
5105 * spurious interrupts. The flush impacts performance but
5106 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5107 */
c04cb347 5108 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5109 if (tg3_irq_sync(tp))
5110 goto out;
5111 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5112 if (likely(tg3_has_work(tnapi))) {
72334482 5113 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5114 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5115 } else {
5116 /* No work, shared interrupt perhaps? re-enable
5117 * interrupts, and flush that PCI write
5118 */
5119 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5120 0x00000000);
fac9b83e 5121 }
f47c11ee 5122out:
fac9b83e
DM		 5123 return IRQ_RETVAL(handled);
5124}
5125
7d12e780 5126static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5127{
09943a18
MC		 5128 struct tg3_napi *tnapi = dev_id;
5129 struct tg3 *tp = tnapi->tp;
898a56f8 5130 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5131 unsigned int handled = 1;
5132
fac9b83e
DM		 5133 /* In INTx mode, it is possible for the interrupt to arrive at
5134 * the CPU before the status block posted prior to the interrupt.
5135 * Reading the PCI State register will confirm whether the
5136 * interrupt is ours and will flush the status block.
5137 */
898a56f8 5138 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5139 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5140 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5141 handled = 0;
f47c11ee 5142 goto out;
1da177e4 5143 }
d18edcb2
MC		 5144 }
5145
5146 /*
5147 * writing any value to intr-mbox-0 clears PCI INTA# and
5148 * chip-internal interrupt pending events.
5149 * writing non-zero to intr-mbox-0 additional tells the
5150 * NIC to stop sending us irqs, engaging "in-intr-handler"
5151 * event coalescing.
c04cb347
MC		 5152 *
5153 * Flush the mailbox to de-assert the IRQ immediately to prevent
5154 * spurious interrupts. The flush impacts performance but
5155 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5156 */
c04cb347 5157 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5158
5159 /*
5160 * In a shared interrupt configuration, sometimes other devices'
5161 * interrupts will scream. We record the current status tag here
5162 * so that the above check can report that the screaming interrupts
5163 * are unhandled. Eventually they will be silenced.
5164 */
898a56f8 5165 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5166
d18edcb2
MC		 5167 if (tg3_irq_sync(tp))
5168 goto out;
624f8e50 5169
72334482 5170 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5171
09943a18 5172 napi_schedule(&tnapi->napi);
624f8e50 5173
f47c11ee 5174out:
1da177e4
LT		 5175 return IRQ_RETVAL(handled);
5176}
5177
7938109f 5178/* ISR for interrupt test */
7d12e780 5179static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5180{
09943a18
MC		 5181 struct tg3_napi *tnapi = dev_id;
5182 struct tg3 *tp = tnapi->tp;
898a56f8 5183 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5184
f9804ddb
MC		 5185 if ((sblk->status & SD_STATUS_UPDATED) ||
5186 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5187 tg3_disable_ints(tp);
7938109f
MC		 5188 return IRQ_RETVAL(1);
5189 }
5190 return IRQ_RETVAL(0);
5191}
5192
8e7a22e3 5193static int tg3_init_hw(struct tg3 *, int);
944d980e 5194static int tg3_halt(struct tg3 *, int, int);
1da177e4 5195
b9ec6c1b
MC		 5196/* Restart hardware after configuration changes, self-test, etc.
5197 * Invoked with tp->lock held.
5198 */
5199static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5200 __releases(tp->lock)
5201 __acquires(tp->lock)
b9ec6c1b
MC		 5202{
5203 int err;
5204
5205 err = tg3_init_hw(tp, reset_phy);
5206 if (err) {
5207 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5208 "aborting.\n", tp->dev->name);
5209 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5210 tg3_full_unlock(tp);
5211 del_timer_sync(&tp->timer);
5212 tp->irq_sync = 0;
fed97810 5213 tg3_napi_enable(tp);
b9ec6c1b
MC		 5214 dev_close(tp->dev);
5215 tg3_full_lock(tp, 0);
5216 }
5217 return err;
5218}
5219
1da177e4
LT		 5220#ifdef CONFIG_NET_POLL_CONTROLLER
5221static void tg3_poll_controller(struct net_device *dev)
5222{
4f125f42 5223 int i;
88b06bc2
MC		 5224 struct tg3 *tp = netdev_priv(dev);
5225
4f125f42
MC		 5226 for (i = 0; i < tp->irq_cnt; i++)
5227 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5228}
5229#endif
5230
c4028958 5231static void tg3_reset_task(struct work_struct *work)
1da177e4 5232{
c4028958 5233 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5234 int err;
1da177e4
LT		 5235 unsigned int restart_timer;
5236
7faa006f 5237 tg3_full_lock(tp, 0);
7faa006f
MC		 5238
5239 if (!netif_running(tp->dev)) {
7faa006f
MC		 5240 tg3_full_unlock(tp);
5241 return;
5242 }
5243
5244 tg3_full_unlock(tp);
5245
b02fd9e3
MC		 5246 tg3_phy_stop(tp);
5247
1da177e4
LT		 5248 tg3_netif_stop(tp);
5249
f47c11ee 5250 tg3_full_lock(tp, 1);
1da177e4
LT		 5251
5252 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5253 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5254
df3e6548
MC		 5255 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5256 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5257 tp->write32_rx_mbox = tg3_write_flush_reg32;
5258 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5259 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5260 }
5261
944d980e 5262 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5263 err = tg3_init_hw(tp, 1);
5264 if (err)
b9ec6c1b 5265 goto out;
1da177e4
LT		 5266
5267 tg3_netif_start(tp);
5268
1da177e4
LT		 5269 if (restart_timer)
5270 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5271
b9ec6c1b 5272out:
7faa006f 5273 tg3_full_unlock(tp);
b02fd9e3
MC		 5274
5275 if (!err)
5276 tg3_phy_start(tp);
1da177e4
LT		 5277}
5278
b0408751
MC		 5279static void tg3_dump_short_state(struct tg3 *tp)
5280{
5281 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5282 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5283 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5284 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5285}
5286
1da177e4
LT		 5287static void tg3_tx_timeout(struct net_device *dev)
5288{
5289 struct tg3 *tp = netdev_priv(dev);
5290
b0408751 5291 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5292 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5293 dev->name);
b0408751
MC		 5294 tg3_dump_short_state(tp);
5295 }
1da177e4
LT		 5296
5297 schedule_work(&tp->reset_task);
5298}
5299
c58ec932
MC		 5300/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5301static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5302{
5303 u32 base = (u32) mapping & 0xffffffff;
5304
5305 return ((base > 0xffffdcc0) &&
5306 (base + len + 8 < base));
5307}
5308
72f2afb8
MC		 5309/* Test for DMA addresses > 40-bit */
5310static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5311 int len)
5312{
5313#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5314 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5315 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5316 return 0;
5317#else
5318 return 0;
5319#endif
5320}
5321
f3f3f27e 5322static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5323
72f2afb8 5324/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5325static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5326 struct sk_buff *skb, u32 last_plus_one,
5327 u32 *start, u32 base_flags, u32 mss)
1da177e4 5328{
24f4efd4 5329 struct tg3 *tp = tnapi->tp;
41588ba1 5330 struct sk_buff *new_skb;
c58ec932 5331 dma_addr_t new_addr = 0;
1da177e4 5332 u32 entry = *start;
c58ec932 5333 int i, ret = 0;
1da177e4 5334
41588ba1
MC		 5335 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5336 new_skb = skb_copy(skb, GFP_ATOMIC);
5337 else {
5338 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5339
5340 new_skb = skb_copy_expand(skb,
5341 skb_headroom(skb) + more_headroom,
5342 skb_tailroom(skb), GFP_ATOMIC);
5343 }
5344
1da177e4 5345 if (!new_skb) {
c58ec932
MC		 5346 ret = -1;
5347 } else {
5348 /* New SKB is guaranteed to be linear. */
5349 entry = *start;
f4188d8a
AD		 5350 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5351 PCI_DMA_TODEVICE);
5352 /* Make sure the mapping succeeded */
5353 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5354 ret = -1;
5355 dev_kfree_skb(new_skb);
5356 new_skb = NULL;
90079ce8 5357
c58ec932
MC		 5358 /* Make sure new skb does not cross any 4G boundaries.
5359 * Drop the packet if it does.
5360 */
f4188d8a
AD		 5361 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5362 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5363 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5364 PCI_DMA_TODEVICE);
c58ec932
MC		 5365 ret = -1;
5366 dev_kfree_skb(new_skb);
5367 new_skb = NULL;
5368 } else {
f3f3f27e 5369 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5370 base_flags, 1 | (mss << 1));
5371 *start = NEXT_TX(entry);
5372 }
1da177e4
LT		 5373 }
5374
1da177e4
LT		 5375 /* Now clean up the sw ring entries. */
5376 i = 0;
5377 while (entry != last_plus_one) {
f4188d8a
AD		 5378 int len;
5379
f3f3f27e 5380 if (i == 0)
f4188d8a 5381 len = skb_headlen(skb);
f3f3f27e 5382 else
f4188d8a
AD		 5383 len = skb_shinfo(skb)->frags[i-1].size;
5384
5385 pci_unmap_single(tp->pdev,
5386 pci_unmap_addr(&tnapi->tx_buffers[entry],
5387 mapping),
5388 len, PCI_DMA_TODEVICE);
5389 if (i == 0) {
5390 tnapi->tx_buffers[entry].skb = new_skb;
5391 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5392 new_addr);
5393 } else {
f3f3f27e 5394 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5395 }
1da177e4
LT		 5396 entry = NEXT_TX(entry);
5397 i++;
5398 }
5399
5400 dev_kfree_skb(skb);
5401
c58ec932 5402 return ret;
1da177e4
LT		 5403}
5404
f3f3f27e 5405static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5406 dma_addr_t mapping, int len, u32 flags,
5407 u32 mss_and_is_end)
5408{
f3f3f27e 5409 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5410 int is_end = (mss_and_is_end & 0x1);
5411 u32 mss = (mss_and_is_end >> 1);
5412 u32 vlan_tag = 0;
5413
5414 if (is_end)
5415 flags |= TXD_FLAG_END;
5416 if (flags & TXD_FLAG_VLAN) {
5417 vlan_tag = flags >> 16;
5418 flags &= 0xffff;
5419 }
5420 vlan_tag |= (mss << TXD_MSS_SHIFT);
5421
5422 txd->addr_hi = ((u64) mapping >> 32);
5423 txd->addr_lo = ((u64) mapping & 0xffffffff);
5424 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5425 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5426}
5427
5a6f3074 5428/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5429 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5430 */
61357325
SH		 5431static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5432 struct net_device *dev)
5a6f3074
MC		 5433{
5434 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5435 u32 len, entry, base_flags, mss;
90079ce8 5436 dma_addr_t mapping;
fe5f5787
MC		 5437 struct tg3_napi *tnapi;
5438 struct netdev_queue *txq;
f4188d8a
AD		 5439 unsigned int i, last;
5440
5a6f3074 5441
fe5f5787
MC		 5442 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5443 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5444 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5445 tnapi++;
5a6f3074 5446
00b70504 5447 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5448 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5449 * interrupt. Furthermore, IRQ processing runs lockless so we have
5450 * no IRQ context deadlocks to worry about either. Rejoice!
5451 */
f3f3f27e 5452 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5453 if (!netif_tx_queue_stopped(txq)) {
5454 netif_tx_stop_queue(txq);
5a6f3074
MC		 5455
5456 /* This is a hard error, log it. */
5457 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5458 "queue awake!\n", dev->name);
5459 }
5a6f3074
MC		 5460 return NETDEV_TX_BUSY;
5461 }
5462
f3f3f27e 5463 entry = tnapi->tx_prod;
5a6f3074 5464 base_flags = 0;
5a6f3074 5465 mss = 0;
c13e3713 5466 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5467 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5468 u32 hdrlen;
5a6f3074
MC		 5469
5470 if (skb_header_cloned(skb) &&
5471 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5472 dev_kfree_skb(skb);
5473 goto out_unlock;
5474 }
5475
b0026624 5476 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5477 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5478 else {
eddc9ec5
ACM		 5479 struct iphdr *iph = ip_hdr(skb);
5480
ab6a5bb6 5481 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5482 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5483
eddc9ec5
ACM		 5484 iph->check = 0;
5485 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5486 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5487 }
5a6f3074 5488
e849cdc3 5489 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5490 mss |= (hdrlen & 0xc) << 12;
5491 if (hdrlen & 0x10)
5492 base_flags |= 0x00000010;
5493 base_flags |= (hdrlen & 0x3e0) << 5;
5494 } else
5495 mss |= hdrlen << 9;
5496
5a6f3074
MC		 5497 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5498 TXD_FLAG_CPU_POST_DMA);
5499
aa8223c7 5500 tcp_hdr(skb)->check = 0;
5a6f3074 5501
5a6f3074 5502 }
84fa7933 5503 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5504 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5505#if TG3_VLAN_TAG_USED
5506 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5507 base_flags |= (TXD_FLAG_VLAN |
5508 (vlan_tx_tag_get(skb) << 16));
5509#endif
5510
f4188d8a
AD		 5511 len = skb_headlen(skb);
5512
5513 /* Queue skb data, a.k.a. the main skb fragment. */
5514 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5515 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5516 dev_kfree_skb(skb);
5517 goto out_unlock;
5518 }
5519
f3f3f27e 5520 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5521 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5522
b703df6f 5523 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5524 !mss && skb->len > ETH_DATA_LEN)
5525 base_flags |= TXD_FLAG_JMB_PKT;
5526
f3f3f27e 5527 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5528 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5529
5530 entry = NEXT_TX(entry);
5531
5532 /* Now loop through additional data fragments, and queue them. */
5533 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5534 last = skb_shinfo(skb)->nr_frags - 1;
5535 for (i = 0; i <= last; i++) {
5536 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5537
5538 len = frag->size;
f4188d8a
AD		 5539 mapping = pci_map_page(tp->pdev,
5540 frag->page,
5541 frag->page_offset,
5542 len, PCI_DMA_TODEVICE);
5543 if (pci_dma_mapping_error(tp->pdev, mapping))
5544 goto dma_error;
5545
f3f3f27e 5546 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5547 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5548 mapping);
5a6f3074 5549
f3f3f27e 5550 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5551 base_flags, (i == last) | (mss << 1));
5552
5553 entry = NEXT_TX(entry);
5554 }
5555 }
5556
5557 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5558 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5559
f3f3f27e
MC		 5560 tnapi->tx_prod = entry;
5561 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5562 netif_tx_stop_queue(txq);
f3f3f27e 5563 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5564 netif_tx_wake_queue(txq);
5a6f3074
MC		 5565 }
5566
5567out_unlock:
cdd0db05 5568 mmiowb();
5a6f3074
MC		 5569
5570 return NETDEV_TX_OK;
f4188d8a
AD		 5571
5572dma_error:
5573 last = i;
5574 entry = tnapi->tx_prod;
5575 tnapi->tx_buffers[entry].skb = NULL;
5576 pci_unmap_single(tp->pdev,
5577 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5578 skb_headlen(skb),
5579 PCI_DMA_TODEVICE);
5580 for (i = 0; i <= last; i++) {
5581 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5582 entry = NEXT_TX(entry);
5583
5584 pci_unmap_page(tp->pdev,
5585 pci_unmap_addr(&tnapi->tx_buffers[entry],
5586 mapping),
5587 frag->size, PCI_DMA_TODEVICE);
5588 }
5589
5590 dev_kfree_skb(skb);
5591 return NETDEV_TX_OK;
5a6f3074
MC		 5592}
5593
61357325
SH		 5594static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5595 struct net_device *);
52c0fd83
MC		 5596
5597/* Use GSO to workaround a rare TSO bug that may be triggered when the
5598 * TSO header is greater than 80 bytes.
5599 */
5600static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5601{
5602 struct sk_buff *segs, *nskb;
f3f3f27e 5603 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5604
5605 /* Estimate the number of fragments in the worst case */
f3f3f27e 5606 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5607 netif_stop_queue(tp->dev);
f3f3f27e 5608 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5609 return NETDEV_TX_BUSY;
5610
5611 netif_wake_queue(tp->dev);
52c0fd83
MC		 5612 }
5613
5614 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5615 if (IS_ERR(segs))
52c0fd83
MC		 5616 goto tg3_tso_bug_end;
5617
5618 do {
5619 nskb = segs;
5620 segs = segs->next;
5621 nskb->next = NULL;
5622 tg3_start_xmit_dma_bug(nskb, tp->dev);
5623 } while (segs);
5624
5625tg3_tso_bug_end:
5626 dev_kfree_skb(skb);
5627
5628 return NETDEV_TX_OK;
5629}
52c0fd83 5630
5a6f3074
MC		 5631/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5632 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5633 */
61357325
SH		 5634static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5635 struct net_device *dev)
1da177e4
LT		 5636{
5637 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5638 u32 len, entry, base_flags, mss;
5639 int would_hit_hwbug;
90079ce8 5640 dma_addr_t mapping;
24f4efd4
MC		 5641 struct tg3_napi *tnapi;
5642 struct netdev_queue *txq;
f4188d8a
AD		 5643 unsigned int i, last;
5644
1da177e4 5645
24f4efd4
MC		 5646 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5647 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5648 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5649 tnapi++;
1da177e4 5650
00b70504 5651 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5652 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5653 * interrupt. Furthermore, IRQ processing runs lockless so we have
5654 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5655 */
f3f3f27e 5656 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5657 if (!netif_tx_queue_stopped(txq)) {
5658 netif_tx_stop_queue(txq);
1f064a87
SH		 5659
5660 /* This is a hard error, log it. */
5661 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5662 "queue awake!\n", dev->name);
5663 }
1da177e4
LT		 5664 return NETDEV_TX_BUSY;
5665 }
5666
f3f3f27e 5667 entry = tnapi->tx_prod;
1da177e4 5668 base_flags = 0;
84fa7933 5669 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5670 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5671
c13e3713 5672 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5673 struct iphdr *iph;
92c6b8d1 5674 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5675
5676 if (skb_header_cloned(skb) &&
5677 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5678 dev_kfree_skb(skb);
5679 goto out_unlock;
5680 }
5681
ab6a5bb6 5682 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5683 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5684
52c0fd83
MC		 5685 hdr_len = ip_tcp_len + tcp_opt_len;
5686 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5687 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5688 return (tg3_tso_bug(tp, skb));
5689
1da177e4
LT		 5690 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5691 TXD_FLAG_CPU_POST_DMA);
5692
eddc9ec5
ACM		 5693 iph = ip_hdr(skb);
5694 iph->check = 0;
5695 iph->tot_len = htons(mss + hdr_len);
1da177e4 5696 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5697 tcp_hdr(skb)->check = 0;
1da177e4 5698 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5699 } else
5700 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5701 iph->daddr, 0,
5702 IPPROTO_TCP,
5703 0);
1da177e4 5704
615774fe
MC		 5705 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5706 mss |= (hdr_len & 0xc) << 12;
5707 if (hdr_len & 0x10)
5708 base_flags |= 0x00000010;
5709 base_flags |= (hdr_len & 0x3e0) << 5;
5710 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5711 mss |= hdr_len << 9;
5712 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5714 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5715 int tsflags;
5716
eddc9ec5 5717 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5718 mss |= (tsflags << 11);
5719 }
5720 } else {
eddc9ec5 5721 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5722 int tsflags;
5723
eddc9ec5 5724 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5725 base_flags |= tsflags << 12;
5726 }
5727 }
5728 }
1da177e4
LT		 5729#if TG3_VLAN_TAG_USED
5730 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5731 base_flags |= (TXD_FLAG_VLAN |
5732 (vlan_tx_tag_get(skb) << 16));
5733#endif
5734
b703df6f 5735 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5736 !mss && skb->len > ETH_DATA_LEN)
5737 base_flags |= TXD_FLAG_JMB_PKT;
5738
f4188d8a
AD		 5739 len = skb_headlen(skb);
5740
5741 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5742 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5743 dev_kfree_skb(skb);
5744 goto out_unlock;
5745 }
5746
f3f3f27e 5747 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5748 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5749
5750 would_hit_hwbug = 0;
5751
92c6b8d1
MC		 5752 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5753 would_hit_hwbug = 1;
5754
0e1406dd
MC		 5755 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5756 tg3_4g_overflow_test(mapping, len))
5757 would_hit_hwbug = 1;
5758
5759 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5760 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5761 would_hit_hwbug = 1;
0e1406dd
MC		 5762
5763 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5764 would_hit_hwbug = 1;
1da177e4 5765
f3f3f27e 5766 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5767 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5768
5769 entry = NEXT_TX(entry);
5770
5771 /* Now loop through additional data fragments, and queue them. */
5772 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5773 last = skb_shinfo(skb)->nr_frags - 1;
5774 for (i = 0; i <= last; i++) {
5775 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5776
5777 len = frag->size;
f4188d8a
AD		 5778 mapping = pci_map_page(tp->pdev,
5779 frag->page,
5780 frag->page_offset,
5781 len, PCI_DMA_TODEVICE);
1da177e4 5782
f3f3f27e 5783 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5784 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5785 mapping);
5786 if (pci_dma_mapping_error(tp->pdev, mapping))
5787 goto dma_error;
1da177e4 5788
92c6b8d1
MC		 5789 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5790 len <= 8)
5791 would_hit_hwbug = 1;
5792
0e1406dd
MC		 5793 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5794 tg3_4g_overflow_test(mapping, len))
c58ec932 5795 would_hit_hwbug = 1;
1da177e4 5796
0e1406dd
MC		 5797 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5798 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5799 would_hit_hwbug = 1;
5800
1da177e4 5801 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5802 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5803 base_flags, (i == last)|(mss << 1));
5804 else
f3f3f27e 5805 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5806 base_flags, (i == last));
5807
5808 entry = NEXT_TX(entry);
5809 }
5810 }
5811
5812 if (would_hit_hwbug) {
5813 u32 last_plus_one = entry;
5814 u32 start;
1da177e4 5815
c58ec932
MC		 5816 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5817 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5818
5819 /* If the workaround fails due to memory/mapping
5820 * failure, silently drop this packet.
5821 */
24f4efd4 5822 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5823 &start, base_flags, mss))
1da177e4
LT		 5824 goto out_unlock;
5825
5826 entry = start;
5827 }
5828
5829 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5830 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5831
f3f3f27e
MC		 5832 tnapi->tx_prod = entry;
5833 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5834 netif_tx_stop_queue(txq);
f3f3f27e 5835 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5836 netif_tx_wake_queue(txq);
51b91468 5837 }
1da177e4
LT		 5838
5839out_unlock:
cdd0db05 5840 mmiowb();
1da177e4
LT		 5841
5842 return NETDEV_TX_OK;
f4188d8a
AD		 5843
5844dma_error:
5845 last = i;
5846 entry = tnapi->tx_prod;
5847 tnapi->tx_buffers[entry].skb = NULL;
5848 pci_unmap_single(tp->pdev,
5849 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5850 skb_headlen(skb),
5851 PCI_DMA_TODEVICE);
5852 for (i = 0; i <= last; i++) {
5853 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5854 entry = NEXT_TX(entry);
5855
5856 pci_unmap_page(tp->pdev,
5857 pci_unmap_addr(&tnapi->tx_buffers[entry],
5858 mapping),
5859 frag->size, PCI_DMA_TODEVICE);
5860 }
5861
5862 dev_kfree_skb(skb);
5863 return NETDEV_TX_OK;
1da177e4
LT		 5864}
5865
5866static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5867 int new_mtu)
5868{
5869 dev->mtu = new_mtu;
5870
ef7f5ec0 5871 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5872 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5873 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5874 ethtool_op_set_tso(dev, 0);
5875 }
5876 else
5877 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5878 } else {
a4e2b347 5879 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5880 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5881 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5882 }
1da177e4
LT		 5883}
5884
5885static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5886{
5887 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5888 int err;
1da177e4
LT		 5889
5890 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5891 return -EINVAL;
5892
5893 if (!netif_running(dev)) {
5894 /* We'll just catch it later when the
5895 * device is up'd.
5896 */
5897 tg3_set_mtu(dev, tp, new_mtu);
5898 return 0;
5899 }
5900
b02fd9e3
MC		 5901 tg3_phy_stop(tp);
5902
1da177e4 5903 tg3_netif_stop(tp);
f47c11ee
DM		 5904
5905 tg3_full_lock(tp, 1);
1da177e4 5906
944d980e 5907 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5908
5909 tg3_set_mtu(dev, tp, new_mtu);
5910
b9ec6c1b 5911 err = tg3_restart_hw(tp, 0);
1da177e4 5912
b9ec6c1b
MC		 5913 if (!err)
5914 tg3_netif_start(tp);
1da177e4 5915
f47c11ee 5916 tg3_full_unlock(tp);
1da177e4 5917
b02fd9e3
MC		 5918 if (!err)
5919 tg3_phy_start(tp);
5920
b9ec6c1b 5921 return err;
1da177e4
LT		 5922}
5923
21f581a5
MC		 5924static void tg3_rx_prodring_free(struct tg3 *tp,
5925 struct tg3_rx_prodring_set *tpr)
1da177e4 5926{
1da177e4
LT		 5927 int i;
5928
b196c7e4
MC		 5929 if (tpr != &tp->prodring[0]) {
5930 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5931 i = (i + 1) % TG3_RX_RING_SIZE)
5932 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5933 tp->rx_pkt_map_sz);
5934
5935 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5936 for (i = tpr->rx_jmb_cons_idx;
5937 i != tpr->rx_jmb_prod_idx;
5938 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5939 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5940 TG3_RX_JMB_MAP_SZ);
5941 }
5942 }
5943
2b2cdb65 5944 return;
b196c7e4 5945 }
1da177e4 5946
2b2cdb65
MC		 5947 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5948 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5949 tp->rx_pkt_map_sz);
1da177e4 5950
cf7a7298 5951 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5952 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5953 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5954 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5955 }
5956}
5957
5958/* Initialize tx/rx rings for packet processing.
5959 *
5960 * The chip has been shut down and the driver detached from
5961 * the networking, so no interrupts or new tx packets will
5962 * end up in the driver. tp->{tx,}lock are held and thus
5963 * we may not sleep.
5964 */
21f581a5
MC		 5965static int tg3_rx_prodring_alloc(struct tg3 *tp,
5966 struct tg3_rx_prodring_set *tpr)
1da177e4 5967{
287be12e 5968 u32 i, rx_pkt_dma_sz;
1da177e4 5969
b196c7e4
MC		 5970 tpr->rx_std_cons_idx = 0;
5971 tpr->rx_std_prod_idx = 0;
5972 tpr->rx_jmb_cons_idx = 0;
5973 tpr->rx_jmb_prod_idx = 0;
5974
2b2cdb65
MC		 5975 if (tpr != &tp->prodring[0]) {
5976 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5977 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5978 memset(&tpr->rx_jmb_buffers[0], 0,
5979 TG3_RX_JMB_BUFF_RING_SIZE);
5980 goto done;
5981 }
5982
1da177e4 5983 /* Zero out all descriptors. */
21f581a5 5984 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5985
287be12e 5986 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5987 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5988 tp->dev->mtu > ETH_DATA_LEN)
5989 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5990 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5991
1da177e4
LT		 5992 /* Initialize invariants of the rings, we only set this
5993 * stuff once. This works because the card does not
5994 * write into the rx buffer posting rings.
5995 */
5996 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5997 struct tg3_rx_buffer_desc *rxd;
5998
21f581a5 5999 rxd = &tpr->rx_std[i];
287be12e 6000 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6001 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6002 rxd->opaque = (RXD_OPAQUE_RING_STD |
6003 (i << RXD_OPAQUE_INDEX_SHIFT));
6004 }
6005
1da177e4
LT		 6006 /* Now allocate fresh SKBs for each rx ring. */
6007 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6008 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6009 printk(KERN_WARNING PFX
6010 "%s: Using a smaller RX standard ring, "
6011 "only %d out of %d buffers were allocated "
6012 "successfully.\n",
6013 tp->dev->name, i, tp->rx_pending);
6014 if (i == 0)
cf7a7298 6015 goto initfail;
32d8c572 6016 tp->rx_pending = i;
1da177e4 6017 break;
32d8c572 6018 }
1da177e4
LT		 6019 }
6020
cf7a7298
MC		 6021 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6022 goto done;
6023
21f581a5 6024 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6025
0f893dc6 6026 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6027 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6028 struct tg3_rx_buffer_desc *rxd;
6029
79ed5ac7 6030 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6031 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6032 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6033 RXD_FLAG_JUMBO;
6034 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6035 (i << RXD_OPAQUE_INDEX_SHIFT));
6036 }
6037
1da177e4 6038 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6039 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6040 i) < 0) {
32d8c572
MC		 6041 printk(KERN_WARNING PFX
6042 "%s: Using a smaller RX jumbo ring, "
6043 "only %d out of %d buffers were "
6044 "allocated successfully.\n",
6045 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6046 if (i == 0)
6047 goto initfail;
32d8c572 6048 tp->rx_jumbo_pending = i;
1da177e4 6049 break;
32d8c572 6050 }
1da177e4
LT		 6051 }
6052 }
cf7a7298
MC		 6053
6054done:
32d8c572 6055 return 0;
cf7a7298
MC		 6056
6057initfail:
21f581a5 6058 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6059 return -ENOMEM;
1da177e4
LT		 6060}
6061
21f581a5
MC		 6062static void tg3_rx_prodring_fini(struct tg3 *tp,
6063 struct tg3_rx_prodring_set *tpr)
1da177e4 6064{
21f581a5
MC		 6065 kfree(tpr->rx_std_buffers);
6066 tpr->rx_std_buffers = NULL;
6067 kfree(tpr->rx_jmb_buffers);
6068 tpr->rx_jmb_buffers = NULL;
6069 if (tpr->rx_std) {
1da177e4 6070 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6071 tpr->rx_std, tpr->rx_std_mapping);
6072 tpr->rx_std = NULL;
1da177e4 6073 }
21f581a5 6074 if (tpr->rx_jmb) {
1da177e4 6075 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6076 tpr->rx_jmb, tpr->rx_jmb_mapping);
6077 tpr->rx_jmb = NULL;
1da177e4 6078 }
cf7a7298
MC		 6079}
6080
21f581a5
MC		 6081static int tg3_rx_prodring_init(struct tg3 *tp,
6082 struct tg3_rx_prodring_set *tpr)
cf7a7298 6083{
2b2cdb65 6084 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6085 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6086 return -ENOMEM;
6087
21f581a5
MC		 6088 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6089 &tpr->rx_std_mapping);
6090 if (!tpr->rx_std)
cf7a7298
MC		 6091 goto err_out;
6092
6093 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6094 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6095 GFP_KERNEL);
6096 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6097 goto err_out;
6098
21f581a5
MC		 6099 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6100 TG3_RX_JUMBO_RING_BYTES,
6101 &tpr->rx_jmb_mapping);
6102 if (!tpr->rx_jmb)
cf7a7298
MC		 6103 goto err_out;
6104 }
6105
6106 return 0;
6107
6108err_out:
21f581a5 6109 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6110 return -ENOMEM;
6111}
6112
6113/* Free up pending packets in all rx/tx rings.
6114 *
6115 * The chip has been shut down and the driver detached from
6116 * the networking, so no interrupts or new tx packets will
6117 * end up in the driver. tp->{tx,}lock is not held and we are not
6118 * in an interrupt context and thus may sleep.
6119 */
6120static void tg3_free_rings(struct tg3 *tp)
6121{
f77a6a8e 6122 int i, j;
cf7a7298 6123
f77a6a8e
MC		 6124 for (j = 0; j < tp->irq_cnt; j++) {
6125 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6126
0c1d0e2b
MC		 6127 if (!tnapi->tx_buffers)
6128 continue;
6129
f77a6a8e 6130 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6131 struct ring_info *txp;
f77a6a8e 6132 struct sk_buff *skb;
f4188d8a 6133 unsigned int k;
cf7a7298 6134
f77a6a8e
MC		 6135 txp = &tnapi->tx_buffers[i];
6136 skb = txp->skb;
cf7a7298 6137
f77a6a8e
MC		 6138 if (skb == NULL) {
6139 i++;
6140 continue;
6141 }
cf7a7298 6142
f4188d8a
AD		 6143 pci_unmap_single(tp->pdev,
6144 pci_unmap_addr(txp, mapping),
6145 skb_headlen(skb),
6146 PCI_DMA_TODEVICE);
f77a6a8e 6147 txp->skb = NULL;
cf7a7298 6148
f4188d8a
AD		 6149 i++;
6150
6151 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6152 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6153 pci_unmap_page(tp->pdev,
6154 pci_unmap_addr(txp, mapping),
6155 skb_shinfo(skb)->frags[k].size,
6156 PCI_DMA_TODEVICE);
6157 i++;
6158 }
f77a6a8e
MC		 6159
6160 dev_kfree_skb_any(skb);
6161 }
cf7a7298 6162
2b2cdb65
MC		 6163 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6164 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6165 }
cf7a7298
MC		 6166}
6167
6168/* Initialize tx/rx rings for packet processing.
6169 *
6170 * The chip has been shut down and the driver detached from
6171 * the networking, so no interrupts or new tx packets will
6172 * end up in the driver. tp->{tx,}lock are held and thus
6173 * we may not sleep.
6174 */
6175static int tg3_init_rings(struct tg3 *tp)
6176{
f77a6a8e 6177 int i;
72334482 6178
cf7a7298
MC		 6179 /* Free up all the SKBs. */
6180 tg3_free_rings(tp);
6181
f77a6a8e
MC		 6182 for (i = 0; i < tp->irq_cnt; i++) {
6183 struct tg3_napi *tnapi = &tp->napi[i];
6184
6185 tnapi->last_tag = 0;
6186 tnapi->last_irq_tag = 0;
6187 tnapi->hw_status->status = 0;
6188 tnapi->hw_status->status_tag = 0;
6189 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6190
f77a6a8e
MC		 6191 tnapi->tx_prod = 0;
6192 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6193 if (tnapi->tx_ring)
6194 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6195
6196 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6197 if (tnapi->rx_rcb)
6198 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 6199
6200 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6201 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6202 return -ENOMEM;
f77a6a8e 6203 }
72334482 6204
2b2cdb65 6205 return 0;
cf7a7298
MC		 6206}
6207
6208/*
6209 * Must not be invoked with interrupt sources disabled and
6210 * the hardware shutdown down.
6211 */
6212static void tg3_free_consistent(struct tg3 *tp)
6213{
f77a6a8e 6214 int i;
898a56f8 6215
f77a6a8e
MC		 6216 for (i = 0; i < tp->irq_cnt; i++) {
6217 struct tg3_napi *tnapi = &tp->napi[i];
6218
6219 if (tnapi->tx_ring) {
6220 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6221 tnapi->tx_ring, tnapi->tx_desc_mapping);
6222 tnapi->tx_ring = NULL;
6223 }
6224
6225 kfree(tnapi->tx_buffers);
6226 tnapi->tx_buffers = NULL;
6227
6228 if (tnapi->rx_rcb) {
6229 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6230 tnapi->rx_rcb,
6231 tnapi->rx_rcb_mapping);
6232 tnapi->rx_rcb = NULL;
6233 }
6234
6235 if (tnapi->hw_status) {
6236 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6237 tnapi->hw_status,
6238 tnapi->status_mapping);
6239 tnapi->hw_status = NULL;
6240 }
1da177e4 6241 }
f77a6a8e 6242
1da177e4
LT		 6243 if (tp->hw_stats) {
6244 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6245 tp->hw_stats, tp->stats_mapping);
6246 tp->hw_stats = NULL;
6247 }
f77a6a8e 6248
2b2cdb65
MC		 6249 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6250 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6251}
6252
6253/*
6254 * Must not be invoked with interrupt sources disabled and
6255 * the hardware shutdown down. Can sleep.
6256 */
6257static int tg3_alloc_consistent(struct tg3 *tp)
6258{
f77a6a8e 6259 int i;
898a56f8 6260
2b2cdb65
MC		 6261 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6262 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6263 goto err_out;
6264 }
1da177e4 6265
f77a6a8e
MC		 6266 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6267 sizeof(struct tg3_hw_stats),
6268 &tp->stats_mapping);
6269 if (!tp->hw_stats)
1da177e4
LT		 6270 goto err_out;
6271
f77a6a8e 6272 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6273
f77a6a8e
MC		 6274 for (i = 0; i < tp->irq_cnt; i++) {
6275 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6276 struct tg3_hw_status *sblk;
1da177e4 6277
f77a6a8e
MC		 6278 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6279 TG3_HW_STATUS_SIZE,
6280 &tnapi->status_mapping);
6281 if (!tnapi->hw_status)
6282 goto err_out;
898a56f8 6283
f77a6a8e 6284 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6285 sblk = tnapi->hw_status;
6286
19cfaecc
MC		 6287 /* If multivector TSS is enabled, vector 0 does not handle
6288 * tx interrupts. Don't allocate any resources for it.
6289 */
6290 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6291 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6292 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6293 TG3_TX_RING_SIZE,
6294 GFP_KERNEL);
6295 if (!tnapi->tx_buffers)
6296 goto err_out;
6297
6298 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6299 TG3_TX_RING_BYTES,
6300 &tnapi->tx_desc_mapping);
6301 if (!tnapi->tx_ring)
6302 goto err_out;
6303 }
6304
8d9d7cfc
MC		 6305 /*
6306 * When RSS is enabled, the status block format changes
6307 * slightly. The "rx_jumbo_consumer", "reserved",
6308 * and "rx_mini_consumer" members get mapped to the
6309 * other three rx return ring producer indexes.
6310 */
6311 switch (i) {
6312 default:
6313 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6314 break;
6315 case 2:
6316 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6317 break;
6318 case 3:
6319 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6320 break;
6321 case 4:
6322 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6323 break;
6324 }
72334482 6325
b196c7e4
MC		 6326 if (tp->irq_cnt == 1)
6327 tnapi->prodring = &tp->prodring[0];
6328 else if (i)
6329 tnapi->prodring = &tp->prodring[i - 1];
6330
0c1d0e2b
MC		 6331 /*
6332 * If multivector RSS is enabled, vector 0 does not handle
6333 * rx or tx interrupts. Don't allocate any resources for it.
6334 */
6335 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6336 continue;
6337
f77a6a8e
MC		 6338 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6339 TG3_RX_RCB_RING_BYTES(tp),
6340 &tnapi->rx_rcb_mapping);
6341 if (!tnapi->rx_rcb)
6342 goto err_out;
72334482 6343
f77a6a8e 6344 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6345 }
1da177e4
LT		 6346
6347 return 0;
6348
6349err_out:
6350 tg3_free_consistent(tp);
6351 return -ENOMEM;
6352}
6353
6354#define MAX_WAIT_CNT 1000
6355
6356/* To stop a block, clear the enable bit and poll till it
6357 * clears. tp->lock is held.
6358 */
b3b7d6be 6359static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6360{
6361 unsigned int i;
6362 u32 val;
6363
6364 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6365 switch (ofs) {
6366 case RCVLSC_MODE:
6367 case DMAC_MODE:
6368 case MBFREE_MODE:
6369 case BUFMGR_MODE:
6370 case MEMARB_MODE:
6371 /* We can't enable/disable these bits of the
6372 * 5705/5750, just say success.
6373 */
6374 return 0;
6375
6376 default:
6377 break;
855e1111 6378 }
1da177e4
LT		 6379 }
6380
6381 val = tr32(ofs);
6382 val &= ~enable_bit;
6383 tw32_f(ofs, val);
6384
6385 for (i = 0; i < MAX_WAIT_CNT; i++) {
6386 udelay(100);
6387 val = tr32(ofs);
6388 if ((val & enable_bit) == 0)
6389 break;
6390 }
6391
b3b7d6be 6392 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6393 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6394 "ofs=%lx enable_bit=%x\n",
6395 ofs, enable_bit);
6396 return -ENODEV;
6397 }
6398
6399 return 0;
6400}
6401
6402/* tp->lock is held. */
b3b7d6be 6403static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6404{
6405 int i, err;
6406
6407 tg3_disable_ints(tp);
6408
6409 tp->rx_mode &= ~RX_MODE_ENABLE;
6410 tw32_f(MAC_RX_MODE, tp->rx_mode);
6411 udelay(10);
6412
b3b7d6be
DM		 6413 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6414 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6415 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6416 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6417 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6418 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6419
6420 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6421 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6422 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6423 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6424 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6425 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6426 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6427
6428 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6429 tw32_f(MAC_MODE, tp->mac_mode);
6430 udelay(40);
6431
6432 tp->tx_mode &= ~TX_MODE_ENABLE;
6433 tw32_f(MAC_TX_MODE, tp->tx_mode);
6434
6435 for (i = 0; i < MAX_WAIT_CNT; i++) {
6436 udelay(100);
6437 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6438 break;
6439 }
6440 if (i >= MAX_WAIT_CNT) {
6441 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6442 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6443 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6444 err |= -ENODEV;
1da177e4
LT		 6445 }
6446
e6de8ad1 6447 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6448 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6449 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6450
6451 tw32(FTQ_RESET, 0xffffffff);
6452 tw32(FTQ_RESET, 0x00000000);
6453
b3b7d6be
DM		 6454 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6455 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6456
f77a6a8e
MC		 6457 for (i = 0; i < tp->irq_cnt; i++) {
6458 struct tg3_napi *tnapi = &tp->napi[i];
6459 if (tnapi->hw_status)
6460 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6461 }
1da177e4
LT		 6462 if (tp->hw_stats)
6463 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6464
1da177e4
LT		 6465 return err;
6466}
6467
0d3031d9
MC		 6468static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6469{
6470 int i;
6471 u32 apedata;
6472
6473 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6474 if (apedata != APE_SEG_SIG_MAGIC)
6475 return;
6476
6477 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6478 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6479 return;
6480
6481 /* Wait for up to 1 millisecond for APE to service previous event. */
6482 for (i = 0; i < 10; i++) {
6483 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6484 return;
6485
6486 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6487
6488 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6490 event | APE_EVENT_STATUS_EVENT_PENDING);
6491
6492 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6493
6494 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6495 break;
6496
6497 udelay(100);
6498 }
6499
6500 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6501 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6502}
6503
6504static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6505{
6506 u32 event;
6507 u32 apedata;
6508
6509 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6510 return;
6511
6512 switch (kind) {
6513 case RESET_KIND_INIT:
6514 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6515 APE_HOST_SEG_SIG_MAGIC);
6516 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6517 APE_HOST_SEG_LEN_MAGIC);
6518 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6519 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6520 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6521 APE_HOST_DRIVER_ID_MAGIC);
6522 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6523 APE_HOST_BEHAV_NO_PHYLOCK);
6524
6525 event = APE_EVENT_STATUS_STATE_START;
6526 break;
6527 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6528 /* With the interface we are currently using,
6529 * APE does not track driver state. Wiping
6530 * out the HOST SEGMENT SIGNATURE forces
6531 * the APE to assume OS absent status.
6532 */
6533 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6534
0d3031d9
MC		 6535 event = APE_EVENT_STATUS_STATE_UNLOAD;
6536 break;
6537 case RESET_KIND_SUSPEND:
6538 event = APE_EVENT_STATUS_STATE_SUSPEND;
6539 break;
6540 default:
6541 return;
6542 }
6543
6544 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6545
6546 tg3_ape_send_event(tp, event);
6547}
6548
1da177e4
LT		 6549/* tp->lock is held. */
6550static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6551{
f49639e6
DM		 6552 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6553 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6554
6555 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6556 switch (kind) {
6557 case RESET_KIND_INIT:
6558 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6559 DRV_STATE_START);
6560 break;
6561
6562 case RESET_KIND_SHUTDOWN:
6563 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6564 DRV_STATE_UNLOAD);
6565 break;
6566
6567 case RESET_KIND_SUSPEND:
6568 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6569 DRV_STATE_SUSPEND);
6570 break;
6571
6572 default:
6573 break;
855e1111 6574 }
1da177e4 6575 }
0d3031d9
MC		 6576
6577 if (kind == RESET_KIND_INIT ||
6578 kind == RESET_KIND_SUSPEND)
6579 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6580}
6581
6582/* tp->lock is held. */
6583static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6584{
6585 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6586 switch (kind) {
6587 case RESET_KIND_INIT:
6588 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6589 DRV_STATE_START_DONE);
6590 break;
6591
6592 case RESET_KIND_SHUTDOWN:
6593 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6594 DRV_STATE_UNLOAD_DONE);
6595 break;
6596
6597 default:
6598 break;
855e1111 6599 }
1da177e4 6600 }
0d3031d9
MC		 6601
6602 if (kind == RESET_KIND_SHUTDOWN)
6603 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6604}
6605
6606/* tp->lock is held. */
6607static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6608{
6609 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6610 switch (kind) {
6611 case RESET_KIND_INIT:
6612 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6613 DRV_STATE_START);
6614 break;
6615
6616 case RESET_KIND_SHUTDOWN:
6617 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6618 DRV_STATE_UNLOAD);
6619 break;
6620
6621 case RESET_KIND_SUSPEND:
6622 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6623 DRV_STATE_SUSPEND);
6624 break;
6625
6626 default:
6627 break;
855e1111 6628 }
1da177e4
LT		 6629 }
6630}
6631
7a6f4369
MC		 6632static int tg3_poll_fw(struct tg3 *tp)
6633{
6634 int i;
6635 u32 val;
6636
b5d3772c 6637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6638 /* Wait up to 20ms for init done. */
6639 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6640 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6641 return 0;
0ccead18 6642 udelay(100);
b5d3772c
MC		 6643 }
6644 return -ENODEV;
6645 }
6646
7a6f4369
MC		 6647 /* Wait for firmware initialization to complete. */
6648 for (i = 0; i < 100000; i++) {
6649 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6650 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6651 break;
6652 udelay(10);
6653 }
6654
6655 /* Chip might not be fitted with firmware. Some Sun onboard
6656 * parts are configured like that. So don't signal the timeout
6657 * of the above loop as an error, but do report the lack of
6658 * running firmware once.
6659 */
6660 if (i >= 100000 &&
6661 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6662 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6663
6664 printk(KERN_INFO PFX "%s: No firmware running.\n",
6665 tp->dev->name);
6666 }
6667
6668 return 0;
6669}
6670
ee6a99b5
MC		 6671/* Save PCI command register before chip reset */
6672static void tg3_save_pci_state(struct tg3 *tp)
6673{
8a6eac90 6674 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6675}
6676
6677/* Restore PCI state after chip reset */
6678static void tg3_restore_pci_state(struct tg3 *tp)
6679{
6680 u32 val;
6681
6682 /* Re-enable indirect register accesses. */
6683 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6684 tp->misc_host_ctrl);
6685
6686 /* Set MAX PCI retry to zero. */
6687 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6688 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6689 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6690 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6691 /* Allow reads and writes to the APE register and memory space. */
6692 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6693 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6694 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6695 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6696
8a6eac90 6697 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6698
fcb389df
MC		 6699 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6700 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6701 pcie_set_readrq(tp->pdev, 4096);
6702 else {
6703 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6704 tp->pci_cacheline_sz);
6705 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6706 tp->pci_lat_timer);
6707 }
114342f2 6708 }
5f5c51e3 6709
ee6a99b5 6710 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6711 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6712 u16 pcix_cmd;
6713
6714 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6715 &pcix_cmd);
6716 pcix_cmd &= ~PCI_X_CMD_ERO;
6717 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6718 pcix_cmd);
6719 }
ee6a99b5
MC		 6720
6721 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6722
6723 /* Chip reset on 5780 will reset MSI enable bit,
6724 * so need to restore it.
6725 */
6726 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6727 u16 ctrl;
6728
6729 pci_read_config_word(tp->pdev,
6730 tp->msi_cap + PCI_MSI_FLAGS,
6731 &ctrl);
6732 pci_write_config_word(tp->pdev,
6733 tp->msi_cap + PCI_MSI_FLAGS,
6734 ctrl | PCI_MSI_FLAGS_ENABLE);
6735 val = tr32(MSGINT_MODE);
6736 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6737 }
6738 }
6739}
6740
1da177e4
LT		 6741static void tg3_stop_fw(struct tg3 *);
6742
6743/* tp->lock is held. */
6744static int tg3_chip_reset(struct tg3 *tp)
6745{
6746 u32 val;
1ee582d8 6747 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6748 int i, err;
1da177e4 6749
f49639e6
DM		 6750 tg3_nvram_lock(tp);
6751
77b483f1
MC		 6752 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6753
f49639e6
DM		 6754 /* No matching tg3_nvram_unlock() after this because
6755 * chip reset below will undo the nvram lock.
6756 */
6757 tp->nvram_lock_cnt = 0;
1da177e4 6758
ee6a99b5
MC		 6759 /* GRC_MISC_CFG core clock reset will clear the memory
6760 * enable bit in PCI register 4 and the MSI enable bit
6761 * on some chips, so we save relevant registers here.
6762 */
6763 tg3_save_pci_state(tp);
6764
d9ab5ad1 6765 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6766 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6767 tw32(GRC_FASTBOOT_PC, 0);
6768
1da177e4
LT		 6769 /*
6770 * We must avoid the readl() that normally takes place.
6771 * It locks machines, causes machine checks, and other
6772 * fun things. So, temporarily disable the 5701
6773 * hardware workaround, while we do the reset.
6774 */
1ee582d8
MC		 6775 write_op = tp->write32;
6776 if (write_op == tg3_write_flush_reg32)
6777 tp->write32 = tg3_write32;
1da177e4 6778
d18edcb2
MC		 6779 /* Prevent the irq handler from reading or writing PCI registers
6780 * during chip reset when the memory enable bit in the PCI command
6781 * register may be cleared. The chip does not generate interrupt
6782 * at this time, but the irq handler may still be called due to irq
6783 * sharing or irqpoll.
6784 */
6785 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6786 for (i = 0; i < tp->irq_cnt; i++) {
6787 struct tg3_napi *tnapi = &tp->napi[i];
6788 if (tnapi->hw_status) {
6789 tnapi->hw_status->status = 0;
6790 tnapi->hw_status->status_tag = 0;
6791 }
6792 tnapi->last_tag = 0;
6793 tnapi->last_irq_tag = 0;
b8fa2f3a 6794 }
d18edcb2 6795 smp_mb();
4f125f42
MC		 6796
6797 for (i = 0; i < tp->irq_cnt; i++)
6798 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6799
255ca311
MC		 6800 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6801 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6802 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6803 }
6804
1da177e4
LT		 6805 /* do the reset */
6806 val = GRC_MISC_CFG_CORECLK_RESET;
6807
6808 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6809 if (tr32(0x7e2c) == 0x60) {
6810 tw32(0x7e2c, 0x20);
6811 }
6812 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6813 tw32(GRC_MISC_CFG, (1 << 29));
6814 val |= (1 << 29);
6815 }
6816 }
6817
b5d3772c
MC		 6818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6819 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6820 tw32(GRC_VCPU_EXT_CTRL,
6821 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6822 }
6823
1da177e4
LT		 6824 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6825 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6826 tw32(GRC_MISC_CFG, val);
6827
1ee582d8
MC		 6828 /* restore 5701 hardware bug workaround write method */
6829 tp->write32 = write_op;
1da177e4
LT		 6830
6831 /* Unfortunately, we have to delay before the PCI read back.
6832 * Some 575X chips even will not respond to a PCI cfg access
6833 * when the reset command is given to the chip.
6834 *
6835 * How do these hardware designers expect things to work
6836 * properly if the PCI write is posted for a long period
6837 * of time? It is always necessary to have some method by
6838 * which a register read back can occur to push the write
6839 * out which does the reset.
6840 *
6841 * For most tg3 variants the trick below was working.
6842 * Ho hum...
6843 */
6844 udelay(120);
6845
6846 /* Flush PCI posted writes. The normal MMIO registers
6847 * are inaccessible at this time so this is the only
6848 * way to make this reliably (actually, this is no longer
6849 * the case, see above). I tried to use indirect
6850 * register read/write but this upset some 5701 variants.
6851 */
6852 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6853
6854 udelay(120);
6855
5e7dfd0f 6856 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6857 u16 val16;
6858
1da177e4
LT		 6859 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6860 int i;
6861 u32 cfg_val;
6862
6863 /* Wait for link training to complete. */
6864 for (i = 0; i < 5000; i++)
6865 udelay(100);
6866
6867 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6868 pci_write_config_dword(tp->pdev, 0xc4,
6869 cfg_val | (1 << 15));
6870 }
5e7dfd0f 6871
e7126997
MC		 6872 /* Clear the "no snoop" and "relaxed ordering" bits. */
6873 pci_read_config_word(tp->pdev,
6874 tp->pcie_cap + PCI_EXP_DEVCTL,
6875 &val16);
6876 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6877 PCI_EXP_DEVCTL_NOSNOOP_EN);
6878 /*
6879 * Older PCIe devices only support the 128 byte
6880 * MPS setting. Enforce the restriction.
5e7dfd0f 6881 */
e7126997
MC		 6882 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6883 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6884 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6885 pci_write_config_word(tp->pdev,
6886 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6887 val16);
5e7dfd0f
MC		 6888
6889 pcie_set_readrq(tp->pdev, 4096);
6890
6891 /* Clear error status */
6892 pci_write_config_word(tp->pdev,
6893 tp->pcie_cap + PCI_EXP_DEVSTA,
6894 PCI_EXP_DEVSTA_CED |
6895 PCI_EXP_DEVSTA_NFED |
6896 PCI_EXP_DEVSTA_FED |
6897 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6898 }
6899
ee6a99b5 6900 tg3_restore_pci_state(tp);
1da177e4 6901
d18edcb2
MC		 6902 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6903
ee6a99b5
MC		 6904 val = 0;
6905 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6906 val = tr32(MEMARB_MODE);
ee6a99b5 6907 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6908
6909 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6910 tg3_stop_fw(tp);
6911 tw32(0x5000, 0x400);
6912 }
6913
6914 tw32(GRC_MODE, tp->grc_mode);
6915
6916 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6917 val = tr32(0xc4);
1da177e4
LT		 6918
6919 tw32(0xc4, val | (1 << 15));
6920 }
6921
6922 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6924 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6925 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6926 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6927 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6928 }
6929
6930 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6931 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6932 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6933 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6934 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6935 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6936 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6937 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6938 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6939 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6940 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6941 } else
6942 tw32_f(MAC_MODE, 0);
6943 udelay(40);
6944
77b483f1
MC		 6945 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6946
7a6f4369
MC		 6947 err = tg3_poll_fw(tp);
6948 if (err)
6949 return err;
1da177e4 6950
0a9140cf
MC		 6951 tg3_mdio_start(tp);
6952
52cdf852
MC		 6953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6954 u8 phy_addr;
6955
6956 phy_addr = tp->phy_addr;
6957 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6958
6959 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6960 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6961 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6962 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6963 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6964 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6965 udelay(10);
6966
6967 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6968 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6969 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6970 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6971 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6972 udelay(10);
6973
6974 tp->phy_addr = phy_addr;
6975 }
6976
1da177e4 6977 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6978 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6979 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 6980 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6981 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 6982 val = tr32(0x7c00);
1da177e4
LT		 6983
6984 tw32(0x7c00, val | (1 << 25));
6985 }
6986
6987 /* Reprobe ASF enable state. */
6988 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6989 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6990 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6991 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6992 u32 nic_cfg;
6993
6994 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6995 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6996 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6997 tp->last_event_jiffies = jiffies;
cbf46853 6998 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6999 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7000 }
7001 }
7002
7003 return 0;
7004}
7005
7006/* tp->lock is held. */
7007static void tg3_stop_fw(struct tg3 *tp)
7008{
0d3031d9
MC		 7009 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7010 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7011 /* Wait for RX cpu to ACK the previous event. */
7012 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7013
7014 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7015
7016 tg3_generate_fw_event(tp);
1da177e4 7017
7c5026aa
MC		 7018 /* Wait for RX cpu to ACK this event. */
7019 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7020 }
7021}
7022
7023/* tp->lock is held. */
944d980e 7024static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7025{
7026 int err;
7027
7028 tg3_stop_fw(tp);
7029
944d980e 7030 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7031
b3b7d6be 7032 tg3_abort_hw(tp, silent);
1da177e4
LT		 7033 err = tg3_chip_reset(tp);
7034
daba2a63
MC		 7035 __tg3_set_mac_addr(tp, 0);
7036
944d980e
MC		 7037 tg3_write_sig_legacy(tp, kind);
7038 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7039
7040 if (err)
7041 return err;
7042
7043 return 0;
7044}
7045
1da177e4
LT		 7046#define RX_CPU_SCRATCH_BASE 0x30000
7047#define RX_CPU_SCRATCH_SIZE 0x04000
7048#define TX_CPU_SCRATCH_BASE 0x34000
7049#define TX_CPU_SCRATCH_SIZE 0x04000
7050
7051/* tp->lock is held. */
7052static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7053{
7054 int i;
7055
5d9428de
ES		 7056 BUG_ON(offset == TX_CPU_BASE &&
7057 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7058
b5d3772c
MC		 7059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7060 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7061
7062 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7063 return 0;
7064 }
1da177e4
LT		 7065 if (offset == RX_CPU_BASE) {
7066 for (i = 0; i < 10000; i++) {
7067 tw32(offset + CPU_STATE, 0xffffffff);
7068 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7069 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7070 break;
7071 }
7072
7073 tw32(offset + CPU_STATE, 0xffffffff);
7074 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7075 udelay(10);
7076 } else {
7077 for (i = 0; i < 10000; i++) {
7078 tw32(offset + CPU_STATE, 0xffffffff);
7079 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7080 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7081 break;
7082 }
7083 }
7084
7085 if (i >= 10000) {
7086 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7087 "and %s CPU\n",
7088 tp->dev->name,
7089 (offset == RX_CPU_BASE ? "RX" : "TX"));
7090 return -ENODEV;
7091 }
ec41c7df
MC		 7092
7093 /* Clear firmware's nvram arbitration. */
7094 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7095 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7096 return 0;
7097}
7098
7099struct fw_info {
077f849d
JSR		 7100 unsigned int fw_base;
7101 unsigned int fw_len;
7102 const __be32 *fw_data;
1da177e4
LT		 7103};
7104
7105/* tp->lock is held. */
7106static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7107 int cpu_scratch_size, struct fw_info *info)
7108{
ec41c7df 7109 int err, lock_err, i;
1da177e4
LT		 7110 void (*write_op)(struct tg3 *, u32, u32);
7111
7112 if (cpu_base == TX_CPU_BASE &&
7113 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7114 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7115 "TX cpu firmware on %s which is 5705.\n",
7116 tp->dev->name);
7117 return -EINVAL;
7118 }
7119
7120 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7121 write_op = tg3_write_mem;
7122 else
7123 write_op = tg3_write_indirect_reg32;
7124
1b628151
MC		 7125 /* It is possible that bootcode is still loading at this point.
7126 * Get the nvram lock first before halting the cpu.
7127 */
ec41c7df 7128 lock_err = tg3_nvram_lock(tp);
1da177e4 7129 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7130 if (!lock_err)
7131 tg3_nvram_unlock(tp);
1da177e4
LT		 7132 if (err)
7133 goto out;
7134
7135 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7136 write_op(tp, cpu_scratch_base + i, 0);
7137 tw32(cpu_base + CPU_STATE, 0xffffffff);
7138 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7139 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7140 write_op(tp, (cpu_scratch_base +
077f849d 7141 (info->fw_base & 0xffff) +
1da177e4 7142 (i * sizeof(u32))),
077f849d 7143 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7144
7145 err = 0;
7146
7147out:
1da177e4
LT		 7148 return err;
7149}
7150
7151/* tp->lock is held. */
7152static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7153{
7154 struct fw_info info;
077f849d 7155 const __be32 *fw_data;
1da177e4
LT		 7156 int err, i;
7157
077f849d
JSR		 7158 fw_data = (void *)tp->fw->data;
7159
7160 /* Firmware blob starts with version numbers, followed by
7161 start address and length. We are setting complete length.
7162 length = end_address_of_bss - start_address_of_text.
7163 Remainder is the blob to be loaded contiguously
7164 from start address. */
7165
7166 info.fw_base = be32_to_cpu(fw_data[1]);
7167 info.fw_len = tp->fw->size - 12;
7168 info.fw_data = &fw_data[3];
1da177e4
LT		 7169
7170 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7171 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7172 &info);
7173 if (err)
7174 return err;
7175
7176 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7177 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7178 &info);
7179 if (err)
7180 return err;
7181
7182 /* Now startup only the RX cpu. */
7183 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7184 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7185
7186 for (i = 0; i < 5; i++) {
077f849d 7187 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7188 break;
7189 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7190 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7191 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7192 udelay(1000);
7193 }
7194 if (i >= 5) {
7195 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7196 "to set RX CPU PC, is %08x should be %08x\n",
7197 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7198 info.fw_base);
1da177e4
LT		 7199 return -ENODEV;
7200 }
7201 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7202 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7203
7204 return 0;
7205}
7206
1da177e4 7207/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7208
7209/* tp->lock is held. */
7210static int tg3_load_tso_firmware(struct tg3 *tp)
7211{
7212 struct fw_info info;
077f849d 7213 const __be32 *fw_data;
1da177e4
LT		 7214 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7215 int err, i;
7216
7217 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7218 return 0;
7219
077f849d
JSR		 7220 fw_data = (void *)tp->fw->data;
7221
7222 /* Firmware blob starts with version numbers, followed by
7223 start address and length. We are setting complete length.
7224 length = end_address_of_bss - start_address_of_text.
7225 Remainder is the blob to be loaded contiguously
7226 from start address. */
7227
7228 info.fw_base = be32_to_cpu(fw_data[1]);
7229 cpu_scratch_size = tp->fw_len;
7230 info.fw_len = tp->fw->size - 12;
7231 info.fw_data = &fw_data[3];
7232
1da177e4 7233 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7234 cpu_base = RX_CPU_BASE;
7235 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7236 } else {
1da177e4
LT		 7237 cpu_base = TX_CPU_BASE;
7238 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7239 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7240 }
7241
7242 err = tg3_load_firmware_cpu(tp, cpu_base,
7243 cpu_scratch_base, cpu_scratch_size,
7244 &info);
7245 if (err)
7246 return err;
7247
7248 /* Now startup the cpu. */
7249 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7250 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7251
7252 for (i = 0; i < 5; i++) {
077f849d 7253 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7254 break;
7255 tw32(cpu_base + CPU_STATE, 0xffffffff);
7256 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7257 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7258 udelay(1000);
7259 }
7260 if (i >= 5) {
7261 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7262 "to set CPU PC, is %08x should be %08x\n",
7263 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7264 info.fw_base);
1da177e4
LT		 7265 return -ENODEV;
7266 }
7267 tw32(cpu_base + CPU_STATE, 0xffffffff);
7268 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7269 return 0;
7270}
7271
1da177e4 7272
1da177e4
LT		 7273static int tg3_set_mac_addr(struct net_device *dev, void *p)
7274{
7275 struct tg3 *tp = netdev_priv(dev);
7276 struct sockaddr *addr = p;
986e0aeb 7277 int err = 0, skip_mac_1 = 0;
1da177e4 7278
f9804ddb
MC		 7279 if (!is_valid_ether_addr(addr->sa_data))
7280 return -EINVAL;
7281
1da177e4
LT		 7282 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7283
e75f7c90
MC		 7284 if (!netif_running(dev))
7285 return 0;
7286
58712ef9 7287 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7288 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7289
986e0aeb
MC		 7290 addr0_high = tr32(MAC_ADDR_0_HIGH);
7291 addr0_low = tr32(MAC_ADDR_0_LOW);
7292 addr1_high = tr32(MAC_ADDR_1_HIGH);
7293 addr1_low = tr32(MAC_ADDR_1_LOW);
7294
7295 /* Skip MAC addr 1 if ASF is using it. */
7296 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7297 !(addr1_high == 0 && addr1_low == 0))
7298 skip_mac_1 = 1;
58712ef9 7299 }
986e0aeb
MC		 7300 spin_lock_bh(&tp->lock);
7301 __tg3_set_mac_addr(tp, skip_mac_1);
7302 spin_unlock_bh(&tp->lock);
1da177e4 7303
b9ec6c1b 7304 return err;
1da177e4
LT		 7305}
7306
7307/* tp->lock is held. */
7308static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7309 dma_addr_t mapping, u32 maxlen_flags,
7310 u32 nic_addr)
7311{
7312 tg3_write_mem(tp,
7313 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7314 ((u64) mapping >> 32));
7315 tg3_write_mem(tp,
7316 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7317 ((u64) mapping & 0xffffffff));
7318 tg3_write_mem(tp,
7319 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7320 maxlen_flags);
7321
7322 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7323 tg3_write_mem(tp,
7324 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7325 nic_addr);
7326}
7327
7328static void __tg3_set_rx_mode(struct net_device *);
d244c892 7329static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7330{
b6080e12
MC		 7331 int i;
7332
19cfaecc 7333 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7334 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7335 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7336 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7337 } else {
7338 tw32(HOSTCC_TXCOL_TICKS, 0);
7339 tw32(HOSTCC_TXMAX_FRAMES, 0);
7340 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7341 }
b6080e12 7342
19cfaecc
MC		 7343 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7344 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7345 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7346 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7347 } else {
b6080e12
MC		 7348 tw32(HOSTCC_RXCOL_TICKS, 0);
7349 tw32(HOSTCC_RXMAX_FRAMES, 0);
7350 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7351 }
b6080e12 7352
15f9850d
DM		 7353 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7354 u32 val = ec->stats_block_coalesce_usecs;
7355
b6080e12
MC		 7356 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7357 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7358
15f9850d
DM		 7359 if (!netif_carrier_ok(tp->dev))
7360 val = 0;
7361
7362 tw32(HOSTCC_STAT_COAL_TICKS, val);
7363 }
b6080e12
MC		 7364
7365 for (i = 0; i < tp->irq_cnt - 1; i++) {
7366 u32 reg;
7367
7368 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7369 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7370 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7371 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7372 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7373 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7374
7375 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7376 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7377 tw32(reg, ec->tx_coalesce_usecs);
7378 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7379 tw32(reg, ec->tx_max_coalesced_frames);
7380 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7381 tw32(reg, ec->tx_max_coalesced_frames_irq);
7382 }
b6080e12
MC		 7383 }
7384
7385 for (; i < tp->irq_max - 1; i++) {
7386 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7387 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7388 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7389
7390 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7391 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7392 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7393 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7394 }
b6080e12 7395 }
15f9850d 7396}
1da177e4 7397
2d31ecaf
MC		 7398/* tp->lock is held. */
7399static void tg3_rings_reset(struct tg3 *tp)
7400{
7401 int i;
f77a6a8e 7402 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7403 struct tg3_napi *tnapi = &tp->napi[0];
7404
7405 /* Disable all transmit rings but the first. */
7406 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7407 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7408 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7409 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7410 else
7411 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7412
7413 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7414 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7415 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7416 BDINFO_FLAGS_DISABLED);
7417
7418
7419 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7420 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7421 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7422 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7423 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7424 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7426 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7427 else
7428 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7429
7430 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7431 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7432 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7433 BDINFO_FLAGS_DISABLED);
7434
7435 /* Disable interrupts */
7436 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7437
7438 /* Zero mailbox registers. */
f77a6a8e
MC		 7439 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7440 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7441 tp->napi[i].tx_prod = 0;
7442 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7444 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7445 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7446 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7447 }
c2353a32
MC		 7448 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7449 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7450 } else {
7451 tp->napi[0].tx_prod = 0;
7452 tp->napi[0].tx_cons = 0;
7453 tw32_mailbox(tp->napi[0].prodmbox, 0);
7454 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7455 }
2d31ecaf
MC		 7456
7457 /* Make sure the NIC-based send BD rings are disabled. */
7458 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7459 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7460 for (i = 0; i < 16; i++)
7461 tw32_tx_mbox(mbox + i * 8, 0);
7462 }
7463
7464 txrcb = NIC_SRAM_SEND_RCB;
7465 rxrcb = NIC_SRAM_RCV_RET_RCB;
7466
7467 /* Clear status block in ram. */
7468 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7469
7470 /* Set status block DMA address */
7471 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7472 ((u64) tnapi->status_mapping >> 32));
7473 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7474 ((u64) tnapi->status_mapping & 0xffffffff));
7475
f77a6a8e
MC		 7476 if (tnapi->tx_ring) {
7477 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7478 (TG3_TX_RING_SIZE <<
7479 BDINFO_FLAGS_MAXLEN_SHIFT),
7480 NIC_SRAM_TX_BUFFER_DESC);
7481 txrcb += TG3_BDINFO_SIZE;
7482 }
7483
7484 if (tnapi->rx_rcb) {
7485 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7486 (TG3_RX_RCB_RING_SIZE(tp) <<
7487 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7488 rxrcb += TG3_BDINFO_SIZE;
7489 }
7490
7491 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7492
f77a6a8e
MC		 7493 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7494 u64 mapping = (u64)tnapi->status_mapping;
7495 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7496 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7497
7498 /* Clear status block in ram. */
7499 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7500
19cfaecc
MC		 7501 if (tnapi->tx_ring) {
7502 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7503 (TG3_TX_RING_SIZE <<
7504 BDINFO_FLAGS_MAXLEN_SHIFT),
7505 NIC_SRAM_TX_BUFFER_DESC);
7506 txrcb += TG3_BDINFO_SIZE;
7507 }
f77a6a8e
MC		 7508
7509 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7510 (TG3_RX_RCB_RING_SIZE(tp) <<
7511 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7512
7513 stblk += 8;
f77a6a8e
MC		 7514 rxrcb += TG3_BDINFO_SIZE;
7515 }
2d31ecaf
MC		 7516}
7517
1da177e4 7518/* tp->lock is held. */
8e7a22e3 7519static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7520{
7521 u32 val, rdmac_mode;
7522 int i, err, limit;
21f581a5 7523 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7524
7525 tg3_disable_ints(tp);
7526
7527 tg3_stop_fw(tp);
7528
7529 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7530
7531 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7532 tg3_abort_hw(tp, 1);
1da177e4
LT		 7533 }
7534
dd477003
MC		 7535 if (reset_phy &&
7536 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7537 tg3_phy_reset(tp);
7538
1da177e4
LT		 7539 err = tg3_chip_reset(tp);
7540 if (err)
7541 return err;
7542
7543 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7544
bcb37f6c 7545 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7546 val = tr32(TG3_CPMU_CTRL);
7547 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7548 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7549
7550 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7551 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7552 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7553 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7554
7555 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7556 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7557 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7558 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7559
7560 val = tr32(TG3_CPMU_HST_ACC);
7561 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7562 val |= CPMU_HST_ACC_MACCLK_6_25;
7563 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7564 }
7565
33466d93
MC		 7566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7567 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7568 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7569 PCIE_PWR_MGMT_L1_THRESH_4MS;
7570 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7571
7572 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7573 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7574
7575 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7576
f40386c8
MC		 7577 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7578 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7579 }
7580
614b0590
MC		 7581 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7582 u32 grc_mode = tr32(GRC_MODE);
7583
7584 /* Access the lower 1K of PL PCIE block registers. */
7585 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7586 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7587
7588 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7589 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7590 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7591
7592 tw32(GRC_MODE, grc_mode);
7593 }
7594
1da177e4
LT		 7595 /* This works around an issue with Athlon chipsets on
7596 * B3 tigon3 silicon. This bit has no effect on any
7597 * other revision. But do not set this on PCI Express
795d01c5 7598 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7599 */
795d01c5
MC		 7600 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7601 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7602 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7603 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7604 }
1da177e4
LT		 7605
7606 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7607 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7608 val = tr32(TG3PCI_PCISTATE);
7609 val |= PCISTATE_RETRY_SAME_DMA;
7610 tw32(TG3PCI_PCISTATE, val);
7611 }
7612
0d3031d9
MC		 7613 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7614 /* Allow reads and writes to the
7615 * APE register and memory space.
7616 */
7617 val = tr32(TG3PCI_PCISTATE);
7618 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7619 PCISTATE_ALLOW_APE_SHMEM_WR;
7620 tw32(TG3PCI_PCISTATE, val);
7621 }
7622
1da177e4
LT		 7623 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7624 /* Enable some hw fixes. */
7625 val = tr32(TG3PCI_MSI_DATA);
7626 val |= (1 << 26) | (1 << 28) | (1 << 29);
7627 tw32(TG3PCI_MSI_DATA, val);
7628 }
7629
7630 /* Descriptor ring init may make accesses to the
7631 * NIC SRAM area to setup the TX descriptors, so we
7632 * can only do this after the hardware has been
7633 * successfully reset.
7634 */
32d8c572
MC		 7635 err = tg3_init_rings(tp);
7636 if (err)
7637 return err;
1da177e4 7638
b703df6f
MC		 7639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7641 val = tr32(TG3PCI_DMA_RW_CTRL) &
7642 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7643 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7644 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7645 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7646 /* This value is determined during the probe time DMA
7647 * engine test, tg3_test_dma.
7648 */
7649 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7650 }
1da177e4
LT		 7651
7652 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7653 GRC_MODE_4X_NIC_SEND_RINGS |
7654 GRC_MODE_NO_TX_PHDR_CSUM |
7655 GRC_MODE_NO_RX_PHDR_CSUM);
7656 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7657
7658 /* Pseudo-header checksum is done by hardware logic and not
7659 * the offload processers, so make the chip do the pseudo-
7660 * header checksums on receive. For transmit it is more
7661 * convenient to do the pseudo-header checksum in software
7662 * as Linux does that on transmit for us in all cases.
7663 */
7664 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7665
7666 tw32(GRC_MODE,
7667 tp->grc_mode |
7668 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7669
7670 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7671 val = tr32(GRC_MISC_CFG);
7672 val &= ~0xff;
7673 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7674 tw32(GRC_MISC_CFG, val);
7675
7676 /* Initialize MBUF/DESC pool. */
cbf46853 7677 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7678 /* Do nothing. */
7679 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7680 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7682 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7683 else
7684 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7685 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7686 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7687 }
1da177e4
LT		 7688 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7689 int fw_len;
7690
077f849d 7691 fw_len = tp->fw_len;
1da177e4
LT		 7692 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7693 tw32(BUFMGR_MB_POOL_ADDR,
7694 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7695 tw32(BUFMGR_MB_POOL_SIZE,
7696 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7697 }
1da177e4 7698
0f893dc6 7699 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7700 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7701 tp->bufmgr_config.mbuf_read_dma_low_water);
7702 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7703 tp->bufmgr_config.mbuf_mac_rx_low_water);
7704 tw32(BUFMGR_MB_HIGH_WATER,
7705 tp->bufmgr_config.mbuf_high_water);
7706 } else {
7707 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7708 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7709 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7710 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7711 tw32(BUFMGR_MB_HIGH_WATER,
7712 tp->bufmgr_config.mbuf_high_water_jumbo);
7713 }
7714 tw32(BUFMGR_DMA_LOW_WATER,
7715 tp->bufmgr_config.dma_low_water);
7716 tw32(BUFMGR_DMA_HIGH_WATER,
7717 tp->bufmgr_config.dma_high_water);
7718
7719 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7720 for (i = 0; i < 2000; i++) {
7721 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7722 break;
7723 udelay(10);
7724 }
7725 if (i >= 2000) {
7726 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7727 tp->dev->name);
7728 return -ENODEV;
7729 }
7730
7731 /* Setup replenish threshold. */
f92905de
MC		 7732 val = tp->rx_pending / 8;
7733 if (val == 0)
7734 val = 1;
7735 else if (val > tp->rx_std_max_post)
7736 val = tp->rx_std_max_post;
b5d3772c
MC		 7737 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7738 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7739 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7740
7741 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7742 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7743 }
f92905de
MC		 7744
7745 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7746
7747 /* Initialize TG3_BDINFO's at:
7748 * RCVDBDI_STD_BD: standard eth size rx ring
7749 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7750 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7751 *
7752 * like so:
7753 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7754 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7755 * ring attribute flags
7756 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7757 *
7758 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7759 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7760 *
7761 * The size of each ring is fixed in the firmware, but the location is
7762 * configurable.
7763 */
7764 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7765 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7766 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7767 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7768 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7769 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7770 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7771
fdb72b38
MC		 7772 /* Disable the mini ring */
7773 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7774 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7775 BDINFO_FLAGS_DISABLED);
7776
fdb72b38
MC		 7777 /* Program the jumbo buffer descriptor ring control
7778 * blocks on those devices that have them.
7779 */
8f666b07 7780 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7781 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7782 /* Setup replenish threshold. */
7783 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7784
0f893dc6 7785 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7786 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7787 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7788 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7789 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7790 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7791 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7792 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7793 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7794 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7795 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7796 } else {
7797 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7798 BDINFO_FLAGS_DISABLED);
7799 }
7800
b703df6f
MC		 7801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7803 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7804 (RX_STD_MAX_SIZE << 2);
7805 else
7806 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7807 } else
7808 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7809
7810 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7811
411da640 7812 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7813 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7814
411da640 7815 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7816 tp->rx_jumbo_pending : 0;
66711e66 7817 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7818
b703df6f
MC		 7819 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7821 tw32(STD_REPLENISH_LWM, 32);
7822 tw32(JMB_REPLENISH_LWM, 16);
7823 }
7824
2d31ecaf
MC		 7825 tg3_rings_reset(tp);
7826
1da177e4 7827 /* Initialize MAC address and backoff seed. */
986e0aeb 7828 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7829
7830 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7831 tw32(MAC_RX_MTU_SIZE,
7832 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7833
7834 /* The slot time is changed by tg3_setup_phy if we
7835 * run at gigabit with half duplex.
7836 */
7837 tw32(MAC_TX_LENGTHS,
7838 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7839 (6 << TX_LENGTHS_IPG_SHIFT) |
7840 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7841
7842 /* Receive rules. */
7843 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7844 tw32(RCVLPC_CONFIG, 0x0181);
7845
7846 /* Calculate RDMAC_MODE setting early, we need it to determine
7847 * the RCVLPC_STATE_ENABLE mask.
7848 */
7849 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7850 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7851 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7852 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7853 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7854
57e6983c 7855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7856 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7858 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7859 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7860 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7861
85e94ced
MC		 7862 /* If statement applies to 5705 and 5750 PCI devices only */
7863 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7864 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7865 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7866 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7868 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7869 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7870 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7871 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7872 }
7873 }
7874
85e94ced
MC		 7875 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7876 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7877
1da177e4 7878 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7879 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7880
e849cdc3
MC		 7881 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7884 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7885
7886 /* Receive/send statistics. */
1661394e
MC		 7887 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7888 val = tr32(RCVLPC_STATS_ENABLE);
7889 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7890 tw32(RCVLPC_STATS_ENABLE, val);
7891 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7892 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7893 val = tr32(RCVLPC_STATS_ENABLE);
7894 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7895 tw32(RCVLPC_STATS_ENABLE, val);
7896 } else {
7897 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7898 }
7899 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7900 tw32(SNDDATAI_STATSENAB, 0xffffff);
7901 tw32(SNDDATAI_STATSCTRL,
7902 (SNDDATAI_SCTRL_ENABLE |
7903 SNDDATAI_SCTRL_FASTUPD));
7904
7905 /* Setup host coalescing engine. */
7906 tw32(HOSTCC_MODE, 0);
7907 for (i = 0; i < 2000; i++) {
7908 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7909 break;
7910 udelay(10);
7911 }
7912
d244c892 7913 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7914
1da177e4
LT		 7915 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7916 /* Status/statistics block address. See tg3_timer,
7917 * the tg3_periodic_fetch_stats call there, and
7918 * tg3_get_stats to see how this works for 5705/5750 chips.
7919 */
1da177e4
LT		 7920 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7921 ((u64) tp->stats_mapping >> 32));
7922 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7923 ((u64) tp->stats_mapping & 0xffffffff));
7924 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7925
1da177e4 7926 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7927
7928 /* Clear statistics and status block memory areas */
7929 for (i = NIC_SRAM_STATS_BLK;
7930 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7931 i += sizeof(u32)) {
7932 tg3_write_mem(tp, i, 0);
7933 udelay(40);
7934 }
1da177e4
LT		 7935 }
7936
7937 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7938
7939 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7940 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7941 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7942 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7943
c94e3941
MC		 7944 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7945 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7946 /* reset to prevent losing 1st rx packet intermittently */
7947 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7948 udelay(10);
7949 }
7950
3bda1258
MC		 7951 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7952 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7953 else
7954 tp->mac_mode = 0;
7955 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7956 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7957 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7958 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7959 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7960 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7961 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7962 udelay(40);
7963
314fba34 7964 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7965 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7966 * register to preserve the GPIO settings for LOMs. The GPIOs,
7967 * whether used as inputs or outputs, are set by boot code after
7968 * reset.
7969 */
9d26e213 7970 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7971 u32 gpio_mask;
7972
9d26e213
MC		 7973 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7974 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7975 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7976
7977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7978 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7979 GRC_LCLCTRL_GPIO_OUTPUT3;
7980
af36e6b6
MC		 7981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7982 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7983
aaf84465 7984 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7985 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7986
7987 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7988 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7989 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7990 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7991 }
1da177e4
LT		 7992 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7993 udelay(100);
7994
baf8a94a
MC		 7995 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7996 val = tr32(MSGINT_MODE);
7997 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7998 tw32(MSGINT_MODE, val);
7999 }
8000
1da177e4
LT		 8001 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8002 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8003 udelay(40);
8004 }
8005
8006 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8007 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8008 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8009 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8010 WDMAC_MODE_LNGREAD_ENAB);
8011
85e94ced
MC		 8012 /* If statement applies to 5705 and 5750 PCI devices only */
8013 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8014 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8016 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8017 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8018 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8019 /* nothing */
8020 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8021 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8022 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8023 val |= WDMAC_MODE_RX_ACCEL;
8024 }
8025 }
8026
d9ab5ad1 8027 /* Enable host coalescing bug fix */
321d32a0 8028 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8029 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8030
788a035e
MC		 8031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8032 val |= WDMAC_MODE_BURST_ALL_DATA;
8033
1da177e4
LT		 8034 tw32_f(WDMAC_MODE, val);
8035 udelay(40);
8036
9974a356
MC		 8037 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8038 u16 pcix_cmd;
8039
8040 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8041 &pcix_cmd);
1da177e4 8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8043 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8044 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8045 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8046 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8047 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8048 }
9974a356
MC		 8049 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8050 pcix_cmd);
1da177e4
LT		 8051 }
8052
8053 tw32_f(RDMAC_MODE, rdmac_mode);
8054 udelay(40);
8055
8056 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8057 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8058 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8059
8060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8061 tw32(SNDDATAC_MODE,
8062 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8063 else
8064 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8065
1da177e4
LT		 8066 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8067 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8068 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8069 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8070 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8071 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8072 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8073 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8074 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8075 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8076 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8077
8078 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8079 err = tg3_load_5701_a0_firmware_fix(tp);
8080 if (err)
8081 return err;
8082 }
8083
1da177e4
LT		 8084 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8085 err = tg3_load_tso_firmware(tp);
8086 if (err)
8087 return err;
8088 }
1da177e4
LT		 8089
8090 tp->tx_mode = TX_MODE_ENABLE;
8091 tw32_f(MAC_TX_MODE, tp->tx_mode);
8092 udelay(100);
8093
baf8a94a
MC		 8094 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8095 u32 reg = MAC_RSS_INDIR_TBL_0;
8096 u8 *ent = (u8 *)&val;
8097
8098 /* Setup the indirection table */
8099 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8100 int idx = i % sizeof(val);
8101
8102 ent[idx] = i % (tp->irq_cnt - 1);
8103 if (idx == sizeof(val) - 1) {
8104 tw32(reg, val);
8105 reg += 4;
8106 }
8107 }
8108
8109 /* Setup the "secret" hash key. */
8110 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8111 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8112 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8113 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8114 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8115 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8116 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8117 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8118 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8119 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8120 }
8121
1da177e4 8122 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8123 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8124 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8125
baf8a94a
MC		 8126 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8127 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8128 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8129 RX_MODE_RSS_IPV6_HASH_EN |
8130 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8131 RX_MODE_RSS_IPV4_HASH_EN |
8132 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8133
1da177e4
LT		 8134 tw32_f(MAC_RX_MODE, tp->rx_mode);
8135 udelay(10);
8136
1da177e4
LT		 8137 tw32(MAC_LED_CTRL, tp->led_ctrl);
8138
8139 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8140 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8141 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8142 udelay(10);
8143 }
8144 tw32_f(MAC_RX_MODE, tp->rx_mode);
8145 udelay(10);
8146
8147 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8149 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8150 /* Set drive transmission level to 1.2V */
8151 /* only if the signal pre-emphasis bit is not set */
8152 val = tr32(MAC_SERDES_CFG);
8153 val &= 0xfffff000;
8154 val |= 0x880;
8155 tw32(MAC_SERDES_CFG, val);
8156 }
8157 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8158 tw32(MAC_SERDES_CFG, 0x616000);
8159 }
8160
8161 /* Prevent chip from dropping frames when flow control
8162 * is enabled.
8163 */
666bc831
MC		 8164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8165 val = 1;
8166 else
8167 val = 2;
8168 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8169
8170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8171 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8172 /* Use hardware link auto-negotiation */
8173 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8174 }
8175
d4d2c558
MC		 8176 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8177 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8178 u32 tmp;
8179
8180 tmp = tr32(SERDES_RX_CTRL);
8181 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8182 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8183 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8184 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8185 }
8186
dd477003
MC		 8187 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8188 if (tp->link_config.phy_is_low_power) {
8189 tp->link_config.phy_is_low_power = 0;
8190 tp->link_config.speed = tp->link_config.orig_speed;
8191 tp->link_config.duplex = tp->link_config.orig_duplex;
8192 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8193 }
1da177e4 8194
dd477003
MC		 8195 err = tg3_setup_phy(tp, 0);
8196 if (err)
8197 return err;
1da177e4 8198
dd477003 8199 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8200 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8201 u32 tmp;
8202
8203 /* Clear CRC stats. */
8204 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8205 tg3_writephy(tp, MII_TG3_TEST1,
8206 tmp | MII_TG3_TEST1_CRC_EN);
8207 tg3_readphy(tp, 0x14, &tmp);
8208 }
1da177e4
LT		 8209 }
8210 }
8211
8212 __tg3_set_rx_mode(tp->dev);
8213
8214 /* Initialize receive rules. */
8215 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8216 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8217 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8218 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8219
4cf78e4f 8220 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8221 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8222 limit = 8;
8223 else
8224 limit = 16;
8225 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8226 limit -= 4;
8227 switch (limit) {
8228 case 16:
8229 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8230 case 15:
8231 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8232 case 14:
8233 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8234 case 13:
8235 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8236 case 12:
8237 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8238 case 11:
8239 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8240 case 10:
8241 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8242 case 9:
8243 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8244 case 8:
8245 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8246 case 7:
8247 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8248 case 6:
8249 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8250 case 5:
8251 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8252 case 4:
8253 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8254 case 3:
8255 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8256 case 2:
8257 case 1:
8258
8259 default:
8260 break;
855e1111 8261 }
1da177e4 8262
9ce768ea
MC		 8263 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8264 /* Write our heartbeat update interval to APE. */
8265 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8266 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8267
1da177e4
LT		 8268 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8269
1da177e4
LT		 8270 return 0;
8271}
8272
8273/* Called at device open time to get the chip ready for
8274 * packet processing. Invoked with tp->lock held.
8275 */
8e7a22e3 8276static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8277{
1da177e4
LT		 8278 tg3_switch_clocks(tp);
8279
8280 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8281
2f751b67 8282 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8283}
8284
8285#define TG3_STAT_ADD32(PSTAT, REG) \
8286do { u32 __val = tr32(REG); \
8287 (PSTAT)->low += __val; \
8288 if ((PSTAT)->low < __val) \
8289 (PSTAT)->high += 1; \
8290} while (0)
8291
8292static void tg3_periodic_fetch_stats(struct tg3 *tp)
8293{
8294 struct tg3_hw_stats *sp = tp->hw_stats;
8295
8296 if (!netif_carrier_ok(tp->dev))
8297 return;
8298
8299 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8300 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8301 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8302 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8303 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8304 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8305 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8306 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8307 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8308 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8309 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8310 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8311 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8312
8313 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8314 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8315 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8316 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8317 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8318 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8319 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8320 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8321 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8322 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8323 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8324 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8325 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8326 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8327
8328 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8329 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8330 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8331}
8332
8333static void tg3_timer(unsigned long __opaque)
8334{
8335 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8336
f475f163
MC		 8337 if (tp->irq_sync)
8338 goto restart_timer;
8339
f47c11ee 8340 spin_lock(&tp->lock);
1da177e4 8341
fac9b83e
DM		 8342 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8343 /* All of this garbage is because when using non-tagged
8344 * IRQ status the mailbox/status_block protocol the chip
8345 * uses with the cpu is race prone.
8346 */
898a56f8 8347 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8348 tw32(GRC_LOCAL_CTRL,
8349 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8350 } else {
8351 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8352 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8353 }
1da177e4 8354
fac9b83e
DM		 8355 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8356 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8357 spin_unlock(&tp->lock);
fac9b83e
DM		 8358 schedule_work(&tp->reset_task);
8359 return;
8360 }
1da177e4
LT		 8361 }
8362
1da177e4
LT		 8363 /* This part only runs once per second. */
8364 if (!--tp->timer_counter) {
fac9b83e
DM		 8365 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8366 tg3_periodic_fetch_stats(tp);
8367
1da177e4
LT		 8368 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8369 u32 mac_stat;
8370 int phy_event;
8371
8372 mac_stat = tr32(MAC_STATUS);
8373
8374 phy_event = 0;
8375 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8376 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8377 phy_event = 1;
8378 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8379 phy_event = 1;
8380
8381 if (phy_event)
8382 tg3_setup_phy(tp, 0);
8383 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8384 u32 mac_stat = tr32(MAC_STATUS);
8385 int need_setup = 0;
8386
8387 if (netif_carrier_ok(tp->dev) &&
8388 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8389 need_setup = 1;
8390 }
8391 if (! netif_carrier_ok(tp->dev) &&
8392 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8393 MAC_STATUS_SIGNAL_DET))) {
8394 need_setup = 1;
8395 }
8396 if (need_setup) {
3d3ebe74
MC		 8397 if (!tp->serdes_counter) {
8398 tw32_f(MAC_MODE,
8399 (tp->mac_mode &
8400 ~MAC_MODE_PORT_MODE_MASK));
8401 udelay(40);
8402 tw32_f(MAC_MODE, tp->mac_mode);
8403 udelay(40);
8404 }
1da177e4
LT		 8405 tg3_setup_phy(tp, 0);
8406 }
747e8f8b
MC		 8407 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8408 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8409
8410 tp->timer_counter = tp->timer_multiplier;
8411 }
8412
130b8e4d
MC		 8413 /* Heartbeat is only sent once every 2 seconds.
8414 *
8415 * The heartbeat is to tell the ASF firmware that the host
8416 * driver is still alive. In the event that the OS crashes,
8417 * ASF needs to reset the hardware to free up the FIFO space
8418 * that may be filled with rx packets destined for the host.
8419 * If the FIFO is full, ASF will no longer function properly.
8420 *
8421 * Unintended resets have been reported on real time kernels
8422 * where the timer doesn't run on time. Netpoll will also have
8423 * same problem.
8424 *
8425 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8426 * to check the ring condition when the heartbeat is expiring
8427 * before doing the reset. This will prevent most unintended
8428 * resets.
8429 */
1da177e4 8430 if (!--tp->asf_counter) {
bc7959b2
MC		 8431 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8432 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8433 tg3_wait_for_event_ack(tp);
8434
bbadf503 8435 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8436 FWCMD_NICDRV_ALIVE3);
bbadf503 8437 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8438 /* 5 seconds timeout */
bbadf503 8439 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8440
8441 tg3_generate_fw_event(tp);
1da177e4
LT		 8442 }
8443 tp->asf_counter = tp->asf_multiplier;
8444 }
8445
f47c11ee 8446 spin_unlock(&tp->lock);
1da177e4 8447
f475f163 8448restart_timer:
1da177e4
LT		 8449 tp->timer.expires = jiffies + tp->timer_offset;
8450 add_timer(&tp->timer);
8451}
8452
4f125f42 8453static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8454{
7d12e780 8455 irq_handler_t fn;
fcfa0a32 8456 unsigned long flags;
4f125f42
MC		 8457 char *name;
8458 struct tg3_napi *tnapi = &tp->napi[irq_num];
8459
8460 if (tp->irq_cnt == 1)
8461 name = tp->dev->name;
8462 else {
8463 name = &tnapi->irq_lbl[0];
8464 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8465 name[IFNAMSIZ-1] = 0;
8466 }
fcfa0a32 8467
679563f4 8468 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8469 fn = tg3_msi;
8470 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8471 fn = tg3_msi_1shot;
1fb9df5d 8472 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8473 } else {
8474 fn = tg3_interrupt;
8475 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8476 fn = tg3_interrupt_tagged;
1fb9df5d 8477 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8478 }
4f125f42
MC		 8479
8480 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8481}
8482
7938109f
MC		 8483static int tg3_test_interrupt(struct tg3 *tp)
8484{
09943a18 8485 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8486 struct net_device *dev = tp->dev;
b16250e3 8487 int err, i, intr_ok = 0;
f6eb9b1f 8488 u32 val;
7938109f 8489
d4bc3927
MC		 8490 if (!netif_running(dev))
8491 return -ENODEV;
8492
7938109f
MC		 8493 tg3_disable_ints(tp);
8494
4f125f42 8495 free_irq(tnapi->irq_vec, tnapi);
7938109f 8496
f6eb9b1f
MC		 8497 /*
8498 * Turn off MSI one shot mode. Otherwise this test has no
8499 * observable way to know whether the interrupt was delivered.
8500 */
b703df6f
MC		 8501 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8502 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8503 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8504 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8505 tw32(MSGINT_MODE, val);
8506 }
8507
4f125f42 8508 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8509 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8510 if (err)
8511 return err;
8512
898a56f8 8513 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8514 tg3_enable_ints(tp);
8515
8516 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8517 tnapi->coal_now);
7938109f
MC		 8518
8519 for (i = 0; i < 5; i++) {
b16250e3
MC		 8520 u32 int_mbox, misc_host_ctrl;
8521
898a56f8 8522 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8523 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8524
8525 if ((int_mbox != 0) ||
8526 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8527 intr_ok = 1;
7938109f 8528 break;
b16250e3
MC		 8529 }
8530
7938109f
MC		 8531 msleep(10);
8532 }
8533
8534 tg3_disable_ints(tp);
8535
4f125f42 8536 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8537
4f125f42 8538 err = tg3_request_irq(tp, 0);
7938109f
MC		 8539
8540 if (err)
8541 return err;
8542
f6eb9b1f
MC		 8543 if (intr_ok) {
8544 /* Reenable MSI one shot mode. */
b703df6f
MC		 8545 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8547 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8548 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8549 tw32(MSGINT_MODE, val);
8550 }
7938109f 8551 return 0;
f6eb9b1f 8552 }
7938109f
MC		 8553
8554 return -EIO;
8555}
8556
8557/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8558 * successfully restored
8559 */
8560static int tg3_test_msi(struct tg3 *tp)
8561{
7938109f
MC		 8562 int err;
8563 u16 pci_cmd;
8564
8565 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8566 return 0;
8567
8568 /* Turn off SERR reporting in case MSI terminates with Master
8569 * Abort.
8570 */
8571 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8572 pci_write_config_word(tp->pdev, PCI_COMMAND,
8573 pci_cmd & ~PCI_COMMAND_SERR);
8574
8575 err = tg3_test_interrupt(tp);
8576
8577 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8578
8579 if (!err)
8580 return 0;
8581
8582 /* other failures */
8583 if (err != -EIO)
8584 return err;
8585
8586 /* MSI test failed, go back to INTx mode */
8587 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8588 "switching to INTx mode. Please report this failure to "
8589 "the PCI maintainer and include system chipset information.\n",
8590 tp->dev->name);
8591
4f125f42 8592 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8593
7938109f
MC		 8594 pci_disable_msi(tp->pdev);
8595
8596 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8597
4f125f42 8598 err = tg3_request_irq(tp, 0);
7938109f
MC		 8599 if (err)
8600 return err;
8601
8602 /* Need to reset the chip because the MSI cycle may have terminated
8603 * with Master Abort.
8604 */
f47c11ee 8605 tg3_full_lock(tp, 1);
7938109f 8606
944d980e 8607 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8608 err = tg3_init_hw(tp, 1);
7938109f 8609
f47c11ee 8610 tg3_full_unlock(tp);
7938109f
MC		 8611
8612 if (err)
4f125f42 8613 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8614
8615 return err;
8616}
8617
9e9fd12d
MC		 8618static int tg3_request_firmware(struct tg3 *tp)
8619{
8620 const __be32 *fw_data;
8621
8622 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8623 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8624 tp->dev->name, tp->fw_needed);
8625 return -ENOENT;
8626 }
8627
8628 fw_data = (void *)tp->fw->data;
8629
8630 /* Firmware blob starts with version numbers, followed by
8631 * start address and _full_ length including BSS sections
8632 * (which must be longer than the actual data, of course
8633 */
8634
8635 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8636 if (tp->fw_len < (tp->fw->size - 12)) {
8637 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8638 tp->dev->name, tp->fw_len, tp->fw_needed);
8639 release_firmware(tp->fw);
8640 tp->fw = NULL;
8641 return -EINVAL;
8642 }
8643
8644 /* We no longer need firmware; we have it. */
8645 tp->fw_needed = NULL;
8646 return 0;
8647}
8648
679563f4
MC		 8649static bool tg3_enable_msix(struct tg3 *tp)
8650{
8651 int i, rc, cpus = num_online_cpus();
8652 struct msix_entry msix_ent[tp->irq_max];
8653
8654 if (cpus == 1)
8655 /* Just fallback to the simpler MSI mode. */
8656 return false;
8657
8658 /*
8659 * We want as many rx rings enabled as there are cpus.
8660 * The first MSIX vector only deals with link interrupts, etc,
8661 * so we add one to the number of vectors we are requesting.
8662 */
8663 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8664
8665 for (i = 0; i < tp->irq_max; i++) {
8666 msix_ent[i].entry = i;
8667 msix_ent[i].vector = 0;
8668 }
8669
8670 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8671 if (rc != 0) {
8672 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8673 return false;
8674 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8675 return false;
8676 printk(KERN_NOTICE
8677 "%s: Requested %d MSI-X vectors, received %d\n",
8678 tp->dev->name, tp->irq_cnt, rc);
8679 tp->irq_cnt = rc;
8680 }
8681
baf8a94a
MC		 8682 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8683
679563f4
MC		 8684 for (i = 0; i < tp->irq_max; i++)
8685 tp->napi[i].irq_vec = msix_ent[i].vector;
8686
19cfaecc
MC		 8687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8688 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8689 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8690 } else
8691 tp->dev->real_num_tx_queues = 1;
fe5f5787 8692
679563f4
MC		 8693 return true;
8694}
8695
07b0173c
MC		 8696static void tg3_ints_init(struct tg3 *tp)
8697{
679563f4
MC		 8698 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8699 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8700 /* All MSI supporting chips should support tagged
8701 * status. Assert that this is the case.
8702 */
679563f4
MC		 8703 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8704 "Not using MSI.\n", tp->dev->name);
8705 goto defcfg;
07b0173c 8706 }
4f125f42 8707
679563f4
MC		 8708 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8709 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8710 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8711 pci_enable_msi(tp->pdev) == 0)
8712 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8713
8714 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8715 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8716 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8717 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8718 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8719 }
8720defcfg:
8721 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8722 tp->irq_cnt = 1;
8723 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8724 tp->dev->real_num_tx_queues = 1;
679563f4 8725 }
07b0173c
MC		 8726}
8727
8728static void tg3_ints_fini(struct tg3 *tp)
8729{
679563f4
MC		 8730 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8731 pci_disable_msix(tp->pdev);
8732 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8733 pci_disable_msi(tp->pdev);
8734 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8735 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8736}
8737
1da177e4
LT		 8738static int tg3_open(struct net_device *dev)
8739{
8740 struct tg3 *tp = netdev_priv(dev);
4f125f42 8741 int i, err;
1da177e4 8742
9e9fd12d
MC		 8743 if (tp->fw_needed) {
8744 err = tg3_request_firmware(tp);
8745 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8746 if (err)
8747 return err;
8748 } else if (err) {
8749 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8750 tp->dev->name);
8751 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8752 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8753 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8754 tp->dev->name);
8755 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8756 }
8757 }
8758
c49a1561
MC		 8759 netif_carrier_off(tp->dev);
8760
bc1c7567 8761 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8762 if (err)
bc1c7567 8763 return err;
2f751b67
MC		 8764
8765 tg3_full_lock(tp, 0);
bc1c7567 8766
1da177e4
LT		 8767 tg3_disable_ints(tp);
8768 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8769
f47c11ee 8770 tg3_full_unlock(tp);
1da177e4 8771
679563f4
MC		 8772 /*
8773 * Setup interrupts first so we know how
8774 * many NAPI resources to allocate
8775 */
8776 tg3_ints_init(tp);
8777
1da177e4
LT		 8778 /* The placement of this call is tied
8779 * to the setup and use of Host TX descriptors.
8780 */
8781 err = tg3_alloc_consistent(tp);
8782 if (err)
679563f4 8783 goto err_out1;
88b06bc2 8784
fed97810 8785 tg3_napi_enable(tp);
1da177e4 8786
4f125f42
MC		 8787 for (i = 0; i < tp->irq_cnt; i++) {
8788 struct tg3_napi *tnapi = &tp->napi[i];
8789 err = tg3_request_irq(tp, i);
8790 if (err) {
8791 for (i--; i >= 0; i--)
8792 free_irq(tnapi->irq_vec, tnapi);
8793 break;
8794 }
8795 }
1da177e4 8796
07b0173c 8797 if (err)
679563f4 8798 goto err_out2;
bea3348e 8799
f47c11ee 8800 tg3_full_lock(tp, 0);
1da177e4 8801
8e7a22e3 8802 err = tg3_init_hw(tp, 1);
1da177e4 8803 if (err) {
944d980e 8804 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8805 tg3_free_rings(tp);
8806 } else {
fac9b83e
DM		 8807 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8808 tp->timer_offset = HZ;
8809 else
8810 tp->timer_offset = HZ / 10;
8811
8812 BUG_ON(tp->timer_offset > HZ);
8813 tp->timer_counter = tp->timer_multiplier =
8814 (HZ / tp->timer_offset);
8815 tp->asf_counter = tp->asf_multiplier =
28fbef78 8816 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8817
8818 init_timer(&tp->timer);
8819 tp->timer.expires = jiffies + tp->timer_offset;
8820 tp->timer.data = (unsigned long) tp;
8821 tp->timer.function = tg3_timer;
1da177e4
LT		 8822 }
8823
f47c11ee 8824 tg3_full_unlock(tp);
1da177e4 8825
07b0173c 8826 if (err)
679563f4 8827 goto err_out3;
1da177e4 8828
7938109f
MC		 8829 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8830 err = tg3_test_msi(tp);
fac9b83e 8831
7938109f 8832 if (err) {
f47c11ee 8833 tg3_full_lock(tp, 0);
944d980e 8834 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8835 tg3_free_rings(tp);
f47c11ee 8836 tg3_full_unlock(tp);
7938109f 8837
679563f4 8838 goto err_out2;
7938109f 8839 }
fcfa0a32 8840
f6eb9b1f 8841 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8842 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8843 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8844 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8845 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8846
f6eb9b1f
MC		 8847 tw32(PCIE_TRANSACTION_CFG,
8848 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8849 }
7938109f
MC		 8850 }
8851
b02fd9e3
MC		 8852 tg3_phy_start(tp);
8853
f47c11ee 8854 tg3_full_lock(tp, 0);
1da177e4 8855
7938109f
MC		 8856 add_timer(&tp->timer);
8857 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8858 tg3_enable_ints(tp);
8859
f47c11ee 8860 tg3_full_unlock(tp);
1da177e4 8861
fe5f5787 8862 netif_tx_start_all_queues(dev);
1da177e4
LT		 8863
8864 return 0;
07b0173c 8865
679563f4 8866err_out3:
4f125f42
MC		 8867 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8868 struct tg3_napi *tnapi = &tp->napi[i];
8869 free_irq(tnapi->irq_vec, tnapi);
8870 }
07b0173c 8871
679563f4 8872err_out2:
fed97810 8873 tg3_napi_disable(tp);
07b0173c 8874 tg3_free_consistent(tp);
679563f4
MC		 8875
8876err_out1:
8877 tg3_ints_fini(tp);
07b0173c 8878 return err;
1da177e4
LT		 8879}
8880
8881#if 0
8882/*static*/ void tg3_dump_state(struct tg3 *tp)
8883{
8884 u32 val32, val32_2, val32_3, val32_4, val32_5;
8885 u16 val16;
8886 int i;
898a56f8 8887 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8888
8889 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8890 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8891 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8892 val16, val32);
8893
8894 /* MAC block */
8895 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8896 tr32(MAC_MODE), tr32(MAC_STATUS));
8897 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8898 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8899 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8900 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8901 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8902 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8903
8904 /* Send data initiator control block */
8905 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8906 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8907 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8908 tr32(SNDDATAI_STATSCTRL));
8909
8910 /* Send data completion control block */
8911 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8912
8913 /* Send BD ring selector block */
8914 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8915 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8916
8917 /* Send BD initiator control block */
8918 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8919 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8920
8921 /* Send BD completion control block */
8922 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8923
8924 /* Receive list placement control block */
8925 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8926 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8927 printk(" RCVLPC_STATSCTRL[%08x]\n",
8928 tr32(RCVLPC_STATSCTRL));
8929
8930 /* Receive data and receive BD initiator control block */
8931 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8932 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8933
8934 /* Receive data completion control block */
8935 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8936 tr32(RCVDCC_MODE));
8937
8938 /* Receive BD initiator control block */
8939 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8940 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8941
8942 /* Receive BD completion control block */
8943 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8944 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8945
8946 /* Receive list selector control block */
8947 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8948 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8949
8950 /* Mbuf cluster free block */
8951 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8952 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8953
8954 /* Host coalescing control block */
8955 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8956 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8957 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8958 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8959 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8960 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8961 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8962 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8963 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8964 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8965 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8966 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8967
8968 /* Memory arbiter control block */
8969 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8970 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8971
8972 /* Buffer manager control block */
8973 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8974 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8975 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8976 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8977 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8978 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8979 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8980 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8981
8982 /* Read DMA control block */
8983 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8984 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8985
8986 /* Write DMA control block */
8987 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8988 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8989
8990 /* DMA completion block */
8991 printk("DEBUG: DMAC_MODE[%08x]\n",
8992 tr32(DMAC_MODE));
8993
8994 /* GRC block */
8995 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8996 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8997 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8998 tr32(GRC_LOCAL_CTRL));
8999
9000 /* TG3_BDINFOs */
9001 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9002 tr32(RCVDBDI_JUMBO_BD + 0x0),
9003 tr32(RCVDBDI_JUMBO_BD + 0x4),
9004 tr32(RCVDBDI_JUMBO_BD + 0x8),
9005 tr32(RCVDBDI_JUMBO_BD + 0xc));
9006 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9007 tr32(RCVDBDI_STD_BD + 0x0),
9008 tr32(RCVDBDI_STD_BD + 0x4),
9009 tr32(RCVDBDI_STD_BD + 0x8),
9010 tr32(RCVDBDI_STD_BD + 0xc));
9011 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9012 tr32(RCVDBDI_MINI_BD + 0x0),
9013 tr32(RCVDBDI_MINI_BD + 0x4),
9014 tr32(RCVDBDI_MINI_BD + 0x8),
9015 tr32(RCVDBDI_MINI_BD + 0xc));
9016
9017 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9018 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9019 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9020 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9021 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9022 val32, val32_2, val32_3, val32_4);
9023
9024 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9025 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9026 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9027 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9028 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9029 val32, val32_2, val32_3, val32_4);
9030
9031 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9032 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9033 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9034 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9035 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9036 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9037 val32, val32_2, val32_3, val32_4, val32_5);
9038
9039 /* SW status block */
898a56f8
MC		 9040 printk(KERN_DEBUG
9041 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9042 sblk->status,
9043 sblk->status_tag,
9044 sblk->rx_jumbo_consumer,
9045 sblk->rx_consumer,
9046 sblk->rx_mini_consumer,
9047 sblk->idx[0].rx_producer,
9048 sblk->idx[0].tx_consumer);
1da177e4
LT		 9049
9050 /* SW statistics block */
9051 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9052 ((u32 *)tp->hw_stats)[0],
9053 ((u32 *)tp->hw_stats)[1],
9054 ((u32 *)tp->hw_stats)[2],
9055 ((u32 *)tp->hw_stats)[3]);
9056
9057 /* Mailboxes */
9058 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9059 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9060 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9061 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9062 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9063
9064 /* NIC side send descriptors. */
9065 for (i = 0; i < 6; i++) {
9066 unsigned long txd;
9067
9068 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9069 + (i * sizeof(struct tg3_tx_buffer_desc));
9070 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9071 i,
9072 readl(txd + 0x0), readl(txd + 0x4),
9073 readl(txd + 0x8), readl(txd + 0xc));
9074 }
9075
9076 /* NIC side RX descriptors. */
9077 for (i = 0; i < 6; i++) {
9078 unsigned long rxd;
9079
9080 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9081 + (i * sizeof(struct tg3_rx_buffer_desc));
9082 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9083 i,
9084 readl(rxd + 0x0), readl(rxd + 0x4),
9085 readl(rxd + 0x8), readl(rxd + 0xc));
9086 rxd += (4 * sizeof(u32));
9087 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9088 i,
9089 readl(rxd + 0x0), readl(rxd + 0x4),
9090 readl(rxd + 0x8), readl(rxd + 0xc));
9091 }
9092
9093 for (i = 0; i < 6; i++) {
9094 unsigned long rxd;
9095
9096 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9097 + (i * sizeof(struct tg3_rx_buffer_desc));
9098 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9099 i,
9100 readl(rxd + 0x0), readl(rxd + 0x4),
9101 readl(rxd + 0x8), readl(rxd + 0xc));
9102 rxd += (4 * sizeof(u32));
9103 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9104 i,
9105 readl(rxd + 0x0), readl(rxd + 0x4),
9106 readl(rxd + 0x8), readl(rxd + 0xc));
9107 }
9108}
9109#endif
9110
9111static struct net_device_stats *tg3_get_stats(struct net_device *);
9112static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9113
9114static int tg3_close(struct net_device *dev)
9115{
4f125f42 9116 int i;
1da177e4
LT		 9117 struct tg3 *tp = netdev_priv(dev);
9118
fed97810 9119 tg3_napi_disable(tp);
28e53bdd 9120 cancel_work_sync(&tp->reset_task);
7faa006f 9121
fe5f5787 9122 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9123
9124 del_timer_sync(&tp->timer);
9125
24bb4fb6
MC		 9126 tg3_phy_stop(tp);
9127
f47c11ee 9128 tg3_full_lock(tp, 1);
1da177e4
LT		 9129#if 0
9130 tg3_dump_state(tp);
9131#endif
9132
9133 tg3_disable_ints(tp);
9134
944d980e 9135 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9136 tg3_free_rings(tp);
5cf64b8a 9137 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9138
f47c11ee 9139 tg3_full_unlock(tp);
1da177e4 9140
4f125f42
MC		 9141 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9142 struct tg3_napi *tnapi = &tp->napi[i];
9143 free_irq(tnapi->irq_vec, tnapi);
9144 }
07b0173c
MC		 9145
9146 tg3_ints_fini(tp);
1da177e4
LT		 9147
9148 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9149 sizeof(tp->net_stats_prev));
9150 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9151 sizeof(tp->estats_prev));
9152
9153 tg3_free_consistent(tp);
9154
bc1c7567
MC		 9155 tg3_set_power_state(tp, PCI_D3hot);
9156
9157 netif_carrier_off(tp->dev);
9158
1da177e4
LT		 9159 return 0;
9160}
9161
9162static inline unsigned long get_stat64(tg3_stat64_t *val)
9163{
9164 unsigned long ret;
9165
9166#if (BITS_PER_LONG == 32)
9167 ret = val->low;
9168#else
9169 ret = ((u64)val->high << 32) | ((u64)val->low);
9170#endif
9171 return ret;
9172}
9173
816f8b86
SB		 9174static inline u64 get_estat64(tg3_stat64_t *val)
9175{
9176 return ((u64)val->high << 32) | ((u64)val->low);
9177}
9178
1da177e4
LT		 9179static unsigned long calc_crc_errors(struct tg3 *tp)
9180{
9181 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9182
9183 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9184 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9186 u32 val;
9187
f47c11ee 9188 spin_lock_bh(&tp->lock);
569a5df8
MC		 9189 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9190 tg3_writephy(tp, MII_TG3_TEST1,
9191 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9192 tg3_readphy(tp, 0x14, &val);
9193 } else
9194 val = 0;
f47c11ee 9195 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9196
9197 tp->phy_crc_errors += val;
9198
9199 return tp->phy_crc_errors;
9200 }
9201
9202 return get_stat64(&hw_stats->rx_fcs_errors);
9203}
9204
9205#define ESTAT_ADD(member) \
9206 estats->member = old_estats->member + \
816f8b86 9207 get_estat64(&hw_stats->member)
1da177e4
LT		 9208
9209static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9210{
9211 struct tg3_ethtool_stats *estats = &tp->estats;
9212 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9213 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9214
9215 if (!hw_stats)
9216 return old_estats;
9217
9218 ESTAT_ADD(rx_octets);
9219 ESTAT_ADD(rx_fragments);
9220 ESTAT_ADD(rx_ucast_packets);
9221 ESTAT_ADD(rx_mcast_packets);
9222 ESTAT_ADD(rx_bcast_packets);
9223 ESTAT_ADD(rx_fcs_errors);
9224 ESTAT_ADD(rx_align_errors);
9225 ESTAT_ADD(rx_xon_pause_rcvd);
9226 ESTAT_ADD(rx_xoff_pause_rcvd);
9227 ESTAT_ADD(rx_mac_ctrl_rcvd);
9228 ESTAT_ADD(rx_xoff_entered);
9229 ESTAT_ADD(rx_frame_too_long_errors);
9230 ESTAT_ADD(rx_jabbers);
9231 ESTAT_ADD(rx_undersize_packets);
9232 ESTAT_ADD(rx_in_length_errors);
9233 ESTAT_ADD(rx_out_length_errors);
9234 ESTAT_ADD(rx_64_or_less_octet_packets);
9235 ESTAT_ADD(rx_65_to_127_octet_packets);
9236 ESTAT_ADD(rx_128_to_255_octet_packets);
9237 ESTAT_ADD(rx_256_to_511_octet_packets);
9238 ESTAT_ADD(rx_512_to_1023_octet_packets);
9239 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9240 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9241 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9242 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9243 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9244
9245 ESTAT_ADD(tx_octets);
9246 ESTAT_ADD(tx_collisions);
9247 ESTAT_ADD(tx_xon_sent);
9248 ESTAT_ADD(tx_xoff_sent);
9249 ESTAT_ADD(tx_flow_control);
9250 ESTAT_ADD(tx_mac_errors);
9251 ESTAT_ADD(tx_single_collisions);
9252 ESTAT_ADD(tx_mult_collisions);
9253 ESTAT_ADD(tx_deferred);
9254 ESTAT_ADD(tx_excessive_collisions);
9255 ESTAT_ADD(tx_late_collisions);
9256 ESTAT_ADD(tx_collide_2times);
9257 ESTAT_ADD(tx_collide_3times);
9258 ESTAT_ADD(tx_collide_4times);
9259 ESTAT_ADD(tx_collide_5times);
9260 ESTAT_ADD(tx_collide_6times);
9261 ESTAT_ADD(tx_collide_7times);
9262 ESTAT_ADD(tx_collide_8times);
9263 ESTAT_ADD(tx_collide_9times);
9264 ESTAT_ADD(tx_collide_10times);
9265 ESTAT_ADD(tx_collide_11times);
9266 ESTAT_ADD(tx_collide_12times);
9267 ESTAT_ADD(tx_collide_13times);
9268 ESTAT_ADD(tx_collide_14times);
9269 ESTAT_ADD(tx_collide_15times);
9270 ESTAT_ADD(tx_ucast_packets);
9271 ESTAT_ADD(tx_mcast_packets);
9272 ESTAT_ADD(tx_bcast_packets);
9273 ESTAT_ADD(tx_carrier_sense_errors);
9274 ESTAT_ADD(tx_discards);
9275 ESTAT_ADD(tx_errors);
9276
9277 ESTAT_ADD(dma_writeq_full);
9278 ESTAT_ADD(dma_write_prioq_full);
9279 ESTAT_ADD(rxbds_empty);
9280 ESTAT_ADD(rx_discards);
9281 ESTAT_ADD(rx_errors);
9282 ESTAT_ADD(rx_threshold_hit);
9283
9284 ESTAT_ADD(dma_readq_full);
9285 ESTAT_ADD(dma_read_prioq_full);
9286 ESTAT_ADD(tx_comp_queue_full);
9287
9288 ESTAT_ADD(ring_set_send_prod_index);
9289 ESTAT_ADD(ring_status_update);
9290 ESTAT_ADD(nic_irqs);
9291 ESTAT_ADD(nic_avoided_irqs);
9292 ESTAT_ADD(nic_tx_threshold_hit);
9293
9294 return estats;
9295}
9296
9297static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9298{
9299 struct tg3 *tp = netdev_priv(dev);
9300 struct net_device_stats *stats = &tp->net_stats;
9301 struct net_device_stats *old_stats = &tp->net_stats_prev;
9302 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9303
9304 if (!hw_stats)
9305 return old_stats;
9306
9307 stats->rx_packets = old_stats->rx_packets +
9308 get_stat64(&hw_stats->rx_ucast_packets) +
9309 get_stat64(&hw_stats->rx_mcast_packets) +
9310 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9311
1da177e4
LT		 9312 stats->tx_packets = old_stats->tx_packets +
9313 get_stat64(&hw_stats->tx_ucast_packets) +
9314 get_stat64(&hw_stats->tx_mcast_packets) +
9315 get_stat64(&hw_stats->tx_bcast_packets);
9316
9317 stats->rx_bytes = old_stats->rx_bytes +
9318 get_stat64(&hw_stats->rx_octets);
9319 stats->tx_bytes = old_stats->tx_bytes +
9320 get_stat64(&hw_stats->tx_octets);
9321
9322 stats->rx_errors = old_stats->rx_errors +
4f63b877 9323 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9324 stats->tx_errors = old_stats->tx_errors +
9325 get_stat64(&hw_stats->tx_errors) +
9326 get_stat64(&hw_stats->tx_mac_errors) +
9327 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9328 get_stat64(&hw_stats->tx_discards);
9329
9330 stats->multicast = old_stats->multicast +
9331 get_stat64(&hw_stats->rx_mcast_packets);
9332 stats->collisions = old_stats->collisions +
9333 get_stat64(&hw_stats->tx_collisions);
9334
9335 stats->rx_length_errors = old_stats->rx_length_errors +
9336 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9337 get_stat64(&hw_stats->rx_undersize_packets);
9338
9339 stats->rx_over_errors = old_stats->rx_over_errors +
9340 get_stat64(&hw_stats->rxbds_empty);
9341 stats->rx_frame_errors = old_stats->rx_frame_errors +
9342 get_stat64(&hw_stats->rx_align_errors);
9343 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9344 get_stat64(&hw_stats->tx_discards);
9345 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9346 get_stat64(&hw_stats->tx_carrier_sense_errors);
9347
9348 stats->rx_crc_errors = old_stats->rx_crc_errors +
9349 calc_crc_errors(tp);
9350
4f63b877
JL		 9351 stats->rx_missed_errors = old_stats->rx_missed_errors +
9352 get_stat64(&hw_stats->rx_discards);
9353
1da177e4
LT		 9354 return stats;
9355}
9356
9357static inline u32 calc_crc(unsigned char *buf, int len)
9358{
9359 u32 reg;
9360 u32 tmp;
9361 int j, k;
9362
9363 reg = 0xffffffff;
9364
9365 for (j = 0; j < len; j++) {
9366 reg ^= buf[j];
9367
9368 for (k = 0; k < 8; k++) {
9369 tmp = reg & 0x01;
9370
9371 reg >>= 1;
9372
9373 if (tmp) {
9374 reg ^= 0xedb88320;
9375 }
9376 }
9377 }
9378
9379 return ~reg;
9380}
9381
9382static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9383{
9384 /* accept or reject all multicast frames */
9385 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9386 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9387 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9388 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9389}
9390
9391static void __tg3_set_rx_mode(struct net_device *dev)
9392{
9393 struct tg3 *tp = netdev_priv(dev);
9394 u32 rx_mode;
9395
9396 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9397 RX_MODE_KEEP_VLAN_TAG);
9398
9399 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9400 * flag clear.
9401 */
9402#if TG3_VLAN_TAG_USED
9403 if (!tp->vlgrp &&
9404 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9405 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9406#else
9407 /* By definition, VLAN is disabled always in this
9408 * case.
9409 */
9410 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9411 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9412#endif
9413
9414 if (dev->flags & IFF_PROMISC) {
9415 /* Promiscuous mode. */
9416 rx_mode |= RX_MODE_PROMISC;
9417 } else if (dev->flags & IFF_ALLMULTI) {
9418 /* Accept all multicast. */
9419 tg3_set_multi (tp, 1);
9420 } else if (dev->mc_count < 1) {
9421 /* Reject all multicast. */
9422 tg3_set_multi (tp, 0);
9423 } else {
9424 /* Accept one or more multicast(s). */
9425 struct dev_mc_list *mclist;
9426 unsigned int i;
9427 u32 mc_filter[4] = { 0, };
9428 u32 regidx;
9429 u32 bit;
9430 u32 crc;
9431
9432 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9433 i++, mclist = mclist->next) {
9434
9435 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9436 bit = ~crc & 0x7f;
9437 regidx = (bit & 0x60) >> 5;
9438 bit &= 0x1f;
9439 mc_filter[regidx] |= (1 << bit);
9440 }
9441
9442 tw32(MAC_HASH_REG_0, mc_filter[0]);
9443 tw32(MAC_HASH_REG_1, mc_filter[1]);
9444 tw32(MAC_HASH_REG_2, mc_filter[2]);
9445 tw32(MAC_HASH_REG_3, mc_filter[3]);
9446 }
9447
9448 if (rx_mode != tp->rx_mode) {
9449 tp->rx_mode = rx_mode;
9450 tw32_f(MAC_RX_MODE, rx_mode);
9451 udelay(10);
9452 }
9453}
9454
9455static void tg3_set_rx_mode(struct net_device *dev)
9456{
9457 struct tg3 *tp = netdev_priv(dev);
9458
e75f7c90
MC		 9459 if (!netif_running(dev))
9460 return;
9461
f47c11ee 9462 tg3_full_lock(tp, 0);
1da177e4 9463 __tg3_set_rx_mode(dev);
f47c11ee 9464 tg3_full_unlock(tp);
1da177e4
LT		 9465}
9466
9467#define TG3_REGDUMP_LEN (32 * 1024)
9468
9469static int tg3_get_regs_len(struct net_device *dev)
9470{
9471 return TG3_REGDUMP_LEN;
9472}
9473
9474static void tg3_get_regs(struct net_device *dev,
9475 struct ethtool_regs *regs, void *_p)
9476{
9477 u32 *p = _p;
9478 struct tg3 *tp = netdev_priv(dev);
9479 u8 *orig_p = _p;
9480 int i;
9481
9482 regs->version = 0;
9483
9484 memset(p, 0, TG3_REGDUMP_LEN);
9485
bc1c7567
MC		 9486 if (tp->link_config.phy_is_low_power)
9487 return;
9488
f47c11ee 9489 tg3_full_lock(tp, 0);
1da177e4
LT		 9490
9491#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9492#define GET_REG32_LOOP(base,len) \
9493do { p = (u32 *)(orig_p + (base)); \
9494 for (i = 0; i < len; i += 4) \
9495 __GET_REG32((base) + i); \
9496} while (0)
9497#define GET_REG32_1(reg) \
9498do { p = (u32 *)(orig_p + (reg)); \
9499 __GET_REG32((reg)); \
9500} while (0)
9501
9502 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9503 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9504 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9505 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9506 GET_REG32_1(SNDDATAC_MODE);
9507 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9508 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9509 GET_REG32_1(SNDBDC_MODE);
9510 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9511 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9512 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9513 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9514 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9515 GET_REG32_1(RCVDCC_MODE);
9516 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9517 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9518 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9519 GET_REG32_1(MBFREE_MODE);
9520 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9521 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9522 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9523 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9524 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9525 GET_REG32_1(RX_CPU_MODE);
9526 GET_REG32_1(RX_CPU_STATE);
9527 GET_REG32_1(RX_CPU_PGMCTR);
9528 GET_REG32_1(RX_CPU_HWBKPT);
9529 GET_REG32_1(TX_CPU_MODE);
9530 GET_REG32_1(TX_CPU_STATE);
9531 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9532 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9533 GET_REG32_LOOP(FTQ_RESET, 0x120);
9534 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9535 GET_REG32_1(DMAC_MODE);
9536 GET_REG32_LOOP(GRC_MODE, 0x4c);
9537 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9538 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9539
9540#undef __GET_REG32
9541#undef GET_REG32_LOOP
9542#undef GET_REG32_1
9543
f47c11ee 9544 tg3_full_unlock(tp);
1da177e4
LT		 9545}
9546
9547static int tg3_get_eeprom_len(struct net_device *dev)
9548{
9549 struct tg3 *tp = netdev_priv(dev);
9550
9551 return tp->nvram_size;
9552}
9553
1da177e4
LT		 9554static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9555{
9556 struct tg3 *tp = netdev_priv(dev);
9557 int ret;
9558 u8 *pd;
b9fc7dc5 9559 u32 i, offset, len, b_offset, b_count;
a9dc529d 9560 __be32 val;
1da177e4 9561
df259d8c
MC		 9562 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9563 return -EINVAL;
9564
bc1c7567
MC		 9565 if (tp->link_config.phy_is_low_power)
9566 return -EAGAIN;
9567
1da177e4
LT		 9568 offset = eeprom->offset;
9569 len = eeprom->len;
9570 eeprom->len = 0;
9571
9572 eeprom->magic = TG3_EEPROM_MAGIC;
9573
9574 if (offset & 3) {
9575 /* adjustments to start on required 4 byte boundary */
9576 b_offset = offset & 3;
9577 b_count = 4 - b_offset;
9578 if (b_count > len) {
9579 /* i.e. offset=1 len=2 */
9580 b_count = len;
9581 }
a9dc529d 9582 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9583 if (ret)
9584 return ret;
1da177e4
LT		 9585 memcpy(data, ((char*)&val) + b_offset, b_count);
9586 len -= b_count;
9587 offset += b_count;
9588 eeprom->len += b_count;
9589 }
9590
9591 /* read bytes upto the last 4 byte boundary */
9592 pd = &data[eeprom->len];
9593 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9594 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9595 if (ret) {
9596 eeprom->len += i;
9597 return ret;
9598 }
1da177e4
LT		 9599 memcpy(pd + i, &val, 4);
9600 }
9601 eeprom->len += i;
9602
9603 if (len & 3) {
9604 /* read last bytes not ending on 4 byte boundary */
9605 pd = &data[eeprom->len];
9606 b_count = len & 3;
9607 b_offset = offset + len - b_count;
a9dc529d 9608 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9609 if (ret)
9610 return ret;
b9fc7dc5 9611 memcpy(pd, &val, b_count);
1da177e4
LT		 9612 eeprom->len += b_count;
9613 }
9614 return 0;
9615}
9616
6aa20a22 9617static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9618
9619static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9620{
9621 struct tg3 *tp = netdev_priv(dev);
9622 int ret;
b9fc7dc5 9623 u32 offset, len, b_offset, odd_len;
1da177e4 9624 u8 *buf;
a9dc529d 9625 __be32 start, end;
1da177e4 9626
bc1c7567
MC		 9627 if (tp->link_config.phy_is_low_power)
9628 return -EAGAIN;
9629
df259d8c
MC		 9630 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9631 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9632 return -EINVAL;
9633
9634 offset = eeprom->offset;
9635 len = eeprom->len;
9636
9637 if ((b_offset = (offset & 3))) {
9638 /* adjustments to start on required 4 byte boundary */
a9dc529d 9639 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9640 if (ret)
9641 return ret;
1da177e4
LT		 9642 len += b_offset;
9643 offset &= ~3;
1c8594b4
MC		 9644 if (len < 4)
9645 len = 4;
1da177e4
LT		 9646 }
9647
9648 odd_len = 0;
1c8594b4 9649 if (len & 3) {
1da177e4
LT		 9650 /* adjustments to end on required 4 byte boundary */
9651 odd_len = 1;
9652 len = (len + 3) & ~3;
a9dc529d 9653 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9654 if (ret)
9655 return ret;
1da177e4
LT		 9656 }
9657
9658 buf = data;
9659 if (b_offset || odd_len) {
9660 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9661 if (!buf)
1da177e4
LT		 9662 return -ENOMEM;
9663 if (b_offset)
9664 memcpy(buf, &start, 4);
9665 if (odd_len)
9666 memcpy(buf+len-4, &end, 4);
9667 memcpy(buf + b_offset, data, eeprom->len);
9668 }
9669
9670 ret = tg3_nvram_write_block(tp, offset, len, buf);
9671
9672 if (buf != data)
9673 kfree(buf);
9674
9675 return ret;
9676}
9677
9678static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9679{
b02fd9e3
MC		 9680 struct tg3 *tp = netdev_priv(dev);
9681
9682 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9683 struct phy_device *phydev;
b02fd9e3
MC		 9684 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9685 return -EAGAIN;
3f0e3ad7
MC		 9686 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9687 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9688 }
6aa20a22 9689
1da177e4
LT		 9690 cmd->supported = (SUPPORTED_Autoneg);
9691
9692 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9693 cmd->supported |= (SUPPORTED_1000baseT_Half |
9694 SUPPORTED_1000baseT_Full);
9695
ef348144 9696 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9697 cmd->supported |= (SUPPORTED_100baseT_Half |
9698 SUPPORTED_100baseT_Full |
9699 SUPPORTED_10baseT_Half |
9700 SUPPORTED_10baseT_Full |
3bebab59 9701 SUPPORTED_TP);
ef348144
KK		 9702 cmd->port = PORT_TP;
9703 } else {
1da177e4 9704 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9705 cmd->port = PORT_FIBRE;
9706 }
6aa20a22 9707
1da177e4
LT		 9708 cmd->advertising = tp->link_config.advertising;
9709 if (netif_running(dev)) {
9710 cmd->speed = tp->link_config.active_speed;
9711 cmd->duplex = tp->link_config.active_duplex;
9712 }
882e9793 9713 cmd->phy_address = tp->phy_addr;
7e5856bd 9714 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9715 cmd->autoneg = tp->link_config.autoneg;
9716 cmd->maxtxpkt = 0;
9717 cmd->maxrxpkt = 0;
9718 return 0;
9719}
6aa20a22 9720
1da177e4
LT		 9721static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9722{
9723 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9724
b02fd9e3 9725 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9726 struct phy_device *phydev;
b02fd9e3
MC		 9727 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9728 return -EAGAIN;
3f0e3ad7
MC		 9729 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9730 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9731 }
9732
7e5856bd
MC		 9733 if (cmd->autoneg != AUTONEG_ENABLE &&
9734 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9735 return -EINVAL;
7e5856bd
MC		 9736
9737 if (cmd->autoneg == AUTONEG_DISABLE &&
9738 cmd->duplex != DUPLEX_FULL &&
9739 cmd->duplex != DUPLEX_HALF)
37ff238d 9740 return -EINVAL;
1da177e4 9741
7e5856bd
MC		 9742 if (cmd->autoneg == AUTONEG_ENABLE) {
9743 u32 mask = ADVERTISED_Autoneg |
9744 ADVERTISED_Pause |
9745 ADVERTISED_Asym_Pause;
9746
9747 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9748 mask |= ADVERTISED_1000baseT_Half |
9749 ADVERTISED_1000baseT_Full;
9750
9751 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9752 mask |= ADVERTISED_100baseT_Half |
9753 ADVERTISED_100baseT_Full |
9754 ADVERTISED_10baseT_Half |
9755 ADVERTISED_10baseT_Full |
9756 ADVERTISED_TP;
9757 else
9758 mask |= ADVERTISED_FIBRE;
9759
9760 if (cmd->advertising & ~mask)
9761 return -EINVAL;
9762
9763 mask &= (ADVERTISED_1000baseT_Half |
9764 ADVERTISED_1000baseT_Full |
9765 ADVERTISED_100baseT_Half |
9766 ADVERTISED_100baseT_Full |
9767 ADVERTISED_10baseT_Half |
9768 ADVERTISED_10baseT_Full);
9769
9770 cmd->advertising &= mask;
9771 } else {
9772 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9773 if (cmd->speed != SPEED_1000)
9774 return -EINVAL;
9775
9776 if (cmd->duplex != DUPLEX_FULL)
9777 return -EINVAL;
9778 } else {
9779 if (cmd->speed != SPEED_100 &&
9780 cmd->speed != SPEED_10)
9781 return -EINVAL;
9782 }
9783 }
9784
f47c11ee 9785 tg3_full_lock(tp, 0);
1da177e4
LT		 9786
9787 tp->link_config.autoneg = cmd->autoneg;
9788 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9789 tp->link_config.advertising = (cmd->advertising |
9790 ADVERTISED_Autoneg);
1da177e4
LT		 9791 tp->link_config.speed = SPEED_INVALID;
9792 tp->link_config.duplex = DUPLEX_INVALID;
9793 } else {
9794 tp->link_config.advertising = 0;
9795 tp->link_config.speed = cmd->speed;
9796 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9797 }
6aa20a22 9798
24fcad6b
MC		 9799 tp->link_config.orig_speed = tp->link_config.speed;
9800 tp->link_config.orig_duplex = tp->link_config.duplex;
9801 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9802
1da177e4
LT		 9803 if (netif_running(dev))
9804 tg3_setup_phy(tp, 1);
9805
f47c11ee 9806 tg3_full_unlock(tp);
6aa20a22 9807
1da177e4
LT		 9808 return 0;
9809}
6aa20a22 9810
1da177e4
LT		 9811static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9812{
9813 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9814
1da177e4
LT		 9815 strcpy(info->driver, DRV_MODULE_NAME);
9816 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9817 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9818 strcpy(info->bus_info, pci_name(tp->pdev));
9819}
6aa20a22 9820
1da177e4
LT		 9821static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9822{
9823 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9824
12dac075
RW		 9825 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9826 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9827 wol->supported = WAKE_MAGIC;
9828 else
9829 wol->supported = 0;
1da177e4 9830 wol->wolopts = 0;
05ac4cb7
MC		 9831 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9832 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9833 wol->wolopts = WAKE_MAGIC;
9834 memset(&wol->sopass, 0, sizeof(wol->sopass));
9835}
6aa20a22 9836
1da177e4
LT		 9837static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9838{
9839 struct tg3 *tp = netdev_priv(dev);
12dac075 9840 struct device *dp = &tp->pdev->dev;
6aa20a22 9841
1da177e4
LT		 9842 if (wol->wolopts & ~WAKE_MAGIC)
9843 return -EINVAL;
9844 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9845 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9846 return -EINVAL;
6aa20a22 9847
f47c11ee 9848 spin_lock_bh(&tp->lock);
12dac075 9849 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9850 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9851 device_set_wakeup_enable(dp, true);
9852 } else {
1da177e4 9853 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9854 device_set_wakeup_enable(dp, false);
9855 }
f47c11ee 9856 spin_unlock_bh(&tp->lock);
6aa20a22 9857
1da177e4
LT		 9858 return 0;
9859}
6aa20a22 9860
1da177e4
LT		 9861static u32 tg3_get_msglevel(struct net_device *dev)
9862{
9863 struct tg3 *tp = netdev_priv(dev);
9864 return tp->msg_enable;
9865}
6aa20a22 9866
1da177e4
LT		 9867static void tg3_set_msglevel(struct net_device *dev, u32 value)
9868{
9869 struct tg3 *tp = netdev_priv(dev);
9870 tp->msg_enable = value;
9871}
6aa20a22 9872
1da177e4
LT		 9873static int tg3_set_tso(struct net_device *dev, u32 value)
9874{
9875 struct tg3 *tp = netdev_priv(dev);
9876
9877 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9878 if (value)
9879 return -EINVAL;
9880 return 0;
9881 }
027455ad 9882 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9883 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9884 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9885 if (value) {
b0026624 9886 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9887 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9889 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9890 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9893 dev->features |= NETIF_F_TSO_ECN;
9894 } else
9895 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9896 }
1da177e4
LT		 9897 return ethtool_op_set_tso(dev, value);
9898}
6aa20a22 9899
1da177e4
LT		 9900static int tg3_nway_reset(struct net_device *dev)
9901{
9902 struct tg3 *tp = netdev_priv(dev);
1da177e4 9903 int r;
6aa20a22 9904
1da177e4
LT		 9905 if (!netif_running(dev))
9906 return -EAGAIN;
9907
c94e3941
MC		 9908 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9909 return -EINVAL;
9910
b02fd9e3
MC		 9911 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9912 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9913 return -EAGAIN;
3f0e3ad7 9914 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9915 } else {
9916 u32 bmcr;
9917
9918 spin_lock_bh(&tp->lock);
9919 r = -EINVAL;
9920 tg3_readphy(tp, MII_BMCR, &bmcr);
9921 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9922 ((bmcr & BMCR_ANENABLE) ||
9923 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9924 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9925 BMCR_ANENABLE);
9926 r = 0;
9927 }
9928 spin_unlock_bh(&tp->lock);
1da177e4 9929 }
6aa20a22 9930
1da177e4
LT		 9931 return r;
9932}
6aa20a22 9933
1da177e4
LT		 9934static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9935{
9936 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9937
1da177e4
LT		 9938 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9939 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9940 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9941 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9942 else
9943 ering->rx_jumbo_max_pending = 0;
9944
9945 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9946
9947 ering->rx_pending = tp->rx_pending;
9948 ering->rx_mini_pending = 0;
4f81c32b
MC		 9949 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9950 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9951 else
9952 ering->rx_jumbo_pending = 0;
9953
f3f3f27e 9954 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9955}
6aa20a22 9956
1da177e4
LT		 9957static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9958{
9959 struct tg3 *tp = netdev_priv(dev);
646c9edd 9960 int i, irq_sync = 0, err = 0;
6aa20a22 9961
1da177e4
LT		 9962 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9963 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9964 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9965 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9966 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9967 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9968 return -EINVAL;
6aa20a22 9969
bbe832c0 9970 if (netif_running(dev)) {
b02fd9e3 9971 tg3_phy_stop(tp);
1da177e4 9972 tg3_netif_stop(tp);
bbe832c0
MC		 9973 irq_sync = 1;
9974 }
1da177e4 9975
bbe832c0 9976 tg3_full_lock(tp, irq_sync);
6aa20a22 9977
1da177e4
LT		 9978 tp->rx_pending = ering->rx_pending;
9979
9980 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9981 tp->rx_pending > 63)
9982 tp->rx_pending = 63;
9983 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9984
9985 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9986 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9987
9988 if (netif_running(dev)) {
944d980e 9989 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9990 err = tg3_restart_hw(tp, 1);
9991 if (!err)
9992 tg3_netif_start(tp);
1da177e4
LT		 9993 }
9994
f47c11ee 9995 tg3_full_unlock(tp);
6aa20a22 9996
b02fd9e3
MC		 9997 if (irq_sync && !err)
9998 tg3_phy_start(tp);
9999
b9ec6c1b 10000 return err;
1da177e4 10001}
6aa20a22 10002
1da177e4
LT		 10003static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10004{
10005 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10006
1da177e4 10007 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 10008
e18ce346 10009 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 10010 epause->rx_pause = 1;
10011 else
10012 epause->rx_pause = 0;
10013
e18ce346 10014 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10015 epause->tx_pause = 1;
10016 else
10017 epause->tx_pause = 0;
1da177e4 10018}
6aa20a22 10019
1da177e4
LT		 10020static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10021{
10022 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10023 int err = 0;
6aa20a22 10024
b02fd9e3
MC		 10025 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10026 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10027 return -EAGAIN;
1da177e4 10028
b02fd9e3
MC		 10029 if (epause->autoneg) {
10030 u32 newadv;
10031 struct phy_device *phydev;
f47c11ee 10032
3f0e3ad7 10033 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 10034
b02fd9e3
MC		 10035 if (epause->rx_pause) {
10036 if (epause->tx_pause)
10037 newadv = ADVERTISED_Pause;
10038 else
10039 newadv = ADVERTISED_Pause |
10040 ADVERTISED_Asym_Pause;
10041 } else if (epause->tx_pause) {
10042 newadv = ADVERTISED_Asym_Pause;
10043 } else
10044 newadv = 0;
10045
10046 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10047 u32 oldadv = phydev->advertising &
10048 (ADVERTISED_Pause |
10049 ADVERTISED_Asym_Pause);
10050 if (oldadv != newadv) {
10051 phydev->advertising &=
10052 ~(ADVERTISED_Pause |
10053 ADVERTISED_Asym_Pause);
10054 phydev->advertising |= newadv;
10055 err = phy_start_aneg(phydev);
10056 }
10057 } else {
10058 tp->link_config.advertising &=
10059 ~(ADVERTISED_Pause |
10060 ADVERTISED_Asym_Pause);
10061 tp->link_config.advertising |= newadv;
10062 }
10063 } else {
10064 if (epause->rx_pause)
e18ce346 10065 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10066 else
e18ce346 10067 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10068
b02fd9e3 10069 if (epause->tx_pause)
e18ce346 10070 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10071 else
e18ce346 10072 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10073
10074 if (netif_running(dev))
10075 tg3_setup_flow_control(tp, 0, 0);
10076 }
10077 } else {
10078 int irq_sync = 0;
10079
10080 if (netif_running(dev)) {
10081 tg3_netif_stop(tp);
10082 irq_sync = 1;
10083 }
10084
10085 tg3_full_lock(tp, irq_sync);
10086
10087 if (epause->autoneg)
10088 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10089 else
10090 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10091 if (epause->rx_pause)
e18ce346 10092 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10093 else
e18ce346 10094 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10095 if (epause->tx_pause)
e18ce346 10096 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10097 else
e18ce346 10098 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10099
10100 if (netif_running(dev)) {
10101 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10102 err = tg3_restart_hw(tp, 1);
10103 if (!err)
10104 tg3_netif_start(tp);
10105 }
10106
10107 tg3_full_unlock(tp);
10108 }
6aa20a22 10109
b9ec6c1b 10110 return err;
1da177e4 10111}
6aa20a22 10112
1da177e4
LT		 10113static u32 tg3_get_rx_csum(struct net_device *dev)
10114{
10115 struct tg3 *tp = netdev_priv(dev);
10116 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10117}
6aa20a22 10118
1da177e4
LT		 10119static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10120{
10121 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10122
1da177e4
LT		 10123 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10124 if (data != 0)
10125 return -EINVAL;
10126 return 0;
10127 }
6aa20a22 10128
f47c11ee 10129 spin_lock_bh(&tp->lock);
1da177e4
LT		 10130 if (data)
10131 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10132 else
10133 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10134 spin_unlock_bh(&tp->lock);
6aa20a22 10135
1da177e4
LT		 10136 return 0;
10137}
6aa20a22 10138
1da177e4
LT		 10139static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10140{
10141 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10142
1da177e4
LT		 10143 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10144 if (data != 0)
10145 return -EINVAL;
10146 return 0;
10147 }
6aa20a22 10148
321d32a0 10149 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10150 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10151 else
9c27dbdf 10152 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10153
10154 return 0;
10155}
10156
b9f2c044 10157static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10158{
b9f2c044
JG		 10159 switch (sset) {
10160 case ETH_SS_TEST:
10161 return TG3_NUM_TEST;
10162 case ETH_SS_STATS:
10163 return TG3_NUM_STATS;
10164 default:
10165 return -EOPNOTSUPP;
10166 }
4cafd3f5
MC		 10167}
10168
1da177e4
LT		 10169static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10170{
10171 switch (stringset) {
10172 case ETH_SS_STATS:
10173 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10174 break;
4cafd3f5
MC		 10175 case ETH_SS_TEST:
10176 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10177 break;
1da177e4
LT		 10178 default:
10179 WARN_ON(1); /* we need a WARN() */
10180 break;
10181 }
10182}
10183
4009a93d
MC		 10184static int tg3_phys_id(struct net_device *dev, u32 data)
10185{
10186 struct tg3 *tp = netdev_priv(dev);
10187 int i;
10188
10189 if (!netif_running(tp->dev))
10190 return -EAGAIN;
10191
10192 if (data == 0)
759afc31 10193 data = UINT_MAX / 2;
4009a93d
MC		 10194
10195 for (i = 0; i < (data * 2); i++) {
10196 if ((i % 2) == 0)
10197 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10198 LED_CTRL_1000MBPS_ON |
10199 LED_CTRL_100MBPS_ON |
10200 LED_CTRL_10MBPS_ON |
10201 LED_CTRL_TRAFFIC_OVERRIDE |
10202 LED_CTRL_TRAFFIC_BLINK |
10203 LED_CTRL_TRAFFIC_LED);
6aa20a22 10204
4009a93d
MC		 10205 else
10206 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10207 LED_CTRL_TRAFFIC_OVERRIDE);
10208
10209 if (msleep_interruptible(500))
10210 break;
10211 }
10212 tw32(MAC_LED_CTRL, tp->led_ctrl);
10213 return 0;
10214}
10215
1da177e4
LT		 10216static void tg3_get_ethtool_stats (struct net_device *dev,
10217 struct ethtool_stats *estats, u64 *tmp_stats)
10218{
10219 struct tg3 *tp = netdev_priv(dev);
10220 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10221}
10222
566f86ad 10223#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10224#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10225#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10226#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10227#define NVRAM_SELFBOOT_HW_SIZE 0x20
10228#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10229
10230static int tg3_test_nvram(struct tg3 *tp)
10231{
b9fc7dc5 10232 u32 csum, magic;
a9dc529d 10233 __be32 *buf;
ab0049b4 10234 int i, j, k, err = 0, size;
566f86ad 10235
df259d8c
MC		 10236 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10237 return 0;
10238
e4f34110 10239 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10240 return -EIO;
10241
1b27777a
MC		 10242 if (magic == TG3_EEPROM_MAGIC)
10243 size = NVRAM_TEST_SIZE;
b16250e3 10244 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10245 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10246 TG3_EEPROM_SB_FORMAT_1) {
10247 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10248 case TG3_EEPROM_SB_REVISION_0:
10249 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10250 break;
10251 case TG3_EEPROM_SB_REVISION_2:
10252 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10253 break;
10254 case TG3_EEPROM_SB_REVISION_3:
10255 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10256 break;
10257 default:
10258 return 0;
10259 }
10260 } else
1b27777a 10261 return 0;
b16250e3
MC		 10262 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10263 size = NVRAM_SELFBOOT_HW_SIZE;
10264 else
1b27777a
MC		 10265 return -EIO;
10266
10267 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10268 if (buf == NULL)
10269 return -ENOMEM;
10270
1b27777a
MC		 10271 err = -EIO;
10272 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10273 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10274 if (err)
566f86ad 10275 break;
566f86ad 10276 }
1b27777a 10277 if (i < size)
566f86ad
MC		 10278 goto out;
10279
1b27777a 10280 /* Selfboot format */
a9dc529d 10281 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10282 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10283 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10284 u8 *buf8 = (u8 *) buf, csum8 = 0;
10285
b9fc7dc5 10286 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10287 TG3_EEPROM_SB_REVISION_2) {
10288 /* For rev 2, the csum doesn't include the MBA. */
10289 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10290 csum8 += buf8[i];
10291 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10292 csum8 += buf8[i];
10293 } else {
10294 for (i = 0; i < size; i++)
10295 csum8 += buf8[i];
10296 }
1b27777a 10297
ad96b485
AB		 10298 if (csum8 == 0) {
10299 err = 0;
10300 goto out;
10301 }
10302
10303 err = -EIO;
10304 goto out;
1b27777a 10305 }
566f86ad 10306
b9fc7dc5 10307 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10308 TG3_EEPROM_MAGIC_HW) {
10309 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10310 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10311 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10312
10313 /* Separate the parity bits and the data bytes. */
10314 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10315 if ((i == 0) || (i == 8)) {
10316 int l;
10317 u8 msk;
10318
10319 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10320 parity[k++] = buf8[i] & msk;
10321 i++;
10322 }
10323 else if (i == 16) {
10324 int l;
10325 u8 msk;
10326
10327 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10328 parity[k++] = buf8[i] & msk;
10329 i++;
10330
10331 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10332 parity[k++] = buf8[i] & msk;
10333 i++;
10334 }
10335 data[j++] = buf8[i];
10336 }
10337
10338 err = -EIO;
10339 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10340 u8 hw8 = hweight8(data[i]);
10341
10342 if ((hw8 & 0x1) && parity[i])
10343 goto out;
10344 else if (!(hw8 & 0x1) && !parity[i])
10345 goto out;
10346 }
10347 err = 0;
10348 goto out;
10349 }
10350
566f86ad
MC		 10351 /* Bootstrap checksum at offset 0x10 */
10352 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10353 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10354 goto out;
10355
10356 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10357 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10358 if (csum != be32_to_cpu(buf[0xfc/4]))
10359 goto out;
566f86ad
MC		 10360
10361 err = 0;
10362
10363out:
10364 kfree(buf);
10365 return err;
10366}
10367
ca43007a
MC		 10368#define TG3_SERDES_TIMEOUT_SEC 2
10369#define TG3_COPPER_TIMEOUT_SEC 6
10370
10371static int tg3_test_link(struct tg3 *tp)
10372{
10373 int i, max;
10374
10375 if (!netif_running(tp->dev))
10376 return -ENODEV;
10377
4c987487 10378 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10379 max = TG3_SERDES_TIMEOUT_SEC;
10380 else
10381 max = TG3_COPPER_TIMEOUT_SEC;
10382
10383 for (i = 0; i < max; i++) {
10384 if (netif_carrier_ok(tp->dev))
10385 return 0;
10386
10387 if (msleep_interruptible(1000))
10388 break;
10389 }
10390
10391 return -EIO;
10392}
10393
a71116d1 10394/* Only test the commonly used registers */
30ca3e37 10395static int tg3_test_registers(struct tg3 *tp)
a71116d1 10396{
b16250e3 10397 int i, is_5705, is_5750;
a71116d1
MC		 10398 u32 offset, read_mask, write_mask, val, save_val, read_val;
10399 static struct {
10400 u16 offset;
10401 u16 flags;
10402#define TG3_FL_5705 0x1
10403#define TG3_FL_NOT_5705 0x2
10404#define TG3_FL_NOT_5788 0x4
b16250e3 10405#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10406 u32 read_mask;
10407 u32 write_mask;
10408 } reg_tbl[] = {
10409 /* MAC Control Registers */
10410 { MAC_MODE, TG3_FL_NOT_5705,
10411 0x00000000, 0x00ef6f8c },
10412 { MAC_MODE, TG3_FL_5705,
10413 0x00000000, 0x01ef6b8c },
10414 { MAC_STATUS, TG3_FL_NOT_5705,
10415 0x03800107, 0x00000000 },
10416 { MAC_STATUS, TG3_FL_5705,
10417 0x03800100, 0x00000000 },
10418 { MAC_ADDR_0_HIGH, 0x0000,
10419 0x00000000, 0x0000ffff },
10420 { MAC_ADDR_0_LOW, 0x0000,
10421 0x00000000, 0xffffffff },
10422 { MAC_RX_MTU_SIZE, 0x0000,
10423 0x00000000, 0x0000ffff },
10424 { MAC_TX_MODE, 0x0000,
10425 0x00000000, 0x00000070 },
10426 { MAC_TX_LENGTHS, 0x0000,
10427 0x00000000, 0x00003fff },
10428 { MAC_RX_MODE, TG3_FL_NOT_5705,
10429 0x00000000, 0x000007fc },
10430 { MAC_RX_MODE, TG3_FL_5705,
10431 0x00000000, 0x000007dc },
10432 { MAC_HASH_REG_0, 0x0000,
10433 0x00000000, 0xffffffff },
10434 { MAC_HASH_REG_1, 0x0000,
10435 0x00000000, 0xffffffff },
10436 { MAC_HASH_REG_2, 0x0000,
10437 0x00000000, 0xffffffff },
10438 { MAC_HASH_REG_3, 0x0000,
10439 0x00000000, 0xffffffff },
10440
10441 /* Receive Data and Receive BD Initiator Control Registers. */
10442 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10443 0x00000000, 0xffffffff },
10444 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10445 0x00000000, 0xffffffff },
10446 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10447 0x00000000, 0x00000003 },
10448 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10449 0x00000000, 0xffffffff },
10450 { RCVDBDI_STD_BD+0, 0x0000,
10451 0x00000000, 0xffffffff },
10452 { RCVDBDI_STD_BD+4, 0x0000,
10453 0x00000000, 0xffffffff },
10454 { RCVDBDI_STD_BD+8, 0x0000,
10455 0x00000000, 0xffff0002 },
10456 { RCVDBDI_STD_BD+0xc, 0x0000,
10457 0x00000000, 0xffffffff },
6aa20a22 10458
a71116d1
MC		 10459 /* Receive BD Initiator Control Registers. */
10460 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10461 0x00000000, 0xffffffff },
10462 { RCVBDI_STD_THRESH, TG3_FL_5705,
10463 0x00000000, 0x000003ff },
10464 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10465 0x00000000, 0xffffffff },
6aa20a22 10466
a71116d1
MC		 10467 /* Host Coalescing Control Registers. */
10468 { HOSTCC_MODE, TG3_FL_NOT_5705,
10469 0x00000000, 0x00000004 },
10470 { HOSTCC_MODE, TG3_FL_5705,
10471 0x00000000, 0x000000f6 },
10472 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10473 0x00000000, 0xffffffff },
10474 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10475 0x00000000, 0x000003ff },
10476 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10477 0x00000000, 0xffffffff },
10478 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10479 0x00000000, 0x000003ff },
10480 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10481 0x00000000, 0xffffffff },
10482 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10483 0x00000000, 0x000000ff },
10484 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10485 0x00000000, 0xffffffff },
10486 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10487 0x00000000, 0x000000ff },
10488 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10489 0x00000000, 0xffffffff },
10490 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10491 0x00000000, 0xffffffff },
10492 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10493 0x00000000, 0xffffffff },
10494 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10495 0x00000000, 0x000000ff },
10496 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10497 0x00000000, 0xffffffff },
10498 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10499 0x00000000, 0x000000ff },
10500 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10501 0x00000000, 0xffffffff },
10502 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10503 0x00000000, 0xffffffff },
10504 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10505 0x00000000, 0xffffffff },
10506 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10507 0x00000000, 0xffffffff },
10508 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10509 0x00000000, 0xffffffff },
10510 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10511 0xffffffff, 0x00000000 },
10512 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10513 0xffffffff, 0x00000000 },
10514
10515 /* Buffer Manager Control Registers. */
b16250e3 10516 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10517 0x00000000, 0x007fff80 },
b16250e3 10518 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10519 0x00000000, 0x007fffff },
10520 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10521 0x00000000, 0x0000003f },
10522 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10523 0x00000000, 0x000001ff },
10524 { BUFMGR_MB_HIGH_WATER, 0x0000,
10525 0x00000000, 0x000001ff },
10526 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10527 0xffffffff, 0x00000000 },
10528 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10529 0xffffffff, 0x00000000 },
6aa20a22 10530
a71116d1
MC		 10531 /* Mailbox Registers */
10532 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10533 0x00000000, 0x000001ff },
10534 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10535 0x00000000, 0x000001ff },
10536 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10537 0x00000000, 0x000007ff },
10538 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10539 0x00000000, 0x000001ff },
10540
10541 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10542 };
10543
b16250e3
MC		 10544 is_5705 = is_5750 = 0;
10545 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10546 is_5705 = 1;
b16250e3
MC		 10547 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10548 is_5750 = 1;
10549 }
a71116d1
MC		 10550
10551 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10552 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10553 continue;
10554
10555 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10556 continue;
10557
10558 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10559 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10560 continue;
10561
b16250e3
MC		 10562 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10563 continue;
10564
a71116d1
MC		 10565 offset = (u32) reg_tbl[i].offset;
10566 read_mask = reg_tbl[i].read_mask;
10567 write_mask = reg_tbl[i].write_mask;
10568
10569 /* Save the original register content */
10570 save_val = tr32(offset);
10571
10572 /* Determine the read-only value. */
10573 read_val = save_val & read_mask;
10574
10575 /* Write zero to the register, then make sure the read-only bits
10576 * are not changed and the read/write bits are all zeros.
10577 */
10578 tw32(offset, 0);
10579
10580 val = tr32(offset);
10581
10582 /* Test the read-only and read/write bits. */
10583 if (((val & read_mask) != read_val) || (val & write_mask))
10584 goto out;
10585
10586 /* Write ones to all the bits defined by RdMask and WrMask, then
10587 * make sure the read-only bits are not changed and the
10588 * read/write bits are all ones.
10589 */
10590 tw32(offset, read_mask | write_mask);
10591
10592 val = tr32(offset);
10593
10594 /* Test the read-only bits. */
10595 if ((val & read_mask) != read_val)
10596 goto out;
10597
10598 /* Test the read/write bits. */
10599 if ((val & write_mask) != write_mask)
10600 goto out;
10601
10602 tw32(offset, save_val);
10603 }
10604
10605 return 0;
10606
10607out:
9f88f29f
MC		 10608 if (netif_msg_hw(tp))
10609 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10610 offset);
a71116d1
MC		 10611 tw32(offset, save_val);
10612 return -EIO;
10613}
10614
7942e1db
MC		 10615static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10616{
f71e1309 10617 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10618 int i;
10619 u32 j;
10620
e9edda69 10621 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10622 for (j = 0; j < len; j += 4) {
10623 u32 val;
10624
10625 tg3_write_mem(tp, offset + j, test_pattern[i]);
10626 tg3_read_mem(tp, offset + j, &val);
10627 if (val != test_pattern[i])
10628 return -EIO;
10629 }
10630 }
10631 return 0;
10632}
10633
10634static int tg3_test_memory(struct tg3 *tp)
10635{
10636 static struct mem_entry {
10637 u32 offset;
10638 u32 len;
10639 } mem_tbl_570x[] = {
38690194 10640 { 0x00000000, 0x00b50},
7942e1db
MC		 10641 { 0x00002000, 0x1c000},
10642 { 0xffffffff, 0x00000}
10643 }, mem_tbl_5705[] = {
10644 { 0x00000100, 0x0000c},
10645 { 0x00000200, 0x00008},
7942e1db
MC		 10646 { 0x00004000, 0x00800},
10647 { 0x00006000, 0x01000},
10648 { 0x00008000, 0x02000},
10649 { 0x00010000, 0x0e000},
10650 { 0xffffffff, 0x00000}
79f4d13a
MC		 10651 }, mem_tbl_5755[] = {
10652 { 0x00000200, 0x00008},
10653 { 0x00004000, 0x00800},
10654 { 0x00006000, 0x00800},
10655 { 0x00008000, 0x02000},
10656 { 0x00010000, 0x0c000},
10657 { 0xffffffff, 0x00000}
b16250e3
MC		 10658 }, mem_tbl_5906[] = {
10659 { 0x00000200, 0x00008},
10660 { 0x00004000, 0x00400},
10661 { 0x00006000, 0x00400},
10662 { 0x00008000, 0x01000},
10663 { 0x00010000, 0x01000},
10664 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10665 }, mem_tbl_5717[] = {
10666 { 0x00000200, 0x00008},
10667 { 0x00010000, 0x0a000},
10668 { 0x00020000, 0x13c00},
10669 { 0xffffffff, 0x00000}
10670 }, mem_tbl_57765[] = {
10671 { 0x00000200, 0x00008},
10672 { 0x00004000, 0x00800},
10673 { 0x00006000, 0x09800},
10674 { 0x00010000, 0x0a000},
10675 { 0xffffffff, 0x00000}
7942e1db
MC		 10676 };
10677 struct mem_entry *mem_tbl;
10678 int err = 0;
10679 int i;
10680
8b5a6c42
MC		 10681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10682 mem_tbl = mem_tbl_5717;
10683 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10684 mem_tbl = mem_tbl_57765;
10685 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10686 mem_tbl = mem_tbl_5755;
10687 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10688 mem_tbl = mem_tbl_5906;
10689 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10690 mem_tbl = mem_tbl_5705;
10691 else
7942e1db
MC		 10692 mem_tbl = mem_tbl_570x;
10693
10694 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10695 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10696 mem_tbl[i].len)) != 0)
10697 break;
10698 }
6aa20a22 10699
7942e1db
MC		 10700 return err;
10701}
10702
9f40dead
MC		 10703#define TG3_MAC_LOOPBACK 0
10704#define TG3_PHY_LOOPBACK 1
10705
10706static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10707{
9f40dead 10708 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10709 u32 desc_idx, coal_now;
c76949a6
MC		 10710 struct sk_buff *skb, *rx_skb;
10711 u8 *tx_data;
10712 dma_addr_t map;
10713 int num_pkts, tx_len, rx_len, i, err;
10714 struct tg3_rx_buffer_desc *desc;
898a56f8 10715 struct tg3_napi *tnapi, *rnapi;
21f581a5 10716 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10717
0c1d0e2b
MC		 10718 if (tp->irq_cnt > 1) {
10719 tnapi = &tp->napi[1];
10720 rnapi = &tp->napi[1];
10721 } else {
10722 tnapi = &tp->napi[0];
10723 rnapi = &tp->napi[0];
10724 }
fd2ce37f 10725 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10726
9f40dead 10727 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10728 /* HW errata - mac loopback fails in some cases on 5780.
10729 * Normal traffic and PHY loopback are not affected by
10730 * errata.
10731 */
10732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10733 return 0;
10734
9f40dead 10735 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10736 MAC_MODE_PORT_INT_LPBACK;
10737 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10738 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10739 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10740 mac_mode |= MAC_MODE_PORT_MODE_MII;
10741 else
10742 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10743 tw32(MAC_MODE, mac_mode);
10744 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10745 u32 val;
10746
7f97a4bd
MC		 10747 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10748 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10749 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10750 } else
10751 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10752
9ef8ca99
MC		 10753 tg3_phy_toggle_automdix(tp, 0);
10754
3f7045c1 10755 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10756 udelay(40);
5d64ad34 10757
e8f3f6ca 10758 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10759 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10760 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10761 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10762 mac_mode |= MAC_MODE_PORT_MODE_MII;
10763 } else
10764 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10765
c94e3941
MC		 10766 /* reset to prevent losing 1st rx packet intermittently */
10767 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10768 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10769 udelay(10);
10770 tw32_f(MAC_RX_MODE, tp->rx_mode);
10771 }
e8f3f6ca
MC		 10772 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10773 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10774 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10775 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10776 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10777 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10778 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10779 }
9f40dead 10780 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10781 }
10782 else
10783 return -EINVAL;
c76949a6
MC		 10784
10785 err = -EIO;
10786
c76949a6 10787 tx_len = 1514;
a20e9c62 10788 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10789 if (!skb)
10790 return -ENOMEM;
10791
c76949a6
MC		 10792 tx_data = skb_put(skb, tx_len);
10793 memcpy(tx_data, tp->dev->dev_addr, 6);
10794 memset(tx_data + 6, 0x0, 8);
10795
10796 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10797
10798 for (i = 14; i < tx_len; i++)
10799 tx_data[i] = (u8) (i & 0xff);
10800
f4188d8a
AD		 10801 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10802 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10803 dev_kfree_skb(skb);
10804 return -EIO;
10805 }
c76949a6
MC		 10806
10807 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10808 rnapi->coal_now);
c76949a6
MC		 10809
10810 udelay(10);
10811
898a56f8 10812 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10813
c76949a6
MC		 10814 num_pkts = 0;
10815
f4188d8a 10816 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10817
f3f3f27e 10818 tnapi->tx_prod++;
c76949a6
MC		 10819 num_pkts++;
10820
f3f3f27e
MC		 10821 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10822 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10823
10824 udelay(10);
10825
303fc921
MC		 10826 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10827 for (i = 0; i < 35; i++) {
c76949a6 10828 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10829 coal_now);
c76949a6
MC		 10830
10831 udelay(10);
10832
898a56f8
MC		 10833 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10834 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10835 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10836 (rx_idx == (rx_start_idx + num_pkts)))
10837 break;
10838 }
10839
f4188d8a 10840 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10841 dev_kfree_skb(skb);
10842
f3f3f27e 10843 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10844 goto out;
10845
10846 if (rx_idx != rx_start_idx + num_pkts)
10847 goto out;
10848
72334482 10849 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10850 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10851 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10852 if (opaque_key != RXD_OPAQUE_RING_STD)
10853 goto out;
10854
10855 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10856 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10857 goto out;
10858
10859 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10860 if (rx_len != tx_len)
10861 goto out;
10862
21f581a5 10863 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10864
21f581a5 10865 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10866 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10867
10868 for (i = 14; i < tx_len; i++) {
10869 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10870 goto out;
10871 }
10872 err = 0;
6aa20a22 10873
c76949a6
MC		 10874 /* tg3_free_rings will unmap and free the rx_skb */
10875out:
10876 return err;
10877}
10878
9f40dead
MC		 10879#define TG3_MAC_LOOPBACK_FAILED 1
10880#define TG3_PHY_LOOPBACK_FAILED 2
10881#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10882 TG3_PHY_LOOPBACK_FAILED)
10883
10884static int tg3_test_loopback(struct tg3 *tp)
10885{
10886 int err = 0;
9936bcf6 10887 u32 cpmuctrl = 0;
9f40dead
MC		 10888
10889 if (!netif_running(tp->dev))
10890 return TG3_LOOPBACK_FAILED;
10891
b9ec6c1b
MC		 10892 err = tg3_reset_hw(tp, 1);
10893 if (err)
10894 return TG3_LOOPBACK_FAILED;
9f40dead 10895
6833c043
MC		 10896 /* Turn off gphy autopowerdown. */
10897 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10898 tg3_phy_toggle_apd(tp, false);
10899
321d32a0 10900 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10901 int i;
10902 u32 status;
10903
10904 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10905
10906 /* Wait for up to 40 microseconds to acquire lock. */
10907 for (i = 0; i < 4; i++) {
10908 status = tr32(TG3_CPMU_MUTEX_GNT);
10909 if (status == CPMU_MUTEX_GNT_DRIVER)
10910 break;
10911 udelay(10);
10912 }
10913
10914 if (status != CPMU_MUTEX_GNT_DRIVER)
10915 return TG3_LOOPBACK_FAILED;
10916
b2a5c19c 10917 /* Turn off link-based power management. */
e875093c 10918 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10919 tw32(TG3_CPMU_CTRL,
10920 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10921 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10922 }
10923
9f40dead
MC		 10924 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10925 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10926
321d32a0 10927 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10928 tw32(TG3_CPMU_CTRL, cpmuctrl);
10929
10930 /* Release the mutex */
10931 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10932 }
10933
dd477003
MC		 10934 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10935 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10936 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10937 err |= TG3_PHY_LOOPBACK_FAILED;
10938 }
10939
6833c043
MC		 10940 /* Re-enable gphy autopowerdown. */
10941 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10942 tg3_phy_toggle_apd(tp, true);
10943
9f40dead
MC		 10944 return err;
10945}
10946
4cafd3f5
MC		 10947static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10948 u64 *data)
10949{
566f86ad
MC		 10950 struct tg3 *tp = netdev_priv(dev);
10951
bc1c7567
MC		 10952 if (tp->link_config.phy_is_low_power)
10953 tg3_set_power_state(tp, PCI_D0);
10954
566f86ad
MC		 10955 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10956
10957 if (tg3_test_nvram(tp) != 0) {
10958 etest->flags |= ETH_TEST_FL_FAILED;
10959 data[0] = 1;
10960 }
ca43007a
MC		 10961 if (tg3_test_link(tp) != 0) {
10962 etest->flags |= ETH_TEST_FL_FAILED;
10963 data[1] = 1;
10964 }
a71116d1 10965 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10966 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10967
10968 if (netif_running(dev)) {
b02fd9e3 10969 tg3_phy_stop(tp);
a71116d1 10970 tg3_netif_stop(tp);
bbe832c0
MC		 10971 irq_sync = 1;
10972 }
a71116d1 10973
bbe832c0 10974 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10975
10976 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10977 err = tg3_nvram_lock(tp);
a71116d1
MC		 10978 tg3_halt_cpu(tp, RX_CPU_BASE);
10979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10980 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10981 if (!err)
10982 tg3_nvram_unlock(tp);
a71116d1 10983
d9ab5ad1
MC		 10984 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10985 tg3_phy_reset(tp);
10986
a71116d1
MC		 10987 if (tg3_test_registers(tp) != 0) {
10988 etest->flags |= ETH_TEST_FL_FAILED;
10989 data[2] = 1;
10990 }
7942e1db
MC		 10991 if (tg3_test_memory(tp) != 0) {
10992 etest->flags |= ETH_TEST_FL_FAILED;
10993 data[3] = 1;
10994 }
9f40dead 10995 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10996 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10997
f47c11ee
DM		 10998 tg3_full_unlock(tp);
10999
d4bc3927
MC		 11000 if (tg3_test_interrupt(tp) != 0) {
11001 etest->flags |= ETH_TEST_FL_FAILED;
11002 data[5] = 1;
11003 }
f47c11ee
DM		 11004
11005 tg3_full_lock(tp, 0);
d4bc3927 11006
a71116d1
MC		 11007 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11008 if (netif_running(dev)) {
11009 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 11010 err2 = tg3_restart_hw(tp, 1);
11011 if (!err2)
b9ec6c1b 11012 tg3_netif_start(tp);
a71116d1 11013 }
f47c11ee
DM		 11014
11015 tg3_full_unlock(tp);
b02fd9e3
MC		 11016
11017 if (irq_sync && !err2)
11018 tg3_phy_start(tp);
a71116d1 11019 }
bc1c7567
MC		 11020 if (tp->link_config.phy_is_low_power)
11021 tg3_set_power_state(tp, PCI_D3hot);
11022
4cafd3f5
MC		 11023}
11024
1da177e4
LT		 11025static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11026{
11027 struct mii_ioctl_data *data = if_mii(ifr);
11028 struct tg3 *tp = netdev_priv(dev);
11029 int err;
11030
b02fd9e3 11031 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11032 struct phy_device *phydev;
b02fd9e3
MC		 11033 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11034 return -EAGAIN;
3f0e3ad7
MC		 11035 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11036 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11037 }
11038
1da177e4
LT		 11039 switch(cmd) {
11040 case SIOCGMIIPHY:
882e9793 11041 data->phy_id = tp->phy_addr;
1da177e4
LT		 11042
11043 /* fallthru */
11044 case SIOCGMIIREG: {
11045 u32 mii_regval;
11046
11047 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11048 break; /* We have no PHY */
11049
bc1c7567
MC		 11050 if (tp->link_config.phy_is_low_power)
11051 return -EAGAIN;
11052
f47c11ee 11053 spin_lock_bh(&tp->lock);
1da177e4 11054 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11055 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11056
11057 data->val_out = mii_regval;
11058
11059 return err;
11060 }
11061
11062 case SIOCSMIIREG:
11063 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11064 break; /* We have no PHY */
11065
bc1c7567
MC		 11066 if (tp->link_config.phy_is_low_power)
11067 return -EAGAIN;
11068
f47c11ee 11069 spin_lock_bh(&tp->lock);
1da177e4 11070 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11071 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11072
11073 return err;
11074
11075 default:
11076 /* do nothing */
11077 break;
11078 }
11079 return -EOPNOTSUPP;
11080}
11081
11082#if TG3_VLAN_TAG_USED
11083static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11084{
11085 struct tg3 *tp = netdev_priv(dev);
11086
844b3eed
MC		 11087 if (!netif_running(dev)) {
11088 tp->vlgrp = grp;
11089 return;
11090 }
11091
11092 tg3_netif_stop(tp);
29315e87 11093
f47c11ee 11094 tg3_full_lock(tp, 0);
1da177e4
LT		 11095
11096 tp->vlgrp = grp;
11097
11098 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11099 __tg3_set_rx_mode(dev);
11100
844b3eed 11101 tg3_netif_start(tp);
46966545
MC		 11102
11103 tg3_full_unlock(tp);
1da177e4 11104}
1da177e4
LT		 11105#endif
11106
15f9850d
DM		 11107static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11108{
11109 struct tg3 *tp = netdev_priv(dev);
11110
11111 memcpy(ec, &tp->coal, sizeof(*ec));
11112 return 0;
11113}
11114
d244c892
MC		 11115static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11116{
11117 struct tg3 *tp = netdev_priv(dev);
11118 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11119 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11120
11121 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11122 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11123 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11124 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11125 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11126 }
11127
11128 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11129 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11130 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11131 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11132 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11133 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11134 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11135 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11136 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11137 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11138 return -EINVAL;
11139
11140 /* No rx interrupts will be generated if both are zero */
11141 if ((ec->rx_coalesce_usecs == 0) &&
11142 (ec->rx_max_coalesced_frames == 0))
11143 return -EINVAL;
11144
11145 /* No tx interrupts will be generated if both are zero */
11146 if ((ec->tx_coalesce_usecs == 0) &&
11147 (ec->tx_max_coalesced_frames == 0))
11148 return -EINVAL;
11149
11150 /* Only copy relevant parameters, ignore all others. */
11151 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11152 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11153 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11154 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11155 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11156 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11157 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11158 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11159 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11160
11161 if (netif_running(dev)) {
11162 tg3_full_lock(tp, 0);
11163 __tg3_set_coalesce(tp, &tp->coal);
11164 tg3_full_unlock(tp);
11165 }
11166 return 0;
11167}
11168
7282d491 11169static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11170 .get_settings = tg3_get_settings,
11171 .set_settings = tg3_set_settings,
11172 .get_drvinfo = tg3_get_drvinfo,
11173 .get_regs_len = tg3_get_regs_len,
11174 .get_regs = tg3_get_regs,
11175 .get_wol = tg3_get_wol,
11176 .set_wol = tg3_set_wol,
11177 .get_msglevel = tg3_get_msglevel,
11178 .set_msglevel = tg3_set_msglevel,
11179 .nway_reset = tg3_nway_reset,
11180 .get_link = ethtool_op_get_link,
11181 .get_eeprom_len = tg3_get_eeprom_len,
11182 .get_eeprom = tg3_get_eeprom,
11183 .set_eeprom = tg3_set_eeprom,
11184 .get_ringparam = tg3_get_ringparam,
11185 .set_ringparam = tg3_set_ringparam,
11186 .get_pauseparam = tg3_get_pauseparam,
11187 .set_pauseparam = tg3_set_pauseparam,
11188 .get_rx_csum = tg3_get_rx_csum,
11189 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11190 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11191 .set_sg = ethtool_op_set_sg,
1da177e4 11192 .set_tso = tg3_set_tso,
4cafd3f5 11193 .self_test = tg3_self_test,
1da177e4 11194 .get_strings = tg3_get_strings,
4009a93d 11195 .phys_id = tg3_phys_id,
1da177e4 11196 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11197 .get_coalesce = tg3_get_coalesce,
d244c892 11198 .set_coalesce = tg3_set_coalesce,
b9f2c044 11199 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11200};
11201
11202static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11203{
1b27777a 11204 u32 cursize, val, magic;
1da177e4
LT		 11205
11206 tp->nvram_size = EEPROM_CHIP_SIZE;
11207
e4f34110 11208 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11209 return;
11210
b16250e3
MC		 11211 if ((magic != TG3_EEPROM_MAGIC) &&
11212 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11213 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11214 return;
11215
11216 /*
11217 * Size the chip by reading offsets at increasing powers of two.
11218 * When we encounter our validation signature, we know the addressing
11219 * has wrapped around, and thus have our chip size.
11220 */
1b27777a 11221 cursize = 0x10;
1da177e4
LT		 11222
11223 while (cursize < tp->nvram_size) {
e4f34110 11224 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11225 return;
11226
1820180b 11227 if (val == magic)
1da177e4
LT		 11228 break;
11229
11230 cursize <<= 1;
11231 }
11232
11233 tp->nvram_size = cursize;
11234}
6aa20a22 11235
1da177e4
LT		 11236static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11237{
11238 u32 val;
11239
df259d8c
MC		 11240 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11241 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11242 return;
11243
11244 /* Selfboot format */
1820180b 11245 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11246 tg3_get_eeprom_size(tp);
11247 return;
11248 }
11249
6d348f2c 11250 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11251 if (val != 0) {
6d348f2c
MC		 11252 /* This is confusing. We want to operate on the
11253 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11254 * call will read from NVRAM and byteswap the data
11255 * according to the byteswapping settings for all
11256 * other register accesses. This ensures the data we
11257 * want will always reside in the lower 16-bits.
11258 * However, the data in NVRAM is in LE format, which
11259 * means the data from the NVRAM read will always be
11260 * opposite the endianness of the CPU. The 16-bit
11261 * byteswap then brings the data to CPU endianness.
11262 */
11263 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11264 return;
11265 }
11266 }
fd1122a2 11267 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11268}
11269
11270static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11271{
11272 u32 nvcfg1;
11273
11274 nvcfg1 = tr32(NVRAM_CFG1);
11275 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11276 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11277 } else {
1da177e4
LT		 11278 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11279 tw32(NVRAM_CFG1, nvcfg1);
11280 }
11281
4c987487 11282 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11283 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11284 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11285 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11286 tp->nvram_jedecnum = JEDEC_ATMEL;
11287 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11288 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11289 break;
11290 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11291 tp->nvram_jedecnum = JEDEC_ATMEL;
11292 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11293 break;
11294 case FLASH_VENDOR_ATMEL_EEPROM:
11295 tp->nvram_jedecnum = JEDEC_ATMEL;
11296 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11297 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11298 break;
11299 case FLASH_VENDOR_ST:
11300 tp->nvram_jedecnum = JEDEC_ST;
11301 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11302 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11303 break;
11304 case FLASH_VENDOR_SAIFUN:
11305 tp->nvram_jedecnum = JEDEC_SAIFUN;
11306 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11307 break;
11308 case FLASH_VENDOR_SST_SMALL:
11309 case FLASH_VENDOR_SST_LARGE:
11310 tp->nvram_jedecnum = JEDEC_SST;
11311 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11312 break;
1da177e4 11313 }
8590a603 11314 } else {
1da177e4
LT		 11315 tp->nvram_jedecnum = JEDEC_ATMEL;
11316 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11317 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11318 }
11319}
11320
a1b950d5
MC		 11321static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11322{
11323 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11324 case FLASH_5752PAGE_SIZE_256:
11325 tp->nvram_pagesize = 256;
11326 break;
11327 case FLASH_5752PAGE_SIZE_512:
11328 tp->nvram_pagesize = 512;
11329 break;
11330 case FLASH_5752PAGE_SIZE_1K:
11331 tp->nvram_pagesize = 1024;
11332 break;
11333 case FLASH_5752PAGE_SIZE_2K:
11334 tp->nvram_pagesize = 2048;
11335 break;
11336 case FLASH_5752PAGE_SIZE_4K:
11337 tp->nvram_pagesize = 4096;
11338 break;
11339 case FLASH_5752PAGE_SIZE_264:
11340 tp->nvram_pagesize = 264;
11341 break;
11342 case FLASH_5752PAGE_SIZE_528:
11343 tp->nvram_pagesize = 528;
11344 break;
11345 }
11346}
11347
361b4ac2
MC		 11348static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11349{
11350 u32 nvcfg1;
11351
11352 nvcfg1 = tr32(NVRAM_CFG1);
11353
e6af301b
MC		 11354 /* NVRAM protection for TPM */
11355 if (nvcfg1 & (1 << 27))
f66a29b0 11356 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11357
361b4ac2 11358 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11359 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11360 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11361 tp->nvram_jedecnum = JEDEC_ATMEL;
11362 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11363 break;
11364 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11365 tp->nvram_jedecnum = JEDEC_ATMEL;
11366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11368 break;
11369 case FLASH_5752VENDOR_ST_M45PE10:
11370 case FLASH_5752VENDOR_ST_M45PE20:
11371 case FLASH_5752VENDOR_ST_M45PE40:
11372 tp->nvram_jedecnum = JEDEC_ST;
11373 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11374 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11375 break;
361b4ac2
MC		 11376 }
11377
11378 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11379 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11380 } else {
361b4ac2
MC		 11381 /* For eeprom, set pagesize to maximum eeprom size */
11382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11383
11384 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11385 tw32(NVRAM_CFG1, nvcfg1);
11386 }
11387}
11388
d3c7b886
MC		 11389static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11390{
989a9d23 11391 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11392
11393 nvcfg1 = tr32(NVRAM_CFG1);
11394
11395 /* NVRAM protection for TPM */
989a9d23 11396 if (nvcfg1 & (1 << 27)) {
f66a29b0 11397 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11398 protect = 1;
11399 }
d3c7b886 11400
989a9d23
MC		 11401 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11402 switch (nvcfg1) {
8590a603
MC		 11403 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11404 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11405 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11406 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11407 tp->nvram_jedecnum = JEDEC_ATMEL;
11408 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11409 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11410 tp->nvram_pagesize = 264;
11411 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11412 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11413 tp->nvram_size = (protect ? 0x3e200 :
11414 TG3_NVRAM_SIZE_512KB);
11415 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11416 tp->nvram_size = (protect ? 0x1f200 :
11417 TG3_NVRAM_SIZE_256KB);
11418 else
11419 tp->nvram_size = (protect ? 0x1f200 :
11420 TG3_NVRAM_SIZE_128KB);
11421 break;
11422 case FLASH_5752VENDOR_ST_M45PE10:
11423 case FLASH_5752VENDOR_ST_M45PE20:
11424 case FLASH_5752VENDOR_ST_M45PE40:
11425 tp->nvram_jedecnum = JEDEC_ST;
11426 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11427 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11428 tp->nvram_pagesize = 256;
11429 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11430 tp->nvram_size = (protect ?
11431 TG3_NVRAM_SIZE_64KB :
11432 TG3_NVRAM_SIZE_128KB);
11433 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11434 tp->nvram_size = (protect ?
11435 TG3_NVRAM_SIZE_64KB :
11436 TG3_NVRAM_SIZE_256KB);
11437 else
11438 tp->nvram_size = (protect ?
11439 TG3_NVRAM_SIZE_128KB :
11440 TG3_NVRAM_SIZE_512KB);
11441 break;
d3c7b886
MC		 11442 }
11443}
11444
1b27777a
MC		 11445static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11446{
11447 u32 nvcfg1;
11448
11449 nvcfg1 = tr32(NVRAM_CFG1);
11450
11451 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11452 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11453 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11454 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11455 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11456 tp->nvram_jedecnum = JEDEC_ATMEL;
11457 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11458 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11459
8590a603
MC		 11460 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11461 tw32(NVRAM_CFG1, nvcfg1);
11462 break;
11463 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11464 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11465 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11466 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11467 tp->nvram_jedecnum = JEDEC_ATMEL;
11468 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11469 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11470 tp->nvram_pagesize = 264;
11471 break;
11472 case FLASH_5752VENDOR_ST_M45PE10:
11473 case FLASH_5752VENDOR_ST_M45PE20:
11474 case FLASH_5752VENDOR_ST_M45PE40:
11475 tp->nvram_jedecnum = JEDEC_ST;
11476 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11477 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11478 tp->nvram_pagesize = 256;
11479 break;
1b27777a
MC		 11480 }
11481}
11482
6b91fa02
MC		 11483static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11484{
11485 u32 nvcfg1, protect = 0;
11486
11487 nvcfg1 = tr32(NVRAM_CFG1);
11488
11489 /* NVRAM protection for TPM */
11490 if (nvcfg1 & (1 << 27)) {
f66a29b0 11491 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11492 protect = 1;
11493 }
11494
11495 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11496 switch (nvcfg1) {
8590a603
MC		 11497 case FLASH_5761VENDOR_ATMEL_ADB021D:
11498 case FLASH_5761VENDOR_ATMEL_ADB041D:
11499 case FLASH_5761VENDOR_ATMEL_ADB081D:
11500 case FLASH_5761VENDOR_ATMEL_ADB161D:
11501 case FLASH_5761VENDOR_ATMEL_MDB021D:
11502 case FLASH_5761VENDOR_ATMEL_MDB041D:
11503 case FLASH_5761VENDOR_ATMEL_MDB081D:
11504 case FLASH_5761VENDOR_ATMEL_MDB161D:
11505 tp->nvram_jedecnum = JEDEC_ATMEL;
11506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11507 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11508 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11509 tp->nvram_pagesize = 256;
11510 break;
11511 case FLASH_5761VENDOR_ST_A_M45PE20:
11512 case FLASH_5761VENDOR_ST_A_M45PE40:
11513 case FLASH_5761VENDOR_ST_A_M45PE80:
11514 case FLASH_5761VENDOR_ST_A_M45PE16:
11515 case FLASH_5761VENDOR_ST_M_M45PE20:
11516 case FLASH_5761VENDOR_ST_M_M45PE40:
11517 case FLASH_5761VENDOR_ST_M_M45PE80:
11518 case FLASH_5761VENDOR_ST_M_M45PE16:
11519 tp->nvram_jedecnum = JEDEC_ST;
11520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11522 tp->nvram_pagesize = 256;
11523 break;
6b91fa02
MC		 11524 }
11525
11526 if (protect) {
11527 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11528 } else {
11529 switch (nvcfg1) {
8590a603
MC		 11530 case FLASH_5761VENDOR_ATMEL_ADB161D:
11531 case FLASH_5761VENDOR_ATMEL_MDB161D:
11532 case FLASH_5761VENDOR_ST_A_M45PE16:
11533 case FLASH_5761VENDOR_ST_M_M45PE16:
11534 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11535 break;
11536 case FLASH_5761VENDOR_ATMEL_ADB081D:
11537 case FLASH_5761VENDOR_ATMEL_MDB081D:
11538 case FLASH_5761VENDOR_ST_A_M45PE80:
11539 case FLASH_5761VENDOR_ST_M_M45PE80:
11540 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11541 break;
11542 case FLASH_5761VENDOR_ATMEL_ADB041D:
11543 case FLASH_5761VENDOR_ATMEL_MDB041D:
11544 case FLASH_5761VENDOR_ST_A_M45PE40:
11545 case FLASH_5761VENDOR_ST_M_M45PE40:
11546 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11547 break;
11548 case FLASH_5761VENDOR_ATMEL_ADB021D:
11549 case FLASH_5761VENDOR_ATMEL_MDB021D:
11550 case FLASH_5761VENDOR_ST_A_M45PE20:
11551 case FLASH_5761VENDOR_ST_M_M45PE20:
11552 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11553 break;
6b91fa02
MC		 11554 }
11555 }
11556}
11557
b5d3772c
MC		 11558static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11559{
11560 tp->nvram_jedecnum = JEDEC_ATMEL;
11561 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11562 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11563}
11564
321d32a0
MC		 11565static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11566{
11567 u32 nvcfg1;
11568
11569 nvcfg1 = tr32(NVRAM_CFG1);
11570
11571 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11572 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11573 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11574 tp->nvram_jedecnum = JEDEC_ATMEL;
11575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11576 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11577
11578 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11579 tw32(NVRAM_CFG1, nvcfg1);
11580 return;
11581 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11582 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11583 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11584 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11585 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11586 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11587 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11588 tp->nvram_jedecnum = JEDEC_ATMEL;
11589 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11590 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11591
11592 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11593 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11594 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11595 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11596 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11597 break;
11598 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11599 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11600 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11601 break;
11602 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11603 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11604 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11605 break;
11606 }
11607 break;
11608 case FLASH_5752VENDOR_ST_M45PE10:
11609 case FLASH_5752VENDOR_ST_M45PE20:
11610 case FLASH_5752VENDOR_ST_M45PE40:
11611 tp->nvram_jedecnum = JEDEC_ST;
11612 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11613 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11614
11615 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11616 case FLASH_5752VENDOR_ST_M45PE10:
11617 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11618 break;
11619 case FLASH_5752VENDOR_ST_M45PE20:
11620 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11621 break;
11622 case FLASH_5752VENDOR_ST_M45PE40:
11623 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11624 break;
11625 }
11626 break;
11627 default:
df259d8c 11628 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11629 return;
11630 }
11631
a1b950d5
MC		 11632 tg3_nvram_get_pagesize(tp, nvcfg1);
11633 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11634 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11635}
11636
11637
11638static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11639{
11640 u32 nvcfg1;
11641
11642 nvcfg1 = tr32(NVRAM_CFG1);
11643
11644 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11645 case FLASH_5717VENDOR_ATMEL_EEPROM:
11646 case FLASH_5717VENDOR_MICRO_EEPROM:
11647 tp->nvram_jedecnum = JEDEC_ATMEL;
11648 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11649 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11650
11651 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11652 tw32(NVRAM_CFG1, nvcfg1);
11653 return;
11654 case FLASH_5717VENDOR_ATMEL_MDB011D:
11655 case FLASH_5717VENDOR_ATMEL_ADB011B:
11656 case FLASH_5717VENDOR_ATMEL_ADB011D:
11657 case FLASH_5717VENDOR_ATMEL_MDB021D:
11658 case FLASH_5717VENDOR_ATMEL_ADB021B:
11659 case FLASH_5717VENDOR_ATMEL_ADB021D:
11660 case FLASH_5717VENDOR_ATMEL_45USPT:
11661 tp->nvram_jedecnum = JEDEC_ATMEL;
11662 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11663 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11664
11665 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11666 case FLASH_5717VENDOR_ATMEL_MDB021D:
11667 case FLASH_5717VENDOR_ATMEL_ADB021B:
11668 case FLASH_5717VENDOR_ATMEL_ADB021D:
11669 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11670 break;
11671 default:
11672 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11673 break;
11674 }
321d32a0 11675 break;
a1b950d5
MC		 11676 case FLASH_5717VENDOR_ST_M_M25PE10:
11677 case FLASH_5717VENDOR_ST_A_M25PE10:
11678 case FLASH_5717VENDOR_ST_M_M45PE10:
11679 case FLASH_5717VENDOR_ST_A_M45PE10:
11680 case FLASH_5717VENDOR_ST_M_M25PE20:
11681 case FLASH_5717VENDOR_ST_A_M25PE20:
11682 case FLASH_5717VENDOR_ST_M_M45PE20:
11683 case FLASH_5717VENDOR_ST_A_M45PE20:
11684 case FLASH_5717VENDOR_ST_25USPT:
11685 case FLASH_5717VENDOR_ST_45USPT:
11686 tp->nvram_jedecnum = JEDEC_ST;
11687 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11688 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11689
11690 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11691 case FLASH_5717VENDOR_ST_M_M25PE20:
11692 case FLASH_5717VENDOR_ST_A_M25PE20:
11693 case FLASH_5717VENDOR_ST_M_M45PE20:
11694 case FLASH_5717VENDOR_ST_A_M45PE20:
11695 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11696 break;
11697 default:
11698 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11699 break;
11700 }
321d32a0 11701 break;
a1b950d5
MC		 11702 default:
11703 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11704 return;
321d32a0 11705 }
a1b950d5
MC		 11706
11707 tg3_nvram_get_pagesize(tp, nvcfg1);
11708 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11709 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11710}
11711
1da177e4
LT		 11712/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11713static void __devinit tg3_nvram_init(struct tg3 *tp)
11714{
1da177e4
LT		 11715 tw32_f(GRC_EEPROM_ADDR,
11716 (EEPROM_ADDR_FSM_RESET |
11717 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11718 EEPROM_ADDR_CLKPERD_SHIFT)));
11719
9d57f01c 11720 msleep(1);
1da177e4
LT		 11721
11722 /* Enable seeprom accesses. */
11723 tw32_f(GRC_LOCAL_CTRL,
11724 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11725 udelay(100);
11726
11727 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11728 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11729 tp->tg3_flags |= TG3_FLAG_NVRAM;
11730
ec41c7df
MC		 11731 if (tg3_nvram_lock(tp)) {
11732 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11733 "tg3_nvram_init failed.\n", tp->dev->name);
11734 return;
11735 }
e6af301b 11736 tg3_enable_nvram_access(tp);
1da177e4 11737
989a9d23
MC		 11738 tp->nvram_size = 0;
11739
361b4ac2
MC		 11740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11741 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11742 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11743 tg3_get_5755_nvram_info(tp);
d30cdd28 11744 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11746 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11747 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11748 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11749 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11750 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11751 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11752 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11753 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11754 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11755 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11756 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11757 else
11758 tg3_get_nvram_info(tp);
11759
989a9d23
MC		 11760 if (tp->nvram_size == 0)
11761 tg3_get_nvram_size(tp);
1da177e4 11762
e6af301b 11763 tg3_disable_nvram_access(tp);
381291b7 11764 tg3_nvram_unlock(tp);
1da177e4
LT		 11765
11766 } else {
11767 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11768
11769 tg3_get_eeprom_size(tp);
11770 }
11771}
11772
1da177e4
LT		 11773static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11774 u32 offset, u32 len, u8 *buf)
11775{
11776 int i, j, rc = 0;
11777 u32 val;
11778
11779 for (i = 0; i < len; i += 4) {
b9fc7dc5 11780 u32 addr;
a9dc529d 11781 __be32 data;
1da177e4
LT		 11782
11783 addr = offset + i;
11784
11785 memcpy(&data, buf + i, 4);
11786
62cedd11
MC		 11787 /*
11788 * The SEEPROM interface expects the data to always be opposite
11789 * the native endian format. We accomplish this by reversing
11790 * all the operations that would have been performed on the
11791 * data from a call to tg3_nvram_read_be32().
11792 */
11793 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11794
11795 val = tr32(GRC_EEPROM_ADDR);
11796 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11797
11798 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11799 EEPROM_ADDR_READ);
11800 tw32(GRC_EEPROM_ADDR, val |
11801 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11802 (addr & EEPROM_ADDR_ADDR_MASK) |
11803 EEPROM_ADDR_START |
11804 EEPROM_ADDR_WRITE);
6aa20a22 11805
9d57f01c 11806 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11807 val = tr32(GRC_EEPROM_ADDR);
11808
11809 if (val & EEPROM_ADDR_COMPLETE)
11810 break;
9d57f01c 11811 msleep(1);
1da177e4
LT		 11812 }
11813 if (!(val & EEPROM_ADDR_COMPLETE)) {
11814 rc = -EBUSY;
11815 break;
11816 }
11817 }
11818
11819 return rc;
11820}
11821
11822/* offset and length are dword aligned */
11823static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11824 u8 *buf)
11825{
11826 int ret = 0;
11827 u32 pagesize = tp->nvram_pagesize;
11828 u32 pagemask = pagesize - 1;
11829 u32 nvram_cmd;
11830 u8 *tmp;
11831
11832 tmp = kmalloc(pagesize, GFP_KERNEL);
11833 if (tmp == NULL)
11834 return -ENOMEM;
11835
11836 while (len) {
11837 int j;
e6af301b 11838 u32 phy_addr, page_off, size;
1da177e4
LT		 11839
11840 phy_addr = offset & ~pagemask;
6aa20a22 11841
1da177e4 11842 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11843 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11844 (__be32 *) (tmp + j));
11845 if (ret)
1da177e4
LT		 11846 break;
11847 }
11848 if (ret)
11849 break;
11850
11851 page_off = offset & pagemask;
11852 size = pagesize;
11853 if (len < size)
11854 size = len;
11855
11856 len -= size;
11857
11858 memcpy(tmp + page_off, buf, size);
11859
11860 offset = offset + (pagesize - page_off);
11861
e6af301b 11862 tg3_enable_nvram_access(tp);
1da177e4
LT		 11863
11864 /*
11865 * Before we can erase the flash page, we need
11866 * to issue a special "write enable" command.
11867 */
11868 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11869
11870 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11871 break;
11872
11873 /* Erase the target page */
11874 tw32(NVRAM_ADDR, phy_addr);
11875
11876 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11877 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11878
11879 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11880 break;
11881
11882 /* Issue another write enable to start the write. */
11883 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11884
11885 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11886 break;
11887
11888 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11889 __be32 data;
1da177e4 11890
b9fc7dc5 11891 data = *((__be32 *) (tmp + j));
a9dc529d 11892
b9fc7dc5 11893 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11894
11895 tw32(NVRAM_ADDR, phy_addr + j);
11896
11897 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11898 NVRAM_CMD_WR;
11899
11900 if (j == 0)
11901 nvram_cmd |= NVRAM_CMD_FIRST;
11902 else if (j == (pagesize - 4))
11903 nvram_cmd |= NVRAM_CMD_LAST;
11904
11905 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11906 break;
11907 }
11908 if (ret)
11909 break;
11910 }
11911
11912 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11913 tg3_nvram_exec_cmd(tp, nvram_cmd);
11914
11915 kfree(tmp);
11916
11917 return ret;
11918}
11919
11920/* offset and length are dword aligned */
11921static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11922 u8 *buf)
11923{
11924 int i, ret = 0;
11925
11926 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11927 u32 page_off, phy_addr, nvram_cmd;
11928 __be32 data;
1da177e4
LT		 11929
11930 memcpy(&data, buf + i, 4);
b9fc7dc5 11931 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11932
11933 page_off = offset % tp->nvram_pagesize;
11934
1820180b 11935 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11936
11937 tw32(NVRAM_ADDR, phy_addr);
11938
11939 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11940
11941 if ((page_off == 0) || (i == 0))
11942 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11943 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11944 nvram_cmd |= NVRAM_CMD_LAST;
11945
11946 if (i == (len - 4))
11947 nvram_cmd |= NVRAM_CMD_LAST;
11948
321d32a0
MC		 11949 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11950 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11951 (tp->nvram_jedecnum == JEDEC_ST) &&
11952 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11953
11954 if ((ret = tg3_nvram_exec_cmd(tp,
11955 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11956 NVRAM_CMD_DONE)))
11957
11958 break;
11959 }
11960 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11961 /* We always do complete word writes to eeprom. */
11962 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11963 }
11964
11965 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11966 break;
11967 }
11968 return ret;
11969}
11970
11971/* offset and length are dword aligned */
11972static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11973{
11974 int ret;
11975
1da177e4 11976 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11977 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11978 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11979 udelay(40);
11980 }
11981
11982 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11983 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11984 }
11985 else {
11986 u32 grc_mode;
11987
ec41c7df
MC		 11988 ret = tg3_nvram_lock(tp);
11989 if (ret)
11990 return ret;
1da177e4 11991
e6af301b
MC		 11992 tg3_enable_nvram_access(tp);
11993 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11994 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11995 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11996
11997 grc_mode = tr32(GRC_MODE);
11998 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11999
12000 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12001 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12002
12003 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12004 buf);
12005 }
12006 else {
12007 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12008 buf);
12009 }
12010
12011 grc_mode = tr32(GRC_MODE);
12012 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12013
e6af301b 12014 tg3_disable_nvram_access(tp);
1da177e4
LT		 12015 tg3_nvram_unlock(tp);
12016 }
12017
12018 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 12019 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 12020 udelay(40);
12021 }
12022
12023 return ret;
12024}
12025
12026struct subsys_tbl_ent {
12027 u16 subsys_vendor, subsys_devid;
12028 u32 phy_id;
12029};
12030
12031static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12032 /* Broadcom boards. */
12033 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12034 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12035 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12036 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12037 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12038 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12039 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12040 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12041 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12042 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12043 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12044
12045 /* 3com boards. */
12046 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12047 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12048 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12049 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12050 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12051
12052 /* DELL boards. */
12053 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12054 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12055 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12056 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12057
12058 /* Compaq boards. */
12059 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12060 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12061 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12062 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12063 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12064
12065 /* IBM boards. */
12066 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12067};
12068
12069static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12070{
12071 int i;
12072
12073 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12074 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12075 tp->pdev->subsystem_vendor) &&
12076 (subsys_id_to_phy_id[i].subsys_devid ==
12077 tp->pdev->subsystem_device))
12078 return &subsys_id_to_phy_id[i];
12079 }
12080 return NULL;
12081}
12082
7d0c41ef 12083static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12084{
1da177e4 12085 u32 val;
caf636c7
MC		 12086 u16 pmcsr;
12087
12088 /* On some early chips the SRAM cannot be accessed in D3hot state,
12089 * so need make sure we're in D0.
12090 */
12091 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12092 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12093 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12094 msleep(1);
7d0c41ef
MC		 12095
12096 /* Make sure register accesses (indirect or otherwise)
12097 * will function correctly.
12098 */
12099 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12100 tp->misc_host_ctrl);
1da177e4 12101
f49639e6
DM		 12102 /* The memory arbiter has to be enabled in order for SRAM accesses
12103 * to succeed. Normally on powerup the tg3 chip firmware will make
12104 * sure it is enabled, but other entities such as system netboot
12105 * code might disable it.
12106 */
12107 val = tr32(MEMARB_MODE);
12108 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12109
1da177e4 12110 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12111 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12112
a85feb8c
GZ		 12113 /* Assume an onboard device and WOL capable by default. */
12114 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12115
b5d3772c 12116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12117 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12118 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12119 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12120 }
0527ba35
MC		 12121 val = tr32(VCPU_CFGSHDW);
12122 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12123 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12124 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12125 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12126 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12127 goto done;
b5d3772c
MC		 12128 }
12129
1da177e4
LT		 12130 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12131 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12132 u32 nic_cfg, led_cfg;
a9daf367 12133 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12134 int eeprom_phy_serdes = 0;
1da177e4
LT		 12135
12136 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12137 tp->nic_sram_data_cfg = nic_cfg;
12138
12139 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12140 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12141 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12142 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12143 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12144 (ver > 0) && (ver < 0x100))
12145 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12146
a9daf367
MC		 12147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12148 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12149
1da177e4
LT		 12150 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12151 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12152 eeprom_phy_serdes = 1;
12153
12154 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12155 if (nic_phy_id != 0) {
12156 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12157 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12158
12159 eeprom_phy_id = (id1 >> 16) << 10;
12160 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12161 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12162 } else
12163 eeprom_phy_id = 0;
12164
7d0c41ef 12165 tp->phy_id = eeprom_phy_id;
747e8f8b 12166 if (eeprom_phy_serdes) {
a4e2b347 12167 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 12168 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12169 else
12170 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12171 }
7d0c41ef 12172
cbf46853 12173 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12174 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12175 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12176 else
1da177e4
LT		 12177 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12178
12179 switch (led_cfg) {
12180 default:
12181 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12182 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12183 break;
12184
12185 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12186 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12187 break;
12188
12189 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12190 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12191
12192 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12193 * read on some older 5700/5701 bootcode.
12194 */
12195 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12196 ASIC_REV_5700 ||
12197 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12198 ASIC_REV_5701)
12199 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12200
1da177e4
LT		 12201 break;
12202
12203 case SHASTA_EXT_LED_SHARED:
12204 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12205 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12206 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12207 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12208 LED_CTRL_MODE_PHY_2);
12209 break;
12210
12211 case SHASTA_EXT_LED_MAC:
12212 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12213 break;
12214
12215 case SHASTA_EXT_LED_COMBO:
12216 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12217 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12218 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12219 LED_CTRL_MODE_PHY_2);
12220 break;
12221
855e1111 12222 }
1da177e4
LT		 12223
12224 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12226 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12227 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12228
b2a5c19c
MC		 12229 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12230 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12231
9d26e213 12232 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12233 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12234 if ((tp->pdev->subsystem_vendor ==
12235 PCI_VENDOR_ID_ARIMA) &&
12236 (tp->pdev->subsystem_device == 0x205a ||
12237 tp->pdev->subsystem_device == 0x2063))
12238 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12239 } else {
f49639e6 12240 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12241 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12242 }
1da177e4
LT		 12243
12244 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12245 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12246 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12247 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12248 }
b2b98d4a
MC		 12249
12250 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12251 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12252 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12253
a85feb8c
GZ		 12254 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12255 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12256 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12257
12dac075 12258 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12259 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12260 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12261
1da177e4
LT		 12262 if (cfg2 & (1 << 17))
12263 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12264
12265 /* serdes signal pre-emphasis in register 0x590 set by */
12266 /* bootcode if bit 18 is set */
12267 if (cfg2 & (1 << 18))
12268 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12269
321d32a0
MC		 12270 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12271 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12272 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12273 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12274
8ed5d97e
MC		 12275 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12276 u32 cfg3;
12277
12278 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12279 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12280 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12281 }
a9daf367
MC		 12282
12283 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12284 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12285 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12286 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12287 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12288 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12289 }
05ac4cb7
MC		 12290done:
12291 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12292 device_set_wakeup_enable(&tp->pdev->dev,
12293 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12294}
12295
b2a5c19c
MC		 12296static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12297{
12298 int i;
12299 u32 val;
12300
12301 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12302 tw32(OTP_CTRL, cmd);
12303
12304 /* Wait for up to 1 ms for command to execute. */
12305 for (i = 0; i < 100; i++) {
12306 val = tr32(OTP_STATUS);
12307 if (val & OTP_STATUS_CMD_DONE)
12308 break;
12309 udelay(10);
12310 }
12311
12312 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12313}
12314
12315/* Read the gphy configuration from the OTP region of the chip. The gphy
12316 * configuration is a 32-bit value that straddles the alignment boundary.
12317 * We do two 32-bit reads and then shift and merge the results.
12318 */
12319static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12320{
12321 u32 bhalf_otp, thalf_otp;
12322
12323 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12324
12325 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12326 return 0;
12327
12328 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12329
12330 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12331 return 0;
12332
12333 thalf_otp = tr32(OTP_READ_DATA);
12334
12335 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12336
12337 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12338 return 0;
12339
12340 bhalf_otp = tr32(OTP_READ_DATA);
12341
12342 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12343}
12344
7d0c41ef
MC		 12345static int __devinit tg3_phy_probe(struct tg3 *tp)
12346{
12347 u32 hw_phy_id_1, hw_phy_id_2;
12348 u32 hw_phy_id, hw_phy_id_masked;
12349 int err;
1da177e4 12350
b02fd9e3
MC		 12351 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12352 return tg3_phy_init(tp);
12353
1da177e4 12354 /* Reading the PHY ID register can conflict with ASF
877d0310 12355 * firmware access to the PHY hardware.
1da177e4
LT		 12356 */
12357 err = 0;
0d3031d9
MC		 12358 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12359 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12360 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12361 } else {
12362 /* Now read the physical PHY_ID from the chip and verify
12363 * that it is sane. If it doesn't look good, we fall back
12364 * to either the hard-coded table based PHY_ID and failing
12365 * that the value found in the eeprom area.
12366 */
12367 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12368 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12369
12370 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12371 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12372 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12373
12374 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12375 }
12376
12377 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12378 tp->phy_id = hw_phy_id;
12379 if (hw_phy_id_masked == PHY_ID_BCM8002)
12380 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12381 else
12382 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12383 } else {
7d0c41ef
MC		 12384 if (tp->phy_id != PHY_ID_INVALID) {
12385 /* Do nothing, phy ID already set up in
12386 * tg3_get_eeprom_hw_cfg().
12387 */
1da177e4
LT		 12388 } else {
12389 struct subsys_tbl_ent *p;
12390
12391 /* No eeprom signature? Try the hardcoded
12392 * subsys device table.
12393 */
12394 p = lookup_by_subsys(tp);
12395 if (!p)
12396 return -ENODEV;
12397
12398 tp->phy_id = p->phy_id;
12399 if (!tp->phy_id ||
12400 tp->phy_id == PHY_ID_BCM8002)
12401 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12402 }
12403 }
12404
747e8f8b 12405 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12406 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12407 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12408 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12409
12410 tg3_readphy(tp, MII_BMSR, &bmsr);
12411 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12412 (bmsr & BMSR_LSTATUS))
12413 goto skip_phy_reset;
6aa20a22 12414
1da177e4
LT		 12415 err = tg3_phy_reset(tp);
12416 if (err)
12417 return err;
12418
12419 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12420 ADVERTISE_100HALF | ADVERTISE_100FULL |
12421 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12422 tg3_ctrl = 0;
12423 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12424 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12425 MII_TG3_CTRL_ADV_1000_FULL);
12426 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12427 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12428 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12429 MII_TG3_CTRL_ENABLE_AS_MASTER);
12430 }
12431
3600d918
MC		 12432 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12433 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12434 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12435 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12436 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12437
12438 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12439 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12440
12441 tg3_writephy(tp, MII_BMCR,
12442 BMCR_ANENABLE | BMCR_ANRESTART);
12443 }
12444 tg3_phy_set_wirespeed(tp);
12445
12446 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12447 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12448 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12449 }
12450
12451skip_phy_reset:
12452 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12453 err = tg3_init_5401phy_dsp(tp);
12454 if (err)
12455 return err;
12456 }
12457
12458 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12459 err = tg3_init_5401phy_dsp(tp);
12460 }
12461
747e8f8b 12462 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12463 tp->link_config.advertising =
12464 (ADVERTISED_1000baseT_Half |
12465 ADVERTISED_1000baseT_Full |
12466 ADVERTISED_Autoneg |
12467 ADVERTISED_FIBRE);
12468 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12469 tp->link_config.advertising &=
12470 ~(ADVERTISED_1000baseT_Half |
12471 ADVERTISED_1000baseT_Full);
12472
12473 return err;
12474}
12475
12476static void __devinit tg3_read_partno(struct tg3 *tp)
12477{
141518c9 12478 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12479 unsigned int i;
1b27777a 12480 u32 magic;
1da177e4 12481
df259d8c
MC		 12482 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12483 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12484 goto out_not_found;
1da177e4 12485
1820180b 12486 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12487 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12488 u32 tmp;
1da177e4 12489
6d348f2c
MC		 12490 /* The data is in little-endian format in NVRAM.
12491 * Use the big-endian read routines to preserve
12492 * the byte order as it exists in NVRAM.
12493 */
141518c9 12494 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12495 goto out_not_found;
12496
6d348f2c 12497 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12498 }
12499 } else {
94c982bd
MC		 12500 ssize_t cnt;
12501 unsigned int pos = 0, i = 0;
12502
12503 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12504 cnt = pci_read_vpd(tp->pdev, pos,
12505 TG3_NVM_VPD_LEN - pos,
12506 &vpd_data[pos]);
12507 if (cnt == -ETIMEDOUT || -EINTR)
12508 cnt = 0;
12509 else if (cnt < 0)
f49639e6 12510 goto out_not_found;
1b27777a 12511 }
94c982bd
MC		 12512 if (pos != TG3_NVM_VPD_LEN)
12513 goto out_not_found;
1da177e4
LT		 12514 }
12515
12516 /* Now parse and find the part number. */
141518c9 12517 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12518 unsigned char val = vpd_data[i];
af2c6a4a 12519 unsigned int block_end;
1da177e4
LT		 12520
12521 if (val == 0x82 || val == 0x91) {
12522 i = (i + 3 +
12523 (vpd_data[i + 1] +
12524 (vpd_data[i + 2] << 8)));
12525 continue;
12526 }
12527
12528 if (val != 0x90)
12529 goto out_not_found;
12530
12531 block_end = (i + 3 +
12532 (vpd_data[i + 1] +
12533 (vpd_data[i + 2] << 8)));
12534 i += 3;
af2c6a4a 12535
141518c9 12536 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12537 goto out_not_found;
12538
12539 while (i < (block_end - 2)) {
1da177e4
LT		 12540 if (vpd_data[i + 0] == 'P' &&
12541 vpd_data[i + 1] == 'N') {
12542 int partno_len = vpd_data[i + 2];
12543
af2c6a4a 12544 i += 3;
141518c9
MC		 12545 if (partno_len > TG3_BPN_SIZE ||
12546 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12547 goto out_not_found;
12548
12549 memcpy(tp->board_part_number,
af2c6a4a 12550 &vpd_data[i], partno_len);
1da177e4
LT		 12551
12552 /* Success. */
12553 return;
12554 }
af2c6a4a 12555 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12556 }
12557
12558 /* Part number not found. */
12559 goto out_not_found;
12560 }
12561
12562out_not_found:
b5d3772c
MC		 12563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12564 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12565 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12566 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12567 strcpy(tp->board_part_number, "BCM57780");
12568 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12569 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12570 strcpy(tp->board_part_number, "BCM57760");
12571 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12572 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12573 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12574 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12576 strcpy(tp->board_part_number, "BCM57788");
b703df6f
MC		 12577 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12578 strcpy(tp->board_part_number, "BCM57765");
b5d3772c
MC		 12579 else
12580 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12581}
12582
9c8a620e
MC		 12583static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12584{
12585 u32 val;
12586
e4f34110 12587 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12588 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12589 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12590 val != 0)
12591 return 0;
12592
12593 return 1;
12594}
12595
acd9c119
MC		 12596static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12597{
ff3a7cb2 12598 u32 val, offset, start, ver_offset;
acd9c119 12599 int i;
ff3a7cb2 12600 bool newver = false;
acd9c119
MC		 12601
12602 if (tg3_nvram_read(tp, 0xc, &offset) ||
12603 tg3_nvram_read(tp, 0x4, &start))
12604 return;
12605
12606 offset = tg3_nvram_logical_addr(tp, offset);
12607
ff3a7cb2 12608 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12609 return;
12610
ff3a7cb2
MC		 12611 if ((val & 0xfc000000) == 0x0c000000) {
12612 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12613 return;
12614
ff3a7cb2
MC		 12615 if (val == 0)
12616 newver = true;
12617 }
12618
12619 if (newver) {
12620 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12621 return;
12622
12623 offset = offset + ver_offset - start;
12624 for (i = 0; i < 16; i += 4) {
12625 __be32 v;
12626 if (tg3_nvram_read_be32(tp, offset + i, &v))
12627 return;
12628
12629 memcpy(tp->fw_ver + i, &v, sizeof(v));
12630 }
12631 } else {
12632 u32 major, minor;
12633
12634 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12635 return;
12636
12637 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12638 TG3_NVM_BCVER_MAJSFT;
12639 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12640 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12641 }
12642}
12643
a6f6cb1c
MC		 12644static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12645{
12646 u32 val, major, minor;
12647
12648 /* Use native endian representation */
12649 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12650 return;
12651
12652 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12653 TG3_NVM_HWSB_CFG1_MAJSFT;
12654 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12655 TG3_NVM_HWSB_CFG1_MINSFT;
12656
12657 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12658}
12659
dfe00d7d
MC		 12660static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12661{
12662 u32 offset, major, minor, build;
12663
12664 tp->fw_ver[0] = 's';
12665 tp->fw_ver[1] = 'b';
12666 tp->fw_ver[2] = '\0';
12667
12668 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12669 return;
12670
12671 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12672 case TG3_EEPROM_SB_REVISION_0:
12673 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12674 break;
12675 case TG3_EEPROM_SB_REVISION_2:
12676 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12677 break;
12678 case TG3_EEPROM_SB_REVISION_3:
12679 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12680 break;
12681 default:
12682 return;
12683 }
12684
e4f34110 12685 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12686 return;
12687
12688 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12689 TG3_EEPROM_SB_EDH_BLD_SHFT;
12690 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12691 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12692 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12693
12694 if (minor > 99 || build > 26)
12695 return;
12696
12697 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12698
12699 if (build > 0) {
12700 tp->fw_ver[8] = 'a' + build - 1;
12701 tp->fw_ver[9] = '\0';
12702 }
12703}
12704
acd9c119 12705static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12706{
12707 u32 val, offset, start;
acd9c119 12708 int i, vlen;
9c8a620e
MC		 12709
12710 for (offset = TG3_NVM_DIR_START;
12711 offset < TG3_NVM_DIR_END;
12712 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12713 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12714 return;
12715
9c8a620e
MC		 12716 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12717 break;
12718 }
12719
12720 if (offset == TG3_NVM_DIR_END)
12721 return;
12722
12723 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12724 start = 0x08000000;
e4f34110 12725 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12726 return;
12727
e4f34110 12728 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12729 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12730 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12731 return;
12732
12733 offset += val - start;
12734
acd9c119 12735 vlen = strlen(tp->fw_ver);
9c8a620e 12736
acd9c119
MC		 12737 tp->fw_ver[vlen++] = ',';
12738 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12739
12740 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12741 __be32 v;
12742 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12743 return;
12744
b9fc7dc5 12745 offset += sizeof(v);
c4e6575c 12746
acd9c119
MC		 12747 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12748 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12749 break;
c4e6575c 12750 }
9c8a620e 12751
acd9c119
MC		 12752 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12753 vlen += sizeof(v);
c4e6575c 12754 }
acd9c119
MC		 12755}
12756
7fd76445
MC		 12757static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12758{
12759 int vlen;
12760 u32 apedata;
12761
12762 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12763 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12764 return;
12765
12766 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12767 if (apedata != APE_SEG_SIG_MAGIC)
12768 return;
12769
12770 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12771 if (!(apedata & APE_FW_STATUS_READY))
12772 return;
12773
12774 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12775
12776 vlen = strlen(tp->fw_ver);
12777
12778 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12779 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12780 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12781 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12782 (apedata & APE_FW_VERSION_BLDMSK));
12783}
12784
acd9c119
MC		 12785static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12786{
12787 u32 val;
12788
df259d8c
MC		 12789 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12790 tp->fw_ver[0] = 's';
12791 tp->fw_ver[1] = 'b';
12792 tp->fw_ver[2] = '\0';
12793
12794 return;
12795 }
12796
acd9c119
MC		 12797 if (tg3_nvram_read(tp, 0, &val))
12798 return;
12799
12800 if (val == TG3_EEPROM_MAGIC)
12801 tg3_read_bc_ver(tp);
12802 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12803 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12804 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12805 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12806 else
12807 return;
12808
12809 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12810 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12811 return;
12812
12813 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12814
12815 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12816}
12817
7544b097
MC		 12818static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12819
1da177e4
LT		 12820static int __devinit tg3_get_invariants(struct tg3 *tp)
12821{
12822 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12823 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12824 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12825 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12826 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12827 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12828 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12829 { },
12830 };
12831 u32 misc_ctrl_reg;
1da177e4
LT		 12832 u32 pci_state_reg, grc_misc_cfg;
12833 u32 val;
12834 u16 pci_cmd;
5e7dfd0f 12835 int err;
1da177e4 12836
1da177e4
LT		 12837 /* Force memory write invalidate off. If we leave it on,
12838 * then on 5700_BX chips we have to enable a workaround.
12839 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12840 * to match the cacheline size. The Broadcom driver have this
12841 * workaround but turns MWI off all the times so never uses
12842 * it. This seems to suggest that the workaround is insufficient.
12843 */
12844 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12845 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12846 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12847
12848 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12849 * has the register indirect write enable bit set before
12850 * we try to access any of the MMIO registers. It is also
12851 * critical that the PCI-X hw workaround situation is decided
12852 * before that as well.
12853 */
12854 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12855 &misc_ctrl_reg);
12856
12857 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12858 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12860 u32 prod_id_asic_rev;
12861
5001e2f6
MC		 12862 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12863 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12864 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12865 pci_read_config_dword(tp->pdev,
12866 TG3PCI_GEN2_PRODID_ASICREV,
12867 &prod_id_asic_rev);
b703df6f
MC		 12868 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12869 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12870 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12874 pci_read_config_dword(tp->pdev,
12875 TG3PCI_GEN15_PRODID_ASICREV,
12876 &prod_id_asic_rev);
f6eb9b1f
MC		 12877 else
12878 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12879 &prod_id_asic_rev);
12880
321d32a0 12881 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12882 }
1da177e4 12883
ff645bec
MC		 12884 /* Wrong chip ID in 5752 A0. This code can be removed later
12885 * as A0 is not in production.
12886 */
12887 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12888 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12889
6892914f
MC		 12890 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12891 * we need to disable memory and use config. cycles
12892 * only to access all registers. The 5702/03 chips
12893 * can mistakenly decode the special cycles from the
12894 * ICH chipsets as memory write cycles, causing corruption
12895 * of register and memory space. Only certain ICH bridges
12896 * will drive special cycles with non-zero data during the
12897 * address phase which can fall within the 5703's address
12898 * range. This is not an ICH bug as the PCI spec allows
12899 * non-zero address during special cycles. However, only
12900 * these ICH bridges are known to drive non-zero addresses
12901 * during special cycles.
12902 *
12903 * Since special cycles do not cross PCI bridges, we only
12904 * enable this workaround if the 5703 is on the secondary
12905 * bus of these ICH bridges.
12906 */
12907 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12908 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12909 static struct tg3_dev_id {
12910 u32 vendor;
12911 u32 device;
12912 u32 rev;
12913 } ich_chipsets[] = {
12914 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12915 PCI_ANY_ID },
12916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12917 PCI_ANY_ID },
12918 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12919 0xa },
12920 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12921 PCI_ANY_ID },
12922 { },
12923 };
12924 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12925 struct pci_dev *bridge = NULL;
12926
12927 while (pci_id->vendor != 0) {
12928 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12929 bridge);
12930 if (!bridge) {
12931 pci_id++;
12932 continue;
12933 }
12934 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12935 if (bridge->revision > pci_id->rev)
6892914f
MC		 12936 continue;
12937 }
12938 if (bridge->subordinate &&
12939 (bridge->subordinate->number ==
12940 tp->pdev->bus->number)) {
12941
12942 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12943 pci_dev_put(bridge);
12944 break;
12945 }
12946 }
12947 }
12948
41588ba1
MC		 12949 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12950 static struct tg3_dev_id {
12951 u32 vendor;
12952 u32 device;
12953 } bridge_chipsets[] = {
12954 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12955 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12956 { },
12957 };
12958 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12959 struct pci_dev *bridge = NULL;
12960
12961 while (pci_id->vendor != 0) {
12962 bridge = pci_get_device(pci_id->vendor,
12963 pci_id->device,
12964 bridge);
12965 if (!bridge) {
12966 pci_id++;
12967 continue;
12968 }
12969 if (bridge->subordinate &&
12970 (bridge->subordinate->number <=
12971 tp->pdev->bus->number) &&
12972 (bridge->subordinate->subordinate >=
12973 tp->pdev->bus->number)) {
12974 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12975 pci_dev_put(bridge);
12976 break;
12977 }
12978 }
12979 }
12980
4a29cc2e
MC		 12981 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12982 * DMA addresses > 40-bit. This bridge may have other additional
12983 * 57xx devices behind it in some 4-port NIC designs for example.
12984 * Any tg3 device found behind the bridge will also need the 40-bit
12985 * DMA workaround.
12986 */
a4e2b347
MC		 12987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12989 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12990 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12991 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12992 }
4a29cc2e
MC		 12993 else {
12994 struct pci_dev *bridge = NULL;
12995
12996 do {
12997 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12998 PCI_DEVICE_ID_SERVERWORKS_EPB,
12999 bridge);
13000 if (bridge && bridge->subordinate &&
13001 (bridge->subordinate->number <=
13002 tp->pdev->bus->number) &&
13003 (bridge->subordinate->subordinate >=
13004 tp->pdev->bus->number)) {
13005 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13006 pci_dev_put(bridge);
13007 break;
13008 }
13009 } while (bridge);
13010 }
4cf78e4f 13011
1da177e4
LT		 13012 /* Initialize misc host control in PCI block. */
13013 tp->misc_host_ctrl |= (misc_ctrl_reg &
13014 MISC_HOST_CTRL_CHIPREV);
13015 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13016 tp->misc_host_ctrl);
13017
f6eb9b1f
MC		 13018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 13021 tp->pdev_peer = tg3_find_peer(tp);
13022
321d32a0
MC		 13023 /* Intentionally exclude ASIC_REV_5906 */
13024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 13025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 13026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 13027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13032 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13033
13034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13037 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13038 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13039 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13040
1b440c56
JL		 13041 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13042 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13043 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13044
027455ad
MC		 13045 /* 5700 B0 chips do not support checksumming correctly due
13046 * to hardware bugs.
13047 */
13048 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13049 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13050 else {
13051 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13052 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13053 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13054 tp->dev->features |= NETIF_F_IPV6_CSUM;
13055 }
13056
507399f1 13057 /* Determine TSO capabilities */
b703df6f
MC		 13058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13060 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13061 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13063 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13064 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13065 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13067 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13068 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13069 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13070 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13071 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13072 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13074 tp->fw_needed = FIRMWARE_TG3TSO5;
13075 else
13076 tp->fw_needed = FIRMWARE_TG3TSO;
13077 }
13078
13079 tp->irq_max = 1;
13080
5a6f3074 13081 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13082 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13083 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13084 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13085 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13086 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13087 tp->pdev_peer == tp->pdev))
13088 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13089
321d32a0 13090 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13092 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13093 }
4f125f42 13094
b703df6f
MC		 13095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13097 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13098 tp->irq_max = TG3_IRQ_MAX_VECS;
13099 }
f6eb9b1f 13100 }
0e1406dd 13101
615774fe
MC		 13102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13104 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13105 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13106 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13107 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13108 }
f6eb9b1f 13109
b703df6f
MC		 13110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13112 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13113
f51f3562 13114 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13115 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13116 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13117 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13118
52f4490c
MC		 13119 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13120 &pci_state_reg);
13121
5e7dfd0f
MC		 13122 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13123 if (tp->pcie_cap != 0) {
13124 u16 lnkctl;
13125
1da177e4 13126 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13127
13128 pcie_set_readrq(tp->pdev, 4096);
13129
5e7dfd0f
MC		 13130 pci_read_config_word(tp->pdev,
13131 tp->pcie_cap + PCI_EXP_LNKCTL,
13132 &lnkctl);
13133 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13135 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13138 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13139 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13140 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13141 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13142 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13143 }
52f4490c 13144 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13145 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13146 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13147 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13148 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13149 if (!tp->pcix_cap) {
13150 printk(KERN_ERR PFX "Cannot find PCI-X "
13151 "capability, aborting.\n");
13152 return -EIO;
13153 }
13154
13155 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13156 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13157 }
1da177e4 13158
399de50b
MC		 13159 /* If we have an AMD 762 or VIA K8T800 chipset, write
13160 * reordering to the mailbox registers done by the host
13161 * controller can cause major troubles. We read back from
13162 * every mailbox register write to force the writes to be
13163 * posted to the chip in order.
13164 */
13165 if (pci_dev_present(write_reorder_chipsets) &&
13166 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13167 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13168
69fc4053
MC		 13169 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13170 &tp->pci_cacheline_sz);
13171 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13172 &tp->pci_lat_timer);
1da177e4
LT		 13173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13174 tp->pci_lat_timer < 64) {
13175 tp->pci_lat_timer = 64;
69fc4053
MC		 13176 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13177 tp->pci_lat_timer);
1da177e4
LT		 13178 }
13179
52f4490c
MC		 13180 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13181 /* 5700 BX chips need to have their TX producer index
13182 * mailboxes written twice to workaround a bug.
13183 */
13184 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13185
52f4490c 13186 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13187 *
13188 * The workaround is to use indirect register accesses
13189 * for all chip writes not to mailbox registers.
13190 */
52f4490c 13191 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13192 u32 pm_reg;
1da177e4
LT		 13193
13194 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13195
13196 /* The chip can have it's power management PCI config
13197 * space registers clobbered due to this bug.
13198 * So explicitly force the chip into D0 here.
13199 */
9974a356
MC		 13200 pci_read_config_dword(tp->pdev,
13201 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13202 &pm_reg);
13203 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13204 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13205 pci_write_config_dword(tp->pdev,
13206 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13207 pm_reg);
13208
13209 /* Also, force SERR#/PERR# in PCI command. */
13210 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13211 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13212 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13213 }
13214 }
13215
1da177e4
LT		 13216 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13217 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13218 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13219 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13220
13221 /* Chip-specific fixup from Broadcom driver */
13222 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13223 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13224 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13225 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13226 }
13227
1ee582d8 13228 /* Default fast path register access methods */
20094930 13229 tp->read32 = tg3_read32;
1ee582d8 13230 tp->write32 = tg3_write32;
09ee929c 13231 tp->read32_mbox = tg3_read32;
20094930 13232 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13233 tp->write32_tx_mbox = tg3_write32;
13234 tp->write32_rx_mbox = tg3_write32;
13235
13236 /* Various workaround register access methods */
13237 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13238 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13239 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13240 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13241 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13242 /*
13243 * Back to back register writes can cause problems on these
13244 * chips, the workaround is to read back all reg writes
13245 * except those to mailbox regs.
13246 *
13247 * See tg3_write_indirect_reg32().
13248 */
1ee582d8 13249 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13250 }
13251
1ee582d8
MC		 13252 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13253 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13254 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13255 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13256 tp->write32_rx_mbox = tg3_write_flush_reg32;
13257 }
20094930 13258
6892914f
MC		 13259 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13260 tp->read32 = tg3_read_indirect_reg32;
13261 tp->write32 = tg3_write_indirect_reg32;
13262 tp->read32_mbox = tg3_read_indirect_mbox;
13263 tp->write32_mbox = tg3_write_indirect_mbox;
13264 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13265 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13266
13267 iounmap(tp->regs);
22abe310 13268 tp->regs = NULL;
6892914f
MC		 13269
13270 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13271 pci_cmd &= ~PCI_COMMAND_MEMORY;
13272 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13273 }
b5d3772c
MC		 13274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13275 tp->read32_mbox = tg3_read32_mbox_5906;
13276 tp->write32_mbox = tg3_write32_mbox_5906;
13277 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13278 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13279 }
6892914f 13280
bbadf503
MC		 13281 if (tp->write32 == tg3_write_indirect_reg32 ||
13282 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13283 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13285 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13286
7d0c41ef 13287 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13288 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13289 * determined before calling tg3_set_power_state() so that
13290 * we know whether or not to switch out of Vaux power.
13291 * When the flag is set, it means that GPIO1 is used for eeprom
13292 * write protect and also implies that it is a LOM where GPIOs
13293 * are not used to switch power.
6aa20a22 13294 */
7d0c41ef
MC		 13295 tg3_get_eeprom_hw_cfg(tp);
13296
0d3031d9
MC		 13297 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13298 /* Allow reads and writes to the
13299 * APE register and memory space.
13300 */
13301 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13302 PCISTATE_ALLOW_APE_SHMEM_WR;
13303 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13304 pci_state_reg);
13305 }
13306
9936bcf6 13307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13313 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13314
314fba34
MC		 13315 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13316 * GPIO1 driven high will bring 5700's external PHY out of reset.
13317 * It is also used as eeprom write protect on LOMs.
13318 */
13319 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13320 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13321 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13322 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13323 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13324 /* Unused GPIO3 must be driven as output on 5752 because there
13325 * are no pull-up resistors on unused GPIO pins.
13326 */
13327 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13328 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13329
321d32a0 13330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13331 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13332 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13333 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13334
8d519ab2
MC		 13335 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13336 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13337 /* Turn off the debug UART. */
13338 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13339 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13340 /* Keep VMain power. */
13341 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13342 GRC_LCLCTRL_GPIO_OUTPUT0;
13343 }
13344
1da177e4 13345 /* Force the chip into D0. */
bc1c7567 13346 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13347 if (err) {
13348 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13349 pci_name(tp->pdev));
13350 return err;
13351 }
13352
1da177e4
LT		 13353 /* Derive initial jumbo mode from MTU assigned in
13354 * ether_setup() via the alloc_etherdev() call
13355 */
0f893dc6 13356 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13357 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13358 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13359
13360 /* Determine WakeOnLan speed to use. */
13361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13362 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13363 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13364 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13365 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13366 } else {
13367 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13368 }
13369
7f97a4bd
MC		 13370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13371 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13372
1da177e4
LT		 13373 /* A few boards don't want Ethernet@WireSpeed phy feature */
13374 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13375 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13376 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13377 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13378 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13379 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13380 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13381
13382 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13383 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13384 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13385 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13386 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13387
321d32a0 13388 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13389 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13390 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13391 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13392 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13393 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13395 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13397 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13398 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13399 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13400 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13401 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13402 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13403 } else
c424cb24
MC		 13404 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13405 }
1da177e4 13406
b2a5c19c
MC		 13407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13408 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13409 tp->phy_otp = tg3_read_otp_phycfg(tp);
13410 if (tp->phy_otp == 0)
13411 tp->phy_otp = TG3_OTP_DEFAULT;
13412 }
13413
f51f3562 13414 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13415 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13416 else
13417 tp->mi_mode = MAC_MI_MODE_BASE;
13418
1da177e4 13419 tp->coalesce_mode = 0;
1da177e4
LT		 13420 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13421 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13422 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13423
321d32a0
MC		 13424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13426 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13427
158d7abd
MC		 13428 err = tg3_mdio_init(tp);
13429 if (err)
13430 return err;
1da177e4
LT		 13431
13432 /* Initialize data/descriptor byte/word swapping. */
13433 val = tr32(GRC_MODE);
13434 val &= GRC_MODE_HOST_STACKUP;
13435 tw32(GRC_MODE, val | tp->grc_mode);
13436
13437 tg3_switch_clocks(tp);
13438
13439 /* Clear this out for sanity. */
13440 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13441
13442 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13443 &pci_state_reg);
13444 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13445 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13446 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13447
13448 if (chiprevid == CHIPREV_ID_5701_A0 ||
13449 chiprevid == CHIPREV_ID_5701_B0 ||
13450 chiprevid == CHIPREV_ID_5701_B2 ||
13451 chiprevid == CHIPREV_ID_5701_B5) {
13452 void __iomem *sram_base;
13453
13454 /* Write some dummy words into the SRAM status block
13455 * area, see if it reads back correctly. If the return
13456 * value is bad, force enable the PCIX workaround.
13457 */
13458 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13459
13460 writel(0x00000000, sram_base);
13461 writel(0x00000000, sram_base + 4);
13462 writel(0xffffffff, sram_base + 4);
13463 if (readl(sram_base) != 0x00000000)
13464 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13465 }
13466 }
13467
13468 udelay(50);
13469 tg3_nvram_init(tp);
13470
13471 grc_misc_cfg = tr32(GRC_MISC_CFG);
13472 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13473
1da177e4
LT		 13474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13475 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13476 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13477 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13478
fac9b83e
DM		 13479 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13480 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13481 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13482 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13483 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13484 HOSTCC_MODE_CLRTICK_TXBD);
13485
13486 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13487 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13488 tp->misc_host_ctrl);
13489 }
13490
3bda1258
MC		 13491 /* Preserve the APE MAC_MODE bits */
13492 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13493 tp->mac_mode = tr32(MAC_MODE) |
13494 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13495 else
13496 tp->mac_mode = TG3_DEF_MAC_MODE;
13497
1da177e4
LT		 13498 /* these are limited to 10/100 only */
13499 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13500 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13501 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13502 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13503 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13504 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13505 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13506 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13507 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13508 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13509 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13510 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13511 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13512 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13513
13514 err = tg3_phy_probe(tp);
13515 if (err) {
13516 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13517 pci_name(tp->pdev), err);
13518 /* ... but do not return immediately ... */
b02fd9e3 13519 tg3_mdio_fini(tp);
1da177e4
LT		 13520 }
13521
13522 tg3_read_partno(tp);
c4e6575c 13523 tg3_read_fw_ver(tp);
1da177e4
LT		 13524
13525 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13526 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13527 } else {
13528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13529 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13530 else
13531 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13532 }
13533
13534 /* 5700 {AX,BX} chips have a broken status block link
13535 * change bit implementation, so we must use the
13536 * status register in those cases.
13537 */
13538 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13539 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13540 else
13541 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13542
13543 /* The led_ctrl is set during tg3_phy_probe, here we might
13544 * have to force the link status polling mechanism based
13545 * upon subsystem IDs.
13546 */
13547 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13549 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13550 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13551 TG3_FLAG_USE_LINKCHG_REG);
13552 }
13553
13554 /* For all SERDES we poll the MAC status register. */
13555 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13556 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13557 else
13558 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13559
ad829268 13560 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13562 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13563 tp->rx_offset = 0;
13564
f92905de
MC		 13565 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13566
13567 /* Increment the rx prod index on the rx std ring by at most
13568 * 8 for these chips to workaround hw errata.
13569 */
13570 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13573 tp->rx_std_max_post = 8;
13574
8ed5d97e
MC		 13575 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13576 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13577 PCIE_PWR_MGMT_L1_THRESH_MSK;
13578
1da177e4
LT		 13579 return err;
13580}
13581
49b6e95f 13582#ifdef CONFIG_SPARC
1da177e4
LT		 13583static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13584{
13585 struct net_device *dev = tp->dev;
13586 struct pci_dev *pdev = tp->pdev;
49b6e95f 13587 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13588 const unsigned char *addr;
49b6e95f
DM		 13589 int len;
13590
13591 addr = of_get_property(dp, "local-mac-address", &len);
13592 if (addr && len == 6) {
13593 memcpy(dev->dev_addr, addr, 6);
13594 memcpy(dev->perm_addr, dev->dev_addr, 6);
13595 return 0;
1da177e4
LT		 13596 }
13597 return -ENODEV;
13598}
13599
13600static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13601{
13602 struct net_device *dev = tp->dev;
13603
13604 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13605 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13606 return 0;
13607}
13608#endif
13609
13610static int __devinit tg3_get_device_address(struct tg3 *tp)
13611{
13612 struct net_device *dev = tp->dev;
13613 u32 hi, lo, mac_offset;
008652b3 13614 int addr_ok = 0;
1da177e4 13615
49b6e95f 13616#ifdef CONFIG_SPARC
1da177e4
LT		 13617 if (!tg3_get_macaddr_sparc(tp))
13618 return 0;
13619#endif
13620
13621 mac_offset = 0x7c;
f49639e6 13622 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13623 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13624 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13625 mac_offset = 0xcc;
13626 if (tg3_nvram_lock(tp))
13627 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13628 else
13629 tg3_nvram_unlock(tp);
a1b950d5
MC		 13630 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13631 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13632 mac_offset = 0xcc;
13633 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13634 mac_offset = 0x10;
1da177e4
LT		 13635
13636 /* First try to get it from MAC address mailbox. */
13637 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13638 if ((hi >> 16) == 0x484b) {
13639 dev->dev_addr[0] = (hi >> 8) & 0xff;
13640 dev->dev_addr[1] = (hi >> 0) & 0xff;
13641
13642 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13643 dev->dev_addr[2] = (lo >> 24) & 0xff;
13644 dev->dev_addr[3] = (lo >> 16) & 0xff;
13645 dev->dev_addr[4] = (lo >> 8) & 0xff;
13646 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13647
008652b3
MC		 13648 /* Some old bootcode may report a 0 MAC address in SRAM */
13649 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13650 }
13651 if (!addr_ok) {
13652 /* Next, try NVRAM. */
df259d8c
MC		 13653 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13654 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13655 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13656 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13657 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13658 }
13659 /* Finally just fetch it out of the MAC control regs. */
13660 else {
13661 hi = tr32(MAC_ADDR_0_HIGH);
13662 lo = tr32(MAC_ADDR_0_LOW);
13663
13664 dev->dev_addr[5] = lo & 0xff;
13665 dev->dev_addr[4] = (lo >> 8) & 0xff;
13666 dev->dev_addr[3] = (lo >> 16) & 0xff;
13667 dev->dev_addr[2] = (lo >> 24) & 0xff;
13668 dev->dev_addr[1] = hi & 0xff;
13669 dev->dev_addr[0] = (hi >> 8) & 0xff;
13670 }
1da177e4
LT		 13671 }
13672
13673 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13674#ifdef CONFIG_SPARC
1da177e4
LT		 13675 if (!tg3_get_default_macaddr_sparc(tp))
13676 return 0;
13677#endif
13678 return -EINVAL;
13679 }
2ff43697 13680 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13681 return 0;
13682}
13683
59e6b434
DM		 13684#define BOUNDARY_SINGLE_CACHELINE 1
13685#define BOUNDARY_MULTI_CACHELINE 2
13686
13687static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13688{
13689 int cacheline_size;
13690 u8 byte;
13691 int goal;
13692
13693 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13694 if (byte == 0)
13695 cacheline_size = 1024;
13696 else
13697 cacheline_size = (int) byte * 4;
13698
13699 /* On 5703 and later chips, the boundary bits have no
13700 * effect.
13701 */
13702 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13703 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13704 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13705 goto out;
13706
13707#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13708 goal = BOUNDARY_MULTI_CACHELINE;
13709#else
13710#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13711 goal = BOUNDARY_SINGLE_CACHELINE;
13712#else
13713 goal = 0;
13714#endif
13715#endif
13716
b703df6f
MC		 13717 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13719 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13720 goto out;
13721 }
13722
59e6b434
DM		 13723 if (!goal)
13724 goto out;
13725
13726 /* PCI controllers on most RISC systems tend to disconnect
13727 * when a device tries to burst across a cache-line boundary.
13728 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13729 *
13730 * Unfortunately, for PCI-E there are only limited
13731 * write-side controls for this, and thus for reads
13732 * we will still get the disconnects. We'll also waste
13733 * these PCI cycles for both read and write for chips
13734 * other than 5700 and 5701 which do not implement the
13735 * boundary bits.
13736 */
13737 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13738 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13739 switch (cacheline_size) {
13740 case 16:
13741 case 32:
13742 case 64:
13743 case 128:
13744 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13745 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13746 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13747 } else {
13748 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13749 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13750 }
13751 break;
13752
13753 case 256:
13754 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13755 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13756 break;
13757
13758 default:
13759 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13760 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13761 break;
855e1111 13762 }
59e6b434
DM		 13763 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13764 switch (cacheline_size) {
13765 case 16:
13766 case 32:
13767 case 64:
13768 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13769 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13770 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13771 break;
13772 }
13773 /* fallthrough */
13774 case 128:
13775 default:
13776 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13777 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13778 break;
855e1111 13779 }
59e6b434
DM		 13780 } else {
13781 switch (cacheline_size) {
13782 case 16:
13783 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13784 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13785 DMA_RWCTRL_WRITE_BNDRY_16);
13786 break;
13787 }
13788 /* fallthrough */
13789 case 32:
13790 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13791 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13792 DMA_RWCTRL_WRITE_BNDRY_32);
13793 break;
13794 }
13795 /* fallthrough */
13796 case 64:
13797 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13798 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13799 DMA_RWCTRL_WRITE_BNDRY_64);
13800 break;
13801 }
13802 /* fallthrough */
13803 case 128:
13804 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13805 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13806 DMA_RWCTRL_WRITE_BNDRY_128);
13807 break;
13808 }
13809 /* fallthrough */
13810 case 256:
13811 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13812 DMA_RWCTRL_WRITE_BNDRY_256);
13813 break;
13814 case 512:
13815 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13816 DMA_RWCTRL_WRITE_BNDRY_512);
13817 break;
13818 case 1024:
13819 default:
13820 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13821 DMA_RWCTRL_WRITE_BNDRY_1024);
13822 break;
855e1111 13823 }
59e6b434
DM		 13824 }
13825
13826out:
13827 return val;
13828}
13829
1da177e4
LT		 13830static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13831{
13832 struct tg3_internal_buffer_desc test_desc;
13833 u32 sram_dma_descs;
13834 int i, ret;
13835
13836 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13837
13838 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13839 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13840 tw32(RDMAC_STATUS, 0);
13841 tw32(WDMAC_STATUS, 0);
13842
13843 tw32(BUFMGR_MODE, 0);
13844 tw32(FTQ_RESET, 0);
13845
13846 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13847 test_desc.addr_lo = buf_dma & 0xffffffff;
13848 test_desc.nic_mbuf = 0x00002100;
13849 test_desc.len = size;
13850
13851 /*
13852 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13853 * the *second* time the tg3 driver was getting loaded after an
13854 * initial scan.
13855 *
13856 * Broadcom tells me:
13857 * ...the DMA engine is connected to the GRC block and a DMA
13858 * reset may affect the GRC block in some unpredictable way...
13859 * The behavior of resets to individual blocks has not been tested.
13860 *
13861 * Broadcom noted the GRC reset will also reset all sub-components.
13862 */
13863 if (to_device) {
13864 test_desc.cqid_sqid = (13 << 8) | 2;
13865
13866 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13867 udelay(40);
13868 } else {
13869 test_desc.cqid_sqid = (16 << 8) | 7;
13870
13871 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13872 udelay(40);
13873 }
13874 test_desc.flags = 0x00000005;
13875
13876 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13877 u32 val;
13878
13879 val = *(((u32 *)&test_desc) + i);
13880 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13881 sram_dma_descs + (i * sizeof(u32)));
13882 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13883 }
13884 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13885
13886 if (to_device) {
13887 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13888 } else {
13889 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13890 }
13891
13892 ret = -ENODEV;
13893 for (i = 0; i < 40; i++) {
13894 u32 val;
13895
13896 if (to_device)
13897 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13898 else
13899 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13900 if ((val & 0xffff) == sram_dma_descs) {
13901 ret = 0;
13902 break;
13903 }
13904
13905 udelay(100);
13906 }
13907
13908 return ret;
13909}
13910
ded7340d 13911#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13912
13913static int __devinit tg3_test_dma(struct tg3 *tp)
13914{
13915 dma_addr_t buf_dma;
59e6b434 13916 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13917 int ret = 0;
1da177e4
LT		 13918
13919 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13920 if (!buf) {
13921 ret = -ENOMEM;
13922 goto out_nofree;
13923 }
13924
13925 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13926 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13927
59e6b434 13928 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13929
b703df6f
MC		 13930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13932 goto out;
13933
1da177e4
LT		 13934 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13935 /* DMA read watermark not used on PCIE */
13936 tp->dma_rwctrl |= 0x00180000;
13937 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13940 tp->dma_rwctrl |= 0x003f0000;
13941 else
13942 tp->dma_rwctrl |= 0x003f000f;
13943 } else {
13944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13946 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13947 u32 read_water = 0x7;
1da177e4 13948
4a29cc2e
MC		 13949 /* If the 5704 is behind the EPB bridge, we can
13950 * do the less restrictive ONE_DMA workaround for
13951 * better performance.
13952 */
13953 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13955 tp->dma_rwctrl |= 0x8000;
13956 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13957 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13958
49afdeb6
MC		 13959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13960 read_water = 4;
59e6b434 13961 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13962 tp->dma_rwctrl |=
13963 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13964 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13965 (1 << 23);
4cf78e4f
MC		 13966 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13967 /* 5780 always in PCIX mode */
13968 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13969 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13970 /* 5714 always in PCIX mode */
13971 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13972 } else {
13973 tp->dma_rwctrl |= 0x001b000f;
13974 }
13975 }
13976
13977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13979 tp->dma_rwctrl &= 0xfffffff0;
13980
13981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13982 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13983 /* Remove this if it causes problems for some boards. */
13984 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13985
13986 /* On 5700/5701 chips, we need to set this bit.
13987 * Otherwise the chip will issue cacheline transactions
13988 * to streamable DMA memory with not all the byte
13989 * enables turned on. This is an error on several
13990 * RISC PCI controllers, in particular sparc64.
13991 *
13992 * On 5703/5704 chips, this bit has been reassigned
13993 * a different meaning. In particular, it is used
13994 * on those chips to enable a PCI-X workaround.
13995 */
13996 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13997 }
13998
13999 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14000
14001#if 0
14002 /* Unneeded, already done by tg3_get_invariants. */
14003 tg3_switch_clocks(tp);
14004#endif
14005
1da177e4
LT		 14006 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14007 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14008 goto out;
14009
59e6b434
DM		 14010 /* It is best to perform DMA test with maximum write burst size
14011 * to expose the 5700/5701 write DMA bug.
14012 */
14013 saved_dma_rwctrl = tp->dma_rwctrl;
14014 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14015 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14016
1da177e4
LT		 14017 while (1) {
14018 u32 *p = buf, i;
14019
14020 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14021 p[i] = i;
14022
14023 /* Send the buffer to the chip. */
14024 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14025 if (ret) {
14026 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14027 break;
14028 }
14029
14030#if 0
14031 /* validate data reached card RAM correctly. */
14032 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14033 u32 val;
14034 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14035 if (le32_to_cpu(val) != p[i]) {
14036 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14037 /* ret = -ENODEV here? */
14038 }
14039 p[i] = 0;
14040 }
14041#endif
14042 /* Now read it back. */
14043 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14044 if (ret) {
14045 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14046
14047 break;
14048 }
14049
14050 /* Verify it. */
14051 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14052 if (p[i] == i)
14053 continue;
14054
59e6b434
DM		 14055 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14056 DMA_RWCTRL_WRITE_BNDRY_16) {
14057 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14058 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14059 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14060 break;
14061 } else {
14062 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14063 ret = -ENODEV;
14064 goto out;
14065 }
14066 }
14067
14068 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14069 /* Success. */
14070 ret = 0;
14071 break;
14072 }
14073 }
59e6b434
DM		 14074 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14075 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14076 static struct pci_device_id dma_wait_state_chipsets[] = {
14077 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14078 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14079 { },
14080 };
14081
59e6b434 14082 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14083 * now look for chipsets that are known to expose the
14084 * DMA bug without failing the test.
59e6b434 14085 */
6d1cfbab
MC		 14086 if (pci_dev_present(dma_wait_state_chipsets)) {
14087 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14088 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14089 }
14090 else
14091 /* Safe to use the calculated DMA boundary. */
14092 tp->dma_rwctrl = saved_dma_rwctrl;
14093
59e6b434
DM		 14094 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14095 }
1da177e4
LT		 14096
14097out:
14098 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14099out_nofree:
14100 return ret;
14101}
14102
14103static void __devinit tg3_init_link_config(struct tg3 *tp)
14104{
14105 tp->link_config.advertising =
14106 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14107 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14108 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14109 ADVERTISED_Autoneg | ADVERTISED_MII);
14110 tp->link_config.speed = SPEED_INVALID;
14111 tp->link_config.duplex = DUPLEX_INVALID;
14112 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14113 tp->link_config.active_speed = SPEED_INVALID;
14114 tp->link_config.active_duplex = DUPLEX_INVALID;
14115 tp->link_config.phy_is_low_power = 0;
14116 tp->link_config.orig_speed = SPEED_INVALID;
14117 tp->link_config.orig_duplex = DUPLEX_INVALID;
14118 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14119}
14120
14121static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14122{
666bc831
MC		 14123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14125 tp->bufmgr_config.mbuf_read_dma_low_water =
14126 DEFAULT_MB_RDMA_LOW_WATER_5705;
14127 tp->bufmgr_config.mbuf_mac_rx_low_water =
14128 DEFAULT_MB_MACRX_LOW_WATER_57765;
14129 tp->bufmgr_config.mbuf_high_water =
14130 DEFAULT_MB_HIGH_WATER_57765;
14131
14132 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14133 DEFAULT_MB_RDMA_LOW_WATER_5705;
14134 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14135 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14136 tp->bufmgr_config.mbuf_high_water_jumbo =
14137 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14138 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14139 tp->bufmgr_config.mbuf_read_dma_low_water =
14140 DEFAULT_MB_RDMA_LOW_WATER_5705;
14141 tp->bufmgr_config.mbuf_mac_rx_low_water =
14142 DEFAULT_MB_MACRX_LOW_WATER_5705;
14143 tp->bufmgr_config.mbuf_high_water =
14144 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14146 tp->bufmgr_config.mbuf_mac_rx_low_water =
14147 DEFAULT_MB_MACRX_LOW_WATER_5906;
14148 tp->bufmgr_config.mbuf_high_water =
14149 DEFAULT_MB_HIGH_WATER_5906;
14150 }
fdfec172
MC		 14151
14152 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14153 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14154 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14155 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14156 tp->bufmgr_config.mbuf_high_water_jumbo =
14157 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14158 } else {
14159 tp->bufmgr_config.mbuf_read_dma_low_water =
14160 DEFAULT_MB_RDMA_LOW_WATER;
14161 tp->bufmgr_config.mbuf_mac_rx_low_water =
14162 DEFAULT_MB_MACRX_LOW_WATER;
14163 tp->bufmgr_config.mbuf_high_water =
14164 DEFAULT_MB_HIGH_WATER;
14165
14166 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14167 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14168 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14169 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14170 tp->bufmgr_config.mbuf_high_water_jumbo =
14171 DEFAULT_MB_HIGH_WATER_JUMBO;
14172 }
1da177e4
LT		 14173
14174 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14175 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14176}
14177
14178static char * __devinit tg3_phy_string(struct tg3 *tp)
14179{
14180 switch (tp->phy_id & PHY_ID_MASK) {
14181 case PHY_ID_BCM5400: return "5400";
14182 case PHY_ID_BCM5401: return "5401";
14183 case PHY_ID_BCM5411: return "5411";
14184 case PHY_ID_BCM5701: return "5701";
14185 case PHY_ID_BCM5703: return "5703";
14186 case PHY_ID_BCM5704: return "5704";
14187 case PHY_ID_BCM5705: return "5705";
14188 case PHY_ID_BCM5750: return "5750";
85e94ced 14189 case PHY_ID_BCM5752: return "5752";
a4e2b347 14190 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14191 case PHY_ID_BCM5780: return "5780";
af36e6b6 14192 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14193 case PHY_ID_BCM5787: return "5787";
d30cdd28 14194 case PHY_ID_BCM5784: return "5784";
126a3368 14195 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14196 case PHY_ID_BCM5906: return "5906";
9936bcf6 14197 case PHY_ID_BCM5761: return "5761";
9b952f51
MC		 14198 case PHY_ID_BCM5718C: return "5718C";
14199 case PHY_ID_BCM5718S: return "5718S";
1da177e4
LT		 14200 case PHY_ID_BCM8002: return "8002/serdes";
14201 case 0: return "serdes";
14202 default: return "unknown";
855e1111 14203 }
1da177e4
LT		 14204}
14205
f9804ddb
MC		 14206static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14207{
14208 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14209 strcpy(str, "PCI Express");
14210 return str;
14211 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14212 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14213
14214 strcpy(str, "PCIX:");
14215
14216 if ((clock_ctrl == 7) ||
14217 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14218 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14219 strcat(str, "133MHz");
14220 else if (clock_ctrl == 0)
14221 strcat(str, "33MHz");
14222 else if (clock_ctrl == 2)
14223 strcat(str, "50MHz");
14224 else if (clock_ctrl == 4)
14225 strcat(str, "66MHz");
14226 else if (clock_ctrl == 6)
14227 strcat(str, "100MHz");
f9804ddb
MC		 14228 } else {
14229 strcpy(str, "PCI:");
14230 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14231 strcat(str, "66MHz");
14232 else
14233 strcat(str, "33MHz");
14234 }
14235 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14236 strcat(str, ":32-bit");
14237 else
14238 strcat(str, ":64-bit");
14239 return str;
14240}
14241
8c2dc7e1 14242static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14243{
14244 struct pci_dev *peer;
14245 unsigned int func, devnr = tp->pdev->devfn & ~7;
14246
14247 for (func = 0; func < 8; func++) {
14248 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14249 if (peer && peer != tp->pdev)
14250 break;
14251 pci_dev_put(peer);
14252 }
16fe9d74
MC		 14253 /* 5704 can be configured in single-port mode, set peer to
14254 * tp->pdev in that case.
14255 */
14256 if (!peer) {
14257 peer = tp->pdev;
14258 return peer;
14259 }
1da177e4
LT		 14260
14261 /*
14262 * We don't need to keep the refcount elevated; there's no way
14263 * to remove one half of this device without removing the other
14264 */
14265 pci_dev_put(peer);
14266
14267 return peer;
14268}
14269
15f9850d
DM		 14270static void __devinit tg3_init_coal(struct tg3 *tp)
14271{
14272 struct ethtool_coalesce *ec = &tp->coal;
14273
14274 memset(ec, 0, sizeof(*ec));
14275 ec->cmd = ETHTOOL_GCOALESCE;
14276 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14277 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14278 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14279 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14280 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14281 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14282 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14283 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14284 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14285
14286 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14287 HOSTCC_MODE_CLRTICK_TXBD)) {
14288 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14289 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14290 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14291 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14292 }
d244c892
MC		 14293
14294 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14295 ec->rx_coalesce_usecs_irq = 0;
14296 ec->tx_coalesce_usecs_irq = 0;
14297 ec->stats_block_coalesce_usecs = 0;
14298 }
15f9850d
DM		 14299}
14300
7c7d64b8
SH		 14301static const struct net_device_ops tg3_netdev_ops = {
14302 .ndo_open = tg3_open,
14303 .ndo_stop = tg3_close,
00829823
SH		 14304 .ndo_start_xmit = tg3_start_xmit,
14305 .ndo_get_stats = tg3_get_stats,
14306 .ndo_validate_addr = eth_validate_addr,
14307 .ndo_set_multicast_list = tg3_set_rx_mode,
14308 .ndo_set_mac_address = tg3_set_mac_addr,
14309 .ndo_do_ioctl = tg3_ioctl,
14310 .ndo_tx_timeout = tg3_tx_timeout,
14311 .ndo_change_mtu = tg3_change_mtu,
14312#if TG3_VLAN_TAG_USED
14313 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14314#endif
14315#ifdef CONFIG_NET_POLL_CONTROLLER
14316 .ndo_poll_controller = tg3_poll_controller,
14317#endif
14318};
14319
14320static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14321 .ndo_open = tg3_open,
14322 .ndo_stop = tg3_close,
14323 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14324 .ndo_get_stats = tg3_get_stats,
14325 .ndo_validate_addr = eth_validate_addr,
14326 .ndo_set_multicast_list = tg3_set_rx_mode,
14327 .ndo_set_mac_address = tg3_set_mac_addr,
14328 .ndo_do_ioctl = tg3_ioctl,
14329 .ndo_tx_timeout = tg3_tx_timeout,
14330 .ndo_change_mtu = tg3_change_mtu,
14331#if TG3_VLAN_TAG_USED
14332 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14333#endif
14334#ifdef CONFIG_NET_POLL_CONTROLLER
14335 .ndo_poll_controller = tg3_poll_controller,
14336#endif
14337};
14338
1da177e4
LT		 14339static int __devinit tg3_init_one(struct pci_dev *pdev,
14340 const struct pci_device_id *ent)
14341{
14342 static int tg3_version_printed = 0;
1da177e4
LT		 14343 struct net_device *dev;
14344 struct tg3 *tp;
646c9edd
MC		 14345 int i, err, pm_cap;
14346 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14347 char str[40];
72f2afb8 14348 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14349
14350 if (tg3_version_printed++ == 0)
14351 printk(KERN_INFO "%s", version);
14352
14353 err = pci_enable_device(pdev);
14354 if (err) {
14355 printk(KERN_ERR PFX "Cannot enable PCI device, "
14356 "aborting.\n");
14357 return err;
14358 }
14359
1da177e4
LT		 14360 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14361 if (err) {
14362 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14363 "aborting.\n");
14364 goto err_out_disable_pdev;
14365 }
14366
14367 pci_set_master(pdev);
14368
14369 /* Find power-management capability. */
14370 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14371 if (pm_cap == 0) {
14372 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14373 "aborting.\n");
14374 err = -EIO;
14375 goto err_out_free_res;
14376 }
14377
fe5f5787 14378 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14379 if (!dev) {
14380 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14381 err = -ENOMEM;
14382 goto err_out_free_res;
14383 }
14384
1da177e4
LT		 14385 SET_NETDEV_DEV(dev, &pdev->dev);
14386
1da177e4
LT		 14387#if TG3_VLAN_TAG_USED
14388 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14389#endif
14390
14391 tp = netdev_priv(dev);
14392 tp->pdev = pdev;
14393 tp->dev = dev;
14394 tp->pm_cap = pm_cap;
1da177e4
LT		 14395 tp->rx_mode = TG3_DEF_RX_MODE;
14396 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14397
1da177e4
LT		 14398 if (tg3_debug > 0)
14399 tp->msg_enable = tg3_debug;
14400 else
14401 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14402
14403 /* The word/byte swap controls here control register access byte
14404 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14405 * setting below.
14406 */
14407 tp->misc_host_ctrl =
14408 MISC_HOST_CTRL_MASK_PCI_INT |
14409 MISC_HOST_CTRL_WORD_SWAP |
14410 MISC_HOST_CTRL_INDIR_ACCESS |
14411 MISC_HOST_CTRL_PCISTATE_RW;
14412
14413 /* The NONFRM (non-frame) byte/word swap controls take effect
14414 * on descriptor entries, anything which isn't packet data.
14415 *
14416 * The StrongARM chips on the board (one for tx, one for rx)
14417 * are running in big-endian mode.
14418 */
14419 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14420 GRC_MODE_WSWAP_NONFRM_DATA);
14421#ifdef __BIG_ENDIAN
14422 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14423#endif
14424 spin_lock_init(&tp->lock);
1da177e4 14425 spin_lock_init(&tp->indirect_lock);
c4028958 14426 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14427
d5fe488a 14428 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14429 if (!tp->regs) {
1da177e4
LT		 14430 printk(KERN_ERR PFX "Cannot map device registers, "
14431 "aborting.\n");
14432 err = -ENOMEM;
14433 goto err_out_free_dev;
14434 }
14435
14436 tg3_init_link_config(tp);
14437
1da177e4
LT		 14438 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14439 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14440
1da177e4 14441 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14442 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14443 dev->irq = pdev->irq;
1da177e4
LT		 14444
14445 err = tg3_get_invariants(tp);
14446 if (err) {
14447 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14448 "aborting.\n");
14449 goto err_out_iounmap;
14450 }
14451
615774fe
MC		 14452 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14453 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14454 dev->netdev_ops = &tg3_netdev_ops;
14455 else
14456 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14457
14458
4a29cc2e
MC		 14459 /* The EPB bridge inside 5714, 5715, and 5780 and any
14460 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14461 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14462 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14463 * do DMA address check in tg3_start_xmit().
14464 */
4a29cc2e 14465 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14466 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14467 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14468 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14469#ifdef CONFIG_HIGHMEM
6a35528a 14470 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14471#endif
4a29cc2e 14472 } else
6a35528a 14473 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14474
14475 /* Configure DMA attributes. */
284901a9 14476 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14477 err = pci_set_dma_mask(pdev, dma_mask);
14478 if (!err) {
14479 dev->features |= NETIF_F_HIGHDMA;
14480 err = pci_set_consistent_dma_mask(pdev,
14481 persist_dma_mask);
14482 if (err < 0) {
14483 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14484 "DMA for consistent allocations\n");
14485 goto err_out_iounmap;
14486 }
14487 }
14488 }
284901a9
YH		 14489 if (err || dma_mask == DMA_BIT_MASK(32)) {
14490 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14491 if (err) {
14492 printk(KERN_ERR PFX "No usable DMA configuration, "
14493 "aborting.\n");
14494 goto err_out_iounmap;
14495 }
14496 }
14497
fdfec172 14498 tg3_init_bufmgr_config(tp);
1da177e4 14499
507399f1
MC		 14500 /* Selectively allow TSO based on operating conditions */
14501 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14502 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14503 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14504 else {
14505 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14506 tp->fw_needed = NULL;
1da177e4 14507 }
507399f1
MC		 14508
14509 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14510 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14511
4e3a7aaa
MC		 14512 /* TSO is on by default on chips that support hardware TSO.
14513 * Firmware TSO on older chips gives lower performance, so it
14514 * is off by default, but can be enabled using ethtool.
14515 */
e849cdc3
MC		 14516 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14517 (dev->features & NETIF_F_IP_CSUM))
14518 dev->features |= NETIF_F_TSO;
14519
14520 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14521 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14522 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14523 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14524 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14526 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14527 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14529 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14530 dev->features |= NETIF_F_TSO_ECN;
b0026624 14531 }
1da177e4 14532
1da177e4
LT		 14533 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14534 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14535 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14536 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14537 tp->rx_pending = 63;
14538 }
14539
1da177e4
LT		 14540 err = tg3_get_device_address(tp);
14541 if (err) {
14542 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14543 "aborting.\n");
026a6c21 14544 goto err_out_iounmap;
1da177e4
LT		 14545 }
14546
c88864df 14547 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14548 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14549 if (!tp->aperegs) {
c88864df
MC		 14550 printk(KERN_ERR PFX "Cannot map APE registers, "
14551 "aborting.\n");
14552 err = -ENOMEM;
026a6c21 14553 goto err_out_iounmap;
c88864df
MC		 14554 }
14555
14556 tg3_ape_lock_init(tp);
7fd76445
MC		 14557
14558 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14559 tg3_read_dash_ver(tp);
c88864df
MC		 14560 }
14561
1da177e4
LT		 14562 /*
14563 * Reset chip in case UNDI or EFI driver did not shutdown
14564 * DMA self test will enable WDMAC and we'll see (spurious)
14565 * pending DMA on the PCI bus at that point.
14566 */
14567 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14568 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14569 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14570 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14571 }
14572
14573 err = tg3_test_dma(tp);
14574 if (err) {
14575 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14576 goto err_out_apeunmap;
1da177e4
LT		 14577 }
14578
1da177e4
LT		 14579 /* flow control autonegotiation is default behavior */
14580 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14581 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14582
78f90dcf
MC		 14583 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14584 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14585 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14586 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14587 struct tg3_napi *tnapi = &tp->napi[i];
14588
14589 tnapi->tp = tp;
14590 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14591
14592 tnapi->int_mbox = intmbx;
14593 if (i < 4)
14594 intmbx += 0x8;
14595 else
14596 intmbx += 0x4;
14597
14598 tnapi->consmbox = rcvmbx;
14599 tnapi->prodmbox = sndmbx;
14600
14601 if (i) {
14602 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14603 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14604 } else {
14605 tnapi->coal_now = HOSTCC_MODE_NOW;
14606 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14607 }
14608
14609 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14610 break;
14611
14612 /*
14613 * If we support MSIX, we'll be using RSS. If we're using
14614 * RSS, the first vector only handles link interrupts and the
14615 * remaining vectors handle rx and tx interrupts. Reuse the
14616 * mailbox values for the next iteration. The values we setup
14617 * above are still useful for the single vectored mode.
14618 */
14619 if (!i)
14620 continue;
14621
14622 rcvmbx += 0x8;
14623
14624 if (sndmbx & 0x4)
14625 sndmbx -= 0x4;
14626 else
14627 sndmbx += 0xc;
14628 }
14629
15f9850d
DM		 14630 tg3_init_coal(tp);
14631
c49a1561
MC		 14632 pci_set_drvdata(pdev, dev);
14633
1da177e4
LT		 14634 err = register_netdev(dev);
14635 if (err) {
14636 printk(KERN_ERR PFX "Cannot register net device, "
14637 "aborting.\n");
0d3031d9 14638 goto err_out_apeunmap;
1da177e4
LT		 14639 }
14640
df59c940 14641 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14642 dev->name,
14643 tp->board_part_number,
14644 tp->pci_chip_rev_id,
f9804ddb 14645 tg3_bus_string(tp, str),
e174961c 14646 dev->dev_addr);
1da177e4 14647
3f0e3ad7
MC		 14648 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14649 struct phy_device *phydev;
14650 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14651 printk(KERN_INFO
14652 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14653 tp->dev->name, phydev->drv->name,
14654 dev_name(&phydev->dev));
14655 } else
df59c940
MC		 14656 printk(KERN_INFO
14657 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14658 tp->dev->name, tg3_phy_string(tp),
14659 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14660 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14661 "10/100/1000Base-T")),
14662 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14663
14664 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14665 dev->name,
14666 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14667 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14668 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14669 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14670 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14671 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14672 dev->name, tp->dma_rwctrl,
284901a9 14673 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14674 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14675
14676 return 0;
14677
0d3031d9
MC		 14678err_out_apeunmap:
14679 if (tp->aperegs) {
14680 iounmap(tp->aperegs);
14681 tp->aperegs = NULL;
14682 }
14683
1da177e4 14684err_out_iounmap:
6892914f
MC		 14685 if (tp->regs) {
14686 iounmap(tp->regs);
22abe310 14687 tp->regs = NULL;
6892914f 14688 }
1da177e4
LT		 14689
14690err_out_free_dev:
14691 free_netdev(dev);
14692
14693err_out_free_res:
14694 pci_release_regions(pdev);
14695
14696err_out_disable_pdev:
14697 pci_disable_device(pdev);
14698 pci_set_drvdata(pdev, NULL);
14699 return err;
14700}
14701
14702static void __devexit tg3_remove_one(struct pci_dev *pdev)
14703{
14704 struct net_device *dev = pci_get_drvdata(pdev);
14705
14706 if (dev) {
14707 struct tg3 *tp = netdev_priv(dev);
14708
077f849d
JSR		 14709 if (tp->fw)
14710 release_firmware(tp->fw);
14711
7faa006f 14712 flush_scheduled_work();
158d7abd 14713
b02fd9e3
MC		 14714 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14715 tg3_phy_fini(tp);
158d7abd 14716 tg3_mdio_fini(tp);
b02fd9e3 14717 }
158d7abd 14718
1da177e4 14719 unregister_netdev(dev);
0d3031d9
MC		 14720 if (tp->aperegs) {
14721 iounmap(tp->aperegs);
14722 tp->aperegs = NULL;
14723 }
6892914f
MC		 14724 if (tp->regs) {
14725 iounmap(tp->regs);
22abe310 14726 tp->regs = NULL;
6892914f 14727 }
1da177e4
LT		 14728 free_netdev(dev);
14729 pci_release_regions(pdev);
14730 pci_disable_device(pdev);
14731 pci_set_drvdata(pdev, NULL);
14732 }
14733}
14734
14735static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14736{
14737 struct net_device *dev = pci_get_drvdata(pdev);
14738 struct tg3 *tp = netdev_priv(dev);
12dac075 14739 pci_power_t target_state;
1da177e4
LT		 14740 int err;
14741
3e0c95fd
MC		 14742 /* PCI register 4 needs to be saved whether netif_running() or not.
14743 * MSI address and data need to be saved if using MSI and
14744 * netif_running().
14745 */
14746 pci_save_state(pdev);
14747
1da177e4
LT		 14748 if (!netif_running(dev))
14749 return 0;
14750
7faa006f 14751 flush_scheduled_work();
b02fd9e3 14752 tg3_phy_stop(tp);
1da177e4
LT		 14753 tg3_netif_stop(tp);
14754
14755 del_timer_sync(&tp->timer);
14756
f47c11ee 14757 tg3_full_lock(tp, 1);
1da177e4 14758 tg3_disable_ints(tp);
f47c11ee 14759 tg3_full_unlock(tp);
1da177e4
LT		 14760
14761 netif_device_detach(dev);
14762
f47c11ee 14763 tg3_full_lock(tp, 0);
944d980e 14764 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14765 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14766 tg3_full_unlock(tp);
1da177e4 14767
12dac075
RW		 14768 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14769
14770 err = tg3_set_power_state(tp, target_state);
1da177e4 14771 if (err) {
b02fd9e3
MC		 14772 int err2;
14773
f47c11ee 14774 tg3_full_lock(tp, 0);
1da177e4 14775
6a9eba15 14776 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14777 err2 = tg3_restart_hw(tp, 1);
14778 if (err2)
b9ec6c1b 14779 goto out;
1da177e4
LT		 14780
14781 tp->timer.expires = jiffies + tp->timer_offset;
14782 add_timer(&tp->timer);
14783
14784 netif_device_attach(dev);
14785 tg3_netif_start(tp);
14786
b9ec6c1b 14787out:
f47c11ee 14788 tg3_full_unlock(tp);
b02fd9e3
MC		 14789
14790 if (!err2)
14791 tg3_phy_start(tp);
1da177e4
LT		 14792 }
14793
14794 return err;
14795}
14796
14797static int tg3_resume(struct pci_dev *pdev)
14798{
14799 struct net_device *dev = pci_get_drvdata(pdev);
14800 struct tg3 *tp = netdev_priv(dev);
14801 int err;
14802
3e0c95fd
MC		 14803 pci_restore_state(tp->pdev);
14804
1da177e4
LT		 14805 if (!netif_running(dev))
14806 return 0;
14807
bc1c7567 14808 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14809 if (err)
14810 return err;
14811
14812 netif_device_attach(dev);
14813
f47c11ee 14814 tg3_full_lock(tp, 0);
1da177e4 14815
6a9eba15 14816 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14817 err = tg3_restart_hw(tp, 1);
14818 if (err)
14819 goto out;
1da177e4
LT		 14820
14821 tp->timer.expires = jiffies + tp->timer_offset;
14822 add_timer(&tp->timer);
14823
1da177e4
LT		 14824 tg3_netif_start(tp);
14825
b9ec6c1b 14826out:
f47c11ee 14827 tg3_full_unlock(tp);
1da177e4 14828
b02fd9e3
MC		 14829 if (!err)
14830 tg3_phy_start(tp);
14831
b9ec6c1b 14832 return err;
1da177e4
LT		 14833}
14834
14835static struct pci_driver tg3_driver = {
14836 .name = DRV_MODULE_NAME,
14837 .id_table = tg3_pci_tbl,
14838 .probe = tg3_init_one,
14839 .remove = __devexit_p(tg3_remove_one),
14840 .suspend = tg3_suspend,
14841 .resume = tg3_resume
14842};
14843
14844static int __init tg3_init(void)
14845{
29917620 14846 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14847}
14848
14849static void __exit tg3_cleanup(void)
14850{
14851 pci_unregister_driver(&tg3_driver);
14852}
14853
14854module_init(tg3_init);
14855module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree