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tg3: Enable PLL PD when CLKREQ disabled for 5717A0
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
cceea982
MC		 71#define DRV_MODULE_VERSION "3.105"
72#define DRV_MODULE_RELDATE "December 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
13185217
HK		 247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254 {}
1da177e4
LT		 255};
256
257MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
50da859d 259static const struct {
1da177e4
LT		 260 const char string[ETH_GSTRING_LEN];
261} ethtool_stats_keys[TG3_NUM_STATS] = {
262 { "rx_octets" },
263 { "rx_fragments" },
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
267 { "rx_fcs_errors" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
274 { "rx_jabbers" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
288
289 { "tx_octets" },
290 { "tx_collisions" },
291
292 { "tx_xon_sent" },
293 { "tx_xoff_sent" },
294 { "tx_flow_control" },
295 { "tx_mac_errors" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
298 { "tx_deferred" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
319 { "tx_discards" },
320 { "tx_errors" },
321
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
324 { "rxbds_empty" },
325 { "rx_discards" },
326 { "rx_errors" },
327 { "rx_threshold_hit" },
328
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
332
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
335 { "nic_irqs" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
338};
339
50da859d 340static const struct {
4cafd3f5
MC		 341 const char string[ETH_GSTRING_LEN];
342} ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
349};
350
b401e9e2
MC		 351static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354}
355
356static u32 tg3_read32(struct tg3 *tp, u32 off)
357{
6aa20a22 358 return (readl(tp->regs + off));
b401e9e2
MC		 359}
360
0d3031d9
MC		 361static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->aperegs + off);
364}
365
366static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367{
368 return (readl(tp->aperegs + off));
369}
370
1da177e4
LT		 371static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372{
6892914f
MC		 373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 379}
380
381static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382{
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
1da177e4
LT		 385}
386
6892914f 387static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 388{
6892914f
MC		 389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
399static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
66711e66 408 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
1da177e4 412 }
6892914f
MC		 413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427}
428
429static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430{
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439}
440
b401e9e2
MC		 441/* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 447{
b401e9e2
MC		 448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
1da177e4
LT		 464}
465
09ee929c
MC		 466static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467{
468 tp->write32_mbox(tp, off, val);
6892914f
MC		 469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
09ee929c
MC		 472}
473
20094930 474static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 475{
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482}
483
b5d3772c
MC		 484static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485{
486 return (readl(tp->regs + off + GRCMBOX_BASE));
487}
488
489static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off + GRCMBOX_BASE);
492}
493
20094930 494#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 495#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 496#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 498#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 499
500#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 501#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 503#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 504
505static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506{
6892914f
MC		 507 unsigned long flags;
508
b5d3772c
MC		 509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511 return;
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 528}
529
1da177e4
LT		 530static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536 *val = 0;
537 return;
538 }
539
6892914f 540 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 544
bbadf503
MC		 545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 } else {
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 }
6892914f 554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 555}
556
0d3031d9
MC		 557static void tg3_ape_lock_init(struct tg3 *tp)
558{
559 int i;
560
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
565}
566
567static int tg3_ape_lock(struct tg3 *tp, int locknum)
568{
569 int i, off;
570 int ret = 0;
571 u32 status;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return 0;
575
576 switch (locknum) {
77b483f1 577 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 off = 4 * locknum;
585
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
592 break;
593 udelay(10);
594 }
595
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
600
601 ret = -EBUSY;
602 }
603
604 return ret;
605}
606
607static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608{
609 int off;
610
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612 return;
613
614 switch (locknum) {
77b483f1 615 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 616 case TG3_APE_LOCK_MEM:
617 break;
618 default:
619 return;
620 }
621
622 off = 4 * locknum;
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624}
625
1da177e4
LT		 626static void tg3_disable_ints(struct tg3 *tp)
627{
89aeb3bc
MC		 628 int i;
629
1da177e4
LT		 630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 634}
635
1da177e4
LT		 636static void tg3_enable_ints(struct tg3 *tp)
637{
89aeb3bc
MC		 638 int i;
639 u32 coal_now = 0;
640
bbe832c0
MC		 641 tp->irq_sync = 0;
642 wmb();
643
1da177e4
LT		 644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 646
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 652
89aeb3bc
MC		 653 coal_now |= tnapi->coal_now;
654 }
f19af9c2
MC		 655
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660 else
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 663}
664
17375d25 665static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 666{
17375d25 667 struct tg3 *tp = tnapi->tp;
898a56f8 668 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 669 unsigned int work_exists = 0;
670
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
676 work_exists = 1;
677 }
678 /* check for RX/TX work to do */
f3f3f27e 679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 681 work_exists = 1;
682
683 return work_exists;
684}
685
17375d25 686/* tg3_int_reenable
04237ddd
MC		 687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
6aa20a22 689 * which reenables interrupts
1da177e4 690 */
17375d25 691static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 692{
17375d25
MC		 693 struct tg3 *tp = tnapi->tp;
694
898a56f8 695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 696 mmiowb();
697
fac9b83e
DM		 698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
701 */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 703 tg3_has_work(tnapi))
04237ddd 704 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 706}
707
fed97810
MC		 708static void tg3_napi_disable(struct tg3 *tp)
709{
710 int i;
711
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
714}
715
716static void tg3_napi_enable(struct tg3 *tp)
717{
718 int i;
719
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
722}
723
1da177e4
LT		 724static inline void tg3_netif_stop(struct tg3 *tp)
725{
bbe832c0 726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 727 tg3_napi_disable(tp);
1da177e4
LT		 728 netif_tx_disable(tp->dev);
729}
730
731static inline void tg3_netif_start(struct tg3 *tp)
732{
fe5f5787
MC		 733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
1da177e4 736 */
fe5f5787
MC		 737 netif_tx_wake_all_queues(tp->dev);
738
fed97810
MC		 739 tg3_napi_enable(tp);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 741 tg3_enable_ints(tp);
1da177e4
LT		 742}
743
744static void tg3_switch_clocks(struct tg3 *tp)
745{
f6eb9b1f 746 u32 clock_ctrl;
1da177e4
LT		 747 u32 orig_clock_ctrl;
748
795d01c5
MC		 749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 751 return;
752
f6eb9b1f
MC		 753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
1da177e4
LT		 755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
758 0x1f);
759 tp->pci_clock_ctrl = clock_ctrl;
760
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 765 }
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl |
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770 40);
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
773 40);
1da177e4 774 }
b401e9e2 775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 776}
777
778#define PHY_BUSY_LOOPS 5000
779
780static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781{
782 u32 frame_val;
783 unsigned int loops;
784 int ret;
785
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787 tw32_f(MAC_MI_MODE,
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789 udelay(80);
790 }
791
792 *val = 0x0;
793
882e9793 794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 799
1da177e4
LT		 800 tw32_f(MAC_MI_COM, frame_val);
801
802 loops = PHY_BUSY_LOOPS;
803 while (loops != 0) {
804 udelay(10);
805 frame_val = tr32(MAC_MI_COM);
806
807 if ((frame_val & MI_COM_BUSY) == 0) {
808 udelay(5);
809 frame_val = tr32(MAC_MI_COM);
810 break;
811 }
812 loops -= 1;
813 }
814
815 ret = -EBUSY;
816 if (loops != 0) {
817 *val = frame_val & MI_COM_DATA_MASK;
818 ret = 0;
819 }
820
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
823 udelay(80);
824 }
825
826 return ret;
827}
828
829static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830{
831 u32 frame_val;
832 unsigned int loops;
833 int ret;
834
7f97a4bd 835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837 return 0;
838
1da177e4
LT		 839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840 tw32_f(MAC_MI_MODE,
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842 udelay(80);
843 }
844
882e9793 845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 851
1da177e4
LT		 852 tw32_f(MAC_MI_COM, frame_val);
853
854 loops = PHY_BUSY_LOOPS;
855 while (loops != 0) {
856 udelay(10);
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
859 udelay(5);
860 frame_val = tr32(MAC_MI_COM);
861 break;
862 }
863 loops -= 1;
864 }
865
866 ret = -EBUSY;
867 if (loops != 0)
868 ret = 0;
869
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
872 udelay(80);
873 }
874
875 return ret;
876}
877
95e2869a
MC		 878static int tg3_bmcr_reset(struct tg3 *tp)
879{
880 u32 phy_control;
881 int limit, err;
882
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
885 */
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
888 if (err != 0)
889 return -EBUSY;
890
891 limit = 5000;
892 while (limit--) {
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 if ((phy_control & BMCR_RESET) == 0) {
898 udelay(40);
899 break;
900 }
901 udelay(10);
902 }
d4675b52 903 if (limit < 0)
95e2869a
MC		 904 return -EBUSY;
905
906 return 0;
907}
908
158d7abd
MC		 909static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910{
3d16543d 911 struct tg3 *tp = bp->priv;
158d7abd
MC		 912 u32 val;
913
24bb4fb6 914 spin_lock_bh(&tp->lock);
158d7abd
MC		 915
916 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 917 val = -EIO;
918
919 spin_unlock_bh(&tp->lock);
158d7abd
MC		 920
921 return val;
922}
923
924static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925{
3d16543d 926 struct tg3 *tp = bp->priv;
24bb4fb6 927 u32 ret = 0;
158d7abd 928
24bb4fb6 929 spin_lock_bh(&tp->lock);
158d7abd
MC		 930
931 if (tg3_writephy(tp, reg, val))
24bb4fb6 932 ret = -EIO;
158d7abd 933
24bb4fb6
MC		 934 spin_unlock_bh(&tp->lock);
935
936 return ret;
158d7abd
MC		 937}
938
939static int tg3_mdio_reset(struct mii_bus *bp)
940{
941 return 0;
942}
943
9c61d6bc 944static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 945{
946 u32 val;
fcb389df 947 struct phy_device *phydev;
a9daf367 948
3f0e3ad7 949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
c73430d0 952 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 953 val = MAC_PHYCFG2_50610_LED_MODES;
954 break;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960 break;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963 break;
964 default:
a9daf367 965 return;
fcb389df
MC		 966 }
967
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
970
971 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 975 tw32(MAC_PHYCFG1, val);
976
977 return;
978 }
979
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
987
988 tw32(MAC_PHYCFG2, val);
a9daf367 989
bb85fbb6
MC		 990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998 }
bb85fbb6
MC		 999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
a9daf367 1002
a9daf367
MC		 1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
fcb389df 1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1021 }
1022 tw32(MAC_EXT_RGMII_MODE, val);
1023}
1024
158d7abd
MC		 1025static void tg3_mdio_start(struct tg3 *tp)
1026{
158d7abd
MC		 1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1029 udelay(80);
a9daf367 1030
882e9793
MC		 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1033
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035 if (funcnum)
1036 tp->phy_addr = 2;
1037 else
1038 tp->phy_addr = 1;
1039
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041 if (is_serdes)
1042 tp->phy_addr += 7;
1043 } else
3f0e3ad7 1044 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1045
9c61d6bc
MC		 1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
158d7abd
MC		 1049}
1050
158d7abd
MC		 1051static int tg3_mdio_init(struct tg3 *tp)
1052{
1053 int i;
1054 u32 reg;
a9daf367 1055 struct phy_device *phydev;
158d7abd
MC		 1056
1057 tg3_mdio_start(tp);
1058
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061 return 0;
1062
298cf9be
LB		 1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1065 return -ENOMEM;
158d7abd 1066
298cf9be
LB		 1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1077
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1079 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1080
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1085 */
1086 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087 tg3_bmcr_reset(tp);
1088
298cf9be 1089 i = mdiobus_register(tp->mdio_bus);
a9daf367 1090 if (i) {
158d7abd
MC		 1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092 tp->dev->name, i);
9c61d6bc 1093 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1094 return i;
1095 }
158d7abd 1096
3f0e3ad7 1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1098
9c61d6bc
MC		 1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1103 return -ENODEV;
1104 }
1105
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1110 break;
a9daf367 1111 case TG3_PHY_ID_BCM50610:
c73430d0 1112 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1114 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1123 /* fallthru */
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1126 break;
fcb389df 1127 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1132 break;
1133 }
1134
9c61d6bc
MC		 1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
a9daf367
MC		 1139
1140 return 0;
158d7abd
MC		 1141}
1142
1143static void tg3_mdio_fini(struct tg3 *tp)
1144{
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1149 }
1150}
1151
4ba526ce
MC		 1152/* tp->lock is held. */
1153static inline void tg3_generate_fw_event(struct tg3 *tp)
1154{
1155 u32 val;
1156
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161 tp->last_event_jiffies = jiffies;
1162}
1163
1164#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
95e2869a
MC		 1166/* tp->lock is held. */
1167static void tg3_wait_for_event_ack(struct tg3 *tp)
1168{
1169 int i;
4ba526ce
MC		 1170 unsigned int delay_cnt;
1171 long time_remain;
1172
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176 (long)jiffies;
1177 if (time_remain < 0)
1178 return;
1179
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1185
4ba526ce 1186 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188 break;
4ba526ce 1189 udelay(8);
95e2869a
MC		 1190 }
1191}
1192
1193/* tp->lock is held. */
1194static void tg3_ump_link_report(struct tg3 *tp)
1195{
1196 u32 reg;
1197 u32 val;
1198
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1201 return;
1202
1203 tg3_wait_for_event_ack(tp);
1204
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209 val = 0;
1210 if (!tg3_readphy(tp, MII_BMCR, &reg))
1211 val = reg << 16;
1212 if (!tg3_readphy(tp, MII_BMSR, &reg))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216 val = 0;
1217 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218 val = reg << 16;
1219 if (!tg3_readphy(tp, MII_LPA, &reg))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223 val = 0;
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226 val = reg << 16;
1227 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228 val |= (reg & 0xffff);
1229 }
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233 val = reg << 16;
1234 else
1235 val = 0;
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
4ba526ce 1238 tg3_generate_fw_event(tp);
95e2869a
MC		 1239}
1240
1241static void tg3_link_report(struct tg3 *tp)
1242{
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1246 tp->dev->name);
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250 tp->dev->name,
1251 (tp->link_config.active_speed == SPEED_1000 ?
1252 1000 :
1253 (tp->link_config.active_speed == SPEED_100 ?
1254 100 : 10)),
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1256 "full" : "half"));
1257
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1260 tp->dev->name,
e18ce346 1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1262 "on" : "off",
e18ce346 1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1264 "on" : "off");
1265 tg3_ump_link_report(tp);
1266 }
1267}
1268
1269static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270{
1271 u16 miireg;
1272
e18ce346 1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1274 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1275 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1276 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1277 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279 else
1280 miireg = 0;
1281
1282 return miireg;
1283}
1284
1285static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286{
1287 u16 miireg;
1288
e18ce346 1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1290 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1291 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1292 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1293 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295 else
1296 miireg = 0;
1297
1298 return miireg;
1299}
1300
95e2869a
MC		 1301static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302{
1303 u8 cap = 0;
1304
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1310 cap = FLOW_CTRL_RX;
95e2869a
MC		 1311 } else {
1312 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1314 }
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1317 cap = FLOW_CTRL_TX;
95e2869a
MC		 1318 }
1319
1320 return cap;
1321}
1322
f51f3562 1323static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1324{
b02fd9e3 1325 u8 autoneg;
f51f3562 1326 u8 flowctrl = 0;
95e2869a
MC		 1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1329
b02fd9e3 1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1332 else
1333 autoneg = tp->link_config.autoneg;
1334
1335 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1339 else
bc02ff95 1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1341 } else
1342 flowctrl = tp->link_config.flowctrl;
95e2869a 1343
f51f3562 1344 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1345
e18ce346 1346 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348 else
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
f51f3562 1351 if (old_rx_mode != tp->rx_mode)
95e2869a 1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1353
e18ce346 1354 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356 else
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
f51f3562 1359 if (old_tx_mode != tp->tx_mode)
95e2869a 1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1361}
1362
b02fd9e3
MC		 1363static void tg3_adjust_link(struct net_device *dev)
1364{
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1369
24bb4fb6 1370 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1371
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1374
1375 oldflowctrl = tp->link_config.active_flowctrl;
1376
1377 if (phydev->link) {
1378 lcl_adv = 0;
1379 rmt_adv = 0;
1380
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1386 else
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1388
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1391 else {
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1394
1395 if (phydev->pause)
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1399 }
1400
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402 } else
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1408 udelay(40);
1409 }
1410
fcb389df
MC		 1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1413 tw32(MAC_MI_STAT,
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416 else
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418 }
1419
b02fd9e3
MC		 1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425 else
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1436 linkmesg = 1;
1437
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1440
24bb4fb6 1441 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1442
1443 if (linkmesg)
1444 tg3_link_report(tp);
1445}
1446
1447static int tg3_phy_init(struct tg3 *tp)
1448{
1449 struct phy_device *phydev;
1450
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452 return 0;
1453
1454 /* Bring the PHY back to a known state. */
1455 tg3_bmcr_reset(tp);
1456
3f0e3ad7 1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1458
1459 /* Attach the MAC to the PHY. */
fb28ad35 1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1461 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1465 }
1466
b02fd9e3 1467 /* Mask with MAC supported features. */
9c61d6bc
MC		 1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1473 SUPPORTED_Pause |
1474 SUPPORTED_Asym_Pause);
1475 break;
1476 }
1477 /* fallthru */
9c61d6bc
MC		 1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 default:
3f0e3ad7 1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1485 return -EINVAL;
1486 }
1487
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1489
1490 phydev->advertising = phydev->supported;
1491
b02fd9e3
MC		 1492 return 0;
1493}
1494
1495static void tg3_phy_start(struct tg3 *tp)
1496{
1497 struct phy_device *phydev;
1498
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1503
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1510 }
1511
1512 phy_start(phydev);
1513
1514 phy_start_aneg(phydev);
1515}
1516
1517static void tg3_phy_stop(struct tg3 *tp)
1518{
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520 return;
1521
3f0e3ad7 1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1523}
1524
1525static void tg3_phy_fini(struct tg3 *tp)
1526{
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530 }
1531}
1532
b2a5c19c
MC		 1533static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534{
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537}
1538
7f97a4bd
MC		 1539static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 phytest;
1542
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544 u32 phy;
1545
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549 if (enable)
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551 else
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554 }
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556 }
1557}
1558
6833c043
MC		 1559static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560{
1561 u32 reg;
1562
7f97a4bd 1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1564 return;
1565
7f97a4bd
MC		 1566 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567 tg3_phy_fet_toggle_apd(tp, enable);
1568 return;
1569 }
1570
6833c043
MC		 1571 reg = MII_TG3_MISC_SHDW_WREN |
1572 MII_TG3_MISC_SHDW_SCR5_SEL |
1573 MII_TG3_MISC_SHDW_SCR5_LPED |
1574 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575 MII_TG3_MISC_SHDW_SCR5_SDTL |
1576 MII_TG3_MISC_SHDW_SCR5_C125OE;
1577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1579
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581
1582
1583 reg = MII_TG3_MISC_SHDW_WREN |
1584 MII_TG3_MISC_SHDW_APD_SEL |
1585 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1586 if (enable)
1587 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1588
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590}
1591
9ef8ca99
MC		 1592static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1593{
1594 u32 phy;
1595
1596 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1598 return;
1599
7f97a4bd 1600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1601 u32 ephy;
1602
535ef6e1
MC		 1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1605
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 ephy | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1609 if (enable)
535ef6e1 1610 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1611 else
535ef6e1
MC		 1612 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613 tg3_writephy(tp, reg, phy);
9ef8ca99 1614 }
535ef6e1 1615 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1616 }
1617 } else {
1618 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619 MII_TG3_AUXCTL_SHDWSEL_MISC;
1620 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1622 if (enable)
1623 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1624 else
1625 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 phy |= MII_TG3_AUXCTL_MISC_WREN;
1627 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1628 }
1629 }
1630}
1631
1da177e4
LT		 1632static void tg3_phy_set_wirespeed(struct tg3 *tp)
1633{
1634 u32 val;
1635
1636 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1637 return;
1638
1639 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642 (val | (1 << 15) | (1 << 4)));
1643}
1644
b2a5c19c
MC		 1645static void tg3_phy_apply_otp(struct tg3 *tp)
1646{
1647 u32 otp, phy;
1648
1649 if (!tp->phy_otp)
1650 return;
1651
1652 otp = tp->phy_otp;
1653
1654 /* Enable SM_DSP clock and tx 6dB coding. */
1655 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657 MII_TG3_AUXCTL_ACTL_TX_6DB;
1658 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659
1660 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1663
1664 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1667
1668 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1671
1672 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1674
1675 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1677
1678 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1681
1682 /* Turn off SM_DSP clock. */
1683 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686}
1687
1da177e4
LT		 1688static int tg3_wait_macro_done(struct tg3 *tp)
1689{
1690 int limit = 100;
1691
1692 while (limit--) {
1693 u32 tmp32;
1694
1695 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696 if ((tmp32 & 0x1000) == 0)
1697 break;
1698 }
1699 }
d4675b52 1700 if (limit < 0)
1da177e4
LT		 1701 return -EBUSY;
1702
1703 return 0;
1704}
1705
1706static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1707{
1708 static const u32 test_pat[4][6] = {
1709 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1713 };
1714 int chan;
1715
1716 for (chan = 0; chan < 4; chan++) {
1717 int i;
1718
1719 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720 (chan * 0x2000) | 0x0200);
1721 tg3_writephy(tp, 0x16, 0x0002);
1722
1723 for (i = 0; i < 6; i++)
1724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1725 test_pat[chan][i]);
1726
1727 tg3_writephy(tp, 0x16, 0x0202);
1728 if (tg3_wait_macro_done(tp)) {
1729 *resetp = 1;
1730 return -EBUSY;
1731 }
1732
1733 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734 (chan * 0x2000) | 0x0200);
1735 tg3_writephy(tp, 0x16, 0x0082);
1736 if (tg3_wait_macro_done(tp)) {
1737 *resetp = 1;
1738 return -EBUSY;
1739 }
1740
1741 tg3_writephy(tp, 0x16, 0x0802);
1742 if (tg3_wait_macro_done(tp)) {
1743 *resetp = 1;
1744 return -EBUSY;
1745 }
1746
1747 for (i = 0; i < 6; i += 2) {
1748 u32 low, high;
1749
1750 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752 tg3_wait_macro_done(tp)) {
1753 *resetp = 1;
1754 return -EBUSY;
1755 }
1756 low &= 0x7fff;
1757 high &= 0x000f;
1758 if (low != test_pat[chan][i] ||
1759 high != test_pat[chan][i+1]) {
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1763
1764 return -EBUSY;
1765 }
1766 }
1767 }
1768
1769 return 0;
1770}
1771
1772static int tg3_phy_reset_chanpat(struct tg3 *tp)
1773{
1774 int chan;
1775
1776 for (chan = 0; chan < 4; chan++) {
1777 int i;
1778
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780 (chan * 0x2000) | 0x0200);
1781 tg3_writephy(tp, 0x16, 0x0002);
1782 for (i = 0; i < 6; i++)
1783 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784 tg3_writephy(tp, 0x16, 0x0202);
1785 if (tg3_wait_macro_done(tp))
1786 return -EBUSY;
1787 }
1788
1789 return 0;
1790}
1791
1792static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1793{
1794 u32 reg32, phy9_orig;
1795 int retries, do_phy_reset, err;
1796
1797 retries = 10;
1798 do_phy_reset = 1;
1799 do {
1800 if (do_phy_reset) {
1801 err = tg3_bmcr_reset(tp);
1802 if (err)
1803 return err;
1804 do_phy_reset = 0;
1805 }
1806
1807 /* Disable transmitter and interrupt. */
1808 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1809 continue;
1810
1811 reg32 |= 0x3000;
1812 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1813
1814 /* Set full-duplex, 1000 mbps. */
1815 tg3_writephy(tp, MII_BMCR,
1816 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1817
1818 /* Set to master mode. */
1819 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1820 continue;
1821
1822 tg3_writephy(tp, MII_TG3_CTRL,
1823 (MII_TG3_CTRL_AS_MASTER |
1824 MII_TG3_CTRL_ENABLE_AS_MASTER));
1825
1826 /* Enable SM_DSP_CLOCK and 6dB. */
1827 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1828
1829 /* Block the PHY control access. */
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1832
1833 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1834 if (!err)
1835 break;
1836 } while (--retries);
1837
1838 err = tg3_phy_reset_chanpat(tp);
1839 if (err)
1840 return err;
1841
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1844
1845 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846 tg3_writephy(tp, 0x16, 0x0000);
1847
1848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850 /* Set Extended packet length bit for jumbo frames */
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1852 }
1853 else {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1855 }
1856
1857 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1858
1859 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1860 reg32 &= ~0x3000;
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1862 } else if (!err)
1863 err = -EBUSY;
1864
1865 return err;
1866}
1867
1868/* This will reset the tigon3 PHY if there is no valid
1869 * link unless the FORCE argument is non-zero.
1870 */
1871static int tg3_phy_reset(struct tg3 *tp)
1872{
b2a5c19c 1873 u32 cpmuctrl;
1da177e4
LT		 1874 u32 phy_status;
1875 int err;
1876
60189ddf
MC		 1877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1878 u32 val;
1879
1880 val = tr32(GRC_MISC_CFG);
1881 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1882 udelay(40);
1883 }
1da177e4
LT		 1884 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1885 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1886 if (err != 0)
1887 return -EBUSY;
1888
c8e1e82b
MC		 1889 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890 netif_carrier_off(tp->dev);
1891 tg3_link_report(tp);
1892 }
1893
1da177e4
LT		 1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897 err = tg3_phy_reset_5703_4_5(tp);
1898 if (err)
1899 return err;
1900 goto out;
1901 }
1902
b2a5c19c
MC		 1903 cpmuctrl = 0;
1904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1908 tw32(TG3_CPMU_CTRL,
1909 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1910 }
1911
1da177e4
LT		 1912 err = tg3_bmcr_reset(tp);
1913 if (err)
1914 return err;
1915
b2a5c19c
MC		 1916 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1917 u32 phy;
1918
1919 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1921
1922 tw32(TG3_CPMU_CTRL, cpmuctrl);
1923 }
1924
bcb37f6c
MC		 1925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1927 u32 val;
1928
1929 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931 CPMU_LSPD_1000MB_MACCLK_12_5) {
1932 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1933 udelay(40);
1934 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1935 }
1936 }
1937
b2a5c19c
MC		 1938 tg3_phy_apply_otp(tp);
1939
6833c043
MC		 1940 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941 tg3_phy_toggle_apd(tp, true);
1942 else
1943 tg3_phy_toggle_apd(tp, false);
1944
1da177e4
LT		 1945out:
1946 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953 }
1954 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955 tg3_writephy(tp, 0x1c, 0x8d68);
1956 tg3_writephy(tp, 0x1c, 0x8d68);
1957 }
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1967 }
c424cb24
MC		 1968 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973 tg3_writephy(tp, MII_TG3_TEST1,
1974 MII_TG3_TEST1_TRIM_EN | 0x4);
1975 } else
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1978 }
1da177e4
LT		 1979 /* Set Extended packet length bit (bit 14) on all chips that */
1980 /* support jumbo frames */
1981 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982 /* Cannot do read-modify-write on 5401 */
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1984 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1985 u32 phy_reg;
1986
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1991 }
1992
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1995 */
8f666b07 1996 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1997 u32 phy_reg;
1998
1999 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002 }
2003
715116a1 2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2005 /* adjust output voltage */
535ef6e1 2006 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2007 }
2008
9ef8ca99 2009 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2010 tg3_phy_set_wirespeed(tp);
2011 return 0;
2012}
2013
2014static void tg3_frob_aux_power(struct tg3 *tp)
2015{
2016 struct tg3 *tp_peer = tp;
2017
9d26e213 2018 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2019 return;
2020
f6eb9b1f
MC		 2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2024 struct net_device *dev_peer;
2025
2026 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2027 /* remove_one() may have been run on the peer. */
8c2dc7e1 2028 if (!dev_peer)
bc1c7567
MC		 2029 tp_peer = tp;
2030 else
2031 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2032 }
2033
1da177e4 2034 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2035 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 (GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1),
2046 100);
8d519ab2
MC		 2047 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2049 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051 GRC_LCLCTRL_GPIO_OE1 |
2052 GRC_LCLCTRL_GPIO_OE2 |
2053 GRC_LCLCTRL_GPIO_OUTPUT0 |
2054 GRC_LCLCTRL_GPIO_OUTPUT1 |
2055 tp->grc_local_ctrl;
2056 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060
2061 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2063 } else {
2064 u32 no_gpio2;
dc56b7d4 2065 u32 grc_local_ctrl = 0;
1da177e4
LT		 2066
2067 if (tp_peer != tp &&
2068 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2069 return;
2070
dc56b7d4
MC		 2071 /* Workaround to prevent overdrawing Amps. */
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2073 ASIC_REV_5714) {
2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2075 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076 grc_local_ctrl, 100);
dc56b7d4
MC		 2077 }
2078
1da177e4
LT		 2079 /* On 5753 and variants, GPIO2 cannot be used. */
2080 no_gpio2 = tp->nic_sram_data_cfg &
2081 NIC_SRAM_DATA_CFG_NO_GPIO2;
2082
dc56b7d4 2083 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2084 GRC_LCLCTRL_GPIO_OE1 |
2085 GRC_LCLCTRL_GPIO_OE2 |
2086 GRC_LCLCTRL_GPIO_OUTPUT1 |
2087 GRC_LCLCTRL_GPIO_OUTPUT2;
2088 if (no_gpio2) {
2089 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090 GRC_LCLCTRL_GPIO_OUTPUT2);
2091 }
b401e9e2
MC		 2092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093 grc_local_ctrl, 100);
1da177e4
LT		 2094
2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2096
b401e9e2
MC		 2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 grc_local_ctrl, 100);
1da177e4
LT		 2099
2100 if (!no_gpio2) {
2101 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2102 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103 grc_local_ctrl, 100);
1da177e4
LT		 2104 }
2105 }
2106 } else {
2107 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109 if (tp_peer != tp &&
2110 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2111 return;
2112
b401e9e2
MC		 2113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114 (GRC_LCLCTRL_GPIO_OE1 |
2115 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2116
b401e9e2
MC		 2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2119
b401e9e2
MC		 2120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121 (GRC_LCLCTRL_GPIO_OE1 |
2122 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2123 }
2124 }
2125}
2126
e8f3f6ca
MC		 2127static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2128{
2129 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2130 return 1;
2131 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132 if (speed != SPEED_10)
2133 return 1;
2134 } else if (speed == SPEED_10)
2135 return 1;
2136
2137 return 0;
2138}
2139
1da177e4
LT		 2140static int tg3_setup_phy(struct tg3 *, int);
2141
2142#define RESET_KIND_SHUTDOWN 0
2143#define RESET_KIND_INIT 1
2144#define RESET_KIND_SUSPEND 2
2145
2146static void tg3_write_sig_post_reset(struct tg3 *, int);
2147static int tg3_halt_cpu(struct tg3 *, u32);
2148
0a459aac 2149static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2150{
ce057f01
MC		 2151 u32 val;
2152
5129724a
MC		 2153 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2157
2158 sg_dig_ctrl |=
2159 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2162 }
3f7045c1 2163 return;
5129724a 2164 }
3f7045c1 2165
60189ddf 2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2167 tg3_bmcr_reset(tp);
2168 val = tr32(GRC_MISC_CFG);
2169 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2170 udelay(40);
2171 return;
0e5f784c
MC		 2172 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2173 u32 phytest;
2174 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2175 u32 phy;
2176
2177 tg3_writephy(tp, MII_ADVERTISE, 0);
2178 tg3_writephy(tp, MII_BMCR,
2179 BMCR_ANENABLE | BMCR_ANRESTART);
2180
2181 tg3_writephy(tp, MII_TG3_FET_TEST,
2182 phytest | MII_TG3_FET_SHADOW_EN);
2183 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2185 tg3_writephy(tp,
2186 MII_TG3_FET_SHDW_AUXMODE4,
2187 phy);
2188 }
2189 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2190 }
2191 return;
0a459aac 2192 } else if (do_low_power) {
715116a1
MC		 2193 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2195
2196 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2201 }
3f7045c1 2202
15c3b696
MC		 2203 /* The PHY should not be powered down on some chips because
2204 * of bugs.
2205 */
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2210 return;
ce057f01 2211
bcb37f6c
MC		 2212 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2214 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2218 }
2219
15c3b696
MC		 2220 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2221}
2222
ffbcfed4
MC		 2223/* tp->lock is held. */
2224static int tg3_nvram_lock(struct tg3 *tp)
2225{
2226 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2227 int i;
2228
2229 if (tp->nvram_lock_cnt == 0) {
2230 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231 for (i = 0; i < 8000; i++) {
2232 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2233 break;
2234 udelay(20);
2235 }
2236 if (i == 8000) {
2237 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2238 return -ENODEV;
2239 }
2240 }
2241 tp->nvram_lock_cnt++;
2242 }
2243 return 0;
2244}
2245
2246/* tp->lock is held. */
2247static void tg3_nvram_unlock(struct tg3 *tp)
2248{
2249 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250 if (tp->nvram_lock_cnt > 0)
2251 tp->nvram_lock_cnt--;
2252 if (tp->nvram_lock_cnt == 0)
2253 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2254 }
2255}
2256
2257/* tp->lock is held. */
2258static void tg3_enable_nvram_access(struct tg3 *tp)
2259{
2260 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2261 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2262 u32 nvaccess = tr32(NVRAM_ACCESS);
2263
2264 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2265 }
2266}
2267
2268/* tp->lock is held. */
2269static void tg3_disable_nvram_access(struct tg3 *tp)
2270{
2271 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2272 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2273 u32 nvaccess = tr32(NVRAM_ACCESS);
2274
2275 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2276 }
2277}
2278
2279static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280 u32 offset, u32 *val)
2281{
2282 u32 tmp;
2283 int i;
2284
2285 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2286 return -EINVAL;
2287
2288 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289 EEPROM_ADDR_DEVID_MASK |
2290 EEPROM_ADDR_READ);
2291 tw32(GRC_EEPROM_ADDR,
2292 tmp |
2293 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295 EEPROM_ADDR_ADDR_MASK) |
2296 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2297
2298 for (i = 0; i < 1000; i++) {
2299 tmp = tr32(GRC_EEPROM_ADDR);
2300
2301 if (tmp & EEPROM_ADDR_COMPLETE)
2302 break;
2303 msleep(1);
2304 }
2305 if (!(tmp & EEPROM_ADDR_COMPLETE))
2306 return -EBUSY;
2307
62cedd11
MC		 2308 tmp = tr32(GRC_EEPROM_DATA);
2309
2310 /*
2311 * The data will always be opposite the native endian
2312 * format. Perform a blind byteswap to compensate.
2313 */
2314 *val = swab32(tmp);
2315
ffbcfed4
MC		 2316 return 0;
2317}
2318
2319#define NVRAM_CMD_TIMEOUT 10000
2320
2321static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2322{
2323 int i;
2324
2325 tw32(NVRAM_CMD, nvram_cmd);
2326 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2327 udelay(10);
2328 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2329 udelay(10);
2330 break;
2331 }
2332 }
2333
2334 if (i == NVRAM_CMD_TIMEOUT)
2335 return -EBUSY;
2336
2337 return 0;
2338}
2339
2340static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2341{
2342 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346 (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348 addr = ((addr / tp->nvram_pagesize) <<
2349 ATMEL_AT45DB0X1B_PAGE_POS) +
2350 (addr % tp->nvram_pagesize);
2351
2352 return addr;
2353}
2354
2355static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2356{
2357 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361 (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364 tp->nvram_pagesize) +
2365 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2366
2367 return addr;
2368}
2369
e4f34110
MC		 2370/* NOTE: Data read in from NVRAM is byteswapped according to
2371 * the byteswapping settings for all other register accesses.
2372 * tg3 devices are BE devices, so on a BE machine, the data
2373 * returned will be exactly as it is seen in NVRAM. On a LE
2374 * machine, the 32-bit value will be byteswapped.
2375 */
ffbcfed4
MC		 2376static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2377{
2378 int ret;
2379
2380 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381 return tg3_nvram_read_using_eeprom(tp, offset, val);
2382
2383 offset = tg3_nvram_phys_addr(tp, offset);
2384
2385 if (offset > NVRAM_ADDR_MSK)
2386 return -EINVAL;
2387
2388 ret = tg3_nvram_lock(tp);
2389 if (ret)
2390 return ret;
2391
2392 tg3_enable_nvram_access(tp);
2393
2394 tw32(NVRAM_ADDR, offset);
2395 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2397
2398 if (ret == 0)
e4f34110 2399 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2400
2401 tg3_disable_nvram_access(tp);
2402
2403 tg3_nvram_unlock(tp);
2404
2405 return ret;
2406}
2407
a9dc529d
MC		 2408/* Ensures NVRAM data is in bytestream format. */
2409static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2410{
2411 u32 v;
a9dc529d 2412 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2413 if (!res)
a9dc529d 2414 *val = cpu_to_be32(v);
ffbcfed4
MC		 2415 return res;
2416}
2417
3f007891
MC		 2418/* tp->lock is held. */
2419static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2420{
2421 u32 addr_high, addr_low;
2422 int i;
2423
2424 addr_high = ((tp->dev->dev_addr[0] << 8) |
2425 tp->dev->dev_addr[1]);
2426 addr_low = ((tp->dev->dev_addr[2] << 24) |
2427 (tp->dev->dev_addr[3] << 16) |
2428 (tp->dev->dev_addr[4] << 8) |
2429 (tp->dev->dev_addr[5] << 0));
2430 for (i = 0; i < 4; i++) {
2431 if (i == 1 && skip_mac_1)
2432 continue;
2433 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2435 }
2436
2437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439 for (i = 0; i < 12; i++) {
2440 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2442 }
2443 }
2444
2445 addr_high = (tp->dev->dev_addr[0] +
2446 tp->dev->dev_addr[1] +
2447 tp->dev->dev_addr[2] +
2448 tp->dev->dev_addr[3] +
2449 tp->dev->dev_addr[4] +
2450 tp->dev->dev_addr[5]) &
2451 TX_BACKOFF_SEED_MASK;
2452 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2453}
2454
bc1c7567 2455static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2456{
2457 u32 misc_host_ctrl;
0a459aac 2458 bool device_should_wake, do_low_power;
1da177e4
LT		 2459
2460 /* Make sure register accesses (indirect or otherwise)
2461 * will function correctly.
2462 */
2463 pci_write_config_dword(tp->pdev,
2464 TG3PCI_MISC_HOST_CTRL,
2465 tp->misc_host_ctrl);
2466
1da177e4 2467 switch (state) {
bc1c7567 2468 case PCI_D0:
12dac075
RW		 2469 pci_enable_wake(tp->pdev, state, false);
2470 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2471
9d26e213
MC		 2472 /* Switch out of Vaux if it is a NIC */
2473 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2474 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2475
2476 return 0;
2477
bc1c7567 2478 case PCI_D1:
bc1c7567 2479 case PCI_D2:
bc1c7567 2480 case PCI_D3hot:
1da177e4
LT		 2481 break;
2482
2483 default:
12dac075
RW		 2484 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485 tp->dev->name, state);
1da177e4 2486 return -EINVAL;
855e1111 2487 }
5e7dfd0f
MC		 2488
2489 /* Restore the CLKREQ setting. */
2490 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2491 u16 lnkctl;
2492
2493 pci_read_config_word(tp->pdev,
2494 tp->pcie_cap + PCI_EXP_LNKCTL,
2495 &lnkctl);
2496 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497 pci_write_config_word(tp->pdev,
2498 tp->pcie_cap + PCI_EXP_LNKCTL,
2499 lnkctl);
2500 }
2501
1da177e4
LT		 2502 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503 tw32(TG3PCI_MISC_HOST_CTRL,
2504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2505
05ac4cb7
MC		 2506 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507 device_may_wakeup(&tp->pdev->dev) &&
2508 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2509
dd477003 2510 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2511 do_low_power = false;
b02fd9e3
MC		 2512 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513 !tp->link_config.phy_is_low_power) {
2514 struct phy_device *phydev;
0a459aac 2515 u32 phyid, advertising;
b02fd9e3 2516
3f0e3ad7 2517 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2518
2519 tp->link_config.phy_is_low_power = 1;
2520
2521 tp->link_config.orig_speed = phydev->speed;
2522 tp->link_config.orig_duplex = phydev->duplex;
2523 tp->link_config.orig_autoneg = phydev->autoneg;
2524 tp->link_config.orig_advertising = phydev->advertising;
2525
2526 advertising = ADVERTISED_TP |
2527 ADVERTISED_Pause |
2528 ADVERTISED_Autoneg |
2529 ADVERTISED_10baseT_Half;
2530
2531 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2532 device_should_wake) {
b02fd9e3
MC		 2533 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2534 advertising |=
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full |
2537 ADVERTISED_10baseT_Full;
2538 else
2539 advertising |= ADVERTISED_10baseT_Full;
2540 }
2541
2542 phydev->advertising = advertising;
2543
2544 phy_start_aneg(phydev);
0a459aac
MC		 2545
2546 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547 if (phyid != TG3_PHY_ID_BCMAC131) {
2548 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2549 if (phyid == TG3_PHY_OUI_1 ||
2550 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2551 phyid == TG3_PHY_OUI_3)
2552 do_low_power = true;
2553 }
b02fd9e3 2554 }
dd477003 2555 } else {
2023276e 2556 do_low_power = true;
0a459aac 2557
dd477003
MC		 2558 if (tp->link_config.phy_is_low_power == 0) {
2559 tp->link_config.phy_is_low_power = 1;
2560 tp->link_config.orig_speed = tp->link_config.speed;
2561 tp->link_config.orig_duplex = tp->link_config.duplex;
2562 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2563 }
1da177e4 2564
dd477003
MC		 2565 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566 tp->link_config.speed = SPEED_10;
2567 tp->link_config.duplex = DUPLEX_HALF;
2568 tp->link_config.autoneg = AUTONEG_ENABLE;
2569 tg3_setup_phy(tp, 0);
2570 }
1da177e4
LT		 2571 }
2572
b5d3772c
MC		 2573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2574 u32 val;
2575
2576 val = tr32(GRC_VCPU_EXT_CTRL);
2577 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2579 int i;
2580 u32 val;
2581
2582 for (i = 0; i < 200; i++) {
2583 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2585 break;
2586 msleep(1);
2587 }
2588 }
a85feb8c
GZ		 2589 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591 WOL_DRV_STATE_SHUTDOWN |
2592 WOL_DRV_WOL |
2593 WOL_SET_MAGIC_PKT);
6921d201 2594
05ac4cb7 2595 if (device_should_wake) {
1da177e4
LT		 2596 u32 mac_mode;
2597
2598 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2599 if (do_low_power) {
dd477003
MC		 2600 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2601 udelay(40);
2602 }
1da177e4 2603
3f7045c1
MC		 2604 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605 mac_mode = MAC_MODE_PORT_MODE_GMII;
2606 else
2607 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2608
e8f3f6ca
MC		 2609 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2611 ASIC_REV_5700) {
2612 u32 speed = (tp->tg3_flags &
2613 TG3_FLAG_WOL_SPEED_100MB) ?
2614 SPEED_100 : SPEED_10;
2615 if (tg3_5700_link_polarity(tp, speed))
2616 mac_mode |= MAC_MODE_LINK_POLARITY;
2617 else
2618 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2619 }
1da177e4
LT		 2620 } else {
2621 mac_mode = MAC_MODE_PORT_MODE_TBI;
2622 }
2623
cbf46853 2624 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2625 tw32(MAC_LED_CTRL, tp->led_ctrl);
2626
05ac4cb7
MC		 2627 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2633
3bda1258
MC		 2634 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635 mac_mode |= tp->mac_mode &
2636 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637 if (mac_mode & MAC_MODE_APE_TX_EN)
2638 mac_mode |= MAC_MODE_TDE_ENABLE;
2639 }
2640
1da177e4
LT		 2641 tw32_f(MAC_MODE, mac_mode);
2642 udelay(100);
2643
2644 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2645 udelay(10);
2646 }
2647
2648 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2651 u32 base_val;
2652
2653 base_val = tp->pci_clock_ctrl;
2654 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655 CLOCK_CTRL_TXCLK_DISABLE);
2656
b401e9e2
MC		 2657 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2659 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2660 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2662 /* do nothing */
85e94ced 2663 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2664 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665 u32 newbits1, newbits2;
2666
2667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670 CLOCK_CTRL_TXCLK_DISABLE |
2671 CLOCK_CTRL_ALTCLK);
2672 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674 newbits1 = CLOCK_CTRL_625_CORE;
2675 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2676 } else {
2677 newbits1 = CLOCK_CTRL_ALTCLK;
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679 }
2680
b401e9e2
MC		 2681 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2682 40);
1da177e4 2683
b401e9e2
MC		 2684 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2685 40);
1da177e4
LT		 2686
2687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2688 u32 newbits3;
2689
2690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693 CLOCK_CTRL_TXCLK_DISABLE |
2694 CLOCK_CTRL_44MHZ_CORE);
2695 } else {
2696 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2697 }
2698
b401e9e2
MC		 2699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2701 }
2702 }
2703
05ac4cb7 2704 if (!(device_should_wake) &&
22435849 2705 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2706 tg3_power_down_phy(tp, do_low_power);
6921d201 2707
1da177e4
LT		 2708 tg3_frob_aux_power(tp);
2709
2710 /* Workaround for unstable PLL clock */
2711 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713 u32 val = tr32(0x7d00);
2714
2715 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2716 tw32(0x7d00, val);
6921d201 2717 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2718 int err;
2719
2720 err = tg3_nvram_lock(tp);
1da177e4 2721 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2722 if (!err)
2723 tg3_nvram_unlock(tp);
6921d201 2724 }
1da177e4
LT		 2725 }
2726
bbadf503
MC		 2727 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2728
05ac4cb7 2729 if (device_should_wake)
12dac075
RW		 2730 pci_enable_wake(tp->pdev, state, true);
2731
1da177e4 2732 /* Finally, set the new power state. */
12dac075 2733 pci_set_power_state(tp->pdev, state);
1da177e4 2734
1da177e4
LT		 2735 return 0;
2736}
2737
1da177e4
LT		 2738static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2739{
2740 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741 case MII_TG3_AUX_STAT_10HALF:
2742 *speed = SPEED_10;
2743 *duplex = DUPLEX_HALF;
2744 break;
2745
2746 case MII_TG3_AUX_STAT_10FULL:
2747 *speed = SPEED_10;
2748 *duplex = DUPLEX_FULL;
2749 break;
2750
2751 case MII_TG3_AUX_STAT_100HALF:
2752 *speed = SPEED_100;
2753 *duplex = DUPLEX_HALF;
2754 break;
2755
2756 case MII_TG3_AUX_STAT_100FULL:
2757 *speed = SPEED_100;
2758 *duplex = DUPLEX_FULL;
2759 break;
2760
2761 case MII_TG3_AUX_STAT_1000HALF:
2762 *speed = SPEED_1000;
2763 *duplex = DUPLEX_HALF;
2764 break;
2765
2766 case MII_TG3_AUX_STAT_1000FULL:
2767 *speed = SPEED_1000;
2768 *duplex = DUPLEX_FULL;
2769 break;
2770
2771 default:
7f97a4bd 2772 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2773 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2774 SPEED_10;
2775 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2776 DUPLEX_HALF;
2777 break;
2778 }
1da177e4
LT		 2779 *speed = SPEED_INVALID;
2780 *duplex = DUPLEX_INVALID;
2781 break;
855e1111 2782 }
1da177e4
LT		 2783}
2784
2785static void tg3_phy_copper_begin(struct tg3 *tp)
2786{
2787 u32 new_adv;
2788 int i;
2789
2790 if (tp->link_config.phy_is_low_power) {
2791 /* Entering low power mode. Disable gigabit and
2792 * 100baseT advertisements.
2793 */
2794 tg3_writephy(tp, MII_TG3_CTRL, 0);
2795
2796 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2800
2801 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2803 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804 tp->link_config.advertising &=
2805 ~(ADVERTISED_1000baseT_Half |
2806 ADVERTISED_1000baseT_Full);
2807
ba4d07a8 2808 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2809 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810 new_adv |= ADVERTISE_10HALF;
2811 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812 new_adv |= ADVERTISE_10FULL;
2813 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814 new_adv |= ADVERTISE_100HALF;
2815 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2817
2818 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2819
1da177e4
LT		 2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822 if (tp->link_config.advertising &
2823 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2824 new_adv = 0;
2825 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833 MII_TG3_CTRL_ENABLE_AS_MASTER);
2834 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2835 } else {
2836 tg3_writephy(tp, MII_TG3_CTRL, 0);
2837 }
2838 } else {
ba4d07a8
MC		 2839 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840 new_adv |= ADVERTISE_CSMA;
2841
1da177e4
LT		 2842 /* Asking for a specific link mode. */
2843 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2844 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2845
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2848 else
2849 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2854 } else {
1da177e4
LT		 2855 if (tp->link_config.speed == SPEED_100) {
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 new_adv |= ADVERTISE_100FULL;
2858 else
2859 new_adv |= ADVERTISE_100HALF;
2860 } else {
2861 if (tp->link_config.duplex == DUPLEX_FULL)
2862 new_adv |= ADVERTISE_10FULL;
2863 else
2864 new_adv |= ADVERTISE_10HALF;
2865 }
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2867
2868 new_adv = 0;
1da177e4 2869 }
ba4d07a8
MC		 2870
2871 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2872 }
2873
2874 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875 tp->link_config.speed != SPEED_INVALID) {
2876 u32 bmcr, orig_bmcr;
2877
2878 tp->link_config.active_speed = tp->link_config.speed;
2879 tp->link_config.active_duplex = tp->link_config.duplex;
2880
2881 bmcr = 0;
2882 switch (tp->link_config.speed) {
2883 default:
2884 case SPEED_10:
2885 break;
2886
2887 case SPEED_100:
2888 bmcr |= BMCR_SPEED100;
2889 break;
2890
2891 case SPEED_1000:
2892 bmcr |= TG3_BMCR_SPEED1000;
2893 break;
855e1111 2894 }
1da177e4
LT		 2895
2896 if (tp->link_config.duplex == DUPLEX_FULL)
2897 bmcr |= BMCR_FULLDPLX;
2898
2899 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900 (bmcr != orig_bmcr)) {
2901 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902 for (i = 0; i < 1500; i++) {
2903 u32 tmp;
2904
2905 udelay(10);
2906 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907 tg3_readphy(tp, MII_BMSR, &tmp))
2908 continue;
2909 if (!(tmp & BMSR_LSTATUS)) {
2910 udelay(40);
2911 break;
2912 }
2913 }
2914 tg3_writephy(tp, MII_BMCR, bmcr);
2915 udelay(40);
2916 }
2917 } else {
2918 tg3_writephy(tp, MII_BMCR,
2919 BMCR_ANENABLE | BMCR_ANRESTART);
2920 }
2921}
2922
2923static int tg3_init_5401phy_dsp(struct tg3 *tp)
2924{
2925 int err;
2926
2927 /* Turn off tap power management. */
2928 /* Set Extended packet length bit */
2929 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2936
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2939
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2942
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2945
2946 udelay(40);
2947
2948 return err;
2949}
2950
3600d918 2951static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2952{
3600d918
MC		 2953 u32 adv_reg, all_mask = 0;
2954
2955 if (mask & ADVERTISED_10baseT_Half)
2956 all_mask |= ADVERTISE_10HALF;
2957 if (mask & ADVERTISED_10baseT_Full)
2958 all_mask |= ADVERTISE_10FULL;
2959 if (mask & ADVERTISED_100baseT_Half)
2960 all_mask |= ADVERTISE_100HALF;
2961 if (mask & ADVERTISED_100baseT_Full)
2962 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2963
2964 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2965 return 0;
2966
1da177e4
LT		 2967 if ((adv_reg & all_mask) != all_mask)
2968 return 0;
2969 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2970 u32 tg3_ctrl;
2971
3600d918
MC		 2972 all_mask = 0;
2973 if (mask & ADVERTISED_1000baseT_Half)
2974 all_mask |= ADVERTISE_1000HALF;
2975 if (mask & ADVERTISED_1000baseT_Full)
2976 all_mask |= ADVERTISE_1000FULL;
2977
1da177e4
LT		 2978 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2979 return 0;
2980
1da177e4
LT		 2981 if ((tg3_ctrl & all_mask) != all_mask)
2982 return 0;
2983 }
2984 return 1;
2985}
2986
ef167e27
MC		 2987static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2988{
2989 u32 curadv, reqadv;
2990
2991 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2992 return 1;
2993
2994 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2996
2997 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998 if (curadv != reqadv)
2999 return 0;
3000
3001 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002 tg3_readphy(tp, MII_LPA, rmtadv);
3003 } else {
3004 /* Reprogram the advertisement register, even if it
3005 * does not affect the current link. If the link
3006 * gets renegotiated in the future, we can save an
3007 * additional renegotiation cycle by advertising
3008 * it correctly in the first place.
3009 */
3010 if (curadv != reqadv) {
3011 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012 ADVERTISE_PAUSE_ASYM);
3013 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3014 }
3015 }
3016
3017 return 1;
3018}
3019
1da177e4
LT		 3020static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3021{
3022 int current_link_up;
3023 u32 bmsr, dummy;
ef167e27 3024 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3025 u16 current_speed;
3026 u8 current_duplex;
3027 int i, err;
3028
3029 tw32(MAC_EVENT, 0);
3030
3031 tw32_f(MAC_STATUS,
3032 (MAC_STATUS_SYNC_CHANGED |
3033 MAC_STATUS_CFG_CHANGED |
3034 MAC_STATUS_MI_COMPLETION |
3035 MAC_STATUS_LNKSTATE_CHANGED));
3036 udelay(40);
3037
8ef21428
MC		 3038 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3039 tw32_f(MAC_MI_MODE,
3040 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3041 udelay(80);
3042 }
1da177e4
LT		 3043
3044 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3045
3046 /* Some third-party PHYs need to be reset on link going
3047 * down.
3048 */
3049 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052 netif_carrier_ok(tp->dev)) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055 !(bmsr & BMSR_LSTATUS))
3056 force_reset = 1;
3057 }
3058 if (force_reset)
3059 tg3_phy_reset(tp);
3060
3061 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062 tg3_readphy(tp, MII_BMSR, &bmsr);
3063 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3065 bmsr = 0;
3066
3067 if (!(bmsr & BMSR_LSTATUS)) {
3068 err = tg3_init_5401phy_dsp(tp);
3069 if (err)
3070 return err;
3071
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 for (i = 0; i < 1000; i++) {
3074 udelay(10);
3075 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076 (bmsr & BMSR_LSTATUS)) {
3077 udelay(40);
3078 break;
3079 }
3080 }
3081
3082 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083 !(bmsr & BMSR_LSTATUS) &&
3084 tp->link_config.active_speed == SPEED_1000) {
3085 err = tg3_phy_reset(tp);
3086 if (!err)
3087 err = tg3_init_5401phy_dsp(tp);
3088 if (err)
3089 return err;
3090 }
3091 }
3092 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094 /* 5701 {A0,B0} CRC bug workaround */
3095 tg3_writephy(tp, 0x15, 0x0a75);
3096 tg3_writephy(tp, 0x1c, 0x8c68);
3097 tg3_writephy(tp, 0x1c, 0x8d68);
3098 tg3_writephy(tp, 0x1c, 0x8c68);
3099 }
3100
3101 /* Clear pending interrupts... */
3102 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3104
3105 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3107 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3108 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3109
3110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3115 else
3116 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3117 }
3118
3119 current_link_up = 0;
3120 current_speed = SPEED_INVALID;
3121 current_duplex = DUPLEX_INVALID;
3122
3123 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3124 u32 val;
3125
3126 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128 if (!(val & (1 << 10))) {
3129 val |= (1 << 10);
3130 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3131 goto relink;
3132 }
3133 }
3134
3135 bmsr = 0;
3136 for (i = 0; i < 100; i++) {
3137 tg3_readphy(tp, MII_BMSR, &bmsr);
3138 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139 (bmsr & BMSR_LSTATUS))
3140 break;
3141 udelay(40);
3142 }
3143
3144 if (bmsr & BMSR_LSTATUS) {
3145 u32 aux_stat, bmcr;
3146
3147 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148 for (i = 0; i < 2000; i++) {
3149 udelay(10);
3150 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3151 aux_stat)
3152 break;
3153 }
3154
3155 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3156 &current_speed,
3157 &current_duplex);
3158
3159 bmcr = 0;
3160 for (i = 0; i < 200; i++) {
3161 tg3_readphy(tp, MII_BMCR, &bmcr);
3162 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3163 continue;
3164 if (bmcr && bmcr != 0x7fff)
3165 break;
3166 udelay(10);
3167 }
3168
ef167e27
MC		 3169 lcl_adv = 0;
3170 rmt_adv = 0;
1da177e4 3171
ef167e27
MC		 3172 tp->link_config.active_speed = current_speed;
3173 tp->link_config.active_duplex = current_duplex;
3174
3175 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176 if ((bmcr & BMCR_ANENABLE) &&
3177 tg3_copper_is_advertising_all(tp,
3178 tp->link_config.advertising)) {
3179 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3180 &rmt_adv))
3181 current_link_up = 1;
1da177e4
LT		 3182 }
3183 } else {
3184 if (!(bmcr & BMCR_ANENABLE) &&
3185 tp->link_config.speed == current_speed &&
ef167e27
MC		 3186 tp->link_config.duplex == current_duplex &&
3187 tp->link_config.flowctrl ==
3188 tp->link_config.active_flowctrl) {
1da177e4 3189 current_link_up = 1;
1da177e4
LT		 3190 }
3191 }
3192
ef167e27
MC		 3193 if (current_link_up == 1 &&
3194 tp->link_config.active_duplex == DUPLEX_FULL)
3195 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3196 }
3197
1da177e4 3198relink:
6921d201 3199 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3200 u32 tmp;
3201
3202 tg3_phy_copper_begin(tp);
3203
3204 tg3_readphy(tp, MII_BMSR, &tmp);
3205 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206 (tmp & BMSR_LSTATUS))
3207 current_link_up = 1;
3208 }
3209
3210 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211 if (current_link_up == 1) {
3212 if (tp->link_config.active_speed == SPEED_100 ||
3213 tp->link_config.active_speed == SPEED_10)
3214 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3215 else
3216 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3217 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219 else
1da177e4
LT		 3220 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3221
3222 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223 if (tp->link_config.active_duplex == DUPLEX_HALF)
3224 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3225
1da177e4 3226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3227 if (current_link_up == 1 &&
3228 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3229 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3230 else
3231 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3232 }
3233
3234 /* ??? Without this setting Netgear GA302T PHY does not
3235 * ??? send/receive packets...
3236 */
3237 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240 tw32_f(MAC_MI_MODE, tp->mi_mode);
3241 udelay(80);
3242 }
3243
3244 tw32_f(MAC_MODE, tp->mac_mode);
3245 udelay(40);
3246
3247 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248 /* Polled via timer. */
3249 tw32_f(MAC_EVENT, 0);
3250 } else {
3251 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3252 }
3253 udelay(40);
3254
3255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256 current_link_up == 1 &&
3257 tp->link_config.active_speed == SPEED_1000 &&
3258 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3260 udelay(120);
3261 tw32_f(MAC_STATUS,
3262 (MAC_STATUS_SYNC_CHANGED |
3263 MAC_STATUS_CFG_CHANGED));
3264 udelay(40);
3265 tg3_write_mem(tp,
3266 NIC_SRAM_FIRMWARE_MBOX,
3267 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3268 }
3269
5e7dfd0f
MC		 3270 /* Prevent send BD corruption. */
3271 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272 u16 oldlnkctl, newlnkctl;
3273
3274 pci_read_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3276 &oldlnkctl);
3277 if (tp->link_config.active_speed == SPEED_100 ||
3278 tp->link_config.active_speed == SPEED_10)
3279 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3280 else
3281 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282 if (newlnkctl != oldlnkctl)
3283 pci_write_config_word(tp->pdev,
3284 tp->pcie_cap + PCI_EXP_LNKCTL,
3285 newlnkctl);
3286 }
3287
1da177e4
LT		 3288 if (current_link_up != netif_carrier_ok(tp->dev)) {
3289 if (current_link_up)
3290 netif_carrier_on(tp->dev);
3291 else
3292 netif_carrier_off(tp->dev);
3293 tg3_link_report(tp);
3294 }
3295
3296 return 0;
3297}
3298
3299struct tg3_fiber_aneginfo {
3300 int state;
3301#define ANEG_STATE_UNKNOWN 0
3302#define ANEG_STATE_AN_ENABLE 1
3303#define ANEG_STATE_RESTART_INIT 2
3304#define ANEG_STATE_RESTART 3
3305#define ANEG_STATE_DISABLE_LINK_OK 4
3306#define ANEG_STATE_ABILITY_DETECT_INIT 5
3307#define ANEG_STATE_ABILITY_DETECT 6
3308#define ANEG_STATE_ACK_DETECT_INIT 7
3309#define ANEG_STATE_ACK_DETECT 8
3310#define ANEG_STATE_COMPLETE_ACK_INIT 9
3311#define ANEG_STATE_COMPLETE_ACK 10
3312#define ANEG_STATE_IDLE_DETECT_INIT 11
3313#define ANEG_STATE_IDLE_DETECT 12
3314#define ANEG_STATE_LINK_OK 13
3315#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3316#define ANEG_STATE_NEXT_PAGE_WAIT 15
3317
3318 u32 flags;
3319#define MR_AN_ENABLE 0x00000001
3320#define MR_RESTART_AN 0x00000002
3321#define MR_AN_COMPLETE 0x00000004
3322#define MR_PAGE_RX 0x00000008
3323#define MR_NP_LOADED 0x00000010
3324#define MR_TOGGLE_TX 0x00000020
3325#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3326#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3327#define MR_LP_ADV_SYM_PAUSE 0x00000100
3328#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3329#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331#define MR_LP_ADV_NEXT_PAGE 0x00001000
3332#define MR_TOGGLE_RX 0x00002000
3333#define MR_NP_RX 0x00004000
3334
3335#define MR_LINK_OK 0x80000000
3336
3337 unsigned long link_time, cur_time;
3338
3339 u32 ability_match_cfg;
3340 int ability_match_count;
3341
3342 char ability_match, idle_match, ack_match;
3343
3344 u32 txconfig, rxconfig;
3345#define ANEG_CFG_NP 0x00000080
3346#define ANEG_CFG_ACK 0x00000040
3347#define ANEG_CFG_RF2 0x00000020
3348#define ANEG_CFG_RF1 0x00000010
3349#define ANEG_CFG_PS2 0x00000001
3350#define ANEG_CFG_PS1 0x00008000
3351#define ANEG_CFG_HD 0x00004000
3352#define ANEG_CFG_FD 0x00002000
3353#define ANEG_CFG_INVAL 0x00001f06
3354
3355};
3356#define ANEG_OK 0
3357#define ANEG_DONE 1
3358#define ANEG_TIMER_ENAB 2
3359#define ANEG_FAILED -1
3360
3361#define ANEG_STATE_SETTLE_TIME 10000
3362
3363static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364 struct tg3_fiber_aneginfo *ap)
3365{
5be73b47 3366 u16 flowctrl;
1da177e4
LT		 3367 unsigned long delta;
3368 u32 rx_cfg_reg;
3369 int ret;
3370
3371 if (ap->state == ANEG_STATE_UNKNOWN) {
3372 ap->rxconfig = 0;
3373 ap->link_time = 0;
3374 ap->cur_time = 0;
3375 ap->ability_match_cfg = 0;
3376 ap->ability_match_count = 0;
3377 ap->ability_match = 0;
3378 ap->idle_match = 0;
3379 ap->ack_match = 0;
3380 }
3381 ap->cur_time++;
3382
3383 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3385
3386 if (rx_cfg_reg != ap->ability_match_cfg) {
3387 ap->ability_match_cfg = rx_cfg_reg;
3388 ap->ability_match = 0;
3389 ap->ability_match_count = 0;
3390 } else {
3391 if (++ap->ability_match_count > 1) {
3392 ap->ability_match = 1;
3393 ap->ability_match_cfg = rx_cfg_reg;
3394 }
3395 }
3396 if (rx_cfg_reg & ANEG_CFG_ACK)
3397 ap->ack_match = 1;
3398 else
3399 ap->ack_match = 0;
3400
3401 ap->idle_match = 0;
3402 } else {
3403 ap->idle_match = 1;
3404 ap->ability_match_cfg = 0;
3405 ap->ability_match_count = 0;
3406 ap->ability_match = 0;
3407 ap->ack_match = 0;
3408
3409 rx_cfg_reg = 0;
3410 }
3411
3412 ap->rxconfig = rx_cfg_reg;
3413 ret = ANEG_OK;
3414
3415 switch(ap->state) {
3416 case ANEG_STATE_UNKNOWN:
3417 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418 ap->state = ANEG_STATE_AN_ENABLE;
3419
3420 /* fallthru */
3421 case ANEG_STATE_AN_ENABLE:
3422 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423 if (ap->flags & MR_AN_ENABLE) {
3424 ap->link_time = 0;
3425 ap->cur_time = 0;
3426 ap->ability_match_cfg = 0;
3427 ap->ability_match_count = 0;
3428 ap->ability_match = 0;
3429 ap->idle_match = 0;
3430 ap->ack_match = 0;
3431
3432 ap->state = ANEG_STATE_RESTART_INIT;
3433 } else {
3434 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3435 }
3436 break;
3437
3438 case ANEG_STATE_RESTART_INIT:
3439 ap->link_time = ap->cur_time;
3440 ap->flags &= ~(MR_NP_LOADED);
3441 ap->txconfig = 0;
3442 tw32(MAC_TX_AUTO_NEG, 0);
3443 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444 tw32_f(MAC_MODE, tp->mac_mode);
3445 udelay(40);
3446
3447 ret = ANEG_TIMER_ENAB;
3448 ap->state = ANEG_STATE_RESTART;
3449
3450 /* fallthru */
3451 case ANEG_STATE_RESTART:
3452 delta = ap->cur_time - ap->link_time;
3453 if (delta > ANEG_STATE_SETTLE_TIME) {
3454 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3455 } else {
3456 ret = ANEG_TIMER_ENAB;
3457 }
3458 break;
3459
3460 case ANEG_STATE_DISABLE_LINK_OK:
3461 ret = ANEG_DONE;
3462 break;
3463
3464 case ANEG_STATE_ABILITY_DETECT_INIT:
3465 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3466 ap->txconfig = ANEG_CFG_FD;
3467 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468 if (flowctrl & ADVERTISE_1000XPAUSE)
3469 ap->txconfig |= ANEG_CFG_PS1;
3470 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3472 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474 tw32_f(MAC_MODE, tp->mac_mode);
3475 udelay(40);
3476
3477 ap->state = ANEG_STATE_ABILITY_DETECT;
3478 break;
3479
3480 case ANEG_STATE_ABILITY_DETECT:
3481 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3483 }
3484 break;
3485
3486 case ANEG_STATE_ACK_DETECT_INIT:
3487 ap->txconfig |= ANEG_CFG_ACK;
3488 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490 tw32_f(MAC_MODE, tp->mac_mode);
3491 udelay(40);
3492
3493 ap->state = ANEG_STATE_ACK_DETECT;
3494
3495 /* fallthru */
3496 case ANEG_STATE_ACK_DETECT:
3497 if (ap->ack_match != 0) {
3498 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3501 } else {
3502 ap->state = ANEG_STATE_AN_ENABLE;
3503 }
3504 } else if (ap->ability_match != 0 &&
3505 ap->rxconfig == 0) {
3506 ap->state = ANEG_STATE_AN_ENABLE;
3507 }
3508 break;
3509
3510 case ANEG_STATE_COMPLETE_ACK_INIT:
3511 if (ap->rxconfig & ANEG_CFG_INVAL) {
3512 ret = ANEG_FAILED;
3513 break;
3514 }
3515 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516 MR_LP_ADV_HALF_DUPLEX |
3517 MR_LP_ADV_SYM_PAUSE |
3518 MR_LP_ADV_ASYM_PAUSE |
3519 MR_LP_ADV_REMOTE_FAULT1 |
3520 MR_LP_ADV_REMOTE_FAULT2 |
3521 MR_LP_ADV_NEXT_PAGE |
3522 MR_TOGGLE_RX |
3523 MR_NP_RX);
3524 if (ap->rxconfig & ANEG_CFG_FD)
3525 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526 if (ap->rxconfig & ANEG_CFG_HD)
3527 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528 if (ap->rxconfig & ANEG_CFG_PS1)
3529 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530 if (ap->rxconfig & ANEG_CFG_PS2)
3531 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532 if (ap->rxconfig & ANEG_CFG_RF1)
3533 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534 if (ap->rxconfig & ANEG_CFG_RF2)
3535 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536 if (ap->rxconfig & ANEG_CFG_NP)
3537 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3538
3539 ap->link_time = ap->cur_time;
3540
3541 ap->flags ^= (MR_TOGGLE_TX);
3542 if (ap->rxconfig & 0x0008)
3543 ap->flags |= MR_TOGGLE_RX;
3544 if (ap->rxconfig & ANEG_CFG_NP)
3545 ap->flags |= MR_NP_RX;
3546 ap->flags |= MR_PAGE_RX;
3547
3548 ap->state = ANEG_STATE_COMPLETE_ACK;
3549 ret = ANEG_TIMER_ENAB;
3550 break;
3551
3552 case ANEG_STATE_COMPLETE_ACK:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3556 break;
3557 }
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3562 } else {
3563 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564 !(ap->flags & MR_NP_RX)) {
3565 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566 } else {
3567 ret = ANEG_FAILED;
3568 }
3569 }
3570 }
3571 break;
3572
3573 case ANEG_STATE_IDLE_DETECT_INIT:
3574 ap->link_time = ap->cur_time;
3575 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576 tw32_f(MAC_MODE, tp->mac_mode);
3577 udelay(40);
3578
3579 ap->state = ANEG_STATE_IDLE_DETECT;
3580 ret = ANEG_TIMER_ENAB;
3581 break;
3582
3583 case ANEG_STATE_IDLE_DETECT:
3584 if (ap->ability_match != 0 &&
3585 ap->rxconfig == 0) {
3586 ap->state = ANEG_STATE_AN_ENABLE;
3587 break;
3588 }
3589 delta = ap->cur_time - ap->link_time;
3590 if (delta > ANEG_STATE_SETTLE_TIME) {
3591 /* XXX another gem from the Broadcom driver :( */
3592 ap->state = ANEG_STATE_LINK_OK;
3593 }
3594 break;
3595
3596 case ANEG_STATE_LINK_OK:
3597 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3598 ret = ANEG_DONE;
3599 break;
3600
3601 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602 /* ??? unimplemented */
3603 break;
3604
3605 case ANEG_STATE_NEXT_PAGE_WAIT:
3606 /* ??? unimplemented */
3607 break;
3608
3609 default:
3610 ret = ANEG_FAILED;
3611 break;
855e1111 3612 }
1da177e4
LT		 3613
3614 return ret;
3615}
3616
5be73b47 3617static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3618{
3619 int res = 0;
3620 struct tg3_fiber_aneginfo aninfo;
3621 int status = ANEG_FAILED;
3622 unsigned int tick;
3623 u32 tmp;
3624
3625 tw32_f(MAC_TX_AUTO_NEG, 0);
3626
3627 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3629 udelay(40);
3630
3631 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3632 udelay(40);
3633
3634 memset(&aninfo, 0, sizeof(aninfo));
3635 aninfo.flags |= MR_AN_ENABLE;
3636 aninfo.state = ANEG_STATE_UNKNOWN;
3637 aninfo.cur_time = 0;
3638 tick = 0;
3639 while (++tick < 195000) {
3640 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641 if (status == ANEG_DONE || status == ANEG_FAILED)
3642 break;
3643
3644 udelay(1);
3645 }
3646
3647 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648 tw32_f(MAC_MODE, tp->mac_mode);
3649 udelay(40);
3650
5be73b47
MC		 3651 *txflags = aninfo.txconfig;
3652 *rxflags = aninfo.flags;
1da177e4
LT		 3653
3654 if (status == ANEG_DONE &&
3655 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656 MR_LP_ADV_FULL_DUPLEX)))
3657 res = 1;
3658
3659 return res;
3660}
3661
3662static void tg3_init_bcm8002(struct tg3 *tp)
3663{
3664 u32 mac_status = tr32(MAC_STATUS);
3665 int i;
3666
3667 /* Reset when initting first time or we have a link. */
3668 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669 !(mac_status & MAC_STATUS_PCS_SYNCED))
3670 return;
3671
3672 /* Set PLL lock range. */
3673 tg3_writephy(tp, 0x16, 0x8007);
3674
3675 /* SW reset */
3676 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3677
3678 /* Wait for reset to complete. */
3679 /* XXX schedule_timeout() ... */
3680 for (i = 0; i < 500; i++)
3681 udelay(10);
3682
3683 /* Config mode; select PMA/Ch 1 regs. */
3684 tg3_writephy(tp, 0x10, 0x8411);
3685
3686 /* Enable auto-lock and comdet, select txclk for tx. */
3687 tg3_writephy(tp, 0x11, 0x0a10);
3688
3689 tg3_writephy(tp, 0x18, 0x00a0);
3690 tg3_writephy(tp, 0x16, 0x41ff);
3691
3692 /* Assert and deassert POR. */
3693 tg3_writephy(tp, 0x13, 0x0400);
3694 udelay(40);
3695 tg3_writephy(tp, 0x13, 0x0000);
3696
3697 tg3_writephy(tp, 0x11, 0x0a50);
3698 udelay(40);
3699 tg3_writephy(tp, 0x11, 0x0a10);
3700
3701 /* Wait for signal to stabilize */
3702 /* XXX schedule_timeout() ... */
3703 for (i = 0; i < 15000; i++)
3704 udelay(10);
3705
3706 /* Deselect the channel register so we can read the PHYID
3707 * later.
3708 */
3709 tg3_writephy(tp, 0x10, 0x8011);
3710}
3711
3712static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3713{
82cd3d11 3714 u16 flowctrl;
1da177e4
LT		 3715 u32 sg_dig_ctrl, sg_dig_status;
3716 u32 serdes_cfg, expected_sg_dig_ctrl;
3717 int workaround, port_a;
3718 int current_link_up;
3719
3720 serdes_cfg = 0;
3721 expected_sg_dig_ctrl = 0;
3722 workaround = 0;
3723 port_a = 1;
3724 current_link_up = 0;
3725
3726 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3728 workaround = 1;
3729 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3730 port_a = 0;
3731
3732 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733 /* preserve bits 20-23 for voltage regulator */
3734 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3735 }
3736
3737 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3738
3739 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3740 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3741 if (workaround) {
3742 u32 val = serdes_cfg;
3743
3744 if (port_a)
3745 val |= 0xc010000;
3746 else
3747 val |= 0x4010000;
3748 tw32_f(MAC_SERDES_CFG, val);
3749 }
c98f6e3b
MC		 3750
3751 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3752 }
3753 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754 tg3_setup_flow_control(tp, 0, 0);
3755 current_link_up = 1;
3756 }
3757 goto out;
3758 }
3759
3760 /* Want auto-negotiation. */
c98f6e3b 3761 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3762
82cd3d11
MC		 3763 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764 if (flowctrl & ADVERTISE_1000XPAUSE)
3765 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3768
3769 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3770 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771 tp->serdes_counter &&
3772 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773 MAC_STATUS_RCVD_CFG)) ==
3774 MAC_STATUS_PCS_SYNCED)) {
3775 tp->serdes_counter--;
3776 current_link_up = 1;
3777 goto out;
3778 }
3779restart_autoneg:
1da177e4
LT		 3780 if (workaround)
3781 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3782 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3783 udelay(5);
3784 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3785
3d3ebe74
MC		 3786 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3788 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3790 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3791 mac_status = tr32(MAC_STATUS);
3792
c98f6e3b 3793 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3794 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3795 u32 local_adv = 0, remote_adv = 0;
3796
3797 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798 local_adv |= ADVERTISE_1000XPAUSE;
3799 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3801
c98f6e3b 3802 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3803 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3804 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3805 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3806
3807 tg3_setup_flow_control(tp, local_adv, remote_adv);
3808 current_link_up = 1;
3d3ebe74
MC		 3809 tp->serdes_counter = 0;
3810 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3811 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3812 if (tp->serdes_counter)
3813 tp->serdes_counter--;
1da177e4
LT		 3814 else {
3815 if (workaround) {
3816 u32 val = serdes_cfg;
3817
3818 if (port_a)
3819 val |= 0xc010000;
3820 else
3821 val |= 0x4010000;
3822
3823 tw32_f(MAC_SERDES_CFG, val);
3824 }
3825
c98f6e3b 3826 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3827 udelay(40);
3828
3829 /* Link parallel detection - link is up */
3830 /* only if we have PCS_SYNC and not */
3831 /* receiving config code words */
3832 mac_status = tr32(MAC_STATUS);
3833 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835 tg3_setup_flow_control(tp, 0, 0);
3836 current_link_up = 1;
3d3ebe74
MC		 3837 tp->tg3_flags2 |=
3838 TG3_FLG2_PARALLEL_DETECT;
3839 tp->serdes_counter =
3840 SERDES_PARALLEL_DET_TIMEOUT;
3841 } else
3842 goto restart_autoneg;
1da177e4
LT		 3843 }
3844 }
3d3ebe74
MC		 3845 } else {
3846 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3848 }
3849
3850out:
3851 return current_link_up;
3852}
3853
3854static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3855{
3856 int current_link_up = 0;
3857
5cf64b8a 3858 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3859 goto out;
1da177e4
LT		 3860
3861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3862 u32 txflags, rxflags;
1da177e4 3863 int i;
6aa20a22 3864
5be73b47
MC		 3865 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866 u32 local_adv = 0, remote_adv = 0;
1da177e4 3867
5be73b47
MC		 3868 if (txflags & ANEG_CFG_PS1)
3869 local_adv |= ADVERTISE_1000XPAUSE;
3870 if (txflags & ANEG_CFG_PS2)
3871 local_adv |= ADVERTISE_1000XPSE_ASYM;
3872
3873 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874 remote_adv |= LPA_1000XPAUSE;
3875 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3877
3878 tg3_setup_flow_control(tp, local_adv, remote_adv);
3879
1da177e4
LT		 3880 current_link_up = 1;
3881 }
3882 for (i = 0; i < 30; i++) {
3883 udelay(20);
3884 tw32_f(MAC_STATUS,
3885 (MAC_STATUS_SYNC_CHANGED |
3886 MAC_STATUS_CFG_CHANGED));
3887 udelay(40);
3888 if ((tr32(MAC_STATUS) &
3889 (MAC_STATUS_SYNC_CHANGED |
3890 MAC_STATUS_CFG_CHANGED)) == 0)
3891 break;
3892 }
3893
3894 mac_status = tr32(MAC_STATUS);
3895 if (current_link_up == 0 &&
3896 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897 !(mac_status & MAC_STATUS_RCVD_CFG))
3898 current_link_up = 1;
3899 } else {
5be73b47
MC		 3900 tg3_setup_flow_control(tp, 0, 0);
3901
1da177e4
LT		 3902 /* Forcing 1000FD link up. */
3903 current_link_up = 1;
1da177e4
LT		 3904
3905 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3906 udelay(40);
e8f3f6ca
MC		 3907
3908 tw32_f(MAC_MODE, tp->mac_mode);
3909 udelay(40);
1da177e4
LT		 3910 }
3911
3912out:
3913 return current_link_up;
3914}
3915
3916static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3917{
3918 u32 orig_pause_cfg;
3919 u16 orig_active_speed;
3920 u8 orig_active_duplex;
3921 u32 mac_status;
3922 int current_link_up;
3923 int i;
3924
8d018621 3925 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3926 orig_active_speed = tp->link_config.active_speed;
3927 orig_active_duplex = tp->link_config.active_duplex;
3928
3929 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930 netif_carrier_ok(tp->dev) &&
3931 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932 mac_status = tr32(MAC_STATUS);
3933 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934 MAC_STATUS_SIGNAL_DET |
3935 MAC_STATUS_CFG_CHANGED |
3936 MAC_STATUS_RCVD_CFG);
3937 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938 MAC_STATUS_SIGNAL_DET)) {
3939 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940 MAC_STATUS_CFG_CHANGED));
3941 return 0;
3942 }
3943 }
3944
3945 tw32_f(MAC_TX_AUTO_NEG, 0);
3946
3947 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949 tw32_f(MAC_MODE, tp->mac_mode);
3950 udelay(40);
3951
3952 if (tp->phy_id == PHY_ID_BCM8002)
3953 tg3_init_bcm8002(tp);
3954
3955 /* Enable link change event even when serdes polling. */
3956 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3957 udelay(40);
3958
3959 current_link_up = 0;
3960 mac_status = tr32(MAC_STATUS);
3961
3962 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3964 else
3965 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3966
898a56f8 3967 tp->napi[0].hw_status->status =
1da177e4 3968 (SD_STATUS_UPDATED |
898a56f8 3969 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3970
3971 for (i = 0; i < 100; i++) {
3972 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973 MAC_STATUS_CFG_CHANGED));
3974 udelay(5);
3975 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3976 MAC_STATUS_CFG_CHANGED |
3977 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3978 break;
3979 }
3980
3981 mac_status = tr32(MAC_STATUS);
3982 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983 current_link_up = 0;
3d3ebe74
MC		 3984 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985 tp->serdes_counter == 0) {
1da177e4
LT		 3986 tw32_f(MAC_MODE, (tp->mac_mode |
3987 MAC_MODE_SEND_CONFIGS));
3988 udelay(1);
3989 tw32_f(MAC_MODE, tp->mac_mode);
3990 }
3991 }
3992
3993 if (current_link_up == 1) {
3994 tp->link_config.active_speed = SPEED_1000;
3995 tp->link_config.active_duplex = DUPLEX_FULL;
3996 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997 LED_CTRL_LNKLED_OVERRIDE |
3998 LED_CTRL_1000MBPS_ON));
3999 } else {
4000 tp->link_config.active_speed = SPEED_INVALID;
4001 tp->link_config.active_duplex = DUPLEX_INVALID;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_TRAFFIC_OVERRIDE));
4005 }
4006
4007 if (current_link_up != netif_carrier_ok(tp->dev)) {
4008 if (current_link_up)
4009 netif_carrier_on(tp->dev);
4010 else
4011 netif_carrier_off(tp->dev);
4012 tg3_link_report(tp);
4013 } else {
8d018621 4014 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4015 if (orig_pause_cfg != now_pause_cfg ||
4016 orig_active_speed != tp->link_config.active_speed ||
4017 orig_active_duplex != tp->link_config.active_duplex)
4018 tg3_link_report(tp);
4019 }
4020
4021 return 0;
4022}
4023
747e8f8b
MC		 4024static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4025{
4026 int current_link_up, err = 0;
4027 u32 bmsr, bmcr;
4028 u16 current_speed;
4029 u8 current_duplex;
ef167e27 4030 u32 local_adv, remote_adv;
747e8f8b
MC		 4031
4032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033 tw32_f(MAC_MODE, tp->mac_mode);
4034 udelay(40);
4035
4036 tw32(MAC_EVENT, 0);
4037
4038 tw32_f(MAC_STATUS,
4039 (MAC_STATUS_SYNC_CHANGED |
4040 MAC_STATUS_CFG_CHANGED |
4041 MAC_STATUS_MI_COMPLETION |
4042 MAC_STATUS_LNKSTATE_CHANGED));
4043 udelay(40);
4044
4045 if (force_reset)
4046 tg3_phy_reset(tp);
4047
4048 current_link_up = 0;
4049 current_speed = SPEED_INVALID;
4050 current_duplex = DUPLEX_INVALID;
4051
4052 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056 bmsr |= BMSR_LSTATUS;
4057 else
4058 bmsr &= ~BMSR_LSTATUS;
4059 }
747e8f8b
MC		 4060
4061 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4062
4063 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4064 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4065 /* do nothing, just check for link up at the end */
4066 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4067 u32 adv, new_adv;
4068
4069 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071 ADVERTISE_1000XPAUSE |
4072 ADVERTISE_1000XPSE_ASYM |
4073 ADVERTISE_SLCT);
4074
ba4d07a8 4075 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4076
4077 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078 new_adv |= ADVERTISE_1000XHALF;
4079 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080 new_adv |= ADVERTISE_1000XFULL;
4081
4082 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085 tg3_writephy(tp, MII_BMCR, bmcr);
4086
4087 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4088 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4089 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4090
4091 return err;
4092 }
4093 } else {
4094 u32 new_bmcr;
4095
4096 bmcr &= ~BMCR_SPEED1000;
4097 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4098
4099 if (tp->link_config.duplex == DUPLEX_FULL)
4100 new_bmcr |= BMCR_FULLDPLX;
4101
4102 if (new_bmcr != bmcr) {
4103 /* BMCR_SPEED1000 is a reserved bit that needs
4104 * to be set on write.
4105 */
4106 new_bmcr |= BMCR_SPEED1000;
4107
4108 /* Force a linkdown */
4109 if (netif_carrier_ok(tp->dev)) {
4110 u32 adv;
4111
4112 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113 adv &= ~(ADVERTISE_1000XFULL |
4114 ADVERTISE_1000XHALF |
4115 ADVERTISE_SLCT);
4116 tg3_writephy(tp, MII_ADVERTISE, adv);
4117 tg3_writephy(tp, MII_BMCR, bmcr |
4118 BMCR_ANRESTART |
4119 BMCR_ANENABLE);
4120 udelay(10);
4121 netif_carrier_off(tp->dev);
4122 }
4123 tg3_writephy(tp, MII_BMCR, new_bmcr);
4124 bmcr = new_bmcr;
4125 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4127 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4128 ASIC_REV_5714) {
4129 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130 bmsr |= BMSR_LSTATUS;
4131 else
4132 bmsr &= ~BMSR_LSTATUS;
4133 }
747e8f8b
MC		 4134 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135 }
4136 }
4137
4138 if (bmsr & BMSR_LSTATUS) {
4139 current_speed = SPEED_1000;
4140 current_link_up = 1;
4141 if (bmcr & BMCR_FULLDPLX)
4142 current_duplex = DUPLEX_FULL;
4143 else
4144 current_duplex = DUPLEX_HALF;
4145
ef167e27
MC		 4146 local_adv = 0;
4147 remote_adv = 0;
4148
747e8f8b 4149 if (bmcr & BMCR_ANENABLE) {
ef167e27 4150 u32 common;
747e8f8b
MC		 4151
4152 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154 common = local_adv & remote_adv;
4155 if (common & (ADVERTISE_1000XHALF |
4156 ADVERTISE_1000XFULL)) {
4157 if (common & ADVERTISE_1000XFULL)
4158 current_duplex = DUPLEX_FULL;
4159 else
4160 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4161 }
4162 else
4163 current_link_up = 0;
4164 }
4165 }
4166
ef167e27
MC		 4167 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168 tg3_setup_flow_control(tp, local_adv, remote_adv);
4169
747e8f8b
MC		 4170 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171 if (tp->link_config.active_duplex == DUPLEX_HALF)
4172 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4173
4174 tw32_f(MAC_MODE, tp->mac_mode);
4175 udelay(40);
4176
4177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4178
4179 tp->link_config.active_speed = current_speed;
4180 tp->link_config.active_duplex = current_duplex;
4181
4182 if (current_link_up != netif_carrier_ok(tp->dev)) {
4183 if (current_link_up)
4184 netif_carrier_on(tp->dev);
4185 else {
4186 netif_carrier_off(tp->dev);
4187 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188 }
4189 tg3_link_report(tp);
4190 }
4191 return err;
4192}
4193
4194static void tg3_serdes_parallel_detect(struct tg3 *tp)
4195{
3d3ebe74 4196 if (tp->serdes_counter) {
747e8f8b 4197 /* Give autoneg time to complete. */
3d3ebe74 4198 tp->serdes_counter--;
747e8f8b
MC		 4199 return;
4200 }
4201 if (!netif_carrier_ok(tp->dev) &&
4202 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4203 u32 bmcr;
4204
4205 tg3_readphy(tp, MII_BMCR, &bmcr);
4206 if (bmcr & BMCR_ANENABLE) {
4207 u32 phy1, phy2;
4208
4209 /* Select shadow register 0x1f */
4210 tg3_writephy(tp, 0x1c, 0x7c00);
4211 tg3_readphy(tp, 0x1c, &phy1);
4212
4213 /* Select expansion interrupt status register */
4214 tg3_writephy(tp, 0x17, 0x0f01);
4215 tg3_readphy(tp, 0x15, &phy2);
4216 tg3_readphy(tp, 0x15, &phy2);
4217
4218 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219 /* We have signal detect and not receiving
4220 * config code words, link is up by parallel
4221 * detection.
4222 */
4223
4224 bmcr &= ~BMCR_ANENABLE;
4225 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226 tg3_writephy(tp, MII_BMCR, bmcr);
4227 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4228 }
4229 }
4230 }
4231 else if (netif_carrier_ok(tp->dev) &&
4232 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4234 u32 phy2;
4235
4236 /* Select expansion interrupt status register */
4237 tg3_writephy(tp, 0x17, 0x0f01);
4238 tg3_readphy(tp, 0x15, &phy2);
4239 if (phy2 & 0x20) {
4240 u32 bmcr;
4241
4242 /* Config code words received, turn on autoneg. */
4243 tg3_readphy(tp, MII_BMCR, &bmcr);
4244 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4245
4246 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4247
4248 }
4249 }
4250}
4251
1da177e4
LT		 4252static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4253{
4254 int err;
4255
4256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4258 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4260 } else {
4261 err = tg3_setup_copper_phy(tp, force_reset);
4262 }
4263
bcb37f6c 4264 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4265 u32 val, scale;
4266
4267 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4269 scale = 65;
4270 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4271 scale = 6;
4272 else
4273 scale = 12;
4274
4275 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277 tw32(GRC_MISC_CFG, val);
4278 }
4279
1da177e4
LT		 4280 if (tp->link_config.active_speed == SPEED_1000 &&
4281 tp->link_config.active_duplex == DUPLEX_HALF)
4282 tw32(MAC_TX_LENGTHS,
4283 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284 (6 << TX_LENGTHS_IPG_SHIFT) |
4285 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4286 else
4287 tw32(MAC_TX_LENGTHS,
4288 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289 (6 << TX_LENGTHS_IPG_SHIFT) |
4290 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4291
4292 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293 if (netif_carrier_ok(tp->dev)) {
4294 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4295 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4296 } else {
4297 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4298 }
4299 }
4300
8ed5d97e
MC		 4301 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303 if (!netif_carrier_ok(tp->dev))
4304 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4305 tp->pwrmgmt_thresh;
4306 else
4307 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308 tw32(PCIE_PWR_MGMT_THRESH, val);
4309 }
4310
1da177e4
LT		 4311 return err;
4312}
4313
df3e6548
MC		 4314/* This is called whenever we suspect that the system chipset is re-
4315 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316 * is bogus tx completions. We try to recover by setting the
4317 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318 * in the workqueue.
4319 */
4320static void tg3_tx_recover(struct tg3 *tp)
4321{
4322 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4324
4325 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326 "mapped I/O cycles to the network device, attempting to "
4327 "recover. Please report the problem to the driver maintainer "
4328 "and include system chipset information.\n", tp->dev->name);
4329
4330 spin_lock(&tp->lock);
df3e6548 4331 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4332 spin_unlock(&tp->lock);
4333}
4334
f3f3f27e 4335static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4336{
4337 smp_mb();
f3f3f27e
MC		 4338 return tnapi->tx_pending -
4339 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4340}
4341
1da177e4
LT		 4342/* Tigon3 never reports partial packet sends. So we do not
4343 * need special logic to handle SKBs that have not had all
4344 * of their frags sent yet, like SunGEM does.
4345 */
17375d25 4346static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4347{
17375d25 4348 struct tg3 *tp = tnapi->tp;
898a56f8 4349 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4350 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4351 struct netdev_queue *txq;
4352 int index = tnapi - tp->napi;
4353
19cfaecc 4354 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4355 index--;
4356
4357 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4358
4359 while (sw_idx != hw_idx) {
f4188d8a 4360 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4361 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4362 int i, tx_bug = 0;
4363
4364 if (unlikely(skb == NULL)) {
4365 tg3_tx_recover(tp);
4366 return;
4367 }
1da177e4 4368
f4188d8a
AD		 4369 pci_unmap_single(tp->pdev,
4370 pci_unmap_addr(ri, mapping),
4371 skb_headlen(skb),
4372 PCI_DMA_TODEVICE);
1da177e4
LT		 4373
4374 ri->skb = NULL;
4375
4376 sw_idx = NEXT_TX(sw_idx);
4377
4378 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4379 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4380 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4381 tx_bug = 1;
f4188d8a
AD		 4382
4383 pci_unmap_page(tp->pdev,
4384 pci_unmap_addr(ri, mapping),
4385 skb_shinfo(skb)->frags[i].size,
4386 PCI_DMA_TODEVICE);
1da177e4
LT		 4387 sw_idx = NEXT_TX(sw_idx);
4388 }
4389
f47c11ee 4390 dev_kfree_skb(skb);
df3e6548
MC		 4391
4392 if (unlikely(tx_bug)) {
4393 tg3_tx_recover(tp);
4394 return;
4395 }
1da177e4
LT		 4396 }
4397
f3f3f27e 4398 tnapi->tx_cons = sw_idx;
1da177e4 4399
1b2a7205
MC		 4400 /* Need to make the tx_cons update visible to tg3_start_xmit()
4401 * before checking for netif_queue_stopped(). Without the
4402 * memory barrier, there is a small possibility that tg3_start_xmit()
4403 * will miss it and cause the queue to be stopped forever.
4404 */
4405 smp_mb();
4406
fe5f5787 4407 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4408 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4409 __netif_tx_lock(txq, smp_processor_id());
4410 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4411 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4412 netif_tx_wake_queue(txq);
4413 __netif_tx_unlock(txq);
51b91468 4414 }
1da177e4
LT		 4415}
4416
2b2cdb65
MC		 4417static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4418{
4419 if (!ri->skb)
4420 return;
4421
4422 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423 map_sz, PCI_DMA_FROMDEVICE);
4424 dev_kfree_skb_any(ri->skb);
4425 ri->skb = NULL;
4426}
4427
1da177e4
LT		 4428/* Returns size of skb allocated or < 0 on error.
4429 *
4430 * We only need to fill in the address because the other members
4431 * of the RX descriptor are invariant, see tg3_init_rings.
4432 *
4433 * Note the purposeful assymetry of cpu vs. chip accesses. For
4434 * posting buffers we only dirty the first cache line of the RX
4435 * descriptor (containing the address). Whereas for the RX status
4436 * buffers the cpu only reads the last cacheline of the RX descriptor
4437 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4438 */
86b21e59 4439static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4440 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4441{
4442 struct tg3_rx_buffer_desc *desc;
4443 struct ring_info *map, *src_map;
4444 struct sk_buff *skb;
4445 dma_addr_t mapping;
4446 int skb_size, dest_idx;
4447
4448 src_map = NULL;
4449 switch (opaque_key) {
4450 case RXD_OPAQUE_RING_STD:
4451 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4452 desc = &tpr->rx_std[dest_idx];
4453 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4454 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4455 break;
4456
4457 case RXD_OPAQUE_RING_JUMBO:
4458 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4459 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4460 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4461 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4462 break;
4463
4464 default:
4465 return -EINVAL;
855e1111 4466 }
1da177e4
LT		 4467
4468 /* Do not overwrite any of the map or rp information
4469 * until we are sure we can commit to a new buffer.
4470 *
4471 * Callers depend upon this behavior and assume that
4472 * we leave everything unchanged if we fail.
4473 */
287be12e 4474 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4475 if (skb == NULL)
4476 return -ENOMEM;
4477
1da177e4
LT		 4478 skb_reserve(skb, tp->rx_offset);
4479
287be12e 4480 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4481 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4482 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4483 dev_kfree_skb(skb);
4484 return -EIO;
4485 }
1da177e4
LT		 4486
4487 map->skb = skb;
4488 pci_unmap_addr_set(map, mapping, mapping);
4489
1da177e4
LT		 4490 desc->addr_hi = ((u64)mapping >> 32);
4491 desc->addr_lo = ((u64)mapping & 0xffffffff);
4492
4493 return skb_size;
4494}
4495
4496/* We only need to move over in the address because the other
4497 * members of the RX descriptor are invariant. See notes above
4498 * tg3_alloc_rx_skb for full details.
4499 */
a3896167
MC		 4500static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501 struct tg3_rx_prodring_set *dpr,
4502 u32 opaque_key, int src_idx,
4503 u32 dest_idx_unmasked)
1da177e4 4504{
17375d25 4505 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4506 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507 struct ring_info *src_map, *dest_map;
4508 int dest_idx;
a3896167 4509 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4510
4511 switch (opaque_key) {
4512 case RXD_OPAQUE_RING_STD:
4513 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4514 dest_desc = &dpr->rx_std[dest_idx];
4515 dest_map = &dpr->rx_std_buffers[dest_idx];
4516 src_desc = &spr->rx_std[src_idx];
4517 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4518 break;
4519
4520 case RXD_OPAQUE_RING_JUMBO:
4521 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4522 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524 src_desc = &spr->rx_jmb[src_idx].std;
4525 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4526 break;
4527
4528 default:
4529 return;
855e1111 4530 }
1da177e4
LT		 4531
4532 dest_map->skb = src_map->skb;
4533 pci_unmap_addr_set(dest_map, mapping,
4534 pci_unmap_addr(src_map, mapping));
4535 dest_desc->addr_hi = src_desc->addr_hi;
4536 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4537 src_map->skb = NULL;
4538}
4539
1da177e4
LT		 4540/* The RX ring scheme is composed of multiple rings which post fresh
4541 * buffers to the chip, and one special ring the chip uses to report
4542 * status back to the host.
4543 *
4544 * The special ring reports the status of received packets to the
4545 * host. The chip does not write into the original descriptor the
4546 * RX buffer was obtained from. The chip simply takes the original
4547 * descriptor as provided by the host, updates the status and length
4548 * field, then writes this into the next status ring entry.
4549 *
4550 * Each ring the host uses to post buffers to the chip is described
4551 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4552 * it is first placed into the on-chip ram. When the packet's length
4553 * is known, it walks down the TG3_BDINFO entries to select the ring.
4554 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555 * which is within the range of the new packet's length is chosen.
4556 *
4557 * The "separate ring for rx status" scheme may sound queer, but it makes
4558 * sense from a cache coherency perspective. If only the host writes
4559 * to the buffer post rings, and only the chip writes to the rx status
4560 * rings, then cache lines never move beyond shared-modified state.
4561 * If both the host and chip were to write into the same ring, cache line
4562 * eviction could occur since both entities want it in an exclusive state.
4563 */
17375d25 4564static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4565{
17375d25 4566 struct tg3 *tp = tnapi->tp;
f92905de 4567 u32 work_mask, rx_std_posted = 0;
4361935a 4568 u32 std_prod_idx, jmb_prod_idx;
72334482 4569 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4570 u16 hw_idx;
1da177e4 4571 int received;
b196c7e4 4572 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4573
8d9d7cfc 4574 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4575 /*
4576 * We need to order the read of hw_idx and the read of
4577 * the opaque cookie.
4578 */
4579 rmb();
1da177e4
LT		 4580 work_mask = 0;
4581 received = 0;
4361935a
MC		 4582 std_prod_idx = tpr->rx_std_prod_idx;
4583 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4584 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4585 struct ring_info *ri;
72334482 4586 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4587 unsigned int len;
4588 struct sk_buff *skb;
4589 dma_addr_t dma_addr;
4590 u32 opaque_key, desc_idx, *post_ptr;
4591
4592 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4595 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4596 dma_addr = pci_unmap_addr(ri, mapping);
4597 skb = ri->skb;
4361935a 4598 post_ptr = &std_prod_idx;
f92905de 4599 rx_std_posted++;
1da177e4 4600 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4601 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4602 dma_addr = pci_unmap_addr(ri, mapping);
4603 skb = ri->skb;
4361935a 4604 post_ptr = &jmb_prod_idx;
21f581a5 4605 } else
1da177e4 4606 goto next_pkt_nopost;
1da177e4
LT		 4607
4608 work_mask |= opaque_key;
4609
4610 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4612 drop_it:
a3896167 4613 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4614 desc_idx, *post_ptr);
4615 drop_it_no_recycle:
4616 /* Other statistics kept track of by card. */
4617 tp->net_stats.rx_dropped++;
4618 goto next_pkt;
4619 }
4620
ad829268
MC		 4621 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4622 ETH_FCS_LEN;
1da177e4 4623
8e95a202
JP		 4624 if (len > RX_COPY_THRESHOLD &&
4625 tp->rx_offset == NET_IP_ALIGN) {
4626 /* rx_offset will likely not equal NET_IP_ALIGN
4627 * if this is a 5701 card running in PCI-X mode
4628 * [see tg3_get_invariants()]
4629 */
1da177e4
LT		 4630 int skb_size;
4631
86b21e59 4632 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4633 *post_ptr);
1da177e4
LT		 4634 if (skb_size < 0)
4635 goto drop_it;
4636
afc081f8
MC		 4637 ri->skb = NULL;
4638
287be12e 4639 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4640 PCI_DMA_FROMDEVICE);
4641
4642 skb_put(skb, len);
4643 } else {
4644 struct sk_buff *copy_skb;
4645
a3896167 4646 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4647 desc_idx, *post_ptr);
4648
ad829268
MC		 4649 copy_skb = netdev_alloc_skb(tp->dev,
4650 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4651 if (copy_skb == NULL)
4652 goto drop_it_no_recycle;
4653
ad829268 4654 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4655 skb_put(copy_skb, len);
4656 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4657 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4658 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4659
4660 /* We'll reuse the original ring buffer. */
4661 skb = copy_skb;
4662 }
4663
4664 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4665 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4666 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4667 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4668 skb->ip_summed = CHECKSUM_UNNECESSARY;
4669 else
4670 skb->ip_summed = CHECKSUM_NONE;
4671
4672 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4673
4674 if (len > (tp->dev->mtu + ETH_HLEN) &&
4675 skb->protocol != htons(ETH_P_8021Q)) {
4676 dev_kfree_skb(skb);
4677 goto next_pkt;
4678 }
4679
1da177e4
LT		 4680#if TG3_VLAN_TAG_USED
4681 if (tp->vlgrp != NULL &&
4682 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4683 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4684 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4685 } else
4686#endif
17375d25 4687 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4688
1da177e4
LT		 4689 received++;
4690 budget--;
4691
4692next_pkt:
4693 (*post_ptr)++;
f92905de
MC		 4694
4695 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4696 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
66711e66 4697 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
f92905de
MC		 4698 work_mask &= ~RXD_OPAQUE_RING_STD;
4699 rx_std_posted = 0;
4700 }
1da177e4 4701next_pkt_nopost:
483ba50b 4702 sw_idx++;
6b31a515 4703 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4704
4705 /* Refresh hw_idx to see if there is new work */
4706 if (sw_idx == hw_idx) {
8d9d7cfc 4707 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4708 rmb();
4709 }
1da177e4
LT		 4710 }
4711
4712 /* ACK the status ring. */
72334482
MC		 4713 tnapi->rx_rcb_ptr = sw_idx;
4714 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4715
4716 /* Refill RX ring(s). */
b196c7e4
MC		 4717 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4718 if (work_mask & RXD_OPAQUE_RING_STD) {
4719 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721 tpr->rx_std_prod_idx);
4722 }
4723 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4724 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4725 TG3_RX_JUMBO_RING_SIZE;
4726 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4727 tpr->rx_jmb_prod_idx);
4728 }
4729 mmiowb();
4730 } else if (work_mask) {
4731 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4732 * updated before the producer indices can be updated.
4733 */
4734 smp_wmb();
4735
4361935a 4736 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4737 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4
MC		 4738
4739 napi_schedule(&tp->napi[1].napi);
1da177e4 4740 }
1da177e4
LT		 4741
4742 return received;
4743}
4744
35f2d7d0 4745static void tg3_poll_link(struct tg3 *tp)
1da177e4 4746{
1da177e4
LT		 4747 /* handle link change and other phy events */
4748 if (!(tp->tg3_flags &
4749 (TG3_FLAG_USE_LINKCHG_REG |
4750 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4751 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4752
1da177e4
LT		 4753 if (sblk->status & SD_STATUS_LINK_CHG) {
4754 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4755 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4756 spin_lock(&tp->lock);
dd477003
MC		 4757 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4758 tw32_f(MAC_STATUS,
4759 (MAC_STATUS_SYNC_CHANGED |
4760 MAC_STATUS_CFG_CHANGED |
4761 MAC_STATUS_MI_COMPLETION |
4762 MAC_STATUS_LNKSTATE_CHANGED));
4763 udelay(40);
4764 } else
4765 tg3_setup_phy(tp, 0);
f47c11ee 4766 spin_unlock(&tp->lock);
1da177e4
LT		 4767 }
4768 }
35f2d7d0
MC		 4769}
4770
b196c7e4
MC		 4771static void tg3_rx_prodring_xfer(struct tg3 *tp,
4772 struct tg3_rx_prodring_set *dpr,
4773 struct tg3_rx_prodring_set *spr)
4774{
4775 u32 si, di, cpycnt, src_prod_idx;
4776 int i;
4777
4778 while (1) {
4779 src_prod_idx = spr->rx_std_prod_idx;
4780
4781 /* Make sure updates to the rx_std_buffers[] entries and the
4782 * standard producer index are seen in the correct order.
4783 */
4784 smp_rmb();
4785
4786 if (spr->rx_std_cons_idx == src_prod_idx)
4787 break;
4788
4789 if (spr->rx_std_cons_idx < src_prod_idx)
4790 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4791 else
4792 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4793
4794 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4795
4796 si = spr->rx_std_cons_idx;
4797 di = dpr->rx_std_prod_idx;
4798
4799 memcpy(&dpr->rx_std_buffers[di],
4800 &spr->rx_std_buffers[si],
4801 cpycnt * sizeof(struct ring_info));
4802
4803 for (i = 0; i < cpycnt; i++, di++, si++) {
4804 struct tg3_rx_buffer_desc *sbd, *dbd;
4805 sbd = &spr->rx_std[si];
4806 dbd = &dpr->rx_std[di];
4807 dbd->addr_hi = sbd->addr_hi;
4808 dbd->addr_lo = sbd->addr_lo;
4809 }
4810
4811 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4812 TG3_RX_RING_SIZE;
4813 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4814 TG3_RX_RING_SIZE;
4815 }
4816
4817 while (1) {
4818 src_prod_idx = spr->rx_jmb_prod_idx;
4819
4820 /* Make sure updates to the rx_jmb_buffers[] entries and
4821 * the jumbo producer index are seen in the correct order.
4822 */
4823 smp_rmb();
4824
4825 if (spr->rx_jmb_cons_idx == src_prod_idx)
4826 break;
4827
4828 if (spr->rx_jmb_cons_idx < src_prod_idx)
4829 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4830 else
4831 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4832
4833 cpycnt = min(cpycnt,
4834 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4835
4836 si = spr->rx_jmb_cons_idx;
4837 di = dpr->rx_jmb_prod_idx;
4838
4839 memcpy(&dpr->rx_jmb_buffers[di],
4840 &spr->rx_jmb_buffers[si],
4841 cpycnt * sizeof(struct ring_info));
4842
4843 for (i = 0; i < cpycnt; i++, di++, si++) {
4844 struct tg3_rx_buffer_desc *sbd, *dbd;
4845 sbd = &spr->rx_jmb[si].std;
4846 dbd = &dpr->rx_jmb[di].std;
4847 dbd->addr_hi = sbd->addr_hi;
4848 dbd->addr_lo = sbd->addr_lo;
4849 }
4850
4851 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4852 TG3_RX_JUMBO_RING_SIZE;
4853 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4854 TG3_RX_JUMBO_RING_SIZE;
4855 }
4856}
4857
35f2d7d0
MC		 4858static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4859{
4860 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4861
4862 /* run TX completion thread */
f3f3f27e 4863 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4864 tg3_tx(tnapi);
6f535763 4865 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4866 return work_done;
1da177e4
LT		 4867 }
4868
1da177e4
LT		 4869 /* run RX thread, within the bounds set by NAPI.
4870 * All RX "locking" is done by ensuring outside
bea3348e 4871 * code synchronizes with tg3->napi.poll()
1da177e4 4872 */
8d9d7cfc 4873 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4874 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4875
b196c7e4
MC		 4876 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4877 int i;
4878 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4879 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4880
4881 for (i = 2; i < tp->irq_cnt; i++)
4882 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4883 tp->napi[i].prodring);
4884
4885 wmb();
4886
4887 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4888 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4889 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4890 }
4891
4892 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4893 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4894 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4895 }
4896
4897 mmiowb();
4898 }
4899
6f535763
DM		 4900 return work_done;
4901}
4902
35f2d7d0
MC		 4903static int tg3_poll_msix(struct napi_struct *napi, int budget)
4904{
4905 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4906 struct tg3 *tp = tnapi->tp;
4907 int work_done = 0;
4908 struct tg3_hw_status *sblk = tnapi->hw_status;
4909
4910 while (1) {
4911 work_done = tg3_poll_work(tnapi, work_done, budget);
4912
4913 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4914 goto tx_recovery;
4915
4916 if (unlikely(work_done >= budget))
4917 break;
4918
4919 /* tp->last_tag is used in tg3_restart_ints() below
4920 * to tell the hw how much work has been processed,
4921 * so we must read it before checking for more work.
4922 */
4923 tnapi->last_tag = sblk->status_tag;
4924 tnapi->last_irq_tag = tnapi->last_tag;
4925 rmb();
4926
4927 /* check for RX/TX work to do */
4928 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4929 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4930 napi_complete(napi);
4931 /* Reenable interrupts. */
4932 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4933 mmiowb();
4934 break;
4935 }
4936 }
4937
4938 return work_done;
4939
4940tx_recovery:
4941 /* work_done is guaranteed to be less than budget. */
4942 napi_complete(napi);
4943 schedule_work(&tp->reset_task);
4944 return work_done;
4945}
4946
6f535763
DM		 4947static int tg3_poll(struct napi_struct *napi, int budget)
4948{
8ef0442f
MC		 4949 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4950 struct tg3 *tp = tnapi->tp;
6f535763 4951 int work_done = 0;
898a56f8 4952 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4953
4954 while (1) {
35f2d7d0
MC		 4955 tg3_poll_link(tp);
4956
17375d25 4957 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4958
4959 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4960 goto tx_recovery;
4961
4962 if (unlikely(work_done >= budget))
4963 break;
4964
4fd7ab59 4965 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4966 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4967 * to tell the hw how much work has been processed,
4968 * so we must read it before checking for more work.
4969 */
898a56f8
MC		 4970 tnapi->last_tag = sblk->status_tag;
4971 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4972 rmb();
4973 } else
4974 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4975
17375d25 4976 if (likely(!tg3_has_work(tnapi))) {
288379f0 4977 napi_complete(napi);
17375d25 4978 tg3_int_reenable(tnapi);
6f535763
DM		 4979 break;
4980 }
1da177e4
LT		 4981 }
4982
bea3348e 4983 return work_done;
6f535763
DM		 4984
4985tx_recovery:
4fd7ab59 4986 /* work_done is guaranteed to be less than budget. */
288379f0 4987 napi_complete(napi);
6f535763 4988 schedule_work(&tp->reset_task);
4fd7ab59 4989 return work_done;
1da177e4
LT		 4990}
4991
f47c11ee
DM		 4992static void tg3_irq_quiesce(struct tg3 *tp)
4993{
4f125f42
MC		 4994 int i;
4995
f47c11ee
DM		 4996 BUG_ON(tp->irq_sync);
4997
4998 tp->irq_sync = 1;
4999 smp_mb();
5000
4f125f42
MC		 5001 for (i = 0; i < tp->irq_cnt; i++)
5002 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5003}
5004
5005static inline int tg3_irq_sync(struct tg3 *tp)
5006{
5007 return tp->irq_sync;
5008}
5009
5010/* Fully shutdown all tg3 driver activity elsewhere in the system.
5011 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5012 * with as well. Most of the time, this is not necessary except when
5013 * shutting down the device.
5014 */
5015static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5016{
46966545 5017 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5018 if (irq_sync)
5019 tg3_irq_quiesce(tp);
f47c11ee
DM		 5020}
5021
5022static inline void tg3_full_unlock(struct tg3 *tp)
5023{
f47c11ee
DM		 5024 spin_unlock_bh(&tp->lock);
5025}
5026
fcfa0a32
MC		 5027/* One-shot MSI handler - Chip automatically disables interrupt
5028 * after sending MSI so driver doesn't have to do it.
5029 */
7d12e780 5030static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5031{
09943a18
MC		 5032 struct tg3_napi *tnapi = dev_id;
5033 struct tg3 *tp = tnapi->tp;
fcfa0a32 5034
898a56f8 5035 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5036 if (tnapi->rx_rcb)
5037 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5038
5039 if (likely(!tg3_irq_sync(tp)))
09943a18 5040 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5041
5042 return IRQ_HANDLED;
5043}
5044
88b06bc2
MC		 5045/* MSI ISR - No need to check for interrupt sharing and no need to
5046 * flush status block and interrupt mailbox. PCI ordering rules
5047 * guarantee that MSI will arrive after the status block.
5048 */
7d12e780 5049static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5050{
09943a18
MC		 5051 struct tg3_napi *tnapi = dev_id;
5052 struct tg3 *tp = tnapi->tp;
88b06bc2 5053
898a56f8 5054 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5055 if (tnapi->rx_rcb)
5056 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5057 /*
fac9b83e 5058 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5059 * chip-internal interrupt pending events.
fac9b83e 5060 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5061 * NIC to stop sending us irqs, engaging "in-intr-handler"
5062 * event coalescing.
5063 */
5064 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5065 if (likely(!tg3_irq_sync(tp)))
09943a18 5066 napi_schedule(&tnapi->napi);
61487480 5067
88b06bc2
MC		 5068 return IRQ_RETVAL(1);
5069}
5070
7d12e780 5071static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5072{
09943a18
MC		 5073 struct tg3_napi *tnapi = dev_id;
5074 struct tg3 *tp = tnapi->tp;
898a56f8 5075 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5076 unsigned int handled = 1;
5077
1da177e4
LT		 5078 /* In INTx mode, it is possible for the interrupt to arrive at
5079 * the CPU before the status block posted prior to the interrupt.
5080 * Reading the PCI State register will confirm whether the
5081 * interrupt is ours and will flush the status block.
5082 */
d18edcb2
MC		 5083 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5084 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5085 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5086 handled = 0;
f47c11ee 5087 goto out;
fac9b83e 5088 }
d18edcb2
MC		 5089 }
5090
5091 /*
5092 * Writing any value to intr-mbox-0 clears PCI INTA# and
5093 * chip-internal interrupt pending events.
5094 * Writing non-zero to intr-mbox-0 additional tells the
5095 * NIC to stop sending us irqs, engaging "in-intr-handler"
5096 * event coalescing.
c04cb347
MC		 5097 *
5098 * Flush the mailbox to de-assert the IRQ immediately to prevent
5099 * spurious interrupts. The flush impacts performance but
5100 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5101 */
c04cb347 5102 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5103 if (tg3_irq_sync(tp))
5104 goto out;
5105 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5106 if (likely(tg3_has_work(tnapi))) {
72334482 5107 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5108 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5109 } else {
5110 /* No work, shared interrupt perhaps? re-enable
5111 * interrupts, and flush that PCI write
5112 */
5113 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5114 0x00000000);
fac9b83e 5115 }
f47c11ee 5116out:
fac9b83e
DM		 5117 return IRQ_RETVAL(handled);
5118}
5119
7d12e780 5120static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5121{
09943a18
MC		 5122 struct tg3_napi *tnapi = dev_id;
5123 struct tg3 *tp = tnapi->tp;
898a56f8 5124 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5125 unsigned int handled = 1;
5126
fac9b83e
DM		 5127 /* In INTx mode, it is possible for the interrupt to arrive at
5128 * the CPU before the status block posted prior to the interrupt.
5129 * Reading the PCI State register will confirm whether the
5130 * interrupt is ours and will flush the status block.
5131 */
898a56f8 5132 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5133 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5134 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5135 handled = 0;
f47c11ee 5136 goto out;
1da177e4 5137 }
d18edcb2
MC		 5138 }
5139
5140 /*
5141 * writing any value to intr-mbox-0 clears PCI INTA# and
5142 * chip-internal interrupt pending events.
5143 * writing non-zero to intr-mbox-0 additional tells the
5144 * NIC to stop sending us irqs, engaging "in-intr-handler"
5145 * event coalescing.
c04cb347
MC		 5146 *
5147 * Flush the mailbox to de-assert the IRQ immediately to prevent
5148 * spurious interrupts. The flush impacts performance but
5149 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5150 */
c04cb347 5151 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5152
5153 /*
5154 * In a shared interrupt configuration, sometimes other devices'
5155 * interrupts will scream. We record the current status tag here
5156 * so that the above check can report that the screaming interrupts
5157 * are unhandled. Eventually they will be silenced.
5158 */
898a56f8 5159 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5160
d18edcb2
MC		 5161 if (tg3_irq_sync(tp))
5162 goto out;
624f8e50 5163
72334482 5164 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5165
09943a18 5166 napi_schedule(&tnapi->napi);
624f8e50 5167
f47c11ee 5168out:
1da177e4
LT		 5169 return IRQ_RETVAL(handled);
5170}
5171
7938109f 5172/* ISR for interrupt test */
7d12e780 5173static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5174{
09943a18
MC		 5175 struct tg3_napi *tnapi = dev_id;
5176 struct tg3 *tp = tnapi->tp;
898a56f8 5177 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5178
f9804ddb
MC		 5179 if ((sblk->status & SD_STATUS_UPDATED) ||
5180 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5181 tg3_disable_ints(tp);
7938109f
MC		 5182 return IRQ_RETVAL(1);
5183 }
5184 return IRQ_RETVAL(0);
5185}
5186
8e7a22e3 5187static int tg3_init_hw(struct tg3 *, int);
944d980e 5188static int tg3_halt(struct tg3 *, int, int);
1da177e4 5189
b9ec6c1b
MC		 5190/* Restart hardware after configuration changes, self-test, etc.
5191 * Invoked with tp->lock held.
5192 */
5193static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5194 __releases(tp->lock)
5195 __acquires(tp->lock)
b9ec6c1b
MC		 5196{
5197 int err;
5198
5199 err = tg3_init_hw(tp, reset_phy);
5200 if (err) {
5201 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5202 "aborting.\n", tp->dev->name);
5203 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5204 tg3_full_unlock(tp);
5205 del_timer_sync(&tp->timer);
5206 tp->irq_sync = 0;
fed97810 5207 tg3_napi_enable(tp);
b9ec6c1b
MC		 5208 dev_close(tp->dev);
5209 tg3_full_lock(tp, 0);
5210 }
5211 return err;
5212}
5213
1da177e4
LT		 5214#ifdef CONFIG_NET_POLL_CONTROLLER
5215static void tg3_poll_controller(struct net_device *dev)
5216{
4f125f42 5217 int i;
88b06bc2
MC		 5218 struct tg3 *tp = netdev_priv(dev);
5219
4f125f42
MC		 5220 for (i = 0; i < tp->irq_cnt; i++)
5221 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5222}
5223#endif
5224
c4028958 5225static void tg3_reset_task(struct work_struct *work)
1da177e4 5226{
c4028958 5227 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5228 int err;
1da177e4
LT		 5229 unsigned int restart_timer;
5230
7faa006f 5231 tg3_full_lock(tp, 0);
7faa006f
MC		 5232
5233 if (!netif_running(tp->dev)) {
7faa006f
MC		 5234 tg3_full_unlock(tp);
5235 return;
5236 }
5237
5238 tg3_full_unlock(tp);
5239
b02fd9e3
MC		 5240 tg3_phy_stop(tp);
5241
1da177e4
LT		 5242 tg3_netif_stop(tp);
5243
f47c11ee 5244 tg3_full_lock(tp, 1);
1da177e4
LT		 5245
5246 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5247 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5248
df3e6548
MC		 5249 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5250 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5251 tp->write32_rx_mbox = tg3_write_flush_reg32;
5252 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5253 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5254 }
5255
944d980e 5256 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5257 err = tg3_init_hw(tp, 1);
5258 if (err)
b9ec6c1b 5259 goto out;
1da177e4
LT		 5260
5261 tg3_netif_start(tp);
5262
1da177e4
LT		 5263 if (restart_timer)
5264 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5265
b9ec6c1b 5266out:
7faa006f 5267 tg3_full_unlock(tp);
b02fd9e3
MC		 5268
5269 if (!err)
5270 tg3_phy_start(tp);
1da177e4
LT		 5271}
5272
b0408751
MC		 5273static void tg3_dump_short_state(struct tg3 *tp)
5274{
5275 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5276 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5277 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5278 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5279}
5280
1da177e4
LT		 5281static void tg3_tx_timeout(struct net_device *dev)
5282{
5283 struct tg3 *tp = netdev_priv(dev);
5284
b0408751 5285 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5286 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5287 dev->name);
b0408751
MC		 5288 tg3_dump_short_state(tp);
5289 }
1da177e4
LT		 5290
5291 schedule_work(&tp->reset_task);
5292}
5293
c58ec932
MC		 5294/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5295static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5296{
5297 u32 base = (u32) mapping & 0xffffffff;
5298
5299 return ((base > 0xffffdcc0) &&
5300 (base + len + 8 < base));
5301}
5302
72f2afb8
MC		 5303/* Test for DMA addresses > 40-bit */
5304static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5305 int len)
5306{
5307#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5308 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5309 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5310 return 0;
5311#else
5312 return 0;
5313#endif
5314}
5315
f3f3f27e 5316static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5317
72f2afb8 5318/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5319static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5320 struct sk_buff *skb, u32 last_plus_one,
5321 u32 *start, u32 base_flags, u32 mss)
1da177e4 5322{
24f4efd4 5323 struct tg3 *tp = tnapi->tp;
41588ba1 5324 struct sk_buff *new_skb;
c58ec932 5325 dma_addr_t new_addr = 0;
1da177e4 5326 u32 entry = *start;
c58ec932 5327 int i, ret = 0;
1da177e4 5328
41588ba1
MC		 5329 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5330 new_skb = skb_copy(skb, GFP_ATOMIC);
5331 else {
5332 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5333
5334 new_skb = skb_copy_expand(skb,
5335 skb_headroom(skb) + more_headroom,
5336 skb_tailroom(skb), GFP_ATOMIC);
5337 }
5338
1da177e4 5339 if (!new_skb) {
c58ec932
MC		 5340 ret = -1;
5341 } else {
5342 /* New SKB is guaranteed to be linear. */
5343 entry = *start;
f4188d8a
AD		 5344 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5345 PCI_DMA_TODEVICE);
5346 /* Make sure the mapping succeeded */
5347 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5348 ret = -1;
5349 dev_kfree_skb(new_skb);
5350 new_skb = NULL;
90079ce8 5351
c58ec932
MC		 5352 /* Make sure new skb does not cross any 4G boundaries.
5353 * Drop the packet if it does.
5354 */
f4188d8a
AD		 5355 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5356 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5357 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5358 PCI_DMA_TODEVICE);
c58ec932
MC		 5359 ret = -1;
5360 dev_kfree_skb(new_skb);
5361 new_skb = NULL;
5362 } else {
f3f3f27e 5363 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5364 base_flags, 1 | (mss << 1));
5365 *start = NEXT_TX(entry);
5366 }
1da177e4
LT		 5367 }
5368
1da177e4
LT		 5369 /* Now clean up the sw ring entries. */
5370 i = 0;
5371 while (entry != last_plus_one) {
f4188d8a
AD		 5372 int len;
5373
f3f3f27e 5374 if (i == 0)
f4188d8a 5375 len = skb_headlen(skb);
f3f3f27e 5376 else
f4188d8a
AD		 5377 len = skb_shinfo(skb)->frags[i-1].size;
5378
5379 pci_unmap_single(tp->pdev,
5380 pci_unmap_addr(&tnapi->tx_buffers[entry],
5381 mapping),
5382 len, PCI_DMA_TODEVICE);
5383 if (i == 0) {
5384 tnapi->tx_buffers[entry].skb = new_skb;
5385 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5386 new_addr);
5387 } else {
f3f3f27e 5388 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5389 }
1da177e4
LT		 5390 entry = NEXT_TX(entry);
5391 i++;
5392 }
5393
5394 dev_kfree_skb(skb);
5395
c58ec932 5396 return ret;
1da177e4
LT		 5397}
5398
f3f3f27e 5399static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5400 dma_addr_t mapping, int len, u32 flags,
5401 u32 mss_and_is_end)
5402{
f3f3f27e 5403 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5404 int is_end = (mss_and_is_end & 0x1);
5405 u32 mss = (mss_and_is_end >> 1);
5406 u32 vlan_tag = 0;
5407
5408 if (is_end)
5409 flags |= TXD_FLAG_END;
5410 if (flags & TXD_FLAG_VLAN) {
5411 vlan_tag = flags >> 16;
5412 flags &= 0xffff;
5413 }
5414 vlan_tag |= (mss << TXD_MSS_SHIFT);
5415
5416 txd->addr_hi = ((u64) mapping >> 32);
5417 txd->addr_lo = ((u64) mapping & 0xffffffff);
5418 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5419 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5420}
5421
5a6f3074 5422/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5423 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5424 */
61357325
SH		 5425static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5426 struct net_device *dev)
5a6f3074
MC		 5427{
5428 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5429 u32 len, entry, base_flags, mss;
90079ce8 5430 dma_addr_t mapping;
fe5f5787
MC		 5431 struct tg3_napi *tnapi;
5432 struct netdev_queue *txq;
f4188d8a
AD		 5433 unsigned int i, last;
5434
5a6f3074 5435
fe5f5787
MC		 5436 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5437 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5438 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5439 tnapi++;
5a6f3074 5440
00b70504 5441 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5442 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5443 * interrupt. Furthermore, IRQ processing runs lockless so we have
5444 * no IRQ context deadlocks to worry about either. Rejoice!
5445 */
f3f3f27e 5446 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5447 if (!netif_tx_queue_stopped(txq)) {
5448 netif_tx_stop_queue(txq);
5a6f3074
MC		 5449
5450 /* This is a hard error, log it. */
5451 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5452 "queue awake!\n", dev->name);
5453 }
5a6f3074
MC		 5454 return NETDEV_TX_BUSY;
5455 }
5456
f3f3f27e 5457 entry = tnapi->tx_prod;
5a6f3074 5458 base_flags = 0;
5a6f3074 5459 mss = 0;
c13e3713 5460 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5461 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5462 u32 hdrlen;
5a6f3074
MC		 5463
5464 if (skb_header_cloned(skb) &&
5465 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5466 dev_kfree_skb(skb);
5467 goto out_unlock;
5468 }
5469
b0026624 5470 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5471 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5472 else {
eddc9ec5
ACM		 5473 struct iphdr *iph = ip_hdr(skb);
5474
ab6a5bb6 5475 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5476 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5477
eddc9ec5
ACM		 5478 iph->check = 0;
5479 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5480 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5481 }
5a6f3074 5482
e849cdc3 5483 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5484 mss |= (hdrlen & 0xc) << 12;
5485 if (hdrlen & 0x10)
5486 base_flags |= 0x00000010;
5487 base_flags |= (hdrlen & 0x3e0) << 5;
5488 } else
5489 mss |= hdrlen << 9;
5490
5a6f3074
MC		 5491 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5492 TXD_FLAG_CPU_POST_DMA);
5493
aa8223c7 5494 tcp_hdr(skb)->check = 0;
5a6f3074 5495
5a6f3074 5496 }
84fa7933 5497 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5498 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5499#if TG3_VLAN_TAG_USED
5500 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5501 base_flags |= (TXD_FLAG_VLAN |
5502 (vlan_tx_tag_get(skb) << 16));
5503#endif
5504
f4188d8a
AD		 5505 len = skb_headlen(skb);
5506
5507 /* Queue skb data, a.k.a. the main skb fragment. */
5508 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5509 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5510 dev_kfree_skb(skb);
5511 goto out_unlock;
5512 }
5513
f3f3f27e 5514 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5515 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5516
b703df6f 5517 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5518 !mss && skb->len > ETH_DATA_LEN)
5519 base_flags |= TXD_FLAG_JMB_PKT;
5520
f3f3f27e 5521 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5522 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5523
5524 entry = NEXT_TX(entry);
5525
5526 /* Now loop through additional data fragments, and queue them. */
5527 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5528 last = skb_shinfo(skb)->nr_frags - 1;
5529 for (i = 0; i <= last; i++) {
5530 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5531
5532 len = frag->size;
f4188d8a
AD		 5533 mapping = pci_map_page(tp->pdev,
5534 frag->page,
5535 frag->page_offset,
5536 len, PCI_DMA_TODEVICE);
5537 if (pci_dma_mapping_error(tp->pdev, mapping))
5538 goto dma_error;
5539
f3f3f27e 5540 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5541 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5542 mapping);
5a6f3074 5543
f3f3f27e 5544 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5545 base_flags, (i == last) | (mss << 1));
5546
5547 entry = NEXT_TX(entry);
5548 }
5549 }
5550
5551 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5552 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5553
f3f3f27e
MC		 5554 tnapi->tx_prod = entry;
5555 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5556 netif_tx_stop_queue(txq);
f3f3f27e 5557 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5558 netif_tx_wake_queue(txq);
5a6f3074
MC		 5559 }
5560
5561out_unlock:
cdd0db05 5562 mmiowb();
5a6f3074
MC		 5563
5564 return NETDEV_TX_OK;
f4188d8a
AD		 5565
5566dma_error:
5567 last = i;
5568 entry = tnapi->tx_prod;
5569 tnapi->tx_buffers[entry].skb = NULL;
5570 pci_unmap_single(tp->pdev,
5571 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5572 skb_headlen(skb),
5573 PCI_DMA_TODEVICE);
5574 for (i = 0; i <= last; i++) {
5575 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5576 entry = NEXT_TX(entry);
5577
5578 pci_unmap_page(tp->pdev,
5579 pci_unmap_addr(&tnapi->tx_buffers[entry],
5580 mapping),
5581 frag->size, PCI_DMA_TODEVICE);
5582 }
5583
5584 dev_kfree_skb(skb);
5585 return NETDEV_TX_OK;
5a6f3074
MC		 5586}
5587
61357325
SH		 5588static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5589 struct net_device *);
52c0fd83
MC		 5590
5591/* Use GSO to workaround a rare TSO bug that may be triggered when the
5592 * TSO header is greater than 80 bytes.
5593 */
5594static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5595{
5596 struct sk_buff *segs, *nskb;
f3f3f27e 5597 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5598
5599 /* Estimate the number of fragments in the worst case */
f3f3f27e 5600 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5601 netif_stop_queue(tp->dev);
f3f3f27e 5602 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5603 return NETDEV_TX_BUSY;
5604
5605 netif_wake_queue(tp->dev);
52c0fd83
MC		 5606 }
5607
5608 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5609 if (IS_ERR(segs))
52c0fd83
MC		 5610 goto tg3_tso_bug_end;
5611
5612 do {
5613 nskb = segs;
5614 segs = segs->next;
5615 nskb->next = NULL;
5616 tg3_start_xmit_dma_bug(nskb, tp->dev);
5617 } while (segs);
5618
5619tg3_tso_bug_end:
5620 dev_kfree_skb(skb);
5621
5622 return NETDEV_TX_OK;
5623}
52c0fd83 5624
5a6f3074
MC		 5625/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5626 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5627 */
61357325
SH		 5628static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5629 struct net_device *dev)
1da177e4
LT		 5630{
5631 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5632 u32 len, entry, base_flags, mss;
5633 int would_hit_hwbug;
90079ce8 5634 dma_addr_t mapping;
24f4efd4
MC		 5635 struct tg3_napi *tnapi;
5636 struct netdev_queue *txq;
f4188d8a
AD		 5637 unsigned int i, last;
5638
1da177e4 5639
24f4efd4
MC		 5640 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5641 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5642 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5643 tnapi++;
1da177e4 5644
00b70504 5645 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5646 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5647 * interrupt. Furthermore, IRQ processing runs lockless so we have
5648 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5649 */
f3f3f27e 5650 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5651 if (!netif_tx_queue_stopped(txq)) {
5652 netif_tx_stop_queue(txq);
1f064a87
SH		 5653
5654 /* This is a hard error, log it. */
5655 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5656 "queue awake!\n", dev->name);
5657 }
1da177e4
LT		 5658 return NETDEV_TX_BUSY;
5659 }
5660
f3f3f27e 5661 entry = tnapi->tx_prod;
1da177e4 5662 base_flags = 0;
84fa7933 5663 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5664 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5665
c13e3713 5666 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5667 struct iphdr *iph;
92c6b8d1 5668 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5669
5670 if (skb_header_cloned(skb) &&
5671 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5672 dev_kfree_skb(skb);
5673 goto out_unlock;
5674 }
5675
ab6a5bb6 5676 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5677 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5678
52c0fd83
MC		 5679 hdr_len = ip_tcp_len + tcp_opt_len;
5680 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5681 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5682 return (tg3_tso_bug(tp, skb));
5683
1da177e4
LT		 5684 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5685 TXD_FLAG_CPU_POST_DMA);
5686
eddc9ec5
ACM		 5687 iph = ip_hdr(skb);
5688 iph->check = 0;
5689 iph->tot_len = htons(mss + hdr_len);
1da177e4 5690 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5691 tcp_hdr(skb)->check = 0;
1da177e4 5692 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5693 } else
5694 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5695 iph->daddr, 0,
5696 IPPROTO_TCP,
5697 0);
1da177e4 5698
615774fe
MC		 5699 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5700 mss |= (hdr_len & 0xc) << 12;
5701 if (hdr_len & 0x10)
5702 base_flags |= 0x00000010;
5703 base_flags |= (hdr_len & 0x3e0) << 5;
5704 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5705 mss |= hdr_len << 9;
5706 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5708 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5709 int tsflags;
5710
eddc9ec5 5711 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5712 mss |= (tsflags << 11);
5713 }
5714 } else {
eddc9ec5 5715 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5716 int tsflags;
5717
eddc9ec5 5718 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5719 base_flags |= tsflags << 12;
5720 }
5721 }
5722 }
1da177e4
LT		 5723#if TG3_VLAN_TAG_USED
5724 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5725 base_flags |= (TXD_FLAG_VLAN |
5726 (vlan_tx_tag_get(skb) << 16));
5727#endif
5728
b703df6f 5729 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5730 !mss && skb->len > ETH_DATA_LEN)
5731 base_flags |= TXD_FLAG_JMB_PKT;
5732
f4188d8a
AD		 5733 len = skb_headlen(skb);
5734
5735 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5736 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5737 dev_kfree_skb(skb);
5738 goto out_unlock;
5739 }
5740
f3f3f27e 5741 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5742 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5743
5744 would_hit_hwbug = 0;
5745
92c6b8d1
MC		 5746 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5747 would_hit_hwbug = 1;
5748
0e1406dd
MC		 5749 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5750 tg3_4g_overflow_test(mapping, len))
5751 would_hit_hwbug = 1;
5752
5753 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5754 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5755 would_hit_hwbug = 1;
0e1406dd
MC		 5756
5757 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5758 would_hit_hwbug = 1;
1da177e4 5759
f3f3f27e 5760 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5761 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5762
5763 entry = NEXT_TX(entry);
5764
5765 /* Now loop through additional data fragments, and queue them. */
5766 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5767 last = skb_shinfo(skb)->nr_frags - 1;
5768 for (i = 0; i <= last; i++) {
5769 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5770
5771 len = frag->size;
f4188d8a
AD		 5772 mapping = pci_map_page(tp->pdev,
5773 frag->page,
5774 frag->page_offset,
5775 len, PCI_DMA_TODEVICE);
1da177e4 5776
f3f3f27e 5777 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5778 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5779 mapping);
5780 if (pci_dma_mapping_error(tp->pdev, mapping))
5781 goto dma_error;
1da177e4 5782
92c6b8d1
MC		 5783 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5784 len <= 8)
5785 would_hit_hwbug = 1;
5786
0e1406dd
MC		 5787 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5788 tg3_4g_overflow_test(mapping, len))
c58ec932 5789 would_hit_hwbug = 1;
1da177e4 5790
0e1406dd
MC		 5791 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5792 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5793 would_hit_hwbug = 1;
5794
1da177e4 5795 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5796 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5797 base_flags, (i == last)|(mss << 1));
5798 else
f3f3f27e 5799 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5800 base_flags, (i == last));
5801
5802 entry = NEXT_TX(entry);
5803 }
5804 }
5805
5806 if (would_hit_hwbug) {
5807 u32 last_plus_one = entry;
5808 u32 start;
1da177e4 5809
c58ec932
MC		 5810 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5811 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5812
5813 /* If the workaround fails due to memory/mapping
5814 * failure, silently drop this packet.
5815 */
24f4efd4 5816 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5817 &start, base_flags, mss))
1da177e4
LT		 5818 goto out_unlock;
5819
5820 entry = start;
5821 }
5822
5823 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5824 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5825
f3f3f27e
MC		 5826 tnapi->tx_prod = entry;
5827 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5828 netif_tx_stop_queue(txq);
f3f3f27e 5829 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5830 netif_tx_wake_queue(txq);
51b91468 5831 }
1da177e4
LT		 5832
5833out_unlock:
cdd0db05 5834 mmiowb();
1da177e4
LT		 5835
5836 return NETDEV_TX_OK;
f4188d8a
AD		 5837
5838dma_error:
5839 last = i;
5840 entry = tnapi->tx_prod;
5841 tnapi->tx_buffers[entry].skb = NULL;
5842 pci_unmap_single(tp->pdev,
5843 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5844 skb_headlen(skb),
5845 PCI_DMA_TODEVICE);
5846 for (i = 0; i <= last; i++) {
5847 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5848 entry = NEXT_TX(entry);
5849
5850 pci_unmap_page(tp->pdev,
5851 pci_unmap_addr(&tnapi->tx_buffers[entry],
5852 mapping),
5853 frag->size, PCI_DMA_TODEVICE);
5854 }
5855
5856 dev_kfree_skb(skb);
5857 return NETDEV_TX_OK;
1da177e4
LT		 5858}
5859
5860static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5861 int new_mtu)
5862{
5863 dev->mtu = new_mtu;
5864
ef7f5ec0 5865 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5866 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5867 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5868 ethtool_op_set_tso(dev, 0);
5869 }
5870 else
5871 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5872 } else {
a4e2b347 5873 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5874 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5875 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5876 }
1da177e4
LT		 5877}
5878
5879static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5880{
5881 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5882 int err;
1da177e4
LT		 5883
5884 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5885 return -EINVAL;
5886
5887 if (!netif_running(dev)) {
5888 /* We'll just catch it later when the
5889 * device is up'd.
5890 */
5891 tg3_set_mtu(dev, tp, new_mtu);
5892 return 0;
5893 }
5894
b02fd9e3
MC		 5895 tg3_phy_stop(tp);
5896
1da177e4 5897 tg3_netif_stop(tp);
f47c11ee
DM		 5898
5899 tg3_full_lock(tp, 1);
1da177e4 5900
944d980e 5901 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5902
5903 tg3_set_mtu(dev, tp, new_mtu);
5904
b9ec6c1b 5905 err = tg3_restart_hw(tp, 0);
1da177e4 5906
b9ec6c1b
MC		 5907 if (!err)
5908 tg3_netif_start(tp);
1da177e4 5909
f47c11ee 5910 tg3_full_unlock(tp);
1da177e4 5911
b02fd9e3
MC		 5912 if (!err)
5913 tg3_phy_start(tp);
5914
b9ec6c1b 5915 return err;
1da177e4
LT		 5916}
5917
21f581a5
MC		 5918static void tg3_rx_prodring_free(struct tg3 *tp,
5919 struct tg3_rx_prodring_set *tpr)
1da177e4 5920{
1da177e4
LT		 5921 int i;
5922
b196c7e4
MC		 5923 if (tpr != &tp->prodring[0]) {
5924 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5925 i = (i + 1) % TG3_RX_RING_SIZE)
5926 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5927 tp->rx_pkt_map_sz);
5928
5929 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5930 for (i = tpr->rx_jmb_cons_idx;
5931 i != tpr->rx_jmb_prod_idx;
5932 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5933 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5934 TG3_RX_JMB_MAP_SZ);
5935 }
5936 }
5937
2b2cdb65 5938 return;
b196c7e4 5939 }
1da177e4 5940
2b2cdb65
MC		 5941 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5942 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5943 tp->rx_pkt_map_sz);
1da177e4 5944
cf7a7298 5945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5946 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5947 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5948 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5949 }
5950}
5951
5952/* Initialize tx/rx rings for packet processing.
5953 *
5954 * The chip has been shut down and the driver detached from
5955 * the networking, so no interrupts or new tx packets will
5956 * end up in the driver. tp->{tx,}lock are held and thus
5957 * we may not sleep.
5958 */
21f581a5
MC		 5959static int tg3_rx_prodring_alloc(struct tg3 *tp,
5960 struct tg3_rx_prodring_set *tpr)
1da177e4 5961{
287be12e 5962 u32 i, rx_pkt_dma_sz;
1da177e4 5963
b196c7e4
MC		 5964 tpr->rx_std_cons_idx = 0;
5965 tpr->rx_std_prod_idx = 0;
5966 tpr->rx_jmb_cons_idx = 0;
5967 tpr->rx_jmb_prod_idx = 0;
5968
2b2cdb65
MC		 5969 if (tpr != &tp->prodring[0]) {
5970 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5971 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5972 memset(&tpr->rx_jmb_buffers[0], 0,
5973 TG3_RX_JMB_BUFF_RING_SIZE);
5974 goto done;
5975 }
5976
1da177e4 5977 /* Zero out all descriptors. */
21f581a5 5978 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5979
287be12e 5980 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5981 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5982 tp->dev->mtu > ETH_DATA_LEN)
5983 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5984 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5985
1da177e4
LT		 5986 /* Initialize invariants of the rings, we only set this
5987 * stuff once. This works because the card does not
5988 * write into the rx buffer posting rings.
5989 */
5990 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5991 struct tg3_rx_buffer_desc *rxd;
5992
21f581a5 5993 rxd = &tpr->rx_std[i];
287be12e 5994 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5995 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5996 rxd->opaque = (RXD_OPAQUE_RING_STD |
5997 (i << RXD_OPAQUE_INDEX_SHIFT));
5998 }
5999
1da177e4
LT		 6000 /* Now allocate fresh SKBs for each rx ring. */
6001 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6002 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6003 printk(KERN_WARNING PFX
6004 "%s: Using a smaller RX standard ring, "
6005 "only %d out of %d buffers were allocated "
6006 "successfully.\n",
6007 tp->dev->name, i, tp->rx_pending);
6008 if (i == 0)
cf7a7298 6009 goto initfail;
32d8c572 6010 tp->rx_pending = i;
1da177e4 6011 break;
32d8c572 6012 }
1da177e4
LT		 6013 }
6014
cf7a7298
MC		 6015 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6016 goto done;
6017
21f581a5 6018 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6019
0f893dc6 6020 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6021 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6022 struct tg3_rx_buffer_desc *rxd;
6023
79ed5ac7 6024 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6025 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6026 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6027 RXD_FLAG_JUMBO;
6028 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6029 (i << RXD_OPAQUE_INDEX_SHIFT));
6030 }
6031
1da177e4 6032 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6033 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6034 i) < 0) {
32d8c572
MC		 6035 printk(KERN_WARNING PFX
6036 "%s: Using a smaller RX jumbo ring, "
6037 "only %d out of %d buffers were "
6038 "allocated successfully.\n",
6039 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6040 if (i == 0)
6041 goto initfail;
32d8c572 6042 tp->rx_jumbo_pending = i;
1da177e4 6043 break;
32d8c572 6044 }
1da177e4
LT		 6045 }
6046 }
cf7a7298
MC		 6047
6048done:
32d8c572 6049 return 0;
cf7a7298
MC		 6050
6051initfail:
21f581a5 6052 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6053 return -ENOMEM;
1da177e4
LT		 6054}
6055
21f581a5
MC		 6056static void tg3_rx_prodring_fini(struct tg3 *tp,
6057 struct tg3_rx_prodring_set *tpr)
1da177e4 6058{
21f581a5
MC		 6059 kfree(tpr->rx_std_buffers);
6060 tpr->rx_std_buffers = NULL;
6061 kfree(tpr->rx_jmb_buffers);
6062 tpr->rx_jmb_buffers = NULL;
6063 if (tpr->rx_std) {
1da177e4 6064 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6065 tpr->rx_std, tpr->rx_std_mapping);
6066 tpr->rx_std = NULL;
1da177e4 6067 }
21f581a5 6068 if (tpr->rx_jmb) {
1da177e4 6069 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6070 tpr->rx_jmb, tpr->rx_jmb_mapping);
6071 tpr->rx_jmb = NULL;
1da177e4 6072 }
cf7a7298
MC		 6073}
6074
21f581a5
MC		 6075static int tg3_rx_prodring_init(struct tg3 *tp,
6076 struct tg3_rx_prodring_set *tpr)
cf7a7298 6077{
2b2cdb65 6078 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6079 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6080 return -ENOMEM;
6081
21f581a5
MC		 6082 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6083 &tpr->rx_std_mapping);
6084 if (!tpr->rx_std)
cf7a7298
MC		 6085 goto err_out;
6086
6087 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6088 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6089 GFP_KERNEL);
6090 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6091 goto err_out;
6092
21f581a5
MC		 6093 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6094 TG3_RX_JUMBO_RING_BYTES,
6095 &tpr->rx_jmb_mapping);
6096 if (!tpr->rx_jmb)
cf7a7298
MC		 6097 goto err_out;
6098 }
6099
6100 return 0;
6101
6102err_out:
21f581a5 6103 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6104 return -ENOMEM;
6105}
6106
6107/* Free up pending packets in all rx/tx rings.
6108 *
6109 * The chip has been shut down and the driver detached from
6110 * the networking, so no interrupts or new tx packets will
6111 * end up in the driver. tp->{tx,}lock is not held and we are not
6112 * in an interrupt context and thus may sleep.
6113 */
6114static void tg3_free_rings(struct tg3 *tp)
6115{
f77a6a8e 6116 int i, j;
cf7a7298 6117
f77a6a8e
MC		 6118 for (j = 0; j < tp->irq_cnt; j++) {
6119 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6120
0c1d0e2b
MC		 6121 if (!tnapi->tx_buffers)
6122 continue;
6123
f77a6a8e 6124 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6125 struct ring_info *txp;
f77a6a8e 6126 struct sk_buff *skb;
f4188d8a 6127 unsigned int k;
cf7a7298 6128
f77a6a8e
MC		 6129 txp = &tnapi->tx_buffers[i];
6130 skb = txp->skb;
cf7a7298 6131
f77a6a8e
MC		 6132 if (skb == NULL) {
6133 i++;
6134 continue;
6135 }
cf7a7298 6136
f4188d8a
AD		 6137 pci_unmap_single(tp->pdev,
6138 pci_unmap_addr(txp, mapping),
6139 skb_headlen(skb),
6140 PCI_DMA_TODEVICE);
f77a6a8e 6141 txp->skb = NULL;
cf7a7298 6142
f4188d8a
AD		 6143 i++;
6144
6145 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6146 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6147 pci_unmap_page(tp->pdev,
6148 pci_unmap_addr(txp, mapping),
6149 skb_shinfo(skb)->frags[k].size,
6150 PCI_DMA_TODEVICE);
6151 i++;
6152 }
f77a6a8e
MC		 6153
6154 dev_kfree_skb_any(skb);
6155 }
cf7a7298 6156
2b2cdb65
MC		 6157 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6158 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6159 }
cf7a7298
MC		 6160}
6161
6162/* Initialize tx/rx rings for packet processing.
6163 *
6164 * The chip has been shut down and the driver detached from
6165 * the networking, so no interrupts or new tx packets will
6166 * end up in the driver. tp->{tx,}lock are held and thus
6167 * we may not sleep.
6168 */
6169static int tg3_init_rings(struct tg3 *tp)
6170{
f77a6a8e 6171 int i;
72334482 6172
cf7a7298
MC		 6173 /* Free up all the SKBs. */
6174 tg3_free_rings(tp);
6175
f77a6a8e
MC		 6176 for (i = 0; i < tp->irq_cnt; i++) {
6177 struct tg3_napi *tnapi = &tp->napi[i];
6178
6179 tnapi->last_tag = 0;
6180 tnapi->last_irq_tag = 0;
6181 tnapi->hw_status->status = 0;
6182 tnapi->hw_status->status_tag = 0;
6183 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6184
f77a6a8e
MC		 6185 tnapi->tx_prod = 0;
6186 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6187 if (tnapi->tx_ring)
6188 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6189
6190 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6191 if (tnapi->rx_rcb)
6192 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 6193
6194 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6195 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6196 return -ENOMEM;
f77a6a8e 6197 }
72334482 6198
2b2cdb65 6199 return 0;
cf7a7298
MC		 6200}
6201
6202/*
6203 * Must not be invoked with interrupt sources disabled and
6204 * the hardware shutdown down.
6205 */
6206static void tg3_free_consistent(struct tg3 *tp)
6207{
f77a6a8e 6208 int i;
898a56f8 6209
f77a6a8e
MC		 6210 for (i = 0; i < tp->irq_cnt; i++) {
6211 struct tg3_napi *tnapi = &tp->napi[i];
6212
6213 if (tnapi->tx_ring) {
6214 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6215 tnapi->tx_ring, tnapi->tx_desc_mapping);
6216 tnapi->tx_ring = NULL;
6217 }
6218
6219 kfree(tnapi->tx_buffers);
6220 tnapi->tx_buffers = NULL;
6221
6222 if (tnapi->rx_rcb) {
6223 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6224 tnapi->rx_rcb,
6225 tnapi->rx_rcb_mapping);
6226 tnapi->rx_rcb = NULL;
6227 }
6228
6229 if (tnapi->hw_status) {
6230 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6231 tnapi->hw_status,
6232 tnapi->status_mapping);
6233 tnapi->hw_status = NULL;
6234 }
1da177e4 6235 }
f77a6a8e 6236
1da177e4
LT		 6237 if (tp->hw_stats) {
6238 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6239 tp->hw_stats, tp->stats_mapping);
6240 tp->hw_stats = NULL;
6241 }
f77a6a8e 6242
2b2cdb65
MC		 6243 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6244 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6245}
6246
6247/*
6248 * Must not be invoked with interrupt sources disabled and
6249 * the hardware shutdown down. Can sleep.
6250 */
6251static int tg3_alloc_consistent(struct tg3 *tp)
6252{
f77a6a8e 6253 int i;
898a56f8 6254
2b2cdb65
MC		 6255 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6256 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6257 goto err_out;
6258 }
1da177e4 6259
f77a6a8e
MC		 6260 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6261 sizeof(struct tg3_hw_stats),
6262 &tp->stats_mapping);
6263 if (!tp->hw_stats)
1da177e4
LT		 6264 goto err_out;
6265
f77a6a8e 6266 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6267
f77a6a8e
MC		 6268 for (i = 0; i < tp->irq_cnt; i++) {
6269 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6270 struct tg3_hw_status *sblk;
1da177e4 6271
f77a6a8e
MC		 6272 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6273 TG3_HW_STATUS_SIZE,
6274 &tnapi->status_mapping);
6275 if (!tnapi->hw_status)
6276 goto err_out;
898a56f8 6277
f77a6a8e 6278 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6279 sblk = tnapi->hw_status;
6280
19cfaecc
MC		 6281 /* If multivector TSS is enabled, vector 0 does not handle
6282 * tx interrupts. Don't allocate any resources for it.
6283 */
6284 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6285 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6286 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6287 TG3_TX_RING_SIZE,
6288 GFP_KERNEL);
6289 if (!tnapi->tx_buffers)
6290 goto err_out;
6291
6292 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6293 TG3_TX_RING_BYTES,
6294 &tnapi->tx_desc_mapping);
6295 if (!tnapi->tx_ring)
6296 goto err_out;
6297 }
6298
8d9d7cfc
MC		 6299 /*
6300 * When RSS is enabled, the status block format changes
6301 * slightly. The "rx_jumbo_consumer", "reserved",
6302 * and "rx_mini_consumer" members get mapped to the
6303 * other three rx return ring producer indexes.
6304 */
6305 switch (i) {
6306 default:
6307 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6308 break;
6309 case 2:
6310 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6311 break;
6312 case 3:
6313 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6314 break;
6315 case 4:
6316 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6317 break;
6318 }
72334482 6319
b196c7e4
MC		 6320 if (tp->irq_cnt == 1)
6321 tnapi->prodring = &tp->prodring[0];
6322 else if (i)
6323 tnapi->prodring = &tp->prodring[i - 1];
6324
0c1d0e2b
MC		 6325 /*
6326 * If multivector RSS is enabled, vector 0 does not handle
6327 * rx or tx interrupts. Don't allocate any resources for it.
6328 */
6329 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6330 continue;
6331
f77a6a8e
MC		 6332 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6333 TG3_RX_RCB_RING_BYTES(tp),
6334 &tnapi->rx_rcb_mapping);
6335 if (!tnapi->rx_rcb)
6336 goto err_out;
72334482 6337
f77a6a8e 6338 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6339 }
1da177e4
LT		 6340
6341 return 0;
6342
6343err_out:
6344 tg3_free_consistent(tp);
6345 return -ENOMEM;
6346}
6347
6348#define MAX_WAIT_CNT 1000
6349
6350/* To stop a block, clear the enable bit and poll till it
6351 * clears. tp->lock is held.
6352 */
b3b7d6be 6353static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6354{
6355 unsigned int i;
6356 u32 val;
6357
6358 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6359 switch (ofs) {
6360 case RCVLSC_MODE:
6361 case DMAC_MODE:
6362 case MBFREE_MODE:
6363 case BUFMGR_MODE:
6364 case MEMARB_MODE:
6365 /* We can't enable/disable these bits of the
6366 * 5705/5750, just say success.
6367 */
6368 return 0;
6369
6370 default:
6371 break;
855e1111 6372 }
1da177e4
LT		 6373 }
6374
6375 val = tr32(ofs);
6376 val &= ~enable_bit;
6377 tw32_f(ofs, val);
6378
6379 for (i = 0; i < MAX_WAIT_CNT; i++) {
6380 udelay(100);
6381 val = tr32(ofs);
6382 if ((val & enable_bit) == 0)
6383 break;
6384 }
6385
b3b7d6be 6386 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6387 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6388 "ofs=%lx enable_bit=%x\n",
6389 ofs, enable_bit);
6390 return -ENODEV;
6391 }
6392
6393 return 0;
6394}
6395
6396/* tp->lock is held. */
b3b7d6be 6397static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6398{
6399 int i, err;
6400
6401 tg3_disable_ints(tp);
6402
6403 tp->rx_mode &= ~RX_MODE_ENABLE;
6404 tw32_f(MAC_RX_MODE, tp->rx_mode);
6405 udelay(10);
6406
b3b7d6be
DM		 6407 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6408 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6409 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6410 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6411 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6412 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6413
6414 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6415 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6416 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6417 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6418 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6419 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6420 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6421
6422 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6423 tw32_f(MAC_MODE, tp->mac_mode);
6424 udelay(40);
6425
6426 tp->tx_mode &= ~TX_MODE_ENABLE;
6427 tw32_f(MAC_TX_MODE, tp->tx_mode);
6428
6429 for (i = 0; i < MAX_WAIT_CNT; i++) {
6430 udelay(100);
6431 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6432 break;
6433 }
6434 if (i >= MAX_WAIT_CNT) {
6435 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6436 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6437 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6438 err |= -ENODEV;
1da177e4
LT		 6439 }
6440
e6de8ad1 6441 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6442 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6443 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6444
6445 tw32(FTQ_RESET, 0xffffffff);
6446 tw32(FTQ_RESET, 0x00000000);
6447
b3b7d6be
DM		 6448 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6449 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6450
f77a6a8e
MC		 6451 for (i = 0; i < tp->irq_cnt; i++) {
6452 struct tg3_napi *tnapi = &tp->napi[i];
6453 if (tnapi->hw_status)
6454 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6455 }
1da177e4
LT		 6456 if (tp->hw_stats)
6457 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6458
1da177e4
LT		 6459 return err;
6460}
6461
0d3031d9
MC		 6462static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6463{
6464 int i;
6465 u32 apedata;
6466
6467 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6468 if (apedata != APE_SEG_SIG_MAGIC)
6469 return;
6470
6471 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6472 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6473 return;
6474
6475 /* Wait for up to 1 millisecond for APE to service previous event. */
6476 for (i = 0; i < 10; i++) {
6477 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6478 return;
6479
6480 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6481
6482 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6483 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6484 event | APE_EVENT_STATUS_EVENT_PENDING);
6485
6486 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6487
6488 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489 break;
6490
6491 udelay(100);
6492 }
6493
6494 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6495 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6496}
6497
6498static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6499{
6500 u32 event;
6501 u32 apedata;
6502
6503 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6504 return;
6505
6506 switch (kind) {
6507 case RESET_KIND_INIT:
6508 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6509 APE_HOST_SEG_SIG_MAGIC);
6510 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6511 APE_HOST_SEG_LEN_MAGIC);
6512 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6513 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6514 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6515 APE_HOST_DRIVER_ID_MAGIC);
6516 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6517 APE_HOST_BEHAV_NO_PHYLOCK);
6518
6519 event = APE_EVENT_STATUS_STATE_START;
6520 break;
6521 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6522 /* With the interface we are currently using,
6523 * APE does not track driver state. Wiping
6524 * out the HOST SEGMENT SIGNATURE forces
6525 * the APE to assume OS absent status.
6526 */
6527 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6528
0d3031d9
MC		 6529 event = APE_EVENT_STATUS_STATE_UNLOAD;
6530 break;
6531 case RESET_KIND_SUSPEND:
6532 event = APE_EVENT_STATUS_STATE_SUSPEND;
6533 break;
6534 default:
6535 return;
6536 }
6537
6538 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6539
6540 tg3_ape_send_event(tp, event);
6541}
6542
1da177e4
LT		 6543/* tp->lock is held. */
6544static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6545{
f49639e6
DM		 6546 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6547 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6548
6549 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6550 switch (kind) {
6551 case RESET_KIND_INIT:
6552 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6553 DRV_STATE_START);
6554 break;
6555
6556 case RESET_KIND_SHUTDOWN:
6557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6558 DRV_STATE_UNLOAD);
6559 break;
6560
6561 case RESET_KIND_SUSPEND:
6562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6563 DRV_STATE_SUSPEND);
6564 break;
6565
6566 default:
6567 break;
855e1111 6568 }
1da177e4 6569 }
0d3031d9
MC		 6570
6571 if (kind == RESET_KIND_INIT ||
6572 kind == RESET_KIND_SUSPEND)
6573 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6574}
6575
6576/* tp->lock is held. */
6577static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6578{
6579 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6580 switch (kind) {
6581 case RESET_KIND_INIT:
6582 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6583 DRV_STATE_START_DONE);
6584 break;
6585
6586 case RESET_KIND_SHUTDOWN:
6587 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6588 DRV_STATE_UNLOAD_DONE);
6589 break;
6590
6591 default:
6592 break;
855e1111 6593 }
1da177e4 6594 }
0d3031d9
MC		 6595
6596 if (kind == RESET_KIND_SHUTDOWN)
6597 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6598}
6599
6600/* tp->lock is held. */
6601static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6602{
6603 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6604 switch (kind) {
6605 case RESET_KIND_INIT:
6606 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6607 DRV_STATE_START);
6608 break;
6609
6610 case RESET_KIND_SHUTDOWN:
6611 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612 DRV_STATE_UNLOAD);
6613 break;
6614
6615 case RESET_KIND_SUSPEND:
6616 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6617 DRV_STATE_SUSPEND);
6618 break;
6619
6620 default:
6621 break;
855e1111 6622 }
1da177e4
LT		 6623 }
6624}
6625
7a6f4369
MC		 6626static int tg3_poll_fw(struct tg3 *tp)
6627{
6628 int i;
6629 u32 val;
6630
b5d3772c 6631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6632 /* Wait up to 20ms for init done. */
6633 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6634 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6635 return 0;
0ccead18 6636 udelay(100);
b5d3772c
MC		 6637 }
6638 return -ENODEV;
6639 }
6640
7a6f4369
MC		 6641 /* Wait for firmware initialization to complete. */
6642 for (i = 0; i < 100000; i++) {
6643 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6644 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6645 break;
6646 udelay(10);
6647 }
6648
6649 /* Chip might not be fitted with firmware. Some Sun onboard
6650 * parts are configured like that. So don't signal the timeout
6651 * of the above loop as an error, but do report the lack of
6652 * running firmware once.
6653 */
6654 if (i >= 100000 &&
6655 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6656 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6657
6658 printk(KERN_INFO PFX "%s: No firmware running.\n",
6659 tp->dev->name);
6660 }
6661
6662 return 0;
6663}
6664
ee6a99b5
MC		 6665/* Save PCI command register before chip reset */
6666static void tg3_save_pci_state(struct tg3 *tp)
6667{
8a6eac90 6668 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6669}
6670
6671/* Restore PCI state after chip reset */
6672static void tg3_restore_pci_state(struct tg3 *tp)
6673{
6674 u32 val;
6675
6676 /* Re-enable indirect register accesses. */
6677 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6678 tp->misc_host_ctrl);
6679
6680 /* Set MAX PCI retry to zero. */
6681 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6682 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6683 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6684 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6685 /* Allow reads and writes to the APE register and memory space. */
6686 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6687 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6688 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6689 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6690
8a6eac90 6691 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6692
fcb389df
MC		 6693 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6694 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6695 pcie_set_readrq(tp->pdev, 4096);
6696 else {
6697 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6698 tp->pci_cacheline_sz);
6699 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6700 tp->pci_lat_timer);
6701 }
114342f2 6702 }
5f5c51e3 6703
ee6a99b5 6704 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6705 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6706 u16 pcix_cmd;
6707
6708 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6709 &pcix_cmd);
6710 pcix_cmd &= ~PCI_X_CMD_ERO;
6711 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6712 pcix_cmd);
6713 }
ee6a99b5
MC		 6714
6715 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6716
6717 /* Chip reset on 5780 will reset MSI enable bit,
6718 * so need to restore it.
6719 */
6720 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6721 u16 ctrl;
6722
6723 pci_read_config_word(tp->pdev,
6724 tp->msi_cap + PCI_MSI_FLAGS,
6725 &ctrl);
6726 pci_write_config_word(tp->pdev,
6727 tp->msi_cap + PCI_MSI_FLAGS,
6728 ctrl | PCI_MSI_FLAGS_ENABLE);
6729 val = tr32(MSGINT_MODE);
6730 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6731 }
6732 }
6733}
6734
1da177e4
LT		 6735static void tg3_stop_fw(struct tg3 *);
6736
6737/* tp->lock is held. */
6738static int tg3_chip_reset(struct tg3 *tp)
6739{
6740 u32 val;
1ee582d8 6741 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6742 int i, err;
1da177e4 6743
f49639e6
DM		 6744 tg3_nvram_lock(tp);
6745
77b483f1
MC		 6746 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6747
f49639e6
DM		 6748 /* No matching tg3_nvram_unlock() after this because
6749 * chip reset below will undo the nvram lock.
6750 */
6751 tp->nvram_lock_cnt = 0;
1da177e4 6752
ee6a99b5
MC		 6753 /* GRC_MISC_CFG core clock reset will clear the memory
6754 * enable bit in PCI register 4 and the MSI enable bit
6755 * on some chips, so we save relevant registers here.
6756 */
6757 tg3_save_pci_state(tp);
6758
d9ab5ad1 6759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6760 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6761 tw32(GRC_FASTBOOT_PC, 0);
6762
1da177e4
LT		 6763 /*
6764 * We must avoid the readl() that normally takes place.
6765 * It locks machines, causes machine checks, and other
6766 * fun things. So, temporarily disable the 5701
6767 * hardware workaround, while we do the reset.
6768 */
1ee582d8
MC		 6769 write_op = tp->write32;
6770 if (write_op == tg3_write_flush_reg32)
6771 tp->write32 = tg3_write32;
1da177e4 6772
d18edcb2
MC		 6773 /* Prevent the irq handler from reading or writing PCI registers
6774 * during chip reset when the memory enable bit in the PCI command
6775 * register may be cleared. The chip does not generate interrupt
6776 * at this time, but the irq handler may still be called due to irq
6777 * sharing or irqpoll.
6778 */
6779 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6780 for (i = 0; i < tp->irq_cnt; i++) {
6781 struct tg3_napi *tnapi = &tp->napi[i];
6782 if (tnapi->hw_status) {
6783 tnapi->hw_status->status = 0;
6784 tnapi->hw_status->status_tag = 0;
6785 }
6786 tnapi->last_tag = 0;
6787 tnapi->last_irq_tag = 0;
b8fa2f3a 6788 }
d18edcb2 6789 smp_mb();
4f125f42
MC		 6790
6791 for (i = 0; i < tp->irq_cnt; i++)
6792 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6793
255ca311
MC		 6794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6795 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6796 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6797 }
6798
1da177e4
LT		 6799 /* do the reset */
6800 val = GRC_MISC_CFG_CORECLK_RESET;
6801
6802 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6803 if (tr32(0x7e2c) == 0x60) {
6804 tw32(0x7e2c, 0x20);
6805 }
6806 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6807 tw32(GRC_MISC_CFG, (1 << 29));
6808 val |= (1 << 29);
6809 }
6810 }
6811
b5d3772c
MC		 6812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6813 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6814 tw32(GRC_VCPU_EXT_CTRL,
6815 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6816 }
6817
1da177e4
LT		 6818 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6819 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6820 tw32(GRC_MISC_CFG, val);
6821
1ee582d8
MC		 6822 /* restore 5701 hardware bug workaround write method */
6823 tp->write32 = write_op;
1da177e4
LT		 6824
6825 /* Unfortunately, we have to delay before the PCI read back.
6826 * Some 575X chips even will not respond to a PCI cfg access
6827 * when the reset command is given to the chip.
6828 *
6829 * How do these hardware designers expect things to work
6830 * properly if the PCI write is posted for a long period
6831 * of time? It is always necessary to have some method by
6832 * which a register read back can occur to push the write
6833 * out which does the reset.
6834 *
6835 * For most tg3 variants the trick below was working.
6836 * Ho hum...
6837 */
6838 udelay(120);
6839
6840 /* Flush PCI posted writes. The normal MMIO registers
6841 * are inaccessible at this time so this is the only
6842 * way to make this reliably (actually, this is no longer
6843 * the case, see above). I tried to use indirect
6844 * register read/write but this upset some 5701 variants.
6845 */
6846 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6847
6848 udelay(120);
6849
5e7dfd0f 6850 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6851 u16 val16;
6852
1da177e4
LT		 6853 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6854 int i;
6855 u32 cfg_val;
6856
6857 /* Wait for link training to complete. */
6858 for (i = 0; i < 5000; i++)
6859 udelay(100);
6860
6861 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6862 pci_write_config_dword(tp->pdev, 0xc4,
6863 cfg_val | (1 << 15));
6864 }
5e7dfd0f 6865
e7126997
MC		 6866 /* Clear the "no snoop" and "relaxed ordering" bits. */
6867 pci_read_config_word(tp->pdev,
6868 tp->pcie_cap + PCI_EXP_DEVCTL,
6869 &val16);
6870 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6871 PCI_EXP_DEVCTL_NOSNOOP_EN);
6872 /*
6873 * Older PCIe devices only support the 128 byte
6874 * MPS setting. Enforce the restriction.
5e7dfd0f 6875 */
e7126997
MC		 6876 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6877 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6878 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6879 pci_write_config_word(tp->pdev,
6880 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6881 val16);
5e7dfd0f
MC		 6882
6883 pcie_set_readrq(tp->pdev, 4096);
6884
6885 /* Clear error status */
6886 pci_write_config_word(tp->pdev,
6887 tp->pcie_cap + PCI_EXP_DEVSTA,
6888 PCI_EXP_DEVSTA_CED |
6889 PCI_EXP_DEVSTA_NFED |
6890 PCI_EXP_DEVSTA_FED |
6891 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6892 }
6893
ee6a99b5 6894 tg3_restore_pci_state(tp);
1da177e4 6895
d18edcb2
MC		 6896 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6897
ee6a99b5
MC		 6898 val = 0;
6899 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6900 val = tr32(MEMARB_MODE);
ee6a99b5 6901 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6902
6903 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6904 tg3_stop_fw(tp);
6905 tw32(0x5000, 0x400);
6906 }
6907
6908 tw32(GRC_MODE, tp->grc_mode);
6909
6910 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6911 val = tr32(0xc4);
1da177e4
LT		 6912
6913 tw32(0xc4, val | (1 << 15));
6914 }
6915
6916 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6917 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6918 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6919 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6920 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6921 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6922 }
6923
6924 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6925 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6926 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6927 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6928 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6929 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6930 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6931 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6932 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6933 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6934 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6935 } else
6936 tw32_f(MAC_MODE, 0);
6937 udelay(40);
6938
77b483f1
MC		 6939 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6940
7a6f4369
MC		 6941 err = tg3_poll_fw(tp);
6942 if (err)
6943 return err;
1da177e4 6944
0a9140cf
MC		 6945 tg3_mdio_start(tp);
6946
52cdf852
MC		 6947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6948 u8 phy_addr;
6949
6950 phy_addr = tp->phy_addr;
6951 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6952
6953 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6954 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6955 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6956 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6957 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6958 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6959 udelay(10);
6960
6961 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6962 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6963 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6964 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6965 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6966 udelay(10);
6967
6968 tp->phy_addr = phy_addr;
6969 }
6970
1da177e4 6971 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6972 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6973 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 6974 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6975 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 6976 val = tr32(0x7c00);
1da177e4
LT		 6977
6978 tw32(0x7c00, val | (1 << 25));
6979 }
6980
6981 /* Reprobe ASF enable state. */
6982 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6983 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6984 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6985 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6986 u32 nic_cfg;
6987
6988 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6989 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6990 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6991 tp->last_event_jiffies = jiffies;
cbf46853 6992 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6993 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6994 }
6995 }
6996
6997 return 0;
6998}
6999
7000/* tp->lock is held. */
7001static void tg3_stop_fw(struct tg3 *tp)
7002{
0d3031d9
MC		 7003 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7004 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7005 /* Wait for RX cpu to ACK the previous event. */
7006 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7007
7008 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7009
7010 tg3_generate_fw_event(tp);
1da177e4 7011
7c5026aa
MC		 7012 /* Wait for RX cpu to ACK this event. */
7013 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7014 }
7015}
7016
7017/* tp->lock is held. */
944d980e 7018static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7019{
7020 int err;
7021
7022 tg3_stop_fw(tp);
7023
944d980e 7024 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7025
b3b7d6be 7026 tg3_abort_hw(tp, silent);
1da177e4
LT		 7027 err = tg3_chip_reset(tp);
7028
daba2a63
MC		 7029 __tg3_set_mac_addr(tp, 0);
7030
944d980e
MC		 7031 tg3_write_sig_legacy(tp, kind);
7032 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7033
7034 if (err)
7035 return err;
7036
7037 return 0;
7038}
7039
1da177e4
LT		 7040#define RX_CPU_SCRATCH_BASE 0x30000
7041#define RX_CPU_SCRATCH_SIZE 0x04000
7042#define TX_CPU_SCRATCH_BASE 0x34000
7043#define TX_CPU_SCRATCH_SIZE 0x04000
7044
7045/* tp->lock is held. */
7046static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7047{
7048 int i;
7049
5d9428de
ES		 7050 BUG_ON(offset == TX_CPU_BASE &&
7051 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7052
b5d3772c
MC		 7053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7054 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7055
7056 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7057 return 0;
7058 }
1da177e4
LT		 7059 if (offset == RX_CPU_BASE) {
7060 for (i = 0; i < 10000; i++) {
7061 tw32(offset + CPU_STATE, 0xffffffff);
7062 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7063 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7064 break;
7065 }
7066
7067 tw32(offset + CPU_STATE, 0xffffffff);
7068 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7069 udelay(10);
7070 } else {
7071 for (i = 0; i < 10000; i++) {
7072 tw32(offset + CPU_STATE, 0xffffffff);
7073 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7074 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7075 break;
7076 }
7077 }
7078
7079 if (i >= 10000) {
7080 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7081 "and %s CPU\n",
7082 tp->dev->name,
7083 (offset == RX_CPU_BASE ? "RX" : "TX"));
7084 return -ENODEV;
7085 }
ec41c7df
MC		 7086
7087 /* Clear firmware's nvram arbitration. */
7088 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7089 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7090 return 0;
7091}
7092
7093struct fw_info {
077f849d
JSR		 7094 unsigned int fw_base;
7095 unsigned int fw_len;
7096 const __be32 *fw_data;
1da177e4
LT		 7097};
7098
7099/* tp->lock is held. */
7100static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7101 int cpu_scratch_size, struct fw_info *info)
7102{
ec41c7df 7103 int err, lock_err, i;
1da177e4
LT		 7104 void (*write_op)(struct tg3 *, u32, u32);
7105
7106 if (cpu_base == TX_CPU_BASE &&
7107 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7108 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7109 "TX cpu firmware on %s which is 5705.\n",
7110 tp->dev->name);
7111 return -EINVAL;
7112 }
7113
7114 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7115 write_op = tg3_write_mem;
7116 else
7117 write_op = tg3_write_indirect_reg32;
7118
1b628151
MC		 7119 /* It is possible that bootcode is still loading at this point.
7120 * Get the nvram lock first before halting the cpu.
7121 */
ec41c7df 7122 lock_err = tg3_nvram_lock(tp);
1da177e4 7123 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7124 if (!lock_err)
7125 tg3_nvram_unlock(tp);
1da177e4
LT		 7126 if (err)
7127 goto out;
7128
7129 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7130 write_op(tp, cpu_scratch_base + i, 0);
7131 tw32(cpu_base + CPU_STATE, 0xffffffff);
7132 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7133 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7134 write_op(tp, (cpu_scratch_base +
077f849d 7135 (info->fw_base & 0xffff) +
1da177e4 7136 (i * sizeof(u32))),
077f849d 7137 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7138
7139 err = 0;
7140
7141out:
1da177e4
LT		 7142 return err;
7143}
7144
7145/* tp->lock is held. */
7146static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7147{
7148 struct fw_info info;
077f849d 7149 const __be32 *fw_data;
1da177e4
LT		 7150 int err, i;
7151
077f849d
JSR		 7152 fw_data = (void *)tp->fw->data;
7153
7154 /* Firmware blob starts with version numbers, followed by
7155 start address and length. We are setting complete length.
7156 length = end_address_of_bss - start_address_of_text.
7157 Remainder is the blob to be loaded contiguously
7158 from start address. */
7159
7160 info.fw_base = be32_to_cpu(fw_data[1]);
7161 info.fw_len = tp->fw->size - 12;
7162 info.fw_data = &fw_data[3];
1da177e4
LT		 7163
7164 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7165 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7166 &info);
7167 if (err)
7168 return err;
7169
7170 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7171 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7172 &info);
7173 if (err)
7174 return err;
7175
7176 /* Now startup only the RX cpu. */
7177 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7178 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7179
7180 for (i = 0; i < 5; i++) {
077f849d 7181 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7182 break;
7183 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7184 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7185 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7186 udelay(1000);
7187 }
7188 if (i >= 5) {
7189 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7190 "to set RX CPU PC, is %08x should be %08x\n",
7191 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7192 info.fw_base);
1da177e4
LT		 7193 return -ENODEV;
7194 }
7195 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7196 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7197
7198 return 0;
7199}
7200
1da177e4 7201/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7202
7203/* tp->lock is held. */
7204static int tg3_load_tso_firmware(struct tg3 *tp)
7205{
7206 struct fw_info info;
077f849d 7207 const __be32 *fw_data;
1da177e4
LT		 7208 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7209 int err, i;
7210
7211 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7212 return 0;
7213
077f849d
JSR		 7214 fw_data = (void *)tp->fw->data;
7215
7216 /* Firmware blob starts with version numbers, followed by
7217 start address and length. We are setting complete length.
7218 length = end_address_of_bss - start_address_of_text.
7219 Remainder is the blob to be loaded contiguously
7220 from start address. */
7221
7222 info.fw_base = be32_to_cpu(fw_data[1]);
7223 cpu_scratch_size = tp->fw_len;
7224 info.fw_len = tp->fw->size - 12;
7225 info.fw_data = &fw_data[3];
7226
1da177e4 7227 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7228 cpu_base = RX_CPU_BASE;
7229 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7230 } else {
1da177e4
LT		 7231 cpu_base = TX_CPU_BASE;
7232 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7233 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7234 }
7235
7236 err = tg3_load_firmware_cpu(tp, cpu_base,
7237 cpu_scratch_base, cpu_scratch_size,
7238 &info);
7239 if (err)
7240 return err;
7241
7242 /* Now startup the cpu. */
7243 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7244 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7245
7246 for (i = 0; i < 5; i++) {
077f849d 7247 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7248 break;
7249 tw32(cpu_base + CPU_STATE, 0xffffffff);
7250 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7251 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7252 udelay(1000);
7253 }
7254 if (i >= 5) {
7255 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7256 "to set CPU PC, is %08x should be %08x\n",
7257 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7258 info.fw_base);
1da177e4
LT		 7259 return -ENODEV;
7260 }
7261 tw32(cpu_base + CPU_STATE, 0xffffffff);
7262 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7263 return 0;
7264}
7265
1da177e4 7266
1da177e4
LT		 7267static int tg3_set_mac_addr(struct net_device *dev, void *p)
7268{
7269 struct tg3 *tp = netdev_priv(dev);
7270 struct sockaddr *addr = p;
986e0aeb 7271 int err = 0, skip_mac_1 = 0;
1da177e4 7272
f9804ddb
MC		 7273 if (!is_valid_ether_addr(addr->sa_data))
7274 return -EINVAL;
7275
1da177e4
LT		 7276 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7277
e75f7c90
MC		 7278 if (!netif_running(dev))
7279 return 0;
7280
58712ef9 7281 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7282 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7283
986e0aeb
MC		 7284 addr0_high = tr32(MAC_ADDR_0_HIGH);
7285 addr0_low = tr32(MAC_ADDR_0_LOW);
7286 addr1_high = tr32(MAC_ADDR_1_HIGH);
7287 addr1_low = tr32(MAC_ADDR_1_LOW);
7288
7289 /* Skip MAC addr 1 if ASF is using it. */
7290 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7291 !(addr1_high == 0 && addr1_low == 0))
7292 skip_mac_1 = 1;
58712ef9 7293 }
986e0aeb
MC		 7294 spin_lock_bh(&tp->lock);
7295 __tg3_set_mac_addr(tp, skip_mac_1);
7296 spin_unlock_bh(&tp->lock);
1da177e4 7297
b9ec6c1b 7298 return err;
1da177e4
LT		 7299}
7300
7301/* tp->lock is held. */
7302static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7303 dma_addr_t mapping, u32 maxlen_flags,
7304 u32 nic_addr)
7305{
7306 tg3_write_mem(tp,
7307 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7308 ((u64) mapping >> 32));
7309 tg3_write_mem(tp,
7310 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7311 ((u64) mapping & 0xffffffff));
7312 tg3_write_mem(tp,
7313 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7314 maxlen_flags);
7315
7316 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7317 tg3_write_mem(tp,
7318 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7319 nic_addr);
7320}
7321
7322static void __tg3_set_rx_mode(struct net_device *);
d244c892 7323static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7324{
b6080e12
MC		 7325 int i;
7326
19cfaecc 7327 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7328 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7329 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7330 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7331 } else {
7332 tw32(HOSTCC_TXCOL_TICKS, 0);
7333 tw32(HOSTCC_TXMAX_FRAMES, 0);
7334 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7335 }
b6080e12 7336
19cfaecc
MC		 7337 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7338 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7339 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7340 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7341 } else {
b6080e12
MC		 7342 tw32(HOSTCC_RXCOL_TICKS, 0);
7343 tw32(HOSTCC_RXMAX_FRAMES, 0);
7344 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7345 }
b6080e12 7346
15f9850d
DM		 7347 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7348 u32 val = ec->stats_block_coalesce_usecs;
7349
b6080e12
MC		 7350 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7351 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7352
15f9850d
DM		 7353 if (!netif_carrier_ok(tp->dev))
7354 val = 0;
7355
7356 tw32(HOSTCC_STAT_COAL_TICKS, val);
7357 }
b6080e12
MC		 7358
7359 for (i = 0; i < tp->irq_cnt - 1; i++) {
7360 u32 reg;
7361
7362 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7363 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7364 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7365 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7366 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7367 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7368
7369 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7370 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7371 tw32(reg, ec->tx_coalesce_usecs);
7372 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7373 tw32(reg, ec->tx_max_coalesced_frames);
7374 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7375 tw32(reg, ec->tx_max_coalesced_frames_irq);
7376 }
b6080e12
MC		 7377 }
7378
7379 for (; i < tp->irq_max - 1; i++) {
7380 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7381 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7382 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7383
7384 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7385 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7386 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7387 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7388 }
b6080e12 7389 }
15f9850d 7390}
1da177e4 7391
2d31ecaf
MC		 7392/* tp->lock is held. */
7393static void tg3_rings_reset(struct tg3 *tp)
7394{
7395 int i;
f77a6a8e 7396 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7397 struct tg3_napi *tnapi = &tp->napi[0];
7398
7399 /* Disable all transmit rings but the first. */
7400 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7401 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7402 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7403 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7404 else
7405 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7406
7407 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7408 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7409 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7410 BDINFO_FLAGS_DISABLED);
7411
7412
7413 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7415 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7416 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7417 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7418 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7420 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7421 else
7422 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7423
7424 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7425 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7426 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7427 BDINFO_FLAGS_DISABLED);
7428
7429 /* Disable interrupts */
7430 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7431
7432 /* Zero mailbox registers. */
f77a6a8e
MC		 7433 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7434 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7435 tp->napi[i].tx_prod = 0;
7436 tp->napi[i].tx_cons = 0;
7437 tw32_mailbox(tp->napi[i].prodmbox, 0);
7438 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7439 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7440 }
7441 } else {
7442 tp->napi[0].tx_prod = 0;
7443 tp->napi[0].tx_cons = 0;
7444 tw32_mailbox(tp->napi[0].prodmbox, 0);
7445 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7446 }
2d31ecaf
MC		 7447
7448 /* Make sure the NIC-based send BD rings are disabled. */
7449 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7450 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7451 for (i = 0; i < 16; i++)
7452 tw32_tx_mbox(mbox + i * 8, 0);
7453 }
7454
7455 txrcb = NIC_SRAM_SEND_RCB;
7456 rxrcb = NIC_SRAM_RCV_RET_RCB;
7457
7458 /* Clear status block in ram. */
7459 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7460
7461 /* Set status block DMA address */
7462 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7463 ((u64) tnapi->status_mapping >> 32));
7464 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7465 ((u64) tnapi->status_mapping & 0xffffffff));
7466
f77a6a8e
MC		 7467 if (tnapi->tx_ring) {
7468 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7469 (TG3_TX_RING_SIZE <<
7470 BDINFO_FLAGS_MAXLEN_SHIFT),
7471 NIC_SRAM_TX_BUFFER_DESC);
7472 txrcb += TG3_BDINFO_SIZE;
7473 }
7474
7475 if (tnapi->rx_rcb) {
7476 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7477 (TG3_RX_RCB_RING_SIZE(tp) <<
7478 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7479 rxrcb += TG3_BDINFO_SIZE;
7480 }
7481
7482 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7483
f77a6a8e
MC		 7484 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7485 u64 mapping = (u64)tnapi->status_mapping;
7486 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7487 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7488
7489 /* Clear status block in ram. */
7490 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7491
19cfaecc
MC		 7492 if (tnapi->tx_ring) {
7493 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7494 (TG3_TX_RING_SIZE <<
7495 BDINFO_FLAGS_MAXLEN_SHIFT),
7496 NIC_SRAM_TX_BUFFER_DESC);
7497 txrcb += TG3_BDINFO_SIZE;
7498 }
f77a6a8e
MC		 7499
7500 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7501 (TG3_RX_RCB_RING_SIZE(tp) <<
7502 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7503
7504 stblk += 8;
f77a6a8e
MC		 7505 rxrcb += TG3_BDINFO_SIZE;
7506 }
2d31ecaf
MC		 7507}
7508
1da177e4 7509/* tp->lock is held. */
8e7a22e3 7510static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7511{
7512 u32 val, rdmac_mode;
7513 int i, err, limit;
21f581a5 7514 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7515
7516 tg3_disable_ints(tp);
7517
7518 tg3_stop_fw(tp);
7519
7520 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7521
7522 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7523 tg3_abort_hw(tp, 1);
1da177e4
LT		 7524 }
7525
dd477003
MC		 7526 if (reset_phy &&
7527 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7528 tg3_phy_reset(tp);
7529
1da177e4
LT		 7530 err = tg3_chip_reset(tp);
7531 if (err)
7532 return err;
7533
7534 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7535
bcb37f6c 7536 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7537 val = tr32(TG3_CPMU_CTRL);
7538 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7539 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7540
7541 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7542 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7543 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7544 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7545
7546 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7547 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7548 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7549 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7550
7551 val = tr32(TG3_CPMU_HST_ACC);
7552 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7553 val |= CPMU_HST_ACC_MACCLK_6_25;
7554 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7555 }
7556
33466d93
MC		 7557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7558 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7559 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7560 PCIE_PWR_MGMT_L1_THRESH_4MS;
7561 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7562
7563 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7564 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7565
7566 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7567
f40386c8
MC		 7568 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7569 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7570 }
7571
614b0590
MC		 7572 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7573 u32 grc_mode = tr32(GRC_MODE);
7574
7575 /* Access the lower 1K of PL PCIE block registers. */
7576 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7577 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7578
7579 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7580 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7581 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7582
7583 tw32(GRC_MODE, grc_mode);
7584 }
7585
1da177e4
LT		 7586 /* This works around an issue with Athlon chipsets on
7587 * B3 tigon3 silicon. This bit has no effect on any
7588 * other revision. But do not set this on PCI Express
795d01c5 7589 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7590 */
795d01c5
MC		 7591 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7592 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7593 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7594 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7595 }
1da177e4
LT		 7596
7597 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7598 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7599 val = tr32(TG3PCI_PCISTATE);
7600 val |= PCISTATE_RETRY_SAME_DMA;
7601 tw32(TG3PCI_PCISTATE, val);
7602 }
7603
0d3031d9
MC		 7604 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7605 /* Allow reads and writes to the
7606 * APE register and memory space.
7607 */
7608 val = tr32(TG3PCI_PCISTATE);
7609 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7610 PCISTATE_ALLOW_APE_SHMEM_WR;
7611 tw32(TG3PCI_PCISTATE, val);
7612 }
7613
1da177e4
LT		 7614 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7615 /* Enable some hw fixes. */
7616 val = tr32(TG3PCI_MSI_DATA);
7617 val |= (1 << 26) | (1 << 28) | (1 << 29);
7618 tw32(TG3PCI_MSI_DATA, val);
7619 }
7620
7621 /* Descriptor ring init may make accesses to the
7622 * NIC SRAM area to setup the TX descriptors, so we
7623 * can only do this after the hardware has been
7624 * successfully reset.
7625 */
32d8c572
MC		 7626 err = tg3_init_rings(tp);
7627 if (err)
7628 return err;
1da177e4 7629
b703df6f
MC		 7630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7632 val = tr32(TG3PCI_DMA_RW_CTRL) &
7633 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7634 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7635 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7636 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7637 /* This value is determined during the probe time DMA
7638 * engine test, tg3_test_dma.
7639 */
7640 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7641 }
1da177e4
LT		 7642
7643 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7644 GRC_MODE_4X_NIC_SEND_RINGS |
7645 GRC_MODE_NO_TX_PHDR_CSUM |
7646 GRC_MODE_NO_RX_PHDR_CSUM);
7647 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7648
7649 /* Pseudo-header checksum is done by hardware logic and not
7650 * the offload processers, so make the chip do the pseudo-
7651 * header checksums on receive. For transmit it is more
7652 * convenient to do the pseudo-header checksum in software
7653 * as Linux does that on transmit for us in all cases.
7654 */
7655 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7656
7657 tw32(GRC_MODE,
7658 tp->grc_mode |
7659 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7660
7661 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7662 val = tr32(GRC_MISC_CFG);
7663 val &= ~0xff;
7664 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7665 tw32(GRC_MISC_CFG, val);
7666
7667 /* Initialize MBUF/DESC pool. */
cbf46853 7668 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7669 /* Do nothing. */
7670 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7671 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7672 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7673 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7674 else
7675 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7676 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7677 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7678 }
1da177e4
LT		 7679 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7680 int fw_len;
7681
077f849d 7682 fw_len = tp->fw_len;
1da177e4
LT		 7683 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7684 tw32(BUFMGR_MB_POOL_ADDR,
7685 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7686 tw32(BUFMGR_MB_POOL_SIZE,
7687 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7688 }
1da177e4 7689
0f893dc6 7690 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7691 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7692 tp->bufmgr_config.mbuf_read_dma_low_water);
7693 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7694 tp->bufmgr_config.mbuf_mac_rx_low_water);
7695 tw32(BUFMGR_MB_HIGH_WATER,
7696 tp->bufmgr_config.mbuf_high_water);
7697 } else {
7698 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7699 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7700 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7701 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7702 tw32(BUFMGR_MB_HIGH_WATER,
7703 tp->bufmgr_config.mbuf_high_water_jumbo);
7704 }
7705 tw32(BUFMGR_DMA_LOW_WATER,
7706 tp->bufmgr_config.dma_low_water);
7707 tw32(BUFMGR_DMA_HIGH_WATER,
7708 tp->bufmgr_config.dma_high_water);
7709
7710 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7711 for (i = 0; i < 2000; i++) {
7712 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7713 break;
7714 udelay(10);
7715 }
7716 if (i >= 2000) {
7717 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7718 tp->dev->name);
7719 return -ENODEV;
7720 }
7721
7722 /* Setup replenish threshold. */
f92905de
MC		 7723 val = tp->rx_pending / 8;
7724 if (val == 0)
7725 val = 1;
7726 else if (val > tp->rx_std_max_post)
7727 val = tp->rx_std_max_post;
b5d3772c
MC		 7728 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7729 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7730 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7731
7732 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7733 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7734 }
f92905de
MC		 7735
7736 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7737
7738 /* Initialize TG3_BDINFO's at:
7739 * RCVDBDI_STD_BD: standard eth size rx ring
7740 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7741 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7742 *
7743 * like so:
7744 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7745 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7746 * ring attribute flags
7747 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7748 *
7749 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7750 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7751 *
7752 * The size of each ring is fixed in the firmware, but the location is
7753 * configurable.
7754 */
7755 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7756 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7757 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7758 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7759 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7760 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7761 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7762
fdb72b38
MC		 7763 /* Disable the mini ring */
7764 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7765 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7766 BDINFO_FLAGS_DISABLED);
7767
fdb72b38
MC		 7768 /* Program the jumbo buffer descriptor ring control
7769 * blocks on those devices that have them.
7770 */
8f666b07 7771 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7772 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7773 /* Setup replenish threshold. */
7774 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7775
0f893dc6 7776 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7777 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7778 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7779 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7780 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7781 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7782 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7783 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7785 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7786 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7787 } else {
7788 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7789 BDINFO_FLAGS_DISABLED);
7790 }
7791
b703df6f
MC		 7792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7794 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7795 (RX_STD_MAX_SIZE << 2);
7796 else
7797 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7798 } else
7799 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7800
7801 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7802
411da640 7803 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7804 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7805
411da640 7806 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7807 tp->rx_jumbo_pending : 0;
66711e66 7808 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7809
b703df6f
MC		 7810 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7812 tw32(STD_REPLENISH_LWM, 32);
7813 tw32(JMB_REPLENISH_LWM, 16);
7814 }
7815
2d31ecaf
MC		 7816 tg3_rings_reset(tp);
7817
1da177e4 7818 /* Initialize MAC address and backoff seed. */
986e0aeb 7819 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7820
7821 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7822 tw32(MAC_RX_MTU_SIZE,
7823 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7824
7825 /* The slot time is changed by tg3_setup_phy if we
7826 * run at gigabit with half duplex.
7827 */
7828 tw32(MAC_TX_LENGTHS,
7829 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7830 (6 << TX_LENGTHS_IPG_SHIFT) |
7831 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7832
7833 /* Receive rules. */
7834 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7835 tw32(RCVLPC_CONFIG, 0x0181);
7836
7837 /* Calculate RDMAC_MODE setting early, we need it to determine
7838 * the RCVLPC_STATE_ENABLE mask.
7839 */
7840 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7841 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7842 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7843 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7844 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7845
57e6983c 7846 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7849 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7850 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7851 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7852
85e94ced
MC		 7853 /* If statement applies to 5705 and 5750 PCI devices only */
7854 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7855 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7856 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7857 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7859 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7860 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7861 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7862 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7863 }
7864 }
7865
85e94ced
MC		 7866 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7867 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7868
1da177e4 7869 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7870 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7871
e849cdc3
MC		 7872 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7873 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7874 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7875 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7876
7877 /* Receive/send statistics. */
1661394e
MC		 7878 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7879 val = tr32(RCVLPC_STATS_ENABLE);
7880 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7881 tw32(RCVLPC_STATS_ENABLE, val);
7882 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7883 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7884 val = tr32(RCVLPC_STATS_ENABLE);
7885 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7886 tw32(RCVLPC_STATS_ENABLE, val);
7887 } else {
7888 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7889 }
7890 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7891 tw32(SNDDATAI_STATSENAB, 0xffffff);
7892 tw32(SNDDATAI_STATSCTRL,
7893 (SNDDATAI_SCTRL_ENABLE |
7894 SNDDATAI_SCTRL_FASTUPD));
7895
7896 /* Setup host coalescing engine. */
7897 tw32(HOSTCC_MODE, 0);
7898 for (i = 0; i < 2000; i++) {
7899 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7900 break;
7901 udelay(10);
7902 }
7903
d244c892 7904 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7905
1da177e4
LT		 7906 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7907 /* Status/statistics block address. See tg3_timer,
7908 * the tg3_periodic_fetch_stats call there, and
7909 * tg3_get_stats to see how this works for 5705/5750 chips.
7910 */
1da177e4
LT		 7911 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7912 ((u64) tp->stats_mapping >> 32));
7913 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7914 ((u64) tp->stats_mapping & 0xffffffff));
7915 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7916
1da177e4 7917 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7918
7919 /* Clear statistics and status block memory areas */
7920 for (i = NIC_SRAM_STATS_BLK;
7921 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7922 i += sizeof(u32)) {
7923 tg3_write_mem(tp, i, 0);
7924 udelay(40);
7925 }
1da177e4
LT		 7926 }
7927
7928 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7929
7930 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7931 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7932 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7933 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7934
c94e3941
MC		 7935 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7936 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7937 /* reset to prevent losing 1st rx packet intermittently */
7938 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7939 udelay(10);
7940 }
7941
3bda1258
MC		 7942 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7943 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7944 else
7945 tp->mac_mode = 0;
7946 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7947 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7948 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7949 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7950 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7951 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7952 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7953 udelay(40);
7954
314fba34 7955 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7956 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7957 * register to preserve the GPIO settings for LOMs. The GPIOs,
7958 * whether used as inputs or outputs, are set by boot code after
7959 * reset.
7960 */
9d26e213 7961 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7962 u32 gpio_mask;
7963
9d26e213
MC		 7964 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7965 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7966 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7967
7968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7969 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7970 GRC_LCLCTRL_GPIO_OUTPUT3;
7971
af36e6b6
MC		 7972 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7973 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7974
aaf84465 7975 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7976 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7977
7978 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7979 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7980 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7981 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7982 }
1da177e4
LT		 7983 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7984 udelay(100);
7985
baf8a94a
MC		 7986 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7987 val = tr32(MSGINT_MODE);
7988 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7989 tw32(MSGINT_MODE, val);
7990 }
7991
1da177e4
LT		 7992 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7993 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7994 udelay(40);
7995 }
7996
7997 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7998 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7999 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8000 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8001 WDMAC_MODE_LNGREAD_ENAB);
8002
85e94ced
MC		 8003 /* If statement applies to 5705 and 5750 PCI devices only */
8004 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8005 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8007 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8008 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8009 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8010 /* nothing */
8011 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8012 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8013 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8014 val |= WDMAC_MODE_RX_ACCEL;
8015 }
8016 }
8017
d9ab5ad1 8018 /* Enable host coalescing bug fix */
321d32a0 8019 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8020 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8021
788a035e
MC		 8022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8023 val |= WDMAC_MODE_BURST_ALL_DATA;
8024
1da177e4
LT		 8025 tw32_f(WDMAC_MODE, val);
8026 udelay(40);
8027
9974a356
MC		 8028 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8029 u16 pcix_cmd;
8030
8031 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8032 &pcix_cmd);
1da177e4 8033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8034 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8035 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8036 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8037 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8038 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8039 }
9974a356
MC		 8040 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8041 pcix_cmd);
1da177e4
LT		 8042 }
8043
8044 tw32_f(RDMAC_MODE, rdmac_mode);
8045 udelay(40);
8046
8047 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8048 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8049 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8050
8051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8052 tw32(SNDDATAC_MODE,
8053 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8054 else
8055 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8056
1da177e4
LT		 8057 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8058 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8059 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8060 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8061 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8062 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8063 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8064 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8065 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8066 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8067 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8068
8069 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8070 err = tg3_load_5701_a0_firmware_fix(tp);
8071 if (err)
8072 return err;
8073 }
8074
1da177e4
LT		 8075 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8076 err = tg3_load_tso_firmware(tp);
8077 if (err)
8078 return err;
8079 }
1da177e4
LT		 8080
8081 tp->tx_mode = TX_MODE_ENABLE;
8082 tw32_f(MAC_TX_MODE, tp->tx_mode);
8083 udelay(100);
8084
baf8a94a
MC		 8085 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8086 u32 reg = MAC_RSS_INDIR_TBL_0;
8087 u8 *ent = (u8 *)&val;
8088
8089 /* Setup the indirection table */
8090 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8091 int idx = i % sizeof(val);
8092
8093 ent[idx] = i % (tp->irq_cnt - 1);
8094 if (idx == sizeof(val) - 1) {
8095 tw32(reg, val);
8096 reg += 4;
8097 }
8098 }
8099
8100 /* Setup the "secret" hash key. */
8101 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8102 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8103 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8104 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8105 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8106 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8107 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8108 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8109 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8110 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8111 }
8112
1da177e4 8113 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8114 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8115 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8116
baf8a94a
MC		 8117 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8118 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8119 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8120 RX_MODE_RSS_IPV6_HASH_EN |
8121 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8122 RX_MODE_RSS_IPV4_HASH_EN |
8123 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8124
1da177e4
LT		 8125 tw32_f(MAC_RX_MODE, tp->rx_mode);
8126 udelay(10);
8127
1da177e4
LT		 8128 tw32(MAC_LED_CTRL, tp->led_ctrl);
8129
8130 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8131 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8132 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8133 udelay(10);
8134 }
8135 tw32_f(MAC_RX_MODE, tp->rx_mode);
8136 udelay(10);
8137
8138 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8139 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8140 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8141 /* Set drive transmission level to 1.2V */
8142 /* only if the signal pre-emphasis bit is not set */
8143 val = tr32(MAC_SERDES_CFG);
8144 val &= 0xfffff000;
8145 val |= 0x880;
8146 tw32(MAC_SERDES_CFG, val);
8147 }
8148 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8149 tw32(MAC_SERDES_CFG, 0x616000);
8150 }
8151
8152 /* Prevent chip from dropping frames when flow control
8153 * is enabled.
8154 */
8155 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8156
8157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8158 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8159 /* Use hardware link auto-negotiation */
8160 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8161 }
8162
d4d2c558
MC		 8163 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8164 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8165 u32 tmp;
8166
8167 tmp = tr32(SERDES_RX_CTRL);
8168 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8169 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8170 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8171 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8172 }
8173
dd477003
MC		 8174 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8175 if (tp->link_config.phy_is_low_power) {
8176 tp->link_config.phy_is_low_power = 0;
8177 tp->link_config.speed = tp->link_config.orig_speed;
8178 tp->link_config.duplex = tp->link_config.orig_duplex;
8179 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8180 }
1da177e4 8181
dd477003
MC		 8182 err = tg3_setup_phy(tp, 0);
8183 if (err)
8184 return err;
1da177e4 8185
dd477003 8186 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8187 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8188 u32 tmp;
8189
8190 /* Clear CRC stats. */
8191 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8192 tg3_writephy(tp, MII_TG3_TEST1,
8193 tmp | MII_TG3_TEST1_CRC_EN);
8194 tg3_readphy(tp, 0x14, &tmp);
8195 }
1da177e4
LT		 8196 }
8197 }
8198
8199 __tg3_set_rx_mode(tp->dev);
8200
8201 /* Initialize receive rules. */
8202 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8203 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8204 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8205 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8206
4cf78e4f 8207 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8208 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8209 limit = 8;
8210 else
8211 limit = 16;
8212 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8213 limit -= 4;
8214 switch (limit) {
8215 case 16:
8216 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8217 case 15:
8218 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8219 case 14:
8220 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8221 case 13:
8222 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8223 case 12:
8224 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8225 case 11:
8226 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8227 case 10:
8228 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8229 case 9:
8230 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8231 case 8:
8232 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8233 case 7:
8234 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8235 case 6:
8236 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8237 case 5:
8238 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8239 case 4:
8240 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8241 case 3:
8242 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8243 case 2:
8244 case 1:
8245
8246 default:
8247 break;
855e1111 8248 }
1da177e4 8249
9ce768ea
MC		 8250 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8251 /* Write our heartbeat update interval to APE. */
8252 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8253 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8254
1da177e4
LT		 8255 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8256
1da177e4
LT		 8257 return 0;
8258}
8259
8260/* Called at device open time to get the chip ready for
8261 * packet processing. Invoked with tp->lock held.
8262 */
8e7a22e3 8263static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8264{
1da177e4
LT		 8265 tg3_switch_clocks(tp);
8266
8267 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8268
2f751b67 8269 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8270}
8271
8272#define TG3_STAT_ADD32(PSTAT, REG) \
8273do { u32 __val = tr32(REG); \
8274 (PSTAT)->low += __val; \
8275 if ((PSTAT)->low < __val) \
8276 (PSTAT)->high += 1; \
8277} while (0)
8278
8279static void tg3_periodic_fetch_stats(struct tg3 *tp)
8280{
8281 struct tg3_hw_stats *sp = tp->hw_stats;
8282
8283 if (!netif_carrier_ok(tp->dev))
8284 return;
8285
8286 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8287 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8288 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8289 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8290 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8291 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8292 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8293 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8294 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8295 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8296 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8297 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8298 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8299
8300 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8301 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8302 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8303 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8304 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8305 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8306 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8307 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8308 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8309 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8310 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8311 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8312 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8313 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8314
8315 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8316 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8317 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8318}
8319
8320static void tg3_timer(unsigned long __opaque)
8321{
8322 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8323
f475f163
MC		 8324 if (tp->irq_sync)
8325 goto restart_timer;
8326
f47c11ee 8327 spin_lock(&tp->lock);
1da177e4 8328
fac9b83e
DM		 8329 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8330 /* All of this garbage is because when using non-tagged
8331 * IRQ status the mailbox/status_block protocol the chip
8332 * uses with the cpu is race prone.
8333 */
898a56f8 8334 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8335 tw32(GRC_LOCAL_CTRL,
8336 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8337 } else {
8338 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8339 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8340 }
1da177e4 8341
fac9b83e
DM		 8342 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8343 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8344 spin_unlock(&tp->lock);
fac9b83e
DM		 8345 schedule_work(&tp->reset_task);
8346 return;
8347 }
1da177e4
LT		 8348 }
8349
1da177e4
LT		 8350 /* This part only runs once per second. */
8351 if (!--tp->timer_counter) {
fac9b83e
DM		 8352 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8353 tg3_periodic_fetch_stats(tp);
8354
1da177e4
LT		 8355 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8356 u32 mac_stat;
8357 int phy_event;
8358
8359 mac_stat = tr32(MAC_STATUS);
8360
8361 phy_event = 0;
8362 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8363 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8364 phy_event = 1;
8365 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8366 phy_event = 1;
8367
8368 if (phy_event)
8369 tg3_setup_phy(tp, 0);
8370 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8371 u32 mac_stat = tr32(MAC_STATUS);
8372 int need_setup = 0;
8373
8374 if (netif_carrier_ok(tp->dev) &&
8375 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8376 need_setup = 1;
8377 }
8378 if (! netif_carrier_ok(tp->dev) &&
8379 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8380 MAC_STATUS_SIGNAL_DET))) {
8381 need_setup = 1;
8382 }
8383 if (need_setup) {
3d3ebe74
MC		 8384 if (!tp->serdes_counter) {
8385 tw32_f(MAC_MODE,
8386 (tp->mac_mode &
8387 ~MAC_MODE_PORT_MODE_MASK));
8388 udelay(40);
8389 tw32_f(MAC_MODE, tp->mac_mode);
8390 udelay(40);
8391 }
1da177e4
LT		 8392 tg3_setup_phy(tp, 0);
8393 }
747e8f8b
MC		 8394 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8395 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8396
8397 tp->timer_counter = tp->timer_multiplier;
8398 }
8399
130b8e4d
MC		 8400 /* Heartbeat is only sent once every 2 seconds.
8401 *
8402 * The heartbeat is to tell the ASF firmware that the host
8403 * driver is still alive. In the event that the OS crashes,
8404 * ASF needs to reset the hardware to free up the FIFO space
8405 * that may be filled with rx packets destined for the host.
8406 * If the FIFO is full, ASF will no longer function properly.
8407 *
8408 * Unintended resets have been reported on real time kernels
8409 * where the timer doesn't run on time. Netpoll will also have
8410 * same problem.
8411 *
8412 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8413 * to check the ring condition when the heartbeat is expiring
8414 * before doing the reset. This will prevent most unintended
8415 * resets.
8416 */
1da177e4 8417 if (!--tp->asf_counter) {
bc7959b2
MC		 8418 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8419 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8420 tg3_wait_for_event_ack(tp);
8421
bbadf503 8422 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8423 FWCMD_NICDRV_ALIVE3);
bbadf503 8424 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8425 /* 5 seconds timeout */
bbadf503 8426 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8427
8428 tg3_generate_fw_event(tp);
1da177e4
LT		 8429 }
8430 tp->asf_counter = tp->asf_multiplier;
8431 }
8432
f47c11ee 8433 spin_unlock(&tp->lock);
1da177e4 8434
f475f163 8435restart_timer:
1da177e4
LT		 8436 tp->timer.expires = jiffies + tp->timer_offset;
8437 add_timer(&tp->timer);
8438}
8439
4f125f42 8440static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8441{
7d12e780 8442 irq_handler_t fn;
fcfa0a32 8443 unsigned long flags;
4f125f42
MC		 8444 char *name;
8445 struct tg3_napi *tnapi = &tp->napi[irq_num];
8446
8447 if (tp->irq_cnt == 1)
8448 name = tp->dev->name;
8449 else {
8450 name = &tnapi->irq_lbl[0];
8451 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8452 name[IFNAMSIZ-1] = 0;
8453 }
fcfa0a32 8454
679563f4 8455 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8456 fn = tg3_msi;
8457 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8458 fn = tg3_msi_1shot;
1fb9df5d 8459 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8460 } else {
8461 fn = tg3_interrupt;
8462 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8463 fn = tg3_interrupt_tagged;
1fb9df5d 8464 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8465 }
4f125f42
MC		 8466
8467 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8468}
8469
7938109f
MC		 8470static int tg3_test_interrupt(struct tg3 *tp)
8471{
09943a18 8472 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8473 struct net_device *dev = tp->dev;
b16250e3 8474 int err, i, intr_ok = 0;
f6eb9b1f 8475 u32 val;
7938109f 8476
d4bc3927
MC		 8477 if (!netif_running(dev))
8478 return -ENODEV;
8479
7938109f
MC		 8480 tg3_disable_ints(tp);
8481
4f125f42 8482 free_irq(tnapi->irq_vec, tnapi);
7938109f 8483
f6eb9b1f
MC		 8484 /*
8485 * Turn off MSI one shot mode. Otherwise this test has no
8486 * observable way to know whether the interrupt was delivered.
8487 */
b703df6f
MC		 8488 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8489 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8490 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8491 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8492 tw32(MSGINT_MODE, val);
8493 }
8494
4f125f42 8495 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8496 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8497 if (err)
8498 return err;
8499
898a56f8 8500 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8501 tg3_enable_ints(tp);
8502
8503 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8504 tnapi->coal_now);
7938109f
MC		 8505
8506 for (i = 0; i < 5; i++) {
b16250e3
MC		 8507 u32 int_mbox, misc_host_ctrl;
8508
898a56f8 8509 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8510 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8511
8512 if ((int_mbox != 0) ||
8513 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8514 intr_ok = 1;
7938109f 8515 break;
b16250e3
MC		 8516 }
8517
7938109f
MC		 8518 msleep(10);
8519 }
8520
8521 tg3_disable_ints(tp);
8522
4f125f42 8523 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8524
4f125f42 8525 err = tg3_request_irq(tp, 0);
7938109f
MC		 8526
8527 if (err)
8528 return err;
8529
f6eb9b1f
MC		 8530 if (intr_ok) {
8531 /* Reenable MSI one shot mode. */
b703df6f
MC		 8532 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8534 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8535 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8536 tw32(MSGINT_MODE, val);
8537 }
7938109f 8538 return 0;
f6eb9b1f 8539 }
7938109f
MC		 8540
8541 return -EIO;
8542}
8543
8544/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8545 * successfully restored
8546 */
8547static int tg3_test_msi(struct tg3 *tp)
8548{
7938109f
MC		 8549 int err;
8550 u16 pci_cmd;
8551
8552 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8553 return 0;
8554
8555 /* Turn off SERR reporting in case MSI terminates with Master
8556 * Abort.
8557 */
8558 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8559 pci_write_config_word(tp->pdev, PCI_COMMAND,
8560 pci_cmd & ~PCI_COMMAND_SERR);
8561
8562 err = tg3_test_interrupt(tp);
8563
8564 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8565
8566 if (!err)
8567 return 0;
8568
8569 /* other failures */
8570 if (err != -EIO)
8571 return err;
8572
8573 /* MSI test failed, go back to INTx mode */
8574 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8575 "switching to INTx mode. Please report this failure to "
8576 "the PCI maintainer and include system chipset information.\n",
8577 tp->dev->name);
8578
4f125f42 8579 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8580
7938109f
MC		 8581 pci_disable_msi(tp->pdev);
8582
8583 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8584
4f125f42 8585 err = tg3_request_irq(tp, 0);
7938109f
MC		 8586 if (err)
8587 return err;
8588
8589 /* Need to reset the chip because the MSI cycle may have terminated
8590 * with Master Abort.
8591 */
f47c11ee 8592 tg3_full_lock(tp, 1);
7938109f 8593
944d980e 8594 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8595 err = tg3_init_hw(tp, 1);
7938109f 8596
f47c11ee 8597 tg3_full_unlock(tp);
7938109f
MC		 8598
8599 if (err)
4f125f42 8600 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8601
8602 return err;
8603}
8604
9e9fd12d
MC		 8605static int tg3_request_firmware(struct tg3 *tp)
8606{
8607 const __be32 *fw_data;
8608
8609 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8610 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8611 tp->dev->name, tp->fw_needed);
8612 return -ENOENT;
8613 }
8614
8615 fw_data = (void *)tp->fw->data;
8616
8617 /* Firmware blob starts with version numbers, followed by
8618 * start address and _full_ length including BSS sections
8619 * (which must be longer than the actual data, of course
8620 */
8621
8622 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8623 if (tp->fw_len < (tp->fw->size - 12)) {
8624 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8625 tp->dev->name, tp->fw_len, tp->fw_needed);
8626 release_firmware(tp->fw);
8627 tp->fw = NULL;
8628 return -EINVAL;
8629 }
8630
8631 /* We no longer need firmware; we have it. */
8632 tp->fw_needed = NULL;
8633 return 0;
8634}
8635
679563f4
MC		 8636static bool tg3_enable_msix(struct tg3 *tp)
8637{
8638 int i, rc, cpus = num_online_cpus();
8639 struct msix_entry msix_ent[tp->irq_max];
8640
8641 if (cpus == 1)
8642 /* Just fallback to the simpler MSI mode. */
8643 return false;
8644
8645 /*
8646 * We want as many rx rings enabled as there are cpus.
8647 * The first MSIX vector only deals with link interrupts, etc,
8648 * so we add one to the number of vectors we are requesting.
8649 */
8650 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8651
8652 for (i = 0; i < tp->irq_max; i++) {
8653 msix_ent[i].entry = i;
8654 msix_ent[i].vector = 0;
8655 }
8656
8657 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8658 if (rc != 0) {
8659 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8660 return false;
8661 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8662 return false;
8663 printk(KERN_NOTICE
8664 "%s: Requested %d MSI-X vectors, received %d\n",
8665 tp->dev->name, tp->irq_cnt, rc);
8666 tp->irq_cnt = rc;
8667 }
8668
baf8a94a
MC		 8669 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8670
679563f4
MC		 8671 for (i = 0; i < tp->irq_max; i++)
8672 tp->napi[i].irq_vec = msix_ent[i].vector;
8673
19cfaecc
MC		 8674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8675 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8676 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8677 } else
8678 tp->dev->real_num_tx_queues = 1;
fe5f5787 8679
679563f4
MC		 8680 return true;
8681}
8682
07b0173c
MC		 8683static void tg3_ints_init(struct tg3 *tp)
8684{
679563f4
MC		 8685 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8686 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8687 /* All MSI supporting chips should support tagged
8688 * status. Assert that this is the case.
8689 */
679563f4
MC		 8690 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8691 "Not using MSI.\n", tp->dev->name);
8692 goto defcfg;
07b0173c 8693 }
4f125f42 8694
679563f4
MC		 8695 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8696 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8697 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8698 pci_enable_msi(tp->pdev) == 0)
8699 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8700
8701 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8702 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8703 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8704 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8705 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8706 }
8707defcfg:
8708 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8709 tp->irq_cnt = 1;
8710 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8711 tp->dev->real_num_tx_queues = 1;
679563f4 8712 }
07b0173c
MC		 8713}
8714
8715static void tg3_ints_fini(struct tg3 *tp)
8716{
679563f4
MC		 8717 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8718 pci_disable_msix(tp->pdev);
8719 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8720 pci_disable_msi(tp->pdev);
8721 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8722 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8723}
8724
1da177e4
LT		 8725static int tg3_open(struct net_device *dev)
8726{
8727 struct tg3 *tp = netdev_priv(dev);
4f125f42 8728 int i, err;
1da177e4 8729
9e9fd12d
MC		 8730 if (tp->fw_needed) {
8731 err = tg3_request_firmware(tp);
8732 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8733 if (err)
8734 return err;
8735 } else if (err) {
8736 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8737 tp->dev->name);
8738 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8739 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8740 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8741 tp->dev->name);
8742 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8743 }
8744 }
8745
c49a1561
MC		 8746 netif_carrier_off(tp->dev);
8747
bc1c7567 8748 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8749 if (err)
bc1c7567 8750 return err;
2f751b67
MC		 8751
8752 tg3_full_lock(tp, 0);
bc1c7567 8753
1da177e4
LT		 8754 tg3_disable_ints(tp);
8755 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8756
f47c11ee 8757 tg3_full_unlock(tp);
1da177e4 8758
679563f4
MC		 8759 /*
8760 * Setup interrupts first so we know how
8761 * many NAPI resources to allocate
8762 */
8763 tg3_ints_init(tp);
8764
1da177e4
LT		 8765 /* The placement of this call is tied
8766 * to the setup and use of Host TX descriptors.
8767 */
8768 err = tg3_alloc_consistent(tp);
8769 if (err)
679563f4 8770 goto err_out1;
88b06bc2 8771
fed97810 8772 tg3_napi_enable(tp);
1da177e4 8773
4f125f42
MC		 8774 for (i = 0; i < tp->irq_cnt; i++) {
8775 struct tg3_napi *tnapi = &tp->napi[i];
8776 err = tg3_request_irq(tp, i);
8777 if (err) {
8778 for (i--; i >= 0; i--)
8779 free_irq(tnapi->irq_vec, tnapi);
8780 break;
8781 }
8782 }
1da177e4 8783
07b0173c 8784 if (err)
679563f4 8785 goto err_out2;
bea3348e 8786
f47c11ee 8787 tg3_full_lock(tp, 0);
1da177e4 8788
8e7a22e3 8789 err = tg3_init_hw(tp, 1);
1da177e4 8790 if (err) {
944d980e 8791 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8792 tg3_free_rings(tp);
8793 } else {
fac9b83e
DM		 8794 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8795 tp->timer_offset = HZ;
8796 else
8797 tp->timer_offset = HZ / 10;
8798
8799 BUG_ON(tp->timer_offset > HZ);
8800 tp->timer_counter = tp->timer_multiplier =
8801 (HZ / tp->timer_offset);
8802 tp->asf_counter = tp->asf_multiplier =
28fbef78 8803 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8804
8805 init_timer(&tp->timer);
8806 tp->timer.expires = jiffies + tp->timer_offset;
8807 tp->timer.data = (unsigned long) tp;
8808 tp->timer.function = tg3_timer;
1da177e4
LT		 8809 }
8810
f47c11ee 8811 tg3_full_unlock(tp);
1da177e4 8812
07b0173c 8813 if (err)
679563f4 8814 goto err_out3;
1da177e4 8815
7938109f
MC		 8816 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8817 err = tg3_test_msi(tp);
fac9b83e 8818
7938109f 8819 if (err) {
f47c11ee 8820 tg3_full_lock(tp, 0);
944d980e 8821 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8822 tg3_free_rings(tp);
f47c11ee 8823 tg3_full_unlock(tp);
7938109f 8824
679563f4 8825 goto err_out2;
7938109f 8826 }
fcfa0a32 8827
f6eb9b1f 8828 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8829 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8830 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8831 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8832 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8833
f6eb9b1f
MC		 8834 tw32(PCIE_TRANSACTION_CFG,
8835 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8836 }
7938109f
MC		 8837 }
8838
b02fd9e3
MC		 8839 tg3_phy_start(tp);
8840
f47c11ee 8841 tg3_full_lock(tp, 0);
1da177e4 8842
7938109f
MC		 8843 add_timer(&tp->timer);
8844 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8845 tg3_enable_ints(tp);
8846
f47c11ee 8847 tg3_full_unlock(tp);
1da177e4 8848
fe5f5787 8849 netif_tx_start_all_queues(dev);
1da177e4
LT		 8850
8851 return 0;
07b0173c 8852
679563f4 8853err_out3:
4f125f42
MC		 8854 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8855 struct tg3_napi *tnapi = &tp->napi[i];
8856 free_irq(tnapi->irq_vec, tnapi);
8857 }
07b0173c 8858
679563f4 8859err_out2:
fed97810 8860 tg3_napi_disable(tp);
07b0173c 8861 tg3_free_consistent(tp);
679563f4
MC		 8862
8863err_out1:
8864 tg3_ints_fini(tp);
07b0173c 8865 return err;
1da177e4
LT		 8866}
8867
8868#if 0
8869/*static*/ void tg3_dump_state(struct tg3 *tp)
8870{
8871 u32 val32, val32_2, val32_3, val32_4, val32_5;
8872 u16 val16;
8873 int i;
898a56f8 8874 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8875
8876 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8877 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8878 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8879 val16, val32);
8880
8881 /* MAC block */
8882 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8883 tr32(MAC_MODE), tr32(MAC_STATUS));
8884 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8885 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8886 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8887 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8888 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8889 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8890
8891 /* Send data initiator control block */
8892 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8893 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8894 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8895 tr32(SNDDATAI_STATSCTRL));
8896
8897 /* Send data completion control block */
8898 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8899
8900 /* Send BD ring selector block */
8901 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8902 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8903
8904 /* Send BD initiator control block */
8905 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8906 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8907
8908 /* Send BD completion control block */
8909 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8910
8911 /* Receive list placement control block */
8912 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8913 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8914 printk(" RCVLPC_STATSCTRL[%08x]\n",
8915 tr32(RCVLPC_STATSCTRL));
8916
8917 /* Receive data and receive BD initiator control block */
8918 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8919 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8920
8921 /* Receive data completion control block */
8922 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8923 tr32(RCVDCC_MODE));
8924
8925 /* Receive BD initiator control block */
8926 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8927 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8928
8929 /* Receive BD completion control block */
8930 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8931 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8932
8933 /* Receive list selector control block */
8934 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8935 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8936
8937 /* Mbuf cluster free block */
8938 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8939 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8940
8941 /* Host coalescing control block */
8942 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8943 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8944 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8945 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8946 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8947 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8948 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8949 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8950 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8951 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8952 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8953 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8954
8955 /* Memory arbiter control block */
8956 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8957 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8958
8959 /* Buffer manager control block */
8960 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8961 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8962 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8963 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8964 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8965 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8966 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8967 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8968
8969 /* Read DMA control block */
8970 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8971 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8972
8973 /* Write DMA control block */
8974 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8975 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8976
8977 /* DMA completion block */
8978 printk("DEBUG: DMAC_MODE[%08x]\n",
8979 tr32(DMAC_MODE));
8980
8981 /* GRC block */
8982 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8983 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8984 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8985 tr32(GRC_LOCAL_CTRL));
8986
8987 /* TG3_BDINFOs */
8988 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8989 tr32(RCVDBDI_JUMBO_BD + 0x0),
8990 tr32(RCVDBDI_JUMBO_BD + 0x4),
8991 tr32(RCVDBDI_JUMBO_BD + 0x8),
8992 tr32(RCVDBDI_JUMBO_BD + 0xc));
8993 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8994 tr32(RCVDBDI_STD_BD + 0x0),
8995 tr32(RCVDBDI_STD_BD + 0x4),
8996 tr32(RCVDBDI_STD_BD + 0x8),
8997 tr32(RCVDBDI_STD_BD + 0xc));
8998 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8999 tr32(RCVDBDI_MINI_BD + 0x0),
9000 tr32(RCVDBDI_MINI_BD + 0x4),
9001 tr32(RCVDBDI_MINI_BD + 0x8),
9002 tr32(RCVDBDI_MINI_BD + 0xc));
9003
9004 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9005 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9006 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9007 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9008 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9009 val32, val32_2, val32_3, val32_4);
9010
9011 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9012 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9013 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9014 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9015 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9016 val32, val32_2, val32_3, val32_4);
9017
9018 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9019 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9020 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9021 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9022 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9023 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9024 val32, val32_2, val32_3, val32_4, val32_5);
9025
9026 /* SW status block */
898a56f8
MC		 9027 printk(KERN_DEBUG
9028 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9029 sblk->status,
9030 sblk->status_tag,
9031 sblk->rx_jumbo_consumer,
9032 sblk->rx_consumer,
9033 sblk->rx_mini_consumer,
9034 sblk->idx[0].rx_producer,
9035 sblk->idx[0].tx_consumer);
1da177e4
LT		 9036
9037 /* SW statistics block */
9038 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9039 ((u32 *)tp->hw_stats)[0],
9040 ((u32 *)tp->hw_stats)[1],
9041 ((u32 *)tp->hw_stats)[2],
9042 ((u32 *)tp->hw_stats)[3]);
9043
9044 /* Mailboxes */
9045 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9046 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9047 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9048 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9049 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9050
9051 /* NIC side send descriptors. */
9052 for (i = 0; i < 6; i++) {
9053 unsigned long txd;
9054
9055 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9056 + (i * sizeof(struct tg3_tx_buffer_desc));
9057 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9058 i,
9059 readl(txd + 0x0), readl(txd + 0x4),
9060 readl(txd + 0x8), readl(txd + 0xc));
9061 }
9062
9063 /* NIC side RX descriptors. */
9064 for (i = 0; i < 6; i++) {
9065 unsigned long rxd;
9066
9067 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9068 + (i * sizeof(struct tg3_rx_buffer_desc));
9069 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9070 i,
9071 readl(rxd + 0x0), readl(rxd + 0x4),
9072 readl(rxd + 0x8), readl(rxd + 0xc));
9073 rxd += (4 * sizeof(u32));
9074 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9075 i,
9076 readl(rxd + 0x0), readl(rxd + 0x4),
9077 readl(rxd + 0x8), readl(rxd + 0xc));
9078 }
9079
9080 for (i = 0; i < 6; i++) {
9081 unsigned long rxd;
9082
9083 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9084 + (i * sizeof(struct tg3_rx_buffer_desc));
9085 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9086 i,
9087 readl(rxd + 0x0), readl(rxd + 0x4),
9088 readl(rxd + 0x8), readl(rxd + 0xc));
9089 rxd += (4 * sizeof(u32));
9090 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9091 i,
9092 readl(rxd + 0x0), readl(rxd + 0x4),
9093 readl(rxd + 0x8), readl(rxd + 0xc));
9094 }
9095}
9096#endif
9097
9098static struct net_device_stats *tg3_get_stats(struct net_device *);
9099static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9100
9101static int tg3_close(struct net_device *dev)
9102{
4f125f42 9103 int i;
1da177e4
LT		 9104 struct tg3 *tp = netdev_priv(dev);
9105
fed97810 9106 tg3_napi_disable(tp);
28e53bdd 9107 cancel_work_sync(&tp->reset_task);
7faa006f 9108
fe5f5787 9109 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9110
9111 del_timer_sync(&tp->timer);
9112
24bb4fb6
MC		 9113 tg3_phy_stop(tp);
9114
f47c11ee 9115 tg3_full_lock(tp, 1);
1da177e4
LT		 9116#if 0
9117 tg3_dump_state(tp);
9118#endif
9119
9120 tg3_disable_ints(tp);
9121
944d980e 9122 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9123 tg3_free_rings(tp);
5cf64b8a 9124 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9125
f47c11ee 9126 tg3_full_unlock(tp);
1da177e4 9127
4f125f42
MC		 9128 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9129 struct tg3_napi *tnapi = &tp->napi[i];
9130 free_irq(tnapi->irq_vec, tnapi);
9131 }
07b0173c
MC		 9132
9133 tg3_ints_fini(tp);
1da177e4
LT		 9134
9135 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9136 sizeof(tp->net_stats_prev));
9137 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9138 sizeof(tp->estats_prev));
9139
9140 tg3_free_consistent(tp);
9141
bc1c7567
MC		 9142 tg3_set_power_state(tp, PCI_D3hot);
9143
9144 netif_carrier_off(tp->dev);
9145
1da177e4
LT		 9146 return 0;
9147}
9148
9149static inline unsigned long get_stat64(tg3_stat64_t *val)
9150{
9151 unsigned long ret;
9152
9153#if (BITS_PER_LONG == 32)
9154 ret = val->low;
9155#else
9156 ret = ((u64)val->high << 32) | ((u64)val->low);
9157#endif
9158 return ret;
9159}
9160
816f8b86
SB		 9161static inline u64 get_estat64(tg3_stat64_t *val)
9162{
9163 return ((u64)val->high << 32) | ((u64)val->low);
9164}
9165
1da177e4
LT		 9166static unsigned long calc_crc_errors(struct tg3 *tp)
9167{
9168 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9169
9170 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9171 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9173 u32 val;
9174
f47c11ee 9175 spin_lock_bh(&tp->lock);
569a5df8
MC		 9176 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9177 tg3_writephy(tp, MII_TG3_TEST1,
9178 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9179 tg3_readphy(tp, 0x14, &val);
9180 } else
9181 val = 0;
f47c11ee 9182 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9183
9184 tp->phy_crc_errors += val;
9185
9186 return tp->phy_crc_errors;
9187 }
9188
9189 return get_stat64(&hw_stats->rx_fcs_errors);
9190}
9191
9192#define ESTAT_ADD(member) \
9193 estats->member = old_estats->member + \
816f8b86 9194 get_estat64(&hw_stats->member)
1da177e4
LT		 9195
9196static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9197{
9198 struct tg3_ethtool_stats *estats = &tp->estats;
9199 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9200 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9201
9202 if (!hw_stats)
9203 return old_estats;
9204
9205 ESTAT_ADD(rx_octets);
9206 ESTAT_ADD(rx_fragments);
9207 ESTAT_ADD(rx_ucast_packets);
9208 ESTAT_ADD(rx_mcast_packets);
9209 ESTAT_ADD(rx_bcast_packets);
9210 ESTAT_ADD(rx_fcs_errors);
9211 ESTAT_ADD(rx_align_errors);
9212 ESTAT_ADD(rx_xon_pause_rcvd);
9213 ESTAT_ADD(rx_xoff_pause_rcvd);
9214 ESTAT_ADD(rx_mac_ctrl_rcvd);
9215 ESTAT_ADD(rx_xoff_entered);
9216 ESTAT_ADD(rx_frame_too_long_errors);
9217 ESTAT_ADD(rx_jabbers);
9218 ESTAT_ADD(rx_undersize_packets);
9219 ESTAT_ADD(rx_in_length_errors);
9220 ESTAT_ADD(rx_out_length_errors);
9221 ESTAT_ADD(rx_64_or_less_octet_packets);
9222 ESTAT_ADD(rx_65_to_127_octet_packets);
9223 ESTAT_ADD(rx_128_to_255_octet_packets);
9224 ESTAT_ADD(rx_256_to_511_octet_packets);
9225 ESTAT_ADD(rx_512_to_1023_octet_packets);
9226 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9227 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9228 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9229 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9230 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9231
9232 ESTAT_ADD(tx_octets);
9233 ESTAT_ADD(tx_collisions);
9234 ESTAT_ADD(tx_xon_sent);
9235 ESTAT_ADD(tx_xoff_sent);
9236 ESTAT_ADD(tx_flow_control);
9237 ESTAT_ADD(tx_mac_errors);
9238 ESTAT_ADD(tx_single_collisions);
9239 ESTAT_ADD(tx_mult_collisions);
9240 ESTAT_ADD(tx_deferred);
9241 ESTAT_ADD(tx_excessive_collisions);
9242 ESTAT_ADD(tx_late_collisions);
9243 ESTAT_ADD(tx_collide_2times);
9244 ESTAT_ADD(tx_collide_3times);
9245 ESTAT_ADD(tx_collide_4times);
9246 ESTAT_ADD(tx_collide_5times);
9247 ESTAT_ADD(tx_collide_6times);
9248 ESTAT_ADD(tx_collide_7times);
9249 ESTAT_ADD(tx_collide_8times);
9250 ESTAT_ADD(tx_collide_9times);
9251 ESTAT_ADD(tx_collide_10times);
9252 ESTAT_ADD(tx_collide_11times);
9253 ESTAT_ADD(tx_collide_12times);
9254 ESTAT_ADD(tx_collide_13times);
9255 ESTAT_ADD(tx_collide_14times);
9256 ESTAT_ADD(tx_collide_15times);
9257 ESTAT_ADD(tx_ucast_packets);
9258 ESTAT_ADD(tx_mcast_packets);
9259 ESTAT_ADD(tx_bcast_packets);
9260 ESTAT_ADD(tx_carrier_sense_errors);
9261 ESTAT_ADD(tx_discards);
9262 ESTAT_ADD(tx_errors);
9263
9264 ESTAT_ADD(dma_writeq_full);
9265 ESTAT_ADD(dma_write_prioq_full);
9266 ESTAT_ADD(rxbds_empty);
9267 ESTAT_ADD(rx_discards);
9268 ESTAT_ADD(rx_errors);
9269 ESTAT_ADD(rx_threshold_hit);
9270
9271 ESTAT_ADD(dma_readq_full);
9272 ESTAT_ADD(dma_read_prioq_full);
9273 ESTAT_ADD(tx_comp_queue_full);
9274
9275 ESTAT_ADD(ring_set_send_prod_index);
9276 ESTAT_ADD(ring_status_update);
9277 ESTAT_ADD(nic_irqs);
9278 ESTAT_ADD(nic_avoided_irqs);
9279 ESTAT_ADD(nic_tx_threshold_hit);
9280
9281 return estats;
9282}
9283
9284static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9285{
9286 struct tg3 *tp = netdev_priv(dev);
9287 struct net_device_stats *stats = &tp->net_stats;
9288 struct net_device_stats *old_stats = &tp->net_stats_prev;
9289 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9290
9291 if (!hw_stats)
9292 return old_stats;
9293
9294 stats->rx_packets = old_stats->rx_packets +
9295 get_stat64(&hw_stats->rx_ucast_packets) +
9296 get_stat64(&hw_stats->rx_mcast_packets) +
9297 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9298
1da177e4
LT		 9299 stats->tx_packets = old_stats->tx_packets +
9300 get_stat64(&hw_stats->tx_ucast_packets) +
9301 get_stat64(&hw_stats->tx_mcast_packets) +
9302 get_stat64(&hw_stats->tx_bcast_packets);
9303
9304 stats->rx_bytes = old_stats->rx_bytes +
9305 get_stat64(&hw_stats->rx_octets);
9306 stats->tx_bytes = old_stats->tx_bytes +
9307 get_stat64(&hw_stats->tx_octets);
9308
9309 stats->rx_errors = old_stats->rx_errors +
4f63b877 9310 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9311 stats->tx_errors = old_stats->tx_errors +
9312 get_stat64(&hw_stats->tx_errors) +
9313 get_stat64(&hw_stats->tx_mac_errors) +
9314 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9315 get_stat64(&hw_stats->tx_discards);
9316
9317 stats->multicast = old_stats->multicast +
9318 get_stat64(&hw_stats->rx_mcast_packets);
9319 stats->collisions = old_stats->collisions +
9320 get_stat64(&hw_stats->tx_collisions);
9321
9322 stats->rx_length_errors = old_stats->rx_length_errors +
9323 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9324 get_stat64(&hw_stats->rx_undersize_packets);
9325
9326 stats->rx_over_errors = old_stats->rx_over_errors +
9327 get_stat64(&hw_stats->rxbds_empty);
9328 stats->rx_frame_errors = old_stats->rx_frame_errors +
9329 get_stat64(&hw_stats->rx_align_errors);
9330 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9331 get_stat64(&hw_stats->tx_discards);
9332 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9333 get_stat64(&hw_stats->tx_carrier_sense_errors);
9334
9335 stats->rx_crc_errors = old_stats->rx_crc_errors +
9336 calc_crc_errors(tp);
9337
4f63b877
JL		 9338 stats->rx_missed_errors = old_stats->rx_missed_errors +
9339 get_stat64(&hw_stats->rx_discards);
9340
1da177e4
LT		 9341 return stats;
9342}
9343
9344static inline u32 calc_crc(unsigned char *buf, int len)
9345{
9346 u32 reg;
9347 u32 tmp;
9348 int j, k;
9349
9350 reg = 0xffffffff;
9351
9352 for (j = 0; j < len; j++) {
9353 reg ^= buf[j];
9354
9355 for (k = 0; k < 8; k++) {
9356 tmp = reg & 0x01;
9357
9358 reg >>= 1;
9359
9360 if (tmp) {
9361 reg ^= 0xedb88320;
9362 }
9363 }
9364 }
9365
9366 return ~reg;
9367}
9368
9369static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9370{
9371 /* accept or reject all multicast frames */
9372 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9373 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9374 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9375 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9376}
9377
9378static void __tg3_set_rx_mode(struct net_device *dev)
9379{
9380 struct tg3 *tp = netdev_priv(dev);
9381 u32 rx_mode;
9382
9383 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9384 RX_MODE_KEEP_VLAN_TAG);
9385
9386 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9387 * flag clear.
9388 */
9389#if TG3_VLAN_TAG_USED
9390 if (!tp->vlgrp &&
9391 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9392 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9393#else
9394 /* By definition, VLAN is disabled always in this
9395 * case.
9396 */
9397 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9398 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9399#endif
9400
9401 if (dev->flags & IFF_PROMISC) {
9402 /* Promiscuous mode. */
9403 rx_mode |= RX_MODE_PROMISC;
9404 } else if (dev->flags & IFF_ALLMULTI) {
9405 /* Accept all multicast. */
9406 tg3_set_multi (tp, 1);
9407 } else if (dev->mc_count < 1) {
9408 /* Reject all multicast. */
9409 tg3_set_multi (tp, 0);
9410 } else {
9411 /* Accept one or more multicast(s). */
9412 struct dev_mc_list *mclist;
9413 unsigned int i;
9414 u32 mc_filter[4] = { 0, };
9415 u32 regidx;
9416 u32 bit;
9417 u32 crc;
9418
9419 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9420 i++, mclist = mclist->next) {
9421
9422 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9423 bit = ~crc & 0x7f;
9424 regidx = (bit & 0x60) >> 5;
9425 bit &= 0x1f;
9426 mc_filter[regidx] |= (1 << bit);
9427 }
9428
9429 tw32(MAC_HASH_REG_0, mc_filter[0]);
9430 tw32(MAC_HASH_REG_1, mc_filter[1]);
9431 tw32(MAC_HASH_REG_2, mc_filter[2]);
9432 tw32(MAC_HASH_REG_3, mc_filter[3]);
9433 }
9434
9435 if (rx_mode != tp->rx_mode) {
9436 tp->rx_mode = rx_mode;
9437 tw32_f(MAC_RX_MODE, rx_mode);
9438 udelay(10);
9439 }
9440}
9441
9442static void tg3_set_rx_mode(struct net_device *dev)
9443{
9444 struct tg3 *tp = netdev_priv(dev);
9445
e75f7c90
MC		 9446 if (!netif_running(dev))
9447 return;
9448
f47c11ee 9449 tg3_full_lock(tp, 0);
1da177e4 9450 __tg3_set_rx_mode(dev);
f47c11ee 9451 tg3_full_unlock(tp);
1da177e4
LT		 9452}
9453
9454#define TG3_REGDUMP_LEN (32 * 1024)
9455
9456static int tg3_get_regs_len(struct net_device *dev)
9457{
9458 return TG3_REGDUMP_LEN;
9459}
9460
9461static void tg3_get_regs(struct net_device *dev,
9462 struct ethtool_regs *regs, void *_p)
9463{
9464 u32 *p = _p;
9465 struct tg3 *tp = netdev_priv(dev);
9466 u8 *orig_p = _p;
9467 int i;
9468
9469 regs->version = 0;
9470
9471 memset(p, 0, TG3_REGDUMP_LEN);
9472
bc1c7567
MC		 9473 if (tp->link_config.phy_is_low_power)
9474 return;
9475
f47c11ee 9476 tg3_full_lock(tp, 0);
1da177e4
LT		 9477
9478#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9479#define GET_REG32_LOOP(base,len) \
9480do { p = (u32 *)(orig_p + (base)); \
9481 for (i = 0; i < len; i += 4) \
9482 __GET_REG32((base) + i); \
9483} while (0)
9484#define GET_REG32_1(reg) \
9485do { p = (u32 *)(orig_p + (reg)); \
9486 __GET_REG32((reg)); \
9487} while (0)
9488
9489 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9490 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9491 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9492 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9493 GET_REG32_1(SNDDATAC_MODE);
9494 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9495 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9496 GET_REG32_1(SNDBDC_MODE);
9497 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9498 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9499 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9500 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9501 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9502 GET_REG32_1(RCVDCC_MODE);
9503 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9504 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9505 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9506 GET_REG32_1(MBFREE_MODE);
9507 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9508 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9509 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9510 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9511 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9512 GET_REG32_1(RX_CPU_MODE);
9513 GET_REG32_1(RX_CPU_STATE);
9514 GET_REG32_1(RX_CPU_PGMCTR);
9515 GET_REG32_1(RX_CPU_HWBKPT);
9516 GET_REG32_1(TX_CPU_MODE);
9517 GET_REG32_1(TX_CPU_STATE);
9518 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9519 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9520 GET_REG32_LOOP(FTQ_RESET, 0x120);
9521 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9522 GET_REG32_1(DMAC_MODE);
9523 GET_REG32_LOOP(GRC_MODE, 0x4c);
9524 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9525 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9526
9527#undef __GET_REG32
9528#undef GET_REG32_LOOP
9529#undef GET_REG32_1
9530
f47c11ee 9531 tg3_full_unlock(tp);
1da177e4
LT		 9532}
9533
9534static int tg3_get_eeprom_len(struct net_device *dev)
9535{
9536 struct tg3 *tp = netdev_priv(dev);
9537
9538 return tp->nvram_size;
9539}
9540
1da177e4
LT		 9541static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9542{
9543 struct tg3 *tp = netdev_priv(dev);
9544 int ret;
9545 u8 *pd;
b9fc7dc5 9546 u32 i, offset, len, b_offset, b_count;
a9dc529d 9547 __be32 val;
1da177e4 9548
df259d8c
MC		 9549 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9550 return -EINVAL;
9551
bc1c7567
MC		 9552 if (tp->link_config.phy_is_low_power)
9553 return -EAGAIN;
9554
1da177e4
LT		 9555 offset = eeprom->offset;
9556 len = eeprom->len;
9557 eeprom->len = 0;
9558
9559 eeprom->magic = TG3_EEPROM_MAGIC;
9560
9561 if (offset & 3) {
9562 /* adjustments to start on required 4 byte boundary */
9563 b_offset = offset & 3;
9564 b_count = 4 - b_offset;
9565 if (b_count > len) {
9566 /* i.e. offset=1 len=2 */
9567 b_count = len;
9568 }
a9dc529d 9569 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9570 if (ret)
9571 return ret;
1da177e4
LT		 9572 memcpy(data, ((char*)&val) + b_offset, b_count);
9573 len -= b_count;
9574 offset += b_count;
9575 eeprom->len += b_count;
9576 }
9577
9578 /* read bytes upto the last 4 byte boundary */
9579 pd = &data[eeprom->len];
9580 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9581 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9582 if (ret) {
9583 eeprom->len += i;
9584 return ret;
9585 }
1da177e4
LT		 9586 memcpy(pd + i, &val, 4);
9587 }
9588 eeprom->len += i;
9589
9590 if (len & 3) {
9591 /* read last bytes not ending on 4 byte boundary */
9592 pd = &data[eeprom->len];
9593 b_count = len & 3;
9594 b_offset = offset + len - b_count;
a9dc529d 9595 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9596 if (ret)
9597 return ret;
b9fc7dc5 9598 memcpy(pd, &val, b_count);
1da177e4
LT		 9599 eeprom->len += b_count;
9600 }
9601 return 0;
9602}
9603
6aa20a22 9604static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9605
9606static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9607{
9608 struct tg3 *tp = netdev_priv(dev);
9609 int ret;
b9fc7dc5 9610 u32 offset, len, b_offset, odd_len;
1da177e4 9611 u8 *buf;
a9dc529d 9612 __be32 start, end;
1da177e4 9613
bc1c7567
MC		 9614 if (tp->link_config.phy_is_low_power)
9615 return -EAGAIN;
9616
df259d8c
MC		 9617 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9618 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9619 return -EINVAL;
9620
9621 offset = eeprom->offset;
9622 len = eeprom->len;
9623
9624 if ((b_offset = (offset & 3))) {
9625 /* adjustments to start on required 4 byte boundary */
a9dc529d 9626 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9627 if (ret)
9628 return ret;
1da177e4
LT		 9629 len += b_offset;
9630 offset &= ~3;
1c8594b4
MC		 9631 if (len < 4)
9632 len = 4;
1da177e4
LT		 9633 }
9634
9635 odd_len = 0;
1c8594b4 9636 if (len & 3) {
1da177e4
LT		 9637 /* adjustments to end on required 4 byte boundary */
9638 odd_len = 1;
9639 len = (len + 3) & ~3;
a9dc529d 9640 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9641 if (ret)
9642 return ret;
1da177e4
LT		 9643 }
9644
9645 buf = data;
9646 if (b_offset || odd_len) {
9647 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9648 if (!buf)
1da177e4
LT		 9649 return -ENOMEM;
9650 if (b_offset)
9651 memcpy(buf, &start, 4);
9652 if (odd_len)
9653 memcpy(buf+len-4, &end, 4);
9654 memcpy(buf + b_offset, data, eeprom->len);
9655 }
9656
9657 ret = tg3_nvram_write_block(tp, offset, len, buf);
9658
9659 if (buf != data)
9660 kfree(buf);
9661
9662 return ret;
9663}
9664
9665static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9666{
b02fd9e3
MC		 9667 struct tg3 *tp = netdev_priv(dev);
9668
9669 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9670 struct phy_device *phydev;
b02fd9e3
MC		 9671 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9672 return -EAGAIN;
3f0e3ad7
MC		 9673 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9674 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9675 }
6aa20a22 9676
1da177e4
LT		 9677 cmd->supported = (SUPPORTED_Autoneg);
9678
9679 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9680 cmd->supported |= (SUPPORTED_1000baseT_Half |
9681 SUPPORTED_1000baseT_Full);
9682
ef348144 9683 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9684 cmd->supported |= (SUPPORTED_100baseT_Half |
9685 SUPPORTED_100baseT_Full |
9686 SUPPORTED_10baseT_Half |
9687 SUPPORTED_10baseT_Full |
3bebab59 9688 SUPPORTED_TP);
ef348144
KK		 9689 cmd->port = PORT_TP;
9690 } else {
1da177e4 9691 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9692 cmd->port = PORT_FIBRE;
9693 }
6aa20a22 9694
1da177e4
LT		 9695 cmd->advertising = tp->link_config.advertising;
9696 if (netif_running(dev)) {
9697 cmd->speed = tp->link_config.active_speed;
9698 cmd->duplex = tp->link_config.active_duplex;
9699 }
882e9793 9700 cmd->phy_address = tp->phy_addr;
7e5856bd 9701 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9702 cmd->autoneg = tp->link_config.autoneg;
9703 cmd->maxtxpkt = 0;
9704 cmd->maxrxpkt = 0;
9705 return 0;
9706}
6aa20a22 9707
1da177e4
LT		 9708static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9709{
9710 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9711
b02fd9e3 9712 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9713 struct phy_device *phydev;
b02fd9e3
MC		 9714 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9715 return -EAGAIN;
3f0e3ad7
MC		 9716 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9717 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9718 }
9719
7e5856bd
MC		 9720 if (cmd->autoneg != AUTONEG_ENABLE &&
9721 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9722 return -EINVAL;
7e5856bd
MC		 9723
9724 if (cmd->autoneg == AUTONEG_DISABLE &&
9725 cmd->duplex != DUPLEX_FULL &&
9726 cmd->duplex != DUPLEX_HALF)
37ff238d 9727 return -EINVAL;
1da177e4 9728
7e5856bd
MC		 9729 if (cmd->autoneg == AUTONEG_ENABLE) {
9730 u32 mask = ADVERTISED_Autoneg |
9731 ADVERTISED_Pause |
9732 ADVERTISED_Asym_Pause;
9733
9734 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9735 mask |= ADVERTISED_1000baseT_Half |
9736 ADVERTISED_1000baseT_Full;
9737
9738 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9739 mask |= ADVERTISED_100baseT_Half |
9740 ADVERTISED_100baseT_Full |
9741 ADVERTISED_10baseT_Half |
9742 ADVERTISED_10baseT_Full |
9743 ADVERTISED_TP;
9744 else
9745 mask |= ADVERTISED_FIBRE;
9746
9747 if (cmd->advertising & ~mask)
9748 return -EINVAL;
9749
9750 mask &= (ADVERTISED_1000baseT_Half |
9751 ADVERTISED_1000baseT_Full |
9752 ADVERTISED_100baseT_Half |
9753 ADVERTISED_100baseT_Full |
9754 ADVERTISED_10baseT_Half |
9755 ADVERTISED_10baseT_Full);
9756
9757 cmd->advertising &= mask;
9758 } else {
9759 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9760 if (cmd->speed != SPEED_1000)
9761 return -EINVAL;
9762
9763 if (cmd->duplex != DUPLEX_FULL)
9764 return -EINVAL;
9765 } else {
9766 if (cmd->speed != SPEED_100 &&
9767 cmd->speed != SPEED_10)
9768 return -EINVAL;
9769 }
9770 }
9771
f47c11ee 9772 tg3_full_lock(tp, 0);
1da177e4
LT		 9773
9774 tp->link_config.autoneg = cmd->autoneg;
9775 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9776 tp->link_config.advertising = (cmd->advertising |
9777 ADVERTISED_Autoneg);
1da177e4
LT		 9778 tp->link_config.speed = SPEED_INVALID;
9779 tp->link_config.duplex = DUPLEX_INVALID;
9780 } else {
9781 tp->link_config.advertising = 0;
9782 tp->link_config.speed = cmd->speed;
9783 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9784 }
6aa20a22 9785
24fcad6b
MC		 9786 tp->link_config.orig_speed = tp->link_config.speed;
9787 tp->link_config.orig_duplex = tp->link_config.duplex;
9788 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9789
1da177e4
LT		 9790 if (netif_running(dev))
9791 tg3_setup_phy(tp, 1);
9792
f47c11ee 9793 tg3_full_unlock(tp);
6aa20a22 9794
1da177e4
LT		 9795 return 0;
9796}
6aa20a22 9797
1da177e4
LT		 9798static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9799{
9800 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9801
1da177e4
LT		 9802 strcpy(info->driver, DRV_MODULE_NAME);
9803 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9804 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9805 strcpy(info->bus_info, pci_name(tp->pdev));
9806}
6aa20a22 9807
1da177e4
LT		 9808static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9809{
9810 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9811
12dac075
RW		 9812 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9813 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9814 wol->supported = WAKE_MAGIC;
9815 else
9816 wol->supported = 0;
1da177e4 9817 wol->wolopts = 0;
05ac4cb7
MC		 9818 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9819 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9820 wol->wolopts = WAKE_MAGIC;
9821 memset(&wol->sopass, 0, sizeof(wol->sopass));
9822}
6aa20a22 9823
1da177e4
LT		 9824static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9825{
9826 struct tg3 *tp = netdev_priv(dev);
12dac075 9827 struct device *dp = &tp->pdev->dev;
6aa20a22 9828
1da177e4
LT		 9829 if (wol->wolopts & ~WAKE_MAGIC)
9830 return -EINVAL;
9831 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9832 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9833 return -EINVAL;
6aa20a22 9834
f47c11ee 9835 spin_lock_bh(&tp->lock);
12dac075 9836 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9837 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9838 device_set_wakeup_enable(dp, true);
9839 } else {
1da177e4 9840 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9841 device_set_wakeup_enable(dp, false);
9842 }
f47c11ee 9843 spin_unlock_bh(&tp->lock);
6aa20a22 9844
1da177e4
LT		 9845 return 0;
9846}
6aa20a22 9847
1da177e4
LT		 9848static u32 tg3_get_msglevel(struct net_device *dev)
9849{
9850 struct tg3 *tp = netdev_priv(dev);
9851 return tp->msg_enable;
9852}
6aa20a22 9853
1da177e4
LT		 9854static void tg3_set_msglevel(struct net_device *dev, u32 value)
9855{
9856 struct tg3 *tp = netdev_priv(dev);
9857 tp->msg_enable = value;
9858}
6aa20a22 9859
1da177e4
LT		 9860static int tg3_set_tso(struct net_device *dev, u32 value)
9861{
9862 struct tg3 *tp = netdev_priv(dev);
9863
9864 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9865 if (value)
9866 return -EINVAL;
9867 return 0;
9868 }
027455ad 9869 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9870 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9871 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9872 if (value) {
b0026624 9873 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9874 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9876 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9877 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9878 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9880 dev->features |= NETIF_F_TSO_ECN;
9881 } else
9882 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9883 }
1da177e4
LT		 9884 return ethtool_op_set_tso(dev, value);
9885}
6aa20a22 9886
1da177e4
LT		 9887static int tg3_nway_reset(struct net_device *dev)
9888{
9889 struct tg3 *tp = netdev_priv(dev);
1da177e4 9890 int r;
6aa20a22 9891
1da177e4
LT		 9892 if (!netif_running(dev))
9893 return -EAGAIN;
9894
c94e3941
MC		 9895 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9896 return -EINVAL;
9897
b02fd9e3
MC		 9898 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9899 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9900 return -EAGAIN;
3f0e3ad7 9901 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9902 } else {
9903 u32 bmcr;
9904
9905 spin_lock_bh(&tp->lock);
9906 r = -EINVAL;
9907 tg3_readphy(tp, MII_BMCR, &bmcr);
9908 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9909 ((bmcr & BMCR_ANENABLE) ||
9910 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9911 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9912 BMCR_ANENABLE);
9913 r = 0;
9914 }
9915 spin_unlock_bh(&tp->lock);
1da177e4 9916 }
6aa20a22 9917
1da177e4
LT		 9918 return r;
9919}
6aa20a22 9920
1da177e4
LT		 9921static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9922{
9923 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9924
1da177e4
LT		 9925 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9926 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9927 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9928 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9929 else
9930 ering->rx_jumbo_max_pending = 0;
9931
9932 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9933
9934 ering->rx_pending = tp->rx_pending;
9935 ering->rx_mini_pending = 0;
4f81c32b
MC		 9936 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9937 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9938 else
9939 ering->rx_jumbo_pending = 0;
9940
f3f3f27e 9941 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9942}
6aa20a22 9943
1da177e4
LT		 9944static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9945{
9946 struct tg3 *tp = netdev_priv(dev);
646c9edd 9947 int i, irq_sync = 0, err = 0;
6aa20a22 9948
1da177e4
LT		 9949 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9950 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9951 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9952 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9953 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9954 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9955 return -EINVAL;
6aa20a22 9956
bbe832c0 9957 if (netif_running(dev)) {
b02fd9e3 9958 tg3_phy_stop(tp);
1da177e4 9959 tg3_netif_stop(tp);
bbe832c0
MC		 9960 irq_sync = 1;
9961 }
1da177e4 9962
bbe832c0 9963 tg3_full_lock(tp, irq_sync);
6aa20a22 9964
1da177e4
LT		 9965 tp->rx_pending = ering->rx_pending;
9966
9967 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9968 tp->rx_pending > 63)
9969 tp->rx_pending = 63;
9970 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9971
9972 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9973 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9974
9975 if (netif_running(dev)) {
944d980e 9976 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9977 err = tg3_restart_hw(tp, 1);
9978 if (!err)
9979 tg3_netif_start(tp);
1da177e4
LT		 9980 }
9981
f47c11ee 9982 tg3_full_unlock(tp);
6aa20a22 9983
b02fd9e3
MC		 9984 if (irq_sync && !err)
9985 tg3_phy_start(tp);
9986
b9ec6c1b 9987 return err;
1da177e4 9988}
6aa20a22 9989
1da177e4
LT		 9990static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9991{
9992 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9993
1da177e4 9994 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9995
e18ce346 9996 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9997 epause->rx_pause = 1;
9998 else
9999 epause->rx_pause = 0;
10000
e18ce346 10001 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10002 epause->tx_pause = 1;
10003 else
10004 epause->tx_pause = 0;
1da177e4 10005}
6aa20a22 10006
1da177e4
LT		 10007static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10008{
10009 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10010 int err = 0;
6aa20a22 10011
b02fd9e3
MC		 10012 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10013 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10014 return -EAGAIN;
1da177e4 10015
b02fd9e3
MC		 10016 if (epause->autoneg) {
10017 u32 newadv;
10018 struct phy_device *phydev;
f47c11ee 10019
3f0e3ad7 10020 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 10021
b02fd9e3
MC		 10022 if (epause->rx_pause) {
10023 if (epause->tx_pause)
10024 newadv = ADVERTISED_Pause;
10025 else
10026 newadv = ADVERTISED_Pause |
10027 ADVERTISED_Asym_Pause;
10028 } else if (epause->tx_pause) {
10029 newadv = ADVERTISED_Asym_Pause;
10030 } else
10031 newadv = 0;
10032
10033 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10034 u32 oldadv = phydev->advertising &
10035 (ADVERTISED_Pause |
10036 ADVERTISED_Asym_Pause);
10037 if (oldadv != newadv) {
10038 phydev->advertising &=
10039 ~(ADVERTISED_Pause |
10040 ADVERTISED_Asym_Pause);
10041 phydev->advertising |= newadv;
10042 err = phy_start_aneg(phydev);
10043 }
10044 } else {
10045 tp->link_config.advertising &=
10046 ~(ADVERTISED_Pause |
10047 ADVERTISED_Asym_Pause);
10048 tp->link_config.advertising |= newadv;
10049 }
10050 } else {
10051 if (epause->rx_pause)
e18ce346 10052 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10053 else
e18ce346 10054 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10055
b02fd9e3 10056 if (epause->tx_pause)
e18ce346 10057 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10058 else
e18ce346 10059 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10060
10061 if (netif_running(dev))
10062 tg3_setup_flow_control(tp, 0, 0);
10063 }
10064 } else {
10065 int irq_sync = 0;
10066
10067 if (netif_running(dev)) {
10068 tg3_netif_stop(tp);
10069 irq_sync = 1;
10070 }
10071
10072 tg3_full_lock(tp, irq_sync);
10073
10074 if (epause->autoneg)
10075 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10076 else
10077 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10078 if (epause->rx_pause)
e18ce346 10079 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10080 else
e18ce346 10081 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10082 if (epause->tx_pause)
e18ce346 10083 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10084 else
e18ce346 10085 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10086
10087 if (netif_running(dev)) {
10088 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10089 err = tg3_restart_hw(tp, 1);
10090 if (!err)
10091 tg3_netif_start(tp);
10092 }
10093
10094 tg3_full_unlock(tp);
10095 }
6aa20a22 10096
b9ec6c1b 10097 return err;
1da177e4 10098}
6aa20a22 10099
1da177e4
LT		 10100static u32 tg3_get_rx_csum(struct net_device *dev)
10101{
10102 struct tg3 *tp = netdev_priv(dev);
10103 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10104}
6aa20a22 10105
1da177e4
LT		 10106static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10107{
10108 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10109
1da177e4
LT		 10110 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10111 if (data != 0)
10112 return -EINVAL;
10113 return 0;
10114 }
6aa20a22 10115
f47c11ee 10116 spin_lock_bh(&tp->lock);
1da177e4
LT		 10117 if (data)
10118 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10119 else
10120 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10121 spin_unlock_bh(&tp->lock);
6aa20a22 10122
1da177e4
LT		 10123 return 0;
10124}
6aa20a22 10125
1da177e4
LT		 10126static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10127{
10128 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10129
1da177e4
LT		 10130 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10131 if (data != 0)
10132 return -EINVAL;
10133 return 0;
10134 }
6aa20a22 10135
321d32a0 10136 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10137 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10138 else
9c27dbdf 10139 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10140
10141 return 0;
10142}
10143
b9f2c044 10144static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10145{
b9f2c044
JG		 10146 switch (sset) {
10147 case ETH_SS_TEST:
10148 return TG3_NUM_TEST;
10149 case ETH_SS_STATS:
10150 return TG3_NUM_STATS;
10151 default:
10152 return -EOPNOTSUPP;
10153 }
4cafd3f5
MC		 10154}
10155
1da177e4
LT		 10156static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10157{
10158 switch (stringset) {
10159 case ETH_SS_STATS:
10160 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10161 break;
4cafd3f5
MC		 10162 case ETH_SS_TEST:
10163 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10164 break;
1da177e4
LT		 10165 default:
10166 WARN_ON(1); /* we need a WARN() */
10167 break;
10168 }
10169}
10170
4009a93d
MC		 10171static int tg3_phys_id(struct net_device *dev, u32 data)
10172{
10173 struct tg3 *tp = netdev_priv(dev);
10174 int i;
10175
10176 if (!netif_running(tp->dev))
10177 return -EAGAIN;
10178
10179 if (data == 0)
759afc31 10180 data = UINT_MAX / 2;
4009a93d
MC		 10181
10182 for (i = 0; i < (data * 2); i++) {
10183 if ((i % 2) == 0)
10184 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10185 LED_CTRL_1000MBPS_ON |
10186 LED_CTRL_100MBPS_ON |
10187 LED_CTRL_10MBPS_ON |
10188 LED_CTRL_TRAFFIC_OVERRIDE |
10189 LED_CTRL_TRAFFIC_BLINK |
10190 LED_CTRL_TRAFFIC_LED);
6aa20a22 10191
4009a93d
MC		 10192 else
10193 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10194 LED_CTRL_TRAFFIC_OVERRIDE);
10195
10196 if (msleep_interruptible(500))
10197 break;
10198 }
10199 tw32(MAC_LED_CTRL, tp->led_ctrl);
10200 return 0;
10201}
10202
1da177e4
LT		 10203static void tg3_get_ethtool_stats (struct net_device *dev,
10204 struct ethtool_stats *estats, u64 *tmp_stats)
10205{
10206 struct tg3 *tp = netdev_priv(dev);
10207 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10208}
10209
566f86ad 10210#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10211#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10212#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10213#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10214#define NVRAM_SELFBOOT_HW_SIZE 0x20
10215#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10216
10217static int tg3_test_nvram(struct tg3 *tp)
10218{
b9fc7dc5 10219 u32 csum, magic;
a9dc529d 10220 __be32 *buf;
ab0049b4 10221 int i, j, k, err = 0, size;
566f86ad 10222
df259d8c
MC		 10223 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10224 return 0;
10225
e4f34110 10226 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10227 return -EIO;
10228
1b27777a
MC		 10229 if (magic == TG3_EEPROM_MAGIC)
10230 size = NVRAM_TEST_SIZE;
b16250e3 10231 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10232 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10233 TG3_EEPROM_SB_FORMAT_1) {
10234 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10235 case TG3_EEPROM_SB_REVISION_0:
10236 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10237 break;
10238 case TG3_EEPROM_SB_REVISION_2:
10239 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10240 break;
10241 case TG3_EEPROM_SB_REVISION_3:
10242 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10243 break;
10244 default:
10245 return 0;
10246 }
10247 } else
1b27777a 10248 return 0;
b16250e3
MC		 10249 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10250 size = NVRAM_SELFBOOT_HW_SIZE;
10251 else
1b27777a
MC		 10252 return -EIO;
10253
10254 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10255 if (buf == NULL)
10256 return -ENOMEM;
10257
1b27777a
MC		 10258 err = -EIO;
10259 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10260 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10261 if (err)
566f86ad 10262 break;
566f86ad 10263 }
1b27777a 10264 if (i < size)
566f86ad
MC		 10265 goto out;
10266
1b27777a 10267 /* Selfboot format */
a9dc529d 10268 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10269 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10270 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10271 u8 *buf8 = (u8 *) buf, csum8 = 0;
10272
b9fc7dc5 10273 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10274 TG3_EEPROM_SB_REVISION_2) {
10275 /* For rev 2, the csum doesn't include the MBA. */
10276 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10277 csum8 += buf8[i];
10278 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10279 csum8 += buf8[i];
10280 } else {
10281 for (i = 0; i < size; i++)
10282 csum8 += buf8[i];
10283 }
1b27777a 10284
ad96b485
AB		 10285 if (csum8 == 0) {
10286 err = 0;
10287 goto out;
10288 }
10289
10290 err = -EIO;
10291 goto out;
1b27777a 10292 }
566f86ad 10293
b9fc7dc5 10294 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10295 TG3_EEPROM_MAGIC_HW) {
10296 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10297 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10298 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10299
10300 /* Separate the parity bits and the data bytes. */
10301 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10302 if ((i == 0) || (i == 8)) {
10303 int l;
10304 u8 msk;
10305
10306 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10307 parity[k++] = buf8[i] & msk;
10308 i++;
10309 }
10310 else if (i == 16) {
10311 int l;
10312 u8 msk;
10313
10314 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10315 parity[k++] = buf8[i] & msk;
10316 i++;
10317
10318 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10319 parity[k++] = buf8[i] & msk;
10320 i++;
10321 }
10322 data[j++] = buf8[i];
10323 }
10324
10325 err = -EIO;
10326 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10327 u8 hw8 = hweight8(data[i]);
10328
10329 if ((hw8 & 0x1) && parity[i])
10330 goto out;
10331 else if (!(hw8 & 0x1) && !parity[i])
10332 goto out;
10333 }
10334 err = 0;
10335 goto out;
10336 }
10337
566f86ad
MC		 10338 /* Bootstrap checksum at offset 0x10 */
10339 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10340 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10341 goto out;
10342
10343 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10344 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10345 if (csum != be32_to_cpu(buf[0xfc/4]))
10346 goto out;
566f86ad
MC		 10347
10348 err = 0;
10349
10350out:
10351 kfree(buf);
10352 return err;
10353}
10354
ca43007a
MC		 10355#define TG3_SERDES_TIMEOUT_SEC 2
10356#define TG3_COPPER_TIMEOUT_SEC 6
10357
10358static int tg3_test_link(struct tg3 *tp)
10359{
10360 int i, max;
10361
10362 if (!netif_running(tp->dev))
10363 return -ENODEV;
10364
4c987487 10365 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10366 max = TG3_SERDES_TIMEOUT_SEC;
10367 else
10368 max = TG3_COPPER_TIMEOUT_SEC;
10369
10370 for (i = 0; i < max; i++) {
10371 if (netif_carrier_ok(tp->dev))
10372 return 0;
10373
10374 if (msleep_interruptible(1000))
10375 break;
10376 }
10377
10378 return -EIO;
10379}
10380
a71116d1 10381/* Only test the commonly used registers */
30ca3e37 10382static int tg3_test_registers(struct tg3 *tp)
a71116d1 10383{
b16250e3 10384 int i, is_5705, is_5750;
a71116d1
MC		 10385 u32 offset, read_mask, write_mask, val, save_val, read_val;
10386 static struct {
10387 u16 offset;
10388 u16 flags;
10389#define TG3_FL_5705 0x1
10390#define TG3_FL_NOT_5705 0x2
10391#define TG3_FL_NOT_5788 0x4
b16250e3 10392#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10393 u32 read_mask;
10394 u32 write_mask;
10395 } reg_tbl[] = {
10396 /* MAC Control Registers */
10397 { MAC_MODE, TG3_FL_NOT_5705,
10398 0x00000000, 0x00ef6f8c },
10399 { MAC_MODE, TG3_FL_5705,
10400 0x00000000, 0x01ef6b8c },
10401 { MAC_STATUS, TG3_FL_NOT_5705,
10402 0x03800107, 0x00000000 },
10403 { MAC_STATUS, TG3_FL_5705,
10404 0x03800100, 0x00000000 },
10405 { MAC_ADDR_0_HIGH, 0x0000,
10406 0x00000000, 0x0000ffff },
10407 { MAC_ADDR_0_LOW, 0x0000,
10408 0x00000000, 0xffffffff },
10409 { MAC_RX_MTU_SIZE, 0x0000,
10410 0x00000000, 0x0000ffff },
10411 { MAC_TX_MODE, 0x0000,
10412 0x00000000, 0x00000070 },
10413 { MAC_TX_LENGTHS, 0x0000,
10414 0x00000000, 0x00003fff },
10415 { MAC_RX_MODE, TG3_FL_NOT_5705,
10416 0x00000000, 0x000007fc },
10417 { MAC_RX_MODE, TG3_FL_5705,
10418 0x00000000, 0x000007dc },
10419 { MAC_HASH_REG_0, 0x0000,
10420 0x00000000, 0xffffffff },
10421 { MAC_HASH_REG_1, 0x0000,
10422 0x00000000, 0xffffffff },
10423 { MAC_HASH_REG_2, 0x0000,
10424 0x00000000, 0xffffffff },
10425 { MAC_HASH_REG_3, 0x0000,
10426 0x00000000, 0xffffffff },
10427
10428 /* Receive Data and Receive BD Initiator Control Registers. */
10429 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10430 0x00000000, 0xffffffff },
10431 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10432 0x00000000, 0xffffffff },
10433 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10434 0x00000000, 0x00000003 },
10435 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10436 0x00000000, 0xffffffff },
10437 { RCVDBDI_STD_BD+0, 0x0000,
10438 0x00000000, 0xffffffff },
10439 { RCVDBDI_STD_BD+4, 0x0000,
10440 0x00000000, 0xffffffff },
10441 { RCVDBDI_STD_BD+8, 0x0000,
10442 0x00000000, 0xffff0002 },
10443 { RCVDBDI_STD_BD+0xc, 0x0000,
10444 0x00000000, 0xffffffff },
6aa20a22 10445
a71116d1
MC		 10446 /* Receive BD Initiator Control Registers. */
10447 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10448 0x00000000, 0xffffffff },
10449 { RCVBDI_STD_THRESH, TG3_FL_5705,
10450 0x00000000, 0x000003ff },
10451 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10452 0x00000000, 0xffffffff },
6aa20a22 10453
a71116d1
MC		 10454 /* Host Coalescing Control Registers. */
10455 { HOSTCC_MODE, TG3_FL_NOT_5705,
10456 0x00000000, 0x00000004 },
10457 { HOSTCC_MODE, TG3_FL_5705,
10458 0x00000000, 0x000000f6 },
10459 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10460 0x00000000, 0xffffffff },
10461 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10462 0x00000000, 0x000003ff },
10463 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10464 0x00000000, 0xffffffff },
10465 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10466 0x00000000, 0x000003ff },
10467 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10468 0x00000000, 0xffffffff },
10469 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10470 0x00000000, 0x000000ff },
10471 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10472 0x00000000, 0xffffffff },
10473 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10474 0x00000000, 0x000000ff },
10475 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10476 0x00000000, 0xffffffff },
10477 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10478 0x00000000, 0xffffffff },
10479 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10480 0x00000000, 0xffffffff },
10481 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10482 0x00000000, 0x000000ff },
10483 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10484 0x00000000, 0xffffffff },
10485 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10486 0x00000000, 0x000000ff },
10487 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10488 0x00000000, 0xffffffff },
10489 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10490 0x00000000, 0xffffffff },
10491 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10492 0x00000000, 0xffffffff },
10493 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10494 0x00000000, 0xffffffff },
10495 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10496 0x00000000, 0xffffffff },
10497 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10498 0xffffffff, 0x00000000 },
10499 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10500 0xffffffff, 0x00000000 },
10501
10502 /* Buffer Manager Control Registers. */
b16250e3 10503 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10504 0x00000000, 0x007fff80 },
b16250e3 10505 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10506 0x00000000, 0x007fffff },
10507 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10508 0x00000000, 0x0000003f },
10509 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10510 0x00000000, 0x000001ff },
10511 { BUFMGR_MB_HIGH_WATER, 0x0000,
10512 0x00000000, 0x000001ff },
10513 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10514 0xffffffff, 0x00000000 },
10515 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10516 0xffffffff, 0x00000000 },
6aa20a22 10517
a71116d1
MC		 10518 /* Mailbox Registers */
10519 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10520 0x00000000, 0x000001ff },
10521 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10522 0x00000000, 0x000001ff },
10523 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10524 0x00000000, 0x000007ff },
10525 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10526 0x00000000, 0x000001ff },
10527
10528 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10529 };
10530
b16250e3
MC		 10531 is_5705 = is_5750 = 0;
10532 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10533 is_5705 = 1;
b16250e3
MC		 10534 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10535 is_5750 = 1;
10536 }
a71116d1
MC		 10537
10538 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10539 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10540 continue;
10541
10542 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10543 continue;
10544
10545 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10546 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10547 continue;
10548
b16250e3
MC		 10549 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10550 continue;
10551
a71116d1
MC		 10552 offset = (u32) reg_tbl[i].offset;
10553 read_mask = reg_tbl[i].read_mask;
10554 write_mask = reg_tbl[i].write_mask;
10555
10556 /* Save the original register content */
10557 save_val = tr32(offset);
10558
10559 /* Determine the read-only value. */
10560 read_val = save_val & read_mask;
10561
10562 /* Write zero to the register, then make sure the read-only bits
10563 * are not changed and the read/write bits are all zeros.
10564 */
10565 tw32(offset, 0);
10566
10567 val = tr32(offset);
10568
10569 /* Test the read-only and read/write bits. */
10570 if (((val & read_mask) != read_val) || (val & write_mask))
10571 goto out;
10572
10573 /* Write ones to all the bits defined by RdMask and WrMask, then
10574 * make sure the read-only bits are not changed and the
10575 * read/write bits are all ones.
10576 */
10577 tw32(offset, read_mask | write_mask);
10578
10579 val = tr32(offset);
10580
10581 /* Test the read-only bits. */
10582 if ((val & read_mask) != read_val)
10583 goto out;
10584
10585 /* Test the read/write bits. */
10586 if ((val & write_mask) != write_mask)
10587 goto out;
10588
10589 tw32(offset, save_val);
10590 }
10591
10592 return 0;
10593
10594out:
9f88f29f
MC		 10595 if (netif_msg_hw(tp))
10596 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10597 offset);
a71116d1
MC		 10598 tw32(offset, save_val);
10599 return -EIO;
10600}
10601
7942e1db
MC		 10602static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10603{
f71e1309 10604 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10605 int i;
10606 u32 j;
10607
e9edda69 10608 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10609 for (j = 0; j < len; j += 4) {
10610 u32 val;
10611
10612 tg3_write_mem(tp, offset + j, test_pattern[i]);
10613 tg3_read_mem(tp, offset + j, &val);
10614 if (val != test_pattern[i])
10615 return -EIO;
10616 }
10617 }
10618 return 0;
10619}
10620
10621static int tg3_test_memory(struct tg3 *tp)
10622{
10623 static struct mem_entry {
10624 u32 offset;
10625 u32 len;
10626 } mem_tbl_570x[] = {
38690194 10627 { 0x00000000, 0x00b50},
7942e1db
MC		 10628 { 0x00002000, 0x1c000},
10629 { 0xffffffff, 0x00000}
10630 }, mem_tbl_5705[] = {
10631 { 0x00000100, 0x0000c},
10632 { 0x00000200, 0x00008},
7942e1db
MC		 10633 { 0x00004000, 0x00800},
10634 { 0x00006000, 0x01000},
10635 { 0x00008000, 0x02000},
10636 { 0x00010000, 0x0e000},
10637 { 0xffffffff, 0x00000}
79f4d13a
MC		 10638 }, mem_tbl_5755[] = {
10639 { 0x00000200, 0x00008},
10640 { 0x00004000, 0x00800},
10641 { 0x00006000, 0x00800},
10642 { 0x00008000, 0x02000},
10643 { 0x00010000, 0x0c000},
10644 { 0xffffffff, 0x00000}
b16250e3
MC		 10645 }, mem_tbl_5906[] = {
10646 { 0x00000200, 0x00008},
10647 { 0x00004000, 0x00400},
10648 { 0x00006000, 0x00400},
10649 { 0x00008000, 0x01000},
10650 { 0x00010000, 0x01000},
10651 { 0xffffffff, 0x00000}
7942e1db
MC		 10652 };
10653 struct mem_entry *mem_tbl;
10654 int err = 0;
10655 int i;
10656
321d32a0
MC		 10657 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10658 mem_tbl = mem_tbl_5755;
10659 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10660 mem_tbl = mem_tbl_5906;
10661 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10662 mem_tbl = mem_tbl_5705;
10663 else
7942e1db
MC		 10664 mem_tbl = mem_tbl_570x;
10665
10666 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10667 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10668 mem_tbl[i].len)) != 0)
10669 break;
10670 }
6aa20a22 10671
7942e1db
MC		 10672 return err;
10673}
10674
9f40dead
MC		 10675#define TG3_MAC_LOOPBACK 0
10676#define TG3_PHY_LOOPBACK 1
10677
10678static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10679{
9f40dead 10680 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10681 u32 desc_idx, coal_now;
c76949a6
MC		 10682 struct sk_buff *skb, *rx_skb;
10683 u8 *tx_data;
10684 dma_addr_t map;
10685 int num_pkts, tx_len, rx_len, i, err;
10686 struct tg3_rx_buffer_desc *desc;
898a56f8 10687 struct tg3_napi *tnapi, *rnapi;
21f581a5 10688 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10689
0c1d0e2b
MC		 10690 if (tp->irq_cnt > 1) {
10691 tnapi = &tp->napi[1];
10692 rnapi = &tp->napi[1];
10693 } else {
10694 tnapi = &tp->napi[0];
10695 rnapi = &tp->napi[0];
10696 }
fd2ce37f 10697 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10698
9f40dead 10699 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10700 /* HW errata - mac loopback fails in some cases on 5780.
10701 * Normal traffic and PHY loopback are not affected by
10702 * errata.
10703 */
10704 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10705 return 0;
10706
9f40dead 10707 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10708 MAC_MODE_PORT_INT_LPBACK;
10709 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10710 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10711 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10712 mac_mode |= MAC_MODE_PORT_MODE_MII;
10713 else
10714 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10715 tw32(MAC_MODE, mac_mode);
10716 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10717 u32 val;
10718
7f97a4bd
MC		 10719 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10720 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10721 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10722 } else
10723 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10724
9ef8ca99
MC		 10725 tg3_phy_toggle_automdix(tp, 0);
10726
3f7045c1 10727 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10728 udelay(40);
5d64ad34 10729
e8f3f6ca 10730 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10731 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10733 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10734 mac_mode |= MAC_MODE_PORT_MODE_MII;
10735 } else
10736 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10737
c94e3941
MC		 10738 /* reset to prevent losing 1st rx packet intermittently */
10739 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10740 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10741 udelay(10);
10742 tw32_f(MAC_RX_MODE, tp->rx_mode);
10743 }
e8f3f6ca
MC		 10744 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10745 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10746 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10747 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10748 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10749 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10750 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10751 }
9f40dead 10752 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10753 }
10754 else
10755 return -EINVAL;
c76949a6
MC		 10756
10757 err = -EIO;
10758
c76949a6 10759 tx_len = 1514;
a20e9c62 10760 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10761 if (!skb)
10762 return -ENOMEM;
10763
c76949a6
MC		 10764 tx_data = skb_put(skb, tx_len);
10765 memcpy(tx_data, tp->dev->dev_addr, 6);
10766 memset(tx_data + 6, 0x0, 8);
10767
10768 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10769
10770 for (i = 14; i < tx_len; i++)
10771 tx_data[i] = (u8) (i & 0xff);
10772
f4188d8a
AD		 10773 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10774 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10775 dev_kfree_skb(skb);
10776 return -EIO;
10777 }
c76949a6
MC		 10778
10779 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10780 rnapi->coal_now);
c76949a6
MC		 10781
10782 udelay(10);
10783
898a56f8 10784 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10785
c76949a6
MC		 10786 num_pkts = 0;
10787
f4188d8a 10788 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10789
f3f3f27e 10790 tnapi->tx_prod++;
c76949a6
MC		 10791 num_pkts++;
10792
f3f3f27e
MC		 10793 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10794 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10795
10796 udelay(10);
10797
303fc921
MC		 10798 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10799 for (i = 0; i < 35; i++) {
c76949a6 10800 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10801 coal_now);
c76949a6
MC		 10802
10803 udelay(10);
10804
898a56f8
MC		 10805 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10806 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10807 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10808 (rx_idx == (rx_start_idx + num_pkts)))
10809 break;
10810 }
10811
f4188d8a 10812 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10813 dev_kfree_skb(skb);
10814
f3f3f27e 10815 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10816 goto out;
10817
10818 if (rx_idx != rx_start_idx + num_pkts)
10819 goto out;
10820
72334482 10821 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10822 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10823 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10824 if (opaque_key != RXD_OPAQUE_RING_STD)
10825 goto out;
10826
10827 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10828 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10829 goto out;
10830
10831 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10832 if (rx_len != tx_len)
10833 goto out;
10834
21f581a5 10835 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10836
21f581a5 10837 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10838 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10839
10840 for (i = 14; i < tx_len; i++) {
10841 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10842 goto out;
10843 }
10844 err = 0;
6aa20a22 10845
c76949a6
MC		 10846 /* tg3_free_rings will unmap and free the rx_skb */
10847out:
10848 return err;
10849}
10850
9f40dead
MC		 10851#define TG3_MAC_LOOPBACK_FAILED 1
10852#define TG3_PHY_LOOPBACK_FAILED 2
10853#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10854 TG3_PHY_LOOPBACK_FAILED)
10855
10856static int tg3_test_loopback(struct tg3 *tp)
10857{
10858 int err = 0;
9936bcf6 10859 u32 cpmuctrl = 0;
9f40dead
MC		 10860
10861 if (!netif_running(tp->dev))
10862 return TG3_LOOPBACK_FAILED;
10863
b9ec6c1b
MC		 10864 err = tg3_reset_hw(tp, 1);
10865 if (err)
10866 return TG3_LOOPBACK_FAILED;
9f40dead 10867
6833c043
MC		 10868 /* Turn off gphy autopowerdown. */
10869 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10870 tg3_phy_toggle_apd(tp, false);
10871
321d32a0 10872 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10873 int i;
10874 u32 status;
10875
10876 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10877
10878 /* Wait for up to 40 microseconds to acquire lock. */
10879 for (i = 0; i < 4; i++) {
10880 status = tr32(TG3_CPMU_MUTEX_GNT);
10881 if (status == CPMU_MUTEX_GNT_DRIVER)
10882 break;
10883 udelay(10);
10884 }
10885
10886 if (status != CPMU_MUTEX_GNT_DRIVER)
10887 return TG3_LOOPBACK_FAILED;
10888
b2a5c19c 10889 /* Turn off link-based power management. */
e875093c 10890 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10891 tw32(TG3_CPMU_CTRL,
10892 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10893 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10894 }
10895
9f40dead
MC		 10896 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10897 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10898
321d32a0 10899 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10900 tw32(TG3_CPMU_CTRL, cpmuctrl);
10901
10902 /* Release the mutex */
10903 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10904 }
10905
dd477003
MC		 10906 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10907 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10908 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10909 err |= TG3_PHY_LOOPBACK_FAILED;
10910 }
10911
6833c043
MC		 10912 /* Re-enable gphy autopowerdown. */
10913 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10914 tg3_phy_toggle_apd(tp, true);
10915
9f40dead
MC		 10916 return err;
10917}
10918
4cafd3f5
MC		 10919static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10920 u64 *data)
10921{
566f86ad
MC		 10922 struct tg3 *tp = netdev_priv(dev);
10923
bc1c7567
MC		 10924 if (tp->link_config.phy_is_low_power)
10925 tg3_set_power_state(tp, PCI_D0);
10926
566f86ad
MC		 10927 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10928
10929 if (tg3_test_nvram(tp) != 0) {
10930 etest->flags |= ETH_TEST_FL_FAILED;
10931 data[0] = 1;
10932 }
ca43007a
MC		 10933 if (tg3_test_link(tp) != 0) {
10934 etest->flags |= ETH_TEST_FL_FAILED;
10935 data[1] = 1;
10936 }
a71116d1 10937 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10938 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10939
10940 if (netif_running(dev)) {
b02fd9e3 10941 tg3_phy_stop(tp);
a71116d1 10942 tg3_netif_stop(tp);
bbe832c0
MC		 10943 irq_sync = 1;
10944 }
a71116d1 10945
bbe832c0 10946 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10947
10948 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10949 err = tg3_nvram_lock(tp);
a71116d1
MC		 10950 tg3_halt_cpu(tp, RX_CPU_BASE);
10951 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10952 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10953 if (!err)
10954 tg3_nvram_unlock(tp);
a71116d1 10955
d9ab5ad1
MC		 10956 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10957 tg3_phy_reset(tp);
10958
a71116d1
MC		 10959 if (tg3_test_registers(tp) != 0) {
10960 etest->flags |= ETH_TEST_FL_FAILED;
10961 data[2] = 1;
10962 }
7942e1db
MC		 10963 if (tg3_test_memory(tp) != 0) {
10964 etest->flags |= ETH_TEST_FL_FAILED;
10965 data[3] = 1;
10966 }
9f40dead 10967 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10968 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10969
f47c11ee
DM		 10970 tg3_full_unlock(tp);
10971
d4bc3927
MC		 10972 if (tg3_test_interrupt(tp) != 0) {
10973 etest->flags |= ETH_TEST_FL_FAILED;
10974 data[5] = 1;
10975 }
f47c11ee
DM		 10976
10977 tg3_full_lock(tp, 0);
d4bc3927 10978
a71116d1
MC		 10979 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10980 if (netif_running(dev)) {
10981 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10982 err2 = tg3_restart_hw(tp, 1);
10983 if (!err2)
b9ec6c1b 10984 tg3_netif_start(tp);
a71116d1 10985 }
f47c11ee
DM		 10986
10987 tg3_full_unlock(tp);
b02fd9e3
MC		 10988
10989 if (irq_sync && !err2)
10990 tg3_phy_start(tp);
a71116d1 10991 }
bc1c7567
MC		 10992 if (tp->link_config.phy_is_low_power)
10993 tg3_set_power_state(tp, PCI_D3hot);
10994
4cafd3f5
MC		 10995}
10996
1da177e4
LT		 10997static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10998{
10999 struct mii_ioctl_data *data = if_mii(ifr);
11000 struct tg3 *tp = netdev_priv(dev);
11001 int err;
11002
b02fd9e3 11003 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11004 struct phy_device *phydev;
b02fd9e3
MC		 11005 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11006 return -EAGAIN;
3f0e3ad7
MC		 11007 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11008 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11009 }
11010
1da177e4
LT		 11011 switch(cmd) {
11012 case SIOCGMIIPHY:
882e9793 11013 data->phy_id = tp->phy_addr;
1da177e4
LT		 11014
11015 /* fallthru */
11016 case SIOCGMIIREG: {
11017 u32 mii_regval;
11018
11019 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11020 break; /* We have no PHY */
11021
bc1c7567
MC		 11022 if (tp->link_config.phy_is_low_power)
11023 return -EAGAIN;
11024
f47c11ee 11025 spin_lock_bh(&tp->lock);
1da177e4 11026 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11027 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11028
11029 data->val_out = mii_regval;
11030
11031 return err;
11032 }
11033
11034 case SIOCSMIIREG:
11035 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11036 break; /* We have no PHY */
11037
bc1c7567
MC		 11038 if (tp->link_config.phy_is_low_power)
11039 return -EAGAIN;
11040
f47c11ee 11041 spin_lock_bh(&tp->lock);
1da177e4 11042 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11043 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11044
11045 return err;
11046
11047 default:
11048 /* do nothing */
11049 break;
11050 }
11051 return -EOPNOTSUPP;
11052}
11053
11054#if TG3_VLAN_TAG_USED
11055static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11056{
11057 struct tg3 *tp = netdev_priv(dev);
11058
844b3eed
MC		 11059 if (!netif_running(dev)) {
11060 tp->vlgrp = grp;
11061 return;
11062 }
11063
11064 tg3_netif_stop(tp);
29315e87 11065
f47c11ee 11066 tg3_full_lock(tp, 0);
1da177e4
LT		 11067
11068 tp->vlgrp = grp;
11069
11070 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11071 __tg3_set_rx_mode(dev);
11072
844b3eed 11073 tg3_netif_start(tp);
46966545
MC		 11074
11075 tg3_full_unlock(tp);
1da177e4 11076}
1da177e4
LT		 11077#endif
11078
15f9850d
DM		 11079static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11080{
11081 struct tg3 *tp = netdev_priv(dev);
11082
11083 memcpy(ec, &tp->coal, sizeof(*ec));
11084 return 0;
11085}
11086
d244c892
MC		 11087static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11088{
11089 struct tg3 *tp = netdev_priv(dev);
11090 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11091 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11092
11093 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11094 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11095 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11096 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11097 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11098 }
11099
11100 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11101 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11102 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11103 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11104 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11105 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11106 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11107 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11108 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11109 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11110 return -EINVAL;
11111
11112 /* No rx interrupts will be generated if both are zero */
11113 if ((ec->rx_coalesce_usecs == 0) &&
11114 (ec->rx_max_coalesced_frames == 0))
11115 return -EINVAL;
11116
11117 /* No tx interrupts will be generated if both are zero */
11118 if ((ec->tx_coalesce_usecs == 0) &&
11119 (ec->tx_max_coalesced_frames == 0))
11120 return -EINVAL;
11121
11122 /* Only copy relevant parameters, ignore all others. */
11123 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11124 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11125 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11126 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11127 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11128 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11129 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11130 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11131 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11132
11133 if (netif_running(dev)) {
11134 tg3_full_lock(tp, 0);
11135 __tg3_set_coalesce(tp, &tp->coal);
11136 tg3_full_unlock(tp);
11137 }
11138 return 0;
11139}
11140
7282d491 11141static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11142 .get_settings = tg3_get_settings,
11143 .set_settings = tg3_set_settings,
11144 .get_drvinfo = tg3_get_drvinfo,
11145 .get_regs_len = tg3_get_regs_len,
11146 .get_regs = tg3_get_regs,
11147 .get_wol = tg3_get_wol,
11148 .set_wol = tg3_set_wol,
11149 .get_msglevel = tg3_get_msglevel,
11150 .set_msglevel = tg3_set_msglevel,
11151 .nway_reset = tg3_nway_reset,
11152 .get_link = ethtool_op_get_link,
11153 .get_eeprom_len = tg3_get_eeprom_len,
11154 .get_eeprom = tg3_get_eeprom,
11155 .set_eeprom = tg3_set_eeprom,
11156 .get_ringparam = tg3_get_ringparam,
11157 .set_ringparam = tg3_set_ringparam,
11158 .get_pauseparam = tg3_get_pauseparam,
11159 .set_pauseparam = tg3_set_pauseparam,
11160 .get_rx_csum = tg3_get_rx_csum,
11161 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11162 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11163 .set_sg = ethtool_op_set_sg,
1da177e4 11164 .set_tso = tg3_set_tso,
4cafd3f5 11165 .self_test = tg3_self_test,
1da177e4 11166 .get_strings = tg3_get_strings,
4009a93d 11167 .phys_id = tg3_phys_id,
1da177e4 11168 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11169 .get_coalesce = tg3_get_coalesce,
d244c892 11170 .set_coalesce = tg3_set_coalesce,
b9f2c044 11171 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11172};
11173
11174static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11175{
1b27777a 11176 u32 cursize, val, magic;
1da177e4
LT		 11177
11178 tp->nvram_size = EEPROM_CHIP_SIZE;
11179
e4f34110 11180 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11181 return;
11182
b16250e3
MC		 11183 if ((magic != TG3_EEPROM_MAGIC) &&
11184 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11185 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11186 return;
11187
11188 /*
11189 * Size the chip by reading offsets at increasing powers of two.
11190 * When we encounter our validation signature, we know the addressing
11191 * has wrapped around, and thus have our chip size.
11192 */
1b27777a 11193 cursize = 0x10;
1da177e4
LT		 11194
11195 while (cursize < tp->nvram_size) {
e4f34110 11196 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11197 return;
11198
1820180b 11199 if (val == magic)
1da177e4
LT		 11200 break;
11201
11202 cursize <<= 1;
11203 }
11204
11205 tp->nvram_size = cursize;
11206}
6aa20a22 11207
1da177e4
LT		 11208static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11209{
11210 u32 val;
11211
df259d8c
MC		 11212 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11213 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11214 return;
11215
11216 /* Selfboot format */
1820180b 11217 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11218 tg3_get_eeprom_size(tp);
11219 return;
11220 }
11221
6d348f2c 11222 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11223 if (val != 0) {
6d348f2c
MC		 11224 /* This is confusing. We want to operate on the
11225 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11226 * call will read from NVRAM and byteswap the data
11227 * according to the byteswapping settings for all
11228 * other register accesses. This ensures the data we
11229 * want will always reside in the lower 16-bits.
11230 * However, the data in NVRAM is in LE format, which
11231 * means the data from the NVRAM read will always be
11232 * opposite the endianness of the CPU. The 16-bit
11233 * byteswap then brings the data to CPU endianness.
11234 */
11235 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11236 return;
11237 }
11238 }
fd1122a2 11239 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11240}
11241
11242static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11243{
11244 u32 nvcfg1;
11245
11246 nvcfg1 = tr32(NVRAM_CFG1);
11247 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11248 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11249 } else {
1da177e4
LT		 11250 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11251 tw32(NVRAM_CFG1, nvcfg1);
11252 }
11253
4c987487 11254 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11255 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11256 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11257 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11258 tp->nvram_jedecnum = JEDEC_ATMEL;
11259 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11260 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261 break;
11262 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11263 tp->nvram_jedecnum = JEDEC_ATMEL;
11264 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11265 break;
11266 case FLASH_VENDOR_ATMEL_EEPROM:
11267 tp->nvram_jedecnum = JEDEC_ATMEL;
11268 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11269 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11270 break;
11271 case FLASH_VENDOR_ST:
11272 tp->nvram_jedecnum = JEDEC_ST;
11273 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11274 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11275 break;
11276 case FLASH_VENDOR_SAIFUN:
11277 tp->nvram_jedecnum = JEDEC_SAIFUN;
11278 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11279 break;
11280 case FLASH_VENDOR_SST_SMALL:
11281 case FLASH_VENDOR_SST_LARGE:
11282 tp->nvram_jedecnum = JEDEC_SST;
11283 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11284 break;
1da177e4 11285 }
8590a603 11286 } else {
1da177e4
LT		 11287 tp->nvram_jedecnum = JEDEC_ATMEL;
11288 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11289 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11290 }
11291}
11292
a1b950d5
MC		 11293static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11294{
11295 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11296 case FLASH_5752PAGE_SIZE_256:
11297 tp->nvram_pagesize = 256;
11298 break;
11299 case FLASH_5752PAGE_SIZE_512:
11300 tp->nvram_pagesize = 512;
11301 break;
11302 case FLASH_5752PAGE_SIZE_1K:
11303 tp->nvram_pagesize = 1024;
11304 break;
11305 case FLASH_5752PAGE_SIZE_2K:
11306 tp->nvram_pagesize = 2048;
11307 break;
11308 case FLASH_5752PAGE_SIZE_4K:
11309 tp->nvram_pagesize = 4096;
11310 break;
11311 case FLASH_5752PAGE_SIZE_264:
11312 tp->nvram_pagesize = 264;
11313 break;
11314 case FLASH_5752PAGE_SIZE_528:
11315 tp->nvram_pagesize = 528;
11316 break;
11317 }
11318}
11319
361b4ac2
MC		 11320static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11321{
11322 u32 nvcfg1;
11323
11324 nvcfg1 = tr32(NVRAM_CFG1);
11325
e6af301b
MC		 11326 /* NVRAM protection for TPM */
11327 if (nvcfg1 & (1 << 27))
f66a29b0 11328 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11329
361b4ac2 11330 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11331 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11332 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11333 tp->nvram_jedecnum = JEDEC_ATMEL;
11334 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11335 break;
11336 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11337 tp->nvram_jedecnum = JEDEC_ATMEL;
11338 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11339 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11340 break;
11341 case FLASH_5752VENDOR_ST_M45PE10:
11342 case FLASH_5752VENDOR_ST_M45PE20:
11343 case FLASH_5752VENDOR_ST_M45PE40:
11344 tp->nvram_jedecnum = JEDEC_ST;
11345 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11346 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11347 break;
361b4ac2
MC		 11348 }
11349
11350 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11351 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11352 } else {
361b4ac2
MC		 11353 /* For eeprom, set pagesize to maximum eeprom size */
11354 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11355
11356 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11357 tw32(NVRAM_CFG1, nvcfg1);
11358 }
11359}
11360
d3c7b886
MC		 11361static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11362{
989a9d23 11363 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11364
11365 nvcfg1 = tr32(NVRAM_CFG1);
11366
11367 /* NVRAM protection for TPM */
989a9d23 11368 if (nvcfg1 & (1 << 27)) {
f66a29b0 11369 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11370 protect = 1;
11371 }
d3c7b886 11372
989a9d23
MC		 11373 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11374 switch (nvcfg1) {
8590a603
MC		 11375 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11376 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11377 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11378 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11379 tp->nvram_jedecnum = JEDEC_ATMEL;
11380 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11381 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11382 tp->nvram_pagesize = 264;
11383 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11384 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11385 tp->nvram_size = (protect ? 0x3e200 :
11386 TG3_NVRAM_SIZE_512KB);
11387 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11388 tp->nvram_size = (protect ? 0x1f200 :
11389 TG3_NVRAM_SIZE_256KB);
11390 else
11391 tp->nvram_size = (protect ? 0x1f200 :
11392 TG3_NVRAM_SIZE_128KB);
11393 break;
11394 case FLASH_5752VENDOR_ST_M45PE10:
11395 case FLASH_5752VENDOR_ST_M45PE20:
11396 case FLASH_5752VENDOR_ST_M45PE40:
11397 tp->nvram_jedecnum = JEDEC_ST;
11398 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11399 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11400 tp->nvram_pagesize = 256;
11401 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11402 tp->nvram_size = (protect ?
11403 TG3_NVRAM_SIZE_64KB :
11404 TG3_NVRAM_SIZE_128KB);
11405 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11406 tp->nvram_size = (protect ?
11407 TG3_NVRAM_SIZE_64KB :
11408 TG3_NVRAM_SIZE_256KB);
11409 else
11410 tp->nvram_size = (protect ?
11411 TG3_NVRAM_SIZE_128KB :
11412 TG3_NVRAM_SIZE_512KB);
11413 break;
d3c7b886
MC		 11414 }
11415}
11416
1b27777a
MC		 11417static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11418{
11419 u32 nvcfg1;
11420
11421 nvcfg1 = tr32(NVRAM_CFG1);
11422
11423 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11424 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11425 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11426 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11427 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11428 tp->nvram_jedecnum = JEDEC_ATMEL;
11429 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11430 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11431
8590a603
MC		 11432 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11433 tw32(NVRAM_CFG1, nvcfg1);
11434 break;
11435 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11436 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11437 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11438 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11439 tp->nvram_jedecnum = JEDEC_ATMEL;
11440 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11441 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11442 tp->nvram_pagesize = 264;
11443 break;
11444 case FLASH_5752VENDOR_ST_M45PE10:
11445 case FLASH_5752VENDOR_ST_M45PE20:
11446 case FLASH_5752VENDOR_ST_M45PE40:
11447 tp->nvram_jedecnum = JEDEC_ST;
11448 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11450 tp->nvram_pagesize = 256;
11451 break;
1b27777a
MC		 11452 }
11453}
11454
6b91fa02
MC		 11455static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11456{
11457 u32 nvcfg1, protect = 0;
11458
11459 nvcfg1 = tr32(NVRAM_CFG1);
11460
11461 /* NVRAM protection for TPM */
11462 if (nvcfg1 & (1 << 27)) {
f66a29b0 11463 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11464 protect = 1;
11465 }
11466
11467 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11468 switch (nvcfg1) {
8590a603
MC		 11469 case FLASH_5761VENDOR_ATMEL_ADB021D:
11470 case FLASH_5761VENDOR_ATMEL_ADB041D:
11471 case FLASH_5761VENDOR_ATMEL_ADB081D:
11472 case FLASH_5761VENDOR_ATMEL_ADB161D:
11473 case FLASH_5761VENDOR_ATMEL_MDB021D:
11474 case FLASH_5761VENDOR_ATMEL_MDB041D:
11475 case FLASH_5761VENDOR_ATMEL_MDB081D:
11476 case FLASH_5761VENDOR_ATMEL_MDB161D:
11477 tp->nvram_jedecnum = JEDEC_ATMEL;
11478 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11479 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11480 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11481 tp->nvram_pagesize = 256;
11482 break;
11483 case FLASH_5761VENDOR_ST_A_M45PE20:
11484 case FLASH_5761VENDOR_ST_A_M45PE40:
11485 case FLASH_5761VENDOR_ST_A_M45PE80:
11486 case FLASH_5761VENDOR_ST_A_M45PE16:
11487 case FLASH_5761VENDOR_ST_M_M45PE20:
11488 case FLASH_5761VENDOR_ST_M_M45PE40:
11489 case FLASH_5761VENDOR_ST_M_M45PE80:
11490 case FLASH_5761VENDOR_ST_M_M45PE16:
11491 tp->nvram_jedecnum = JEDEC_ST;
11492 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11493 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11494 tp->nvram_pagesize = 256;
11495 break;
6b91fa02
MC		 11496 }
11497
11498 if (protect) {
11499 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11500 } else {
11501 switch (nvcfg1) {
8590a603
MC		 11502 case FLASH_5761VENDOR_ATMEL_ADB161D:
11503 case FLASH_5761VENDOR_ATMEL_MDB161D:
11504 case FLASH_5761VENDOR_ST_A_M45PE16:
11505 case FLASH_5761VENDOR_ST_M_M45PE16:
11506 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11507 break;
11508 case FLASH_5761VENDOR_ATMEL_ADB081D:
11509 case FLASH_5761VENDOR_ATMEL_MDB081D:
11510 case FLASH_5761VENDOR_ST_A_M45PE80:
11511 case FLASH_5761VENDOR_ST_M_M45PE80:
11512 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11513 break;
11514 case FLASH_5761VENDOR_ATMEL_ADB041D:
11515 case FLASH_5761VENDOR_ATMEL_MDB041D:
11516 case FLASH_5761VENDOR_ST_A_M45PE40:
11517 case FLASH_5761VENDOR_ST_M_M45PE40:
11518 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11519 break;
11520 case FLASH_5761VENDOR_ATMEL_ADB021D:
11521 case FLASH_5761VENDOR_ATMEL_MDB021D:
11522 case FLASH_5761VENDOR_ST_A_M45PE20:
11523 case FLASH_5761VENDOR_ST_M_M45PE20:
11524 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11525 break;
6b91fa02
MC		 11526 }
11527 }
11528}
11529
b5d3772c
MC		 11530static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11531{
11532 tp->nvram_jedecnum = JEDEC_ATMEL;
11533 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11534 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11535}
11536
321d32a0
MC		 11537static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11538{
11539 u32 nvcfg1;
11540
11541 nvcfg1 = tr32(NVRAM_CFG1);
11542
11543 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11544 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11545 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11546 tp->nvram_jedecnum = JEDEC_ATMEL;
11547 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11548 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11549
11550 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11551 tw32(NVRAM_CFG1, nvcfg1);
11552 return;
11553 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11554 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11555 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11556 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11557 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11558 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11559 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11560 tp->nvram_jedecnum = JEDEC_ATMEL;
11561 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11562 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11563
11564 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11565 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11566 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11567 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11568 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11569 break;
11570 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11571 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11572 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11573 break;
11574 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11575 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11576 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11577 break;
11578 }
11579 break;
11580 case FLASH_5752VENDOR_ST_M45PE10:
11581 case FLASH_5752VENDOR_ST_M45PE20:
11582 case FLASH_5752VENDOR_ST_M45PE40:
11583 tp->nvram_jedecnum = JEDEC_ST;
11584 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11585 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11586
11587 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11588 case FLASH_5752VENDOR_ST_M45PE10:
11589 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11590 break;
11591 case FLASH_5752VENDOR_ST_M45PE20:
11592 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11593 break;
11594 case FLASH_5752VENDOR_ST_M45PE40:
11595 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11596 break;
11597 }
11598 break;
11599 default:
df259d8c 11600 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11601 return;
11602 }
11603
a1b950d5
MC		 11604 tg3_nvram_get_pagesize(tp, nvcfg1);
11605 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11606 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11607}
11608
11609
11610static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11611{
11612 u32 nvcfg1;
11613
11614 nvcfg1 = tr32(NVRAM_CFG1);
11615
11616 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11617 case FLASH_5717VENDOR_ATMEL_EEPROM:
11618 case FLASH_5717VENDOR_MICRO_EEPROM:
11619 tp->nvram_jedecnum = JEDEC_ATMEL;
11620 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11621 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11622
11623 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11624 tw32(NVRAM_CFG1, nvcfg1);
11625 return;
11626 case FLASH_5717VENDOR_ATMEL_MDB011D:
11627 case FLASH_5717VENDOR_ATMEL_ADB011B:
11628 case FLASH_5717VENDOR_ATMEL_ADB011D:
11629 case FLASH_5717VENDOR_ATMEL_MDB021D:
11630 case FLASH_5717VENDOR_ATMEL_ADB021B:
11631 case FLASH_5717VENDOR_ATMEL_ADB021D:
11632 case FLASH_5717VENDOR_ATMEL_45USPT:
11633 tp->nvram_jedecnum = JEDEC_ATMEL;
11634 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11635 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11636
11637 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11638 case FLASH_5717VENDOR_ATMEL_MDB021D:
11639 case FLASH_5717VENDOR_ATMEL_ADB021B:
11640 case FLASH_5717VENDOR_ATMEL_ADB021D:
11641 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11642 break;
11643 default:
11644 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11645 break;
11646 }
321d32a0 11647 break;
a1b950d5
MC		 11648 case FLASH_5717VENDOR_ST_M_M25PE10:
11649 case FLASH_5717VENDOR_ST_A_M25PE10:
11650 case FLASH_5717VENDOR_ST_M_M45PE10:
11651 case FLASH_5717VENDOR_ST_A_M45PE10:
11652 case FLASH_5717VENDOR_ST_M_M25PE20:
11653 case FLASH_5717VENDOR_ST_A_M25PE20:
11654 case FLASH_5717VENDOR_ST_M_M45PE20:
11655 case FLASH_5717VENDOR_ST_A_M45PE20:
11656 case FLASH_5717VENDOR_ST_25USPT:
11657 case FLASH_5717VENDOR_ST_45USPT:
11658 tp->nvram_jedecnum = JEDEC_ST;
11659 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11660 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11661
11662 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11663 case FLASH_5717VENDOR_ST_M_M25PE20:
11664 case FLASH_5717VENDOR_ST_A_M25PE20:
11665 case FLASH_5717VENDOR_ST_M_M45PE20:
11666 case FLASH_5717VENDOR_ST_A_M45PE20:
11667 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11668 break;
11669 default:
11670 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11671 break;
11672 }
321d32a0 11673 break;
a1b950d5
MC		 11674 default:
11675 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11676 return;
321d32a0 11677 }
a1b950d5
MC		 11678
11679 tg3_nvram_get_pagesize(tp, nvcfg1);
11680 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11681 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11682}
11683
1da177e4
LT		 11684/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11685static void __devinit tg3_nvram_init(struct tg3 *tp)
11686{
1da177e4
LT		 11687 tw32_f(GRC_EEPROM_ADDR,
11688 (EEPROM_ADDR_FSM_RESET |
11689 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11690 EEPROM_ADDR_CLKPERD_SHIFT)));
11691
9d57f01c 11692 msleep(1);
1da177e4
LT		 11693
11694 /* Enable seeprom accesses. */
11695 tw32_f(GRC_LOCAL_CTRL,
11696 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11697 udelay(100);
11698
11699 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11700 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11701 tp->tg3_flags |= TG3_FLAG_NVRAM;
11702
ec41c7df
MC		 11703 if (tg3_nvram_lock(tp)) {
11704 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11705 "tg3_nvram_init failed.\n", tp->dev->name);
11706 return;
11707 }
e6af301b 11708 tg3_enable_nvram_access(tp);
1da177e4 11709
989a9d23
MC		 11710 tp->nvram_size = 0;
11711
361b4ac2
MC		 11712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11713 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11714 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11715 tg3_get_5755_nvram_info(tp);
d30cdd28 11716 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11719 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11720 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11721 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11722 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11723 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11724 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11725 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11726 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11727 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11728 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11729 else
11730 tg3_get_nvram_info(tp);
11731
989a9d23
MC		 11732 if (tp->nvram_size == 0)
11733 tg3_get_nvram_size(tp);
1da177e4 11734
e6af301b 11735 tg3_disable_nvram_access(tp);
381291b7 11736 tg3_nvram_unlock(tp);
1da177e4
LT		 11737
11738 } else {
11739 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11740
11741 tg3_get_eeprom_size(tp);
11742 }
11743}
11744
1da177e4
LT		 11745static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11746 u32 offset, u32 len, u8 *buf)
11747{
11748 int i, j, rc = 0;
11749 u32 val;
11750
11751 for (i = 0; i < len; i += 4) {
b9fc7dc5 11752 u32 addr;
a9dc529d 11753 __be32 data;
1da177e4
LT		 11754
11755 addr = offset + i;
11756
11757 memcpy(&data, buf + i, 4);
11758
62cedd11
MC		 11759 /*
11760 * The SEEPROM interface expects the data to always be opposite
11761 * the native endian format. We accomplish this by reversing
11762 * all the operations that would have been performed on the
11763 * data from a call to tg3_nvram_read_be32().
11764 */
11765 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11766
11767 val = tr32(GRC_EEPROM_ADDR);
11768 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11769
11770 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11771 EEPROM_ADDR_READ);
11772 tw32(GRC_EEPROM_ADDR, val |
11773 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11774 (addr & EEPROM_ADDR_ADDR_MASK) |
11775 EEPROM_ADDR_START |
11776 EEPROM_ADDR_WRITE);
6aa20a22 11777
9d57f01c 11778 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11779 val = tr32(GRC_EEPROM_ADDR);
11780
11781 if (val & EEPROM_ADDR_COMPLETE)
11782 break;
9d57f01c 11783 msleep(1);
1da177e4
LT		 11784 }
11785 if (!(val & EEPROM_ADDR_COMPLETE)) {
11786 rc = -EBUSY;
11787 break;
11788 }
11789 }
11790
11791 return rc;
11792}
11793
11794/* offset and length are dword aligned */
11795static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11796 u8 *buf)
11797{
11798 int ret = 0;
11799 u32 pagesize = tp->nvram_pagesize;
11800 u32 pagemask = pagesize - 1;
11801 u32 nvram_cmd;
11802 u8 *tmp;
11803
11804 tmp = kmalloc(pagesize, GFP_KERNEL);
11805 if (tmp == NULL)
11806 return -ENOMEM;
11807
11808 while (len) {
11809 int j;
e6af301b 11810 u32 phy_addr, page_off, size;
1da177e4
LT		 11811
11812 phy_addr = offset & ~pagemask;
6aa20a22 11813
1da177e4 11814 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11815 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11816 (__be32 *) (tmp + j));
11817 if (ret)
1da177e4
LT		 11818 break;
11819 }
11820 if (ret)
11821 break;
11822
11823 page_off = offset & pagemask;
11824 size = pagesize;
11825 if (len < size)
11826 size = len;
11827
11828 len -= size;
11829
11830 memcpy(tmp + page_off, buf, size);
11831
11832 offset = offset + (pagesize - page_off);
11833
e6af301b 11834 tg3_enable_nvram_access(tp);
1da177e4
LT		 11835
11836 /*
11837 * Before we can erase the flash page, we need
11838 * to issue a special "write enable" command.
11839 */
11840 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11841
11842 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11843 break;
11844
11845 /* Erase the target page */
11846 tw32(NVRAM_ADDR, phy_addr);
11847
11848 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11849 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11850
11851 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11852 break;
11853
11854 /* Issue another write enable to start the write. */
11855 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11856
11857 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11858 break;
11859
11860 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11861 __be32 data;
1da177e4 11862
b9fc7dc5 11863 data = *((__be32 *) (tmp + j));
a9dc529d 11864
b9fc7dc5 11865 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11866
11867 tw32(NVRAM_ADDR, phy_addr + j);
11868
11869 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11870 NVRAM_CMD_WR;
11871
11872 if (j == 0)
11873 nvram_cmd |= NVRAM_CMD_FIRST;
11874 else if (j == (pagesize - 4))
11875 nvram_cmd |= NVRAM_CMD_LAST;
11876
11877 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11878 break;
11879 }
11880 if (ret)
11881 break;
11882 }
11883
11884 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11885 tg3_nvram_exec_cmd(tp, nvram_cmd);
11886
11887 kfree(tmp);
11888
11889 return ret;
11890}
11891
11892/* offset and length are dword aligned */
11893static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11894 u8 *buf)
11895{
11896 int i, ret = 0;
11897
11898 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11899 u32 page_off, phy_addr, nvram_cmd;
11900 __be32 data;
1da177e4
LT		 11901
11902 memcpy(&data, buf + i, 4);
b9fc7dc5 11903 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11904
11905 page_off = offset % tp->nvram_pagesize;
11906
1820180b 11907 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11908
11909 tw32(NVRAM_ADDR, phy_addr);
11910
11911 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11912
11913 if ((page_off == 0) || (i == 0))
11914 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11915 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11916 nvram_cmd |= NVRAM_CMD_LAST;
11917
11918 if (i == (len - 4))
11919 nvram_cmd |= NVRAM_CMD_LAST;
11920
321d32a0
MC		 11921 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11922 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11923 (tp->nvram_jedecnum == JEDEC_ST) &&
11924 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11925
11926 if ((ret = tg3_nvram_exec_cmd(tp,
11927 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11928 NVRAM_CMD_DONE)))
11929
11930 break;
11931 }
11932 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11933 /* We always do complete word writes to eeprom. */
11934 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11935 }
11936
11937 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11938 break;
11939 }
11940 return ret;
11941}
11942
11943/* offset and length are dword aligned */
11944static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11945{
11946 int ret;
11947
1da177e4 11948 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11949 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11950 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11951 udelay(40);
11952 }
11953
11954 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11955 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11956 }
11957 else {
11958 u32 grc_mode;
11959
ec41c7df
MC		 11960 ret = tg3_nvram_lock(tp);
11961 if (ret)
11962 return ret;
1da177e4 11963
e6af301b
MC		 11964 tg3_enable_nvram_access(tp);
11965 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11966 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11967 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11968
11969 grc_mode = tr32(GRC_MODE);
11970 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11971
11972 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11973 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11974
11975 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11976 buf);
11977 }
11978 else {
11979 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11980 buf);
11981 }
11982
11983 grc_mode = tr32(GRC_MODE);
11984 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11985
e6af301b 11986 tg3_disable_nvram_access(tp);
1da177e4
LT		 11987 tg3_nvram_unlock(tp);
11988 }
11989
11990 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11991 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11992 udelay(40);
11993 }
11994
11995 return ret;
11996}
11997
11998struct subsys_tbl_ent {
11999 u16 subsys_vendor, subsys_devid;
12000 u32 phy_id;
12001};
12002
12003static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12004 /* Broadcom boards. */
12005 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12006 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12007 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12008 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12009 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12010 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12011 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12012 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12013 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12014 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12015 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12016
12017 /* 3com boards. */
12018 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12019 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12020 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12021 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12022 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12023
12024 /* DELL boards. */
12025 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12026 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12027 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12028 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12029
12030 /* Compaq boards. */
12031 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12032 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12033 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12034 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12035 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12036
12037 /* IBM boards. */
12038 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12039};
12040
12041static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12042{
12043 int i;
12044
12045 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12046 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12047 tp->pdev->subsystem_vendor) &&
12048 (subsys_id_to_phy_id[i].subsys_devid ==
12049 tp->pdev->subsystem_device))
12050 return &subsys_id_to_phy_id[i];
12051 }
12052 return NULL;
12053}
12054
7d0c41ef 12055static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12056{
1da177e4 12057 u32 val;
caf636c7
MC		 12058 u16 pmcsr;
12059
12060 /* On some early chips the SRAM cannot be accessed in D3hot state,
12061 * so need make sure we're in D0.
12062 */
12063 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12064 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12065 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12066 msleep(1);
7d0c41ef
MC		 12067
12068 /* Make sure register accesses (indirect or otherwise)
12069 * will function correctly.
12070 */
12071 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12072 tp->misc_host_ctrl);
1da177e4 12073
f49639e6
DM		 12074 /* The memory arbiter has to be enabled in order for SRAM accesses
12075 * to succeed. Normally on powerup the tg3 chip firmware will make
12076 * sure it is enabled, but other entities such as system netboot
12077 * code might disable it.
12078 */
12079 val = tr32(MEMARB_MODE);
12080 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12081
1da177e4 12082 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12083 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12084
a85feb8c
GZ		 12085 /* Assume an onboard device and WOL capable by default. */
12086 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12087
b5d3772c 12088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12089 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12090 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12091 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12092 }
0527ba35
MC		 12093 val = tr32(VCPU_CFGSHDW);
12094 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12095 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12096 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12097 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12098 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12099 goto done;
b5d3772c
MC		 12100 }
12101
1da177e4
LT		 12102 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12103 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12104 u32 nic_cfg, led_cfg;
a9daf367 12105 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12106 int eeprom_phy_serdes = 0;
1da177e4
LT		 12107
12108 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12109 tp->nic_sram_data_cfg = nic_cfg;
12110
12111 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12112 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12113 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12114 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12115 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12116 (ver > 0) && (ver < 0x100))
12117 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12118
a9daf367
MC		 12119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12120 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12121
1da177e4
LT		 12122 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12123 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12124 eeprom_phy_serdes = 1;
12125
12126 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12127 if (nic_phy_id != 0) {
12128 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12129 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12130
12131 eeprom_phy_id = (id1 >> 16) << 10;
12132 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12133 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12134 } else
12135 eeprom_phy_id = 0;
12136
7d0c41ef 12137 tp->phy_id = eeprom_phy_id;
747e8f8b 12138 if (eeprom_phy_serdes) {
a4e2b347 12139 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 12140 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12141 else
12142 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12143 }
7d0c41ef 12144
cbf46853 12145 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12146 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12147 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12148 else
1da177e4
LT		 12149 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12150
12151 switch (led_cfg) {
12152 default:
12153 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12154 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12155 break;
12156
12157 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12158 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12159 break;
12160
12161 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12162 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12163
12164 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12165 * read on some older 5700/5701 bootcode.
12166 */
12167 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12168 ASIC_REV_5700 ||
12169 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12170 ASIC_REV_5701)
12171 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12172
1da177e4
LT		 12173 break;
12174
12175 case SHASTA_EXT_LED_SHARED:
12176 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12177 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12178 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12179 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12180 LED_CTRL_MODE_PHY_2);
12181 break;
12182
12183 case SHASTA_EXT_LED_MAC:
12184 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12185 break;
12186
12187 case SHASTA_EXT_LED_COMBO:
12188 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12189 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12190 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12191 LED_CTRL_MODE_PHY_2);
12192 break;
12193
855e1111 12194 }
1da177e4
LT		 12195
12196 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12198 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12199 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12200
b2a5c19c
MC		 12201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12202 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12203
9d26e213 12204 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12205 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12206 if ((tp->pdev->subsystem_vendor ==
12207 PCI_VENDOR_ID_ARIMA) &&
12208 (tp->pdev->subsystem_device == 0x205a ||
12209 tp->pdev->subsystem_device == 0x2063))
12210 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12211 } else {
f49639e6 12212 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12213 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12214 }
1da177e4
LT		 12215
12216 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12217 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12218 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12219 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12220 }
b2b98d4a
MC		 12221
12222 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12223 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12224 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12225
a85feb8c
GZ		 12226 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12227 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12228 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12229
12dac075 12230 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12231 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12232 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12233
1da177e4
LT		 12234 if (cfg2 & (1 << 17))
12235 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12236
12237 /* serdes signal pre-emphasis in register 0x590 set by */
12238 /* bootcode if bit 18 is set */
12239 if (cfg2 & (1 << 18))
12240 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12241
321d32a0
MC		 12242 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12243 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12244 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12245 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12246
8ed5d97e
MC		 12247 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12248 u32 cfg3;
12249
12250 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12251 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12252 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12253 }
a9daf367
MC		 12254
12255 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12256 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12257 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12258 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12259 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12260 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12261 }
05ac4cb7
MC		 12262done:
12263 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12264 device_set_wakeup_enable(&tp->pdev->dev,
12265 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12266}
12267
b2a5c19c
MC		 12268static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12269{
12270 int i;
12271 u32 val;
12272
12273 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12274 tw32(OTP_CTRL, cmd);
12275
12276 /* Wait for up to 1 ms for command to execute. */
12277 for (i = 0; i < 100; i++) {
12278 val = tr32(OTP_STATUS);
12279 if (val & OTP_STATUS_CMD_DONE)
12280 break;
12281 udelay(10);
12282 }
12283
12284 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12285}
12286
12287/* Read the gphy configuration from the OTP region of the chip. The gphy
12288 * configuration is a 32-bit value that straddles the alignment boundary.
12289 * We do two 32-bit reads and then shift and merge the results.
12290 */
12291static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12292{
12293 u32 bhalf_otp, thalf_otp;
12294
12295 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12296
12297 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12298 return 0;
12299
12300 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12301
12302 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12303 return 0;
12304
12305 thalf_otp = tr32(OTP_READ_DATA);
12306
12307 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12308
12309 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12310 return 0;
12311
12312 bhalf_otp = tr32(OTP_READ_DATA);
12313
12314 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12315}
12316
7d0c41ef
MC		 12317static int __devinit tg3_phy_probe(struct tg3 *tp)
12318{
12319 u32 hw_phy_id_1, hw_phy_id_2;
12320 u32 hw_phy_id, hw_phy_id_masked;
12321 int err;
1da177e4 12322
b02fd9e3
MC		 12323 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12324 return tg3_phy_init(tp);
12325
1da177e4 12326 /* Reading the PHY ID register can conflict with ASF
877d0310 12327 * firmware access to the PHY hardware.
1da177e4
LT		 12328 */
12329 err = 0;
0d3031d9
MC		 12330 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12331 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12332 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12333 } else {
12334 /* Now read the physical PHY_ID from the chip and verify
12335 * that it is sane. If it doesn't look good, we fall back
12336 * to either the hard-coded table based PHY_ID and failing
12337 * that the value found in the eeprom area.
12338 */
12339 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12340 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12341
12342 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12343 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12344 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12345
12346 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12347 }
12348
12349 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12350 tp->phy_id = hw_phy_id;
12351 if (hw_phy_id_masked == PHY_ID_BCM8002)
12352 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12353 else
12354 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12355 } else {
7d0c41ef
MC		 12356 if (tp->phy_id != PHY_ID_INVALID) {
12357 /* Do nothing, phy ID already set up in
12358 * tg3_get_eeprom_hw_cfg().
12359 */
1da177e4
LT		 12360 } else {
12361 struct subsys_tbl_ent *p;
12362
12363 /* No eeprom signature? Try the hardcoded
12364 * subsys device table.
12365 */
12366 p = lookup_by_subsys(tp);
12367 if (!p)
12368 return -ENODEV;
12369
12370 tp->phy_id = p->phy_id;
12371 if (!tp->phy_id ||
12372 tp->phy_id == PHY_ID_BCM8002)
12373 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12374 }
12375 }
12376
747e8f8b 12377 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12378 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12379 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12380 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12381
12382 tg3_readphy(tp, MII_BMSR, &bmsr);
12383 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12384 (bmsr & BMSR_LSTATUS))
12385 goto skip_phy_reset;
6aa20a22 12386
1da177e4
LT		 12387 err = tg3_phy_reset(tp);
12388 if (err)
12389 return err;
12390
12391 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12392 ADVERTISE_100HALF | ADVERTISE_100FULL |
12393 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12394 tg3_ctrl = 0;
12395 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12396 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12397 MII_TG3_CTRL_ADV_1000_FULL);
12398 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12399 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12400 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12401 MII_TG3_CTRL_ENABLE_AS_MASTER);
12402 }
12403
3600d918
MC		 12404 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12405 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12406 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12407 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12408 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12409
12410 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12411 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12412
12413 tg3_writephy(tp, MII_BMCR,
12414 BMCR_ANENABLE | BMCR_ANRESTART);
12415 }
12416 tg3_phy_set_wirespeed(tp);
12417
12418 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12419 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12420 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12421 }
12422
12423skip_phy_reset:
12424 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12425 err = tg3_init_5401phy_dsp(tp);
12426 if (err)
12427 return err;
12428 }
12429
12430 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12431 err = tg3_init_5401phy_dsp(tp);
12432 }
12433
747e8f8b 12434 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12435 tp->link_config.advertising =
12436 (ADVERTISED_1000baseT_Half |
12437 ADVERTISED_1000baseT_Full |
12438 ADVERTISED_Autoneg |
12439 ADVERTISED_FIBRE);
12440 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12441 tp->link_config.advertising &=
12442 ~(ADVERTISED_1000baseT_Half |
12443 ADVERTISED_1000baseT_Full);
12444
12445 return err;
12446}
12447
12448static void __devinit tg3_read_partno(struct tg3 *tp)
12449{
141518c9 12450 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12451 unsigned int i;
1b27777a 12452 u32 magic;
1da177e4 12453
df259d8c
MC		 12454 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12455 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12456 goto out_not_found;
1da177e4 12457
1820180b 12458 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12459 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12460 u32 tmp;
1da177e4 12461
6d348f2c
MC		 12462 /* The data is in little-endian format in NVRAM.
12463 * Use the big-endian read routines to preserve
12464 * the byte order as it exists in NVRAM.
12465 */
141518c9 12466 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12467 goto out_not_found;
12468
6d348f2c 12469 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12470 }
12471 } else {
94c982bd
MC		 12472 ssize_t cnt;
12473 unsigned int pos = 0, i = 0;
12474
12475 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12476 cnt = pci_read_vpd(tp->pdev, pos,
12477 TG3_NVM_VPD_LEN - pos,
12478 &vpd_data[pos]);
12479 if (cnt == -ETIMEDOUT || -EINTR)
12480 cnt = 0;
12481 else if (cnt < 0)
f49639e6 12482 goto out_not_found;
1b27777a 12483 }
94c982bd
MC		 12484 if (pos != TG3_NVM_VPD_LEN)
12485 goto out_not_found;
1da177e4
LT		 12486 }
12487
12488 /* Now parse and find the part number. */
141518c9 12489 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12490 unsigned char val = vpd_data[i];
af2c6a4a 12491 unsigned int block_end;
1da177e4
LT		 12492
12493 if (val == 0x82 || val == 0x91) {
12494 i = (i + 3 +
12495 (vpd_data[i + 1] +
12496 (vpd_data[i + 2] << 8)));
12497 continue;
12498 }
12499
12500 if (val != 0x90)
12501 goto out_not_found;
12502
12503 block_end = (i + 3 +
12504 (vpd_data[i + 1] +
12505 (vpd_data[i + 2] << 8)));
12506 i += 3;
af2c6a4a 12507
141518c9 12508 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12509 goto out_not_found;
12510
12511 while (i < (block_end - 2)) {
1da177e4
LT		 12512 if (vpd_data[i + 0] == 'P' &&
12513 vpd_data[i + 1] == 'N') {
12514 int partno_len = vpd_data[i + 2];
12515
af2c6a4a 12516 i += 3;
141518c9
MC		 12517 if (partno_len > TG3_BPN_SIZE ||
12518 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12519 goto out_not_found;
12520
12521 memcpy(tp->board_part_number,
af2c6a4a 12522 &vpd_data[i], partno_len);
1da177e4
LT		 12523
12524 /* Success. */
12525 return;
12526 }
af2c6a4a 12527 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12528 }
12529
12530 /* Part number not found. */
12531 goto out_not_found;
12532 }
12533
12534out_not_found:
b5d3772c
MC		 12535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12536 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12537 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12538 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12539 strcpy(tp->board_part_number, "BCM57780");
12540 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12541 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12542 strcpy(tp->board_part_number, "BCM57760");
12543 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12544 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12545 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12546 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12547 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12548 strcpy(tp->board_part_number, "BCM57788");
b703df6f
MC		 12549 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12550 strcpy(tp->board_part_number, "BCM57765");
b5d3772c
MC		 12551 else
12552 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12553}
12554
9c8a620e
MC		 12555static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12556{
12557 u32 val;
12558
e4f34110 12559 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12560 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12561 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12562 val != 0)
12563 return 0;
12564
12565 return 1;
12566}
12567
acd9c119
MC		 12568static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12569{
ff3a7cb2 12570 u32 val, offset, start, ver_offset;
acd9c119 12571 int i;
ff3a7cb2 12572 bool newver = false;
acd9c119
MC		 12573
12574 if (tg3_nvram_read(tp, 0xc, &offset) ||
12575 tg3_nvram_read(tp, 0x4, &start))
12576 return;
12577
12578 offset = tg3_nvram_logical_addr(tp, offset);
12579
ff3a7cb2 12580 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12581 return;
12582
ff3a7cb2
MC		 12583 if ((val & 0xfc000000) == 0x0c000000) {
12584 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12585 return;
12586
ff3a7cb2
MC		 12587 if (val == 0)
12588 newver = true;
12589 }
12590
12591 if (newver) {
12592 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12593 return;
12594
12595 offset = offset + ver_offset - start;
12596 for (i = 0; i < 16; i += 4) {
12597 __be32 v;
12598 if (tg3_nvram_read_be32(tp, offset + i, &v))
12599 return;
12600
12601 memcpy(tp->fw_ver + i, &v, sizeof(v));
12602 }
12603 } else {
12604 u32 major, minor;
12605
12606 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12607 return;
12608
12609 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12610 TG3_NVM_BCVER_MAJSFT;
12611 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12612 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12613 }
12614}
12615
a6f6cb1c
MC		 12616static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12617{
12618 u32 val, major, minor;
12619
12620 /* Use native endian representation */
12621 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12622 return;
12623
12624 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12625 TG3_NVM_HWSB_CFG1_MAJSFT;
12626 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12627 TG3_NVM_HWSB_CFG1_MINSFT;
12628
12629 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12630}
12631
dfe00d7d
MC		 12632static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12633{
12634 u32 offset, major, minor, build;
12635
12636 tp->fw_ver[0] = 's';
12637 tp->fw_ver[1] = 'b';
12638 tp->fw_ver[2] = '\0';
12639
12640 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12641 return;
12642
12643 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12644 case TG3_EEPROM_SB_REVISION_0:
12645 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12646 break;
12647 case TG3_EEPROM_SB_REVISION_2:
12648 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12649 break;
12650 case TG3_EEPROM_SB_REVISION_3:
12651 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12652 break;
12653 default:
12654 return;
12655 }
12656
e4f34110 12657 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12658 return;
12659
12660 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12661 TG3_EEPROM_SB_EDH_BLD_SHFT;
12662 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12663 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12664 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12665
12666 if (minor > 99 || build > 26)
12667 return;
12668
12669 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12670
12671 if (build > 0) {
12672 tp->fw_ver[8] = 'a' + build - 1;
12673 tp->fw_ver[9] = '\0';
12674 }
12675}
12676
acd9c119 12677static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12678{
12679 u32 val, offset, start;
acd9c119 12680 int i, vlen;
9c8a620e
MC		 12681
12682 for (offset = TG3_NVM_DIR_START;
12683 offset < TG3_NVM_DIR_END;
12684 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12685 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12686 return;
12687
9c8a620e
MC		 12688 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12689 break;
12690 }
12691
12692 if (offset == TG3_NVM_DIR_END)
12693 return;
12694
12695 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12696 start = 0x08000000;
e4f34110 12697 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12698 return;
12699
e4f34110 12700 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12701 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12702 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12703 return;
12704
12705 offset += val - start;
12706
acd9c119 12707 vlen = strlen(tp->fw_ver);
9c8a620e 12708
acd9c119
MC		 12709 tp->fw_ver[vlen++] = ',';
12710 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12711
12712 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12713 __be32 v;
12714 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12715 return;
12716
b9fc7dc5 12717 offset += sizeof(v);
c4e6575c 12718
acd9c119
MC		 12719 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12720 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12721 break;
c4e6575c 12722 }
9c8a620e 12723
acd9c119
MC		 12724 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12725 vlen += sizeof(v);
c4e6575c 12726 }
acd9c119
MC		 12727}
12728
7fd76445
MC		 12729static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12730{
12731 int vlen;
12732 u32 apedata;
12733
12734 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12735 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12736 return;
12737
12738 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12739 if (apedata != APE_SEG_SIG_MAGIC)
12740 return;
12741
12742 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12743 if (!(apedata & APE_FW_STATUS_READY))
12744 return;
12745
12746 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12747
12748 vlen = strlen(tp->fw_ver);
12749
12750 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12751 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12752 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12753 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12754 (apedata & APE_FW_VERSION_BLDMSK));
12755}
12756
acd9c119
MC		 12757static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12758{
12759 u32 val;
12760
df259d8c
MC		 12761 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12762 tp->fw_ver[0] = 's';
12763 tp->fw_ver[1] = 'b';
12764 tp->fw_ver[2] = '\0';
12765
12766 return;
12767 }
12768
acd9c119
MC		 12769 if (tg3_nvram_read(tp, 0, &val))
12770 return;
12771
12772 if (val == TG3_EEPROM_MAGIC)
12773 tg3_read_bc_ver(tp);
12774 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12775 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12776 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12777 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12778 else
12779 return;
12780
12781 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12782 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12783 return;
12784
12785 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12786
12787 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12788}
12789
7544b097
MC		 12790static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12791
1da177e4
LT		 12792static int __devinit tg3_get_invariants(struct tg3 *tp)
12793{
12794 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12795 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12796 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12797 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12798 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12799 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12800 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12801 { },
12802 };
12803 u32 misc_ctrl_reg;
1da177e4
LT		 12804 u32 pci_state_reg, grc_misc_cfg;
12805 u32 val;
12806 u16 pci_cmd;
5e7dfd0f 12807 int err;
1da177e4 12808
1da177e4
LT		 12809 /* Force memory write invalidate off. If we leave it on,
12810 * then on 5700_BX chips we have to enable a workaround.
12811 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12812 * to match the cacheline size. The Broadcom driver have this
12813 * workaround but turns MWI off all the times so never uses
12814 * it. This seems to suggest that the workaround is insufficient.
12815 */
12816 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12817 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12818 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12819
12820 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12821 * has the register indirect write enable bit set before
12822 * we try to access any of the MMIO registers. It is also
12823 * critical that the PCI-X hw workaround situation is decided
12824 * before that as well.
12825 */
12826 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12827 &misc_ctrl_reg);
12828
12829 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12830 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12832 u32 prod_id_asic_rev;
12833
5001e2f6
MC		 12834 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12835 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12836 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12837 pci_read_config_dword(tp->pdev,
12838 TG3PCI_GEN2_PRODID_ASICREV,
12839 &prod_id_asic_rev);
b703df6f
MC		 12840 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12841 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12842 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12843 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12844 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12845 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12846 pci_read_config_dword(tp->pdev,
12847 TG3PCI_GEN15_PRODID_ASICREV,
12848 &prod_id_asic_rev);
f6eb9b1f
MC		 12849 else
12850 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12851 &prod_id_asic_rev);
12852
321d32a0 12853 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12854 }
1da177e4 12855
ff645bec
MC		 12856 /* Wrong chip ID in 5752 A0. This code can be removed later
12857 * as A0 is not in production.
12858 */
12859 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12860 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12861
6892914f
MC		 12862 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12863 * we need to disable memory and use config. cycles
12864 * only to access all registers. The 5702/03 chips
12865 * can mistakenly decode the special cycles from the
12866 * ICH chipsets as memory write cycles, causing corruption
12867 * of register and memory space. Only certain ICH bridges
12868 * will drive special cycles with non-zero data during the
12869 * address phase which can fall within the 5703's address
12870 * range. This is not an ICH bug as the PCI spec allows
12871 * non-zero address during special cycles. However, only
12872 * these ICH bridges are known to drive non-zero addresses
12873 * during special cycles.
12874 *
12875 * Since special cycles do not cross PCI bridges, we only
12876 * enable this workaround if the 5703 is on the secondary
12877 * bus of these ICH bridges.
12878 */
12879 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12880 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12881 static struct tg3_dev_id {
12882 u32 vendor;
12883 u32 device;
12884 u32 rev;
12885 } ich_chipsets[] = {
12886 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12887 PCI_ANY_ID },
12888 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12889 PCI_ANY_ID },
12890 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12891 0xa },
12892 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12893 PCI_ANY_ID },
12894 { },
12895 };
12896 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12897 struct pci_dev *bridge = NULL;
12898
12899 while (pci_id->vendor != 0) {
12900 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12901 bridge);
12902 if (!bridge) {
12903 pci_id++;
12904 continue;
12905 }
12906 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12907 if (bridge->revision > pci_id->rev)
6892914f
MC		 12908 continue;
12909 }
12910 if (bridge->subordinate &&
12911 (bridge->subordinate->number ==
12912 tp->pdev->bus->number)) {
12913
12914 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12915 pci_dev_put(bridge);
12916 break;
12917 }
12918 }
12919 }
12920
41588ba1
MC		 12921 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12922 static struct tg3_dev_id {
12923 u32 vendor;
12924 u32 device;
12925 } bridge_chipsets[] = {
12926 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12927 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12928 { },
12929 };
12930 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12931 struct pci_dev *bridge = NULL;
12932
12933 while (pci_id->vendor != 0) {
12934 bridge = pci_get_device(pci_id->vendor,
12935 pci_id->device,
12936 bridge);
12937 if (!bridge) {
12938 pci_id++;
12939 continue;
12940 }
12941 if (bridge->subordinate &&
12942 (bridge->subordinate->number <=
12943 tp->pdev->bus->number) &&
12944 (bridge->subordinate->subordinate >=
12945 tp->pdev->bus->number)) {
12946 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12947 pci_dev_put(bridge);
12948 break;
12949 }
12950 }
12951 }
12952
4a29cc2e
MC		 12953 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12954 * DMA addresses > 40-bit. This bridge may have other additional
12955 * 57xx devices behind it in some 4-port NIC designs for example.
12956 * Any tg3 device found behind the bridge will also need the 40-bit
12957 * DMA workaround.
12958 */
a4e2b347
MC		 12959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12961 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12962 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12963 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12964 }
4a29cc2e
MC		 12965 else {
12966 struct pci_dev *bridge = NULL;
12967
12968 do {
12969 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12970 PCI_DEVICE_ID_SERVERWORKS_EPB,
12971 bridge);
12972 if (bridge && bridge->subordinate &&
12973 (bridge->subordinate->number <=
12974 tp->pdev->bus->number) &&
12975 (bridge->subordinate->subordinate >=
12976 tp->pdev->bus->number)) {
12977 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12978 pci_dev_put(bridge);
12979 break;
12980 }
12981 } while (bridge);
12982 }
4cf78e4f 12983
1da177e4
LT		 12984 /* Initialize misc host control in PCI block. */
12985 tp->misc_host_ctrl |= (misc_ctrl_reg &
12986 MISC_HOST_CTRL_CHIPREV);
12987 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12988 tp->misc_host_ctrl);
12989
f6eb9b1f
MC		 12990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12993 tp->pdev_peer = tg3_find_peer(tp);
12994
321d32a0
MC		 12995 /* Intentionally exclude ASIC_REV_5906 */
12996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13004 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13005
13006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13009 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13010 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13011 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13012
1b440c56
JL		 13013 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13014 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13015 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13016
027455ad
MC		 13017 /* 5700 B0 chips do not support checksumming correctly due
13018 * to hardware bugs.
13019 */
13020 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13021 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13022 else {
13023 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13024 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13025 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13026 tp->dev->features |= NETIF_F_IPV6_CSUM;
13027 }
13028
507399f1 13029 /* Determine TSO capabilities */
b703df6f
MC		 13030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13032 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13033 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13035 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13036 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13037 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13039 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13040 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13041 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13042 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13043 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13044 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13046 tp->fw_needed = FIRMWARE_TG3TSO5;
13047 else
13048 tp->fw_needed = FIRMWARE_TG3TSO;
13049 }
13050
13051 tp->irq_max = 1;
13052
5a6f3074 13053 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13054 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13055 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13056 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13057 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13058 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13059 tp->pdev_peer == tp->pdev))
13060 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13061
321d32a0 13062 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13064 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13065 }
4f125f42 13066
b703df6f
MC		 13067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13069 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13070 tp->irq_max = TG3_IRQ_MAX_VECS;
13071 }
f6eb9b1f 13072 }
0e1406dd 13073
615774fe
MC		 13074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13076 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13077 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13078 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13079 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13080 }
f6eb9b1f 13081
b703df6f
MC		 13082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13083 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13084 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13085
f51f3562 13086 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13087 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13088 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13089 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13090
52f4490c
MC		 13091 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13092 &pci_state_reg);
13093
5e7dfd0f
MC		 13094 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13095 if (tp->pcie_cap != 0) {
13096 u16 lnkctl;
13097
1da177e4 13098 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13099
13100 pcie_set_readrq(tp->pdev, 4096);
13101
5e7dfd0f
MC		 13102 pci_read_config_word(tp->pdev,
13103 tp->pcie_cap + PCI_EXP_LNKCTL,
13104 &lnkctl);
13105 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13107 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13110 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13111 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13112 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13113 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13114 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13115 }
52f4490c 13116 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13117 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13118 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13119 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13120 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13121 if (!tp->pcix_cap) {
13122 printk(KERN_ERR PFX "Cannot find PCI-X "
13123 "capability, aborting.\n");
13124 return -EIO;
13125 }
13126
13127 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13128 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13129 }
1da177e4 13130
399de50b
MC		 13131 /* If we have an AMD 762 or VIA K8T800 chipset, write
13132 * reordering to the mailbox registers done by the host
13133 * controller can cause major troubles. We read back from
13134 * every mailbox register write to force the writes to be
13135 * posted to the chip in order.
13136 */
13137 if (pci_dev_present(write_reorder_chipsets) &&
13138 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13139 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13140
69fc4053
MC		 13141 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13142 &tp->pci_cacheline_sz);
13143 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13144 &tp->pci_lat_timer);
1da177e4
LT		 13145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13146 tp->pci_lat_timer < 64) {
13147 tp->pci_lat_timer = 64;
69fc4053
MC		 13148 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13149 tp->pci_lat_timer);
1da177e4
LT		 13150 }
13151
52f4490c
MC		 13152 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13153 /* 5700 BX chips need to have their TX producer index
13154 * mailboxes written twice to workaround a bug.
13155 */
13156 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13157
52f4490c 13158 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13159 *
13160 * The workaround is to use indirect register accesses
13161 * for all chip writes not to mailbox registers.
13162 */
52f4490c 13163 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13164 u32 pm_reg;
1da177e4
LT		 13165
13166 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13167
13168 /* The chip can have it's power management PCI config
13169 * space registers clobbered due to this bug.
13170 * So explicitly force the chip into D0 here.
13171 */
9974a356
MC		 13172 pci_read_config_dword(tp->pdev,
13173 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13174 &pm_reg);
13175 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13176 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13177 pci_write_config_dword(tp->pdev,
13178 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13179 pm_reg);
13180
13181 /* Also, force SERR#/PERR# in PCI command. */
13182 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13183 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13184 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13185 }
13186 }
13187
1da177e4
LT		 13188 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13189 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13190 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13191 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13192
13193 /* Chip-specific fixup from Broadcom driver */
13194 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13195 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13196 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13197 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13198 }
13199
1ee582d8 13200 /* Default fast path register access methods */
20094930 13201 tp->read32 = tg3_read32;
1ee582d8 13202 tp->write32 = tg3_write32;
09ee929c 13203 tp->read32_mbox = tg3_read32;
20094930 13204 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13205 tp->write32_tx_mbox = tg3_write32;
13206 tp->write32_rx_mbox = tg3_write32;
13207
13208 /* Various workaround register access methods */
13209 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13210 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13211 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13212 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13213 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13214 /*
13215 * Back to back register writes can cause problems on these
13216 * chips, the workaround is to read back all reg writes
13217 * except those to mailbox regs.
13218 *
13219 * See tg3_write_indirect_reg32().
13220 */
1ee582d8 13221 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13222 }
13223
1ee582d8
MC		 13224 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13225 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13226 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13227 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13228 tp->write32_rx_mbox = tg3_write_flush_reg32;
13229 }
20094930 13230
6892914f
MC		 13231 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13232 tp->read32 = tg3_read_indirect_reg32;
13233 tp->write32 = tg3_write_indirect_reg32;
13234 tp->read32_mbox = tg3_read_indirect_mbox;
13235 tp->write32_mbox = tg3_write_indirect_mbox;
13236 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13237 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13238
13239 iounmap(tp->regs);
22abe310 13240 tp->regs = NULL;
6892914f
MC		 13241
13242 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13243 pci_cmd &= ~PCI_COMMAND_MEMORY;
13244 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13245 }
b5d3772c
MC		 13246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13247 tp->read32_mbox = tg3_read32_mbox_5906;
13248 tp->write32_mbox = tg3_write32_mbox_5906;
13249 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13250 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13251 }
6892914f 13252
bbadf503
MC		 13253 if (tp->write32 == tg3_write_indirect_reg32 ||
13254 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13255 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13257 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13258
7d0c41ef 13259 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13260 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13261 * determined before calling tg3_set_power_state() so that
13262 * we know whether or not to switch out of Vaux power.
13263 * When the flag is set, it means that GPIO1 is used for eeprom
13264 * write protect and also implies that it is a LOM where GPIOs
13265 * are not used to switch power.
6aa20a22 13266 */
7d0c41ef
MC		 13267 tg3_get_eeprom_hw_cfg(tp);
13268
0d3031d9
MC		 13269 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13270 /* Allow reads and writes to the
13271 * APE register and memory space.
13272 */
13273 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13274 PCISTATE_ALLOW_APE_SHMEM_WR;
13275 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13276 pci_state_reg);
13277 }
13278
9936bcf6 13279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13280 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13281 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13283 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13285 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13286
314fba34
MC		 13287 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13288 * GPIO1 driven high will bring 5700's external PHY out of reset.
13289 * It is also used as eeprom write protect on LOMs.
13290 */
13291 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13292 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13293 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13294 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13295 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13296 /* Unused GPIO3 must be driven as output on 5752 because there
13297 * are no pull-up resistors on unused GPIO pins.
13298 */
13299 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13300 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13301
321d32a0
MC		 13302 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13303 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 13304 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13305
8d519ab2
MC		 13306 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13307 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13308 /* Turn off the debug UART. */
13309 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13310 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13311 /* Keep VMain power. */
13312 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13313 GRC_LCLCTRL_GPIO_OUTPUT0;
13314 }
13315
1da177e4 13316 /* Force the chip into D0. */
bc1c7567 13317 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13318 if (err) {
13319 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13320 pci_name(tp->pdev));
13321 return err;
13322 }
13323
1da177e4
LT		 13324 /* Derive initial jumbo mode from MTU assigned in
13325 * ether_setup() via the alloc_etherdev() call
13326 */
0f893dc6 13327 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13328 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13329 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13330
13331 /* Determine WakeOnLan speed to use. */
13332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13333 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13334 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13335 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13336 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13337 } else {
13338 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13339 }
13340
7f97a4bd
MC		 13341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13342 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13343
1da177e4
LT		 13344 /* A few boards don't want Ethernet@WireSpeed phy feature */
13345 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13346 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13347 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13348 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13349 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13350 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13351 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13352
13353 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13354 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13355 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13356 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13357 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13358
321d32a0 13359 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13360 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13361 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13362 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13363 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13364 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13369 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13370 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13371 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13372 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13373 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13374 } else
c424cb24
MC		 13375 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13376 }
1da177e4 13377
b2a5c19c
MC		 13378 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13379 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13380 tp->phy_otp = tg3_read_otp_phycfg(tp);
13381 if (tp->phy_otp == 0)
13382 tp->phy_otp = TG3_OTP_DEFAULT;
13383 }
13384
f51f3562 13385 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13386 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13387 else
13388 tp->mi_mode = MAC_MI_MODE_BASE;
13389
1da177e4 13390 tp->coalesce_mode = 0;
1da177e4
LT		 13391 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13392 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13393 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13394
321d32a0
MC		 13395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13397 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13398
158d7abd
MC		 13399 err = tg3_mdio_init(tp);
13400 if (err)
13401 return err;
1da177e4
LT		 13402
13403 /* Initialize data/descriptor byte/word swapping. */
13404 val = tr32(GRC_MODE);
13405 val &= GRC_MODE_HOST_STACKUP;
13406 tw32(GRC_MODE, val | tp->grc_mode);
13407
13408 tg3_switch_clocks(tp);
13409
13410 /* Clear this out for sanity. */
13411 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13412
13413 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13414 &pci_state_reg);
13415 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13416 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13417 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13418
13419 if (chiprevid == CHIPREV_ID_5701_A0 ||
13420 chiprevid == CHIPREV_ID_5701_B0 ||
13421 chiprevid == CHIPREV_ID_5701_B2 ||
13422 chiprevid == CHIPREV_ID_5701_B5) {
13423 void __iomem *sram_base;
13424
13425 /* Write some dummy words into the SRAM status block
13426 * area, see if it reads back correctly. If the return
13427 * value is bad, force enable the PCIX workaround.
13428 */
13429 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13430
13431 writel(0x00000000, sram_base);
13432 writel(0x00000000, sram_base + 4);
13433 writel(0xffffffff, sram_base + 4);
13434 if (readl(sram_base) != 0x00000000)
13435 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13436 }
13437 }
13438
13439 udelay(50);
13440 tg3_nvram_init(tp);
13441
13442 grc_misc_cfg = tr32(GRC_MISC_CFG);
13443 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13444
1da177e4
LT		 13445 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13446 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13447 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13448 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13449
fac9b83e
DM		 13450 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13451 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13452 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13453 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13454 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13455 HOSTCC_MODE_CLRTICK_TXBD);
13456
13457 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13458 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13459 tp->misc_host_ctrl);
13460 }
13461
3bda1258
MC		 13462 /* Preserve the APE MAC_MODE bits */
13463 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13464 tp->mac_mode = tr32(MAC_MODE) |
13465 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13466 else
13467 tp->mac_mode = TG3_DEF_MAC_MODE;
13468
1da177e4
LT		 13469 /* these are limited to 10/100 only */
13470 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13471 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13472 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13473 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13474 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13475 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13476 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13477 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13478 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13479 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13480 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13481 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13482 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13483 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13484
13485 err = tg3_phy_probe(tp);
13486 if (err) {
13487 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13488 pci_name(tp->pdev), err);
13489 /* ... but do not return immediately ... */
b02fd9e3 13490 tg3_mdio_fini(tp);
1da177e4
LT		 13491 }
13492
13493 tg3_read_partno(tp);
c4e6575c 13494 tg3_read_fw_ver(tp);
1da177e4
LT		 13495
13496 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13497 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13498 } else {
13499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13500 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13501 else
13502 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13503 }
13504
13505 /* 5700 {AX,BX} chips have a broken status block link
13506 * change bit implementation, so we must use the
13507 * status register in those cases.
13508 */
13509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13510 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13511 else
13512 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13513
13514 /* The led_ctrl is set during tg3_phy_probe, here we might
13515 * have to force the link status polling mechanism based
13516 * upon subsystem IDs.
13517 */
13518 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13519 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13520 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13521 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13522 TG3_FLAG_USE_LINKCHG_REG);
13523 }
13524
13525 /* For all SERDES we poll the MAC status register. */
13526 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13527 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13528 else
13529 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13530
ad829268 13531 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13533 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13534 tp->rx_offset = 0;
13535
f92905de
MC		 13536 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13537
13538 /* Increment the rx prod index on the rx std ring by at most
13539 * 8 for these chips to workaround hw errata.
13540 */
13541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13542 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13543 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13544 tp->rx_std_max_post = 8;
13545
8ed5d97e
MC		 13546 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13547 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13548 PCIE_PWR_MGMT_L1_THRESH_MSK;
13549
1da177e4
LT		 13550 return err;
13551}
13552
49b6e95f 13553#ifdef CONFIG_SPARC
1da177e4
LT		 13554static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13555{
13556 struct net_device *dev = tp->dev;
13557 struct pci_dev *pdev = tp->pdev;
49b6e95f 13558 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13559 const unsigned char *addr;
49b6e95f
DM		 13560 int len;
13561
13562 addr = of_get_property(dp, "local-mac-address", &len);
13563 if (addr && len == 6) {
13564 memcpy(dev->dev_addr, addr, 6);
13565 memcpy(dev->perm_addr, dev->dev_addr, 6);
13566 return 0;
1da177e4
LT		 13567 }
13568 return -ENODEV;
13569}
13570
13571static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13572{
13573 struct net_device *dev = tp->dev;
13574
13575 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13576 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13577 return 0;
13578}
13579#endif
13580
13581static int __devinit tg3_get_device_address(struct tg3 *tp)
13582{
13583 struct net_device *dev = tp->dev;
13584 u32 hi, lo, mac_offset;
008652b3 13585 int addr_ok = 0;
1da177e4 13586
49b6e95f 13587#ifdef CONFIG_SPARC
1da177e4
LT		 13588 if (!tg3_get_macaddr_sparc(tp))
13589 return 0;
13590#endif
13591
13592 mac_offset = 0x7c;
f49639e6 13593 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13594 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13595 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13596 mac_offset = 0xcc;
13597 if (tg3_nvram_lock(tp))
13598 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13599 else
13600 tg3_nvram_unlock(tp);
a1b950d5
MC		 13601 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13602 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13603 mac_offset = 0xcc;
13604 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13605 mac_offset = 0x10;
1da177e4
LT		 13606
13607 /* First try to get it from MAC address mailbox. */
13608 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13609 if ((hi >> 16) == 0x484b) {
13610 dev->dev_addr[0] = (hi >> 8) & 0xff;
13611 dev->dev_addr[1] = (hi >> 0) & 0xff;
13612
13613 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13614 dev->dev_addr[2] = (lo >> 24) & 0xff;
13615 dev->dev_addr[3] = (lo >> 16) & 0xff;
13616 dev->dev_addr[4] = (lo >> 8) & 0xff;
13617 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13618
008652b3
MC		 13619 /* Some old bootcode may report a 0 MAC address in SRAM */
13620 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13621 }
13622 if (!addr_ok) {
13623 /* Next, try NVRAM. */
df259d8c
MC		 13624 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13625 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13626 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13627 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13628 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13629 }
13630 /* Finally just fetch it out of the MAC control regs. */
13631 else {
13632 hi = tr32(MAC_ADDR_0_HIGH);
13633 lo = tr32(MAC_ADDR_0_LOW);
13634
13635 dev->dev_addr[5] = lo & 0xff;
13636 dev->dev_addr[4] = (lo >> 8) & 0xff;
13637 dev->dev_addr[3] = (lo >> 16) & 0xff;
13638 dev->dev_addr[2] = (lo >> 24) & 0xff;
13639 dev->dev_addr[1] = hi & 0xff;
13640 dev->dev_addr[0] = (hi >> 8) & 0xff;
13641 }
1da177e4
LT		 13642 }
13643
13644 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13645#ifdef CONFIG_SPARC
1da177e4
LT		 13646 if (!tg3_get_default_macaddr_sparc(tp))
13647 return 0;
13648#endif
13649 return -EINVAL;
13650 }
2ff43697 13651 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13652 return 0;
13653}
13654
59e6b434
DM		 13655#define BOUNDARY_SINGLE_CACHELINE 1
13656#define BOUNDARY_MULTI_CACHELINE 2
13657
13658static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13659{
13660 int cacheline_size;
13661 u8 byte;
13662 int goal;
13663
13664 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13665 if (byte == 0)
13666 cacheline_size = 1024;
13667 else
13668 cacheline_size = (int) byte * 4;
13669
13670 /* On 5703 and later chips, the boundary bits have no
13671 * effect.
13672 */
13673 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13674 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13675 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13676 goto out;
13677
13678#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13679 goal = BOUNDARY_MULTI_CACHELINE;
13680#else
13681#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13682 goal = BOUNDARY_SINGLE_CACHELINE;
13683#else
13684 goal = 0;
13685#endif
13686#endif
13687
b703df6f
MC		 13688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13689 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13690 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13691 goto out;
13692 }
13693
59e6b434
DM		 13694 if (!goal)
13695 goto out;
13696
13697 /* PCI controllers on most RISC systems tend to disconnect
13698 * when a device tries to burst across a cache-line boundary.
13699 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13700 *
13701 * Unfortunately, for PCI-E there are only limited
13702 * write-side controls for this, and thus for reads
13703 * we will still get the disconnects. We'll also waste
13704 * these PCI cycles for both read and write for chips
13705 * other than 5700 and 5701 which do not implement the
13706 * boundary bits.
13707 */
13708 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13709 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13710 switch (cacheline_size) {
13711 case 16:
13712 case 32:
13713 case 64:
13714 case 128:
13715 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13716 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13717 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13718 } else {
13719 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13720 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13721 }
13722 break;
13723
13724 case 256:
13725 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13726 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13727 break;
13728
13729 default:
13730 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13731 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13732 break;
855e1111 13733 }
59e6b434
DM		 13734 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13735 switch (cacheline_size) {
13736 case 16:
13737 case 32:
13738 case 64:
13739 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13740 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13741 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13742 break;
13743 }
13744 /* fallthrough */
13745 case 128:
13746 default:
13747 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13748 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13749 break;
855e1111 13750 }
59e6b434
DM		 13751 } else {
13752 switch (cacheline_size) {
13753 case 16:
13754 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13755 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13756 DMA_RWCTRL_WRITE_BNDRY_16);
13757 break;
13758 }
13759 /* fallthrough */
13760 case 32:
13761 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13762 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13763 DMA_RWCTRL_WRITE_BNDRY_32);
13764 break;
13765 }
13766 /* fallthrough */
13767 case 64:
13768 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13769 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13770 DMA_RWCTRL_WRITE_BNDRY_64);
13771 break;
13772 }
13773 /* fallthrough */
13774 case 128:
13775 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13776 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13777 DMA_RWCTRL_WRITE_BNDRY_128);
13778 break;
13779 }
13780 /* fallthrough */
13781 case 256:
13782 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13783 DMA_RWCTRL_WRITE_BNDRY_256);
13784 break;
13785 case 512:
13786 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13787 DMA_RWCTRL_WRITE_BNDRY_512);
13788 break;
13789 case 1024:
13790 default:
13791 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13792 DMA_RWCTRL_WRITE_BNDRY_1024);
13793 break;
855e1111 13794 }
59e6b434
DM		 13795 }
13796
13797out:
13798 return val;
13799}
13800
1da177e4
LT		 13801static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13802{
13803 struct tg3_internal_buffer_desc test_desc;
13804 u32 sram_dma_descs;
13805 int i, ret;
13806
13807 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13808
13809 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13810 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13811 tw32(RDMAC_STATUS, 0);
13812 tw32(WDMAC_STATUS, 0);
13813
13814 tw32(BUFMGR_MODE, 0);
13815 tw32(FTQ_RESET, 0);
13816
13817 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13818 test_desc.addr_lo = buf_dma & 0xffffffff;
13819 test_desc.nic_mbuf = 0x00002100;
13820 test_desc.len = size;
13821
13822 /*
13823 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13824 * the *second* time the tg3 driver was getting loaded after an
13825 * initial scan.
13826 *
13827 * Broadcom tells me:
13828 * ...the DMA engine is connected to the GRC block and a DMA
13829 * reset may affect the GRC block in some unpredictable way...
13830 * The behavior of resets to individual blocks has not been tested.
13831 *
13832 * Broadcom noted the GRC reset will also reset all sub-components.
13833 */
13834 if (to_device) {
13835 test_desc.cqid_sqid = (13 << 8) | 2;
13836
13837 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13838 udelay(40);
13839 } else {
13840 test_desc.cqid_sqid = (16 << 8) | 7;
13841
13842 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13843 udelay(40);
13844 }
13845 test_desc.flags = 0x00000005;
13846
13847 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13848 u32 val;
13849
13850 val = *(((u32 *)&test_desc) + i);
13851 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13852 sram_dma_descs + (i * sizeof(u32)));
13853 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13854 }
13855 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13856
13857 if (to_device) {
13858 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13859 } else {
13860 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13861 }
13862
13863 ret = -ENODEV;
13864 for (i = 0; i < 40; i++) {
13865 u32 val;
13866
13867 if (to_device)
13868 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13869 else
13870 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13871 if ((val & 0xffff) == sram_dma_descs) {
13872 ret = 0;
13873 break;
13874 }
13875
13876 udelay(100);
13877 }
13878
13879 return ret;
13880}
13881
ded7340d 13882#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13883
13884static int __devinit tg3_test_dma(struct tg3 *tp)
13885{
13886 dma_addr_t buf_dma;
59e6b434 13887 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13888 int ret = 0;
1da177e4
LT		 13889
13890 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13891 if (!buf) {
13892 ret = -ENOMEM;
13893 goto out_nofree;
13894 }
13895
13896 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13897 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13898
59e6b434 13899 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13900
b703df6f
MC		 13901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13903 goto out;
13904
1da177e4
LT		 13905 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13906 /* DMA read watermark not used on PCIE */
13907 tp->dma_rwctrl |= 0x00180000;
13908 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13911 tp->dma_rwctrl |= 0x003f0000;
13912 else
13913 tp->dma_rwctrl |= 0x003f000f;
13914 } else {
13915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13917 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13918 u32 read_water = 0x7;
1da177e4 13919
4a29cc2e
MC		 13920 /* If the 5704 is behind the EPB bridge, we can
13921 * do the less restrictive ONE_DMA workaround for
13922 * better performance.
13923 */
13924 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13926 tp->dma_rwctrl |= 0x8000;
13927 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13928 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13929
49afdeb6
MC		 13930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13931 read_water = 4;
59e6b434 13932 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13933 tp->dma_rwctrl |=
13934 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13935 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13936 (1 << 23);
4cf78e4f
MC		 13937 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13938 /* 5780 always in PCIX mode */
13939 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13940 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13941 /* 5714 always in PCIX mode */
13942 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13943 } else {
13944 tp->dma_rwctrl |= 0x001b000f;
13945 }
13946 }
13947
13948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13950 tp->dma_rwctrl &= 0xfffffff0;
13951
13952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13954 /* Remove this if it causes problems for some boards. */
13955 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13956
13957 /* On 5700/5701 chips, we need to set this bit.
13958 * Otherwise the chip will issue cacheline transactions
13959 * to streamable DMA memory with not all the byte
13960 * enables turned on. This is an error on several
13961 * RISC PCI controllers, in particular sparc64.
13962 *
13963 * On 5703/5704 chips, this bit has been reassigned
13964 * a different meaning. In particular, it is used
13965 * on those chips to enable a PCI-X workaround.
13966 */
13967 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13968 }
13969
13970 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13971
13972#if 0
13973 /* Unneeded, already done by tg3_get_invariants. */
13974 tg3_switch_clocks(tp);
13975#endif
13976
1da177e4
LT		 13977 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13978 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13979 goto out;
13980
59e6b434
DM		 13981 /* It is best to perform DMA test with maximum write burst size
13982 * to expose the 5700/5701 write DMA bug.
13983 */
13984 saved_dma_rwctrl = tp->dma_rwctrl;
13985 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13986 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13987
1da177e4
LT		 13988 while (1) {
13989 u32 *p = buf, i;
13990
13991 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13992 p[i] = i;
13993
13994 /* Send the buffer to the chip. */
13995 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13996 if (ret) {
13997 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13998 break;
13999 }
14000
14001#if 0
14002 /* validate data reached card RAM correctly. */
14003 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14004 u32 val;
14005 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14006 if (le32_to_cpu(val) != p[i]) {
14007 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14008 /* ret = -ENODEV here? */
14009 }
14010 p[i] = 0;
14011 }
14012#endif
14013 /* Now read it back. */
14014 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14015 if (ret) {
14016 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14017
14018 break;
14019 }
14020
14021 /* Verify it. */
14022 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14023 if (p[i] == i)
14024 continue;
14025
59e6b434
DM		 14026 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14027 DMA_RWCTRL_WRITE_BNDRY_16) {
14028 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14029 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14030 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14031 break;
14032 } else {
14033 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14034 ret = -ENODEV;
14035 goto out;
14036 }
14037 }
14038
14039 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14040 /* Success. */
14041 ret = 0;
14042 break;
14043 }
14044 }
59e6b434
DM		 14045 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14046 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14047 static struct pci_device_id dma_wait_state_chipsets[] = {
14048 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14049 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14050 { },
14051 };
14052
59e6b434 14053 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14054 * now look for chipsets that are known to expose the
14055 * DMA bug without failing the test.
59e6b434 14056 */
6d1cfbab
MC		 14057 if (pci_dev_present(dma_wait_state_chipsets)) {
14058 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14059 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14060 }
14061 else
14062 /* Safe to use the calculated DMA boundary. */
14063 tp->dma_rwctrl = saved_dma_rwctrl;
14064
59e6b434
DM		 14065 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14066 }
1da177e4
LT		 14067
14068out:
14069 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14070out_nofree:
14071 return ret;
14072}
14073
14074static void __devinit tg3_init_link_config(struct tg3 *tp)
14075{
14076 tp->link_config.advertising =
14077 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14078 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14079 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14080 ADVERTISED_Autoneg | ADVERTISED_MII);
14081 tp->link_config.speed = SPEED_INVALID;
14082 tp->link_config.duplex = DUPLEX_INVALID;
14083 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14084 tp->link_config.active_speed = SPEED_INVALID;
14085 tp->link_config.active_duplex = DUPLEX_INVALID;
14086 tp->link_config.phy_is_low_power = 0;
14087 tp->link_config.orig_speed = SPEED_INVALID;
14088 tp->link_config.orig_duplex = DUPLEX_INVALID;
14089 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14090}
14091
14092static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14093{
f6eb9b1f 14094 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
b703df6f
MC		 14095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14096 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
fdfec172
MC		 14097 tp->bufmgr_config.mbuf_read_dma_low_water =
14098 DEFAULT_MB_RDMA_LOW_WATER_5705;
14099 tp->bufmgr_config.mbuf_mac_rx_low_water =
14100 DEFAULT_MB_MACRX_LOW_WATER_5705;
14101 tp->bufmgr_config.mbuf_high_water =
14102 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14104 tp->bufmgr_config.mbuf_mac_rx_low_water =
14105 DEFAULT_MB_MACRX_LOW_WATER_5906;
14106 tp->bufmgr_config.mbuf_high_water =
14107 DEFAULT_MB_HIGH_WATER_5906;
14108 }
fdfec172
MC		 14109
14110 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14111 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14112 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14113 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14114 tp->bufmgr_config.mbuf_high_water_jumbo =
14115 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14116 } else {
14117 tp->bufmgr_config.mbuf_read_dma_low_water =
14118 DEFAULT_MB_RDMA_LOW_WATER;
14119 tp->bufmgr_config.mbuf_mac_rx_low_water =
14120 DEFAULT_MB_MACRX_LOW_WATER;
14121 tp->bufmgr_config.mbuf_high_water =
14122 DEFAULT_MB_HIGH_WATER;
14123
14124 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14125 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14126 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14127 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14128 tp->bufmgr_config.mbuf_high_water_jumbo =
14129 DEFAULT_MB_HIGH_WATER_JUMBO;
14130 }
1da177e4
LT		 14131
14132 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14133 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14134}
14135
14136static char * __devinit tg3_phy_string(struct tg3 *tp)
14137{
14138 switch (tp->phy_id & PHY_ID_MASK) {
14139 case PHY_ID_BCM5400: return "5400";
14140 case PHY_ID_BCM5401: return "5401";
14141 case PHY_ID_BCM5411: return "5411";
14142 case PHY_ID_BCM5701: return "5701";
14143 case PHY_ID_BCM5703: return "5703";
14144 case PHY_ID_BCM5704: return "5704";
14145 case PHY_ID_BCM5705: return "5705";
14146 case PHY_ID_BCM5750: return "5750";
85e94ced 14147 case PHY_ID_BCM5752: return "5752";
a4e2b347 14148 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14149 case PHY_ID_BCM5780: return "5780";
af36e6b6 14150 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14151 case PHY_ID_BCM5787: return "5787";
d30cdd28 14152 case PHY_ID_BCM5784: return "5784";
126a3368 14153 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14154 case PHY_ID_BCM5906: return "5906";
9936bcf6 14155 case PHY_ID_BCM5761: return "5761";
c2060fe1 14156 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 14157 case PHY_ID_BCM8002: return "8002/serdes";
14158 case 0: return "serdes";
14159 default: return "unknown";
855e1111 14160 }
1da177e4
LT		 14161}
14162
f9804ddb
MC		 14163static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14164{
14165 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14166 strcpy(str, "PCI Express");
14167 return str;
14168 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14169 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14170
14171 strcpy(str, "PCIX:");
14172
14173 if ((clock_ctrl == 7) ||
14174 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14175 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14176 strcat(str, "133MHz");
14177 else if (clock_ctrl == 0)
14178 strcat(str, "33MHz");
14179 else if (clock_ctrl == 2)
14180 strcat(str, "50MHz");
14181 else if (clock_ctrl == 4)
14182 strcat(str, "66MHz");
14183 else if (clock_ctrl == 6)
14184 strcat(str, "100MHz");
f9804ddb
MC		 14185 } else {
14186 strcpy(str, "PCI:");
14187 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14188 strcat(str, "66MHz");
14189 else
14190 strcat(str, "33MHz");
14191 }
14192 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14193 strcat(str, ":32-bit");
14194 else
14195 strcat(str, ":64-bit");
14196 return str;
14197}
14198
8c2dc7e1 14199static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14200{
14201 struct pci_dev *peer;
14202 unsigned int func, devnr = tp->pdev->devfn & ~7;
14203
14204 for (func = 0; func < 8; func++) {
14205 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14206 if (peer && peer != tp->pdev)
14207 break;
14208 pci_dev_put(peer);
14209 }
16fe9d74
MC		 14210 /* 5704 can be configured in single-port mode, set peer to
14211 * tp->pdev in that case.
14212 */
14213 if (!peer) {
14214 peer = tp->pdev;
14215 return peer;
14216 }
1da177e4
LT		 14217
14218 /*
14219 * We don't need to keep the refcount elevated; there's no way
14220 * to remove one half of this device without removing the other
14221 */
14222 pci_dev_put(peer);
14223
14224 return peer;
14225}
14226
15f9850d
DM		 14227static void __devinit tg3_init_coal(struct tg3 *tp)
14228{
14229 struct ethtool_coalesce *ec = &tp->coal;
14230
14231 memset(ec, 0, sizeof(*ec));
14232 ec->cmd = ETHTOOL_GCOALESCE;
14233 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14234 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14235 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14236 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14237 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14238 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14239 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14240 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14241 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14242
14243 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14244 HOSTCC_MODE_CLRTICK_TXBD)) {
14245 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14246 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14247 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14248 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14249 }
d244c892
MC		 14250
14251 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14252 ec->rx_coalesce_usecs_irq = 0;
14253 ec->tx_coalesce_usecs_irq = 0;
14254 ec->stats_block_coalesce_usecs = 0;
14255 }
15f9850d
DM		 14256}
14257
7c7d64b8
SH		 14258static const struct net_device_ops tg3_netdev_ops = {
14259 .ndo_open = tg3_open,
14260 .ndo_stop = tg3_close,
00829823
SH		 14261 .ndo_start_xmit = tg3_start_xmit,
14262 .ndo_get_stats = tg3_get_stats,
14263 .ndo_validate_addr = eth_validate_addr,
14264 .ndo_set_multicast_list = tg3_set_rx_mode,
14265 .ndo_set_mac_address = tg3_set_mac_addr,
14266 .ndo_do_ioctl = tg3_ioctl,
14267 .ndo_tx_timeout = tg3_tx_timeout,
14268 .ndo_change_mtu = tg3_change_mtu,
14269#if TG3_VLAN_TAG_USED
14270 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14271#endif
14272#ifdef CONFIG_NET_POLL_CONTROLLER
14273 .ndo_poll_controller = tg3_poll_controller,
14274#endif
14275};
14276
14277static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14278 .ndo_open = tg3_open,
14279 .ndo_stop = tg3_close,
14280 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14281 .ndo_get_stats = tg3_get_stats,
14282 .ndo_validate_addr = eth_validate_addr,
14283 .ndo_set_multicast_list = tg3_set_rx_mode,
14284 .ndo_set_mac_address = tg3_set_mac_addr,
14285 .ndo_do_ioctl = tg3_ioctl,
14286 .ndo_tx_timeout = tg3_tx_timeout,
14287 .ndo_change_mtu = tg3_change_mtu,
14288#if TG3_VLAN_TAG_USED
14289 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14290#endif
14291#ifdef CONFIG_NET_POLL_CONTROLLER
14292 .ndo_poll_controller = tg3_poll_controller,
14293#endif
14294};
14295
1da177e4
LT		 14296static int __devinit tg3_init_one(struct pci_dev *pdev,
14297 const struct pci_device_id *ent)
14298{
14299 static int tg3_version_printed = 0;
1da177e4
LT		 14300 struct net_device *dev;
14301 struct tg3 *tp;
646c9edd
MC		 14302 int i, err, pm_cap;
14303 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14304 char str[40];
72f2afb8 14305 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14306
14307 if (tg3_version_printed++ == 0)
14308 printk(KERN_INFO "%s", version);
14309
14310 err = pci_enable_device(pdev);
14311 if (err) {
14312 printk(KERN_ERR PFX "Cannot enable PCI device, "
14313 "aborting.\n");
14314 return err;
14315 }
14316
1da177e4
LT		 14317 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14318 if (err) {
14319 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14320 "aborting.\n");
14321 goto err_out_disable_pdev;
14322 }
14323
14324 pci_set_master(pdev);
14325
14326 /* Find power-management capability. */
14327 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14328 if (pm_cap == 0) {
14329 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14330 "aborting.\n");
14331 err = -EIO;
14332 goto err_out_free_res;
14333 }
14334
fe5f5787 14335 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14336 if (!dev) {
14337 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14338 err = -ENOMEM;
14339 goto err_out_free_res;
14340 }
14341
1da177e4
LT		 14342 SET_NETDEV_DEV(dev, &pdev->dev);
14343
1da177e4
LT		 14344#if TG3_VLAN_TAG_USED
14345 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14346#endif
14347
14348 tp = netdev_priv(dev);
14349 tp->pdev = pdev;
14350 tp->dev = dev;
14351 tp->pm_cap = pm_cap;
1da177e4
LT		 14352 tp->rx_mode = TG3_DEF_RX_MODE;
14353 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14354
1da177e4
LT		 14355 if (tg3_debug > 0)
14356 tp->msg_enable = tg3_debug;
14357 else
14358 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14359
14360 /* The word/byte swap controls here control register access byte
14361 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14362 * setting below.
14363 */
14364 tp->misc_host_ctrl =
14365 MISC_HOST_CTRL_MASK_PCI_INT |
14366 MISC_HOST_CTRL_WORD_SWAP |
14367 MISC_HOST_CTRL_INDIR_ACCESS |
14368 MISC_HOST_CTRL_PCISTATE_RW;
14369
14370 /* The NONFRM (non-frame) byte/word swap controls take effect
14371 * on descriptor entries, anything which isn't packet data.
14372 *
14373 * The StrongARM chips on the board (one for tx, one for rx)
14374 * are running in big-endian mode.
14375 */
14376 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14377 GRC_MODE_WSWAP_NONFRM_DATA);
14378#ifdef __BIG_ENDIAN
14379 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14380#endif
14381 spin_lock_init(&tp->lock);
1da177e4 14382 spin_lock_init(&tp->indirect_lock);
c4028958 14383 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14384
d5fe488a 14385 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14386 if (!tp->regs) {
1da177e4
LT		 14387 printk(KERN_ERR PFX "Cannot map device registers, "
14388 "aborting.\n");
14389 err = -ENOMEM;
14390 goto err_out_free_dev;
14391 }
14392
14393 tg3_init_link_config(tp);
14394
1da177e4
LT		 14395 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14396 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14397
1da177e4 14398 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14399 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14400 dev->irq = pdev->irq;
1da177e4
LT		 14401
14402 err = tg3_get_invariants(tp);
14403 if (err) {
14404 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14405 "aborting.\n");
14406 goto err_out_iounmap;
14407 }
14408
615774fe
MC		 14409 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14410 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14411 dev->netdev_ops = &tg3_netdev_ops;
14412 else
14413 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14414
14415
4a29cc2e
MC		 14416 /* The EPB bridge inside 5714, 5715, and 5780 and any
14417 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14418 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14419 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14420 * do DMA address check in tg3_start_xmit().
14421 */
4a29cc2e 14422 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14423 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14424 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14425 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14426#ifdef CONFIG_HIGHMEM
6a35528a 14427 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14428#endif
4a29cc2e 14429 } else
6a35528a 14430 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14431
14432 /* Configure DMA attributes. */
284901a9 14433 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14434 err = pci_set_dma_mask(pdev, dma_mask);
14435 if (!err) {
14436 dev->features |= NETIF_F_HIGHDMA;
14437 err = pci_set_consistent_dma_mask(pdev,
14438 persist_dma_mask);
14439 if (err < 0) {
14440 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14441 "DMA for consistent allocations\n");
14442 goto err_out_iounmap;
14443 }
14444 }
14445 }
284901a9
YH		 14446 if (err || dma_mask == DMA_BIT_MASK(32)) {
14447 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14448 if (err) {
14449 printk(KERN_ERR PFX "No usable DMA configuration, "
14450 "aborting.\n");
14451 goto err_out_iounmap;
14452 }
14453 }
14454
fdfec172 14455 tg3_init_bufmgr_config(tp);
1da177e4 14456
507399f1
MC		 14457 /* Selectively allow TSO based on operating conditions */
14458 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14459 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14460 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14461 else {
14462 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14463 tp->fw_needed = NULL;
1da177e4 14464 }
507399f1
MC		 14465
14466 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14467 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14468
4e3a7aaa
MC		 14469 /* TSO is on by default on chips that support hardware TSO.
14470 * Firmware TSO on older chips gives lower performance, so it
14471 * is off by default, but can be enabled using ethtool.
14472 */
e849cdc3
MC		 14473 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14474 (dev->features & NETIF_F_IP_CSUM))
14475 dev->features |= NETIF_F_TSO;
14476
14477 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14478 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14479 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14480 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14481 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14483 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14484 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14487 dev->features |= NETIF_F_TSO_ECN;
b0026624 14488 }
1da177e4 14489
1da177e4
LT		 14490 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14491 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14492 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14493 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14494 tp->rx_pending = 63;
14495 }
14496
1da177e4
LT		 14497 err = tg3_get_device_address(tp);
14498 if (err) {
14499 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14500 "aborting.\n");
026a6c21 14501 goto err_out_iounmap;
1da177e4
LT		 14502 }
14503
c88864df 14504 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14505 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14506 if (!tp->aperegs) {
c88864df
MC		 14507 printk(KERN_ERR PFX "Cannot map APE registers, "
14508 "aborting.\n");
14509 err = -ENOMEM;
026a6c21 14510 goto err_out_iounmap;
c88864df
MC		 14511 }
14512
14513 tg3_ape_lock_init(tp);
7fd76445
MC		 14514
14515 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14516 tg3_read_dash_ver(tp);
c88864df
MC		 14517 }
14518
1da177e4
LT		 14519 /*
14520 * Reset chip in case UNDI or EFI driver did not shutdown
14521 * DMA self test will enable WDMAC and we'll see (spurious)
14522 * pending DMA on the PCI bus at that point.
14523 */
14524 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14525 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14526 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14527 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14528 }
14529
14530 err = tg3_test_dma(tp);
14531 if (err) {
14532 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14533 goto err_out_apeunmap;
1da177e4
LT		 14534 }
14535
1da177e4
LT		 14536 /* flow control autonegotiation is default behavior */
14537 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14538 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14539
78f90dcf
MC		 14540 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14541 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14542 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14543 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14544 struct tg3_napi *tnapi = &tp->napi[i];
14545
14546 tnapi->tp = tp;
14547 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14548
14549 tnapi->int_mbox = intmbx;
14550 if (i < 4)
14551 intmbx += 0x8;
14552 else
14553 intmbx += 0x4;
14554
14555 tnapi->consmbox = rcvmbx;
14556 tnapi->prodmbox = sndmbx;
14557
14558 if (i) {
14559 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14560 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14561 } else {
14562 tnapi->coal_now = HOSTCC_MODE_NOW;
14563 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14564 }
14565
14566 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14567 break;
14568
14569 /*
14570 * If we support MSIX, we'll be using RSS. If we're using
14571 * RSS, the first vector only handles link interrupts and the
14572 * remaining vectors handle rx and tx interrupts. Reuse the
14573 * mailbox values for the next iteration. The values we setup
14574 * above are still useful for the single vectored mode.
14575 */
14576 if (!i)
14577 continue;
14578
14579 rcvmbx += 0x8;
14580
14581 if (sndmbx & 0x4)
14582 sndmbx -= 0x4;
14583 else
14584 sndmbx += 0xc;
14585 }
14586
15f9850d
DM		 14587 tg3_init_coal(tp);
14588
c49a1561
MC		 14589 pci_set_drvdata(pdev, dev);
14590
1da177e4
LT		 14591 err = register_netdev(dev);
14592 if (err) {
14593 printk(KERN_ERR PFX "Cannot register net device, "
14594 "aborting.\n");
0d3031d9 14595 goto err_out_apeunmap;
1da177e4
LT		 14596 }
14597
df59c940 14598 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14599 dev->name,
14600 tp->board_part_number,
14601 tp->pci_chip_rev_id,
f9804ddb 14602 tg3_bus_string(tp, str),
e174961c 14603 dev->dev_addr);
1da177e4 14604
3f0e3ad7
MC		 14605 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14606 struct phy_device *phydev;
14607 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14608 printk(KERN_INFO
14609 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14610 tp->dev->name, phydev->drv->name,
14611 dev_name(&phydev->dev));
14612 } else
df59c940
MC		 14613 printk(KERN_INFO
14614 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14615 tp->dev->name, tg3_phy_string(tp),
14616 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14617 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14618 "10/100/1000Base-T")),
14619 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14620
14621 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14622 dev->name,
14623 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14624 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14625 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14626 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14627 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14628 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14629 dev->name, tp->dma_rwctrl,
284901a9 14630 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14631 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14632
14633 return 0;
14634
0d3031d9
MC		 14635err_out_apeunmap:
14636 if (tp->aperegs) {
14637 iounmap(tp->aperegs);
14638 tp->aperegs = NULL;
14639 }
14640
1da177e4 14641err_out_iounmap:
6892914f
MC		 14642 if (tp->regs) {
14643 iounmap(tp->regs);
22abe310 14644 tp->regs = NULL;
6892914f 14645 }
1da177e4
LT		 14646
14647err_out_free_dev:
14648 free_netdev(dev);
14649
14650err_out_free_res:
14651 pci_release_regions(pdev);
14652
14653err_out_disable_pdev:
14654 pci_disable_device(pdev);
14655 pci_set_drvdata(pdev, NULL);
14656 return err;
14657}
14658
14659static void __devexit tg3_remove_one(struct pci_dev *pdev)
14660{
14661 struct net_device *dev = pci_get_drvdata(pdev);
14662
14663 if (dev) {
14664 struct tg3 *tp = netdev_priv(dev);
14665
077f849d
JSR		 14666 if (tp->fw)
14667 release_firmware(tp->fw);
14668
7faa006f 14669 flush_scheduled_work();
158d7abd 14670
b02fd9e3
MC		 14671 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14672 tg3_phy_fini(tp);
158d7abd 14673 tg3_mdio_fini(tp);
b02fd9e3 14674 }
158d7abd 14675
1da177e4 14676 unregister_netdev(dev);
0d3031d9
MC		 14677 if (tp->aperegs) {
14678 iounmap(tp->aperegs);
14679 tp->aperegs = NULL;
14680 }
6892914f
MC		 14681 if (tp->regs) {
14682 iounmap(tp->regs);
22abe310 14683 tp->regs = NULL;
6892914f 14684 }
1da177e4
LT		 14685 free_netdev(dev);
14686 pci_release_regions(pdev);
14687 pci_disable_device(pdev);
14688 pci_set_drvdata(pdev, NULL);
14689 }
14690}
14691
14692static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14693{
14694 struct net_device *dev = pci_get_drvdata(pdev);
14695 struct tg3 *tp = netdev_priv(dev);
12dac075 14696 pci_power_t target_state;
1da177e4
LT		 14697 int err;
14698
3e0c95fd
MC		 14699 /* PCI register 4 needs to be saved whether netif_running() or not.
14700 * MSI address and data need to be saved if using MSI and
14701 * netif_running().
14702 */
14703 pci_save_state(pdev);
14704
1da177e4
LT		 14705 if (!netif_running(dev))
14706 return 0;
14707
7faa006f 14708 flush_scheduled_work();
b02fd9e3 14709 tg3_phy_stop(tp);
1da177e4
LT		 14710 tg3_netif_stop(tp);
14711
14712 del_timer_sync(&tp->timer);
14713
f47c11ee 14714 tg3_full_lock(tp, 1);
1da177e4 14715 tg3_disable_ints(tp);
f47c11ee 14716 tg3_full_unlock(tp);
1da177e4
LT		 14717
14718 netif_device_detach(dev);
14719
f47c11ee 14720 tg3_full_lock(tp, 0);
944d980e 14721 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14722 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14723 tg3_full_unlock(tp);
1da177e4 14724
12dac075
RW		 14725 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14726
14727 err = tg3_set_power_state(tp, target_state);
1da177e4 14728 if (err) {
b02fd9e3
MC		 14729 int err2;
14730
f47c11ee 14731 tg3_full_lock(tp, 0);
1da177e4 14732
6a9eba15 14733 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14734 err2 = tg3_restart_hw(tp, 1);
14735 if (err2)
b9ec6c1b 14736 goto out;
1da177e4
LT		 14737
14738 tp->timer.expires = jiffies + tp->timer_offset;
14739 add_timer(&tp->timer);
14740
14741 netif_device_attach(dev);
14742 tg3_netif_start(tp);
14743
b9ec6c1b 14744out:
f47c11ee 14745 tg3_full_unlock(tp);
b02fd9e3
MC		 14746
14747 if (!err2)
14748 tg3_phy_start(tp);
1da177e4
LT		 14749 }
14750
14751 return err;
14752}
14753
14754static int tg3_resume(struct pci_dev *pdev)
14755{
14756 struct net_device *dev = pci_get_drvdata(pdev);
14757 struct tg3 *tp = netdev_priv(dev);
14758 int err;
14759
3e0c95fd
MC		 14760 pci_restore_state(tp->pdev);
14761
1da177e4
LT		 14762 if (!netif_running(dev))
14763 return 0;
14764
bc1c7567 14765 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14766 if (err)
14767 return err;
14768
14769 netif_device_attach(dev);
14770
f47c11ee 14771 tg3_full_lock(tp, 0);
1da177e4 14772
6a9eba15 14773 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14774 err = tg3_restart_hw(tp, 1);
14775 if (err)
14776 goto out;
1da177e4
LT		 14777
14778 tp->timer.expires = jiffies + tp->timer_offset;
14779 add_timer(&tp->timer);
14780
1da177e4
LT		 14781 tg3_netif_start(tp);
14782
b9ec6c1b 14783out:
f47c11ee 14784 tg3_full_unlock(tp);
1da177e4 14785
b02fd9e3
MC		 14786 if (!err)
14787 tg3_phy_start(tp);
14788
b9ec6c1b 14789 return err;
1da177e4
LT		 14790}
14791
14792static struct pci_driver tg3_driver = {
14793 .name = DRV_MODULE_NAME,
14794 .id_table = tg3_pci_tbl,
14795 .probe = tg3_init_one,
14796 .remove = __devexit_p(tg3_remove_one),
14797 .suspend = tg3_suspend,
14798 .resume = tg3_resume
14799};
14800
14801static int __init tg3_init(void)
14802{
29917620 14803 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14804}
14805
14806static void __exit tg3_cleanup(void)
14807{
14808 pci_unregister_driver(&tg3_driver);
14809}
14810
14811module_init(tg3_init);
14812module_exit(tg3_cleanup);
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