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tg3: netdev_err() => dev_err()
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
ba5b0bfa 7 * Copyright (C) 2005-2010 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
be7ce530
MC		 70#define DRV_MODULE_VERSION "3.108"
71#define DRV_MODULE_RELDATE "February 17, 2010"
1da177e4
LT		 72
73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0
75#define TG3_DEF_TX_MODE 0
76#define TG3_DEF_MSG_ENABLE \
77 (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86/* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
88 */
89#define TG3_TX_TIMEOUT (5 * HZ)
90
91/* hardware minimum and maximum for a single frame's data payload */
92#define TG3_MIN_MTU 60
93#define TG3_MAX_MTU(tp) \
8f666b07 94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 95
96/* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
99 */
100#define TG3_RX_RING_SIZE 512
101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 104#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
79ed5ac7
MC		 121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
1da177e4 123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 124 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
1da177e4
LT		 127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
287be12e
MC		 129#define TG3_DMA_BYTE_ENAB 64
130
131#define TG3_RX_STD_DMA_SZ 1536
132#define TG3_RX_JMB_DMA_SZ 9046
133
134#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135
136#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 138
2b2cdb65
MC		 139#define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
141
142#define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144
1da177e4 145/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 146#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 147
ad829268
MC		 148#define TG3_RAW_IP_ALIGN 2
149
1da177e4
LT		 150/* number of ETHTOOL_GSTATS u64's */
151#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
152
4cafd3f5
MC		 153#define TG3_NUM_TEST 6
154
077f849d
JSR		 155#define FIRMWARE_TG3 "tigon/tg3.bin"
156#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
157#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
158
1da177e4 159static char version[] __devinitdata =
05dbe005 160 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 161
162MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
163MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
164MODULE_LICENSE("GPL");
165MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 166MODULE_FIRMWARE(FIRMWARE_TG3);
167MODULE_FIRMWARE(FIRMWARE_TG3TSO);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
169
679563f4 170#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 171
172static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
173module_param(tg3_debug, int, 0);
174MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
175
a3aa1884 176static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
b0f75221
MC		 246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
13185217
HK		 252 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
258 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
259 {}
1da177e4
LT		 260};
261
262MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
263
50da859d 264static const struct {
1da177e4
LT		 265 const char string[ETH_GSTRING_LEN];
266} ethtool_stats_keys[TG3_NUM_STATS] = {
267 { "rx_octets" },
268 { "rx_fragments" },
269 { "rx_ucast_packets" },
270 { "rx_mcast_packets" },
271 { "rx_bcast_packets" },
272 { "rx_fcs_errors" },
273 { "rx_align_errors" },
274 { "rx_xon_pause_rcvd" },
275 { "rx_xoff_pause_rcvd" },
276 { "rx_mac_ctrl_rcvd" },
277 { "rx_xoff_entered" },
278 { "rx_frame_too_long_errors" },
279 { "rx_jabbers" },
280 { "rx_undersize_packets" },
281 { "rx_in_length_errors" },
282 { "rx_out_length_errors" },
283 { "rx_64_or_less_octet_packets" },
284 { "rx_65_to_127_octet_packets" },
285 { "rx_128_to_255_octet_packets" },
286 { "rx_256_to_511_octet_packets" },
287 { "rx_512_to_1023_octet_packets" },
288 { "rx_1024_to_1522_octet_packets" },
289 { "rx_1523_to_2047_octet_packets" },
290 { "rx_2048_to_4095_octet_packets" },
291 { "rx_4096_to_8191_octet_packets" },
292 { "rx_8192_to_9022_octet_packets" },
293
294 { "tx_octets" },
295 { "tx_collisions" },
296
297 { "tx_xon_sent" },
298 { "tx_xoff_sent" },
299 { "tx_flow_control" },
300 { "tx_mac_errors" },
301 { "tx_single_collisions" },
302 { "tx_mult_collisions" },
303 { "tx_deferred" },
304 { "tx_excessive_collisions" },
305 { "tx_late_collisions" },
306 { "tx_collide_2times" },
307 { "tx_collide_3times" },
308 { "tx_collide_4times" },
309 { "tx_collide_5times" },
310 { "tx_collide_6times" },
311 { "tx_collide_7times" },
312 { "tx_collide_8times" },
313 { "tx_collide_9times" },
314 { "tx_collide_10times" },
315 { "tx_collide_11times" },
316 { "tx_collide_12times" },
317 { "tx_collide_13times" },
318 { "tx_collide_14times" },
319 { "tx_collide_15times" },
320 { "tx_ucast_packets" },
321 { "tx_mcast_packets" },
322 { "tx_bcast_packets" },
323 { "tx_carrier_sense_errors" },
324 { "tx_discards" },
325 { "tx_errors" },
326
327 { "dma_writeq_full" },
328 { "dma_write_prioq_full" },
329 { "rxbds_empty" },
330 { "rx_discards" },
331 { "rx_errors" },
332 { "rx_threshold_hit" },
333
334 { "dma_readq_full" },
335 { "dma_read_prioq_full" },
336 { "tx_comp_queue_full" },
337
338 { "ring_set_send_prod_index" },
339 { "ring_status_update" },
340 { "nic_irqs" },
341 { "nic_avoided_irqs" },
342 { "nic_tx_threshold_hit" }
343};
344
50da859d 345static const struct {
4cafd3f5
MC		 346 const char string[ETH_GSTRING_LEN];
347} ethtool_test_keys[TG3_NUM_TEST] = {
348 { "nvram test (online) " },
349 { "link test (online) " },
350 { "register test (offline)" },
351 { "memory test (offline)" },
352 { "loopback test (offline)" },
353 { "interrupt test (offline)" },
354};
355
b401e9e2
MC		 356static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
357{
358 writel(val, tp->regs + off);
359}
360
361static u32 tg3_read32(struct tg3 *tp, u32 off)
362{
6aa20a22 363 return (readl(tp->regs + off));
b401e9e2
MC		 364}
365
0d3031d9
MC		 366static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
367{
368 writel(val, tp->aperegs + off);
369}
370
371static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
372{
373 return (readl(tp->aperegs + off));
374}
375
1da177e4
LT		 376static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
377{
6892914f
MC		 378 unsigned long flags;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 384}
385
386static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
387{
388 writel(val, tp->regs + off);
389 readl(tp->regs + off);
1da177e4
LT		 390}
391
6892914f 392static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 393{
6892914f
MC		 394 unsigned long flags;
395 u32 val;
396
397 spin_lock_irqsave(&tp->indirect_lock, flags);
398 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
399 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
400 spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 return val;
402}
403
404static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
405{
406 unsigned long flags;
407
408 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
409 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
412 }
66711e66 413 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 414 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
415 TG3_64BIT_REG_LOW, val);
416 return;
1da177e4 417 }
6892914f
MC		 418
419 spin_lock_irqsave(&tp->indirect_lock, flags);
420 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
422 spin_unlock_irqrestore(&tp->indirect_lock, flags);
423
424 /* In indirect mode when disabling interrupts, we also need
425 * to clear the interrupt bit in the GRC local ctrl register.
426 */
427 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
428 (val == 0x1)) {
429 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
430 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
431 }
432}
433
434static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
435{
436 unsigned long flags;
437 u32 val;
438
439 spin_lock_irqsave(&tp->indirect_lock, flags);
440 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
441 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
442 spin_unlock_irqrestore(&tp->indirect_lock, flags);
443 return val;
444}
445
b401e9e2
MC		 446/* usec_wait specifies the wait time in usec when writing to certain registers
447 * where it is unsafe to read back the register without some delay.
448 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
449 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
450 */
451static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 452{
b401e9e2
MC		 453 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
454 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
455 /* Non-posted methods */
456 tp->write32(tp, off, val);
457 else {
458 /* Posted method */
459 tg3_write32(tp, off, val);
460 if (usec_wait)
461 udelay(usec_wait);
462 tp->read32(tp, off);
463 }
464 /* Wait again after the read for the posted method to guarantee that
465 * the wait time is met.
466 */
467 if (usec_wait)
468 udelay(usec_wait);
1da177e4
LT		 469}
470
09ee929c
MC		 471static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
472{
473 tp->write32_mbox(tp, off, val);
6892914f
MC		 474 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
475 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
476 tp->read32_mbox(tp, off);
09ee929c
MC		 477}
478
20094930 479static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 480{
481 void __iomem *mbox = tp->regs + off;
482 writel(val, mbox);
483 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
484 writel(val, mbox);
485 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
486 readl(mbox);
487}
488
b5d3772c
MC		 489static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
490{
491 return (readl(tp->regs + off + GRCMBOX_BASE));
492}
493
494static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
495{
496 writel(val, tp->regs + off + GRCMBOX_BASE);
497}
498
20094930 499#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 500#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 501#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
502#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 503#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 504
505#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 506#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
507#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 508#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 509
510static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
516 return;
517
6892914f 518 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 519 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
520 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 522
bbadf503
MC		 523 /* Always leave this as zero. */
524 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
525 } else {
526 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
527 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 528
bbadf503
MC		 529 /* Always leave this as zero. */
530 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
531 }
532 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 533}
534
1da177e4
LT		 535static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
536{
6892914f
MC		 537 unsigned long flags;
538
b5d3772c
MC		 539 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
541 *val = 0;
542 return;
543 }
544
6892914f 545 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 546 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
548 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 549
bbadf503
MC		 550 /* Always leave this as zero. */
551 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
552 } else {
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
554 *val = tr32(TG3PCI_MEM_WIN_DATA);
555
556 /* Always leave this as zero. */
557 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
558 }
6892914f 559 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 560}
561
0d3031d9
MC		 562static void tg3_ape_lock_init(struct tg3 *tp)
563{
564 int i;
565
566 /* Make sure the driver hasn't any stale locks. */
567 for (i = 0; i < 8; i++)
568 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
569 APE_LOCK_GRANT_DRIVER);
570}
571
572static int tg3_ape_lock(struct tg3 *tp, int locknum)
573{
574 int i, off;
575 int ret = 0;
576 u32 status;
577
578 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
579 return 0;
580
581 switch (locknum) {
77b483f1 582 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 583 case TG3_APE_LOCK_MEM:
584 break;
585 default:
586 return -EINVAL;
587 }
588
589 off = 4 * locknum;
590
591 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
592
593 /* Wait for up to 1 millisecond to acquire lock. */
594 for (i = 0; i < 100; i++) {
595 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
596 if (status == APE_LOCK_GRANT_DRIVER)
597 break;
598 udelay(10);
599 }
600
601 if (status != APE_LOCK_GRANT_DRIVER) {
602 /* Revoke the lock request. */
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
604 APE_LOCK_GRANT_DRIVER);
605
606 ret = -EBUSY;
607 }
608
609 return ret;
610}
611
612static void tg3_ape_unlock(struct tg3 *tp, int locknum)
613{
614 int off;
615
616 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
617 return;
618
619 switch (locknum) {
77b483f1 620 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 621 case TG3_APE_LOCK_MEM:
622 break;
623 default:
624 return;
625 }
626
627 off = 4 * locknum;
628 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
629}
630
1da177e4
LT		 631static void tg3_disable_ints(struct tg3 *tp)
632{
89aeb3bc
MC		 633 int i;
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637 for (i = 0; i < tp->irq_max; i++)
638 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 639}
640
1da177e4
LT		 641static void tg3_enable_ints(struct tg3 *tp)
642{
89aeb3bc 643 int i;
89aeb3bc 644
bbe832c0
MC		 645 tp->irq_sync = 0;
646 wmb();
647
1da177e4
LT		 648 tw32(TG3PCI_MISC_HOST_CTRL,
649 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 650
f89f38b8 651 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 652 for (i = 0; i < tp->irq_cnt; i++) {
653 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 654 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 655 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
656 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 657
f89f38b8 658 tp->coal_now |= tnapi->coal_now;
89aeb3bc 659 }
f19af9c2
MC		 660
661 /* Force an initial interrupt */
662 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
663 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
664 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
665 else
f89f38b8
MC		 666 tw32(HOSTCC_MODE, tp->coal_now);
667
668 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 669}
670
17375d25 671static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 672{
17375d25 673 struct tg3 *tp = tnapi->tp;
898a56f8 674 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 675 unsigned int work_exists = 0;
676
677 /* check for phy events */
678 if (!(tp->tg3_flags &
679 (TG3_FLAG_USE_LINKCHG_REG |
680 TG3_FLAG_POLL_SERDES))) {
681 if (sblk->status & SD_STATUS_LINK_CHG)
682 work_exists = 1;
683 }
684 /* check for RX/TX work to do */
f3f3f27e 685 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 686 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 687 work_exists = 1;
688
689 return work_exists;
690}
691
17375d25 692/* tg3_int_reenable
04237ddd
MC		 693 * similar to tg3_enable_ints, but it accurately determines whether there
694 * is new work pending and can return without flushing the PIO write
6aa20a22 695 * which reenables interrupts
1da177e4 696 */
17375d25 697static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 698{
17375d25
MC		 699 struct tg3 *tp = tnapi->tp;
700
898a56f8 701 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 702 mmiowb();
703
fac9b83e
DM		 704 /* When doing tagged status, this work check is unnecessary.
705 * The last_tag we write above tells the chip which piece of
706 * work we've completed.
707 */
708 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 709 tg3_has_work(tnapi))
04237ddd 710 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 711 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 712}
713
fed97810
MC		 714static void tg3_napi_disable(struct tg3 *tp)
715{
716 int i;
717
718 for (i = tp->irq_cnt - 1; i >= 0; i--)
719 napi_disable(&tp->napi[i].napi);
720}
721
722static void tg3_napi_enable(struct tg3 *tp)
723{
724 int i;
725
726 for (i = 0; i < tp->irq_cnt; i++)
727 napi_enable(&tp->napi[i].napi);
728}
729
1da177e4
LT		 730static inline void tg3_netif_stop(struct tg3 *tp)
731{
bbe832c0 732 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 733 tg3_napi_disable(tp);
1da177e4
LT		 734 netif_tx_disable(tp->dev);
735}
736
737static inline void tg3_netif_start(struct tg3 *tp)
738{
fe5f5787
MC		 739 /* NOTE: unconditional netif_tx_wake_all_queues is only
740 * appropriate so long as all callers are assured to
741 * have free tx slots (such as after tg3_init_hw)
1da177e4 742 */
fe5f5787
MC		 743 netif_tx_wake_all_queues(tp->dev);
744
fed97810
MC		 745 tg3_napi_enable(tp);
746 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 747 tg3_enable_ints(tp);
1da177e4
LT		 748}
749
750static void tg3_switch_clocks(struct tg3 *tp)
751{
f6eb9b1f 752 u32 clock_ctrl;
1da177e4
LT		 753 u32 orig_clock_ctrl;
754
795d01c5
MC		 755 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
756 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 757 return;
758
f6eb9b1f
MC		 759 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
760
1da177e4
LT		 761 orig_clock_ctrl = clock_ctrl;
762 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
763 CLOCK_CTRL_CLKRUN_OENABLE |
764 0x1f);
765 tp->pci_clock_ctrl = clock_ctrl;
766
767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
768 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 769 tw32_wait_f(TG3PCI_CLOCK_CTRL,
770 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 771 }
772 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 773 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774 clock_ctrl |
775 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
776 40);
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 clock_ctrl | (CLOCK_CTRL_ALTCLK),
779 40);
1da177e4 780 }
b401e9e2 781 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 782}
783
784#define PHY_BUSY_LOOPS 5000
785
786static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
787{
788 u32 frame_val;
789 unsigned int loops;
790 int ret;
791
792 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793 tw32_f(MAC_MI_MODE,
794 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795 udelay(80);
796 }
797
798 *val = 0x0;
799
882e9793 800 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 801 MI_COM_PHY_ADDR_MASK);
802 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
803 MI_COM_REG_ADDR_MASK);
804 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 805
1da177e4
LT		 806 tw32_f(MAC_MI_COM, frame_val);
807
808 loops = PHY_BUSY_LOOPS;
809 while (loops != 0) {
810 udelay(10);
811 frame_val = tr32(MAC_MI_COM);
812
813 if ((frame_val & MI_COM_BUSY) == 0) {
814 udelay(5);
815 frame_val = tr32(MAC_MI_COM);
816 break;
817 }
818 loops -= 1;
819 }
820
821 ret = -EBUSY;
822 if (loops != 0) {
823 *val = frame_val & MI_COM_DATA_MASK;
824 ret = 0;
825 }
826
827 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
828 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 udelay(80);
830 }
831
832 return ret;
833}
834
835static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
836{
837 u32 frame_val;
838 unsigned int loops;
839 int ret;
840
7f97a4bd 841 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 842 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843 return 0;
844
1da177e4
LT		 845 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
846 tw32_f(MAC_MI_MODE,
847 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848 udelay(80);
849 }
850
882e9793 851 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 852 MI_COM_PHY_ADDR_MASK);
853 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
854 MI_COM_REG_ADDR_MASK);
855 frame_val |= (val & MI_COM_DATA_MASK);
856 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 857
1da177e4
LT		 858 tw32_f(MAC_MI_COM, frame_val);
859
860 loops = PHY_BUSY_LOOPS;
861 while (loops != 0) {
862 udelay(10);
863 frame_val = tr32(MAC_MI_COM);
864 if ((frame_val & MI_COM_BUSY) == 0) {
865 udelay(5);
866 frame_val = tr32(MAC_MI_COM);
867 break;
868 }
869 loops -= 1;
870 }
871
872 ret = -EBUSY;
873 if (loops != 0)
874 ret = 0;
875
876 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 udelay(80);
879 }
880
881 return ret;
882}
883
95e2869a
MC		 884static int tg3_bmcr_reset(struct tg3 *tp)
885{
886 u32 phy_control;
887 int limit, err;
888
889 /* OK, reset it, and poll the BMCR_RESET bit until it
890 * clears or we time out.
891 */
892 phy_control = BMCR_RESET;
893 err = tg3_writephy(tp, MII_BMCR, phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 limit = 5000;
898 while (limit--) {
899 err = tg3_readphy(tp, MII_BMCR, &phy_control);
900 if (err != 0)
901 return -EBUSY;
902
903 if ((phy_control & BMCR_RESET) == 0) {
904 udelay(40);
905 break;
906 }
907 udelay(10);
908 }
d4675b52 909 if (limit < 0)
95e2869a
MC		 910 return -EBUSY;
911
912 return 0;
913}
914
158d7abd
MC		 915static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
158d7abd
MC		 918 u32 val;
919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 923 val = -EIO;
924
925 spin_unlock_bh(&tp->lock);
158d7abd
MC		 926
927 return val;
928}
929
930static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
931{
3d16543d 932 struct tg3 *tp = bp->priv;
24bb4fb6 933 u32 ret = 0;
158d7abd 934
24bb4fb6 935 spin_lock_bh(&tp->lock);
158d7abd
MC		 936
937 if (tg3_writephy(tp, reg, val))
24bb4fb6 938 ret = -EIO;
158d7abd 939
24bb4fb6
MC		 940 spin_unlock_bh(&tp->lock);
941
942 return ret;
158d7abd
MC		 943}
944
945static int tg3_mdio_reset(struct mii_bus *bp)
946{
947 return 0;
948}
949
9c61d6bc 950static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 951{
952 u32 val;
fcb389df 953 struct phy_device *phydev;
a9daf367 954
3f0e3ad7 955 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 956 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 957 case PHY_ID_BCM50610:
958 case PHY_ID_BCM50610M:
fcb389df
MC		 959 val = MAC_PHYCFG2_50610_LED_MODES;
960 break;
6a443a0f 961 case PHY_ID_BCMAC131:
fcb389df
MC		 962 val = MAC_PHYCFG2_AC131_LED_MODES;
963 break;
6a443a0f 964 case PHY_ID_RTL8211C:
fcb389df
MC		 965 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
966 break;
6a443a0f 967 case PHY_ID_RTL8201E:
fcb389df
MC		 968 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
969 break;
970 default:
a9daf367 971 return;
fcb389df
MC		 972 }
973
974 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
975 tw32(MAC_PHYCFG2, val);
976
977 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 978 val &= ~(MAC_PHYCFG1_RGMII_INT |
979 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
980 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 981 tw32(MAC_PHYCFG1, val);
982
983 return;
984 }
985
14417063 986 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
fcb389df
MC		 987 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
988 MAC_PHYCFG2_FMODE_MASK_MASK |
989 MAC_PHYCFG2_GMODE_MASK_MASK |
990 MAC_PHYCFG2_ACT_MASK_MASK |
991 MAC_PHYCFG2_QUAL_MASK_MASK |
992 MAC_PHYCFG2_INBAND_ENABLE;
993
994 tw32(MAC_PHYCFG2, val);
a9daf367 995
bb85fbb6
MC		 996 val = tr32(MAC_PHYCFG1);
997 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
998 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
14417063 999 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1000 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004 }
bb85fbb6
MC		 1005 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007 tw32(MAC_PHYCFG1, val);
a9daf367 1008
a9daf367
MC		 1009 val = tr32(MAC_EXT_RGMII_MODE);
1010 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011 MAC_RGMII_MODE_RX_QUALITY |
1012 MAC_RGMII_MODE_RX_ACTIVITY |
1013 MAC_RGMII_MODE_RX_ENG_DET |
1014 MAC_RGMII_MODE_TX_ENABLE |
1015 MAC_RGMII_MODE_TX_LOWPWR |
1016 MAC_RGMII_MODE_TX_RESET);
14417063 1017 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1018 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019 val |= MAC_RGMII_MODE_RX_INT_B |
1020 MAC_RGMII_MODE_RX_QUALITY |
1021 MAC_RGMII_MODE_RX_ACTIVITY |
1022 MAC_RGMII_MODE_RX_ENG_DET;
1023 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024 val |= MAC_RGMII_MODE_TX_ENABLE |
1025 MAC_RGMII_MODE_TX_LOWPWR |
1026 MAC_RGMII_MODE_TX_RESET;
1027 }
1028 tw32(MAC_EXT_RGMII_MODE, val);
1029}
1030
158d7abd
MC		 1031static void tg3_mdio_start(struct tg3 *tp)
1032{
158d7abd
MC		 1033 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034 tw32_f(MAC_MI_MODE, tp->mi_mode);
1035 udelay(80);
a9daf367 1036
9ea4818d
MC		 1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
1040}
1041
1042static int tg3_mdio_init(struct tg3 *tp)
1043{
1044 int i;
1045 u32 reg;
1046 struct phy_device *phydev;
1047
882e9793
MC		 1048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1049 u32 funcnum, is_serdes;
1050
1051 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1052 if (funcnum)
1053 tp->phy_addr = 2;
1054 else
1055 tp->phy_addr = 1;
1056
d1ec96af
MC		 1057 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1058 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1059 else
1060 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1061 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1062 if (is_serdes)
1063 tp->phy_addr += 7;
1064 } else
3f0e3ad7 1065 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1066
158d7abd
MC		 1067 tg3_mdio_start(tp);
1068
1069 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1070 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1071 return 0;
1072
298cf9be
LB		 1073 tp->mdio_bus = mdiobus_alloc();
1074 if (tp->mdio_bus == NULL)
1075 return -ENOMEM;
158d7abd 1076
298cf9be
LB		 1077 tp->mdio_bus->name = "tg3 mdio bus";
1078 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1079 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1080 tp->mdio_bus->priv = tp;
1081 tp->mdio_bus->parent = &tp->pdev->dev;
1082 tp->mdio_bus->read = &tg3_mdio_read;
1083 tp->mdio_bus->write = &tg3_mdio_write;
1084 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1085 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1086 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1087
1088 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1089 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1090
1091 /* The bus registration will look for all the PHYs on the mdio bus.
1092 * Unfortunately, it does not ensure the PHY is powered up before
1093 * accessing the PHY ID registers. A chip reset is the
1094 * quickest way to bring the device back to an operational state..
1095 */
1096 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1097 tg3_bmcr_reset(tp);
1098
298cf9be 1099 i = mdiobus_register(tp->mdio_bus);
a9daf367 1100 if (i) {
ab96b241 1101 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1102 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1103 return i;
1104 }
158d7abd 1105
3f0e3ad7 1106 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1107
9c61d6bc 1108 if (!phydev || !phydev->drv) {
ab96b241 1109 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1110 mdiobus_unregister(tp->mdio_bus);
1111 mdiobus_free(tp->mdio_bus);
1112 return -ENODEV;
1113 }
1114
1115 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1116 case PHY_ID_BCM57780:
321d32a0 1117 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1118 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1119 break;
6a443a0f
MC		 1120 case PHY_ID_BCM50610:
1121 case PHY_ID_BCM50610M:
32e5a8d6 1122 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1123 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1124 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1125 PHY_BRCM_AUTO_PWRDWN_ENABLE;
14417063 1126 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
a9daf367
MC		 1127 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1128 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1129 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1131 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1132 /* fallthru */
6a443a0f 1133 case PHY_ID_RTL8211C:
fcb389df 1134 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1135 break;
6a443a0f
MC		 1136 case PHY_ID_RTL8201E:
1137 case PHY_ID_BCMAC131:
a9daf367 1138 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1139 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1140 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1141 break;
1142 }
1143
9c61d6bc
MC		 1144 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1145
1146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1147 tg3_mdio_config_5785(tp);
a9daf367
MC		 1148
1149 return 0;
158d7abd
MC		 1150}
1151
1152static void tg3_mdio_fini(struct tg3 *tp)
1153{
1154 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1155 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1156 mdiobus_unregister(tp->mdio_bus);
1157 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1158 }
1159}
1160
4ba526ce
MC		 1161/* tp->lock is held. */
1162static inline void tg3_generate_fw_event(struct tg3 *tp)
1163{
1164 u32 val;
1165
1166 val = tr32(GRC_RX_CPU_EVENT);
1167 val |= GRC_RX_CPU_DRIVER_EVENT;
1168 tw32_f(GRC_RX_CPU_EVENT, val);
1169
1170 tp->last_event_jiffies = jiffies;
1171}
1172
1173#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1174
95e2869a
MC		 1175/* tp->lock is held. */
1176static void tg3_wait_for_event_ack(struct tg3 *tp)
1177{
1178 int i;
4ba526ce
MC		 1179 unsigned int delay_cnt;
1180 long time_remain;
1181
1182 /* If enough time has passed, no wait is necessary. */
1183 time_remain = (long)(tp->last_event_jiffies + 1 +
1184 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1185 (long)jiffies;
1186 if (time_remain < 0)
1187 return;
1188
1189 /* Check if we can shorten the wait time. */
1190 delay_cnt = jiffies_to_usecs(time_remain);
1191 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1192 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1193 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1194
4ba526ce 1195 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1196 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1197 break;
4ba526ce 1198 udelay(8);
95e2869a
MC		 1199 }
1200}
1201
1202/* tp->lock is held. */
1203static void tg3_ump_link_report(struct tg3 *tp)
1204{
1205 u32 reg;
1206 u32 val;
1207
1208 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1209 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1210 return;
1211
1212 tg3_wait_for_event_ack(tp);
1213
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1215
1216 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1217
1218 val = 0;
1219 if (!tg3_readphy(tp, MII_BMCR, &reg))
1220 val = reg << 16;
1221 if (!tg3_readphy(tp, MII_BMSR, &reg))
1222 val |= (reg & 0xffff);
1223 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1224
1225 val = 0;
1226 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1227 val = reg << 16;
1228 if (!tg3_readphy(tp, MII_LPA, &reg))
1229 val |= (reg & 0xffff);
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1231
1232 val = 0;
1233 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1234 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1235 val = reg << 16;
1236 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1237 val |= (reg & 0xffff);
1238 }
1239 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1240
1241 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1242 val = reg << 16;
1243 else
1244 val = 0;
1245 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1246
4ba526ce 1247 tg3_generate_fw_event(tp);
95e2869a
MC		 1248}
1249
1250static void tg3_link_report(struct tg3 *tp)
1251{
1252 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1253 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1254 tg3_ump_link_report(tp);
1255 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1256 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1257 (tp->link_config.active_speed == SPEED_1000 ?
1258 1000 :
1259 (tp->link_config.active_speed == SPEED_100 ?
1260 100 : 10)),
1261 (tp->link_config.active_duplex == DUPLEX_FULL ?
1262 "full" : "half"));
1263
1264 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1265 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1266 "on" : "off",
1267 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1268 "on" : "off");
95e2869a
MC		 1269 tg3_ump_link_report(tp);
1270 }
1271}
1272
1273static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1274{
1275 u16 miireg;
1276
e18ce346 1277 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1278 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1279 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1280 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1281 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1282 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1283 else
1284 miireg = 0;
1285
1286 return miireg;
1287}
1288
1289static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1290{
1291 u16 miireg;
1292
e18ce346 1293 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1294 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1295 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1296 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1297 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1298 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1299 else
1300 miireg = 0;
1301
1302 return miireg;
1303}
1304
95e2869a
MC		 1305static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1306{
1307 u8 cap = 0;
1308
1309 if (lcladv & ADVERTISE_1000XPAUSE) {
1310 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1311 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1312 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1313 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1314 cap = FLOW_CTRL_RX;
95e2869a
MC		 1315 } else {
1316 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1317 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1318 }
1319 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1320 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1321 cap = FLOW_CTRL_TX;
95e2869a
MC		 1322 }
1323
1324 return cap;
1325}
1326
f51f3562 1327static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1328{
b02fd9e3 1329 u8 autoneg;
f51f3562 1330 u8 flowctrl = 0;
95e2869a
MC		 1331 u32 old_rx_mode = tp->rx_mode;
1332 u32 old_tx_mode = tp->tx_mode;
1333
b02fd9e3 1334 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1335 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1336 else
1337 autoneg = tp->link_config.autoneg;
1338
1339 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1340 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1341 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1342 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1343 else
bc02ff95 1344 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1345 } else
1346 flowctrl = tp->link_config.flowctrl;
95e2869a 1347
f51f3562 1348 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1349
e18ce346 1350 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1351 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1352 else
1353 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1354
f51f3562 1355 if (old_rx_mode != tp->rx_mode)
95e2869a 1356 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1357
e18ce346 1358 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1359 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1360 else
1361 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1362
f51f3562 1363 if (old_tx_mode != tp->tx_mode)
95e2869a 1364 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1365}
1366
b02fd9e3
MC		 1367static void tg3_adjust_link(struct net_device *dev)
1368{
1369 u8 oldflowctrl, linkmesg = 0;
1370 u32 mac_mode, lcl_adv, rmt_adv;
1371 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1372 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1373
24bb4fb6 1374 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1375
1376 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1377 MAC_MODE_HALF_DUPLEX);
1378
1379 oldflowctrl = tp->link_config.active_flowctrl;
1380
1381 if (phydev->link) {
1382 lcl_adv = 0;
1383 rmt_adv = 0;
1384
1385 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1386 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1387 else if (phydev->speed == SPEED_1000 ||
1388 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1389 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1390 else
1391 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1392
1393 if (phydev->duplex == DUPLEX_HALF)
1394 mac_mode |= MAC_MODE_HALF_DUPLEX;
1395 else {
1396 lcl_adv = tg3_advert_flowctrl_1000T(
1397 tp->link_config.flowctrl);
1398
1399 if (phydev->pause)
1400 rmt_adv = LPA_PAUSE_CAP;
1401 if (phydev->asym_pause)
1402 rmt_adv |= LPA_PAUSE_ASYM;
1403 }
1404
1405 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1406 } else
1407 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1408
1409 if (mac_mode != tp->mac_mode) {
1410 tp->mac_mode = mac_mode;
1411 tw32_f(MAC_MODE, tp->mac_mode);
1412 udelay(40);
1413 }
1414
fcb389df
MC		 1415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1416 if (phydev->speed == SPEED_10)
1417 tw32(MAC_MI_STAT,
1418 MAC_MI_STAT_10MBPS_MODE |
1419 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420 else
1421 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422 }
1423
b02fd9e3
MC		 1424 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1425 tw32(MAC_TX_LENGTHS,
1426 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1427 (6 << TX_LENGTHS_IPG_SHIFT) |
1428 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1429 else
1430 tw32(MAC_TX_LENGTHS,
1431 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1432 (6 << TX_LENGTHS_IPG_SHIFT) |
1433 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1434
1435 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1436 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1437 phydev->speed != tp->link_config.active_speed ||
1438 phydev->duplex != tp->link_config.active_duplex ||
1439 oldflowctrl != tp->link_config.active_flowctrl)
1440 linkmesg = 1;
1441
1442 tp->link_config.active_speed = phydev->speed;
1443 tp->link_config.active_duplex = phydev->duplex;
1444
24bb4fb6 1445 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1446
1447 if (linkmesg)
1448 tg3_link_report(tp);
1449}
1450
1451static int tg3_phy_init(struct tg3 *tp)
1452{
1453 struct phy_device *phydev;
1454
1455 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1456 return 0;
1457
1458 /* Bring the PHY back to a known state. */
1459 tg3_bmcr_reset(tp);
1460
3f0e3ad7 1461 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1462
1463 /* Attach the MAC to the PHY. */
fb28ad35 1464 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1465 phydev->dev_flags, phydev->interface);
b02fd9e3 1466 if (IS_ERR(phydev)) {
ab96b241 1467 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 1468 return PTR_ERR(phydev);
1469 }
1470
b02fd9e3 1471 /* Mask with MAC supported features. */
9c61d6bc
MC		 1472 switch (phydev->interface) {
1473 case PHY_INTERFACE_MODE_GMII:
1474 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1475 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1476 phydev->supported &= (PHY_GBIT_FEATURES |
1477 SUPPORTED_Pause |
1478 SUPPORTED_Asym_Pause);
1479 break;
1480 }
1481 /* fallthru */
9c61d6bc
MC		 1482 case PHY_INTERFACE_MODE_MII:
1483 phydev->supported &= (PHY_BASIC_FEATURES |
1484 SUPPORTED_Pause |
1485 SUPPORTED_Asym_Pause);
1486 break;
1487 default:
3f0e3ad7 1488 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1489 return -EINVAL;
1490 }
1491
1492 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1493
1494 phydev->advertising = phydev->supported;
1495
b02fd9e3
MC		 1496 return 0;
1497}
1498
1499static void tg3_phy_start(struct tg3 *tp)
1500{
1501 struct phy_device *phydev;
1502
1503 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1504 return;
1505
3f0e3ad7 1506 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1507
1508 if (tp->link_config.phy_is_low_power) {
1509 tp->link_config.phy_is_low_power = 0;
1510 phydev->speed = tp->link_config.orig_speed;
1511 phydev->duplex = tp->link_config.orig_duplex;
1512 phydev->autoneg = tp->link_config.orig_autoneg;
1513 phydev->advertising = tp->link_config.orig_advertising;
1514 }
1515
1516 phy_start(phydev);
1517
1518 phy_start_aneg(phydev);
1519}
1520
1521static void tg3_phy_stop(struct tg3 *tp)
1522{
1523 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1524 return;
1525
3f0e3ad7 1526 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1527}
1528
1529static void tg3_phy_fini(struct tg3 *tp)
1530{
1531 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1532 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1533 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1534 }
1535}
1536
b2a5c19c
MC		 1537static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1538{
1539 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1540 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1541}
1542
7f97a4bd
MC		 1543static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1544{
1545 u32 phytest;
1546
1547 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1548 u32 phy;
1549
1550 tg3_writephy(tp, MII_TG3_FET_TEST,
1551 phytest | MII_TG3_FET_SHADOW_EN);
1552 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1553 if (enable)
1554 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1555 else
1556 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1557 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1558 }
1559 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1560 }
1561}
1562
6833c043
MC		 1563static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1564{
1565 u32 reg;
1566
ecf1410b
MC		 1567 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1568 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1569 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1570 return;
1571
7f97a4bd
MC		 1572 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1573 tg3_phy_fet_toggle_apd(tp, enable);
1574 return;
1575 }
1576
6833c043
MC		 1577 reg = MII_TG3_MISC_SHDW_WREN |
1578 MII_TG3_MISC_SHDW_SCR5_SEL |
1579 MII_TG3_MISC_SHDW_SCR5_LPED |
1580 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1581 MII_TG3_MISC_SHDW_SCR5_SDTL |
1582 MII_TG3_MISC_SHDW_SCR5_C125OE;
1583 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1584 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1585
1586 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1587
1588
1589 reg = MII_TG3_MISC_SHDW_WREN |
1590 MII_TG3_MISC_SHDW_APD_SEL |
1591 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1592 if (enable)
1593 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1594
1595 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1596}
1597
9ef8ca99
MC		 1598static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1599{
1600 u32 phy;
1601
1602 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1603 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1604 return;
1605
7f97a4bd 1606 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1607 u32 ephy;
1608
535ef6e1
MC		 1609 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1610 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1611
1612 tg3_writephy(tp, MII_TG3_FET_TEST,
1613 ephy | MII_TG3_FET_SHADOW_EN);
1614 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1615 if (enable)
535ef6e1 1616 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1617 else
535ef6e1
MC		 1618 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1619 tg3_writephy(tp, reg, phy);
9ef8ca99 1620 }
535ef6e1 1621 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1622 }
1623 } else {
1624 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1625 MII_TG3_AUXCTL_SHDWSEL_MISC;
1626 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1627 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1628 if (enable)
1629 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1630 else
1631 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1632 phy |= MII_TG3_AUXCTL_MISC_WREN;
1633 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1634 }
1635 }
1636}
1637
1da177e4
LT		 1638static void tg3_phy_set_wirespeed(struct tg3 *tp)
1639{
1640 u32 val;
1641
1642 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1643 return;
1644
1645 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1646 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1647 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1648 (val | (1 << 15) | (1 << 4)));
1649}
1650
b2a5c19c
MC		 1651static void tg3_phy_apply_otp(struct tg3 *tp)
1652{
1653 u32 otp, phy;
1654
1655 if (!tp->phy_otp)
1656 return;
1657
1658 otp = tp->phy_otp;
1659
1660 /* Enable SM_DSP clock and tx 6dB coding. */
1661 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1662 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1663 MII_TG3_AUXCTL_ACTL_TX_6DB;
1664 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1665
1666 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1667 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1668 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1669
1670 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1671 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1672 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1673
1674 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1675 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1676 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1677
1678 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1680
1681 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1683
1684 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1685 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1687
1688 /* Turn off SM_DSP clock. */
1689 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1690 MII_TG3_AUXCTL_ACTL_TX_6DB;
1691 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1692}
1693
1da177e4
LT		 1694static int tg3_wait_macro_done(struct tg3 *tp)
1695{
1696 int limit = 100;
1697
1698 while (limit--) {
1699 u32 tmp32;
1700
1701 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1702 if ((tmp32 & 0x1000) == 0)
1703 break;
1704 }
1705 }
d4675b52 1706 if (limit < 0)
1da177e4
LT		 1707 return -EBUSY;
1708
1709 return 0;
1710}
1711
1712static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1713{
1714 static const u32 test_pat[4][6] = {
1715 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1716 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1717 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1718 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1719 };
1720 int chan;
1721
1722 for (chan = 0; chan < 4; chan++) {
1723 int i;
1724
1725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1726 (chan * 0x2000) | 0x0200);
1727 tg3_writephy(tp, 0x16, 0x0002);
1728
1729 for (i = 0; i < 6; i++)
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1731 test_pat[chan][i]);
1732
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp)) {
1735 *resetp = 1;
1736 return -EBUSY;
1737 }
1738
1739 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1740 (chan * 0x2000) | 0x0200);
1741 tg3_writephy(tp, 0x16, 0x0082);
1742 if (tg3_wait_macro_done(tp)) {
1743 *resetp = 1;
1744 return -EBUSY;
1745 }
1746
1747 tg3_writephy(tp, 0x16, 0x0802);
1748 if (tg3_wait_macro_done(tp)) {
1749 *resetp = 1;
1750 return -EBUSY;
1751 }
1752
1753 for (i = 0; i < 6; i += 2) {
1754 u32 low, high;
1755
1756 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1757 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1758 tg3_wait_macro_done(tp)) {
1759 *resetp = 1;
1760 return -EBUSY;
1761 }
1762 low &= 0x7fff;
1763 high &= 0x000f;
1764 if (low != test_pat[chan][i] ||
1765 high != test_pat[chan][i+1]) {
1766 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1767 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1768 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1769
1770 return -EBUSY;
1771 }
1772 }
1773 }
1774
1775 return 0;
1776}
1777
1778static int tg3_phy_reset_chanpat(struct tg3 *tp)
1779{
1780 int chan;
1781
1782 for (chan = 0; chan < 4; chan++) {
1783 int i;
1784
1785 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1786 (chan * 0x2000) | 0x0200);
1787 tg3_writephy(tp, 0x16, 0x0002);
1788 for (i = 0; i < 6; i++)
1789 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1790 tg3_writephy(tp, 0x16, 0x0202);
1791 if (tg3_wait_macro_done(tp))
1792 return -EBUSY;
1793 }
1794
1795 return 0;
1796}
1797
1798static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1799{
1800 u32 reg32, phy9_orig;
1801 int retries, do_phy_reset, err;
1802
1803 retries = 10;
1804 do_phy_reset = 1;
1805 do {
1806 if (do_phy_reset) {
1807 err = tg3_bmcr_reset(tp);
1808 if (err)
1809 return err;
1810 do_phy_reset = 0;
1811 }
1812
1813 /* Disable transmitter and interrupt. */
1814 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1815 continue;
1816
1817 reg32 |= 0x3000;
1818 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1819
1820 /* Set full-duplex, 1000 mbps. */
1821 tg3_writephy(tp, MII_BMCR,
1822 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1823
1824 /* Set to master mode. */
1825 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1826 continue;
1827
1828 tg3_writephy(tp, MII_TG3_CTRL,
1829 (MII_TG3_CTRL_AS_MASTER |
1830 MII_TG3_CTRL_ENABLE_AS_MASTER));
1831
1832 /* Enable SM_DSP_CLOCK and 6dB. */
1833 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1834
1835 /* Block the PHY control access. */
1836 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1837 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1838
1839 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1840 if (!err)
1841 break;
1842 } while (--retries);
1843
1844 err = tg3_phy_reset_chanpat(tp);
1845 if (err)
1846 return err;
1847
1848 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1849 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1850
1851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1852 tg3_writephy(tp, 0x16, 0x0000);
1853
1854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1856 /* Set Extended packet length bit for jumbo frames */
1857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1858 }
1859 else {
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1861 }
1862
1863 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1864
1865 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1866 reg32 &= ~0x3000;
1867 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1868 } else if (!err)
1869 err = -EBUSY;
1870
1871 return err;
1872}
1873
1874/* This will reset the tigon3 PHY if there is no valid
1875 * link unless the FORCE argument is non-zero.
1876 */
1877static int tg3_phy_reset(struct tg3 *tp)
1878{
b2a5c19c 1879 u32 cpmuctrl;
1da177e4
LT		 1880 u32 phy_status;
1881 int err;
1882
60189ddf
MC		 1883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1884 u32 val;
1885
1886 val = tr32(GRC_MISC_CFG);
1887 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1888 udelay(40);
1889 }
1da177e4
LT		 1890 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1891 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1892 if (err != 0)
1893 return -EBUSY;
1894
c8e1e82b
MC		 1895 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1896 netif_carrier_off(tp->dev);
1897 tg3_link_report(tp);
1898 }
1899
1da177e4
LT		 1900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1901 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1903 err = tg3_phy_reset_5703_4_5(tp);
1904 if (err)
1905 return err;
1906 goto out;
1907 }
1908
b2a5c19c
MC		 1909 cpmuctrl = 0;
1910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1911 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1912 cpmuctrl = tr32(TG3_CPMU_CTRL);
1913 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1914 tw32(TG3_CPMU_CTRL,
1915 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1916 }
1917
1da177e4
LT		 1918 err = tg3_bmcr_reset(tp);
1919 if (err)
1920 return err;
1921
b2a5c19c
MC		 1922 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1923 u32 phy;
1924
1925 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1926 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1927
1928 tw32(TG3_CPMU_CTRL, cpmuctrl);
1929 }
1930
bcb37f6c
MC		 1931 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1932 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1933 u32 val;
1934
1935 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1936 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1937 CPMU_LSPD_1000MB_MACCLK_12_5) {
1938 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1939 udelay(40);
1940 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1941 }
1942 }
1943
ecf1410b
MC		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1945 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1946 return 0;
1947
b2a5c19c
MC		 1948 tg3_phy_apply_otp(tp);
1949
6833c043
MC		 1950 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1951 tg3_phy_toggle_apd(tp, true);
1952 else
1953 tg3_phy_toggle_apd(tp, false);
1954
1da177e4
LT		 1955out:
1956 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1958 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1959 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1962 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1963 }
1964 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1965 tg3_writephy(tp, 0x1c, 0x8d68);
1966 tg3_writephy(tp, 0x1c, 0x8d68);
1967 }
1968 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1972 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1973 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1975 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1977 }
c424cb24
MC		 1978 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1981 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1983 tg3_writephy(tp, MII_TG3_TEST1,
1984 MII_TG3_TEST1_TRIM_EN | 0x4);
1985 } else
1986 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1987 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1988 }
1da177e4
LT		 1989 /* Set Extended packet length bit (bit 14) on all chips that */
1990 /* support jumbo frames */
79eb6904 1991 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 1992 /* Cannot do read-modify-write on 5401 */
1993 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1994 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1995 u32 phy_reg;
1996
1997 /* Set bit 14 with read-modify-write to preserve other bits */
1998 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1999 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2001 }
2002
2003 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2004 * jumbo frames transmission.
2005 */
8f666b07 2006 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2007 u32 phy_reg;
2008
2009 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2010 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2011 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2012 }
2013
715116a1 2014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2015 /* adjust output voltage */
535ef6e1 2016 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2017 }
2018
9ef8ca99 2019 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2020 tg3_phy_set_wirespeed(tp);
2021 return 0;
2022}
2023
2024static void tg3_frob_aux_power(struct tg3 *tp)
2025{
2026 struct tg3 *tp_peer = tp;
2027
334355aa
MC		 2028 /* The GPIOs do something completely different on 57765. */
2029 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2031 return;
2032
f6eb9b1f
MC		 2033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2036 struct net_device *dev_peer;
2037
2038 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2039 /* remove_one() may have been run on the peer. */
8c2dc7e1 2040 if (!dev_peer)
bc1c7567
MC		 2041 tp_peer = tp;
2042 else
2043 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2044 }
2045
1da177e4 2046 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2047 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2048 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2049 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2052 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2053 (GRC_LCLCTRL_GPIO_OE0 |
2054 GRC_LCLCTRL_GPIO_OE1 |
2055 GRC_LCLCTRL_GPIO_OE2 |
2056 GRC_LCLCTRL_GPIO_OUTPUT0 |
2057 GRC_LCLCTRL_GPIO_OUTPUT1),
2058 100);
8d519ab2
MC		 2059 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2060 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2061 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2062 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2063 GRC_LCLCTRL_GPIO_OE1 |
2064 GRC_LCLCTRL_GPIO_OE2 |
2065 GRC_LCLCTRL_GPIO_OUTPUT0 |
2066 GRC_LCLCTRL_GPIO_OUTPUT1 |
2067 tp->grc_local_ctrl;
2068 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2069
2070 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2071 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2072
2073 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2074 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2075 } else {
2076 u32 no_gpio2;
dc56b7d4 2077 u32 grc_local_ctrl = 0;
1da177e4
LT		 2078
2079 if (tp_peer != tp &&
2080 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2081 return;
2082
dc56b7d4
MC		 2083 /* Workaround to prevent overdrawing Amps. */
2084 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2085 ASIC_REV_5714) {
2086 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088 grc_local_ctrl, 100);
dc56b7d4
MC		 2089 }
2090
1da177e4
LT		 2091 /* On 5753 and variants, GPIO2 cannot be used. */
2092 no_gpio2 = tp->nic_sram_data_cfg &
2093 NIC_SRAM_DATA_CFG_NO_GPIO2;
2094
dc56b7d4 2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2096 GRC_LCLCTRL_GPIO_OE1 |
2097 GRC_LCLCTRL_GPIO_OE2 |
2098 GRC_LCLCTRL_GPIO_OUTPUT1 |
2099 GRC_LCLCTRL_GPIO_OUTPUT2;
2100 if (no_gpio2) {
2101 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2102 GRC_LCLCTRL_GPIO_OUTPUT2);
2103 }
b401e9e2
MC		 2104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105 grc_local_ctrl, 100);
1da177e4
LT		 2106
2107 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2108
b401e9e2
MC		 2109 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2110 grc_local_ctrl, 100);
1da177e4
LT		 2111
2112 if (!no_gpio2) {
2113 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2114 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115 grc_local_ctrl, 100);
1da177e4
LT		 2116 }
2117 }
2118 } else {
2119 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2120 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2121 if (tp_peer != tp &&
2122 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2123 return;
2124
b401e9e2
MC		 2125 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126 (GRC_LCLCTRL_GPIO_OE1 |
2127 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2128
b401e9e2
MC		 2129 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2130 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2131
b401e9e2
MC		 2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 (GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2135 }
2136 }
2137}
2138
e8f3f6ca
MC		 2139static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2140{
2141 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2142 return 1;
79eb6904 2143 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 2144 if (speed != SPEED_10)
2145 return 1;
2146 } else if (speed == SPEED_10)
2147 return 1;
2148
2149 return 0;
2150}
2151
1da177e4
LT		 2152static int tg3_setup_phy(struct tg3 *, int);
2153
2154#define RESET_KIND_SHUTDOWN 0
2155#define RESET_KIND_INIT 1
2156#define RESET_KIND_SUSPEND 2
2157
2158static void tg3_write_sig_post_reset(struct tg3 *, int);
2159static int tg3_halt_cpu(struct tg3 *, u32);
2160
0a459aac 2161static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2162{
ce057f01
MC		 2163 u32 val;
2164
5129724a
MC		 2165 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2167 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2168 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2169
2170 sg_dig_ctrl |=
2171 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2172 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2173 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2174 }
3f7045c1 2175 return;
5129724a 2176 }
3f7045c1 2177
60189ddf 2178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2179 tg3_bmcr_reset(tp);
2180 val = tr32(GRC_MISC_CFG);
2181 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2182 udelay(40);
2183 return;
0e5f784c
MC		 2184 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2185 u32 phytest;
2186 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2187 u32 phy;
2188
2189 tg3_writephy(tp, MII_ADVERTISE, 0);
2190 tg3_writephy(tp, MII_BMCR,
2191 BMCR_ANENABLE | BMCR_ANRESTART);
2192
2193 tg3_writephy(tp, MII_TG3_FET_TEST,
2194 phytest | MII_TG3_FET_SHADOW_EN);
2195 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2196 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2197 tg3_writephy(tp,
2198 MII_TG3_FET_SHDW_AUXMODE4,
2199 phy);
2200 }
2201 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2202 }
2203 return;
0a459aac 2204 } else if (do_low_power) {
715116a1
MC		 2205 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2206 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2207
2208 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2209 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2210 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2211 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2212 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2213 }
3f7045c1 2214
15c3b696
MC		 2215 /* The PHY should not be powered down on some chips because
2216 * of bugs.
2217 */
2218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2219 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2220 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2221 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2222 return;
ce057f01 2223
bcb37f6c
MC		 2224 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2225 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2226 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2227 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2228 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2229 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2230 }
2231
15c3b696
MC		 2232 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2233}
2234
ffbcfed4
MC		 2235/* tp->lock is held. */
2236static int tg3_nvram_lock(struct tg3 *tp)
2237{
2238 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2239 int i;
2240
2241 if (tp->nvram_lock_cnt == 0) {
2242 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2243 for (i = 0; i < 8000; i++) {
2244 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2245 break;
2246 udelay(20);
2247 }
2248 if (i == 8000) {
2249 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2250 return -ENODEV;
2251 }
2252 }
2253 tp->nvram_lock_cnt++;
2254 }
2255 return 0;
2256}
2257
2258/* tp->lock is held. */
2259static void tg3_nvram_unlock(struct tg3 *tp)
2260{
2261 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2262 if (tp->nvram_lock_cnt > 0)
2263 tp->nvram_lock_cnt--;
2264 if (tp->nvram_lock_cnt == 0)
2265 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2266 }
2267}
2268
2269/* tp->lock is held. */
2270static void tg3_enable_nvram_access(struct tg3 *tp)
2271{
2272 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2273 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2274 u32 nvaccess = tr32(NVRAM_ACCESS);
2275
2276 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2277 }
2278}
2279
2280/* tp->lock is held. */
2281static void tg3_disable_nvram_access(struct tg3 *tp)
2282{
2283 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2284 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2285 u32 nvaccess = tr32(NVRAM_ACCESS);
2286
2287 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2288 }
2289}
2290
2291static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2292 u32 offset, u32 *val)
2293{
2294 u32 tmp;
2295 int i;
2296
2297 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2298 return -EINVAL;
2299
2300 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2301 EEPROM_ADDR_DEVID_MASK |
2302 EEPROM_ADDR_READ);
2303 tw32(GRC_EEPROM_ADDR,
2304 tmp |
2305 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2306 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2307 EEPROM_ADDR_ADDR_MASK) |
2308 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2309
2310 for (i = 0; i < 1000; i++) {
2311 tmp = tr32(GRC_EEPROM_ADDR);
2312
2313 if (tmp & EEPROM_ADDR_COMPLETE)
2314 break;
2315 msleep(1);
2316 }
2317 if (!(tmp & EEPROM_ADDR_COMPLETE))
2318 return -EBUSY;
2319
62cedd11
MC		 2320 tmp = tr32(GRC_EEPROM_DATA);
2321
2322 /*
2323 * The data will always be opposite the native endian
2324 * format. Perform a blind byteswap to compensate.
2325 */
2326 *val = swab32(tmp);
2327
ffbcfed4
MC		 2328 return 0;
2329}
2330
2331#define NVRAM_CMD_TIMEOUT 10000
2332
2333static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2334{
2335 int i;
2336
2337 tw32(NVRAM_CMD, nvram_cmd);
2338 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2339 udelay(10);
2340 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2341 udelay(10);
2342 break;
2343 }
2344 }
2345
2346 if (i == NVRAM_CMD_TIMEOUT)
2347 return -EBUSY;
2348
2349 return 0;
2350}
2351
2352static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2353{
2354 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2355 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2356 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2357 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2358 (tp->nvram_jedecnum == JEDEC_ATMEL))
2359
2360 addr = ((addr / tp->nvram_pagesize) <<
2361 ATMEL_AT45DB0X1B_PAGE_POS) +
2362 (addr % tp->nvram_pagesize);
2363
2364 return addr;
2365}
2366
2367static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2368{
2369 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2370 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2371 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2372 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2373 (tp->nvram_jedecnum == JEDEC_ATMEL))
2374
2375 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2376 tp->nvram_pagesize) +
2377 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2378
2379 return addr;
2380}
2381
e4f34110
MC		 2382/* NOTE: Data read in from NVRAM is byteswapped according to
2383 * the byteswapping settings for all other register accesses.
2384 * tg3 devices are BE devices, so on a BE machine, the data
2385 * returned will be exactly as it is seen in NVRAM. On a LE
2386 * machine, the 32-bit value will be byteswapped.
2387 */
ffbcfed4
MC		 2388static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2389{
2390 int ret;
2391
2392 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2393 return tg3_nvram_read_using_eeprom(tp, offset, val);
2394
2395 offset = tg3_nvram_phys_addr(tp, offset);
2396
2397 if (offset > NVRAM_ADDR_MSK)
2398 return -EINVAL;
2399
2400 ret = tg3_nvram_lock(tp);
2401 if (ret)
2402 return ret;
2403
2404 tg3_enable_nvram_access(tp);
2405
2406 tw32(NVRAM_ADDR, offset);
2407 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2408 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2409
2410 if (ret == 0)
e4f34110 2411 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2412
2413 tg3_disable_nvram_access(tp);
2414
2415 tg3_nvram_unlock(tp);
2416
2417 return ret;
2418}
2419
a9dc529d
MC		 2420/* Ensures NVRAM data is in bytestream format. */
2421static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2422{
2423 u32 v;
a9dc529d 2424 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2425 if (!res)
a9dc529d 2426 *val = cpu_to_be32(v);
ffbcfed4
MC		 2427 return res;
2428}
2429
3f007891
MC		 2430/* tp->lock is held. */
2431static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2432{
2433 u32 addr_high, addr_low;
2434 int i;
2435
2436 addr_high = ((tp->dev->dev_addr[0] << 8) |
2437 tp->dev->dev_addr[1]);
2438 addr_low = ((tp->dev->dev_addr[2] << 24) |
2439 (tp->dev->dev_addr[3] << 16) |
2440 (tp->dev->dev_addr[4] << 8) |
2441 (tp->dev->dev_addr[5] << 0));
2442 for (i = 0; i < 4; i++) {
2443 if (i == 1 && skip_mac_1)
2444 continue;
2445 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2446 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2447 }
2448
2449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2451 for (i = 0; i < 12; i++) {
2452 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2453 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2454 }
2455 }
2456
2457 addr_high = (tp->dev->dev_addr[0] +
2458 tp->dev->dev_addr[1] +
2459 tp->dev->dev_addr[2] +
2460 tp->dev->dev_addr[3] +
2461 tp->dev->dev_addr[4] +
2462 tp->dev->dev_addr[5]) &
2463 TX_BACKOFF_SEED_MASK;
2464 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2465}
2466
bc1c7567 2467static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2468{
2469 u32 misc_host_ctrl;
0a459aac 2470 bool device_should_wake, do_low_power;
1da177e4
LT		 2471
2472 /* Make sure register accesses (indirect or otherwise)
2473 * will function correctly.
2474 */
2475 pci_write_config_dword(tp->pdev,
2476 TG3PCI_MISC_HOST_CTRL,
2477 tp->misc_host_ctrl);
2478
1da177e4 2479 switch (state) {
bc1c7567 2480 case PCI_D0:
12dac075
RW		 2481 pci_enable_wake(tp->pdev, state, false);
2482 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2483
9d26e213
MC		 2484 /* Switch out of Vaux if it is a NIC */
2485 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2486 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2487
2488 return 0;
2489
bc1c7567 2490 case PCI_D1:
bc1c7567 2491 case PCI_D2:
bc1c7567 2492 case PCI_D3hot:
1da177e4
LT		 2493 break;
2494
2495 default:
05dbe005
JP		 2496 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2497 state);
1da177e4 2498 return -EINVAL;
855e1111 2499 }
5e7dfd0f
MC		 2500
2501 /* Restore the CLKREQ setting. */
2502 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2503 u16 lnkctl;
2504
2505 pci_read_config_word(tp->pdev,
2506 tp->pcie_cap + PCI_EXP_LNKCTL,
2507 &lnkctl);
2508 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2509 pci_write_config_word(tp->pdev,
2510 tp->pcie_cap + PCI_EXP_LNKCTL,
2511 lnkctl);
2512 }
2513
1da177e4
LT		 2514 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2515 tw32(TG3PCI_MISC_HOST_CTRL,
2516 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2517
05ac4cb7
MC		 2518 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2519 device_may_wakeup(&tp->pdev->dev) &&
2520 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2521
dd477003 2522 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2523 do_low_power = false;
b02fd9e3
MC		 2524 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2525 !tp->link_config.phy_is_low_power) {
2526 struct phy_device *phydev;
0a459aac 2527 u32 phyid, advertising;
b02fd9e3 2528
3f0e3ad7 2529 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2530
2531 tp->link_config.phy_is_low_power = 1;
2532
2533 tp->link_config.orig_speed = phydev->speed;
2534 tp->link_config.orig_duplex = phydev->duplex;
2535 tp->link_config.orig_autoneg = phydev->autoneg;
2536 tp->link_config.orig_advertising = phydev->advertising;
2537
2538 advertising = ADVERTISED_TP |
2539 ADVERTISED_Pause |
2540 ADVERTISED_Autoneg |
2541 ADVERTISED_10baseT_Half;
2542
2543 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2544 device_should_wake) {
b02fd9e3
MC		 2545 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2546 advertising |=
2547 ADVERTISED_100baseT_Half |
2548 ADVERTISED_100baseT_Full |
2549 ADVERTISED_10baseT_Full;
2550 else
2551 advertising |= ADVERTISED_10baseT_Full;
2552 }
2553
2554 phydev->advertising = advertising;
2555
2556 phy_start_aneg(phydev);
0a459aac
MC		 2557
2558 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 2559 if (phyid != PHY_ID_BCMAC131) {
2560 phyid &= PHY_BCM_OUI_MASK;
2561 if (phyid == PHY_BCM_OUI_1 ||
2562 phyid == PHY_BCM_OUI_2 ||
2563 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 2564 do_low_power = true;
2565 }
b02fd9e3 2566 }
dd477003 2567 } else {
2023276e 2568 do_low_power = true;
0a459aac 2569
dd477003
MC		 2570 if (tp->link_config.phy_is_low_power == 0) {
2571 tp->link_config.phy_is_low_power = 1;
2572 tp->link_config.orig_speed = tp->link_config.speed;
2573 tp->link_config.orig_duplex = tp->link_config.duplex;
2574 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2575 }
1da177e4 2576
dd477003
MC		 2577 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2578 tp->link_config.speed = SPEED_10;
2579 tp->link_config.duplex = DUPLEX_HALF;
2580 tp->link_config.autoneg = AUTONEG_ENABLE;
2581 tg3_setup_phy(tp, 0);
2582 }
1da177e4
LT		 2583 }
2584
b5d3772c
MC		 2585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2586 u32 val;
2587
2588 val = tr32(GRC_VCPU_EXT_CTRL);
2589 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2590 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2591 int i;
2592 u32 val;
2593
2594 for (i = 0; i < 200; i++) {
2595 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2596 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2597 break;
2598 msleep(1);
2599 }
2600 }
a85feb8c
GZ		 2601 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2602 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2603 WOL_DRV_STATE_SHUTDOWN |
2604 WOL_DRV_WOL |
2605 WOL_SET_MAGIC_PKT);
6921d201 2606
05ac4cb7 2607 if (device_should_wake) {
1da177e4
LT		 2608 u32 mac_mode;
2609
2610 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2611 if (do_low_power) {
dd477003
MC		 2612 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2613 udelay(40);
2614 }
1da177e4 2615
3f7045c1
MC		 2616 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2617 mac_mode = MAC_MODE_PORT_MODE_GMII;
2618 else
2619 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2620
e8f3f6ca
MC		 2621 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2622 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2623 ASIC_REV_5700) {
2624 u32 speed = (tp->tg3_flags &
2625 TG3_FLAG_WOL_SPEED_100MB) ?
2626 SPEED_100 : SPEED_10;
2627 if (tg3_5700_link_polarity(tp, speed))
2628 mac_mode |= MAC_MODE_LINK_POLARITY;
2629 else
2630 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2631 }
1da177e4
LT		 2632 } else {
2633 mac_mode = MAC_MODE_PORT_MODE_TBI;
2634 }
2635
cbf46853 2636 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2637 tw32(MAC_LED_CTRL, tp->led_ctrl);
2638
05ac4cb7
MC		 2639 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2640 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2641 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2642 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2643 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2644 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2645
3bda1258
MC		 2646 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2647 mac_mode |= tp->mac_mode &
2648 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2649 if (mac_mode & MAC_MODE_APE_TX_EN)
2650 mac_mode |= MAC_MODE_TDE_ENABLE;
2651 }
2652
1da177e4
LT		 2653 tw32_f(MAC_MODE, mac_mode);
2654 udelay(100);
2655
2656 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2657 udelay(10);
2658 }
2659
2660 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2663 u32 base_val;
2664
2665 base_val = tp->pci_clock_ctrl;
2666 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2667 CLOCK_CTRL_TXCLK_DISABLE);
2668
b401e9e2
MC		 2669 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2670 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2671 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2672 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2673 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2674 /* do nothing */
85e94ced 2675 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2676 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2677 u32 newbits1, newbits2;
2678
2679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2681 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2682 CLOCK_CTRL_TXCLK_DISABLE |
2683 CLOCK_CTRL_ALTCLK);
2684 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2685 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2686 newbits1 = CLOCK_CTRL_625_CORE;
2687 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2688 } else {
2689 newbits1 = CLOCK_CTRL_ALTCLK;
2690 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2691 }
2692
b401e9e2
MC		 2693 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2694 40);
1da177e4 2695
b401e9e2
MC		 2696 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2697 40);
1da177e4
LT		 2698
2699 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2700 u32 newbits3;
2701
2702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2704 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2705 CLOCK_CTRL_TXCLK_DISABLE |
2706 CLOCK_CTRL_44MHZ_CORE);
2707 } else {
2708 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2709 }
2710
b401e9e2
MC		 2711 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2712 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2713 }
2714 }
2715
05ac4cb7 2716 if (!(device_should_wake) &&
22435849 2717 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2718 tg3_power_down_phy(tp, do_low_power);
6921d201 2719
1da177e4
LT		 2720 tg3_frob_aux_power(tp);
2721
2722 /* Workaround for unstable PLL clock */
2723 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2724 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2725 u32 val = tr32(0x7d00);
2726
2727 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2728 tw32(0x7d00, val);
6921d201 2729 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2730 int err;
2731
2732 err = tg3_nvram_lock(tp);
1da177e4 2733 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2734 if (!err)
2735 tg3_nvram_unlock(tp);
6921d201 2736 }
1da177e4
LT		 2737 }
2738
bbadf503
MC		 2739 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2740
05ac4cb7 2741 if (device_should_wake)
12dac075
RW		 2742 pci_enable_wake(tp->pdev, state, true);
2743
1da177e4 2744 /* Finally, set the new power state. */
12dac075 2745 pci_set_power_state(tp->pdev, state);
1da177e4 2746
1da177e4
LT		 2747 return 0;
2748}
2749
1da177e4
LT		 2750static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2751{
2752 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2753 case MII_TG3_AUX_STAT_10HALF:
2754 *speed = SPEED_10;
2755 *duplex = DUPLEX_HALF;
2756 break;
2757
2758 case MII_TG3_AUX_STAT_10FULL:
2759 *speed = SPEED_10;
2760 *duplex = DUPLEX_FULL;
2761 break;
2762
2763 case MII_TG3_AUX_STAT_100HALF:
2764 *speed = SPEED_100;
2765 *duplex = DUPLEX_HALF;
2766 break;
2767
2768 case MII_TG3_AUX_STAT_100FULL:
2769 *speed = SPEED_100;
2770 *duplex = DUPLEX_FULL;
2771 break;
2772
2773 case MII_TG3_AUX_STAT_1000HALF:
2774 *speed = SPEED_1000;
2775 *duplex = DUPLEX_HALF;
2776 break;
2777
2778 case MII_TG3_AUX_STAT_1000FULL:
2779 *speed = SPEED_1000;
2780 *duplex = DUPLEX_FULL;
2781 break;
2782
2783 default:
7f97a4bd 2784 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2785 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2786 SPEED_10;
2787 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2788 DUPLEX_HALF;
2789 break;
2790 }
1da177e4
LT		 2791 *speed = SPEED_INVALID;
2792 *duplex = DUPLEX_INVALID;
2793 break;
855e1111 2794 }
1da177e4
LT		 2795}
2796
2797static void tg3_phy_copper_begin(struct tg3 *tp)
2798{
2799 u32 new_adv;
2800 int i;
2801
2802 if (tp->link_config.phy_is_low_power) {
2803 /* Entering low power mode. Disable gigabit and
2804 * 100baseT advertisements.
2805 */
2806 tg3_writephy(tp, MII_TG3_CTRL, 0);
2807
2808 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2809 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2810 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2811 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2812
2813 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2814 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2815 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2816 tp->link_config.advertising &=
2817 ~(ADVERTISED_1000baseT_Half |
2818 ADVERTISED_1000baseT_Full);
2819
ba4d07a8 2820 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2821 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2822 new_adv |= ADVERTISE_10HALF;
2823 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2824 new_adv |= ADVERTISE_10FULL;
2825 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2826 new_adv |= ADVERTISE_100HALF;
2827 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2828 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2829
2830 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831
1da177e4
LT		 2832 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2833
2834 if (tp->link_config.advertising &
2835 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2836 new_adv = 0;
2837 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2838 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2839 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2840 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2841 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2842 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2843 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2844 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2845 MII_TG3_CTRL_ENABLE_AS_MASTER);
2846 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2847 } else {
2848 tg3_writephy(tp, MII_TG3_CTRL, 0);
2849 }
2850 } else {
ba4d07a8
MC		 2851 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2852 new_adv |= ADVERTISE_CSMA;
2853
1da177e4
LT		 2854 /* Asking for a specific link mode. */
2855 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2856 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2857
2858 if (tp->link_config.duplex == DUPLEX_FULL)
2859 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2860 else
2861 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2862 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2863 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2864 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2865 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2866 } else {
1da177e4
LT		 2867 if (tp->link_config.speed == SPEED_100) {
2868 if (tp->link_config.duplex == DUPLEX_FULL)
2869 new_adv |= ADVERTISE_100FULL;
2870 else
2871 new_adv |= ADVERTISE_100HALF;
2872 } else {
2873 if (tp->link_config.duplex == DUPLEX_FULL)
2874 new_adv |= ADVERTISE_10FULL;
2875 else
2876 new_adv |= ADVERTISE_10HALF;
2877 }
2878 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2879
2880 new_adv = 0;
1da177e4 2881 }
ba4d07a8
MC		 2882
2883 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2884 }
2885
2886 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2887 tp->link_config.speed != SPEED_INVALID) {
2888 u32 bmcr, orig_bmcr;
2889
2890 tp->link_config.active_speed = tp->link_config.speed;
2891 tp->link_config.active_duplex = tp->link_config.duplex;
2892
2893 bmcr = 0;
2894 switch (tp->link_config.speed) {
2895 default:
2896 case SPEED_10:
2897 break;
2898
2899 case SPEED_100:
2900 bmcr |= BMCR_SPEED100;
2901 break;
2902
2903 case SPEED_1000:
2904 bmcr |= TG3_BMCR_SPEED1000;
2905 break;
855e1111 2906 }
1da177e4
LT		 2907
2908 if (tp->link_config.duplex == DUPLEX_FULL)
2909 bmcr |= BMCR_FULLDPLX;
2910
2911 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2912 (bmcr != orig_bmcr)) {
2913 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2914 for (i = 0; i < 1500; i++) {
2915 u32 tmp;
2916
2917 udelay(10);
2918 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2919 tg3_readphy(tp, MII_BMSR, &tmp))
2920 continue;
2921 if (!(tmp & BMSR_LSTATUS)) {
2922 udelay(40);
2923 break;
2924 }
2925 }
2926 tg3_writephy(tp, MII_BMCR, bmcr);
2927 udelay(40);
2928 }
2929 } else {
2930 tg3_writephy(tp, MII_BMCR,
2931 BMCR_ANENABLE | BMCR_ANRESTART);
2932 }
2933}
2934
2935static int tg3_init_5401phy_dsp(struct tg3 *tp)
2936{
2937 int err;
2938
2939 /* Turn off tap power management. */
2940 /* Set Extended packet length bit */
2941 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2942
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2945
2946 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2947 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2948
2949 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2951
2952 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2953 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2954
2955 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2956 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2957
2958 udelay(40);
2959
2960 return err;
2961}
2962
3600d918 2963static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2964{
3600d918
MC		 2965 u32 adv_reg, all_mask = 0;
2966
2967 if (mask & ADVERTISED_10baseT_Half)
2968 all_mask |= ADVERTISE_10HALF;
2969 if (mask & ADVERTISED_10baseT_Full)
2970 all_mask |= ADVERTISE_10FULL;
2971 if (mask & ADVERTISED_100baseT_Half)
2972 all_mask |= ADVERTISE_100HALF;
2973 if (mask & ADVERTISED_100baseT_Full)
2974 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2975
2976 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2977 return 0;
2978
1da177e4
LT		 2979 if ((adv_reg & all_mask) != all_mask)
2980 return 0;
2981 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2982 u32 tg3_ctrl;
2983
3600d918
MC		 2984 all_mask = 0;
2985 if (mask & ADVERTISED_1000baseT_Half)
2986 all_mask |= ADVERTISE_1000HALF;
2987 if (mask & ADVERTISED_1000baseT_Full)
2988 all_mask |= ADVERTISE_1000FULL;
2989
1da177e4
LT		 2990 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2991 return 0;
2992
1da177e4
LT		 2993 if ((tg3_ctrl & all_mask) != all_mask)
2994 return 0;
2995 }
2996 return 1;
2997}
2998
ef167e27
MC		 2999static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3000{
3001 u32 curadv, reqadv;
3002
3003 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3004 return 1;
3005
3006 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3007 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3008
3009 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3010 if (curadv != reqadv)
3011 return 0;
3012
3013 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3014 tg3_readphy(tp, MII_LPA, rmtadv);
3015 } else {
3016 /* Reprogram the advertisement register, even if it
3017 * does not affect the current link. If the link
3018 * gets renegotiated in the future, we can save an
3019 * additional renegotiation cycle by advertising
3020 * it correctly in the first place.
3021 */
3022 if (curadv != reqadv) {
3023 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3024 ADVERTISE_PAUSE_ASYM);
3025 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3026 }
3027 }
3028
3029 return 1;
3030}
3031
1da177e4
LT		 3032static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3033{
3034 int current_link_up;
3035 u32 bmsr, dummy;
ef167e27 3036 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3037 u16 current_speed;
3038 u8 current_duplex;
3039 int i, err;
3040
3041 tw32(MAC_EVENT, 0);
3042
3043 tw32_f(MAC_STATUS,
3044 (MAC_STATUS_SYNC_CHANGED |
3045 MAC_STATUS_CFG_CHANGED |
3046 MAC_STATUS_MI_COMPLETION |
3047 MAC_STATUS_LNKSTATE_CHANGED));
3048 udelay(40);
3049
8ef21428
MC		 3050 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3051 tw32_f(MAC_MI_MODE,
3052 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3053 udelay(80);
3054 }
1da177e4
LT		 3055
3056 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3057
3058 /* Some third-party PHYs need to be reset on link going
3059 * down.
3060 */
3061 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3064 netif_carrier_ok(tp->dev)) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 !(bmsr & BMSR_LSTATUS))
3068 force_reset = 1;
3069 }
3070 if (force_reset)
3071 tg3_phy_reset(tp);
3072
79eb6904 3073 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 3074 tg3_readphy(tp, MII_BMSR, &bmsr);
3075 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3076 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3077 bmsr = 0;
3078
3079 if (!(bmsr & BMSR_LSTATUS)) {
3080 err = tg3_init_5401phy_dsp(tp);
3081 if (err)
3082 return err;
3083
3084 tg3_readphy(tp, MII_BMSR, &bmsr);
3085 for (i = 0; i < 1000; i++) {
3086 udelay(10);
3087 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3088 (bmsr & BMSR_LSTATUS)) {
3089 udelay(40);
3090 break;
3091 }
3092 }
3093
79eb6904
MC		 3094 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3095 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 3096 !(bmsr & BMSR_LSTATUS) &&
3097 tp->link_config.active_speed == SPEED_1000) {
3098 err = tg3_phy_reset(tp);
3099 if (!err)
3100 err = tg3_init_5401phy_dsp(tp);
3101 if (err)
3102 return err;
3103 }
3104 }
3105 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3106 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3107 /* 5701 {A0,B0} CRC bug workaround */
3108 tg3_writephy(tp, 0x15, 0x0a75);
3109 tg3_writephy(tp, 0x1c, 0x8c68);
3110 tg3_writephy(tp, 0x1c, 0x8d68);
3111 tg3_writephy(tp, 0x1c, 0x8c68);
3112 }
3113
3114 /* Clear pending interrupts... */
3115 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3116 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3117
3118 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3119 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3120 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3121 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3122
3123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3125 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3126 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3127 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3128 else
3129 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3130 }
3131
3132 current_link_up = 0;
3133 current_speed = SPEED_INVALID;
3134 current_duplex = DUPLEX_INVALID;
3135
3136 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3137 u32 val;
3138
3139 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3140 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3141 if (!(val & (1 << 10))) {
3142 val |= (1 << 10);
3143 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3144 goto relink;
3145 }
3146 }
3147
3148 bmsr = 0;
3149 for (i = 0; i < 100; i++) {
3150 tg3_readphy(tp, MII_BMSR, &bmsr);
3151 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3152 (bmsr & BMSR_LSTATUS))
3153 break;
3154 udelay(40);
3155 }
3156
3157 if (bmsr & BMSR_LSTATUS) {
3158 u32 aux_stat, bmcr;
3159
3160 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3161 for (i = 0; i < 2000; i++) {
3162 udelay(10);
3163 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3164 aux_stat)
3165 break;
3166 }
3167
3168 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3169 &current_speed,
3170 &current_duplex);
3171
3172 bmcr = 0;
3173 for (i = 0; i < 200; i++) {
3174 tg3_readphy(tp, MII_BMCR, &bmcr);
3175 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3176 continue;
3177 if (bmcr && bmcr != 0x7fff)
3178 break;
3179 udelay(10);
3180 }
3181
ef167e27
MC		 3182 lcl_adv = 0;
3183 rmt_adv = 0;
1da177e4 3184
ef167e27
MC		 3185 tp->link_config.active_speed = current_speed;
3186 tp->link_config.active_duplex = current_duplex;
3187
3188 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3189 if ((bmcr & BMCR_ANENABLE) &&
3190 tg3_copper_is_advertising_all(tp,
3191 tp->link_config.advertising)) {
3192 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3193 &rmt_adv))
3194 current_link_up = 1;
1da177e4
LT		 3195 }
3196 } else {
3197 if (!(bmcr & BMCR_ANENABLE) &&
3198 tp->link_config.speed == current_speed &&
ef167e27
MC		 3199 tp->link_config.duplex == current_duplex &&
3200 tp->link_config.flowctrl ==
3201 tp->link_config.active_flowctrl) {
1da177e4 3202 current_link_up = 1;
1da177e4
LT		 3203 }
3204 }
3205
ef167e27
MC		 3206 if (current_link_up == 1 &&
3207 tp->link_config.active_duplex == DUPLEX_FULL)
3208 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3209 }
3210
1da177e4 3211relink:
6921d201 3212 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3213 u32 tmp;
3214
3215 tg3_phy_copper_begin(tp);
3216
3217 tg3_readphy(tp, MII_BMSR, &tmp);
3218 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3219 (tmp & BMSR_LSTATUS))
3220 current_link_up = 1;
3221 }
3222
3223 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3224 if (current_link_up == 1) {
3225 if (tp->link_config.active_speed == SPEED_100 ||
3226 tp->link_config.active_speed == SPEED_10)
3227 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3228 else
3229 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3230 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3231 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3232 else
1da177e4
LT		 3233 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3234
3235 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3236 if (tp->link_config.active_duplex == DUPLEX_HALF)
3237 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3238
1da177e4 3239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3240 if (current_link_up == 1 &&
3241 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3242 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3243 else
3244 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3245 }
3246
3247 /* ??? Without this setting Netgear GA302T PHY does not
3248 * ??? send/receive packets...
3249 */
79eb6904 3250 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1da177e4
LT		 3251 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3252 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3253 tw32_f(MAC_MI_MODE, tp->mi_mode);
3254 udelay(80);
3255 }
3256
3257 tw32_f(MAC_MODE, tp->mac_mode);
3258 udelay(40);
3259
3260 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3261 /* Polled via timer. */
3262 tw32_f(MAC_EVENT, 0);
3263 } else {
3264 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3265 }
3266 udelay(40);
3267
3268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3269 current_link_up == 1 &&
3270 tp->link_config.active_speed == SPEED_1000 &&
3271 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3272 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3273 udelay(120);
3274 tw32_f(MAC_STATUS,
3275 (MAC_STATUS_SYNC_CHANGED |
3276 MAC_STATUS_CFG_CHANGED));
3277 udelay(40);
3278 tg3_write_mem(tp,
3279 NIC_SRAM_FIRMWARE_MBOX,
3280 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3281 }
3282
5e7dfd0f
MC		 3283 /* Prevent send BD corruption. */
3284 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3285 u16 oldlnkctl, newlnkctl;
3286
3287 pci_read_config_word(tp->pdev,
3288 tp->pcie_cap + PCI_EXP_LNKCTL,
3289 &oldlnkctl);
3290 if (tp->link_config.active_speed == SPEED_100 ||
3291 tp->link_config.active_speed == SPEED_10)
3292 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3293 else
3294 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3295 if (newlnkctl != oldlnkctl)
3296 pci_write_config_word(tp->pdev,
3297 tp->pcie_cap + PCI_EXP_LNKCTL,
3298 newlnkctl);
3299 }
3300
1da177e4
LT		 3301 if (current_link_up != netif_carrier_ok(tp->dev)) {
3302 if (current_link_up)
3303 netif_carrier_on(tp->dev);
3304 else
3305 netif_carrier_off(tp->dev);
3306 tg3_link_report(tp);
3307 }
3308
3309 return 0;
3310}
3311
3312struct tg3_fiber_aneginfo {
3313 int state;
3314#define ANEG_STATE_UNKNOWN 0
3315#define ANEG_STATE_AN_ENABLE 1
3316#define ANEG_STATE_RESTART_INIT 2
3317#define ANEG_STATE_RESTART 3
3318#define ANEG_STATE_DISABLE_LINK_OK 4
3319#define ANEG_STATE_ABILITY_DETECT_INIT 5
3320#define ANEG_STATE_ABILITY_DETECT 6
3321#define ANEG_STATE_ACK_DETECT_INIT 7
3322#define ANEG_STATE_ACK_DETECT 8
3323#define ANEG_STATE_COMPLETE_ACK_INIT 9
3324#define ANEG_STATE_COMPLETE_ACK 10
3325#define ANEG_STATE_IDLE_DETECT_INIT 11
3326#define ANEG_STATE_IDLE_DETECT 12
3327#define ANEG_STATE_LINK_OK 13
3328#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3329#define ANEG_STATE_NEXT_PAGE_WAIT 15
3330
3331 u32 flags;
3332#define MR_AN_ENABLE 0x00000001
3333#define MR_RESTART_AN 0x00000002
3334#define MR_AN_COMPLETE 0x00000004
3335#define MR_PAGE_RX 0x00000008
3336#define MR_NP_LOADED 0x00000010
3337#define MR_TOGGLE_TX 0x00000020
3338#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3339#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3340#define MR_LP_ADV_SYM_PAUSE 0x00000100
3341#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3342#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3343#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3344#define MR_LP_ADV_NEXT_PAGE 0x00001000
3345#define MR_TOGGLE_RX 0x00002000
3346#define MR_NP_RX 0x00004000
3347
3348#define MR_LINK_OK 0x80000000
3349
3350 unsigned long link_time, cur_time;
3351
3352 u32 ability_match_cfg;
3353 int ability_match_count;
3354
3355 char ability_match, idle_match, ack_match;
3356
3357 u32 txconfig, rxconfig;
3358#define ANEG_CFG_NP 0x00000080
3359#define ANEG_CFG_ACK 0x00000040
3360#define ANEG_CFG_RF2 0x00000020
3361#define ANEG_CFG_RF1 0x00000010
3362#define ANEG_CFG_PS2 0x00000001
3363#define ANEG_CFG_PS1 0x00008000
3364#define ANEG_CFG_HD 0x00004000
3365#define ANEG_CFG_FD 0x00002000
3366#define ANEG_CFG_INVAL 0x00001f06
3367
3368};
3369#define ANEG_OK 0
3370#define ANEG_DONE 1
3371#define ANEG_TIMER_ENAB 2
3372#define ANEG_FAILED -1
3373
3374#define ANEG_STATE_SETTLE_TIME 10000
3375
3376static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3377 struct tg3_fiber_aneginfo *ap)
3378{
5be73b47 3379 u16 flowctrl;
1da177e4
LT		 3380 unsigned long delta;
3381 u32 rx_cfg_reg;
3382 int ret;
3383
3384 if (ap->state == ANEG_STATE_UNKNOWN) {
3385 ap->rxconfig = 0;
3386 ap->link_time = 0;
3387 ap->cur_time = 0;
3388 ap->ability_match_cfg = 0;
3389 ap->ability_match_count = 0;
3390 ap->ability_match = 0;
3391 ap->idle_match = 0;
3392 ap->ack_match = 0;
3393 }
3394 ap->cur_time++;
3395
3396 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3397 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3398
3399 if (rx_cfg_reg != ap->ability_match_cfg) {
3400 ap->ability_match_cfg = rx_cfg_reg;
3401 ap->ability_match = 0;
3402 ap->ability_match_count = 0;
3403 } else {
3404 if (++ap->ability_match_count > 1) {
3405 ap->ability_match = 1;
3406 ap->ability_match_cfg = rx_cfg_reg;
3407 }
3408 }
3409 if (rx_cfg_reg & ANEG_CFG_ACK)
3410 ap->ack_match = 1;
3411 else
3412 ap->ack_match = 0;
3413
3414 ap->idle_match = 0;
3415 } else {
3416 ap->idle_match = 1;
3417 ap->ability_match_cfg = 0;
3418 ap->ability_match_count = 0;
3419 ap->ability_match = 0;
3420 ap->ack_match = 0;
3421
3422 rx_cfg_reg = 0;
3423 }
3424
3425 ap->rxconfig = rx_cfg_reg;
3426 ret = ANEG_OK;
3427
3428 switch(ap->state) {
3429 case ANEG_STATE_UNKNOWN:
3430 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3431 ap->state = ANEG_STATE_AN_ENABLE;
3432
3433 /* fallthru */
3434 case ANEG_STATE_AN_ENABLE:
3435 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3436 if (ap->flags & MR_AN_ENABLE) {
3437 ap->link_time = 0;
3438 ap->cur_time = 0;
3439 ap->ability_match_cfg = 0;
3440 ap->ability_match_count = 0;
3441 ap->ability_match = 0;
3442 ap->idle_match = 0;
3443 ap->ack_match = 0;
3444
3445 ap->state = ANEG_STATE_RESTART_INIT;
3446 } else {
3447 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3448 }
3449 break;
3450
3451 case ANEG_STATE_RESTART_INIT:
3452 ap->link_time = ap->cur_time;
3453 ap->flags &= ~(MR_NP_LOADED);
3454 ap->txconfig = 0;
3455 tw32(MAC_TX_AUTO_NEG, 0);
3456 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3457 tw32_f(MAC_MODE, tp->mac_mode);
3458 udelay(40);
3459
3460 ret = ANEG_TIMER_ENAB;
3461 ap->state = ANEG_STATE_RESTART;
3462
3463 /* fallthru */
3464 case ANEG_STATE_RESTART:
3465 delta = ap->cur_time - ap->link_time;
3466 if (delta > ANEG_STATE_SETTLE_TIME) {
3467 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3468 } else {
3469 ret = ANEG_TIMER_ENAB;
3470 }
3471 break;
3472
3473 case ANEG_STATE_DISABLE_LINK_OK:
3474 ret = ANEG_DONE;
3475 break;
3476
3477 case ANEG_STATE_ABILITY_DETECT_INIT:
3478 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3479 ap->txconfig = ANEG_CFG_FD;
3480 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3481 if (flowctrl & ADVERTISE_1000XPAUSE)
3482 ap->txconfig |= ANEG_CFG_PS1;
3483 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3484 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3485 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487 tw32_f(MAC_MODE, tp->mac_mode);
3488 udelay(40);
3489
3490 ap->state = ANEG_STATE_ABILITY_DETECT;
3491 break;
3492
3493 case ANEG_STATE_ABILITY_DETECT:
3494 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3495 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3496 }
3497 break;
3498
3499 case ANEG_STATE_ACK_DETECT_INIT:
3500 ap->txconfig |= ANEG_CFG_ACK;
3501 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3502 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3503 tw32_f(MAC_MODE, tp->mac_mode);
3504 udelay(40);
3505
3506 ap->state = ANEG_STATE_ACK_DETECT;
3507
3508 /* fallthru */
3509 case ANEG_STATE_ACK_DETECT:
3510 if (ap->ack_match != 0) {
3511 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3512 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3513 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3514 } else {
3515 ap->state = ANEG_STATE_AN_ENABLE;
3516 }
3517 } else if (ap->ability_match != 0 &&
3518 ap->rxconfig == 0) {
3519 ap->state = ANEG_STATE_AN_ENABLE;
3520 }
3521 break;
3522
3523 case ANEG_STATE_COMPLETE_ACK_INIT:
3524 if (ap->rxconfig & ANEG_CFG_INVAL) {
3525 ret = ANEG_FAILED;
3526 break;
3527 }
3528 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3529 MR_LP_ADV_HALF_DUPLEX |
3530 MR_LP_ADV_SYM_PAUSE |
3531 MR_LP_ADV_ASYM_PAUSE |
3532 MR_LP_ADV_REMOTE_FAULT1 |
3533 MR_LP_ADV_REMOTE_FAULT2 |
3534 MR_LP_ADV_NEXT_PAGE |
3535 MR_TOGGLE_RX |
3536 MR_NP_RX);
3537 if (ap->rxconfig & ANEG_CFG_FD)
3538 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3539 if (ap->rxconfig & ANEG_CFG_HD)
3540 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3541 if (ap->rxconfig & ANEG_CFG_PS1)
3542 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3543 if (ap->rxconfig & ANEG_CFG_PS2)
3544 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3545 if (ap->rxconfig & ANEG_CFG_RF1)
3546 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3547 if (ap->rxconfig & ANEG_CFG_RF2)
3548 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3549 if (ap->rxconfig & ANEG_CFG_NP)
3550 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3551
3552 ap->link_time = ap->cur_time;
3553
3554 ap->flags ^= (MR_TOGGLE_TX);
3555 if (ap->rxconfig & 0x0008)
3556 ap->flags |= MR_TOGGLE_RX;
3557 if (ap->rxconfig & ANEG_CFG_NP)
3558 ap->flags |= MR_NP_RX;
3559 ap->flags |= MR_PAGE_RX;
3560
3561 ap->state = ANEG_STATE_COMPLETE_ACK;
3562 ret = ANEG_TIMER_ENAB;
3563 break;
3564
3565 case ANEG_STATE_COMPLETE_ACK:
3566 if (ap->ability_match != 0 &&
3567 ap->rxconfig == 0) {
3568 ap->state = ANEG_STATE_AN_ENABLE;
3569 break;
3570 }
3571 delta = ap->cur_time - ap->link_time;
3572 if (delta > ANEG_STATE_SETTLE_TIME) {
3573 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3574 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3575 } else {
3576 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3577 !(ap->flags & MR_NP_RX)) {
3578 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3579 } else {
3580 ret = ANEG_FAILED;
3581 }
3582 }
3583 }
3584 break;
3585
3586 case ANEG_STATE_IDLE_DETECT_INIT:
3587 ap->link_time = ap->cur_time;
3588 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3589 tw32_f(MAC_MODE, tp->mac_mode);
3590 udelay(40);
3591
3592 ap->state = ANEG_STATE_IDLE_DETECT;
3593 ret = ANEG_TIMER_ENAB;
3594 break;
3595
3596 case ANEG_STATE_IDLE_DETECT:
3597 if (ap->ability_match != 0 &&
3598 ap->rxconfig == 0) {
3599 ap->state = ANEG_STATE_AN_ENABLE;
3600 break;
3601 }
3602 delta = ap->cur_time - ap->link_time;
3603 if (delta > ANEG_STATE_SETTLE_TIME) {
3604 /* XXX another gem from the Broadcom driver :( */
3605 ap->state = ANEG_STATE_LINK_OK;
3606 }
3607 break;
3608
3609 case ANEG_STATE_LINK_OK:
3610 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3611 ret = ANEG_DONE;
3612 break;
3613
3614 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3615 /* ??? unimplemented */
3616 break;
3617
3618 case ANEG_STATE_NEXT_PAGE_WAIT:
3619 /* ??? unimplemented */
3620 break;
3621
3622 default:
3623 ret = ANEG_FAILED;
3624 break;
855e1111 3625 }
1da177e4
LT		 3626
3627 return ret;
3628}
3629
5be73b47 3630static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3631{
3632 int res = 0;
3633 struct tg3_fiber_aneginfo aninfo;
3634 int status = ANEG_FAILED;
3635 unsigned int tick;
3636 u32 tmp;
3637
3638 tw32_f(MAC_TX_AUTO_NEG, 0);
3639
3640 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3641 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3642 udelay(40);
3643
3644 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3645 udelay(40);
3646
3647 memset(&aninfo, 0, sizeof(aninfo));
3648 aninfo.flags |= MR_AN_ENABLE;
3649 aninfo.state = ANEG_STATE_UNKNOWN;
3650 aninfo.cur_time = 0;
3651 tick = 0;
3652 while (++tick < 195000) {
3653 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3654 if (status == ANEG_DONE || status == ANEG_FAILED)
3655 break;
3656
3657 udelay(1);
3658 }
3659
3660 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3661 tw32_f(MAC_MODE, tp->mac_mode);
3662 udelay(40);
3663
5be73b47
MC		 3664 *txflags = aninfo.txconfig;
3665 *rxflags = aninfo.flags;
1da177e4
LT		 3666
3667 if (status == ANEG_DONE &&
3668 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3669 MR_LP_ADV_FULL_DUPLEX)))
3670 res = 1;
3671
3672 return res;
3673}
3674
3675static void tg3_init_bcm8002(struct tg3 *tp)
3676{
3677 u32 mac_status = tr32(MAC_STATUS);
3678 int i;
3679
3680 /* Reset when initting first time or we have a link. */
3681 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3682 !(mac_status & MAC_STATUS_PCS_SYNCED))
3683 return;
3684
3685 /* Set PLL lock range. */
3686 tg3_writephy(tp, 0x16, 0x8007);
3687
3688 /* SW reset */
3689 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3690
3691 /* Wait for reset to complete. */
3692 /* XXX schedule_timeout() ... */
3693 for (i = 0; i < 500; i++)
3694 udelay(10);
3695
3696 /* Config mode; select PMA/Ch 1 regs. */
3697 tg3_writephy(tp, 0x10, 0x8411);
3698
3699 /* Enable auto-lock and comdet, select txclk for tx. */
3700 tg3_writephy(tp, 0x11, 0x0a10);
3701
3702 tg3_writephy(tp, 0x18, 0x00a0);
3703 tg3_writephy(tp, 0x16, 0x41ff);
3704
3705 /* Assert and deassert POR. */
3706 tg3_writephy(tp, 0x13, 0x0400);
3707 udelay(40);
3708 tg3_writephy(tp, 0x13, 0x0000);
3709
3710 tg3_writephy(tp, 0x11, 0x0a50);
3711 udelay(40);
3712 tg3_writephy(tp, 0x11, 0x0a10);
3713
3714 /* Wait for signal to stabilize */
3715 /* XXX schedule_timeout() ... */
3716 for (i = 0; i < 15000; i++)
3717 udelay(10);
3718
3719 /* Deselect the channel register so we can read the PHYID
3720 * later.
3721 */
3722 tg3_writephy(tp, 0x10, 0x8011);
3723}
3724
3725static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3726{
82cd3d11 3727 u16 flowctrl;
1da177e4
LT		 3728 u32 sg_dig_ctrl, sg_dig_status;
3729 u32 serdes_cfg, expected_sg_dig_ctrl;
3730 int workaround, port_a;
3731 int current_link_up;
3732
3733 serdes_cfg = 0;
3734 expected_sg_dig_ctrl = 0;
3735 workaround = 0;
3736 port_a = 1;
3737 current_link_up = 0;
3738
3739 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3740 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3741 workaround = 1;
3742 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3743 port_a = 0;
3744
3745 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3746 /* preserve bits 20-23 for voltage regulator */
3747 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3748 }
3749
3750 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3751
3752 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3753 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3754 if (workaround) {
3755 u32 val = serdes_cfg;
3756
3757 if (port_a)
3758 val |= 0xc010000;
3759 else
3760 val |= 0x4010000;
3761 tw32_f(MAC_SERDES_CFG, val);
3762 }
c98f6e3b
MC		 3763
3764 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3765 }
3766 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3767 tg3_setup_flow_control(tp, 0, 0);
3768 current_link_up = 1;
3769 }
3770 goto out;
3771 }
3772
3773 /* Want auto-negotiation. */
c98f6e3b 3774 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3775
82cd3d11
MC		 3776 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3777 if (flowctrl & ADVERTISE_1000XPAUSE)
3778 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3779 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3780 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3781
3782 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3783 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3784 tp->serdes_counter &&
3785 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3786 MAC_STATUS_RCVD_CFG)) ==
3787 MAC_STATUS_PCS_SYNCED)) {
3788 tp->serdes_counter--;
3789 current_link_up = 1;
3790 goto out;
3791 }
3792restart_autoneg:
1da177e4
LT		 3793 if (workaround)
3794 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3795 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3796 udelay(5);
3797 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3798
3d3ebe74
MC		 3799 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3800 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3801 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3802 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3803 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3804 mac_status = tr32(MAC_STATUS);
3805
c98f6e3b 3806 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3807 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3808 u32 local_adv = 0, remote_adv = 0;
3809
3810 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3811 local_adv |= ADVERTISE_1000XPAUSE;
3812 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3813 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3814
c98f6e3b 3815 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3816 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3817 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3818 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3819
3820 tg3_setup_flow_control(tp, local_adv, remote_adv);
3821 current_link_up = 1;
3d3ebe74
MC		 3822 tp->serdes_counter = 0;
3823 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3824 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3825 if (tp->serdes_counter)
3826 tp->serdes_counter--;
1da177e4
LT		 3827 else {
3828 if (workaround) {
3829 u32 val = serdes_cfg;
3830
3831 if (port_a)
3832 val |= 0xc010000;
3833 else
3834 val |= 0x4010000;
3835
3836 tw32_f(MAC_SERDES_CFG, val);
3837 }
3838
c98f6e3b 3839 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3840 udelay(40);
3841
3842 /* Link parallel detection - link is up */
3843 /* only if we have PCS_SYNC and not */
3844 /* receiving config code words */
3845 mac_status = tr32(MAC_STATUS);
3846 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3847 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3848 tg3_setup_flow_control(tp, 0, 0);
3849 current_link_up = 1;
3d3ebe74
MC		 3850 tp->tg3_flags2 |=
3851 TG3_FLG2_PARALLEL_DETECT;
3852 tp->serdes_counter =
3853 SERDES_PARALLEL_DET_TIMEOUT;
3854 } else
3855 goto restart_autoneg;
1da177e4
LT		 3856 }
3857 }
3d3ebe74
MC		 3858 } else {
3859 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3860 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3861 }
3862
3863out:
3864 return current_link_up;
3865}
3866
3867static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3868{
3869 int current_link_up = 0;
3870
5cf64b8a 3871 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3872 goto out;
1da177e4
LT		 3873
3874 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3875 u32 txflags, rxflags;
1da177e4 3876 int i;
6aa20a22 3877
5be73b47
MC		 3878 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3879 u32 local_adv = 0, remote_adv = 0;
1da177e4 3880
5be73b47
MC		 3881 if (txflags & ANEG_CFG_PS1)
3882 local_adv |= ADVERTISE_1000XPAUSE;
3883 if (txflags & ANEG_CFG_PS2)
3884 local_adv |= ADVERTISE_1000XPSE_ASYM;
3885
3886 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3887 remote_adv |= LPA_1000XPAUSE;
3888 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3889 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3890
3891 tg3_setup_flow_control(tp, local_adv, remote_adv);
3892
1da177e4
LT		 3893 current_link_up = 1;
3894 }
3895 for (i = 0; i < 30; i++) {
3896 udelay(20);
3897 tw32_f(MAC_STATUS,
3898 (MAC_STATUS_SYNC_CHANGED |
3899 MAC_STATUS_CFG_CHANGED));
3900 udelay(40);
3901 if ((tr32(MAC_STATUS) &
3902 (MAC_STATUS_SYNC_CHANGED |
3903 MAC_STATUS_CFG_CHANGED)) == 0)
3904 break;
3905 }
3906
3907 mac_status = tr32(MAC_STATUS);
3908 if (current_link_up == 0 &&
3909 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3910 !(mac_status & MAC_STATUS_RCVD_CFG))
3911 current_link_up = 1;
3912 } else {
5be73b47
MC		 3913 tg3_setup_flow_control(tp, 0, 0);
3914
1da177e4
LT		 3915 /* Forcing 1000FD link up. */
3916 current_link_up = 1;
1da177e4
LT		 3917
3918 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3919 udelay(40);
e8f3f6ca
MC		 3920
3921 tw32_f(MAC_MODE, tp->mac_mode);
3922 udelay(40);
1da177e4
LT		 3923 }
3924
3925out:
3926 return current_link_up;
3927}
3928
3929static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3930{
3931 u32 orig_pause_cfg;
3932 u16 orig_active_speed;
3933 u8 orig_active_duplex;
3934 u32 mac_status;
3935 int current_link_up;
3936 int i;
3937
8d018621 3938 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3939 orig_active_speed = tp->link_config.active_speed;
3940 orig_active_duplex = tp->link_config.active_duplex;
3941
3942 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3943 netif_carrier_ok(tp->dev) &&
3944 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3945 mac_status = tr32(MAC_STATUS);
3946 mac_status &= (MAC_STATUS_PCS_SYNCED |
3947 MAC_STATUS_SIGNAL_DET |
3948 MAC_STATUS_CFG_CHANGED |
3949 MAC_STATUS_RCVD_CFG);
3950 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3951 MAC_STATUS_SIGNAL_DET)) {
3952 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3953 MAC_STATUS_CFG_CHANGED));
3954 return 0;
3955 }
3956 }
3957
3958 tw32_f(MAC_TX_AUTO_NEG, 0);
3959
3960 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3961 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3962 tw32_f(MAC_MODE, tp->mac_mode);
3963 udelay(40);
3964
79eb6904 3965 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 3966 tg3_init_bcm8002(tp);
3967
3968 /* Enable link change event even when serdes polling. */
3969 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3970 udelay(40);
3971
3972 current_link_up = 0;
3973 mac_status = tr32(MAC_STATUS);
3974
3975 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3976 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3977 else
3978 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3979
898a56f8 3980 tp->napi[0].hw_status->status =
1da177e4 3981 (SD_STATUS_UPDATED |
898a56f8 3982 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3983
3984 for (i = 0; i < 100; i++) {
3985 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3986 MAC_STATUS_CFG_CHANGED));
3987 udelay(5);
3988 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3989 MAC_STATUS_CFG_CHANGED |
3990 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3991 break;
3992 }
3993
3994 mac_status = tr32(MAC_STATUS);
3995 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3996 current_link_up = 0;
3d3ebe74
MC		 3997 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3998 tp->serdes_counter == 0) {
1da177e4
LT		 3999 tw32_f(MAC_MODE, (tp->mac_mode |
4000 MAC_MODE_SEND_CONFIGS));
4001 udelay(1);
4002 tw32_f(MAC_MODE, tp->mac_mode);
4003 }
4004 }
4005
4006 if (current_link_up == 1) {
4007 tp->link_config.active_speed = SPEED_1000;
4008 tp->link_config.active_duplex = DUPLEX_FULL;
4009 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4010 LED_CTRL_LNKLED_OVERRIDE |
4011 LED_CTRL_1000MBPS_ON));
4012 } else {
4013 tp->link_config.active_speed = SPEED_INVALID;
4014 tp->link_config.active_duplex = DUPLEX_INVALID;
4015 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016 LED_CTRL_LNKLED_OVERRIDE |
4017 LED_CTRL_TRAFFIC_OVERRIDE));
4018 }
4019
4020 if (current_link_up != netif_carrier_ok(tp->dev)) {
4021 if (current_link_up)
4022 netif_carrier_on(tp->dev);
4023 else
4024 netif_carrier_off(tp->dev);
4025 tg3_link_report(tp);
4026 } else {
8d018621 4027 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4028 if (orig_pause_cfg != now_pause_cfg ||
4029 orig_active_speed != tp->link_config.active_speed ||
4030 orig_active_duplex != tp->link_config.active_duplex)
4031 tg3_link_report(tp);
4032 }
4033
4034 return 0;
4035}
4036
747e8f8b
MC		 4037static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4038{
4039 int current_link_up, err = 0;
4040 u32 bmsr, bmcr;
4041 u16 current_speed;
4042 u8 current_duplex;
ef167e27 4043 u32 local_adv, remote_adv;
747e8f8b
MC		 4044
4045 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4046 tw32_f(MAC_MODE, tp->mac_mode);
4047 udelay(40);
4048
4049 tw32(MAC_EVENT, 0);
4050
4051 tw32_f(MAC_STATUS,
4052 (MAC_STATUS_SYNC_CHANGED |
4053 MAC_STATUS_CFG_CHANGED |
4054 MAC_STATUS_MI_COMPLETION |
4055 MAC_STATUS_LNKSTATE_CHANGED));
4056 udelay(40);
4057
4058 if (force_reset)
4059 tg3_phy_reset(tp);
4060
4061 current_link_up = 0;
4062 current_speed = SPEED_INVALID;
4063 current_duplex = DUPLEX_INVALID;
4064
4065 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4066 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4068 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4069 bmsr |= BMSR_LSTATUS;
4070 else
4071 bmsr &= ~BMSR_LSTATUS;
4072 }
747e8f8b
MC		 4073
4074 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4075
4076 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4077 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4078 /* do nothing, just check for link up at the end */
4079 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4080 u32 adv, new_adv;
4081
4082 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4083 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4084 ADVERTISE_1000XPAUSE |
4085 ADVERTISE_1000XPSE_ASYM |
4086 ADVERTISE_SLCT);
4087
ba4d07a8 4088 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4089
4090 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4091 new_adv |= ADVERTISE_1000XHALF;
4092 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4093 new_adv |= ADVERTISE_1000XFULL;
4094
4095 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4096 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4097 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4098 tg3_writephy(tp, MII_BMCR, bmcr);
4099
4100 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4101 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4102 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4103
4104 return err;
4105 }
4106 } else {
4107 u32 new_bmcr;
4108
4109 bmcr &= ~BMCR_SPEED1000;
4110 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4111
4112 if (tp->link_config.duplex == DUPLEX_FULL)
4113 new_bmcr |= BMCR_FULLDPLX;
4114
4115 if (new_bmcr != bmcr) {
4116 /* BMCR_SPEED1000 is a reserved bit that needs
4117 * to be set on write.
4118 */
4119 new_bmcr |= BMCR_SPEED1000;
4120
4121 /* Force a linkdown */
4122 if (netif_carrier_ok(tp->dev)) {
4123 u32 adv;
4124
4125 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4126 adv &= ~(ADVERTISE_1000XFULL |
4127 ADVERTISE_1000XHALF |
4128 ADVERTISE_SLCT);
4129 tg3_writephy(tp, MII_ADVERTISE, adv);
4130 tg3_writephy(tp, MII_BMCR, bmcr |
4131 BMCR_ANRESTART |
4132 BMCR_ANENABLE);
4133 udelay(10);
4134 netif_carrier_off(tp->dev);
4135 }
4136 tg3_writephy(tp, MII_BMCR, new_bmcr);
4137 bmcr = new_bmcr;
4138 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4139 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4140 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4141 ASIC_REV_5714) {
4142 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4143 bmsr |= BMSR_LSTATUS;
4144 else
4145 bmsr &= ~BMSR_LSTATUS;
4146 }
747e8f8b
MC		 4147 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4148 }
4149 }
4150
4151 if (bmsr & BMSR_LSTATUS) {
4152 current_speed = SPEED_1000;
4153 current_link_up = 1;
4154 if (bmcr & BMCR_FULLDPLX)
4155 current_duplex = DUPLEX_FULL;
4156 else
4157 current_duplex = DUPLEX_HALF;
4158
ef167e27
MC		 4159 local_adv = 0;
4160 remote_adv = 0;
4161
747e8f8b 4162 if (bmcr & BMCR_ANENABLE) {
ef167e27 4163 u32 common;
747e8f8b
MC		 4164
4165 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4166 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4167 common = local_adv & remote_adv;
4168 if (common & (ADVERTISE_1000XHALF |
4169 ADVERTISE_1000XFULL)) {
4170 if (common & ADVERTISE_1000XFULL)
4171 current_duplex = DUPLEX_FULL;
4172 else
4173 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4174 }
4175 else
4176 current_link_up = 0;
4177 }
4178 }
4179
ef167e27
MC		 4180 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4181 tg3_setup_flow_control(tp, local_adv, remote_adv);
4182
747e8f8b
MC		 4183 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4184 if (tp->link_config.active_duplex == DUPLEX_HALF)
4185 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4186
4187 tw32_f(MAC_MODE, tp->mac_mode);
4188 udelay(40);
4189
4190 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4191
4192 tp->link_config.active_speed = current_speed;
4193 tp->link_config.active_duplex = current_duplex;
4194
4195 if (current_link_up != netif_carrier_ok(tp->dev)) {
4196 if (current_link_up)
4197 netif_carrier_on(tp->dev);
4198 else {
4199 netif_carrier_off(tp->dev);
4200 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4201 }
4202 tg3_link_report(tp);
4203 }
4204 return err;
4205}
4206
4207static void tg3_serdes_parallel_detect(struct tg3 *tp)
4208{
3d3ebe74 4209 if (tp->serdes_counter) {
747e8f8b 4210 /* Give autoneg time to complete. */
3d3ebe74 4211 tp->serdes_counter--;
747e8f8b
MC		 4212 return;
4213 }
4214 if (!netif_carrier_ok(tp->dev) &&
4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4216 u32 bmcr;
4217
4218 tg3_readphy(tp, MII_BMCR, &bmcr);
4219 if (bmcr & BMCR_ANENABLE) {
4220 u32 phy1, phy2;
4221
4222 /* Select shadow register 0x1f */
4223 tg3_writephy(tp, 0x1c, 0x7c00);
4224 tg3_readphy(tp, 0x1c, &phy1);
4225
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp, 0x17, 0x0f01);
4228 tg3_readphy(tp, 0x15, &phy2);
4229 tg3_readphy(tp, 0x15, &phy2);
4230
4231 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4232 /* We have signal detect and not receiving
4233 * config code words, link is up by parallel
4234 * detection.
4235 */
4236
4237 bmcr &= ~BMCR_ANENABLE;
4238 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4239 tg3_writephy(tp, MII_BMCR, bmcr);
4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4241 }
4242 }
4243 }
4244 else if (netif_carrier_ok(tp->dev) &&
4245 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4246 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4247 u32 phy2;
4248
4249 /* Select expansion interrupt status register */
4250 tg3_writephy(tp, 0x17, 0x0f01);
4251 tg3_readphy(tp, 0x15, &phy2);
4252 if (phy2 & 0x20) {
4253 u32 bmcr;
4254
4255 /* Config code words received, turn on autoneg. */
4256 tg3_readphy(tp, MII_BMCR, &bmcr);
4257 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4258
4259 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4260
4261 }
4262 }
4263}
4264
1da177e4
LT		 4265static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4266{
4267 int err;
4268
4269 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4270 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4271 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4272 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4273 } else {
4274 err = tg3_setup_copper_phy(tp, force_reset);
4275 }
4276
bcb37f6c 4277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4278 u32 val, scale;
4279
4280 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4281 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4282 scale = 65;
4283 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4284 scale = 6;
4285 else
4286 scale = 12;
4287
4288 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4289 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4290 tw32(GRC_MISC_CFG, val);
4291 }
4292
1da177e4
LT		 4293 if (tp->link_config.active_speed == SPEED_1000 &&
4294 tp->link_config.active_duplex == DUPLEX_HALF)
4295 tw32(MAC_TX_LENGTHS,
4296 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4297 (6 << TX_LENGTHS_IPG_SHIFT) |
4298 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4299 else
4300 tw32(MAC_TX_LENGTHS,
4301 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4302 (6 << TX_LENGTHS_IPG_SHIFT) |
4303 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4304
4305 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4306 if (netif_carrier_ok(tp->dev)) {
4307 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4308 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4309 } else {
4310 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4311 }
4312 }
4313
8ed5d97e
MC		 4314 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4315 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4316 if (!netif_carrier_ok(tp->dev))
4317 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4318 tp->pwrmgmt_thresh;
4319 else
4320 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4321 tw32(PCIE_PWR_MGMT_THRESH, val);
4322 }
4323
1da177e4
LT		 4324 return err;
4325}
4326
df3e6548
MC		 4327/* This is called whenever we suspect that the system chipset is re-
4328 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4329 * is bogus tx completions. We try to recover by setting the
4330 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4331 * in the workqueue.
4332 */
4333static void tg3_tx_recover(struct tg3 *tp)
4334{
4335 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4336 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4337
05dbe005
JP		 4338 netdev_warn(tp->dev, "The system may be re-ordering memory-mapped I/O cycles to the network device, attempting to recover\n"
4339 "Please report the problem to the driver maintainer and include system chipset information.\n");
df3e6548
MC		 4340
4341 spin_lock(&tp->lock);
df3e6548 4342 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4343 spin_unlock(&tp->lock);
4344}
4345
f3f3f27e 4346static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4347{
4348 smp_mb();
f3f3f27e
MC		 4349 return tnapi->tx_pending -
4350 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4351}
4352
1da177e4
LT		 4353/* Tigon3 never reports partial packet sends. So we do not
4354 * need special logic to handle SKBs that have not had all
4355 * of their frags sent yet, like SunGEM does.
4356 */
17375d25 4357static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4358{
17375d25 4359 struct tg3 *tp = tnapi->tp;
898a56f8 4360 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4361 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4362 struct netdev_queue *txq;
4363 int index = tnapi - tp->napi;
4364
19cfaecc 4365 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4366 index--;
4367
4368 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4369
4370 while (sw_idx != hw_idx) {
f4188d8a 4371 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4372 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4373 int i, tx_bug = 0;
4374
4375 if (unlikely(skb == NULL)) {
4376 tg3_tx_recover(tp);
4377 return;
4378 }
1da177e4 4379
f4188d8a
AD		 4380 pci_unmap_single(tp->pdev,
4381 pci_unmap_addr(ri, mapping),
4382 skb_headlen(skb),
4383 PCI_DMA_TODEVICE);
1da177e4
LT		 4384
4385 ri->skb = NULL;
4386
4387 sw_idx = NEXT_TX(sw_idx);
4388
4389 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4390 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4391 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4392 tx_bug = 1;
f4188d8a
AD		 4393
4394 pci_unmap_page(tp->pdev,
4395 pci_unmap_addr(ri, mapping),
4396 skb_shinfo(skb)->frags[i].size,
4397 PCI_DMA_TODEVICE);
1da177e4
LT		 4398 sw_idx = NEXT_TX(sw_idx);
4399 }
4400
f47c11ee 4401 dev_kfree_skb(skb);
df3e6548
MC		 4402
4403 if (unlikely(tx_bug)) {
4404 tg3_tx_recover(tp);
4405 return;
4406 }
1da177e4
LT		 4407 }
4408
f3f3f27e 4409 tnapi->tx_cons = sw_idx;
1da177e4 4410
1b2a7205
MC		 4411 /* Need to make the tx_cons update visible to tg3_start_xmit()
4412 * before checking for netif_queue_stopped(). Without the
4413 * memory barrier, there is a small possibility that tg3_start_xmit()
4414 * will miss it and cause the queue to be stopped forever.
4415 */
4416 smp_mb();
4417
fe5f5787 4418 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4419 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4420 __netif_tx_lock(txq, smp_processor_id());
4421 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4422 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4423 netif_tx_wake_queue(txq);
4424 __netif_tx_unlock(txq);
51b91468 4425 }
1da177e4
LT		 4426}
4427
2b2cdb65
MC		 4428static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4429{
4430 if (!ri->skb)
4431 return;
4432
4433 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4434 map_sz, PCI_DMA_FROMDEVICE);
4435 dev_kfree_skb_any(ri->skb);
4436 ri->skb = NULL;
4437}
4438
1da177e4
LT		 4439/* Returns size of skb allocated or < 0 on error.
4440 *
4441 * We only need to fill in the address because the other members
4442 * of the RX descriptor are invariant, see tg3_init_rings.
4443 *
4444 * Note the purposeful assymetry of cpu vs. chip accesses. For
4445 * posting buffers we only dirty the first cache line of the RX
4446 * descriptor (containing the address). Whereas for the RX status
4447 * buffers the cpu only reads the last cacheline of the RX descriptor
4448 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4449 */
86b21e59 4450static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4451 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4452{
4453 struct tg3_rx_buffer_desc *desc;
4454 struct ring_info *map, *src_map;
4455 struct sk_buff *skb;
4456 dma_addr_t mapping;
4457 int skb_size, dest_idx;
4458
4459 src_map = NULL;
4460 switch (opaque_key) {
4461 case RXD_OPAQUE_RING_STD:
4462 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4463 desc = &tpr->rx_std[dest_idx];
4464 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4465 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4466 break;
4467
4468 case RXD_OPAQUE_RING_JUMBO:
4469 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4470 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4471 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4472 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4473 break;
4474
4475 default:
4476 return -EINVAL;
855e1111 4477 }
1da177e4
LT		 4478
4479 /* Do not overwrite any of the map or rp information
4480 * until we are sure we can commit to a new buffer.
4481 *
4482 * Callers depend upon this behavior and assume that
4483 * we leave everything unchanged if we fail.
4484 */
287be12e 4485 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4486 if (skb == NULL)
4487 return -ENOMEM;
4488
1da177e4
LT		 4489 skb_reserve(skb, tp->rx_offset);
4490
287be12e 4491 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4492 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4493 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4494 dev_kfree_skb(skb);
4495 return -EIO;
4496 }
1da177e4
LT		 4497
4498 map->skb = skb;
4499 pci_unmap_addr_set(map, mapping, mapping);
4500
1da177e4
LT		 4501 desc->addr_hi = ((u64)mapping >> 32);
4502 desc->addr_lo = ((u64)mapping & 0xffffffff);
4503
4504 return skb_size;
4505}
4506
4507/* We only need to move over in the address because the other
4508 * members of the RX descriptor are invariant. See notes above
4509 * tg3_alloc_rx_skb for full details.
4510 */
a3896167
MC		 4511static void tg3_recycle_rx(struct tg3_napi *tnapi,
4512 struct tg3_rx_prodring_set *dpr,
4513 u32 opaque_key, int src_idx,
4514 u32 dest_idx_unmasked)
1da177e4 4515{
17375d25 4516 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4517 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4518 struct ring_info *src_map, *dest_map;
4519 int dest_idx;
a3896167 4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4521
4522 switch (opaque_key) {
4523 case RXD_OPAQUE_RING_STD:
4524 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4525 dest_desc = &dpr->rx_std[dest_idx];
4526 dest_map = &dpr->rx_std_buffers[dest_idx];
4527 src_desc = &spr->rx_std[src_idx];
4528 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4529 break;
4530
4531 case RXD_OPAQUE_RING_JUMBO:
4532 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4533 dest_desc = &dpr->rx_jmb[dest_idx].std;
4534 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4535 src_desc = &spr->rx_jmb[src_idx].std;
4536 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4537 break;
4538
4539 default:
4540 return;
855e1111 4541 }
1da177e4
LT		 4542
4543 dest_map->skb = src_map->skb;
4544 pci_unmap_addr_set(dest_map, mapping,
4545 pci_unmap_addr(src_map, mapping));
4546 dest_desc->addr_hi = src_desc->addr_hi;
4547 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 4548
4549 /* Ensure that the update to the skb happens after the physical
4550 * addresses have been transferred to the new BD location.
4551 */
4552 smp_wmb();
4553
1da177e4
LT		 4554 src_map->skb = NULL;
4555}
4556
1da177e4
LT		 4557/* The RX ring scheme is composed of multiple rings which post fresh
4558 * buffers to the chip, and one special ring the chip uses to report
4559 * status back to the host.
4560 *
4561 * The special ring reports the status of received packets to the
4562 * host. The chip does not write into the original descriptor the
4563 * RX buffer was obtained from. The chip simply takes the original
4564 * descriptor as provided by the host, updates the status and length
4565 * field, then writes this into the next status ring entry.
4566 *
4567 * Each ring the host uses to post buffers to the chip is described
4568 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4569 * it is first placed into the on-chip ram. When the packet's length
4570 * is known, it walks down the TG3_BDINFO entries to select the ring.
4571 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4572 * which is within the range of the new packet's length is chosen.
4573 *
4574 * The "separate ring for rx status" scheme may sound queer, but it makes
4575 * sense from a cache coherency perspective. If only the host writes
4576 * to the buffer post rings, and only the chip writes to the rx status
4577 * rings, then cache lines never move beyond shared-modified state.
4578 * If both the host and chip were to write into the same ring, cache line
4579 * eviction could occur since both entities want it in an exclusive state.
4580 */
17375d25 4581static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4582{
17375d25 4583 struct tg3 *tp = tnapi->tp;
f92905de 4584 u32 work_mask, rx_std_posted = 0;
4361935a 4585 u32 std_prod_idx, jmb_prod_idx;
72334482 4586 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4587 u16 hw_idx;
1da177e4 4588 int received;
b196c7e4 4589 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4590
8d9d7cfc 4591 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4592 /*
4593 * We need to order the read of hw_idx and the read of
4594 * the opaque cookie.
4595 */
4596 rmb();
1da177e4
LT		 4597 work_mask = 0;
4598 received = 0;
4361935a
MC		 4599 std_prod_idx = tpr->rx_std_prod_idx;
4600 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4601 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4602 struct ring_info *ri;
72334482 4603 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4604 unsigned int len;
4605 struct sk_buff *skb;
4606 dma_addr_t dma_addr;
4607 u32 opaque_key, desc_idx, *post_ptr;
4608
4609 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4610 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4611 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4612 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4613 dma_addr = pci_unmap_addr(ri, mapping);
4614 skb = ri->skb;
4361935a 4615 post_ptr = &std_prod_idx;
f92905de 4616 rx_std_posted++;
1da177e4 4617 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4618 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4619 dma_addr = pci_unmap_addr(ri, mapping);
4620 skb = ri->skb;
4361935a 4621 post_ptr = &jmb_prod_idx;
21f581a5 4622 } else
1da177e4 4623 goto next_pkt_nopost;
1da177e4
LT		 4624
4625 work_mask |= opaque_key;
4626
4627 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4628 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4629 drop_it:
a3896167 4630 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4631 desc_idx, *post_ptr);
4632 drop_it_no_recycle:
4633 /* Other statistics kept track of by card. */
4634 tp->net_stats.rx_dropped++;
4635 goto next_pkt;
4636 }
4637
ad829268
MC		 4638 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4639 ETH_FCS_LEN;
1da177e4 4640
8e95a202
JP		 4641 if (len > RX_COPY_THRESHOLD &&
4642 tp->rx_offset == NET_IP_ALIGN) {
4643 /* rx_offset will likely not equal NET_IP_ALIGN
4644 * if this is a 5701 card running in PCI-X mode
4645 * [see tg3_get_invariants()]
4646 */
1da177e4
LT		 4647 int skb_size;
4648
86b21e59 4649 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4650 *post_ptr);
1da177e4
LT		 4651 if (skb_size < 0)
4652 goto drop_it;
4653
287be12e 4654 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4655 PCI_DMA_FROMDEVICE);
4656
61e800cf
MC		 4657 /* Ensure that the update to the skb happens
4658 * after the usage of the old DMA mapping.
4659 */
4660 smp_wmb();
4661
4662 ri->skb = NULL;
4663
1da177e4
LT		 4664 skb_put(skb, len);
4665 } else {
4666 struct sk_buff *copy_skb;
4667
a3896167 4668 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4669 desc_idx, *post_ptr);
4670
ad829268
MC		 4671 copy_skb = netdev_alloc_skb(tp->dev,
4672 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4673 if (copy_skb == NULL)
4674 goto drop_it_no_recycle;
4675
ad829268 4676 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4677 skb_put(copy_skb, len);
4678 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4679 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4680 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4681
4682 /* We'll reuse the original ring buffer. */
4683 skb = copy_skb;
4684 }
4685
4686 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4687 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4688 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4689 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4690 skb->ip_summed = CHECKSUM_UNNECESSARY;
4691 else
4692 skb->ip_summed = CHECKSUM_NONE;
4693
4694 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4695
4696 if (len > (tp->dev->mtu + ETH_HLEN) &&
4697 skb->protocol != htons(ETH_P_8021Q)) {
4698 dev_kfree_skb(skb);
4699 goto next_pkt;
4700 }
4701
1da177e4
LT		 4702#if TG3_VLAN_TAG_USED
4703 if (tp->vlgrp != NULL &&
4704 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4705 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4706 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4707 } else
4708#endif
17375d25 4709 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4710
1da177e4
LT		 4711 received++;
4712 budget--;
4713
4714next_pkt:
4715 (*post_ptr)++;
f92905de
MC		 4716
4717 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4718 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4719 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4720 tpr->rx_std_prod_idx);
f92905de
MC		 4721 work_mask &= ~RXD_OPAQUE_RING_STD;
4722 rx_std_posted = 0;
4723 }
1da177e4 4724next_pkt_nopost:
483ba50b 4725 sw_idx++;
6b31a515 4726 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4727
4728 /* Refresh hw_idx to see if there is new work */
4729 if (sw_idx == hw_idx) {
8d9d7cfc 4730 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4731 rmb();
4732 }
1da177e4
LT		 4733 }
4734
4735 /* ACK the status ring. */
72334482
MC		 4736 tnapi->rx_rcb_ptr = sw_idx;
4737 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4738
4739 /* Refill RX ring(s). */
e4af1af9 4740 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
b196c7e4
MC		 4741 if (work_mask & RXD_OPAQUE_RING_STD) {
4742 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4744 tpr->rx_std_prod_idx);
4745 }
4746 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4747 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4748 TG3_RX_JUMBO_RING_SIZE;
4749 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4750 tpr->rx_jmb_prod_idx);
4751 }
4752 mmiowb();
4753 } else if (work_mask) {
4754 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4755 * updated before the producer indices can be updated.
4756 */
4757 smp_wmb();
4758
4361935a 4759 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4760 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4 4761
e4af1af9
MC		 4762 if (tnapi != &tp->napi[1])
4763 napi_schedule(&tp->napi[1].napi);
1da177e4 4764 }
1da177e4
LT		 4765
4766 return received;
4767}
4768
35f2d7d0 4769static void tg3_poll_link(struct tg3 *tp)
1da177e4 4770{
1da177e4
LT		 4771 /* handle link change and other phy events */
4772 if (!(tp->tg3_flags &
4773 (TG3_FLAG_USE_LINKCHG_REG |
4774 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4775 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4776
1da177e4
LT		 4777 if (sblk->status & SD_STATUS_LINK_CHG) {
4778 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4779 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4780 spin_lock(&tp->lock);
dd477003
MC		 4781 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4782 tw32_f(MAC_STATUS,
4783 (MAC_STATUS_SYNC_CHANGED |
4784 MAC_STATUS_CFG_CHANGED |
4785 MAC_STATUS_MI_COMPLETION |
4786 MAC_STATUS_LNKSTATE_CHANGED));
4787 udelay(40);
4788 } else
4789 tg3_setup_phy(tp, 0);
f47c11ee 4790 spin_unlock(&tp->lock);
1da177e4
LT		 4791 }
4792 }
35f2d7d0
MC		 4793}
4794
f89f38b8
MC		 4795static int tg3_rx_prodring_xfer(struct tg3 *tp,
4796 struct tg3_rx_prodring_set *dpr,
4797 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 4798{
4799 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 4800 int i, err = 0;
b196c7e4
MC		 4801
4802 while (1) {
4803 src_prod_idx = spr->rx_std_prod_idx;
4804
4805 /* Make sure updates to the rx_std_buffers[] entries and the
4806 * standard producer index are seen in the correct order.
4807 */
4808 smp_rmb();
4809
4810 if (spr->rx_std_cons_idx == src_prod_idx)
4811 break;
4812
4813 if (spr->rx_std_cons_idx < src_prod_idx)
4814 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4815 else
4816 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4817
4818 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4819
4820 si = spr->rx_std_cons_idx;
4821 di = dpr->rx_std_prod_idx;
4822
e92967bf
MC		 4823 for (i = di; i < di + cpycnt; i++) {
4824 if (dpr->rx_std_buffers[i].skb) {
4825 cpycnt = i - di;
f89f38b8 4826 err = -ENOSPC;
e92967bf
MC		 4827 break;
4828 }
4829 }
4830
4831 if (!cpycnt)
4832 break;
4833
4834 /* Ensure that updates to the rx_std_buffers ring and the
4835 * shadowed hardware producer ring from tg3_recycle_skb() are
4836 * ordered correctly WRT the skb check above.
4837 */
4838 smp_rmb();
4839
b196c7e4
MC		 4840 memcpy(&dpr->rx_std_buffers[di],
4841 &spr->rx_std_buffers[si],
4842 cpycnt * sizeof(struct ring_info));
4843
4844 for (i = 0; i < cpycnt; i++, di++, si++) {
4845 struct tg3_rx_buffer_desc *sbd, *dbd;
4846 sbd = &spr->rx_std[si];
4847 dbd = &dpr->rx_std[di];
4848 dbd->addr_hi = sbd->addr_hi;
4849 dbd->addr_lo = sbd->addr_lo;
4850 }
4851
4852 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4853 TG3_RX_RING_SIZE;
4854 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4855 TG3_RX_RING_SIZE;
4856 }
4857
4858 while (1) {
4859 src_prod_idx = spr->rx_jmb_prod_idx;
4860
4861 /* Make sure updates to the rx_jmb_buffers[] entries and
4862 * the jumbo producer index are seen in the correct order.
4863 */
4864 smp_rmb();
4865
4866 if (spr->rx_jmb_cons_idx == src_prod_idx)
4867 break;
4868
4869 if (spr->rx_jmb_cons_idx < src_prod_idx)
4870 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4871 else
4872 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4873
4874 cpycnt = min(cpycnt,
4875 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4876
4877 si = spr->rx_jmb_cons_idx;
4878 di = dpr->rx_jmb_prod_idx;
4879
e92967bf
MC		 4880 for (i = di; i < di + cpycnt; i++) {
4881 if (dpr->rx_jmb_buffers[i].skb) {
4882 cpycnt = i - di;
f89f38b8 4883 err = -ENOSPC;
e92967bf
MC		 4884 break;
4885 }
4886 }
4887
4888 if (!cpycnt)
4889 break;
4890
4891 /* Ensure that updates to the rx_jmb_buffers ring and the
4892 * shadowed hardware producer ring from tg3_recycle_skb() are
4893 * ordered correctly WRT the skb check above.
4894 */
4895 smp_rmb();
4896
b196c7e4
MC		 4897 memcpy(&dpr->rx_jmb_buffers[di],
4898 &spr->rx_jmb_buffers[si],
4899 cpycnt * sizeof(struct ring_info));
4900
4901 for (i = 0; i < cpycnt; i++, di++, si++) {
4902 struct tg3_rx_buffer_desc *sbd, *dbd;
4903 sbd = &spr->rx_jmb[si].std;
4904 dbd = &dpr->rx_jmb[di].std;
4905 dbd->addr_hi = sbd->addr_hi;
4906 dbd->addr_lo = sbd->addr_lo;
4907 }
4908
4909 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4910 TG3_RX_JUMBO_RING_SIZE;
4911 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4912 TG3_RX_JUMBO_RING_SIZE;
4913 }
f89f38b8
MC		 4914
4915 return err;
b196c7e4
MC		 4916}
4917
35f2d7d0
MC		 4918static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4919{
4920 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4921
4922 /* run TX completion thread */
f3f3f27e 4923 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4924 tg3_tx(tnapi);
6f535763 4925 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4926 return work_done;
1da177e4
LT		 4927 }
4928
1da177e4
LT		 4929 /* run RX thread, within the bounds set by NAPI.
4930 * All RX "locking" is done by ensuring outside
bea3348e 4931 * code synchronizes with tg3->napi.poll()
1da177e4 4932 */
8d9d7cfc 4933 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4934 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4935
b196c7e4 4936 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
e4af1af9 4937 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
f89f38b8 4938 int i, err = 0;
e4af1af9
MC		 4939 u32 std_prod_idx = dpr->rx_std_prod_idx;
4940 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 4941
e4af1af9 4942 for (i = 1; i < tp->irq_cnt; i++)
f89f38b8
MC		 4943 err |= tg3_rx_prodring_xfer(tp, dpr,
4944 tp->napi[i].prodring);
b196c7e4
MC		 4945
4946 wmb();
4947
e4af1af9
MC		 4948 if (std_prod_idx != dpr->rx_std_prod_idx)
4949 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4950 dpr->rx_std_prod_idx);
b196c7e4 4951
e4af1af9
MC		 4952 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4953 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4954 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 4955
4956 mmiowb();
f89f38b8
MC		 4957
4958 if (err)
4959 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 4960 }
4961
6f535763
DM		 4962 return work_done;
4963}
4964
35f2d7d0
MC		 4965static int tg3_poll_msix(struct napi_struct *napi, int budget)
4966{
4967 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4968 struct tg3 *tp = tnapi->tp;
4969 int work_done = 0;
4970 struct tg3_hw_status *sblk = tnapi->hw_status;
4971
4972 while (1) {
4973 work_done = tg3_poll_work(tnapi, work_done, budget);
4974
4975 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4976 goto tx_recovery;
4977
4978 if (unlikely(work_done >= budget))
4979 break;
4980
4981 /* tp->last_tag is used in tg3_restart_ints() below
4982 * to tell the hw how much work has been processed,
4983 * so we must read it before checking for more work.
4984 */
4985 tnapi->last_tag = sblk->status_tag;
4986 tnapi->last_irq_tag = tnapi->last_tag;
4987 rmb();
4988
4989 /* check for RX/TX work to do */
6d40db7b
MC		 4990 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
35f2d7d0
MC		 4992 napi_complete(napi);
4993 /* Reenable interrupts. */
4994 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4995 mmiowb();
4996 break;
4997 }
4998 }
4999
5000 return work_done;
5001
5002tx_recovery:
5003 /* work_done is guaranteed to be less than budget. */
5004 napi_complete(napi);
5005 schedule_work(&tp->reset_task);
5006 return work_done;
5007}
5008
6f535763
DM		 5009static int tg3_poll(struct napi_struct *napi, int budget)
5010{
8ef0442f
MC		 5011 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5012 struct tg3 *tp = tnapi->tp;
6f535763 5013 int work_done = 0;
898a56f8 5014 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 5015
5016 while (1) {
35f2d7d0
MC		 5017 tg3_poll_link(tp);
5018
17375d25 5019 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 5020
5021 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5022 goto tx_recovery;
5023
5024 if (unlikely(work_done >= budget))
5025 break;
5026
4fd7ab59 5027 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 5028 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 5029 * to tell the hw how much work has been processed,
5030 * so we must read it before checking for more work.
5031 */
898a56f8
MC		 5032 tnapi->last_tag = sblk->status_tag;
5033 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 5034 rmb();
5035 } else
5036 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 5037
17375d25 5038 if (likely(!tg3_has_work(tnapi))) {
288379f0 5039 napi_complete(napi);
17375d25 5040 tg3_int_reenable(tnapi);
6f535763
DM		 5041 break;
5042 }
1da177e4
LT		 5043 }
5044
bea3348e 5045 return work_done;
6f535763
DM		 5046
5047tx_recovery:
4fd7ab59 5048 /* work_done is guaranteed to be less than budget. */
288379f0 5049 napi_complete(napi);
6f535763 5050 schedule_work(&tp->reset_task);
4fd7ab59 5051 return work_done;
1da177e4
LT		 5052}
5053
f47c11ee
DM		 5054static void tg3_irq_quiesce(struct tg3 *tp)
5055{
4f125f42
MC		 5056 int i;
5057
f47c11ee
DM		 5058 BUG_ON(tp->irq_sync);
5059
5060 tp->irq_sync = 1;
5061 smp_mb();
5062
4f125f42
MC		 5063 for (i = 0; i < tp->irq_cnt; i++)
5064 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5065}
5066
5067static inline int tg3_irq_sync(struct tg3 *tp)
5068{
5069 return tp->irq_sync;
5070}
5071
5072/* Fully shutdown all tg3 driver activity elsewhere in the system.
5073 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5074 * with as well. Most of the time, this is not necessary except when
5075 * shutting down the device.
5076 */
5077static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5078{
46966545 5079 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5080 if (irq_sync)
5081 tg3_irq_quiesce(tp);
f47c11ee
DM		 5082}
5083
5084static inline void tg3_full_unlock(struct tg3 *tp)
5085{
f47c11ee
DM		 5086 spin_unlock_bh(&tp->lock);
5087}
5088
fcfa0a32
MC		 5089/* One-shot MSI handler - Chip automatically disables interrupt
5090 * after sending MSI so driver doesn't have to do it.
5091 */
7d12e780 5092static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5093{
09943a18
MC		 5094 struct tg3_napi *tnapi = dev_id;
5095 struct tg3 *tp = tnapi->tp;
fcfa0a32 5096
898a56f8 5097 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5098 if (tnapi->rx_rcb)
5099 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5100
5101 if (likely(!tg3_irq_sync(tp)))
09943a18 5102 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5103
5104 return IRQ_HANDLED;
5105}
5106
88b06bc2
MC		 5107/* MSI ISR - No need to check for interrupt sharing and no need to
5108 * flush status block and interrupt mailbox. PCI ordering rules
5109 * guarantee that MSI will arrive after the status block.
5110 */
7d12e780 5111static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5112{
09943a18
MC		 5113 struct tg3_napi *tnapi = dev_id;
5114 struct tg3 *tp = tnapi->tp;
88b06bc2 5115
898a56f8 5116 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5117 if (tnapi->rx_rcb)
5118 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5119 /*
fac9b83e 5120 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5121 * chip-internal interrupt pending events.
fac9b83e 5122 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5123 * NIC to stop sending us irqs, engaging "in-intr-handler"
5124 * event coalescing.
5125 */
5126 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5127 if (likely(!tg3_irq_sync(tp)))
09943a18 5128 napi_schedule(&tnapi->napi);
61487480 5129
88b06bc2
MC		 5130 return IRQ_RETVAL(1);
5131}
5132
7d12e780 5133static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5134{
09943a18
MC		 5135 struct tg3_napi *tnapi = dev_id;
5136 struct tg3 *tp = tnapi->tp;
898a56f8 5137 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5138 unsigned int handled = 1;
5139
1da177e4
LT		 5140 /* In INTx mode, it is possible for the interrupt to arrive at
5141 * the CPU before the status block posted prior to the interrupt.
5142 * Reading the PCI State register will confirm whether the
5143 * interrupt is ours and will flush the status block.
5144 */
d18edcb2
MC		 5145 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5146 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5147 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5148 handled = 0;
f47c11ee 5149 goto out;
fac9b83e 5150 }
d18edcb2
MC		 5151 }
5152
5153 /*
5154 * Writing any value to intr-mbox-0 clears PCI INTA# and
5155 * chip-internal interrupt pending events.
5156 * Writing non-zero to intr-mbox-0 additional tells the
5157 * NIC to stop sending us irqs, engaging "in-intr-handler"
5158 * event coalescing.
c04cb347
MC		 5159 *
5160 * Flush the mailbox to de-assert the IRQ immediately to prevent
5161 * spurious interrupts. The flush impacts performance but
5162 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5163 */
c04cb347 5164 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5165 if (tg3_irq_sync(tp))
5166 goto out;
5167 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5168 if (likely(tg3_has_work(tnapi))) {
72334482 5169 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5170 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5171 } else {
5172 /* No work, shared interrupt perhaps? re-enable
5173 * interrupts, and flush that PCI write
5174 */
5175 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5176 0x00000000);
fac9b83e 5177 }
f47c11ee 5178out:
fac9b83e
DM		 5179 return IRQ_RETVAL(handled);
5180}
5181
7d12e780 5182static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5183{
09943a18
MC		 5184 struct tg3_napi *tnapi = dev_id;
5185 struct tg3 *tp = tnapi->tp;
898a56f8 5186 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5187 unsigned int handled = 1;
5188
fac9b83e
DM		 5189 /* In INTx mode, it is possible for the interrupt to arrive at
5190 * the CPU before the status block posted prior to the interrupt.
5191 * Reading the PCI State register will confirm whether the
5192 * interrupt is ours and will flush the status block.
5193 */
898a56f8 5194 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5195 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5196 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5197 handled = 0;
f47c11ee 5198 goto out;
1da177e4 5199 }
d18edcb2
MC		 5200 }
5201
5202 /*
5203 * writing any value to intr-mbox-0 clears PCI INTA# and
5204 * chip-internal interrupt pending events.
5205 * writing non-zero to intr-mbox-0 additional tells the
5206 * NIC to stop sending us irqs, engaging "in-intr-handler"
5207 * event coalescing.
c04cb347
MC		 5208 *
5209 * Flush the mailbox to de-assert the IRQ immediately to prevent
5210 * spurious interrupts. The flush impacts performance but
5211 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5212 */
c04cb347 5213 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5214
5215 /*
5216 * In a shared interrupt configuration, sometimes other devices'
5217 * interrupts will scream. We record the current status tag here
5218 * so that the above check can report that the screaming interrupts
5219 * are unhandled. Eventually they will be silenced.
5220 */
898a56f8 5221 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5222
d18edcb2
MC		 5223 if (tg3_irq_sync(tp))
5224 goto out;
624f8e50 5225
72334482 5226 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5227
09943a18 5228 napi_schedule(&tnapi->napi);
624f8e50 5229
f47c11ee 5230out:
1da177e4
LT		 5231 return IRQ_RETVAL(handled);
5232}
5233
7938109f 5234/* ISR for interrupt test */
7d12e780 5235static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5236{
09943a18
MC		 5237 struct tg3_napi *tnapi = dev_id;
5238 struct tg3 *tp = tnapi->tp;
898a56f8 5239 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5240
f9804ddb
MC		 5241 if ((sblk->status & SD_STATUS_UPDATED) ||
5242 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5243 tg3_disable_ints(tp);
7938109f
MC		 5244 return IRQ_RETVAL(1);
5245 }
5246 return IRQ_RETVAL(0);
5247}
5248
8e7a22e3 5249static int tg3_init_hw(struct tg3 *, int);
944d980e 5250static int tg3_halt(struct tg3 *, int, int);
1da177e4 5251
b9ec6c1b
MC		 5252/* Restart hardware after configuration changes, self-test, etc.
5253 * Invoked with tp->lock held.
5254 */
5255static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5256 __releases(tp->lock)
5257 __acquires(tp->lock)
b9ec6c1b
MC		 5258{
5259 int err;
5260
5261 err = tg3_init_hw(tp, reset_phy);
5262 if (err) {
05dbe005 5263 netdev_err(tp->dev, "Failed to re-initialize device, aborting\n");
b9ec6c1b
MC		 5264 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5265 tg3_full_unlock(tp);
5266 del_timer_sync(&tp->timer);
5267 tp->irq_sync = 0;
fed97810 5268 tg3_napi_enable(tp);
b9ec6c1b
MC		 5269 dev_close(tp->dev);
5270 tg3_full_lock(tp, 0);
5271 }
5272 return err;
5273}
5274
1da177e4
LT		 5275#ifdef CONFIG_NET_POLL_CONTROLLER
5276static void tg3_poll_controller(struct net_device *dev)
5277{
4f125f42 5278 int i;
88b06bc2
MC		 5279 struct tg3 *tp = netdev_priv(dev);
5280
4f125f42 5281 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 5282 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 5283}
5284#endif
5285
c4028958 5286static void tg3_reset_task(struct work_struct *work)
1da177e4 5287{
c4028958 5288 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5289 int err;
1da177e4
LT		 5290 unsigned int restart_timer;
5291
7faa006f 5292 tg3_full_lock(tp, 0);
7faa006f
MC		 5293
5294 if (!netif_running(tp->dev)) {
7faa006f
MC		 5295 tg3_full_unlock(tp);
5296 return;
5297 }
5298
5299 tg3_full_unlock(tp);
5300
b02fd9e3
MC		 5301 tg3_phy_stop(tp);
5302
1da177e4
LT		 5303 tg3_netif_stop(tp);
5304
f47c11ee 5305 tg3_full_lock(tp, 1);
1da177e4
LT		 5306
5307 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5308 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5309
df3e6548
MC		 5310 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5311 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5312 tp->write32_rx_mbox = tg3_write_flush_reg32;
5313 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5314 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5315 }
5316
944d980e 5317 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5318 err = tg3_init_hw(tp, 1);
5319 if (err)
b9ec6c1b 5320 goto out;
1da177e4
LT		 5321
5322 tg3_netif_start(tp);
5323
1da177e4
LT		 5324 if (restart_timer)
5325 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5326
b9ec6c1b 5327out:
7faa006f 5328 tg3_full_unlock(tp);
b02fd9e3
MC		 5329
5330 if (!err)
5331 tg3_phy_start(tp);
1da177e4
LT		 5332}
5333
b0408751
MC		 5334static void tg3_dump_short_state(struct tg3 *tp)
5335{
05dbe005
JP		 5336 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5337 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5338 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5339 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
b0408751
MC		 5340}
5341
1da177e4
LT		 5342static void tg3_tx_timeout(struct net_device *dev)
5343{
5344 struct tg3 *tp = netdev_priv(dev);
5345
b0408751 5346 if (netif_msg_tx_err(tp)) {
05dbe005 5347 netdev_err(dev, "transmit timed out, resetting\n");
b0408751
MC		 5348 tg3_dump_short_state(tp);
5349 }
1da177e4
LT		 5350
5351 schedule_work(&tp->reset_task);
5352}
5353
c58ec932
MC		 5354/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5355static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5356{
5357 u32 base = (u32) mapping & 0xffffffff;
5358
5359 return ((base > 0xffffdcc0) &&
5360 (base + len + 8 < base));
5361}
5362
72f2afb8
MC		 5363/* Test for DMA addresses > 40-bit */
5364static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5365 int len)
5366{
5367#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5368 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5369 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5370 return 0;
5371#else
5372 return 0;
5373#endif
5374}
5375
f3f3f27e 5376static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5377
72f2afb8 5378/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5379static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5380 struct sk_buff *skb, u32 last_plus_one,
5381 u32 *start, u32 base_flags, u32 mss)
1da177e4 5382{
24f4efd4 5383 struct tg3 *tp = tnapi->tp;
41588ba1 5384 struct sk_buff *new_skb;
c58ec932 5385 dma_addr_t new_addr = 0;
1da177e4 5386 u32 entry = *start;
c58ec932 5387 int i, ret = 0;
1da177e4 5388
41588ba1
MC		 5389 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5390 new_skb = skb_copy(skb, GFP_ATOMIC);
5391 else {
5392 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5393
5394 new_skb = skb_copy_expand(skb,
5395 skb_headroom(skb) + more_headroom,
5396 skb_tailroom(skb), GFP_ATOMIC);
5397 }
5398
1da177e4 5399 if (!new_skb) {
c58ec932
MC		 5400 ret = -1;
5401 } else {
5402 /* New SKB is guaranteed to be linear. */
5403 entry = *start;
f4188d8a
AD		 5404 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5405 PCI_DMA_TODEVICE);
5406 /* Make sure the mapping succeeded */
5407 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5408 ret = -1;
5409 dev_kfree_skb(new_skb);
5410 new_skb = NULL;
90079ce8 5411
c58ec932
MC		 5412 /* Make sure new skb does not cross any 4G boundaries.
5413 * Drop the packet if it does.
5414 */
f4188d8a
AD		 5415 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5416 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5417 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5418 PCI_DMA_TODEVICE);
c58ec932
MC		 5419 ret = -1;
5420 dev_kfree_skb(new_skb);
5421 new_skb = NULL;
5422 } else {
f3f3f27e 5423 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5424 base_flags, 1 | (mss << 1));
5425 *start = NEXT_TX(entry);
5426 }
1da177e4
LT		 5427 }
5428
1da177e4
LT		 5429 /* Now clean up the sw ring entries. */
5430 i = 0;
5431 while (entry != last_plus_one) {
f4188d8a
AD		 5432 int len;
5433
f3f3f27e 5434 if (i == 0)
f4188d8a 5435 len = skb_headlen(skb);
f3f3f27e 5436 else
f4188d8a
AD		 5437 len = skb_shinfo(skb)->frags[i-1].size;
5438
5439 pci_unmap_single(tp->pdev,
5440 pci_unmap_addr(&tnapi->tx_buffers[entry],
5441 mapping),
5442 len, PCI_DMA_TODEVICE);
5443 if (i == 0) {
5444 tnapi->tx_buffers[entry].skb = new_skb;
5445 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5446 new_addr);
5447 } else {
f3f3f27e 5448 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5449 }
1da177e4
LT		 5450 entry = NEXT_TX(entry);
5451 i++;
5452 }
5453
5454 dev_kfree_skb(skb);
5455
c58ec932 5456 return ret;
1da177e4
LT		 5457}
5458
f3f3f27e 5459static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5460 dma_addr_t mapping, int len, u32 flags,
5461 u32 mss_and_is_end)
5462{
f3f3f27e 5463 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5464 int is_end = (mss_and_is_end & 0x1);
5465 u32 mss = (mss_and_is_end >> 1);
5466 u32 vlan_tag = 0;
5467
5468 if (is_end)
5469 flags |= TXD_FLAG_END;
5470 if (flags & TXD_FLAG_VLAN) {
5471 vlan_tag = flags >> 16;
5472 flags &= 0xffff;
5473 }
5474 vlan_tag |= (mss << TXD_MSS_SHIFT);
5475
5476 txd->addr_hi = ((u64) mapping >> 32);
5477 txd->addr_lo = ((u64) mapping & 0xffffffff);
5478 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5479 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5480}
5481
5a6f3074 5482/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5483 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5484 */
61357325
SH		 5485static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5486 struct net_device *dev)
5a6f3074
MC		 5487{
5488 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5489 u32 len, entry, base_flags, mss;
90079ce8 5490 dma_addr_t mapping;
fe5f5787
MC		 5491 struct tg3_napi *tnapi;
5492 struct netdev_queue *txq;
f4188d8a
AD		 5493 unsigned int i, last;
5494
5a6f3074 5495
fe5f5787
MC		 5496 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5497 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5498 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5499 tnapi++;
5a6f3074 5500
00b70504 5501 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5502 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5503 * interrupt. Furthermore, IRQ processing runs lockless so we have
5504 * no IRQ context deadlocks to worry about either. Rejoice!
5505 */
f3f3f27e 5506 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5507 if (!netif_tx_queue_stopped(txq)) {
5508 netif_tx_stop_queue(txq);
5a6f3074
MC		 5509
5510 /* This is a hard error, log it. */
05dbe005 5511 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5a6f3074 5512 }
5a6f3074
MC		 5513 return NETDEV_TX_BUSY;
5514 }
5515
f3f3f27e 5516 entry = tnapi->tx_prod;
5a6f3074 5517 base_flags = 0;
5a6f3074 5518 mss = 0;
c13e3713 5519 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5520 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5521 u32 hdrlen;
5a6f3074
MC		 5522
5523 if (skb_header_cloned(skb) &&
5524 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5525 dev_kfree_skb(skb);
5526 goto out_unlock;
5527 }
5528
b0026624 5529 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5530 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5531 else {
eddc9ec5
ACM		 5532 struct iphdr *iph = ip_hdr(skb);
5533
ab6a5bb6 5534 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5535 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5536
eddc9ec5
ACM		 5537 iph->check = 0;
5538 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5539 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5540 }
5a6f3074 5541
e849cdc3 5542 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5543 mss |= (hdrlen & 0xc) << 12;
5544 if (hdrlen & 0x10)
5545 base_flags |= 0x00000010;
5546 base_flags |= (hdrlen & 0x3e0) << 5;
5547 } else
5548 mss |= hdrlen << 9;
5549
5a6f3074
MC		 5550 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5551 TXD_FLAG_CPU_POST_DMA);
5552
aa8223c7 5553 tcp_hdr(skb)->check = 0;
5a6f3074 5554
5a6f3074 5555 }
84fa7933 5556 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5557 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5558#if TG3_VLAN_TAG_USED
5559 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5560 base_flags |= (TXD_FLAG_VLAN |
5561 (vlan_tx_tag_get(skb) << 16));
5562#endif
5563
f4188d8a
AD		 5564 len = skb_headlen(skb);
5565
5566 /* Queue skb data, a.k.a. the main skb fragment. */
5567 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5568 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5569 dev_kfree_skb(skb);
5570 goto out_unlock;
5571 }
5572
f3f3f27e 5573 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5574 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5575
b703df6f 5576 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5577 !mss && skb->len > ETH_DATA_LEN)
5578 base_flags |= TXD_FLAG_JMB_PKT;
5579
f3f3f27e 5580 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5581 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5582
5583 entry = NEXT_TX(entry);
5584
5585 /* Now loop through additional data fragments, and queue them. */
5586 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5587 last = skb_shinfo(skb)->nr_frags - 1;
5588 for (i = 0; i <= last; i++) {
5589 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5590
5591 len = frag->size;
f4188d8a
AD		 5592 mapping = pci_map_page(tp->pdev,
5593 frag->page,
5594 frag->page_offset,
5595 len, PCI_DMA_TODEVICE);
5596 if (pci_dma_mapping_error(tp->pdev, mapping))
5597 goto dma_error;
5598
f3f3f27e 5599 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5600 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5601 mapping);
5a6f3074 5602
f3f3f27e 5603 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5604 base_flags, (i == last) | (mss << 1));
5605
5606 entry = NEXT_TX(entry);
5607 }
5608 }
5609
5610 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5611 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5612
f3f3f27e
MC		 5613 tnapi->tx_prod = entry;
5614 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5615 netif_tx_stop_queue(txq);
f3f3f27e 5616 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5617 netif_tx_wake_queue(txq);
5a6f3074
MC		 5618 }
5619
5620out_unlock:
cdd0db05 5621 mmiowb();
5a6f3074
MC		 5622
5623 return NETDEV_TX_OK;
f4188d8a
AD		 5624
5625dma_error:
5626 last = i;
5627 entry = tnapi->tx_prod;
5628 tnapi->tx_buffers[entry].skb = NULL;
5629 pci_unmap_single(tp->pdev,
5630 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5631 skb_headlen(skb),
5632 PCI_DMA_TODEVICE);
5633 for (i = 0; i <= last; i++) {
5634 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5635 entry = NEXT_TX(entry);
5636
5637 pci_unmap_page(tp->pdev,
5638 pci_unmap_addr(&tnapi->tx_buffers[entry],
5639 mapping),
5640 frag->size, PCI_DMA_TODEVICE);
5641 }
5642
5643 dev_kfree_skb(skb);
5644 return NETDEV_TX_OK;
5a6f3074
MC		 5645}
5646
61357325
SH		 5647static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5648 struct net_device *);
52c0fd83
MC		 5649
5650/* Use GSO to workaround a rare TSO bug that may be triggered when the
5651 * TSO header is greater than 80 bytes.
5652 */
5653static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5654{
5655 struct sk_buff *segs, *nskb;
f3f3f27e 5656 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5657
5658 /* Estimate the number of fragments in the worst case */
f3f3f27e 5659 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5660 netif_stop_queue(tp->dev);
f3f3f27e 5661 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5662 return NETDEV_TX_BUSY;
5663
5664 netif_wake_queue(tp->dev);
52c0fd83
MC		 5665 }
5666
5667 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5668 if (IS_ERR(segs))
52c0fd83
MC		 5669 goto tg3_tso_bug_end;
5670
5671 do {
5672 nskb = segs;
5673 segs = segs->next;
5674 nskb->next = NULL;
5675 tg3_start_xmit_dma_bug(nskb, tp->dev);
5676 } while (segs);
5677
5678tg3_tso_bug_end:
5679 dev_kfree_skb(skb);
5680
5681 return NETDEV_TX_OK;
5682}
52c0fd83 5683
5a6f3074
MC		 5684/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5685 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5686 */
61357325
SH		 5687static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5688 struct net_device *dev)
1da177e4
LT		 5689{
5690 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5691 u32 len, entry, base_flags, mss;
5692 int would_hit_hwbug;
90079ce8 5693 dma_addr_t mapping;
24f4efd4
MC		 5694 struct tg3_napi *tnapi;
5695 struct netdev_queue *txq;
f4188d8a
AD		 5696 unsigned int i, last;
5697
1da177e4 5698
24f4efd4
MC		 5699 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5700 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5701 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5702 tnapi++;
1da177e4 5703
00b70504 5704 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5705 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5706 * interrupt. Furthermore, IRQ processing runs lockless so we have
5707 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5708 */
f3f3f27e 5709 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5710 if (!netif_tx_queue_stopped(txq)) {
5711 netif_tx_stop_queue(txq);
1f064a87
SH		 5712
5713 /* This is a hard error, log it. */
05dbe005 5714 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1f064a87 5715 }
1da177e4
LT		 5716 return NETDEV_TX_BUSY;
5717 }
5718
f3f3f27e 5719 entry = tnapi->tx_prod;
1da177e4 5720 base_flags = 0;
84fa7933 5721 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5722 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5723
c13e3713 5724 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5725 struct iphdr *iph;
92c6b8d1 5726 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5727
5728 if (skb_header_cloned(skb) &&
5729 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5730 dev_kfree_skb(skb);
5731 goto out_unlock;
5732 }
5733
ab6a5bb6 5734 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5735 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5736
52c0fd83
MC		 5737 hdr_len = ip_tcp_len + tcp_opt_len;
5738 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5739 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5740 return (tg3_tso_bug(tp, skb));
5741
1da177e4
LT		 5742 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5743 TXD_FLAG_CPU_POST_DMA);
5744
eddc9ec5
ACM		 5745 iph = ip_hdr(skb);
5746 iph->check = 0;
5747 iph->tot_len = htons(mss + hdr_len);
1da177e4 5748 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5749 tcp_hdr(skb)->check = 0;
1da177e4 5750 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5751 } else
5752 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5753 iph->daddr, 0,
5754 IPPROTO_TCP,
5755 0);
1da177e4 5756
615774fe
MC		 5757 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5758 mss |= (hdr_len & 0xc) << 12;
5759 if (hdr_len & 0x10)
5760 base_flags |= 0x00000010;
5761 base_flags |= (hdr_len & 0x3e0) << 5;
5762 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5763 mss |= hdr_len << 9;
5764 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5766 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5767 int tsflags;
5768
eddc9ec5 5769 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5770 mss |= (tsflags << 11);
5771 }
5772 } else {
eddc9ec5 5773 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5774 int tsflags;
5775
eddc9ec5 5776 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5777 base_flags |= tsflags << 12;
5778 }
5779 }
5780 }
1da177e4
LT		 5781#if TG3_VLAN_TAG_USED
5782 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5783 base_flags |= (TXD_FLAG_VLAN |
5784 (vlan_tx_tag_get(skb) << 16));
5785#endif
5786
b703df6f 5787 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5788 !mss && skb->len > ETH_DATA_LEN)
5789 base_flags |= TXD_FLAG_JMB_PKT;
5790
f4188d8a
AD		 5791 len = skb_headlen(skb);
5792
5793 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5794 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5795 dev_kfree_skb(skb);
5796 goto out_unlock;
5797 }
5798
f3f3f27e 5799 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5800 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5801
5802 would_hit_hwbug = 0;
5803
92c6b8d1
MC		 5804 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5805 would_hit_hwbug = 1;
5806
0e1406dd
MC		 5807 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5808 tg3_4g_overflow_test(mapping, len))
5809 would_hit_hwbug = 1;
5810
5811 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5812 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5813 would_hit_hwbug = 1;
0e1406dd
MC		 5814
5815 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5816 would_hit_hwbug = 1;
1da177e4 5817
f3f3f27e 5818 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5819 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5820
5821 entry = NEXT_TX(entry);
5822
5823 /* Now loop through additional data fragments, and queue them. */
5824 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5825 last = skb_shinfo(skb)->nr_frags - 1;
5826 for (i = 0; i <= last; i++) {
5827 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5828
5829 len = frag->size;
f4188d8a
AD		 5830 mapping = pci_map_page(tp->pdev,
5831 frag->page,
5832 frag->page_offset,
5833 len, PCI_DMA_TODEVICE);
1da177e4 5834
f3f3f27e 5835 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5836 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5837 mapping);
5838 if (pci_dma_mapping_error(tp->pdev, mapping))
5839 goto dma_error;
1da177e4 5840
92c6b8d1
MC		 5841 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5842 len <= 8)
5843 would_hit_hwbug = 1;
5844
0e1406dd
MC		 5845 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5846 tg3_4g_overflow_test(mapping, len))
c58ec932 5847 would_hit_hwbug = 1;
1da177e4 5848
0e1406dd
MC		 5849 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5850 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5851 would_hit_hwbug = 1;
5852
1da177e4 5853 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5854 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5855 base_flags, (i == last)|(mss << 1));
5856 else
f3f3f27e 5857 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5858 base_flags, (i == last));
5859
5860 entry = NEXT_TX(entry);
5861 }
5862 }
5863
5864 if (would_hit_hwbug) {
5865 u32 last_plus_one = entry;
5866 u32 start;
1da177e4 5867
c58ec932
MC		 5868 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5869 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5870
5871 /* If the workaround fails due to memory/mapping
5872 * failure, silently drop this packet.
5873 */
24f4efd4 5874 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5875 &start, base_flags, mss))
1da177e4
LT		 5876 goto out_unlock;
5877
5878 entry = start;
5879 }
5880
5881 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5882 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5883
f3f3f27e
MC		 5884 tnapi->tx_prod = entry;
5885 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5886 netif_tx_stop_queue(txq);
f3f3f27e 5887 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5888 netif_tx_wake_queue(txq);
51b91468 5889 }
1da177e4
LT		 5890
5891out_unlock:
cdd0db05 5892 mmiowb();
1da177e4
LT		 5893
5894 return NETDEV_TX_OK;
f4188d8a
AD		 5895
5896dma_error:
5897 last = i;
5898 entry = tnapi->tx_prod;
5899 tnapi->tx_buffers[entry].skb = NULL;
5900 pci_unmap_single(tp->pdev,
5901 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5902 skb_headlen(skb),
5903 PCI_DMA_TODEVICE);
5904 for (i = 0; i <= last; i++) {
5905 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5906 entry = NEXT_TX(entry);
5907
5908 pci_unmap_page(tp->pdev,
5909 pci_unmap_addr(&tnapi->tx_buffers[entry],
5910 mapping),
5911 frag->size, PCI_DMA_TODEVICE);
5912 }
5913
5914 dev_kfree_skb(skb);
5915 return NETDEV_TX_OK;
1da177e4
LT		 5916}
5917
5918static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5919 int new_mtu)
5920{
5921 dev->mtu = new_mtu;
5922
ef7f5ec0 5923 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5924 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5925 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5926 ethtool_op_set_tso(dev, 0);
5927 }
5928 else
5929 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5930 } else {
a4e2b347 5931 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5932 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5933 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5934 }
1da177e4
LT		 5935}
5936
5937static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5938{
5939 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5940 int err;
1da177e4
LT		 5941
5942 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5943 return -EINVAL;
5944
5945 if (!netif_running(dev)) {
5946 /* We'll just catch it later when the
5947 * device is up'd.
5948 */
5949 tg3_set_mtu(dev, tp, new_mtu);
5950 return 0;
5951 }
5952
b02fd9e3
MC		 5953 tg3_phy_stop(tp);
5954
1da177e4 5955 tg3_netif_stop(tp);
f47c11ee
DM		 5956
5957 tg3_full_lock(tp, 1);
1da177e4 5958
944d980e 5959 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5960
5961 tg3_set_mtu(dev, tp, new_mtu);
5962
b9ec6c1b 5963 err = tg3_restart_hw(tp, 0);
1da177e4 5964
b9ec6c1b
MC		 5965 if (!err)
5966 tg3_netif_start(tp);
1da177e4 5967
f47c11ee 5968 tg3_full_unlock(tp);
1da177e4 5969
b02fd9e3
MC		 5970 if (!err)
5971 tg3_phy_start(tp);
5972
b9ec6c1b 5973 return err;
1da177e4
LT		 5974}
5975
21f581a5
MC		 5976static void tg3_rx_prodring_free(struct tg3 *tp,
5977 struct tg3_rx_prodring_set *tpr)
1da177e4 5978{
1da177e4
LT		 5979 int i;
5980
b196c7e4
MC		 5981 if (tpr != &tp->prodring[0]) {
5982 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5983 i = (i + 1) % TG3_RX_RING_SIZE)
5984 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5985 tp->rx_pkt_map_sz);
5986
5987 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5988 for (i = tpr->rx_jmb_cons_idx;
5989 i != tpr->rx_jmb_prod_idx;
5990 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5991 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5992 TG3_RX_JMB_MAP_SZ);
5993 }
5994 }
5995
2b2cdb65 5996 return;
b196c7e4 5997 }
1da177e4 5998
2b2cdb65
MC		 5999 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6000 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6001 tp->rx_pkt_map_sz);
1da177e4 6002
cf7a7298 6003 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 6004 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6005 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6006 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 6007 }
6008}
6009
6010/* Initialize tx/rx rings for packet processing.
6011 *
6012 * The chip has been shut down and the driver detached from
6013 * the networking, so no interrupts or new tx packets will
6014 * end up in the driver. tp->{tx,}lock are held and thus
6015 * we may not sleep.
6016 */
21f581a5
MC		 6017static int tg3_rx_prodring_alloc(struct tg3 *tp,
6018 struct tg3_rx_prodring_set *tpr)
1da177e4 6019{
287be12e 6020 u32 i, rx_pkt_dma_sz;
1da177e4 6021
b196c7e4
MC		 6022 tpr->rx_std_cons_idx = 0;
6023 tpr->rx_std_prod_idx = 0;
6024 tpr->rx_jmb_cons_idx = 0;
6025 tpr->rx_jmb_prod_idx = 0;
6026
2b2cdb65
MC		 6027 if (tpr != &tp->prodring[0]) {
6028 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6029 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6030 memset(&tpr->rx_jmb_buffers[0], 0,
6031 TG3_RX_JMB_BUFF_RING_SIZE);
6032 goto done;
6033 }
6034
1da177e4 6035 /* Zero out all descriptors. */
21f581a5 6036 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 6037
287be12e 6038 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 6039 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 6040 tp->dev->mtu > ETH_DATA_LEN)
6041 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6042 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 6043
1da177e4
LT		 6044 /* Initialize invariants of the rings, we only set this
6045 * stuff once. This works because the card does not
6046 * write into the rx buffer posting rings.
6047 */
6048 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6049 struct tg3_rx_buffer_desc *rxd;
6050
21f581a5 6051 rxd = &tpr->rx_std[i];
287be12e 6052 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6053 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6054 rxd->opaque = (RXD_OPAQUE_RING_STD |
6055 (i << RXD_OPAQUE_INDEX_SHIFT));
6056 }
6057
1da177e4
LT		 6058 /* Now allocate fresh SKBs for each rx ring. */
6059 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6060 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
05dbe005
JP		 6061 netdev_warn(tp->dev, "Using a smaller RX standard ring, only %d out of %d buffers were allocated successfully\n",
6062 i, tp->rx_pending);
32d8c572 6063 if (i == 0)
cf7a7298 6064 goto initfail;
32d8c572 6065 tp->rx_pending = i;
1da177e4 6066 break;
32d8c572 6067 }
1da177e4
LT		 6068 }
6069
cf7a7298
MC		 6070 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6071 goto done;
6072
21f581a5 6073 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6074
0d86df80
MC		 6075 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6076 goto done;
cf7a7298 6077
0d86df80
MC		 6078 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6079 struct tg3_rx_buffer_desc *rxd;
6080
6081 rxd = &tpr->rx_jmb[i].std;
6082 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6083 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6084 RXD_FLAG_JUMBO;
6085 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6086 (i << RXD_OPAQUE_INDEX_SHIFT));
6087 }
6088
6089 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6090 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
05dbe005
JP		 6091 netdev_warn(tp->dev, "Using a smaller RX jumbo ring, only %d out of %d buffers were allocated successfully\n",
6092 i, tp->rx_jumbo_pending);
0d86df80
MC		 6093 if (i == 0)
6094 goto initfail;
6095 tp->rx_jumbo_pending = i;
6096 break;
1da177e4
LT		 6097 }
6098 }
cf7a7298
MC		 6099
6100done:
32d8c572 6101 return 0;
cf7a7298
MC		 6102
6103initfail:
21f581a5 6104 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6105 return -ENOMEM;
1da177e4
LT		 6106}
6107
21f581a5
MC		 6108static void tg3_rx_prodring_fini(struct tg3 *tp,
6109 struct tg3_rx_prodring_set *tpr)
1da177e4 6110{
21f581a5
MC		 6111 kfree(tpr->rx_std_buffers);
6112 tpr->rx_std_buffers = NULL;
6113 kfree(tpr->rx_jmb_buffers);
6114 tpr->rx_jmb_buffers = NULL;
6115 if (tpr->rx_std) {
1da177e4 6116 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6117 tpr->rx_std, tpr->rx_std_mapping);
6118 tpr->rx_std = NULL;
1da177e4 6119 }
21f581a5 6120 if (tpr->rx_jmb) {
1da177e4 6121 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6122 tpr->rx_jmb, tpr->rx_jmb_mapping);
6123 tpr->rx_jmb = NULL;
1da177e4 6124 }
cf7a7298
MC		 6125}
6126
21f581a5
MC		 6127static int tg3_rx_prodring_init(struct tg3 *tp,
6128 struct tg3_rx_prodring_set *tpr)
cf7a7298 6129{
2b2cdb65 6130 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6131 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6132 return -ENOMEM;
6133
21f581a5
MC		 6134 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6135 &tpr->rx_std_mapping);
6136 if (!tpr->rx_std)
cf7a7298
MC		 6137 goto err_out;
6138
6139 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6140 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6141 GFP_KERNEL);
6142 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6143 goto err_out;
6144
21f581a5
MC		 6145 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6146 TG3_RX_JUMBO_RING_BYTES,
6147 &tpr->rx_jmb_mapping);
6148 if (!tpr->rx_jmb)
cf7a7298
MC		 6149 goto err_out;
6150 }
6151
6152 return 0;
6153
6154err_out:
21f581a5 6155 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6156 return -ENOMEM;
6157}
6158
6159/* Free up pending packets in all rx/tx rings.
6160 *
6161 * The chip has been shut down and the driver detached from
6162 * the networking, so no interrupts or new tx packets will
6163 * end up in the driver. tp->{tx,}lock is not held and we are not
6164 * in an interrupt context and thus may sleep.
6165 */
6166static void tg3_free_rings(struct tg3 *tp)
6167{
f77a6a8e 6168 int i, j;
cf7a7298 6169
f77a6a8e
MC		 6170 for (j = 0; j < tp->irq_cnt; j++) {
6171 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6172
0c1d0e2b
MC		 6173 if (!tnapi->tx_buffers)
6174 continue;
6175
f77a6a8e 6176 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6177 struct ring_info *txp;
f77a6a8e 6178 struct sk_buff *skb;
f4188d8a 6179 unsigned int k;
cf7a7298 6180
f77a6a8e
MC		 6181 txp = &tnapi->tx_buffers[i];
6182 skb = txp->skb;
cf7a7298 6183
f77a6a8e
MC		 6184 if (skb == NULL) {
6185 i++;
6186 continue;
6187 }
cf7a7298 6188
f4188d8a
AD		 6189 pci_unmap_single(tp->pdev,
6190 pci_unmap_addr(txp, mapping),
6191 skb_headlen(skb),
6192 PCI_DMA_TODEVICE);
f77a6a8e 6193 txp->skb = NULL;
cf7a7298 6194
f4188d8a
AD		 6195 i++;
6196
6197 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6198 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6199 pci_unmap_page(tp->pdev,
6200 pci_unmap_addr(txp, mapping),
6201 skb_shinfo(skb)->frags[k].size,
6202 PCI_DMA_TODEVICE);
6203 i++;
6204 }
f77a6a8e
MC		 6205
6206 dev_kfree_skb_any(skb);
6207 }
cf7a7298 6208
e4af1af9 6209 tg3_rx_prodring_free(tp, &tp->prodring[j]);
2b2cdb65 6210 }
cf7a7298
MC		 6211}
6212
6213/* Initialize tx/rx rings for packet processing.
6214 *
6215 * The chip has been shut down and the driver detached from
6216 * the networking, so no interrupts or new tx packets will
6217 * end up in the driver. tp->{tx,}lock are held and thus
6218 * we may not sleep.
6219 */
6220static int tg3_init_rings(struct tg3 *tp)
6221{
f77a6a8e 6222 int i;
72334482 6223
cf7a7298
MC		 6224 /* Free up all the SKBs. */
6225 tg3_free_rings(tp);
6226
f77a6a8e
MC		 6227 for (i = 0; i < tp->irq_cnt; i++) {
6228 struct tg3_napi *tnapi = &tp->napi[i];
6229
6230 tnapi->last_tag = 0;
6231 tnapi->last_irq_tag = 0;
6232 tnapi->hw_status->status = 0;
6233 tnapi->hw_status->status_tag = 0;
6234 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6235
f77a6a8e
MC		 6236 tnapi->tx_prod = 0;
6237 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6238 if (tnapi->tx_ring)
6239 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6240
6241 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6242 if (tnapi->rx_rcb)
6243 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 6244
e4af1af9
MC		 6245 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6246 tg3_free_rings(tp);
2b2cdb65 6247 return -ENOMEM;
e4af1af9 6248 }
f77a6a8e 6249 }
72334482 6250
2b2cdb65 6251 return 0;
cf7a7298
MC		 6252}
6253
6254/*
6255 * Must not be invoked with interrupt sources disabled and
6256 * the hardware shutdown down.
6257 */
6258static void tg3_free_consistent(struct tg3 *tp)
6259{
f77a6a8e 6260 int i;
898a56f8 6261
f77a6a8e
MC		 6262 for (i = 0; i < tp->irq_cnt; i++) {
6263 struct tg3_napi *tnapi = &tp->napi[i];
6264
6265 if (tnapi->tx_ring) {
6266 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6267 tnapi->tx_ring, tnapi->tx_desc_mapping);
6268 tnapi->tx_ring = NULL;
6269 }
6270
6271 kfree(tnapi->tx_buffers);
6272 tnapi->tx_buffers = NULL;
6273
6274 if (tnapi->rx_rcb) {
6275 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6276 tnapi->rx_rcb,
6277 tnapi->rx_rcb_mapping);
6278 tnapi->rx_rcb = NULL;
6279 }
6280
6281 if (tnapi->hw_status) {
6282 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6283 tnapi->hw_status,
6284 tnapi->status_mapping);
6285 tnapi->hw_status = NULL;
6286 }
1da177e4 6287 }
f77a6a8e 6288
1da177e4
LT		 6289 if (tp->hw_stats) {
6290 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6291 tp->hw_stats, tp->stats_mapping);
6292 tp->hw_stats = NULL;
6293 }
f77a6a8e 6294
e4af1af9 6295 for (i = 0; i < tp->irq_cnt; i++)
2b2cdb65 6296 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6297}
6298
6299/*
6300 * Must not be invoked with interrupt sources disabled and
6301 * the hardware shutdown down. Can sleep.
6302 */
6303static int tg3_alloc_consistent(struct tg3 *tp)
6304{
f77a6a8e 6305 int i;
898a56f8 6306
e4af1af9 6307 for (i = 0; i < tp->irq_cnt; i++) {
2b2cdb65
MC		 6308 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6309 goto err_out;
6310 }
1da177e4 6311
f77a6a8e
MC		 6312 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6313 sizeof(struct tg3_hw_stats),
6314 &tp->stats_mapping);
6315 if (!tp->hw_stats)
1da177e4
LT		 6316 goto err_out;
6317
f77a6a8e 6318 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6319
f77a6a8e
MC		 6320 for (i = 0; i < tp->irq_cnt; i++) {
6321 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6322 struct tg3_hw_status *sblk;
1da177e4 6323
f77a6a8e
MC		 6324 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6325 TG3_HW_STATUS_SIZE,
6326 &tnapi->status_mapping);
6327 if (!tnapi->hw_status)
6328 goto err_out;
898a56f8 6329
f77a6a8e 6330 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6331 sblk = tnapi->hw_status;
6332
19cfaecc
MC		 6333 /* If multivector TSS is enabled, vector 0 does not handle
6334 * tx interrupts. Don't allocate any resources for it.
6335 */
6336 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6337 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6338 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6339 TG3_TX_RING_SIZE,
6340 GFP_KERNEL);
6341 if (!tnapi->tx_buffers)
6342 goto err_out;
6343
6344 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6345 TG3_TX_RING_BYTES,
6346 &tnapi->tx_desc_mapping);
6347 if (!tnapi->tx_ring)
6348 goto err_out;
6349 }
6350
8d9d7cfc
MC		 6351 /*
6352 * When RSS is enabled, the status block format changes
6353 * slightly. The "rx_jumbo_consumer", "reserved",
6354 * and "rx_mini_consumer" members get mapped to the
6355 * other three rx return ring producer indexes.
6356 */
6357 switch (i) {
6358 default:
6359 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6360 break;
6361 case 2:
6362 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6363 break;
6364 case 3:
6365 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6366 break;
6367 case 4:
6368 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6369 break;
6370 }
72334482 6371
e4af1af9 6372 tnapi->prodring = &tp->prodring[i];
b196c7e4 6373
0c1d0e2b
MC		 6374 /*
6375 * If multivector RSS is enabled, vector 0 does not handle
6376 * rx or tx interrupts. Don't allocate any resources for it.
6377 */
6378 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6379 continue;
6380
f77a6a8e
MC		 6381 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6382 TG3_RX_RCB_RING_BYTES(tp),
6383 &tnapi->rx_rcb_mapping);
6384 if (!tnapi->rx_rcb)
6385 goto err_out;
72334482 6386
f77a6a8e 6387 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6388 }
1da177e4
LT		 6389
6390 return 0;
6391
6392err_out:
6393 tg3_free_consistent(tp);
6394 return -ENOMEM;
6395}
6396
6397#define MAX_WAIT_CNT 1000
6398
6399/* To stop a block, clear the enable bit and poll till it
6400 * clears. tp->lock is held.
6401 */
b3b7d6be 6402static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6403{
6404 unsigned int i;
6405 u32 val;
6406
6407 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6408 switch (ofs) {
6409 case RCVLSC_MODE:
6410 case DMAC_MODE:
6411 case MBFREE_MODE:
6412 case BUFMGR_MODE:
6413 case MEMARB_MODE:
6414 /* We can't enable/disable these bits of the
6415 * 5705/5750, just say success.
6416 */
6417 return 0;
6418
6419 default:
6420 break;
855e1111 6421 }
1da177e4
LT		 6422 }
6423
6424 val = tr32(ofs);
6425 val &= ~enable_bit;
6426 tw32_f(ofs, val);
6427
6428 for (i = 0; i < MAX_WAIT_CNT; i++) {
6429 udelay(100);
6430 val = tr32(ofs);
6431 if ((val & enable_bit) == 0)
6432 break;
6433 }
6434
b3b7d6be 6435 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 6436 dev_err(&tp->pdev->dev,
6437 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6438 ofs, enable_bit);
1da177e4
LT		 6439 return -ENODEV;
6440 }
6441
6442 return 0;
6443}
6444
6445/* tp->lock is held. */
b3b7d6be 6446static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6447{
6448 int i, err;
6449
6450 tg3_disable_ints(tp);
6451
6452 tp->rx_mode &= ~RX_MODE_ENABLE;
6453 tw32_f(MAC_RX_MODE, tp->rx_mode);
6454 udelay(10);
6455
b3b7d6be
DM		 6456 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6457 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6458 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6459 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6460 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6461 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6462
6463 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6464 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6465 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6466 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6467 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6468 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6469 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6470
6471 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6472 tw32_f(MAC_MODE, tp->mac_mode);
6473 udelay(40);
6474
6475 tp->tx_mode &= ~TX_MODE_ENABLE;
6476 tw32_f(MAC_TX_MODE, tp->tx_mode);
6477
6478 for (i = 0; i < MAX_WAIT_CNT; i++) {
6479 udelay(100);
6480 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6481 break;
6482 }
6483 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 6484 dev_err(&tp->pdev->dev,
6485 "%s timed out, TX_MODE_ENABLE will not clear "
6486 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 6487 err |= -ENODEV;
1da177e4
LT		 6488 }
6489
e6de8ad1 6490 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6491 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6492 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6493
6494 tw32(FTQ_RESET, 0xffffffff);
6495 tw32(FTQ_RESET, 0x00000000);
6496
b3b7d6be
DM		 6497 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6498 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6499
f77a6a8e
MC		 6500 for (i = 0; i < tp->irq_cnt; i++) {
6501 struct tg3_napi *tnapi = &tp->napi[i];
6502 if (tnapi->hw_status)
6503 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6504 }
1da177e4
LT		 6505 if (tp->hw_stats)
6506 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6507
1da177e4
LT		 6508 return err;
6509}
6510
0d3031d9
MC		 6511static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6512{
6513 int i;
6514 u32 apedata;
6515
6516 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6517 if (apedata != APE_SEG_SIG_MAGIC)
6518 return;
6519
6520 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6521 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6522 return;
6523
6524 /* Wait for up to 1 millisecond for APE to service previous event. */
6525 for (i = 0; i < 10; i++) {
6526 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6527 return;
6528
6529 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6530
6531 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6532 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6533 event | APE_EVENT_STATUS_EVENT_PENDING);
6534
6535 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6536
6537 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6538 break;
6539
6540 udelay(100);
6541 }
6542
6543 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6544 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6545}
6546
6547static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6548{
6549 u32 event;
6550 u32 apedata;
6551
6552 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6553 return;
6554
6555 switch (kind) {
6556 case RESET_KIND_INIT:
6557 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6558 APE_HOST_SEG_SIG_MAGIC);
6559 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6560 APE_HOST_SEG_LEN_MAGIC);
6561 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6562 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6563 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6564 APE_HOST_DRIVER_ID_MAGIC);
6565 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6566 APE_HOST_BEHAV_NO_PHYLOCK);
6567
6568 event = APE_EVENT_STATUS_STATE_START;
6569 break;
6570 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6571 /* With the interface we are currently using,
6572 * APE does not track driver state. Wiping
6573 * out the HOST SEGMENT SIGNATURE forces
6574 * the APE to assume OS absent status.
6575 */
6576 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6577
0d3031d9
MC		 6578 event = APE_EVENT_STATUS_STATE_UNLOAD;
6579 break;
6580 case RESET_KIND_SUSPEND:
6581 event = APE_EVENT_STATUS_STATE_SUSPEND;
6582 break;
6583 default:
6584 return;
6585 }
6586
6587 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6588
6589 tg3_ape_send_event(tp, event);
6590}
6591
1da177e4
LT		 6592/* tp->lock is held. */
6593static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6594{
f49639e6
DM		 6595 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6596 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6597
6598 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6599 switch (kind) {
6600 case RESET_KIND_INIT:
6601 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6602 DRV_STATE_START);
6603 break;
6604
6605 case RESET_KIND_SHUTDOWN:
6606 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6607 DRV_STATE_UNLOAD);
6608 break;
6609
6610 case RESET_KIND_SUSPEND:
6611 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612 DRV_STATE_SUSPEND);
6613 break;
6614
6615 default:
6616 break;
855e1111 6617 }
1da177e4 6618 }
0d3031d9
MC		 6619
6620 if (kind == RESET_KIND_INIT ||
6621 kind == RESET_KIND_SUSPEND)
6622 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6623}
6624
6625/* tp->lock is held. */
6626static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6627{
6628 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6629 switch (kind) {
6630 case RESET_KIND_INIT:
6631 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6632 DRV_STATE_START_DONE);
6633 break;
6634
6635 case RESET_KIND_SHUTDOWN:
6636 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6637 DRV_STATE_UNLOAD_DONE);
6638 break;
6639
6640 default:
6641 break;
855e1111 6642 }
1da177e4 6643 }
0d3031d9
MC		 6644
6645 if (kind == RESET_KIND_SHUTDOWN)
6646 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6647}
6648
6649/* tp->lock is held. */
6650static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6651{
6652 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6653 switch (kind) {
6654 case RESET_KIND_INIT:
6655 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6656 DRV_STATE_START);
6657 break;
6658
6659 case RESET_KIND_SHUTDOWN:
6660 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6661 DRV_STATE_UNLOAD);
6662 break;
6663
6664 case RESET_KIND_SUSPEND:
6665 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6666 DRV_STATE_SUSPEND);
6667 break;
6668
6669 default:
6670 break;
855e1111 6671 }
1da177e4
LT		 6672 }
6673}
6674
7a6f4369
MC		 6675static int tg3_poll_fw(struct tg3 *tp)
6676{
6677 int i;
6678 u32 val;
6679
b5d3772c 6680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6681 /* Wait up to 20ms for init done. */
6682 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6683 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6684 return 0;
0ccead18 6685 udelay(100);
b5d3772c
MC		 6686 }
6687 return -ENODEV;
6688 }
6689
7a6f4369
MC		 6690 /* Wait for firmware initialization to complete. */
6691 for (i = 0; i < 100000; i++) {
6692 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6693 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6694 break;
6695 udelay(10);
6696 }
6697
6698 /* Chip might not be fitted with firmware. Some Sun onboard
6699 * parts are configured like that. So don't signal the timeout
6700 * of the above loop as an error, but do report the lack of
6701 * running firmware once.
6702 */
6703 if (i >= 100000 &&
6704 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6705 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6706
05dbe005 6707 netdev_info(tp->dev, "No firmware running\n");
7a6f4369
MC		 6708 }
6709
6b10c165
MC		 6710 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6711 /* The 57765 A0 needs a little more
6712 * time to do some important work.
6713 */
6714 mdelay(10);
6715 }
6716
7a6f4369
MC		 6717 return 0;
6718}
6719
ee6a99b5
MC		 6720/* Save PCI command register before chip reset */
6721static void tg3_save_pci_state(struct tg3 *tp)
6722{
8a6eac90 6723 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6724}
6725
6726/* Restore PCI state after chip reset */
6727static void tg3_restore_pci_state(struct tg3 *tp)
6728{
6729 u32 val;
6730
6731 /* Re-enable indirect register accesses. */
6732 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6733 tp->misc_host_ctrl);
6734
6735 /* Set MAX PCI retry to zero. */
6736 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6737 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6738 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6739 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6740 /* Allow reads and writes to the APE register and memory space. */
6741 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6742 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6743 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6744 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6745
8a6eac90 6746 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6747
fcb389df
MC		 6748 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6749 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6750 pcie_set_readrq(tp->pdev, 4096);
6751 else {
6752 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6753 tp->pci_cacheline_sz);
6754 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6755 tp->pci_lat_timer);
6756 }
114342f2 6757 }
5f5c51e3 6758
ee6a99b5 6759 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6760 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6761 u16 pcix_cmd;
6762
6763 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6764 &pcix_cmd);
6765 pcix_cmd &= ~PCI_X_CMD_ERO;
6766 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6767 pcix_cmd);
6768 }
ee6a99b5
MC		 6769
6770 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6771
6772 /* Chip reset on 5780 will reset MSI enable bit,
6773 * so need to restore it.
6774 */
6775 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6776 u16 ctrl;
6777
6778 pci_read_config_word(tp->pdev,
6779 tp->msi_cap + PCI_MSI_FLAGS,
6780 &ctrl);
6781 pci_write_config_word(tp->pdev,
6782 tp->msi_cap + PCI_MSI_FLAGS,
6783 ctrl | PCI_MSI_FLAGS_ENABLE);
6784 val = tr32(MSGINT_MODE);
6785 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6786 }
6787 }
6788}
6789
1da177e4
LT		 6790static void tg3_stop_fw(struct tg3 *);
6791
6792/* tp->lock is held. */
6793static int tg3_chip_reset(struct tg3 *tp)
6794{
6795 u32 val;
1ee582d8 6796 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6797 int i, err;
1da177e4 6798
f49639e6
DM		 6799 tg3_nvram_lock(tp);
6800
77b483f1
MC		 6801 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6802
f49639e6
DM		 6803 /* No matching tg3_nvram_unlock() after this because
6804 * chip reset below will undo the nvram lock.
6805 */
6806 tp->nvram_lock_cnt = 0;
1da177e4 6807
ee6a99b5
MC		 6808 /* GRC_MISC_CFG core clock reset will clear the memory
6809 * enable bit in PCI register 4 and the MSI enable bit
6810 * on some chips, so we save relevant registers here.
6811 */
6812 tg3_save_pci_state(tp);
6813
d9ab5ad1 6814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6815 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6816 tw32(GRC_FASTBOOT_PC, 0);
6817
1da177e4
LT		 6818 /*
6819 * We must avoid the readl() that normally takes place.
6820 * It locks machines, causes machine checks, and other
6821 * fun things. So, temporarily disable the 5701
6822 * hardware workaround, while we do the reset.
6823 */
1ee582d8
MC		 6824 write_op = tp->write32;
6825 if (write_op == tg3_write_flush_reg32)
6826 tp->write32 = tg3_write32;
1da177e4 6827
d18edcb2
MC		 6828 /* Prevent the irq handler from reading or writing PCI registers
6829 * during chip reset when the memory enable bit in the PCI command
6830 * register may be cleared. The chip does not generate interrupt
6831 * at this time, but the irq handler may still be called due to irq
6832 * sharing or irqpoll.
6833 */
6834 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6835 for (i = 0; i < tp->irq_cnt; i++) {
6836 struct tg3_napi *tnapi = &tp->napi[i];
6837 if (tnapi->hw_status) {
6838 tnapi->hw_status->status = 0;
6839 tnapi->hw_status->status_tag = 0;
6840 }
6841 tnapi->last_tag = 0;
6842 tnapi->last_irq_tag = 0;
b8fa2f3a 6843 }
d18edcb2 6844 smp_mb();
4f125f42
MC		 6845
6846 for (i = 0; i < tp->irq_cnt; i++)
6847 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6848
255ca311
MC		 6849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6850 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6851 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6852 }
6853
1da177e4
LT		 6854 /* do the reset */
6855 val = GRC_MISC_CFG_CORECLK_RESET;
6856
6857 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6858 if (tr32(0x7e2c) == 0x60) {
6859 tw32(0x7e2c, 0x20);
6860 }
6861 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6862 tw32(GRC_MISC_CFG, (1 << 29));
6863 val |= (1 << 29);
6864 }
6865 }
6866
b5d3772c
MC		 6867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6868 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6869 tw32(GRC_VCPU_EXT_CTRL,
6870 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6871 }
6872
1da177e4
LT		 6873 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6874 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6875 tw32(GRC_MISC_CFG, val);
6876
1ee582d8
MC		 6877 /* restore 5701 hardware bug workaround write method */
6878 tp->write32 = write_op;
1da177e4
LT		 6879
6880 /* Unfortunately, we have to delay before the PCI read back.
6881 * Some 575X chips even will not respond to a PCI cfg access
6882 * when the reset command is given to the chip.
6883 *
6884 * How do these hardware designers expect things to work
6885 * properly if the PCI write is posted for a long period
6886 * of time? It is always necessary to have some method by
6887 * which a register read back can occur to push the write
6888 * out which does the reset.
6889 *
6890 * For most tg3 variants the trick below was working.
6891 * Ho hum...
6892 */
6893 udelay(120);
6894
6895 /* Flush PCI posted writes. The normal MMIO registers
6896 * are inaccessible at this time so this is the only
6897 * way to make this reliably (actually, this is no longer
6898 * the case, see above). I tried to use indirect
6899 * register read/write but this upset some 5701 variants.
6900 */
6901 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6902
6903 udelay(120);
6904
5e7dfd0f 6905 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6906 u16 val16;
6907
1da177e4
LT		 6908 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6909 int i;
6910 u32 cfg_val;
6911
6912 /* Wait for link training to complete. */
6913 for (i = 0; i < 5000; i++)
6914 udelay(100);
6915
6916 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6917 pci_write_config_dword(tp->pdev, 0xc4,
6918 cfg_val | (1 << 15));
6919 }
5e7dfd0f 6920
e7126997
MC		 6921 /* Clear the "no snoop" and "relaxed ordering" bits. */
6922 pci_read_config_word(tp->pdev,
6923 tp->pcie_cap + PCI_EXP_DEVCTL,
6924 &val16);
6925 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6926 PCI_EXP_DEVCTL_NOSNOOP_EN);
6927 /*
6928 * Older PCIe devices only support the 128 byte
6929 * MPS setting. Enforce the restriction.
5e7dfd0f 6930 */
e7126997
MC		 6931 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6932 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6933 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6934 pci_write_config_word(tp->pdev,
6935 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6936 val16);
5e7dfd0f
MC		 6937
6938 pcie_set_readrq(tp->pdev, 4096);
6939
6940 /* Clear error status */
6941 pci_write_config_word(tp->pdev,
6942 tp->pcie_cap + PCI_EXP_DEVSTA,
6943 PCI_EXP_DEVSTA_CED |
6944 PCI_EXP_DEVSTA_NFED |
6945 PCI_EXP_DEVSTA_FED |
6946 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6947 }
6948
ee6a99b5 6949 tg3_restore_pci_state(tp);
1da177e4 6950
d18edcb2
MC		 6951 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6952
ee6a99b5
MC		 6953 val = 0;
6954 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6955 val = tr32(MEMARB_MODE);
ee6a99b5 6956 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6957
6958 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6959 tg3_stop_fw(tp);
6960 tw32(0x5000, 0x400);
6961 }
6962
6963 tw32(GRC_MODE, tp->grc_mode);
6964
6965 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6966 val = tr32(0xc4);
1da177e4
LT		 6967
6968 tw32(0xc4, val | (1 << 15));
6969 }
6970
6971 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6973 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6974 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6975 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6976 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6977 }
6978
6979 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6980 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6981 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6982 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6983 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6984 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6985 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6986 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6987 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6988 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6989 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6990 } else
6991 tw32_f(MAC_MODE, 0);
6992 udelay(40);
6993
77b483f1
MC		 6994 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6995
7a6f4369
MC		 6996 err = tg3_poll_fw(tp);
6997 if (err)
6998 return err;
1da177e4 6999
0a9140cf
MC		 7000 tg3_mdio_start(tp);
7001
52cdf852
MC		 7002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7003 u8 phy_addr;
7004
7005 phy_addr = tp->phy_addr;
7006 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7007
7008 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7009 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7010 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7011 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7012 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7013 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7014 udelay(10);
7015
7016 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7017 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7018 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7019 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7020 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7021 udelay(10);
7022
7023 tp->phy_addr = phy_addr;
7024 }
7025
1da177e4 7026 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 7027 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7028 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 7029 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7030 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 7031 val = tr32(0x7c00);
1da177e4
LT		 7032
7033 tw32(0x7c00, val | (1 << 25));
7034 }
7035
7036 /* Reprobe ASF enable state. */
7037 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7038 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7039 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7040 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7041 u32 nic_cfg;
7042
7043 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7044 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7045 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 7046 tp->last_event_jiffies = jiffies;
cbf46853 7047 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7048 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7049 }
7050 }
7051
7052 return 0;
7053}
7054
7055/* tp->lock is held. */
7056static void tg3_stop_fw(struct tg3 *tp)
7057{
0d3031d9
MC		 7058 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7059 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7060 /* Wait for RX cpu to ACK the previous event. */
7061 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7062
7063 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7064
7065 tg3_generate_fw_event(tp);
1da177e4 7066
7c5026aa
MC		 7067 /* Wait for RX cpu to ACK this event. */
7068 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7069 }
7070}
7071
7072/* tp->lock is held. */
944d980e 7073static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7074{
7075 int err;
7076
7077 tg3_stop_fw(tp);
7078
944d980e 7079 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7080
b3b7d6be 7081 tg3_abort_hw(tp, silent);
1da177e4
LT		 7082 err = tg3_chip_reset(tp);
7083
daba2a63
MC		 7084 __tg3_set_mac_addr(tp, 0);
7085
944d980e
MC		 7086 tg3_write_sig_legacy(tp, kind);
7087 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7088
7089 if (err)
7090 return err;
7091
7092 return 0;
7093}
7094
1da177e4
LT		 7095#define RX_CPU_SCRATCH_BASE 0x30000
7096#define RX_CPU_SCRATCH_SIZE 0x04000
7097#define TX_CPU_SCRATCH_BASE 0x34000
7098#define TX_CPU_SCRATCH_SIZE 0x04000
7099
7100/* tp->lock is held. */
7101static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7102{
7103 int i;
7104
5d9428de
ES		 7105 BUG_ON(offset == TX_CPU_BASE &&
7106 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7107
b5d3772c
MC		 7108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7109 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7110
7111 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7112 return 0;
7113 }
1da177e4
LT		 7114 if (offset == RX_CPU_BASE) {
7115 for (i = 0; i < 10000; i++) {
7116 tw32(offset + CPU_STATE, 0xffffffff);
7117 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7118 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7119 break;
7120 }
7121
7122 tw32(offset + CPU_STATE, 0xffffffff);
7123 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7124 udelay(10);
7125 } else {
7126 for (i = 0; i < 10000; i++) {
7127 tw32(offset + CPU_STATE, 0xffffffff);
7128 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7129 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7130 break;
7131 }
7132 }
7133
7134 if (i >= 10000) {
05dbe005
JP		 7135 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7136 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
1da177e4
LT		 7137 return -ENODEV;
7138 }
ec41c7df
MC		 7139
7140 /* Clear firmware's nvram arbitration. */
7141 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7142 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7143 return 0;
7144}
7145
7146struct fw_info {
077f849d
JSR		 7147 unsigned int fw_base;
7148 unsigned int fw_len;
7149 const __be32 *fw_data;
1da177e4
LT		 7150};
7151
7152/* tp->lock is held. */
7153static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7154 int cpu_scratch_size, struct fw_info *info)
7155{
ec41c7df 7156 int err, lock_err, i;
1da177e4
LT		 7157 void (*write_op)(struct tg3 *, u32, u32);
7158
7159 if (cpu_base == TX_CPU_BASE &&
7160 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
05dbe005
JP		 7161 netdev_err(tp->dev, "%s: Trying to load TX cpu firmware which is 5705\n",
7162 __func__);
1da177e4
LT		 7163 return -EINVAL;
7164 }
7165
7166 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7167 write_op = tg3_write_mem;
7168 else
7169 write_op = tg3_write_indirect_reg32;
7170
1b628151
MC		 7171 /* It is possible that bootcode is still loading at this point.
7172 * Get the nvram lock first before halting the cpu.
7173 */
ec41c7df 7174 lock_err = tg3_nvram_lock(tp);
1da177e4 7175 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7176 if (!lock_err)
7177 tg3_nvram_unlock(tp);
1da177e4
LT		 7178 if (err)
7179 goto out;
7180
7181 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7182 write_op(tp, cpu_scratch_base + i, 0);
7183 tw32(cpu_base + CPU_STATE, 0xffffffff);
7184 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7185 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7186 write_op(tp, (cpu_scratch_base +
077f849d 7187 (info->fw_base & 0xffff) +
1da177e4 7188 (i * sizeof(u32))),
077f849d 7189 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7190
7191 err = 0;
7192
7193out:
1da177e4
LT		 7194 return err;
7195}
7196
7197/* tp->lock is held. */
7198static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7199{
7200 struct fw_info info;
077f849d 7201 const __be32 *fw_data;
1da177e4
LT		 7202 int err, i;
7203
077f849d
JSR		 7204 fw_data = (void *)tp->fw->data;
7205
7206 /* Firmware blob starts with version numbers, followed by
7207 start address and length. We are setting complete length.
7208 length = end_address_of_bss - start_address_of_text.
7209 Remainder is the blob to be loaded contiguously
7210 from start address. */
7211
7212 info.fw_base = be32_to_cpu(fw_data[1]);
7213 info.fw_len = tp->fw->size - 12;
7214 info.fw_data = &fw_data[3];
1da177e4
LT		 7215
7216 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7217 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7218 &info);
7219 if (err)
7220 return err;
7221
7222 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7223 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7224 &info);
7225 if (err)
7226 return err;
7227
7228 /* Now startup only the RX cpu. */
7229 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7230 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7231
7232 for (i = 0; i < 5; i++) {
077f849d 7233 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7234 break;
7235 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7236 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7237 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7238 udelay(1000);
7239 }
7240 if (i >= 5) {
05dbe005
JP		 7241 netdev_err(tp->dev, "tg3_load_firmware fails to set RX CPU PC, is %08x should be %08x\n",
7242 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
1da177e4
LT		 7243 return -ENODEV;
7244 }
7245 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7246 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7247
7248 return 0;
7249}
7250
1da177e4 7251/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7252
7253/* tp->lock is held. */
7254static int tg3_load_tso_firmware(struct tg3 *tp)
7255{
7256 struct fw_info info;
077f849d 7257 const __be32 *fw_data;
1da177e4
LT		 7258 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7259 int err, i;
7260
7261 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7262 return 0;
7263
077f849d
JSR		 7264 fw_data = (void *)tp->fw->data;
7265
7266 /* Firmware blob starts with version numbers, followed by
7267 start address and length. We are setting complete length.
7268 length = end_address_of_bss - start_address_of_text.
7269 Remainder is the blob to be loaded contiguously
7270 from start address. */
7271
7272 info.fw_base = be32_to_cpu(fw_data[1]);
7273 cpu_scratch_size = tp->fw_len;
7274 info.fw_len = tp->fw->size - 12;
7275 info.fw_data = &fw_data[3];
7276
1da177e4 7277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7278 cpu_base = RX_CPU_BASE;
7279 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7280 } else {
1da177e4
LT		 7281 cpu_base = TX_CPU_BASE;
7282 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7283 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7284 }
7285
7286 err = tg3_load_firmware_cpu(tp, cpu_base,
7287 cpu_scratch_base, cpu_scratch_size,
7288 &info);
7289 if (err)
7290 return err;
7291
7292 /* Now startup the cpu. */
7293 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7294 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7295
7296 for (i = 0; i < 5; i++) {
077f849d 7297 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7298 break;
7299 tw32(cpu_base + CPU_STATE, 0xffffffff);
7300 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7301 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7302 udelay(1000);
7303 }
7304 if (i >= 5) {
05dbe005
JP		 7305 netdev_err(tp->dev, "%s fails to set CPU PC, is %08x should be %08x\n",
7306 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
1da177e4
LT		 7307 return -ENODEV;
7308 }
7309 tw32(cpu_base + CPU_STATE, 0xffffffff);
7310 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7311 return 0;
7312}
7313
1da177e4 7314
1da177e4
LT		 7315static int tg3_set_mac_addr(struct net_device *dev, void *p)
7316{
7317 struct tg3 *tp = netdev_priv(dev);
7318 struct sockaddr *addr = p;
986e0aeb 7319 int err = 0, skip_mac_1 = 0;
1da177e4 7320
f9804ddb
MC		 7321 if (!is_valid_ether_addr(addr->sa_data))
7322 return -EINVAL;
7323
1da177e4
LT		 7324 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7325
e75f7c90
MC		 7326 if (!netif_running(dev))
7327 return 0;
7328
58712ef9 7329 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7330 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7331
986e0aeb
MC		 7332 addr0_high = tr32(MAC_ADDR_0_HIGH);
7333 addr0_low = tr32(MAC_ADDR_0_LOW);
7334 addr1_high = tr32(MAC_ADDR_1_HIGH);
7335 addr1_low = tr32(MAC_ADDR_1_LOW);
7336
7337 /* Skip MAC addr 1 if ASF is using it. */
7338 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7339 !(addr1_high == 0 && addr1_low == 0))
7340 skip_mac_1 = 1;
58712ef9 7341 }
986e0aeb
MC		 7342 spin_lock_bh(&tp->lock);
7343 __tg3_set_mac_addr(tp, skip_mac_1);
7344 spin_unlock_bh(&tp->lock);
1da177e4 7345
b9ec6c1b 7346 return err;
1da177e4
LT		 7347}
7348
7349/* tp->lock is held. */
7350static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7351 dma_addr_t mapping, u32 maxlen_flags,
7352 u32 nic_addr)
7353{
7354 tg3_write_mem(tp,
7355 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7356 ((u64) mapping >> 32));
7357 tg3_write_mem(tp,
7358 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7359 ((u64) mapping & 0xffffffff));
7360 tg3_write_mem(tp,
7361 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7362 maxlen_flags);
7363
7364 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7365 tg3_write_mem(tp,
7366 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7367 nic_addr);
7368}
7369
7370static void __tg3_set_rx_mode(struct net_device *);
d244c892 7371static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7372{
b6080e12
MC		 7373 int i;
7374
19cfaecc 7375 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7376 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7377 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7378 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7379 } else {
7380 tw32(HOSTCC_TXCOL_TICKS, 0);
7381 tw32(HOSTCC_TXMAX_FRAMES, 0);
7382 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7383 }
b6080e12 7384
19cfaecc
MC		 7385 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7386 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7387 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7388 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7389 } else {
b6080e12
MC		 7390 tw32(HOSTCC_RXCOL_TICKS, 0);
7391 tw32(HOSTCC_RXMAX_FRAMES, 0);
7392 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7393 }
b6080e12 7394
15f9850d
DM		 7395 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7396 u32 val = ec->stats_block_coalesce_usecs;
7397
b6080e12
MC		 7398 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7399 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7400
15f9850d
DM		 7401 if (!netif_carrier_ok(tp->dev))
7402 val = 0;
7403
7404 tw32(HOSTCC_STAT_COAL_TICKS, val);
7405 }
b6080e12
MC		 7406
7407 for (i = 0; i < tp->irq_cnt - 1; i++) {
7408 u32 reg;
7409
7410 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7411 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7412 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7413 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7414 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7415 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7416
7417 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7418 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7419 tw32(reg, ec->tx_coalesce_usecs);
7420 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7421 tw32(reg, ec->tx_max_coalesced_frames);
7422 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7423 tw32(reg, ec->tx_max_coalesced_frames_irq);
7424 }
b6080e12
MC		 7425 }
7426
7427 for (; i < tp->irq_max - 1; i++) {
7428 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7429 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7430 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7431
7432 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7433 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7434 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7435 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7436 }
b6080e12 7437 }
15f9850d 7438}
1da177e4 7439
2d31ecaf
MC		 7440/* tp->lock is held. */
7441static void tg3_rings_reset(struct tg3 *tp)
7442{
7443 int i;
f77a6a8e 7444 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7445 struct tg3_napi *tnapi = &tp->napi[0];
7446
7447 /* Disable all transmit rings but the first. */
7448 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7449 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7450 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7451 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7452 else
7453 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7454
7455 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7456 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7457 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7458 BDINFO_FLAGS_DISABLED);
7459
7460
7461 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7463 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7464 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7465 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7466 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7468 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7469 else
7470 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7471
7472 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7473 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7474 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7475 BDINFO_FLAGS_DISABLED);
7476
7477 /* Disable interrupts */
7478 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7479
7480 /* Zero mailbox registers. */
f77a6a8e
MC		 7481 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7482 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7483 tp->napi[i].tx_prod = 0;
7484 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7485 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7486 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7487 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7488 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7489 }
c2353a32
MC		 7490 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7491 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7492 } else {
7493 tp->napi[0].tx_prod = 0;
7494 tp->napi[0].tx_cons = 0;
7495 tw32_mailbox(tp->napi[0].prodmbox, 0);
7496 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7497 }
2d31ecaf
MC		 7498
7499 /* Make sure the NIC-based send BD rings are disabled. */
7500 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7501 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7502 for (i = 0; i < 16; i++)
7503 tw32_tx_mbox(mbox + i * 8, 0);
7504 }
7505
7506 txrcb = NIC_SRAM_SEND_RCB;
7507 rxrcb = NIC_SRAM_RCV_RET_RCB;
7508
7509 /* Clear status block in ram. */
7510 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7511
7512 /* Set status block DMA address */
7513 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7514 ((u64) tnapi->status_mapping >> 32));
7515 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7516 ((u64) tnapi->status_mapping & 0xffffffff));
7517
f77a6a8e
MC		 7518 if (tnapi->tx_ring) {
7519 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7520 (TG3_TX_RING_SIZE <<
7521 BDINFO_FLAGS_MAXLEN_SHIFT),
7522 NIC_SRAM_TX_BUFFER_DESC);
7523 txrcb += TG3_BDINFO_SIZE;
7524 }
7525
7526 if (tnapi->rx_rcb) {
7527 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7528 (TG3_RX_RCB_RING_SIZE(tp) <<
7529 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7530 rxrcb += TG3_BDINFO_SIZE;
7531 }
7532
7533 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7534
f77a6a8e
MC		 7535 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7536 u64 mapping = (u64)tnapi->status_mapping;
7537 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7538 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7539
7540 /* Clear status block in ram. */
7541 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7542
19cfaecc
MC		 7543 if (tnapi->tx_ring) {
7544 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7545 (TG3_TX_RING_SIZE <<
7546 BDINFO_FLAGS_MAXLEN_SHIFT),
7547 NIC_SRAM_TX_BUFFER_DESC);
7548 txrcb += TG3_BDINFO_SIZE;
7549 }
f77a6a8e
MC		 7550
7551 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7552 (TG3_RX_RCB_RING_SIZE(tp) <<
7553 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7554
7555 stblk += 8;
f77a6a8e
MC		 7556 rxrcb += TG3_BDINFO_SIZE;
7557 }
2d31ecaf
MC		 7558}
7559
1da177e4 7560/* tp->lock is held. */
8e7a22e3 7561static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7562{
7563 u32 val, rdmac_mode;
7564 int i, err, limit;
21f581a5 7565 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7566
7567 tg3_disable_ints(tp);
7568
7569 tg3_stop_fw(tp);
7570
7571 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7572
7573 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7574 tg3_abort_hw(tp, 1);
1da177e4
LT		 7575 }
7576
603f1173 7577 if (reset_phy)
d4d2c558
MC		 7578 tg3_phy_reset(tp);
7579
1da177e4
LT		 7580 err = tg3_chip_reset(tp);
7581 if (err)
7582 return err;
7583
7584 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7585
bcb37f6c 7586 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7587 val = tr32(TG3_CPMU_CTRL);
7588 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7589 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7590
7591 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7592 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7593 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7594 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7595
7596 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7597 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7598 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7599 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7600
7601 val = tr32(TG3_CPMU_HST_ACC);
7602 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7603 val |= CPMU_HST_ACC_MACCLK_6_25;
7604 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7605 }
7606
33466d93
MC		 7607 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7608 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7609 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7610 PCIE_PWR_MGMT_L1_THRESH_4MS;
7611 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7612
7613 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7614 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7615
7616 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7617
f40386c8
MC		 7618 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7619 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7620 }
7621
614b0590
MC		 7622 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7623 u32 grc_mode = tr32(GRC_MODE);
7624
7625 /* Access the lower 1K of PL PCIE block registers. */
7626 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7627 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7628
7629 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7630 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7631 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7632
7633 tw32(GRC_MODE, grc_mode);
7634 }
7635
1da177e4
LT		 7636 /* This works around an issue with Athlon chipsets on
7637 * B3 tigon3 silicon. This bit has no effect on any
7638 * other revision. But do not set this on PCI Express
795d01c5 7639 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7640 */
795d01c5
MC		 7641 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7642 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7643 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7644 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7645 }
1da177e4
LT		 7646
7647 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7648 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7649 val = tr32(TG3PCI_PCISTATE);
7650 val |= PCISTATE_RETRY_SAME_DMA;
7651 tw32(TG3PCI_PCISTATE, val);
7652 }
7653
0d3031d9
MC		 7654 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7655 /* Allow reads and writes to the
7656 * APE register and memory space.
7657 */
7658 val = tr32(TG3PCI_PCISTATE);
7659 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7660 PCISTATE_ALLOW_APE_SHMEM_WR;
7661 tw32(TG3PCI_PCISTATE, val);
7662 }
7663
1da177e4
LT		 7664 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7665 /* Enable some hw fixes. */
7666 val = tr32(TG3PCI_MSI_DATA);
7667 val |= (1 << 26) | (1 << 28) | (1 << 29);
7668 tw32(TG3PCI_MSI_DATA, val);
7669 }
7670
7671 /* Descriptor ring init may make accesses to the
7672 * NIC SRAM area to setup the TX descriptors, so we
7673 * can only do this after the hardware has been
7674 * successfully reset.
7675 */
32d8c572
MC		 7676 err = tg3_init_rings(tp);
7677 if (err)
7678 return err;
1da177e4 7679
b703df6f
MC		 7680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7682 val = tr32(TG3PCI_DMA_RW_CTRL) &
7683 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7684 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7685 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7686 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7687 /* This value is determined during the probe time DMA
7688 * engine test, tg3_test_dma.
7689 */
7690 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7691 }
1da177e4
LT		 7692
7693 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7694 GRC_MODE_4X_NIC_SEND_RINGS |
7695 GRC_MODE_NO_TX_PHDR_CSUM |
7696 GRC_MODE_NO_RX_PHDR_CSUM);
7697 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7698
7699 /* Pseudo-header checksum is done by hardware logic and not
7700 * the offload processers, so make the chip do the pseudo-
7701 * header checksums on receive. For transmit it is more
7702 * convenient to do the pseudo-header checksum in software
7703 * as Linux does that on transmit for us in all cases.
7704 */
7705 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7706
7707 tw32(GRC_MODE,
7708 tp->grc_mode |
7709 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7710
7711 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7712 val = tr32(GRC_MISC_CFG);
7713 val &= ~0xff;
7714 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7715 tw32(GRC_MISC_CFG, val);
7716
7717 /* Initialize MBUF/DESC pool. */
cbf46853 7718 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7719 /* Do nothing. */
7720 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7721 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7722 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7723 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7724 else
7725 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7726 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7727 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7728 }
1da177e4
LT		 7729 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7730 int fw_len;
7731
077f849d 7732 fw_len = tp->fw_len;
1da177e4
LT		 7733 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7734 tw32(BUFMGR_MB_POOL_ADDR,
7735 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7736 tw32(BUFMGR_MB_POOL_SIZE,
7737 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7738 }
1da177e4 7739
0f893dc6 7740 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7741 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7742 tp->bufmgr_config.mbuf_read_dma_low_water);
7743 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7744 tp->bufmgr_config.mbuf_mac_rx_low_water);
7745 tw32(BUFMGR_MB_HIGH_WATER,
7746 tp->bufmgr_config.mbuf_high_water);
7747 } else {
7748 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7749 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7750 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7751 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7752 tw32(BUFMGR_MB_HIGH_WATER,
7753 tp->bufmgr_config.mbuf_high_water_jumbo);
7754 }
7755 tw32(BUFMGR_DMA_LOW_WATER,
7756 tp->bufmgr_config.dma_low_water);
7757 tw32(BUFMGR_DMA_HIGH_WATER,
7758 tp->bufmgr_config.dma_high_water);
7759
7760 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7761 for (i = 0; i < 2000; i++) {
7762 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7763 break;
7764 udelay(10);
7765 }
7766 if (i >= 2000) {
05dbe005 7767 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 7768 return -ENODEV;
7769 }
7770
7771 /* Setup replenish threshold. */
f92905de
MC		 7772 val = tp->rx_pending / 8;
7773 if (val == 0)
7774 val = 1;
7775 else if (val > tp->rx_std_max_post)
7776 val = tp->rx_std_max_post;
b5d3772c
MC		 7777 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7778 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7779 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7780
7781 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7782 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7783 }
f92905de
MC		 7784
7785 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7786
7787 /* Initialize TG3_BDINFO's at:
7788 * RCVDBDI_STD_BD: standard eth size rx ring
7789 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7790 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7791 *
7792 * like so:
7793 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7794 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7795 * ring attribute flags
7796 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7797 *
7798 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7799 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7800 *
7801 * The size of each ring is fixed in the firmware, but the location is
7802 * configurable.
7803 */
7804 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7805 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7806 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7807 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7808 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7809 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7810 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7811
fdb72b38
MC		 7812 /* Disable the mini ring */
7813 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7814 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7815 BDINFO_FLAGS_DISABLED);
7816
fdb72b38
MC		 7817 /* Program the jumbo buffer descriptor ring control
7818 * blocks on those devices that have them.
7819 */
8f666b07 7820 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7821 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7822 /* Setup replenish threshold. */
7823 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7824
0f893dc6 7825 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7826 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7827 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7828 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7829 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7830 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7831 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7832 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7833 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7834 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7835 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7836 } else {
7837 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7838 BDINFO_FLAGS_DISABLED);
7839 }
7840
b703df6f
MC		 7841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7843 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7844 (RX_STD_MAX_SIZE << 2);
7845 else
7846 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7847 } else
7848 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7849
7850 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7851
411da640 7852 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7853 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7854
411da640 7855 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7856 tp->rx_jumbo_pending : 0;
66711e66 7857 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7858
b703df6f
MC		 7859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7860 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7861 tw32(STD_REPLENISH_LWM, 32);
7862 tw32(JMB_REPLENISH_LWM, 16);
7863 }
7864
2d31ecaf
MC		 7865 tg3_rings_reset(tp);
7866
1da177e4 7867 /* Initialize MAC address and backoff seed. */
986e0aeb 7868 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7869
7870 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7871 tw32(MAC_RX_MTU_SIZE,
7872 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7873
7874 /* The slot time is changed by tg3_setup_phy if we
7875 * run at gigabit with half duplex.
7876 */
7877 tw32(MAC_TX_LENGTHS,
7878 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7879 (6 << TX_LENGTHS_IPG_SHIFT) |
7880 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7881
7882 /* Receive rules. */
7883 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7884 tw32(RCVLPC_CONFIG, 0x0181);
7885
7886 /* Calculate RDMAC_MODE setting early, we need it to determine
7887 * the RCVLPC_STATE_ENABLE mask.
7888 */
7889 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7890 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7891 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7892 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7893 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7894
0339e4e3
MC		 7895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7896 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7897
57e6983c 7898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7900 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7901 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7902 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7903 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7904
85e94ced
MC		 7905 /* If statement applies to 5705 and 5750 PCI devices only */
7906 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7907 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7908 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7909 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7911 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7912 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7913 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7914 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7915 }
7916 }
7917
85e94ced
MC		 7918 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7919 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7920
1da177e4 7921 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7922 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7923
e849cdc3
MC		 7924 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7927 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7928
7929 /* Receive/send statistics. */
1661394e
MC		 7930 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7931 val = tr32(RCVLPC_STATS_ENABLE);
7932 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7933 tw32(RCVLPC_STATS_ENABLE, val);
7934 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7935 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7936 val = tr32(RCVLPC_STATS_ENABLE);
7937 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7938 tw32(RCVLPC_STATS_ENABLE, val);
7939 } else {
7940 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7941 }
7942 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7943 tw32(SNDDATAI_STATSENAB, 0xffffff);
7944 tw32(SNDDATAI_STATSCTRL,
7945 (SNDDATAI_SCTRL_ENABLE |
7946 SNDDATAI_SCTRL_FASTUPD));
7947
7948 /* Setup host coalescing engine. */
7949 tw32(HOSTCC_MODE, 0);
7950 for (i = 0; i < 2000; i++) {
7951 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7952 break;
7953 udelay(10);
7954 }
7955
d244c892 7956 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7957
1da177e4
LT		 7958 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7959 /* Status/statistics block address. See tg3_timer,
7960 * the tg3_periodic_fetch_stats call there, and
7961 * tg3_get_stats to see how this works for 5705/5750 chips.
7962 */
1da177e4
LT		 7963 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7964 ((u64) tp->stats_mapping >> 32));
7965 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7966 ((u64) tp->stats_mapping & 0xffffffff));
7967 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7968
1da177e4 7969 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7970
7971 /* Clear statistics and status block memory areas */
7972 for (i = NIC_SRAM_STATS_BLK;
7973 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7974 i += sizeof(u32)) {
7975 tg3_write_mem(tp, i, 0);
7976 udelay(40);
7977 }
1da177e4
LT		 7978 }
7979
7980 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7981
7982 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7983 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7984 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7985 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7986
c94e3941
MC		 7987 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7988 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7989 /* reset to prevent losing 1st rx packet intermittently */
7990 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7991 udelay(10);
7992 }
7993
3bda1258
MC		 7994 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7995 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7996 else
7997 tp->mac_mode = 0;
7998 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7999 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 8000 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8001 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8002 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8003 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 8004 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8005 udelay(40);
8006
314fba34 8007 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 8008 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 8009 * register to preserve the GPIO settings for LOMs. The GPIOs,
8010 * whether used as inputs or outputs, are set by boot code after
8011 * reset.
8012 */
9d26e213 8013 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 8014 u32 gpio_mask;
8015
9d26e213
MC		 8016 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8017 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8018 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 8019
8020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8021 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8022 GRC_LCLCTRL_GPIO_OUTPUT3;
8023
af36e6b6
MC		 8024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8025 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8026
aaf84465 8027 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 8028 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8029
8030 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 8031 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8032 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8033 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 8034 }
1da177e4
LT		 8035 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8036 udelay(100);
8037
baf8a94a
MC		 8038 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8039 val = tr32(MSGINT_MODE);
8040 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8041 tw32(MSGINT_MODE, val);
8042 }
8043
1da177e4
LT		 8044 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8045 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8046 udelay(40);
8047 }
8048
8049 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8050 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8051 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8052 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8053 WDMAC_MODE_LNGREAD_ENAB);
8054
85e94ced
MC		 8055 /* If statement applies to 5705 and 5750 PCI devices only */
8056 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8057 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8059 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8060 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8061 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8062 /* nothing */
8063 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8064 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8065 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8066 val |= WDMAC_MODE_RX_ACCEL;
8067 }
8068 }
8069
d9ab5ad1 8070 /* Enable host coalescing bug fix */
321d32a0 8071 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8072 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8073
788a035e
MC		 8074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8075 val |= WDMAC_MODE_BURST_ALL_DATA;
8076
1da177e4
LT		 8077 tw32_f(WDMAC_MODE, val);
8078 udelay(40);
8079
9974a356
MC		 8080 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8081 u16 pcix_cmd;
8082
8083 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8084 &pcix_cmd);
1da177e4 8085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8086 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8087 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8088 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8089 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8090 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8091 }
9974a356
MC		 8092 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8093 pcix_cmd);
1da177e4
LT		 8094 }
8095
8096 tw32_f(RDMAC_MODE, rdmac_mode);
8097 udelay(40);
8098
8099 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8100 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8101 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8102
8103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8104 tw32(SNDDATAC_MODE,
8105 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8106 else
8107 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8108
1da177e4
LT		 8109 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8110 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8111 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8112 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8113 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8114 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8115 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8116 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8117 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8118 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8119 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8120
8121 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8122 err = tg3_load_5701_a0_firmware_fix(tp);
8123 if (err)
8124 return err;
8125 }
8126
1da177e4
LT		 8127 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8128 err = tg3_load_tso_firmware(tp);
8129 if (err)
8130 return err;
8131 }
1da177e4
LT		 8132
8133 tp->tx_mode = TX_MODE_ENABLE;
8134 tw32_f(MAC_TX_MODE, tp->tx_mode);
8135 udelay(100);
8136
baf8a94a
MC		 8137 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8138 u32 reg = MAC_RSS_INDIR_TBL_0;
8139 u8 *ent = (u8 *)&val;
8140
8141 /* Setup the indirection table */
8142 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8143 int idx = i % sizeof(val);
8144
8145 ent[idx] = i % (tp->irq_cnt - 1);
8146 if (idx == sizeof(val) - 1) {
8147 tw32(reg, val);
8148 reg += 4;
8149 }
8150 }
8151
8152 /* Setup the "secret" hash key. */
8153 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8154 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8155 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8156 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8157 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8158 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8159 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8160 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8161 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8162 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8163 }
8164
1da177e4 8165 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8166 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8167 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8168
baf8a94a
MC		 8169 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8170 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8171 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8172 RX_MODE_RSS_IPV6_HASH_EN |
8173 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8174 RX_MODE_RSS_IPV4_HASH_EN |
8175 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8176
1da177e4
LT		 8177 tw32_f(MAC_RX_MODE, tp->rx_mode);
8178 udelay(10);
8179
1da177e4
LT		 8180 tw32(MAC_LED_CTRL, tp->led_ctrl);
8181
8182 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8183 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8184 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8185 udelay(10);
8186 }
8187 tw32_f(MAC_RX_MODE, tp->rx_mode);
8188 udelay(10);
8189
8190 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8191 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8192 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8193 /* Set drive transmission level to 1.2V */
8194 /* only if the signal pre-emphasis bit is not set */
8195 val = tr32(MAC_SERDES_CFG);
8196 val &= 0xfffff000;
8197 val |= 0x880;
8198 tw32(MAC_SERDES_CFG, val);
8199 }
8200 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8201 tw32(MAC_SERDES_CFG, 0x616000);
8202 }
8203
8204 /* Prevent chip from dropping frames when flow control
8205 * is enabled.
8206 */
666bc831
MC		 8207 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8208 val = 1;
8209 else
8210 val = 2;
8211 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8212
8213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8214 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8215 /* Use hardware link auto-negotiation */
8216 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8217 }
8218
d4d2c558
MC		 8219 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8220 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8221 u32 tmp;
8222
8223 tmp = tr32(SERDES_RX_CTRL);
8224 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8225 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8226 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8227 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8228 }
8229
dd477003
MC		 8230 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8231 if (tp->link_config.phy_is_low_power) {
8232 tp->link_config.phy_is_low_power = 0;
8233 tp->link_config.speed = tp->link_config.orig_speed;
8234 tp->link_config.duplex = tp->link_config.orig_duplex;
8235 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8236 }
1da177e4 8237
dd477003
MC		 8238 err = tg3_setup_phy(tp, 0);
8239 if (err)
8240 return err;
1da177e4 8241
dd477003 8242 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8243 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8244 u32 tmp;
8245
8246 /* Clear CRC stats. */
8247 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8248 tg3_writephy(tp, MII_TG3_TEST1,
8249 tmp | MII_TG3_TEST1_CRC_EN);
8250 tg3_readphy(tp, 0x14, &tmp);
8251 }
1da177e4
LT		 8252 }
8253 }
8254
8255 __tg3_set_rx_mode(tp->dev);
8256
8257 /* Initialize receive rules. */
8258 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8259 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8260 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8261 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8262
4cf78e4f 8263 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8264 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8265 limit = 8;
8266 else
8267 limit = 16;
8268 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8269 limit -= 4;
8270 switch (limit) {
8271 case 16:
8272 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8273 case 15:
8274 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8275 case 14:
8276 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8277 case 13:
8278 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8279 case 12:
8280 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8281 case 11:
8282 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8283 case 10:
8284 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8285 case 9:
8286 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8287 case 8:
8288 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8289 case 7:
8290 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8291 case 6:
8292 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8293 case 5:
8294 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8295 case 4:
8296 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8297 case 3:
8298 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8299 case 2:
8300 case 1:
8301
8302 default:
8303 break;
855e1111 8304 }
1da177e4 8305
9ce768ea
MC		 8306 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8307 /* Write our heartbeat update interval to APE. */
8308 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8309 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8310
1da177e4
LT		 8311 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8312
1da177e4
LT		 8313 return 0;
8314}
8315
8316/* Called at device open time to get the chip ready for
8317 * packet processing. Invoked with tp->lock held.
8318 */
8e7a22e3 8319static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8320{
1da177e4
LT		 8321 tg3_switch_clocks(tp);
8322
8323 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8324
2f751b67 8325 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8326}
8327
8328#define TG3_STAT_ADD32(PSTAT, REG) \
8329do { u32 __val = tr32(REG); \
8330 (PSTAT)->low += __val; \
8331 if ((PSTAT)->low < __val) \
8332 (PSTAT)->high += 1; \
8333} while (0)
8334
8335static void tg3_periodic_fetch_stats(struct tg3 *tp)
8336{
8337 struct tg3_hw_stats *sp = tp->hw_stats;
8338
8339 if (!netif_carrier_ok(tp->dev))
8340 return;
8341
8342 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8343 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8344 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8345 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8346 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8347 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8348 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8349 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8350 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8351 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8352 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8353 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8354 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8355
8356 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8357 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8358 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8359 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8360 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8361 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8362 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8363 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8364 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8365 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8366 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8367 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8368 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8369 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8370
8371 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8372 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8373 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8374}
8375
8376static void tg3_timer(unsigned long __opaque)
8377{
8378 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8379
f475f163
MC		 8380 if (tp->irq_sync)
8381 goto restart_timer;
8382
f47c11ee 8383 spin_lock(&tp->lock);
1da177e4 8384
fac9b83e
DM		 8385 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8386 /* All of this garbage is because when using non-tagged
8387 * IRQ status the mailbox/status_block protocol the chip
8388 * uses with the cpu is race prone.
8389 */
898a56f8 8390 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8391 tw32(GRC_LOCAL_CTRL,
8392 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8393 } else {
8394 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8395 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8396 }
1da177e4 8397
fac9b83e
DM		 8398 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8399 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8400 spin_unlock(&tp->lock);
fac9b83e
DM		 8401 schedule_work(&tp->reset_task);
8402 return;
8403 }
1da177e4
LT		 8404 }
8405
1da177e4
LT		 8406 /* This part only runs once per second. */
8407 if (!--tp->timer_counter) {
fac9b83e
DM		 8408 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8409 tg3_periodic_fetch_stats(tp);
8410
1da177e4
LT		 8411 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8412 u32 mac_stat;
8413 int phy_event;
8414
8415 mac_stat = tr32(MAC_STATUS);
8416
8417 phy_event = 0;
8418 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8419 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8420 phy_event = 1;
8421 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8422 phy_event = 1;
8423
8424 if (phy_event)
8425 tg3_setup_phy(tp, 0);
8426 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8427 u32 mac_stat = tr32(MAC_STATUS);
8428 int need_setup = 0;
8429
8430 if (netif_carrier_ok(tp->dev) &&
8431 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8432 need_setup = 1;
8433 }
8434 if (! netif_carrier_ok(tp->dev) &&
8435 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8436 MAC_STATUS_SIGNAL_DET))) {
8437 need_setup = 1;
8438 }
8439 if (need_setup) {
3d3ebe74
MC		 8440 if (!tp->serdes_counter) {
8441 tw32_f(MAC_MODE,
8442 (tp->mac_mode &
8443 ~MAC_MODE_PORT_MODE_MASK));
8444 udelay(40);
8445 tw32_f(MAC_MODE, tp->mac_mode);
8446 udelay(40);
8447 }
1da177e4
LT		 8448 tg3_setup_phy(tp, 0);
8449 }
747e8f8b
MC		 8450 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8451 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8452
8453 tp->timer_counter = tp->timer_multiplier;
8454 }
8455
130b8e4d
MC		 8456 /* Heartbeat is only sent once every 2 seconds.
8457 *
8458 * The heartbeat is to tell the ASF firmware that the host
8459 * driver is still alive. In the event that the OS crashes,
8460 * ASF needs to reset the hardware to free up the FIFO space
8461 * that may be filled with rx packets destined for the host.
8462 * If the FIFO is full, ASF will no longer function properly.
8463 *
8464 * Unintended resets have been reported on real time kernels
8465 * where the timer doesn't run on time. Netpoll will also have
8466 * same problem.
8467 *
8468 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8469 * to check the ring condition when the heartbeat is expiring
8470 * before doing the reset. This will prevent most unintended
8471 * resets.
8472 */
1da177e4 8473 if (!--tp->asf_counter) {
bc7959b2
MC		 8474 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8475 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8476 tg3_wait_for_event_ack(tp);
8477
bbadf503 8478 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8479 FWCMD_NICDRV_ALIVE3);
bbadf503 8480 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8481 /* 5 seconds timeout */
bbadf503 8482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8483
8484 tg3_generate_fw_event(tp);
1da177e4
LT		 8485 }
8486 tp->asf_counter = tp->asf_multiplier;
8487 }
8488
f47c11ee 8489 spin_unlock(&tp->lock);
1da177e4 8490
f475f163 8491restart_timer:
1da177e4
LT		 8492 tp->timer.expires = jiffies + tp->timer_offset;
8493 add_timer(&tp->timer);
8494}
8495
4f125f42 8496static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8497{
7d12e780 8498 irq_handler_t fn;
fcfa0a32 8499 unsigned long flags;
4f125f42
MC		 8500 char *name;
8501 struct tg3_napi *tnapi = &tp->napi[irq_num];
8502
8503 if (tp->irq_cnt == 1)
8504 name = tp->dev->name;
8505 else {
8506 name = &tnapi->irq_lbl[0];
8507 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8508 name[IFNAMSIZ-1] = 0;
8509 }
fcfa0a32 8510
679563f4 8511 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8512 fn = tg3_msi;
8513 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8514 fn = tg3_msi_1shot;
1fb9df5d 8515 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8516 } else {
8517 fn = tg3_interrupt;
8518 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8519 fn = tg3_interrupt_tagged;
1fb9df5d 8520 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8521 }
4f125f42
MC		 8522
8523 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8524}
8525
7938109f
MC		 8526static int tg3_test_interrupt(struct tg3 *tp)
8527{
09943a18 8528 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8529 struct net_device *dev = tp->dev;
b16250e3 8530 int err, i, intr_ok = 0;
f6eb9b1f 8531 u32 val;
7938109f 8532
d4bc3927
MC		 8533 if (!netif_running(dev))
8534 return -ENODEV;
8535
7938109f
MC		 8536 tg3_disable_ints(tp);
8537
4f125f42 8538 free_irq(tnapi->irq_vec, tnapi);
7938109f 8539
f6eb9b1f
MC		 8540 /*
8541 * Turn off MSI one shot mode. Otherwise this test has no
8542 * observable way to know whether the interrupt was delivered.
8543 */
b703df6f
MC		 8544 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8546 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8547 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8548 tw32(MSGINT_MODE, val);
8549 }
8550
4f125f42 8551 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8552 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8553 if (err)
8554 return err;
8555
898a56f8 8556 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8557 tg3_enable_ints(tp);
8558
8559 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8560 tnapi->coal_now);
7938109f
MC		 8561
8562 for (i = 0; i < 5; i++) {
b16250e3
MC		 8563 u32 int_mbox, misc_host_ctrl;
8564
898a56f8 8565 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8566 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8567
8568 if ((int_mbox != 0) ||
8569 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8570 intr_ok = 1;
7938109f 8571 break;
b16250e3
MC		 8572 }
8573
7938109f
MC		 8574 msleep(10);
8575 }
8576
8577 tg3_disable_ints(tp);
8578
4f125f42 8579 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8580
4f125f42 8581 err = tg3_request_irq(tp, 0);
7938109f
MC		 8582
8583 if (err)
8584 return err;
8585
f6eb9b1f
MC		 8586 if (intr_ok) {
8587 /* Reenable MSI one shot mode. */
b703df6f
MC		 8588 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8589 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8590 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8591 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8592 tw32(MSGINT_MODE, val);
8593 }
7938109f 8594 return 0;
f6eb9b1f 8595 }
7938109f
MC		 8596
8597 return -EIO;
8598}
8599
8600/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8601 * successfully restored
8602 */
8603static int tg3_test_msi(struct tg3 *tp)
8604{
7938109f
MC		 8605 int err;
8606 u16 pci_cmd;
8607
8608 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8609 return 0;
8610
8611 /* Turn off SERR reporting in case MSI terminates with Master
8612 * Abort.
8613 */
8614 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8615 pci_write_config_word(tp->pdev, PCI_COMMAND,
8616 pci_cmd & ~PCI_COMMAND_SERR);
8617
8618 err = tg3_test_interrupt(tp);
8619
8620 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8621
8622 if (!err)
8623 return 0;
8624
8625 /* other failures */
8626 if (err != -EIO)
8627 return err;
8628
8629 /* MSI test failed, go back to INTx mode */
05dbe005
JP		 8630 netdev_warn(tp->dev, "No interrupt was generated using MSI, switching to INTx mode\n"
8631 "Please report this failure to the PCI maintainer and include system chipset information\n");
7938109f 8632
4f125f42 8633 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8634
7938109f
MC		 8635 pci_disable_msi(tp->pdev);
8636
8637 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8638
4f125f42 8639 err = tg3_request_irq(tp, 0);
7938109f
MC		 8640 if (err)
8641 return err;
8642
8643 /* Need to reset the chip because the MSI cycle may have terminated
8644 * with Master Abort.
8645 */
f47c11ee 8646 tg3_full_lock(tp, 1);
7938109f 8647
944d980e 8648 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8649 err = tg3_init_hw(tp, 1);
7938109f 8650
f47c11ee 8651 tg3_full_unlock(tp);
7938109f
MC		 8652
8653 if (err)
4f125f42 8654 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8655
8656 return err;
8657}
8658
9e9fd12d
MC		 8659static int tg3_request_firmware(struct tg3 *tp)
8660{
8661 const __be32 *fw_data;
8662
8663 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 8664 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8665 tp->fw_needed);
9e9fd12d
MC		 8666 return -ENOENT;
8667 }
8668
8669 fw_data = (void *)tp->fw->data;
8670
8671 /* Firmware blob starts with version numbers, followed by
8672 * start address and _full_ length including BSS sections
8673 * (which must be longer than the actual data, of course
8674 */
8675
8676 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8677 if (tp->fw_len < (tp->fw->size - 12)) {
05dbe005
JP		 8678 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8679 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 8680 release_firmware(tp->fw);
8681 tp->fw = NULL;
8682 return -EINVAL;
8683 }
8684
8685 /* We no longer need firmware; we have it. */
8686 tp->fw_needed = NULL;
8687 return 0;
8688}
8689
679563f4
MC		 8690static bool tg3_enable_msix(struct tg3 *tp)
8691{
8692 int i, rc, cpus = num_online_cpus();
8693 struct msix_entry msix_ent[tp->irq_max];
8694
8695 if (cpus == 1)
8696 /* Just fallback to the simpler MSI mode. */
8697 return false;
8698
8699 /*
8700 * We want as many rx rings enabled as there are cpus.
8701 * The first MSIX vector only deals with link interrupts, etc,
8702 * so we add one to the number of vectors we are requesting.
8703 */
8704 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8705
8706 for (i = 0; i < tp->irq_max; i++) {
8707 msix_ent[i].entry = i;
8708 msix_ent[i].vector = 0;
8709 }
8710
8711 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8712 if (rc != 0) {
8713 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8714 return false;
8715 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8716 return false;
05dbe005
JP		 8717 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8718 tp->irq_cnt, rc);
679563f4
MC		 8719 tp->irq_cnt = rc;
8720 }
8721
baf8a94a
MC		 8722 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8723
679563f4
MC		 8724 for (i = 0; i < tp->irq_max; i++)
8725 tp->napi[i].irq_vec = msix_ent[i].vector;
8726
19cfaecc
MC		 8727 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8728 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8729 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8730 } else
8731 tp->dev->real_num_tx_queues = 1;
fe5f5787 8732
679563f4
MC		 8733 return true;
8734}
8735
07b0173c
MC		 8736static void tg3_ints_init(struct tg3 *tp)
8737{
679563f4
MC		 8738 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8739 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8740 /* All MSI supporting chips should support tagged
8741 * status. Assert that this is the case.
8742 */
05dbe005 8743 netdev_warn(tp->dev, "MSI without TAGGED? Not using MSI\n");
679563f4 8744 goto defcfg;
07b0173c 8745 }
4f125f42 8746
679563f4
MC		 8747 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8748 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8749 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8750 pci_enable_msi(tp->pdev) == 0)
8751 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8752
8753 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8754 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8755 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8756 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8757 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8758 }
8759defcfg:
8760 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8761 tp->irq_cnt = 1;
8762 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8763 tp->dev->real_num_tx_queues = 1;
679563f4 8764 }
07b0173c
MC		 8765}
8766
8767static void tg3_ints_fini(struct tg3 *tp)
8768{
679563f4
MC		 8769 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8770 pci_disable_msix(tp->pdev);
8771 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8772 pci_disable_msi(tp->pdev);
8773 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8774 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8775}
8776
1da177e4
LT		 8777static int tg3_open(struct net_device *dev)
8778{
8779 struct tg3 *tp = netdev_priv(dev);
4f125f42 8780 int i, err;
1da177e4 8781
9e9fd12d
MC		 8782 if (tp->fw_needed) {
8783 err = tg3_request_firmware(tp);
8784 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8785 if (err)
8786 return err;
8787 } else if (err) {
05dbe005 8788 netdev_warn(tp->dev, "TSO capability disabled\n");
9e9fd12d
MC		 8789 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8790 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
05dbe005 8791 netdev_notice(tp->dev, "TSO capability restored\n");
9e9fd12d
MC		 8792 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8793 }
8794 }
8795
c49a1561
MC		 8796 netif_carrier_off(tp->dev);
8797
bc1c7567 8798 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8799 if (err)
bc1c7567 8800 return err;
2f751b67
MC		 8801
8802 tg3_full_lock(tp, 0);
bc1c7567 8803
1da177e4
LT		 8804 tg3_disable_ints(tp);
8805 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8806
f47c11ee 8807 tg3_full_unlock(tp);
1da177e4 8808
679563f4
MC		 8809 /*
8810 * Setup interrupts first so we know how
8811 * many NAPI resources to allocate
8812 */
8813 tg3_ints_init(tp);
8814
1da177e4
LT		 8815 /* The placement of this call is tied
8816 * to the setup and use of Host TX descriptors.
8817 */
8818 err = tg3_alloc_consistent(tp);
8819 if (err)
679563f4 8820 goto err_out1;
88b06bc2 8821
fed97810 8822 tg3_napi_enable(tp);
1da177e4 8823
4f125f42
MC		 8824 for (i = 0; i < tp->irq_cnt; i++) {
8825 struct tg3_napi *tnapi = &tp->napi[i];
8826 err = tg3_request_irq(tp, i);
8827 if (err) {
8828 for (i--; i >= 0; i--)
8829 free_irq(tnapi->irq_vec, tnapi);
8830 break;
8831 }
8832 }
1da177e4 8833
07b0173c 8834 if (err)
679563f4 8835 goto err_out2;
bea3348e 8836
f47c11ee 8837 tg3_full_lock(tp, 0);
1da177e4 8838
8e7a22e3 8839 err = tg3_init_hw(tp, 1);
1da177e4 8840 if (err) {
944d980e 8841 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8842 tg3_free_rings(tp);
8843 } else {
fac9b83e
DM		 8844 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8845 tp->timer_offset = HZ;
8846 else
8847 tp->timer_offset = HZ / 10;
8848
8849 BUG_ON(tp->timer_offset > HZ);
8850 tp->timer_counter = tp->timer_multiplier =
8851 (HZ / tp->timer_offset);
8852 tp->asf_counter = tp->asf_multiplier =
28fbef78 8853 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8854
8855 init_timer(&tp->timer);
8856 tp->timer.expires = jiffies + tp->timer_offset;
8857 tp->timer.data = (unsigned long) tp;
8858 tp->timer.function = tg3_timer;
1da177e4
LT		 8859 }
8860
f47c11ee 8861 tg3_full_unlock(tp);
1da177e4 8862
07b0173c 8863 if (err)
679563f4 8864 goto err_out3;
1da177e4 8865
7938109f
MC		 8866 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8867 err = tg3_test_msi(tp);
fac9b83e 8868
7938109f 8869 if (err) {
f47c11ee 8870 tg3_full_lock(tp, 0);
944d980e 8871 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8872 tg3_free_rings(tp);
f47c11ee 8873 tg3_full_unlock(tp);
7938109f 8874
679563f4 8875 goto err_out2;
7938109f 8876 }
fcfa0a32 8877
f6eb9b1f 8878 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8879 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8880 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8881 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8882 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8883
f6eb9b1f
MC		 8884 tw32(PCIE_TRANSACTION_CFG,
8885 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8886 }
7938109f
MC		 8887 }
8888
b02fd9e3
MC		 8889 tg3_phy_start(tp);
8890
f47c11ee 8891 tg3_full_lock(tp, 0);
1da177e4 8892
7938109f
MC		 8893 add_timer(&tp->timer);
8894 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8895 tg3_enable_ints(tp);
8896
f47c11ee 8897 tg3_full_unlock(tp);
1da177e4 8898
fe5f5787 8899 netif_tx_start_all_queues(dev);
1da177e4
LT		 8900
8901 return 0;
07b0173c 8902
679563f4 8903err_out3:
4f125f42
MC		 8904 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8905 struct tg3_napi *tnapi = &tp->napi[i];
8906 free_irq(tnapi->irq_vec, tnapi);
8907 }
07b0173c 8908
679563f4 8909err_out2:
fed97810 8910 tg3_napi_disable(tp);
07b0173c 8911 tg3_free_consistent(tp);
679563f4
MC		 8912
8913err_out1:
8914 tg3_ints_fini(tp);
07b0173c 8915 return err;
1da177e4
LT		 8916}
8917
8918#if 0
8919/*static*/ void tg3_dump_state(struct tg3 *tp)
8920{
8921 u32 val32, val32_2, val32_3, val32_4, val32_5;
8922 u16 val16;
8923 int i;
898a56f8 8924 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8925
8926 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8927 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8928 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8929 val16, val32);
8930
8931 /* MAC block */
8932 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8933 tr32(MAC_MODE), tr32(MAC_STATUS));
8934 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8935 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8936 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8937 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8938 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8939 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8940
8941 /* Send data initiator control block */
8942 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8943 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8944 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8945 tr32(SNDDATAI_STATSCTRL));
8946
8947 /* Send data completion control block */
8948 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8949
8950 /* Send BD ring selector block */
8951 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8952 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8953
8954 /* Send BD initiator control block */
8955 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8956 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8957
8958 /* Send BD completion control block */
8959 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8960
8961 /* Receive list placement control block */
8962 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8963 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8964 printk(" RCVLPC_STATSCTRL[%08x]\n",
8965 tr32(RCVLPC_STATSCTRL));
8966
8967 /* Receive data and receive BD initiator control block */
8968 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8969 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8970
8971 /* Receive data completion control block */
8972 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8973 tr32(RCVDCC_MODE));
8974
8975 /* Receive BD initiator control block */
8976 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8977 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8978
8979 /* Receive BD completion control block */
8980 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8981 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8982
8983 /* Receive list selector control block */
8984 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8985 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8986
8987 /* Mbuf cluster free block */
8988 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8989 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8990
8991 /* Host coalescing control block */
8992 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8993 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8994 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8995 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8996 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8997 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8998 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8999 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9000 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9001 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9002 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9003 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9004
9005 /* Memory arbiter control block */
9006 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9007 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9008
9009 /* Buffer manager control block */
9010 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9011 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9012 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9013 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9014 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9015 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9016 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9017 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9018
9019 /* Read DMA control block */
9020 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9021 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9022
9023 /* Write DMA control block */
9024 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9025 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9026
9027 /* DMA completion block */
9028 printk("DEBUG: DMAC_MODE[%08x]\n",
9029 tr32(DMAC_MODE));
9030
9031 /* GRC block */
9032 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9033 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9034 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9035 tr32(GRC_LOCAL_CTRL));
9036
9037 /* TG3_BDINFOs */
9038 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9039 tr32(RCVDBDI_JUMBO_BD + 0x0),
9040 tr32(RCVDBDI_JUMBO_BD + 0x4),
9041 tr32(RCVDBDI_JUMBO_BD + 0x8),
9042 tr32(RCVDBDI_JUMBO_BD + 0xc));
9043 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9044 tr32(RCVDBDI_STD_BD + 0x0),
9045 tr32(RCVDBDI_STD_BD + 0x4),
9046 tr32(RCVDBDI_STD_BD + 0x8),
9047 tr32(RCVDBDI_STD_BD + 0xc));
9048 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9049 tr32(RCVDBDI_MINI_BD + 0x0),
9050 tr32(RCVDBDI_MINI_BD + 0x4),
9051 tr32(RCVDBDI_MINI_BD + 0x8),
9052 tr32(RCVDBDI_MINI_BD + 0xc));
9053
9054 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9055 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9056 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9057 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9058 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9059 val32, val32_2, val32_3, val32_4);
9060
9061 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9062 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9063 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9064 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9065 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9066 val32, val32_2, val32_3, val32_4);
9067
9068 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9069 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9070 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9071 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9072 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9073 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9074 val32, val32_2, val32_3, val32_4, val32_5);
9075
9076 /* SW status block */
898a56f8
MC		 9077 printk(KERN_DEBUG
9078 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9079 sblk->status,
9080 sblk->status_tag,
9081 sblk->rx_jumbo_consumer,
9082 sblk->rx_consumer,
9083 sblk->rx_mini_consumer,
9084 sblk->idx[0].rx_producer,
9085 sblk->idx[0].tx_consumer);
1da177e4
LT		 9086
9087 /* SW statistics block */
9088 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9089 ((u32 *)tp->hw_stats)[0],
9090 ((u32 *)tp->hw_stats)[1],
9091 ((u32 *)tp->hw_stats)[2],
9092 ((u32 *)tp->hw_stats)[3]);
9093
9094 /* Mailboxes */
9095 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9096 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9097 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9098 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9099 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9100
9101 /* NIC side send descriptors. */
9102 for (i = 0; i < 6; i++) {
9103 unsigned long txd;
9104
9105 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9106 + (i * sizeof(struct tg3_tx_buffer_desc));
9107 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9108 i,
9109 readl(txd + 0x0), readl(txd + 0x4),
9110 readl(txd + 0x8), readl(txd + 0xc));
9111 }
9112
9113 /* NIC side RX descriptors. */
9114 for (i = 0; i < 6; i++) {
9115 unsigned long rxd;
9116
9117 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9118 + (i * sizeof(struct tg3_rx_buffer_desc));
9119 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9120 i,
9121 readl(rxd + 0x0), readl(rxd + 0x4),
9122 readl(rxd + 0x8), readl(rxd + 0xc));
9123 rxd += (4 * sizeof(u32));
9124 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9125 i,
9126 readl(rxd + 0x0), readl(rxd + 0x4),
9127 readl(rxd + 0x8), readl(rxd + 0xc));
9128 }
9129
9130 for (i = 0; i < 6; i++) {
9131 unsigned long rxd;
9132
9133 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9134 + (i * sizeof(struct tg3_rx_buffer_desc));
9135 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9136 i,
9137 readl(rxd + 0x0), readl(rxd + 0x4),
9138 readl(rxd + 0x8), readl(rxd + 0xc));
9139 rxd += (4 * sizeof(u32));
9140 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9141 i,
9142 readl(rxd + 0x0), readl(rxd + 0x4),
9143 readl(rxd + 0x8), readl(rxd + 0xc));
9144 }
9145}
9146#endif
9147
9148static struct net_device_stats *tg3_get_stats(struct net_device *);
9149static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9150
9151static int tg3_close(struct net_device *dev)
9152{
4f125f42 9153 int i;
1da177e4
LT		 9154 struct tg3 *tp = netdev_priv(dev);
9155
fed97810 9156 tg3_napi_disable(tp);
28e53bdd 9157 cancel_work_sync(&tp->reset_task);
7faa006f 9158
fe5f5787 9159 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9160
9161 del_timer_sync(&tp->timer);
9162
24bb4fb6
MC		 9163 tg3_phy_stop(tp);
9164
f47c11ee 9165 tg3_full_lock(tp, 1);
1da177e4
LT		 9166#if 0
9167 tg3_dump_state(tp);
9168#endif
9169
9170 tg3_disable_ints(tp);
9171
944d980e 9172 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9173 tg3_free_rings(tp);
5cf64b8a 9174 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9175
f47c11ee 9176 tg3_full_unlock(tp);
1da177e4 9177
4f125f42
MC		 9178 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9179 struct tg3_napi *tnapi = &tp->napi[i];
9180 free_irq(tnapi->irq_vec, tnapi);
9181 }
07b0173c
MC		 9182
9183 tg3_ints_fini(tp);
1da177e4
LT		 9184
9185 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9186 sizeof(tp->net_stats_prev));
9187 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9188 sizeof(tp->estats_prev));
9189
9190 tg3_free_consistent(tp);
9191
bc1c7567
MC		 9192 tg3_set_power_state(tp, PCI_D3hot);
9193
9194 netif_carrier_off(tp->dev);
9195
1da177e4
LT		 9196 return 0;
9197}
9198
9199static inline unsigned long get_stat64(tg3_stat64_t *val)
9200{
9201 unsigned long ret;
9202
9203#if (BITS_PER_LONG == 32)
9204 ret = val->low;
9205#else
9206 ret = ((u64)val->high << 32) | ((u64)val->low);
9207#endif
9208 return ret;
9209}
9210
816f8b86
SB		 9211static inline u64 get_estat64(tg3_stat64_t *val)
9212{
9213 return ((u64)val->high << 32) | ((u64)val->low);
9214}
9215
1da177e4
LT		 9216static unsigned long calc_crc_errors(struct tg3 *tp)
9217{
9218 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9219
9220 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9223 u32 val;
9224
f47c11ee 9225 spin_lock_bh(&tp->lock);
569a5df8
MC		 9226 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9227 tg3_writephy(tp, MII_TG3_TEST1,
9228 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9229 tg3_readphy(tp, 0x14, &val);
9230 } else
9231 val = 0;
f47c11ee 9232 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9233
9234 tp->phy_crc_errors += val;
9235
9236 return tp->phy_crc_errors;
9237 }
9238
9239 return get_stat64(&hw_stats->rx_fcs_errors);
9240}
9241
9242#define ESTAT_ADD(member) \
9243 estats->member = old_estats->member + \
816f8b86 9244 get_estat64(&hw_stats->member)
1da177e4
LT		 9245
9246static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9247{
9248 struct tg3_ethtool_stats *estats = &tp->estats;
9249 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9250 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9251
9252 if (!hw_stats)
9253 return old_estats;
9254
9255 ESTAT_ADD(rx_octets);
9256 ESTAT_ADD(rx_fragments);
9257 ESTAT_ADD(rx_ucast_packets);
9258 ESTAT_ADD(rx_mcast_packets);
9259 ESTAT_ADD(rx_bcast_packets);
9260 ESTAT_ADD(rx_fcs_errors);
9261 ESTAT_ADD(rx_align_errors);
9262 ESTAT_ADD(rx_xon_pause_rcvd);
9263 ESTAT_ADD(rx_xoff_pause_rcvd);
9264 ESTAT_ADD(rx_mac_ctrl_rcvd);
9265 ESTAT_ADD(rx_xoff_entered);
9266 ESTAT_ADD(rx_frame_too_long_errors);
9267 ESTAT_ADD(rx_jabbers);
9268 ESTAT_ADD(rx_undersize_packets);
9269 ESTAT_ADD(rx_in_length_errors);
9270 ESTAT_ADD(rx_out_length_errors);
9271 ESTAT_ADD(rx_64_or_less_octet_packets);
9272 ESTAT_ADD(rx_65_to_127_octet_packets);
9273 ESTAT_ADD(rx_128_to_255_octet_packets);
9274 ESTAT_ADD(rx_256_to_511_octet_packets);
9275 ESTAT_ADD(rx_512_to_1023_octet_packets);
9276 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9277 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9278 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9279 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9280 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9281
9282 ESTAT_ADD(tx_octets);
9283 ESTAT_ADD(tx_collisions);
9284 ESTAT_ADD(tx_xon_sent);
9285 ESTAT_ADD(tx_xoff_sent);
9286 ESTAT_ADD(tx_flow_control);
9287 ESTAT_ADD(tx_mac_errors);
9288 ESTAT_ADD(tx_single_collisions);
9289 ESTAT_ADD(tx_mult_collisions);
9290 ESTAT_ADD(tx_deferred);
9291 ESTAT_ADD(tx_excessive_collisions);
9292 ESTAT_ADD(tx_late_collisions);
9293 ESTAT_ADD(tx_collide_2times);
9294 ESTAT_ADD(tx_collide_3times);
9295 ESTAT_ADD(tx_collide_4times);
9296 ESTAT_ADD(tx_collide_5times);
9297 ESTAT_ADD(tx_collide_6times);
9298 ESTAT_ADD(tx_collide_7times);
9299 ESTAT_ADD(tx_collide_8times);
9300 ESTAT_ADD(tx_collide_9times);
9301 ESTAT_ADD(tx_collide_10times);
9302 ESTAT_ADD(tx_collide_11times);
9303 ESTAT_ADD(tx_collide_12times);
9304 ESTAT_ADD(tx_collide_13times);
9305 ESTAT_ADD(tx_collide_14times);
9306 ESTAT_ADD(tx_collide_15times);
9307 ESTAT_ADD(tx_ucast_packets);
9308 ESTAT_ADD(tx_mcast_packets);
9309 ESTAT_ADD(tx_bcast_packets);
9310 ESTAT_ADD(tx_carrier_sense_errors);
9311 ESTAT_ADD(tx_discards);
9312 ESTAT_ADD(tx_errors);
9313
9314 ESTAT_ADD(dma_writeq_full);
9315 ESTAT_ADD(dma_write_prioq_full);
9316 ESTAT_ADD(rxbds_empty);
9317 ESTAT_ADD(rx_discards);
9318 ESTAT_ADD(rx_errors);
9319 ESTAT_ADD(rx_threshold_hit);
9320
9321 ESTAT_ADD(dma_readq_full);
9322 ESTAT_ADD(dma_read_prioq_full);
9323 ESTAT_ADD(tx_comp_queue_full);
9324
9325 ESTAT_ADD(ring_set_send_prod_index);
9326 ESTAT_ADD(ring_status_update);
9327 ESTAT_ADD(nic_irqs);
9328 ESTAT_ADD(nic_avoided_irqs);
9329 ESTAT_ADD(nic_tx_threshold_hit);
9330
9331 return estats;
9332}
9333
9334static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9335{
9336 struct tg3 *tp = netdev_priv(dev);
9337 struct net_device_stats *stats = &tp->net_stats;
9338 struct net_device_stats *old_stats = &tp->net_stats_prev;
9339 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9340
9341 if (!hw_stats)
9342 return old_stats;
9343
9344 stats->rx_packets = old_stats->rx_packets +
9345 get_stat64(&hw_stats->rx_ucast_packets) +
9346 get_stat64(&hw_stats->rx_mcast_packets) +
9347 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9348
1da177e4
LT		 9349 stats->tx_packets = old_stats->tx_packets +
9350 get_stat64(&hw_stats->tx_ucast_packets) +
9351 get_stat64(&hw_stats->tx_mcast_packets) +
9352 get_stat64(&hw_stats->tx_bcast_packets);
9353
9354 stats->rx_bytes = old_stats->rx_bytes +
9355 get_stat64(&hw_stats->rx_octets);
9356 stats->tx_bytes = old_stats->tx_bytes +
9357 get_stat64(&hw_stats->tx_octets);
9358
9359 stats->rx_errors = old_stats->rx_errors +
4f63b877 9360 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9361 stats->tx_errors = old_stats->tx_errors +
9362 get_stat64(&hw_stats->tx_errors) +
9363 get_stat64(&hw_stats->tx_mac_errors) +
9364 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9365 get_stat64(&hw_stats->tx_discards);
9366
9367 stats->multicast = old_stats->multicast +
9368 get_stat64(&hw_stats->rx_mcast_packets);
9369 stats->collisions = old_stats->collisions +
9370 get_stat64(&hw_stats->tx_collisions);
9371
9372 stats->rx_length_errors = old_stats->rx_length_errors +
9373 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9374 get_stat64(&hw_stats->rx_undersize_packets);
9375
9376 stats->rx_over_errors = old_stats->rx_over_errors +
9377 get_stat64(&hw_stats->rxbds_empty);
9378 stats->rx_frame_errors = old_stats->rx_frame_errors +
9379 get_stat64(&hw_stats->rx_align_errors);
9380 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9381 get_stat64(&hw_stats->tx_discards);
9382 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9383 get_stat64(&hw_stats->tx_carrier_sense_errors);
9384
9385 stats->rx_crc_errors = old_stats->rx_crc_errors +
9386 calc_crc_errors(tp);
9387
4f63b877
JL		 9388 stats->rx_missed_errors = old_stats->rx_missed_errors +
9389 get_stat64(&hw_stats->rx_discards);
9390
1da177e4
LT		 9391 return stats;
9392}
9393
9394static inline u32 calc_crc(unsigned char *buf, int len)
9395{
9396 u32 reg;
9397 u32 tmp;
9398 int j, k;
9399
9400 reg = 0xffffffff;
9401
9402 for (j = 0; j < len; j++) {
9403 reg ^= buf[j];
9404
9405 for (k = 0; k < 8; k++) {
9406 tmp = reg & 0x01;
9407
9408 reg >>= 1;
9409
9410 if (tmp) {
9411 reg ^= 0xedb88320;
9412 }
9413 }
9414 }
9415
9416 return ~reg;
9417}
9418
9419static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9420{
9421 /* accept or reject all multicast frames */
9422 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9423 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9424 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9425 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9426}
9427
9428static void __tg3_set_rx_mode(struct net_device *dev)
9429{
9430 struct tg3 *tp = netdev_priv(dev);
9431 u32 rx_mode;
9432
9433 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9434 RX_MODE_KEEP_VLAN_TAG);
9435
9436 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9437 * flag clear.
9438 */
9439#if TG3_VLAN_TAG_USED
9440 if (!tp->vlgrp &&
9441 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9442 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9443#else
9444 /* By definition, VLAN is disabled always in this
9445 * case.
9446 */
9447 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9448 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9449#endif
9450
9451 if (dev->flags & IFF_PROMISC) {
9452 /* Promiscuous mode. */
9453 rx_mode |= RX_MODE_PROMISC;
9454 } else if (dev->flags & IFF_ALLMULTI) {
9455 /* Accept all multicast. */
9456 tg3_set_multi (tp, 1);
4cd24eaf 9457 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 9458 /* Reject all multicast. */
9459 tg3_set_multi (tp, 0);
9460 } else {
9461 /* Accept one or more multicast(s). */
22bedad3 9462 struct netdev_hw_addr *ha;
1da177e4
LT		 9463 u32 mc_filter[4] = { 0, };
9464 u32 regidx;
9465 u32 bit;
9466 u32 crc;
9467
22bedad3
JP		 9468 netdev_for_each_mc_addr(ha, dev) {
9469 crc = calc_crc(ha->addr, ETH_ALEN);
1da177e4
LT		 9470 bit = ~crc & 0x7f;
9471 regidx = (bit & 0x60) >> 5;
9472 bit &= 0x1f;
9473 mc_filter[regidx] |= (1 << bit);
9474 }
9475
9476 tw32(MAC_HASH_REG_0, mc_filter[0]);
9477 tw32(MAC_HASH_REG_1, mc_filter[1]);
9478 tw32(MAC_HASH_REG_2, mc_filter[2]);
9479 tw32(MAC_HASH_REG_3, mc_filter[3]);
9480 }
9481
9482 if (rx_mode != tp->rx_mode) {
9483 tp->rx_mode = rx_mode;
9484 tw32_f(MAC_RX_MODE, rx_mode);
9485 udelay(10);
9486 }
9487}
9488
9489static void tg3_set_rx_mode(struct net_device *dev)
9490{
9491 struct tg3 *tp = netdev_priv(dev);
9492
e75f7c90
MC		 9493 if (!netif_running(dev))
9494 return;
9495
f47c11ee 9496 tg3_full_lock(tp, 0);
1da177e4 9497 __tg3_set_rx_mode(dev);
f47c11ee 9498 tg3_full_unlock(tp);
1da177e4
LT		 9499}
9500
9501#define TG3_REGDUMP_LEN (32 * 1024)
9502
9503static int tg3_get_regs_len(struct net_device *dev)
9504{
9505 return TG3_REGDUMP_LEN;
9506}
9507
9508static void tg3_get_regs(struct net_device *dev,
9509 struct ethtool_regs *regs, void *_p)
9510{
9511 u32 *p = _p;
9512 struct tg3 *tp = netdev_priv(dev);
9513 u8 *orig_p = _p;
9514 int i;
9515
9516 regs->version = 0;
9517
9518 memset(p, 0, TG3_REGDUMP_LEN);
9519
bc1c7567
MC		 9520 if (tp->link_config.phy_is_low_power)
9521 return;
9522
f47c11ee 9523 tg3_full_lock(tp, 0);
1da177e4
LT		 9524
9525#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9526#define GET_REG32_LOOP(base,len) \
9527do { p = (u32 *)(orig_p + (base)); \
9528 for (i = 0; i < len; i += 4) \
9529 __GET_REG32((base) + i); \
9530} while (0)
9531#define GET_REG32_1(reg) \
9532do { p = (u32 *)(orig_p + (reg)); \
9533 __GET_REG32((reg)); \
9534} while (0)
9535
9536 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9537 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9538 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9539 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9540 GET_REG32_1(SNDDATAC_MODE);
9541 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9542 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9543 GET_REG32_1(SNDBDC_MODE);
9544 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9545 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9546 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9547 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9548 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9549 GET_REG32_1(RCVDCC_MODE);
9550 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9551 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9552 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9553 GET_REG32_1(MBFREE_MODE);
9554 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9555 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9556 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9557 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9558 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9559 GET_REG32_1(RX_CPU_MODE);
9560 GET_REG32_1(RX_CPU_STATE);
9561 GET_REG32_1(RX_CPU_PGMCTR);
9562 GET_REG32_1(RX_CPU_HWBKPT);
9563 GET_REG32_1(TX_CPU_MODE);
9564 GET_REG32_1(TX_CPU_STATE);
9565 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9566 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9567 GET_REG32_LOOP(FTQ_RESET, 0x120);
9568 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9569 GET_REG32_1(DMAC_MODE);
9570 GET_REG32_LOOP(GRC_MODE, 0x4c);
9571 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9572 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9573
9574#undef __GET_REG32
9575#undef GET_REG32_LOOP
9576#undef GET_REG32_1
9577
f47c11ee 9578 tg3_full_unlock(tp);
1da177e4
LT		 9579}
9580
9581static int tg3_get_eeprom_len(struct net_device *dev)
9582{
9583 struct tg3 *tp = netdev_priv(dev);
9584
9585 return tp->nvram_size;
9586}
9587
1da177e4
LT		 9588static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9589{
9590 struct tg3 *tp = netdev_priv(dev);
9591 int ret;
9592 u8 *pd;
b9fc7dc5 9593 u32 i, offset, len, b_offset, b_count;
a9dc529d 9594 __be32 val;
1da177e4 9595
df259d8c
MC		 9596 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9597 return -EINVAL;
9598
bc1c7567
MC		 9599 if (tp->link_config.phy_is_low_power)
9600 return -EAGAIN;
9601
1da177e4
LT		 9602 offset = eeprom->offset;
9603 len = eeprom->len;
9604 eeprom->len = 0;
9605
9606 eeprom->magic = TG3_EEPROM_MAGIC;
9607
9608 if (offset & 3) {
9609 /* adjustments to start on required 4 byte boundary */
9610 b_offset = offset & 3;
9611 b_count = 4 - b_offset;
9612 if (b_count > len) {
9613 /* i.e. offset=1 len=2 */
9614 b_count = len;
9615 }
a9dc529d 9616 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9617 if (ret)
9618 return ret;
1da177e4
LT		 9619 memcpy(data, ((char*)&val) + b_offset, b_count);
9620 len -= b_count;
9621 offset += b_count;
9622 eeprom->len += b_count;
9623 }
9624
9625 /* read bytes upto the last 4 byte boundary */
9626 pd = &data[eeprom->len];
9627 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9628 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9629 if (ret) {
9630 eeprom->len += i;
9631 return ret;
9632 }
1da177e4
LT		 9633 memcpy(pd + i, &val, 4);
9634 }
9635 eeprom->len += i;
9636
9637 if (len & 3) {
9638 /* read last bytes not ending on 4 byte boundary */
9639 pd = &data[eeprom->len];
9640 b_count = len & 3;
9641 b_offset = offset + len - b_count;
a9dc529d 9642 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9643 if (ret)
9644 return ret;
b9fc7dc5 9645 memcpy(pd, &val, b_count);
1da177e4
LT		 9646 eeprom->len += b_count;
9647 }
9648 return 0;
9649}
9650
6aa20a22 9651static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9652
9653static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9654{
9655 struct tg3 *tp = netdev_priv(dev);
9656 int ret;
b9fc7dc5 9657 u32 offset, len, b_offset, odd_len;
1da177e4 9658 u8 *buf;
a9dc529d 9659 __be32 start, end;
1da177e4 9660
bc1c7567
MC		 9661 if (tp->link_config.phy_is_low_power)
9662 return -EAGAIN;
9663
df259d8c
MC		 9664 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9665 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9666 return -EINVAL;
9667
9668 offset = eeprom->offset;
9669 len = eeprom->len;
9670
9671 if ((b_offset = (offset & 3))) {
9672 /* adjustments to start on required 4 byte boundary */
a9dc529d 9673 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9674 if (ret)
9675 return ret;
1da177e4
LT		 9676 len += b_offset;
9677 offset &= ~3;
1c8594b4
MC		 9678 if (len < 4)
9679 len = 4;
1da177e4
LT		 9680 }
9681
9682 odd_len = 0;
1c8594b4 9683 if (len & 3) {
1da177e4
LT		 9684 /* adjustments to end on required 4 byte boundary */
9685 odd_len = 1;
9686 len = (len + 3) & ~3;
a9dc529d 9687 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9688 if (ret)
9689 return ret;
1da177e4
LT		 9690 }
9691
9692 buf = data;
9693 if (b_offset || odd_len) {
9694 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9695 if (!buf)
1da177e4
LT		 9696 return -ENOMEM;
9697 if (b_offset)
9698 memcpy(buf, &start, 4);
9699 if (odd_len)
9700 memcpy(buf+len-4, &end, 4);
9701 memcpy(buf + b_offset, data, eeprom->len);
9702 }
9703
9704 ret = tg3_nvram_write_block(tp, offset, len, buf);
9705
9706 if (buf != data)
9707 kfree(buf);
9708
9709 return ret;
9710}
9711
9712static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9713{
b02fd9e3
MC		 9714 struct tg3 *tp = netdev_priv(dev);
9715
9716 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9717 struct phy_device *phydev;
b02fd9e3
MC		 9718 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9719 return -EAGAIN;
3f0e3ad7
MC		 9720 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9721 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9722 }
6aa20a22 9723
1da177e4
LT		 9724 cmd->supported = (SUPPORTED_Autoneg);
9725
9726 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9727 cmd->supported |= (SUPPORTED_1000baseT_Half |
9728 SUPPORTED_1000baseT_Full);
9729
ef348144 9730 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9731 cmd->supported |= (SUPPORTED_100baseT_Half |
9732 SUPPORTED_100baseT_Full |
9733 SUPPORTED_10baseT_Half |
9734 SUPPORTED_10baseT_Full |
3bebab59 9735 SUPPORTED_TP);
ef348144
KK		 9736 cmd->port = PORT_TP;
9737 } else {
1da177e4 9738 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9739 cmd->port = PORT_FIBRE;
9740 }
6aa20a22 9741
1da177e4
LT		 9742 cmd->advertising = tp->link_config.advertising;
9743 if (netif_running(dev)) {
9744 cmd->speed = tp->link_config.active_speed;
9745 cmd->duplex = tp->link_config.active_duplex;
9746 }
882e9793 9747 cmd->phy_address = tp->phy_addr;
7e5856bd 9748 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9749 cmd->autoneg = tp->link_config.autoneg;
9750 cmd->maxtxpkt = 0;
9751 cmd->maxrxpkt = 0;
9752 return 0;
9753}
6aa20a22 9754
1da177e4
LT		 9755static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9756{
9757 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9758
b02fd9e3 9759 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9760 struct phy_device *phydev;
b02fd9e3
MC		 9761 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9762 return -EAGAIN;
3f0e3ad7
MC		 9763 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9764 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9765 }
9766
7e5856bd
MC		 9767 if (cmd->autoneg != AUTONEG_ENABLE &&
9768 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9769 return -EINVAL;
7e5856bd
MC		 9770
9771 if (cmd->autoneg == AUTONEG_DISABLE &&
9772 cmd->duplex != DUPLEX_FULL &&
9773 cmd->duplex != DUPLEX_HALF)
37ff238d 9774 return -EINVAL;
1da177e4 9775
7e5856bd
MC		 9776 if (cmd->autoneg == AUTONEG_ENABLE) {
9777 u32 mask = ADVERTISED_Autoneg |
9778 ADVERTISED_Pause |
9779 ADVERTISED_Asym_Pause;
9780
3f07d129 9781 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7e5856bd
MC		 9782 mask |= ADVERTISED_1000baseT_Half |
9783 ADVERTISED_1000baseT_Full;
9784
9785 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9786 mask |= ADVERTISED_100baseT_Half |
9787 ADVERTISED_100baseT_Full |
9788 ADVERTISED_10baseT_Half |
9789 ADVERTISED_10baseT_Full |
9790 ADVERTISED_TP;
9791 else
9792 mask |= ADVERTISED_FIBRE;
9793
9794 if (cmd->advertising & ~mask)
9795 return -EINVAL;
9796
9797 mask &= (ADVERTISED_1000baseT_Half |
9798 ADVERTISED_1000baseT_Full |
9799 ADVERTISED_100baseT_Half |
9800 ADVERTISED_100baseT_Full |
9801 ADVERTISED_10baseT_Half |
9802 ADVERTISED_10baseT_Full);
9803
9804 cmd->advertising &= mask;
9805 } else {
9806 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9807 if (cmd->speed != SPEED_1000)
9808 return -EINVAL;
9809
9810 if (cmd->duplex != DUPLEX_FULL)
9811 return -EINVAL;
9812 } else {
9813 if (cmd->speed != SPEED_100 &&
9814 cmd->speed != SPEED_10)
9815 return -EINVAL;
9816 }
9817 }
9818
f47c11ee 9819 tg3_full_lock(tp, 0);
1da177e4
LT		 9820
9821 tp->link_config.autoneg = cmd->autoneg;
9822 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9823 tp->link_config.advertising = (cmd->advertising |
9824 ADVERTISED_Autoneg);
1da177e4
LT		 9825 tp->link_config.speed = SPEED_INVALID;
9826 tp->link_config.duplex = DUPLEX_INVALID;
9827 } else {
9828 tp->link_config.advertising = 0;
9829 tp->link_config.speed = cmd->speed;
9830 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9831 }
6aa20a22 9832
24fcad6b
MC		 9833 tp->link_config.orig_speed = tp->link_config.speed;
9834 tp->link_config.orig_duplex = tp->link_config.duplex;
9835 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9836
1da177e4
LT		 9837 if (netif_running(dev))
9838 tg3_setup_phy(tp, 1);
9839
f47c11ee 9840 tg3_full_unlock(tp);
6aa20a22 9841
1da177e4
LT		 9842 return 0;
9843}
6aa20a22 9844
1da177e4
LT		 9845static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9846{
9847 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9848
1da177e4
LT		 9849 strcpy(info->driver, DRV_MODULE_NAME);
9850 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9851 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9852 strcpy(info->bus_info, pci_name(tp->pdev));
9853}
6aa20a22 9854
1da177e4
LT		 9855static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9856{
9857 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9858
12dac075
RW		 9859 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9860 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9861 wol->supported = WAKE_MAGIC;
9862 else
9863 wol->supported = 0;
1da177e4 9864 wol->wolopts = 0;
05ac4cb7
MC		 9865 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9866 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9867 wol->wolopts = WAKE_MAGIC;
9868 memset(&wol->sopass, 0, sizeof(wol->sopass));
9869}
6aa20a22 9870
1da177e4
LT		 9871static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9872{
9873 struct tg3 *tp = netdev_priv(dev);
12dac075 9874 struct device *dp = &tp->pdev->dev;
6aa20a22 9875
1da177e4
LT		 9876 if (wol->wolopts & ~WAKE_MAGIC)
9877 return -EINVAL;
9878 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9879 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9880 return -EINVAL;
6aa20a22 9881
f47c11ee 9882 spin_lock_bh(&tp->lock);
12dac075 9883 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9884 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9885 device_set_wakeup_enable(dp, true);
9886 } else {
1da177e4 9887 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9888 device_set_wakeup_enable(dp, false);
9889 }
f47c11ee 9890 spin_unlock_bh(&tp->lock);
6aa20a22 9891
1da177e4
LT		 9892 return 0;
9893}
6aa20a22 9894
1da177e4
LT		 9895static u32 tg3_get_msglevel(struct net_device *dev)
9896{
9897 struct tg3 *tp = netdev_priv(dev);
9898 return tp->msg_enable;
9899}
6aa20a22 9900
1da177e4
LT		 9901static void tg3_set_msglevel(struct net_device *dev, u32 value)
9902{
9903 struct tg3 *tp = netdev_priv(dev);
9904 tp->msg_enable = value;
9905}
6aa20a22 9906
1da177e4
LT		 9907static int tg3_set_tso(struct net_device *dev, u32 value)
9908{
9909 struct tg3 *tp = netdev_priv(dev);
9910
9911 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9912 if (value)
9913 return -EINVAL;
9914 return 0;
9915 }
027455ad 9916 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9917 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9918 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9919 if (value) {
b0026624 9920 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9921 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9923 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9924 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9927 dev->features |= NETIF_F_TSO_ECN;
9928 } else
9929 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9930 }
1da177e4
LT		 9931 return ethtool_op_set_tso(dev, value);
9932}
6aa20a22 9933
1da177e4
LT		 9934static int tg3_nway_reset(struct net_device *dev)
9935{
9936 struct tg3 *tp = netdev_priv(dev);
1da177e4 9937 int r;
6aa20a22 9938
1da177e4
LT		 9939 if (!netif_running(dev))
9940 return -EAGAIN;
9941
c94e3941
MC		 9942 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9943 return -EINVAL;
9944
b02fd9e3
MC		 9945 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9946 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9947 return -EAGAIN;
3f0e3ad7 9948 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9949 } else {
9950 u32 bmcr;
9951
9952 spin_lock_bh(&tp->lock);
9953 r = -EINVAL;
9954 tg3_readphy(tp, MII_BMCR, &bmcr);
9955 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9956 ((bmcr & BMCR_ANENABLE) ||
9957 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9958 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9959 BMCR_ANENABLE);
9960 r = 0;
9961 }
9962 spin_unlock_bh(&tp->lock);
1da177e4 9963 }
6aa20a22 9964
1da177e4
LT		 9965 return r;
9966}
6aa20a22 9967
1da177e4
LT		 9968static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9969{
9970 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9971
1da177e4
LT		 9972 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9973 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9974 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9975 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9976 else
9977 ering->rx_jumbo_max_pending = 0;
9978
9979 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9980
9981 ering->rx_pending = tp->rx_pending;
9982 ering->rx_mini_pending = 0;
4f81c32b
MC		 9983 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9984 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9985 else
9986 ering->rx_jumbo_pending = 0;
9987
f3f3f27e 9988 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9989}
6aa20a22 9990
1da177e4
LT		 9991static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9992{
9993 struct tg3 *tp = netdev_priv(dev);
646c9edd 9994 int i, irq_sync = 0, err = 0;
6aa20a22 9995
1da177e4
LT		 9996 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9997 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9998 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9999 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 10000 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 10001 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 10002 return -EINVAL;
6aa20a22 10003
bbe832c0 10004 if (netif_running(dev)) {
b02fd9e3 10005 tg3_phy_stop(tp);
1da177e4 10006 tg3_netif_stop(tp);
bbe832c0
MC		 10007 irq_sync = 1;
10008 }
1da177e4 10009
bbe832c0 10010 tg3_full_lock(tp, irq_sync);
6aa20a22 10011
1da177e4
LT		 10012 tp->rx_pending = ering->rx_pending;
10013
10014 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10015 tp->rx_pending > 63)
10016 tp->rx_pending = 63;
10017 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 10018
10019 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10020 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 10021
10022 if (netif_running(dev)) {
944d980e 10023 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 10024 err = tg3_restart_hw(tp, 1);
10025 if (!err)
10026 tg3_netif_start(tp);
1da177e4
LT		 10027 }
10028
f47c11ee 10029 tg3_full_unlock(tp);
6aa20a22 10030
b02fd9e3
MC		 10031 if (irq_sync && !err)
10032 tg3_phy_start(tp);
10033
b9ec6c1b 10034 return err;
1da177e4 10035}
6aa20a22 10036
1da177e4
LT		 10037static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10038{
10039 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10040
1da177e4 10041 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 10042
e18ce346 10043 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 10044 epause->rx_pause = 1;
10045 else
10046 epause->rx_pause = 0;
10047
e18ce346 10048 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10049 epause->tx_pause = 1;
10050 else
10051 epause->tx_pause = 0;
1da177e4 10052}
6aa20a22 10053
1da177e4
LT		 10054static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10055{
10056 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10057 int err = 0;
6aa20a22 10058
b02fd9e3 10059 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2712168f
MC		 10060 u32 newadv;
10061 struct phy_device *phydev;
1da177e4 10062
2712168f 10063 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 10064
2712168f
MC		 10065 if (!(phydev->supported & SUPPORTED_Pause) ||
10066 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10067 ((epause->rx_pause && !epause->tx_pause) ||
10068 (!epause->rx_pause && epause->tx_pause))))
10069 return -EINVAL;
1da177e4 10070
2712168f
MC		 10071 tp->link_config.flowctrl = 0;
10072 if (epause->rx_pause) {
10073 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10074
10075 if (epause->tx_pause) {
10076 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10077 newadv = ADVERTISED_Pause;
b02fd9e3 10078 } else
2712168f
MC		 10079 newadv = ADVERTISED_Pause |
10080 ADVERTISED_Asym_Pause;
10081 } else if (epause->tx_pause) {
10082 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10083 newadv = ADVERTISED_Asym_Pause;
10084 } else
10085 newadv = 0;
10086
10087 if (epause->autoneg)
10088 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10089 else
10090 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10091
10092 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10093 u32 oldadv = phydev->advertising &
10094 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10095 if (oldadv != newadv) {
10096 phydev->advertising &=
10097 ~(ADVERTISED_Pause |
10098 ADVERTISED_Asym_Pause);
10099 phydev->advertising |= newadv;
10100 if (phydev->autoneg) {
10101 /*
10102 * Always renegotiate the link to
10103 * inform our link partner of our
10104 * flow control settings, even if the
10105 * flow control is forced. Let
10106 * tg3_adjust_link() do the final
10107 * flow control setup.
10108 */
10109 return phy_start_aneg(phydev);
b02fd9e3 10110 }
b02fd9e3 10111 }
b02fd9e3 10112
2712168f 10113 if (!epause->autoneg)
b02fd9e3 10114 tg3_setup_flow_control(tp, 0, 0);
2712168f
MC		 10115 } else {
10116 tp->link_config.orig_advertising &=
10117 ~(ADVERTISED_Pause |
10118 ADVERTISED_Asym_Pause);
10119 tp->link_config.orig_advertising |= newadv;
b02fd9e3
MC		 10120 }
10121 } else {
10122 int irq_sync = 0;
10123
10124 if (netif_running(dev)) {
10125 tg3_netif_stop(tp);
10126 irq_sync = 1;
10127 }
10128
10129 tg3_full_lock(tp, irq_sync);
10130
10131 if (epause->autoneg)
10132 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10133 else
10134 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10135 if (epause->rx_pause)
e18ce346 10136 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10137 else
e18ce346 10138 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10139 if (epause->tx_pause)
e18ce346 10140 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10141 else
e18ce346 10142 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10143
10144 if (netif_running(dev)) {
10145 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10146 err = tg3_restart_hw(tp, 1);
10147 if (!err)
10148 tg3_netif_start(tp);
10149 }
10150
10151 tg3_full_unlock(tp);
10152 }
6aa20a22 10153
b9ec6c1b 10154 return err;
1da177e4 10155}
6aa20a22 10156
1da177e4
LT		 10157static u32 tg3_get_rx_csum(struct net_device *dev)
10158{
10159 struct tg3 *tp = netdev_priv(dev);
10160 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10161}
6aa20a22 10162
1da177e4
LT		 10163static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10164{
10165 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10166
1da177e4
LT		 10167 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10168 if (data != 0)
10169 return -EINVAL;
10170 return 0;
10171 }
6aa20a22 10172
f47c11ee 10173 spin_lock_bh(&tp->lock);
1da177e4
LT		 10174 if (data)
10175 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10176 else
10177 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10178 spin_unlock_bh(&tp->lock);
6aa20a22 10179
1da177e4
LT		 10180 return 0;
10181}
6aa20a22 10182
1da177e4
LT		 10183static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10184{
10185 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10186
1da177e4
LT		 10187 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10188 if (data != 0)
10189 return -EINVAL;
10190 return 0;
10191 }
6aa20a22 10192
321d32a0 10193 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10194 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10195 else
9c27dbdf 10196 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10197
10198 return 0;
10199}
10200
b9f2c044 10201static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10202{
b9f2c044
JG		 10203 switch (sset) {
10204 case ETH_SS_TEST:
10205 return TG3_NUM_TEST;
10206 case ETH_SS_STATS:
10207 return TG3_NUM_STATS;
10208 default:
10209 return -EOPNOTSUPP;
10210 }
4cafd3f5
MC		 10211}
10212
1da177e4
LT		 10213static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10214{
10215 switch (stringset) {
10216 case ETH_SS_STATS:
10217 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10218 break;
4cafd3f5
MC		 10219 case ETH_SS_TEST:
10220 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10221 break;
1da177e4
LT		 10222 default:
10223 WARN_ON(1); /* we need a WARN() */
10224 break;
10225 }
10226}
10227
4009a93d
MC		 10228static int tg3_phys_id(struct net_device *dev, u32 data)
10229{
10230 struct tg3 *tp = netdev_priv(dev);
10231 int i;
10232
10233 if (!netif_running(tp->dev))
10234 return -EAGAIN;
10235
10236 if (data == 0)
759afc31 10237 data = UINT_MAX / 2;
4009a93d
MC		 10238
10239 for (i = 0; i < (data * 2); i++) {
10240 if ((i % 2) == 0)
10241 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10242 LED_CTRL_1000MBPS_ON |
10243 LED_CTRL_100MBPS_ON |
10244 LED_CTRL_10MBPS_ON |
10245 LED_CTRL_TRAFFIC_OVERRIDE |
10246 LED_CTRL_TRAFFIC_BLINK |
10247 LED_CTRL_TRAFFIC_LED);
6aa20a22 10248
4009a93d
MC		 10249 else
10250 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10251 LED_CTRL_TRAFFIC_OVERRIDE);
10252
10253 if (msleep_interruptible(500))
10254 break;
10255 }
10256 tw32(MAC_LED_CTRL, tp->led_ctrl);
10257 return 0;
10258}
10259
1da177e4
LT		 10260static void tg3_get_ethtool_stats (struct net_device *dev,
10261 struct ethtool_stats *estats, u64 *tmp_stats)
10262{
10263 struct tg3 *tp = netdev_priv(dev);
10264 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10265}
10266
566f86ad 10267#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10268#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10269#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10270#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10271#define NVRAM_SELFBOOT_HW_SIZE 0x20
10272#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10273
10274static int tg3_test_nvram(struct tg3 *tp)
10275{
b9fc7dc5 10276 u32 csum, magic;
a9dc529d 10277 __be32 *buf;
ab0049b4 10278 int i, j, k, err = 0, size;
566f86ad 10279
df259d8c
MC		 10280 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10281 return 0;
10282
e4f34110 10283 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10284 return -EIO;
10285
1b27777a
MC		 10286 if (magic == TG3_EEPROM_MAGIC)
10287 size = NVRAM_TEST_SIZE;
b16250e3 10288 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10289 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10290 TG3_EEPROM_SB_FORMAT_1) {
10291 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10292 case TG3_EEPROM_SB_REVISION_0:
10293 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10294 break;
10295 case TG3_EEPROM_SB_REVISION_2:
10296 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10297 break;
10298 case TG3_EEPROM_SB_REVISION_3:
10299 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10300 break;
10301 default:
10302 return 0;
10303 }
10304 } else
1b27777a 10305 return 0;
b16250e3
MC		 10306 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10307 size = NVRAM_SELFBOOT_HW_SIZE;
10308 else
1b27777a
MC		 10309 return -EIO;
10310
10311 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10312 if (buf == NULL)
10313 return -ENOMEM;
10314
1b27777a
MC		 10315 err = -EIO;
10316 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10317 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10318 if (err)
566f86ad 10319 break;
566f86ad 10320 }
1b27777a 10321 if (i < size)
566f86ad
MC		 10322 goto out;
10323
1b27777a 10324 /* Selfboot format */
a9dc529d 10325 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10326 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10327 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10328 u8 *buf8 = (u8 *) buf, csum8 = 0;
10329
b9fc7dc5 10330 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10331 TG3_EEPROM_SB_REVISION_2) {
10332 /* For rev 2, the csum doesn't include the MBA. */
10333 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10334 csum8 += buf8[i];
10335 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10336 csum8 += buf8[i];
10337 } else {
10338 for (i = 0; i < size; i++)
10339 csum8 += buf8[i];
10340 }
1b27777a 10341
ad96b485
AB		 10342 if (csum8 == 0) {
10343 err = 0;
10344 goto out;
10345 }
10346
10347 err = -EIO;
10348 goto out;
1b27777a 10349 }
566f86ad 10350
b9fc7dc5 10351 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10352 TG3_EEPROM_MAGIC_HW) {
10353 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10354 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10355 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10356
10357 /* Separate the parity bits and the data bytes. */
10358 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10359 if ((i == 0) || (i == 8)) {
10360 int l;
10361 u8 msk;
10362
10363 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10364 parity[k++] = buf8[i] & msk;
10365 i++;
10366 }
10367 else if (i == 16) {
10368 int l;
10369 u8 msk;
10370
10371 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10372 parity[k++] = buf8[i] & msk;
10373 i++;
10374
10375 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10376 parity[k++] = buf8[i] & msk;
10377 i++;
10378 }
10379 data[j++] = buf8[i];
10380 }
10381
10382 err = -EIO;
10383 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10384 u8 hw8 = hweight8(data[i]);
10385
10386 if ((hw8 & 0x1) && parity[i])
10387 goto out;
10388 else if (!(hw8 & 0x1) && !parity[i])
10389 goto out;
10390 }
10391 err = 0;
10392 goto out;
10393 }
10394
566f86ad
MC		 10395 /* Bootstrap checksum at offset 0x10 */
10396 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10397 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10398 goto out;
10399
10400 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10401 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10402 if (csum != be32_to_cpu(buf[0xfc/4]))
10403 goto out;
566f86ad
MC		 10404
10405 err = 0;
10406
10407out:
10408 kfree(buf);
10409 return err;
10410}
10411
ca43007a
MC		 10412#define TG3_SERDES_TIMEOUT_SEC 2
10413#define TG3_COPPER_TIMEOUT_SEC 6
10414
10415static int tg3_test_link(struct tg3 *tp)
10416{
10417 int i, max;
10418
10419 if (!netif_running(tp->dev))
10420 return -ENODEV;
10421
4c987487 10422 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10423 max = TG3_SERDES_TIMEOUT_SEC;
10424 else
10425 max = TG3_COPPER_TIMEOUT_SEC;
10426
10427 for (i = 0; i < max; i++) {
10428 if (netif_carrier_ok(tp->dev))
10429 return 0;
10430
10431 if (msleep_interruptible(1000))
10432 break;
10433 }
10434
10435 return -EIO;
10436}
10437
a71116d1 10438/* Only test the commonly used registers */
30ca3e37 10439static int tg3_test_registers(struct tg3 *tp)
a71116d1 10440{
b16250e3 10441 int i, is_5705, is_5750;
a71116d1
MC		 10442 u32 offset, read_mask, write_mask, val, save_val, read_val;
10443 static struct {
10444 u16 offset;
10445 u16 flags;
10446#define TG3_FL_5705 0x1
10447#define TG3_FL_NOT_5705 0x2
10448#define TG3_FL_NOT_5788 0x4
b16250e3 10449#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10450 u32 read_mask;
10451 u32 write_mask;
10452 } reg_tbl[] = {
10453 /* MAC Control Registers */
10454 { MAC_MODE, TG3_FL_NOT_5705,
10455 0x00000000, 0x00ef6f8c },
10456 { MAC_MODE, TG3_FL_5705,
10457 0x00000000, 0x01ef6b8c },
10458 { MAC_STATUS, TG3_FL_NOT_5705,
10459 0x03800107, 0x00000000 },
10460 { MAC_STATUS, TG3_FL_5705,
10461 0x03800100, 0x00000000 },
10462 { MAC_ADDR_0_HIGH, 0x0000,
10463 0x00000000, 0x0000ffff },
10464 { MAC_ADDR_0_LOW, 0x0000,
10465 0x00000000, 0xffffffff },
10466 { MAC_RX_MTU_SIZE, 0x0000,
10467 0x00000000, 0x0000ffff },
10468 { MAC_TX_MODE, 0x0000,
10469 0x00000000, 0x00000070 },
10470 { MAC_TX_LENGTHS, 0x0000,
10471 0x00000000, 0x00003fff },
10472 { MAC_RX_MODE, TG3_FL_NOT_5705,
10473 0x00000000, 0x000007fc },
10474 { MAC_RX_MODE, TG3_FL_5705,
10475 0x00000000, 0x000007dc },
10476 { MAC_HASH_REG_0, 0x0000,
10477 0x00000000, 0xffffffff },
10478 { MAC_HASH_REG_1, 0x0000,
10479 0x00000000, 0xffffffff },
10480 { MAC_HASH_REG_2, 0x0000,
10481 0x00000000, 0xffffffff },
10482 { MAC_HASH_REG_3, 0x0000,
10483 0x00000000, 0xffffffff },
10484
10485 /* Receive Data and Receive BD Initiator Control Registers. */
10486 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10487 0x00000000, 0xffffffff },
10488 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10489 0x00000000, 0xffffffff },
10490 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10491 0x00000000, 0x00000003 },
10492 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10493 0x00000000, 0xffffffff },
10494 { RCVDBDI_STD_BD+0, 0x0000,
10495 0x00000000, 0xffffffff },
10496 { RCVDBDI_STD_BD+4, 0x0000,
10497 0x00000000, 0xffffffff },
10498 { RCVDBDI_STD_BD+8, 0x0000,
10499 0x00000000, 0xffff0002 },
10500 { RCVDBDI_STD_BD+0xc, 0x0000,
10501 0x00000000, 0xffffffff },
6aa20a22 10502
a71116d1
MC		 10503 /* Receive BD Initiator Control Registers. */
10504 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10505 0x00000000, 0xffffffff },
10506 { RCVBDI_STD_THRESH, TG3_FL_5705,
10507 0x00000000, 0x000003ff },
10508 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10509 0x00000000, 0xffffffff },
6aa20a22 10510
a71116d1
MC		 10511 /* Host Coalescing Control Registers. */
10512 { HOSTCC_MODE, TG3_FL_NOT_5705,
10513 0x00000000, 0x00000004 },
10514 { HOSTCC_MODE, TG3_FL_5705,
10515 0x00000000, 0x000000f6 },
10516 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10517 0x00000000, 0xffffffff },
10518 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10519 0x00000000, 0x000003ff },
10520 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10521 0x00000000, 0xffffffff },
10522 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10523 0x00000000, 0x000003ff },
10524 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10525 0x00000000, 0xffffffff },
10526 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10527 0x00000000, 0x000000ff },
10528 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10529 0x00000000, 0xffffffff },
10530 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10531 0x00000000, 0x000000ff },
10532 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10533 0x00000000, 0xffffffff },
10534 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10535 0x00000000, 0xffffffff },
10536 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10537 0x00000000, 0xffffffff },
10538 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10539 0x00000000, 0x000000ff },
10540 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10541 0x00000000, 0xffffffff },
10542 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10543 0x00000000, 0x000000ff },
10544 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10545 0x00000000, 0xffffffff },
10546 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10547 0x00000000, 0xffffffff },
10548 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10549 0x00000000, 0xffffffff },
10550 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10551 0x00000000, 0xffffffff },
10552 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10553 0x00000000, 0xffffffff },
10554 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10555 0xffffffff, 0x00000000 },
10556 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10557 0xffffffff, 0x00000000 },
10558
10559 /* Buffer Manager Control Registers. */
b16250e3 10560 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10561 0x00000000, 0x007fff80 },
b16250e3 10562 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10563 0x00000000, 0x007fffff },
10564 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10565 0x00000000, 0x0000003f },
10566 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10567 0x00000000, 0x000001ff },
10568 { BUFMGR_MB_HIGH_WATER, 0x0000,
10569 0x00000000, 0x000001ff },
10570 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10571 0xffffffff, 0x00000000 },
10572 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10573 0xffffffff, 0x00000000 },
6aa20a22 10574
a71116d1
MC		 10575 /* Mailbox Registers */
10576 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10577 0x00000000, 0x000001ff },
10578 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10579 0x00000000, 0x000001ff },
10580 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10581 0x00000000, 0x000007ff },
10582 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10583 0x00000000, 0x000001ff },
10584
10585 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10586 };
10587
b16250e3
MC		 10588 is_5705 = is_5750 = 0;
10589 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10590 is_5705 = 1;
b16250e3
MC		 10591 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10592 is_5750 = 1;
10593 }
a71116d1
MC		 10594
10595 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10596 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10597 continue;
10598
10599 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10600 continue;
10601
10602 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10603 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10604 continue;
10605
b16250e3
MC		 10606 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10607 continue;
10608
a71116d1
MC		 10609 offset = (u32) reg_tbl[i].offset;
10610 read_mask = reg_tbl[i].read_mask;
10611 write_mask = reg_tbl[i].write_mask;
10612
10613 /* Save the original register content */
10614 save_val = tr32(offset);
10615
10616 /* Determine the read-only value. */
10617 read_val = save_val & read_mask;
10618
10619 /* Write zero to the register, then make sure the read-only bits
10620 * are not changed and the read/write bits are all zeros.
10621 */
10622 tw32(offset, 0);
10623
10624 val = tr32(offset);
10625
10626 /* Test the read-only and read/write bits. */
10627 if (((val & read_mask) != read_val) || (val & write_mask))
10628 goto out;
10629
10630 /* Write ones to all the bits defined by RdMask and WrMask, then
10631 * make sure the read-only bits are not changed and the
10632 * read/write bits are all ones.
10633 */
10634 tw32(offset, read_mask | write_mask);
10635
10636 val = tr32(offset);
10637
10638 /* Test the read-only bits. */
10639 if ((val & read_mask) != read_val)
10640 goto out;
10641
10642 /* Test the read/write bits. */
10643 if ((val & write_mask) != write_mask)
10644 goto out;
10645
10646 tw32(offset, save_val);
10647 }
10648
10649 return 0;
10650
10651out:
9f88f29f 10652 if (netif_msg_hw(tp))
2445e461
MC		 10653 netdev_err(tp->dev,
10654 "Register test failed at offset %x\n", offset);
a71116d1
MC		 10655 tw32(offset, save_val);
10656 return -EIO;
10657}
10658
7942e1db
MC		 10659static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10660{
f71e1309 10661 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10662 int i;
10663 u32 j;
10664
e9edda69 10665 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10666 for (j = 0; j < len; j += 4) {
10667 u32 val;
10668
10669 tg3_write_mem(tp, offset + j, test_pattern[i]);
10670 tg3_read_mem(tp, offset + j, &val);
10671 if (val != test_pattern[i])
10672 return -EIO;
10673 }
10674 }
10675 return 0;
10676}
10677
10678static int tg3_test_memory(struct tg3 *tp)
10679{
10680 static struct mem_entry {
10681 u32 offset;
10682 u32 len;
10683 } mem_tbl_570x[] = {
38690194 10684 { 0x00000000, 0x00b50},
7942e1db
MC		 10685 { 0x00002000, 0x1c000},
10686 { 0xffffffff, 0x00000}
10687 }, mem_tbl_5705[] = {
10688 { 0x00000100, 0x0000c},
10689 { 0x00000200, 0x00008},
7942e1db
MC		 10690 { 0x00004000, 0x00800},
10691 { 0x00006000, 0x01000},
10692 { 0x00008000, 0x02000},
10693 { 0x00010000, 0x0e000},
10694 { 0xffffffff, 0x00000}
79f4d13a
MC		 10695 }, mem_tbl_5755[] = {
10696 { 0x00000200, 0x00008},
10697 { 0x00004000, 0x00800},
10698 { 0x00006000, 0x00800},
10699 { 0x00008000, 0x02000},
10700 { 0x00010000, 0x0c000},
10701 { 0xffffffff, 0x00000}
b16250e3
MC		 10702 }, mem_tbl_5906[] = {
10703 { 0x00000200, 0x00008},
10704 { 0x00004000, 0x00400},
10705 { 0x00006000, 0x00400},
10706 { 0x00008000, 0x01000},
10707 { 0x00010000, 0x01000},
10708 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10709 }, mem_tbl_5717[] = {
10710 { 0x00000200, 0x00008},
10711 { 0x00010000, 0x0a000},
10712 { 0x00020000, 0x13c00},
10713 { 0xffffffff, 0x00000}
10714 }, mem_tbl_57765[] = {
10715 { 0x00000200, 0x00008},
10716 { 0x00004000, 0x00800},
10717 { 0x00006000, 0x09800},
10718 { 0x00010000, 0x0a000},
10719 { 0xffffffff, 0x00000}
7942e1db
MC		 10720 };
10721 struct mem_entry *mem_tbl;
10722 int err = 0;
10723 int i;
10724
8b5a6c42
MC		 10725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10726 mem_tbl = mem_tbl_5717;
10727 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10728 mem_tbl = mem_tbl_57765;
10729 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10730 mem_tbl = mem_tbl_5755;
10731 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10732 mem_tbl = mem_tbl_5906;
10733 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10734 mem_tbl = mem_tbl_5705;
10735 else
7942e1db
MC		 10736 mem_tbl = mem_tbl_570x;
10737
10738 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10739 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10740 mem_tbl[i].len)) != 0)
10741 break;
10742 }
6aa20a22 10743
7942e1db
MC		 10744 return err;
10745}
10746
9f40dead
MC		 10747#define TG3_MAC_LOOPBACK 0
10748#define TG3_PHY_LOOPBACK 1
10749
10750static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10751{
9f40dead 10752 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10753 u32 desc_idx, coal_now;
c76949a6
MC		 10754 struct sk_buff *skb, *rx_skb;
10755 u8 *tx_data;
10756 dma_addr_t map;
10757 int num_pkts, tx_len, rx_len, i, err;
10758 struct tg3_rx_buffer_desc *desc;
898a56f8 10759 struct tg3_napi *tnapi, *rnapi;
21f581a5 10760 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10761
c8873405
MC		 10762 tnapi = &tp->napi[0];
10763 rnapi = &tp->napi[0];
0c1d0e2b 10764 if (tp->irq_cnt > 1) {
0c1d0e2b 10765 rnapi = &tp->napi[1];
c8873405
MC		 10766 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10767 tnapi = &tp->napi[1];
0c1d0e2b 10768 }
fd2ce37f 10769 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10770
9f40dead 10771 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10772 /* HW errata - mac loopback fails in some cases on 5780.
10773 * Normal traffic and PHY loopback are not affected by
10774 * errata.
10775 */
10776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10777 return 0;
10778
9f40dead 10779 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10780 MAC_MODE_PORT_INT_LPBACK;
10781 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10782 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10783 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10784 mac_mode |= MAC_MODE_PORT_MODE_MII;
10785 else
10786 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10787 tw32(MAC_MODE, mac_mode);
10788 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10789 u32 val;
10790
7f97a4bd
MC		 10791 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10792 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10793 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10794 } else
10795 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10796
9ef8ca99
MC		 10797 tg3_phy_toggle_automdix(tp, 0);
10798
3f7045c1 10799 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10800 udelay(40);
5d64ad34 10801
e8f3f6ca 10802 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd 10803 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1061b7c5
MC		 10804 tg3_writephy(tp, MII_TG3_FET_PTEST,
10805 MII_TG3_FET_PTEST_FRC_TX_LINK |
10806 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10807 /* The write needs to be flushed for the AC131 */
10808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10809 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
5d64ad34
MC		 10810 mac_mode |= MAC_MODE_PORT_MODE_MII;
10811 } else
10812 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10813
c94e3941
MC		 10814 /* reset to prevent losing 1st rx packet intermittently */
10815 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10816 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10817 udelay(10);
10818 tw32_f(MAC_RX_MODE, tp->rx_mode);
10819 }
e8f3f6ca 10820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
79eb6904
MC		 10821 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10822 if (masked_phy_id == TG3_PHY_ID_BCM5401)
e8f3f6ca 10823 mac_mode &= ~MAC_MODE_LINK_POLARITY;
79eb6904 10824 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
e8f3f6ca 10825 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10826 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10827 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10828 }
9f40dead 10829 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10830 }
10831 else
10832 return -EINVAL;
c76949a6
MC		 10833
10834 err = -EIO;
10835
c76949a6 10836 tx_len = 1514;
a20e9c62 10837 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10838 if (!skb)
10839 return -ENOMEM;
10840
c76949a6
MC		 10841 tx_data = skb_put(skb, tx_len);
10842 memcpy(tx_data, tp->dev->dev_addr, 6);
10843 memset(tx_data + 6, 0x0, 8);
10844
10845 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10846
10847 for (i = 14; i < tx_len; i++)
10848 tx_data[i] = (u8) (i & 0xff);
10849
f4188d8a
AD		 10850 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10851 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10852 dev_kfree_skb(skb);
10853 return -EIO;
10854 }
c76949a6
MC		 10855
10856 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10857 rnapi->coal_now);
c76949a6
MC		 10858
10859 udelay(10);
10860
898a56f8 10861 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10862
c76949a6
MC		 10863 num_pkts = 0;
10864
f4188d8a 10865 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10866
f3f3f27e 10867 tnapi->tx_prod++;
c76949a6
MC		 10868 num_pkts++;
10869
f3f3f27e
MC		 10870 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10871 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10872
10873 udelay(10);
10874
303fc921
MC		 10875 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10876 for (i = 0; i < 35; i++) {
c76949a6 10877 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10878 coal_now);
c76949a6
MC		 10879
10880 udelay(10);
10881
898a56f8
MC		 10882 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10883 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10884 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10885 (rx_idx == (rx_start_idx + num_pkts)))
10886 break;
10887 }
10888
f4188d8a 10889 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10890 dev_kfree_skb(skb);
10891
f3f3f27e 10892 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10893 goto out;
10894
10895 if (rx_idx != rx_start_idx + num_pkts)
10896 goto out;
10897
72334482 10898 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10899 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10900 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10901 if (opaque_key != RXD_OPAQUE_RING_STD)
10902 goto out;
10903
10904 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10905 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10906 goto out;
10907
10908 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10909 if (rx_len != tx_len)
10910 goto out;
10911
21f581a5 10912 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10913
21f581a5 10914 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10915 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10916
10917 for (i = 14; i < tx_len; i++) {
10918 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10919 goto out;
10920 }
10921 err = 0;
6aa20a22 10922
c76949a6
MC		 10923 /* tg3_free_rings will unmap and free the rx_skb */
10924out:
10925 return err;
10926}
10927
9f40dead
MC		 10928#define TG3_MAC_LOOPBACK_FAILED 1
10929#define TG3_PHY_LOOPBACK_FAILED 2
10930#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10931 TG3_PHY_LOOPBACK_FAILED)
10932
10933static int tg3_test_loopback(struct tg3 *tp)
10934{
10935 int err = 0;
9936bcf6 10936 u32 cpmuctrl = 0;
9f40dead
MC		 10937
10938 if (!netif_running(tp->dev))
10939 return TG3_LOOPBACK_FAILED;
10940
b9ec6c1b
MC		 10941 err = tg3_reset_hw(tp, 1);
10942 if (err)
10943 return TG3_LOOPBACK_FAILED;
9f40dead 10944
6833c043
MC		 10945 /* Turn off gphy autopowerdown. */
10946 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10947 tg3_phy_toggle_apd(tp, false);
10948
321d32a0 10949 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10950 int i;
10951 u32 status;
10952
10953 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10954
10955 /* Wait for up to 40 microseconds to acquire lock. */
10956 for (i = 0; i < 4; i++) {
10957 status = tr32(TG3_CPMU_MUTEX_GNT);
10958 if (status == CPMU_MUTEX_GNT_DRIVER)
10959 break;
10960 udelay(10);
10961 }
10962
10963 if (status != CPMU_MUTEX_GNT_DRIVER)
10964 return TG3_LOOPBACK_FAILED;
10965
b2a5c19c 10966 /* Turn off link-based power management. */
e875093c 10967 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10968 tw32(TG3_CPMU_CTRL,
10969 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10970 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10971 }
10972
9f40dead
MC		 10973 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10974 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10975
321d32a0 10976 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10977 tw32(TG3_CPMU_CTRL, cpmuctrl);
10978
10979 /* Release the mutex */
10980 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10981 }
10982
dd477003
MC		 10983 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10984 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10985 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10986 err |= TG3_PHY_LOOPBACK_FAILED;
10987 }
10988
6833c043
MC		 10989 /* Re-enable gphy autopowerdown. */
10990 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10991 tg3_phy_toggle_apd(tp, true);
10992
9f40dead
MC		 10993 return err;
10994}
10995
4cafd3f5
MC		 10996static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10997 u64 *data)
10998{
566f86ad
MC		 10999 struct tg3 *tp = netdev_priv(dev);
11000
bc1c7567
MC		 11001 if (tp->link_config.phy_is_low_power)
11002 tg3_set_power_state(tp, PCI_D0);
11003
566f86ad
MC		 11004 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11005
11006 if (tg3_test_nvram(tp) != 0) {
11007 etest->flags |= ETH_TEST_FL_FAILED;
11008 data[0] = 1;
11009 }
ca43007a
MC		 11010 if (tg3_test_link(tp) != 0) {
11011 etest->flags |= ETH_TEST_FL_FAILED;
11012 data[1] = 1;
11013 }
a71116d1 11014 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 11015 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 11016
11017 if (netif_running(dev)) {
b02fd9e3 11018 tg3_phy_stop(tp);
a71116d1 11019 tg3_netif_stop(tp);
bbe832c0
MC		 11020 irq_sync = 1;
11021 }
a71116d1 11022
bbe832c0 11023 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 11024
11025 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 11026 err = tg3_nvram_lock(tp);
a71116d1
MC		 11027 tg3_halt_cpu(tp, RX_CPU_BASE);
11028 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11029 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 11030 if (!err)
11031 tg3_nvram_unlock(tp);
a71116d1 11032
d9ab5ad1
MC		 11033 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11034 tg3_phy_reset(tp);
11035
a71116d1
MC		 11036 if (tg3_test_registers(tp) != 0) {
11037 etest->flags |= ETH_TEST_FL_FAILED;
11038 data[2] = 1;
11039 }
7942e1db
MC		 11040 if (tg3_test_memory(tp) != 0) {
11041 etest->flags |= ETH_TEST_FL_FAILED;
11042 data[3] = 1;
11043 }
9f40dead 11044 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 11045 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 11046
f47c11ee
DM		 11047 tg3_full_unlock(tp);
11048
d4bc3927
MC		 11049 if (tg3_test_interrupt(tp) != 0) {
11050 etest->flags |= ETH_TEST_FL_FAILED;
11051 data[5] = 1;
11052 }
f47c11ee
DM		 11053
11054 tg3_full_lock(tp, 0);
d4bc3927 11055
a71116d1
MC		 11056 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11057 if (netif_running(dev)) {
11058 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 11059 err2 = tg3_restart_hw(tp, 1);
11060 if (!err2)
b9ec6c1b 11061 tg3_netif_start(tp);
a71116d1 11062 }
f47c11ee
DM		 11063
11064 tg3_full_unlock(tp);
b02fd9e3
MC		 11065
11066 if (irq_sync && !err2)
11067 tg3_phy_start(tp);
a71116d1 11068 }
bc1c7567
MC		 11069 if (tp->link_config.phy_is_low_power)
11070 tg3_set_power_state(tp, PCI_D3hot);
11071
4cafd3f5
MC		 11072}
11073
1da177e4
LT		 11074static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11075{
11076 struct mii_ioctl_data *data = if_mii(ifr);
11077 struct tg3 *tp = netdev_priv(dev);
11078 int err;
11079
b02fd9e3 11080 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11081 struct phy_device *phydev;
b02fd9e3
MC		 11082 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11083 return -EAGAIN;
3f0e3ad7
MC		 11084 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11085 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11086 }
11087
1da177e4
LT		 11088 switch(cmd) {
11089 case SIOCGMIIPHY:
882e9793 11090 data->phy_id = tp->phy_addr;
1da177e4
LT		 11091
11092 /* fallthru */
11093 case SIOCGMIIREG: {
11094 u32 mii_regval;
11095
11096 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11097 break; /* We have no PHY */
11098
bc1c7567
MC		 11099 if (tp->link_config.phy_is_low_power)
11100 return -EAGAIN;
11101
f47c11ee 11102 spin_lock_bh(&tp->lock);
1da177e4 11103 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11104 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11105
11106 data->val_out = mii_regval;
11107
11108 return err;
11109 }
11110
11111 case SIOCSMIIREG:
11112 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11113 break; /* We have no PHY */
11114
bc1c7567
MC		 11115 if (tp->link_config.phy_is_low_power)
11116 return -EAGAIN;
11117
f47c11ee 11118 spin_lock_bh(&tp->lock);
1da177e4 11119 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11120 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11121
11122 return err;
11123
11124 default:
11125 /* do nothing */
11126 break;
11127 }
11128 return -EOPNOTSUPP;
11129}
11130
11131#if TG3_VLAN_TAG_USED
11132static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11133{
11134 struct tg3 *tp = netdev_priv(dev);
11135
844b3eed
MC		 11136 if (!netif_running(dev)) {
11137 tp->vlgrp = grp;
11138 return;
11139 }
11140
11141 tg3_netif_stop(tp);
29315e87 11142
f47c11ee 11143 tg3_full_lock(tp, 0);
1da177e4
LT		 11144
11145 tp->vlgrp = grp;
11146
11147 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11148 __tg3_set_rx_mode(dev);
11149
844b3eed 11150 tg3_netif_start(tp);
46966545
MC		 11151
11152 tg3_full_unlock(tp);
1da177e4 11153}
1da177e4
LT		 11154#endif
11155
15f9850d
DM		 11156static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11157{
11158 struct tg3 *tp = netdev_priv(dev);
11159
11160 memcpy(ec, &tp->coal, sizeof(*ec));
11161 return 0;
11162}
11163
d244c892
MC		 11164static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11165{
11166 struct tg3 *tp = netdev_priv(dev);
11167 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11168 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11169
11170 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11171 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11172 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11173 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11174 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11175 }
11176
11177 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11178 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11179 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11180 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11181 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11182 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11183 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11184 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11185 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11186 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11187 return -EINVAL;
11188
11189 /* No rx interrupts will be generated if both are zero */
11190 if ((ec->rx_coalesce_usecs == 0) &&
11191 (ec->rx_max_coalesced_frames == 0))
11192 return -EINVAL;
11193
11194 /* No tx interrupts will be generated if both are zero */
11195 if ((ec->tx_coalesce_usecs == 0) &&
11196 (ec->tx_max_coalesced_frames == 0))
11197 return -EINVAL;
11198
11199 /* Only copy relevant parameters, ignore all others. */
11200 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11201 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11202 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11203 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11204 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11205 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11206 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11207 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11208 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11209
11210 if (netif_running(dev)) {
11211 tg3_full_lock(tp, 0);
11212 __tg3_set_coalesce(tp, &tp->coal);
11213 tg3_full_unlock(tp);
11214 }
11215 return 0;
11216}
11217
7282d491 11218static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11219 .get_settings = tg3_get_settings,
11220 .set_settings = tg3_set_settings,
11221 .get_drvinfo = tg3_get_drvinfo,
11222 .get_regs_len = tg3_get_regs_len,
11223 .get_regs = tg3_get_regs,
11224 .get_wol = tg3_get_wol,
11225 .set_wol = tg3_set_wol,
11226 .get_msglevel = tg3_get_msglevel,
11227 .set_msglevel = tg3_set_msglevel,
11228 .nway_reset = tg3_nway_reset,
11229 .get_link = ethtool_op_get_link,
11230 .get_eeprom_len = tg3_get_eeprom_len,
11231 .get_eeprom = tg3_get_eeprom,
11232 .set_eeprom = tg3_set_eeprom,
11233 .get_ringparam = tg3_get_ringparam,
11234 .set_ringparam = tg3_set_ringparam,
11235 .get_pauseparam = tg3_get_pauseparam,
11236 .set_pauseparam = tg3_set_pauseparam,
11237 .get_rx_csum = tg3_get_rx_csum,
11238 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11239 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11240 .set_sg = ethtool_op_set_sg,
1da177e4 11241 .set_tso = tg3_set_tso,
4cafd3f5 11242 .self_test = tg3_self_test,
1da177e4 11243 .get_strings = tg3_get_strings,
4009a93d 11244 .phys_id = tg3_phys_id,
1da177e4 11245 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11246 .get_coalesce = tg3_get_coalesce,
d244c892 11247 .set_coalesce = tg3_set_coalesce,
b9f2c044 11248 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11249};
11250
11251static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11252{
1b27777a 11253 u32 cursize, val, magic;
1da177e4
LT		 11254
11255 tp->nvram_size = EEPROM_CHIP_SIZE;
11256
e4f34110 11257 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11258 return;
11259
b16250e3
MC		 11260 if ((magic != TG3_EEPROM_MAGIC) &&
11261 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11262 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11263 return;
11264
11265 /*
11266 * Size the chip by reading offsets at increasing powers of two.
11267 * When we encounter our validation signature, we know the addressing
11268 * has wrapped around, and thus have our chip size.
11269 */
1b27777a 11270 cursize = 0x10;
1da177e4
LT		 11271
11272 while (cursize < tp->nvram_size) {
e4f34110 11273 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11274 return;
11275
1820180b 11276 if (val == magic)
1da177e4
LT		 11277 break;
11278
11279 cursize <<= 1;
11280 }
11281
11282 tp->nvram_size = cursize;
11283}
6aa20a22 11284
1da177e4
LT		 11285static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11286{
11287 u32 val;
11288
df259d8c
MC		 11289 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11290 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11291 return;
11292
11293 /* Selfboot format */
1820180b 11294 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11295 tg3_get_eeprom_size(tp);
11296 return;
11297 }
11298
6d348f2c 11299 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11300 if (val != 0) {
6d348f2c
MC		 11301 /* This is confusing. We want to operate on the
11302 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11303 * call will read from NVRAM and byteswap the data
11304 * according to the byteswapping settings for all
11305 * other register accesses. This ensures the data we
11306 * want will always reside in the lower 16-bits.
11307 * However, the data in NVRAM is in LE format, which
11308 * means the data from the NVRAM read will always be
11309 * opposite the endianness of the CPU. The 16-bit
11310 * byteswap then brings the data to CPU endianness.
11311 */
11312 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11313 return;
11314 }
11315 }
fd1122a2 11316 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11317}
11318
11319static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11320{
11321 u32 nvcfg1;
11322
11323 nvcfg1 = tr32(NVRAM_CFG1);
11324 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11325 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11326 } else {
1da177e4
LT		 11327 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11328 tw32(NVRAM_CFG1, nvcfg1);
11329 }
11330
4c987487 11331 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11332 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11333 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11334 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11335 tp->nvram_jedecnum = JEDEC_ATMEL;
11336 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11337 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11338 break;
11339 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11340 tp->nvram_jedecnum = JEDEC_ATMEL;
11341 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11342 break;
11343 case FLASH_VENDOR_ATMEL_EEPROM:
11344 tp->nvram_jedecnum = JEDEC_ATMEL;
11345 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11346 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11347 break;
11348 case FLASH_VENDOR_ST:
11349 tp->nvram_jedecnum = JEDEC_ST;
11350 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11351 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11352 break;
11353 case FLASH_VENDOR_SAIFUN:
11354 tp->nvram_jedecnum = JEDEC_SAIFUN;
11355 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11356 break;
11357 case FLASH_VENDOR_SST_SMALL:
11358 case FLASH_VENDOR_SST_LARGE:
11359 tp->nvram_jedecnum = JEDEC_SST;
11360 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11361 break;
1da177e4 11362 }
8590a603 11363 } else {
1da177e4
LT		 11364 tp->nvram_jedecnum = JEDEC_ATMEL;
11365 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367 }
11368}
11369
a1b950d5
MC		 11370static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11371{
11372 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11373 case FLASH_5752PAGE_SIZE_256:
11374 tp->nvram_pagesize = 256;
11375 break;
11376 case FLASH_5752PAGE_SIZE_512:
11377 tp->nvram_pagesize = 512;
11378 break;
11379 case FLASH_5752PAGE_SIZE_1K:
11380 tp->nvram_pagesize = 1024;
11381 break;
11382 case FLASH_5752PAGE_SIZE_2K:
11383 tp->nvram_pagesize = 2048;
11384 break;
11385 case FLASH_5752PAGE_SIZE_4K:
11386 tp->nvram_pagesize = 4096;
11387 break;
11388 case FLASH_5752PAGE_SIZE_264:
11389 tp->nvram_pagesize = 264;
11390 break;
11391 case FLASH_5752PAGE_SIZE_528:
11392 tp->nvram_pagesize = 528;
11393 break;
11394 }
11395}
11396
361b4ac2
MC		 11397static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11398{
11399 u32 nvcfg1;
11400
11401 nvcfg1 = tr32(NVRAM_CFG1);
11402
e6af301b
MC		 11403 /* NVRAM protection for TPM */
11404 if (nvcfg1 & (1 << 27))
f66a29b0 11405 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11406
361b4ac2 11407 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11408 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11409 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11410 tp->nvram_jedecnum = JEDEC_ATMEL;
11411 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11412 break;
11413 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11414 tp->nvram_jedecnum = JEDEC_ATMEL;
11415 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11416 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11417 break;
11418 case FLASH_5752VENDOR_ST_M45PE10:
11419 case FLASH_5752VENDOR_ST_M45PE20:
11420 case FLASH_5752VENDOR_ST_M45PE40:
11421 tp->nvram_jedecnum = JEDEC_ST;
11422 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11423 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11424 break;
361b4ac2
MC		 11425 }
11426
11427 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11428 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11429 } else {
361b4ac2
MC		 11430 /* For eeprom, set pagesize to maximum eeprom size */
11431 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11432
11433 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11434 tw32(NVRAM_CFG1, nvcfg1);
11435 }
11436}
11437
d3c7b886
MC		 11438static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11439{
989a9d23 11440 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11441
11442 nvcfg1 = tr32(NVRAM_CFG1);
11443
11444 /* NVRAM protection for TPM */
989a9d23 11445 if (nvcfg1 & (1 << 27)) {
f66a29b0 11446 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11447 protect = 1;
11448 }
d3c7b886 11449
989a9d23
MC		 11450 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11451 switch (nvcfg1) {
8590a603
MC		 11452 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11453 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11454 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11455 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11456 tp->nvram_jedecnum = JEDEC_ATMEL;
11457 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11458 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11459 tp->nvram_pagesize = 264;
11460 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11461 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11462 tp->nvram_size = (protect ? 0x3e200 :
11463 TG3_NVRAM_SIZE_512KB);
11464 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11465 tp->nvram_size = (protect ? 0x1f200 :
11466 TG3_NVRAM_SIZE_256KB);
11467 else
11468 tp->nvram_size = (protect ? 0x1f200 :
11469 TG3_NVRAM_SIZE_128KB);
11470 break;
11471 case FLASH_5752VENDOR_ST_M45PE10:
11472 case FLASH_5752VENDOR_ST_M45PE20:
11473 case FLASH_5752VENDOR_ST_M45PE40:
11474 tp->nvram_jedecnum = JEDEC_ST;
11475 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11476 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11477 tp->nvram_pagesize = 256;
11478 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11479 tp->nvram_size = (protect ?
11480 TG3_NVRAM_SIZE_64KB :
11481 TG3_NVRAM_SIZE_128KB);
11482 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11483 tp->nvram_size = (protect ?
11484 TG3_NVRAM_SIZE_64KB :
11485 TG3_NVRAM_SIZE_256KB);
11486 else
11487 tp->nvram_size = (protect ?
11488 TG3_NVRAM_SIZE_128KB :
11489 TG3_NVRAM_SIZE_512KB);
11490 break;
d3c7b886
MC		 11491 }
11492}
11493
1b27777a
MC		 11494static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11495{
11496 u32 nvcfg1;
11497
11498 nvcfg1 = tr32(NVRAM_CFG1);
11499
11500 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11501 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11502 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11503 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11504 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11505 tp->nvram_jedecnum = JEDEC_ATMEL;
11506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11507 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11508
8590a603
MC		 11509 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11510 tw32(NVRAM_CFG1, nvcfg1);
11511 break;
11512 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11513 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11514 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11515 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11516 tp->nvram_jedecnum = JEDEC_ATMEL;
11517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11519 tp->nvram_pagesize = 264;
11520 break;
11521 case FLASH_5752VENDOR_ST_M45PE10:
11522 case FLASH_5752VENDOR_ST_M45PE20:
11523 case FLASH_5752VENDOR_ST_M45PE40:
11524 tp->nvram_jedecnum = JEDEC_ST;
11525 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11526 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11527 tp->nvram_pagesize = 256;
11528 break;
1b27777a
MC		 11529 }
11530}
11531
6b91fa02
MC		 11532static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11533{
11534 u32 nvcfg1, protect = 0;
11535
11536 nvcfg1 = tr32(NVRAM_CFG1);
11537
11538 /* NVRAM protection for TPM */
11539 if (nvcfg1 & (1 << 27)) {
f66a29b0 11540 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11541 protect = 1;
11542 }
11543
11544 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11545 switch (nvcfg1) {
8590a603
MC		 11546 case FLASH_5761VENDOR_ATMEL_ADB021D:
11547 case FLASH_5761VENDOR_ATMEL_ADB041D:
11548 case FLASH_5761VENDOR_ATMEL_ADB081D:
11549 case FLASH_5761VENDOR_ATMEL_ADB161D:
11550 case FLASH_5761VENDOR_ATMEL_MDB021D:
11551 case FLASH_5761VENDOR_ATMEL_MDB041D:
11552 case FLASH_5761VENDOR_ATMEL_MDB081D:
11553 case FLASH_5761VENDOR_ATMEL_MDB161D:
11554 tp->nvram_jedecnum = JEDEC_ATMEL;
11555 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11556 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11557 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11558 tp->nvram_pagesize = 256;
11559 break;
11560 case FLASH_5761VENDOR_ST_A_M45PE20:
11561 case FLASH_5761VENDOR_ST_A_M45PE40:
11562 case FLASH_5761VENDOR_ST_A_M45PE80:
11563 case FLASH_5761VENDOR_ST_A_M45PE16:
11564 case FLASH_5761VENDOR_ST_M_M45PE20:
11565 case FLASH_5761VENDOR_ST_M_M45PE40:
11566 case FLASH_5761VENDOR_ST_M_M45PE80:
11567 case FLASH_5761VENDOR_ST_M_M45PE16:
11568 tp->nvram_jedecnum = JEDEC_ST;
11569 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11570 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11571 tp->nvram_pagesize = 256;
11572 break;
6b91fa02
MC		 11573 }
11574
11575 if (protect) {
11576 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11577 } else {
11578 switch (nvcfg1) {
8590a603
MC		 11579 case FLASH_5761VENDOR_ATMEL_ADB161D:
11580 case FLASH_5761VENDOR_ATMEL_MDB161D:
11581 case FLASH_5761VENDOR_ST_A_M45PE16:
11582 case FLASH_5761VENDOR_ST_M_M45PE16:
11583 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11584 break;
11585 case FLASH_5761VENDOR_ATMEL_ADB081D:
11586 case FLASH_5761VENDOR_ATMEL_MDB081D:
11587 case FLASH_5761VENDOR_ST_A_M45PE80:
11588 case FLASH_5761VENDOR_ST_M_M45PE80:
11589 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11590 break;
11591 case FLASH_5761VENDOR_ATMEL_ADB041D:
11592 case FLASH_5761VENDOR_ATMEL_MDB041D:
11593 case FLASH_5761VENDOR_ST_A_M45PE40:
11594 case FLASH_5761VENDOR_ST_M_M45PE40:
11595 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11596 break;
11597 case FLASH_5761VENDOR_ATMEL_ADB021D:
11598 case FLASH_5761VENDOR_ATMEL_MDB021D:
11599 case FLASH_5761VENDOR_ST_A_M45PE20:
11600 case FLASH_5761VENDOR_ST_M_M45PE20:
11601 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11602 break;
6b91fa02
MC		 11603 }
11604 }
11605}
11606
b5d3772c
MC		 11607static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11608{
11609 tp->nvram_jedecnum = JEDEC_ATMEL;
11610 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11611 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11612}
11613
321d32a0
MC		 11614static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11615{
11616 u32 nvcfg1;
11617
11618 nvcfg1 = tr32(NVRAM_CFG1);
11619
11620 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11621 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11622 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11623 tp->nvram_jedecnum = JEDEC_ATMEL;
11624 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11625 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11626
11627 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11628 tw32(NVRAM_CFG1, nvcfg1);
11629 return;
11630 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11631 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11632 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11633 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11634 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11635 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11636 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11637 tp->nvram_jedecnum = JEDEC_ATMEL;
11638 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11639 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11640
11641 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11642 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11643 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11644 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11645 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11646 break;
11647 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11648 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11649 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11650 break;
11651 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11652 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11653 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11654 break;
11655 }
11656 break;
11657 case FLASH_5752VENDOR_ST_M45PE10:
11658 case FLASH_5752VENDOR_ST_M45PE20:
11659 case FLASH_5752VENDOR_ST_M45PE40:
11660 tp->nvram_jedecnum = JEDEC_ST;
11661 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11662 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11663
11664 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11665 case FLASH_5752VENDOR_ST_M45PE10:
11666 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11667 break;
11668 case FLASH_5752VENDOR_ST_M45PE20:
11669 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11670 break;
11671 case FLASH_5752VENDOR_ST_M45PE40:
11672 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11673 break;
11674 }
11675 break;
11676 default:
df259d8c 11677 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11678 return;
11679 }
11680
a1b950d5
MC		 11681 tg3_nvram_get_pagesize(tp, nvcfg1);
11682 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11683 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11684}
11685
11686
11687static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11688{
11689 u32 nvcfg1;
11690
11691 nvcfg1 = tr32(NVRAM_CFG1);
11692
11693 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11694 case FLASH_5717VENDOR_ATMEL_EEPROM:
11695 case FLASH_5717VENDOR_MICRO_EEPROM:
11696 tp->nvram_jedecnum = JEDEC_ATMEL;
11697 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11698 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11699
11700 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11701 tw32(NVRAM_CFG1, nvcfg1);
11702 return;
11703 case FLASH_5717VENDOR_ATMEL_MDB011D:
11704 case FLASH_5717VENDOR_ATMEL_ADB011B:
11705 case FLASH_5717VENDOR_ATMEL_ADB011D:
11706 case FLASH_5717VENDOR_ATMEL_MDB021D:
11707 case FLASH_5717VENDOR_ATMEL_ADB021B:
11708 case FLASH_5717VENDOR_ATMEL_ADB021D:
11709 case FLASH_5717VENDOR_ATMEL_45USPT:
11710 tp->nvram_jedecnum = JEDEC_ATMEL;
11711 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11712 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11713
11714 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11715 case FLASH_5717VENDOR_ATMEL_MDB021D:
11716 case FLASH_5717VENDOR_ATMEL_ADB021B:
11717 case FLASH_5717VENDOR_ATMEL_ADB021D:
11718 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11719 break;
11720 default:
11721 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11722 break;
11723 }
321d32a0 11724 break;
a1b950d5
MC		 11725 case FLASH_5717VENDOR_ST_M_M25PE10:
11726 case FLASH_5717VENDOR_ST_A_M25PE10:
11727 case FLASH_5717VENDOR_ST_M_M45PE10:
11728 case FLASH_5717VENDOR_ST_A_M45PE10:
11729 case FLASH_5717VENDOR_ST_M_M25PE20:
11730 case FLASH_5717VENDOR_ST_A_M25PE20:
11731 case FLASH_5717VENDOR_ST_M_M45PE20:
11732 case FLASH_5717VENDOR_ST_A_M45PE20:
11733 case FLASH_5717VENDOR_ST_25USPT:
11734 case FLASH_5717VENDOR_ST_45USPT:
11735 tp->nvram_jedecnum = JEDEC_ST;
11736 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11737 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11738
11739 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11740 case FLASH_5717VENDOR_ST_M_M25PE20:
11741 case FLASH_5717VENDOR_ST_A_M25PE20:
11742 case FLASH_5717VENDOR_ST_M_M45PE20:
11743 case FLASH_5717VENDOR_ST_A_M45PE20:
11744 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11745 break;
11746 default:
11747 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11748 break;
11749 }
321d32a0 11750 break;
a1b950d5
MC		 11751 default:
11752 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11753 return;
321d32a0 11754 }
a1b950d5
MC		 11755
11756 tg3_nvram_get_pagesize(tp, nvcfg1);
11757 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11758 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11759}
11760
1da177e4
LT		 11761/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11762static void __devinit tg3_nvram_init(struct tg3 *tp)
11763{
1da177e4
LT		 11764 tw32_f(GRC_EEPROM_ADDR,
11765 (EEPROM_ADDR_FSM_RESET |
11766 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11767 EEPROM_ADDR_CLKPERD_SHIFT)));
11768
9d57f01c 11769 msleep(1);
1da177e4
LT		 11770
11771 /* Enable seeprom accesses. */
11772 tw32_f(GRC_LOCAL_CTRL,
11773 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11774 udelay(100);
11775
11776 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11777 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11778 tp->tg3_flags |= TG3_FLAG_NVRAM;
11779
ec41c7df 11780 if (tg3_nvram_lock(tp)) {
05dbe005
JP		 11781 netdev_warn(tp->dev, "Cannot get nvram lock, %s failed\n",
11782 __func__);
ec41c7df
MC		 11783 return;
11784 }
e6af301b 11785 tg3_enable_nvram_access(tp);
1da177e4 11786
989a9d23
MC		 11787 tp->nvram_size = 0;
11788
361b4ac2
MC		 11789 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11790 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11791 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11792 tg3_get_5755_nvram_info(tp);
d30cdd28 11793 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11794 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11796 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11797 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11798 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11799 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11800 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11801 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11803 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11804 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11805 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11806 else
11807 tg3_get_nvram_info(tp);
11808
989a9d23
MC		 11809 if (tp->nvram_size == 0)
11810 tg3_get_nvram_size(tp);
1da177e4 11811
e6af301b 11812 tg3_disable_nvram_access(tp);
381291b7 11813 tg3_nvram_unlock(tp);
1da177e4
LT		 11814
11815 } else {
11816 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11817
11818 tg3_get_eeprom_size(tp);
11819 }
11820}
11821
1da177e4
LT		 11822static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11823 u32 offset, u32 len, u8 *buf)
11824{
11825 int i, j, rc = 0;
11826 u32 val;
11827
11828 for (i = 0; i < len; i += 4) {
b9fc7dc5 11829 u32 addr;
a9dc529d 11830 __be32 data;
1da177e4
LT		 11831
11832 addr = offset + i;
11833
11834 memcpy(&data, buf + i, 4);
11835
62cedd11
MC		 11836 /*
11837 * The SEEPROM interface expects the data to always be opposite
11838 * the native endian format. We accomplish this by reversing
11839 * all the operations that would have been performed on the
11840 * data from a call to tg3_nvram_read_be32().
11841 */
11842 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11843
11844 val = tr32(GRC_EEPROM_ADDR);
11845 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11846
11847 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11848 EEPROM_ADDR_READ);
11849 tw32(GRC_EEPROM_ADDR, val |
11850 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11851 (addr & EEPROM_ADDR_ADDR_MASK) |
11852 EEPROM_ADDR_START |
11853 EEPROM_ADDR_WRITE);
6aa20a22 11854
9d57f01c 11855 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11856 val = tr32(GRC_EEPROM_ADDR);
11857
11858 if (val & EEPROM_ADDR_COMPLETE)
11859 break;
9d57f01c 11860 msleep(1);
1da177e4
LT		 11861 }
11862 if (!(val & EEPROM_ADDR_COMPLETE)) {
11863 rc = -EBUSY;
11864 break;
11865 }
11866 }
11867
11868 return rc;
11869}
11870
11871/* offset and length are dword aligned */
11872static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11873 u8 *buf)
11874{
11875 int ret = 0;
11876 u32 pagesize = tp->nvram_pagesize;
11877 u32 pagemask = pagesize - 1;
11878 u32 nvram_cmd;
11879 u8 *tmp;
11880
11881 tmp = kmalloc(pagesize, GFP_KERNEL);
11882 if (tmp == NULL)
11883 return -ENOMEM;
11884
11885 while (len) {
11886 int j;
e6af301b 11887 u32 phy_addr, page_off, size;
1da177e4
LT		 11888
11889 phy_addr = offset & ~pagemask;
6aa20a22 11890
1da177e4 11891 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11892 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11893 (__be32 *) (tmp + j));
11894 if (ret)
1da177e4
LT		 11895 break;
11896 }
11897 if (ret)
11898 break;
11899
11900 page_off = offset & pagemask;
11901 size = pagesize;
11902 if (len < size)
11903 size = len;
11904
11905 len -= size;
11906
11907 memcpy(tmp + page_off, buf, size);
11908
11909 offset = offset + (pagesize - page_off);
11910
e6af301b 11911 tg3_enable_nvram_access(tp);
1da177e4
LT		 11912
11913 /*
11914 * Before we can erase the flash page, we need
11915 * to issue a special "write enable" command.
11916 */
11917 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11918
11919 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11920 break;
11921
11922 /* Erase the target page */
11923 tw32(NVRAM_ADDR, phy_addr);
11924
11925 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11926 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11927
11928 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11929 break;
11930
11931 /* Issue another write enable to start the write. */
11932 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11933
11934 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11935 break;
11936
11937 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11938 __be32 data;
1da177e4 11939
b9fc7dc5 11940 data = *((__be32 *) (tmp + j));
a9dc529d 11941
b9fc7dc5 11942 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11943
11944 tw32(NVRAM_ADDR, phy_addr + j);
11945
11946 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11947 NVRAM_CMD_WR;
11948
11949 if (j == 0)
11950 nvram_cmd |= NVRAM_CMD_FIRST;
11951 else if (j == (pagesize - 4))
11952 nvram_cmd |= NVRAM_CMD_LAST;
11953
11954 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11955 break;
11956 }
11957 if (ret)
11958 break;
11959 }
11960
11961 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11962 tg3_nvram_exec_cmd(tp, nvram_cmd);
11963
11964 kfree(tmp);
11965
11966 return ret;
11967}
11968
11969/* offset and length are dword aligned */
11970static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11971 u8 *buf)
11972{
11973 int i, ret = 0;
11974
11975 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11976 u32 page_off, phy_addr, nvram_cmd;
11977 __be32 data;
1da177e4
LT		 11978
11979 memcpy(&data, buf + i, 4);
b9fc7dc5 11980 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11981
11982 page_off = offset % tp->nvram_pagesize;
11983
1820180b 11984 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11985
11986 tw32(NVRAM_ADDR, phy_addr);
11987
11988 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11989
11990 if ((page_off == 0) || (i == 0))
11991 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11992 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11993 nvram_cmd |= NVRAM_CMD_LAST;
11994
11995 if (i == (len - 4))
11996 nvram_cmd |= NVRAM_CMD_LAST;
11997
321d32a0
MC		 11998 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11999 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 12000 (tp->nvram_jedecnum == JEDEC_ST) &&
12001 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 12002
12003 if ((ret = tg3_nvram_exec_cmd(tp,
12004 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12005 NVRAM_CMD_DONE)))
12006
12007 break;
12008 }
12009 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12010 /* We always do complete word writes to eeprom. */
12011 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12012 }
12013
12014 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12015 break;
12016 }
12017 return ret;
12018}
12019
12020/* offset and length are dword aligned */
12021static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12022{
12023 int ret;
12024
1da177e4 12025 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 12026 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12027 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 12028 udelay(40);
12029 }
12030
12031 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12032 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12033 }
12034 else {
12035 u32 grc_mode;
12036
ec41c7df
MC		 12037 ret = tg3_nvram_lock(tp);
12038 if (ret)
12039 return ret;
1da177e4 12040
e6af301b
MC		 12041 tg3_enable_nvram_access(tp);
12042 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 12043 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 12044 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 12045
12046 grc_mode = tr32(GRC_MODE);
12047 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12048
12049 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12050 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12051
12052 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12053 buf);
12054 }
12055 else {
12056 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12057 buf);
12058 }
12059
12060 grc_mode = tr32(GRC_MODE);
12061 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12062
e6af301b 12063 tg3_disable_nvram_access(tp);
1da177e4
LT		 12064 tg3_nvram_unlock(tp);
12065 }
12066
12067 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 12068 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 12069 udelay(40);
12070 }
12071
12072 return ret;
12073}
12074
12075struct subsys_tbl_ent {
12076 u16 subsys_vendor, subsys_devid;
12077 u32 phy_id;
12078};
12079
24daf2b0 12080static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
1da177e4 12081 /* Broadcom boards. */
24daf2b0 12082 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12083 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 12084 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12085 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 12086 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12087 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 12088 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12089 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12090 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12091 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 12092 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12093 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12094 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12095 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12096 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12097 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 12098 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12099 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 12100 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12101 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 12102 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12103 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 12104
12105 /* 3com boards. */
24daf2b0 12106 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12107 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 12108 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12109 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12110 { TG3PCI_SUBVENDOR_ID_3COM,
12111 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12112 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12113 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 12114 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12115 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 12116
12117 /* DELL boards. */
24daf2b0 12118 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12119 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 12120 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12121 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 12122 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12123 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 12124 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12125 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 12126
12127 /* Compaq boards. */
24daf2b0 12128 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12129 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 12130 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12131 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12132 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12133 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12134 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12135 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 12136 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12137 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 12138
12139 /* IBM boards. */
24daf2b0
MC		 12140 { TG3PCI_SUBVENDOR_ID_IBM,
12141 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 12142};
12143
24daf2b0 12144static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 12145{
12146 int i;
12147
12148 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12149 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12150 tp->pdev->subsystem_vendor) &&
12151 (subsys_id_to_phy_id[i].subsys_devid ==
12152 tp->pdev->subsystem_device))
12153 return &subsys_id_to_phy_id[i];
12154 }
12155 return NULL;
12156}
12157
7d0c41ef 12158static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12159{
1da177e4 12160 u32 val;
caf636c7
MC		 12161 u16 pmcsr;
12162
12163 /* On some early chips the SRAM cannot be accessed in D3hot state,
12164 * so need make sure we're in D0.
12165 */
12166 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12167 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12168 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12169 msleep(1);
7d0c41ef
MC		 12170
12171 /* Make sure register accesses (indirect or otherwise)
12172 * will function correctly.
12173 */
12174 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12175 tp->misc_host_ctrl);
1da177e4 12176
f49639e6
DM		 12177 /* The memory arbiter has to be enabled in order for SRAM accesses
12178 * to succeed. Normally on powerup the tg3 chip firmware will make
12179 * sure it is enabled, but other entities such as system netboot
12180 * code might disable it.
12181 */
12182 val = tr32(MEMARB_MODE);
12183 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12184
79eb6904 12185 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 12186 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12187
a85feb8c
GZ		 12188 /* Assume an onboard device and WOL capable by default. */
12189 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12190
b5d3772c 12191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12192 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12193 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12194 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12195 }
0527ba35
MC		 12196 val = tr32(VCPU_CFGSHDW);
12197 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12198 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12199 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12200 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12201 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12202 goto done;
b5d3772c
MC		 12203 }
12204
1da177e4
LT		 12205 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12206 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12207 u32 nic_cfg, led_cfg;
a9daf367 12208 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12209 int eeprom_phy_serdes = 0;
1da177e4
LT		 12210
12211 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12212 tp->nic_sram_data_cfg = nic_cfg;
12213
12214 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12215 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12216 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12217 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12218 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12219 (ver > 0) && (ver < 0x100))
12220 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12221
a9daf367
MC		 12222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12223 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12224
1da177e4
LT		 12225 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12226 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12227 eeprom_phy_serdes = 1;
12228
12229 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12230 if (nic_phy_id != 0) {
12231 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12232 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12233
12234 eeprom_phy_id = (id1 >> 16) << 10;
12235 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12236 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12237 } else
12238 eeprom_phy_id = 0;
12239
7d0c41ef 12240 tp->phy_id = eeprom_phy_id;
747e8f8b 12241 if (eeprom_phy_serdes) {
d1ec96af
MC		 12242 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12243 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12244 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12245 else
12246 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12247 }
7d0c41ef 12248
cbf46853 12249 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12250 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12251 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12252 else
1da177e4
LT		 12253 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12254
12255 switch (led_cfg) {
12256 default:
12257 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12258 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12259 break;
12260
12261 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12262 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12263 break;
12264
12265 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12266 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12267
12268 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12269 * read on some older 5700/5701 bootcode.
12270 */
12271 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12272 ASIC_REV_5700 ||
12273 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12274 ASIC_REV_5701)
12275 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12276
1da177e4
LT		 12277 break;
12278
12279 case SHASTA_EXT_LED_SHARED:
12280 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12281 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12282 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12283 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12284 LED_CTRL_MODE_PHY_2);
12285 break;
12286
12287 case SHASTA_EXT_LED_MAC:
12288 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12289 break;
12290
12291 case SHASTA_EXT_LED_COMBO:
12292 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12293 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12294 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12295 LED_CTRL_MODE_PHY_2);
12296 break;
12297
855e1111 12298 }
1da177e4
LT		 12299
12300 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12301 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12302 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12303 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12304
b2a5c19c
MC		 12305 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12306 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12307
9d26e213 12308 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12309 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12310 if ((tp->pdev->subsystem_vendor ==
12311 PCI_VENDOR_ID_ARIMA) &&
12312 (tp->pdev->subsystem_device == 0x205a ||
12313 tp->pdev->subsystem_device == 0x2063))
12314 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12315 } else {
f49639e6 12316 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12317 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12318 }
1da177e4
LT		 12319
12320 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12321 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12322 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12323 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12324 }
b2b98d4a
MC		 12325
12326 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12327 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12328 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12329
a85feb8c
GZ		 12330 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12331 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12332 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12333
12dac075 12334 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12335 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12336 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12337
1da177e4
LT		 12338 if (cfg2 & (1 << 17))
12339 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12340
12341 /* serdes signal pre-emphasis in register 0x590 set by */
12342 /* bootcode if bit 18 is set */
12343 if (cfg2 & (1 << 18))
12344 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12345
321d32a0
MC		 12346 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12347 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12348 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12349 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12350
8ed5d97e
MC		 12351 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12352 u32 cfg3;
12353
12354 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12355 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12356 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12357 }
a9daf367 12358
14417063
MC		 12359 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12360 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
a9daf367
MC		 12361 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12362 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12363 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12364 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12365 }
05ac4cb7
MC		 12366done:
12367 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12368 device_set_wakeup_enable(&tp->pdev->dev,
12369 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12370}
12371
b2a5c19c
MC		 12372static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12373{
12374 int i;
12375 u32 val;
12376
12377 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12378 tw32(OTP_CTRL, cmd);
12379
12380 /* Wait for up to 1 ms for command to execute. */
12381 for (i = 0; i < 100; i++) {
12382 val = tr32(OTP_STATUS);
12383 if (val & OTP_STATUS_CMD_DONE)
12384 break;
12385 udelay(10);
12386 }
12387
12388 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12389}
12390
12391/* Read the gphy configuration from the OTP region of the chip. The gphy
12392 * configuration is a 32-bit value that straddles the alignment boundary.
12393 * We do two 32-bit reads and then shift and merge the results.
12394 */
12395static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12396{
12397 u32 bhalf_otp, thalf_otp;
12398
12399 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12400
12401 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12402 return 0;
12403
12404 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12405
12406 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12407 return 0;
12408
12409 thalf_otp = tr32(OTP_READ_DATA);
12410
12411 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12412
12413 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12414 return 0;
12415
12416 bhalf_otp = tr32(OTP_READ_DATA);
12417
12418 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12419}
12420
7d0c41ef
MC		 12421static int __devinit tg3_phy_probe(struct tg3 *tp)
12422{
12423 u32 hw_phy_id_1, hw_phy_id_2;
12424 u32 hw_phy_id, hw_phy_id_masked;
12425 int err;
1da177e4 12426
b02fd9e3
MC		 12427 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12428 return tg3_phy_init(tp);
12429
1da177e4 12430 /* Reading the PHY ID register can conflict with ASF
877d0310 12431 * firmware access to the PHY hardware.
1da177e4
LT		 12432 */
12433 err = 0;
0d3031d9
MC		 12434 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12435 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
79eb6904 12436 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 12437 } else {
12438 /* Now read the physical PHY_ID from the chip and verify
12439 * that it is sane. If it doesn't look good, we fall back
12440 * to either the hard-coded table based PHY_ID and failing
12441 * that the value found in the eeprom area.
12442 */
12443 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12444 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12445
12446 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12447 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12448 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12449
79eb6904 12450 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 12451 }
12452
79eb6904 12453 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 12454 tp->phy_id = hw_phy_id;
79eb6904 12455 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
1da177e4 12456 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12457 else
12458 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12459 } else {
79eb6904 12460 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 12461 /* Do nothing, phy ID already set up in
12462 * tg3_get_eeprom_hw_cfg().
12463 */
1da177e4
LT		 12464 } else {
12465 struct subsys_tbl_ent *p;
12466
12467 /* No eeprom signature? Try the hardcoded
12468 * subsys device table.
12469 */
24daf2b0 12470 p = tg3_lookup_by_subsys(tp);
1da177e4
LT		 12471 if (!p)
12472 return -ENODEV;
12473
12474 tp->phy_id = p->phy_id;
12475 if (!tp->phy_id ||
79eb6904 12476 tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 12477 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12478 }
12479 }
12480
747e8f8b 12481 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12482 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12483 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12484 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12485
12486 tg3_readphy(tp, MII_BMSR, &bmsr);
12487 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12488 (bmsr & BMSR_LSTATUS))
12489 goto skip_phy_reset;
6aa20a22 12490
1da177e4
LT		 12491 err = tg3_phy_reset(tp);
12492 if (err)
12493 return err;
12494
12495 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12496 ADVERTISE_100HALF | ADVERTISE_100FULL |
12497 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12498 tg3_ctrl = 0;
12499 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12500 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12501 MII_TG3_CTRL_ADV_1000_FULL);
12502 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12503 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12504 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12505 MII_TG3_CTRL_ENABLE_AS_MASTER);
12506 }
12507
3600d918
MC		 12508 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12509 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12510 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12511 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12512 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12513
12514 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12515 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12516
12517 tg3_writephy(tp, MII_BMCR,
12518 BMCR_ANENABLE | BMCR_ANRESTART);
12519 }
12520 tg3_phy_set_wirespeed(tp);
12521
12522 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12523 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12524 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12525 }
12526
12527skip_phy_reset:
79eb6904 12528 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 12529 err = tg3_init_5401phy_dsp(tp);
12530 if (err)
12531 return err;
1da177e4 12532
1da177e4
LT		 12533 err = tg3_init_5401phy_dsp(tp);
12534 }
12535
747e8f8b 12536 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12537 tp->link_config.advertising =
12538 (ADVERTISED_1000baseT_Half |
12539 ADVERTISED_1000baseT_Full |
12540 ADVERTISED_Autoneg |
12541 ADVERTISED_FIBRE);
12542 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12543 tp->link_config.advertising &=
12544 ~(ADVERTISED_1000baseT_Half |
12545 ADVERTISED_1000baseT_Full);
12546
12547 return err;
12548}
12549
12550static void __devinit tg3_read_partno(struct tg3 *tp)
12551{
141518c9 12552 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
4181b2c8
MC		 12553 unsigned int block_end, rosize, len;
12554 int i = 0;
1b27777a 12555 u32 magic;
1da177e4 12556
df259d8c
MC		 12557 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12558 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12559 goto out_not_found;
1da177e4 12560
1820180b 12561 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12562 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12563 u32 tmp;
1da177e4 12564
6d348f2c
MC		 12565 /* The data is in little-endian format in NVRAM.
12566 * Use the big-endian read routines to preserve
12567 * the byte order as it exists in NVRAM.
12568 */
141518c9 12569 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12570 goto out_not_found;
12571
6d348f2c 12572 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12573 }
12574 } else {
94c982bd 12575 ssize_t cnt;
4181b2c8 12576 unsigned int pos = 0;
94c982bd
MC		 12577
12578 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12579 cnt = pci_read_vpd(tp->pdev, pos,
12580 TG3_NVM_VPD_LEN - pos,
12581 &vpd_data[pos]);
12582 if (cnt == -ETIMEDOUT || -EINTR)
12583 cnt = 0;
12584 else if (cnt < 0)
f49639e6 12585 goto out_not_found;
1b27777a 12586 }
94c982bd
MC		 12587 if (pos != TG3_NVM_VPD_LEN)
12588 goto out_not_found;
1da177e4
LT		 12589 }
12590
4181b2c8
MC		 12591 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12592 PCI_VPD_LRDT_RO_DATA);
12593 if (i < 0)
12594 goto out_not_found;
1da177e4 12595
4181b2c8
MC		 12596 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12597 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12598 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 12599
4181b2c8
MC		 12600 if (block_end > TG3_NVM_VPD_LEN)
12601 goto out_not_found;
af2c6a4a 12602
4181b2c8
MC		 12603 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12604 PCI_VPD_RO_KEYWORD_PARTNO);
12605 if (i < 0)
12606 goto out_not_found;
af2c6a4a 12607
4181b2c8 12608 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 12609
4181b2c8
MC		 12610 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12611 if (len > TG3_BPN_SIZE ||
12612 (len + i) > TG3_NVM_VPD_LEN)
12613 goto out_not_found;
1da177e4 12614
4181b2c8 12615 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 12616
4181b2c8 12617 return;
1da177e4
LT		 12618
12619out_not_found:
b5d3772c
MC		 12620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12621 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12622 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12623 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12624 strcpy(tp->board_part_number, "BCM57780");
12625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12626 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12627 strcpy(tp->board_part_number, "BCM57760");
12628 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12629 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12630 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12631 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12632 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12633 strcpy(tp->board_part_number, "BCM57788");
b474eca7
MC		 12634 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12635 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12636 strcpy(tp->board_part_number, "BCM57761");
12637 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12638 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
b703df6f 12639 strcpy(tp->board_part_number, "BCM57765");
b474eca7
MC		 12640 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12641 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12642 strcpy(tp->board_part_number, "BCM57781");
12643 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12644 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12645 strcpy(tp->board_part_number, "BCM57785");
12646 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12648 strcpy(tp->board_part_number, "BCM57791");
12649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12651 strcpy(tp->board_part_number, "BCM57795");
b5d3772c
MC		 12652 else
12653 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12654}
12655
9c8a620e
MC		 12656static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12657{
12658 u32 val;
12659
e4f34110 12660 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12661 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12662 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12663 val != 0)
12664 return 0;
12665
12666 return 1;
12667}
12668
acd9c119
MC		 12669static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12670{
ff3a7cb2 12671 u32 val, offset, start, ver_offset;
acd9c119 12672 int i;
ff3a7cb2 12673 bool newver = false;
acd9c119
MC		 12674
12675 if (tg3_nvram_read(tp, 0xc, &offset) ||
12676 tg3_nvram_read(tp, 0x4, &start))
12677 return;
12678
12679 offset = tg3_nvram_logical_addr(tp, offset);
12680
ff3a7cb2 12681 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12682 return;
12683
ff3a7cb2
MC		 12684 if ((val & 0xfc000000) == 0x0c000000) {
12685 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12686 return;
12687
ff3a7cb2
MC		 12688 if (val == 0)
12689 newver = true;
12690 }
12691
12692 if (newver) {
12693 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12694 return;
12695
12696 offset = offset + ver_offset - start;
12697 for (i = 0; i < 16; i += 4) {
12698 __be32 v;
12699 if (tg3_nvram_read_be32(tp, offset + i, &v))
12700 return;
12701
12702 memcpy(tp->fw_ver + i, &v, sizeof(v));
12703 }
12704 } else {
12705 u32 major, minor;
12706
12707 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12708 return;
12709
12710 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12711 TG3_NVM_BCVER_MAJSFT;
12712 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12713 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12714 }
12715}
12716
a6f6cb1c
MC		 12717static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12718{
12719 u32 val, major, minor;
12720
12721 /* Use native endian representation */
12722 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12723 return;
12724
12725 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12726 TG3_NVM_HWSB_CFG1_MAJSFT;
12727 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12728 TG3_NVM_HWSB_CFG1_MINSFT;
12729
12730 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12731}
12732
dfe00d7d
MC		 12733static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12734{
12735 u32 offset, major, minor, build;
12736
12737 tp->fw_ver[0] = 's';
12738 tp->fw_ver[1] = 'b';
12739 tp->fw_ver[2] = '\0';
12740
12741 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12742 return;
12743
12744 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12745 case TG3_EEPROM_SB_REVISION_0:
12746 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12747 break;
12748 case TG3_EEPROM_SB_REVISION_2:
12749 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12750 break;
12751 case TG3_EEPROM_SB_REVISION_3:
12752 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12753 break;
a4153d40
MC		 12754 case TG3_EEPROM_SB_REVISION_4:
12755 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12756 break;
12757 case TG3_EEPROM_SB_REVISION_5:
12758 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12759 break;
dfe00d7d
MC		 12760 default:
12761 return;
12762 }
12763
e4f34110 12764 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12765 return;
12766
12767 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12768 TG3_EEPROM_SB_EDH_BLD_SHFT;
12769 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12770 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12771 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12772
12773 if (minor > 99 || build > 26)
12774 return;
12775
12776 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12777
12778 if (build > 0) {
12779 tp->fw_ver[8] = 'a' + build - 1;
12780 tp->fw_ver[9] = '\0';
12781 }
12782}
12783
acd9c119 12784static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12785{
12786 u32 val, offset, start;
acd9c119 12787 int i, vlen;
9c8a620e
MC		 12788
12789 for (offset = TG3_NVM_DIR_START;
12790 offset < TG3_NVM_DIR_END;
12791 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12792 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12793 return;
12794
9c8a620e
MC		 12795 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12796 break;
12797 }
12798
12799 if (offset == TG3_NVM_DIR_END)
12800 return;
12801
12802 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12803 start = 0x08000000;
e4f34110 12804 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12805 return;
12806
e4f34110 12807 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12808 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12809 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12810 return;
12811
12812 offset += val - start;
12813
acd9c119 12814 vlen = strlen(tp->fw_ver);
9c8a620e 12815
acd9c119
MC		 12816 tp->fw_ver[vlen++] = ',';
12817 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12818
12819 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12820 __be32 v;
12821 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12822 return;
12823
b9fc7dc5 12824 offset += sizeof(v);
c4e6575c 12825
acd9c119
MC		 12826 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12827 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12828 break;
c4e6575c 12829 }
9c8a620e 12830
acd9c119
MC		 12831 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12832 vlen += sizeof(v);
c4e6575c 12833 }
acd9c119
MC		 12834}
12835
7fd76445
MC		 12836static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12837{
12838 int vlen;
12839 u32 apedata;
12840
12841 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12842 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12843 return;
12844
12845 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12846 if (apedata != APE_SEG_SIG_MAGIC)
12847 return;
12848
12849 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12850 if (!(apedata & APE_FW_STATUS_READY))
12851 return;
12852
12853 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12854
12855 vlen = strlen(tp->fw_ver);
12856
12857 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12858 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12859 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12860 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12861 (apedata & APE_FW_VERSION_BLDMSK));
12862}
12863
acd9c119
MC		 12864static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12865{
12866 u32 val;
12867
df259d8c
MC		 12868 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12869 tp->fw_ver[0] = 's';
12870 tp->fw_ver[1] = 'b';
12871 tp->fw_ver[2] = '\0';
12872
12873 return;
12874 }
12875
acd9c119
MC		 12876 if (tg3_nvram_read(tp, 0, &val))
12877 return;
12878
12879 if (val == TG3_EEPROM_MAGIC)
12880 tg3_read_bc_ver(tp);
12881 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12882 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12883 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12884 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12885 else
12886 return;
12887
12888 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12889 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12890 return;
12891
12892 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12893
12894 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12895}
12896
7544b097
MC		 12897static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12898
1da177e4
LT		 12899static int __devinit tg3_get_invariants(struct tg3 *tp)
12900{
12901 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12902 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12903 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12904 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12905 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12906 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12907 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12908 { },
12909 };
12910 u32 misc_ctrl_reg;
1da177e4
LT		 12911 u32 pci_state_reg, grc_misc_cfg;
12912 u32 val;
12913 u16 pci_cmd;
5e7dfd0f 12914 int err;
1da177e4 12915
1da177e4
LT		 12916 /* Force memory write invalidate off. If we leave it on,
12917 * then on 5700_BX chips we have to enable a workaround.
12918 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12919 * to match the cacheline size. The Broadcom driver have this
12920 * workaround but turns MWI off all the times so never uses
12921 * it. This seems to suggest that the workaround is insufficient.
12922 */
12923 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12924 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12925 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12926
12927 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12928 * has the register indirect write enable bit set before
12929 * we try to access any of the MMIO registers. It is also
12930 * critical that the PCI-X hw workaround situation is decided
12931 * before that as well.
12932 */
12933 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12934 &misc_ctrl_reg);
12935
12936 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12937 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12939 u32 prod_id_asic_rev;
12940
5001e2f6
MC		 12941 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12944 pci_read_config_dword(tp->pdev,
12945 TG3PCI_GEN2_PRODID_ASICREV,
12946 &prod_id_asic_rev);
b703df6f
MC		 12947 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12951 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12953 pci_read_config_dword(tp->pdev,
12954 TG3PCI_GEN15_PRODID_ASICREV,
12955 &prod_id_asic_rev);
f6eb9b1f
MC		 12956 else
12957 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12958 &prod_id_asic_rev);
12959
321d32a0 12960 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12961 }
1da177e4 12962
ff645bec
MC		 12963 /* Wrong chip ID in 5752 A0. This code can be removed later
12964 * as A0 is not in production.
12965 */
12966 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12967 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12968
6892914f
MC		 12969 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12970 * we need to disable memory and use config. cycles
12971 * only to access all registers. The 5702/03 chips
12972 * can mistakenly decode the special cycles from the
12973 * ICH chipsets as memory write cycles, causing corruption
12974 * of register and memory space. Only certain ICH bridges
12975 * will drive special cycles with non-zero data during the
12976 * address phase which can fall within the 5703's address
12977 * range. This is not an ICH bug as the PCI spec allows
12978 * non-zero address during special cycles. However, only
12979 * these ICH bridges are known to drive non-zero addresses
12980 * during special cycles.
12981 *
12982 * Since special cycles do not cross PCI bridges, we only
12983 * enable this workaround if the 5703 is on the secondary
12984 * bus of these ICH bridges.
12985 */
12986 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12987 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12988 static struct tg3_dev_id {
12989 u32 vendor;
12990 u32 device;
12991 u32 rev;
12992 } ich_chipsets[] = {
12993 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12994 PCI_ANY_ID },
12995 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12996 PCI_ANY_ID },
12997 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12998 0xa },
12999 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13000 PCI_ANY_ID },
13001 { },
13002 };
13003 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13004 struct pci_dev *bridge = NULL;
13005
13006 while (pci_id->vendor != 0) {
13007 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13008 bridge);
13009 if (!bridge) {
13010 pci_id++;
13011 continue;
13012 }
13013 if (pci_id->rev != PCI_ANY_ID) {
44c10138 13014 if (bridge->revision > pci_id->rev)
6892914f
MC		 13015 continue;
13016 }
13017 if (bridge->subordinate &&
13018 (bridge->subordinate->number ==
13019 tp->pdev->bus->number)) {
13020
13021 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13022 pci_dev_put(bridge);
13023 break;
13024 }
13025 }
13026 }
13027
41588ba1
MC		 13028 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13029 static struct tg3_dev_id {
13030 u32 vendor;
13031 u32 device;
13032 } bridge_chipsets[] = {
13033 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13034 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13035 { },
13036 };
13037 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13038 struct pci_dev *bridge = NULL;
13039
13040 while (pci_id->vendor != 0) {
13041 bridge = pci_get_device(pci_id->vendor,
13042 pci_id->device,
13043 bridge);
13044 if (!bridge) {
13045 pci_id++;
13046 continue;
13047 }
13048 if (bridge->subordinate &&
13049 (bridge->subordinate->number <=
13050 tp->pdev->bus->number) &&
13051 (bridge->subordinate->subordinate >=
13052 tp->pdev->bus->number)) {
13053 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13054 pci_dev_put(bridge);
13055 break;
13056 }
13057 }
13058 }
13059
4a29cc2e
MC		 13060 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13061 * DMA addresses > 40-bit. This bridge may have other additional
13062 * 57xx devices behind it in some 4-port NIC designs for example.
13063 * Any tg3 device found behind the bridge will also need the 40-bit
13064 * DMA workaround.
13065 */
a4e2b347
MC		 13066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13068 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 13069 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 13070 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 13071 }
4a29cc2e
MC		 13072 else {
13073 struct pci_dev *bridge = NULL;
13074
13075 do {
13076 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13077 PCI_DEVICE_ID_SERVERWORKS_EPB,
13078 bridge);
13079 if (bridge && bridge->subordinate &&
13080 (bridge->subordinate->number <=
13081 tp->pdev->bus->number) &&
13082 (bridge->subordinate->subordinate >=
13083 tp->pdev->bus->number)) {
13084 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13085 pci_dev_put(bridge);
13086 break;
13087 }
13088 } while (bridge);
13089 }
4cf78e4f 13090
1da177e4
LT		 13091 /* Initialize misc host control in PCI block. */
13092 tp->misc_host_ctrl |= (misc_ctrl_reg &
13093 MISC_HOST_CTRL_CHIPREV);
13094 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13095 tp->misc_host_ctrl);
13096
f6eb9b1f
MC		 13097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 13100 tp->pdev_peer = tg3_find_peer(tp);
13101
321d32a0
MC		 13102 /* Intentionally exclude ASIC_REV_5906 */
13103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 13104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 13105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 13106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13111 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13112
13113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13116 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13117 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13118 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13119
1b440c56
JL		 13120 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13121 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13122 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13123
027455ad
MC		 13124 /* 5700 B0 chips do not support checksumming correctly due
13125 * to hardware bugs.
13126 */
13127 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13128 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13129 else {
13130 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13131 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13132 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13133 tp->dev->features |= NETIF_F_IPV6_CSUM;
13134 }
13135
507399f1 13136 /* Determine TSO capabilities */
b703df6f
MC		 13137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13139 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13140 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13141 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13142 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13143 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13144 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13146 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13147 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13148 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13149 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13150 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13151 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13153 tp->fw_needed = FIRMWARE_TG3TSO5;
13154 else
13155 tp->fw_needed = FIRMWARE_TG3TSO;
13156 }
13157
13158 tp->irq_max = 1;
13159
5a6f3074 13160 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13161 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13162 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13163 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13164 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13165 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13166 tp->pdev_peer == tp->pdev))
13167 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13168
321d32a0 13169 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13171 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13172 }
4f125f42 13173
b703df6f
MC		 13174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13175 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13176 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13177 tp->irq_max = TG3_IRQ_MAX_VECS;
13178 }
f6eb9b1f 13179 }
0e1406dd 13180
615774fe
MC		 13181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13182 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13183 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13184 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13185 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13186 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13187 }
f6eb9b1f 13188
b703df6f
MC		 13189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13191 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13192
f51f3562 13193 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13194 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13195 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13196 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13197
52f4490c
MC		 13198 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13199 &pci_state_reg);
13200
5e7dfd0f
MC		 13201 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13202 if (tp->pcie_cap != 0) {
13203 u16 lnkctl;
13204
1da177e4 13205 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13206
13207 pcie_set_readrq(tp->pdev, 4096);
13208
5e7dfd0f
MC		 13209 pci_read_config_word(tp->pdev,
13210 tp->pcie_cap + PCI_EXP_LNKCTL,
13211 &lnkctl);
13212 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13214 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13216 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13217 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13218 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13219 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13220 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13221 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13222 }
52f4490c 13223 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13224 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13225 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13226 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13227 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13228 if (!tp->pcix_cap) {
2445e461
MC		 13229 dev_err(&tp->pdev->dev,
13230 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 13231 return -EIO;
13232 }
13233
13234 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13235 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13236 }
1da177e4 13237
399de50b
MC		 13238 /* If we have an AMD 762 or VIA K8T800 chipset, write
13239 * reordering to the mailbox registers done by the host
13240 * controller can cause major troubles. We read back from
13241 * every mailbox register write to force the writes to be
13242 * posted to the chip in order.
13243 */
13244 if (pci_dev_present(write_reorder_chipsets) &&
13245 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13246 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13247
69fc4053
MC		 13248 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13249 &tp->pci_cacheline_sz);
13250 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13251 &tp->pci_lat_timer);
1da177e4
LT		 13252 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13253 tp->pci_lat_timer < 64) {
13254 tp->pci_lat_timer = 64;
69fc4053
MC		 13255 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13256 tp->pci_lat_timer);
1da177e4
LT		 13257 }
13258
52f4490c
MC		 13259 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13260 /* 5700 BX chips need to have their TX producer index
13261 * mailboxes written twice to workaround a bug.
13262 */
13263 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13264
52f4490c 13265 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13266 *
13267 * The workaround is to use indirect register accesses
13268 * for all chip writes not to mailbox registers.
13269 */
52f4490c 13270 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13271 u32 pm_reg;
1da177e4
LT		 13272
13273 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13274
13275 /* The chip can have it's power management PCI config
13276 * space registers clobbered due to this bug.
13277 * So explicitly force the chip into D0 here.
13278 */
9974a356
MC		 13279 pci_read_config_dword(tp->pdev,
13280 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13281 &pm_reg);
13282 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13283 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13284 pci_write_config_dword(tp->pdev,
13285 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13286 pm_reg);
13287
13288 /* Also, force SERR#/PERR# in PCI command. */
13289 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13290 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13291 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13292 }
13293 }
13294
1da177e4
LT		 13295 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13296 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13297 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13298 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13299
13300 /* Chip-specific fixup from Broadcom driver */
13301 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13302 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13303 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13304 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13305 }
13306
1ee582d8 13307 /* Default fast path register access methods */
20094930 13308 tp->read32 = tg3_read32;
1ee582d8 13309 tp->write32 = tg3_write32;
09ee929c 13310 tp->read32_mbox = tg3_read32;
20094930 13311 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13312 tp->write32_tx_mbox = tg3_write32;
13313 tp->write32_rx_mbox = tg3_write32;
13314
13315 /* Various workaround register access methods */
13316 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13317 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13318 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13319 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13320 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13321 /*
13322 * Back to back register writes can cause problems on these
13323 * chips, the workaround is to read back all reg writes
13324 * except those to mailbox regs.
13325 *
13326 * See tg3_write_indirect_reg32().
13327 */
1ee582d8 13328 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13329 }
13330
1ee582d8
MC		 13331 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13332 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13333 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13334 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13335 tp->write32_rx_mbox = tg3_write_flush_reg32;
13336 }
20094930 13337
6892914f
MC		 13338 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13339 tp->read32 = tg3_read_indirect_reg32;
13340 tp->write32 = tg3_write_indirect_reg32;
13341 tp->read32_mbox = tg3_read_indirect_mbox;
13342 tp->write32_mbox = tg3_write_indirect_mbox;
13343 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13344 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13345
13346 iounmap(tp->regs);
22abe310 13347 tp->regs = NULL;
6892914f
MC		 13348
13349 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13350 pci_cmd &= ~PCI_COMMAND_MEMORY;
13351 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13352 }
b5d3772c
MC		 13353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13354 tp->read32_mbox = tg3_read32_mbox_5906;
13355 tp->write32_mbox = tg3_write32_mbox_5906;
13356 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13357 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13358 }
6892914f 13359
bbadf503
MC		 13360 if (tp->write32 == tg3_write_indirect_reg32 ||
13361 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13362 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13364 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13365
7d0c41ef 13366 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13367 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13368 * determined before calling tg3_set_power_state() so that
13369 * we know whether or not to switch out of Vaux power.
13370 * When the flag is set, it means that GPIO1 is used for eeprom
13371 * write protect and also implies that it is a LOM where GPIOs
13372 * are not used to switch power.
6aa20a22 13373 */
7d0c41ef
MC		 13374 tg3_get_eeprom_hw_cfg(tp);
13375
0d3031d9
MC		 13376 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13377 /* Allow reads and writes to the
13378 * APE register and memory space.
13379 */
13380 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13381 PCISTATE_ALLOW_APE_SHMEM_WR;
13382 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13383 pci_state_reg);
13384 }
13385
9936bcf6 13386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13388 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13389 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13392 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13393
314fba34
MC		 13394 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13395 * GPIO1 driven high will bring 5700's external PHY out of reset.
13396 * It is also used as eeprom write protect on LOMs.
13397 */
13398 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13399 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13400 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13401 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13402 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13403 /* Unused GPIO3 must be driven as output on 5752 because there
13404 * are no pull-up resistors on unused GPIO pins.
13405 */
13406 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13407 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13408
321d32a0 13409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13412 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13413
8d519ab2
MC		 13414 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13415 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13416 /* Turn off the debug UART. */
13417 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13418 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13419 /* Keep VMain power. */
13420 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13421 GRC_LCLCTRL_GPIO_OUTPUT0;
13422 }
13423
1da177e4 13424 /* Force the chip into D0. */
bc1c7567 13425 err = tg3_set_power_state(tp, PCI_D0);
1da177e4 13426 if (err) {
2445e461 13427 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
1da177e4
LT		 13428 return err;
13429 }
13430
1da177e4
LT		 13431 /* Derive initial jumbo mode from MTU assigned in
13432 * ether_setup() via the alloc_etherdev() call
13433 */
0f893dc6 13434 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13435 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13436 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13437
13438 /* Determine WakeOnLan speed to use. */
13439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13440 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13441 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13442 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13443 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13444 } else {
13445 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13446 }
13447
7f97a4bd
MC		 13448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13449 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13450
1da177e4
LT		 13451 /* A few boards don't want Ethernet@WireSpeed phy feature */
13452 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13453 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13454 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13455 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13456 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13457 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13458 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13459
13460 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13461 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13462 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13463 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13464 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13465
321d32a0 13466 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13467 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13468 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13469 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13470 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13471 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13474 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13476 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13477 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13478 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13479 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13480 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13481 } else
c424cb24
MC		 13482 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13483 }
1da177e4 13484
b2a5c19c
MC		 13485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13486 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13487 tp->phy_otp = tg3_read_otp_phycfg(tp);
13488 if (tp->phy_otp == 0)
13489 tp->phy_otp = TG3_OTP_DEFAULT;
13490 }
13491
f51f3562 13492 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13493 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13494 else
13495 tp->mi_mode = MAC_MI_MODE_BASE;
13496
1da177e4 13497 tp->coalesce_mode = 0;
1da177e4
LT		 13498 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13499 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13500 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13501
321d32a0
MC		 13502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13504 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13505
158d7abd
MC		 13506 err = tg3_mdio_init(tp);
13507 if (err)
13508 return err;
1da177e4 13509
55dffe79
MC		 13510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13511 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13512 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13513 return -ENOTSUPP;
13514
1da177e4
LT		 13515 /* Initialize data/descriptor byte/word swapping. */
13516 val = tr32(GRC_MODE);
13517 val &= GRC_MODE_HOST_STACKUP;
13518 tw32(GRC_MODE, val | tp->grc_mode);
13519
13520 tg3_switch_clocks(tp);
13521
13522 /* Clear this out for sanity. */
13523 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13524
13525 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13526 &pci_state_reg);
13527 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13528 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13529 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13530
13531 if (chiprevid == CHIPREV_ID_5701_A0 ||
13532 chiprevid == CHIPREV_ID_5701_B0 ||
13533 chiprevid == CHIPREV_ID_5701_B2 ||
13534 chiprevid == CHIPREV_ID_5701_B5) {
13535 void __iomem *sram_base;
13536
13537 /* Write some dummy words into the SRAM status block
13538 * area, see if it reads back correctly. If the return
13539 * value is bad, force enable the PCIX workaround.
13540 */
13541 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13542
13543 writel(0x00000000, sram_base);
13544 writel(0x00000000, sram_base + 4);
13545 writel(0xffffffff, sram_base + 4);
13546 if (readl(sram_base) != 0x00000000)
13547 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13548 }
13549 }
13550
13551 udelay(50);
13552 tg3_nvram_init(tp);
13553
13554 grc_misc_cfg = tr32(GRC_MISC_CFG);
13555 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13556
1da177e4
LT		 13557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13558 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13559 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13560 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13561
fac9b83e
DM		 13562 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13563 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13564 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13565 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13566 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13567 HOSTCC_MODE_CLRTICK_TXBD);
13568
13569 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13570 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13571 tp->misc_host_ctrl);
13572 }
13573
3bda1258
MC		 13574 /* Preserve the APE MAC_MODE bits */
13575 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13576 tp->mac_mode = tr32(MAC_MODE) |
13577 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13578 else
13579 tp->mac_mode = TG3_DEF_MAC_MODE;
13580
1da177e4
LT		 13581 /* these are limited to 10/100 only */
13582 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13583 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13584 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13585 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13586 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13587 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13588 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13589 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13590 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13591 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13592 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13593 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
d1101142
MC		 13594 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13595 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
7f97a4bd 13596 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13597 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13598
13599 err = tg3_phy_probe(tp);
13600 if (err) {
2445e461 13601 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 13602 /* ... but do not return immediately ... */
b02fd9e3 13603 tg3_mdio_fini(tp);
1da177e4
LT		 13604 }
13605
13606 tg3_read_partno(tp);
c4e6575c 13607 tg3_read_fw_ver(tp);
1da177e4
LT		 13608
13609 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13610 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13611 } else {
13612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13613 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13614 else
13615 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13616 }
13617
13618 /* 5700 {AX,BX} chips have a broken status block link
13619 * change bit implementation, so we must use the
13620 * status register in those cases.
13621 */
13622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13623 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13624 else
13625 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13626
13627 /* The led_ctrl is set during tg3_phy_probe, here we might
13628 * have to force the link status polling mechanism based
13629 * upon subsystem IDs.
13630 */
13631 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13633 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13634 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13635 TG3_FLAG_USE_LINKCHG_REG);
13636 }
13637
13638 /* For all SERDES we poll the MAC status register. */
13639 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13640 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13641 else
13642 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13643
ad829268 13644 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13645 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13646 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13647 tp->rx_offset = 0;
13648
f92905de
MC		 13649 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13650
13651 /* Increment the rx prod index on the rx std ring by at most
13652 * 8 for these chips to workaround hw errata.
13653 */
13654 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13657 tp->rx_std_max_post = 8;
13658
8ed5d97e
MC		 13659 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13660 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13661 PCIE_PWR_MGMT_L1_THRESH_MSK;
13662
1da177e4
LT		 13663 return err;
13664}
13665
49b6e95f 13666#ifdef CONFIG_SPARC
1da177e4
LT		 13667static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13668{
13669 struct net_device *dev = tp->dev;
13670 struct pci_dev *pdev = tp->pdev;
49b6e95f 13671 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13672 const unsigned char *addr;
49b6e95f
DM		 13673 int len;
13674
13675 addr = of_get_property(dp, "local-mac-address", &len);
13676 if (addr && len == 6) {
13677 memcpy(dev->dev_addr, addr, 6);
13678 memcpy(dev->perm_addr, dev->dev_addr, 6);
13679 return 0;
1da177e4
LT		 13680 }
13681 return -ENODEV;
13682}
13683
13684static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13685{
13686 struct net_device *dev = tp->dev;
13687
13688 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13689 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13690 return 0;
13691}
13692#endif
13693
13694static int __devinit tg3_get_device_address(struct tg3 *tp)
13695{
13696 struct net_device *dev = tp->dev;
13697 u32 hi, lo, mac_offset;
008652b3 13698 int addr_ok = 0;
1da177e4 13699
49b6e95f 13700#ifdef CONFIG_SPARC
1da177e4
LT		 13701 if (!tg3_get_macaddr_sparc(tp))
13702 return 0;
13703#endif
13704
13705 mac_offset = 0x7c;
f49639e6 13706 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13707 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13708 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13709 mac_offset = 0xcc;
13710 if (tg3_nvram_lock(tp))
13711 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13712 else
13713 tg3_nvram_unlock(tp);
a1b950d5
MC		 13714 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13715 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13716 mac_offset = 0xcc;
13717 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13718 mac_offset = 0x10;
1da177e4
LT		 13719
13720 /* First try to get it from MAC address mailbox. */
13721 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13722 if ((hi >> 16) == 0x484b) {
13723 dev->dev_addr[0] = (hi >> 8) & 0xff;
13724 dev->dev_addr[1] = (hi >> 0) & 0xff;
13725
13726 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13727 dev->dev_addr[2] = (lo >> 24) & 0xff;
13728 dev->dev_addr[3] = (lo >> 16) & 0xff;
13729 dev->dev_addr[4] = (lo >> 8) & 0xff;
13730 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13731
008652b3
MC		 13732 /* Some old bootcode may report a 0 MAC address in SRAM */
13733 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13734 }
13735 if (!addr_ok) {
13736 /* Next, try NVRAM. */
df259d8c
MC		 13737 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13738 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13739 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13740 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13741 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13742 }
13743 /* Finally just fetch it out of the MAC control regs. */
13744 else {
13745 hi = tr32(MAC_ADDR_0_HIGH);
13746 lo = tr32(MAC_ADDR_0_LOW);
13747
13748 dev->dev_addr[5] = lo & 0xff;
13749 dev->dev_addr[4] = (lo >> 8) & 0xff;
13750 dev->dev_addr[3] = (lo >> 16) & 0xff;
13751 dev->dev_addr[2] = (lo >> 24) & 0xff;
13752 dev->dev_addr[1] = hi & 0xff;
13753 dev->dev_addr[0] = (hi >> 8) & 0xff;
13754 }
1da177e4
LT		 13755 }
13756
13757 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13758#ifdef CONFIG_SPARC
1da177e4
LT		 13759 if (!tg3_get_default_macaddr_sparc(tp))
13760 return 0;
13761#endif
13762 return -EINVAL;
13763 }
2ff43697 13764 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13765 return 0;
13766}
13767
59e6b434
DM		 13768#define BOUNDARY_SINGLE_CACHELINE 1
13769#define BOUNDARY_MULTI_CACHELINE 2
13770
13771static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13772{
13773 int cacheline_size;
13774 u8 byte;
13775 int goal;
13776
13777 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13778 if (byte == 0)
13779 cacheline_size = 1024;
13780 else
13781 cacheline_size = (int) byte * 4;
13782
13783 /* On 5703 and later chips, the boundary bits have no
13784 * effect.
13785 */
13786 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13787 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13788 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13789 goto out;
13790
13791#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13792 goal = BOUNDARY_MULTI_CACHELINE;
13793#else
13794#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13795 goal = BOUNDARY_SINGLE_CACHELINE;
13796#else
13797 goal = 0;
13798#endif
13799#endif
13800
b703df6f
MC		 13801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13803 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13804 goto out;
13805 }
13806
59e6b434
DM		 13807 if (!goal)
13808 goto out;
13809
13810 /* PCI controllers on most RISC systems tend to disconnect
13811 * when a device tries to burst across a cache-line boundary.
13812 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13813 *
13814 * Unfortunately, for PCI-E there are only limited
13815 * write-side controls for this, and thus for reads
13816 * we will still get the disconnects. We'll also waste
13817 * these PCI cycles for both read and write for chips
13818 * other than 5700 and 5701 which do not implement the
13819 * boundary bits.
13820 */
13821 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13822 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13823 switch (cacheline_size) {
13824 case 16:
13825 case 32:
13826 case 64:
13827 case 128:
13828 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13829 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13830 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13831 } else {
13832 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13833 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13834 }
13835 break;
13836
13837 case 256:
13838 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13839 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13840 break;
13841
13842 default:
13843 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13844 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13845 break;
855e1111 13846 }
59e6b434
DM		 13847 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13848 switch (cacheline_size) {
13849 case 16:
13850 case 32:
13851 case 64:
13852 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13853 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13854 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13855 break;
13856 }
13857 /* fallthrough */
13858 case 128:
13859 default:
13860 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13861 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13862 break;
855e1111 13863 }
59e6b434
DM		 13864 } else {
13865 switch (cacheline_size) {
13866 case 16:
13867 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13868 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13869 DMA_RWCTRL_WRITE_BNDRY_16);
13870 break;
13871 }
13872 /* fallthrough */
13873 case 32:
13874 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13875 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13876 DMA_RWCTRL_WRITE_BNDRY_32);
13877 break;
13878 }
13879 /* fallthrough */
13880 case 64:
13881 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13882 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13883 DMA_RWCTRL_WRITE_BNDRY_64);
13884 break;
13885 }
13886 /* fallthrough */
13887 case 128:
13888 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13889 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13890 DMA_RWCTRL_WRITE_BNDRY_128);
13891 break;
13892 }
13893 /* fallthrough */
13894 case 256:
13895 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13896 DMA_RWCTRL_WRITE_BNDRY_256);
13897 break;
13898 case 512:
13899 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13900 DMA_RWCTRL_WRITE_BNDRY_512);
13901 break;
13902 case 1024:
13903 default:
13904 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13905 DMA_RWCTRL_WRITE_BNDRY_1024);
13906 break;
855e1111 13907 }
59e6b434
DM		 13908 }
13909
13910out:
13911 return val;
13912}
13913
1da177e4
LT		 13914static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13915{
13916 struct tg3_internal_buffer_desc test_desc;
13917 u32 sram_dma_descs;
13918 int i, ret;
13919
13920 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13921
13922 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13923 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13924 tw32(RDMAC_STATUS, 0);
13925 tw32(WDMAC_STATUS, 0);
13926
13927 tw32(BUFMGR_MODE, 0);
13928 tw32(FTQ_RESET, 0);
13929
13930 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13931 test_desc.addr_lo = buf_dma & 0xffffffff;
13932 test_desc.nic_mbuf = 0x00002100;
13933 test_desc.len = size;
13934
13935 /*
13936 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13937 * the *second* time the tg3 driver was getting loaded after an
13938 * initial scan.
13939 *
13940 * Broadcom tells me:
13941 * ...the DMA engine is connected to the GRC block and a DMA
13942 * reset may affect the GRC block in some unpredictable way...
13943 * The behavior of resets to individual blocks has not been tested.
13944 *
13945 * Broadcom noted the GRC reset will also reset all sub-components.
13946 */
13947 if (to_device) {
13948 test_desc.cqid_sqid = (13 << 8) | 2;
13949
13950 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13951 udelay(40);
13952 } else {
13953 test_desc.cqid_sqid = (16 << 8) | 7;
13954
13955 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13956 udelay(40);
13957 }
13958 test_desc.flags = 0x00000005;
13959
13960 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13961 u32 val;
13962
13963 val = *(((u32 *)&test_desc) + i);
13964 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13965 sram_dma_descs + (i * sizeof(u32)));
13966 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13967 }
13968 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13969
13970 if (to_device) {
13971 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13972 } else {
13973 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13974 }
13975
13976 ret = -ENODEV;
13977 for (i = 0; i < 40; i++) {
13978 u32 val;
13979
13980 if (to_device)
13981 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13982 else
13983 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13984 if ((val & 0xffff) == sram_dma_descs) {
13985 ret = 0;
13986 break;
13987 }
13988
13989 udelay(100);
13990 }
13991
13992 return ret;
13993}
13994
ded7340d 13995#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13996
13997static int __devinit tg3_test_dma(struct tg3 *tp)
13998{
13999 dma_addr_t buf_dma;
59e6b434 14000 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 14001 int ret = 0;
1da177e4
LT		 14002
14003 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14004 if (!buf) {
14005 ret = -ENOMEM;
14006 goto out_nofree;
14007 }
14008
14009 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14010 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14011
59e6b434 14012 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 14013
b703df6f
MC		 14014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 14016 goto out;
14017
1da177e4
LT		 14018 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14019 /* DMA read watermark not used on PCIE */
14020 tp->dma_rwctrl |= 0x00180000;
14021 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 14022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 14024 tp->dma_rwctrl |= 0x003f0000;
14025 else
14026 tp->dma_rwctrl |= 0x003f000f;
14027 } else {
14028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14030 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 14031 u32 read_water = 0x7;
1da177e4 14032
4a29cc2e
MC		 14033 /* If the 5704 is behind the EPB bridge, we can
14034 * do the less restrictive ONE_DMA workaround for
14035 * better performance.
14036 */
14037 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14039 tp->dma_rwctrl |= 0x8000;
14040 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 14041 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14042
49afdeb6
MC		 14043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14044 read_water = 4;
59e6b434 14045 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 14046 tp->dma_rwctrl |=
14047 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14048 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14049 (1 << 23);
4cf78e4f
MC		 14050 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14051 /* 5780 always in PCIX mode */
14052 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 14053 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14054 /* 5714 always in PCIX mode */
14055 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 14056 } else {
14057 tp->dma_rwctrl |= 0x001b000f;
14058 }
14059 }
14060
14061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14063 tp->dma_rwctrl &= 0xfffffff0;
14064
14065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14067 /* Remove this if it causes problems for some boards. */
14068 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14069
14070 /* On 5700/5701 chips, we need to set this bit.
14071 * Otherwise the chip will issue cacheline transactions
14072 * to streamable DMA memory with not all the byte
14073 * enables turned on. This is an error on several
14074 * RISC PCI controllers, in particular sparc64.
14075 *
14076 * On 5703/5704 chips, this bit has been reassigned
14077 * a different meaning. In particular, it is used
14078 * on those chips to enable a PCI-X workaround.
14079 */
14080 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14081 }
14082
14083 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14084
14085#if 0
14086 /* Unneeded, already done by tg3_get_invariants. */
14087 tg3_switch_clocks(tp);
14088#endif
14089
1da177e4
LT		 14090 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14091 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14092 goto out;
14093
59e6b434
DM		 14094 /* It is best to perform DMA test with maximum write burst size
14095 * to expose the 5700/5701 write DMA bug.
14096 */
14097 saved_dma_rwctrl = tp->dma_rwctrl;
14098 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14099 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14100
1da177e4
LT		 14101 while (1) {
14102 u32 *p = buf, i;
14103
14104 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14105 p[i] = i;
14106
14107 /* Send the buffer to the chip. */
14108 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14109 if (ret) {
2445e461
MC		 14110 dev_err(&tp->pdev->dev,
14111 "%s: Buffer write failed. err = %d\n",
14112 __func__, ret);
1da177e4
LT		 14113 break;
14114 }
14115
14116#if 0
14117 /* validate data reached card RAM correctly. */
14118 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14119 u32 val;
14120 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14121 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 14122 dev_err(&tp->pdev->dev,
14123 "%s: Buffer corrupted on device! "
14124 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 14125 /* ret = -ENODEV here? */
14126 }
14127 p[i] = 0;
14128 }
14129#endif
14130 /* Now read it back. */
14131 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14132 if (ret) {
2445e461
MC		 14133 dev_err(&tp->pdev->dev,
14134 "%s: Buffer read failed. err = %d\n",
14135 __func__, ret);
1da177e4
LT		 14136 break;
14137 }
14138
14139 /* Verify it. */
14140 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14141 if (p[i] == i)
14142 continue;
14143
59e6b434
DM		 14144 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14145 DMA_RWCTRL_WRITE_BNDRY_16) {
14146 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14147 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14148 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14149 break;
14150 } else {
2445e461
MC		 14151 dev_err(&tp->pdev->dev,
14152 "%s: Buffer corrupted on read back! "
14153 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 14154 ret = -ENODEV;
14155 goto out;
14156 }
14157 }
14158
14159 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14160 /* Success. */
14161 ret = 0;
14162 break;
14163 }
14164 }
59e6b434
DM		 14165 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14166 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14167 static struct pci_device_id dma_wait_state_chipsets[] = {
14168 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14169 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14170 { },
14171 };
14172
59e6b434 14173 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14174 * now look for chipsets that are known to expose the
14175 * DMA bug without failing the test.
59e6b434 14176 */
6d1cfbab
MC		 14177 if (pci_dev_present(dma_wait_state_chipsets)) {
14178 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14179 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14180 }
14181 else
14182 /* Safe to use the calculated DMA boundary. */
14183 tp->dma_rwctrl = saved_dma_rwctrl;
14184
59e6b434
DM		 14185 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14186 }
1da177e4
LT		 14187
14188out:
14189 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14190out_nofree:
14191 return ret;
14192}
14193
14194static void __devinit tg3_init_link_config(struct tg3 *tp)
14195{
14196 tp->link_config.advertising =
14197 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14198 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14199 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14200 ADVERTISED_Autoneg | ADVERTISED_MII);
14201 tp->link_config.speed = SPEED_INVALID;
14202 tp->link_config.duplex = DUPLEX_INVALID;
14203 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14204 tp->link_config.active_speed = SPEED_INVALID;
14205 tp->link_config.active_duplex = DUPLEX_INVALID;
14206 tp->link_config.phy_is_low_power = 0;
14207 tp->link_config.orig_speed = SPEED_INVALID;
14208 tp->link_config.orig_duplex = DUPLEX_INVALID;
14209 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14210}
14211
14212static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14213{
666bc831
MC		 14214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14215 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14216 tp->bufmgr_config.mbuf_read_dma_low_water =
14217 DEFAULT_MB_RDMA_LOW_WATER_5705;
14218 tp->bufmgr_config.mbuf_mac_rx_low_water =
14219 DEFAULT_MB_MACRX_LOW_WATER_57765;
14220 tp->bufmgr_config.mbuf_high_water =
14221 DEFAULT_MB_HIGH_WATER_57765;
14222
14223 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14224 DEFAULT_MB_RDMA_LOW_WATER_5705;
14225 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14226 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14227 tp->bufmgr_config.mbuf_high_water_jumbo =
14228 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14229 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14230 tp->bufmgr_config.mbuf_read_dma_low_water =
14231 DEFAULT_MB_RDMA_LOW_WATER_5705;
14232 tp->bufmgr_config.mbuf_mac_rx_low_water =
14233 DEFAULT_MB_MACRX_LOW_WATER_5705;
14234 tp->bufmgr_config.mbuf_high_water =
14235 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14236 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14237 tp->bufmgr_config.mbuf_mac_rx_low_water =
14238 DEFAULT_MB_MACRX_LOW_WATER_5906;
14239 tp->bufmgr_config.mbuf_high_water =
14240 DEFAULT_MB_HIGH_WATER_5906;
14241 }
fdfec172
MC		 14242
14243 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14244 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14245 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14246 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14247 tp->bufmgr_config.mbuf_high_water_jumbo =
14248 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14249 } else {
14250 tp->bufmgr_config.mbuf_read_dma_low_water =
14251 DEFAULT_MB_RDMA_LOW_WATER;
14252 tp->bufmgr_config.mbuf_mac_rx_low_water =
14253 DEFAULT_MB_MACRX_LOW_WATER;
14254 tp->bufmgr_config.mbuf_high_water =
14255 DEFAULT_MB_HIGH_WATER;
14256
14257 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14258 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14259 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14260 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14261 tp->bufmgr_config.mbuf_high_water_jumbo =
14262 DEFAULT_MB_HIGH_WATER_JUMBO;
14263 }
1da177e4
LT		 14264
14265 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14266 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14267}
14268
14269static char * __devinit tg3_phy_string(struct tg3 *tp)
14270{
79eb6904
MC		 14271 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14272 case TG3_PHY_ID_BCM5400: return "5400";
14273 case TG3_PHY_ID_BCM5401: return "5401";
14274 case TG3_PHY_ID_BCM5411: return "5411";
14275 case TG3_PHY_ID_BCM5701: return "5701";
14276 case TG3_PHY_ID_BCM5703: return "5703";
14277 case TG3_PHY_ID_BCM5704: return "5704";
14278 case TG3_PHY_ID_BCM5705: return "5705";
14279 case TG3_PHY_ID_BCM5750: return "5750";
14280 case TG3_PHY_ID_BCM5752: return "5752";
14281 case TG3_PHY_ID_BCM5714: return "5714";
14282 case TG3_PHY_ID_BCM5780: return "5780";
14283 case TG3_PHY_ID_BCM5755: return "5755";
14284 case TG3_PHY_ID_BCM5787: return "5787";
14285 case TG3_PHY_ID_BCM5784: return "5784";
14286 case TG3_PHY_ID_BCM5756: return "5722/5756";
14287 case TG3_PHY_ID_BCM5906: return "5906";
14288 case TG3_PHY_ID_BCM5761: return "5761";
14289 case TG3_PHY_ID_BCM5718C: return "5718C";
14290 case TG3_PHY_ID_BCM5718S: return "5718S";
14291 case TG3_PHY_ID_BCM57765: return "57765";
14292 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 14293 case 0: return "serdes";
14294 default: return "unknown";
855e1111 14295 }
1da177e4
LT		 14296}
14297
f9804ddb
MC		 14298static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14299{
14300 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14301 strcpy(str, "PCI Express");
14302 return str;
14303 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14304 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14305
14306 strcpy(str, "PCIX:");
14307
14308 if ((clock_ctrl == 7) ||
14309 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14310 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14311 strcat(str, "133MHz");
14312 else if (clock_ctrl == 0)
14313 strcat(str, "33MHz");
14314 else if (clock_ctrl == 2)
14315 strcat(str, "50MHz");
14316 else if (clock_ctrl == 4)
14317 strcat(str, "66MHz");
14318 else if (clock_ctrl == 6)
14319 strcat(str, "100MHz");
f9804ddb
MC		 14320 } else {
14321 strcpy(str, "PCI:");
14322 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14323 strcat(str, "66MHz");
14324 else
14325 strcat(str, "33MHz");
14326 }
14327 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14328 strcat(str, ":32-bit");
14329 else
14330 strcat(str, ":64-bit");
14331 return str;
14332}
14333
8c2dc7e1 14334static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14335{
14336 struct pci_dev *peer;
14337 unsigned int func, devnr = tp->pdev->devfn & ~7;
14338
14339 for (func = 0; func < 8; func++) {
14340 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14341 if (peer && peer != tp->pdev)
14342 break;
14343 pci_dev_put(peer);
14344 }
16fe9d74
MC		 14345 /* 5704 can be configured in single-port mode, set peer to
14346 * tp->pdev in that case.
14347 */
14348 if (!peer) {
14349 peer = tp->pdev;
14350 return peer;
14351 }
1da177e4
LT		 14352
14353 /*
14354 * We don't need to keep the refcount elevated; there's no way
14355 * to remove one half of this device without removing the other
14356 */
14357 pci_dev_put(peer);
14358
14359 return peer;
14360}
14361
15f9850d
DM		 14362static void __devinit tg3_init_coal(struct tg3 *tp)
14363{
14364 struct ethtool_coalesce *ec = &tp->coal;
14365
14366 memset(ec, 0, sizeof(*ec));
14367 ec->cmd = ETHTOOL_GCOALESCE;
14368 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14369 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14370 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14371 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14372 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14373 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14374 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14375 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14376 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14377
14378 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14379 HOSTCC_MODE_CLRTICK_TXBD)) {
14380 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14381 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14382 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14383 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14384 }
d244c892
MC		 14385
14386 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14387 ec->rx_coalesce_usecs_irq = 0;
14388 ec->tx_coalesce_usecs_irq = 0;
14389 ec->stats_block_coalesce_usecs = 0;
14390 }
15f9850d
DM		 14391}
14392
7c7d64b8
SH		 14393static const struct net_device_ops tg3_netdev_ops = {
14394 .ndo_open = tg3_open,
14395 .ndo_stop = tg3_close,
00829823
SH		 14396 .ndo_start_xmit = tg3_start_xmit,
14397 .ndo_get_stats = tg3_get_stats,
14398 .ndo_validate_addr = eth_validate_addr,
14399 .ndo_set_multicast_list = tg3_set_rx_mode,
14400 .ndo_set_mac_address = tg3_set_mac_addr,
14401 .ndo_do_ioctl = tg3_ioctl,
14402 .ndo_tx_timeout = tg3_tx_timeout,
14403 .ndo_change_mtu = tg3_change_mtu,
14404#if TG3_VLAN_TAG_USED
14405 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14406#endif
14407#ifdef CONFIG_NET_POLL_CONTROLLER
14408 .ndo_poll_controller = tg3_poll_controller,
14409#endif
14410};
14411
14412static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14413 .ndo_open = tg3_open,
14414 .ndo_stop = tg3_close,
14415 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14416 .ndo_get_stats = tg3_get_stats,
14417 .ndo_validate_addr = eth_validate_addr,
14418 .ndo_set_multicast_list = tg3_set_rx_mode,
14419 .ndo_set_mac_address = tg3_set_mac_addr,
14420 .ndo_do_ioctl = tg3_ioctl,
14421 .ndo_tx_timeout = tg3_tx_timeout,
14422 .ndo_change_mtu = tg3_change_mtu,
14423#if TG3_VLAN_TAG_USED
14424 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14425#endif
14426#ifdef CONFIG_NET_POLL_CONTROLLER
14427 .ndo_poll_controller = tg3_poll_controller,
14428#endif
14429};
14430
1da177e4
LT		 14431static int __devinit tg3_init_one(struct pci_dev *pdev,
14432 const struct pci_device_id *ent)
14433{
1da177e4
LT		 14434 struct net_device *dev;
14435 struct tg3 *tp;
646c9edd
MC		 14436 int i, err, pm_cap;
14437 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14438 char str[40];
72f2afb8 14439 u64 dma_mask, persist_dma_mask;
1da177e4 14440
05dbe005 14441 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 14442
14443 err = pci_enable_device(pdev);
14444 if (err) {
2445e461 14445 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 14446 return err;
14447 }
14448
1da177e4
LT		 14449 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14450 if (err) {
2445e461 14451 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 14452 goto err_out_disable_pdev;
14453 }
14454
14455 pci_set_master(pdev);
14456
14457 /* Find power-management capability. */
14458 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14459 if (pm_cap == 0) {
2445e461
MC		 14460 dev_err(&pdev->dev,
14461 "Cannot find Power Management capability, aborting\n");
1da177e4
LT		 14462 err = -EIO;
14463 goto err_out_free_res;
14464 }
14465
fe5f5787 14466 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 14467 if (!dev) {
2445e461 14468 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4
LT		 14469 err = -ENOMEM;
14470 goto err_out_free_res;
14471 }
14472
1da177e4
LT		 14473 SET_NETDEV_DEV(dev, &pdev->dev);
14474
1da177e4
LT		 14475#if TG3_VLAN_TAG_USED
14476 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14477#endif
14478
14479 tp = netdev_priv(dev);
14480 tp->pdev = pdev;
14481 tp->dev = dev;
14482 tp->pm_cap = pm_cap;
1da177e4
LT		 14483 tp->rx_mode = TG3_DEF_RX_MODE;
14484 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14485
1da177e4
LT		 14486 if (tg3_debug > 0)
14487 tp->msg_enable = tg3_debug;
14488 else
14489 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14490
14491 /* The word/byte swap controls here control register access byte
14492 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14493 * setting below.
14494 */
14495 tp->misc_host_ctrl =
14496 MISC_HOST_CTRL_MASK_PCI_INT |
14497 MISC_HOST_CTRL_WORD_SWAP |
14498 MISC_HOST_CTRL_INDIR_ACCESS |
14499 MISC_HOST_CTRL_PCISTATE_RW;
14500
14501 /* The NONFRM (non-frame) byte/word swap controls take effect
14502 * on descriptor entries, anything which isn't packet data.
14503 *
14504 * The StrongARM chips on the board (one for tx, one for rx)
14505 * are running in big-endian mode.
14506 */
14507 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14508 GRC_MODE_WSWAP_NONFRM_DATA);
14509#ifdef __BIG_ENDIAN
14510 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14511#endif
14512 spin_lock_init(&tp->lock);
1da177e4 14513 spin_lock_init(&tp->indirect_lock);
c4028958 14514 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14515
d5fe488a 14516 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14517 if (!tp->regs) {
ab96b241 14518 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 14519 err = -ENOMEM;
14520 goto err_out_free_dev;
14521 }
14522
14523 tg3_init_link_config(tp);
14524
1da177e4
LT		 14525 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14526 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14527
1da177e4 14528 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14529 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14530 dev->irq = pdev->irq;
1da177e4
LT		 14531
14532 err = tg3_get_invariants(tp);
14533 if (err) {
ab96b241
MC		 14534 dev_err(&pdev->dev,
14535 "Problem fetching invariants of chip, aborting\n");
1da177e4
LT		 14536 goto err_out_iounmap;
14537 }
14538
615774fe
MC		 14539 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14540 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14541 dev->netdev_ops = &tg3_netdev_ops;
14542 else
14543 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14544
14545
4a29cc2e
MC		 14546 /* The EPB bridge inside 5714, 5715, and 5780 and any
14547 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14548 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14549 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14550 * do DMA address check in tg3_start_xmit().
14551 */
4a29cc2e 14552 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14553 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14554 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14555 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14556#ifdef CONFIG_HIGHMEM
6a35528a 14557 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14558#endif
4a29cc2e 14559 } else
6a35528a 14560 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14561
14562 /* Configure DMA attributes. */
284901a9 14563 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14564 err = pci_set_dma_mask(pdev, dma_mask);
14565 if (!err) {
14566 dev->features |= NETIF_F_HIGHDMA;
14567 err = pci_set_consistent_dma_mask(pdev,
14568 persist_dma_mask);
14569 if (err < 0) {
ab96b241
MC		 14570 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14571 "DMA for consistent allocations\n");
72f2afb8
MC		 14572 goto err_out_iounmap;
14573 }
14574 }
14575 }
284901a9
YH		 14576 if (err || dma_mask == DMA_BIT_MASK(32)) {
14577 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 14578 if (err) {
ab96b241
MC		 14579 dev_err(&pdev->dev,
14580 "No usable DMA configuration, aborting\n");
72f2afb8
MC		 14581 goto err_out_iounmap;
14582 }
14583 }
14584
fdfec172 14585 tg3_init_bufmgr_config(tp);
1da177e4 14586
507399f1
MC		 14587 /* Selectively allow TSO based on operating conditions */
14588 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14589 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14590 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14591 else {
14592 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14593 tp->fw_needed = NULL;
1da177e4 14594 }
507399f1
MC		 14595
14596 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14597 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14598
4e3a7aaa
MC		 14599 /* TSO is on by default on chips that support hardware TSO.
14600 * Firmware TSO on older chips gives lower performance, so it
14601 * is off by default, but can be enabled using ethtool.
14602 */
e849cdc3
MC		 14603 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14604 (dev->features & NETIF_F_IP_CSUM))
14605 dev->features |= NETIF_F_TSO;
14606
14607 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14608 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14609 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14610 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14611 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14613 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14614 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14615 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14617 dev->features |= NETIF_F_TSO_ECN;
b0026624 14618 }
1da177e4 14619
1da177e4
LT		 14620 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14621 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14622 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14623 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14624 tp->rx_pending = 63;
14625 }
14626
1da177e4
LT		 14627 err = tg3_get_device_address(tp);
14628 if (err) {
ab96b241
MC		 14629 dev_err(&pdev->dev,
14630 "Could not obtain valid ethernet address, aborting\n");
026a6c21 14631 goto err_out_iounmap;
1da177e4
LT		 14632 }
14633
c88864df 14634 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14635 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14636 if (!tp->aperegs) {
ab96b241
MC		 14637 dev_err(&pdev->dev,
14638 "Cannot map APE registers, aborting\n");
c88864df 14639 err = -ENOMEM;
026a6c21 14640 goto err_out_iounmap;
c88864df
MC		 14641 }
14642
14643 tg3_ape_lock_init(tp);
7fd76445
MC		 14644
14645 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14646 tg3_read_dash_ver(tp);
c88864df
MC		 14647 }
14648
1da177e4
LT		 14649 /*
14650 * Reset chip in case UNDI or EFI driver did not shutdown
14651 * DMA self test will enable WDMAC and we'll see (spurious)
14652 * pending DMA on the PCI bus at that point.
14653 */
14654 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14655 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14656 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14657 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14658 }
14659
14660 err = tg3_test_dma(tp);
14661 if (err) {
ab96b241 14662 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 14663 goto err_out_apeunmap;
1da177e4
LT		 14664 }
14665
1da177e4
LT		 14666 /* flow control autonegotiation is default behavior */
14667 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14668 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14669
78f90dcf
MC		 14670 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14671 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14672 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14673 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14674 struct tg3_napi *tnapi = &tp->napi[i];
14675
14676 tnapi->tp = tp;
14677 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14678
14679 tnapi->int_mbox = intmbx;
14680 if (i < 4)
14681 intmbx += 0x8;
14682 else
14683 intmbx += 0x4;
14684
14685 tnapi->consmbox = rcvmbx;
14686 tnapi->prodmbox = sndmbx;
14687
14688 if (i) {
14689 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14690 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14691 } else {
14692 tnapi->coal_now = HOSTCC_MODE_NOW;
14693 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14694 }
14695
14696 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14697 break;
14698
14699 /*
14700 * If we support MSIX, we'll be using RSS. If we're using
14701 * RSS, the first vector only handles link interrupts and the
14702 * remaining vectors handle rx and tx interrupts. Reuse the
14703 * mailbox values for the next iteration. The values we setup
14704 * above are still useful for the single vectored mode.
14705 */
14706 if (!i)
14707 continue;
14708
14709 rcvmbx += 0x8;
14710
14711 if (sndmbx & 0x4)
14712 sndmbx -= 0x4;
14713 else
14714 sndmbx += 0xc;
14715 }
14716
15f9850d
DM		 14717 tg3_init_coal(tp);
14718
c49a1561
MC		 14719 pci_set_drvdata(pdev, dev);
14720
1da177e4
LT		 14721 err = register_netdev(dev);
14722 if (err) {
ab96b241 14723 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 14724 goto err_out_apeunmap;
1da177e4
LT		 14725 }
14726
05dbe005
JP		 14727 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14728 tp->board_part_number,
14729 tp->pci_chip_rev_id,
14730 tg3_bus_string(tp, str),
14731 dev->dev_addr);
1da177e4 14732
3f0e3ad7
MC		 14733 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14734 struct phy_device *phydev;
14735 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
05dbe005
JP		 14736 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14737 phydev->drv->name, dev_name(&phydev->dev));
3f0e3ad7 14738 } else
05dbe005
JP		 14739 netdev_info(dev, "attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14740 tg3_phy_string(tp),
14741 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14742 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14743 "10/100/1000Base-T")),
14744 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14745
14746 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14747 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14748 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14749 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14750 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14751 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14752 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14753 tp->dma_rwctrl,
14754 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14755 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4
LT		 14756
14757 return 0;
14758
0d3031d9
MC		 14759err_out_apeunmap:
14760 if (tp->aperegs) {
14761 iounmap(tp->aperegs);
14762 tp->aperegs = NULL;
14763 }
14764
1da177e4 14765err_out_iounmap:
6892914f
MC		 14766 if (tp->regs) {
14767 iounmap(tp->regs);
22abe310 14768 tp->regs = NULL;
6892914f 14769 }
1da177e4
LT		 14770
14771err_out_free_dev:
14772 free_netdev(dev);
14773
14774err_out_free_res:
14775 pci_release_regions(pdev);
14776
14777err_out_disable_pdev:
14778 pci_disable_device(pdev);
14779 pci_set_drvdata(pdev, NULL);
14780 return err;
14781}
14782
14783static void __devexit tg3_remove_one(struct pci_dev *pdev)
14784{
14785 struct net_device *dev = pci_get_drvdata(pdev);
14786
14787 if (dev) {
14788 struct tg3 *tp = netdev_priv(dev);
14789
077f849d
JSR		 14790 if (tp->fw)
14791 release_firmware(tp->fw);
14792
7faa006f 14793 flush_scheduled_work();
158d7abd 14794
b02fd9e3
MC		 14795 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14796 tg3_phy_fini(tp);
158d7abd 14797 tg3_mdio_fini(tp);
b02fd9e3 14798 }
158d7abd 14799
1da177e4 14800 unregister_netdev(dev);
0d3031d9
MC		 14801 if (tp->aperegs) {
14802 iounmap(tp->aperegs);
14803 tp->aperegs = NULL;
14804 }
6892914f
MC		 14805 if (tp->regs) {
14806 iounmap(tp->regs);
22abe310 14807 tp->regs = NULL;
6892914f 14808 }
1da177e4
LT		 14809 free_netdev(dev);
14810 pci_release_regions(pdev);
14811 pci_disable_device(pdev);
14812 pci_set_drvdata(pdev, NULL);
14813 }
14814}
14815
14816static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14817{
14818 struct net_device *dev = pci_get_drvdata(pdev);
14819 struct tg3 *tp = netdev_priv(dev);
12dac075 14820 pci_power_t target_state;
1da177e4
LT		 14821 int err;
14822
3e0c95fd
MC		 14823 /* PCI register 4 needs to be saved whether netif_running() or not.
14824 * MSI address and data need to be saved if using MSI and
14825 * netif_running().
14826 */
14827 pci_save_state(pdev);
14828
1da177e4
LT		 14829 if (!netif_running(dev))
14830 return 0;
14831
7faa006f 14832 flush_scheduled_work();
b02fd9e3 14833 tg3_phy_stop(tp);
1da177e4
LT		 14834 tg3_netif_stop(tp);
14835
14836 del_timer_sync(&tp->timer);
14837
f47c11ee 14838 tg3_full_lock(tp, 1);
1da177e4 14839 tg3_disable_ints(tp);
f47c11ee 14840 tg3_full_unlock(tp);
1da177e4
LT		 14841
14842 netif_device_detach(dev);
14843
f47c11ee 14844 tg3_full_lock(tp, 0);
944d980e 14845 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14846 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14847 tg3_full_unlock(tp);
1da177e4 14848
12dac075
RW		 14849 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14850
14851 err = tg3_set_power_state(tp, target_state);
1da177e4 14852 if (err) {
b02fd9e3
MC		 14853 int err2;
14854
f47c11ee 14855 tg3_full_lock(tp, 0);
1da177e4 14856
6a9eba15 14857 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14858 err2 = tg3_restart_hw(tp, 1);
14859 if (err2)
b9ec6c1b 14860 goto out;
1da177e4
LT		 14861
14862 tp->timer.expires = jiffies + tp->timer_offset;
14863 add_timer(&tp->timer);
14864
14865 netif_device_attach(dev);
14866 tg3_netif_start(tp);
14867
b9ec6c1b 14868out:
f47c11ee 14869 tg3_full_unlock(tp);
b02fd9e3
MC		 14870
14871 if (!err2)
14872 tg3_phy_start(tp);
1da177e4
LT		 14873 }
14874
14875 return err;
14876}
14877
14878static int tg3_resume(struct pci_dev *pdev)
14879{
14880 struct net_device *dev = pci_get_drvdata(pdev);
14881 struct tg3 *tp = netdev_priv(dev);
14882 int err;
14883
3e0c95fd
MC		 14884 pci_restore_state(tp->pdev);
14885
1da177e4
LT		 14886 if (!netif_running(dev))
14887 return 0;
14888
bc1c7567 14889 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14890 if (err)
14891 return err;
14892
14893 netif_device_attach(dev);
14894
f47c11ee 14895 tg3_full_lock(tp, 0);
1da177e4 14896
6a9eba15 14897 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14898 err = tg3_restart_hw(tp, 1);
14899 if (err)
14900 goto out;
1da177e4
LT		 14901
14902 tp->timer.expires = jiffies + tp->timer_offset;
14903 add_timer(&tp->timer);
14904
1da177e4
LT		 14905 tg3_netif_start(tp);
14906
b9ec6c1b 14907out:
f47c11ee 14908 tg3_full_unlock(tp);
1da177e4 14909
b02fd9e3
MC		 14910 if (!err)
14911 tg3_phy_start(tp);
14912
b9ec6c1b 14913 return err;
1da177e4
LT		 14914}
14915
14916static struct pci_driver tg3_driver = {
14917 .name = DRV_MODULE_NAME,
14918 .id_table = tg3_pci_tbl,
14919 .probe = tg3_init_one,
14920 .remove = __devexit_p(tg3_remove_one),
14921 .suspend = tg3_suspend,
14922 .resume = tg3_resume
14923};
14924
14925static int __init tg3_init(void)
14926{
29917620 14927 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14928}
14929
14930static void __exit tg3_cleanup(void)
14931{
14932 pci_unregister_driver(&tg3_driver);
14933}
14934
14935module_init(tg3_init);
14936module_exit(tg3_cleanup);
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