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[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
ba5b0bfa 7 * Copyright (C) 2005-2010 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
b3b3f04f
MC		 71#define DRV_MODULE_VERSION "3.107"
72#define DRV_MODULE_RELDATE "February 12, 2010"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
b0f75221
MC		 247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
13185217
HK		 253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
259 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
260 {}
1da177e4
LT		 261};
262
263MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
264
50da859d 265static const struct {
1da177e4
LT		 266 const char string[ETH_GSTRING_LEN];
267} ethtool_stats_keys[TG3_NUM_STATS] = {
268 { "rx_octets" },
269 { "rx_fragments" },
270 { "rx_ucast_packets" },
271 { "rx_mcast_packets" },
272 { "rx_bcast_packets" },
273 { "rx_fcs_errors" },
274 { "rx_align_errors" },
275 { "rx_xon_pause_rcvd" },
276 { "rx_xoff_pause_rcvd" },
277 { "rx_mac_ctrl_rcvd" },
278 { "rx_xoff_entered" },
279 { "rx_frame_too_long_errors" },
280 { "rx_jabbers" },
281 { "rx_undersize_packets" },
282 { "rx_in_length_errors" },
283 { "rx_out_length_errors" },
284 { "rx_64_or_less_octet_packets" },
285 { "rx_65_to_127_octet_packets" },
286 { "rx_128_to_255_octet_packets" },
287 { "rx_256_to_511_octet_packets" },
288 { "rx_512_to_1023_octet_packets" },
289 { "rx_1024_to_1522_octet_packets" },
290 { "rx_1523_to_2047_octet_packets" },
291 { "rx_2048_to_4095_octet_packets" },
292 { "rx_4096_to_8191_octet_packets" },
293 { "rx_8192_to_9022_octet_packets" },
294
295 { "tx_octets" },
296 { "tx_collisions" },
297
298 { "tx_xon_sent" },
299 { "tx_xoff_sent" },
300 { "tx_flow_control" },
301 { "tx_mac_errors" },
302 { "tx_single_collisions" },
303 { "tx_mult_collisions" },
304 { "tx_deferred" },
305 { "tx_excessive_collisions" },
306 { "tx_late_collisions" },
307 { "tx_collide_2times" },
308 { "tx_collide_3times" },
309 { "tx_collide_4times" },
310 { "tx_collide_5times" },
311 { "tx_collide_6times" },
312 { "tx_collide_7times" },
313 { "tx_collide_8times" },
314 { "tx_collide_9times" },
315 { "tx_collide_10times" },
316 { "tx_collide_11times" },
317 { "tx_collide_12times" },
318 { "tx_collide_13times" },
319 { "tx_collide_14times" },
320 { "tx_collide_15times" },
321 { "tx_ucast_packets" },
322 { "tx_mcast_packets" },
323 { "tx_bcast_packets" },
324 { "tx_carrier_sense_errors" },
325 { "tx_discards" },
326 { "tx_errors" },
327
328 { "dma_writeq_full" },
329 { "dma_write_prioq_full" },
330 { "rxbds_empty" },
331 { "rx_discards" },
332 { "rx_errors" },
333 { "rx_threshold_hit" },
334
335 { "dma_readq_full" },
336 { "dma_read_prioq_full" },
337 { "tx_comp_queue_full" },
338
339 { "ring_set_send_prod_index" },
340 { "ring_status_update" },
341 { "nic_irqs" },
342 { "nic_avoided_irqs" },
343 { "nic_tx_threshold_hit" }
344};
345
50da859d 346static const struct {
4cafd3f5
MC		 347 const char string[ETH_GSTRING_LEN];
348} ethtool_test_keys[TG3_NUM_TEST] = {
349 { "nvram test (online) " },
350 { "link test (online) " },
351 { "register test (offline)" },
352 { "memory test (offline)" },
353 { "loopback test (offline)" },
354 { "interrupt test (offline)" },
355};
356
b401e9e2
MC		 357static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
358{
359 writel(val, tp->regs + off);
360}
361
362static u32 tg3_read32(struct tg3 *tp, u32 off)
363{
6aa20a22 364 return (readl(tp->regs + off));
b401e9e2
MC		 365}
366
0d3031d9
MC		 367static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
368{
369 writel(val, tp->aperegs + off);
370}
371
372static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
373{
374 return (readl(tp->aperegs + off));
375}
376
1da177e4
LT		 377static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
378{
6892914f
MC		 379 unsigned long flags;
380
381 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 385}
386
387static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
388{
389 writel(val, tp->regs + off);
390 readl(tp->regs + off);
1da177e4
LT		 391}
392
6892914f 393static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 394{
6892914f
MC		 395 unsigned long flags;
396 u32 val;
397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 return val;
403}
404
405static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
406{
407 unsigned long flags;
408
409 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
410 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
411 TG3_64BIT_REG_LOW, val);
412 return;
413 }
66711e66 414 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 415 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
416 TG3_64BIT_REG_LOW, val);
417 return;
1da177e4 418 }
6892914f
MC		 419
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424
425 /* In indirect mode when disabling interrupts, we also need
426 * to clear the interrupt bit in the GRC local ctrl register.
427 */
428 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
429 (val == 0x1)) {
430 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
431 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
432 }
433}
434
435static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
436{
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
442 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
444 return val;
445}
446
b401e9e2
MC		 447/* usec_wait specifies the wait time in usec when writing to certain registers
448 * where it is unsafe to read back the register without some delay.
449 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
450 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
451 */
452static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 453{
b401e9e2
MC		 454 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
455 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
456 /* Non-posted methods */
457 tp->write32(tp, off, val);
458 else {
459 /* Posted method */
460 tg3_write32(tp, off, val);
461 if (usec_wait)
462 udelay(usec_wait);
463 tp->read32(tp, off);
464 }
465 /* Wait again after the read for the posted method to guarantee that
466 * the wait time is met.
467 */
468 if (usec_wait)
469 udelay(usec_wait);
1da177e4
LT		 470}
471
09ee929c
MC		 472static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
473{
474 tp->write32_mbox(tp, off, val);
6892914f
MC		 475 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
476 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477 tp->read32_mbox(tp, off);
09ee929c
MC		 478}
479
20094930 480static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 481{
482 void __iomem *mbox = tp->regs + off;
483 writel(val, mbox);
484 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
485 writel(val, mbox);
486 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
487 readl(mbox);
488}
489
b5d3772c
MC		 490static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
491{
492 return (readl(tp->regs + off + GRCMBOX_BASE));
493}
494
495static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
496{
497 writel(val, tp->regs + off + GRCMBOX_BASE);
498}
499
20094930 500#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 501#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 502#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
503#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 504#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 505
506#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 507#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
508#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 509#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 510
511static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
512{
6892914f
MC		 513 unsigned long flags;
514
b5d3772c
MC		 515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
516 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
517 return;
518
6892914f 519 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 520 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 } else {
527 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
528 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 529
bbadf503
MC		 530 /* Always leave this as zero. */
531 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
532 }
533 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 534}
535
1da177e4
LT		 536static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
537{
6892914f
MC		 538 unsigned long flags;
539
b5d3772c
MC		 540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
542 *val = 0;
543 return;
544 }
545
6892914f 546 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 547 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
548 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
549 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 550
bbadf503
MC		 551 /* Always leave this as zero. */
552 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 } else {
554 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
555 *val = tr32(TG3PCI_MEM_WIN_DATA);
556
557 /* Always leave this as zero. */
558 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
559 }
6892914f 560 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 561}
562
0d3031d9
MC		 563static void tg3_ape_lock_init(struct tg3 *tp)
564{
565 int i;
566
567 /* Make sure the driver hasn't any stale locks. */
568 for (i = 0; i < 8; i++)
569 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
570 APE_LOCK_GRANT_DRIVER);
571}
572
573static int tg3_ape_lock(struct tg3 *tp, int locknum)
574{
575 int i, off;
576 int ret = 0;
577 u32 status;
578
579 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
580 return 0;
581
582 switch (locknum) {
77b483f1 583 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 584 case TG3_APE_LOCK_MEM:
585 break;
586 default:
587 return -EINVAL;
588 }
589
590 off = 4 * locknum;
591
592 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
593
594 /* Wait for up to 1 millisecond to acquire lock. */
595 for (i = 0; i < 100; i++) {
596 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
597 if (status == APE_LOCK_GRANT_DRIVER)
598 break;
599 udelay(10);
600 }
601
602 if (status != APE_LOCK_GRANT_DRIVER) {
603 /* Revoke the lock request. */
604 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
605 APE_LOCK_GRANT_DRIVER);
606
607 ret = -EBUSY;
608 }
609
610 return ret;
611}
612
613static void tg3_ape_unlock(struct tg3 *tp, int locknum)
614{
615 int off;
616
617 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
618 return;
619
620 switch (locknum) {
77b483f1 621 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 622 case TG3_APE_LOCK_MEM:
623 break;
624 default:
625 return;
626 }
627
628 off = 4 * locknum;
629 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
630}
631
1da177e4
LT		 632static void tg3_disable_ints(struct tg3 *tp)
633{
89aeb3bc
MC		 634 int i;
635
1da177e4
LT		 636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 638 for (i = 0; i < tp->irq_max; i++)
639 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 640}
641
1da177e4
LT		 642static void tg3_enable_ints(struct tg3 *tp)
643{
89aeb3bc 644 int i;
89aeb3bc 645
bbe832c0
MC		 646 tp->irq_sync = 0;
647 wmb();
648
1da177e4
LT		 649 tw32(TG3PCI_MISC_HOST_CTRL,
650 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 651
f89f38b8 652 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 653 for (i = 0; i < tp->irq_cnt; i++) {
654 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 655 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 656 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 658
f89f38b8 659 tp->coal_now |= tnapi->coal_now;
89aeb3bc 660 }
f19af9c2
MC		 661
662 /* Force an initial interrupt */
663 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
664 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
665 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
666 else
f89f38b8
MC		 667 tw32(HOSTCC_MODE, tp->coal_now);
668
669 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 670}
671
17375d25 672static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 673{
17375d25 674 struct tg3 *tp = tnapi->tp;
898a56f8 675 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 676 unsigned int work_exists = 0;
677
678 /* check for phy events */
679 if (!(tp->tg3_flags &
680 (TG3_FLAG_USE_LINKCHG_REG |
681 TG3_FLAG_POLL_SERDES))) {
682 if (sblk->status & SD_STATUS_LINK_CHG)
683 work_exists = 1;
684 }
685 /* check for RX/TX work to do */
f3f3f27e 686 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 687 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 688 work_exists = 1;
689
690 return work_exists;
691}
692
17375d25 693/* tg3_int_reenable
04237ddd
MC		 694 * similar to tg3_enable_ints, but it accurately determines whether there
695 * is new work pending and can return without flushing the PIO write
6aa20a22 696 * which reenables interrupts
1da177e4 697 */
17375d25 698static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 699{
17375d25
MC		 700 struct tg3 *tp = tnapi->tp;
701
898a56f8 702 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 703 mmiowb();
704
fac9b83e
DM		 705 /* When doing tagged status, this work check is unnecessary.
706 * The last_tag we write above tells the chip which piece of
707 * work we've completed.
708 */
709 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 710 tg3_has_work(tnapi))
04237ddd 711 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 712 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 713}
714
fed97810
MC		 715static void tg3_napi_disable(struct tg3 *tp)
716{
717 int i;
718
719 for (i = tp->irq_cnt - 1; i >= 0; i--)
720 napi_disable(&tp->napi[i].napi);
721}
722
723static void tg3_napi_enable(struct tg3 *tp)
724{
725 int i;
726
727 for (i = 0; i < tp->irq_cnt; i++)
728 napi_enable(&tp->napi[i].napi);
729}
730
1da177e4
LT		 731static inline void tg3_netif_stop(struct tg3 *tp)
732{
bbe832c0 733 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 734 tg3_napi_disable(tp);
1da177e4
LT		 735 netif_tx_disable(tp->dev);
736}
737
738static inline void tg3_netif_start(struct tg3 *tp)
739{
fe5f5787
MC		 740 /* NOTE: unconditional netif_tx_wake_all_queues is only
741 * appropriate so long as all callers are assured to
742 * have free tx slots (such as after tg3_init_hw)
1da177e4 743 */
fe5f5787
MC		 744 netif_tx_wake_all_queues(tp->dev);
745
fed97810
MC		 746 tg3_napi_enable(tp);
747 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 748 tg3_enable_ints(tp);
1da177e4
LT		 749}
750
751static void tg3_switch_clocks(struct tg3 *tp)
752{
f6eb9b1f 753 u32 clock_ctrl;
1da177e4
LT		 754 u32 orig_clock_ctrl;
755
795d01c5
MC		 756 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
757 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 758 return;
759
f6eb9b1f
MC		 760 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
761
1da177e4
LT		 762 orig_clock_ctrl = clock_ctrl;
763 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
764 CLOCK_CTRL_CLKRUN_OENABLE |
765 0x1f);
766 tp->pci_clock_ctrl = clock_ctrl;
767
768 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
769 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 770 tw32_wait_f(TG3PCI_CLOCK_CTRL,
771 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 772 }
773 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 774 tw32_wait_f(TG3PCI_CLOCK_CTRL,
775 clock_ctrl |
776 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
777 40);
778 tw32_wait_f(TG3PCI_CLOCK_CTRL,
779 clock_ctrl | (CLOCK_CTRL_ALTCLK),
780 40);
1da177e4 781 }
b401e9e2 782 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 783}
784
785#define PHY_BUSY_LOOPS 5000
786
787static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
788{
789 u32 frame_val;
790 unsigned int loops;
791 int ret;
792
793 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
794 tw32_f(MAC_MI_MODE,
795 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
796 udelay(80);
797 }
798
799 *val = 0x0;
800
882e9793 801 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 802 MI_COM_PHY_ADDR_MASK);
803 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
804 MI_COM_REG_ADDR_MASK);
805 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 806
1da177e4
LT		 807 tw32_f(MAC_MI_COM, frame_val);
808
809 loops = PHY_BUSY_LOOPS;
810 while (loops != 0) {
811 udelay(10);
812 frame_val = tr32(MAC_MI_COM);
813
814 if ((frame_val & MI_COM_BUSY) == 0) {
815 udelay(5);
816 frame_val = tr32(MAC_MI_COM);
817 break;
818 }
819 loops -= 1;
820 }
821
822 ret = -EBUSY;
823 if (loops != 0) {
824 *val = frame_val & MI_COM_DATA_MASK;
825 ret = 0;
826 }
827
828 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
829 tw32_f(MAC_MI_MODE, tp->mi_mode);
830 udelay(80);
831 }
832
833 return ret;
834}
835
836static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
837{
838 u32 frame_val;
839 unsigned int loops;
840 int ret;
841
7f97a4bd 842 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 843 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
844 return 0;
845
1da177e4
LT		 846 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
847 tw32_f(MAC_MI_MODE,
848 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
849 udelay(80);
850 }
851
882e9793 852 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 853 MI_COM_PHY_ADDR_MASK);
854 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
855 MI_COM_REG_ADDR_MASK);
856 frame_val |= (val & MI_COM_DATA_MASK);
857 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 858
1da177e4
LT		 859 tw32_f(MAC_MI_COM, frame_val);
860
861 loops = PHY_BUSY_LOOPS;
862 while (loops != 0) {
863 udelay(10);
864 frame_val = tr32(MAC_MI_COM);
865 if ((frame_val & MI_COM_BUSY) == 0) {
866 udelay(5);
867 frame_val = tr32(MAC_MI_COM);
868 break;
869 }
870 loops -= 1;
871 }
872
873 ret = -EBUSY;
874 if (loops != 0)
875 ret = 0;
876
877 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
878 tw32_f(MAC_MI_MODE, tp->mi_mode);
879 udelay(80);
880 }
881
882 return ret;
883}
884
95e2869a
MC		 885static int tg3_bmcr_reset(struct tg3 *tp)
886{
887 u32 phy_control;
888 int limit, err;
889
890 /* OK, reset it, and poll the BMCR_RESET bit until it
891 * clears or we time out.
892 */
893 phy_control = BMCR_RESET;
894 err = tg3_writephy(tp, MII_BMCR, phy_control);
895 if (err != 0)
896 return -EBUSY;
897
898 limit = 5000;
899 while (limit--) {
900 err = tg3_readphy(tp, MII_BMCR, &phy_control);
901 if (err != 0)
902 return -EBUSY;
903
904 if ((phy_control & BMCR_RESET) == 0) {
905 udelay(40);
906 break;
907 }
908 udelay(10);
909 }
d4675b52 910 if (limit < 0)
95e2869a
MC		 911 return -EBUSY;
912
913 return 0;
914}
915
158d7abd
MC		 916static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
917{
3d16543d 918 struct tg3 *tp = bp->priv;
158d7abd
MC		 919 u32 val;
920
24bb4fb6 921 spin_lock_bh(&tp->lock);
158d7abd
MC		 922
923 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 924 val = -EIO;
925
926 spin_unlock_bh(&tp->lock);
158d7abd
MC		 927
928 return val;
929}
930
931static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
932{
3d16543d 933 struct tg3 *tp = bp->priv;
24bb4fb6 934 u32 ret = 0;
158d7abd 935
24bb4fb6 936 spin_lock_bh(&tp->lock);
158d7abd
MC		 937
938 if (tg3_writephy(tp, reg, val))
24bb4fb6 939 ret = -EIO;
158d7abd 940
24bb4fb6
MC		 941 spin_unlock_bh(&tp->lock);
942
943 return ret;
158d7abd
MC		 944}
945
946static int tg3_mdio_reset(struct mii_bus *bp)
947{
948 return 0;
949}
950
9c61d6bc 951static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 952{
953 u32 val;
fcb389df 954 struct phy_device *phydev;
a9daf367 955
3f0e3ad7 956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 957 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
958 case TG3_PHY_ID_BCM50610:
c73430d0 959 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 960 val = MAC_PHYCFG2_50610_LED_MODES;
961 break;
962 case TG3_PHY_ID_BCMAC131:
963 val = MAC_PHYCFG2_AC131_LED_MODES;
964 break;
965 case TG3_PHY_ID_RTL8211C:
966 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
967 break;
968 case TG3_PHY_ID_RTL8201E:
969 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
970 break;
971 default:
a9daf367 972 return;
fcb389df
MC		 973 }
974
975 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
976 tw32(MAC_PHYCFG2, val);
977
978 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 979 val &= ~(MAC_PHYCFG1_RGMII_INT |
980 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
981 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 982 tw32(MAC_PHYCFG1, val);
983
984 return;
985 }
986
987 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
988 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
989 MAC_PHYCFG2_FMODE_MASK_MASK |
990 MAC_PHYCFG2_GMODE_MASK_MASK |
991 MAC_PHYCFG2_ACT_MASK_MASK |
992 MAC_PHYCFG2_QUAL_MASK_MASK |
993 MAC_PHYCFG2_INBAND_ENABLE;
994
995 tw32(MAC_PHYCFG2, val);
a9daf367 996
bb85fbb6
MC		 997 val = tr32(MAC_PHYCFG1);
998 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
999 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1000 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1001 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1002 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1004 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1005 }
bb85fbb6
MC		 1006 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1007 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1008 tw32(MAC_PHYCFG1, val);
a9daf367 1009
a9daf367
MC		 1010 val = tr32(MAC_EXT_RGMII_MODE);
1011 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1012 MAC_RGMII_MODE_RX_QUALITY |
1013 MAC_RGMII_MODE_RX_ACTIVITY |
1014 MAC_RGMII_MODE_RX_ENG_DET |
1015 MAC_RGMII_MODE_TX_ENABLE |
1016 MAC_RGMII_MODE_TX_LOWPWR |
1017 MAC_RGMII_MODE_TX_RESET);
fcb389df 1018 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1019 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1020 val |= MAC_RGMII_MODE_RX_INT_B |
1021 MAC_RGMII_MODE_RX_QUALITY |
1022 MAC_RGMII_MODE_RX_ACTIVITY |
1023 MAC_RGMII_MODE_RX_ENG_DET;
1024 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1025 val |= MAC_RGMII_MODE_TX_ENABLE |
1026 MAC_RGMII_MODE_TX_LOWPWR |
1027 MAC_RGMII_MODE_TX_RESET;
1028 }
1029 tw32(MAC_EXT_RGMII_MODE, val);
1030}
1031
158d7abd
MC		 1032static void tg3_mdio_start(struct tg3 *tp)
1033{
158d7abd
MC		 1034 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1035 tw32_f(MAC_MI_MODE, tp->mi_mode);
1036 udelay(80);
a9daf367 1037
882e9793
MC		 1038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1039 u32 funcnum, is_serdes;
1040
1041 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1042 if (funcnum)
1043 tp->phy_addr = 2;
1044 else
1045 tp->phy_addr = 1;
1046
d1ec96af
MC		 1047 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1048 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1049 else
1050 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1051 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1052 if (is_serdes)
1053 tp->phy_addr += 7;
1054 } else
3f0e3ad7 1055 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1056
9c61d6bc
MC		 1057 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1059 tg3_mdio_config_5785(tp);
158d7abd
MC		 1060}
1061
158d7abd
MC		 1062static int tg3_mdio_init(struct tg3 *tp)
1063{
1064 int i;
1065 u32 reg;
a9daf367 1066 struct phy_device *phydev;
158d7abd
MC		 1067
1068 tg3_mdio_start(tp);
1069
1070 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072 return 0;
1073
298cf9be
LB		 1074 tp->mdio_bus = mdiobus_alloc();
1075 if (tp->mdio_bus == NULL)
1076 return -ENOMEM;
158d7abd 1077
298cf9be
LB		 1078 tp->mdio_bus->name = "tg3 mdio bus";
1079 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1080 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1081 tp->mdio_bus->priv = tp;
1082 tp->mdio_bus->parent = &tp->pdev->dev;
1083 tp->mdio_bus->read = &tg3_mdio_read;
1084 tp->mdio_bus->write = &tg3_mdio_write;
1085 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1086 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1087 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1088
1089 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1090 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1091
1092 /* The bus registration will look for all the PHYs on the mdio bus.
1093 * Unfortunately, it does not ensure the PHY is powered up before
1094 * accessing the PHY ID registers. A chip reset is the
1095 * quickest way to bring the device back to an operational state..
1096 */
1097 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098 tg3_bmcr_reset(tp);
1099
298cf9be 1100 i = mdiobus_register(tp->mdio_bus);
a9daf367 1101 if (i) {
158d7abd
MC		 1102 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1103 tp->dev->name, i);
9c61d6bc 1104 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1105 return i;
1106 }
158d7abd 1107
3f0e3ad7 1108 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1109
9c61d6bc
MC		 1110 if (!phydev || !phydev->drv) {
1111 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1112 mdiobus_unregister(tp->mdio_bus);
1113 mdiobus_free(tp->mdio_bus);
1114 return -ENODEV;
1115 }
1116
1117 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1118 case TG3_PHY_ID_BCM57780:
1119 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1121 break;
a9daf367 1122 case TG3_PHY_ID_BCM50610:
c73430d0 1123 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1124 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1125 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1126 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1127 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1128 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1129 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1134 /* fallthru */
1135 case TG3_PHY_ID_RTL8211C:
1136 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1137 break;
fcb389df 1138 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1139 case TG3_PHY_ID_BCMAC131:
1140 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1141 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1142 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1143 break;
1144 }
1145
9c61d6bc
MC		 1146 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147
1148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149 tg3_mdio_config_5785(tp);
a9daf367
MC		 1150
1151 return 0;
158d7abd
MC		 1152}
1153
1154static void tg3_mdio_fini(struct tg3 *tp)
1155{
1156 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1158 mdiobus_unregister(tp->mdio_bus);
1159 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1160 }
1161}
1162
4ba526ce
MC		 1163/* tp->lock is held. */
1164static inline void tg3_generate_fw_event(struct tg3 *tp)
1165{
1166 u32 val;
1167
1168 val = tr32(GRC_RX_CPU_EVENT);
1169 val |= GRC_RX_CPU_DRIVER_EVENT;
1170 tw32_f(GRC_RX_CPU_EVENT, val);
1171
1172 tp->last_event_jiffies = jiffies;
1173}
1174
1175#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176
95e2869a
MC		 1177/* tp->lock is held. */
1178static void tg3_wait_for_event_ack(struct tg3 *tp)
1179{
1180 int i;
4ba526ce
MC		 1181 unsigned int delay_cnt;
1182 long time_remain;
1183
1184 /* If enough time has passed, no wait is necessary. */
1185 time_remain = (long)(tp->last_event_jiffies + 1 +
1186 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187 (long)jiffies;
1188 if (time_remain < 0)
1189 return;
1190
1191 /* Check if we can shorten the wait time. */
1192 delay_cnt = jiffies_to_usecs(time_remain);
1193 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1196
4ba526ce 1197 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1198 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1199 break;
4ba526ce 1200 udelay(8);
95e2869a
MC		 1201 }
1202}
1203
1204/* tp->lock is held. */
1205static void tg3_ump_link_report(struct tg3 *tp)
1206{
1207 u32 reg;
1208 u32 val;
1209
1210 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1212 return;
1213
1214 tg3_wait_for_event_ack(tp);
1215
1216 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1219
1220 val = 0;
1221 if (!tg3_readphy(tp, MII_BMCR, &reg))
1222 val = reg << 16;
1223 if (!tg3_readphy(tp, MII_BMSR, &reg))
1224 val |= (reg & 0xffff);
1225 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1226
1227 val = 0;
1228 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1229 val = reg << 16;
1230 if (!tg3_readphy(tp, MII_LPA, &reg))
1231 val |= (reg & 0xffff);
1232 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1233
1234 val = 0;
1235 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1236 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1237 val = reg << 16;
1238 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1239 val |= (reg & 0xffff);
1240 }
1241 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242
1243 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1244 val = reg << 16;
1245 else
1246 val = 0;
1247 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248
4ba526ce 1249 tg3_generate_fw_event(tp);
95e2869a
MC		 1250}
1251
1252static void tg3_link_report(struct tg3 *tp)
1253{
1254 if (!netif_carrier_ok(tp->dev)) {
1255 if (netif_msg_link(tp))
1256 printk(KERN_INFO PFX "%s: Link is down.\n",
1257 tp->dev->name);
1258 tg3_ump_link_report(tp);
1259 } else if (netif_msg_link(tp)) {
1260 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1261 tp->dev->name,
1262 (tp->link_config.active_speed == SPEED_1000 ?
1263 1000 :
1264 (tp->link_config.active_speed == SPEED_100 ?
1265 100 : 10)),
1266 (tp->link_config.active_duplex == DUPLEX_FULL ?
1267 "full" : "half"));
1268
1269 printk(KERN_INFO PFX
1270 "%s: Flow control is %s for TX and %s for RX.\n",
1271 tp->dev->name,
e18ce346 1272 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1273 "on" : "off",
e18ce346 1274 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1275 "on" : "off");
1276 tg3_ump_link_report(tp);
1277 }
1278}
1279
1280static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1281{
1282 u16 miireg;
1283
e18ce346 1284 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1285 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1286 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1287 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1288 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1289 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1290 else
1291 miireg = 0;
1292
1293 return miireg;
1294}
1295
1296static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1297{
1298 u16 miireg;
1299
e18ce346 1300 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1301 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1302 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1303 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1304 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1305 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1306 else
1307 miireg = 0;
1308
1309 return miireg;
1310}
1311
95e2869a
MC		 1312static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1313{
1314 u8 cap = 0;
1315
1316 if (lcladv & ADVERTISE_1000XPAUSE) {
1317 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1318 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1319 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1320 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1321 cap = FLOW_CTRL_RX;
95e2869a
MC		 1322 } else {
1323 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1324 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1325 }
1326 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1327 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1328 cap = FLOW_CTRL_TX;
95e2869a
MC		 1329 }
1330
1331 return cap;
1332}
1333
f51f3562 1334static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1335{
b02fd9e3 1336 u8 autoneg;
f51f3562 1337 u8 flowctrl = 0;
95e2869a
MC		 1338 u32 old_rx_mode = tp->rx_mode;
1339 u32 old_tx_mode = tp->tx_mode;
1340
b02fd9e3 1341 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1342 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1343 else
1344 autoneg = tp->link_config.autoneg;
1345
1346 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1347 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1349 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1350 else
bc02ff95 1351 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1352 } else
1353 flowctrl = tp->link_config.flowctrl;
95e2869a 1354
f51f3562 1355 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1356
e18ce346 1357 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1358 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1359 else
1360 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1361
f51f3562 1362 if (old_rx_mode != tp->rx_mode)
95e2869a 1363 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1364
e18ce346 1365 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1366 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1367 else
1368 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1369
f51f3562 1370 if (old_tx_mode != tp->tx_mode)
95e2869a 1371 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1372}
1373
b02fd9e3
MC		 1374static void tg3_adjust_link(struct net_device *dev)
1375{
1376 u8 oldflowctrl, linkmesg = 0;
1377 u32 mac_mode, lcl_adv, rmt_adv;
1378 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1379 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1380
24bb4fb6 1381 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1382
1383 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1384 MAC_MODE_HALF_DUPLEX);
1385
1386 oldflowctrl = tp->link_config.active_flowctrl;
1387
1388 if (phydev->link) {
1389 lcl_adv = 0;
1390 rmt_adv = 0;
1391
1392 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1393 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1394 else if (phydev->speed == SPEED_1000 ||
1395 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1396 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1397 else
1398 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1399
1400 if (phydev->duplex == DUPLEX_HALF)
1401 mac_mode |= MAC_MODE_HALF_DUPLEX;
1402 else {
1403 lcl_adv = tg3_advert_flowctrl_1000T(
1404 tp->link_config.flowctrl);
1405
1406 if (phydev->pause)
1407 rmt_adv = LPA_PAUSE_CAP;
1408 if (phydev->asym_pause)
1409 rmt_adv |= LPA_PAUSE_ASYM;
1410 }
1411
1412 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1413 } else
1414 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1415
1416 if (mac_mode != tp->mac_mode) {
1417 tp->mac_mode = mac_mode;
1418 tw32_f(MAC_MODE, tp->mac_mode);
1419 udelay(40);
1420 }
1421
fcb389df
MC		 1422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1423 if (phydev->speed == SPEED_10)
1424 tw32(MAC_MI_STAT,
1425 MAC_MI_STAT_10MBPS_MODE |
1426 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1427 else
1428 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1429 }
1430
b02fd9e3
MC		 1431 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1432 tw32(MAC_TX_LENGTHS,
1433 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434 (6 << TX_LENGTHS_IPG_SHIFT) |
1435 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436 else
1437 tw32(MAC_TX_LENGTHS,
1438 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1439 (6 << TX_LENGTHS_IPG_SHIFT) |
1440 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1441
1442 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1443 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1444 phydev->speed != tp->link_config.active_speed ||
1445 phydev->duplex != tp->link_config.active_duplex ||
1446 oldflowctrl != tp->link_config.active_flowctrl)
1447 linkmesg = 1;
1448
1449 tp->link_config.active_speed = phydev->speed;
1450 tp->link_config.active_duplex = phydev->duplex;
1451
24bb4fb6 1452 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1453
1454 if (linkmesg)
1455 tg3_link_report(tp);
1456}
1457
1458static int tg3_phy_init(struct tg3 *tp)
1459{
1460 struct phy_device *phydev;
1461
1462 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1463 return 0;
1464
1465 /* Bring the PHY back to a known state. */
1466 tg3_bmcr_reset(tp);
1467
3f0e3ad7 1468 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1469
1470 /* Attach the MAC to the PHY. */
fb28ad35 1471 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1472 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1473 if (IS_ERR(phydev)) {
1474 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1475 return PTR_ERR(phydev);
1476 }
1477
b02fd9e3 1478 /* Mask with MAC supported features. */
9c61d6bc
MC		 1479 switch (phydev->interface) {
1480 case PHY_INTERFACE_MODE_GMII:
1481 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1482 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1483 phydev->supported &= (PHY_GBIT_FEATURES |
1484 SUPPORTED_Pause |
1485 SUPPORTED_Asym_Pause);
1486 break;
1487 }
1488 /* fallthru */
9c61d6bc
MC		 1489 case PHY_INTERFACE_MODE_MII:
1490 phydev->supported &= (PHY_BASIC_FEATURES |
1491 SUPPORTED_Pause |
1492 SUPPORTED_Asym_Pause);
1493 break;
1494 default:
3f0e3ad7 1495 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1496 return -EINVAL;
1497 }
1498
1499 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1500
1501 phydev->advertising = phydev->supported;
1502
b02fd9e3
MC		 1503 return 0;
1504}
1505
1506static void tg3_phy_start(struct tg3 *tp)
1507{
1508 struct phy_device *phydev;
1509
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511 return;
1512
3f0e3ad7 1513 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1514
1515 if (tp->link_config.phy_is_low_power) {
1516 tp->link_config.phy_is_low_power = 0;
1517 phydev->speed = tp->link_config.orig_speed;
1518 phydev->duplex = tp->link_config.orig_duplex;
1519 phydev->autoneg = tp->link_config.orig_autoneg;
1520 phydev->advertising = tp->link_config.orig_advertising;
1521 }
1522
1523 phy_start(phydev);
1524
1525 phy_start_aneg(phydev);
1526}
1527
1528static void tg3_phy_stop(struct tg3 *tp)
1529{
1530 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1531 return;
1532
3f0e3ad7 1533 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1534}
1535
1536static void tg3_phy_fini(struct tg3 *tp)
1537{
1538 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1539 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1540 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1541 }
1542}
1543
b2a5c19c
MC		 1544static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1545{
1546 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1547 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1548}
1549
7f97a4bd
MC		 1550static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1551{
1552 u32 phytest;
1553
1554 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1555 u32 phy;
1556
1557 tg3_writephy(tp, MII_TG3_FET_TEST,
1558 phytest | MII_TG3_FET_SHADOW_EN);
1559 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560 if (enable)
1561 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562 else
1563 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565 }
1566 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1567 }
1568}
1569
6833c043
MC		 1570static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1571{
1572 u32 reg;
1573
ecf1410b
MC		 1574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1576 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1577 return;
1578
7f97a4bd
MC		 1579 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1580 tg3_phy_fet_toggle_apd(tp, enable);
1581 return;
1582 }
1583
6833c043
MC		 1584 reg = MII_TG3_MISC_SHDW_WREN |
1585 MII_TG3_MISC_SHDW_SCR5_SEL |
1586 MII_TG3_MISC_SHDW_SCR5_LPED |
1587 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588 MII_TG3_MISC_SHDW_SCR5_SDTL |
1589 MII_TG3_MISC_SHDW_SCR5_C125OE;
1590 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596 reg = MII_TG3_MISC_SHDW_WREN |
1597 MII_TG3_MISC_SHDW_APD_SEL |
1598 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599 if (enable)
1600 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603}
1604
9ef8ca99
MC		 1605static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606{
1607 u32 phy;
1608
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1611 return;
1612
7f97a4bd 1613 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1614 u32 ephy;
1615
535ef6e1
MC		 1616 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619 tg3_writephy(tp, MII_TG3_FET_TEST,
1620 ephy | MII_TG3_FET_SHADOW_EN);
1621 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1622 if (enable)
535ef6e1 1623 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1624 else
535ef6e1
MC		 1625 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626 tg3_writephy(tp, reg, phy);
9ef8ca99 1627 }
535ef6e1 1628 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1629 }
1630 } else {
1631 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632 MII_TG3_AUXCTL_SHDWSEL_MISC;
1633 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635 if (enable)
1636 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637 else
1638 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639 phy |= MII_TG3_AUXCTL_MISC_WREN;
1640 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641 }
1642 }
1643}
1644
1da177e4
LT		 1645static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646{
1647 u32 val;
1648
1649 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1650 return;
1651
1652 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655 (val | (1 << 15) | (1 << 4)));
1656}
1657
b2a5c19c
MC		 1658static void tg3_phy_apply_otp(struct tg3 *tp)
1659{
1660 u32 otp, phy;
1661
1662 if (!tp->phy_otp)
1663 return;
1664
1665 otp = tp->phy_otp;
1666
1667 /* Enable SM_DSP clock and tx 6dB coding. */
1668 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670 MII_TG3_AUXCTL_ACTL_TX_6DB;
1671 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695 /* Turn off SM_DSP clock. */
1696 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697 MII_TG3_AUXCTL_ACTL_TX_6DB;
1698 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699}
1700
1da177e4
LT		 1701static int tg3_wait_macro_done(struct tg3 *tp)
1702{
1703 int limit = 100;
1704
1705 while (limit--) {
1706 u32 tmp32;
1707
1708 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1709 if ((tmp32 & 0x1000) == 0)
1710 break;
1711 }
1712 }
d4675b52 1713 if (limit < 0)
1da177e4
LT		 1714 return -EBUSY;
1715
1716 return 0;
1717}
1718
1719static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720{
1721 static const u32 test_pat[4][6] = {
1722 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726 };
1727 int chan;
1728
1729 for (chan = 0; chan < 4; chan++) {
1730 int i;
1731
1732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733 (chan * 0x2000) | 0x0200);
1734 tg3_writephy(tp, 0x16, 0x0002);
1735
1736 for (i = 0; i < 6; i++)
1737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738 test_pat[chan][i]);
1739
1740 tg3_writephy(tp, 0x16, 0x0202);
1741 if (tg3_wait_macro_done(tp)) {
1742 *resetp = 1;
1743 return -EBUSY;
1744 }
1745
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, 0x16, 0x0082);
1749 if (tg3_wait_macro_done(tp)) {
1750 *resetp = 1;
1751 return -EBUSY;
1752 }
1753
1754 tg3_writephy(tp, 0x16, 0x0802);
1755 if (tg3_wait_macro_done(tp)) {
1756 *resetp = 1;
1757 return -EBUSY;
1758 }
1759
1760 for (i = 0; i < 6; i += 2) {
1761 u32 low, high;
1762
1763 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765 tg3_wait_macro_done(tp)) {
1766 *resetp = 1;
1767 return -EBUSY;
1768 }
1769 low &= 0x7fff;
1770 high &= 0x000f;
1771 if (low != test_pat[chan][i] ||
1772 high != test_pat[chan][i+1]) {
1773 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777 return -EBUSY;
1778 }
1779 }
1780 }
1781
1782 return 0;
1783}
1784
1785static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786{
1787 int chan;
1788
1789 for (chan = 0; chan < 4; chan++) {
1790 int i;
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793 (chan * 0x2000) | 0x0200);
1794 tg3_writephy(tp, 0x16, 0x0002);
1795 for (i = 0; i < 6; i++)
1796 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797 tg3_writephy(tp, 0x16, 0x0202);
1798 if (tg3_wait_macro_done(tp))
1799 return -EBUSY;
1800 }
1801
1802 return 0;
1803}
1804
1805static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806{
1807 u32 reg32, phy9_orig;
1808 int retries, do_phy_reset, err;
1809
1810 retries = 10;
1811 do_phy_reset = 1;
1812 do {
1813 if (do_phy_reset) {
1814 err = tg3_bmcr_reset(tp);
1815 if (err)
1816 return err;
1817 do_phy_reset = 0;
1818 }
1819
1820 /* Disable transmitter and interrupt. */
1821 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822 continue;
1823
1824 reg32 |= 0x3000;
1825 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827 /* Set full-duplex, 1000 mbps. */
1828 tg3_writephy(tp, MII_BMCR,
1829 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831 /* Set to master mode. */
1832 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833 continue;
1834
1835 tg3_writephy(tp, MII_TG3_CTRL,
1836 (MII_TG3_CTRL_AS_MASTER |
1837 MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839 /* Enable SM_DSP_CLOCK and 6dB. */
1840 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842 /* Block the PHY control access. */
1843 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1845
1846 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1847 if (!err)
1848 break;
1849 } while (--retries);
1850
1851 err = tg3_phy_reset_chanpat(tp);
1852 if (err)
1853 return err;
1854
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1857
1858 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1859 tg3_writephy(tp, 0x16, 0x0000);
1860
1861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1863 /* Set Extended packet length bit for jumbo frames */
1864 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1865 }
1866 else {
1867 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1868 }
1869
1870 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1871
1872 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1873 reg32 &= ~0x3000;
1874 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875 } else if (!err)
1876 err = -EBUSY;
1877
1878 return err;
1879}
1880
1881/* This will reset the tigon3 PHY if there is no valid
1882 * link unless the FORCE argument is non-zero.
1883 */
1884static int tg3_phy_reset(struct tg3 *tp)
1885{
b2a5c19c 1886 u32 cpmuctrl;
1da177e4
LT		 1887 u32 phy_status;
1888 int err;
1889
60189ddf
MC		 1890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1891 u32 val;
1892
1893 val = tr32(GRC_MISC_CFG);
1894 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1895 udelay(40);
1896 }
1da177e4
LT		 1897 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1898 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1899 if (err != 0)
1900 return -EBUSY;
1901
c8e1e82b
MC		 1902 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1903 netif_carrier_off(tp->dev);
1904 tg3_link_report(tp);
1905 }
1906
1da177e4
LT		 1907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1910 err = tg3_phy_reset_5703_4_5(tp);
1911 if (err)
1912 return err;
1913 goto out;
1914 }
1915
b2a5c19c
MC		 1916 cpmuctrl = 0;
1917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1918 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1919 cpmuctrl = tr32(TG3_CPMU_CTRL);
1920 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1921 tw32(TG3_CPMU_CTRL,
1922 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1923 }
1924
1da177e4
LT		 1925 err = tg3_bmcr_reset(tp);
1926 if (err)
1927 return err;
1928
b2a5c19c
MC		 1929 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1930 u32 phy;
1931
1932 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1933 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1934
1935 tw32(TG3_CPMU_CTRL, cpmuctrl);
1936 }
1937
bcb37f6c
MC		 1938 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1939 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1940 u32 val;
1941
1942 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1943 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1944 CPMU_LSPD_1000MB_MACCLK_12_5) {
1945 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1946 udelay(40);
1947 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1948 }
1949 }
1950
ecf1410b
MC		 1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1952 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1953 return 0;
1954
b2a5c19c
MC		 1955 tg3_phy_apply_otp(tp);
1956
6833c043
MC		 1957 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1958 tg3_phy_toggle_apd(tp, true);
1959 else
1960 tg3_phy_toggle_apd(tp, false);
1961
1da177e4
LT		 1962out:
1963 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1965 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1966 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1967 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1968 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970 }
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1972 tg3_writephy(tp, 0x1c, 0x8d68);
1973 tg3_writephy(tp, 0x1c, 0x8d68);
1974 }
1975 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1977 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984 }
c424cb24
MC		 1985 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1986 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1987 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1988 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1989 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1990 tg3_writephy(tp, MII_TG3_TEST1,
1991 MII_TG3_TEST1_TRIM_EN | 0x4);
1992 } else
1993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1995 }
1da177e4
LT		 1996 /* Set Extended packet length bit (bit 14) on all chips that */
1997 /* support jumbo frames */
1998 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1999 /* Cannot do read-modify-write on 5401 */
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 2001 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2002 u32 phy_reg;
2003
2004 /* Set bit 14 with read-modify-write to preserve other bits */
2005 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2006 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2007 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2008 }
2009
2010 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2011 * jumbo frames transmission.
2012 */
8f666b07 2013 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2014 u32 phy_reg;
2015
2016 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2017 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2018 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2019 }
2020
715116a1 2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2022 /* adjust output voltage */
535ef6e1 2023 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2024 }
2025
9ef8ca99 2026 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2027 tg3_phy_set_wirespeed(tp);
2028 return 0;
2029}
2030
2031static void tg3_frob_aux_power(struct tg3 *tp)
2032{
2033 struct tg3 *tp_peer = tp;
2034
334355aa
MC		 2035 /* The GPIOs do something completely different on 57765. */
2036 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2038 return;
2039
f6eb9b1f
MC		 2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2043 struct net_device *dev_peer;
2044
2045 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2046 /* remove_one() may have been run on the peer. */
8c2dc7e1 2047 if (!dev_peer)
bc1c7567
MC		 2048 tp_peer = tp;
2049 else
2050 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2051 }
2052
1da177e4 2053 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2054 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2055 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2056 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE0 |
2061 GRC_LCLCTRL_GPIO_OE1 |
2062 GRC_LCLCTRL_GPIO_OE2 |
2063 GRC_LCLCTRL_GPIO_OUTPUT0 |
2064 GRC_LCLCTRL_GPIO_OUTPUT1),
2065 100);
8d519ab2
MC		 2066 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2067 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2068 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2069 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2070 GRC_LCLCTRL_GPIO_OE1 |
2071 GRC_LCLCTRL_GPIO_OE2 |
2072 GRC_LCLCTRL_GPIO_OUTPUT0 |
2073 GRC_LCLCTRL_GPIO_OUTPUT1 |
2074 tp->grc_local_ctrl;
2075 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2076
2077 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2078 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2079
2080 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2081 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2082 } else {
2083 u32 no_gpio2;
dc56b7d4 2084 u32 grc_local_ctrl = 0;
1da177e4
LT		 2085
2086 if (tp_peer != tp &&
2087 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2088 return;
2089
dc56b7d4
MC		 2090 /* Workaround to prevent overdrawing Amps. */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2092 ASIC_REV_5714) {
2093 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095 grc_local_ctrl, 100);
dc56b7d4
MC		 2096 }
2097
1da177e4
LT		 2098 /* On 5753 and variants, GPIO2 cannot be used. */
2099 no_gpio2 = tp->nic_sram_data_cfg &
2100 NIC_SRAM_DATA_CFG_NO_GPIO2;
2101
dc56b7d4 2102 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2103 GRC_LCLCTRL_GPIO_OE1 |
2104 GRC_LCLCTRL_GPIO_OE2 |
2105 GRC_LCLCTRL_GPIO_OUTPUT1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT2;
2107 if (no_gpio2) {
2108 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2109 GRC_LCLCTRL_GPIO_OUTPUT2);
2110 }
b401e9e2
MC		 2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 grc_local_ctrl, 100);
1da177e4
LT		 2113
2114 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2115
b401e9e2
MC		 2116 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2117 grc_local_ctrl, 100);
1da177e4
LT		 2118
2119 if (!no_gpio2) {
2120 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 grc_local_ctrl, 100);
1da177e4
LT		 2123 }
2124 }
2125 } else {
2126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2127 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2128 if (tp_peer != tp &&
2129 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2130 return;
2131
b401e9e2
MC		 2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 (GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2135
b401e9e2
MC		 2136 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2137 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2138
b401e9e2
MC		 2139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140 (GRC_LCLCTRL_GPIO_OE1 |
2141 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2142 }
2143 }
2144}
2145
e8f3f6ca
MC		 2146static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2147{
2148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2149 return 1;
2150 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2151 if (speed != SPEED_10)
2152 return 1;
2153 } else if (speed == SPEED_10)
2154 return 1;
2155
2156 return 0;
2157}
2158
1da177e4
LT		 2159static int tg3_setup_phy(struct tg3 *, int);
2160
2161#define RESET_KIND_SHUTDOWN 0
2162#define RESET_KIND_INIT 1
2163#define RESET_KIND_SUSPEND 2
2164
2165static void tg3_write_sig_post_reset(struct tg3 *, int);
2166static int tg3_halt_cpu(struct tg3 *, u32);
2167
0a459aac 2168static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2169{
ce057f01
MC		 2170 u32 val;
2171
5129724a
MC		 2172 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2174 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2175 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2176
2177 sg_dig_ctrl |=
2178 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2179 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2180 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2181 }
3f7045c1 2182 return;
5129724a 2183 }
3f7045c1 2184
60189ddf 2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2186 tg3_bmcr_reset(tp);
2187 val = tr32(GRC_MISC_CFG);
2188 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2189 udelay(40);
2190 return;
0e5f784c
MC		 2191 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2192 u32 phytest;
2193 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2194 u32 phy;
2195
2196 tg3_writephy(tp, MII_ADVERTISE, 0);
2197 tg3_writephy(tp, MII_BMCR,
2198 BMCR_ANENABLE | BMCR_ANRESTART);
2199
2200 tg3_writephy(tp, MII_TG3_FET_TEST,
2201 phytest | MII_TG3_FET_SHADOW_EN);
2202 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2203 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2204 tg3_writephy(tp,
2205 MII_TG3_FET_SHDW_AUXMODE4,
2206 phy);
2207 }
2208 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2209 }
2210 return;
0a459aac 2211 } else if (do_low_power) {
715116a1
MC		 2212 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2213 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2214
2215 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2216 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2217 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2218 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2219 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2220 }
3f7045c1 2221
15c3b696
MC		 2222 /* The PHY should not be powered down on some chips because
2223 * of bugs.
2224 */
2225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2227 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2228 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2229 return;
ce057f01 2230
bcb37f6c
MC		 2231 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2232 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2233 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2234 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2235 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2236 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2237 }
2238
15c3b696
MC		 2239 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2240}
2241
ffbcfed4
MC		 2242/* tp->lock is held. */
2243static int tg3_nvram_lock(struct tg3 *tp)
2244{
2245 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2246 int i;
2247
2248 if (tp->nvram_lock_cnt == 0) {
2249 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2250 for (i = 0; i < 8000; i++) {
2251 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2252 break;
2253 udelay(20);
2254 }
2255 if (i == 8000) {
2256 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2257 return -ENODEV;
2258 }
2259 }
2260 tp->nvram_lock_cnt++;
2261 }
2262 return 0;
2263}
2264
2265/* tp->lock is held. */
2266static void tg3_nvram_unlock(struct tg3 *tp)
2267{
2268 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2269 if (tp->nvram_lock_cnt > 0)
2270 tp->nvram_lock_cnt--;
2271 if (tp->nvram_lock_cnt == 0)
2272 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2273 }
2274}
2275
2276/* tp->lock is held. */
2277static void tg3_enable_nvram_access(struct tg3 *tp)
2278{
2279 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2280 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2281 u32 nvaccess = tr32(NVRAM_ACCESS);
2282
2283 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2284 }
2285}
2286
2287/* tp->lock is held. */
2288static void tg3_disable_nvram_access(struct tg3 *tp)
2289{
2290 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2291 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2292 u32 nvaccess = tr32(NVRAM_ACCESS);
2293
2294 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2295 }
2296}
2297
2298static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2299 u32 offset, u32 *val)
2300{
2301 u32 tmp;
2302 int i;
2303
2304 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2305 return -EINVAL;
2306
2307 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2308 EEPROM_ADDR_DEVID_MASK |
2309 EEPROM_ADDR_READ);
2310 tw32(GRC_EEPROM_ADDR,
2311 tmp |
2312 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2313 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2314 EEPROM_ADDR_ADDR_MASK) |
2315 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2316
2317 for (i = 0; i < 1000; i++) {
2318 tmp = tr32(GRC_EEPROM_ADDR);
2319
2320 if (tmp & EEPROM_ADDR_COMPLETE)
2321 break;
2322 msleep(1);
2323 }
2324 if (!(tmp & EEPROM_ADDR_COMPLETE))
2325 return -EBUSY;
2326
62cedd11
MC		 2327 tmp = tr32(GRC_EEPROM_DATA);
2328
2329 /*
2330 * The data will always be opposite the native endian
2331 * format. Perform a blind byteswap to compensate.
2332 */
2333 *val = swab32(tmp);
2334
ffbcfed4
MC		 2335 return 0;
2336}
2337
2338#define NVRAM_CMD_TIMEOUT 10000
2339
2340static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2341{
2342 int i;
2343
2344 tw32(NVRAM_CMD, nvram_cmd);
2345 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2346 udelay(10);
2347 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2348 udelay(10);
2349 break;
2350 }
2351 }
2352
2353 if (i == NVRAM_CMD_TIMEOUT)
2354 return -EBUSY;
2355
2356 return 0;
2357}
2358
2359static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2360{
2361 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365 (tp->nvram_jedecnum == JEDEC_ATMEL))
2366
2367 addr = ((addr / tp->nvram_pagesize) <<
2368 ATMEL_AT45DB0X1B_PAGE_POS) +
2369 (addr % tp->nvram_pagesize);
2370
2371 return addr;
2372}
2373
2374static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2375{
2376 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2377 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2378 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2379 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2380 (tp->nvram_jedecnum == JEDEC_ATMEL))
2381
2382 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2383 tp->nvram_pagesize) +
2384 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2385
2386 return addr;
2387}
2388
e4f34110
MC		 2389/* NOTE: Data read in from NVRAM is byteswapped according to
2390 * the byteswapping settings for all other register accesses.
2391 * tg3 devices are BE devices, so on a BE machine, the data
2392 * returned will be exactly as it is seen in NVRAM. On a LE
2393 * machine, the 32-bit value will be byteswapped.
2394 */
ffbcfed4
MC		 2395static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2396{
2397 int ret;
2398
2399 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2400 return tg3_nvram_read_using_eeprom(tp, offset, val);
2401
2402 offset = tg3_nvram_phys_addr(tp, offset);
2403
2404 if (offset > NVRAM_ADDR_MSK)
2405 return -EINVAL;
2406
2407 ret = tg3_nvram_lock(tp);
2408 if (ret)
2409 return ret;
2410
2411 tg3_enable_nvram_access(tp);
2412
2413 tw32(NVRAM_ADDR, offset);
2414 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2415 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2416
2417 if (ret == 0)
e4f34110 2418 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2419
2420 tg3_disable_nvram_access(tp);
2421
2422 tg3_nvram_unlock(tp);
2423
2424 return ret;
2425}
2426
a9dc529d
MC		 2427/* Ensures NVRAM data is in bytestream format. */
2428static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2429{
2430 u32 v;
a9dc529d 2431 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2432 if (!res)
a9dc529d 2433 *val = cpu_to_be32(v);
ffbcfed4
MC		 2434 return res;
2435}
2436
3f007891
MC		 2437/* tp->lock is held. */
2438static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2439{
2440 u32 addr_high, addr_low;
2441 int i;
2442
2443 addr_high = ((tp->dev->dev_addr[0] << 8) |
2444 tp->dev->dev_addr[1]);
2445 addr_low = ((tp->dev->dev_addr[2] << 24) |
2446 (tp->dev->dev_addr[3] << 16) |
2447 (tp->dev->dev_addr[4] << 8) |
2448 (tp->dev->dev_addr[5] << 0));
2449 for (i = 0; i < 4; i++) {
2450 if (i == 1 && skip_mac_1)
2451 continue;
2452 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2453 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2454 }
2455
2456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458 for (i = 0; i < 12; i++) {
2459 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2460 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2461 }
2462 }
2463
2464 addr_high = (tp->dev->dev_addr[0] +
2465 tp->dev->dev_addr[1] +
2466 tp->dev->dev_addr[2] +
2467 tp->dev->dev_addr[3] +
2468 tp->dev->dev_addr[4] +
2469 tp->dev->dev_addr[5]) &
2470 TX_BACKOFF_SEED_MASK;
2471 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2472}
2473
bc1c7567 2474static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2475{
2476 u32 misc_host_ctrl;
0a459aac 2477 bool device_should_wake, do_low_power;
1da177e4
LT		 2478
2479 /* Make sure register accesses (indirect or otherwise)
2480 * will function correctly.
2481 */
2482 pci_write_config_dword(tp->pdev,
2483 TG3PCI_MISC_HOST_CTRL,
2484 tp->misc_host_ctrl);
2485
1da177e4 2486 switch (state) {
bc1c7567 2487 case PCI_D0:
12dac075
RW		 2488 pci_enable_wake(tp->pdev, state, false);
2489 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2490
9d26e213
MC		 2491 /* Switch out of Vaux if it is a NIC */
2492 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2493 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2494
2495 return 0;
2496
bc1c7567 2497 case PCI_D1:
bc1c7567 2498 case PCI_D2:
bc1c7567 2499 case PCI_D3hot:
1da177e4
LT		 2500 break;
2501
2502 default:
12dac075
RW		 2503 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2504 tp->dev->name, state);
1da177e4 2505 return -EINVAL;
855e1111 2506 }
5e7dfd0f
MC		 2507
2508 /* Restore the CLKREQ setting. */
2509 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2510 u16 lnkctl;
2511
2512 pci_read_config_word(tp->pdev,
2513 tp->pcie_cap + PCI_EXP_LNKCTL,
2514 &lnkctl);
2515 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2516 pci_write_config_word(tp->pdev,
2517 tp->pcie_cap + PCI_EXP_LNKCTL,
2518 lnkctl);
2519 }
2520
1da177e4
LT		 2521 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2522 tw32(TG3PCI_MISC_HOST_CTRL,
2523 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2524
05ac4cb7
MC		 2525 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2526 device_may_wakeup(&tp->pdev->dev) &&
2527 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2528
dd477003 2529 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2530 do_low_power = false;
b02fd9e3
MC		 2531 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2532 !tp->link_config.phy_is_low_power) {
2533 struct phy_device *phydev;
0a459aac 2534 u32 phyid, advertising;
b02fd9e3 2535
3f0e3ad7 2536 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2537
2538 tp->link_config.phy_is_low_power = 1;
2539
2540 tp->link_config.orig_speed = phydev->speed;
2541 tp->link_config.orig_duplex = phydev->duplex;
2542 tp->link_config.orig_autoneg = phydev->autoneg;
2543 tp->link_config.orig_advertising = phydev->advertising;
2544
2545 advertising = ADVERTISED_TP |
2546 ADVERTISED_Pause |
2547 ADVERTISED_Autoneg |
2548 ADVERTISED_10baseT_Half;
2549
2550 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2551 device_should_wake) {
b02fd9e3
MC		 2552 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2553 advertising |=
2554 ADVERTISED_100baseT_Half |
2555 ADVERTISED_100baseT_Full |
2556 ADVERTISED_10baseT_Full;
2557 else
2558 advertising |= ADVERTISED_10baseT_Full;
2559 }
2560
2561 phydev->advertising = advertising;
2562
2563 phy_start_aneg(phydev);
0a459aac
MC		 2564
2565 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2566 if (phyid != TG3_PHY_ID_BCMAC131) {
2567 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2568 if (phyid == TG3_PHY_OUI_1 ||
2569 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2570 phyid == TG3_PHY_OUI_3)
2571 do_low_power = true;
2572 }
b02fd9e3 2573 }
dd477003 2574 } else {
2023276e 2575 do_low_power = true;
0a459aac 2576
dd477003
MC		 2577 if (tp->link_config.phy_is_low_power == 0) {
2578 tp->link_config.phy_is_low_power = 1;
2579 tp->link_config.orig_speed = tp->link_config.speed;
2580 tp->link_config.orig_duplex = tp->link_config.duplex;
2581 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2582 }
1da177e4 2583
dd477003
MC		 2584 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2585 tp->link_config.speed = SPEED_10;
2586 tp->link_config.duplex = DUPLEX_HALF;
2587 tp->link_config.autoneg = AUTONEG_ENABLE;
2588 tg3_setup_phy(tp, 0);
2589 }
1da177e4
LT		 2590 }
2591
b5d3772c
MC		 2592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2593 u32 val;
2594
2595 val = tr32(GRC_VCPU_EXT_CTRL);
2596 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2597 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2598 int i;
2599 u32 val;
2600
2601 for (i = 0; i < 200; i++) {
2602 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2603 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2604 break;
2605 msleep(1);
2606 }
2607 }
a85feb8c
GZ		 2608 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2609 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2610 WOL_DRV_STATE_SHUTDOWN |
2611 WOL_DRV_WOL |
2612 WOL_SET_MAGIC_PKT);
6921d201 2613
05ac4cb7 2614 if (device_should_wake) {
1da177e4
LT		 2615 u32 mac_mode;
2616
2617 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2618 if (do_low_power) {
dd477003
MC		 2619 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2620 udelay(40);
2621 }
1da177e4 2622
3f7045c1
MC		 2623 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2624 mac_mode = MAC_MODE_PORT_MODE_GMII;
2625 else
2626 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2627
e8f3f6ca
MC		 2628 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2629 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2630 ASIC_REV_5700) {
2631 u32 speed = (tp->tg3_flags &
2632 TG3_FLAG_WOL_SPEED_100MB) ?
2633 SPEED_100 : SPEED_10;
2634 if (tg3_5700_link_polarity(tp, speed))
2635 mac_mode |= MAC_MODE_LINK_POLARITY;
2636 else
2637 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2638 }
1da177e4
LT		 2639 } else {
2640 mac_mode = MAC_MODE_PORT_MODE_TBI;
2641 }
2642
cbf46853 2643 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2644 tw32(MAC_LED_CTRL, tp->led_ctrl);
2645
05ac4cb7
MC		 2646 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2647 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2648 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2649 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2650 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2651 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2652
3bda1258
MC		 2653 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2654 mac_mode |= tp->mac_mode &
2655 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2656 if (mac_mode & MAC_MODE_APE_TX_EN)
2657 mac_mode |= MAC_MODE_TDE_ENABLE;
2658 }
2659
1da177e4
LT		 2660 tw32_f(MAC_MODE, mac_mode);
2661 udelay(100);
2662
2663 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2664 udelay(10);
2665 }
2666
2667 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2668 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2670 u32 base_val;
2671
2672 base_val = tp->pci_clock_ctrl;
2673 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2674 CLOCK_CTRL_TXCLK_DISABLE);
2675
b401e9e2
MC		 2676 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2677 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2678 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2679 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2680 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2681 /* do nothing */
85e94ced 2682 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2683 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2684 u32 newbits1, newbits2;
2685
2686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2688 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2689 CLOCK_CTRL_TXCLK_DISABLE |
2690 CLOCK_CTRL_ALTCLK);
2691 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2692 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2693 newbits1 = CLOCK_CTRL_625_CORE;
2694 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2695 } else {
2696 newbits1 = CLOCK_CTRL_ALTCLK;
2697 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2698 }
2699
b401e9e2
MC		 2700 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2701 40);
1da177e4 2702
b401e9e2
MC		 2703 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2704 40);
1da177e4
LT		 2705
2706 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2707 u32 newbits3;
2708
2709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2710 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2711 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2712 CLOCK_CTRL_TXCLK_DISABLE |
2713 CLOCK_CTRL_44MHZ_CORE);
2714 } else {
2715 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2716 }
2717
b401e9e2
MC		 2718 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2719 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2720 }
2721 }
2722
05ac4cb7 2723 if (!(device_should_wake) &&
22435849 2724 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2725 tg3_power_down_phy(tp, do_low_power);
6921d201 2726
1da177e4
LT		 2727 tg3_frob_aux_power(tp);
2728
2729 /* Workaround for unstable PLL clock */
2730 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2731 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2732 u32 val = tr32(0x7d00);
2733
2734 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2735 tw32(0x7d00, val);
6921d201 2736 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2737 int err;
2738
2739 err = tg3_nvram_lock(tp);
1da177e4 2740 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2741 if (!err)
2742 tg3_nvram_unlock(tp);
6921d201 2743 }
1da177e4
LT		 2744 }
2745
bbadf503
MC		 2746 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2747
05ac4cb7 2748 if (device_should_wake)
12dac075
RW		 2749 pci_enable_wake(tp->pdev, state, true);
2750
1da177e4 2751 /* Finally, set the new power state. */
12dac075 2752 pci_set_power_state(tp->pdev, state);
1da177e4 2753
1da177e4
LT		 2754 return 0;
2755}
2756
1da177e4
LT		 2757static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2758{
2759 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2760 case MII_TG3_AUX_STAT_10HALF:
2761 *speed = SPEED_10;
2762 *duplex = DUPLEX_HALF;
2763 break;
2764
2765 case MII_TG3_AUX_STAT_10FULL:
2766 *speed = SPEED_10;
2767 *duplex = DUPLEX_FULL;
2768 break;
2769
2770 case MII_TG3_AUX_STAT_100HALF:
2771 *speed = SPEED_100;
2772 *duplex = DUPLEX_HALF;
2773 break;
2774
2775 case MII_TG3_AUX_STAT_100FULL:
2776 *speed = SPEED_100;
2777 *duplex = DUPLEX_FULL;
2778 break;
2779
2780 case MII_TG3_AUX_STAT_1000HALF:
2781 *speed = SPEED_1000;
2782 *duplex = DUPLEX_HALF;
2783 break;
2784
2785 case MII_TG3_AUX_STAT_1000FULL:
2786 *speed = SPEED_1000;
2787 *duplex = DUPLEX_FULL;
2788 break;
2789
2790 default:
7f97a4bd 2791 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2792 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2793 SPEED_10;
2794 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2795 DUPLEX_HALF;
2796 break;
2797 }
1da177e4
LT		 2798 *speed = SPEED_INVALID;
2799 *duplex = DUPLEX_INVALID;
2800 break;
855e1111 2801 }
1da177e4
LT		 2802}
2803
2804static void tg3_phy_copper_begin(struct tg3 *tp)
2805{
2806 u32 new_adv;
2807 int i;
2808
2809 if (tp->link_config.phy_is_low_power) {
2810 /* Entering low power mode. Disable gigabit and
2811 * 100baseT advertisements.
2812 */
2813 tg3_writephy(tp, MII_TG3_CTRL, 0);
2814
2815 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2816 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2817 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2818 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2819
2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2822 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2823 tp->link_config.advertising &=
2824 ~(ADVERTISED_1000baseT_Half |
2825 ADVERTISED_1000baseT_Full);
2826
ba4d07a8 2827 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2828 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2829 new_adv |= ADVERTISE_10HALF;
2830 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2831 new_adv |= ADVERTISE_10FULL;
2832 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2833 new_adv |= ADVERTISE_100HALF;
2834 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2835 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2836
2837 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2838
1da177e4
LT		 2839 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840
2841 if (tp->link_config.advertising &
2842 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2843 new_adv = 0;
2844 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2845 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2846 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2847 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2848 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2849 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2850 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2851 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2852 MII_TG3_CTRL_ENABLE_AS_MASTER);
2853 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2854 } else {
2855 tg3_writephy(tp, MII_TG3_CTRL, 0);
2856 }
2857 } else {
ba4d07a8
MC		 2858 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2859 new_adv |= ADVERTISE_CSMA;
2860
1da177e4
LT		 2861 /* Asking for a specific link mode. */
2862 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2864
2865 if (tp->link_config.duplex == DUPLEX_FULL)
2866 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2867 else
2868 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2869 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2870 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2871 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2872 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2873 } else {
1da177e4
LT		 2874 if (tp->link_config.speed == SPEED_100) {
2875 if (tp->link_config.duplex == DUPLEX_FULL)
2876 new_adv |= ADVERTISE_100FULL;
2877 else
2878 new_adv |= ADVERTISE_100HALF;
2879 } else {
2880 if (tp->link_config.duplex == DUPLEX_FULL)
2881 new_adv |= ADVERTISE_10FULL;
2882 else
2883 new_adv |= ADVERTISE_10HALF;
2884 }
2885 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2886
2887 new_adv = 0;
1da177e4 2888 }
ba4d07a8
MC		 2889
2890 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2891 }
2892
2893 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2894 tp->link_config.speed != SPEED_INVALID) {
2895 u32 bmcr, orig_bmcr;
2896
2897 tp->link_config.active_speed = tp->link_config.speed;
2898 tp->link_config.active_duplex = tp->link_config.duplex;
2899
2900 bmcr = 0;
2901 switch (tp->link_config.speed) {
2902 default:
2903 case SPEED_10:
2904 break;
2905
2906 case SPEED_100:
2907 bmcr |= BMCR_SPEED100;
2908 break;
2909
2910 case SPEED_1000:
2911 bmcr |= TG3_BMCR_SPEED1000;
2912 break;
855e1111 2913 }
1da177e4
LT		 2914
2915 if (tp->link_config.duplex == DUPLEX_FULL)
2916 bmcr |= BMCR_FULLDPLX;
2917
2918 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2919 (bmcr != orig_bmcr)) {
2920 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2921 for (i = 0; i < 1500; i++) {
2922 u32 tmp;
2923
2924 udelay(10);
2925 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2926 tg3_readphy(tp, MII_BMSR, &tmp))
2927 continue;
2928 if (!(tmp & BMSR_LSTATUS)) {
2929 udelay(40);
2930 break;
2931 }
2932 }
2933 tg3_writephy(tp, MII_BMCR, bmcr);
2934 udelay(40);
2935 }
2936 } else {
2937 tg3_writephy(tp, MII_BMCR,
2938 BMCR_ANENABLE | BMCR_ANRESTART);
2939 }
2940}
2941
2942static int tg3_init_5401phy_dsp(struct tg3 *tp)
2943{
2944 int err;
2945
2946 /* Turn off tap power management. */
2947 /* Set Extended packet length bit */
2948 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2949
2950 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2951 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2952
2953 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2954 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2955
2956 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2957 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2958
2959 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2960 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2961
2962 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2963 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2964
2965 udelay(40);
2966
2967 return err;
2968}
2969
3600d918 2970static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2971{
3600d918
MC		 2972 u32 adv_reg, all_mask = 0;
2973
2974 if (mask & ADVERTISED_10baseT_Half)
2975 all_mask |= ADVERTISE_10HALF;
2976 if (mask & ADVERTISED_10baseT_Full)
2977 all_mask |= ADVERTISE_10FULL;
2978 if (mask & ADVERTISED_100baseT_Half)
2979 all_mask |= ADVERTISE_100HALF;
2980 if (mask & ADVERTISED_100baseT_Full)
2981 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2982
2983 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2984 return 0;
2985
1da177e4
LT		 2986 if ((adv_reg & all_mask) != all_mask)
2987 return 0;
2988 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2989 u32 tg3_ctrl;
2990
3600d918
MC		 2991 all_mask = 0;
2992 if (mask & ADVERTISED_1000baseT_Half)
2993 all_mask |= ADVERTISE_1000HALF;
2994 if (mask & ADVERTISED_1000baseT_Full)
2995 all_mask |= ADVERTISE_1000FULL;
2996
1da177e4
LT		 2997 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2998 return 0;
2999
1da177e4
LT		 3000 if ((tg3_ctrl & all_mask) != all_mask)
3001 return 0;
3002 }
3003 return 1;
3004}
3005
ef167e27
MC		 3006static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3007{
3008 u32 curadv, reqadv;
3009
3010 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3011 return 1;
3012
3013 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3014 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3015
3016 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3017 if (curadv != reqadv)
3018 return 0;
3019
3020 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3021 tg3_readphy(tp, MII_LPA, rmtadv);
3022 } else {
3023 /* Reprogram the advertisement register, even if it
3024 * does not affect the current link. If the link
3025 * gets renegotiated in the future, we can save an
3026 * additional renegotiation cycle by advertising
3027 * it correctly in the first place.
3028 */
3029 if (curadv != reqadv) {
3030 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3031 ADVERTISE_PAUSE_ASYM);
3032 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3033 }
3034 }
3035
3036 return 1;
3037}
3038
1da177e4
LT		 3039static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3040{
3041 int current_link_up;
3042 u32 bmsr, dummy;
ef167e27 3043 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3044 u16 current_speed;
3045 u8 current_duplex;
3046 int i, err;
3047
3048 tw32(MAC_EVENT, 0);
3049
3050 tw32_f(MAC_STATUS,
3051 (MAC_STATUS_SYNC_CHANGED |
3052 MAC_STATUS_CFG_CHANGED |
3053 MAC_STATUS_MI_COMPLETION |
3054 MAC_STATUS_LNKSTATE_CHANGED));
3055 udelay(40);
3056
8ef21428
MC		 3057 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3058 tw32_f(MAC_MI_MODE,
3059 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3060 udelay(80);
3061 }
1da177e4
LT		 3062
3063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3064
3065 /* Some third-party PHYs need to be reset on link going
3066 * down.
3067 */
3068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3071 netif_carrier_ok(tp->dev)) {
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3074 !(bmsr & BMSR_LSTATUS))
3075 force_reset = 1;
3076 }
3077 if (force_reset)
3078 tg3_phy_reset(tp);
3079
3080 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3081 tg3_readphy(tp, MII_BMSR, &bmsr);
3082 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3083 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3084 bmsr = 0;
3085
3086 if (!(bmsr & BMSR_LSTATUS)) {
3087 err = tg3_init_5401phy_dsp(tp);
3088 if (err)
3089 return err;
3090
3091 tg3_readphy(tp, MII_BMSR, &bmsr);
3092 for (i = 0; i < 1000; i++) {
3093 udelay(10);
3094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095 (bmsr & BMSR_LSTATUS)) {
3096 udelay(40);
3097 break;
3098 }
3099 }
3100
3101 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3102 !(bmsr & BMSR_LSTATUS) &&
3103 tp->link_config.active_speed == SPEED_1000) {
3104 err = tg3_phy_reset(tp);
3105 if (!err)
3106 err = tg3_init_5401phy_dsp(tp);
3107 if (err)
3108 return err;
3109 }
3110 }
3111 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3112 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3113 /* 5701 {A0,B0} CRC bug workaround */
3114 tg3_writephy(tp, 0x15, 0x0a75);
3115 tg3_writephy(tp, 0x1c, 0x8c68);
3116 tg3_writephy(tp, 0x1c, 0x8d68);
3117 tg3_writephy(tp, 0x1c, 0x8c68);
3118 }
3119
3120 /* Clear pending interrupts... */
3121 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3123
3124 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3125 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3126 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3127 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3128
3129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3131 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3132 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3133 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3134 else
3135 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3136 }
3137
3138 current_link_up = 0;
3139 current_speed = SPEED_INVALID;
3140 current_duplex = DUPLEX_INVALID;
3141
3142 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3143 u32 val;
3144
3145 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3146 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3147 if (!(val & (1 << 10))) {
3148 val |= (1 << 10);
3149 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3150 goto relink;
3151 }
3152 }
3153
3154 bmsr = 0;
3155 for (i = 0; i < 100; i++) {
3156 tg3_readphy(tp, MII_BMSR, &bmsr);
3157 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3158 (bmsr & BMSR_LSTATUS))
3159 break;
3160 udelay(40);
3161 }
3162
3163 if (bmsr & BMSR_LSTATUS) {
3164 u32 aux_stat, bmcr;
3165
3166 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3167 for (i = 0; i < 2000; i++) {
3168 udelay(10);
3169 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3170 aux_stat)
3171 break;
3172 }
3173
3174 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3175 &current_speed,
3176 &current_duplex);
3177
3178 bmcr = 0;
3179 for (i = 0; i < 200; i++) {
3180 tg3_readphy(tp, MII_BMCR, &bmcr);
3181 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3182 continue;
3183 if (bmcr && bmcr != 0x7fff)
3184 break;
3185 udelay(10);
3186 }
3187
ef167e27
MC		 3188 lcl_adv = 0;
3189 rmt_adv = 0;
1da177e4 3190
ef167e27
MC		 3191 tp->link_config.active_speed = current_speed;
3192 tp->link_config.active_duplex = current_duplex;
3193
3194 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3195 if ((bmcr & BMCR_ANENABLE) &&
3196 tg3_copper_is_advertising_all(tp,
3197 tp->link_config.advertising)) {
3198 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3199 &rmt_adv))
3200 current_link_up = 1;
1da177e4
LT		 3201 }
3202 } else {
3203 if (!(bmcr & BMCR_ANENABLE) &&
3204 tp->link_config.speed == current_speed &&
ef167e27
MC		 3205 tp->link_config.duplex == current_duplex &&
3206 tp->link_config.flowctrl ==
3207 tp->link_config.active_flowctrl) {
1da177e4 3208 current_link_up = 1;
1da177e4
LT		 3209 }
3210 }
3211
ef167e27
MC		 3212 if (current_link_up == 1 &&
3213 tp->link_config.active_duplex == DUPLEX_FULL)
3214 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3215 }
3216
1da177e4 3217relink:
6921d201 3218 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3219 u32 tmp;
3220
3221 tg3_phy_copper_begin(tp);
3222
3223 tg3_readphy(tp, MII_BMSR, &tmp);
3224 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3225 (tmp & BMSR_LSTATUS))
3226 current_link_up = 1;
3227 }
3228
3229 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3230 if (current_link_up == 1) {
3231 if (tp->link_config.active_speed == SPEED_100 ||
3232 tp->link_config.active_speed == SPEED_10)
3233 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3234 else
3235 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3236 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3237 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3238 else
1da177e4
LT		 3239 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3240
3241 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3242 if (tp->link_config.active_duplex == DUPLEX_HALF)
3243 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3244
1da177e4 3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3246 if (current_link_up == 1 &&
3247 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3248 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3249 else
3250 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3251 }
3252
3253 /* ??? Without this setting Netgear GA302T PHY does not
3254 * ??? send/receive packets...
3255 */
3256 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3257 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3258 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3259 tw32_f(MAC_MI_MODE, tp->mi_mode);
3260 udelay(80);
3261 }
3262
3263 tw32_f(MAC_MODE, tp->mac_mode);
3264 udelay(40);
3265
3266 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3267 /* Polled via timer. */
3268 tw32_f(MAC_EVENT, 0);
3269 } else {
3270 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3271 }
3272 udelay(40);
3273
3274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3275 current_link_up == 1 &&
3276 tp->link_config.active_speed == SPEED_1000 &&
3277 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3278 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3279 udelay(120);
3280 tw32_f(MAC_STATUS,
3281 (MAC_STATUS_SYNC_CHANGED |
3282 MAC_STATUS_CFG_CHANGED));
3283 udelay(40);
3284 tg3_write_mem(tp,
3285 NIC_SRAM_FIRMWARE_MBOX,
3286 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3287 }
3288
5e7dfd0f
MC		 3289 /* Prevent send BD corruption. */
3290 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3291 u16 oldlnkctl, newlnkctl;
3292
3293 pci_read_config_word(tp->pdev,
3294 tp->pcie_cap + PCI_EXP_LNKCTL,
3295 &oldlnkctl);
3296 if (tp->link_config.active_speed == SPEED_100 ||
3297 tp->link_config.active_speed == SPEED_10)
3298 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3299 else
3300 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3301 if (newlnkctl != oldlnkctl)
3302 pci_write_config_word(tp->pdev,
3303 tp->pcie_cap + PCI_EXP_LNKCTL,
3304 newlnkctl);
3305 }
3306
1da177e4
LT		 3307 if (current_link_up != netif_carrier_ok(tp->dev)) {
3308 if (current_link_up)
3309 netif_carrier_on(tp->dev);
3310 else
3311 netif_carrier_off(tp->dev);
3312 tg3_link_report(tp);
3313 }
3314
3315 return 0;
3316}
3317
3318struct tg3_fiber_aneginfo {
3319 int state;
3320#define ANEG_STATE_UNKNOWN 0
3321#define ANEG_STATE_AN_ENABLE 1
3322#define ANEG_STATE_RESTART_INIT 2
3323#define ANEG_STATE_RESTART 3
3324#define ANEG_STATE_DISABLE_LINK_OK 4
3325#define ANEG_STATE_ABILITY_DETECT_INIT 5
3326#define ANEG_STATE_ABILITY_DETECT 6
3327#define ANEG_STATE_ACK_DETECT_INIT 7
3328#define ANEG_STATE_ACK_DETECT 8
3329#define ANEG_STATE_COMPLETE_ACK_INIT 9
3330#define ANEG_STATE_COMPLETE_ACK 10
3331#define ANEG_STATE_IDLE_DETECT_INIT 11
3332#define ANEG_STATE_IDLE_DETECT 12
3333#define ANEG_STATE_LINK_OK 13
3334#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3335#define ANEG_STATE_NEXT_PAGE_WAIT 15
3336
3337 u32 flags;
3338#define MR_AN_ENABLE 0x00000001
3339#define MR_RESTART_AN 0x00000002
3340#define MR_AN_COMPLETE 0x00000004
3341#define MR_PAGE_RX 0x00000008
3342#define MR_NP_LOADED 0x00000010
3343#define MR_TOGGLE_TX 0x00000020
3344#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3345#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3346#define MR_LP_ADV_SYM_PAUSE 0x00000100
3347#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3348#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3349#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3350#define MR_LP_ADV_NEXT_PAGE 0x00001000
3351#define MR_TOGGLE_RX 0x00002000
3352#define MR_NP_RX 0x00004000
3353
3354#define MR_LINK_OK 0x80000000
3355
3356 unsigned long link_time, cur_time;
3357
3358 u32 ability_match_cfg;
3359 int ability_match_count;
3360
3361 char ability_match, idle_match, ack_match;
3362
3363 u32 txconfig, rxconfig;
3364#define ANEG_CFG_NP 0x00000080
3365#define ANEG_CFG_ACK 0x00000040
3366#define ANEG_CFG_RF2 0x00000020
3367#define ANEG_CFG_RF1 0x00000010
3368#define ANEG_CFG_PS2 0x00000001
3369#define ANEG_CFG_PS1 0x00008000
3370#define ANEG_CFG_HD 0x00004000
3371#define ANEG_CFG_FD 0x00002000
3372#define ANEG_CFG_INVAL 0x00001f06
3373
3374};
3375#define ANEG_OK 0
3376#define ANEG_DONE 1
3377#define ANEG_TIMER_ENAB 2
3378#define ANEG_FAILED -1
3379
3380#define ANEG_STATE_SETTLE_TIME 10000
3381
3382static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3383 struct tg3_fiber_aneginfo *ap)
3384{
5be73b47 3385 u16 flowctrl;
1da177e4
LT		 3386 unsigned long delta;
3387 u32 rx_cfg_reg;
3388 int ret;
3389
3390 if (ap->state == ANEG_STATE_UNKNOWN) {
3391 ap->rxconfig = 0;
3392 ap->link_time = 0;
3393 ap->cur_time = 0;
3394 ap->ability_match_cfg = 0;
3395 ap->ability_match_count = 0;
3396 ap->ability_match = 0;
3397 ap->idle_match = 0;
3398 ap->ack_match = 0;
3399 }
3400 ap->cur_time++;
3401
3402 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3403 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3404
3405 if (rx_cfg_reg != ap->ability_match_cfg) {
3406 ap->ability_match_cfg = rx_cfg_reg;
3407 ap->ability_match = 0;
3408 ap->ability_match_count = 0;
3409 } else {
3410 if (++ap->ability_match_count > 1) {
3411 ap->ability_match = 1;
3412 ap->ability_match_cfg = rx_cfg_reg;
3413 }
3414 }
3415 if (rx_cfg_reg & ANEG_CFG_ACK)
3416 ap->ack_match = 1;
3417 else
3418 ap->ack_match = 0;
3419
3420 ap->idle_match = 0;
3421 } else {
3422 ap->idle_match = 1;
3423 ap->ability_match_cfg = 0;
3424 ap->ability_match_count = 0;
3425 ap->ability_match = 0;
3426 ap->ack_match = 0;
3427
3428 rx_cfg_reg = 0;
3429 }
3430
3431 ap->rxconfig = rx_cfg_reg;
3432 ret = ANEG_OK;
3433
3434 switch(ap->state) {
3435 case ANEG_STATE_UNKNOWN:
3436 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3437 ap->state = ANEG_STATE_AN_ENABLE;
3438
3439 /* fallthru */
3440 case ANEG_STATE_AN_ENABLE:
3441 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3442 if (ap->flags & MR_AN_ENABLE) {
3443 ap->link_time = 0;
3444 ap->cur_time = 0;
3445 ap->ability_match_cfg = 0;
3446 ap->ability_match_count = 0;
3447 ap->ability_match = 0;
3448 ap->idle_match = 0;
3449 ap->ack_match = 0;
3450
3451 ap->state = ANEG_STATE_RESTART_INIT;
3452 } else {
3453 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3454 }
3455 break;
3456
3457 case ANEG_STATE_RESTART_INIT:
3458 ap->link_time = ap->cur_time;
3459 ap->flags &= ~(MR_NP_LOADED);
3460 ap->txconfig = 0;
3461 tw32(MAC_TX_AUTO_NEG, 0);
3462 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3463 tw32_f(MAC_MODE, tp->mac_mode);
3464 udelay(40);
3465
3466 ret = ANEG_TIMER_ENAB;
3467 ap->state = ANEG_STATE_RESTART;
3468
3469 /* fallthru */
3470 case ANEG_STATE_RESTART:
3471 delta = ap->cur_time - ap->link_time;
3472 if (delta > ANEG_STATE_SETTLE_TIME) {
3473 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3474 } else {
3475 ret = ANEG_TIMER_ENAB;
3476 }
3477 break;
3478
3479 case ANEG_STATE_DISABLE_LINK_OK:
3480 ret = ANEG_DONE;
3481 break;
3482
3483 case ANEG_STATE_ABILITY_DETECT_INIT:
3484 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3485 ap->txconfig = ANEG_CFG_FD;
3486 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3487 if (flowctrl & ADVERTISE_1000XPAUSE)
3488 ap->txconfig |= ANEG_CFG_PS1;
3489 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3490 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3491 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3492 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3493 tw32_f(MAC_MODE, tp->mac_mode);
3494 udelay(40);
3495
3496 ap->state = ANEG_STATE_ABILITY_DETECT;
3497 break;
3498
3499 case ANEG_STATE_ABILITY_DETECT:
3500 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3501 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3502 }
3503 break;
3504
3505 case ANEG_STATE_ACK_DETECT_INIT:
3506 ap->txconfig |= ANEG_CFG_ACK;
3507 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3508 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3509 tw32_f(MAC_MODE, tp->mac_mode);
3510 udelay(40);
3511
3512 ap->state = ANEG_STATE_ACK_DETECT;
3513
3514 /* fallthru */
3515 case ANEG_STATE_ACK_DETECT:
3516 if (ap->ack_match != 0) {
3517 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3518 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3519 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3520 } else {
3521 ap->state = ANEG_STATE_AN_ENABLE;
3522 }
3523 } else if (ap->ability_match != 0 &&
3524 ap->rxconfig == 0) {
3525 ap->state = ANEG_STATE_AN_ENABLE;
3526 }
3527 break;
3528
3529 case ANEG_STATE_COMPLETE_ACK_INIT:
3530 if (ap->rxconfig & ANEG_CFG_INVAL) {
3531 ret = ANEG_FAILED;
3532 break;
3533 }
3534 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3535 MR_LP_ADV_HALF_DUPLEX |
3536 MR_LP_ADV_SYM_PAUSE |
3537 MR_LP_ADV_ASYM_PAUSE |
3538 MR_LP_ADV_REMOTE_FAULT1 |
3539 MR_LP_ADV_REMOTE_FAULT2 |
3540 MR_LP_ADV_NEXT_PAGE |
3541 MR_TOGGLE_RX |
3542 MR_NP_RX);
3543 if (ap->rxconfig & ANEG_CFG_FD)
3544 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3545 if (ap->rxconfig & ANEG_CFG_HD)
3546 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3547 if (ap->rxconfig & ANEG_CFG_PS1)
3548 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3549 if (ap->rxconfig & ANEG_CFG_PS2)
3550 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3551 if (ap->rxconfig & ANEG_CFG_RF1)
3552 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3553 if (ap->rxconfig & ANEG_CFG_RF2)
3554 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3555 if (ap->rxconfig & ANEG_CFG_NP)
3556 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3557
3558 ap->link_time = ap->cur_time;
3559
3560 ap->flags ^= (MR_TOGGLE_TX);
3561 if (ap->rxconfig & 0x0008)
3562 ap->flags |= MR_TOGGLE_RX;
3563 if (ap->rxconfig & ANEG_CFG_NP)
3564 ap->flags |= MR_NP_RX;
3565 ap->flags |= MR_PAGE_RX;
3566
3567 ap->state = ANEG_STATE_COMPLETE_ACK;
3568 ret = ANEG_TIMER_ENAB;
3569 break;
3570
3571 case ANEG_STATE_COMPLETE_ACK:
3572 if (ap->ability_match != 0 &&
3573 ap->rxconfig == 0) {
3574 ap->state = ANEG_STATE_AN_ENABLE;
3575 break;
3576 }
3577 delta = ap->cur_time - ap->link_time;
3578 if (delta > ANEG_STATE_SETTLE_TIME) {
3579 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3580 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3581 } else {
3582 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3583 !(ap->flags & MR_NP_RX)) {
3584 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3585 } else {
3586 ret = ANEG_FAILED;
3587 }
3588 }
3589 }
3590 break;
3591
3592 case ANEG_STATE_IDLE_DETECT_INIT:
3593 ap->link_time = ap->cur_time;
3594 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3595 tw32_f(MAC_MODE, tp->mac_mode);
3596 udelay(40);
3597
3598 ap->state = ANEG_STATE_IDLE_DETECT;
3599 ret = ANEG_TIMER_ENAB;
3600 break;
3601
3602 case ANEG_STATE_IDLE_DETECT:
3603 if (ap->ability_match != 0 &&
3604 ap->rxconfig == 0) {
3605 ap->state = ANEG_STATE_AN_ENABLE;
3606 break;
3607 }
3608 delta = ap->cur_time - ap->link_time;
3609 if (delta > ANEG_STATE_SETTLE_TIME) {
3610 /* XXX another gem from the Broadcom driver :( */
3611 ap->state = ANEG_STATE_LINK_OK;
3612 }
3613 break;
3614
3615 case ANEG_STATE_LINK_OK:
3616 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3617 ret = ANEG_DONE;
3618 break;
3619
3620 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3621 /* ??? unimplemented */
3622 break;
3623
3624 case ANEG_STATE_NEXT_PAGE_WAIT:
3625 /* ??? unimplemented */
3626 break;
3627
3628 default:
3629 ret = ANEG_FAILED;
3630 break;
855e1111 3631 }
1da177e4
LT		 3632
3633 return ret;
3634}
3635
5be73b47 3636static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3637{
3638 int res = 0;
3639 struct tg3_fiber_aneginfo aninfo;
3640 int status = ANEG_FAILED;
3641 unsigned int tick;
3642 u32 tmp;
3643
3644 tw32_f(MAC_TX_AUTO_NEG, 0);
3645
3646 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3647 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3648 udelay(40);
3649
3650 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3651 udelay(40);
3652
3653 memset(&aninfo, 0, sizeof(aninfo));
3654 aninfo.flags |= MR_AN_ENABLE;
3655 aninfo.state = ANEG_STATE_UNKNOWN;
3656 aninfo.cur_time = 0;
3657 tick = 0;
3658 while (++tick < 195000) {
3659 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3660 if (status == ANEG_DONE || status == ANEG_FAILED)
3661 break;
3662
3663 udelay(1);
3664 }
3665
3666 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3667 tw32_f(MAC_MODE, tp->mac_mode);
3668 udelay(40);
3669
5be73b47
MC		 3670 *txflags = aninfo.txconfig;
3671 *rxflags = aninfo.flags;
1da177e4
LT		 3672
3673 if (status == ANEG_DONE &&
3674 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3675 MR_LP_ADV_FULL_DUPLEX)))
3676 res = 1;
3677
3678 return res;
3679}
3680
3681static void tg3_init_bcm8002(struct tg3 *tp)
3682{
3683 u32 mac_status = tr32(MAC_STATUS);
3684 int i;
3685
3686 /* Reset when initting first time or we have a link. */
3687 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3688 !(mac_status & MAC_STATUS_PCS_SYNCED))
3689 return;
3690
3691 /* Set PLL lock range. */
3692 tg3_writephy(tp, 0x16, 0x8007);
3693
3694 /* SW reset */
3695 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3696
3697 /* Wait for reset to complete. */
3698 /* XXX schedule_timeout() ... */
3699 for (i = 0; i < 500; i++)
3700 udelay(10);
3701
3702 /* Config mode; select PMA/Ch 1 regs. */
3703 tg3_writephy(tp, 0x10, 0x8411);
3704
3705 /* Enable auto-lock and comdet, select txclk for tx. */
3706 tg3_writephy(tp, 0x11, 0x0a10);
3707
3708 tg3_writephy(tp, 0x18, 0x00a0);
3709 tg3_writephy(tp, 0x16, 0x41ff);
3710
3711 /* Assert and deassert POR. */
3712 tg3_writephy(tp, 0x13, 0x0400);
3713 udelay(40);
3714 tg3_writephy(tp, 0x13, 0x0000);
3715
3716 tg3_writephy(tp, 0x11, 0x0a50);
3717 udelay(40);
3718 tg3_writephy(tp, 0x11, 0x0a10);
3719
3720 /* Wait for signal to stabilize */
3721 /* XXX schedule_timeout() ... */
3722 for (i = 0; i < 15000; i++)
3723 udelay(10);
3724
3725 /* Deselect the channel register so we can read the PHYID
3726 * later.
3727 */
3728 tg3_writephy(tp, 0x10, 0x8011);
3729}
3730
3731static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3732{
82cd3d11 3733 u16 flowctrl;
1da177e4
LT		 3734 u32 sg_dig_ctrl, sg_dig_status;
3735 u32 serdes_cfg, expected_sg_dig_ctrl;
3736 int workaround, port_a;
3737 int current_link_up;
3738
3739 serdes_cfg = 0;
3740 expected_sg_dig_ctrl = 0;
3741 workaround = 0;
3742 port_a = 1;
3743 current_link_up = 0;
3744
3745 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3746 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3747 workaround = 1;
3748 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3749 port_a = 0;
3750
3751 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3752 /* preserve bits 20-23 for voltage regulator */
3753 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3754 }
3755
3756 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3757
3758 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3759 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3760 if (workaround) {
3761 u32 val = serdes_cfg;
3762
3763 if (port_a)
3764 val |= 0xc010000;
3765 else
3766 val |= 0x4010000;
3767 tw32_f(MAC_SERDES_CFG, val);
3768 }
c98f6e3b
MC		 3769
3770 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3771 }
3772 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3773 tg3_setup_flow_control(tp, 0, 0);
3774 current_link_up = 1;
3775 }
3776 goto out;
3777 }
3778
3779 /* Want auto-negotiation. */
c98f6e3b 3780 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3781
82cd3d11
MC		 3782 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3783 if (flowctrl & ADVERTISE_1000XPAUSE)
3784 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3785 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3786 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3787
3788 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3789 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3790 tp->serdes_counter &&
3791 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3792 MAC_STATUS_RCVD_CFG)) ==
3793 MAC_STATUS_PCS_SYNCED)) {
3794 tp->serdes_counter--;
3795 current_link_up = 1;
3796 goto out;
3797 }
3798restart_autoneg:
1da177e4
LT		 3799 if (workaround)
3800 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3801 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3802 udelay(5);
3803 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3804
3d3ebe74
MC		 3805 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3806 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3807 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3808 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3809 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3810 mac_status = tr32(MAC_STATUS);
3811
c98f6e3b 3812 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3813 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3814 u32 local_adv = 0, remote_adv = 0;
3815
3816 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3817 local_adv |= ADVERTISE_1000XPAUSE;
3818 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3819 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3820
c98f6e3b 3821 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3822 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3823 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3824 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3825
3826 tg3_setup_flow_control(tp, local_adv, remote_adv);
3827 current_link_up = 1;
3d3ebe74
MC		 3828 tp->serdes_counter = 0;
3829 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3830 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3831 if (tp->serdes_counter)
3832 tp->serdes_counter--;
1da177e4
LT		 3833 else {
3834 if (workaround) {
3835 u32 val = serdes_cfg;
3836
3837 if (port_a)
3838 val |= 0xc010000;
3839 else
3840 val |= 0x4010000;
3841
3842 tw32_f(MAC_SERDES_CFG, val);
3843 }
3844
c98f6e3b 3845 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3846 udelay(40);
3847
3848 /* Link parallel detection - link is up */
3849 /* only if we have PCS_SYNC and not */
3850 /* receiving config code words */
3851 mac_status = tr32(MAC_STATUS);
3852 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3853 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3854 tg3_setup_flow_control(tp, 0, 0);
3855 current_link_up = 1;
3d3ebe74
MC		 3856 tp->tg3_flags2 |=
3857 TG3_FLG2_PARALLEL_DETECT;
3858 tp->serdes_counter =
3859 SERDES_PARALLEL_DET_TIMEOUT;
3860 } else
3861 goto restart_autoneg;
1da177e4
LT		 3862 }
3863 }
3d3ebe74
MC		 3864 } else {
3865 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3866 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3867 }
3868
3869out:
3870 return current_link_up;
3871}
3872
3873static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3874{
3875 int current_link_up = 0;
3876
5cf64b8a 3877 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3878 goto out;
1da177e4
LT		 3879
3880 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3881 u32 txflags, rxflags;
1da177e4 3882 int i;
6aa20a22 3883
5be73b47
MC		 3884 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3885 u32 local_adv = 0, remote_adv = 0;
1da177e4 3886
5be73b47
MC		 3887 if (txflags & ANEG_CFG_PS1)
3888 local_adv |= ADVERTISE_1000XPAUSE;
3889 if (txflags & ANEG_CFG_PS2)
3890 local_adv |= ADVERTISE_1000XPSE_ASYM;
3891
3892 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3893 remote_adv |= LPA_1000XPAUSE;
3894 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3895 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3896
3897 tg3_setup_flow_control(tp, local_adv, remote_adv);
3898
1da177e4
LT		 3899 current_link_up = 1;
3900 }
3901 for (i = 0; i < 30; i++) {
3902 udelay(20);
3903 tw32_f(MAC_STATUS,
3904 (MAC_STATUS_SYNC_CHANGED |
3905 MAC_STATUS_CFG_CHANGED));
3906 udelay(40);
3907 if ((tr32(MAC_STATUS) &
3908 (MAC_STATUS_SYNC_CHANGED |
3909 MAC_STATUS_CFG_CHANGED)) == 0)
3910 break;
3911 }
3912
3913 mac_status = tr32(MAC_STATUS);
3914 if (current_link_up == 0 &&
3915 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3916 !(mac_status & MAC_STATUS_RCVD_CFG))
3917 current_link_up = 1;
3918 } else {
5be73b47
MC		 3919 tg3_setup_flow_control(tp, 0, 0);
3920
1da177e4
LT		 3921 /* Forcing 1000FD link up. */
3922 current_link_up = 1;
1da177e4
LT		 3923
3924 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3925 udelay(40);
e8f3f6ca
MC		 3926
3927 tw32_f(MAC_MODE, tp->mac_mode);
3928 udelay(40);
1da177e4
LT		 3929 }
3930
3931out:
3932 return current_link_up;
3933}
3934
3935static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3936{
3937 u32 orig_pause_cfg;
3938 u16 orig_active_speed;
3939 u8 orig_active_duplex;
3940 u32 mac_status;
3941 int current_link_up;
3942 int i;
3943
8d018621 3944 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3945 orig_active_speed = tp->link_config.active_speed;
3946 orig_active_duplex = tp->link_config.active_duplex;
3947
3948 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3949 netif_carrier_ok(tp->dev) &&
3950 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3951 mac_status = tr32(MAC_STATUS);
3952 mac_status &= (MAC_STATUS_PCS_SYNCED |
3953 MAC_STATUS_SIGNAL_DET |
3954 MAC_STATUS_CFG_CHANGED |
3955 MAC_STATUS_RCVD_CFG);
3956 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3957 MAC_STATUS_SIGNAL_DET)) {
3958 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3959 MAC_STATUS_CFG_CHANGED));
3960 return 0;
3961 }
3962 }
3963
3964 tw32_f(MAC_TX_AUTO_NEG, 0);
3965
3966 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3967 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3968 tw32_f(MAC_MODE, tp->mac_mode);
3969 udelay(40);
3970
3971 if (tp->phy_id == PHY_ID_BCM8002)
3972 tg3_init_bcm8002(tp);
3973
3974 /* Enable link change event even when serdes polling. */
3975 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3976 udelay(40);
3977
3978 current_link_up = 0;
3979 mac_status = tr32(MAC_STATUS);
3980
3981 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3982 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3983 else
3984 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3985
898a56f8 3986 tp->napi[0].hw_status->status =
1da177e4 3987 (SD_STATUS_UPDATED |
898a56f8 3988 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3989
3990 for (i = 0; i < 100; i++) {
3991 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3992 MAC_STATUS_CFG_CHANGED));
3993 udelay(5);
3994 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3995 MAC_STATUS_CFG_CHANGED |
3996 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3997 break;
3998 }
3999
4000 mac_status = tr32(MAC_STATUS);
4001 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4002 current_link_up = 0;
3d3ebe74
MC		 4003 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4004 tp->serdes_counter == 0) {
1da177e4
LT		 4005 tw32_f(MAC_MODE, (tp->mac_mode |
4006 MAC_MODE_SEND_CONFIGS));
4007 udelay(1);
4008 tw32_f(MAC_MODE, tp->mac_mode);
4009 }
4010 }
4011
4012 if (current_link_up == 1) {
4013 tp->link_config.active_speed = SPEED_1000;
4014 tp->link_config.active_duplex = DUPLEX_FULL;
4015 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016 LED_CTRL_LNKLED_OVERRIDE |
4017 LED_CTRL_1000MBPS_ON));
4018 } else {
4019 tp->link_config.active_speed = SPEED_INVALID;
4020 tp->link_config.active_duplex = DUPLEX_INVALID;
4021 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4022 LED_CTRL_LNKLED_OVERRIDE |
4023 LED_CTRL_TRAFFIC_OVERRIDE));
4024 }
4025
4026 if (current_link_up != netif_carrier_ok(tp->dev)) {
4027 if (current_link_up)
4028 netif_carrier_on(tp->dev);
4029 else
4030 netif_carrier_off(tp->dev);
4031 tg3_link_report(tp);
4032 } else {
8d018621 4033 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4034 if (orig_pause_cfg != now_pause_cfg ||
4035 orig_active_speed != tp->link_config.active_speed ||
4036 orig_active_duplex != tp->link_config.active_duplex)
4037 tg3_link_report(tp);
4038 }
4039
4040 return 0;
4041}
4042
747e8f8b
MC		 4043static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4044{
4045 int current_link_up, err = 0;
4046 u32 bmsr, bmcr;
4047 u16 current_speed;
4048 u8 current_duplex;
ef167e27 4049 u32 local_adv, remote_adv;
747e8f8b
MC		 4050
4051 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4052 tw32_f(MAC_MODE, tp->mac_mode);
4053 udelay(40);
4054
4055 tw32(MAC_EVENT, 0);
4056
4057 tw32_f(MAC_STATUS,
4058 (MAC_STATUS_SYNC_CHANGED |
4059 MAC_STATUS_CFG_CHANGED |
4060 MAC_STATUS_MI_COMPLETION |
4061 MAC_STATUS_LNKSTATE_CHANGED));
4062 udelay(40);
4063
4064 if (force_reset)
4065 tg3_phy_reset(tp);
4066
4067 current_link_up = 0;
4068 current_speed = SPEED_INVALID;
4069 current_duplex = DUPLEX_INVALID;
4070
4071 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4074 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4075 bmsr |= BMSR_LSTATUS;
4076 else
4077 bmsr &= ~BMSR_LSTATUS;
4078 }
747e8f8b
MC		 4079
4080 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4081
4082 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4083 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4084 /* do nothing, just check for link up at the end */
4085 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4086 u32 adv, new_adv;
4087
4088 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4089 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4090 ADVERTISE_1000XPAUSE |
4091 ADVERTISE_1000XPSE_ASYM |
4092 ADVERTISE_SLCT);
4093
ba4d07a8 4094 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4095
4096 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4097 new_adv |= ADVERTISE_1000XHALF;
4098 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4099 new_adv |= ADVERTISE_1000XFULL;
4100
4101 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4102 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4103 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4104 tg3_writephy(tp, MII_BMCR, bmcr);
4105
4106 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4107 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4108 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4109
4110 return err;
4111 }
4112 } else {
4113 u32 new_bmcr;
4114
4115 bmcr &= ~BMCR_SPEED1000;
4116 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4117
4118 if (tp->link_config.duplex == DUPLEX_FULL)
4119 new_bmcr |= BMCR_FULLDPLX;
4120
4121 if (new_bmcr != bmcr) {
4122 /* BMCR_SPEED1000 is a reserved bit that needs
4123 * to be set on write.
4124 */
4125 new_bmcr |= BMCR_SPEED1000;
4126
4127 /* Force a linkdown */
4128 if (netif_carrier_ok(tp->dev)) {
4129 u32 adv;
4130
4131 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4132 adv &= ~(ADVERTISE_1000XFULL |
4133 ADVERTISE_1000XHALF |
4134 ADVERTISE_SLCT);
4135 tg3_writephy(tp, MII_ADVERTISE, adv);
4136 tg3_writephy(tp, MII_BMCR, bmcr |
4137 BMCR_ANRESTART |
4138 BMCR_ANENABLE);
4139 udelay(10);
4140 netif_carrier_off(tp->dev);
4141 }
4142 tg3_writephy(tp, MII_BMCR, new_bmcr);
4143 bmcr = new_bmcr;
4144 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4146 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4147 ASIC_REV_5714) {
4148 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4149 bmsr |= BMSR_LSTATUS;
4150 else
4151 bmsr &= ~BMSR_LSTATUS;
4152 }
747e8f8b
MC		 4153 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4154 }
4155 }
4156
4157 if (bmsr & BMSR_LSTATUS) {
4158 current_speed = SPEED_1000;
4159 current_link_up = 1;
4160 if (bmcr & BMCR_FULLDPLX)
4161 current_duplex = DUPLEX_FULL;
4162 else
4163 current_duplex = DUPLEX_HALF;
4164
ef167e27
MC		 4165 local_adv = 0;
4166 remote_adv = 0;
4167
747e8f8b 4168 if (bmcr & BMCR_ANENABLE) {
ef167e27 4169 u32 common;
747e8f8b
MC		 4170
4171 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4172 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4173 common = local_adv & remote_adv;
4174 if (common & (ADVERTISE_1000XHALF |
4175 ADVERTISE_1000XFULL)) {
4176 if (common & ADVERTISE_1000XFULL)
4177 current_duplex = DUPLEX_FULL;
4178 else
4179 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4180 }
4181 else
4182 current_link_up = 0;
4183 }
4184 }
4185
ef167e27
MC		 4186 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4187 tg3_setup_flow_control(tp, local_adv, remote_adv);
4188
747e8f8b
MC		 4189 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4190 if (tp->link_config.active_duplex == DUPLEX_HALF)
4191 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4192
4193 tw32_f(MAC_MODE, tp->mac_mode);
4194 udelay(40);
4195
4196 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4197
4198 tp->link_config.active_speed = current_speed;
4199 tp->link_config.active_duplex = current_duplex;
4200
4201 if (current_link_up != netif_carrier_ok(tp->dev)) {
4202 if (current_link_up)
4203 netif_carrier_on(tp->dev);
4204 else {
4205 netif_carrier_off(tp->dev);
4206 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4207 }
4208 tg3_link_report(tp);
4209 }
4210 return err;
4211}
4212
4213static void tg3_serdes_parallel_detect(struct tg3 *tp)
4214{
3d3ebe74 4215 if (tp->serdes_counter) {
747e8f8b 4216 /* Give autoneg time to complete. */
3d3ebe74 4217 tp->serdes_counter--;
747e8f8b
MC		 4218 return;
4219 }
4220 if (!netif_carrier_ok(tp->dev) &&
4221 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4222 u32 bmcr;
4223
4224 tg3_readphy(tp, MII_BMCR, &bmcr);
4225 if (bmcr & BMCR_ANENABLE) {
4226 u32 phy1, phy2;
4227
4228 /* Select shadow register 0x1f */
4229 tg3_writephy(tp, 0x1c, 0x7c00);
4230 tg3_readphy(tp, 0x1c, &phy1);
4231
4232 /* Select expansion interrupt status register */
4233 tg3_writephy(tp, 0x17, 0x0f01);
4234 tg3_readphy(tp, 0x15, &phy2);
4235 tg3_readphy(tp, 0x15, &phy2);
4236
4237 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4238 /* We have signal detect and not receiving
4239 * config code words, link is up by parallel
4240 * detection.
4241 */
4242
4243 bmcr &= ~BMCR_ANENABLE;
4244 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4245 tg3_writephy(tp, MII_BMCR, bmcr);
4246 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4247 }
4248 }
4249 }
4250 else if (netif_carrier_ok(tp->dev) &&
4251 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4252 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4253 u32 phy2;
4254
4255 /* Select expansion interrupt status register */
4256 tg3_writephy(tp, 0x17, 0x0f01);
4257 tg3_readphy(tp, 0x15, &phy2);
4258 if (phy2 & 0x20) {
4259 u32 bmcr;
4260
4261 /* Config code words received, turn on autoneg. */
4262 tg3_readphy(tp, MII_BMCR, &bmcr);
4263 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4264
4265 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4266
4267 }
4268 }
4269}
4270
1da177e4
LT		 4271static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4272{
4273 int err;
4274
4275 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4276 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4277 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4278 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4279 } else {
4280 err = tg3_setup_copper_phy(tp, force_reset);
4281 }
4282
bcb37f6c 4283 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4284 u32 val, scale;
4285
4286 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4287 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4288 scale = 65;
4289 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4290 scale = 6;
4291 else
4292 scale = 12;
4293
4294 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4295 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4296 tw32(GRC_MISC_CFG, val);
4297 }
4298
1da177e4
LT		 4299 if (tp->link_config.active_speed == SPEED_1000 &&
4300 tp->link_config.active_duplex == DUPLEX_HALF)
4301 tw32(MAC_TX_LENGTHS,
4302 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4303 (6 << TX_LENGTHS_IPG_SHIFT) |
4304 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4305 else
4306 tw32(MAC_TX_LENGTHS,
4307 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4308 (6 << TX_LENGTHS_IPG_SHIFT) |
4309 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4310
4311 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4312 if (netif_carrier_ok(tp->dev)) {
4313 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4314 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4315 } else {
4316 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4317 }
4318 }
4319
8ed5d97e
MC		 4320 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4321 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4322 if (!netif_carrier_ok(tp->dev))
4323 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4324 tp->pwrmgmt_thresh;
4325 else
4326 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4327 tw32(PCIE_PWR_MGMT_THRESH, val);
4328 }
4329
1da177e4
LT		 4330 return err;
4331}
4332
df3e6548
MC		 4333/* This is called whenever we suspect that the system chipset is re-
4334 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4335 * is bogus tx completions. We try to recover by setting the
4336 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4337 * in the workqueue.
4338 */
4339static void tg3_tx_recover(struct tg3 *tp)
4340{
4341 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4342 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4343
4344 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4345 "mapped I/O cycles to the network device, attempting to "
4346 "recover. Please report the problem to the driver maintainer "
4347 "and include system chipset information.\n", tp->dev->name);
4348
4349 spin_lock(&tp->lock);
df3e6548 4350 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4351 spin_unlock(&tp->lock);
4352}
4353
f3f3f27e 4354static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4355{
4356 smp_mb();
f3f3f27e
MC		 4357 return tnapi->tx_pending -
4358 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4359}
4360
1da177e4
LT		 4361/* Tigon3 never reports partial packet sends. So we do not
4362 * need special logic to handle SKBs that have not had all
4363 * of their frags sent yet, like SunGEM does.
4364 */
17375d25 4365static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4366{
17375d25 4367 struct tg3 *tp = tnapi->tp;
898a56f8 4368 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4369 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4370 struct netdev_queue *txq;
4371 int index = tnapi - tp->napi;
4372
19cfaecc 4373 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4374 index--;
4375
4376 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4377
4378 while (sw_idx != hw_idx) {
f4188d8a 4379 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4380 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4381 int i, tx_bug = 0;
4382
4383 if (unlikely(skb == NULL)) {
4384 tg3_tx_recover(tp);
4385 return;
4386 }
1da177e4 4387
f4188d8a
AD		 4388 pci_unmap_single(tp->pdev,
4389 pci_unmap_addr(ri, mapping),
4390 skb_headlen(skb),
4391 PCI_DMA_TODEVICE);
1da177e4
LT		 4392
4393 ri->skb = NULL;
4394
4395 sw_idx = NEXT_TX(sw_idx);
4396
4397 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4398 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4399 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4400 tx_bug = 1;
f4188d8a
AD		 4401
4402 pci_unmap_page(tp->pdev,
4403 pci_unmap_addr(ri, mapping),
4404 skb_shinfo(skb)->frags[i].size,
4405 PCI_DMA_TODEVICE);
1da177e4
LT		 4406 sw_idx = NEXT_TX(sw_idx);
4407 }
4408
f47c11ee 4409 dev_kfree_skb(skb);
df3e6548
MC		 4410
4411 if (unlikely(tx_bug)) {
4412 tg3_tx_recover(tp);
4413 return;
4414 }
1da177e4
LT		 4415 }
4416
f3f3f27e 4417 tnapi->tx_cons = sw_idx;
1da177e4 4418
1b2a7205
MC		 4419 /* Need to make the tx_cons update visible to tg3_start_xmit()
4420 * before checking for netif_queue_stopped(). Without the
4421 * memory barrier, there is a small possibility that tg3_start_xmit()
4422 * will miss it and cause the queue to be stopped forever.
4423 */
4424 smp_mb();
4425
fe5f5787 4426 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4427 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4428 __netif_tx_lock(txq, smp_processor_id());
4429 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4430 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4431 netif_tx_wake_queue(txq);
4432 __netif_tx_unlock(txq);
51b91468 4433 }
1da177e4
LT		 4434}
4435
2b2cdb65
MC		 4436static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4437{
4438 if (!ri->skb)
4439 return;
4440
4441 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4442 map_sz, PCI_DMA_FROMDEVICE);
4443 dev_kfree_skb_any(ri->skb);
4444 ri->skb = NULL;
4445}
4446
1da177e4
LT		 4447/* Returns size of skb allocated or < 0 on error.
4448 *
4449 * We only need to fill in the address because the other members
4450 * of the RX descriptor are invariant, see tg3_init_rings.
4451 *
4452 * Note the purposeful assymetry of cpu vs. chip accesses. For
4453 * posting buffers we only dirty the first cache line of the RX
4454 * descriptor (containing the address). Whereas for the RX status
4455 * buffers the cpu only reads the last cacheline of the RX descriptor
4456 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4457 */
86b21e59 4458static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4459 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4460{
4461 struct tg3_rx_buffer_desc *desc;
4462 struct ring_info *map, *src_map;
4463 struct sk_buff *skb;
4464 dma_addr_t mapping;
4465 int skb_size, dest_idx;
4466
4467 src_map = NULL;
4468 switch (opaque_key) {
4469 case RXD_OPAQUE_RING_STD:
4470 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4471 desc = &tpr->rx_std[dest_idx];
4472 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4473 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4474 break;
4475
4476 case RXD_OPAQUE_RING_JUMBO:
4477 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4478 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4479 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4480 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4481 break;
4482
4483 default:
4484 return -EINVAL;
855e1111 4485 }
1da177e4
LT		 4486
4487 /* Do not overwrite any of the map or rp information
4488 * until we are sure we can commit to a new buffer.
4489 *
4490 * Callers depend upon this behavior and assume that
4491 * we leave everything unchanged if we fail.
4492 */
287be12e 4493 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4494 if (skb == NULL)
4495 return -ENOMEM;
4496
1da177e4
LT		 4497 skb_reserve(skb, tp->rx_offset);
4498
287be12e 4499 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4500 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4501 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4502 dev_kfree_skb(skb);
4503 return -EIO;
4504 }
1da177e4
LT		 4505
4506 map->skb = skb;
4507 pci_unmap_addr_set(map, mapping, mapping);
4508
1da177e4
LT		 4509 desc->addr_hi = ((u64)mapping >> 32);
4510 desc->addr_lo = ((u64)mapping & 0xffffffff);
4511
4512 return skb_size;
4513}
4514
4515/* We only need to move over in the address because the other
4516 * members of the RX descriptor are invariant. See notes above
4517 * tg3_alloc_rx_skb for full details.
4518 */
a3896167
MC		 4519static void tg3_recycle_rx(struct tg3_napi *tnapi,
4520 struct tg3_rx_prodring_set *dpr,
4521 u32 opaque_key, int src_idx,
4522 u32 dest_idx_unmasked)
1da177e4 4523{
17375d25 4524 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4525 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4526 struct ring_info *src_map, *dest_map;
4527 int dest_idx;
a3896167 4528 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4529
4530 switch (opaque_key) {
4531 case RXD_OPAQUE_RING_STD:
4532 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4533 dest_desc = &dpr->rx_std[dest_idx];
4534 dest_map = &dpr->rx_std_buffers[dest_idx];
4535 src_desc = &spr->rx_std[src_idx];
4536 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4537 break;
4538
4539 case RXD_OPAQUE_RING_JUMBO:
4540 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4541 dest_desc = &dpr->rx_jmb[dest_idx].std;
4542 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4543 src_desc = &spr->rx_jmb[src_idx].std;
4544 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4545 break;
4546
4547 default:
4548 return;
855e1111 4549 }
1da177e4
LT		 4550
4551 dest_map->skb = src_map->skb;
4552 pci_unmap_addr_set(dest_map, mapping,
4553 pci_unmap_addr(src_map, mapping));
4554 dest_desc->addr_hi = src_desc->addr_hi;
4555 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 4556
4557 /* Ensure that the update to the skb happens after the physical
4558 * addresses have been transferred to the new BD location.
4559 */
4560 smp_wmb();
4561
1da177e4
LT		 4562 src_map->skb = NULL;
4563}
4564
1da177e4
LT		 4565/* The RX ring scheme is composed of multiple rings which post fresh
4566 * buffers to the chip, and one special ring the chip uses to report
4567 * status back to the host.
4568 *
4569 * The special ring reports the status of received packets to the
4570 * host. The chip does not write into the original descriptor the
4571 * RX buffer was obtained from. The chip simply takes the original
4572 * descriptor as provided by the host, updates the status and length
4573 * field, then writes this into the next status ring entry.
4574 *
4575 * Each ring the host uses to post buffers to the chip is described
4576 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4577 * it is first placed into the on-chip ram. When the packet's length
4578 * is known, it walks down the TG3_BDINFO entries to select the ring.
4579 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4580 * which is within the range of the new packet's length is chosen.
4581 *
4582 * The "separate ring for rx status" scheme may sound queer, but it makes
4583 * sense from a cache coherency perspective. If only the host writes
4584 * to the buffer post rings, and only the chip writes to the rx status
4585 * rings, then cache lines never move beyond shared-modified state.
4586 * If both the host and chip were to write into the same ring, cache line
4587 * eviction could occur since both entities want it in an exclusive state.
4588 */
17375d25 4589static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4590{
17375d25 4591 struct tg3 *tp = tnapi->tp;
f92905de 4592 u32 work_mask, rx_std_posted = 0;
4361935a 4593 u32 std_prod_idx, jmb_prod_idx;
72334482 4594 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4595 u16 hw_idx;
1da177e4 4596 int received;
b196c7e4 4597 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4598
8d9d7cfc 4599 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4600 /*
4601 * We need to order the read of hw_idx and the read of
4602 * the opaque cookie.
4603 */
4604 rmb();
1da177e4
LT		 4605 work_mask = 0;
4606 received = 0;
4361935a
MC		 4607 std_prod_idx = tpr->rx_std_prod_idx;
4608 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4609 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4610 struct ring_info *ri;
72334482 4611 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4612 unsigned int len;
4613 struct sk_buff *skb;
4614 dma_addr_t dma_addr;
4615 u32 opaque_key, desc_idx, *post_ptr;
4616
4617 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4618 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4619 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4620 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4621 dma_addr = pci_unmap_addr(ri, mapping);
4622 skb = ri->skb;
4361935a 4623 post_ptr = &std_prod_idx;
f92905de 4624 rx_std_posted++;
1da177e4 4625 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4626 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4627 dma_addr = pci_unmap_addr(ri, mapping);
4628 skb = ri->skb;
4361935a 4629 post_ptr = &jmb_prod_idx;
21f581a5 4630 } else
1da177e4 4631 goto next_pkt_nopost;
1da177e4
LT		 4632
4633 work_mask |= opaque_key;
4634
4635 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4636 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4637 drop_it:
a3896167 4638 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4639 desc_idx, *post_ptr);
4640 drop_it_no_recycle:
4641 /* Other statistics kept track of by card. */
4642 tp->net_stats.rx_dropped++;
4643 goto next_pkt;
4644 }
4645
ad829268
MC		 4646 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4647 ETH_FCS_LEN;
1da177e4 4648
8e95a202
JP		 4649 if (len > RX_COPY_THRESHOLD &&
4650 tp->rx_offset == NET_IP_ALIGN) {
4651 /* rx_offset will likely not equal NET_IP_ALIGN
4652 * if this is a 5701 card running in PCI-X mode
4653 * [see tg3_get_invariants()]
4654 */
1da177e4
LT		 4655 int skb_size;
4656
86b21e59 4657 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4658 *post_ptr);
1da177e4
LT		 4659 if (skb_size < 0)
4660 goto drop_it;
4661
afc081f8
MC		 4662 ri->skb = NULL;
4663
287be12e 4664 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4665 PCI_DMA_FROMDEVICE);
4666
4667 skb_put(skb, len);
4668 } else {
4669 struct sk_buff *copy_skb;
4670
a3896167 4671 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4672 desc_idx, *post_ptr);
4673
ad829268
MC		 4674 copy_skb = netdev_alloc_skb(tp->dev,
4675 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4676 if (copy_skb == NULL)
4677 goto drop_it_no_recycle;
4678
ad829268 4679 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4680 skb_put(copy_skb, len);
4681 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4682 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4683 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4684
4685 /* We'll reuse the original ring buffer. */
4686 skb = copy_skb;
4687 }
4688
4689 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4690 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4691 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4692 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4693 skb->ip_summed = CHECKSUM_UNNECESSARY;
4694 else
4695 skb->ip_summed = CHECKSUM_NONE;
4696
4697 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4698
4699 if (len > (tp->dev->mtu + ETH_HLEN) &&
4700 skb->protocol != htons(ETH_P_8021Q)) {
4701 dev_kfree_skb(skb);
4702 goto next_pkt;
4703 }
4704
1da177e4
LT		 4705#if TG3_VLAN_TAG_USED
4706 if (tp->vlgrp != NULL &&
4707 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4708 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4709 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4710 } else
4711#endif
17375d25 4712 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4713
1da177e4
LT		 4714 received++;
4715 budget--;
4716
4717next_pkt:
4718 (*post_ptr)++;
f92905de
MC		 4719
4720 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4721 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4722 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4723 tpr->rx_std_prod_idx);
f92905de
MC		 4724 work_mask &= ~RXD_OPAQUE_RING_STD;
4725 rx_std_posted = 0;
4726 }
1da177e4 4727next_pkt_nopost:
483ba50b 4728 sw_idx++;
6b31a515 4729 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4730
4731 /* Refresh hw_idx to see if there is new work */
4732 if (sw_idx == hw_idx) {
8d9d7cfc 4733 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4734 rmb();
4735 }
1da177e4
LT		 4736 }
4737
4738 /* ACK the status ring. */
72334482
MC		 4739 tnapi->rx_rcb_ptr = sw_idx;
4740 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4741
4742 /* Refill RX ring(s). */
e4af1af9 4743 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
b196c7e4
MC		 4744 if (work_mask & RXD_OPAQUE_RING_STD) {
4745 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4746 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4747 tpr->rx_std_prod_idx);
4748 }
4749 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4750 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4751 TG3_RX_JUMBO_RING_SIZE;
4752 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4753 tpr->rx_jmb_prod_idx);
4754 }
4755 mmiowb();
4756 } else if (work_mask) {
4757 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4758 * updated before the producer indices can be updated.
4759 */
4760 smp_wmb();
4761
4361935a 4762 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4763 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4 4764
e4af1af9
MC		 4765 if (tnapi != &tp->napi[1])
4766 napi_schedule(&tp->napi[1].napi);
1da177e4 4767 }
1da177e4
LT		 4768
4769 return received;
4770}
4771
35f2d7d0 4772static void tg3_poll_link(struct tg3 *tp)
1da177e4 4773{
1da177e4
LT		 4774 /* handle link change and other phy events */
4775 if (!(tp->tg3_flags &
4776 (TG3_FLAG_USE_LINKCHG_REG |
4777 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4778 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4779
1da177e4
LT		 4780 if (sblk->status & SD_STATUS_LINK_CHG) {
4781 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4782 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4783 spin_lock(&tp->lock);
dd477003
MC		 4784 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4785 tw32_f(MAC_STATUS,
4786 (MAC_STATUS_SYNC_CHANGED |
4787 MAC_STATUS_CFG_CHANGED |
4788 MAC_STATUS_MI_COMPLETION |
4789 MAC_STATUS_LNKSTATE_CHANGED));
4790 udelay(40);
4791 } else
4792 tg3_setup_phy(tp, 0);
f47c11ee 4793 spin_unlock(&tp->lock);
1da177e4
LT		 4794 }
4795 }
35f2d7d0
MC		 4796}
4797
f89f38b8
MC		 4798static int tg3_rx_prodring_xfer(struct tg3 *tp,
4799 struct tg3_rx_prodring_set *dpr,
4800 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 4801{
4802 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 4803 int i, err = 0;
b196c7e4
MC		 4804
4805 while (1) {
4806 src_prod_idx = spr->rx_std_prod_idx;
4807
4808 /* Make sure updates to the rx_std_buffers[] entries and the
4809 * standard producer index are seen in the correct order.
4810 */
4811 smp_rmb();
4812
4813 if (spr->rx_std_cons_idx == src_prod_idx)
4814 break;
4815
4816 if (spr->rx_std_cons_idx < src_prod_idx)
4817 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4818 else
4819 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4820
4821 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4822
4823 si = spr->rx_std_cons_idx;
4824 di = dpr->rx_std_prod_idx;
4825
e92967bf
MC		 4826 for (i = di; i < di + cpycnt; i++) {
4827 if (dpr->rx_std_buffers[i].skb) {
4828 cpycnt = i - di;
f89f38b8 4829 err = -ENOSPC;
e92967bf
MC		 4830 break;
4831 }
4832 }
4833
4834 if (!cpycnt)
4835 break;
4836
4837 /* Ensure that updates to the rx_std_buffers ring and the
4838 * shadowed hardware producer ring from tg3_recycle_skb() are
4839 * ordered correctly WRT the skb check above.
4840 */
4841 smp_rmb();
4842
b196c7e4
MC		 4843 memcpy(&dpr->rx_std_buffers[di],
4844 &spr->rx_std_buffers[si],
4845 cpycnt * sizeof(struct ring_info));
4846
4847 for (i = 0; i < cpycnt; i++, di++, si++) {
4848 struct tg3_rx_buffer_desc *sbd, *dbd;
4849 sbd = &spr->rx_std[si];
4850 dbd = &dpr->rx_std[di];
4851 dbd->addr_hi = sbd->addr_hi;
4852 dbd->addr_lo = sbd->addr_lo;
4853 }
4854
4855 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4856 TG3_RX_RING_SIZE;
4857 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4858 TG3_RX_RING_SIZE;
4859 }
4860
4861 while (1) {
4862 src_prod_idx = spr->rx_jmb_prod_idx;
4863
4864 /* Make sure updates to the rx_jmb_buffers[] entries and
4865 * the jumbo producer index are seen in the correct order.
4866 */
4867 smp_rmb();
4868
4869 if (spr->rx_jmb_cons_idx == src_prod_idx)
4870 break;
4871
4872 if (spr->rx_jmb_cons_idx < src_prod_idx)
4873 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4874 else
4875 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4876
4877 cpycnt = min(cpycnt,
4878 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4879
4880 si = spr->rx_jmb_cons_idx;
4881 di = dpr->rx_jmb_prod_idx;
4882
e92967bf
MC		 4883 for (i = di; i < di + cpycnt; i++) {
4884 if (dpr->rx_jmb_buffers[i].skb) {
4885 cpycnt = i - di;
f89f38b8 4886 err = -ENOSPC;
e92967bf
MC		 4887 break;
4888 }
4889 }
4890
4891 if (!cpycnt)
4892 break;
4893
4894 /* Ensure that updates to the rx_jmb_buffers ring and the
4895 * shadowed hardware producer ring from tg3_recycle_skb() are
4896 * ordered correctly WRT the skb check above.
4897 */
4898 smp_rmb();
4899
b196c7e4
MC		 4900 memcpy(&dpr->rx_jmb_buffers[di],
4901 &spr->rx_jmb_buffers[si],
4902 cpycnt * sizeof(struct ring_info));
4903
4904 for (i = 0; i < cpycnt; i++, di++, si++) {
4905 struct tg3_rx_buffer_desc *sbd, *dbd;
4906 sbd = &spr->rx_jmb[si].std;
4907 dbd = &dpr->rx_jmb[di].std;
4908 dbd->addr_hi = sbd->addr_hi;
4909 dbd->addr_lo = sbd->addr_lo;
4910 }
4911
4912 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4913 TG3_RX_JUMBO_RING_SIZE;
4914 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4915 TG3_RX_JUMBO_RING_SIZE;
4916 }
f89f38b8
MC		 4917
4918 return err;
b196c7e4
MC		 4919}
4920
35f2d7d0
MC		 4921static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4922{
4923 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4924
4925 /* run TX completion thread */
f3f3f27e 4926 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4927 tg3_tx(tnapi);
6f535763 4928 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4929 return work_done;
1da177e4
LT		 4930 }
4931
1da177e4
LT		 4932 /* run RX thread, within the bounds set by NAPI.
4933 * All RX "locking" is done by ensuring outside
bea3348e 4934 * code synchronizes with tg3->napi.poll()
1da177e4 4935 */
8d9d7cfc 4936 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4937 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4938
b196c7e4 4939 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
e4af1af9 4940 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
f89f38b8 4941 int i, err = 0;
e4af1af9
MC		 4942 u32 std_prod_idx = dpr->rx_std_prod_idx;
4943 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 4944
e4af1af9 4945 for (i = 1; i < tp->irq_cnt; i++)
f89f38b8
MC		 4946 err |= tg3_rx_prodring_xfer(tp, dpr,
4947 tp->napi[i].prodring);
b196c7e4
MC		 4948
4949 wmb();
4950
e4af1af9
MC		 4951 if (std_prod_idx != dpr->rx_std_prod_idx)
4952 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4953 dpr->rx_std_prod_idx);
b196c7e4 4954
e4af1af9
MC		 4955 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4956 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4957 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 4958
4959 mmiowb();
f89f38b8
MC		 4960
4961 if (err)
4962 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 4963 }
4964
6f535763
DM		 4965 return work_done;
4966}
4967
35f2d7d0
MC		 4968static int tg3_poll_msix(struct napi_struct *napi, int budget)
4969{
4970 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4971 struct tg3 *tp = tnapi->tp;
4972 int work_done = 0;
4973 struct tg3_hw_status *sblk = tnapi->hw_status;
4974
4975 while (1) {
4976 work_done = tg3_poll_work(tnapi, work_done, budget);
4977
4978 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979 goto tx_recovery;
4980
4981 if (unlikely(work_done >= budget))
4982 break;
4983
4984 /* tp->last_tag is used in tg3_restart_ints() below
4985 * to tell the hw how much work has been processed,
4986 * so we must read it before checking for more work.
4987 */
4988 tnapi->last_tag = sblk->status_tag;
4989 tnapi->last_irq_tag = tnapi->last_tag;
4990 rmb();
4991
4992 /* check for RX/TX work to do */
4993 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4994 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4995 napi_complete(napi);
4996 /* Reenable interrupts. */
4997 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4998 mmiowb();
4999 break;
5000 }
5001 }
5002
5003 return work_done;
5004
5005tx_recovery:
5006 /* work_done is guaranteed to be less than budget. */
5007 napi_complete(napi);
5008 schedule_work(&tp->reset_task);
5009 return work_done;
5010}
5011
6f535763
DM		 5012static int tg3_poll(struct napi_struct *napi, int budget)
5013{
8ef0442f
MC		 5014 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015 struct tg3 *tp = tnapi->tp;
6f535763 5016 int work_done = 0;
898a56f8 5017 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 5018
5019 while (1) {
35f2d7d0
MC		 5020 tg3_poll_link(tp);
5021
17375d25 5022 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 5023
5024 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5025 goto tx_recovery;
5026
5027 if (unlikely(work_done >= budget))
5028 break;
5029
4fd7ab59 5030 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 5031 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 5032 * to tell the hw how much work has been processed,
5033 * so we must read it before checking for more work.
5034 */
898a56f8
MC		 5035 tnapi->last_tag = sblk->status_tag;
5036 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 5037 rmb();
5038 } else
5039 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 5040
17375d25 5041 if (likely(!tg3_has_work(tnapi))) {
288379f0 5042 napi_complete(napi);
17375d25 5043 tg3_int_reenable(tnapi);
6f535763
DM		 5044 break;
5045 }
1da177e4
LT		 5046 }
5047
bea3348e 5048 return work_done;
6f535763
DM		 5049
5050tx_recovery:
4fd7ab59 5051 /* work_done is guaranteed to be less than budget. */
288379f0 5052 napi_complete(napi);
6f535763 5053 schedule_work(&tp->reset_task);
4fd7ab59 5054 return work_done;
1da177e4
LT		 5055}
5056
f47c11ee
DM		 5057static void tg3_irq_quiesce(struct tg3 *tp)
5058{
4f125f42
MC		 5059 int i;
5060
f47c11ee
DM		 5061 BUG_ON(tp->irq_sync);
5062
5063 tp->irq_sync = 1;
5064 smp_mb();
5065
4f125f42
MC		 5066 for (i = 0; i < tp->irq_cnt; i++)
5067 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5068}
5069
5070static inline int tg3_irq_sync(struct tg3 *tp)
5071{
5072 return tp->irq_sync;
5073}
5074
5075/* Fully shutdown all tg3 driver activity elsewhere in the system.
5076 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5077 * with as well. Most of the time, this is not necessary except when
5078 * shutting down the device.
5079 */
5080static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5081{
46966545 5082 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5083 if (irq_sync)
5084 tg3_irq_quiesce(tp);
f47c11ee
DM		 5085}
5086
5087static inline void tg3_full_unlock(struct tg3 *tp)
5088{
f47c11ee
DM		 5089 spin_unlock_bh(&tp->lock);
5090}
5091
fcfa0a32
MC		 5092/* One-shot MSI handler - Chip automatically disables interrupt
5093 * after sending MSI so driver doesn't have to do it.
5094 */
7d12e780 5095static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5096{
09943a18
MC		 5097 struct tg3_napi *tnapi = dev_id;
5098 struct tg3 *tp = tnapi->tp;
fcfa0a32 5099
898a56f8 5100 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5101 if (tnapi->rx_rcb)
5102 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5103
5104 if (likely(!tg3_irq_sync(tp)))
09943a18 5105 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5106
5107 return IRQ_HANDLED;
5108}
5109
88b06bc2
MC		 5110/* MSI ISR - No need to check for interrupt sharing and no need to
5111 * flush status block and interrupt mailbox. PCI ordering rules
5112 * guarantee that MSI will arrive after the status block.
5113 */
7d12e780 5114static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5115{
09943a18
MC		 5116 struct tg3_napi *tnapi = dev_id;
5117 struct tg3 *tp = tnapi->tp;
88b06bc2 5118
898a56f8 5119 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5120 if (tnapi->rx_rcb)
5121 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5122 /*
fac9b83e 5123 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5124 * chip-internal interrupt pending events.
fac9b83e 5125 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5126 * NIC to stop sending us irqs, engaging "in-intr-handler"
5127 * event coalescing.
5128 */
5129 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5130 if (likely(!tg3_irq_sync(tp)))
09943a18 5131 napi_schedule(&tnapi->napi);
61487480 5132
88b06bc2
MC		 5133 return IRQ_RETVAL(1);
5134}
5135
7d12e780 5136static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5137{
09943a18
MC		 5138 struct tg3_napi *tnapi = dev_id;
5139 struct tg3 *tp = tnapi->tp;
898a56f8 5140 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5141 unsigned int handled = 1;
5142
1da177e4
LT		 5143 /* In INTx mode, it is possible for the interrupt to arrive at
5144 * the CPU before the status block posted prior to the interrupt.
5145 * Reading the PCI State register will confirm whether the
5146 * interrupt is ours and will flush the status block.
5147 */
d18edcb2
MC		 5148 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5149 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5150 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5151 handled = 0;
f47c11ee 5152 goto out;
fac9b83e 5153 }
d18edcb2
MC		 5154 }
5155
5156 /*
5157 * Writing any value to intr-mbox-0 clears PCI INTA# and
5158 * chip-internal interrupt pending events.
5159 * Writing non-zero to intr-mbox-0 additional tells the
5160 * NIC to stop sending us irqs, engaging "in-intr-handler"
5161 * event coalescing.
c04cb347
MC		 5162 *
5163 * Flush the mailbox to de-assert the IRQ immediately to prevent
5164 * spurious interrupts. The flush impacts performance but
5165 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5166 */
c04cb347 5167 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5168 if (tg3_irq_sync(tp))
5169 goto out;
5170 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5171 if (likely(tg3_has_work(tnapi))) {
72334482 5172 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5173 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5174 } else {
5175 /* No work, shared interrupt perhaps? re-enable
5176 * interrupts, and flush that PCI write
5177 */
5178 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5179 0x00000000);
fac9b83e 5180 }
f47c11ee 5181out:
fac9b83e
DM		 5182 return IRQ_RETVAL(handled);
5183}
5184
7d12e780 5185static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5186{
09943a18
MC		 5187 struct tg3_napi *tnapi = dev_id;
5188 struct tg3 *tp = tnapi->tp;
898a56f8 5189 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5190 unsigned int handled = 1;
5191
fac9b83e
DM		 5192 /* In INTx mode, it is possible for the interrupt to arrive at
5193 * the CPU before the status block posted prior to the interrupt.
5194 * Reading the PCI State register will confirm whether the
5195 * interrupt is ours and will flush the status block.
5196 */
898a56f8 5197 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5198 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5199 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5200 handled = 0;
f47c11ee 5201 goto out;
1da177e4 5202 }
d18edcb2
MC		 5203 }
5204
5205 /*
5206 * writing any value to intr-mbox-0 clears PCI INTA# and
5207 * chip-internal interrupt pending events.
5208 * writing non-zero to intr-mbox-0 additional tells the
5209 * NIC to stop sending us irqs, engaging "in-intr-handler"
5210 * event coalescing.
c04cb347
MC		 5211 *
5212 * Flush the mailbox to de-assert the IRQ immediately to prevent
5213 * spurious interrupts. The flush impacts performance but
5214 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5215 */
c04cb347 5216 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5217
5218 /*
5219 * In a shared interrupt configuration, sometimes other devices'
5220 * interrupts will scream. We record the current status tag here
5221 * so that the above check can report that the screaming interrupts
5222 * are unhandled. Eventually they will be silenced.
5223 */
898a56f8 5224 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5225
d18edcb2
MC		 5226 if (tg3_irq_sync(tp))
5227 goto out;
624f8e50 5228
72334482 5229 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5230
09943a18 5231 napi_schedule(&tnapi->napi);
624f8e50 5232
f47c11ee 5233out:
1da177e4
LT		 5234 return IRQ_RETVAL(handled);
5235}
5236
7938109f 5237/* ISR for interrupt test */
7d12e780 5238static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5239{
09943a18
MC		 5240 struct tg3_napi *tnapi = dev_id;
5241 struct tg3 *tp = tnapi->tp;
898a56f8 5242 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5243
f9804ddb
MC		 5244 if ((sblk->status & SD_STATUS_UPDATED) ||
5245 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5246 tg3_disable_ints(tp);
7938109f
MC		 5247 return IRQ_RETVAL(1);
5248 }
5249 return IRQ_RETVAL(0);
5250}
5251
8e7a22e3 5252static int tg3_init_hw(struct tg3 *, int);
944d980e 5253static int tg3_halt(struct tg3 *, int, int);
1da177e4 5254
b9ec6c1b
MC		 5255/* Restart hardware after configuration changes, self-test, etc.
5256 * Invoked with tp->lock held.
5257 */
5258static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5259 __releases(tp->lock)
5260 __acquires(tp->lock)
b9ec6c1b
MC		 5261{
5262 int err;
5263
5264 err = tg3_init_hw(tp, reset_phy);
5265 if (err) {
5266 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5267 "aborting.\n", tp->dev->name);
5268 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5269 tg3_full_unlock(tp);
5270 del_timer_sync(&tp->timer);
5271 tp->irq_sync = 0;
fed97810 5272 tg3_napi_enable(tp);
b9ec6c1b
MC		 5273 dev_close(tp->dev);
5274 tg3_full_lock(tp, 0);
5275 }
5276 return err;
5277}
5278
1da177e4
LT		 5279#ifdef CONFIG_NET_POLL_CONTROLLER
5280static void tg3_poll_controller(struct net_device *dev)
5281{
4f125f42 5282 int i;
88b06bc2
MC		 5283 struct tg3 *tp = netdev_priv(dev);
5284
4f125f42
MC		 5285 for (i = 0; i < tp->irq_cnt; i++)
5286 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5287}
5288#endif
5289
c4028958 5290static void tg3_reset_task(struct work_struct *work)
1da177e4 5291{
c4028958 5292 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5293 int err;
1da177e4
LT		 5294 unsigned int restart_timer;
5295
7faa006f 5296 tg3_full_lock(tp, 0);
7faa006f
MC		 5297
5298 if (!netif_running(tp->dev)) {
7faa006f
MC		 5299 tg3_full_unlock(tp);
5300 return;
5301 }
5302
5303 tg3_full_unlock(tp);
5304
b02fd9e3
MC		 5305 tg3_phy_stop(tp);
5306
1da177e4
LT		 5307 tg3_netif_stop(tp);
5308
f47c11ee 5309 tg3_full_lock(tp, 1);
1da177e4
LT		 5310
5311 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5312 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5313
df3e6548
MC		 5314 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5315 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5316 tp->write32_rx_mbox = tg3_write_flush_reg32;
5317 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5318 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5319 }
5320
944d980e 5321 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5322 err = tg3_init_hw(tp, 1);
5323 if (err)
b9ec6c1b 5324 goto out;
1da177e4
LT		 5325
5326 tg3_netif_start(tp);
5327
1da177e4
LT		 5328 if (restart_timer)
5329 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5330
b9ec6c1b 5331out:
7faa006f 5332 tg3_full_unlock(tp);
b02fd9e3
MC		 5333
5334 if (!err)
5335 tg3_phy_start(tp);
1da177e4
LT		 5336}
5337
b0408751
MC		 5338static void tg3_dump_short_state(struct tg3 *tp)
5339{
5340 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5341 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5342 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5343 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5344}
5345
1da177e4
LT		 5346static void tg3_tx_timeout(struct net_device *dev)
5347{
5348 struct tg3 *tp = netdev_priv(dev);
5349
b0408751 5350 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5351 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5352 dev->name);
b0408751
MC		 5353 tg3_dump_short_state(tp);
5354 }
1da177e4
LT		 5355
5356 schedule_work(&tp->reset_task);
5357}
5358
c58ec932
MC		 5359/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5360static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5361{
5362 u32 base = (u32) mapping & 0xffffffff;
5363
5364 return ((base > 0xffffdcc0) &&
5365 (base + len + 8 < base));
5366}
5367
72f2afb8
MC		 5368/* Test for DMA addresses > 40-bit */
5369static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5370 int len)
5371{
5372#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5373 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5374 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5375 return 0;
5376#else
5377 return 0;
5378#endif
5379}
5380
f3f3f27e 5381static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5382
72f2afb8 5383/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5384static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5385 struct sk_buff *skb, u32 last_plus_one,
5386 u32 *start, u32 base_flags, u32 mss)
1da177e4 5387{
24f4efd4 5388 struct tg3 *tp = tnapi->tp;
41588ba1 5389 struct sk_buff *new_skb;
c58ec932 5390 dma_addr_t new_addr = 0;
1da177e4 5391 u32 entry = *start;
c58ec932 5392 int i, ret = 0;
1da177e4 5393
41588ba1
MC		 5394 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5395 new_skb = skb_copy(skb, GFP_ATOMIC);
5396 else {
5397 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5398
5399 new_skb = skb_copy_expand(skb,
5400 skb_headroom(skb) + more_headroom,
5401 skb_tailroom(skb), GFP_ATOMIC);
5402 }
5403
1da177e4 5404 if (!new_skb) {
c58ec932
MC		 5405 ret = -1;
5406 } else {
5407 /* New SKB is guaranteed to be linear. */
5408 entry = *start;
f4188d8a
AD		 5409 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5410 PCI_DMA_TODEVICE);
5411 /* Make sure the mapping succeeded */
5412 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5413 ret = -1;
5414 dev_kfree_skb(new_skb);
5415 new_skb = NULL;
90079ce8 5416
c58ec932
MC		 5417 /* Make sure new skb does not cross any 4G boundaries.
5418 * Drop the packet if it does.
5419 */
f4188d8a
AD		 5420 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5421 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5422 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5423 PCI_DMA_TODEVICE);
c58ec932
MC		 5424 ret = -1;
5425 dev_kfree_skb(new_skb);
5426 new_skb = NULL;
5427 } else {
f3f3f27e 5428 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5429 base_flags, 1 | (mss << 1));
5430 *start = NEXT_TX(entry);
5431 }
1da177e4
LT		 5432 }
5433
1da177e4
LT		 5434 /* Now clean up the sw ring entries. */
5435 i = 0;
5436 while (entry != last_plus_one) {
f4188d8a
AD		 5437 int len;
5438
f3f3f27e 5439 if (i == 0)
f4188d8a 5440 len = skb_headlen(skb);
f3f3f27e 5441 else
f4188d8a
AD		 5442 len = skb_shinfo(skb)->frags[i-1].size;
5443
5444 pci_unmap_single(tp->pdev,
5445 pci_unmap_addr(&tnapi->tx_buffers[entry],
5446 mapping),
5447 len, PCI_DMA_TODEVICE);
5448 if (i == 0) {
5449 tnapi->tx_buffers[entry].skb = new_skb;
5450 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5451 new_addr);
5452 } else {
f3f3f27e 5453 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5454 }
1da177e4
LT		 5455 entry = NEXT_TX(entry);
5456 i++;
5457 }
5458
5459 dev_kfree_skb(skb);
5460
c58ec932 5461 return ret;
1da177e4
LT		 5462}
5463
f3f3f27e 5464static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5465 dma_addr_t mapping, int len, u32 flags,
5466 u32 mss_and_is_end)
5467{
f3f3f27e 5468 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5469 int is_end = (mss_and_is_end & 0x1);
5470 u32 mss = (mss_and_is_end >> 1);
5471 u32 vlan_tag = 0;
5472
5473 if (is_end)
5474 flags |= TXD_FLAG_END;
5475 if (flags & TXD_FLAG_VLAN) {
5476 vlan_tag = flags >> 16;
5477 flags &= 0xffff;
5478 }
5479 vlan_tag |= (mss << TXD_MSS_SHIFT);
5480
5481 txd->addr_hi = ((u64) mapping >> 32);
5482 txd->addr_lo = ((u64) mapping & 0xffffffff);
5483 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5484 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5485}
5486
5a6f3074 5487/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5488 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5489 */
61357325
SH		 5490static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5491 struct net_device *dev)
5a6f3074
MC		 5492{
5493 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5494 u32 len, entry, base_flags, mss;
90079ce8 5495 dma_addr_t mapping;
fe5f5787
MC		 5496 struct tg3_napi *tnapi;
5497 struct netdev_queue *txq;
f4188d8a
AD		 5498 unsigned int i, last;
5499
5a6f3074 5500
fe5f5787
MC		 5501 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5502 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5503 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5504 tnapi++;
5a6f3074 5505
00b70504 5506 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5507 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5508 * interrupt. Furthermore, IRQ processing runs lockless so we have
5509 * no IRQ context deadlocks to worry about either. Rejoice!
5510 */
f3f3f27e 5511 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5512 if (!netif_tx_queue_stopped(txq)) {
5513 netif_tx_stop_queue(txq);
5a6f3074
MC		 5514
5515 /* This is a hard error, log it. */
5516 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5517 "queue awake!\n", dev->name);
5518 }
5a6f3074
MC		 5519 return NETDEV_TX_BUSY;
5520 }
5521
f3f3f27e 5522 entry = tnapi->tx_prod;
5a6f3074 5523 base_flags = 0;
5a6f3074 5524 mss = 0;
c13e3713 5525 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5526 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5527 u32 hdrlen;
5a6f3074
MC		 5528
5529 if (skb_header_cloned(skb) &&
5530 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5531 dev_kfree_skb(skb);
5532 goto out_unlock;
5533 }
5534
b0026624 5535 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5536 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5537 else {
eddc9ec5
ACM		 5538 struct iphdr *iph = ip_hdr(skb);
5539
ab6a5bb6 5540 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5541 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5542
eddc9ec5
ACM		 5543 iph->check = 0;
5544 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5545 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5546 }
5a6f3074 5547
e849cdc3 5548 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5549 mss |= (hdrlen & 0xc) << 12;
5550 if (hdrlen & 0x10)
5551 base_flags |= 0x00000010;
5552 base_flags |= (hdrlen & 0x3e0) << 5;
5553 } else
5554 mss |= hdrlen << 9;
5555
5a6f3074
MC		 5556 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5557 TXD_FLAG_CPU_POST_DMA);
5558
aa8223c7 5559 tcp_hdr(skb)->check = 0;
5a6f3074 5560
5a6f3074 5561 }
84fa7933 5562 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5563 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5564#if TG3_VLAN_TAG_USED
5565 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5566 base_flags |= (TXD_FLAG_VLAN |
5567 (vlan_tx_tag_get(skb) << 16));
5568#endif
5569
f4188d8a
AD		 5570 len = skb_headlen(skb);
5571
5572 /* Queue skb data, a.k.a. the main skb fragment. */
5573 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5574 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5575 dev_kfree_skb(skb);
5576 goto out_unlock;
5577 }
5578
f3f3f27e 5579 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5580 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5581
b703df6f 5582 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5583 !mss && skb->len > ETH_DATA_LEN)
5584 base_flags |= TXD_FLAG_JMB_PKT;
5585
f3f3f27e 5586 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5587 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5588
5589 entry = NEXT_TX(entry);
5590
5591 /* Now loop through additional data fragments, and queue them. */
5592 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5593 last = skb_shinfo(skb)->nr_frags - 1;
5594 for (i = 0; i <= last; i++) {
5595 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5596
5597 len = frag->size;
f4188d8a
AD		 5598 mapping = pci_map_page(tp->pdev,
5599 frag->page,
5600 frag->page_offset,
5601 len, PCI_DMA_TODEVICE);
5602 if (pci_dma_mapping_error(tp->pdev, mapping))
5603 goto dma_error;
5604
f3f3f27e 5605 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5606 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5607 mapping);
5a6f3074 5608
f3f3f27e 5609 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5610 base_flags, (i == last) | (mss << 1));
5611
5612 entry = NEXT_TX(entry);
5613 }
5614 }
5615
5616 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5617 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5618
f3f3f27e
MC		 5619 tnapi->tx_prod = entry;
5620 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5621 netif_tx_stop_queue(txq);
f3f3f27e 5622 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5623 netif_tx_wake_queue(txq);
5a6f3074
MC		 5624 }
5625
5626out_unlock:
cdd0db05 5627 mmiowb();
5a6f3074
MC		 5628
5629 return NETDEV_TX_OK;
f4188d8a
AD		 5630
5631dma_error:
5632 last = i;
5633 entry = tnapi->tx_prod;
5634 tnapi->tx_buffers[entry].skb = NULL;
5635 pci_unmap_single(tp->pdev,
5636 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5637 skb_headlen(skb),
5638 PCI_DMA_TODEVICE);
5639 for (i = 0; i <= last; i++) {
5640 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5641 entry = NEXT_TX(entry);
5642
5643 pci_unmap_page(tp->pdev,
5644 pci_unmap_addr(&tnapi->tx_buffers[entry],
5645 mapping),
5646 frag->size, PCI_DMA_TODEVICE);
5647 }
5648
5649 dev_kfree_skb(skb);
5650 return NETDEV_TX_OK;
5a6f3074
MC		 5651}
5652
61357325
SH		 5653static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5654 struct net_device *);
52c0fd83
MC		 5655
5656/* Use GSO to workaround a rare TSO bug that may be triggered when the
5657 * TSO header is greater than 80 bytes.
5658 */
5659static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5660{
5661 struct sk_buff *segs, *nskb;
f3f3f27e 5662 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5663
5664 /* Estimate the number of fragments in the worst case */
f3f3f27e 5665 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5666 netif_stop_queue(tp->dev);
f3f3f27e 5667 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5668 return NETDEV_TX_BUSY;
5669
5670 netif_wake_queue(tp->dev);
52c0fd83
MC		 5671 }
5672
5673 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5674 if (IS_ERR(segs))
52c0fd83
MC		 5675 goto tg3_tso_bug_end;
5676
5677 do {
5678 nskb = segs;
5679 segs = segs->next;
5680 nskb->next = NULL;
5681 tg3_start_xmit_dma_bug(nskb, tp->dev);
5682 } while (segs);
5683
5684tg3_tso_bug_end:
5685 dev_kfree_skb(skb);
5686
5687 return NETDEV_TX_OK;
5688}
52c0fd83 5689
5a6f3074
MC		 5690/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5691 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5692 */
61357325
SH		 5693static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5694 struct net_device *dev)
1da177e4
LT		 5695{
5696 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5697 u32 len, entry, base_flags, mss;
5698 int would_hit_hwbug;
90079ce8 5699 dma_addr_t mapping;
24f4efd4
MC		 5700 struct tg3_napi *tnapi;
5701 struct netdev_queue *txq;
f4188d8a
AD		 5702 unsigned int i, last;
5703
1da177e4 5704
24f4efd4
MC		 5705 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5706 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5707 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5708 tnapi++;
1da177e4 5709
00b70504 5710 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5711 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5712 * interrupt. Furthermore, IRQ processing runs lockless so we have
5713 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5714 */
f3f3f27e 5715 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5716 if (!netif_tx_queue_stopped(txq)) {
5717 netif_tx_stop_queue(txq);
1f064a87
SH		 5718
5719 /* This is a hard error, log it. */
5720 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5721 "queue awake!\n", dev->name);
5722 }
1da177e4
LT		 5723 return NETDEV_TX_BUSY;
5724 }
5725
f3f3f27e 5726 entry = tnapi->tx_prod;
1da177e4 5727 base_flags = 0;
84fa7933 5728 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5729 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5730
c13e3713 5731 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5732 struct iphdr *iph;
92c6b8d1 5733 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5734
5735 if (skb_header_cloned(skb) &&
5736 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5737 dev_kfree_skb(skb);
5738 goto out_unlock;
5739 }
5740
ab6a5bb6 5741 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5742 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5743
52c0fd83
MC		 5744 hdr_len = ip_tcp_len + tcp_opt_len;
5745 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5746 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5747 return (tg3_tso_bug(tp, skb));
5748
1da177e4
LT		 5749 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5750 TXD_FLAG_CPU_POST_DMA);
5751
eddc9ec5
ACM		 5752 iph = ip_hdr(skb);
5753 iph->check = 0;
5754 iph->tot_len = htons(mss + hdr_len);
1da177e4 5755 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5756 tcp_hdr(skb)->check = 0;
1da177e4 5757 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5758 } else
5759 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5760 iph->daddr, 0,
5761 IPPROTO_TCP,
5762 0);
1da177e4 5763
615774fe
MC		 5764 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5765 mss |= (hdr_len & 0xc) << 12;
5766 if (hdr_len & 0x10)
5767 base_flags |= 0x00000010;
5768 base_flags |= (hdr_len & 0x3e0) << 5;
5769 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5770 mss |= hdr_len << 9;
5771 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5773 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5774 int tsflags;
5775
eddc9ec5 5776 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5777 mss |= (tsflags << 11);
5778 }
5779 } else {
eddc9ec5 5780 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5781 int tsflags;
5782
eddc9ec5 5783 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5784 base_flags |= tsflags << 12;
5785 }
5786 }
5787 }
1da177e4
LT		 5788#if TG3_VLAN_TAG_USED
5789 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5790 base_flags |= (TXD_FLAG_VLAN |
5791 (vlan_tx_tag_get(skb) << 16));
5792#endif
5793
b703df6f 5794 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5795 !mss && skb->len > ETH_DATA_LEN)
5796 base_flags |= TXD_FLAG_JMB_PKT;
5797
f4188d8a
AD		 5798 len = skb_headlen(skb);
5799
5800 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5801 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5802 dev_kfree_skb(skb);
5803 goto out_unlock;
5804 }
5805
f3f3f27e 5806 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5807 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5808
5809 would_hit_hwbug = 0;
5810
92c6b8d1
MC		 5811 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5812 would_hit_hwbug = 1;
5813
0e1406dd
MC		 5814 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5815 tg3_4g_overflow_test(mapping, len))
5816 would_hit_hwbug = 1;
5817
5818 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5819 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5820 would_hit_hwbug = 1;
0e1406dd
MC		 5821
5822 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5823 would_hit_hwbug = 1;
1da177e4 5824
f3f3f27e 5825 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5826 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5827
5828 entry = NEXT_TX(entry);
5829
5830 /* Now loop through additional data fragments, and queue them. */
5831 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5832 last = skb_shinfo(skb)->nr_frags - 1;
5833 for (i = 0; i <= last; i++) {
5834 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5835
5836 len = frag->size;
f4188d8a
AD		 5837 mapping = pci_map_page(tp->pdev,
5838 frag->page,
5839 frag->page_offset,
5840 len, PCI_DMA_TODEVICE);
1da177e4 5841
f3f3f27e 5842 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5843 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5844 mapping);
5845 if (pci_dma_mapping_error(tp->pdev, mapping))
5846 goto dma_error;
1da177e4 5847
92c6b8d1
MC		 5848 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5849 len <= 8)
5850 would_hit_hwbug = 1;
5851
0e1406dd
MC		 5852 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5853 tg3_4g_overflow_test(mapping, len))
c58ec932 5854 would_hit_hwbug = 1;
1da177e4 5855
0e1406dd
MC		 5856 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5857 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5858 would_hit_hwbug = 1;
5859
1da177e4 5860 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5861 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5862 base_flags, (i == last)|(mss << 1));
5863 else
f3f3f27e 5864 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5865 base_flags, (i == last));
5866
5867 entry = NEXT_TX(entry);
5868 }
5869 }
5870
5871 if (would_hit_hwbug) {
5872 u32 last_plus_one = entry;
5873 u32 start;
1da177e4 5874
c58ec932
MC		 5875 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5876 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5877
5878 /* If the workaround fails due to memory/mapping
5879 * failure, silently drop this packet.
5880 */
24f4efd4 5881 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5882 &start, base_flags, mss))
1da177e4
LT		 5883 goto out_unlock;
5884
5885 entry = start;
5886 }
5887
5888 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5889 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5890
f3f3f27e
MC		 5891 tnapi->tx_prod = entry;
5892 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5893 netif_tx_stop_queue(txq);
f3f3f27e 5894 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5895 netif_tx_wake_queue(txq);
51b91468 5896 }
1da177e4
LT		 5897
5898out_unlock:
cdd0db05 5899 mmiowb();
1da177e4
LT		 5900
5901 return NETDEV_TX_OK;
f4188d8a
AD		 5902
5903dma_error:
5904 last = i;
5905 entry = tnapi->tx_prod;
5906 tnapi->tx_buffers[entry].skb = NULL;
5907 pci_unmap_single(tp->pdev,
5908 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5909 skb_headlen(skb),
5910 PCI_DMA_TODEVICE);
5911 for (i = 0; i <= last; i++) {
5912 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5913 entry = NEXT_TX(entry);
5914
5915 pci_unmap_page(tp->pdev,
5916 pci_unmap_addr(&tnapi->tx_buffers[entry],
5917 mapping),
5918 frag->size, PCI_DMA_TODEVICE);
5919 }
5920
5921 dev_kfree_skb(skb);
5922 return NETDEV_TX_OK;
1da177e4
LT		 5923}
5924
5925static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5926 int new_mtu)
5927{
5928 dev->mtu = new_mtu;
5929
ef7f5ec0 5930 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5931 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5932 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5933 ethtool_op_set_tso(dev, 0);
5934 }
5935 else
5936 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5937 } else {
a4e2b347 5938 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5939 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5940 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5941 }
1da177e4
LT		 5942}
5943
5944static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5945{
5946 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5947 int err;
1da177e4
LT		 5948
5949 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5950 return -EINVAL;
5951
5952 if (!netif_running(dev)) {
5953 /* We'll just catch it later when the
5954 * device is up'd.
5955 */
5956 tg3_set_mtu(dev, tp, new_mtu);
5957 return 0;
5958 }
5959
b02fd9e3
MC		 5960 tg3_phy_stop(tp);
5961
1da177e4 5962 tg3_netif_stop(tp);
f47c11ee
DM		 5963
5964 tg3_full_lock(tp, 1);
1da177e4 5965
944d980e 5966 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5967
5968 tg3_set_mtu(dev, tp, new_mtu);
5969
b9ec6c1b 5970 err = tg3_restart_hw(tp, 0);
1da177e4 5971
b9ec6c1b
MC		 5972 if (!err)
5973 tg3_netif_start(tp);
1da177e4 5974
f47c11ee 5975 tg3_full_unlock(tp);
1da177e4 5976
b02fd9e3
MC		 5977 if (!err)
5978 tg3_phy_start(tp);
5979
b9ec6c1b 5980 return err;
1da177e4
LT		 5981}
5982
21f581a5
MC		 5983static void tg3_rx_prodring_free(struct tg3 *tp,
5984 struct tg3_rx_prodring_set *tpr)
1da177e4 5985{
1da177e4
LT		 5986 int i;
5987
b196c7e4
MC		 5988 if (tpr != &tp->prodring[0]) {
5989 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5990 i = (i + 1) % TG3_RX_RING_SIZE)
5991 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5992 tp->rx_pkt_map_sz);
5993
5994 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5995 for (i = tpr->rx_jmb_cons_idx;
5996 i != tpr->rx_jmb_prod_idx;
5997 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5998 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5999 TG3_RX_JMB_MAP_SZ);
6000 }
6001 }
6002
2b2cdb65 6003 return;
b196c7e4 6004 }
1da177e4 6005
2b2cdb65
MC		 6006 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6007 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6008 tp->rx_pkt_map_sz);
1da177e4 6009
cf7a7298 6010 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 6011 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6012 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6013 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 6014 }
6015}
6016
6017/* Initialize tx/rx rings for packet processing.
6018 *
6019 * The chip has been shut down and the driver detached from
6020 * the networking, so no interrupts or new tx packets will
6021 * end up in the driver. tp->{tx,}lock are held and thus
6022 * we may not sleep.
6023 */
21f581a5
MC		 6024static int tg3_rx_prodring_alloc(struct tg3 *tp,
6025 struct tg3_rx_prodring_set *tpr)
1da177e4 6026{
287be12e 6027 u32 i, rx_pkt_dma_sz;
1da177e4 6028
b196c7e4
MC		 6029 tpr->rx_std_cons_idx = 0;
6030 tpr->rx_std_prod_idx = 0;
6031 tpr->rx_jmb_cons_idx = 0;
6032 tpr->rx_jmb_prod_idx = 0;
6033
2b2cdb65
MC		 6034 if (tpr != &tp->prodring[0]) {
6035 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6036 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6037 memset(&tpr->rx_jmb_buffers[0], 0,
6038 TG3_RX_JMB_BUFF_RING_SIZE);
6039 goto done;
6040 }
6041
1da177e4 6042 /* Zero out all descriptors. */
21f581a5 6043 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 6044
287be12e 6045 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 6046 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 6047 tp->dev->mtu > ETH_DATA_LEN)
6048 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6049 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 6050
1da177e4
LT		 6051 /* Initialize invariants of the rings, we only set this
6052 * stuff once. This works because the card does not
6053 * write into the rx buffer posting rings.
6054 */
6055 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6056 struct tg3_rx_buffer_desc *rxd;
6057
21f581a5 6058 rxd = &tpr->rx_std[i];
287be12e 6059 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6060 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6061 rxd->opaque = (RXD_OPAQUE_RING_STD |
6062 (i << RXD_OPAQUE_INDEX_SHIFT));
6063 }
6064
1da177e4
LT		 6065 /* Now allocate fresh SKBs for each rx ring. */
6066 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6067 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6068 printk(KERN_WARNING PFX
6069 "%s: Using a smaller RX standard ring, "
6070 "only %d out of %d buffers were allocated "
6071 "successfully.\n",
6072 tp->dev->name, i, tp->rx_pending);
6073 if (i == 0)
cf7a7298 6074 goto initfail;
32d8c572 6075 tp->rx_pending = i;
1da177e4 6076 break;
32d8c572 6077 }
1da177e4
LT		 6078 }
6079
cf7a7298
MC		 6080 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6081 goto done;
6082
21f581a5 6083 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6084
0f893dc6 6085 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6086 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6087 struct tg3_rx_buffer_desc *rxd;
6088
79ed5ac7 6089 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6090 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6091 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6092 RXD_FLAG_JUMBO;
6093 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6094 (i << RXD_OPAQUE_INDEX_SHIFT));
6095 }
6096
1da177e4 6097 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6098 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6099 i) < 0) {
32d8c572
MC		 6100 printk(KERN_WARNING PFX
6101 "%s: Using a smaller RX jumbo ring, "
6102 "only %d out of %d buffers were "
6103 "allocated successfully.\n",
6104 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6105 if (i == 0)
6106 goto initfail;
32d8c572 6107 tp->rx_jumbo_pending = i;
1da177e4 6108 break;
32d8c572 6109 }
1da177e4
LT		 6110 }
6111 }
cf7a7298
MC		 6112
6113done:
32d8c572 6114 return 0;
cf7a7298
MC		 6115
6116initfail:
21f581a5 6117 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6118 return -ENOMEM;
1da177e4
LT		 6119}
6120
21f581a5
MC		 6121static void tg3_rx_prodring_fini(struct tg3 *tp,
6122 struct tg3_rx_prodring_set *tpr)
1da177e4 6123{
21f581a5
MC		 6124 kfree(tpr->rx_std_buffers);
6125 tpr->rx_std_buffers = NULL;
6126 kfree(tpr->rx_jmb_buffers);
6127 tpr->rx_jmb_buffers = NULL;
6128 if (tpr->rx_std) {
1da177e4 6129 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6130 tpr->rx_std, tpr->rx_std_mapping);
6131 tpr->rx_std = NULL;
1da177e4 6132 }
21f581a5 6133 if (tpr->rx_jmb) {
1da177e4 6134 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6135 tpr->rx_jmb, tpr->rx_jmb_mapping);
6136 tpr->rx_jmb = NULL;
1da177e4 6137 }
cf7a7298
MC		 6138}
6139
21f581a5
MC		 6140static int tg3_rx_prodring_init(struct tg3 *tp,
6141 struct tg3_rx_prodring_set *tpr)
cf7a7298 6142{
2b2cdb65 6143 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6144 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6145 return -ENOMEM;
6146
21f581a5
MC		 6147 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6148 &tpr->rx_std_mapping);
6149 if (!tpr->rx_std)
cf7a7298
MC		 6150 goto err_out;
6151
6152 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6153 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6154 GFP_KERNEL);
6155 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6156 goto err_out;
6157
21f581a5
MC		 6158 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6159 TG3_RX_JUMBO_RING_BYTES,
6160 &tpr->rx_jmb_mapping);
6161 if (!tpr->rx_jmb)
cf7a7298
MC		 6162 goto err_out;
6163 }
6164
6165 return 0;
6166
6167err_out:
21f581a5 6168 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6169 return -ENOMEM;
6170}
6171
6172/* Free up pending packets in all rx/tx rings.
6173 *
6174 * The chip has been shut down and the driver detached from
6175 * the networking, so no interrupts or new tx packets will
6176 * end up in the driver. tp->{tx,}lock is not held and we are not
6177 * in an interrupt context and thus may sleep.
6178 */
6179static void tg3_free_rings(struct tg3 *tp)
6180{
f77a6a8e 6181 int i, j;
cf7a7298 6182
f77a6a8e
MC		 6183 for (j = 0; j < tp->irq_cnt; j++) {
6184 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6185
0c1d0e2b
MC		 6186 if (!tnapi->tx_buffers)
6187 continue;
6188
f77a6a8e 6189 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6190 struct ring_info *txp;
f77a6a8e 6191 struct sk_buff *skb;
f4188d8a 6192 unsigned int k;
cf7a7298 6193
f77a6a8e
MC		 6194 txp = &tnapi->tx_buffers[i];
6195 skb = txp->skb;
cf7a7298 6196
f77a6a8e
MC		 6197 if (skb == NULL) {
6198 i++;
6199 continue;
6200 }
cf7a7298 6201
f4188d8a
AD		 6202 pci_unmap_single(tp->pdev,
6203 pci_unmap_addr(txp, mapping),
6204 skb_headlen(skb),
6205 PCI_DMA_TODEVICE);
f77a6a8e 6206 txp->skb = NULL;
cf7a7298 6207
f4188d8a
AD		 6208 i++;
6209
6210 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6211 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6212 pci_unmap_page(tp->pdev,
6213 pci_unmap_addr(txp, mapping),
6214 skb_shinfo(skb)->frags[k].size,
6215 PCI_DMA_TODEVICE);
6216 i++;
6217 }
f77a6a8e
MC		 6218
6219 dev_kfree_skb_any(skb);
6220 }
cf7a7298 6221
e4af1af9 6222 tg3_rx_prodring_free(tp, &tp->prodring[j]);
2b2cdb65 6223 }
cf7a7298
MC		 6224}
6225
6226/* Initialize tx/rx rings for packet processing.
6227 *
6228 * The chip has been shut down and the driver detached from
6229 * the networking, so no interrupts or new tx packets will
6230 * end up in the driver. tp->{tx,}lock are held and thus
6231 * we may not sleep.
6232 */
6233static int tg3_init_rings(struct tg3 *tp)
6234{
f77a6a8e 6235 int i;
72334482 6236
cf7a7298
MC		 6237 /* Free up all the SKBs. */
6238 tg3_free_rings(tp);
6239
f77a6a8e
MC		 6240 for (i = 0; i < tp->irq_cnt; i++) {
6241 struct tg3_napi *tnapi = &tp->napi[i];
6242
6243 tnapi->last_tag = 0;
6244 tnapi->last_irq_tag = 0;
6245 tnapi->hw_status->status = 0;
6246 tnapi->hw_status->status_tag = 0;
6247 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6248
f77a6a8e
MC		 6249 tnapi->tx_prod = 0;
6250 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6251 if (tnapi->tx_ring)
6252 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6253
6254 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6255 if (tnapi->rx_rcb)
6256 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 6257
e4af1af9
MC		 6258 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6259 tg3_free_rings(tp);
2b2cdb65 6260 return -ENOMEM;
e4af1af9 6261 }
f77a6a8e 6262 }
72334482 6263
2b2cdb65 6264 return 0;
cf7a7298
MC		 6265}
6266
6267/*
6268 * Must not be invoked with interrupt sources disabled and
6269 * the hardware shutdown down.
6270 */
6271static void tg3_free_consistent(struct tg3 *tp)
6272{
f77a6a8e 6273 int i;
898a56f8 6274
f77a6a8e
MC		 6275 for (i = 0; i < tp->irq_cnt; i++) {
6276 struct tg3_napi *tnapi = &tp->napi[i];
6277
6278 if (tnapi->tx_ring) {
6279 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6280 tnapi->tx_ring, tnapi->tx_desc_mapping);
6281 tnapi->tx_ring = NULL;
6282 }
6283
6284 kfree(tnapi->tx_buffers);
6285 tnapi->tx_buffers = NULL;
6286
6287 if (tnapi->rx_rcb) {
6288 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6289 tnapi->rx_rcb,
6290 tnapi->rx_rcb_mapping);
6291 tnapi->rx_rcb = NULL;
6292 }
6293
6294 if (tnapi->hw_status) {
6295 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6296 tnapi->hw_status,
6297 tnapi->status_mapping);
6298 tnapi->hw_status = NULL;
6299 }
1da177e4 6300 }
f77a6a8e 6301
1da177e4
LT		 6302 if (tp->hw_stats) {
6303 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6304 tp->hw_stats, tp->stats_mapping);
6305 tp->hw_stats = NULL;
6306 }
f77a6a8e 6307
e4af1af9 6308 for (i = 0; i < tp->irq_cnt; i++)
2b2cdb65 6309 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6310}
6311
6312/*
6313 * Must not be invoked with interrupt sources disabled and
6314 * the hardware shutdown down. Can sleep.
6315 */
6316static int tg3_alloc_consistent(struct tg3 *tp)
6317{
f77a6a8e 6318 int i;
898a56f8 6319
e4af1af9 6320 for (i = 0; i < tp->irq_cnt; i++) {
2b2cdb65
MC		 6321 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6322 goto err_out;
6323 }
1da177e4 6324
f77a6a8e
MC		 6325 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6326 sizeof(struct tg3_hw_stats),
6327 &tp->stats_mapping);
6328 if (!tp->hw_stats)
1da177e4
LT		 6329 goto err_out;
6330
f77a6a8e 6331 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6332
f77a6a8e
MC		 6333 for (i = 0; i < tp->irq_cnt; i++) {
6334 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6335 struct tg3_hw_status *sblk;
1da177e4 6336
f77a6a8e
MC		 6337 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6338 TG3_HW_STATUS_SIZE,
6339 &tnapi->status_mapping);
6340 if (!tnapi->hw_status)
6341 goto err_out;
898a56f8 6342
f77a6a8e 6343 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6344 sblk = tnapi->hw_status;
6345
19cfaecc
MC		 6346 /* If multivector TSS is enabled, vector 0 does not handle
6347 * tx interrupts. Don't allocate any resources for it.
6348 */
6349 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6350 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6351 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6352 TG3_TX_RING_SIZE,
6353 GFP_KERNEL);
6354 if (!tnapi->tx_buffers)
6355 goto err_out;
6356
6357 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6358 TG3_TX_RING_BYTES,
6359 &tnapi->tx_desc_mapping);
6360 if (!tnapi->tx_ring)
6361 goto err_out;
6362 }
6363
8d9d7cfc
MC		 6364 /*
6365 * When RSS is enabled, the status block format changes
6366 * slightly. The "rx_jumbo_consumer", "reserved",
6367 * and "rx_mini_consumer" members get mapped to the
6368 * other three rx return ring producer indexes.
6369 */
6370 switch (i) {
6371 default:
6372 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6373 break;
6374 case 2:
6375 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6376 break;
6377 case 3:
6378 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6379 break;
6380 case 4:
6381 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6382 break;
6383 }
72334482 6384
e4af1af9 6385 tnapi->prodring = &tp->prodring[i];
b196c7e4 6386
0c1d0e2b
MC		 6387 /*
6388 * If multivector RSS is enabled, vector 0 does not handle
6389 * rx or tx interrupts. Don't allocate any resources for it.
6390 */
6391 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6392 continue;
6393
f77a6a8e
MC		 6394 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6395 TG3_RX_RCB_RING_BYTES(tp),
6396 &tnapi->rx_rcb_mapping);
6397 if (!tnapi->rx_rcb)
6398 goto err_out;
72334482 6399
f77a6a8e 6400 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6401 }
1da177e4
LT		 6402
6403 return 0;
6404
6405err_out:
6406 tg3_free_consistent(tp);
6407 return -ENOMEM;
6408}
6409
6410#define MAX_WAIT_CNT 1000
6411
6412/* To stop a block, clear the enable bit and poll till it
6413 * clears. tp->lock is held.
6414 */
b3b7d6be 6415static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6416{
6417 unsigned int i;
6418 u32 val;
6419
6420 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6421 switch (ofs) {
6422 case RCVLSC_MODE:
6423 case DMAC_MODE:
6424 case MBFREE_MODE:
6425 case BUFMGR_MODE:
6426 case MEMARB_MODE:
6427 /* We can't enable/disable these bits of the
6428 * 5705/5750, just say success.
6429 */
6430 return 0;
6431
6432 default:
6433 break;
855e1111 6434 }
1da177e4
LT		 6435 }
6436
6437 val = tr32(ofs);
6438 val &= ~enable_bit;
6439 tw32_f(ofs, val);
6440
6441 for (i = 0; i < MAX_WAIT_CNT; i++) {
6442 udelay(100);
6443 val = tr32(ofs);
6444 if ((val & enable_bit) == 0)
6445 break;
6446 }
6447
b3b7d6be 6448 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6449 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6450 "ofs=%lx enable_bit=%x\n",
6451 ofs, enable_bit);
6452 return -ENODEV;
6453 }
6454
6455 return 0;
6456}
6457
6458/* tp->lock is held. */
b3b7d6be 6459static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6460{
6461 int i, err;
6462
6463 tg3_disable_ints(tp);
6464
6465 tp->rx_mode &= ~RX_MODE_ENABLE;
6466 tw32_f(MAC_RX_MODE, tp->rx_mode);
6467 udelay(10);
6468
b3b7d6be
DM		 6469 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6470 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6471 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6472 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6473 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6474 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6475
6476 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6480 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6481 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6482 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6483
6484 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6485 tw32_f(MAC_MODE, tp->mac_mode);
6486 udelay(40);
6487
6488 tp->tx_mode &= ~TX_MODE_ENABLE;
6489 tw32_f(MAC_TX_MODE, tp->tx_mode);
6490
6491 for (i = 0; i < MAX_WAIT_CNT; i++) {
6492 udelay(100);
6493 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6494 break;
6495 }
6496 if (i >= MAX_WAIT_CNT) {
6497 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6498 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6499 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6500 err |= -ENODEV;
1da177e4
LT		 6501 }
6502
e6de8ad1 6503 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6504 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6505 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6506
6507 tw32(FTQ_RESET, 0xffffffff);
6508 tw32(FTQ_RESET, 0x00000000);
6509
b3b7d6be
DM		 6510 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6511 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6512
f77a6a8e
MC		 6513 for (i = 0; i < tp->irq_cnt; i++) {
6514 struct tg3_napi *tnapi = &tp->napi[i];
6515 if (tnapi->hw_status)
6516 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6517 }
1da177e4
LT		 6518 if (tp->hw_stats)
6519 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6520
1da177e4
LT		 6521 return err;
6522}
6523
0d3031d9
MC		 6524static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6525{
6526 int i;
6527 u32 apedata;
6528
6529 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6530 if (apedata != APE_SEG_SIG_MAGIC)
6531 return;
6532
6533 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6534 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6535 return;
6536
6537 /* Wait for up to 1 millisecond for APE to service previous event. */
6538 for (i = 0; i < 10; i++) {
6539 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6540 return;
6541
6542 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6543
6544 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6545 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6546 event | APE_EVENT_STATUS_EVENT_PENDING);
6547
6548 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6549
6550 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6551 break;
6552
6553 udelay(100);
6554 }
6555
6556 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6557 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6558}
6559
6560static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6561{
6562 u32 event;
6563 u32 apedata;
6564
6565 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6566 return;
6567
6568 switch (kind) {
6569 case RESET_KIND_INIT:
6570 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6571 APE_HOST_SEG_SIG_MAGIC);
6572 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6573 APE_HOST_SEG_LEN_MAGIC);
6574 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6575 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6576 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6577 APE_HOST_DRIVER_ID_MAGIC);
6578 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6579 APE_HOST_BEHAV_NO_PHYLOCK);
6580
6581 event = APE_EVENT_STATUS_STATE_START;
6582 break;
6583 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6584 /* With the interface we are currently using,
6585 * APE does not track driver state. Wiping
6586 * out the HOST SEGMENT SIGNATURE forces
6587 * the APE to assume OS absent status.
6588 */
6589 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6590
0d3031d9
MC		 6591 event = APE_EVENT_STATUS_STATE_UNLOAD;
6592 break;
6593 case RESET_KIND_SUSPEND:
6594 event = APE_EVENT_STATUS_STATE_SUSPEND;
6595 break;
6596 default:
6597 return;
6598 }
6599
6600 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6601
6602 tg3_ape_send_event(tp, event);
6603}
6604
1da177e4
LT		 6605/* tp->lock is held. */
6606static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6607{
f49639e6
DM		 6608 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6609 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6610
6611 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6612 switch (kind) {
6613 case RESET_KIND_INIT:
6614 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6615 DRV_STATE_START);
6616 break;
6617
6618 case RESET_KIND_SHUTDOWN:
6619 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6620 DRV_STATE_UNLOAD);
6621 break;
6622
6623 case RESET_KIND_SUSPEND:
6624 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6625 DRV_STATE_SUSPEND);
6626 break;
6627
6628 default:
6629 break;
855e1111 6630 }
1da177e4 6631 }
0d3031d9
MC		 6632
6633 if (kind == RESET_KIND_INIT ||
6634 kind == RESET_KIND_SUSPEND)
6635 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6636}
6637
6638/* tp->lock is held. */
6639static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6640{
6641 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6642 switch (kind) {
6643 case RESET_KIND_INIT:
6644 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6645 DRV_STATE_START_DONE);
6646 break;
6647
6648 case RESET_KIND_SHUTDOWN:
6649 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6650 DRV_STATE_UNLOAD_DONE);
6651 break;
6652
6653 default:
6654 break;
855e1111 6655 }
1da177e4 6656 }
0d3031d9
MC		 6657
6658 if (kind == RESET_KIND_SHUTDOWN)
6659 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6660}
6661
6662/* tp->lock is held. */
6663static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6664{
6665 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6666 switch (kind) {
6667 case RESET_KIND_INIT:
6668 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6669 DRV_STATE_START);
6670 break;
6671
6672 case RESET_KIND_SHUTDOWN:
6673 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6674 DRV_STATE_UNLOAD);
6675 break;
6676
6677 case RESET_KIND_SUSPEND:
6678 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6679 DRV_STATE_SUSPEND);
6680 break;
6681
6682 default:
6683 break;
855e1111 6684 }
1da177e4
LT		 6685 }
6686}
6687
7a6f4369
MC		 6688static int tg3_poll_fw(struct tg3 *tp)
6689{
6690 int i;
6691 u32 val;
6692
b5d3772c 6693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6694 /* Wait up to 20ms for init done. */
6695 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6696 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6697 return 0;
0ccead18 6698 udelay(100);
b5d3772c
MC		 6699 }
6700 return -ENODEV;
6701 }
6702
7a6f4369
MC		 6703 /* Wait for firmware initialization to complete. */
6704 for (i = 0; i < 100000; i++) {
6705 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6706 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6707 break;
6708 udelay(10);
6709 }
6710
6711 /* Chip might not be fitted with firmware. Some Sun onboard
6712 * parts are configured like that. So don't signal the timeout
6713 * of the above loop as an error, but do report the lack of
6714 * running firmware once.
6715 */
6716 if (i >= 100000 &&
6717 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6718 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6719
6720 printk(KERN_INFO PFX "%s: No firmware running.\n",
6721 tp->dev->name);
6722 }
6723
6b10c165
MC		 6724 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6725 /* The 57765 A0 needs a little more
6726 * time to do some important work.
6727 */
6728 mdelay(10);
6729 }
6730
7a6f4369
MC		 6731 return 0;
6732}
6733
ee6a99b5
MC		 6734/* Save PCI command register before chip reset */
6735static void tg3_save_pci_state(struct tg3 *tp)
6736{
8a6eac90 6737 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6738}
6739
6740/* Restore PCI state after chip reset */
6741static void tg3_restore_pci_state(struct tg3 *tp)
6742{
6743 u32 val;
6744
6745 /* Re-enable indirect register accesses. */
6746 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6747 tp->misc_host_ctrl);
6748
6749 /* Set MAX PCI retry to zero. */
6750 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6751 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6752 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6753 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6754 /* Allow reads and writes to the APE register and memory space. */
6755 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6756 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6757 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6758 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6759
8a6eac90 6760 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6761
fcb389df
MC		 6762 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6763 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6764 pcie_set_readrq(tp->pdev, 4096);
6765 else {
6766 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6767 tp->pci_cacheline_sz);
6768 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6769 tp->pci_lat_timer);
6770 }
114342f2 6771 }
5f5c51e3 6772
ee6a99b5 6773 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6774 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6775 u16 pcix_cmd;
6776
6777 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6778 &pcix_cmd);
6779 pcix_cmd &= ~PCI_X_CMD_ERO;
6780 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6781 pcix_cmd);
6782 }
ee6a99b5
MC		 6783
6784 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6785
6786 /* Chip reset on 5780 will reset MSI enable bit,
6787 * so need to restore it.
6788 */
6789 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6790 u16 ctrl;
6791
6792 pci_read_config_word(tp->pdev,
6793 tp->msi_cap + PCI_MSI_FLAGS,
6794 &ctrl);
6795 pci_write_config_word(tp->pdev,
6796 tp->msi_cap + PCI_MSI_FLAGS,
6797 ctrl | PCI_MSI_FLAGS_ENABLE);
6798 val = tr32(MSGINT_MODE);
6799 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6800 }
6801 }
6802}
6803
1da177e4
LT		 6804static void tg3_stop_fw(struct tg3 *);
6805
6806/* tp->lock is held. */
6807static int tg3_chip_reset(struct tg3 *tp)
6808{
6809 u32 val;
1ee582d8 6810 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6811 int i, err;
1da177e4 6812
f49639e6
DM		 6813 tg3_nvram_lock(tp);
6814
77b483f1
MC		 6815 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6816
f49639e6
DM		 6817 /* No matching tg3_nvram_unlock() after this because
6818 * chip reset below will undo the nvram lock.
6819 */
6820 tp->nvram_lock_cnt = 0;
1da177e4 6821
ee6a99b5
MC		 6822 /* GRC_MISC_CFG core clock reset will clear the memory
6823 * enable bit in PCI register 4 and the MSI enable bit
6824 * on some chips, so we save relevant registers here.
6825 */
6826 tg3_save_pci_state(tp);
6827
d9ab5ad1 6828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6829 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6830 tw32(GRC_FASTBOOT_PC, 0);
6831
1da177e4
LT		 6832 /*
6833 * We must avoid the readl() that normally takes place.
6834 * It locks machines, causes machine checks, and other
6835 * fun things. So, temporarily disable the 5701
6836 * hardware workaround, while we do the reset.
6837 */
1ee582d8
MC		 6838 write_op = tp->write32;
6839 if (write_op == tg3_write_flush_reg32)
6840 tp->write32 = tg3_write32;
1da177e4 6841
d18edcb2
MC		 6842 /* Prevent the irq handler from reading or writing PCI registers
6843 * during chip reset when the memory enable bit in the PCI command
6844 * register may be cleared. The chip does not generate interrupt
6845 * at this time, but the irq handler may still be called due to irq
6846 * sharing or irqpoll.
6847 */
6848 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6849 for (i = 0; i < tp->irq_cnt; i++) {
6850 struct tg3_napi *tnapi = &tp->napi[i];
6851 if (tnapi->hw_status) {
6852 tnapi->hw_status->status = 0;
6853 tnapi->hw_status->status_tag = 0;
6854 }
6855 tnapi->last_tag = 0;
6856 tnapi->last_irq_tag = 0;
b8fa2f3a 6857 }
d18edcb2 6858 smp_mb();
4f125f42
MC		 6859
6860 for (i = 0; i < tp->irq_cnt; i++)
6861 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6862
255ca311
MC		 6863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6864 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6865 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6866 }
6867
1da177e4
LT		 6868 /* do the reset */
6869 val = GRC_MISC_CFG_CORECLK_RESET;
6870
6871 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6872 if (tr32(0x7e2c) == 0x60) {
6873 tw32(0x7e2c, 0x20);
6874 }
6875 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6876 tw32(GRC_MISC_CFG, (1 << 29));
6877 val |= (1 << 29);
6878 }
6879 }
6880
b5d3772c
MC		 6881 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6882 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6883 tw32(GRC_VCPU_EXT_CTRL,
6884 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6885 }
6886
1da177e4
LT		 6887 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6888 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6889 tw32(GRC_MISC_CFG, val);
6890
1ee582d8
MC		 6891 /* restore 5701 hardware bug workaround write method */
6892 tp->write32 = write_op;
1da177e4
LT		 6893
6894 /* Unfortunately, we have to delay before the PCI read back.
6895 * Some 575X chips even will not respond to a PCI cfg access
6896 * when the reset command is given to the chip.
6897 *
6898 * How do these hardware designers expect things to work
6899 * properly if the PCI write is posted for a long period
6900 * of time? It is always necessary to have some method by
6901 * which a register read back can occur to push the write
6902 * out which does the reset.
6903 *
6904 * For most tg3 variants the trick below was working.
6905 * Ho hum...
6906 */
6907 udelay(120);
6908
6909 /* Flush PCI posted writes. The normal MMIO registers
6910 * are inaccessible at this time so this is the only
6911 * way to make this reliably (actually, this is no longer
6912 * the case, see above). I tried to use indirect
6913 * register read/write but this upset some 5701 variants.
6914 */
6915 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6916
6917 udelay(120);
6918
5e7dfd0f 6919 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6920 u16 val16;
6921
1da177e4
LT		 6922 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6923 int i;
6924 u32 cfg_val;
6925
6926 /* Wait for link training to complete. */
6927 for (i = 0; i < 5000; i++)
6928 udelay(100);
6929
6930 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6931 pci_write_config_dword(tp->pdev, 0xc4,
6932 cfg_val | (1 << 15));
6933 }
5e7dfd0f 6934
e7126997
MC		 6935 /* Clear the "no snoop" and "relaxed ordering" bits. */
6936 pci_read_config_word(tp->pdev,
6937 tp->pcie_cap + PCI_EXP_DEVCTL,
6938 &val16);
6939 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6940 PCI_EXP_DEVCTL_NOSNOOP_EN);
6941 /*
6942 * Older PCIe devices only support the 128 byte
6943 * MPS setting. Enforce the restriction.
5e7dfd0f 6944 */
e7126997
MC		 6945 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6946 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6947 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6948 pci_write_config_word(tp->pdev,
6949 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6950 val16);
5e7dfd0f
MC		 6951
6952 pcie_set_readrq(tp->pdev, 4096);
6953
6954 /* Clear error status */
6955 pci_write_config_word(tp->pdev,
6956 tp->pcie_cap + PCI_EXP_DEVSTA,
6957 PCI_EXP_DEVSTA_CED |
6958 PCI_EXP_DEVSTA_NFED |
6959 PCI_EXP_DEVSTA_FED |
6960 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6961 }
6962
ee6a99b5 6963 tg3_restore_pci_state(tp);
1da177e4 6964
d18edcb2
MC		 6965 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6966
ee6a99b5
MC		 6967 val = 0;
6968 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6969 val = tr32(MEMARB_MODE);
ee6a99b5 6970 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6971
6972 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6973 tg3_stop_fw(tp);
6974 tw32(0x5000, 0x400);
6975 }
6976
6977 tw32(GRC_MODE, tp->grc_mode);
6978
6979 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6980 val = tr32(0xc4);
1da177e4
LT		 6981
6982 tw32(0xc4, val | (1 << 15));
6983 }
6984
6985 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6987 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6988 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6989 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6990 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6991 }
6992
6993 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6994 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6995 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6996 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6997 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6998 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6999 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7000 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7001 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7002 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7003 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 7004 } else
7005 tw32_f(MAC_MODE, 0);
7006 udelay(40);
7007
77b483f1
MC		 7008 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7009
7a6f4369
MC		 7010 err = tg3_poll_fw(tp);
7011 if (err)
7012 return err;
1da177e4 7013
0a9140cf
MC		 7014 tg3_mdio_start(tp);
7015
52cdf852
MC		 7016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7017 u8 phy_addr;
7018
7019 phy_addr = tp->phy_addr;
7020 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7021
7022 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7023 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7024 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7025 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7026 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7027 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7028 udelay(10);
7029
7030 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7031 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7032 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7033 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7034 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7035 udelay(10);
7036
7037 tp->phy_addr = phy_addr;
7038 }
7039
1da177e4 7040 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 7041 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7042 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 7043 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7044 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 7045 val = tr32(0x7c00);
1da177e4
LT		 7046
7047 tw32(0x7c00, val | (1 << 25));
7048 }
7049
7050 /* Reprobe ASF enable state. */
7051 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7052 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7053 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7054 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7055 u32 nic_cfg;
7056
7057 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7058 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7059 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 7060 tp->last_event_jiffies = jiffies;
cbf46853 7061 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7062 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7063 }
7064 }
7065
7066 return 0;
7067}
7068
7069/* tp->lock is held. */
7070static void tg3_stop_fw(struct tg3 *tp)
7071{
0d3031d9
MC		 7072 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7073 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7074 /* Wait for RX cpu to ACK the previous event. */
7075 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7076
7077 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7078
7079 tg3_generate_fw_event(tp);
1da177e4 7080
7c5026aa
MC		 7081 /* Wait for RX cpu to ACK this event. */
7082 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7083 }
7084}
7085
7086/* tp->lock is held. */
944d980e 7087static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7088{
7089 int err;
7090
7091 tg3_stop_fw(tp);
7092
944d980e 7093 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7094
b3b7d6be 7095 tg3_abort_hw(tp, silent);
1da177e4
LT		 7096 err = tg3_chip_reset(tp);
7097
daba2a63
MC		 7098 __tg3_set_mac_addr(tp, 0);
7099
944d980e
MC		 7100 tg3_write_sig_legacy(tp, kind);
7101 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7102
7103 if (err)
7104 return err;
7105
7106 return 0;
7107}
7108
1da177e4
LT		 7109#define RX_CPU_SCRATCH_BASE 0x30000
7110#define RX_CPU_SCRATCH_SIZE 0x04000
7111#define TX_CPU_SCRATCH_BASE 0x34000
7112#define TX_CPU_SCRATCH_SIZE 0x04000
7113
7114/* tp->lock is held. */
7115static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7116{
7117 int i;
7118
5d9428de
ES		 7119 BUG_ON(offset == TX_CPU_BASE &&
7120 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7121
b5d3772c
MC		 7122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7123 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7124
7125 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7126 return 0;
7127 }
1da177e4
LT		 7128 if (offset == RX_CPU_BASE) {
7129 for (i = 0; i < 10000; i++) {
7130 tw32(offset + CPU_STATE, 0xffffffff);
7131 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7132 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7133 break;
7134 }
7135
7136 tw32(offset + CPU_STATE, 0xffffffff);
7137 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7138 udelay(10);
7139 } else {
7140 for (i = 0; i < 10000; i++) {
7141 tw32(offset + CPU_STATE, 0xffffffff);
7142 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7143 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7144 break;
7145 }
7146 }
7147
7148 if (i >= 10000) {
7149 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7150 "and %s CPU\n",
7151 tp->dev->name,
7152 (offset == RX_CPU_BASE ? "RX" : "TX"));
7153 return -ENODEV;
7154 }
ec41c7df
MC		 7155
7156 /* Clear firmware's nvram arbitration. */
7157 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7158 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7159 return 0;
7160}
7161
7162struct fw_info {
077f849d
JSR		 7163 unsigned int fw_base;
7164 unsigned int fw_len;
7165 const __be32 *fw_data;
1da177e4
LT		 7166};
7167
7168/* tp->lock is held. */
7169static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7170 int cpu_scratch_size, struct fw_info *info)
7171{
ec41c7df 7172 int err, lock_err, i;
1da177e4
LT		 7173 void (*write_op)(struct tg3 *, u32, u32);
7174
7175 if (cpu_base == TX_CPU_BASE &&
7176 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7177 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7178 "TX cpu firmware on %s which is 5705.\n",
7179 tp->dev->name);
7180 return -EINVAL;
7181 }
7182
7183 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7184 write_op = tg3_write_mem;
7185 else
7186 write_op = tg3_write_indirect_reg32;
7187
1b628151
MC		 7188 /* It is possible that bootcode is still loading at this point.
7189 * Get the nvram lock first before halting the cpu.
7190 */
ec41c7df 7191 lock_err = tg3_nvram_lock(tp);
1da177e4 7192 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7193 if (!lock_err)
7194 tg3_nvram_unlock(tp);
1da177e4
LT		 7195 if (err)
7196 goto out;
7197
7198 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7199 write_op(tp, cpu_scratch_base + i, 0);
7200 tw32(cpu_base + CPU_STATE, 0xffffffff);
7201 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7202 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7203 write_op(tp, (cpu_scratch_base +
077f849d 7204 (info->fw_base & 0xffff) +
1da177e4 7205 (i * sizeof(u32))),
077f849d 7206 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7207
7208 err = 0;
7209
7210out:
1da177e4
LT		 7211 return err;
7212}
7213
7214/* tp->lock is held. */
7215static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7216{
7217 struct fw_info info;
077f849d 7218 const __be32 *fw_data;
1da177e4
LT		 7219 int err, i;
7220
077f849d
JSR		 7221 fw_data = (void *)tp->fw->data;
7222
7223 /* Firmware blob starts with version numbers, followed by
7224 start address and length. We are setting complete length.
7225 length = end_address_of_bss - start_address_of_text.
7226 Remainder is the blob to be loaded contiguously
7227 from start address. */
7228
7229 info.fw_base = be32_to_cpu(fw_data[1]);
7230 info.fw_len = tp->fw->size - 12;
7231 info.fw_data = &fw_data[3];
1da177e4
LT		 7232
7233 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7234 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7235 &info);
7236 if (err)
7237 return err;
7238
7239 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7240 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7241 &info);
7242 if (err)
7243 return err;
7244
7245 /* Now startup only the RX cpu. */
7246 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7247 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7248
7249 for (i = 0; i < 5; i++) {
077f849d 7250 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7251 break;
7252 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7253 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7254 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7255 udelay(1000);
7256 }
7257 if (i >= 5) {
7258 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7259 "to set RX CPU PC, is %08x should be %08x\n",
7260 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7261 info.fw_base);
1da177e4
LT		 7262 return -ENODEV;
7263 }
7264 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7265 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7266
7267 return 0;
7268}
7269
1da177e4 7270/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7271
7272/* tp->lock is held. */
7273static int tg3_load_tso_firmware(struct tg3 *tp)
7274{
7275 struct fw_info info;
077f849d 7276 const __be32 *fw_data;
1da177e4
LT		 7277 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7278 int err, i;
7279
7280 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7281 return 0;
7282
077f849d
JSR		 7283 fw_data = (void *)tp->fw->data;
7284
7285 /* Firmware blob starts with version numbers, followed by
7286 start address and length. We are setting complete length.
7287 length = end_address_of_bss - start_address_of_text.
7288 Remainder is the blob to be loaded contiguously
7289 from start address. */
7290
7291 info.fw_base = be32_to_cpu(fw_data[1]);
7292 cpu_scratch_size = tp->fw_len;
7293 info.fw_len = tp->fw->size - 12;
7294 info.fw_data = &fw_data[3];
7295
1da177e4 7296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7297 cpu_base = RX_CPU_BASE;
7298 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7299 } else {
1da177e4
LT		 7300 cpu_base = TX_CPU_BASE;
7301 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7302 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7303 }
7304
7305 err = tg3_load_firmware_cpu(tp, cpu_base,
7306 cpu_scratch_base, cpu_scratch_size,
7307 &info);
7308 if (err)
7309 return err;
7310
7311 /* Now startup the cpu. */
7312 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7313 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7314
7315 for (i = 0; i < 5; i++) {
077f849d 7316 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7317 break;
7318 tw32(cpu_base + CPU_STATE, 0xffffffff);
7319 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7320 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7321 udelay(1000);
7322 }
7323 if (i >= 5) {
7324 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7325 "to set CPU PC, is %08x should be %08x\n",
7326 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7327 info.fw_base);
1da177e4
LT		 7328 return -ENODEV;
7329 }
7330 tw32(cpu_base + CPU_STATE, 0xffffffff);
7331 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7332 return 0;
7333}
7334
1da177e4 7335
1da177e4
LT		 7336static int tg3_set_mac_addr(struct net_device *dev, void *p)
7337{
7338 struct tg3 *tp = netdev_priv(dev);
7339 struct sockaddr *addr = p;
986e0aeb 7340 int err = 0, skip_mac_1 = 0;
1da177e4 7341
f9804ddb
MC		 7342 if (!is_valid_ether_addr(addr->sa_data))
7343 return -EINVAL;
7344
1da177e4
LT		 7345 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7346
e75f7c90
MC		 7347 if (!netif_running(dev))
7348 return 0;
7349
58712ef9 7350 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7351 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7352
986e0aeb
MC		 7353 addr0_high = tr32(MAC_ADDR_0_HIGH);
7354 addr0_low = tr32(MAC_ADDR_0_LOW);
7355 addr1_high = tr32(MAC_ADDR_1_HIGH);
7356 addr1_low = tr32(MAC_ADDR_1_LOW);
7357
7358 /* Skip MAC addr 1 if ASF is using it. */
7359 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7360 !(addr1_high == 0 && addr1_low == 0))
7361 skip_mac_1 = 1;
58712ef9 7362 }
986e0aeb
MC		 7363 spin_lock_bh(&tp->lock);
7364 __tg3_set_mac_addr(tp, skip_mac_1);
7365 spin_unlock_bh(&tp->lock);
1da177e4 7366
b9ec6c1b 7367 return err;
1da177e4
LT		 7368}
7369
7370/* tp->lock is held. */
7371static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7372 dma_addr_t mapping, u32 maxlen_flags,
7373 u32 nic_addr)
7374{
7375 tg3_write_mem(tp,
7376 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7377 ((u64) mapping >> 32));
7378 tg3_write_mem(tp,
7379 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7380 ((u64) mapping & 0xffffffff));
7381 tg3_write_mem(tp,
7382 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7383 maxlen_flags);
7384
7385 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7386 tg3_write_mem(tp,
7387 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7388 nic_addr);
7389}
7390
7391static void __tg3_set_rx_mode(struct net_device *);
d244c892 7392static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7393{
b6080e12
MC		 7394 int i;
7395
19cfaecc 7396 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7397 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7398 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7399 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7400 } else {
7401 tw32(HOSTCC_TXCOL_TICKS, 0);
7402 tw32(HOSTCC_TXMAX_FRAMES, 0);
7403 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7404 }
b6080e12 7405
19cfaecc
MC		 7406 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7407 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7408 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7409 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7410 } else {
b6080e12
MC		 7411 tw32(HOSTCC_RXCOL_TICKS, 0);
7412 tw32(HOSTCC_RXMAX_FRAMES, 0);
7413 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7414 }
b6080e12 7415
15f9850d
DM		 7416 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7417 u32 val = ec->stats_block_coalesce_usecs;
7418
b6080e12
MC		 7419 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7420 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7421
15f9850d
DM		 7422 if (!netif_carrier_ok(tp->dev))
7423 val = 0;
7424
7425 tw32(HOSTCC_STAT_COAL_TICKS, val);
7426 }
b6080e12
MC		 7427
7428 for (i = 0; i < tp->irq_cnt - 1; i++) {
7429 u32 reg;
7430
7431 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7432 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7433 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7434 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7435 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7436 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7437
7438 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7439 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7440 tw32(reg, ec->tx_coalesce_usecs);
7441 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7442 tw32(reg, ec->tx_max_coalesced_frames);
7443 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7444 tw32(reg, ec->tx_max_coalesced_frames_irq);
7445 }
b6080e12
MC		 7446 }
7447
7448 for (; i < tp->irq_max - 1; i++) {
7449 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7450 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7451 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7452
7453 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7454 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7455 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7456 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7457 }
b6080e12 7458 }
15f9850d 7459}
1da177e4 7460
2d31ecaf
MC		 7461/* tp->lock is held. */
7462static void tg3_rings_reset(struct tg3 *tp)
7463{
7464 int i;
f77a6a8e 7465 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7466 struct tg3_napi *tnapi = &tp->napi[0];
7467
7468 /* Disable all transmit rings but the first. */
7469 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7470 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7471 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7472 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7473 else
7474 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7475
7476 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7477 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7478 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7479 BDINFO_FLAGS_DISABLED);
7480
7481
7482 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7483 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7484 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7485 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7486 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7487 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7488 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7489 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7490 else
7491 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7492
7493 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7494 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7495 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7496 BDINFO_FLAGS_DISABLED);
7497
7498 /* Disable interrupts */
7499 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7500
7501 /* Zero mailbox registers. */
f77a6a8e
MC		 7502 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7503 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7504 tp->napi[i].tx_prod = 0;
7505 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7506 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7507 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7508 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7509 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7510 }
c2353a32
MC		 7511 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7512 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7513 } else {
7514 tp->napi[0].tx_prod = 0;
7515 tp->napi[0].tx_cons = 0;
7516 tw32_mailbox(tp->napi[0].prodmbox, 0);
7517 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7518 }
2d31ecaf
MC		 7519
7520 /* Make sure the NIC-based send BD rings are disabled. */
7521 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7522 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7523 for (i = 0; i < 16; i++)
7524 tw32_tx_mbox(mbox + i * 8, 0);
7525 }
7526
7527 txrcb = NIC_SRAM_SEND_RCB;
7528 rxrcb = NIC_SRAM_RCV_RET_RCB;
7529
7530 /* Clear status block in ram. */
7531 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7532
7533 /* Set status block DMA address */
7534 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7535 ((u64) tnapi->status_mapping >> 32));
7536 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7537 ((u64) tnapi->status_mapping & 0xffffffff));
7538
f77a6a8e
MC		 7539 if (tnapi->tx_ring) {
7540 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7541 (TG3_TX_RING_SIZE <<
7542 BDINFO_FLAGS_MAXLEN_SHIFT),
7543 NIC_SRAM_TX_BUFFER_DESC);
7544 txrcb += TG3_BDINFO_SIZE;
7545 }
7546
7547 if (tnapi->rx_rcb) {
7548 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7549 (TG3_RX_RCB_RING_SIZE(tp) <<
7550 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7551 rxrcb += TG3_BDINFO_SIZE;
7552 }
7553
7554 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7555
f77a6a8e
MC		 7556 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7557 u64 mapping = (u64)tnapi->status_mapping;
7558 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7559 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7560
7561 /* Clear status block in ram. */
7562 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7563
19cfaecc
MC		 7564 if (tnapi->tx_ring) {
7565 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7566 (TG3_TX_RING_SIZE <<
7567 BDINFO_FLAGS_MAXLEN_SHIFT),
7568 NIC_SRAM_TX_BUFFER_DESC);
7569 txrcb += TG3_BDINFO_SIZE;
7570 }
f77a6a8e
MC		 7571
7572 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7573 (TG3_RX_RCB_RING_SIZE(tp) <<
7574 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7575
7576 stblk += 8;
f77a6a8e
MC		 7577 rxrcb += TG3_BDINFO_SIZE;
7578 }
2d31ecaf
MC		 7579}
7580
1da177e4 7581/* tp->lock is held. */
8e7a22e3 7582static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7583{
7584 u32 val, rdmac_mode;
7585 int i, err, limit;
21f581a5 7586 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7587
7588 tg3_disable_ints(tp);
7589
7590 tg3_stop_fw(tp);
7591
7592 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7593
7594 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7595 tg3_abort_hw(tp, 1);
1da177e4
LT		 7596 }
7597
603f1173 7598 if (reset_phy)
d4d2c558
MC		 7599 tg3_phy_reset(tp);
7600
1da177e4
LT		 7601 err = tg3_chip_reset(tp);
7602 if (err)
7603 return err;
7604
7605 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7606
bcb37f6c 7607 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7608 val = tr32(TG3_CPMU_CTRL);
7609 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7610 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7611
7612 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7613 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7614 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7615 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7616
7617 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7618 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7619 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7620 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7621
7622 val = tr32(TG3_CPMU_HST_ACC);
7623 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7624 val |= CPMU_HST_ACC_MACCLK_6_25;
7625 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7626 }
7627
33466d93
MC		 7628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7629 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7630 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7631 PCIE_PWR_MGMT_L1_THRESH_4MS;
7632 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7633
7634 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7635 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7636
7637 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7638
f40386c8
MC		 7639 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7640 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7641 }
7642
614b0590
MC		 7643 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7644 u32 grc_mode = tr32(GRC_MODE);
7645
7646 /* Access the lower 1K of PL PCIE block registers. */
7647 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7648 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7649
7650 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7651 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7652 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7653
7654 tw32(GRC_MODE, grc_mode);
7655 }
7656
1da177e4
LT		 7657 /* This works around an issue with Athlon chipsets on
7658 * B3 tigon3 silicon. This bit has no effect on any
7659 * other revision. But do not set this on PCI Express
795d01c5 7660 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7661 */
795d01c5
MC		 7662 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7663 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7664 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7665 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7666 }
1da177e4
LT		 7667
7668 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7669 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7670 val = tr32(TG3PCI_PCISTATE);
7671 val |= PCISTATE_RETRY_SAME_DMA;
7672 tw32(TG3PCI_PCISTATE, val);
7673 }
7674
0d3031d9
MC		 7675 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7676 /* Allow reads and writes to the
7677 * APE register and memory space.
7678 */
7679 val = tr32(TG3PCI_PCISTATE);
7680 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7681 PCISTATE_ALLOW_APE_SHMEM_WR;
7682 tw32(TG3PCI_PCISTATE, val);
7683 }
7684
1da177e4
LT		 7685 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7686 /* Enable some hw fixes. */
7687 val = tr32(TG3PCI_MSI_DATA);
7688 val |= (1 << 26) | (1 << 28) | (1 << 29);
7689 tw32(TG3PCI_MSI_DATA, val);
7690 }
7691
7692 /* Descriptor ring init may make accesses to the
7693 * NIC SRAM area to setup the TX descriptors, so we
7694 * can only do this after the hardware has been
7695 * successfully reset.
7696 */
32d8c572
MC		 7697 err = tg3_init_rings(tp);
7698 if (err)
7699 return err;
1da177e4 7700
b703df6f
MC		 7701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7703 val = tr32(TG3PCI_DMA_RW_CTRL) &
7704 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7705 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7706 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7707 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7708 /* This value is determined during the probe time DMA
7709 * engine test, tg3_test_dma.
7710 */
7711 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7712 }
1da177e4
LT		 7713
7714 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7715 GRC_MODE_4X_NIC_SEND_RINGS |
7716 GRC_MODE_NO_TX_PHDR_CSUM |
7717 GRC_MODE_NO_RX_PHDR_CSUM);
7718 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7719
7720 /* Pseudo-header checksum is done by hardware logic and not
7721 * the offload processers, so make the chip do the pseudo-
7722 * header checksums on receive. For transmit it is more
7723 * convenient to do the pseudo-header checksum in software
7724 * as Linux does that on transmit for us in all cases.
7725 */
7726 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7727
7728 tw32(GRC_MODE,
7729 tp->grc_mode |
7730 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7731
7732 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7733 val = tr32(GRC_MISC_CFG);
7734 val &= ~0xff;
7735 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7736 tw32(GRC_MISC_CFG, val);
7737
7738 /* Initialize MBUF/DESC pool. */
cbf46853 7739 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7740 /* Do nothing. */
7741 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7742 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7743 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7744 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7745 else
7746 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7747 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7748 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7749 }
1da177e4
LT		 7750 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7751 int fw_len;
7752
077f849d 7753 fw_len = tp->fw_len;
1da177e4
LT		 7754 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7755 tw32(BUFMGR_MB_POOL_ADDR,
7756 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7757 tw32(BUFMGR_MB_POOL_SIZE,
7758 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7759 }
1da177e4 7760
0f893dc6 7761 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7762 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7763 tp->bufmgr_config.mbuf_read_dma_low_water);
7764 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7765 tp->bufmgr_config.mbuf_mac_rx_low_water);
7766 tw32(BUFMGR_MB_HIGH_WATER,
7767 tp->bufmgr_config.mbuf_high_water);
7768 } else {
7769 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7770 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7771 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7772 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7773 tw32(BUFMGR_MB_HIGH_WATER,
7774 tp->bufmgr_config.mbuf_high_water_jumbo);
7775 }
7776 tw32(BUFMGR_DMA_LOW_WATER,
7777 tp->bufmgr_config.dma_low_water);
7778 tw32(BUFMGR_DMA_HIGH_WATER,
7779 tp->bufmgr_config.dma_high_water);
7780
7781 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7782 for (i = 0; i < 2000; i++) {
7783 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7784 break;
7785 udelay(10);
7786 }
7787 if (i >= 2000) {
7788 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7789 tp->dev->name);
7790 return -ENODEV;
7791 }
7792
7793 /* Setup replenish threshold. */
f92905de
MC		 7794 val = tp->rx_pending / 8;
7795 if (val == 0)
7796 val = 1;
7797 else if (val > tp->rx_std_max_post)
7798 val = tp->rx_std_max_post;
b5d3772c
MC		 7799 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7800 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7801 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7802
7803 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7804 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7805 }
f92905de
MC		 7806
7807 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7808
7809 /* Initialize TG3_BDINFO's at:
7810 * RCVDBDI_STD_BD: standard eth size rx ring
7811 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7812 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7813 *
7814 * like so:
7815 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7816 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7817 * ring attribute flags
7818 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7819 *
7820 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7821 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7822 *
7823 * The size of each ring is fixed in the firmware, but the location is
7824 * configurable.
7825 */
7826 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7827 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7828 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7829 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7830 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7831 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7832 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7833
fdb72b38
MC		 7834 /* Disable the mini ring */
7835 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7836 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7837 BDINFO_FLAGS_DISABLED);
7838
fdb72b38
MC		 7839 /* Program the jumbo buffer descriptor ring control
7840 * blocks on those devices that have them.
7841 */
8f666b07 7842 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7843 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7844 /* Setup replenish threshold. */
7845 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7846
0f893dc6 7847 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7848 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7849 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7850 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7851 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7852 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7853 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7854 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7855 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7856 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7857 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7858 } else {
7859 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7860 BDINFO_FLAGS_DISABLED);
7861 }
7862
b703df6f
MC		 7863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7865 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7866 (RX_STD_MAX_SIZE << 2);
7867 else
7868 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7869 } else
7870 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7871
7872 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7873
411da640 7874 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7875 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7876
411da640 7877 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7878 tp->rx_jumbo_pending : 0;
66711e66 7879 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7880
b703df6f
MC		 7881 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7883 tw32(STD_REPLENISH_LWM, 32);
7884 tw32(JMB_REPLENISH_LWM, 16);
7885 }
7886
2d31ecaf
MC		 7887 tg3_rings_reset(tp);
7888
1da177e4 7889 /* Initialize MAC address and backoff seed. */
986e0aeb 7890 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7891
7892 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7893 tw32(MAC_RX_MTU_SIZE,
7894 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7895
7896 /* The slot time is changed by tg3_setup_phy if we
7897 * run at gigabit with half duplex.
7898 */
7899 tw32(MAC_TX_LENGTHS,
7900 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7901 (6 << TX_LENGTHS_IPG_SHIFT) |
7902 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7903
7904 /* Receive rules. */
7905 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7906 tw32(RCVLPC_CONFIG, 0x0181);
7907
7908 /* Calculate RDMAC_MODE setting early, we need it to determine
7909 * the RCVLPC_STATE_ENABLE mask.
7910 */
7911 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7912 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7913 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7914 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7915 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7916
0339e4e3
MC		 7917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7918 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7919
57e6983c 7920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7923 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7924 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7925 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7926
85e94ced
MC		 7927 /* If statement applies to 5705 and 5750 PCI devices only */
7928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7929 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7930 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7931 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7933 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7934 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7935 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7936 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7937 }
7938 }
7939
85e94ced
MC		 7940 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7941 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7942
1da177e4 7943 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7944 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7945
e849cdc3
MC		 7946 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7949 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7950
7951 /* Receive/send statistics. */
1661394e
MC		 7952 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7953 val = tr32(RCVLPC_STATS_ENABLE);
7954 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7955 tw32(RCVLPC_STATS_ENABLE, val);
7956 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7957 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7958 val = tr32(RCVLPC_STATS_ENABLE);
7959 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7960 tw32(RCVLPC_STATS_ENABLE, val);
7961 } else {
7962 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7963 }
7964 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7965 tw32(SNDDATAI_STATSENAB, 0xffffff);
7966 tw32(SNDDATAI_STATSCTRL,
7967 (SNDDATAI_SCTRL_ENABLE |
7968 SNDDATAI_SCTRL_FASTUPD));
7969
7970 /* Setup host coalescing engine. */
7971 tw32(HOSTCC_MODE, 0);
7972 for (i = 0; i < 2000; i++) {
7973 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7974 break;
7975 udelay(10);
7976 }
7977
d244c892 7978 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7979
1da177e4
LT		 7980 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7981 /* Status/statistics block address. See tg3_timer,
7982 * the tg3_periodic_fetch_stats call there, and
7983 * tg3_get_stats to see how this works for 5705/5750 chips.
7984 */
1da177e4
LT		 7985 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7986 ((u64) tp->stats_mapping >> 32));
7987 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7988 ((u64) tp->stats_mapping & 0xffffffff));
7989 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7990
1da177e4 7991 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7992
7993 /* Clear statistics and status block memory areas */
7994 for (i = NIC_SRAM_STATS_BLK;
7995 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7996 i += sizeof(u32)) {
7997 tg3_write_mem(tp, i, 0);
7998 udelay(40);
7999 }
1da177e4
LT		 8000 }
8001
8002 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8003
8004 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8005 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8006 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8007 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8008
c94e3941
MC		 8009 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8010 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8011 /* reset to prevent losing 1st rx packet intermittently */
8012 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8013 udelay(10);
8014 }
8015
3bda1258
MC		 8016 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8017 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8018 else
8019 tp->mac_mode = 0;
8020 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 8021 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 8022 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8023 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8024 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8025 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 8026 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8027 udelay(40);
8028
314fba34 8029 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 8030 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 8031 * register to preserve the GPIO settings for LOMs. The GPIOs,
8032 * whether used as inputs or outputs, are set by boot code after
8033 * reset.
8034 */
9d26e213 8035 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 8036 u32 gpio_mask;
8037
9d26e213
MC		 8038 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8039 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8040 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 8041
8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8043 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8044 GRC_LCLCTRL_GPIO_OUTPUT3;
8045
af36e6b6
MC		 8046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8047 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8048
aaf84465 8049 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 8050 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8051
8052 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 8053 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8054 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8055 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 8056 }
1da177e4
LT		 8057 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8058 udelay(100);
8059
baf8a94a
MC		 8060 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8061 val = tr32(MSGINT_MODE);
8062 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8063 tw32(MSGINT_MODE, val);
8064 }
8065
1da177e4
LT		 8066 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8067 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8068 udelay(40);
8069 }
8070
8071 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8072 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8073 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8074 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8075 WDMAC_MODE_LNGREAD_ENAB);
8076
85e94ced
MC		 8077 /* If statement applies to 5705 and 5750 PCI devices only */
8078 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8079 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8081 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8082 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8083 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8084 /* nothing */
8085 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8086 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8087 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8088 val |= WDMAC_MODE_RX_ACCEL;
8089 }
8090 }
8091
d9ab5ad1 8092 /* Enable host coalescing bug fix */
321d32a0 8093 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8094 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8095
788a035e
MC		 8096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8097 val |= WDMAC_MODE_BURST_ALL_DATA;
8098
1da177e4
LT		 8099 tw32_f(WDMAC_MODE, val);
8100 udelay(40);
8101
9974a356
MC		 8102 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8103 u16 pcix_cmd;
8104
8105 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8106 &pcix_cmd);
1da177e4 8107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8108 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8109 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8110 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8111 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8112 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8113 }
9974a356
MC		 8114 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8115 pcix_cmd);
1da177e4
LT		 8116 }
8117
8118 tw32_f(RDMAC_MODE, rdmac_mode);
8119 udelay(40);
8120
8121 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8122 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8123 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8124
8125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8126 tw32(SNDDATAC_MODE,
8127 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8128 else
8129 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8130
1da177e4
LT		 8131 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8132 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8133 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8134 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8135 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8136 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8137 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8138 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8139 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8140 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8141 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8142
8143 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8144 err = tg3_load_5701_a0_firmware_fix(tp);
8145 if (err)
8146 return err;
8147 }
8148
1da177e4
LT		 8149 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8150 err = tg3_load_tso_firmware(tp);
8151 if (err)
8152 return err;
8153 }
1da177e4
LT		 8154
8155 tp->tx_mode = TX_MODE_ENABLE;
8156 tw32_f(MAC_TX_MODE, tp->tx_mode);
8157 udelay(100);
8158
baf8a94a
MC		 8159 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8160 u32 reg = MAC_RSS_INDIR_TBL_0;
8161 u8 *ent = (u8 *)&val;
8162
8163 /* Setup the indirection table */
8164 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8165 int idx = i % sizeof(val);
8166
8167 ent[idx] = i % (tp->irq_cnt - 1);
8168 if (idx == sizeof(val) - 1) {
8169 tw32(reg, val);
8170 reg += 4;
8171 }
8172 }
8173
8174 /* Setup the "secret" hash key. */
8175 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8176 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8177 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8178 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8179 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8180 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8181 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8182 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8183 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8184 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8185 }
8186
1da177e4 8187 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8188 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8189 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8190
baf8a94a
MC		 8191 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8192 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8193 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8194 RX_MODE_RSS_IPV6_HASH_EN |
8195 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8196 RX_MODE_RSS_IPV4_HASH_EN |
8197 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8198
1da177e4
LT		 8199 tw32_f(MAC_RX_MODE, tp->rx_mode);
8200 udelay(10);
8201
1da177e4
LT		 8202 tw32(MAC_LED_CTRL, tp->led_ctrl);
8203
8204 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8205 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8206 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8207 udelay(10);
8208 }
8209 tw32_f(MAC_RX_MODE, tp->rx_mode);
8210 udelay(10);
8211
8212 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8213 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8214 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8215 /* Set drive transmission level to 1.2V */
8216 /* only if the signal pre-emphasis bit is not set */
8217 val = tr32(MAC_SERDES_CFG);
8218 val &= 0xfffff000;
8219 val |= 0x880;
8220 tw32(MAC_SERDES_CFG, val);
8221 }
8222 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8223 tw32(MAC_SERDES_CFG, 0x616000);
8224 }
8225
8226 /* Prevent chip from dropping frames when flow control
8227 * is enabled.
8228 */
666bc831
MC		 8229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8230 val = 1;
8231 else
8232 val = 2;
8233 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8234
8235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8236 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8237 /* Use hardware link auto-negotiation */
8238 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8239 }
8240
d4d2c558
MC		 8241 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8242 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8243 u32 tmp;
8244
8245 tmp = tr32(SERDES_RX_CTRL);
8246 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8247 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8248 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8249 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8250 }
8251
dd477003
MC		 8252 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8253 if (tp->link_config.phy_is_low_power) {
8254 tp->link_config.phy_is_low_power = 0;
8255 tp->link_config.speed = tp->link_config.orig_speed;
8256 tp->link_config.duplex = tp->link_config.orig_duplex;
8257 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8258 }
1da177e4 8259
dd477003
MC		 8260 err = tg3_setup_phy(tp, 0);
8261 if (err)
8262 return err;
1da177e4 8263
dd477003 8264 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8265 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8266 u32 tmp;
8267
8268 /* Clear CRC stats. */
8269 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8270 tg3_writephy(tp, MII_TG3_TEST1,
8271 tmp | MII_TG3_TEST1_CRC_EN);
8272 tg3_readphy(tp, 0x14, &tmp);
8273 }
1da177e4
LT		 8274 }
8275 }
8276
8277 __tg3_set_rx_mode(tp->dev);
8278
8279 /* Initialize receive rules. */
8280 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8281 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8282 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8283 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8284
4cf78e4f 8285 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8286 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8287 limit = 8;
8288 else
8289 limit = 16;
8290 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8291 limit -= 4;
8292 switch (limit) {
8293 case 16:
8294 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8295 case 15:
8296 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8297 case 14:
8298 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8299 case 13:
8300 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8301 case 12:
8302 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8303 case 11:
8304 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8305 case 10:
8306 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8307 case 9:
8308 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8309 case 8:
8310 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8311 case 7:
8312 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8313 case 6:
8314 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8315 case 5:
8316 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8317 case 4:
8318 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8319 case 3:
8320 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8321 case 2:
8322 case 1:
8323
8324 default:
8325 break;
855e1111 8326 }
1da177e4 8327
9ce768ea
MC		 8328 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8329 /* Write our heartbeat update interval to APE. */
8330 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8331 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8332
1da177e4
LT		 8333 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8334
1da177e4
LT		 8335 return 0;
8336}
8337
8338/* Called at device open time to get the chip ready for
8339 * packet processing. Invoked with tp->lock held.
8340 */
8e7a22e3 8341static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8342{
1da177e4
LT		 8343 tg3_switch_clocks(tp);
8344
8345 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8346
2f751b67 8347 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8348}
8349
8350#define TG3_STAT_ADD32(PSTAT, REG) \
8351do { u32 __val = tr32(REG); \
8352 (PSTAT)->low += __val; \
8353 if ((PSTAT)->low < __val) \
8354 (PSTAT)->high += 1; \
8355} while (0)
8356
8357static void tg3_periodic_fetch_stats(struct tg3 *tp)
8358{
8359 struct tg3_hw_stats *sp = tp->hw_stats;
8360
8361 if (!netif_carrier_ok(tp->dev))
8362 return;
8363
8364 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8365 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8366 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8367 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8368 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8369 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8370 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8371 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8372 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8373 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8374 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8375 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8376 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8377
8378 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8379 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8380 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8381 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8382 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8383 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8384 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8385 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8386 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8387 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8388 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8389 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8390 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8391 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8392
8393 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8394 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8395 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8396}
8397
8398static void tg3_timer(unsigned long __opaque)
8399{
8400 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8401
f475f163
MC		 8402 if (tp->irq_sync)
8403 goto restart_timer;
8404
f47c11ee 8405 spin_lock(&tp->lock);
1da177e4 8406
fac9b83e
DM		 8407 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8408 /* All of this garbage is because when using non-tagged
8409 * IRQ status the mailbox/status_block protocol the chip
8410 * uses with the cpu is race prone.
8411 */
898a56f8 8412 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8413 tw32(GRC_LOCAL_CTRL,
8414 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8415 } else {
8416 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8417 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8418 }
1da177e4 8419
fac9b83e
DM		 8420 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8421 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8422 spin_unlock(&tp->lock);
fac9b83e
DM		 8423 schedule_work(&tp->reset_task);
8424 return;
8425 }
1da177e4
LT		 8426 }
8427
1da177e4
LT		 8428 /* This part only runs once per second. */
8429 if (!--tp->timer_counter) {
fac9b83e
DM		 8430 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8431 tg3_periodic_fetch_stats(tp);
8432
1da177e4
LT		 8433 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8434 u32 mac_stat;
8435 int phy_event;
8436
8437 mac_stat = tr32(MAC_STATUS);
8438
8439 phy_event = 0;
8440 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8441 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8442 phy_event = 1;
8443 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8444 phy_event = 1;
8445
8446 if (phy_event)
8447 tg3_setup_phy(tp, 0);
8448 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8449 u32 mac_stat = tr32(MAC_STATUS);
8450 int need_setup = 0;
8451
8452 if (netif_carrier_ok(tp->dev) &&
8453 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8454 need_setup = 1;
8455 }
8456 if (! netif_carrier_ok(tp->dev) &&
8457 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8458 MAC_STATUS_SIGNAL_DET))) {
8459 need_setup = 1;
8460 }
8461 if (need_setup) {
3d3ebe74
MC		 8462 if (!tp->serdes_counter) {
8463 tw32_f(MAC_MODE,
8464 (tp->mac_mode &
8465 ~MAC_MODE_PORT_MODE_MASK));
8466 udelay(40);
8467 tw32_f(MAC_MODE, tp->mac_mode);
8468 udelay(40);
8469 }
1da177e4
LT		 8470 tg3_setup_phy(tp, 0);
8471 }
747e8f8b
MC		 8472 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8473 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8474
8475 tp->timer_counter = tp->timer_multiplier;
8476 }
8477
130b8e4d
MC		 8478 /* Heartbeat is only sent once every 2 seconds.
8479 *
8480 * The heartbeat is to tell the ASF firmware that the host
8481 * driver is still alive. In the event that the OS crashes,
8482 * ASF needs to reset the hardware to free up the FIFO space
8483 * that may be filled with rx packets destined for the host.
8484 * If the FIFO is full, ASF will no longer function properly.
8485 *
8486 * Unintended resets have been reported on real time kernels
8487 * where the timer doesn't run on time. Netpoll will also have
8488 * same problem.
8489 *
8490 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8491 * to check the ring condition when the heartbeat is expiring
8492 * before doing the reset. This will prevent most unintended
8493 * resets.
8494 */
1da177e4 8495 if (!--tp->asf_counter) {
bc7959b2
MC		 8496 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8497 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8498 tg3_wait_for_event_ack(tp);
8499
bbadf503 8500 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8501 FWCMD_NICDRV_ALIVE3);
bbadf503 8502 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8503 /* 5 seconds timeout */
bbadf503 8504 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8505
8506 tg3_generate_fw_event(tp);
1da177e4
LT		 8507 }
8508 tp->asf_counter = tp->asf_multiplier;
8509 }
8510
f47c11ee 8511 spin_unlock(&tp->lock);
1da177e4 8512
f475f163 8513restart_timer:
1da177e4
LT		 8514 tp->timer.expires = jiffies + tp->timer_offset;
8515 add_timer(&tp->timer);
8516}
8517
4f125f42 8518static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8519{
7d12e780 8520 irq_handler_t fn;
fcfa0a32 8521 unsigned long flags;
4f125f42
MC		 8522 char *name;
8523 struct tg3_napi *tnapi = &tp->napi[irq_num];
8524
8525 if (tp->irq_cnt == 1)
8526 name = tp->dev->name;
8527 else {
8528 name = &tnapi->irq_lbl[0];
8529 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8530 name[IFNAMSIZ-1] = 0;
8531 }
fcfa0a32 8532
679563f4 8533 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8534 fn = tg3_msi;
8535 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8536 fn = tg3_msi_1shot;
1fb9df5d 8537 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8538 } else {
8539 fn = tg3_interrupt;
8540 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8541 fn = tg3_interrupt_tagged;
1fb9df5d 8542 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8543 }
4f125f42
MC		 8544
8545 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8546}
8547
7938109f
MC		 8548static int tg3_test_interrupt(struct tg3 *tp)
8549{
09943a18 8550 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8551 struct net_device *dev = tp->dev;
b16250e3 8552 int err, i, intr_ok = 0;
f6eb9b1f 8553 u32 val;
7938109f 8554
d4bc3927
MC		 8555 if (!netif_running(dev))
8556 return -ENODEV;
8557
7938109f
MC		 8558 tg3_disable_ints(tp);
8559
4f125f42 8560 free_irq(tnapi->irq_vec, tnapi);
7938109f 8561
f6eb9b1f
MC		 8562 /*
8563 * Turn off MSI one shot mode. Otherwise this test has no
8564 * observable way to know whether the interrupt was delivered.
8565 */
b703df6f
MC		 8566 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8568 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8569 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8570 tw32(MSGINT_MODE, val);
8571 }
8572
4f125f42 8573 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8574 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8575 if (err)
8576 return err;
8577
898a56f8 8578 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8579 tg3_enable_ints(tp);
8580
8581 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8582 tnapi->coal_now);
7938109f
MC		 8583
8584 for (i = 0; i < 5; i++) {
b16250e3
MC		 8585 u32 int_mbox, misc_host_ctrl;
8586
898a56f8 8587 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8588 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8589
8590 if ((int_mbox != 0) ||
8591 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8592 intr_ok = 1;
7938109f 8593 break;
b16250e3
MC		 8594 }
8595
7938109f
MC		 8596 msleep(10);
8597 }
8598
8599 tg3_disable_ints(tp);
8600
4f125f42 8601 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8602
4f125f42 8603 err = tg3_request_irq(tp, 0);
7938109f
MC		 8604
8605 if (err)
8606 return err;
8607
f6eb9b1f
MC		 8608 if (intr_ok) {
8609 /* Reenable MSI one shot mode. */
b703df6f
MC		 8610 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8612 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8613 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8614 tw32(MSGINT_MODE, val);
8615 }
7938109f 8616 return 0;
f6eb9b1f 8617 }
7938109f
MC		 8618
8619 return -EIO;
8620}
8621
8622/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8623 * successfully restored
8624 */
8625static int tg3_test_msi(struct tg3 *tp)
8626{
7938109f
MC		 8627 int err;
8628 u16 pci_cmd;
8629
8630 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8631 return 0;
8632
8633 /* Turn off SERR reporting in case MSI terminates with Master
8634 * Abort.
8635 */
8636 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8637 pci_write_config_word(tp->pdev, PCI_COMMAND,
8638 pci_cmd & ~PCI_COMMAND_SERR);
8639
8640 err = tg3_test_interrupt(tp);
8641
8642 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8643
8644 if (!err)
8645 return 0;
8646
8647 /* other failures */
8648 if (err != -EIO)
8649 return err;
8650
8651 /* MSI test failed, go back to INTx mode */
8652 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8653 "switching to INTx mode. Please report this failure to "
8654 "the PCI maintainer and include system chipset information.\n",
8655 tp->dev->name);
8656
4f125f42 8657 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8658
7938109f
MC		 8659 pci_disable_msi(tp->pdev);
8660
8661 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8662
4f125f42 8663 err = tg3_request_irq(tp, 0);
7938109f
MC		 8664 if (err)
8665 return err;
8666
8667 /* Need to reset the chip because the MSI cycle may have terminated
8668 * with Master Abort.
8669 */
f47c11ee 8670 tg3_full_lock(tp, 1);
7938109f 8671
944d980e 8672 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8673 err = tg3_init_hw(tp, 1);
7938109f 8674
f47c11ee 8675 tg3_full_unlock(tp);
7938109f
MC		 8676
8677 if (err)
4f125f42 8678 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8679
8680 return err;
8681}
8682
9e9fd12d
MC		 8683static int tg3_request_firmware(struct tg3 *tp)
8684{
8685 const __be32 *fw_data;
8686
8687 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8688 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8689 tp->dev->name, tp->fw_needed);
8690 return -ENOENT;
8691 }
8692
8693 fw_data = (void *)tp->fw->data;
8694
8695 /* Firmware blob starts with version numbers, followed by
8696 * start address and _full_ length including BSS sections
8697 * (which must be longer than the actual data, of course
8698 */
8699
8700 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8701 if (tp->fw_len < (tp->fw->size - 12)) {
8702 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8703 tp->dev->name, tp->fw_len, tp->fw_needed);
8704 release_firmware(tp->fw);
8705 tp->fw = NULL;
8706 return -EINVAL;
8707 }
8708
8709 /* We no longer need firmware; we have it. */
8710 tp->fw_needed = NULL;
8711 return 0;
8712}
8713
679563f4
MC		 8714static bool tg3_enable_msix(struct tg3 *tp)
8715{
8716 int i, rc, cpus = num_online_cpus();
8717 struct msix_entry msix_ent[tp->irq_max];
8718
8719 if (cpus == 1)
8720 /* Just fallback to the simpler MSI mode. */
8721 return false;
8722
8723 /*
8724 * We want as many rx rings enabled as there are cpus.
8725 * The first MSIX vector only deals with link interrupts, etc,
8726 * so we add one to the number of vectors we are requesting.
8727 */
8728 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8729
8730 for (i = 0; i < tp->irq_max; i++) {
8731 msix_ent[i].entry = i;
8732 msix_ent[i].vector = 0;
8733 }
8734
8735 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8736 if (rc != 0) {
8737 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8738 return false;
8739 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8740 return false;
8741 printk(KERN_NOTICE
8742 "%s: Requested %d MSI-X vectors, received %d\n",
8743 tp->dev->name, tp->irq_cnt, rc);
8744 tp->irq_cnt = rc;
8745 }
8746
baf8a94a
MC		 8747 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8748
679563f4
MC		 8749 for (i = 0; i < tp->irq_max; i++)
8750 tp->napi[i].irq_vec = msix_ent[i].vector;
8751
19cfaecc
MC		 8752 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8753 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8754 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8755 } else
8756 tp->dev->real_num_tx_queues = 1;
fe5f5787 8757
679563f4
MC		 8758 return true;
8759}
8760
07b0173c
MC		 8761static void tg3_ints_init(struct tg3 *tp)
8762{
679563f4
MC		 8763 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8764 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8765 /* All MSI supporting chips should support tagged
8766 * status. Assert that this is the case.
8767 */
679563f4
MC		 8768 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8769 "Not using MSI.\n", tp->dev->name);
8770 goto defcfg;
07b0173c 8771 }
4f125f42 8772
679563f4
MC		 8773 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8774 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8775 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8776 pci_enable_msi(tp->pdev) == 0)
8777 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8778
8779 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8780 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8781 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8782 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8783 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8784 }
8785defcfg:
8786 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8787 tp->irq_cnt = 1;
8788 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8789 tp->dev->real_num_tx_queues = 1;
679563f4 8790 }
07b0173c
MC		 8791}
8792
8793static void tg3_ints_fini(struct tg3 *tp)
8794{
679563f4
MC		 8795 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8796 pci_disable_msix(tp->pdev);
8797 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8798 pci_disable_msi(tp->pdev);
8799 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8800 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8801}
8802
1da177e4
LT		 8803static int tg3_open(struct net_device *dev)
8804{
8805 struct tg3 *tp = netdev_priv(dev);
4f125f42 8806 int i, err;
1da177e4 8807
9e9fd12d
MC		 8808 if (tp->fw_needed) {
8809 err = tg3_request_firmware(tp);
8810 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8811 if (err)
8812 return err;
8813 } else if (err) {
8814 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8815 tp->dev->name);
8816 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8817 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8818 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8819 tp->dev->name);
8820 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8821 }
8822 }
8823
c49a1561
MC		 8824 netif_carrier_off(tp->dev);
8825
bc1c7567 8826 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8827 if (err)
bc1c7567 8828 return err;
2f751b67
MC		 8829
8830 tg3_full_lock(tp, 0);
bc1c7567 8831
1da177e4
LT		 8832 tg3_disable_ints(tp);
8833 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8834
f47c11ee 8835 tg3_full_unlock(tp);
1da177e4 8836
679563f4
MC		 8837 /*
8838 * Setup interrupts first so we know how
8839 * many NAPI resources to allocate
8840 */
8841 tg3_ints_init(tp);
8842
1da177e4
LT		 8843 /* The placement of this call is tied
8844 * to the setup and use of Host TX descriptors.
8845 */
8846 err = tg3_alloc_consistent(tp);
8847 if (err)
679563f4 8848 goto err_out1;
88b06bc2 8849
fed97810 8850 tg3_napi_enable(tp);
1da177e4 8851
4f125f42
MC		 8852 for (i = 0; i < tp->irq_cnt; i++) {
8853 struct tg3_napi *tnapi = &tp->napi[i];
8854 err = tg3_request_irq(tp, i);
8855 if (err) {
8856 for (i--; i >= 0; i--)
8857 free_irq(tnapi->irq_vec, tnapi);
8858 break;
8859 }
8860 }
1da177e4 8861
07b0173c 8862 if (err)
679563f4 8863 goto err_out2;
bea3348e 8864
f47c11ee 8865 tg3_full_lock(tp, 0);
1da177e4 8866
8e7a22e3 8867 err = tg3_init_hw(tp, 1);
1da177e4 8868 if (err) {
944d980e 8869 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8870 tg3_free_rings(tp);
8871 } else {
fac9b83e
DM		 8872 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8873 tp->timer_offset = HZ;
8874 else
8875 tp->timer_offset = HZ / 10;
8876
8877 BUG_ON(tp->timer_offset > HZ);
8878 tp->timer_counter = tp->timer_multiplier =
8879 (HZ / tp->timer_offset);
8880 tp->asf_counter = tp->asf_multiplier =
28fbef78 8881 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8882
8883 init_timer(&tp->timer);
8884 tp->timer.expires = jiffies + tp->timer_offset;
8885 tp->timer.data = (unsigned long) tp;
8886 tp->timer.function = tg3_timer;
1da177e4
LT		 8887 }
8888
f47c11ee 8889 tg3_full_unlock(tp);
1da177e4 8890
07b0173c 8891 if (err)
679563f4 8892 goto err_out3;
1da177e4 8893
7938109f
MC		 8894 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8895 err = tg3_test_msi(tp);
fac9b83e 8896
7938109f 8897 if (err) {
f47c11ee 8898 tg3_full_lock(tp, 0);
944d980e 8899 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8900 tg3_free_rings(tp);
f47c11ee 8901 tg3_full_unlock(tp);
7938109f 8902
679563f4 8903 goto err_out2;
7938109f 8904 }
fcfa0a32 8905
f6eb9b1f 8906 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8907 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8908 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8909 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8910 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8911
f6eb9b1f
MC		 8912 tw32(PCIE_TRANSACTION_CFG,
8913 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8914 }
7938109f
MC		 8915 }
8916
b02fd9e3
MC		 8917 tg3_phy_start(tp);
8918
f47c11ee 8919 tg3_full_lock(tp, 0);
1da177e4 8920
7938109f
MC		 8921 add_timer(&tp->timer);
8922 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8923 tg3_enable_ints(tp);
8924
f47c11ee 8925 tg3_full_unlock(tp);
1da177e4 8926
fe5f5787 8927 netif_tx_start_all_queues(dev);
1da177e4
LT		 8928
8929 return 0;
07b0173c 8930
679563f4 8931err_out3:
4f125f42
MC		 8932 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8933 struct tg3_napi *tnapi = &tp->napi[i];
8934 free_irq(tnapi->irq_vec, tnapi);
8935 }
07b0173c 8936
679563f4 8937err_out2:
fed97810 8938 tg3_napi_disable(tp);
07b0173c 8939 tg3_free_consistent(tp);
679563f4
MC		 8940
8941err_out1:
8942 tg3_ints_fini(tp);
07b0173c 8943 return err;
1da177e4
LT		 8944}
8945
8946#if 0
8947/*static*/ void tg3_dump_state(struct tg3 *tp)
8948{
8949 u32 val32, val32_2, val32_3, val32_4, val32_5;
8950 u16 val16;
8951 int i;
898a56f8 8952 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8953
8954 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8955 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8956 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8957 val16, val32);
8958
8959 /* MAC block */
8960 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8961 tr32(MAC_MODE), tr32(MAC_STATUS));
8962 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8963 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8964 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8965 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8966 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8967 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8968
8969 /* Send data initiator control block */
8970 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8971 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8972 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8973 tr32(SNDDATAI_STATSCTRL));
8974
8975 /* Send data completion control block */
8976 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8977
8978 /* Send BD ring selector block */
8979 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8980 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8981
8982 /* Send BD initiator control block */
8983 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8984 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8985
8986 /* Send BD completion control block */
8987 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8988
8989 /* Receive list placement control block */
8990 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8991 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8992 printk(" RCVLPC_STATSCTRL[%08x]\n",
8993 tr32(RCVLPC_STATSCTRL));
8994
8995 /* Receive data and receive BD initiator control block */
8996 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8997 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8998
8999 /* Receive data completion control block */
9000 printk("DEBUG: RCVDCC_MODE[%08x]\n",
9001 tr32(RCVDCC_MODE));
9002
9003 /* Receive BD initiator control block */
9004 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
9005 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
9006
9007 /* Receive BD completion control block */
9008 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
9009 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
9010
9011 /* Receive list selector control block */
9012 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9013 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9014
9015 /* Mbuf cluster free block */
9016 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9017 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9018
9019 /* Host coalescing control block */
9020 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9021 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9022 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9023 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9024 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9025 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9026 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9027 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9028 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9029 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9030 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9031 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9032
9033 /* Memory arbiter control block */
9034 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9035 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9036
9037 /* Buffer manager control block */
9038 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9039 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9040 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9041 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9042 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9043 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9044 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9045 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9046
9047 /* Read DMA control block */
9048 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9049 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9050
9051 /* Write DMA control block */
9052 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9053 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9054
9055 /* DMA completion block */
9056 printk("DEBUG: DMAC_MODE[%08x]\n",
9057 tr32(DMAC_MODE));
9058
9059 /* GRC block */
9060 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9061 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9062 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9063 tr32(GRC_LOCAL_CTRL));
9064
9065 /* TG3_BDINFOs */
9066 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9067 tr32(RCVDBDI_JUMBO_BD + 0x0),
9068 tr32(RCVDBDI_JUMBO_BD + 0x4),
9069 tr32(RCVDBDI_JUMBO_BD + 0x8),
9070 tr32(RCVDBDI_JUMBO_BD + 0xc));
9071 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9072 tr32(RCVDBDI_STD_BD + 0x0),
9073 tr32(RCVDBDI_STD_BD + 0x4),
9074 tr32(RCVDBDI_STD_BD + 0x8),
9075 tr32(RCVDBDI_STD_BD + 0xc));
9076 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9077 tr32(RCVDBDI_MINI_BD + 0x0),
9078 tr32(RCVDBDI_MINI_BD + 0x4),
9079 tr32(RCVDBDI_MINI_BD + 0x8),
9080 tr32(RCVDBDI_MINI_BD + 0xc));
9081
9082 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9083 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9084 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9085 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9086 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9087 val32, val32_2, val32_3, val32_4);
9088
9089 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9090 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9091 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9092 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9093 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9094 val32, val32_2, val32_3, val32_4);
9095
9096 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9097 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9098 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9099 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9100 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9101 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9102 val32, val32_2, val32_3, val32_4, val32_5);
9103
9104 /* SW status block */
898a56f8
MC		 9105 printk(KERN_DEBUG
9106 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9107 sblk->status,
9108 sblk->status_tag,
9109 sblk->rx_jumbo_consumer,
9110 sblk->rx_consumer,
9111 sblk->rx_mini_consumer,
9112 sblk->idx[0].rx_producer,
9113 sblk->idx[0].tx_consumer);
1da177e4
LT		 9114
9115 /* SW statistics block */
9116 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9117 ((u32 *)tp->hw_stats)[0],
9118 ((u32 *)tp->hw_stats)[1],
9119 ((u32 *)tp->hw_stats)[2],
9120 ((u32 *)tp->hw_stats)[3]);
9121
9122 /* Mailboxes */
9123 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9124 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9125 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9126 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9127 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9128
9129 /* NIC side send descriptors. */
9130 for (i = 0; i < 6; i++) {
9131 unsigned long txd;
9132
9133 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9134 + (i * sizeof(struct tg3_tx_buffer_desc));
9135 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9136 i,
9137 readl(txd + 0x0), readl(txd + 0x4),
9138 readl(txd + 0x8), readl(txd + 0xc));
9139 }
9140
9141 /* NIC side RX descriptors. */
9142 for (i = 0; i < 6; i++) {
9143 unsigned long rxd;
9144
9145 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9146 + (i * sizeof(struct tg3_rx_buffer_desc));
9147 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9148 i,
9149 readl(rxd + 0x0), readl(rxd + 0x4),
9150 readl(rxd + 0x8), readl(rxd + 0xc));
9151 rxd += (4 * sizeof(u32));
9152 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9153 i,
9154 readl(rxd + 0x0), readl(rxd + 0x4),
9155 readl(rxd + 0x8), readl(rxd + 0xc));
9156 }
9157
9158 for (i = 0; i < 6; i++) {
9159 unsigned long rxd;
9160
9161 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9162 + (i * sizeof(struct tg3_rx_buffer_desc));
9163 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9164 i,
9165 readl(rxd + 0x0), readl(rxd + 0x4),
9166 readl(rxd + 0x8), readl(rxd + 0xc));
9167 rxd += (4 * sizeof(u32));
9168 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9169 i,
9170 readl(rxd + 0x0), readl(rxd + 0x4),
9171 readl(rxd + 0x8), readl(rxd + 0xc));
9172 }
9173}
9174#endif
9175
9176static struct net_device_stats *tg3_get_stats(struct net_device *);
9177static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9178
9179static int tg3_close(struct net_device *dev)
9180{
4f125f42 9181 int i;
1da177e4
LT		 9182 struct tg3 *tp = netdev_priv(dev);
9183
fed97810 9184 tg3_napi_disable(tp);
28e53bdd 9185 cancel_work_sync(&tp->reset_task);
7faa006f 9186
fe5f5787 9187 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9188
9189 del_timer_sync(&tp->timer);
9190
24bb4fb6
MC		 9191 tg3_phy_stop(tp);
9192
f47c11ee 9193 tg3_full_lock(tp, 1);
1da177e4
LT		 9194#if 0
9195 tg3_dump_state(tp);
9196#endif
9197
9198 tg3_disable_ints(tp);
9199
944d980e 9200 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9201 tg3_free_rings(tp);
5cf64b8a 9202 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9203
f47c11ee 9204 tg3_full_unlock(tp);
1da177e4 9205
4f125f42
MC		 9206 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9207 struct tg3_napi *tnapi = &tp->napi[i];
9208 free_irq(tnapi->irq_vec, tnapi);
9209 }
07b0173c
MC		 9210
9211 tg3_ints_fini(tp);
1da177e4
LT		 9212
9213 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9214 sizeof(tp->net_stats_prev));
9215 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9216 sizeof(tp->estats_prev));
9217
9218 tg3_free_consistent(tp);
9219
bc1c7567
MC		 9220 tg3_set_power_state(tp, PCI_D3hot);
9221
9222 netif_carrier_off(tp->dev);
9223
1da177e4
LT		 9224 return 0;
9225}
9226
9227static inline unsigned long get_stat64(tg3_stat64_t *val)
9228{
9229 unsigned long ret;
9230
9231#if (BITS_PER_LONG == 32)
9232 ret = val->low;
9233#else
9234 ret = ((u64)val->high << 32) | ((u64)val->low);
9235#endif
9236 return ret;
9237}
9238
816f8b86
SB		 9239static inline u64 get_estat64(tg3_stat64_t *val)
9240{
9241 return ((u64)val->high << 32) | ((u64)val->low);
9242}
9243
1da177e4
LT		 9244static unsigned long calc_crc_errors(struct tg3 *tp)
9245{
9246 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9247
9248 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9251 u32 val;
9252
f47c11ee 9253 spin_lock_bh(&tp->lock);
569a5df8
MC		 9254 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9255 tg3_writephy(tp, MII_TG3_TEST1,
9256 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9257 tg3_readphy(tp, 0x14, &val);
9258 } else
9259 val = 0;
f47c11ee 9260 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9261
9262 tp->phy_crc_errors += val;
9263
9264 return tp->phy_crc_errors;
9265 }
9266
9267 return get_stat64(&hw_stats->rx_fcs_errors);
9268}
9269
9270#define ESTAT_ADD(member) \
9271 estats->member = old_estats->member + \
816f8b86 9272 get_estat64(&hw_stats->member)
1da177e4
LT		 9273
9274static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9275{
9276 struct tg3_ethtool_stats *estats = &tp->estats;
9277 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9278 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9279
9280 if (!hw_stats)
9281 return old_estats;
9282
9283 ESTAT_ADD(rx_octets);
9284 ESTAT_ADD(rx_fragments);
9285 ESTAT_ADD(rx_ucast_packets);
9286 ESTAT_ADD(rx_mcast_packets);
9287 ESTAT_ADD(rx_bcast_packets);
9288 ESTAT_ADD(rx_fcs_errors);
9289 ESTAT_ADD(rx_align_errors);
9290 ESTAT_ADD(rx_xon_pause_rcvd);
9291 ESTAT_ADD(rx_xoff_pause_rcvd);
9292 ESTAT_ADD(rx_mac_ctrl_rcvd);
9293 ESTAT_ADD(rx_xoff_entered);
9294 ESTAT_ADD(rx_frame_too_long_errors);
9295 ESTAT_ADD(rx_jabbers);
9296 ESTAT_ADD(rx_undersize_packets);
9297 ESTAT_ADD(rx_in_length_errors);
9298 ESTAT_ADD(rx_out_length_errors);
9299 ESTAT_ADD(rx_64_or_less_octet_packets);
9300 ESTAT_ADD(rx_65_to_127_octet_packets);
9301 ESTAT_ADD(rx_128_to_255_octet_packets);
9302 ESTAT_ADD(rx_256_to_511_octet_packets);
9303 ESTAT_ADD(rx_512_to_1023_octet_packets);
9304 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9305 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9306 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9307 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9308 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9309
9310 ESTAT_ADD(tx_octets);
9311 ESTAT_ADD(tx_collisions);
9312 ESTAT_ADD(tx_xon_sent);
9313 ESTAT_ADD(tx_xoff_sent);
9314 ESTAT_ADD(tx_flow_control);
9315 ESTAT_ADD(tx_mac_errors);
9316 ESTAT_ADD(tx_single_collisions);
9317 ESTAT_ADD(tx_mult_collisions);
9318 ESTAT_ADD(tx_deferred);
9319 ESTAT_ADD(tx_excessive_collisions);
9320 ESTAT_ADD(tx_late_collisions);
9321 ESTAT_ADD(tx_collide_2times);
9322 ESTAT_ADD(tx_collide_3times);
9323 ESTAT_ADD(tx_collide_4times);
9324 ESTAT_ADD(tx_collide_5times);
9325 ESTAT_ADD(tx_collide_6times);
9326 ESTAT_ADD(tx_collide_7times);
9327 ESTAT_ADD(tx_collide_8times);
9328 ESTAT_ADD(tx_collide_9times);
9329 ESTAT_ADD(tx_collide_10times);
9330 ESTAT_ADD(tx_collide_11times);
9331 ESTAT_ADD(tx_collide_12times);
9332 ESTAT_ADD(tx_collide_13times);
9333 ESTAT_ADD(tx_collide_14times);
9334 ESTAT_ADD(tx_collide_15times);
9335 ESTAT_ADD(tx_ucast_packets);
9336 ESTAT_ADD(tx_mcast_packets);
9337 ESTAT_ADD(tx_bcast_packets);
9338 ESTAT_ADD(tx_carrier_sense_errors);
9339 ESTAT_ADD(tx_discards);
9340 ESTAT_ADD(tx_errors);
9341
9342 ESTAT_ADD(dma_writeq_full);
9343 ESTAT_ADD(dma_write_prioq_full);
9344 ESTAT_ADD(rxbds_empty);
9345 ESTAT_ADD(rx_discards);
9346 ESTAT_ADD(rx_errors);
9347 ESTAT_ADD(rx_threshold_hit);
9348
9349 ESTAT_ADD(dma_readq_full);
9350 ESTAT_ADD(dma_read_prioq_full);
9351 ESTAT_ADD(tx_comp_queue_full);
9352
9353 ESTAT_ADD(ring_set_send_prod_index);
9354 ESTAT_ADD(ring_status_update);
9355 ESTAT_ADD(nic_irqs);
9356 ESTAT_ADD(nic_avoided_irqs);
9357 ESTAT_ADD(nic_tx_threshold_hit);
9358
9359 return estats;
9360}
9361
9362static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9363{
9364 struct tg3 *tp = netdev_priv(dev);
9365 struct net_device_stats *stats = &tp->net_stats;
9366 struct net_device_stats *old_stats = &tp->net_stats_prev;
9367 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9368
9369 if (!hw_stats)
9370 return old_stats;
9371
9372 stats->rx_packets = old_stats->rx_packets +
9373 get_stat64(&hw_stats->rx_ucast_packets) +
9374 get_stat64(&hw_stats->rx_mcast_packets) +
9375 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9376
1da177e4
LT		 9377 stats->tx_packets = old_stats->tx_packets +
9378 get_stat64(&hw_stats->tx_ucast_packets) +
9379 get_stat64(&hw_stats->tx_mcast_packets) +
9380 get_stat64(&hw_stats->tx_bcast_packets);
9381
9382 stats->rx_bytes = old_stats->rx_bytes +
9383 get_stat64(&hw_stats->rx_octets);
9384 stats->tx_bytes = old_stats->tx_bytes +
9385 get_stat64(&hw_stats->tx_octets);
9386
9387 stats->rx_errors = old_stats->rx_errors +
4f63b877 9388 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9389 stats->tx_errors = old_stats->tx_errors +
9390 get_stat64(&hw_stats->tx_errors) +
9391 get_stat64(&hw_stats->tx_mac_errors) +
9392 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9393 get_stat64(&hw_stats->tx_discards);
9394
9395 stats->multicast = old_stats->multicast +
9396 get_stat64(&hw_stats->rx_mcast_packets);
9397 stats->collisions = old_stats->collisions +
9398 get_stat64(&hw_stats->tx_collisions);
9399
9400 stats->rx_length_errors = old_stats->rx_length_errors +
9401 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9402 get_stat64(&hw_stats->rx_undersize_packets);
9403
9404 stats->rx_over_errors = old_stats->rx_over_errors +
9405 get_stat64(&hw_stats->rxbds_empty);
9406 stats->rx_frame_errors = old_stats->rx_frame_errors +
9407 get_stat64(&hw_stats->rx_align_errors);
9408 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9409 get_stat64(&hw_stats->tx_discards);
9410 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9411 get_stat64(&hw_stats->tx_carrier_sense_errors);
9412
9413 stats->rx_crc_errors = old_stats->rx_crc_errors +
9414 calc_crc_errors(tp);
9415
4f63b877
JL		 9416 stats->rx_missed_errors = old_stats->rx_missed_errors +
9417 get_stat64(&hw_stats->rx_discards);
9418
1da177e4
LT		 9419 return stats;
9420}
9421
9422static inline u32 calc_crc(unsigned char *buf, int len)
9423{
9424 u32 reg;
9425 u32 tmp;
9426 int j, k;
9427
9428 reg = 0xffffffff;
9429
9430 for (j = 0; j < len; j++) {
9431 reg ^= buf[j];
9432
9433 for (k = 0; k < 8; k++) {
9434 tmp = reg & 0x01;
9435
9436 reg >>= 1;
9437
9438 if (tmp) {
9439 reg ^= 0xedb88320;
9440 }
9441 }
9442 }
9443
9444 return ~reg;
9445}
9446
9447static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9448{
9449 /* accept or reject all multicast frames */
9450 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9451 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9452 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9453 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9454}
9455
9456static void __tg3_set_rx_mode(struct net_device *dev)
9457{
9458 struct tg3 *tp = netdev_priv(dev);
9459 u32 rx_mode;
9460
9461 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9462 RX_MODE_KEEP_VLAN_TAG);
9463
9464 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9465 * flag clear.
9466 */
9467#if TG3_VLAN_TAG_USED
9468 if (!tp->vlgrp &&
9469 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9470 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9471#else
9472 /* By definition, VLAN is disabled always in this
9473 * case.
9474 */
9475 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9476 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9477#endif
9478
9479 if (dev->flags & IFF_PROMISC) {
9480 /* Promiscuous mode. */
9481 rx_mode |= RX_MODE_PROMISC;
9482 } else if (dev->flags & IFF_ALLMULTI) {
9483 /* Accept all multicast. */
9484 tg3_set_multi (tp, 1);
4cd24eaf 9485 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 9486 /* Reject all multicast. */
9487 tg3_set_multi (tp, 0);
9488 } else {
9489 /* Accept one or more multicast(s). */
9490 struct dev_mc_list *mclist;
9491 unsigned int i;
9492 u32 mc_filter[4] = { 0, };
9493 u32 regidx;
9494 u32 bit;
9495 u32 crc;
9496
4cd24eaf 9497 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
1da177e4
LT		 9498 i++, mclist = mclist->next) {
9499
9500 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9501 bit = ~crc & 0x7f;
9502 regidx = (bit & 0x60) >> 5;
9503 bit &= 0x1f;
9504 mc_filter[regidx] |= (1 << bit);
9505 }
9506
9507 tw32(MAC_HASH_REG_0, mc_filter[0]);
9508 tw32(MAC_HASH_REG_1, mc_filter[1]);
9509 tw32(MAC_HASH_REG_2, mc_filter[2]);
9510 tw32(MAC_HASH_REG_3, mc_filter[3]);
9511 }
9512
9513 if (rx_mode != tp->rx_mode) {
9514 tp->rx_mode = rx_mode;
9515 tw32_f(MAC_RX_MODE, rx_mode);
9516 udelay(10);
9517 }
9518}
9519
9520static void tg3_set_rx_mode(struct net_device *dev)
9521{
9522 struct tg3 *tp = netdev_priv(dev);
9523
e75f7c90
MC		 9524 if (!netif_running(dev))
9525 return;
9526
f47c11ee 9527 tg3_full_lock(tp, 0);
1da177e4 9528 __tg3_set_rx_mode(dev);
f47c11ee 9529 tg3_full_unlock(tp);
1da177e4
LT		 9530}
9531
9532#define TG3_REGDUMP_LEN (32 * 1024)
9533
9534static int tg3_get_regs_len(struct net_device *dev)
9535{
9536 return TG3_REGDUMP_LEN;
9537}
9538
9539static void tg3_get_regs(struct net_device *dev,
9540 struct ethtool_regs *regs, void *_p)
9541{
9542 u32 *p = _p;
9543 struct tg3 *tp = netdev_priv(dev);
9544 u8 *orig_p = _p;
9545 int i;
9546
9547 regs->version = 0;
9548
9549 memset(p, 0, TG3_REGDUMP_LEN);
9550
bc1c7567
MC		 9551 if (tp->link_config.phy_is_low_power)
9552 return;
9553
f47c11ee 9554 tg3_full_lock(tp, 0);
1da177e4
LT		 9555
9556#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9557#define GET_REG32_LOOP(base,len) \
9558do { p = (u32 *)(orig_p + (base)); \
9559 for (i = 0; i < len; i += 4) \
9560 __GET_REG32((base) + i); \
9561} while (0)
9562#define GET_REG32_1(reg) \
9563do { p = (u32 *)(orig_p + (reg)); \
9564 __GET_REG32((reg)); \
9565} while (0)
9566
9567 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9568 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9569 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9570 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9571 GET_REG32_1(SNDDATAC_MODE);
9572 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9573 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9574 GET_REG32_1(SNDBDC_MODE);
9575 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9576 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9577 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9578 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9579 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9580 GET_REG32_1(RCVDCC_MODE);
9581 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9582 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9583 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9584 GET_REG32_1(MBFREE_MODE);
9585 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9586 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9587 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9588 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9589 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9590 GET_REG32_1(RX_CPU_MODE);
9591 GET_REG32_1(RX_CPU_STATE);
9592 GET_REG32_1(RX_CPU_PGMCTR);
9593 GET_REG32_1(RX_CPU_HWBKPT);
9594 GET_REG32_1(TX_CPU_MODE);
9595 GET_REG32_1(TX_CPU_STATE);
9596 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9597 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9598 GET_REG32_LOOP(FTQ_RESET, 0x120);
9599 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9600 GET_REG32_1(DMAC_MODE);
9601 GET_REG32_LOOP(GRC_MODE, 0x4c);
9602 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9603 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9604
9605#undef __GET_REG32
9606#undef GET_REG32_LOOP
9607#undef GET_REG32_1
9608
f47c11ee 9609 tg3_full_unlock(tp);
1da177e4
LT		 9610}
9611
9612static int tg3_get_eeprom_len(struct net_device *dev)
9613{
9614 struct tg3 *tp = netdev_priv(dev);
9615
9616 return tp->nvram_size;
9617}
9618
1da177e4
LT		 9619static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9620{
9621 struct tg3 *tp = netdev_priv(dev);
9622 int ret;
9623 u8 *pd;
b9fc7dc5 9624 u32 i, offset, len, b_offset, b_count;
a9dc529d 9625 __be32 val;
1da177e4 9626
df259d8c
MC		 9627 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9628 return -EINVAL;
9629
bc1c7567
MC		 9630 if (tp->link_config.phy_is_low_power)
9631 return -EAGAIN;
9632
1da177e4
LT		 9633 offset = eeprom->offset;
9634 len = eeprom->len;
9635 eeprom->len = 0;
9636
9637 eeprom->magic = TG3_EEPROM_MAGIC;
9638
9639 if (offset & 3) {
9640 /* adjustments to start on required 4 byte boundary */
9641 b_offset = offset & 3;
9642 b_count = 4 - b_offset;
9643 if (b_count > len) {
9644 /* i.e. offset=1 len=2 */
9645 b_count = len;
9646 }
a9dc529d 9647 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9648 if (ret)
9649 return ret;
1da177e4
LT		 9650 memcpy(data, ((char*)&val) + b_offset, b_count);
9651 len -= b_count;
9652 offset += b_count;
9653 eeprom->len += b_count;
9654 }
9655
9656 /* read bytes upto the last 4 byte boundary */
9657 pd = &data[eeprom->len];
9658 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9659 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9660 if (ret) {
9661 eeprom->len += i;
9662 return ret;
9663 }
1da177e4
LT		 9664 memcpy(pd + i, &val, 4);
9665 }
9666 eeprom->len += i;
9667
9668 if (len & 3) {
9669 /* read last bytes not ending on 4 byte boundary */
9670 pd = &data[eeprom->len];
9671 b_count = len & 3;
9672 b_offset = offset + len - b_count;
a9dc529d 9673 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9674 if (ret)
9675 return ret;
b9fc7dc5 9676 memcpy(pd, &val, b_count);
1da177e4
LT		 9677 eeprom->len += b_count;
9678 }
9679 return 0;
9680}
9681
6aa20a22 9682static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9683
9684static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9685{
9686 struct tg3 *tp = netdev_priv(dev);
9687 int ret;
b9fc7dc5 9688 u32 offset, len, b_offset, odd_len;
1da177e4 9689 u8 *buf;
a9dc529d 9690 __be32 start, end;
1da177e4 9691
bc1c7567
MC		 9692 if (tp->link_config.phy_is_low_power)
9693 return -EAGAIN;
9694
df259d8c
MC		 9695 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9696 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9697 return -EINVAL;
9698
9699 offset = eeprom->offset;
9700 len = eeprom->len;
9701
9702 if ((b_offset = (offset & 3))) {
9703 /* adjustments to start on required 4 byte boundary */
a9dc529d 9704 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9705 if (ret)
9706 return ret;
1da177e4
LT		 9707 len += b_offset;
9708 offset &= ~3;
1c8594b4
MC		 9709 if (len < 4)
9710 len = 4;
1da177e4
LT		 9711 }
9712
9713 odd_len = 0;
1c8594b4 9714 if (len & 3) {
1da177e4
LT		 9715 /* adjustments to end on required 4 byte boundary */
9716 odd_len = 1;
9717 len = (len + 3) & ~3;
a9dc529d 9718 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9719 if (ret)
9720 return ret;
1da177e4
LT		 9721 }
9722
9723 buf = data;
9724 if (b_offset || odd_len) {
9725 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9726 if (!buf)
1da177e4
LT		 9727 return -ENOMEM;
9728 if (b_offset)
9729 memcpy(buf, &start, 4);
9730 if (odd_len)
9731 memcpy(buf+len-4, &end, 4);
9732 memcpy(buf + b_offset, data, eeprom->len);
9733 }
9734
9735 ret = tg3_nvram_write_block(tp, offset, len, buf);
9736
9737 if (buf != data)
9738 kfree(buf);
9739
9740 return ret;
9741}
9742
9743static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9744{
b02fd9e3
MC		 9745 struct tg3 *tp = netdev_priv(dev);
9746
9747 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9748 struct phy_device *phydev;
b02fd9e3
MC		 9749 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9750 return -EAGAIN;
3f0e3ad7
MC		 9751 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9752 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9753 }
6aa20a22 9754
1da177e4
LT		 9755 cmd->supported = (SUPPORTED_Autoneg);
9756
9757 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9758 cmd->supported |= (SUPPORTED_1000baseT_Half |
9759 SUPPORTED_1000baseT_Full);
9760
ef348144 9761 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9762 cmd->supported |= (SUPPORTED_100baseT_Half |
9763 SUPPORTED_100baseT_Full |
9764 SUPPORTED_10baseT_Half |
9765 SUPPORTED_10baseT_Full |
3bebab59 9766 SUPPORTED_TP);
ef348144
KK		 9767 cmd->port = PORT_TP;
9768 } else {
1da177e4 9769 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9770 cmd->port = PORT_FIBRE;
9771 }
6aa20a22 9772
1da177e4
LT		 9773 cmd->advertising = tp->link_config.advertising;
9774 if (netif_running(dev)) {
9775 cmd->speed = tp->link_config.active_speed;
9776 cmd->duplex = tp->link_config.active_duplex;
9777 }
882e9793 9778 cmd->phy_address = tp->phy_addr;
7e5856bd 9779 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9780 cmd->autoneg = tp->link_config.autoneg;
9781 cmd->maxtxpkt = 0;
9782 cmd->maxrxpkt = 0;
9783 return 0;
9784}
6aa20a22 9785
1da177e4
LT		 9786static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9787{
9788 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9789
b02fd9e3 9790 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9791 struct phy_device *phydev;
b02fd9e3
MC		 9792 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9793 return -EAGAIN;
3f0e3ad7
MC		 9794 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9795 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9796 }
9797
7e5856bd
MC		 9798 if (cmd->autoneg != AUTONEG_ENABLE &&
9799 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9800 return -EINVAL;
7e5856bd
MC		 9801
9802 if (cmd->autoneg == AUTONEG_DISABLE &&
9803 cmd->duplex != DUPLEX_FULL &&
9804 cmd->duplex != DUPLEX_HALF)
37ff238d 9805 return -EINVAL;
1da177e4 9806
7e5856bd
MC		 9807 if (cmd->autoneg == AUTONEG_ENABLE) {
9808 u32 mask = ADVERTISED_Autoneg |
9809 ADVERTISED_Pause |
9810 ADVERTISED_Asym_Pause;
9811
9812 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9813 mask |= ADVERTISED_1000baseT_Half |
9814 ADVERTISED_1000baseT_Full;
9815
9816 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9817 mask |= ADVERTISED_100baseT_Half |
9818 ADVERTISED_100baseT_Full |
9819 ADVERTISED_10baseT_Half |
9820 ADVERTISED_10baseT_Full |
9821 ADVERTISED_TP;
9822 else
9823 mask |= ADVERTISED_FIBRE;
9824
9825 if (cmd->advertising & ~mask)
9826 return -EINVAL;
9827
9828 mask &= (ADVERTISED_1000baseT_Half |
9829 ADVERTISED_1000baseT_Full |
9830 ADVERTISED_100baseT_Half |
9831 ADVERTISED_100baseT_Full |
9832 ADVERTISED_10baseT_Half |
9833 ADVERTISED_10baseT_Full);
9834
9835 cmd->advertising &= mask;
9836 } else {
9837 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9838 if (cmd->speed != SPEED_1000)
9839 return -EINVAL;
9840
9841 if (cmd->duplex != DUPLEX_FULL)
9842 return -EINVAL;
9843 } else {
9844 if (cmd->speed != SPEED_100 &&
9845 cmd->speed != SPEED_10)
9846 return -EINVAL;
9847 }
9848 }
9849
f47c11ee 9850 tg3_full_lock(tp, 0);
1da177e4
LT		 9851
9852 tp->link_config.autoneg = cmd->autoneg;
9853 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9854 tp->link_config.advertising = (cmd->advertising |
9855 ADVERTISED_Autoneg);
1da177e4
LT		 9856 tp->link_config.speed = SPEED_INVALID;
9857 tp->link_config.duplex = DUPLEX_INVALID;
9858 } else {
9859 tp->link_config.advertising = 0;
9860 tp->link_config.speed = cmd->speed;
9861 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9862 }
6aa20a22 9863
24fcad6b
MC		 9864 tp->link_config.orig_speed = tp->link_config.speed;
9865 tp->link_config.orig_duplex = tp->link_config.duplex;
9866 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9867
1da177e4
LT		 9868 if (netif_running(dev))
9869 tg3_setup_phy(tp, 1);
9870
f47c11ee 9871 tg3_full_unlock(tp);
6aa20a22 9872
1da177e4
LT		 9873 return 0;
9874}
6aa20a22 9875
1da177e4
LT		 9876static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9877{
9878 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9879
1da177e4
LT		 9880 strcpy(info->driver, DRV_MODULE_NAME);
9881 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9882 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9883 strcpy(info->bus_info, pci_name(tp->pdev));
9884}
6aa20a22 9885
1da177e4
LT		 9886static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9887{
9888 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9889
12dac075
RW		 9890 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9891 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9892 wol->supported = WAKE_MAGIC;
9893 else
9894 wol->supported = 0;
1da177e4 9895 wol->wolopts = 0;
05ac4cb7
MC		 9896 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9897 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9898 wol->wolopts = WAKE_MAGIC;
9899 memset(&wol->sopass, 0, sizeof(wol->sopass));
9900}
6aa20a22 9901
1da177e4
LT		 9902static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9903{
9904 struct tg3 *tp = netdev_priv(dev);
12dac075 9905 struct device *dp = &tp->pdev->dev;
6aa20a22 9906
1da177e4
LT		 9907 if (wol->wolopts & ~WAKE_MAGIC)
9908 return -EINVAL;
9909 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9910 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9911 return -EINVAL;
6aa20a22 9912
f47c11ee 9913 spin_lock_bh(&tp->lock);
12dac075 9914 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9915 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9916 device_set_wakeup_enable(dp, true);
9917 } else {
1da177e4 9918 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9919 device_set_wakeup_enable(dp, false);
9920 }
f47c11ee 9921 spin_unlock_bh(&tp->lock);
6aa20a22 9922
1da177e4
LT		 9923 return 0;
9924}
6aa20a22 9925
1da177e4
LT		 9926static u32 tg3_get_msglevel(struct net_device *dev)
9927{
9928 struct tg3 *tp = netdev_priv(dev);
9929 return tp->msg_enable;
9930}
6aa20a22 9931
1da177e4
LT		 9932static void tg3_set_msglevel(struct net_device *dev, u32 value)
9933{
9934 struct tg3 *tp = netdev_priv(dev);
9935 tp->msg_enable = value;
9936}
6aa20a22 9937
1da177e4
LT		 9938static int tg3_set_tso(struct net_device *dev, u32 value)
9939{
9940 struct tg3 *tp = netdev_priv(dev);
9941
9942 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9943 if (value)
9944 return -EINVAL;
9945 return 0;
9946 }
027455ad 9947 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9948 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9949 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9950 if (value) {
b0026624 9951 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9952 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9954 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9955 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9957 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9958 dev->features |= NETIF_F_TSO_ECN;
9959 } else
9960 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9961 }
1da177e4
LT		 9962 return ethtool_op_set_tso(dev, value);
9963}
6aa20a22 9964
1da177e4
LT		 9965static int tg3_nway_reset(struct net_device *dev)
9966{
9967 struct tg3 *tp = netdev_priv(dev);
1da177e4 9968 int r;
6aa20a22 9969
1da177e4
LT		 9970 if (!netif_running(dev))
9971 return -EAGAIN;
9972
c94e3941
MC		 9973 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9974 return -EINVAL;
9975
b02fd9e3
MC		 9976 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9977 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9978 return -EAGAIN;
3f0e3ad7 9979 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9980 } else {
9981 u32 bmcr;
9982
9983 spin_lock_bh(&tp->lock);
9984 r = -EINVAL;
9985 tg3_readphy(tp, MII_BMCR, &bmcr);
9986 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9987 ((bmcr & BMCR_ANENABLE) ||
9988 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9989 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9990 BMCR_ANENABLE);
9991 r = 0;
9992 }
9993 spin_unlock_bh(&tp->lock);
1da177e4 9994 }
6aa20a22 9995
1da177e4
LT		 9996 return r;
9997}
6aa20a22 9998
1da177e4
LT		 9999static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10000{
10001 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10002
1da177e4
LT		 10003 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
10004 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 10005 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10006 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
10007 else
10008 ering->rx_jumbo_max_pending = 0;
10009
10010 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 10011
10012 ering->rx_pending = tp->rx_pending;
10013 ering->rx_mini_pending = 0;
4f81c32b
MC		 10014 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10015 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10016 else
10017 ering->rx_jumbo_pending = 0;
10018
f3f3f27e 10019 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 10020}
6aa20a22 10021
1da177e4
LT		 10022static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10023{
10024 struct tg3 *tp = netdev_priv(dev);
646c9edd 10025 int i, irq_sync = 0, err = 0;
6aa20a22 10026
1da177e4
LT		 10027 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10028 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 10029 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10030 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 10031 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 10032 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 10033 return -EINVAL;
6aa20a22 10034
bbe832c0 10035 if (netif_running(dev)) {
b02fd9e3 10036 tg3_phy_stop(tp);
1da177e4 10037 tg3_netif_stop(tp);
bbe832c0
MC		 10038 irq_sync = 1;
10039 }
1da177e4 10040
bbe832c0 10041 tg3_full_lock(tp, irq_sync);
6aa20a22 10042
1da177e4
LT		 10043 tp->rx_pending = ering->rx_pending;
10044
10045 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10046 tp->rx_pending > 63)
10047 tp->rx_pending = 63;
10048 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 10049
10050 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10051 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 10052
10053 if (netif_running(dev)) {
944d980e 10054 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 10055 err = tg3_restart_hw(tp, 1);
10056 if (!err)
10057 tg3_netif_start(tp);
1da177e4
LT		 10058 }
10059
f47c11ee 10060 tg3_full_unlock(tp);
6aa20a22 10061
b02fd9e3
MC		 10062 if (irq_sync && !err)
10063 tg3_phy_start(tp);
10064
b9ec6c1b 10065 return err;
1da177e4 10066}
6aa20a22 10067
1da177e4
LT		 10068static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10069{
10070 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10071
1da177e4 10072 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 10073
e18ce346 10074 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 10075 epause->rx_pause = 1;
10076 else
10077 epause->rx_pause = 0;
10078
e18ce346 10079 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10080 epause->tx_pause = 1;
10081 else
10082 epause->tx_pause = 0;
1da177e4 10083}
6aa20a22 10084
1da177e4
LT		 10085static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10086{
10087 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10088 int err = 0;
6aa20a22 10089
b02fd9e3
MC		 10090 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10091 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10092 return -EAGAIN;
1da177e4 10093
b02fd9e3
MC		 10094 if (epause->autoneg) {
10095 u32 newadv;
10096 struct phy_device *phydev;
f47c11ee 10097
3f0e3ad7 10098 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 10099
b02fd9e3
MC		 10100 if (epause->rx_pause) {
10101 if (epause->tx_pause)
10102 newadv = ADVERTISED_Pause;
10103 else
10104 newadv = ADVERTISED_Pause |
10105 ADVERTISED_Asym_Pause;
10106 } else if (epause->tx_pause) {
10107 newadv = ADVERTISED_Asym_Pause;
10108 } else
10109 newadv = 0;
10110
10111 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10112 u32 oldadv = phydev->advertising &
10113 (ADVERTISED_Pause |
10114 ADVERTISED_Asym_Pause);
10115 if (oldadv != newadv) {
10116 phydev->advertising &=
10117 ~(ADVERTISED_Pause |
10118 ADVERTISED_Asym_Pause);
10119 phydev->advertising |= newadv;
10120 err = phy_start_aneg(phydev);
10121 }
10122 } else {
10123 tp->link_config.advertising &=
10124 ~(ADVERTISED_Pause |
10125 ADVERTISED_Asym_Pause);
10126 tp->link_config.advertising |= newadv;
10127 }
10128 } else {
10129 if (epause->rx_pause)
e18ce346 10130 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10131 else
e18ce346 10132 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10133
b02fd9e3 10134 if (epause->tx_pause)
e18ce346 10135 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10136 else
e18ce346 10137 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10138
10139 if (netif_running(dev))
10140 tg3_setup_flow_control(tp, 0, 0);
10141 }
10142 } else {
10143 int irq_sync = 0;
10144
10145 if (netif_running(dev)) {
10146 tg3_netif_stop(tp);
10147 irq_sync = 1;
10148 }
10149
10150 tg3_full_lock(tp, irq_sync);
10151
10152 if (epause->autoneg)
10153 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10154 else
10155 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10156 if (epause->rx_pause)
e18ce346 10157 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10158 else
e18ce346 10159 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10160 if (epause->tx_pause)
e18ce346 10161 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10162 else
e18ce346 10163 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10164
10165 if (netif_running(dev)) {
10166 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10167 err = tg3_restart_hw(tp, 1);
10168 if (!err)
10169 tg3_netif_start(tp);
10170 }
10171
10172 tg3_full_unlock(tp);
10173 }
6aa20a22 10174
b9ec6c1b 10175 return err;
1da177e4 10176}
6aa20a22 10177
1da177e4
LT		 10178static u32 tg3_get_rx_csum(struct net_device *dev)
10179{
10180 struct tg3 *tp = netdev_priv(dev);
10181 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10182}
6aa20a22 10183
1da177e4
LT		 10184static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10185{
10186 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10187
1da177e4
LT		 10188 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10189 if (data != 0)
10190 return -EINVAL;
10191 return 0;
10192 }
6aa20a22 10193
f47c11ee 10194 spin_lock_bh(&tp->lock);
1da177e4
LT		 10195 if (data)
10196 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10197 else
10198 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10199 spin_unlock_bh(&tp->lock);
6aa20a22 10200
1da177e4
LT		 10201 return 0;
10202}
6aa20a22 10203
1da177e4
LT		 10204static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10205{
10206 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10207
1da177e4
LT		 10208 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10209 if (data != 0)
10210 return -EINVAL;
10211 return 0;
10212 }
6aa20a22 10213
321d32a0 10214 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10215 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10216 else
9c27dbdf 10217 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10218
10219 return 0;
10220}
10221
b9f2c044 10222static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10223{
b9f2c044
JG		 10224 switch (sset) {
10225 case ETH_SS_TEST:
10226 return TG3_NUM_TEST;
10227 case ETH_SS_STATS:
10228 return TG3_NUM_STATS;
10229 default:
10230 return -EOPNOTSUPP;
10231 }
4cafd3f5
MC		 10232}
10233
1da177e4
LT		 10234static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10235{
10236 switch (stringset) {
10237 case ETH_SS_STATS:
10238 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10239 break;
4cafd3f5
MC		 10240 case ETH_SS_TEST:
10241 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10242 break;
1da177e4
LT		 10243 default:
10244 WARN_ON(1); /* we need a WARN() */
10245 break;
10246 }
10247}
10248
4009a93d
MC		 10249static int tg3_phys_id(struct net_device *dev, u32 data)
10250{
10251 struct tg3 *tp = netdev_priv(dev);
10252 int i;
10253
10254 if (!netif_running(tp->dev))
10255 return -EAGAIN;
10256
10257 if (data == 0)
759afc31 10258 data = UINT_MAX / 2;
4009a93d
MC		 10259
10260 for (i = 0; i < (data * 2); i++) {
10261 if ((i % 2) == 0)
10262 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10263 LED_CTRL_1000MBPS_ON |
10264 LED_CTRL_100MBPS_ON |
10265 LED_CTRL_10MBPS_ON |
10266 LED_CTRL_TRAFFIC_OVERRIDE |
10267 LED_CTRL_TRAFFIC_BLINK |
10268 LED_CTRL_TRAFFIC_LED);
6aa20a22 10269
4009a93d
MC		 10270 else
10271 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10272 LED_CTRL_TRAFFIC_OVERRIDE);
10273
10274 if (msleep_interruptible(500))
10275 break;
10276 }
10277 tw32(MAC_LED_CTRL, tp->led_ctrl);
10278 return 0;
10279}
10280
1da177e4
LT		 10281static void tg3_get_ethtool_stats (struct net_device *dev,
10282 struct ethtool_stats *estats, u64 *tmp_stats)
10283{
10284 struct tg3 *tp = netdev_priv(dev);
10285 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10286}
10287
566f86ad 10288#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10289#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10290#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10291#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10292#define NVRAM_SELFBOOT_HW_SIZE 0x20
10293#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10294
10295static int tg3_test_nvram(struct tg3 *tp)
10296{
b9fc7dc5 10297 u32 csum, magic;
a9dc529d 10298 __be32 *buf;
ab0049b4 10299 int i, j, k, err = 0, size;
566f86ad 10300
df259d8c
MC		 10301 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10302 return 0;
10303
e4f34110 10304 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10305 return -EIO;
10306
1b27777a
MC		 10307 if (magic == TG3_EEPROM_MAGIC)
10308 size = NVRAM_TEST_SIZE;
b16250e3 10309 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10310 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10311 TG3_EEPROM_SB_FORMAT_1) {
10312 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10313 case TG3_EEPROM_SB_REVISION_0:
10314 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10315 break;
10316 case TG3_EEPROM_SB_REVISION_2:
10317 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10318 break;
10319 case TG3_EEPROM_SB_REVISION_3:
10320 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10321 break;
10322 default:
10323 return 0;
10324 }
10325 } else
1b27777a 10326 return 0;
b16250e3
MC		 10327 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10328 size = NVRAM_SELFBOOT_HW_SIZE;
10329 else
1b27777a
MC		 10330 return -EIO;
10331
10332 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10333 if (buf == NULL)
10334 return -ENOMEM;
10335
1b27777a
MC		 10336 err = -EIO;
10337 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10338 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10339 if (err)
566f86ad 10340 break;
566f86ad 10341 }
1b27777a 10342 if (i < size)
566f86ad
MC		 10343 goto out;
10344
1b27777a 10345 /* Selfboot format */
a9dc529d 10346 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10347 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10348 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10349 u8 *buf8 = (u8 *) buf, csum8 = 0;
10350
b9fc7dc5 10351 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10352 TG3_EEPROM_SB_REVISION_2) {
10353 /* For rev 2, the csum doesn't include the MBA. */
10354 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10355 csum8 += buf8[i];
10356 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10357 csum8 += buf8[i];
10358 } else {
10359 for (i = 0; i < size; i++)
10360 csum8 += buf8[i];
10361 }
1b27777a 10362
ad96b485
AB		 10363 if (csum8 == 0) {
10364 err = 0;
10365 goto out;
10366 }
10367
10368 err = -EIO;
10369 goto out;
1b27777a 10370 }
566f86ad 10371
b9fc7dc5 10372 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10373 TG3_EEPROM_MAGIC_HW) {
10374 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10375 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10376 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10377
10378 /* Separate the parity bits and the data bytes. */
10379 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10380 if ((i == 0) || (i == 8)) {
10381 int l;
10382 u8 msk;
10383
10384 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10385 parity[k++] = buf8[i] & msk;
10386 i++;
10387 }
10388 else if (i == 16) {
10389 int l;
10390 u8 msk;
10391
10392 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10393 parity[k++] = buf8[i] & msk;
10394 i++;
10395
10396 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10397 parity[k++] = buf8[i] & msk;
10398 i++;
10399 }
10400 data[j++] = buf8[i];
10401 }
10402
10403 err = -EIO;
10404 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10405 u8 hw8 = hweight8(data[i]);
10406
10407 if ((hw8 & 0x1) && parity[i])
10408 goto out;
10409 else if (!(hw8 & 0x1) && !parity[i])
10410 goto out;
10411 }
10412 err = 0;
10413 goto out;
10414 }
10415
566f86ad
MC		 10416 /* Bootstrap checksum at offset 0x10 */
10417 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10418 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10419 goto out;
10420
10421 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10422 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10423 if (csum != be32_to_cpu(buf[0xfc/4]))
10424 goto out;
566f86ad
MC		 10425
10426 err = 0;
10427
10428out:
10429 kfree(buf);
10430 return err;
10431}
10432
ca43007a
MC		 10433#define TG3_SERDES_TIMEOUT_SEC 2
10434#define TG3_COPPER_TIMEOUT_SEC 6
10435
10436static int tg3_test_link(struct tg3 *tp)
10437{
10438 int i, max;
10439
10440 if (!netif_running(tp->dev))
10441 return -ENODEV;
10442
4c987487 10443 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10444 max = TG3_SERDES_TIMEOUT_SEC;
10445 else
10446 max = TG3_COPPER_TIMEOUT_SEC;
10447
10448 for (i = 0; i < max; i++) {
10449 if (netif_carrier_ok(tp->dev))
10450 return 0;
10451
10452 if (msleep_interruptible(1000))
10453 break;
10454 }
10455
10456 return -EIO;
10457}
10458
a71116d1 10459/* Only test the commonly used registers */
30ca3e37 10460static int tg3_test_registers(struct tg3 *tp)
a71116d1 10461{
b16250e3 10462 int i, is_5705, is_5750;
a71116d1
MC		 10463 u32 offset, read_mask, write_mask, val, save_val, read_val;
10464 static struct {
10465 u16 offset;
10466 u16 flags;
10467#define TG3_FL_5705 0x1
10468#define TG3_FL_NOT_5705 0x2
10469#define TG3_FL_NOT_5788 0x4
b16250e3 10470#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10471 u32 read_mask;
10472 u32 write_mask;
10473 } reg_tbl[] = {
10474 /* MAC Control Registers */
10475 { MAC_MODE, TG3_FL_NOT_5705,
10476 0x00000000, 0x00ef6f8c },
10477 { MAC_MODE, TG3_FL_5705,
10478 0x00000000, 0x01ef6b8c },
10479 { MAC_STATUS, TG3_FL_NOT_5705,
10480 0x03800107, 0x00000000 },
10481 { MAC_STATUS, TG3_FL_5705,
10482 0x03800100, 0x00000000 },
10483 { MAC_ADDR_0_HIGH, 0x0000,
10484 0x00000000, 0x0000ffff },
10485 { MAC_ADDR_0_LOW, 0x0000,
10486 0x00000000, 0xffffffff },
10487 { MAC_RX_MTU_SIZE, 0x0000,
10488 0x00000000, 0x0000ffff },
10489 { MAC_TX_MODE, 0x0000,
10490 0x00000000, 0x00000070 },
10491 { MAC_TX_LENGTHS, 0x0000,
10492 0x00000000, 0x00003fff },
10493 { MAC_RX_MODE, TG3_FL_NOT_5705,
10494 0x00000000, 0x000007fc },
10495 { MAC_RX_MODE, TG3_FL_5705,
10496 0x00000000, 0x000007dc },
10497 { MAC_HASH_REG_0, 0x0000,
10498 0x00000000, 0xffffffff },
10499 { MAC_HASH_REG_1, 0x0000,
10500 0x00000000, 0xffffffff },
10501 { MAC_HASH_REG_2, 0x0000,
10502 0x00000000, 0xffffffff },
10503 { MAC_HASH_REG_3, 0x0000,
10504 0x00000000, 0xffffffff },
10505
10506 /* Receive Data and Receive BD Initiator Control Registers. */
10507 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10508 0x00000000, 0xffffffff },
10509 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10510 0x00000000, 0xffffffff },
10511 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10512 0x00000000, 0x00000003 },
10513 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10514 0x00000000, 0xffffffff },
10515 { RCVDBDI_STD_BD+0, 0x0000,
10516 0x00000000, 0xffffffff },
10517 { RCVDBDI_STD_BD+4, 0x0000,
10518 0x00000000, 0xffffffff },
10519 { RCVDBDI_STD_BD+8, 0x0000,
10520 0x00000000, 0xffff0002 },
10521 { RCVDBDI_STD_BD+0xc, 0x0000,
10522 0x00000000, 0xffffffff },
6aa20a22 10523
a71116d1
MC		 10524 /* Receive BD Initiator Control Registers. */
10525 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10526 0x00000000, 0xffffffff },
10527 { RCVBDI_STD_THRESH, TG3_FL_5705,
10528 0x00000000, 0x000003ff },
10529 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10530 0x00000000, 0xffffffff },
6aa20a22 10531
a71116d1
MC		 10532 /* Host Coalescing Control Registers. */
10533 { HOSTCC_MODE, TG3_FL_NOT_5705,
10534 0x00000000, 0x00000004 },
10535 { HOSTCC_MODE, TG3_FL_5705,
10536 0x00000000, 0x000000f6 },
10537 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10538 0x00000000, 0xffffffff },
10539 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10540 0x00000000, 0x000003ff },
10541 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10542 0x00000000, 0xffffffff },
10543 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10544 0x00000000, 0x000003ff },
10545 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10546 0x00000000, 0xffffffff },
10547 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10548 0x00000000, 0x000000ff },
10549 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10550 0x00000000, 0xffffffff },
10551 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10552 0x00000000, 0x000000ff },
10553 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10554 0x00000000, 0xffffffff },
10555 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10556 0x00000000, 0xffffffff },
10557 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10558 0x00000000, 0xffffffff },
10559 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10560 0x00000000, 0x000000ff },
10561 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10562 0x00000000, 0xffffffff },
10563 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10564 0x00000000, 0x000000ff },
10565 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10566 0x00000000, 0xffffffff },
10567 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10568 0x00000000, 0xffffffff },
10569 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10570 0x00000000, 0xffffffff },
10571 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10572 0x00000000, 0xffffffff },
10573 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10574 0x00000000, 0xffffffff },
10575 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10576 0xffffffff, 0x00000000 },
10577 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10578 0xffffffff, 0x00000000 },
10579
10580 /* Buffer Manager Control Registers. */
b16250e3 10581 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10582 0x00000000, 0x007fff80 },
b16250e3 10583 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10584 0x00000000, 0x007fffff },
10585 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10586 0x00000000, 0x0000003f },
10587 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10588 0x00000000, 0x000001ff },
10589 { BUFMGR_MB_HIGH_WATER, 0x0000,
10590 0x00000000, 0x000001ff },
10591 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10592 0xffffffff, 0x00000000 },
10593 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10594 0xffffffff, 0x00000000 },
6aa20a22 10595
a71116d1
MC		 10596 /* Mailbox Registers */
10597 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10598 0x00000000, 0x000001ff },
10599 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10600 0x00000000, 0x000001ff },
10601 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10602 0x00000000, 0x000007ff },
10603 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10604 0x00000000, 0x000001ff },
10605
10606 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10607 };
10608
b16250e3
MC		 10609 is_5705 = is_5750 = 0;
10610 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10611 is_5705 = 1;
b16250e3
MC		 10612 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10613 is_5750 = 1;
10614 }
a71116d1
MC		 10615
10616 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10617 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10618 continue;
10619
10620 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10621 continue;
10622
10623 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10624 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10625 continue;
10626
b16250e3
MC		 10627 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10628 continue;
10629
a71116d1
MC		 10630 offset = (u32) reg_tbl[i].offset;
10631 read_mask = reg_tbl[i].read_mask;
10632 write_mask = reg_tbl[i].write_mask;
10633
10634 /* Save the original register content */
10635 save_val = tr32(offset);
10636
10637 /* Determine the read-only value. */
10638 read_val = save_val & read_mask;
10639
10640 /* Write zero to the register, then make sure the read-only bits
10641 * are not changed and the read/write bits are all zeros.
10642 */
10643 tw32(offset, 0);
10644
10645 val = tr32(offset);
10646
10647 /* Test the read-only and read/write bits. */
10648 if (((val & read_mask) != read_val) || (val & write_mask))
10649 goto out;
10650
10651 /* Write ones to all the bits defined by RdMask and WrMask, then
10652 * make sure the read-only bits are not changed and the
10653 * read/write bits are all ones.
10654 */
10655 tw32(offset, read_mask | write_mask);
10656
10657 val = tr32(offset);
10658
10659 /* Test the read-only bits. */
10660 if ((val & read_mask) != read_val)
10661 goto out;
10662
10663 /* Test the read/write bits. */
10664 if ((val & write_mask) != write_mask)
10665 goto out;
10666
10667 tw32(offset, save_val);
10668 }
10669
10670 return 0;
10671
10672out:
9f88f29f
MC		 10673 if (netif_msg_hw(tp))
10674 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10675 offset);
a71116d1
MC		 10676 tw32(offset, save_val);
10677 return -EIO;
10678}
10679
7942e1db
MC		 10680static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10681{
f71e1309 10682 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10683 int i;
10684 u32 j;
10685
e9edda69 10686 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10687 for (j = 0; j < len; j += 4) {
10688 u32 val;
10689
10690 tg3_write_mem(tp, offset + j, test_pattern[i]);
10691 tg3_read_mem(tp, offset + j, &val);
10692 if (val != test_pattern[i])
10693 return -EIO;
10694 }
10695 }
10696 return 0;
10697}
10698
10699static int tg3_test_memory(struct tg3 *tp)
10700{
10701 static struct mem_entry {
10702 u32 offset;
10703 u32 len;
10704 } mem_tbl_570x[] = {
38690194 10705 { 0x00000000, 0x00b50},
7942e1db
MC		 10706 { 0x00002000, 0x1c000},
10707 { 0xffffffff, 0x00000}
10708 }, mem_tbl_5705[] = {
10709 { 0x00000100, 0x0000c},
10710 { 0x00000200, 0x00008},
7942e1db
MC		 10711 { 0x00004000, 0x00800},
10712 { 0x00006000, 0x01000},
10713 { 0x00008000, 0x02000},
10714 { 0x00010000, 0x0e000},
10715 { 0xffffffff, 0x00000}
79f4d13a
MC		 10716 }, mem_tbl_5755[] = {
10717 { 0x00000200, 0x00008},
10718 { 0x00004000, 0x00800},
10719 { 0x00006000, 0x00800},
10720 { 0x00008000, 0x02000},
10721 { 0x00010000, 0x0c000},
10722 { 0xffffffff, 0x00000}
b16250e3
MC		 10723 }, mem_tbl_5906[] = {
10724 { 0x00000200, 0x00008},
10725 { 0x00004000, 0x00400},
10726 { 0x00006000, 0x00400},
10727 { 0x00008000, 0x01000},
10728 { 0x00010000, 0x01000},
10729 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10730 }, mem_tbl_5717[] = {
10731 { 0x00000200, 0x00008},
10732 { 0x00010000, 0x0a000},
10733 { 0x00020000, 0x13c00},
10734 { 0xffffffff, 0x00000}
10735 }, mem_tbl_57765[] = {
10736 { 0x00000200, 0x00008},
10737 { 0x00004000, 0x00800},
10738 { 0x00006000, 0x09800},
10739 { 0x00010000, 0x0a000},
10740 { 0xffffffff, 0x00000}
7942e1db
MC		 10741 };
10742 struct mem_entry *mem_tbl;
10743 int err = 0;
10744 int i;
10745
8b5a6c42
MC		 10746 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10747 mem_tbl = mem_tbl_5717;
10748 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10749 mem_tbl = mem_tbl_57765;
10750 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10751 mem_tbl = mem_tbl_5755;
10752 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10753 mem_tbl = mem_tbl_5906;
10754 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10755 mem_tbl = mem_tbl_5705;
10756 else
7942e1db
MC		 10757 mem_tbl = mem_tbl_570x;
10758
10759 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10760 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10761 mem_tbl[i].len)) != 0)
10762 break;
10763 }
6aa20a22 10764
7942e1db
MC		 10765 return err;
10766}
10767
9f40dead
MC		 10768#define TG3_MAC_LOOPBACK 0
10769#define TG3_PHY_LOOPBACK 1
10770
10771static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10772{
9f40dead 10773 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10774 u32 desc_idx, coal_now;
c76949a6
MC		 10775 struct sk_buff *skb, *rx_skb;
10776 u8 *tx_data;
10777 dma_addr_t map;
10778 int num_pkts, tx_len, rx_len, i, err;
10779 struct tg3_rx_buffer_desc *desc;
898a56f8 10780 struct tg3_napi *tnapi, *rnapi;
21f581a5 10781 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10782
c8873405
MC		 10783 tnapi = &tp->napi[0];
10784 rnapi = &tp->napi[0];
0c1d0e2b 10785 if (tp->irq_cnt > 1) {
0c1d0e2b 10786 rnapi = &tp->napi[1];
c8873405
MC		 10787 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10788 tnapi = &tp->napi[1];
0c1d0e2b 10789 }
fd2ce37f 10790 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10791
9f40dead 10792 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10793 /* HW errata - mac loopback fails in some cases on 5780.
10794 * Normal traffic and PHY loopback are not affected by
10795 * errata.
10796 */
10797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10798 return 0;
10799
9f40dead 10800 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10801 MAC_MODE_PORT_INT_LPBACK;
10802 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10803 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10804 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10805 mac_mode |= MAC_MODE_PORT_MODE_MII;
10806 else
10807 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10808 tw32(MAC_MODE, mac_mode);
10809 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10810 u32 val;
10811
7f97a4bd
MC		 10812 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10813 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10814 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10815 } else
10816 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10817
9ef8ca99
MC		 10818 tg3_phy_toggle_automdix(tp, 0);
10819
3f7045c1 10820 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10821 udelay(40);
5d64ad34 10822
e8f3f6ca 10823 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd 10824 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1061b7c5
MC		 10825 tg3_writephy(tp, MII_TG3_FET_PTEST,
10826 MII_TG3_FET_PTEST_FRC_TX_LINK |
10827 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10828 /* The write needs to be flushed for the AC131 */
10829 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10830 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
5d64ad34
MC		 10831 mac_mode |= MAC_MODE_PORT_MODE_MII;
10832 } else
10833 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10834
c94e3941
MC		 10835 /* reset to prevent losing 1st rx packet intermittently */
10836 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10837 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10838 udelay(10);
10839 tw32_f(MAC_RX_MODE, tp->rx_mode);
10840 }
e8f3f6ca
MC		 10841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10842 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10843 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10844 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10845 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10846 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10847 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10848 }
9f40dead 10849 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10850 }
10851 else
10852 return -EINVAL;
c76949a6
MC		 10853
10854 err = -EIO;
10855
c76949a6 10856 tx_len = 1514;
a20e9c62 10857 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10858 if (!skb)
10859 return -ENOMEM;
10860
c76949a6
MC		 10861 tx_data = skb_put(skb, tx_len);
10862 memcpy(tx_data, tp->dev->dev_addr, 6);
10863 memset(tx_data + 6, 0x0, 8);
10864
10865 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10866
10867 for (i = 14; i < tx_len; i++)
10868 tx_data[i] = (u8) (i & 0xff);
10869
f4188d8a
AD		 10870 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10871 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10872 dev_kfree_skb(skb);
10873 return -EIO;
10874 }
c76949a6
MC		 10875
10876 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10877 rnapi->coal_now);
c76949a6
MC		 10878
10879 udelay(10);
10880
898a56f8 10881 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10882
c76949a6
MC		 10883 num_pkts = 0;
10884
f4188d8a 10885 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10886
f3f3f27e 10887 tnapi->tx_prod++;
c76949a6
MC		 10888 num_pkts++;
10889
f3f3f27e
MC		 10890 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10891 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10892
10893 udelay(10);
10894
303fc921
MC		 10895 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10896 for (i = 0; i < 35; i++) {
c76949a6 10897 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10898 coal_now);
c76949a6
MC		 10899
10900 udelay(10);
10901
898a56f8
MC		 10902 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10903 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10904 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10905 (rx_idx == (rx_start_idx + num_pkts)))
10906 break;
10907 }
10908
f4188d8a 10909 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10910 dev_kfree_skb(skb);
10911
f3f3f27e 10912 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10913 goto out;
10914
10915 if (rx_idx != rx_start_idx + num_pkts)
10916 goto out;
10917
72334482 10918 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10919 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10920 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10921 if (opaque_key != RXD_OPAQUE_RING_STD)
10922 goto out;
10923
10924 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10925 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10926 goto out;
10927
10928 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10929 if (rx_len != tx_len)
10930 goto out;
10931
21f581a5 10932 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10933
21f581a5 10934 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10935 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10936
10937 for (i = 14; i < tx_len; i++) {
10938 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10939 goto out;
10940 }
10941 err = 0;
6aa20a22 10942
c76949a6
MC		 10943 /* tg3_free_rings will unmap and free the rx_skb */
10944out:
10945 return err;
10946}
10947
9f40dead
MC		 10948#define TG3_MAC_LOOPBACK_FAILED 1
10949#define TG3_PHY_LOOPBACK_FAILED 2
10950#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10951 TG3_PHY_LOOPBACK_FAILED)
10952
10953static int tg3_test_loopback(struct tg3 *tp)
10954{
10955 int err = 0;
9936bcf6 10956 u32 cpmuctrl = 0;
9f40dead
MC		 10957
10958 if (!netif_running(tp->dev))
10959 return TG3_LOOPBACK_FAILED;
10960
b9ec6c1b
MC		 10961 err = tg3_reset_hw(tp, 1);
10962 if (err)
10963 return TG3_LOOPBACK_FAILED;
9f40dead 10964
6833c043
MC		 10965 /* Turn off gphy autopowerdown. */
10966 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10967 tg3_phy_toggle_apd(tp, false);
10968
321d32a0 10969 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10970 int i;
10971 u32 status;
10972
10973 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10974
10975 /* Wait for up to 40 microseconds to acquire lock. */
10976 for (i = 0; i < 4; i++) {
10977 status = tr32(TG3_CPMU_MUTEX_GNT);
10978 if (status == CPMU_MUTEX_GNT_DRIVER)
10979 break;
10980 udelay(10);
10981 }
10982
10983 if (status != CPMU_MUTEX_GNT_DRIVER)
10984 return TG3_LOOPBACK_FAILED;
10985
b2a5c19c 10986 /* Turn off link-based power management. */
e875093c 10987 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10988 tw32(TG3_CPMU_CTRL,
10989 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10990 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10991 }
10992
9f40dead
MC		 10993 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10994 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10995
321d32a0 10996 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10997 tw32(TG3_CPMU_CTRL, cpmuctrl);
10998
10999 /* Release the mutex */
11000 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11001 }
11002
dd477003
MC		 11003 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
11004 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 11005 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11006 err |= TG3_PHY_LOOPBACK_FAILED;
11007 }
11008
6833c043
MC		 11009 /* Re-enable gphy autopowerdown. */
11010 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
11011 tg3_phy_toggle_apd(tp, true);
11012
9f40dead
MC		 11013 return err;
11014}
11015
4cafd3f5
MC		 11016static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11017 u64 *data)
11018{
566f86ad
MC		 11019 struct tg3 *tp = netdev_priv(dev);
11020
bc1c7567
MC		 11021 if (tp->link_config.phy_is_low_power)
11022 tg3_set_power_state(tp, PCI_D0);
11023
566f86ad
MC		 11024 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11025
11026 if (tg3_test_nvram(tp) != 0) {
11027 etest->flags |= ETH_TEST_FL_FAILED;
11028 data[0] = 1;
11029 }
ca43007a
MC		 11030 if (tg3_test_link(tp) != 0) {
11031 etest->flags |= ETH_TEST_FL_FAILED;
11032 data[1] = 1;
11033 }
a71116d1 11034 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 11035 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 11036
11037 if (netif_running(dev)) {
b02fd9e3 11038 tg3_phy_stop(tp);
a71116d1 11039 tg3_netif_stop(tp);
bbe832c0
MC		 11040 irq_sync = 1;
11041 }
a71116d1 11042
bbe832c0 11043 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 11044
11045 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 11046 err = tg3_nvram_lock(tp);
a71116d1
MC		 11047 tg3_halt_cpu(tp, RX_CPU_BASE);
11048 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11049 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 11050 if (!err)
11051 tg3_nvram_unlock(tp);
a71116d1 11052
d9ab5ad1
MC		 11053 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11054 tg3_phy_reset(tp);
11055
a71116d1
MC		 11056 if (tg3_test_registers(tp) != 0) {
11057 etest->flags |= ETH_TEST_FL_FAILED;
11058 data[2] = 1;
11059 }
7942e1db
MC		 11060 if (tg3_test_memory(tp) != 0) {
11061 etest->flags |= ETH_TEST_FL_FAILED;
11062 data[3] = 1;
11063 }
9f40dead 11064 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 11065 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 11066
f47c11ee
DM		 11067 tg3_full_unlock(tp);
11068
d4bc3927
MC		 11069 if (tg3_test_interrupt(tp) != 0) {
11070 etest->flags |= ETH_TEST_FL_FAILED;
11071 data[5] = 1;
11072 }
f47c11ee
DM		 11073
11074 tg3_full_lock(tp, 0);
d4bc3927 11075
a71116d1
MC		 11076 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11077 if (netif_running(dev)) {
11078 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 11079 err2 = tg3_restart_hw(tp, 1);
11080 if (!err2)
b9ec6c1b 11081 tg3_netif_start(tp);
a71116d1 11082 }
f47c11ee
DM		 11083
11084 tg3_full_unlock(tp);
b02fd9e3
MC		 11085
11086 if (irq_sync && !err2)
11087 tg3_phy_start(tp);
a71116d1 11088 }
bc1c7567
MC		 11089 if (tp->link_config.phy_is_low_power)
11090 tg3_set_power_state(tp, PCI_D3hot);
11091
4cafd3f5
MC		 11092}
11093
1da177e4
LT		 11094static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11095{
11096 struct mii_ioctl_data *data = if_mii(ifr);
11097 struct tg3 *tp = netdev_priv(dev);
11098 int err;
11099
b02fd9e3 11100 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11101 struct phy_device *phydev;
b02fd9e3
MC		 11102 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11103 return -EAGAIN;
3f0e3ad7
MC		 11104 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11105 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11106 }
11107
1da177e4
LT		 11108 switch(cmd) {
11109 case SIOCGMIIPHY:
882e9793 11110 data->phy_id = tp->phy_addr;
1da177e4
LT		 11111
11112 /* fallthru */
11113 case SIOCGMIIREG: {
11114 u32 mii_regval;
11115
11116 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11117 break; /* We have no PHY */
11118
bc1c7567
MC		 11119 if (tp->link_config.phy_is_low_power)
11120 return -EAGAIN;
11121
f47c11ee 11122 spin_lock_bh(&tp->lock);
1da177e4 11123 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11124 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11125
11126 data->val_out = mii_regval;
11127
11128 return err;
11129 }
11130
11131 case SIOCSMIIREG:
11132 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11133 break; /* We have no PHY */
11134
bc1c7567
MC		 11135 if (tp->link_config.phy_is_low_power)
11136 return -EAGAIN;
11137
f47c11ee 11138 spin_lock_bh(&tp->lock);
1da177e4 11139 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11140 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11141
11142 return err;
11143
11144 default:
11145 /* do nothing */
11146 break;
11147 }
11148 return -EOPNOTSUPP;
11149}
11150
11151#if TG3_VLAN_TAG_USED
11152static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11153{
11154 struct tg3 *tp = netdev_priv(dev);
11155
844b3eed
MC		 11156 if (!netif_running(dev)) {
11157 tp->vlgrp = grp;
11158 return;
11159 }
11160
11161 tg3_netif_stop(tp);
29315e87 11162
f47c11ee 11163 tg3_full_lock(tp, 0);
1da177e4
LT		 11164
11165 tp->vlgrp = grp;
11166
11167 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11168 __tg3_set_rx_mode(dev);
11169
844b3eed 11170 tg3_netif_start(tp);
46966545
MC		 11171
11172 tg3_full_unlock(tp);
1da177e4 11173}
1da177e4
LT		 11174#endif
11175
15f9850d
DM		 11176static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11177{
11178 struct tg3 *tp = netdev_priv(dev);
11179
11180 memcpy(ec, &tp->coal, sizeof(*ec));
11181 return 0;
11182}
11183
d244c892
MC		 11184static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11185{
11186 struct tg3 *tp = netdev_priv(dev);
11187 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11188 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11189
11190 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11191 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11192 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11193 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11194 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11195 }
11196
11197 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11198 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11199 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11200 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11201 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11202 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11203 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11204 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11205 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11206 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11207 return -EINVAL;
11208
11209 /* No rx interrupts will be generated if both are zero */
11210 if ((ec->rx_coalesce_usecs == 0) &&
11211 (ec->rx_max_coalesced_frames == 0))
11212 return -EINVAL;
11213
11214 /* No tx interrupts will be generated if both are zero */
11215 if ((ec->tx_coalesce_usecs == 0) &&
11216 (ec->tx_max_coalesced_frames == 0))
11217 return -EINVAL;
11218
11219 /* Only copy relevant parameters, ignore all others. */
11220 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11221 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11222 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11223 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11224 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11225 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11226 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11227 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11228 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11229
11230 if (netif_running(dev)) {
11231 tg3_full_lock(tp, 0);
11232 __tg3_set_coalesce(tp, &tp->coal);
11233 tg3_full_unlock(tp);
11234 }
11235 return 0;
11236}
11237
7282d491 11238static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11239 .get_settings = tg3_get_settings,
11240 .set_settings = tg3_set_settings,
11241 .get_drvinfo = tg3_get_drvinfo,
11242 .get_regs_len = tg3_get_regs_len,
11243 .get_regs = tg3_get_regs,
11244 .get_wol = tg3_get_wol,
11245 .set_wol = tg3_set_wol,
11246 .get_msglevel = tg3_get_msglevel,
11247 .set_msglevel = tg3_set_msglevel,
11248 .nway_reset = tg3_nway_reset,
11249 .get_link = ethtool_op_get_link,
11250 .get_eeprom_len = tg3_get_eeprom_len,
11251 .get_eeprom = tg3_get_eeprom,
11252 .set_eeprom = tg3_set_eeprom,
11253 .get_ringparam = tg3_get_ringparam,
11254 .set_ringparam = tg3_set_ringparam,
11255 .get_pauseparam = tg3_get_pauseparam,
11256 .set_pauseparam = tg3_set_pauseparam,
11257 .get_rx_csum = tg3_get_rx_csum,
11258 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11259 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11260 .set_sg = ethtool_op_set_sg,
1da177e4 11261 .set_tso = tg3_set_tso,
4cafd3f5 11262 .self_test = tg3_self_test,
1da177e4 11263 .get_strings = tg3_get_strings,
4009a93d 11264 .phys_id = tg3_phys_id,
1da177e4 11265 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11266 .get_coalesce = tg3_get_coalesce,
d244c892 11267 .set_coalesce = tg3_set_coalesce,
b9f2c044 11268 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11269};
11270
11271static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11272{
1b27777a 11273 u32 cursize, val, magic;
1da177e4
LT		 11274
11275 tp->nvram_size = EEPROM_CHIP_SIZE;
11276
e4f34110 11277 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11278 return;
11279
b16250e3
MC		 11280 if ((magic != TG3_EEPROM_MAGIC) &&
11281 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11282 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11283 return;
11284
11285 /*
11286 * Size the chip by reading offsets at increasing powers of two.
11287 * When we encounter our validation signature, we know the addressing
11288 * has wrapped around, and thus have our chip size.
11289 */
1b27777a 11290 cursize = 0x10;
1da177e4
LT		 11291
11292 while (cursize < tp->nvram_size) {
e4f34110 11293 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11294 return;
11295
1820180b 11296 if (val == magic)
1da177e4
LT		 11297 break;
11298
11299 cursize <<= 1;
11300 }
11301
11302 tp->nvram_size = cursize;
11303}
6aa20a22 11304
1da177e4
LT		 11305static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11306{
11307 u32 val;
11308
df259d8c
MC		 11309 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11310 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11311 return;
11312
11313 /* Selfboot format */
1820180b 11314 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11315 tg3_get_eeprom_size(tp);
11316 return;
11317 }
11318
6d348f2c 11319 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11320 if (val != 0) {
6d348f2c
MC		 11321 /* This is confusing. We want to operate on the
11322 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11323 * call will read from NVRAM and byteswap the data
11324 * according to the byteswapping settings for all
11325 * other register accesses. This ensures the data we
11326 * want will always reside in the lower 16-bits.
11327 * However, the data in NVRAM is in LE format, which
11328 * means the data from the NVRAM read will always be
11329 * opposite the endianness of the CPU. The 16-bit
11330 * byteswap then brings the data to CPU endianness.
11331 */
11332 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11333 return;
11334 }
11335 }
fd1122a2 11336 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11337}
11338
11339static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11340{
11341 u32 nvcfg1;
11342
11343 nvcfg1 = tr32(NVRAM_CFG1);
11344 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11345 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11346 } else {
1da177e4
LT		 11347 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11348 tw32(NVRAM_CFG1, nvcfg1);
11349 }
11350
4c987487 11351 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11352 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11353 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11354 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11355 tp->nvram_jedecnum = JEDEC_ATMEL;
11356 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11357 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11358 break;
11359 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11360 tp->nvram_jedecnum = JEDEC_ATMEL;
11361 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11362 break;
11363 case FLASH_VENDOR_ATMEL_EEPROM:
11364 tp->nvram_jedecnum = JEDEC_ATMEL;
11365 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367 break;
11368 case FLASH_VENDOR_ST:
11369 tp->nvram_jedecnum = JEDEC_ST;
11370 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11371 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11372 break;
11373 case FLASH_VENDOR_SAIFUN:
11374 tp->nvram_jedecnum = JEDEC_SAIFUN;
11375 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11376 break;
11377 case FLASH_VENDOR_SST_SMALL:
11378 case FLASH_VENDOR_SST_LARGE:
11379 tp->nvram_jedecnum = JEDEC_SST;
11380 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11381 break;
1da177e4 11382 }
8590a603 11383 } else {
1da177e4
LT		 11384 tp->nvram_jedecnum = JEDEC_ATMEL;
11385 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11386 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11387 }
11388}
11389
a1b950d5
MC		 11390static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11391{
11392 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11393 case FLASH_5752PAGE_SIZE_256:
11394 tp->nvram_pagesize = 256;
11395 break;
11396 case FLASH_5752PAGE_SIZE_512:
11397 tp->nvram_pagesize = 512;
11398 break;
11399 case FLASH_5752PAGE_SIZE_1K:
11400 tp->nvram_pagesize = 1024;
11401 break;
11402 case FLASH_5752PAGE_SIZE_2K:
11403 tp->nvram_pagesize = 2048;
11404 break;
11405 case FLASH_5752PAGE_SIZE_4K:
11406 tp->nvram_pagesize = 4096;
11407 break;
11408 case FLASH_5752PAGE_SIZE_264:
11409 tp->nvram_pagesize = 264;
11410 break;
11411 case FLASH_5752PAGE_SIZE_528:
11412 tp->nvram_pagesize = 528;
11413 break;
11414 }
11415}
11416
361b4ac2
MC		 11417static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11418{
11419 u32 nvcfg1;
11420
11421 nvcfg1 = tr32(NVRAM_CFG1);
11422
e6af301b
MC		 11423 /* NVRAM protection for TPM */
11424 if (nvcfg1 & (1 << 27))
f66a29b0 11425 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11426
361b4ac2 11427 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11428 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11429 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11430 tp->nvram_jedecnum = JEDEC_ATMEL;
11431 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11432 break;
11433 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11434 tp->nvram_jedecnum = JEDEC_ATMEL;
11435 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11436 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11437 break;
11438 case FLASH_5752VENDOR_ST_M45PE10:
11439 case FLASH_5752VENDOR_ST_M45PE20:
11440 case FLASH_5752VENDOR_ST_M45PE40:
11441 tp->nvram_jedecnum = JEDEC_ST;
11442 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11443 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11444 break;
361b4ac2
MC		 11445 }
11446
11447 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11448 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11449 } else {
361b4ac2
MC		 11450 /* For eeprom, set pagesize to maximum eeprom size */
11451 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11452
11453 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11454 tw32(NVRAM_CFG1, nvcfg1);
11455 }
11456}
11457
d3c7b886
MC		 11458static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11459{
989a9d23 11460 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11461
11462 nvcfg1 = tr32(NVRAM_CFG1);
11463
11464 /* NVRAM protection for TPM */
989a9d23 11465 if (nvcfg1 & (1 << 27)) {
f66a29b0 11466 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11467 protect = 1;
11468 }
d3c7b886 11469
989a9d23
MC		 11470 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11471 switch (nvcfg1) {
8590a603
MC		 11472 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11473 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11474 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11475 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11476 tp->nvram_jedecnum = JEDEC_ATMEL;
11477 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11478 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11479 tp->nvram_pagesize = 264;
11480 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11481 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11482 tp->nvram_size = (protect ? 0x3e200 :
11483 TG3_NVRAM_SIZE_512KB);
11484 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11485 tp->nvram_size = (protect ? 0x1f200 :
11486 TG3_NVRAM_SIZE_256KB);
11487 else
11488 tp->nvram_size = (protect ? 0x1f200 :
11489 TG3_NVRAM_SIZE_128KB);
11490 break;
11491 case FLASH_5752VENDOR_ST_M45PE10:
11492 case FLASH_5752VENDOR_ST_M45PE20:
11493 case FLASH_5752VENDOR_ST_M45PE40:
11494 tp->nvram_jedecnum = JEDEC_ST;
11495 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11496 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11497 tp->nvram_pagesize = 256;
11498 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11499 tp->nvram_size = (protect ?
11500 TG3_NVRAM_SIZE_64KB :
11501 TG3_NVRAM_SIZE_128KB);
11502 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11503 tp->nvram_size = (protect ?
11504 TG3_NVRAM_SIZE_64KB :
11505 TG3_NVRAM_SIZE_256KB);
11506 else
11507 tp->nvram_size = (protect ?
11508 TG3_NVRAM_SIZE_128KB :
11509 TG3_NVRAM_SIZE_512KB);
11510 break;
d3c7b886
MC		 11511 }
11512}
11513
1b27777a
MC		 11514static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11515{
11516 u32 nvcfg1;
11517
11518 nvcfg1 = tr32(NVRAM_CFG1);
11519
11520 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11521 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11522 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11523 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11524 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11525 tp->nvram_jedecnum = JEDEC_ATMEL;
11526 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11527 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11528
8590a603
MC		 11529 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11530 tw32(NVRAM_CFG1, nvcfg1);
11531 break;
11532 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11533 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11534 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11535 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11536 tp->nvram_jedecnum = JEDEC_ATMEL;
11537 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11538 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11539 tp->nvram_pagesize = 264;
11540 break;
11541 case FLASH_5752VENDOR_ST_M45PE10:
11542 case FLASH_5752VENDOR_ST_M45PE20:
11543 case FLASH_5752VENDOR_ST_M45PE40:
11544 tp->nvram_jedecnum = JEDEC_ST;
11545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11547 tp->nvram_pagesize = 256;
11548 break;
1b27777a
MC		 11549 }
11550}
11551
6b91fa02
MC		 11552static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11553{
11554 u32 nvcfg1, protect = 0;
11555
11556 nvcfg1 = tr32(NVRAM_CFG1);
11557
11558 /* NVRAM protection for TPM */
11559 if (nvcfg1 & (1 << 27)) {
f66a29b0 11560 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11561 protect = 1;
11562 }
11563
11564 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11565 switch (nvcfg1) {
8590a603
MC		 11566 case FLASH_5761VENDOR_ATMEL_ADB021D:
11567 case FLASH_5761VENDOR_ATMEL_ADB041D:
11568 case FLASH_5761VENDOR_ATMEL_ADB081D:
11569 case FLASH_5761VENDOR_ATMEL_ADB161D:
11570 case FLASH_5761VENDOR_ATMEL_MDB021D:
11571 case FLASH_5761VENDOR_ATMEL_MDB041D:
11572 case FLASH_5761VENDOR_ATMEL_MDB081D:
11573 case FLASH_5761VENDOR_ATMEL_MDB161D:
11574 tp->nvram_jedecnum = JEDEC_ATMEL;
11575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11576 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11577 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11578 tp->nvram_pagesize = 256;
11579 break;
11580 case FLASH_5761VENDOR_ST_A_M45PE20:
11581 case FLASH_5761VENDOR_ST_A_M45PE40:
11582 case FLASH_5761VENDOR_ST_A_M45PE80:
11583 case FLASH_5761VENDOR_ST_A_M45PE16:
11584 case FLASH_5761VENDOR_ST_M_M45PE20:
11585 case FLASH_5761VENDOR_ST_M_M45PE40:
11586 case FLASH_5761VENDOR_ST_M_M45PE80:
11587 case FLASH_5761VENDOR_ST_M_M45PE16:
11588 tp->nvram_jedecnum = JEDEC_ST;
11589 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11590 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11591 tp->nvram_pagesize = 256;
11592 break;
6b91fa02
MC		 11593 }
11594
11595 if (protect) {
11596 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11597 } else {
11598 switch (nvcfg1) {
8590a603
MC		 11599 case FLASH_5761VENDOR_ATMEL_ADB161D:
11600 case FLASH_5761VENDOR_ATMEL_MDB161D:
11601 case FLASH_5761VENDOR_ST_A_M45PE16:
11602 case FLASH_5761VENDOR_ST_M_M45PE16:
11603 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11604 break;
11605 case FLASH_5761VENDOR_ATMEL_ADB081D:
11606 case FLASH_5761VENDOR_ATMEL_MDB081D:
11607 case FLASH_5761VENDOR_ST_A_M45PE80:
11608 case FLASH_5761VENDOR_ST_M_M45PE80:
11609 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11610 break;
11611 case FLASH_5761VENDOR_ATMEL_ADB041D:
11612 case FLASH_5761VENDOR_ATMEL_MDB041D:
11613 case FLASH_5761VENDOR_ST_A_M45PE40:
11614 case FLASH_5761VENDOR_ST_M_M45PE40:
11615 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11616 break;
11617 case FLASH_5761VENDOR_ATMEL_ADB021D:
11618 case FLASH_5761VENDOR_ATMEL_MDB021D:
11619 case FLASH_5761VENDOR_ST_A_M45PE20:
11620 case FLASH_5761VENDOR_ST_M_M45PE20:
11621 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11622 break;
6b91fa02
MC		 11623 }
11624 }
11625}
11626
b5d3772c
MC		 11627static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11628{
11629 tp->nvram_jedecnum = JEDEC_ATMEL;
11630 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11631 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11632}
11633
321d32a0
MC		 11634static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11635{
11636 u32 nvcfg1;
11637
11638 nvcfg1 = tr32(NVRAM_CFG1);
11639
11640 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11641 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11642 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11643 tp->nvram_jedecnum = JEDEC_ATMEL;
11644 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11645 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11646
11647 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11648 tw32(NVRAM_CFG1, nvcfg1);
11649 return;
11650 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11651 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11652 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11653 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11654 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11655 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11656 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11657 tp->nvram_jedecnum = JEDEC_ATMEL;
11658 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11659 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11660
11661 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11662 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11663 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11664 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11665 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11666 break;
11667 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11668 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11669 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11670 break;
11671 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11672 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11673 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11674 break;
11675 }
11676 break;
11677 case FLASH_5752VENDOR_ST_M45PE10:
11678 case FLASH_5752VENDOR_ST_M45PE20:
11679 case FLASH_5752VENDOR_ST_M45PE40:
11680 tp->nvram_jedecnum = JEDEC_ST;
11681 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11682 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11683
11684 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11685 case FLASH_5752VENDOR_ST_M45PE10:
11686 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11687 break;
11688 case FLASH_5752VENDOR_ST_M45PE20:
11689 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11690 break;
11691 case FLASH_5752VENDOR_ST_M45PE40:
11692 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11693 break;
11694 }
11695 break;
11696 default:
df259d8c 11697 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11698 return;
11699 }
11700
a1b950d5
MC		 11701 tg3_nvram_get_pagesize(tp, nvcfg1);
11702 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11703 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11704}
11705
11706
11707static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11708{
11709 u32 nvcfg1;
11710
11711 nvcfg1 = tr32(NVRAM_CFG1);
11712
11713 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11714 case FLASH_5717VENDOR_ATMEL_EEPROM:
11715 case FLASH_5717VENDOR_MICRO_EEPROM:
11716 tp->nvram_jedecnum = JEDEC_ATMEL;
11717 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11718 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11719
11720 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11721 tw32(NVRAM_CFG1, nvcfg1);
11722 return;
11723 case FLASH_5717VENDOR_ATMEL_MDB011D:
11724 case FLASH_5717VENDOR_ATMEL_ADB011B:
11725 case FLASH_5717VENDOR_ATMEL_ADB011D:
11726 case FLASH_5717VENDOR_ATMEL_MDB021D:
11727 case FLASH_5717VENDOR_ATMEL_ADB021B:
11728 case FLASH_5717VENDOR_ATMEL_ADB021D:
11729 case FLASH_5717VENDOR_ATMEL_45USPT:
11730 tp->nvram_jedecnum = JEDEC_ATMEL;
11731 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11732 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11733
11734 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11735 case FLASH_5717VENDOR_ATMEL_MDB021D:
11736 case FLASH_5717VENDOR_ATMEL_ADB021B:
11737 case FLASH_5717VENDOR_ATMEL_ADB021D:
11738 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11739 break;
11740 default:
11741 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11742 break;
11743 }
321d32a0 11744 break;
a1b950d5
MC		 11745 case FLASH_5717VENDOR_ST_M_M25PE10:
11746 case FLASH_5717VENDOR_ST_A_M25PE10:
11747 case FLASH_5717VENDOR_ST_M_M45PE10:
11748 case FLASH_5717VENDOR_ST_A_M45PE10:
11749 case FLASH_5717VENDOR_ST_M_M25PE20:
11750 case FLASH_5717VENDOR_ST_A_M25PE20:
11751 case FLASH_5717VENDOR_ST_M_M45PE20:
11752 case FLASH_5717VENDOR_ST_A_M45PE20:
11753 case FLASH_5717VENDOR_ST_25USPT:
11754 case FLASH_5717VENDOR_ST_45USPT:
11755 tp->nvram_jedecnum = JEDEC_ST;
11756 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11757 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11758
11759 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11760 case FLASH_5717VENDOR_ST_M_M25PE20:
11761 case FLASH_5717VENDOR_ST_A_M25PE20:
11762 case FLASH_5717VENDOR_ST_M_M45PE20:
11763 case FLASH_5717VENDOR_ST_A_M45PE20:
11764 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11765 break;
11766 default:
11767 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11768 break;
11769 }
321d32a0 11770 break;
a1b950d5
MC		 11771 default:
11772 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11773 return;
321d32a0 11774 }
a1b950d5
MC		 11775
11776 tg3_nvram_get_pagesize(tp, nvcfg1);
11777 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11778 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11779}
11780
1da177e4
LT		 11781/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11782static void __devinit tg3_nvram_init(struct tg3 *tp)
11783{
1da177e4
LT		 11784 tw32_f(GRC_EEPROM_ADDR,
11785 (EEPROM_ADDR_FSM_RESET |
11786 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11787 EEPROM_ADDR_CLKPERD_SHIFT)));
11788
9d57f01c 11789 msleep(1);
1da177e4
LT		 11790
11791 /* Enable seeprom accesses. */
11792 tw32_f(GRC_LOCAL_CTRL,
11793 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11794 udelay(100);
11795
11796 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11797 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11798 tp->tg3_flags |= TG3_FLAG_NVRAM;
11799
ec41c7df
MC		 11800 if (tg3_nvram_lock(tp)) {
11801 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11802 "tg3_nvram_init failed.\n", tp->dev->name);
11803 return;
11804 }
e6af301b 11805 tg3_enable_nvram_access(tp);
1da177e4 11806
989a9d23
MC		 11807 tp->nvram_size = 0;
11808
361b4ac2
MC		 11809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11810 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11811 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11812 tg3_get_5755_nvram_info(tp);
d30cdd28 11813 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11815 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11816 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11817 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11818 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11819 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11820 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11821 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11822 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11823 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11824 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11825 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11826 else
11827 tg3_get_nvram_info(tp);
11828
989a9d23
MC		 11829 if (tp->nvram_size == 0)
11830 tg3_get_nvram_size(tp);
1da177e4 11831
e6af301b 11832 tg3_disable_nvram_access(tp);
381291b7 11833 tg3_nvram_unlock(tp);
1da177e4
LT		 11834
11835 } else {
11836 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11837
11838 tg3_get_eeprom_size(tp);
11839 }
11840}
11841
1da177e4
LT		 11842static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11843 u32 offset, u32 len, u8 *buf)
11844{
11845 int i, j, rc = 0;
11846 u32 val;
11847
11848 for (i = 0; i < len; i += 4) {
b9fc7dc5 11849 u32 addr;
a9dc529d 11850 __be32 data;
1da177e4
LT		 11851
11852 addr = offset + i;
11853
11854 memcpy(&data, buf + i, 4);
11855
62cedd11
MC		 11856 /*
11857 * The SEEPROM interface expects the data to always be opposite
11858 * the native endian format. We accomplish this by reversing
11859 * all the operations that would have been performed on the
11860 * data from a call to tg3_nvram_read_be32().
11861 */
11862 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11863
11864 val = tr32(GRC_EEPROM_ADDR);
11865 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11866
11867 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11868 EEPROM_ADDR_READ);
11869 tw32(GRC_EEPROM_ADDR, val |
11870 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11871 (addr & EEPROM_ADDR_ADDR_MASK) |
11872 EEPROM_ADDR_START |
11873 EEPROM_ADDR_WRITE);
6aa20a22 11874
9d57f01c 11875 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11876 val = tr32(GRC_EEPROM_ADDR);
11877
11878 if (val & EEPROM_ADDR_COMPLETE)
11879 break;
9d57f01c 11880 msleep(1);
1da177e4
LT		 11881 }
11882 if (!(val & EEPROM_ADDR_COMPLETE)) {
11883 rc = -EBUSY;
11884 break;
11885 }
11886 }
11887
11888 return rc;
11889}
11890
11891/* offset and length are dword aligned */
11892static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11893 u8 *buf)
11894{
11895 int ret = 0;
11896 u32 pagesize = tp->nvram_pagesize;
11897 u32 pagemask = pagesize - 1;
11898 u32 nvram_cmd;
11899 u8 *tmp;
11900
11901 tmp = kmalloc(pagesize, GFP_KERNEL);
11902 if (tmp == NULL)
11903 return -ENOMEM;
11904
11905 while (len) {
11906 int j;
e6af301b 11907 u32 phy_addr, page_off, size;
1da177e4
LT		 11908
11909 phy_addr = offset & ~pagemask;
6aa20a22 11910
1da177e4 11911 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11912 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11913 (__be32 *) (tmp + j));
11914 if (ret)
1da177e4
LT		 11915 break;
11916 }
11917 if (ret)
11918 break;
11919
11920 page_off = offset & pagemask;
11921 size = pagesize;
11922 if (len < size)
11923 size = len;
11924
11925 len -= size;
11926
11927 memcpy(tmp + page_off, buf, size);
11928
11929 offset = offset + (pagesize - page_off);
11930
e6af301b 11931 tg3_enable_nvram_access(tp);
1da177e4
LT		 11932
11933 /*
11934 * Before we can erase the flash page, we need
11935 * to issue a special "write enable" command.
11936 */
11937 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11938
11939 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11940 break;
11941
11942 /* Erase the target page */
11943 tw32(NVRAM_ADDR, phy_addr);
11944
11945 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11946 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11947
11948 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11949 break;
11950
11951 /* Issue another write enable to start the write. */
11952 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11953
11954 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11955 break;
11956
11957 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11958 __be32 data;
1da177e4 11959
b9fc7dc5 11960 data = *((__be32 *) (tmp + j));
a9dc529d 11961
b9fc7dc5 11962 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11963
11964 tw32(NVRAM_ADDR, phy_addr + j);
11965
11966 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11967 NVRAM_CMD_WR;
11968
11969 if (j == 0)
11970 nvram_cmd |= NVRAM_CMD_FIRST;
11971 else if (j == (pagesize - 4))
11972 nvram_cmd |= NVRAM_CMD_LAST;
11973
11974 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11975 break;
11976 }
11977 if (ret)
11978 break;
11979 }
11980
11981 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11982 tg3_nvram_exec_cmd(tp, nvram_cmd);
11983
11984 kfree(tmp);
11985
11986 return ret;
11987}
11988
11989/* offset and length are dword aligned */
11990static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11991 u8 *buf)
11992{
11993 int i, ret = 0;
11994
11995 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11996 u32 page_off, phy_addr, nvram_cmd;
11997 __be32 data;
1da177e4
LT		 11998
11999 memcpy(&data, buf + i, 4);
b9fc7dc5 12000 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 12001
12002 page_off = offset % tp->nvram_pagesize;
12003
1820180b 12004 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 12005
12006 tw32(NVRAM_ADDR, phy_addr);
12007
12008 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12009
12010 if ((page_off == 0) || (i == 0))
12011 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 12012 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 12013 nvram_cmd |= NVRAM_CMD_LAST;
12014
12015 if (i == (len - 4))
12016 nvram_cmd |= NVRAM_CMD_LAST;
12017
321d32a0
MC		 12018 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12019 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 12020 (tp->nvram_jedecnum == JEDEC_ST) &&
12021 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 12022
12023 if ((ret = tg3_nvram_exec_cmd(tp,
12024 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12025 NVRAM_CMD_DONE)))
12026
12027 break;
12028 }
12029 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12030 /* We always do complete word writes to eeprom. */
12031 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12032 }
12033
12034 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12035 break;
12036 }
12037 return ret;
12038}
12039
12040/* offset and length are dword aligned */
12041static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12042{
12043 int ret;
12044
1da177e4 12045 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 12046 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12047 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 12048 udelay(40);
12049 }
12050
12051 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12052 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12053 }
12054 else {
12055 u32 grc_mode;
12056
ec41c7df
MC		 12057 ret = tg3_nvram_lock(tp);
12058 if (ret)
12059 return ret;
1da177e4 12060
e6af301b
MC		 12061 tg3_enable_nvram_access(tp);
12062 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 12063 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 12064 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 12065
12066 grc_mode = tr32(GRC_MODE);
12067 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12068
12069 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12070 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12071
12072 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12073 buf);
12074 }
12075 else {
12076 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12077 buf);
12078 }
12079
12080 grc_mode = tr32(GRC_MODE);
12081 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12082
e6af301b 12083 tg3_disable_nvram_access(tp);
1da177e4
LT		 12084 tg3_nvram_unlock(tp);
12085 }
12086
12087 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 12088 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 12089 udelay(40);
12090 }
12091
12092 return ret;
12093}
12094
12095struct subsys_tbl_ent {
12096 u16 subsys_vendor, subsys_devid;
12097 u32 phy_id;
12098};
12099
12100static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12101 /* Broadcom boards. */
12102 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12103 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12104 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12105 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12106 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12107 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12108 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12109 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12110 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12111 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12112 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12113
12114 /* 3com boards. */
12115 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12116 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12117 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12118 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12119 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12120
12121 /* DELL boards. */
12122 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12123 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12124 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12125 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12126
12127 /* Compaq boards. */
12128 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12129 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12130 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12131 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12132 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12133
12134 /* IBM boards. */
12135 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12136};
12137
12138static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12139{
12140 int i;
12141
12142 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12143 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12144 tp->pdev->subsystem_vendor) &&
12145 (subsys_id_to_phy_id[i].subsys_devid ==
12146 tp->pdev->subsystem_device))
12147 return &subsys_id_to_phy_id[i];
12148 }
12149 return NULL;
12150}
12151
7d0c41ef 12152static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12153{
1da177e4 12154 u32 val;
caf636c7
MC		 12155 u16 pmcsr;
12156
12157 /* On some early chips the SRAM cannot be accessed in D3hot state,
12158 * so need make sure we're in D0.
12159 */
12160 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12161 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12162 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12163 msleep(1);
7d0c41ef
MC		 12164
12165 /* Make sure register accesses (indirect or otherwise)
12166 * will function correctly.
12167 */
12168 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12169 tp->misc_host_ctrl);
1da177e4 12170
f49639e6
DM		 12171 /* The memory arbiter has to be enabled in order for SRAM accesses
12172 * to succeed. Normally on powerup the tg3 chip firmware will make
12173 * sure it is enabled, but other entities such as system netboot
12174 * code might disable it.
12175 */
12176 val = tr32(MEMARB_MODE);
12177 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12178
1da177e4 12179 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12180 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12181
a85feb8c
GZ		 12182 /* Assume an onboard device and WOL capable by default. */
12183 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12184
b5d3772c 12185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12186 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12187 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12188 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12189 }
0527ba35
MC		 12190 val = tr32(VCPU_CFGSHDW);
12191 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12192 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12193 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12194 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12195 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12196 goto done;
b5d3772c
MC		 12197 }
12198
1da177e4
LT		 12199 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12200 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12201 u32 nic_cfg, led_cfg;
a9daf367 12202 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12203 int eeprom_phy_serdes = 0;
1da177e4
LT		 12204
12205 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12206 tp->nic_sram_data_cfg = nic_cfg;
12207
12208 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12209 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12210 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12211 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12212 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12213 (ver > 0) && (ver < 0x100))
12214 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12215
a9daf367
MC		 12216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12217 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12218
1da177e4
LT		 12219 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12220 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12221 eeprom_phy_serdes = 1;
12222
12223 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12224 if (nic_phy_id != 0) {
12225 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12226 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12227
12228 eeprom_phy_id = (id1 >> 16) << 10;
12229 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12230 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12231 } else
12232 eeprom_phy_id = 0;
12233
7d0c41ef 12234 tp->phy_id = eeprom_phy_id;
747e8f8b 12235 if (eeprom_phy_serdes) {
d1ec96af
MC		 12236 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12238 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12239 else
12240 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12241 }
7d0c41ef 12242
cbf46853 12243 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12244 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12245 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12246 else
1da177e4
LT		 12247 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12248
12249 switch (led_cfg) {
12250 default:
12251 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12252 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12253 break;
12254
12255 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12256 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12257 break;
12258
12259 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12260 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12261
12262 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12263 * read on some older 5700/5701 bootcode.
12264 */
12265 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12266 ASIC_REV_5700 ||
12267 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12268 ASIC_REV_5701)
12269 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12270
1da177e4
LT		 12271 break;
12272
12273 case SHASTA_EXT_LED_SHARED:
12274 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12275 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12276 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12277 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12278 LED_CTRL_MODE_PHY_2);
12279 break;
12280
12281 case SHASTA_EXT_LED_MAC:
12282 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12283 break;
12284
12285 case SHASTA_EXT_LED_COMBO:
12286 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12287 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12288 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12289 LED_CTRL_MODE_PHY_2);
12290 break;
12291
855e1111 12292 }
1da177e4
LT		 12293
12294 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12295 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12296 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12297 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12298
b2a5c19c
MC		 12299 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12300 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12301
9d26e213 12302 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12303 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12304 if ((tp->pdev->subsystem_vendor ==
12305 PCI_VENDOR_ID_ARIMA) &&
12306 (tp->pdev->subsystem_device == 0x205a ||
12307 tp->pdev->subsystem_device == 0x2063))
12308 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12309 } else {
f49639e6 12310 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12311 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12312 }
1da177e4
LT		 12313
12314 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12315 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12316 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12317 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12318 }
b2b98d4a
MC		 12319
12320 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12321 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12322 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12323
a85feb8c
GZ		 12324 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12325 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12326 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12327
12dac075 12328 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12329 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12330 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12331
1da177e4
LT		 12332 if (cfg2 & (1 << 17))
12333 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12334
12335 /* serdes signal pre-emphasis in register 0x590 set by */
12336 /* bootcode if bit 18 is set */
12337 if (cfg2 & (1 << 18))
12338 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12339
321d32a0
MC		 12340 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12341 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12342 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12343 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12344
8ed5d97e
MC		 12345 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12346 u32 cfg3;
12347
12348 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12349 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12350 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12351 }
a9daf367
MC		 12352
12353 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12354 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12355 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12356 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12357 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12358 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12359 }
05ac4cb7
MC		 12360done:
12361 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12362 device_set_wakeup_enable(&tp->pdev->dev,
12363 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12364}
12365
b2a5c19c
MC		 12366static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12367{
12368 int i;
12369 u32 val;
12370
12371 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12372 tw32(OTP_CTRL, cmd);
12373
12374 /* Wait for up to 1 ms for command to execute. */
12375 for (i = 0; i < 100; i++) {
12376 val = tr32(OTP_STATUS);
12377 if (val & OTP_STATUS_CMD_DONE)
12378 break;
12379 udelay(10);
12380 }
12381
12382 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12383}
12384
12385/* Read the gphy configuration from the OTP region of the chip. The gphy
12386 * configuration is a 32-bit value that straddles the alignment boundary.
12387 * We do two 32-bit reads and then shift and merge the results.
12388 */
12389static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12390{
12391 u32 bhalf_otp, thalf_otp;
12392
12393 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12394
12395 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12396 return 0;
12397
12398 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12399
12400 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12401 return 0;
12402
12403 thalf_otp = tr32(OTP_READ_DATA);
12404
12405 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12406
12407 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12408 return 0;
12409
12410 bhalf_otp = tr32(OTP_READ_DATA);
12411
12412 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12413}
12414
7d0c41ef
MC		 12415static int __devinit tg3_phy_probe(struct tg3 *tp)
12416{
12417 u32 hw_phy_id_1, hw_phy_id_2;
12418 u32 hw_phy_id, hw_phy_id_masked;
12419 int err;
1da177e4 12420
b02fd9e3
MC		 12421 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12422 return tg3_phy_init(tp);
12423
1da177e4 12424 /* Reading the PHY ID register can conflict with ASF
877d0310 12425 * firmware access to the PHY hardware.
1da177e4
LT		 12426 */
12427 err = 0;
0d3031d9
MC		 12428 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12429 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12430 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12431 } else {
12432 /* Now read the physical PHY_ID from the chip and verify
12433 * that it is sane. If it doesn't look good, we fall back
12434 * to either the hard-coded table based PHY_ID and failing
12435 * that the value found in the eeprom area.
12436 */
12437 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12438 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12439
12440 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12441 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12442 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12443
12444 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12445 }
12446
12447 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12448 tp->phy_id = hw_phy_id;
12449 if (hw_phy_id_masked == PHY_ID_BCM8002)
12450 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12451 else
12452 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12453 } else {
7d0c41ef
MC		 12454 if (tp->phy_id != PHY_ID_INVALID) {
12455 /* Do nothing, phy ID already set up in
12456 * tg3_get_eeprom_hw_cfg().
12457 */
1da177e4
LT		 12458 } else {
12459 struct subsys_tbl_ent *p;
12460
12461 /* No eeprom signature? Try the hardcoded
12462 * subsys device table.
12463 */
12464 p = lookup_by_subsys(tp);
12465 if (!p)
12466 return -ENODEV;
12467
12468 tp->phy_id = p->phy_id;
12469 if (!tp->phy_id ||
12470 tp->phy_id == PHY_ID_BCM8002)
12471 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12472 }
12473 }
12474
747e8f8b 12475 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12476 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12477 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12478 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12479
12480 tg3_readphy(tp, MII_BMSR, &bmsr);
12481 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12482 (bmsr & BMSR_LSTATUS))
12483 goto skip_phy_reset;
6aa20a22 12484
1da177e4
LT		 12485 err = tg3_phy_reset(tp);
12486 if (err)
12487 return err;
12488
12489 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12490 ADVERTISE_100HALF | ADVERTISE_100FULL |
12491 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12492 tg3_ctrl = 0;
12493 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12494 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12495 MII_TG3_CTRL_ADV_1000_FULL);
12496 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12497 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12498 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12499 MII_TG3_CTRL_ENABLE_AS_MASTER);
12500 }
12501
3600d918
MC		 12502 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12503 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12504 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12505 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12506 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12507
12508 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12509 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12510
12511 tg3_writephy(tp, MII_BMCR,
12512 BMCR_ANENABLE | BMCR_ANRESTART);
12513 }
12514 tg3_phy_set_wirespeed(tp);
12515
12516 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12517 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12518 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12519 }
12520
12521skip_phy_reset:
12522 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12523 err = tg3_init_5401phy_dsp(tp);
12524 if (err)
12525 return err;
12526 }
12527
12528 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12529 err = tg3_init_5401phy_dsp(tp);
12530 }
12531
747e8f8b 12532 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12533 tp->link_config.advertising =
12534 (ADVERTISED_1000baseT_Half |
12535 ADVERTISED_1000baseT_Full |
12536 ADVERTISED_Autoneg |
12537 ADVERTISED_FIBRE);
12538 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12539 tp->link_config.advertising &=
12540 ~(ADVERTISED_1000baseT_Half |
12541 ADVERTISED_1000baseT_Full);
12542
12543 return err;
12544}
12545
12546static void __devinit tg3_read_partno(struct tg3 *tp)
12547{
141518c9 12548 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12549 unsigned int i;
1b27777a 12550 u32 magic;
1da177e4 12551
df259d8c
MC		 12552 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12553 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12554 goto out_not_found;
1da177e4 12555
1820180b 12556 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12557 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12558 u32 tmp;
1da177e4 12559
6d348f2c
MC		 12560 /* The data is in little-endian format in NVRAM.
12561 * Use the big-endian read routines to preserve
12562 * the byte order as it exists in NVRAM.
12563 */
141518c9 12564 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12565 goto out_not_found;
12566
6d348f2c 12567 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12568 }
12569 } else {
94c982bd
MC		 12570 ssize_t cnt;
12571 unsigned int pos = 0, i = 0;
12572
12573 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12574 cnt = pci_read_vpd(tp->pdev, pos,
12575 TG3_NVM_VPD_LEN - pos,
12576 &vpd_data[pos]);
12577 if (cnt == -ETIMEDOUT || -EINTR)
12578 cnt = 0;
12579 else if (cnt < 0)
f49639e6 12580 goto out_not_found;
1b27777a 12581 }
94c982bd
MC		 12582 if (pos != TG3_NVM_VPD_LEN)
12583 goto out_not_found;
1da177e4
LT		 12584 }
12585
12586 /* Now parse and find the part number. */
141518c9 12587 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12588 unsigned char val = vpd_data[i];
af2c6a4a 12589 unsigned int block_end;
1da177e4
LT		 12590
12591 if (val == 0x82 || val == 0x91) {
12592 i = (i + 3 +
12593 (vpd_data[i + 1] +
12594 (vpd_data[i + 2] << 8)));
12595 continue;
12596 }
12597
12598 if (val != 0x90)
12599 goto out_not_found;
12600
12601 block_end = (i + 3 +
12602 (vpd_data[i + 1] +
12603 (vpd_data[i + 2] << 8)));
12604 i += 3;
af2c6a4a 12605
141518c9 12606 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12607 goto out_not_found;
12608
12609 while (i < (block_end - 2)) {
1da177e4
LT		 12610 if (vpd_data[i + 0] == 'P' &&
12611 vpd_data[i + 1] == 'N') {
12612 int partno_len = vpd_data[i + 2];
12613
af2c6a4a 12614 i += 3;
141518c9
MC		 12615 if (partno_len > TG3_BPN_SIZE ||
12616 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12617 goto out_not_found;
12618
12619 memcpy(tp->board_part_number,
af2c6a4a 12620 &vpd_data[i], partno_len);
1da177e4
LT		 12621
12622 /* Success. */
12623 return;
12624 }
af2c6a4a 12625 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12626 }
12627
12628 /* Part number not found. */
12629 goto out_not_found;
12630 }
12631
12632out_not_found:
b5d3772c
MC		 12633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12634 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12635 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12636 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12637 strcpy(tp->board_part_number, "BCM57780");
12638 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12639 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12640 strcpy(tp->board_part_number, "BCM57760");
12641 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12642 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12643 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12644 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12645 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12646 strcpy(tp->board_part_number, "BCM57788");
b703df6f
MC		 12647 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12648 strcpy(tp->board_part_number, "BCM57765");
b5d3772c
MC		 12649 else
12650 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12651}
12652
9c8a620e
MC		 12653static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12654{
12655 u32 val;
12656
e4f34110 12657 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12658 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12659 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12660 val != 0)
12661 return 0;
12662
12663 return 1;
12664}
12665
acd9c119
MC		 12666static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12667{
ff3a7cb2 12668 u32 val, offset, start, ver_offset;
acd9c119 12669 int i;
ff3a7cb2 12670 bool newver = false;
acd9c119
MC		 12671
12672 if (tg3_nvram_read(tp, 0xc, &offset) ||
12673 tg3_nvram_read(tp, 0x4, &start))
12674 return;
12675
12676 offset = tg3_nvram_logical_addr(tp, offset);
12677
ff3a7cb2 12678 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12679 return;
12680
ff3a7cb2
MC		 12681 if ((val & 0xfc000000) == 0x0c000000) {
12682 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12683 return;
12684
ff3a7cb2
MC		 12685 if (val == 0)
12686 newver = true;
12687 }
12688
12689 if (newver) {
12690 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12691 return;
12692
12693 offset = offset + ver_offset - start;
12694 for (i = 0; i < 16; i += 4) {
12695 __be32 v;
12696 if (tg3_nvram_read_be32(tp, offset + i, &v))
12697 return;
12698
12699 memcpy(tp->fw_ver + i, &v, sizeof(v));
12700 }
12701 } else {
12702 u32 major, minor;
12703
12704 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12705 return;
12706
12707 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12708 TG3_NVM_BCVER_MAJSFT;
12709 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12710 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12711 }
12712}
12713
a6f6cb1c
MC		 12714static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12715{
12716 u32 val, major, minor;
12717
12718 /* Use native endian representation */
12719 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12720 return;
12721
12722 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12723 TG3_NVM_HWSB_CFG1_MAJSFT;
12724 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12725 TG3_NVM_HWSB_CFG1_MINSFT;
12726
12727 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12728}
12729
dfe00d7d
MC		 12730static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12731{
12732 u32 offset, major, minor, build;
12733
12734 tp->fw_ver[0] = 's';
12735 tp->fw_ver[1] = 'b';
12736 tp->fw_ver[2] = '\0';
12737
12738 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12739 return;
12740
12741 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12742 case TG3_EEPROM_SB_REVISION_0:
12743 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12744 break;
12745 case TG3_EEPROM_SB_REVISION_2:
12746 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12747 break;
12748 case TG3_EEPROM_SB_REVISION_3:
12749 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12750 break;
12751 default:
12752 return;
12753 }
12754
e4f34110 12755 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12756 return;
12757
12758 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12759 TG3_EEPROM_SB_EDH_BLD_SHFT;
12760 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12761 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12762 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12763
12764 if (minor > 99 || build > 26)
12765 return;
12766
12767 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12768
12769 if (build > 0) {
12770 tp->fw_ver[8] = 'a' + build - 1;
12771 tp->fw_ver[9] = '\0';
12772 }
12773}
12774
acd9c119 12775static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12776{
12777 u32 val, offset, start;
acd9c119 12778 int i, vlen;
9c8a620e
MC		 12779
12780 for (offset = TG3_NVM_DIR_START;
12781 offset < TG3_NVM_DIR_END;
12782 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12783 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12784 return;
12785
9c8a620e
MC		 12786 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12787 break;
12788 }
12789
12790 if (offset == TG3_NVM_DIR_END)
12791 return;
12792
12793 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12794 start = 0x08000000;
e4f34110 12795 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12796 return;
12797
e4f34110 12798 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12799 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12800 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12801 return;
12802
12803 offset += val - start;
12804
acd9c119 12805 vlen = strlen(tp->fw_ver);
9c8a620e 12806
acd9c119
MC		 12807 tp->fw_ver[vlen++] = ',';
12808 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12809
12810 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12811 __be32 v;
12812 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12813 return;
12814
b9fc7dc5 12815 offset += sizeof(v);
c4e6575c 12816
acd9c119
MC		 12817 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12818 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12819 break;
c4e6575c 12820 }
9c8a620e 12821
acd9c119
MC		 12822 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12823 vlen += sizeof(v);
c4e6575c 12824 }
acd9c119
MC		 12825}
12826
7fd76445
MC		 12827static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12828{
12829 int vlen;
12830 u32 apedata;
12831
12832 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12833 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12834 return;
12835
12836 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12837 if (apedata != APE_SEG_SIG_MAGIC)
12838 return;
12839
12840 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12841 if (!(apedata & APE_FW_STATUS_READY))
12842 return;
12843
12844 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12845
12846 vlen = strlen(tp->fw_ver);
12847
12848 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12849 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12850 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12851 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12852 (apedata & APE_FW_VERSION_BLDMSK));
12853}
12854
acd9c119
MC		 12855static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12856{
12857 u32 val;
12858
df259d8c
MC		 12859 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12860 tp->fw_ver[0] = 's';
12861 tp->fw_ver[1] = 'b';
12862 tp->fw_ver[2] = '\0';
12863
12864 return;
12865 }
12866
acd9c119
MC		 12867 if (tg3_nvram_read(tp, 0, &val))
12868 return;
12869
12870 if (val == TG3_EEPROM_MAGIC)
12871 tg3_read_bc_ver(tp);
12872 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12873 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12874 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12875 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12876 else
12877 return;
12878
12879 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12880 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12881 return;
12882
12883 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12884
12885 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12886}
12887
7544b097
MC		 12888static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12889
1da177e4
LT		 12890static int __devinit tg3_get_invariants(struct tg3 *tp)
12891{
12892 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12893 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12894 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12895 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12896 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12897 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12898 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12899 { },
12900 };
12901 u32 misc_ctrl_reg;
1da177e4
LT		 12902 u32 pci_state_reg, grc_misc_cfg;
12903 u32 val;
12904 u16 pci_cmd;
5e7dfd0f 12905 int err;
1da177e4 12906
1da177e4
LT		 12907 /* Force memory write invalidate off. If we leave it on,
12908 * then on 5700_BX chips we have to enable a workaround.
12909 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12910 * to match the cacheline size. The Broadcom driver have this
12911 * workaround but turns MWI off all the times so never uses
12912 * it. This seems to suggest that the workaround is insufficient.
12913 */
12914 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12915 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12916 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12917
12918 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12919 * has the register indirect write enable bit set before
12920 * we try to access any of the MMIO registers. It is also
12921 * critical that the PCI-X hw workaround situation is decided
12922 * before that as well.
12923 */
12924 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12925 &misc_ctrl_reg);
12926
12927 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12928 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12929 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12930 u32 prod_id_asic_rev;
12931
5001e2f6
MC		 12932 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12933 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12934 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12935 pci_read_config_dword(tp->pdev,
12936 TG3PCI_GEN2_PRODID_ASICREV,
12937 &prod_id_asic_rev);
b703df6f
MC		 12938 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12940 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12941 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12944 pci_read_config_dword(tp->pdev,
12945 TG3PCI_GEN15_PRODID_ASICREV,
12946 &prod_id_asic_rev);
f6eb9b1f
MC		 12947 else
12948 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12949 &prod_id_asic_rev);
12950
321d32a0 12951 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12952 }
1da177e4 12953
ff645bec
MC		 12954 /* Wrong chip ID in 5752 A0. This code can be removed later
12955 * as A0 is not in production.
12956 */
12957 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12958 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12959
6892914f
MC		 12960 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12961 * we need to disable memory and use config. cycles
12962 * only to access all registers. The 5702/03 chips
12963 * can mistakenly decode the special cycles from the
12964 * ICH chipsets as memory write cycles, causing corruption
12965 * of register and memory space. Only certain ICH bridges
12966 * will drive special cycles with non-zero data during the
12967 * address phase which can fall within the 5703's address
12968 * range. This is not an ICH bug as the PCI spec allows
12969 * non-zero address during special cycles. However, only
12970 * these ICH bridges are known to drive non-zero addresses
12971 * during special cycles.
12972 *
12973 * Since special cycles do not cross PCI bridges, we only
12974 * enable this workaround if the 5703 is on the secondary
12975 * bus of these ICH bridges.
12976 */
12977 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12978 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12979 static struct tg3_dev_id {
12980 u32 vendor;
12981 u32 device;
12982 u32 rev;
12983 } ich_chipsets[] = {
12984 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12985 PCI_ANY_ID },
12986 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12987 PCI_ANY_ID },
12988 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12989 0xa },
12990 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12991 PCI_ANY_ID },
12992 { },
12993 };
12994 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12995 struct pci_dev *bridge = NULL;
12996
12997 while (pci_id->vendor != 0) {
12998 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12999 bridge);
13000 if (!bridge) {
13001 pci_id++;
13002 continue;
13003 }
13004 if (pci_id->rev != PCI_ANY_ID) {
44c10138 13005 if (bridge->revision > pci_id->rev)
6892914f
MC		 13006 continue;
13007 }
13008 if (bridge->subordinate &&
13009 (bridge->subordinate->number ==
13010 tp->pdev->bus->number)) {
13011
13012 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13013 pci_dev_put(bridge);
13014 break;
13015 }
13016 }
13017 }
13018
41588ba1
MC		 13019 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13020 static struct tg3_dev_id {
13021 u32 vendor;
13022 u32 device;
13023 } bridge_chipsets[] = {
13024 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13025 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13026 { },
13027 };
13028 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13029 struct pci_dev *bridge = NULL;
13030
13031 while (pci_id->vendor != 0) {
13032 bridge = pci_get_device(pci_id->vendor,
13033 pci_id->device,
13034 bridge);
13035 if (!bridge) {
13036 pci_id++;
13037 continue;
13038 }
13039 if (bridge->subordinate &&
13040 (bridge->subordinate->number <=
13041 tp->pdev->bus->number) &&
13042 (bridge->subordinate->subordinate >=
13043 tp->pdev->bus->number)) {
13044 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13045 pci_dev_put(bridge);
13046 break;
13047 }
13048 }
13049 }
13050
4a29cc2e
MC		 13051 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13052 * DMA addresses > 40-bit. This bridge may have other additional
13053 * 57xx devices behind it in some 4-port NIC designs for example.
13054 * Any tg3 device found behind the bridge will also need the 40-bit
13055 * DMA workaround.
13056 */
a4e2b347
MC		 13057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13059 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 13060 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 13061 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 13062 }
4a29cc2e
MC		 13063 else {
13064 struct pci_dev *bridge = NULL;
13065
13066 do {
13067 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13068 PCI_DEVICE_ID_SERVERWORKS_EPB,
13069 bridge);
13070 if (bridge && bridge->subordinate &&
13071 (bridge->subordinate->number <=
13072 tp->pdev->bus->number) &&
13073 (bridge->subordinate->subordinate >=
13074 tp->pdev->bus->number)) {
13075 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13076 pci_dev_put(bridge);
13077 break;
13078 }
13079 } while (bridge);
13080 }
4cf78e4f 13081
1da177e4
LT		 13082 /* Initialize misc host control in PCI block. */
13083 tp->misc_host_ctrl |= (misc_ctrl_reg &
13084 MISC_HOST_CTRL_CHIPREV);
13085 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13086 tp->misc_host_ctrl);
13087
f6eb9b1f
MC		 13088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 13091 tp->pdev_peer = tg3_find_peer(tp);
13092
321d32a0
MC		 13093 /* Intentionally exclude ASIC_REV_5906 */
13094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 13095 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 13096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 13097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13102 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13103
13104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13107 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13108 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13109 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13110
1b440c56
JL		 13111 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13112 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13113 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13114
027455ad
MC		 13115 /* 5700 B0 chips do not support checksumming correctly due
13116 * to hardware bugs.
13117 */
13118 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13119 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13120 else {
13121 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13122 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13123 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13124 tp->dev->features |= NETIF_F_IPV6_CSUM;
13125 }
13126
507399f1 13127 /* Determine TSO capabilities */
b703df6f
MC		 13128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13130 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13131 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13133 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13134 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13135 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13137 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13138 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13139 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13140 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13141 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13142 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13144 tp->fw_needed = FIRMWARE_TG3TSO5;
13145 else
13146 tp->fw_needed = FIRMWARE_TG3TSO;
13147 }
13148
13149 tp->irq_max = 1;
13150
5a6f3074 13151 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13152 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13153 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13154 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13155 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13156 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13157 tp->pdev_peer == tp->pdev))
13158 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13159
321d32a0 13160 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13162 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13163 }
4f125f42 13164
b703df6f
MC		 13165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13167 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13168 tp->irq_max = TG3_IRQ_MAX_VECS;
13169 }
f6eb9b1f 13170 }
0e1406dd 13171
615774fe
MC		 13172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13174 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13175 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13176 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13177 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13178 }
f6eb9b1f 13179
b703df6f
MC		 13180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13182 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13183
f51f3562 13184 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13185 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13186 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13187 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13188
52f4490c
MC		 13189 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13190 &pci_state_reg);
13191
5e7dfd0f
MC		 13192 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13193 if (tp->pcie_cap != 0) {
13194 u16 lnkctl;
13195
1da177e4 13196 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13197
13198 pcie_set_readrq(tp->pdev, 4096);
13199
5e7dfd0f
MC		 13200 pci_read_config_word(tp->pdev,
13201 tp->pcie_cap + PCI_EXP_LNKCTL,
13202 &lnkctl);
13203 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13205 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13208 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13209 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13210 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13211 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13212 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13213 }
52f4490c 13214 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13215 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13216 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13217 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13218 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13219 if (!tp->pcix_cap) {
13220 printk(KERN_ERR PFX "Cannot find PCI-X "
13221 "capability, aborting.\n");
13222 return -EIO;
13223 }
13224
13225 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13226 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13227 }
1da177e4 13228
399de50b
MC		 13229 /* If we have an AMD 762 or VIA K8T800 chipset, write
13230 * reordering to the mailbox registers done by the host
13231 * controller can cause major troubles. We read back from
13232 * every mailbox register write to force the writes to be
13233 * posted to the chip in order.
13234 */
13235 if (pci_dev_present(write_reorder_chipsets) &&
13236 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13237 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13238
69fc4053
MC		 13239 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13240 &tp->pci_cacheline_sz);
13241 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13242 &tp->pci_lat_timer);
1da177e4
LT		 13243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13244 tp->pci_lat_timer < 64) {
13245 tp->pci_lat_timer = 64;
69fc4053
MC		 13246 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13247 tp->pci_lat_timer);
1da177e4
LT		 13248 }
13249
52f4490c
MC		 13250 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13251 /* 5700 BX chips need to have their TX producer index
13252 * mailboxes written twice to workaround a bug.
13253 */
13254 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13255
52f4490c 13256 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13257 *
13258 * The workaround is to use indirect register accesses
13259 * for all chip writes not to mailbox registers.
13260 */
52f4490c 13261 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13262 u32 pm_reg;
1da177e4
LT		 13263
13264 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13265
13266 /* The chip can have it's power management PCI config
13267 * space registers clobbered due to this bug.
13268 * So explicitly force the chip into D0 here.
13269 */
9974a356
MC		 13270 pci_read_config_dword(tp->pdev,
13271 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13272 &pm_reg);
13273 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13274 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13275 pci_write_config_dword(tp->pdev,
13276 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13277 pm_reg);
13278
13279 /* Also, force SERR#/PERR# in PCI command. */
13280 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13281 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13282 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13283 }
13284 }
13285
1da177e4
LT		 13286 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13287 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13288 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13289 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13290
13291 /* Chip-specific fixup from Broadcom driver */
13292 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13293 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13294 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13295 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13296 }
13297
1ee582d8 13298 /* Default fast path register access methods */
20094930 13299 tp->read32 = tg3_read32;
1ee582d8 13300 tp->write32 = tg3_write32;
09ee929c 13301 tp->read32_mbox = tg3_read32;
20094930 13302 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13303 tp->write32_tx_mbox = tg3_write32;
13304 tp->write32_rx_mbox = tg3_write32;
13305
13306 /* Various workaround register access methods */
13307 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13308 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13309 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13310 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13311 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13312 /*
13313 * Back to back register writes can cause problems on these
13314 * chips, the workaround is to read back all reg writes
13315 * except those to mailbox regs.
13316 *
13317 * See tg3_write_indirect_reg32().
13318 */
1ee582d8 13319 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13320 }
13321
1ee582d8
MC		 13322 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13323 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13324 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13325 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13326 tp->write32_rx_mbox = tg3_write_flush_reg32;
13327 }
20094930 13328
6892914f
MC		 13329 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13330 tp->read32 = tg3_read_indirect_reg32;
13331 tp->write32 = tg3_write_indirect_reg32;
13332 tp->read32_mbox = tg3_read_indirect_mbox;
13333 tp->write32_mbox = tg3_write_indirect_mbox;
13334 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13335 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13336
13337 iounmap(tp->regs);
22abe310 13338 tp->regs = NULL;
6892914f
MC		 13339
13340 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13341 pci_cmd &= ~PCI_COMMAND_MEMORY;
13342 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13343 }
b5d3772c
MC		 13344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13345 tp->read32_mbox = tg3_read32_mbox_5906;
13346 tp->write32_mbox = tg3_write32_mbox_5906;
13347 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13348 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13349 }
6892914f 13350
bbadf503
MC		 13351 if (tp->write32 == tg3_write_indirect_reg32 ||
13352 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13353 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13355 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13356
7d0c41ef 13357 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13358 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13359 * determined before calling tg3_set_power_state() so that
13360 * we know whether or not to switch out of Vaux power.
13361 * When the flag is set, it means that GPIO1 is used for eeprom
13362 * write protect and also implies that it is a LOM where GPIOs
13363 * are not used to switch power.
6aa20a22 13364 */
7d0c41ef
MC		 13365 tg3_get_eeprom_hw_cfg(tp);
13366
0d3031d9
MC		 13367 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13368 /* Allow reads and writes to the
13369 * APE register and memory space.
13370 */
13371 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13372 PCISTATE_ALLOW_APE_SHMEM_WR;
13373 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13374 pci_state_reg);
13375 }
13376
9936bcf6 13377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13380 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13381 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13383 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13384
314fba34
MC		 13385 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13386 * GPIO1 driven high will bring 5700's external PHY out of reset.
13387 * It is also used as eeprom write protect on LOMs.
13388 */
13389 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13390 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13391 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13392 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13393 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13394 /* Unused GPIO3 must be driven as output on 5752 because there
13395 * are no pull-up resistors on unused GPIO pins.
13396 */
13397 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13398 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13399
321d32a0 13400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13401 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13403 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13404
8d519ab2
MC		 13405 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13406 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13407 /* Turn off the debug UART. */
13408 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13409 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13410 /* Keep VMain power. */
13411 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13412 GRC_LCLCTRL_GPIO_OUTPUT0;
13413 }
13414
1da177e4 13415 /* Force the chip into D0. */
bc1c7567 13416 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13417 if (err) {
13418 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13419 pci_name(tp->pdev));
13420 return err;
13421 }
13422
1da177e4
LT		 13423 /* Derive initial jumbo mode from MTU assigned in
13424 * ether_setup() via the alloc_etherdev() call
13425 */
0f893dc6 13426 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13427 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13428 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13429
13430 /* Determine WakeOnLan speed to use. */
13431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13432 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13433 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13434 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13435 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13436 } else {
13437 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13438 }
13439
7f97a4bd
MC		 13440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13441 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13442
1da177e4
LT		 13443 /* A few boards don't want Ethernet@WireSpeed phy feature */
13444 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13445 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13446 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13447 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13448 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13449 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13450 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13451
13452 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13453 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13454 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13455 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13456 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13457
321d32a0 13458 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13459 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13460 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13461 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13462 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13463 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13468 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13469 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13470 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13471 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13472 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13473 } else
c424cb24
MC		 13474 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13475 }
1da177e4 13476
b2a5c19c
MC		 13477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13478 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13479 tp->phy_otp = tg3_read_otp_phycfg(tp);
13480 if (tp->phy_otp == 0)
13481 tp->phy_otp = TG3_OTP_DEFAULT;
13482 }
13483
f51f3562 13484 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13485 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13486 else
13487 tp->mi_mode = MAC_MI_MODE_BASE;
13488
1da177e4 13489 tp->coalesce_mode = 0;
1da177e4
LT		 13490 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13491 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13492 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13493
321d32a0
MC		 13494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13495 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13496 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13497
158d7abd
MC		 13498 err = tg3_mdio_init(tp);
13499 if (err)
13500 return err;
1da177e4 13501
55dffe79
MC		 13502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13503 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13504 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13505 return -ENOTSUPP;
13506
1da177e4
LT		 13507 /* Initialize data/descriptor byte/word swapping. */
13508 val = tr32(GRC_MODE);
13509 val &= GRC_MODE_HOST_STACKUP;
13510 tw32(GRC_MODE, val | tp->grc_mode);
13511
13512 tg3_switch_clocks(tp);
13513
13514 /* Clear this out for sanity. */
13515 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13516
13517 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13518 &pci_state_reg);
13519 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13520 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13521 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13522
13523 if (chiprevid == CHIPREV_ID_5701_A0 ||
13524 chiprevid == CHIPREV_ID_5701_B0 ||
13525 chiprevid == CHIPREV_ID_5701_B2 ||
13526 chiprevid == CHIPREV_ID_5701_B5) {
13527 void __iomem *sram_base;
13528
13529 /* Write some dummy words into the SRAM status block
13530 * area, see if it reads back correctly. If the return
13531 * value is bad, force enable the PCIX workaround.
13532 */
13533 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13534
13535 writel(0x00000000, sram_base);
13536 writel(0x00000000, sram_base + 4);
13537 writel(0xffffffff, sram_base + 4);
13538 if (readl(sram_base) != 0x00000000)
13539 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13540 }
13541 }
13542
13543 udelay(50);
13544 tg3_nvram_init(tp);
13545
13546 grc_misc_cfg = tr32(GRC_MISC_CFG);
13547 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13548
1da177e4
LT		 13549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13550 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13551 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13552 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13553
fac9b83e
DM		 13554 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13555 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13556 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13557 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13558 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13559 HOSTCC_MODE_CLRTICK_TXBD);
13560
13561 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13562 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13563 tp->misc_host_ctrl);
13564 }
13565
3bda1258
MC		 13566 /* Preserve the APE MAC_MODE bits */
13567 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13568 tp->mac_mode = tr32(MAC_MODE) |
13569 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13570 else
13571 tp->mac_mode = TG3_DEF_MAC_MODE;
13572
1da177e4
LT		 13573 /* these are limited to 10/100 only */
13574 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13575 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13576 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13577 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13578 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13579 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13580 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13581 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13582 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13583 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13584 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13585 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13586 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13587 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13588
13589 err = tg3_phy_probe(tp);
13590 if (err) {
13591 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13592 pci_name(tp->pdev), err);
13593 /* ... but do not return immediately ... */
b02fd9e3 13594 tg3_mdio_fini(tp);
1da177e4
LT		 13595 }
13596
13597 tg3_read_partno(tp);
c4e6575c 13598 tg3_read_fw_ver(tp);
1da177e4
LT		 13599
13600 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13601 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13602 } else {
13603 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13604 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13605 else
13606 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13607 }
13608
13609 /* 5700 {AX,BX} chips have a broken status block link
13610 * change bit implementation, so we must use the
13611 * status register in those cases.
13612 */
13613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13614 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13615 else
13616 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13617
13618 /* The led_ctrl is set during tg3_phy_probe, here we might
13619 * have to force the link status polling mechanism based
13620 * upon subsystem IDs.
13621 */
13622 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13624 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13625 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13626 TG3_FLAG_USE_LINKCHG_REG);
13627 }
13628
13629 /* For all SERDES we poll the MAC status register. */
13630 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13631 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13632 else
13633 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13634
ad829268 13635 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13637 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13638 tp->rx_offset = 0;
13639
f92905de
MC		 13640 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13641
13642 /* Increment the rx prod index on the rx std ring by at most
13643 * 8 for these chips to workaround hw errata.
13644 */
13645 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13648 tp->rx_std_max_post = 8;
13649
8ed5d97e
MC		 13650 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13651 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13652 PCIE_PWR_MGMT_L1_THRESH_MSK;
13653
1da177e4
LT		 13654 return err;
13655}
13656
49b6e95f 13657#ifdef CONFIG_SPARC
1da177e4
LT		 13658static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13659{
13660 struct net_device *dev = tp->dev;
13661 struct pci_dev *pdev = tp->pdev;
49b6e95f 13662 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13663 const unsigned char *addr;
49b6e95f
DM		 13664 int len;
13665
13666 addr = of_get_property(dp, "local-mac-address", &len);
13667 if (addr && len == 6) {
13668 memcpy(dev->dev_addr, addr, 6);
13669 memcpy(dev->perm_addr, dev->dev_addr, 6);
13670 return 0;
1da177e4
LT		 13671 }
13672 return -ENODEV;
13673}
13674
13675static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13676{
13677 struct net_device *dev = tp->dev;
13678
13679 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13680 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13681 return 0;
13682}
13683#endif
13684
13685static int __devinit tg3_get_device_address(struct tg3 *tp)
13686{
13687 struct net_device *dev = tp->dev;
13688 u32 hi, lo, mac_offset;
008652b3 13689 int addr_ok = 0;
1da177e4 13690
49b6e95f 13691#ifdef CONFIG_SPARC
1da177e4
LT		 13692 if (!tg3_get_macaddr_sparc(tp))
13693 return 0;
13694#endif
13695
13696 mac_offset = 0x7c;
f49639e6 13697 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13698 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13699 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13700 mac_offset = 0xcc;
13701 if (tg3_nvram_lock(tp))
13702 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13703 else
13704 tg3_nvram_unlock(tp);
a1b950d5
MC		 13705 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13706 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13707 mac_offset = 0xcc;
13708 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13709 mac_offset = 0x10;
1da177e4
LT		 13710
13711 /* First try to get it from MAC address mailbox. */
13712 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13713 if ((hi >> 16) == 0x484b) {
13714 dev->dev_addr[0] = (hi >> 8) & 0xff;
13715 dev->dev_addr[1] = (hi >> 0) & 0xff;
13716
13717 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13718 dev->dev_addr[2] = (lo >> 24) & 0xff;
13719 dev->dev_addr[3] = (lo >> 16) & 0xff;
13720 dev->dev_addr[4] = (lo >> 8) & 0xff;
13721 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13722
008652b3
MC		 13723 /* Some old bootcode may report a 0 MAC address in SRAM */
13724 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13725 }
13726 if (!addr_ok) {
13727 /* Next, try NVRAM. */
df259d8c
MC		 13728 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13729 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13730 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13731 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13732 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13733 }
13734 /* Finally just fetch it out of the MAC control regs. */
13735 else {
13736 hi = tr32(MAC_ADDR_0_HIGH);
13737 lo = tr32(MAC_ADDR_0_LOW);
13738
13739 dev->dev_addr[5] = lo & 0xff;
13740 dev->dev_addr[4] = (lo >> 8) & 0xff;
13741 dev->dev_addr[3] = (lo >> 16) & 0xff;
13742 dev->dev_addr[2] = (lo >> 24) & 0xff;
13743 dev->dev_addr[1] = hi & 0xff;
13744 dev->dev_addr[0] = (hi >> 8) & 0xff;
13745 }
1da177e4
LT		 13746 }
13747
13748 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13749#ifdef CONFIG_SPARC
1da177e4
LT		 13750 if (!tg3_get_default_macaddr_sparc(tp))
13751 return 0;
13752#endif
13753 return -EINVAL;
13754 }
2ff43697 13755 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13756 return 0;
13757}
13758
59e6b434
DM		 13759#define BOUNDARY_SINGLE_CACHELINE 1
13760#define BOUNDARY_MULTI_CACHELINE 2
13761
13762static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13763{
13764 int cacheline_size;
13765 u8 byte;
13766 int goal;
13767
13768 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13769 if (byte == 0)
13770 cacheline_size = 1024;
13771 else
13772 cacheline_size = (int) byte * 4;
13773
13774 /* On 5703 and later chips, the boundary bits have no
13775 * effect.
13776 */
13777 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13778 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13779 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13780 goto out;
13781
13782#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13783 goal = BOUNDARY_MULTI_CACHELINE;
13784#else
13785#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13786 goal = BOUNDARY_SINGLE_CACHELINE;
13787#else
13788 goal = 0;
13789#endif
13790#endif
13791
b703df6f
MC		 13792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13794 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13795 goto out;
13796 }
13797
59e6b434
DM		 13798 if (!goal)
13799 goto out;
13800
13801 /* PCI controllers on most RISC systems tend to disconnect
13802 * when a device tries to burst across a cache-line boundary.
13803 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13804 *
13805 * Unfortunately, for PCI-E there are only limited
13806 * write-side controls for this, and thus for reads
13807 * we will still get the disconnects. We'll also waste
13808 * these PCI cycles for both read and write for chips
13809 * other than 5700 and 5701 which do not implement the
13810 * boundary bits.
13811 */
13812 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13813 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13814 switch (cacheline_size) {
13815 case 16:
13816 case 32:
13817 case 64:
13818 case 128:
13819 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13820 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13821 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13822 } else {
13823 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13824 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13825 }
13826 break;
13827
13828 case 256:
13829 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13830 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13831 break;
13832
13833 default:
13834 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13835 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13836 break;
855e1111 13837 }
59e6b434
DM		 13838 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13839 switch (cacheline_size) {
13840 case 16:
13841 case 32:
13842 case 64:
13843 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13844 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13845 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13846 break;
13847 }
13848 /* fallthrough */
13849 case 128:
13850 default:
13851 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13852 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13853 break;
855e1111 13854 }
59e6b434
DM		 13855 } else {
13856 switch (cacheline_size) {
13857 case 16:
13858 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13859 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13860 DMA_RWCTRL_WRITE_BNDRY_16);
13861 break;
13862 }
13863 /* fallthrough */
13864 case 32:
13865 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13866 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13867 DMA_RWCTRL_WRITE_BNDRY_32);
13868 break;
13869 }
13870 /* fallthrough */
13871 case 64:
13872 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13873 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13874 DMA_RWCTRL_WRITE_BNDRY_64);
13875 break;
13876 }
13877 /* fallthrough */
13878 case 128:
13879 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13880 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13881 DMA_RWCTRL_WRITE_BNDRY_128);
13882 break;
13883 }
13884 /* fallthrough */
13885 case 256:
13886 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13887 DMA_RWCTRL_WRITE_BNDRY_256);
13888 break;
13889 case 512:
13890 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13891 DMA_RWCTRL_WRITE_BNDRY_512);
13892 break;
13893 case 1024:
13894 default:
13895 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13896 DMA_RWCTRL_WRITE_BNDRY_1024);
13897 break;
855e1111 13898 }
59e6b434
DM		 13899 }
13900
13901out:
13902 return val;
13903}
13904
1da177e4
LT		 13905static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13906{
13907 struct tg3_internal_buffer_desc test_desc;
13908 u32 sram_dma_descs;
13909 int i, ret;
13910
13911 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13912
13913 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13914 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13915 tw32(RDMAC_STATUS, 0);
13916 tw32(WDMAC_STATUS, 0);
13917
13918 tw32(BUFMGR_MODE, 0);
13919 tw32(FTQ_RESET, 0);
13920
13921 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13922 test_desc.addr_lo = buf_dma & 0xffffffff;
13923 test_desc.nic_mbuf = 0x00002100;
13924 test_desc.len = size;
13925
13926 /*
13927 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13928 * the *second* time the tg3 driver was getting loaded after an
13929 * initial scan.
13930 *
13931 * Broadcom tells me:
13932 * ...the DMA engine is connected to the GRC block and a DMA
13933 * reset may affect the GRC block in some unpredictable way...
13934 * The behavior of resets to individual blocks has not been tested.
13935 *
13936 * Broadcom noted the GRC reset will also reset all sub-components.
13937 */
13938 if (to_device) {
13939 test_desc.cqid_sqid = (13 << 8) | 2;
13940
13941 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13942 udelay(40);
13943 } else {
13944 test_desc.cqid_sqid = (16 << 8) | 7;
13945
13946 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13947 udelay(40);
13948 }
13949 test_desc.flags = 0x00000005;
13950
13951 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13952 u32 val;
13953
13954 val = *(((u32 *)&test_desc) + i);
13955 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13956 sram_dma_descs + (i * sizeof(u32)));
13957 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13958 }
13959 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13960
13961 if (to_device) {
13962 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13963 } else {
13964 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13965 }
13966
13967 ret = -ENODEV;
13968 for (i = 0; i < 40; i++) {
13969 u32 val;
13970
13971 if (to_device)
13972 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13973 else
13974 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13975 if ((val & 0xffff) == sram_dma_descs) {
13976 ret = 0;
13977 break;
13978 }
13979
13980 udelay(100);
13981 }
13982
13983 return ret;
13984}
13985
ded7340d 13986#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13987
13988static int __devinit tg3_test_dma(struct tg3 *tp)
13989{
13990 dma_addr_t buf_dma;
59e6b434 13991 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13992 int ret = 0;
1da177e4
LT		 13993
13994 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13995 if (!buf) {
13996 ret = -ENOMEM;
13997 goto out_nofree;
13998 }
13999
14000 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14001 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14002
59e6b434 14003 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 14004
b703df6f
MC		 14005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 14007 goto out;
14008
1da177e4
LT		 14009 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14010 /* DMA read watermark not used on PCIE */
14011 tp->dma_rwctrl |= 0x00180000;
14012 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 14013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 14015 tp->dma_rwctrl |= 0x003f0000;
14016 else
14017 tp->dma_rwctrl |= 0x003f000f;
14018 } else {
14019 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14021 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 14022 u32 read_water = 0x7;
1da177e4 14023
4a29cc2e
MC		 14024 /* If the 5704 is behind the EPB bridge, we can
14025 * do the less restrictive ONE_DMA workaround for
14026 * better performance.
14027 */
14028 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14030 tp->dma_rwctrl |= 0x8000;
14031 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 14032 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14033
49afdeb6
MC		 14034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14035 read_water = 4;
59e6b434 14036 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 14037 tp->dma_rwctrl |=
14038 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14039 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14040 (1 << 23);
4cf78e4f
MC		 14041 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14042 /* 5780 always in PCIX mode */
14043 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 14044 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14045 /* 5714 always in PCIX mode */
14046 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 14047 } else {
14048 tp->dma_rwctrl |= 0x001b000f;
14049 }
14050 }
14051
14052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14054 tp->dma_rwctrl &= 0xfffffff0;
14055
14056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14058 /* Remove this if it causes problems for some boards. */
14059 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14060
14061 /* On 5700/5701 chips, we need to set this bit.
14062 * Otherwise the chip will issue cacheline transactions
14063 * to streamable DMA memory with not all the byte
14064 * enables turned on. This is an error on several
14065 * RISC PCI controllers, in particular sparc64.
14066 *
14067 * On 5703/5704 chips, this bit has been reassigned
14068 * a different meaning. In particular, it is used
14069 * on those chips to enable a PCI-X workaround.
14070 */
14071 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14072 }
14073
14074 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14075
14076#if 0
14077 /* Unneeded, already done by tg3_get_invariants. */
14078 tg3_switch_clocks(tp);
14079#endif
14080
1da177e4
LT		 14081 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14082 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14083 goto out;
14084
59e6b434
DM		 14085 /* It is best to perform DMA test with maximum write burst size
14086 * to expose the 5700/5701 write DMA bug.
14087 */
14088 saved_dma_rwctrl = tp->dma_rwctrl;
14089 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14090 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14091
1da177e4
LT		 14092 while (1) {
14093 u32 *p = buf, i;
14094
14095 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14096 p[i] = i;
14097
14098 /* Send the buffer to the chip. */
14099 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14100 if (ret) {
14101 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14102 break;
14103 }
14104
14105#if 0
14106 /* validate data reached card RAM correctly. */
14107 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14108 u32 val;
14109 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14110 if (le32_to_cpu(val) != p[i]) {
14111 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14112 /* ret = -ENODEV here? */
14113 }
14114 p[i] = 0;
14115 }
14116#endif
14117 /* Now read it back. */
14118 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14119 if (ret) {
14120 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14121
14122 break;
14123 }
14124
14125 /* Verify it. */
14126 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14127 if (p[i] == i)
14128 continue;
14129
59e6b434
DM		 14130 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14131 DMA_RWCTRL_WRITE_BNDRY_16) {
14132 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14133 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14134 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14135 break;
14136 } else {
14137 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14138 ret = -ENODEV;
14139 goto out;
14140 }
14141 }
14142
14143 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14144 /* Success. */
14145 ret = 0;
14146 break;
14147 }
14148 }
59e6b434
DM		 14149 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14150 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14151 static struct pci_device_id dma_wait_state_chipsets[] = {
14152 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14153 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14154 { },
14155 };
14156
59e6b434 14157 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14158 * now look for chipsets that are known to expose the
14159 * DMA bug without failing the test.
59e6b434 14160 */
6d1cfbab
MC		 14161 if (pci_dev_present(dma_wait_state_chipsets)) {
14162 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14163 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14164 }
14165 else
14166 /* Safe to use the calculated DMA boundary. */
14167 tp->dma_rwctrl = saved_dma_rwctrl;
14168
59e6b434
DM		 14169 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14170 }
1da177e4
LT		 14171
14172out:
14173 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14174out_nofree:
14175 return ret;
14176}
14177
14178static void __devinit tg3_init_link_config(struct tg3 *tp)
14179{
14180 tp->link_config.advertising =
14181 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14182 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14183 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14184 ADVERTISED_Autoneg | ADVERTISED_MII);
14185 tp->link_config.speed = SPEED_INVALID;
14186 tp->link_config.duplex = DUPLEX_INVALID;
14187 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14188 tp->link_config.active_speed = SPEED_INVALID;
14189 tp->link_config.active_duplex = DUPLEX_INVALID;
14190 tp->link_config.phy_is_low_power = 0;
14191 tp->link_config.orig_speed = SPEED_INVALID;
14192 tp->link_config.orig_duplex = DUPLEX_INVALID;
14193 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14194}
14195
14196static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14197{
666bc831
MC		 14198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14199 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14200 tp->bufmgr_config.mbuf_read_dma_low_water =
14201 DEFAULT_MB_RDMA_LOW_WATER_5705;
14202 tp->bufmgr_config.mbuf_mac_rx_low_water =
14203 DEFAULT_MB_MACRX_LOW_WATER_57765;
14204 tp->bufmgr_config.mbuf_high_water =
14205 DEFAULT_MB_HIGH_WATER_57765;
14206
14207 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14208 DEFAULT_MB_RDMA_LOW_WATER_5705;
14209 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14210 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14211 tp->bufmgr_config.mbuf_high_water_jumbo =
14212 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14213 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14214 tp->bufmgr_config.mbuf_read_dma_low_water =
14215 DEFAULT_MB_RDMA_LOW_WATER_5705;
14216 tp->bufmgr_config.mbuf_mac_rx_low_water =
14217 DEFAULT_MB_MACRX_LOW_WATER_5705;
14218 tp->bufmgr_config.mbuf_high_water =
14219 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14221 tp->bufmgr_config.mbuf_mac_rx_low_water =
14222 DEFAULT_MB_MACRX_LOW_WATER_5906;
14223 tp->bufmgr_config.mbuf_high_water =
14224 DEFAULT_MB_HIGH_WATER_5906;
14225 }
fdfec172
MC		 14226
14227 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14228 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14229 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14230 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14231 tp->bufmgr_config.mbuf_high_water_jumbo =
14232 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14233 } else {
14234 tp->bufmgr_config.mbuf_read_dma_low_water =
14235 DEFAULT_MB_RDMA_LOW_WATER;
14236 tp->bufmgr_config.mbuf_mac_rx_low_water =
14237 DEFAULT_MB_MACRX_LOW_WATER;
14238 tp->bufmgr_config.mbuf_high_water =
14239 DEFAULT_MB_HIGH_WATER;
14240
14241 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14242 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14243 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14244 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14245 tp->bufmgr_config.mbuf_high_water_jumbo =
14246 DEFAULT_MB_HIGH_WATER_JUMBO;
14247 }
1da177e4
LT		 14248
14249 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14250 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14251}
14252
14253static char * __devinit tg3_phy_string(struct tg3 *tp)
14254{
14255 switch (tp->phy_id & PHY_ID_MASK) {
14256 case PHY_ID_BCM5400: return "5400";
14257 case PHY_ID_BCM5401: return "5401";
14258 case PHY_ID_BCM5411: return "5411";
14259 case PHY_ID_BCM5701: return "5701";
14260 case PHY_ID_BCM5703: return "5703";
14261 case PHY_ID_BCM5704: return "5704";
14262 case PHY_ID_BCM5705: return "5705";
14263 case PHY_ID_BCM5750: return "5750";
85e94ced 14264 case PHY_ID_BCM5752: return "5752";
a4e2b347 14265 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14266 case PHY_ID_BCM5780: return "5780";
af36e6b6 14267 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14268 case PHY_ID_BCM5787: return "5787";
d30cdd28 14269 case PHY_ID_BCM5784: return "5784";
126a3368 14270 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14271 case PHY_ID_BCM5906: return "5906";
9936bcf6 14272 case PHY_ID_BCM5761: return "5761";
9b952f51
MC		 14273 case PHY_ID_BCM5718C: return "5718C";
14274 case PHY_ID_BCM5718S: return "5718S";
b0f75221 14275 case PHY_ID_BCM57765: return "57765";
1da177e4
LT		 14276 case PHY_ID_BCM8002: return "8002/serdes";
14277 case 0: return "serdes";
14278 default: return "unknown";
855e1111 14279 }
1da177e4
LT		 14280}
14281
f9804ddb
MC		 14282static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14283{
14284 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14285 strcpy(str, "PCI Express");
14286 return str;
14287 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14288 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14289
14290 strcpy(str, "PCIX:");
14291
14292 if ((clock_ctrl == 7) ||
14293 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14294 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14295 strcat(str, "133MHz");
14296 else if (clock_ctrl == 0)
14297 strcat(str, "33MHz");
14298 else if (clock_ctrl == 2)
14299 strcat(str, "50MHz");
14300 else if (clock_ctrl == 4)
14301 strcat(str, "66MHz");
14302 else if (clock_ctrl == 6)
14303 strcat(str, "100MHz");
f9804ddb
MC		 14304 } else {
14305 strcpy(str, "PCI:");
14306 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14307 strcat(str, "66MHz");
14308 else
14309 strcat(str, "33MHz");
14310 }
14311 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14312 strcat(str, ":32-bit");
14313 else
14314 strcat(str, ":64-bit");
14315 return str;
14316}
14317
8c2dc7e1 14318static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14319{
14320 struct pci_dev *peer;
14321 unsigned int func, devnr = tp->pdev->devfn & ~7;
14322
14323 for (func = 0; func < 8; func++) {
14324 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14325 if (peer && peer != tp->pdev)
14326 break;
14327 pci_dev_put(peer);
14328 }
16fe9d74
MC		 14329 /* 5704 can be configured in single-port mode, set peer to
14330 * tp->pdev in that case.
14331 */
14332 if (!peer) {
14333 peer = tp->pdev;
14334 return peer;
14335 }
1da177e4
LT		 14336
14337 /*
14338 * We don't need to keep the refcount elevated; there's no way
14339 * to remove one half of this device without removing the other
14340 */
14341 pci_dev_put(peer);
14342
14343 return peer;
14344}
14345
15f9850d
DM		 14346static void __devinit tg3_init_coal(struct tg3 *tp)
14347{
14348 struct ethtool_coalesce *ec = &tp->coal;
14349
14350 memset(ec, 0, sizeof(*ec));
14351 ec->cmd = ETHTOOL_GCOALESCE;
14352 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14353 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14354 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14355 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14356 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14357 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14358 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14359 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14360 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14361
14362 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14363 HOSTCC_MODE_CLRTICK_TXBD)) {
14364 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14365 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14366 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14367 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14368 }
d244c892
MC		 14369
14370 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14371 ec->rx_coalesce_usecs_irq = 0;
14372 ec->tx_coalesce_usecs_irq = 0;
14373 ec->stats_block_coalesce_usecs = 0;
14374 }
15f9850d
DM		 14375}
14376
7c7d64b8
SH		 14377static const struct net_device_ops tg3_netdev_ops = {
14378 .ndo_open = tg3_open,
14379 .ndo_stop = tg3_close,
00829823
SH		 14380 .ndo_start_xmit = tg3_start_xmit,
14381 .ndo_get_stats = tg3_get_stats,
14382 .ndo_validate_addr = eth_validate_addr,
14383 .ndo_set_multicast_list = tg3_set_rx_mode,
14384 .ndo_set_mac_address = tg3_set_mac_addr,
14385 .ndo_do_ioctl = tg3_ioctl,
14386 .ndo_tx_timeout = tg3_tx_timeout,
14387 .ndo_change_mtu = tg3_change_mtu,
14388#if TG3_VLAN_TAG_USED
14389 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14390#endif
14391#ifdef CONFIG_NET_POLL_CONTROLLER
14392 .ndo_poll_controller = tg3_poll_controller,
14393#endif
14394};
14395
14396static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14397 .ndo_open = tg3_open,
14398 .ndo_stop = tg3_close,
14399 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14400 .ndo_get_stats = tg3_get_stats,
14401 .ndo_validate_addr = eth_validate_addr,
14402 .ndo_set_multicast_list = tg3_set_rx_mode,
14403 .ndo_set_mac_address = tg3_set_mac_addr,
14404 .ndo_do_ioctl = tg3_ioctl,
14405 .ndo_tx_timeout = tg3_tx_timeout,
14406 .ndo_change_mtu = tg3_change_mtu,
14407#if TG3_VLAN_TAG_USED
14408 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14409#endif
14410#ifdef CONFIG_NET_POLL_CONTROLLER
14411 .ndo_poll_controller = tg3_poll_controller,
14412#endif
14413};
14414
1da177e4
LT		 14415static int __devinit tg3_init_one(struct pci_dev *pdev,
14416 const struct pci_device_id *ent)
14417{
14418 static int tg3_version_printed = 0;
1da177e4
LT		 14419 struct net_device *dev;
14420 struct tg3 *tp;
646c9edd
MC		 14421 int i, err, pm_cap;
14422 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14423 char str[40];
72f2afb8 14424 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14425
14426 if (tg3_version_printed++ == 0)
14427 printk(KERN_INFO "%s", version);
14428
14429 err = pci_enable_device(pdev);
14430 if (err) {
14431 printk(KERN_ERR PFX "Cannot enable PCI device, "
14432 "aborting.\n");
14433 return err;
14434 }
14435
1da177e4
LT		 14436 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14437 if (err) {
14438 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14439 "aborting.\n");
14440 goto err_out_disable_pdev;
14441 }
14442
14443 pci_set_master(pdev);
14444
14445 /* Find power-management capability. */
14446 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14447 if (pm_cap == 0) {
14448 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14449 "aborting.\n");
14450 err = -EIO;
14451 goto err_out_free_res;
14452 }
14453
fe5f5787 14454 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14455 if (!dev) {
14456 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14457 err = -ENOMEM;
14458 goto err_out_free_res;
14459 }
14460
1da177e4
LT		 14461 SET_NETDEV_DEV(dev, &pdev->dev);
14462
1da177e4
LT		 14463#if TG3_VLAN_TAG_USED
14464 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14465#endif
14466
14467 tp = netdev_priv(dev);
14468 tp->pdev = pdev;
14469 tp->dev = dev;
14470 tp->pm_cap = pm_cap;
1da177e4
LT		 14471 tp->rx_mode = TG3_DEF_RX_MODE;
14472 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14473
1da177e4
LT		 14474 if (tg3_debug > 0)
14475 tp->msg_enable = tg3_debug;
14476 else
14477 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14478
14479 /* The word/byte swap controls here control register access byte
14480 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14481 * setting below.
14482 */
14483 tp->misc_host_ctrl =
14484 MISC_HOST_CTRL_MASK_PCI_INT |
14485 MISC_HOST_CTRL_WORD_SWAP |
14486 MISC_HOST_CTRL_INDIR_ACCESS |
14487 MISC_HOST_CTRL_PCISTATE_RW;
14488
14489 /* The NONFRM (non-frame) byte/word swap controls take effect
14490 * on descriptor entries, anything which isn't packet data.
14491 *
14492 * The StrongARM chips on the board (one for tx, one for rx)
14493 * are running in big-endian mode.
14494 */
14495 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14496 GRC_MODE_WSWAP_NONFRM_DATA);
14497#ifdef __BIG_ENDIAN
14498 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14499#endif
14500 spin_lock_init(&tp->lock);
1da177e4 14501 spin_lock_init(&tp->indirect_lock);
c4028958 14502 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14503
d5fe488a 14504 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14505 if (!tp->regs) {
1da177e4
LT		 14506 printk(KERN_ERR PFX "Cannot map device registers, "
14507 "aborting.\n");
14508 err = -ENOMEM;
14509 goto err_out_free_dev;
14510 }
14511
14512 tg3_init_link_config(tp);
14513
1da177e4
LT		 14514 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14515 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14516
1da177e4 14517 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14518 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14519 dev->irq = pdev->irq;
1da177e4
LT		 14520
14521 err = tg3_get_invariants(tp);
14522 if (err) {
14523 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14524 "aborting.\n");
14525 goto err_out_iounmap;
14526 }
14527
615774fe
MC		 14528 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14529 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14530 dev->netdev_ops = &tg3_netdev_ops;
14531 else
14532 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14533
14534
4a29cc2e
MC		 14535 /* The EPB bridge inside 5714, 5715, and 5780 and any
14536 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14537 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14538 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14539 * do DMA address check in tg3_start_xmit().
14540 */
4a29cc2e 14541 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14542 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14543 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14544 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14545#ifdef CONFIG_HIGHMEM
6a35528a 14546 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14547#endif
4a29cc2e 14548 } else
6a35528a 14549 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14550
14551 /* Configure DMA attributes. */
284901a9 14552 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14553 err = pci_set_dma_mask(pdev, dma_mask);
14554 if (!err) {
14555 dev->features |= NETIF_F_HIGHDMA;
14556 err = pci_set_consistent_dma_mask(pdev,
14557 persist_dma_mask);
14558 if (err < 0) {
14559 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14560 "DMA for consistent allocations\n");
14561 goto err_out_iounmap;
14562 }
14563 }
14564 }
284901a9
YH		 14565 if (err || dma_mask == DMA_BIT_MASK(32)) {
14566 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14567 if (err) {
14568 printk(KERN_ERR PFX "No usable DMA configuration, "
14569 "aborting.\n");
14570 goto err_out_iounmap;
14571 }
14572 }
14573
fdfec172 14574 tg3_init_bufmgr_config(tp);
1da177e4 14575
507399f1
MC		 14576 /* Selectively allow TSO based on operating conditions */
14577 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14578 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14579 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14580 else {
14581 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14582 tp->fw_needed = NULL;
1da177e4 14583 }
507399f1
MC		 14584
14585 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14586 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14587
4e3a7aaa
MC		 14588 /* TSO is on by default on chips that support hardware TSO.
14589 * Firmware TSO on older chips gives lower performance, so it
14590 * is off by default, but can be enabled using ethtool.
14591 */
e849cdc3
MC		 14592 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14593 (dev->features & NETIF_F_IP_CSUM))
14594 dev->features |= NETIF_F_TSO;
14595
14596 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14597 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14598 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14599 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14600 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14602 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14603 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14604 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14605 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14606 dev->features |= NETIF_F_TSO_ECN;
b0026624 14607 }
1da177e4 14608
1da177e4
LT		 14609 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14610 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14611 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14612 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14613 tp->rx_pending = 63;
14614 }
14615
1da177e4
LT		 14616 err = tg3_get_device_address(tp);
14617 if (err) {
14618 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14619 "aborting.\n");
026a6c21 14620 goto err_out_iounmap;
1da177e4
LT		 14621 }
14622
c88864df 14623 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14624 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14625 if (!tp->aperegs) {
c88864df
MC		 14626 printk(KERN_ERR PFX "Cannot map APE registers, "
14627 "aborting.\n");
14628 err = -ENOMEM;
026a6c21 14629 goto err_out_iounmap;
c88864df
MC		 14630 }
14631
14632 tg3_ape_lock_init(tp);
7fd76445
MC		 14633
14634 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14635 tg3_read_dash_ver(tp);
c88864df
MC		 14636 }
14637
1da177e4
LT		 14638 /*
14639 * Reset chip in case UNDI or EFI driver did not shutdown
14640 * DMA self test will enable WDMAC and we'll see (spurious)
14641 * pending DMA on the PCI bus at that point.
14642 */
14643 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14644 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14645 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14646 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14647 }
14648
14649 err = tg3_test_dma(tp);
14650 if (err) {
14651 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14652 goto err_out_apeunmap;
1da177e4
LT		 14653 }
14654
1da177e4
LT		 14655 /* flow control autonegotiation is default behavior */
14656 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14657 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14658
78f90dcf
MC		 14659 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14660 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14661 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14662 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14663 struct tg3_napi *tnapi = &tp->napi[i];
14664
14665 tnapi->tp = tp;
14666 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14667
14668 tnapi->int_mbox = intmbx;
14669 if (i < 4)
14670 intmbx += 0x8;
14671 else
14672 intmbx += 0x4;
14673
14674 tnapi->consmbox = rcvmbx;
14675 tnapi->prodmbox = sndmbx;
14676
14677 if (i) {
14678 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14679 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14680 } else {
14681 tnapi->coal_now = HOSTCC_MODE_NOW;
14682 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14683 }
14684
14685 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14686 break;
14687
14688 /*
14689 * If we support MSIX, we'll be using RSS. If we're using
14690 * RSS, the first vector only handles link interrupts and the
14691 * remaining vectors handle rx and tx interrupts. Reuse the
14692 * mailbox values for the next iteration. The values we setup
14693 * above are still useful for the single vectored mode.
14694 */
14695 if (!i)
14696 continue;
14697
14698 rcvmbx += 0x8;
14699
14700 if (sndmbx & 0x4)
14701 sndmbx -= 0x4;
14702 else
14703 sndmbx += 0xc;
14704 }
14705
15f9850d
DM		 14706 tg3_init_coal(tp);
14707
c49a1561
MC		 14708 pci_set_drvdata(pdev, dev);
14709
1da177e4
LT		 14710 err = register_netdev(dev);
14711 if (err) {
14712 printk(KERN_ERR PFX "Cannot register net device, "
14713 "aborting.\n");
0d3031d9 14714 goto err_out_apeunmap;
1da177e4
LT		 14715 }
14716
df59c940 14717 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14718 dev->name,
14719 tp->board_part_number,
14720 tp->pci_chip_rev_id,
f9804ddb 14721 tg3_bus_string(tp, str),
e174961c 14722 dev->dev_addr);
1da177e4 14723
3f0e3ad7
MC		 14724 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14725 struct phy_device *phydev;
14726 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14727 printk(KERN_INFO
14728 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14729 tp->dev->name, phydev->drv->name,
14730 dev_name(&phydev->dev));
14731 } else
df59c940
MC		 14732 printk(KERN_INFO
14733 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14734 tp->dev->name, tg3_phy_string(tp),
14735 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14736 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14737 "10/100/1000Base-T")),
14738 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14739
14740 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14741 dev->name,
14742 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14743 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14744 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14745 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14746 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14747 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14748 dev->name, tp->dma_rwctrl,
284901a9 14749 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14750 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14751
14752 return 0;
14753
0d3031d9
MC		 14754err_out_apeunmap:
14755 if (tp->aperegs) {
14756 iounmap(tp->aperegs);
14757 tp->aperegs = NULL;
14758 }
14759
1da177e4 14760err_out_iounmap:
6892914f
MC		 14761 if (tp->regs) {
14762 iounmap(tp->regs);
22abe310 14763 tp->regs = NULL;
6892914f 14764 }
1da177e4
LT		 14765
14766err_out_free_dev:
14767 free_netdev(dev);
14768
14769err_out_free_res:
14770 pci_release_regions(pdev);
14771
14772err_out_disable_pdev:
14773 pci_disable_device(pdev);
14774 pci_set_drvdata(pdev, NULL);
14775 return err;
14776}
14777
14778static void __devexit tg3_remove_one(struct pci_dev *pdev)
14779{
14780 struct net_device *dev = pci_get_drvdata(pdev);
14781
14782 if (dev) {
14783 struct tg3 *tp = netdev_priv(dev);
14784
077f849d
JSR		 14785 if (tp->fw)
14786 release_firmware(tp->fw);
14787
7faa006f 14788 flush_scheduled_work();
158d7abd 14789
b02fd9e3
MC		 14790 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14791 tg3_phy_fini(tp);
158d7abd 14792 tg3_mdio_fini(tp);
b02fd9e3 14793 }
158d7abd 14794
1da177e4 14795 unregister_netdev(dev);
0d3031d9
MC		 14796 if (tp->aperegs) {
14797 iounmap(tp->aperegs);
14798 tp->aperegs = NULL;
14799 }
6892914f
MC		 14800 if (tp->regs) {
14801 iounmap(tp->regs);
22abe310 14802 tp->regs = NULL;
6892914f 14803 }
1da177e4
LT		 14804 free_netdev(dev);
14805 pci_release_regions(pdev);
14806 pci_disable_device(pdev);
14807 pci_set_drvdata(pdev, NULL);
14808 }
14809}
14810
14811static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14812{
14813 struct net_device *dev = pci_get_drvdata(pdev);
14814 struct tg3 *tp = netdev_priv(dev);
12dac075 14815 pci_power_t target_state;
1da177e4
LT		 14816 int err;
14817
3e0c95fd
MC		 14818 /* PCI register 4 needs to be saved whether netif_running() or not.
14819 * MSI address and data need to be saved if using MSI and
14820 * netif_running().
14821 */
14822 pci_save_state(pdev);
14823
1da177e4
LT		 14824 if (!netif_running(dev))
14825 return 0;
14826
7faa006f 14827 flush_scheduled_work();
b02fd9e3 14828 tg3_phy_stop(tp);
1da177e4
LT		 14829 tg3_netif_stop(tp);
14830
14831 del_timer_sync(&tp->timer);
14832
f47c11ee 14833 tg3_full_lock(tp, 1);
1da177e4 14834 tg3_disable_ints(tp);
f47c11ee 14835 tg3_full_unlock(tp);
1da177e4
LT		 14836
14837 netif_device_detach(dev);
14838
f47c11ee 14839 tg3_full_lock(tp, 0);
944d980e 14840 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14841 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14842 tg3_full_unlock(tp);
1da177e4 14843
12dac075
RW		 14844 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14845
14846 err = tg3_set_power_state(tp, target_state);
1da177e4 14847 if (err) {
b02fd9e3
MC		 14848 int err2;
14849
f47c11ee 14850 tg3_full_lock(tp, 0);
1da177e4 14851
6a9eba15 14852 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14853 err2 = tg3_restart_hw(tp, 1);
14854 if (err2)
b9ec6c1b 14855 goto out;
1da177e4
LT		 14856
14857 tp->timer.expires = jiffies + tp->timer_offset;
14858 add_timer(&tp->timer);
14859
14860 netif_device_attach(dev);
14861 tg3_netif_start(tp);
14862
b9ec6c1b 14863out:
f47c11ee 14864 tg3_full_unlock(tp);
b02fd9e3
MC		 14865
14866 if (!err2)
14867 tg3_phy_start(tp);
1da177e4
LT		 14868 }
14869
14870 return err;
14871}
14872
14873static int tg3_resume(struct pci_dev *pdev)
14874{
14875 struct net_device *dev = pci_get_drvdata(pdev);
14876 struct tg3 *tp = netdev_priv(dev);
14877 int err;
14878
3e0c95fd
MC		 14879 pci_restore_state(tp->pdev);
14880
1da177e4
LT		 14881 if (!netif_running(dev))
14882 return 0;
14883
bc1c7567 14884 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14885 if (err)
14886 return err;
14887
14888 netif_device_attach(dev);
14889
f47c11ee 14890 tg3_full_lock(tp, 0);
1da177e4 14891
6a9eba15 14892 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14893 err = tg3_restart_hw(tp, 1);
14894 if (err)
14895 goto out;
1da177e4
LT		 14896
14897 tp->timer.expires = jiffies + tp->timer_offset;
14898 add_timer(&tp->timer);
14899
1da177e4
LT		 14900 tg3_netif_start(tp);
14901
b9ec6c1b 14902out:
f47c11ee 14903 tg3_full_unlock(tp);
1da177e4 14904
b02fd9e3
MC		 14905 if (!err)
14906 tg3_phy_start(tp);
14907
b9ec6c1b 14908 return err;
1da177e4
LT		 14909}
14910
14911static struct pci_driver tg3_driver = {
14912 .name = DRV_MODULE_NAME,
14913 .id_table = tg3_pci_tbl,
14914 .probe = tg3_init_one,
14915 .remove = __devexit_p(tg3_remove_one),
14916 .suspend = tg3_suspend,
14917 .resume = tg3_resume
14918};
14919
14920static int __init tg3_init(void)
14921{
29917620 14922 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14923}
14924
14925static void __exit tg3_cleanup(void)
14926{
14927 pci_unregister_driver(&tg3_driver);
14928}
14929
14930module_init(tg3_init);
14931module_exit(tg3_cleanup);
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