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[net-next-2.6.git] / drivers / net / tg3.c
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1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
ba5b0bfa 7 * Copyright (C) 2005-2010 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
be7ce530
MC		 71#define DRV_MODULE_VERSION "3.108"
72#define DRV_MODULE_RELDATE "February 17, 2010"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
b0f75221
MC		 247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
13185217
HK		 253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
259 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
260 {}
1da177e4
LT		 261};
262
263MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
264
50da859d 265static const struct {
1da177e4
LT		 266 const char string[ETH_GSTRING_LEN];
267} ethtool_stats_keys[TG3_NUM_STATS] = {
268 { "rx_octets" },
269 { "rx_fragments" },
270 { "rx_ucast_packets" },
271 { "rx_mcast_packets" },
272 { "rx_bcast_packets" },
273 { "rx_fcs_errors" },
274 { "rx_align_errors" },
275 { "rx_xon_pause_rcvd" },
276 { "rx_xoff_pause_rcvd" },
277 { "rx_mac_ctrl_rcvd" },
278 { "rx_xoff_entered" },
279 { "rx_frame_too_long_errors" },
280 { "rx_jabbers" },
281 { "rx_undersize_packets" },
282 { "rx_in_length_errors" },
283 { "rx_out_length_errors" },
284 { "rx_64_or_less_octet_packets" },
285 { "rx_65_to_127_octet_packets" },
286 { "rx_128_to_255_octet_packets" },
287 { "rx_256_to_511_octet_packets" },
288 { "rx_512_to_1023_octet_packets" },
289 { "rx_1024_to_1522_octet_packets" },
290 { "rx_1523_to_2047_octet_packets" },
291 { "rx_2048_to_4095_octet_packets" },
292 { "rx_4096_to_8191_octet_packets" },
293 { "rx_8192_to_9022_octet_packets" },
294
295 { "tx_octets" },
296 { "tx_collisions" },
297
298 { "tx_xon_sent" },
299 { "tx_xoff_sent" },
300 { "tx_flow_control" },
301 { "tx_mac_errors" },
302 { "tx_single_collisions" },
303 { "tx_mult_collisions" },
304 { "tx_deferred" },
305 { "tx_excessive_collisions" },
306 { "tx_late_collisions" },
307 { "tx_collide_2times" },
308 { "tx_collide_3times" },
309 { "tx_collide_4times" },
310 { "tx_collide_5times" },
311 { "tx_collide_6times" },
312 { "tx_collide_7times" },
313 { "tx_collide_8times" },
314 { "tx_collide_9times" },
315 { "tx_collide_10times" },
316 { "tx_collide_11times" },
317 { "tx_collide_12times" },
318 { "tx_collide_13times" },
319 { "tx_collide_14times" },
320 { "tx_collide_15times" },
321 { "tx_ucast_packets" },
322 { "tx_mcast_packets" },
323 { "tx_bcast_packets" },
324 { "tx_carrier_sense_errors" },
325 { "tx_discards" },
326 { "tx_errors" },
327
328 { "dma_writeq_full" },
329 { "dma_write_prioq_full" },
330 { "rxbds_empty" },
331 { "rx_discards" },
332 { "rx_errors" },
333 { "rx_threshold_hit" },
334
335 { "dma_readq_full" },
336 { "dma_read_prioq_full" },
337 { "tx_comp_queue_full" },
338
339 { "ring_set_send_prod_index" },
340 { "ring_status_update" },
341 { "nic_irqs" },
342 { "nic_avoided_irqs" },
343 { "nic_tx_threshold_hit" }
344};
345
50da859d 346static const struct {
4cafd3f5
MC		 347 const char string[ETH_GSTRING_LEN];
348} ethtool_test_keys[TG3_NUM_TEST] = {
349 { "nvram test (online) " },
350 { "link test (online) " },
351 { "register test (offline)" },
352 { "memory test (offline)" },
353 { "loopback test (offline)" },
354 { "interrupt test (offline)" },
355};
356
b401e9e2
MC		 357static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
358{
359 writel(val, tp->regs + off);
360}
361
362static u32 tg3_read32(struct tg3 *tp, u32 off)
363{
6aa20a22 364 return (readl(tp->regs + off));
b401e9e2
MC		 365}
366
0d3031d9
MC		 367static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
368{
369 writel(val, tp->aperegs + off);
370}
371
372static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
373{
374 return (readl(tp->aperegs + off));
375}
376
1da177e4
LT		 377static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
378{
6892914f
MC		 379 unsigned long flags;
380
381 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 385}
386
387static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
388{
389 writel(val, tp->regs + off);
390 readl(tp->regs + off);
1da177e4
LT		 391}
392
6892914f 393static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 394{
6892914f
MC		 395 unsigned long flags;
396 u32 val;
397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 return val;
403}
404
405static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
406{
407 unsigned long flags;
408
409 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
410 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
411 TG3_64BIT_REG_LOW, val);
412 return;
413 }
66711e66 414 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 415 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
416 TG3_64BIT_REG_LOW, val);
417 return;
1da177e4 418 }
6892914f
MC		 419
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424
425 /* In indirect mode when disabling interrupts, we also need
426 * to clear the interrupt bit in the GRC local ctrl register.
427 */
428 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
429 (val == 0x1)) {
430 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
431 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
432 }
433}
434
435static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
436{
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
442 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
444 return val;
445}
446
b401e9e2
MC		 447/* usec_wait specifies the wait time in usec when writing to certain registers
448 * where it is unsafe to read back the register without some delay.
449 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
450 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
451 */
452static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 453{
b401e9e2
MC		 454 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
455 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
456 /* Non-posted methods */
457 tp->write32(tp, off, val);
458 else {
459 /* Posted method */
460 tg3_write32(tp, off, val);
461 if (usec_wait)
462 udelay(usec_wait);
463 tp->read32(tp, off);
464 }
465 /* Wait again after the read for the posted method to guarantee that
466 * the wait time is met.
467 */
468 if (usec_wait)
469 udelay(usec_wait);
1da177e4
LT		 470}
471
09ee929c
MC		 472static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
473{
474 tp->write32_mbox(tp, off, val);
6892914f
MC		 475 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
476 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477 tp->read32_mbox(tp, off);
09ee929c
MC		 478}
479
20094930 480static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 481{
482 void __iomem *mbox = tp->regs + off;
483 writel(val, mbox);
484 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
485 writel(val, mbox);
486 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
487 readl(mbox);
488}
489
b5d3772c
MC		 490static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
491{
492 return (readl(tp->regs + off + GRCMBOX_BASE));
493}
494
495static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
496{
497 writel(val, tp->regs + off + GRCMBOX_BASE);
498}
499
20094930 500#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 501#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 502#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
503#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 504#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 505
506#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 507#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
508#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 509#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 510
511static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
512{
6892914f
MC		 513 unsigned long flags;
514
b5d3772c
MC		 515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
516 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
517 return;
518
6892914f 519 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 520 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 } else {
527 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
528 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 529
bbadf503
MC		 530 /* Always leave this as zero. */
531 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
532 }
533 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 534}
535
1da177e4
LT		 536static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
537{
6892914f
MC		 538 unsigned long flags;
539
b5d3772c
MC		 540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
542 *val = 0;
543 return;
544 }
545
6892914f 546 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 547 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
548 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
549 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 550
bbadf503
MC		 551 /* Always leave this as zero. */
552 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 } else {
554 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
555 *val = tr32(TG3PCI_MEM_WIN_DATA);
556
557 /* Always leave this as zero. */
558 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
559 }
6892914f 560 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 561}
562
0d3031d9
MC		 563static void tg3_ape_lock_init(struct tg3 *tp)
564{
565 int i;
566
567 /* Make sure the driver hasn't any stale locks. */
568 for (i = 0; i < 8; i++)
569 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
570 APE_LOCK_GRANT_DRIVER);
571}
572
573static int tg3_ape_lock(struct tg3 *tp, int locknum)
574{
575 int i, off;
576 int ret = 0;
577 u32 status;
578
579 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
580 return 0;
581
582 switch (locknum) {
77b483f1 583 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 584 case TG3_APE_LOCK_MEM:
585 break;
586 default:
587 return -EINVAL;
588 }
589
590 off = 4 * locknum;
591
592 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
593
594 /* Wait for up to 1 millisecond to acquire lock. */
595 for (i = 0; i < 100; i++) {
596 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
597 if (status == APE_LOCK_GRANT_DRIVER)
598 break;
599 udelay(10);
600 }
601
602 if (status != APE_LOCK_GRANT_DRIVER) {
603 /* Revoke the lock request. */
604 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
605 APE_LOCK_GRANT_DRIVER);
606
607 ret = -EBUSY;
608 }
609
610 return ret;
611}
612
613static void tg3_ape_unlock(struct tg3 *tp, int locknum)
614{
615 int off;
616
617 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
618 return;
619
620 switch (locknum) {
77b483f1 621 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 622 case TG3_APE_LOCK_MEM:
623 break;
624 default:
625 return;
626 }
627
628 off = 4 * locknum;
629 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
630}
631
1da177e4
LT		 632static void tg3_disable_ints(struct tg3 *tp)
633{
89aeb3bc
MC		 634 int i;
635
1da177e4
LT		 636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 638 for (i = 0; i < tp->irq_max; i++)
639 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 640}
641
1da177e4
LT		 642static void tg3_enable_ints(struct tg3 *tp)
643{
89aeb3bc 644 int i;
89aeb3bc 645
bbe832c0
MC		 646 tp->irq_sync = 0;
647 wmb();
648
1da177e4
LT		 649 tw32(TG3PCI_MISC_HOST_CTRL,
650 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 651
f89f38b8 652 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 653 for (i = 0; i < tp->irq_cnt; i++) {
654 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 655 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 656 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 658
f89f38b8 659 tp->coal_now |= tnapi->coal_now;
89aeb3bc 660 }
f19af9c2
MC		 661
662 /* Force an initial interrupt */
663 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
664 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
665 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
666 else
f89f38b8
MC		 667 tw32(HOSTCC_MODE, tp->coal_now);
668
669 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 670}
671
17375d25 672static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 673{
17375d25 674 struct tg3 *tp = tnapi->tp;
898a56f8 675 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 676 unsigned int work_exists = 0;
677
678 /* check for phy events */
679 if (!(tp->tg3_flags &
680 (TG3_FLAG_USE_LINKCHG_REG |
681 TG3_FLAG_POLL_SERDES))) {
682 if (sblk->status & SD_STATUS_LINK_CHG)
683 work_exists = 1;
684 }
685 /* check for RX/TX work to do */
f3f3f27e 686 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 687 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 688 work_exists = 1;
689
690 return work_exists;
691}
692
17375d25 693/* tg3_int_reenable
04237ddd
MC		 694 * similar to tg3_enable_ints, but it accurately determines whether there
695 * is new work pending and can return without flushing the PIO write
6aa20a22 696 * which reenables interrupts
1da177e4 697 */
17375d25 698static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 699{
17375d25
MC		 700 struct tg3 *tp = tnapi->tp;
701
898a56f8 702 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 703 mmiowb();
704
fac9b83e
DM		 705 /* When doing tagged status, this work check is unnecessary.
706 * The last_tag we write above tells the chip which piece of
707 * work we've completed.
708 */
709 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 710 tg3_has_work(tnapi))
04237ddd 711 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 712 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 713}
714
fed97810
MC		 715static void tg3_napi_disable(struct tg3 *tp)
716{
717 int i;
718
719 for (i = tp->irq_cnt - 1; i >= 0; i--)
720 napi_disable(&tp->napi[i].napi);
721}
722
723static void tg3_napi_enable(struct tg3 *tp)
724{
725 int i;
726
727 for (i = 0; i < tp->irq_cnt; i++)
728 napi_enable(&tp->napi[i].napi);
729}
730
1da177e4
LT		 731static inline void tg3_netif_stop(struct tg3 *tp)
732{
bbe832c0 733 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 734 tg3_napi_disable(tp);
1da177e4
LT		 735 netif_tx_disable(tp->dev);
736}
737
738static inline void tg3_netif_start(struct tg3 *tp)
739{
fe5f5787
MC		 740 /* NOTE: unconditional netif_tx_wake_all_queues is only
741 * appropriate so long as all callers are assured to
742 * have free tx slots (such as after tg3_init_hw)
1da177e4 743 */
fe5f5787
MC		 744 netif_tx_wake_all_queues(tp->dev);
745
fed97810
MC		 746 tg3_napi_enable(tp);
747 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 748 tg3_enable_ints(tp);
1da177e4
LT		 749}
750
751static void tg3_switch_clocks(struct tg3 *tp)
752{
f6eb9b1f 753 u32 clock_ctrl;
1da177e4
LT		 754 u32 orig_clock_ctrl;
755
795d01c5
MC		 756 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
757 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 758 return;
759
f6eb9b1f
MC		 760 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
761
1da177e4
LT		 762 orig_clock_ctrl = clock_ctrl;
763 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
764 CLOCK_CTRL_CLKRUN_OENABLE |
765 0x1f);
766 tp->pci_clock_ctrl = clock_ctrl;
767
768 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
769 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 770 tw32_wait_f(TG3PCI_CLOCK_CTRL,
771 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 772 }
773 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 774 tw32_wait_f(TG3PCI_CLOCK_CTRL,
775 clock_ctrl |
776 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
777 40);
778 tw32_wait_f(TG3PCI_CLOCK_CTRL,
779 clock_ctrl | (CLOCK_CTRL_ALTCLK),
780 40);
1da177e4 781 }
b401e9e2 782 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 783}
784
785#define PHY_BUSY_LOOPS 5000
786
787static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
788{
789 u32 frame_val;
790 unsigned int loops;
791 int ret;
792
793 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
794 tw32_f(MAC_MI_MODE,
795 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
796 udelay(80);
797 }
798
799 *val = 0x0;
800
882e9793 801 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 802 MI_COM_PHY_ADDR_MASK);
803 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
804 MI_COM_REG_ADDR_MASK);
805 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 806
1da177e4
LT		 807 tw32_f(MAC_MI_COM, frame_val);
808
809 loops = PHY_BUSY_LOOPS;
810 while (loops != 0) {
811 udelay(10);
812 frame_val = tr32(MAC_MI_COM);
813
814 if ((frame_val & MI_COM_BUSY) == 0) {
815 udelay(5);
816 frame_val = tr32(MAC_MI_COM);
817 break;
818 }
819 loops -= 1;
820 }
821
822 ret = -EBUSY;
823 if (loops != 0) {
824 *val = frame_val & MI_COM_DATA_MASK;
825 ret = 0;
826 }
827
828 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
829 tw32_f(MAC_MI_MODE, tp->mi_mode);
830 udelay(80);
831 }
832
833 return ret;
834}
835
836static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
837{
838 u32 frame_val;
839 unsigned int loops;
840 int ret;
841
7f97a4bd 842 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 843 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
844 return 0;
845
1da177e4
LT		 846 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
847 tw32_f(MAC_MI_MODE,
848 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
849 udelay(80);
850 }
851
882e9793 852 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 853 MI_COM_PHY_ADDR_MASK);
854 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
855 MI_COM_REG_ADDR_MASK);
856 frame_val |= (val & MI_COM_DATA_MASK);
857 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 858
1da177e4
LT		 859 tw32_f(MAC_MI_COM, frame_val);
860
861 loops = PHY_BUSY_LOOPS;
862 while (loops != 0) {
863 udelay(10);
864 frame_val = tr32(MAC_MI_COM);
865 if ((frame_val & MI_COM_BUSY) == 0) {
866 udelay(5);
867 frame_val = tr32(MAC_MI_COM);
868 break;
869 }
870 loops -= 1;
871 }
872
873 ret = -EBUSY;
874 if (loops != 0)
875 ret = 0;
876
877 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
878 tw32_f(MAC_MI_MODE, tp->mi_mode);
879 udelay(80);
880 }
881
882 return ret;
883}
884
95e2869a
MC		 885static int tg3_bmcr_reset(struct tg3 *tp)
886{
887 u32 phy_control;
888 int limit, err;
889
890 /* OK, reset it, and poll the BMCR_RESET bit until it
891 * clears or we time out.
892 */
893 phy_control = BMCR_RESET;
894 err = tg3_writephy(tp, MII_BMCR, phy_control);
895 if (err != 0)
896 return -EBUSY;
897
898 limit = 5000;
899 while (limit--) {
900 err = tg3_readphy(tp, MII_BMCR, &phy_control);
901 if (err != 0)
902 return -EBUSY;
903
904 if ((phy_control & BMCR_RESET) == 0) {
905 udelay(40);
906 break;
907 }
908 udelay(10);
909 }
d4675b52 910 if (limit < 0)
95e2869a
MC		 911 return -EBUSY;
912
913 return 0;
914}
915
158d7abd
MC		 916static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
917{
3d16543d 918 struct tg3 *tp = bp->priv;
158d7abd
MC		 919 u32 val;
920
24bb4fb6 921 spin_lock_bh(&tp->lock);
158d7abd
MC		 922
923 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 924 val = -EIO;
925
926 spin_unlock_bh(&tp->lock);
158d7abd
MC		 927
928 return val;
929}
930
931static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
932{
3d16543d 933 struct tg3 *tp = bp->priv;
24bb4fb6 934 u32 ret = 0;
158d7abd 935
24bb4fb6 936 spin_lock_bh(&tp->lock);
158d7abd
MC		 937
938 if (tg3_writephy(tp, reg, val))
24bb4fb6 939 ret = -EIO;
158d7abd 940
24bb4fb6
MC		 941 spin_unlock_bh(&tp->lock);
942
943 return ret;
158d7abd
MC		 944}
945
946static int tg3_mdio_reset(struct mii_bus *bp)
947{
948 return 0;
949}
950
9c61d6bc 951static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 952{
953 u32 val;
fcb389df 954 struct phy_device *phydev;
a9daf367 955
3f0e3ad7 956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 957 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 958 case PHY_ID_BCM50610:
959 case PHY_ID_BCM50610M:
fcb389df
MC		 960 val = MAC_PHYCFG2_50610_LED_MODES;
961 break;
6a443a0f 962 case PHY_ID_BCMAC131:
fcb389df
MC		 963 val = MAC_PHYCFG2_AC131_LED_MODES;
964 break;
6a443a0f 965 case PHY_ID_RTL8211C:
fcb389df
MC		 966 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
967 break;
6a443a0f 968 case PHY_ID_RTL8201E:
fcb389df
MC		 969 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
970 break;
971 default:
a9daf367 972 return;
fcb389df
MC		 973 }
974
975 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
976 tw32(MAC_PHYCFG2, val);
977
978 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 979 val &= ~(MAC_PHYCFG1_RGMII_INT |
980 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
981 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 982 tw32(MAC_PHYCFG1, val);
983
984 return;
985 }
986
14417063 987 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
fcb389df
MC		 988 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
989 MAC_PHYCFG2_FMODE_MASK_MASK |
990 MAC_PHYCFG2_GMODE_MASK_MASK |
991 MAC_PHYCFG2_ACT_MASK_MASK |
992 MAC_PHYCFG2_QUAL_MASK_MASK |
993 MAC_PHYCFG2_INBAND_ENABLE;
994
995 tw32(MAC_PHYCFG2, val);
a9daf367 996
bb85fbb6
MC		 997 val = tr32(MAC_PHYCFG1);
998 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
999 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
14417063 1000 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1001 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1002 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1004 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1005 }
bb85fbb6
MC		 1006 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1007 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1008 tw32(MAC_PHYCFG1, val);
a9daf367 1009
a9daf367
MC		 1010 val = tr32(MAC_EXT_RGMII_MODE);
1011 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1012 MAC_RGMII_MODE_RX_QUALITY |
1013 MAC_RGMII_MODE_RX_ACTIVITY |
1014 MAC_RGMII_MODE_RX_ENG_DET |
1015 MAC_RGMII_MODE_TX_ENABLE |
1016 MAC_RGMII_MODE_TX_LOWPWR |
1017 MAC_RGMII_MODE_TX_RESET);
14417063 1018 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1019 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1020 val |= MAC_RGMII_MODE_RX_INT_B |
1021 MAC_RGMII_MODE_RX_QUALITY |
1022 MAC_RGMII_MODE_RX_ACTIVITY |
1023 MAC_RGMII_MODE_RX_ENG_DET;
1024 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1025 val |= MAC_RGMII_MODE_TX_ENABLE |
1026 MAC_RGMII_MODE_TX_LOWPWR |
1027 MAC_RGMII_MODE_TX_RESET;
1028 }
1029 tw32(MAC_EXT_RGMII_MODE, val);
1030}
1031
158d7abd
MC		 1032static void tg3_mdio_start(struct tg3 *tp)
1033{
158d7abd
MC		 1034 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1035 tw32_f(MAC_MI_MODE, tp->mi_mode);
1036 udelay(80);
a9daf367 1037
9ea4818d
MC		 1038 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1040 tg3_mdio_config_5785(tp);
1041}
1042
1043static int tg3_mdio_init(struct tg3 *tp)
1044{
1045 int i;
1046 u32 reg;
1047 struct phy_device *phydev;
1048
882e9793
MC		 1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1050 u32 funcnum, is_serdes;
1051
1052 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1053 if (funcnum)
1054 tp->phy_addr = 2;
1055 else
1056 tp->phy_addr = 1;
1057
d1ec96af
MC		 1058 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1059 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1060 else
1061 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1062 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1063 if (is_serdes)
1064 tp->phy_addr += 7;
1065 } else
3f0e3ad7 1066 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1067
158d7abd
MC		 1068 tg3_mdio_start(tp);
1069
1070 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072 return 0;
1073
298cf9be
LB		 1074 tp->mdio_bus = mdiobus_alloc();
1075 if (tp->mdio_bus == NULL)
1076 return -ENOMEM;
158d7abd 1077
298cf9be
LB		 1078 tp->mdio_bus->name = "tg3 mdio bus";
1079 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1080 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1081 tp->mdio_bus->priv = tp;
1082 tp->mdio_bus->parent = &tp->pdev->dev;
1083 tp->mdio_bus->read = &tg3_mdio_read;
1084 tp->mdio_bus->write = &tg3_mdio_write;
1085 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1086 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1087 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1088
1089 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1090 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1091
1092 /* The bus registration will look for all the PHYs on the mdio bus.
1093 * Unfortunately, it does not ensure the PHY is powered up before
1094 * accessing the PHY ID registers. A chip reset is the
1095 * quickest way to bring the device back to an operational state..
1096 */
1097 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098 tg3_bmcr_reset(tp);
1099
298cf9be 1100 i = mdiobus_register(tp->mdio_bus);
a9daf367 1101 if (i) {
158d7abd
MC		 1102 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1103 tp->dev->name, i);
9c61d6bc 1104 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1105 return i;
1106 }
158d7abd 1107
3f0e3ad7 1108 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1109
9c61d6bc
MC		 1110 if (!phydev || !phydev->drv) {
1111 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1112 mdiobus_unregister(tp->mdio_bus);
1113 mdiobus_free(tp->mdio_bus);
1114 return -ENODEV;
1115 }
1116
1117 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1118 case PHY_ID_BCM57780:
321d32a0 1119 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1121 break;
6a443a0f
MC		 1122 case PHY_ID_BCM50610:
1123 case PHY_ID_BCM50610M:
32e5a8d6 1124 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1125 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1126 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1127 PHY_BRCM_AUTO_PWRDWN_ENABLE;
14417063 1128 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
a9daf367
MC		 1129 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1134 /* fallthru */
6a443a0f 1135 case PHY_ID_RTL8211C:
fcb389df 1136 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1137 break;
6a443a0f
MC		 1138 case PHY_ID_RTL8201E:
1139 case PHY_ID_BCMAC131:
a9daf367 1140 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1141 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1142 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1143 break;
1144 }
1145
9c61d6bc
MC		 1146 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147
1148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149 tg3_mdio_config_5785(tp);
a9daf367
MC		 1150
1151 return 0;
158d7abd
MC		 1152}
1153
1154static void tg3_mdio_fini(struct tg3 *tp)
1155{
1156 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1158 mdiobus_unregister(tp->mdio_bus);
1159 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1160 }
1161}
1162
4ba526ce
MC		 1163/* tp->lock is held. */
1164static inline void tg3_generate_fw_event(struct tg3 *tp)
1165{
1166 u32 val;
1167
1168 val = tr32(GRC_RX_CPU_EVENT);
1169 val |= GRC_RX_CPU_DRIVER_EVENT;
1170 tw32_f(GRC_RX_CPU_EVENT, val);
1171
1172 tp->last_event_jiffies = jiffies;
1173}
1174
1175#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176
95e2869a
MC		 1177/* tp->lock is held. */
1178static void tg3_wait_for_event_ack(struct tg3 *tp)
1179{
1180 int i;
4ba526ce
MC		 1181 unsigned int delay_cnt;
1182 long time_remain;
1183
1184 /* If enough time has passed, no wait is necessary. */
1185 time_remain = (long)(tp->last_event_jiffies + 1 +
1186 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187 (long)jiffies;
1188 if (time_remain < 0)
1189 return;
1190
1191 /* Check if we can shorten the wait time. */
1192 delay_cnt = jiffies_to_usecs(time_remain);
1193 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1196
4ba526ce 1197 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1198 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1199 break;
4ba526ce 1200 udelay(8);
95e2869a
MC		 1201 }
1202}
1203
1204/* tp->lock is held. */
1205static void tg3_ump_link_report(struct tg3 *tp)
1206{
1207 u32 reg;
1208 u32 val;
1209
1210 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1212 return;
1213
1214 tg3_wait_for_event_ack(tp);
1215
1216 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1219
1220 val = 0;
1221 if (!tg3_readphy(tp, MII_BMCR, &reg))
1222 val = reg << 16;
1223 if (!tg3_readphy(tp, MII_BMSR, &reg))
1224 val |= (reg & 0xffff);
1225 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1226
1227 val = 0;
1228 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1229 val = reg << 16;
1230 if (!tg3_readphy(tp, MII_LPA, &reg))
1231 val |= (reg & 0xffff);
1232 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1233
1234 val = 0;
1235 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1236 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1237 val = reg << 16;
1238 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1239 val |= (reg & 0xffff);
1240 }
1241 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242
1243 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1244 val = reg << 16;
1245 else
1246 val = 0;
1247 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248
4ba526ce 1249 tg3_generate_fw_event(tp);
95e2869a
MC		 1250}
1251
1252static void tg3_link_report(struct tg3 *tp)
1253{
1254 if (!netif_carrier_ok(tp->dev)) {
1255 if (netif_msg_link(tp))
1256 printk(KERN_INFO PFX "%s: Link is down.\n",
1257 tp->dev->name);
1258 tg3_ump_link_report(tp);
1259 } else if (netif_msg_link(tp)) {
1260 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1261 tp->dev->name,
1262 (tp->link_config.active_speed == SPEED_1000 ?
1263 1000 :
1264 (tp->link_config.active_speed == SPEED_100 ?
1265 100 : 10)),
1266 (tp->link_config.active_duplex == DUPLEX_FULL ?
1267 "full" : "half"));
1268
1269 printk(KERN_INFO PFX
1270 "%s: Flow control is %s for TX and %s for RX.\n",
1271 tp->dev->name,
e18ce346 1272 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1273 "on" : "off",
e18ce346 1274 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1275 "on" : "off");
1276 tg3_ump_link_report(tp);
1277 }
1278}
1279
1280static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1281{
1282 u16 miireg;
1283
e18ce346 1284 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1285 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1286 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1287 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1288 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1289 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1290 else
1291 miireg = 0;
1292
1293 return miireg;
1294}
1295
1296static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1297{
1298 u16 miireg;
1299
e18ce346 1300 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1301 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1302 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1303 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1304 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1305 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1306 else
1307 miireg = 0;
1308
1309 return miireg;
1310}
1311
95e2869a
MC		 1312static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1313{
1314 u8 cap = 0;
1315
1316 if (lcladv & ADVERTISE_1000XPAUSE) {
1317 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1318 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1319 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1320 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1321 cap = FLOW_CTRL_RX;
95e2869a
MC		 1322 } else {
1323 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1324 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1325 }
1326 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1327 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1328 cap = FLOW_CTRL_TX;
95e2869a
MC		 1329 }
1330
1331 return cap;
1332}
1333
f51f3562 1334static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1335{
b02fd9e3 1336 u8 autoneg;
f51f3562 1337 u8 flowctrl = 0;
95e2869a
MC		 1338 u32 old_rx_mode = tp->rx_mode;
1339 u32 old_tx_mode = tp->tx_mode;
1340
b02fd9e3 1341 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1342 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1343 else
1344 autoneg = tp->link_config.autoneg;
1345
1346 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1347 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1349 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1350 else
bc02ff95 1351 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1352 } else
1353 flowctrl = tp->link_config.flowctrl;
95e2869a 1354
f51f3562 1355 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1356
e18ce346 1357 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1358 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1359 else
1360 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1361
f51f3562 1362 if (old_rx_mode != tp->rx_mode)
95e2869a 1363 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1364
e18ce346 1365 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1366 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1367 else
1368 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1369
f51f3562 1370 if (old_tx_mode != tp->tx_mode)
95e2869a 1371 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1372}
1373
b02fd9e3
MC		 1374static void tg3_adjust_link(struct net_device *dev)
1375{
1376 u8 oldflowctrl, linkmesg = 0;
1377 u32 mac_mode, lcl_adv, rmt_adv;
1378 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1379 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1380
24bb4fb6 1381 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1382
1383 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1384 MAC_MODE_HALF_DUPLEX);
1385
1386 oldflowctrl = tp->link_config.active_flowctrl;
1387
1388 if (phydev->link) {
1389 lcl_adv = 0;
1390 rmt_adv = 0;
1391
1392 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1393 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1394 else if (phydev->speed == SPEED_1000 ||
1395 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1396 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1397 else
1398 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1399
1400 if (phydev->duplex == DUPLEX_HALF)
1401 mac_mode |= MAC_MODE_HALF_DUPLEX;
1402 else {
1403 lcl_adv = tg3_advert_flowctrl_1000T(
1404 tp->link_config.flowctrl);
1405
1406 if (phydev->pause)
1407 rmt_adv = LPA_PAUSE_CAP;
1408 if (phydev->asym_pause)
1409 rmt_adv |= LPA_PAUSE_ASYM;
1410 }
1411
1412 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1413 } else
1414 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1415
1416 if (mac_mode != tp->mac_mode) {
1417 tp->mac_mode = mac_mode;
1418 tw32_f(MAC_MODE, tp->mac_mode);
1419 udelay(40);
1420 }
1421
fcb389df
MC		 1422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1423 if (phydev->speed == SPEED_10)
1424 tw32(MAC_MI_STAT,
1425 MAC_MI_STAT_10MBPS_MODE |
1426 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1427 else
1428 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1429 }
1430
b02fd9e3
MC		 1431 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1432 tw32(MAC_TX_LENGTHS,
1433 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434 (6 << TX_LENGTHS_IPG_SHIFT) |
1435 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436 else
1437 tw32(MAC_TX_LENGTHS,
1438 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1439 (6 << TX_LENGTHS_IPG_SHIFT) |
1440 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1441
1442 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1443 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1444 phydev->speed != tp->link_config.active_speed ||
1445 phydev->duplex != tp->link_config.active_duplex ||
1446 oldflowctrl != tp->link_config.active_flowctrl)
1447 linkmesg = 1;
1448
1449 tp->link_config.active_speed = phydev->speed;
1450 tp->link_config.active_duplex = phydev->duplex;
1451
24bb4fb6 1452 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1453
1454 if (linkmesg)
1455 tg3_link_report(tp);
1456}
1457
1458static int tg3_phy_init(struct tg3 *tp)
1459{
1460 struct phy_device *phydev;
1461
1462 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1463 return 0;
1464
1465 /* Bring the PHY back to a known state. */
1466 tg3_bmcr_reset(tp);
1467
3f0e3ad7 1468 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1469
1470 /* Attach the MAC to the PHY. */
fb28ad35 1471 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1472 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1473 if (IS_ERR(phydev)) {
1474 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1475 return PTR_ERR(phydev);
1476 }
1477
b02fd9e3 1478 /* Mask with MAC supported features. */
9c61d6bc
MC		 1479 switch (phydev->interface) {
1480 case PHY_INTERFACE_MODE_GMII:
1481 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1482 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1483 phydev->supported &= (PHY_GBIT_FEATURES |
1484 SUPPORTED_Pause |
1485 SUPPORTED_Asym_Pause);
1486 break;
1487 }
1488 /* fallthru */
9c61d6bc
MC		 1489 case PHY_INTERFACE_MODE_MII:
1490 phydev->supported &= (PHY_BASIC_FEATURES |
1491 SUPPORTED_Pause |
1492 SUPPORTED_Asym_Pause);
1493 break;
1494 default:
3f0e3ad7 1495 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1496 return -EINVAL;
1497 }
1498
1499 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1500
1501 phydev->advertising = phydev->supported;
1502
b02fd9e3
MC		 1503 return 0;
1504}
1505
1506static void tg3_phy_start(struct tg3 *tp)
1507{
1508 struct phy_device *phydev;
1509
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511 return;
1512
3f0e3ad7 1513 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1514
1515 if (tp->link_config.phy_is_low_power) {
1516 tp->link_config.phy_is_low_power = 0;
1517 phydev->speed = tp->link_config.orig_speed;
1518 phydev->duplex = tp->link_config.orig_duplex;
1519 phydev->autoneg = tp->link_config.orig_autoneg;
1520 phydev->advertising = tp->link_config.orig_advertising;
1521 }
1522
1523 phy_start(phydev);
1524
1525 phy_start_aneg(phydev);
1526}
1527
1528static void tg3_phy_stop(struct tg3 *tp)
1529{
1530 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1531 return;
1532
3f0e3ad7 1533 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1534}
1535
1536static void tg3_phy_fini(struct tg3 *tp)
1537{
1538 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1539 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1540 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1541 }
1542}
1543
b2a5c19c
MC		 1544static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1545{
1546 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1547 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1548}
1549
7f97a4bd
MC		 1550static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1551{
1552 u32 phytest;
1553
1554 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1555 u32 phy;
1556
1557 tg3_writephy(tp, MII_TG3_FET_TEST,
1558 phytest | MII_TG3_FET_SHADOW_EN);
1559 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560 if (enable)
1561 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562 else
1563 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565 }
1566 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1567 }
1568}
1569
6833c043
MC		 1570static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1571{
1572 u32 reg;
1573
ecf1410b
MC		 1574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1576 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1577 return;
1578
7f97a4bd
MC		 1579 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1580 tg3_phy_fet_toggle_apd(tp, enable);
1581 return;
1582 }
1583
6833c043
MC		 1584 reg = MII_TG3_MISC_SHDW_WREN |
1585 MII_TG3_MISC_SHDW_SCR5_SEL |
1586 MII_TG3_MISC_SHDW_SCR5_LPED |
1587 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588 MII_TG3_MISC_SHDW_SCR5_SDTL |
1589 MII_TG3_MISC_SHDW_SCR5_C125OE;
1590 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596 reg = MII_TG3_MISC_SHDW_WREN |
1597 MII_TG3_MISC_SHDW_APD_SEL |
1598 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599 if (enable)
1600 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603}
1604
9ef8ca99
MC		 1605static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606{
1607 u32 phy;
1608
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1611 return;
1612
7f97a4bd 1613 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1614 u32 ephy;
1615
535ef6e1
MC		 1616 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619 tg3_writephy(tp, MII_TG3_FET_TEST,
1620 ephy | MII_TG3_FET_SHADOW_EN);
1621 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1622 if (enable)
535ef6e1 1623 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1624 else
535ef6e1
MC		 1625 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626 tg3_writephy(tp, reg, phy);
9ef8ca99 1627 }
535ef6e1 1628 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1629 }
1630 } else {
1631 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632 MII_TG3_AUXCTL_SHDWSEL_MISC;
1633 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635 if (enable)
1636 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637 else
1638 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639 phy |= MII_TG3_AUXCTL_MISC_WREN;
1640 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641 }
1642 }
1643}
1644
1da177e4
LT		 1645static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646{
1647 u32 val;
1648
1649 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1650 return;
1651
1652 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655 (val | (1 << 15) | (1 << 4)));
1656}
1657
b2a5c19c
MC		 1658static void tg3_phy_apply_otp(struct tg3 *tp)
1659{
1660 u32 otp, phy;
1661
1662 if (!tp->phy_otp)
1663 return;
1664
1665 otp = tp->phy_otp;
1666
1667 /* Enable SM_DSP clock and tx 6dB coding. */
1668 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670 MII_TG3_AUXCTL_ACTL_TX_6DB;
1671 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695 /* Turn off SM_DSP clock. */
1696 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697 MII_TG3_AUXCTL_ACTL_TX_6DB;
1698 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699}
1700
1da177e4
LT		 1701static int tg3_wait_macro_done(struct tg3 *tp)
1702{
1703 int limit = 100;
1704
1705 while (limit--) {
1706 u32 tmp32;
1707
1708 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1709 if ((tmp32 & 0x1000) == 0)
1710 break;
1711 }
1712 }
d4675b52 1713 if (limit < 0)
1da177e4
LT		 1714 return -EBUSY;
1715
1716 return 0;
1717}
1718
1719static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720{
1721 static const u32 test_pat[4][6] = {
1722 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726 };
1727 int chan;
1728
1729 for (chan = 0; chan < 4; chan++) {
1730 int i;
1731
1732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733 (chan * 0x2000) | 0x0200);
1734 tg3_writephy(tp, 0x16, 0x0002);
1735
1736 for (i = 0; i < 6; i++)
1737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738 test_pat[chan][i]);
1739
1740 tg3_writephy(tp, 0x16, 0x0202);
1741 if (tg3_wait_macro_done(tp)) {
1742 *resetp = 1;
1743 return -EBUSY;
1744 }
1745
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, 0x16, 0x0082);
1749 if (tg3_wait_macro_done(tp)) {
1750 *resetp = 1;
1751 return -EBUSY;
1752 }
1753
1754 tg3_writephy(tp, 0x16, 0x0802);
1755 if (tg3_wait_macro_done(tp)) {
1756 *resetp = 1;
1757 return -EBUSY;
1758 }
1759
1760 for (i = 0; i < 6; i += 2) {
1761 u32 low, high;
1762
1763 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765 tg3_wait_macro_done(tp)) {
1766 *resetp = 1;
1767 return -EBUSY;
1768 }
1769 low &= 0x7fff;
1770 high &= 0x000f;
1771 if (low != test_pat[chan][i] ||
1772 high != test_pat[chan][i+1]) {
1773 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777 return -EBUSY;
1778 }
1779 }
1780 }
1781
1782 return 0;
1783}
1784
1785static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786{
1787 int chan;
1788
1789 for (chan = 0; chan < 4; chan++) {
1790 int i;
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793 (chan * 0x2000) | 0x0200);
1794 tg3_writephy(tp, 0x16, 0x0002);
1795 for (i = 0; i < 6; i++)
1796 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797 tg3_writephy(tp, 0x16, 0x0202);
1798 if (tg3_wait_macro_done(tp))
1799 return -EBUSY;
1800 }
1801
1802 return 0;
1803}
1804
1805static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806{
1807 u32 reg32, phy9_orig;
1808 int retries, do_phy_reset, err;
1809
1810 retries = 10;
1811 do_phy_reset = 1;
1812 do {
1813 if (do_phy_reset) {
1814 err = tg3_bmcr_reset(tp);
1815 if (err)
1816 return err;
1817 do_phy_reset = 0;
1818 }
1819
1820 /* Disable transmitter and interrupt. */
1821 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822 continue;
1823
1824 reg32 |= 0x3000;
1825 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827 /* Set full-duplex, 1000 mbps. */
1828 tg3_writephy(tp, MII_BMCR,
1829 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831 /* Set to master mode. */
1832 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833 continue;
1834
1835 tg3_writephy(tp, MII_TG3_CTRL,
1836 (MII_TG3_CTRL_AS_MASTER |
1837 MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839 /* Enable SM_DSP_CLOCK and 6dB. */
1840 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842 /* Block the PHY control access. */
1843 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1845
1846 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1847 if (!err)
1848 break;
1849 } while (--retries);
1850
1851 err = tg3_phy_reset_chanpat(tp);
1852 if (err)
1853 return err;
1854
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1857
1858 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1859 tg3_writephy(tp, 0x16, 0x0000);
1860
1861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1863 /* Set Extended packet length bit for jumbo frames */
1864 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1865 }
1866 else {
1867 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1868 }
1869
1870 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1871
1872 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1873 reg32 &= ~0x3000;
1874 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875 } else if (!err)
1876 err = -EBUSY;
1877
1878 return err;
1879}
1880
1881/* This will reset the tigon3 PHY if there is no valid
1882 * link unless the FORCE argument is non-zero.
1883 */
1884static int tg3_phy_reset(struct tg3 *tp)
1885{
b2a5c19c 1886 u32 cpmuctrl;
1da177e4
LT		 1887 u32 phy_status;
1888 int err;
1889
60189ddf
MC		 1890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1891 u32 val;
1892
1893 val = tr32(GRC_MISC_CFG);
1894 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1895 udelay(40);
1896 }
1da177e4
LT		 1897 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1898 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1899 if (err != 0)
1900 return -EBUSY;
1901
c8e1e82b
MC		 1902 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1903 netif_carrier_off(tp->dev);
1904 tg3_link_report(tp);
1905 }
1906
1da177e4
LT		 1907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1910 err = tg3_phy_reset_5703_4_5(tp);
1911 if (err)
1912 return err;
1913 goto out;
1914 }
1915
b2a5c19c
MC		 1916 cpmuctrl = 0;
1917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1918 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1919 cpmuctrl = tr32(TG3_CPMU_CTRL);
1920 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1921 tw32(TG3_CPMU_CTRL,
1922 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1923 }
1924
1da177e4
LT		 1925 err = tg3_bmcr_reset(tp);
1926 if (err)
1927 return err;
1928
b2a5c19c
MC		 1929 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1930 u32 phy;
1931
1932 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1933 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1934
1935 tw32(TG3_CPMU_CTRL, cpmuctrl);
1936 }
1937
bcb37f6c
MC		 1938 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1939 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1940 u32 val;
1941
1942 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1943 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1944 CPMU_LSPD_1000MB_MACCLK_12_5) {
1945 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1946 udelay(40);
1947 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1948 }
1949 }
1950
ecf1410b
MC		 1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1952 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1953 return 0;
1954
b2a5c19c
MC		 1955 tg3_phy_apply_otp(tp);
1956
6833c043
MC		 1957 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1958 tg3_phy_toggle_apd(tp, true);
1959 else
1960 tg3_phy_toggle_apd(tp, false);
1961
1da177e4
LT		 1962out:
1963 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1965 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1966 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1967 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1968 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970 }
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1972 tg3_writephy(tp, 0x1c, 0x8d68);
1973 tg3_writephy(tp, 0x1c, 0x8d68);
1974 }
1975 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1977 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984 }
c424cb24
MC		 1985 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1986 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1987 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1988 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1989 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1990 tg3_writephy(tp, MII_TG3_TEST1,
1991 MII_TG3_TEST1_TRIM_EN | 0x4);
1992 } else
1993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1995 }
1da177e4
LT		 1996 /* Set Extended packet length bit (bit 14) on all chips that */
1997 /* support jumbo frames */
79eb6904 1998 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 1999 /* Cannot do read-modify-write on 5401 */
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 2001 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2002 u32 phy_reg;
2003
2004 /* Set bit 14 with read-modify-write to preserve other bits */
2005 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2006 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2007 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2008 }
2009
2010 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2011 * jumbo frames transmission.
2012 */
8f666b07 2013 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2014 u32 phy_reg;
2015
2016 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2017 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2018 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2019 }
2020
715116a1 2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2022 /* adjust output voltage */
535ef6e1 2023 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2024 }
2025
9ef8ca99 2026 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2027 tg3_phy_set_wirespeed(tp);
2028 return 0;
2029}
2030
2031static void tg3_frob_aux_power(struct tg3 *tp)
2032{
2033 struct tg3 *tp_peer = tp;
2034
334355aa
MC		 2035 /* The GPIOs do something completely different on 57765. */
2036 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2038 return;
2039
f6eb9b1f
MC		 2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2043 struct net_device *dev_peer;
2044
2045 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2046 /* remove_one() may have been run on the peer. */
8c2dc7e1 2047 if (!dev_peer)
bc1c7567
MC		 2048 tp_peer = tp;
2049 else
2050 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2051 }
2052
1da177e4 2053 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2054 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2055 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2056 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE0 |
2061 GRC_LCLCTRL_GPIO_OE1 |
2062 GRC_LCLCTRL_GPIO_OE2 |
2063 GRC_LCLCTRL_GPIO_OUTPUT0 |
2064 GRC_LCLCTRL_GPIO_OUTPUT1),
2065 100);
8d519ab2
MC		 2066 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2067 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2068 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2069 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2070 GRC_LCLCTRL_GPIO_OE1 |
2071 GRC_LCLCTRL_GPIO_OE2 |
2072 GRC_LCLCTRL_GPIO_OUTPUT0 |
2073 GRC_LCLCTRL_GPIO_OUTPUT1 |
2074 tp->grc_local_ctrl;
2075 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2076
2077 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2078 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2079
2080 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2081 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2082 } else {
2083 u32 no_gpio2;
dc56b7d4 2084 u32 grc_local_ctrl = 0;
1da177e4
LT		 2085
2086 if (tp_peer != tp &&
2087 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2088 return;
2089
dc56b7d4
MC		 2090 /* Workaround to prevent overdrawing Amps. */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2092 ASIC_REV_5714) {
2093 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095 grc_local_ctrl, 100);
dc56b7d4
MC		 2096 }
2097
1da177e4
LT		 2098 /* On 5753 and variants, GPIO2 cannot be used. */
2099 no_gpio2 = tp->nic_sram_data_cfg &
2100 NIC_SRAM_DATA_CFG_NO_GPIO2;
2101
dc56b7d4 2102 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2103 GRC_LCLCTRL_GPIO_OE1 |
2104 GRC_LCLCTRL_GPIO_OE2 |
2105 GRC_LCLCTRL_GPIO_OUTPUT1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT2;
2107 if (no_gpio2) {
2108 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2109 GRC_LCLCTRL_GPIO_OUTPUT2);
2110 }
b401e9e2
MC		 2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 grc_local_ctrl, 100);
1da177e4
LT		 2113
2114 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2115
b401e9e2
MC		 2116 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2117 grc_local_ctrl, 100);
1da177e4
LT		 2118
2119 if (!no_gpio2) {
2120 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 grc_local_ctrl, 100);
1da177e4
LT		 2123 }
2124 }
2125 } else {
2126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2127 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2128 if (tp_peer != tp &&
2129 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2130 return;
2131
b401e9e2
MC		 2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 (GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2135
b401e9e2
MC		 2136 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2137 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2138
b401e9e2
MC		 2139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140 (GRC_LCLCTRL_GPIO_OE1 |
2141 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2142 }
2143 }
2144}
2145
e8f3f6ca
MC		 2146static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2147{
2148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2149 return 1;
79eb6904 2150 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 2151 if (speed != SPEED_10)
2152 return 1;
2153 } else if (speed == SPEED_10)
2154 return 1;
2155
2156 return 0;
2157}
2158
1da177e4
LT		 2159static int tg3_setup_phy(struct tg3 *, int);
2160
2161#define RESET_KIND_SHUTDOWN 0
2162#define RESET_KIND_INIT 1
2163#define RESET_KIND_SUSPEND 2
2164
2165static void tg3_write_sig_post_reset(struct tg3 *, int);
2166static int tg3_halt_cpu(struct tg3 *, u32);
2167
0a459aac 2168static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2169{
ce057f01
MC		 2170 u32 val;
2171
5129724a
MC		 2172 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2174 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2175 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2176
2177 sg_dig_ctrl |=
2178 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2179 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2180 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2181 }
3f7045c1 2182 return;
5129724a 2183 }
3f7045c1 2184
60189ddf 2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2186 tg3_bmcr_reset(tp);
2187 val = tr32(GRC_MISC_CFG);
2188 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2189 udelay(40);
2190 return;
0e5f784c
MC		 2191 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2192 u32 phytest;
2193 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2194 u32 phy;
2195
2196 tg3_writephy(tp, MII_ADVERTISE, 0);
2197 tg3_writephy(tp, MII_BMCR,
2198 BMCR_ANENABLE | BMCR_ANRESTART);
2199
2200 tg3_writephy(tp, MII_TG3_FET_TEST,
2201 phytest | MII_TG3_FET_SHADOW_EN);
2202 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2203 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2204 tg3_writephy(tp,
2205 MII_TG3_FET_SHDW_AUXMODE4,
2206 phy);
2207 }
2208 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2209 }
2210 return;
0a459aac 2211 } else if (do_low_power) {
715116a1
MC		 2212 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2213 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2214
2215 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2216 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2217 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2218 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2219 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2220 }
3f7045c1 2221
15c3b696
MC		 2222 /* The PHY should not be powered down on some chips because
2223 * of bugs.
2224 */
2225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2227 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2228 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2229 return;
ce057f01 2230
bcb37f6c
MC		 2231 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2232 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2233 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2234 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2235 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2236 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2237 }
2238
15c3b696
MC		 2239 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2240}
2241
ffbcfed4
MC		 2242/* tp->lock is held. */
2243static int tg3_nvram_lock(struct tg3 *tp)
2244{
2245 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2246 int i;
2247
2248 if (tp->nvram_lock_cnt == 0) {
2249 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2250 for (i = 0; i < 8000; i++) {
2251 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2252 break;
2253 udelay(20);
2254 }
2255 if (i == 8000) {
2256 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2257 return -ENODEV;
2258 }
2259 }
2260 tp->nvram_lock_cnt++;
2261 }
2262 return 0;
2263}
2264
2265/* tp->lock is held. */
2266static void tg3_nvram_unlock(struct tg3 *tp)
2267{
2268 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2269 if (tp->nvram_lock_cnt > 0)
2270 tp->nvram_lock_cnt--;
2271 if (tp->nvram_lock_cnt == 0)
2272 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2273 }
2274}
2275
2276/* tp->lock is held. */
2277static void tg3_enable_nvram_access(struct tg3 *tp)
2278{
2279 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2280 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2281 u32 nvaccess = tr32(NVRAM_ACCESS);
2282
2283 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2284 }
2285}
2286
2287/* tp->lock is held. */
2288static void tg3_disable_nvram_access(struct tg3 *tp)
2289{
2290 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2291 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2292 u32 nvaccess = tr32(NVRAM_ACCESS);
2293
2294 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2295 }
2296}
2297
2298static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2299 u32 offset, u32 *val)
2300{
2301 u32 tmp;
2302 int i;
2303
2304 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2305 return -EINVAL;
2306
2307 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2308 EEPROM_ADDR_DEVID_MASK |
2309 EEPROM_ADDR_READ);
2310 tw32(GRC_EEPROM_ADDR,
2311 tmp |
2312 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2313 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2314 EEPROM_ADDR_ADDR_MASK) |
2315 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2316
2317 for (i = 0; i < 1000; i++) {
2318 tmp = tr32(GRC_EEPROM_ADDR);
2319
2320 if (tmp & EEPROM_ADDR_COMPLETE)
2321 break;
2322 msleep(1);
2323 }
2324 if (!(tmp & EEPROM_ADDR_COMPLETE))
2325 return -EBUSY;
2326
62cedd11
MC		 2327 tmp = tr32(GRC_EEPROM_DATA);
2328
2329 /*
2330 * The data will always be opposite the native endian
2331 * format. Perform a blind byteswap to compensate.
2332 */
2333 *val = swab32(tmp);
2334
ffbcfed4
MC		 2335 return 0;
2336}
2337
2338#define NVRAM_CMD_TIMEOUT 10000
2339
2340static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2341{
2342 int i;
2343
2344 tw32(NVRAM_CMD, nvram_cmd);
2345 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2346 udelay(10);
2347 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2348 udelay(10);
2349 break;
2350 }
2351 }
2352
2353 if (i == NVRAM_CMD_TIMEOUT)
2354 return -EBUSY;
2355
2356 return 0;
2357}
2358
2359static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2360{
2361 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365 (tp->nvram_jedecnum == JEDEC_ATMEL))
2366
2367 addr = ((addr / tp->nvram_pagesize) <<
2368 ATMEL_AT45DB0X1B_PAGE_POS) +
2369 (addr % tp->nvram_pagesize);
2370
2371 return addr;
2372}
2373
2374static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2375{
2376 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2377 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2378 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2379 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2380 (tp->nvram_jedecnum == JEDEC_ATMEL))
2381
2382 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2383 tp->nvram_pagesize) +
2384 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2385
2386 return addr;
2387}
2388
e4f34110
MC		 2389/* NOTE: Data read in from NVRAM is byteswapped according to
2390 * the byteswapping settings for all other register accesses.
2391 * tg3 devices are BE devices, so on a BE machine, the data
2392 * returned will be exactly as it is seen in NVRAM. On a LE
2393 * machine, the 32-bit value will be byteswapped.
2394 */
ffbcfed4
MC		 2395static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2396{
2397 int ret;
2398
2399 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2400 return tg3_nvram_read_using_eeprom(tp, offset, val);
2401
2402 offset = tg3_nvram_phys_addr(tp, offset);
2403
2404 if (offset > NVRAM_ADDR_MSK)
2405 return -EINVAL;
2406
2407 ret = tg3_nvram_lock(tp);
2408 if (ret)
2409 return ret;
2410
2411 tg3_enable_nvram_access(tp);
2412
2413 tw32(NVRAM_ADDR, offset);
2414 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2415 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2416
2417 if (ret == 0)
e4f34110 2418 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2419
2420 tg3_disable_nvram_access(tp);
2421
2422 tg3_nvram_unlock(tp);
2423
2424 return ret;
2425}
2426
a9dc529d
MC		 2427/* Ensures NVRAM data is in bytestream format. */
2428static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2429{
2430 u32 v;
a9dc529d 2431 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2432 if (!res)
a9dc529d 2433 *val = cpu_to_be32(v);
ffbcfed4
MC		 2434 return res;
2435}
2436
3f007891
MC		 2437/* tp->lock is held. */
2438static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2439{
2440 u32 addr_high, addr_low;
2441 int i;
2442
2443 addr_high = ((tp->dev->dev_addr[0] << 8) |
2444 tp->dev->dev_addr[1]);
2445 addr_low = ((tp->dev->dev_addr[2] << 24) |
2446 (tp->dev->dev_addr[3] << 16) |
2447 (tp->dev->dev_addr[4] << 8) |
2448 (tp->dev->dev_addr[5] << 0));
2449 for (i = 0; i < 4; i++) {
2450 if (i == 1 && skip_mac_1)
2451 continue;
2452 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2453 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2454 }
2455
2456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458 for (i = 0; i < 12; i++) {
2459 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2460 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2461 }
2462 }
2463
2464 addr_high = (tp->dev->dev_addr[0] +
2465 tp->dev->dev_addr[1] +
2466 tp->dev->dev_addr[2] +
2467 tp->dev->dev_addr[3] +
2468 tp->dev->dev_addr[4] +
2469 tp->dev->dev_addr[5]) &
2470 TX_BACKOFF_SEED_MASK;
2471 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2472}
2473
bc1c7567 2474static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2475{
2476 u32 misc_host_ctrl;
0a459aac 2477 bool device_should_wake, do_low_power;
1da177e4
LT		 2478
2479 /* Make sure register accesses (indirect or otherwise)
2480 * will function correctly.
2481 */
2482 pci_write_config_dword(tp->pdev,
2483 TG3PCI_MISC_HOST_CTRL,
2484 tp->misc_host_ctrl);
2485
1da177e4 2486 switch (state) {
bc1c7567 2487 case PCI_D0:
12dac075
RW		 2488 pci_enable_wake(tp->pdev, state, false);
2489 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2490
9d26e213
MC		 2491 /* Switch out of Vaux if it is a NIC */
2492 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2493 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2494
2495 return 0;
2496
bc1c7567 2497 case PCI_D1:
bc1c7567 2498 case PCI_D2:
bc1c7567 2499 case PCI_D3hot:
1da177e4
LT		 2500 break;
2501
2502 default:
12dac075
RW		 2503 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2504 tp->dev->name, state);
1da177e4 2505 return -EINVAL;
855e1111 2506 }
5e7dfd0f
MC		 2507
2508 /* Restore the CLKREQ setting. */
2509 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2510 u16 lnkctl;
2511
2512 pci_read_config_word(tp->pdev,
2513 tp->pcie_cap + PCI_EXP_LNKCTL,
2514 &lnkctl);
2515 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2516 pci_write_config_word(tp->pdev,
2517 tp->pcie_cap + PCI_EXP_LNKCTL,
2518 lnkctl);
2519 }
2520
1da177e4
LT		 2521 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2522 tw32(TG3PCI_MISC_HOST_CTRL,
2523 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2524
05ac4cb7
MC		 2525 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2526 device_may_wakeup(&tp->pdev->dev) &&
2527 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2528
dd477003 2529 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2530 do_low_power = false;
b02fd9e3
MC		 2531 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2532 !tp->link_config.phy_is_low_power) {
2533 struct phy_device *phydev;
0a459aac 2534 u32 phyid, advertising;
b02fd9e3 2535
3f0e3ad7 2536 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2537
2538 tp->link_config.phy_is_low_power = 1;
2539
2540 tp->link_config.orig_speed = phydev->speed;
2541 tp->link_config.orig_duplex = phydev->duplex;
2542 tp->link_config.orig_autoneg = phydev->autoneg;
2543 tp->link_config.orig_advertising = phydev->advertising;
2544
2545 advertising = ADVERTISED_TP |
2546 ADVERTISED_Pause |
2547 ADVERTISED_Autoneg |
2548 ADVERTISED_10baseT_Half;
2549
2550 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2551 device_should_wake) {
b02fd9e3
MC		 2552 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2553 advertising |=
2554 ADVERTISED_100baseT_Half |
2555 ADVERTISED_100baseT_Full |
2556 ADVERTISED_10baseT_Full;
2557 else
2558 advertising |= ADVERTISED_10baseT_Full;
2559 }
2560
2561 phydev->advertising = advertising;
2562
2563 phy_start_aneg(phydev);
0a459aac
MC		 2564
2565 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 2566 if (phyid != PHY_ID_BCMAC131) {
2567 phyid &= PHY_BCM_OUI_MASK;
2568 if (phyid == PHY_BCM_OUI_1 ||
2569 phyid == PHY_BCM_OUI_2 ||
2570 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 2571 do_low_power = true;
2572 }
b02fd9e3 2573 }
dd477003 2574 } else {
2023276e 2575 do_low_power = true;
0a459aac 2576
dd477003
MC		 2577 if (tp->link_config.phy_is_low_power == 0) {
2578 tp->link_config.phy_is_low_power = 1;
2579 tp->link_config.orig_speed = tp->link_config.speed;
2580 tp->link_config.orig_duplex = tp->link_config.duplex;
2581 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2582 }
1da177e4 2583
dd477003
MC		 2584 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2585 tp->link_config.speed = SPEED_10;
2586 tp->link_config.duplex = DUPLEX_HALF;
2587 tp->link_config.autoneg = AUTONEG_ENABLE;
2588 tg3_setup_phy(tp, 0);
2589 }
1da177e4
LT		 2590 }
2591
b5d3772c
MC		 2592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2593 u32 val;
2594
2595 val = tr32(GRC_VCPU_EXT_CTRL);
2596 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2597 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2598 int i;
2599 u32 val;
2600
2601 for (i = 0; i < 200; i++) {
2602 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2603 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2604 break;
2605 msleep(1);
2606 }
2607 }
a85feb8c
GZ		 2608 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2609 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2610 WOL_DRV_STATE_SHUTDOWN |
2611 WOL_DRV_WOL |
2612 WOL_SET_MAGIC_PKT);
6921d201 2613
05ac4cb7 2614 if (device_should_wake) {
1da177e4
LT		 2615 u32 mac_mode;
2616
2617 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2618 if (do_low_power) {
dd477003
MC		 2619 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2620 udelay(40);
2621 }
1da177e4 2622
3f7045c1
MC		 2623 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2624 mac_mode = MAC_MODE_PORT_MODE_GMII;
2625 else
2626 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2627
e8f3f6ca
MC		 2628 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2629 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2630 ASIC_REV_5700) {
2631 u32 speed = (tp->tg3_flags &
2632 TG3_FLAG_WOL_SPEED_100MB) ?
2633 SPEED_100 : SPEED_10;
2634 if (tg3_5700_link_polarity(tp, speed))
2635 mac_mode |= MAC_MODE_LINK_POLARITY;
2636 else
2637 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2638 }
1da177e4
LT		 2639 } else {
2640 mac_mode = MAC_MODE_PORT_MODE_TBI;
2641 }
2642
cbf46853 2643 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2644 tw32(MAC_LED_CTRL, tp->led_ctrl);
2645
05ac4cb7
MC		 2646 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2647 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2648 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2649 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2650 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2651 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2652
3bda1258
MC		 2653 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2654 mac_mode |= tp->mac_mode &
2655 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2656 if (mac_mode & MAC_MODE_APE_TX_EN)
2657 mac_mode |= MAC_MODE_TDE_ENABLE;
2658 }
2659
1da177e4
LT		 2660 tw32_f(MAC_MODE, mac_mode);
2661 udelay(100);
2662
2663 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2664 udelay(10);
2665 }
2666
2667 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2668 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2670 u32 base_val;
2671
2672 base_val = tp->pci_clock_ctrl;
2673 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2674 CLOCK_CTRL_TXCLK_DISABLE);
2675
b401e9e2
MC		 2676 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2677 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2678 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2679 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2680 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2681 /* do nothing */
85e94ced 2682 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2683 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2684 u32 newbits1, newbits2;
2685
2686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2688 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2689 CLOCK_CTRL_TXCLK_DISABLE |
2690 CLOCK_CTRL_ALTCLK);
2691 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2692 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2693 newbits1 = CLOCK_CTRL_625_CORE;
2694 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2695 } else {
2696 newbits1 = CLOCK_CTRL_ALTCLK;
2697 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2698 }
2699
b401e9e2
MC		 2700 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2701 40);
1da177e4 2702
b401e9e2
MC		 2703 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2704 40);
1da177e4
LT		 2705
2706 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2707 u32 newbits3;
2708
2709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2710 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2711 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2712 CLOCK_CTRL_TXCLK_DISABLE |
2713 CLOCK_CTRL_44MHZ_CORE);
2714 } else {
2715 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2716 }
2717
b401e9e2
MC		 2718 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2719 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2720 }
2721 }
2722
05ac4cb7 2723 if (!(device_should_wake) &&
22435849 2724 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2725 tg3_power_down_phy(tp, do_low_power);
6921d201 2726
1da177e4
LT		 2727 tg3_frob_aux_power(tp);
2728
2729 /* Workaround for unstable PLL clock */
2730 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2731 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2732 u32 val = tr32(0x7d00);
2733
2734 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2735 tw32(0x7d00, val);
6921d201 2736 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2737 int err;
2738
2739 err = tg3_nvram_lock(tp);
1da177e4 2740 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2741 if (!err)
2742 tg3_nvram_unlock(tp);
6921d201 2743 }
1da177e4
LT		 2744 }
2745
bbadf503
MC		 2746 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2747
05ac4cb7 2748 if (device_should_wake)
12dac075
RW		 2749 pci_enable_wake(tp->pdev, state, true);
2750
1da177e4 2751 /* Finally, set the new power state. */
12dac075 2752 pci_set_power_state(tp->pdev, state);
1da177e4 2753
1da177e4
LT		 2754 return 0;
2755}
2756
1da177e4
LT		 2757static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2758{
2759 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2760 case MII_TG3_AUX_STAT_10HALF:
2761 *speed = SPEED_10;
2762 *duplex = DUPLEX_HALF;
2763 break;
2764
2765 case MII_TG3_AUX_STAT_10FULL:
2766 *speed = SPEED_10;
2767 *duplex = DUPLEX_FULL;
2768 break;
2769
2770 case MII_TG3_AUX_STAT_100HALF:
2771 *speed = SPEED_100;
2772 *duplex = DUPLEX_HALF;
2773 break;
2774
2775 case MII_TG3_AUX_STAT_100FULL:
2776 *speed = SPEED_100;
2777 *duplex = DUPLEX_FULL;
2778 break;
2779
2780 case MII_TG3_AUX_STAT_1000HALF:
2781 *speed = SPEED_1000;
2782 *duplex = DUPLEX_HALF;
2783 break;
2784
2785 case MII_TG3_AUX_STAT_1000FULL:
2786 *speed = SPEED_1000;
2787 *duplex = DUPLEX_FULL;
2788 break;
2789
2790 default:
7f97a4bd 2791 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2792 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2793 SPEED_10;
2794 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2795 DUPLEX_HALF;
2796 break;
2797 }
1da177e4
LT		 2798 *speed = SPEED_INVALID;
2799 *duplex = DUPLEX_INVALID;
2800 break;
855e1111 2801 }
1da177e4
LT		 2802}
2803
2804static void tg3_phy_copper_begin(struct tg3 *tp)
2805{
2806 u32 new_adv;
2807 int i;
2808
2809 if (tp->link_config.phy_is_low_power) {
2810 /* Entering low power mode. Disable gigabit and
2811 * 100baseT advertisements.
2812 */
2813 tg3_writephy(tp, MII_TG3_CTRL, 0);
2814
2815 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2816 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2817 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2818 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2819
2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2822 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2823 tp->link_config.advertising &=
2824 ~(ADVERTISED_1000baseT_Half |
2825 ADVERTISED_1000baseT_Full);
2826
ba4d07a8 2827 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2828 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2829 new_adv |= ADVERTISE_10HALF;
2830 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2831 new_adv |= ADVERTISE_10FULL;
2832 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2833 new_adv |= ADVERTISE_100HALF;
2834 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2835 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2836
2837 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2838
1da177e4
LT		 2839 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840
2841 if (tp->link_config.advertising &
2842 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2843 new_adv = 0;
2844 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2845 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2846 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2847 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2848 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2849 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2850 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2851 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2852 MII_TG3_CTRL_ENABLE_AS_MASTER);
2853 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2854 } else {
2855 tg3_writephy(tp, MII_TG3_CTRL, 0);
2856 }
2857 } else {
ba4d07a8
MC		 2858 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2859 new_adv |= ADVERTISE_CSMA;
2860
1da177e4
LT		 2861 /* Asking for a specific link mode. */
2862 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2864
2865 if (tp->link_config.duplex == DUPLEX_FULL)
2866 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2867 else
2868 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2869 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2870 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2871 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2872 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2873 } else {
1da177e4
LT		 2874 if (tp->link_config.speed == SPEED_100) {
2875 if (tp->link_config.duplex == DUPLEX_FULL)
2876 new_adv |= ADVERTISE_100FULL;
2877 else
2878 new_adv |= ADVERTISE_100HALF;
2879 } else {
2880 if (tp->link_config.duplex == DUPLEX_FULL)
2881 new_adv |= ADVERTISE_10FULL;
2882 else
2883 new_adv |= ADVERTISE_10HALF;
2884 }
2885 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2886
2887 new_adv = 0;
1da177e4 2888 }
ba4d07a8
MC		 2889
2890 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2891 }
2892
2893 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2894 tp->link_config.speed != SPEED_INVALID) {
2895 u32 bmcr, orig_bmcr;
2896
2897 tp->link_config.active_speed = tp->link_config.speed;
2898 tp->link_config.active_duplex = tp->link_config.duplex;
2899
2900 bmcr = 0;
2901 switch (tp->link_config.speed) {
2902 default:
2903 case SPEED_10:
2904 break;
2905
2906 case SPEED_100:
2907 bmcr |= BMCR_SPEED100;
2908 break;
2909
2910 case SPEED_1000:
2911 bmcr |= TG3_BMCR_SPEED1000;
2912 break;
855e1111 2913 }
1da177e4
LT		 2914
2915 if (tp->link_config.duplex == DUPLEX_FULL)
2916 bmcr |= BMCR_FULLDPLX;
2917
2918 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2919 (bmcr != orig_bmcr)) {
2920 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2921 for (i = 0; i < 1500; i++) {
2922 u32 tmp;
2923
2924 udelay(10);
2925 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2926 tg3_readphy(tp, MII_BMSR, &tmp))
2927 continue;
2928 if (!(tmp & BMSR_LSTATUS)) {
2929 udelay(40);
2930 break;
2931 }
2932 }
2933 tg3_writephy(tp, MII_BMCR, bmcr);
2934 udelay(40);
2935 }
2936 } else {
2937 tg3_writephy(tp, MII_BMCR,
2938 BMCR_ANENABLE | BMCR_ANRESTART);
2939 }
2940}
2941
2942static int tg3_init_5401phy_dsp(struct tg3 *tp)
2943{
2944 int err;
2945
2946 /* Turn off tap power management. */
2947 /* Set Extended packet length bit */
2948 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2949
2950 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2951 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2952
2953 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2954 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2955
2956 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2957 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2958
2959 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2960 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2961
2962 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2963 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2964
2965 udelay(40);
2966
2967 return err;
2968}
2969
3600d918 2970static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2971{
3600d918
MC		 2972 u32 adv_reg, all_mask = 0;
2973
2974 if (mask & ADVERTISED_10baseT_Half)
2975 all_mask |= ADVERTISE_10HALF;
2976 if (mask & ADVERTISED_10baseT_Full)
2977 all_mask |= ADVERTISE_10FULL;
2978 if (mask & ADVERTISED_100baseT_Half)
2979 all_mask |= ADVERTISE_100HALF;
2980 if (mask & ADVERTISED_100baseT_Full)
2981 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2982
2983 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2984 return 0;
2985
1da177e4
LT		 2986 if ((adv_reg & all_mask) != all_mask)
2987 return 0;
2988 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2989 u32 tg3_ctrl;
2990
3600d918
MC		 2991 all_mask = 0;
2992 if (mask & ADVERTISED_1000baseT_Half)
2993 all_mask |= ADVERTISE_1000HALF;
2994 if (mask & ADVERTISED_1000baseT_Full)
2995 all_mask |= ADVERTISE_1000FULL;
2996
1da177e4
LT		 2997 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2998 return 0;
2999
1da177e4
LT		 3000 if ((tg3_ctrl & all_mask) != all_mask)
3001 return 0;
3002 }
3003 return 1;
3004}
3005
ef167e27
MC		 3006static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3007{
3008 u32 curadv, reqadv;
3009
3010 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3011 return 1;
3012
3013 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3014 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3015
3016 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3017 if (curadv != reqadv)
3018 return 0;
3019
3020 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3021 tg3_readphy(tp, MII_LPA, rmtadv);
3022 } else {
3023 /* Reprogram the advertisement register, even if it
3024 * does not affect the current link. If the link
3025 * gets renegotiated in the future, we can save an
3026 * additional renegotiation cycle by advertising
3027 * it correctly in the first place.
3028 */
3029 if (curadv != reqadv) {
3030 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3031 ADVERTISE_PAUSE_ASYM);
3032 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3033 }
3034 }
3035
3036 return 1;
3037}
3038
1da177e4
LT		 3039static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3040{
3041 int current_link_up;
3042 u32 bmsr, dummy;
ef167e27 3043 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3044 u16 current_speed;
3045 u8 current_duplex;
3046 int i, err;
3047
3048 tw32(MAC_EVENT, 0);
3049
3050 tw32_f(MAC_STATUS,
3051 (MAC_STATUS_SYNC_CHANGED |
3052 MAC_STATUS_CFG_CHANGED |
3053 MAC_STATUS_MI_COMPLETION |
3054 MAC_STATUS_LNKSTATE_CHANGED));
3055 udelay(40);
3056
8ef21428
MC		 3057 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3058 tw32_f(MAC_MI_MODE,
3059 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3060 udelay(80);
3061 }
1da177e4
LT		 3062
3063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3064
3065 /* Some third-party PHYs need to be reset on link going
3066 * down.
3067 */
3068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3071 netif_carrier_ok(tp->dev)) {
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3074 !(bmsr & BMSR_LSTATUS))
3075 force_reset = 1;
3076 }
3077 if (force_reset)
3078 tg3_phy_reset(tp);
3079
79eb6904 3080 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 3081 tg3_readphy(tp, MII_BMSR, &bmsr);
3082 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3083 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3084 bmsr = 0;
3085
3086 if (!(bmsr & BMSR_LSTATUS)) {
3087 err = tg3_init_5401phy_dsp(tp);
3088 if (err)
3089 return err;
3090
3091 tg3_readphy(tp, MII_BMSR, &bmsr);
3092 for (i = 0; i < 1000; i++) {
3093 udelay(10);
3094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095 (bmsr & BMSR_LSTATUS)) {
3096 udelay(40);
3097 break;
3098 }
3099 }
3100
79eb6904
MC		 3101 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3102 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 3103 !(bmsr & BMSR_LSTATUS) &&
3104 tp->link_config.active_speed == SPEED_1000) {
3105 err = tg3_phy_reset(tp);
3106 if (!err)
3107 err = tg3_init_5401phy_dsp(tp);
3108 if (err)
3109 return err;
3110 }
3111 }
3112 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3113 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3114 /* 5701 {A0,B0} CRC bug workaround */
3115 tg3_writephy(tp, 0x15, 0x0a75);
3116 tg3_writephy(tp, 0x1c, 0x8c68);
3117 tg3_writephy(tp, 0x1c, 0x8d68);
3118 tg3_writephy(tp, 0x1c, 0x8c68);
3119 }
3120
3121 /* Clear pending interrupts... */
3122 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3123 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3124
3125 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3126 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3127 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3128 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3129
3130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3132 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3133 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3134 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3135 else
3136 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3137 }
3138
3139 current_link_up = 0;
3140 current_speed = SPEED_INVALID;
3141 current_duplex = DUPLEX_INVALID;
3142
3143 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3144 u32 val;
3145
3146 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3147 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3148 if (!(val & (1 << 10))) {
3149 val |= (1 << 10);
3150 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3151 goto relink;
3152 }
3153 }
3154
3155 bmsr = 0;
3156 for (i = 0; i < 100; i++) {
3157 tg3_readphy(tp, MII_BMSR, &bmsr);
3158 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3159 (bmsr & BMSR_LSTATUS))
3160 break;
3161 udelay(40);
3162 }
3163
3164 if (bmsr & BMSR_LSTATUS) {
3165 u32 aux_stat, bmcr;
3166
3167 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3168 for (i = 0; i < 2000; i++) {
3169 udelay(10);
3170 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3171 aux_stat)
3172 break;
3173 }
3174
3175 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3176 &current_speed,
3177 &current_duplex);
3178
3179 bmcr = 0;
3180 for (i = 0; i < 200; i++) {
3181 tg3_readphy(tp, MII_BMCR, &bmcr);
3182 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3183 continue;
3184 if (bmcr && bmcr != 0x7fff)
3185 break;
3186 udelay(10);
3187 }
3188
ef167e27
MC		 3189 lcl_adv = 0;
3190 rmt_adv = 0;
1da177e4 3191
ef167e27
MC		 3192 tp->link_config.active_speed = current_speed;
3193 tp->link_config.active_duplex = current_duplex;
3194
3195 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3196 if ((bmcr & BMCR_ANENABLE) &&
3197 tg3_copper_is_advertising_all(tp,
3198 tp->link_config.advertising)) {
3199 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3200 &rmt_adv))
3201 current_link_up = 1;
1da177e4
LT		 3202 }
3203 } else {
3204 if (!(bmcr & BMCR_ANENABLE) &&
3205 tp->link_config.speed == current_speed &&
ef167e27
MC		 3206 tp->link_config.duplex == current_duplex &&
3207 tp->link_config.flowctrl ==
3208 tp->link_config.active_flowctrl) {
1da177e4 3209 current_link_up = 1;
1da177e4
LT		 3210 }
3211 }
3212
ef167e27
MC		 3213 if (current_link_up == 1 &&
3214 tp->link_config.active_duplex == DUPLEX_FULL)
3215 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3216 }
3217
1da177e4 3218relink:
6921d201 3219 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3220 u32 tmp;
3221
3222 tg3_phy_copper_begin(tp);
3223
3224 tg3_readphy(tp, MII_BMSR, &tmp);
3225 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3226 (tmp & BMSR_LSTATUS))
3227 current_link_up = 1;
3228 }
3229
3230 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3231 if (current_link_up == 1) {
3232 if (tp->link_config.active_speed == SPEED_100 ||
3233 tp->link_config.active_speed == SPEED_10)
3234 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3235 else
3236 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3237 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3238 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3239 else
1da177e4
LT		 3240 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3241
3242 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3243 if (tp->link_config.active_duplex == DUPLEX_HALF)
3244 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3245
1da177e4 3246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3247 if (current_link_up == 1 &&
3248 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3249 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3250 else
3251 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3252 }
3253
3254 /* ??? Without this setting Netgear GA302T PHY does not
3255 * ??? send/receive packets...
3256 */
79eb6904 3257 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1da177e4
LT		 3258 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3259 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3260 tw32_f(MAC_MI_MODE, tp->mi_mode);
3261 udelay(80);
3262 }
3263
3264 tw32_f(MAC_MODE, tp->mac_mode);
3265 udelay(40);
3266
3267 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3268 /* Polled via timer. */
3269 tw32_f(MAC_EVENT, 0);
3270 } else {
3271 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3272 }
3273 udelay(40);
3274
3275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3276 current_link_up == 1 &&
3277 tp->link_config.active_speed == SPEED_1000 &&
3278 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3279 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3280 udelay(120);
3281 tw32_f(MAC_STATUS,
3282 (MAC_STATUS_SYNC_CHANGED |
3283 MAC_STATUS_CFG_CHANGED));
3284 udelay(40);
3285 tg3_write_mem(tp,
3286 NIC_SRAM_FIRMWARE_MBOX,
3287 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3288 }
3289
5e7dfd0f
MC		 3290 /* Prevent send BD corruption. */
3291 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3292 u16 oldlnkctl, newlnkctl;
3293
3294 pci_read_config_word(tp->pdev,
3295 tp->pcie_cap + PCI_EXP_LNKCTL,
3296 &oldlnkctl);
3297 if (tp->link_config.active_speed == SPEED_100 ||
3298 tp->link_config.active_speed == SPEED_10)
3299 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3300 else
3301 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3302 if (newlnkctl != oldlnkctl)
3303 pci_write_config_word(tp->pdev,
3304 tp->pcie_cap + PCI_EXP_LNKCTL,
3305 newlnkctl);
3306 }
3307
1da177e4
LT		 3308 if (current_link_up != netif_carrier_ok(tp->dev)) {
3309 if (current_link_up)
3310 netif_carrier_on(tp->dev);
3311 else
3312 netif_carrier_off(tp->dev);
3313 tg3_link_report(tp);
3314 }
3315
3316 return 0;
3317}
3318
3319struct tg3_fiber_aneginfo {
3320 int state;
3321#define ANEG_STATE_UNKNOWN 0
3322#define ANEG_STATE_AN_ENABLE 1
3323#define ANEG_STATE_RESTART_INIT 2
3324#define ANEG_STATE_RESTART 3
3325#define ANEG_STATE_DISABLE_LINK_OK 4
3326#define ANEG_STATE_ABILITY_DETECT_INIT 5
3327#define ANEG_STATE_ABILITY_DETECT 6
3328#define ANEG_STATE_ACK_DETECT_INIT 7
3329#define ANEG_STATE_ACK_DETECT 8
3330#define ANEG_STATE_COMPLETE_ACK_INIT 9
3331#define ANEG_STATE_COMPLETE_ACK 10
3332#define ANEG_STATE_IDLE_DETECT_INIT 11
3333#define ANEG_STATE_IDLE_DETECT 12
3334#define ANEG_STATE_LINK_OK 13
3335#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3336#define ANEG_STATE_NEXT_PAGE_WAIT 15
3337
3338 u32 flags;
3339#define MR_AN_ENABLE 0x00000001
3340#define MR_RESTART_AN 0x00000002
3341#define MR_AN_COMPLETE 0x00000004
3342#define MR_PAGE_RX 0x00000008
3343#define MR_NP_LOADED 0x00000010
3344#define MR_TOGGLE_TX 0x00000020
3345#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3346#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3347#define MR_LP_ADV_SYM_PAUSE 0x00000100
3348#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3349#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3350#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3351#define MR_LP_ADV_NEXT_PAGE 0x00001000
3352#define MR_TOGGLE_RX 0x00002000
3353#define MR_NP_RX 0x00004000
3354
3355#define MR_LINK_OK 0x80000000
3356
3357 unsigned long link_time, cur_time;
3358
3359 u32 ability_match_cfg;
3360 int ability_match_count;
3361
3362 char ability_match, idle_match, ack_match;
3363
3364 u32 txconfig, rxconfig;
3365#define ANEG_CFG_NP 0x00000080
3366#define ANEG_CFG_ACK 0x00000040
3367#define ANEG_CFG_RF2 0x00000020
3368#define ANEG_CFG_RF1 0x00000010
3369#define ANEG_CFG_PS2 0x00000001
3370#define ANEG_CFG_PS1 0x00008000
3371#define ANEG_CFG_HD 0x00004000
3372#define ANEG_CFG_FD 0x00002000
3373#define ANEG_CFG_INVAL 0x00001f06
3374
3375};
3376#define ANEG_OK 0
3377#define ANEG_DONE 1
3378#define ANEG_TIMER_ENAB 2
3379#define ANEG_FAILED -1
3380
3381#define ANEG_STATE_SETTLE_TIME 10000
3382
3383static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3384 struct tg3_fiber_aneginfo *ap)
3385{
5be73b47 3386 u16 flowctrl;
1da177e4
LT		 3387 unsigned long delta;
3388 u32 rx_cfg_reg;
3389 int ret;
3390
3391 if (ap->state == ANEG_STATE_UNKNOWN) {
3392 ap->rxconfig = 0;
3393 ap->link_time = 0;
3394 ap->cur_time = 0;
3395 ap->ability_match_cfg = 0;
3396 ap->ability_match_count = 0;
3397 ap->ability_match = 0;
3398 ap->idle_match = 0;
3399 ap->ack_match = 0;
3400 }
3401 ap->cur_time++;
3402
3403 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3404 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3405
3406 if (rx_cfg_reg != ap->ability_match_cfg) {
3407 ap->ability_match_cfg = rx_cfg_reg;
3408 ap->ability_match = 0;
3409 ap->ability_match_count = 0;
3410 } else {
3411 if (++ap->ability_match_count > 1) {
3412 ap->ability_match = 1;
3413 ap->ability_match_cfg = rx_cfg_reg;
3414 }
3415 }
3416 if (rx_cfg_reg & ANEG_CFG_ACK)
3417 ap->ack_match = 1;
3418 else
3419 ap->ack_match = 0;
3420
3421 ap->idle_match = 0;
3422 } else {
3423 ap->idle_match = 1;
3424 ap->ability_match_cfg = 0;
3425 ap->ability_match_count = 0;
3426 ap->ability_match = 0;
3427 ap->ack_match = 0;
3428
3429 rx_cfg_reg = 0;
3430 }
3431
3432 ap->rxconfig = rx_cfg_reg;
3433 ret = ANEG_OK;
3434
3435 switch(ap->state) {
3436 case ANEG_STATE_UNKNOWN:
3437 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3438 ap->state = ANEG_STATE_AN_ENABLE;
3439
3440 /* fallthru */
3441 case ANEG_STATE_AN_ENABLE:
3442 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3443 if (ap->flags & MR_AN_ENABLE) {
3444 ap->link_time = 0;
3445 ap->cur_time = 0;
3446 ap->ability_match_cfg = 0;
3447 ap->ability_match_count = 0;
3448 ap->ability_match = 0;
3449 ap->idle_match = 0;
3450 ap->ack_match = 0;
3451
3452 ap->state = ANEG_STATE_RESTART_INIT;
3453 } else {
3454 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3455 }
3456 break;
3457
3458 case ANEG_STATE_RESTART_INIT:
3459 ap->link_time = ap->cur_time;
3460 ap->flags &= ~(MR_NP_LOADED);
3461 ap->txconfig = 0;
3462 tw32(MAC_TX_AUTO_NEG, 0);
3463 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3464 tw32_f(MAC_MODE, tp->mac_mode);
3465 udelay(40);
3466
3467 ret = ANEG_TIMER_ENAB;
3468 ap->state = ANEG_STATE_RESTART;
3469
3470 /* fallthru */
3471 case ANEG_STATE_RESTART:
3472 delta = ap->cur_time - ap->link_time;
3473 if (delta > ANEG_STATE_SETTLE_TIME) {
3474 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3475 } else {
3476 ret = ANEG_TIMER_ENAB;
3477 }
3478 break;
3479
3480 case ANEG_STATE_DISABLE_LINK_OK:
3481 ret = ANEG_DONE;
3482 break;
3483
3484 case ANEG_STATE_ABILITY_DETECT_INIT:
3485 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3486 ap->txconfig = ANEG_CFG_FD;
3487 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3488 if (flowctrl & ADVERTISE_1000XPAUSE)
3489 ap->txconfig |= ANEG_CFG_PS1;
3490 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3491 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3492 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3493 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3494 tw32_f(MAC_MODE, tp->mac_mode);
3495 udelay(40);
3496
3497 ap->state = ANEG_STATE_ABILITY_DETECT;
3498 break;
3499
3500 case ANEG_STATE_ABILITY_DETECT:
3501 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3502 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3503 }
3504 break;
3505
3506 case ANEG_STATE_ACK_DETECT_INIT:
3507 ap->txconfig |= ANEG_CFG_ACK;
3508 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3509 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3510 tw32_f(MAC_MODE, tp->mac_mode);
3511 udelay(40);
3512
3513 ap->state = ANEG_STATE_ACK_DETECT;
3514
3515 /* fallthru */
3516 case ANEG_STATE_ACK_DETECT:
3517 if (ap->ack_match != 0) {
3518 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3519 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3520 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3521 } else {
3522 ap->state = ANEG_STATE_AN_ENABLE;
3523 }
3524 } else if (ap->ability_match != 0 &&
3525 ap->rxconfig == 0) {
3526 ap->state = ANEG_STATE_AN_ENABLE;
3527 }
3528 break;
3529
3530 case ANEG_STATE_COMPLETE_ACK_INIT:
3531 if (ap->rxconfig & ANEG_CFG_INVAL) {
3532 ret = ANEG_FAILED;
3533 break;
3534 }
3535 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3536 MR_LP_ADV_HALF_DUPLEX |
3537 MR_LP_ADV_SYM_PAUSE |
3538 MR_LP_ADV_ASYM_PAUSE |
3539 MR_LP_ADV_REMOTE_FAULT1 |
3540 MR_LP_ADV_REMOTE_FAULT2 |
3541 MR_LP_ADV_NEXT_PAGE |
3542 MR_TOGGLE_RX |
3543 MR_NP_RX);
3544 if (ap->rxconfig & ANEG_CFG_FD)
3545 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3546 if (ap->rxconfig & ANEG_CFG_HD)
3547 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3548 if (ap->rxconfig & ANEG_CFG_PS1)
3549 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3550 if (ap->rxconfig & ANEG_CFG_PS2)
3551 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3552 if (ap->rxconfig & ANEG_CFG_RF1)
3553 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3554 if (ap->rxconfig & ANEG_CFG_RF2)
3555 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3556 if (ap->rxconfig & ANEG_CFG_NP)
3557 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3558
3559 ap->link_time = ap->cur_time;
3560
3561 ap->flags ^= (MR_TOGGLE_TX);
3562 if (ap->rxconfig & 0x0008)
3563 ap->flags |= MR_TOGGLE_RX;
3564 if (ap->rxconfig & ANEG_CFG_NP)
3565 ap->flags |= MR_NP_RX;
3566 ap->flags |= MR_PAGE_RX;
3567
3568 ap->state = ANEG_STATE_COMPLETE_ACK;
3569 ret = ANEG_TIMER_ENAB;
3570 break;
3571
3572 case ANEG_STATE_COMPLETE_ACK:
3573 if (ap->ability_match != 0 &&
3574 ap->rxconfig == 0) {
3575 ap->state = ANEG_STATE_AN_ENABLE;
3576 break;
3577 }
3578 delta = ap->cur_time - ap->link_time;
3579 if (delta > ANEG_STATE_SETTLE_TIME) {
3580 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3581 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3582 } else {
3583 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3584 !(ap->flags & MR_NP_RX)) {
3585 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3586 } else {
3587 ret = ANEG_FAILED;
3588 }
3589 }
3590 }
3591 break;
3592
3593 case ANEG_STATE_IDLE_DETECT_INIT:
3594 ap->link_time = ap->cur_time;
3595 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3596 tw32_f(MAC_MODE, tp->mac_mode);
3597 udelay(40);
3598
3599 ap->state = ANEG_STATE_IDLE_DETECT;
3600 ret = ANEG_TIMER_ENAB;
3601 break;
3602
3603 case ANEG_STATE_IDLE_DETECT:
3604 if (ap->ability_match != 0 &&
3605 ap->rxconfig == 0) {
3606 ap->state = ANEG_STATE_AN_ENABLE;
3607 break;
3608 }
3609 delta = ap->cur_time - ap->link_time;
3610 if (delta > ANEG_STATE_SETTLE_TIME) {
3611 /* XXX another gem from the Broadcom driver :( */
3612 ap->state = ANEG_STATE_LINK_OK;
3613 }
3614 break;
3615
3616 case ANEG_STATE_LINK_OK:
3617 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3618 ret = ANEG_DONE;
3619 break;
3620
3621 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3622 /* ??? unimplemented */
3623 break;
3624
3625 case ANEG_STATE_NEXT_PAGE_WAIT:
3626 /* ??? unimplemented */
3627 break;
3628
3629 default:
3630 ret = ANEG_FAILED;
3631 break;
855e1111 3632 }
1da177e4
LT		 3633
3634 return ret;
3635}
3636
5be73b47 3637static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3638{
3639 int res = 0;
3640 struct tg3_fiber_aneginfo aninfo;
3641 int status = ANEG_FAILED;
3642 unsigned int tick;
3643 u32 tmp;
3644
3645 tw32_f(MAC_TX_AUTO_NEG, 0);
3646
3647 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3648 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3649 udelay(40);
3650
3651 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3652 udelay(40);
3653
3654 memset(&aninfo, 0, sizeof(aninfo));
3655 aninfo.flags |= MR_AN_ENABLE;
3656 aninfo.state = ANEG_STATE_UNKNOWN;
3657 aninfo.cur_time = 0;
3658 tick = 0;
3659 while (++tick < 195000) {
3660 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3661 if (status == ANEG_DONE || status == ANEG_FAILED)
3662 break;
3663
3664 udelay(1);
3665 }
3666
3667 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3668 tw32_f(MAC_MODE, tp->mac_mode);
3669 udelay(40);
3670
5be73b47
MC		 3671 *txflags = aninfo.txconfig;
3672 *rxflags = aninfo.flags;
1da177e4
LT		 3673
3674 if (status == ANEG_DONE &&
3675 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3676 MR_LP_ADV_FULL_DUPLEX)))
3677 res = 1;
3678
3679 return res;
3680}
3681
3682static void tg3_init_bcm8002(struct tg3 *tp)
3683{
3684 u32 mac_status = tr32(MAC_STATUS);
3685 int i;
3686
3687 /* Reset when initting first time or we have a link. */
3688 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3689 !(mac_status & MAC_STATUS_PCS_SYNCED))
3690 return;
3691
3692 /* Set PLL lock range. */
3693 tg3_writephy(tp, 0x16, 0x8007);
3694
3695 /* SW reset */
3696 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3697
3698 /* Wait for reset to complete. */
3699 /* XXX schedule_timeout() ... */
3700 for (i = 0; i < 500; i++)
3701 udelay(10);
3702
3703 /* Config mode; select PMA/Ch 1 regs. */
3704 tg3_writephy(tp, 0x10, 0x8411);
3705
3706 /* Enable auto-lock and comdet, select txclk for tx. */
3707 tg3_writephy(tp, 0x11, 0x0a10);
3708
3709 tg3_writephy(tp, 0x18, 0x00a0);
3710 tg3_writephy(tp, 0x16, 0x41ff);
3711
3712 /* Assert and deassert POR. */
3713 tg3_writephy(tp, 0x13, 0x0400);
3714 udelay(40);
3715 tg3_writephy(tp, 0x13, 0x0000);
3716
3717 tg3_writephy(tp, 0x11, 0x0a50);
3718 udelay(40);
3719 tg3_writephy(tp, 0x11, 0x0a10);
3720
3721 /* Wait for signal to stabilize */
3722 /* XXX schedule_timeout() ... */
3723 for (i = 0; i < 15000; i++)
3724 udelay(10);
3725
3726 /* Deselect the channel register so we can read the PHYID
3727 * later.
3728 */
3729 tg3_writephy(tp, 0x10, 0x8011);
3730}
3731
3732static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3733{
82cd3d11 3734 u16 flowctrl;
1da177e4
LT		 3735 u32 sg_dig_ctrl, sg_dig_status;
3736 u32 serdes_cfg, expected_sg_dig_ctrl;
3737 int workaround, port_a;
3738 int current_link_up;
3739
3740 serdes_cfg = 0;
3741 expected_sg_dig_ctrl = 0;
3742 workaround = 0;
3743 port_a = 1;
3744 current_link_up = 0;
3745
3746 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3747 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3748 workaround = 1;
3749 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3750 port_a = 0;
3751
3752 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3753 /* preserve bits 20-23 for voltage regulator */
3754 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3755 }
3756
3757 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3758
3759 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3760 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3761 if (workaround) {
3762 u32 val = serdes_cfg;
3763
3764 if (port_a)
3765 val |= 0xc010000;
3766 else
3767 val |= 0x4010000;
3768 tw32_f(MAC_SERDES_CFG, val);
3769 }
c98f6e3b
MC		 3770
3771 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3772 }
3773 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3774 tg3_setup_flow_control(tp, 0, 0);
3775 current_link_up = 1;
3776 }
3777 goto out;
3778 }
3779
3780 /* Want auto-negotiation. */
c98f6e3b 3781 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3782
82cd3d11
MC		 3783 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3784 if (flowctrl & ADVERTISE_1000XPAUSE)
3785 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3786 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3787 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3788
3789 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3790 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3791 tp->serdes_counter &&
3792 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3793 MAC_STATUS_RCVD_CFG)) ==
3794 MAC_STATUS_PCS_SYNCED)) {
3795 tp->serdes_counter--;
3796 current_link_up = 1;
3797 goto out;
3798 }
3799restart_autoneg:
1da177e4
LT		 3800 if (workaround)
3801 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3802 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3803 udelay(5);
3804 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3805
3d3ebe74
MC		 3806 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3807 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3808 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3809 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3810 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3811 mac_status = tr32(MAC_STATUS);
3812
c98f6e3b 3813 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3814 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3815 u32 local_adv = 0, remote_adv = 0;
3816
3817 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3818 local_adv |= ADVERTISE_1000XPAUSE;
3819 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3820 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3821
c98f6e3b 3822 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3823 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3824 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3825 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3826
3827 tg3_setup_flow_control(tp, local_adv, remote_adv);
3828 current_link_up = 1;
3d3ebe74
MC		 3829 tp->serdes_counter = 0;
3830 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3831 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3832 if (tp->serdes_counter)
3833 tp->serdes_counter--;
1da177e4
LT		 3834 else {
3835 if (workaround) {
3836 u32 val = serdes_cfg;
3837
3838 if (port_a)
3839 val |= 0xc010000;
3840 else
3841 val |= 0x4010000;
3842
3843 tw32_f(MAC_SERDES_CFG, val);
3844 }
3845
c98f6e3b 3846 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3847 udelay(40);
3848
3849 /* Link parallel detection - link is up */
3850 /* only if we have PCS_SYNC and not */
3851 /* receiving config code words */
3852 mac_status = tr32(MAC_STATUS);
3853 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3854 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3855 tg3_setup_flow_control(tp, 0, 0);
3856 current_link_up = 1;
3d3ebe74
MC		 3857 tp->tg3_flags2 |=
3858 TG3_FLG2_PARALLEL_DETECT;
3859 tp->serdes_counter =
3860 SERDES_PARALLEL_DET_TIMEOUT;
3861 } else
3862 goto restart_autoneg;
1da177e4
LT		 3863 }
3864 }
3d3ebe74
MC		 3865 } else {
3866 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3867 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3868 }
3869
3870out:
3871 return current_link_up;
3872}
3873
3874static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3875{
3876 int current_link_up = 0;
3877
5cf64b8a 3878 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3879 goto out;
1da177e4
LT		 3880
3881 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3882 u32 txflags, rxflags;
1da177e4 3883 int i;
6aa20a22 3884
5be73b47
MC		 3885 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3886 u32 local_adv = 0, remote_adv = 0;
1da177e4 3887
5be73b47
MC		 3888 if (txflags & ANEG_CFG_PS1)
3889 local_adv |= ADVERTISE_1000XPAUSE;
3890 if (txflags & ANEG_CFG_PS2)
3891 local_adv |= ADVERTISE_1000XPSE_ASYM;
3892
3893 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3894 remote_adv |= LPA_1000XPAUSE;
3895 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3896 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3897
3898 tg3_setup_flow_control(tp, local_adv, remote_adv);
3899
1da177e4
LT		 3900 current_link_up = 1;
3901 }
3902 for (i = 0; i < 30; i++) {
3903 udelay(20);
3904 tw32_f(MAC_STATUS,
3905 (MAC_STATUS_SYNC_CHANGED |
3906 MAC_STATUS_CFG_CHANGED));
3907 udelay(40);
3908 if ((tr32(MAC_STATUS) &
3909 (MAC_STATUS_SYNC_CHANGED |
3910 MAC_STATUS_CFG_CHANGED)) == 0)
3911 break;
3912 }
3913
3914 mac_status = tr32(MAC_STATUS);
3915 if (current_link_up == 0 &&
3916 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3917 !(mac_status & MAC_STATUS_RCVD_CFG))
3918 current_link_up = 1;
3919 } else {
5be73b47
MC		 3920 tg3_setup_flow_control(tp, 0, 0);
3921
1da177e4
LT		 3922 /* Forcing 1000FD link up. */
3923 current_link_up = 1;
1da177e4
LT		 3924
3925 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3926 udelay(40);
e8f3f6ca
MC		 3927
3928 tw32_f(MAC_MODE, tp->mac_mode);
3929 udelay(40);
1da177e4
LT		 3930 }
3931
3932out:
3933 return current_link_up;
3934}
3935
3936static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3937{
3938 u32 orig_pause_cfg;
3939 u16 orig_active_speed;
3940 u8 orig_active_duplex;
3941 u32 mac_status;
3942 int current_link_up;
3943 int i;
3944
8d018621 3945 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3946 orig_active_speed = tp->link_config.active_speed;
3947 orig_active_duplex = tp->link_config.active_duplex;
3948
3949 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3950 netif_carrier_ok(tp->dev) &&
3951 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3952 mac_status = tr32(MAC_STATUS);
3953 mac_status &= (MAC_STATUS_PCS_SYNCED |
3954 MAC_STATUS_SIGNAL_DET |
3955 MAC_STATUS_CFG_CHANGED |
3956 MAC_STATUS_RCVD_CFG);
3957 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3958 MAC_STATUS_SIGNAL_DET)) {
3959 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3960 MAC_STATUS_CFG_CHANGED));
3961 return 0;
3962 }
3963 }
3964
3965 tw32_f(MAC_TX_AUTO_NEG, 0);
3966
3967 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3968 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3969 tw32_f(MAC_MODE, tp->mac_mode);
3970 udelay(40);
3971
79eb6904 3972 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 3973 tg3_init_bcm8002(tp);
3974
3975 /* Enable link change event even when serdes polling. */
3976 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3977 udelay(40);
3978
3979 current_link_up = 0;
3980 mac_status = tr32(MAC_STATUS);
3981
3982 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3983 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3984 else
3985 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3986
898a56f8 3987 tp->napi[0].hw_status->status =
1da177e4 3988 (SD_STATUS_UPDATED |
898a56f8 3989 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3990
3991 for (i = 0; i < 100; i++) {
3992 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3993 MAC_STATUS_CFG_CHANGED));
3994 udelay(5);
3995 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3996 MAC_STATUS_CFG_CHANGED |
3997 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3998 break;
3999 }
4000
4001 mac_status = tr32(MAC_STATUS);
4002 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4003 current_link_up = 0;
3d3ebe74
MC		 4004 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4005 tp->serdes_counter == 0) {
1da177e4
LT		 4006 tw32_f(MAC_MODE, (tp->mac_mode |
4007 MAC_MODE_SEND_CONFIGS));
4008 udelay(1);
4009 tw32_f(MAC_MODE, tp->mac_mode);
4010 }
4011 }
4012
4013 if (current_link_up == 1) {
4014 tp->link_config.active_speed = SPEED_1000;
4015 tp->link_config.active_duplex = DUPLEX_FULL;
4016 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4017 LED_CTRL_LNKLED_OVERRIDE |
4018 LED_CTRL_1000MBPS_ON));
4019 } else {
4020 tp->link_config.active_speed = SPEED_INVALID;
4021 tp->link_config.active_duplex = DUPLEX_INVALID;
4022 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4023 LED_CTRL_LNKLED_OVERRIDE |
4024 LED_CTRL_TRAFFIC_OVERRIDE));
4025 }
4026
4027 if (current_link_up != netif_carrier_ok(tp->dev)) {
4028 if (current_link_up)
4029 netif_carrier_on(tp->dev);
4030 else
4031 netif_carrier_off(tp->dev);
4032 tg3_link_report(tp);
4033 } else {
8d018621 4034 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4035 if (orig_pause_cfg != now_pause_cfg ||
4036 orig_active_speed != tp->link_config.active_speed ||
4037 orig_active_duplex != tp->link_config.active_duplex)
4038 tg3_link_report(tp);
4039 }
4040
4041 return 0;
4042}
4043
747e8f8b
MC		 4044static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4045{
4046 int current_link_up, err = 0;
4047 u32 bmsr, bmcr;
4048 u16 current_speed;
4049 u8 current_duplex;
ef167e27 4050 u32 local_adv, remote_adv;
747e8f8b
MC		 4051
4052 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4053 tw32_f(MAC_MODE, tp->mac_mode);
4054 udelay(40);
4055
4056 tw32(MAC_EVENT, 0);
4057
4058 tw32_f(MAC_STATUS,
4059 (MAC_STATUS_SYNC_CHANGED |
4060 MAC_STATUS_CFG_CHANGED |
4061 MAC_STATUS_MI_COMPLETION |
4062 MAC_STATUS_LNKSTATE_CHANGED));
4063 udelay(40);
4064
4065 if (force_reset)
4066 tg3_phy_reset(tp);
4067
4068 current_link_up = 0;
4069 current_speed = SPEED_INVALID;
4070 current_duplex = DUPLEX_INVALID;
4071
4072 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4073 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4075 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4076 bmsr |= BMSR_LSTATUS;
4077 else
4078 bmsr &= ~BMSR_LSTATUS;
4079 }
747e8f8b
MC		 4080
4081 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4082
4083 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4084 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4085 /* do nothing, just check for link up at the end */
4086 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4087 u32 adv, new_adv;
4088
4089 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4090 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4091 ADVERTISE_1000XPAUSE |
4092 ADVERTISE_1000XPSE_ASYM |
4093 ADVERTISE_SLCT);
4094
ba4d07a8 4095 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4096
4097 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4098 new_adv |= ADVERTISE_1000XHALF;
4099 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4100 new_adv |= ADVERTISE_1000XFULL;
4101
4102 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4103 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4104 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4105 tg3_writephy(tp, MII_BMCR, bmcr);
4106
4107 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4108 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4109 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4110
4111 return err;
4112 }
4113 } else {
4114 u32 new_bmcr;
4115
4116 bmcr &= ~BMCR_SPEED1000;
4117 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4118
4119 if (tp->link_config.duplex == DUPLEX_FULL)
4120 new_bmcr |= BMCR_FULLDPLX;
4121
4122 if (new_bmcr != bmcr) {
4123 /* BMCR_SPEED1000 is a reserved bit that needs
4124 * to be set on write.
4125 */
4126 new_bmcr |= BMCR_SPEED1000;
4127
4128 /* Force a linkdown */
4129 if (netif_carrier_ok(tp->dev)) {
4130 u32 adv;
4131
4132 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4133 adv &= ~(ADVERTISE_1000XFULL |
4134 ADVERTISE_1000XHALF |
4135 ADVERTISE_SLCT);
4136 tg3_writephy(tp, MII_ADVERTISE, adv);
4137 tg3_writephy(tp, MII_BMCR, bmcr |
4138 BMCR_ANRESTART |
4139 BMCR_ANENABLE);
4140 udelay(10);
4141 netif_carrier_off(tp->dev);
4142 }
4143 tg3_writephy(tp, MII_BMCR, new_bmcr);
4144 bmcr = new_bmcr;
4145 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4146 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4147 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4148 ASIC_REV_5714) {
4149 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4150 bmsr |= BMSR_LSTATUS;
4151 else
4152 bmsr &= ~BMSR_LSTATUS;
4153 }
747e8f8b
MC		 4154 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4155 }
4156 }
4157
4158 if (bmsr & BMSR_LSTATUS) {
4159 current_speed = SPEED_1000;
4160 current_link_up = 1;
4161 if (bmcr & BMCR_FULLDPLX)
4162 current_duplex = DUPLEX_FULL;
4163 else
4164 current_duplex = DUPLEX_HALF;
4165
ef167e27
MC		 4166 local_adv = 0;
4167 remote_adv = 0;
4168
747e8f8b 4169 if (bmcr & BMCR_ANENABLE) {
ef167e27 4170 u32 common;
747e8f8b
MC		 4171
4172 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4173 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4174 common = local_adv & remote_adv;
4175 if (common & (ADVERTISE_1000XHALF |
4176 ADVERTISE_1000XFULL)) {
4177 if (common & ADVERTISE_1000XFULL)
4178 current_duplex = DUPLEX_FULL;
4179 else
4180 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4181 }
4182 else
4183 current_link_up = 0;
4184 }
4185 }
4186
ef167e27
MC		 4187 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4188 tg3_setup_flow_control(tp, local_adv, remote_adv);
4189
747e8f8b
MC		 4190 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4191 if (tp->link_config.active_duplex == DUPLEX_HALF)
4192 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4193
4194 tw32_f(MAC_MODE, tp->mac_mode);
4195 udelay(40);
4196
4197 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4198
4199 tp->link_config.active_speed = current_speed;
4200 tp->link_config.active_duplex = current_duplex;
4201
4202 if (current_link_up != netif_carrier_ok(tp->dev)) {
4203 if (current_link_up)
4204 netif_carrier_on(tp->dev);
4205 else {
4206 netif_carrier_off(tp->dev);
4207 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4208 }
4209 tg3_link_report(tp);
4210 }
4211 return err;
4212}
4213
4214static void tg3_serdes_parallel_detect(struct tg3 *tp)
4215{
3d3ebe74 4216 if (tp->serdes_counter) {
747e8f8b 4217 /* Give autoneg time to complete. */
3d3ebe74 4218 tp->serdes_counter--;
747e8f8b
MC		 4219 return;
4220 }
4221 if (!netif_carrier_ok(tp->dev) &&
4222 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4223 u32 bmcr;
4224
4225 tg3_readphy(tp, MII_BMCR, &bmcr);
4226 if (bmcr & BMCR_ANENABLE) {
4227 u32 phy1, phy2;
4228
4229 /* Select shadow register 0x1f */
4230 tg3_writephy(tp, 0x1c, 0x7c00);
4231 tg3_readphy(tp, 0x1c, &phy1);
4232
4233 /* Select expansion interrupt status register */
4234 tg3_writephy(tp, 0x17, 0x0f01);
4235 tg3_readphy(tp, 0x15, &phy2);
4236 tg3_readphy(tp, 0x15, &phy2);
4237
4238 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4239 /* We have signal detect and not receiving
4240 * config code words, link is up by parallel
4241 * detection.
4242 */
4243
4244 bmcr &= ~BMCR_ANENABLE;
4245 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4246 tg3_writephy(tp, MII_BMCR, bmcr);
4247 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4248 }
4249 }
4250 }
4251 else if (netif_carrier_ok(tp->dev) &&
4252 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4253 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4254 u32 phy2;
4255
4256 /* Select expansion interrupt status register */
4257 tg3_writephy(tp, 0x17, 0x0f01);
4258 tg3_readphy(tp, 0x15, &phy2);
4259 if (phy2 & 0x20) {
4260 u32 bmcr;
4261
4262 /* Config code words received, turn on autoneg. */
4263 tg3_readphy(tp, MII_BMCR, &bmcr);
4264 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4265
4266 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4267
4268 }
4269 }
4270}
4271
1da177e4
LT		 4272static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4273{
4274 int err;
4275
4276 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4277 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4278 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4279 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4280 } else {
4281 err = tg3_setup_copper_phy(tp, force_reset);
4282 }
4283
bcb37f6c 4284 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4285 u32 val, scale;
4286
4287 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4288 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4289 scale = 65;
4290 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4291 scale = 6;
4292 else
4293 scale = 12;
4294
4295 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4296 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4297 tw32(GRC_MISC_CFG, val);
4298 }
4299
1da177e4
LT		 4300 if (tp->link_config.active_speed == SPEED_1000 &&
4301 tp->link_config.active_duplex == DUPLEX_HALF)
4302 tw32(MAC_TX_LENGTHS,
4303 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4304 (6 << TX_LENGTHS_IPG_SHIFT) |
4305 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4306 else
4307 tw32(MAC_TX_LENGTHS,
4308 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4309 (6 << TX_LENGTHS_IPG_SHIFT) |
4310 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4311
4312 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4313 if (netif_carrier_ok(tp->dev)) {
4314 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4315 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4316 } else {
4317 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4318 }
4319 }
4320
8ed5d97e
MC		 4321 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4322 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4323 if (!netif_carrier_ok(tp->dev))
4324 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4325 tp->pwrmgmt_thresh;
4326 else
4327 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4328 tw32(PCIE_PWR_MGMT_THRESH, val);
4329 }
4330
1da177e4
LT		 4331 return err;
4332}
4333
df3e6548
MC		 4334/* This is called whenever we suspect that the system chipset is re-
4335 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4336 * is bogus tx completions. We try to recover by setting the
4337 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4338 * in the workqueue.
4339 */
4340static void tg3_tx_recover(struct tg3 *tp)
4341{
4342 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4343 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4344
4345 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4346 "mapped I/O cycles to the network device, attempting to "
4347 "recover. Please report the problem to the driver maintainer "
4348 "and include system chipset information.\n", tp->dev->name);
4349
4350 spin_lock(&tp->lock);
df3e6548 4351 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4352 spin_unlock(&tp->lock);
4353}
4354
f3f3f27e 4355static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4356{
4357 smp_mb();
f3f3f27e
MC		 4358 return tnapi->tx_pending -
4359 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4360}
4361
1da177e4
LT		 4362/* Tigon3 never reports partial packet sends. So we do not
4363 * need special logic to handle SKBs that have not had all
4364 * of their frags sent yet, like SunGEM does.
4365 */
17375d25 4366static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4367{
17375d25 4368 struct tg3 *tp = tnapi->tp;
898a56f8 4369 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4370 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4371 struct netdev_queue *txq;
4372 int index = tnapi - tp->napi;
4373
19cfaecc 4374 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4375 index--;
4376
4377 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4378
4379 while (sw_idx != hw_idx) {
f4188d8a 4380 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4381 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4382 int i, tx_bug = 0;
4383
4384 if (unlikely(skb == NULL)) {
4385 tg3_tx_recover(tp);
4386 return;
4387 }
1da177e4 4388
f4188d8a
AD		 4389 pci_unmap_single(tp->pdev,
4390 pci_unmap_addr(ri, mapping),
4391 skb_headlen(skb),
4392 PCI_DMA_TODEVICE);
1da177e4
LT		 4393
4394 ri->skb = NULL;
4395
4396 sw_idx = NEXT_TX(sw_idx);
4397
4398 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4399 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4400 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4401 tx_bug = 1;
f4188d8a
AD		 4402
4403 pci_unmap_page(tp->pdev,
4404 pci_unmap_addr(ri, mapping),
4405 skb_shinfo(skb)->frags[i].size,
4406 PCI_DMA_TODEVICE);
1da177e4
LT		 4407 sw_idx = NEXT_TX(sw_idx);
4408 }
4409
f47c11ee 4410 dev_kfree_skb(skb);
df3e6548
MC		 4411
4412 if (unlikely(tx_bug)) {
4413 tg3_tx_recover(tp);
4414 return;
4415 }
1da177e4
LT		 4416 }
4417
f3f3f27e 4418 tnapi->tx_cons = sw_idx;
1da177e4 4419
1b2a7205
MC		 4420 /* Need to make the tx_cons update visible to tg3_start_xmit()
4421 * before checking for netif_queue_stopped(). Without the
4422 * memory barrier, there is a small possibility that tg3_start_xmit()
4423 * will miss it and cause the queue to be stopped forever.
4424 */
4425 smp_mb();
4426
fe5f5787 4427 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4428 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4429 __netif_tx_lock(txq, smp_processor_id());
4430 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4431 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4432 netif_tx_wake_queue(txq);
4433 __netif_tx_unlock(txq);
51b91468 4434 }
1da177e4
LT		 4435}
4436
2b2cdb65
MC		 4437static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4438{
4439 if (!ri->skb)
4440 return;
4441
4442 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4443 map_sz, PCI_DMA_FROMDEVICE);
4444 dev_kfree_skb_any(ri->skb);
4445 ri->skb = NULL;
4446}
4447
1da177e4
LT		 4448/* Returns size of skb allocated or < 0 on error.
4449 *
4450 * We only need to fill in the address because the other members
4451 * of the RX descriptor are invariant, see tg3_init_rings.
4452 *
4453 * Note the purposeful assymetry of cpu vs. chip accesses. For
4454 * posting buffers we only dirty the first cache line of the RX
4455 * descriptor (containing the address). Whereas for the RX status
4456 * buffers the cpu only reads the last cacheline of the RX descriptor
4457 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4458 */
86b21e59 4459static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4460 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4461{
4462 struct tg3_rx_buffer_desc *desc;
4463 struct ring_info *map, *src_map;
4464 struct sk_buff *skb;
4465 dma_addr_t mapping;
4466 int skb_size, dest_idx;
4467
4468 src_map = NULL;
4469 switch (opaque_key) {
4470 case RXD_OPAQUE_RING_STD:
4471 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4472 desc = &tpr->rx_std[dest_idx];
4473 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4474 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4475 break;
4476
4477 case RXD_OPAQUE_RING_JUMBO:
4478 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4479 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4480 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4481 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4482 break;
4483
4484 default:
4485 return -EINVAL;
855e1111 4486 }
1da177e4
LT		 4487
4488 /* Do not overwrite any of the map or rp information
4489 * until we are sure we can commit to a new buffer.
4490 *
4491 * Callers depend upon this behavior and assume that
4492 * we leave everything unchanged if we fail.
4493 */
287be12e 4494 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4495 if (skb == NULL)
4496 return -ENOMEM;
4497
1da177e4
LT		 4498 skb_reserve(skb, tp->rx_offset);
4499
287be12e 4500 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4501 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4502 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4503 dev_kfree_skb(skb);
4504 return -EIO;
4505 }
1da177e4
LT		 4506
4507 map->skb = skb;
4508 pci_unmap_addr_set(map, mapping, mapping);
4509
1da177e4
LT		 4510 desc->addr_hi = ((u64)mapping >> 32);
4511 desc->addr_lo = ((u64)mapping & 0xffffffff);
4512
4513 return skb_size;
4514}
4515
4516/* We only need to move over in the address because the other
4517 * members of the RX descriptor are invariant. See notes above
4518 * tg3_alloc_rx_skb for full details.
4519 */
a3896167
MC		 4520static void tg3_recycle_rx(struct tg3_napi *tnapi,
4521 struct tg3_rx_prodring_set *dpr,
4522 u32 opaque_key, int src_idx,
4523 u32 dest_idx_unmasked)
1da177e4 4524{
17375d25 4525 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4526 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4527 struct ring_info *src_map, *dest_map;
4528 int dest_idx;
a3896167 4529 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4530
4531 switch (opaque_key) {
4532 case RXD_OPAQUE_RING_STD:
4533 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4534 dest_desc = &dpr->rx_std[dest_idx];
4535 dest_map = &dpr->rx_std_buffers[dest_idx];
4536 src_desc = &spr->rx_std[src_idx];
4537 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4538 break;
4539
4540 case RXD_OPAQUE_RING_JUMBO:
4541 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4542 dest_desc = &dpr->rx_jmb[dest_idx].std;
4543 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4544 src_desc = &spr->rx_jmb[src_idx].std;
4545 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4546 break;
4547
4548 default:
4549 return;
855e1111 4550 }
1da177e4
LT		 4551
4552 dest_map->skb = src_map->skb;
4553 pci_unmap_addr_set(dest_map, mapping,
4554 pci_unmap_addr(src_map, mapping));
4555 dest_desc->addr_hi = src_desc->addr_hi;
4556 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 4557
4558 /* Ensure that the update to the skb happens after the physical
4559 * addresses have been transferred to the new BD location.
4560 */
4561 smp_wmb();
4562
1da177e4
LT		 4563 src_map->skb = NULL;
4564}
4565
1da177e4
LT		 4566/* The RX ring scheme is composed of multiple rings which post fresh
4567 * buffers to the chip, and one special ring the chip uses to report
4568 * status back to the host.
4569 *
4570 * The special ring reports the status of received packets to the
4571 * host. The chip does not write into the original descriptor the
4572 * RX buffer was obtained from. The chip simply takes the original
4573 * descriptor as provided by the host, updates the status and length
4574 * field, then writes this into the next status ring entry.
4575 *
4576 * Each ring the host uses to post buffers to the chip is described
4577 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4578 * it is first placed into the on-chip ram. When the packet's length
4579 * is known, it walks down the TG3_BDINFO entries to select the ring.
4580 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4581 * which is within the range of the new packet's length is chosen.
4582 *
4583 * The "separate ring for rx status" scheme may sound queer, but it makes
4584 * sense from a cache coherency perspective. If only the host writes
4585 * to the buffer post rings, and only the chip writes to the rx status
4586 * rings, then cache lines never move beyond shared-modified state.
4587 * If both the host and chip were to write into the same ring, cache line
4588 * eviction could occur since both entities want it in an exclusive state.
4589 */
17375d25 4590static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4591{
17375d25 4592 struct tg3 *tp = tnapi->tp;
f92905de 4593 u32 work_mask, rx_std_posted = 0;
4361935a 4594 u32 std_prod_idx, jmb_prod_idx;
72334482 4595 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4596 u16 hw_idx;
1da177e4 4597 int received;
b196c7e4 4598 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4599
8d9d7cfc 4600 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4601 /*
4602 * We need to order the read of hw_idx and the read of
4603 * the opaque cookie.
4604 */
4605 rmb();
1da177e4
LT		 4606 work_mask = 0;
4607 received = 0;
4361935a
MC		 4608 std_prod_idx = tpr->rx_std_prod_idx;
4609 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4610 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4611 struct ring_info *ri;
72334482 4612 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4613 unsigned int len;
4614 struct sk_buff *skb;
4615 dma_addr_t dma_addr;
4616 u32 opaque_key, desc_idx, *post_ptr;
4617
4618 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4619 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4620 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4621 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4622 dma_addr = pci_unmap_addr(ri, mapping);
4623 skb = ri->skb;
4361935a 4624 post_ptr = &std_prod_idx;
f92905de 4625 rx_std_posted++;
1da177e4 4626 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4627 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4628 dma_addr = pci_unmap_addr(ri, mapping);
4629 skb = ri->skb;
4361935a 4630 post_ptr = &jmb_prod_idx;
21f581a5 4631 } else
1da177e4 4632 goto next_pkt_nopost;
1da177e4
LT		 4633
4634 work_mask |= opaque_key;
4635
4636 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4637 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4638 drop_it:
a3896167 4639 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4640 desc_idx, *post_ptr);
4641 drop_it_no_recycle:
4642 /* Other statistics kept track of by card. */
4643 tp->net_stats.rx_dropped++;
4644 goto next_pkt;
4645 }
4646
ad829268
MC		 4647 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4648 ETH_FCS_LEN;
1da177e4 4649
8e95a202
JP		 4650 if (len > RX_COPY_THRESHOLD &&
4651 tp->rx_offset == NET_IP_ALIGN) {
4652 /* rx_offset will likely not equal NET_IP_ALIGN
4653 * if this is a 5701 card running in PCI-X mode
4654 * [see tg3_get_invariants()]
4655 */
1da177e4
LT		 4656 int skb_size;
4657
86b21e59 4658 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4659 *post_ptr);
1da177e4
LT		 4660 if (skb_size < 0)
4661 goto drop_it;
4662
287be12e 4663 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4664 PCI_DMA_FROMDEVICE);
4665
61e800cf
MC		 4666 /* Ensure that the update to the skb happens
4667 * after the usage of the old DMA mapping.
4668 */
4669 smp_wmb();
4670
4671 ri->skb = NULL;
4672
1da177e4
LT		 4673 skb_put(skb, len);
4674 } else {
4675 struct sk_buff *copy_skb;
4676
a3896167 4677 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4678 desc_idx, *post_ptr);
4679
ad829268
MC		 4680 copy_skb = netdev_alloc_skb(tp->dev,
4681 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4682 if (copy_skb == NULL)
4683 goto drop_it_no_recycle;
4684
ad829268 4685 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4686 skb_put(copy_skb, len);
4687 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4688 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4689 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4690
4691 /* We'll reuse the original ring buffer. */
4692 skb = copy_skb;
4693 }
4694
4695 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4696 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4697 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4698 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4699 skb->ip_summed = CHECKSUM_UNNECESSARY;
4700 else
4701 skb->ip_summed = CHECKSUM_NONE;
4702
4703 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4704
4705 if (len > (tp->dev->mtu + ETH_HLEN) &&
4706 skb->protocol != htons(ETH_P_8021Q)) {
4707 dev_kfree_skb(skb);
4708 goto next_pkt;
4709 }
4710
1da177e4
LT		 4711#if TG3_VLAN_TAG_USED
4712 if (tp->vlgrp != NULL &&
4713 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4714 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4715 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4716 } else
4717#endif
17375d25 4718 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4719
1da177e4
LT		 4720 received++;
4721 budget--;
4722
4723next_pkt:
4724 (*post_ptr)++;
f92905de
MC		 4725
4726 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4727 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4728 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4729 tpr->rx_std_prod_idx);
f92905de
MC		 4730 work_mask &= ~RXD_OPAQUE_RING_STD;
4731 rx_std_posted = 0;
4732 }
1da177e4 4733next_pkt_nopost:
483ba50b 4734 sw_idx++;
6b31a515 4735 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4736
4737 /* Refresh hw_idx to see if there is new work */
4738 if (sw_idx == hw_idx) {
8d9d7cfc 4739 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4740 rmb();
4741 }
1da177e4
LT		 4742 }
4743
4744 /* ACK the status ring. */
72334482
MC		 4745 tnapi->rx_rcb_ptr = sw_idx;
4746 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4747
4748 /* Refill RX ring(s). */
e4af1af9 4749 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
b196c7e4
MC		 4750 if (work_mask & RXD_OPAQUE_RING_STD) {
4751 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4752 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4753 tpr->rx_std_prod_idx);
4754 }
4755 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4756 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4757 TG3_RX_JUMBO_RING_SIZE;
4758 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4759 tpr->rx_jmb_prod_idx);
4760 }
4761 mmiowb();
4762 } else if (work_mask) {
4763 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4764 * updated before the producer indices can be updated.
4765 */
4766 smp_wmb();
4767
4361935a 4768 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4769 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4 4770
e4af1af9
MC		 4771 if (tnapi != &tp->napi[1])
4772 napi_schedule(&tp->napi[1].napi);
1da177e4 4773 }
1da177e4
LT		 4774
4775 return received;
4776}
4777
35f2d7d0 4778static void tg3_poll_link(struct tg3 *tp)
1da177e4 4779{
1da177e4
LT		 4780 /* handle link change and other phy events */
4781 if (!(tp->tg3_flags &
4782 (TG3_FLAG_USE_LINKCHG_REG |
4783 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4784 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4785
1da177e4
LT		 4786 if (sblk->status & SD_STATUS_LINK_CHG) {
4787 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4788 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4789 spin_lock(&tp->lock);
dd477003
MC		 4790 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4791 tw32_f(MAC_STATUS,
4792 (MAC_STATUS_SYNC_CHANGED |
4793 MAC_STATUS_CFG_CHANGED |
4794 MAC_STATUS_MI_COMPLETION |
4795 MAC_STATUS_LNKSTATE_CHANGED));
4796 udelay(40);
4797 } else
4798 tg3_setup_phy(tp, 0);
f47c11ee 4799 spin_unlock(&tp->lock);
1da177e4
LT		 4800 }
4801 }
35f2d7d0
MC		 4802}
4803
f89f38b8
MC		 4804static int tg3_rx_prodring_xfer(struct tg3 *tp,
4805 struct tg3_rx_prodring_set *dpr,
4806 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 4807{
4808 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 4809 int i, err = 0;
b196c7e4
MC		 4810
4811 while (1) {
4812 src_prod_idx = spr->rx_std_prod_idx;
4813
4814 /* Make sure updates to the rx_std_buffers[] entries and the
4815 * standard producer index are seen in the correct order.
4816 */
4817 smp_rmb();
4818
4819 if (spr->rx_std_cons_idx == src_prod_idx)
4820 break;
4821
4822 if (spr->rx_std_cons_idx < src_prod_idx)
4823 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4824 else
4825 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4826
4827 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4828
4829 si = spr->rx_std_cons_idx;
4830 di = dpr->rx_std_prod_idx;
4831
e92967bf
MC		 4832 for (i = di; i < di + cpycnt; i++) {
4833 if (dpr->rx_std_buffers[i].skb) {
4834 cpycnt = i - di;
f89f38b8 4835 err = -ENOSPC;
e92967bf
MC		 4836 break;
4837 }
4838 }
4839
4840 if (!cpycnt)
4841 break;
4842
4843 /* Ensure that updates to the rx_std_buffers ring and the
4844 * shadowed hardware producer ring from tg3_recycle_skb() are
4845 * ordered correctly WRT the skb check above.
4846 */
4847 smp_rmb();
4848
b196c7e4
MC		 4849 memcpy(&dpr->rx_std_buffers[di],
4850 &spr->rx_std_buffers[si],
4851 cpycnt * sizeof(struct ring_info));
4852
4853 for (i = 0; i < cpycnt; i++, di++, si++) {
4854 struct tg3_rx_buffer_desc *sbd, *dbd;
4855 sbd = &spr->rx_std[si];
4856 dbd = &dpr->rx_std[di];
4857 dbd->addr_hi = sbd->addr_hi;
4858 dbd->addr_lo = sbd->addr_lo;
4859 }
4860
4861 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4862 TG3_RX_RING_SIZE;
4863 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4864 TG3_RX_RING_SIZE;
4865 }
4866
4867 while (1) {
4868 src_prod_idx = spr->rx_jmb_prod_idx;
4869
4870 /* Make sure updates to the rx_jmb_buffers[] entries and
4871 * the jumbo producer index are seen in the correct order.
4872 */
4873 smp_rmb();
4874
4875 if (spr->rx_jmb_cons_idx == src_prod_idx)
4876 break;
4877
4878 if (spr->rx_jmb_cons_idx < src_prod_idx)
4879 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4880 else
4881 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4882
4883 cpycnt = min(cpycnt,
4884 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4885
4886 si = spr->rx_jmb_cons_idx;
4887 di = dpr->rx_jmb_prod_idx;
4888
e92967bf
MC		 4889 for (i = di; i < di + cpycnt; i++) {
4890 if (dpr->rx_jmb_buffers[i].skb) {
4891 cpycnt = i - di;
f89f38b8 4892 err = -ENOSPC;
e92967bf
MC		 4893 break;
4894 }
4895 }
4896
4897 if (!cpycnt)
4898 break;
4899
4900 /* Ensure that updates to the rx_jmb_buffers ring and the
4901 * shadowed hardware producer ring from tg3_recycle_skb() are
4902 * ordered correctly WRT the skb check above.
4903 */
4904 smp_rmb();
4905
b196c7e4
MC		 4906 memcpy(&dpr->rx_jmb_buffers[di],
4907 &spr->rx_jmb_buffers[si],
4908 cpycnt * sizeof(struct ring_info));
4909
4910 for (i = 0; i < cpycnt; i++, di++, si++) {
4911 struct tg3_rx_buffer_desc *sbd, *dbd;
4912 sbd = &spr->rx_jmb[si].std;
4913 dbd = &dpr->rx_jmb[di].std;
4914 dbd->addr_hi = sbd->addr_hi;
4915 dbd->addr_lo = sbd->addr_lo;
4916 }
4917
4918 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4919 TG3_RX_JUMBO_RING_SIZE;
4920 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4921 TG3_RX_JUMBO_RING_SIZE;
4922 }
f89f38b8
MC		 4923
4924 return err;
b196c7e4
MC		 4925}
4926
35f2d7d0
MC		 4927static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4928{
4929 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4930
4931 /* run TX completion thread */
f3f3f27e 4932 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4933 tg3_tx(tnapi);
6f535763 4934 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4935 return work_done;
1da177e4
LT		 4936 }
4937
1da177e4
LT		 4938 /* run RX thread, within the bounds set by NAPI.
4939 * All RX "locking" is done by ensuring outside
bea3348e 4940 * code synchronizes with tg3->napi.poll()
1da177e4 4941 */
8d9d7cfc 4942 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4943 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4944
b196c7e4 4945 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
e4af1af9 4946 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
f89f38b8 4947 int i, err = 0;
e4af1af9
MC		 4948 u32 std_prod_idx = dpr->rx_std_prod_idx;
4949 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 4950
e4af1af9 4951 for (i = 1; i < tp->irq_cnt; i++)
f89f38b8
MC		 4952 err |= tg3_rx_prodring_xfer(tp, dpr,
4953 tp->napi[i].prodring);
b196c7e4
MC		 4954
4955 wmb();
4956
e4af1af9
MC		 4957 if (std_prod_idx != dpr->rx_std_prod_idx)
4958 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4959 dpr->rx_std_prod_idx);
b196c7e4 4960
e4af1af9
MC		 4961 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4962 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4963 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 4964
4965 mmiowb();
f89f38b8
MC		 4966
4967 if (err)
4968 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 4969 }
4970
6f535763
DM		 4971 return work_done;
4972}
4973
35f2d7d0
MC		 4974static int tg3_poll_msix(struct napi_struct *napi, int budget)
4975{
4976 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4977 struct tg3 *tp = tnapi->tp;
4978 int work_done = 0;
4979 struct tg3_hw_status *sblk = tnapi->hw_status;
4980
4981 while (1) {
4982 work_done = tg3_poll_work(tnapi, work_done, budget);
4983
4984 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4985 goto tx_recovery;
4986
4987 if (unlikely(work_done >= budget))
4988 break;
4989
4990 /* tp->last_tag is used in tg3_restart_ints() below
4991 * to tell the hw how much work has been processed,
4992 * so we must read it before checking for more work.
4993 */
4994 tnapi->last_tag = sblk->status_tag;
4995 tnapi->last_irq_tag = tnapi->last_tag;
4996 rmb();
4997
4998 /* check for RX/TX work to do */
4999 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5000 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
5001 napi_complete(napi);
5002 /* Reenable interrupts. */
5003 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5004 mmiowb();
5005 break;
5006 }
5007 }
5008
5009 return work_done;
5010
5011tx_recovery:
5012 /* work_done is guaranteed to be less than budget. */
5013 napi_complete(napi);
5014 schedule_work(&tp->reset_task);
5015 return work_done;
5016}
5017
6f535763
DM		 5018static int tg3_poll(struct napi_struct *napi, int budget)
5019{
8ef0442f
MC		 5020 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5021 struct tg3 *tp = tnapi->tp;
6f535763 5022 int work_done = 0;
898a56f8 5023 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 5024
5025 while (1) {
35f2d7d0
MC		 5026 tg3_poll_link(tp);
5027
17375d25 5028 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 5029
5030 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5031 goto tx_recovery;
5032
5033 if (unlikely(work_done >= budget))
5034 break;
5035
4fd7ab59 5036 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 5037 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 5038 * to tell the hw how much work has been processed,
5039 * so we must read it before checking for more work.
5040 */
898a56f8
MC		 5041 tnapi->last_tag = sblk->status_tag;
5042 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 5043 rmb();
5044 } else
5045 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 5046
17375d25 5047 if (likely(!tg3_has_work(tnapi))) {
288379f0 5048 napi_complete(napi);
17375d25 5049 tg3_int_reenable(tnapi);
6f535763
DM		 5050 break;
5051 }
1da177e4
LT		 5052 }
5053
bea3348e 5054 return work_done;
6f535763
DM		 5055
5056tx_recovery:
4fd7ab59 5057 /* work_done is guaranteed to be less than budget. */
288379f0 5058 napi_complete(napi);
6f535763 5059 schedule_work(&tp->reset_task);
4fd7ab59 5060 return work_done;
1da177e4
LT		 5061}
5062
f47c11ee
DM		 5063static void tg3_irq_quiesce(struct tg3 *tp)
5064{
4f125f42
MC		 5065 int i;
5066
f47c11ee
DM		 5067 BUG_ON(tp->irq_sync);
5068
5069 tp->irq_sync = 1;
5070 smp_mb();
5071
4f125f42
MC		 5072 for (i = 0; i < tp->irq_cnt; i++)
5073 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5074}
5075
5076static inline int tg3_irq_sync(struct tg3 *tp)
5077{
5078 return tp->irq_sync;
5079}
5080
5081/* Fully shutdown all tg3 driver activity elsewhere in the system.
5082 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5083 * with as well. Most of the time, this is not necessary except when
5084 * shutting down the device.
5085 */
5086static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5087{
46966545 5088 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5089 if (irq_sync)
5090 tg3_irq_quiesce(tp);
f47c11ee
DM		 5091}
5092
5093static inline void tg3_full_unlock(struct tg3 *tp)
5094{
f47c11ee
DM		 5095 spin_unlock_bh(&tp->lock);
5096}
5097
fcfa0a32
MC		 5098/* One-shot MSI handler - Chip automatically disables interrupt
5099 * after sending MSI so driver doesn't have to do it.
5100 */
7d12e780 5101static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5102{
09943a18
MC		 5103 struct tg3_napi *tnapi = dev_id;
5104 struct tg3 *tp = tnapi->tp;
fcfa0a32 5105
898a56f8 5106 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5107 if (tnapi->rx_rcb)
5108 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5109
5110 if (likely(!tg3_irq_sync(tp)))
09943a18 5111 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5112
5113 return IRQ_HANDLED;
5114}
5115
88b06bc2
MC		 5116/* MSI ISR - No need to check for interrupt sharing and no need to
5117 * flush status block and interrupt mailbox. PCI ordering rules
5118 * guarantee that MSI will arrive after the status block.
5119 */
7d12e780 5120static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5121{
09943a18
MC		 5122 struct tg3_napi *tnapi = dev_id;
5123 struct tg3 *tp = tnapi->tp;
88b06bc2 5124
898a56f8 5125 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5126 if (tnapi->rx_rcb)
5127 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5128 /*
fac9b83e 5129 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5130 * chip-internal interrupt pending events.
fac9b83e 5131 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5132 * NIC to stop sending us irqs, engaging "in-intr-handler"
5133 * event coalescing.
5134 */
5135 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5136 if (likely(!tg3_irq_sync(tp)))
09943a18 5137 napi_schedule(&tnapi->napi);
61487480 5138
88b06bc2
MC		 5139 return IRQ_RETVAL(1);
5140}
5141
7d12e780 5142static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5143{
09943a18
MC		 5144 struct tg3_napi *tnapi = dev_id;
5145 struct tg3 *tp = tnapi->tp;
898a56f8 5146 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5147 unsigned int handled = 1;
5148
1da177e4
LT		 5149 /* In INTx mode, it is possible for the interrupt to arrive at
5150 * the CPU before the status block posted prior to the interrupt.
5151 * Reading the PCI State register will confirm whether the
5152 * interrupt is ours and will flush the status block.
5153 */
d18edcb2
MC		 5154 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5155 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5156 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5157 handled = 0;
f47c11ee 5158 goto out;
fac9b83e 5159 }
d18edcb2
MC		 5160 }
5161
5162 /*
5163 * Writing any value to intr-mbox-0 clears PCI INTA# and
5164 * chip-internal interrupt pending events.
5165 * Writing non-zero to intr-mbox-0 additional tells the
5166 * NIC to stop sending us irqs, engaging "in-intr-handler"
5167 * event coalescing.
c04cb347
MC		 5168 *
5169 * Flush the mailbox to de-assert the IRQ immediately to prevent
5170 * spurious interrupts. The flush impacts performance but
5171 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5172 */
c04cb347 5173 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5174 if (tg3_irq_sync(tp))
5175 goto out;
5176 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5177 if (likely(tg3_has_work(tnapi))) {
72334482 5178 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5179 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5180 } else {
5181 /* No work, shared interrupt perhaps? re-enable
5182 * interrupts, and flush that PCI write
5183 */
5184 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5185 0x00000000);
fac9b83e 5186 }
f47c11ee 5187out:
fac9b83e
DM		 5188 return IRQ_RETVAL(handled);
5189}
5190
7d12e780 5191static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5192{
09943a18
MC		 5193 struct tg3_napi *tnapi = dev_id;
5194 struct tg3 *tp = tnapi->tp;
898a56f8 5195 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5196 unsigned int handled = 1;
5197
fac9b83e
DM		 5198 /* In INTx mode, it is possible for the interrupt to arrive at
5199 * the CPU before the status block posted prior to the interrupt.
5200 * Reading the PCI State register will confirm whether the
5201 * interrupt is ours and will flush the status block.
5202 */
898a56f8 5203 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5204 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5205 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5206 handled = 0;
f47c11ee 5207 goto out;
1da177e4 5208 }
d18edcb2
MC		 5209 }
5210
5211 /*
5212 * writing any value to intr-mbox-0 clears PCI INTA# and
5213 * chip-internal interrupt pending events.
5214 * writing non-zero to intr-mbox-0 additional tells the
5215 * NIC to stop sending us irqs, engaging "in-intr-handler"
5216 * event coalescing.
c04cb347
MC		 5217 *
5218 * Flush the mailbox to de-assert the IRQ immediately to prevent
5219 * spurious interrupts. The flush impacts performance but
5220 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5221 */
c04cb347 5222 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5223
5224 /*
5225 * In a shared interrupt configuration, sometimes other devices'
5226 * interrupts will scream. We record the current status tag here
5227 * so that the above check can report that the screaming interrupts
5228 * are unhandled. Eventually they will be silenced.
5229 */
898a56f8 5230 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5231
d18edcb2
MC		 5232 if (tg3_irq_sync(tp))
5233 goto out;
624f8e50 5234
72334482 5235 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5236
09943a18 5237 napi_schedule(&tnapi->napi);
624f8e50 5238
f47c11ee 5239out:
1da177e4
LT		 5240 return IRQ_RETVAL(handled);
5241}
5242
7938109f 5243/* ISR for interrupt test */
7d12e780 5244static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5245{
09943a18
MC		 5246 struct tg3_napi *tnapi = dev_id;
5247 struct tg3 *tp = tnapi->tp;
898a56f8 5248 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5249
f9804ddb
MC		 5250 if ((sblk->status & SD_STATUS_UPDATED) ||
5251 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5252 tg3_disable_ints(tp);
7938109f
MC		 5253 return IRQ_RETVAL(1);
5254 }
5255 return IRQ_RETVAL(0);
5256}
5257
8e7a22e3 5258static int tg3_init_hw(struct tg3 *, int);
944d980e 5259static int tg3_halt(struct tg3 *, int, int);
1da177e4 5260
b9ec6c1b
MC		 5261/* Restart hardware after configuration changes, self-test, etc.
5262 * Invoked with tp->lock held.
5263 */
5264static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5265 __releases(tp->lock)
5266 __acquires(tp->lock)
b9ec6c1b
MC		 5267{
5268 int err;
5269
5270 err = tg3_init_hw(tp, reset_phy);
5271 if (err) {
5272 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5273 "aborting.\n", tp->dev->name);
5274 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5275 tg3_full_unlock(tp);
5276 del_timer_sync(&tp->timer);
5277 tp->irq_sync = 0;
fed97810 5278 tg3_napi_enable(tp);
b9ec6c1b
MC		 5279 dev_close(tp->dev);
5280 tg3_full_lock(tp, 0);
5281 }
5282 return err;
5283}
5284
1da177e4
LT		 5285#ifdef CONFIG_NET_POLL_CONTROLLER
5286static void tg3_poll_controller(struct net_device *dev)
5287{
4f125f42 5288 int i;
88b06bc2
MC		 5289 struct tg3 *tp = netdev_priv(dev);
5290
4f125f42
MC		 5291 for (i = 0; i < tp->irq_cnt; i++)
5292 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5293}
5294#endif
5295
c4028958 5296static void tg3_reset_task(struct work_struct *work)
1da177e4 5297{
c4028958 5298 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5299 int err;
1da177e4
LT		 5300 unsigned int restart_timer;
5301
7faa006f 5302 tg3_full_lock(tp, 0);
7faa006f
MC		 5303
5304 if (!netif_running(tp->dev)) {
7faa006f
MC		 5305 tg3_full_unlock(tp);
5306 return;
5307 }
5308
5309 tg3_full_unlock(tp);
5310
b02fd9e3
MC		 5311 tg3_phy_stop(tp);
5312
1da177e4
LT		 5313 tg3_netif_stop(tp);
5314
f47c11ee 5315 tg3_full_lock(tp, 1);
1da177e4
LT		 5316
5317 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5318 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5319
df3e6548
MC		 5320 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5321 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5322 tp->write32_rx_mbox = tg3_write_flush_reg32;
5323 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5324 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5325 }
5326
944d980e 5327 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5328 err = tg3_init_hw(tp, 1);
5329 if (err)
b9ec6c1b 5330 goto out;
1da177e4
LT		 5331
5332 tg3_netif_start(tp);
5333
1da177e4
LT		 5334 if (restart_timer)
5335 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5336
b9ec6c1b 5337out:
7faa006f 5338 tg3_full_unlock(tp);
b02fd9e3
MC		 5339
5340 if (!err)
5341 tg3_phy_start(tp);
1da177e4
LT		 5342}
5343
b0408751
MC		 5344static void tg3_dump_short_state(struct tg3 *tp)
5345{
5346 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5347 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5348 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5349 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5350}
5351
1da177e4
LT		 5352static void tg3_tx_timeout(struct net_device *dev)
5353{
5354 struct tg3 *tp = netdev_priv(dev);
5355
b0408751 5356 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5357 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5358 dev->name);
b0408751
MC		 5359 tg3_dump_short_state(tp);
5360 }
1da177e4
LT		 5361
5362 schedule_work(&tp->reset_task);
5363}
5364
c58ec932
MC		 5365/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5366static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5367{
5368 u32 base = (u32) mapping & 0xffffffff;
5369
5370 return ((base > 0xffffdcc0) &&
5371 (base + len + 8 < base));
5372}
5373
72f2afb8
MC		 5374/* Test for DMA addresses > 40-bit */
5375static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5376 int len)
5377{
5378#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5379 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5380 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5381 return 0;
5382#else
5383 return 0;
5384#endif
5385}
5386
f3f3f27e 5387static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5388
72f2afb8 5389/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5390static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5391 struct sk_buff *skb, u32 last_plus_one,
5392 u32 *start, u32 base_flags, u32 mss)
1da177e4 5393{
24f4efd4 5394 struct tg3 *tp = tnapi->tp;
41588ba1 5395 struct sk_buff *new_skb;
c58ec932 5396 dma_addr_t new_addr = 0;
1da177e4 5397 u32 entry = *start;
c58ec932 5398 int i, ret = 0;
1da177e4 5399
41588ba1
MC		 5400 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5401 new_skb = skb_copy(skb, GFP_ATOMIC);
5402 else {
5403 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5404
5405 new_skb = skb_copy_expand(skb,
5406 skb_headroom(skb) + more_headroom,
5407 skb_tailroom(skb), GFP_ATOMIC);
5408 }
5409
1da177e4 5410 if (!new_skb) {
c58ec932
MC		 5411 ret = -1;
5412 } else {
5413 /* New SKB is guaranteed to be linear. */
5414 entry = *start;
f4188d8a
AD		 5415 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5416 PCI_DMA_TODEVICE);
5417 /* Make sure the mapping succeeded */
5418 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5419 ret = -1;
5420 dev_kfree_skb(new_skb);
5421 new_skb = NULL;
90079ce8 5422
c58ec932
MC		 5423 /* Make sure new skb does not cross any 4G boundaries.
5424 * Drop the packet if it does.
5425 */
f4188d8a
AD		 5426 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5427 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5428 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5429 PCI_DMA_TODEVICE);
c58ec932
MC		 5430 ret = -1;
5431 dev_kfree_skb(new_skb);
5432 new_skb = NULL;
5433 } else {
f3f3f27e 5434 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5435 base_flags, 1 | (mss << 1));
5436 *start = NEXT_TX(entry);
5437 }
1da177e4
LT		 5438 }
5439
1da177e4
LT		 5440 /* Now clean up the sw ring entries. */
5441 i = 0;
5442 while (entry != last_plus_one) {
f4188d8a
AD		 5443 int len;
5444
f3f3f27e 5445 if (i == 0)
f4188d8a 5446 len = skb_headlen(skb);
f3f3f27e 5447 else
f4188d8a
AD		 5448 len = skb_shinfo(skb)->frags[i-1].size;
5449
5450 pci_unmap_single(tp->pdev,
5451 pci_unmap_addr(&tnapi->tx_buffers[entry],
5452 mapping),
5453 len, PCI_DMA_TODEVICE);
5454 if (i == 0) {
5455 tnapi->tx_buffers[entry].skb = new_skb;
5456 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5457 new_addr);
5458 } else {
f3f3f27e 5459 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5460 }
1da177e4
LT		 5461 entry = NEXT_TX(entry);
5462 i++;
5463 }
5464
5465 dev_kfree_skb(skb);
5466
c58ec932 5467 return ret;
1da177e4
LT		 5468}
5469
f3f3f27e 5470static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5471 dma_addr_t mapping, int len, u32 flags,
5472 u32 mss_and_is_end)
5473{
f3f3f27e 5474 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5475 int is_end = (mss_and_is_end & 0x1);
5476 u32 mss = (mss_and_is_end >> 1);
5477 u32 vlan_tag = 0;
5478
5479 if (is_end)
5480 flags |= TXD_FLAG_END;
5481 if (flags & TXD_FLAG_VLAN) {
5482 vlan_tag = flags >> 16;
5483 flags &= 0xffff;
5484 }
5485 vlan_tag |= (mss << TXD_MSS_SHIFT);
5486
5487 txd->addr_hi = ((u64) mapping >> 32);
5488 txd->addr_lo = ((u64) mapping & 0xffffffff);
5489 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5490 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5491}
5492
5a6f3074 5493/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5494 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5495 */
61357325
SH		 5496static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5497 struct net_device *dev)
5a6f3074
MC		 5498{
5499 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5500 u32 len, entry, base_flags, mss;
90079ce8 5501 dma_addr_t mapping;
fe5f5787
MC		 5502 struct tg3_napi *tnapi;
5503 struct netdev_queue *txq;
f4188d8a
AD		 5504 unsigned int i, last;
5505
5a6f3074 5506
fe5f5787
MC		 5507 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5508 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5509 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5510 tnapi++;
5a6f3074 5511
00b70504 5512 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5513 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5514 * interrupt. Furthermore, IRQ processing runs lockless so we have
5515 * no IRQ context deadlocks to worry about either. Rejoice!
5516 */
f3f3f27e 5517 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5518 if (!netif_tx_queue_stopped(txq)) {
5519 netif_tx_stop_queue(txq);
5a6f3074
MC		 5520
5521 /* This is a hard error, log it. */
5522 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5523 "queue awake!\n", dev->name);
5524 }
5a6f3074
MC		 5525 return NETDEV_TX_BUSY;
5526 }
5527
f3f3f27e 5528 entry = tnapi->tx_prod;
5a6f3074 5529 base_flags = 0;
5a6f3074 5530 mss = 0;
c13e3713 5531 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5532 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5533 u32 hdrlen;
5a6f3074
MC		 5534
5535 if (skb_header_cloned(skb) &&
5536 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5537 dev_kfree_skb(skb);
5538 goto out_unlock;
5539 }
5540
b0026624 5541 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5542 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5543 else {
eddc9ec5
ACM		 5544 struct iphdr *iph = ip_hdr(skb);
5545
ab6a5bb6 5546 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5547 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5548
eddc9ec5
ACM		 5549 iph->check = 0;
5550 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5551 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5552 }
5a6f3074 5553
e849cdc3 5554 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5555 mss |= (hdrlen & 0xc) << 12;
5556 if (hdrlen & 0x10)
5557 base_flags |= 0x00000010;
5558 base_flags |= (hdrlen & 0x3e0) << 5;
5559 } else
5560 mss |= hdrlen << 9;
5561
5a6f3074
MC		 5562 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5563 TXD_FLAG_CPU_POST_DMA);
5564
aa8223c7 5565 tcp_hdr(skb)->check = 0;
5a6f3074 5566
5a6f3074 5567 }
84fa7933 5568 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5569 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5570#if TG3_VLAN_TAG_USED
5571 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5572 base_flags |= (TXD_FLAG_VLAN |
5573 (vlan_tx_tag_get(skb) << 16));
5574#endif
5575
f4188d8a
AD		 5576 len = skb_headlen(skb);
5577
5578 /* Queue skb data, a.k.a. the main skb fragment. */
5579 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5580 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5581 dev_kfree_skb(skb);
5582 goto out_unlock;
5583 }
5584
f3f3f27e 5585 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5586 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5587
b703df6f 5588 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5589 !mss && skb->len > ETH_DATA_LEN)
5590 base_flags |= TXD_FLAG_JMB_PKT;
5591
f3f3f27e 5592 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5593 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5594
5595 entry = NEXT_TX(entry);
5596
5597 /* Now loop through additional data fragments, and queue them. */
5598 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5599 last = skb_shinfo(skb)->nr_frags - 1;
5600 for (i = 0; i <= last; i++) {
5601 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5602
5603 len = frag->size;
f4188d8a
AD		 5604 mapping = pci_map_page(tp->pdev,
5605 frag->page,
5606 frag->page_offset,
5607 len, PCI_DMA_TODEVICE);
5608 if (pci_dma_mapping_error(tp->pdev, mapping))
5609 goto dma_error;
5610
f3f3f27e 5611 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5612 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5613 mapping);
5a6f3074 5614
f3f3f27e 5615 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5616 base_flags, (i == last) | (mss << 1));
5617
5618 entry = NEXT_TX(entry);
5619 }
5620 }
5621
5622 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5623 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5624
f3f3f27e
MC		 5625 tnapi->tx_prod = entry;
5626 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5627 netif_tx_stop_queue(txq);
f3f3f27e 5628 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5629 netif_tx_wake_queue(txq);
5a6f3074
MC		 5630 }
5631
5632out_unlock:
cdd0db05 5633 mmiowb();
5a6f3074
MC		 5634
5635 return NETDEV_TX_OK;
f4188d8a
AD		 5636
5637dma_error:
5638 last = i;
5639 entry = tnapi->tx_prod;
5640 tnapi->tx_buffers[entry].skb = NULL;
5641 pci_unmap_single(tp->pdev,
5642 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5643 skb_headlen(skb),
5644 PCI_DMA_TODEVICE);
5645 for (i = 0; i <= last; i++) {
5646 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5647 entry = NEXT_TX(entry);
5648
5649 pci_unmap_page(tp->pdev,
5650 pci_unmap_addr(&tnapi->tx_buffers[entry],
5651 mapping),
5652 frag->size, PCI_DMA_TODEVICE);
5653 }
5654
5655 dev_kfree_skb(skb);
5656 return NETDEV_TX_OK;
5a6f3074
MC		 5657}
5658
61357325
SH		 5659static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5660 struct net_device *);
52c0fd83
MC		 5661
5662/* Use GSO to workaround a rare TSO bug that may be triggered when the
5663 * TSO header is greater than 80 bytes.
5664 */
5665static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5666{
5667 struct sk_buff *segs, *nskb;
f3f3f27e 5668 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5669
5670 /* Estimate the number of fragments in the worst case */
f3f3f27e 5671 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5672 netif_stop_queue(tp->dev);
f3f3f27e 5673 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5674 return NETDEV_TX_BUSY;
5675
5676 netif_wake_queue(tp->dev);
52c0fd83
MC		 5677 }
5678
5679 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5680 if (IS_ERR(segs))
52c0fd83
MC		 5681 goto tg3_tso_bug_end;
5682
5683 do {
5684 nskb = segs;
5685 segs = segs->next;
5686 nskb->next = NULL;
5687 tg3_start_xmit_dma_bug(nskb, tp->dev);
5688 } while (segs);
5689
5690tg3_tso_bug_end:
5691 dev_kfree_skb(skb);
5692
5693 return NETDEV_TX_OK;
5694}
52c0fd83 5695
5a6f3074
MC		 5696/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5697 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5698 */
61357325
SH		 5699static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5700 struct net_device *dev)
1da177e4
LT		 5701{
5702 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5703 u32 len, entry, base_flags, mss;
5704 int would_hit_hwbug;
90079ce8 5705 dma_addr_t mapping;
24f4efd4
MC		 5706 struct tg3_napi *tnapi;
5707 struct netdev_queue *txq;
f4188d8a
AD		 5708 unsigned int i, last;
5709
1da177e4 5710
24f4efd4
MC		 5711 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5712 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5713 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5714 tnapi++;
1da177e4 5715
00b70504 5716 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5717 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5718 * interrupt. Furthermore, IRQ processing runs lockless so we have
5719 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5720 */
f3f3f27e 5721 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5722 if (!netif_tx_queue_stopped(txq)) {
5723 netif_tx_stop_queue(txq);
1f064a87
SH		 5724
5725 /* This is a hard error, log it. */
5726 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5727 "queue awake!\n", dev->name);
5728 }
1da177e4
LT		 5729 return NETDEV_TX_BUSY;
5730 }
5731
f3f3f27e 5732 entry = tnapi->tx_prod;
1da177e4 5733 base_flags = 0;
84fa7933 5734 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5735 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5736
c13e3713 5737 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5738 struct iphdr *iph;
92c6b8d1 5739 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5740
5741 if (skb_header_cloned(skb) &&
5742 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5743 dev_kfree_skb(skb);
5744 goto out_unlock;
5745 }
5746
ab6a5bb6 5747 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5748 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5749
52c0fd83
MC		 5750 hdr_len = ip_tcp_len + tcp_opt_len;
5751 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5752 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5753 return (tg3_tso_bug(tp, skb));
5754
1da177e4
LT		 5755 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5756 TXD_FLAG_CPU_POST_DMA);
5757
eddc9ec5
ACM		 5758 iph = ip_hdr(skb);
5759 iph->check = 0;
5760 iph->tot_len = htons(mss + hdr_len);
1da177e4 5761 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5762 tcp_hdr(skb)->check = 0;
1da177e4 5763 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5764 } else
5765 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5766 iph->daddr, 0,
5767 IPPROTO_TCP,
5768 0);
1da177e4 5769
615774fe
MC		 5770 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5771 mss |= (hdr_len & 0xc) << 12;
5772 if (hdr_len & 0x10)
5773 base_flags |= 0x00000010;
5774 base_flags |= (hdr_len & 0x3e0) << 5;
5775 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5776 mss |= hdr_len << 9;
5777 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5778 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5779 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5780 int tsflags;
5781
eddc9ec5 5782 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5783 mss |= (tsflags << 11);
5784 }
5785 } else {
eddc9ec5 5786 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5787 int tsflags;
5788
eddc9ec5 5789 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5790 base_flags |= tsflags << 12;
5791 }
5792 }
5793 }
1da177e4
LT		 5794#if TG3_VLAN_TAG_USED
5795 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5796 base_flags |= (TXD_FLAG_VLAN |
5797 (vlan_tx_tag_get(skb) << 16));
5798#endif
5799
b703df6f 5800 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5801 !mss && skb->len > ETH_DATA_LEN)
5802 base_flags |= TXD_FLAG_JMB_PKT;
5803
f4188d8a
AD		 5804 len = skb_headlen(skb);
5805
5806 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5807 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5808 dev_kfree_skb(skb);
5809 goto out_unlock;
5810 }
5811
f3f3f27e 5812 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5813 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5814
5815 would_hit_hwbug = 0;
5816
92c6b8d1
MC		 5817 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5818 would_hit_hwbug = 1;
5819
0e1406dd
MC		 5820 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5821 tg3_4g_overflow_test(mapping, len))
5822 would_hit_hwbug = 1;
5823
5824 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5825 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5826 would_hit_hwbug = 1;
0e1406dd
MC		 5827
5828 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5829 would_hit_hwbug = 1;
1da177e4 5830
f3f3f27e 5831 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5832 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5833
5834 entry = NEXT_TX(entry);
5835
5836 /* Now loop through additional data fragments, and queue them. */
5837 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5838 last = skb_shinfo(skb)->nr_frags - 1;
5839 for (i = 0; i <= last; i++) {
5840 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5841
5842 len = frag->size;
f4188d8a
AD		 5843 mapping = pci_map_page(tp->pdev,
5844 frag->page,
5845 frag->page_offset,
5846 len, PCI_DMA_TODEVICE);
1da177e4 5847
f3f3f27e 5848 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5849 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5850 mapping);
5851 if (pci_dma_mapping_error(tp->pdev, mapping))
5852 goto dma_error;
1da177e4 5853
92c6b8d1
MC		 5854 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5855 len <= 8)
5856 would_hit_hwbug = 1;
5857
0e1406dd
MC		 5858 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5859 tg3_4g_overflow_test(mapping, len))
c58ec932 5860 would_hit_hwbug = 1;
1da177e4 5861
0e1406dd
MC		 5862 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5863 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5864 would_hit_hwbug = 1;
5865
1da177e4 5866 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5867 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5868 base_flags, (i == last)|(mss << 1));
5869 else
f3f3f27e 5870 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5871 base_flags, (i == last));
5872
5873 entry = NEXT_TX(entry);
5874 }
5875 }
5876
5877 if (would_hit_hwbug) {
5878 u32 last_plus_one = entry;
5879 u32 start;
1da177e4 5880
c58ec932
MC		 5881 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5882 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5883
5884 /* If the workaround fails due to memory/mapping
5885 * failure, silently drop this packet.
5886 */
24f4efd4 5887 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5888 &start, base_flags, mss))
1da177e4
LT		 5889 goto out_unlock;
5890
5891 entry = start;
5892 }
5893
5894 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5895 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5896
f3f3f27e
MC		 5897 tnapi->tx_prod = entry;
5898 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5899 netif_tx_stop_queue(txq);
f3f3f27e 5900 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5901 netif_tx_wake_queue(txq);
51b91468 5902 }
1da177e4
LT		 5903
5904out_unlock:
cdd0db05 5905 mmiowb();
1da177e4
LT		 5906
5907 return NETDEV_TX_OK;
f4188d8a
AD		 5908
5909dma_error:
5910 last = i;
5911 entry = tnapi->tx_prod;
5912 tnapi->tx_buffers[entry].skb = NULL;
5913 pci_unmap_single(tp->pdev,
5914 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5915 skb_headlen(skb),
5916 PCI_DMA_TODEVICE);
5917 for (i = 0; i <= last; i++) {
5918 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5919 entry = NEXT_TX(entry);
5920
5921 pci_unmap_page(tp->pdev,
5922 pci_unmap_addr(&tnapi->tx_buffers[entry],
5923 mapping),
5924 frag->size, PCI_DMA_TODEVICE);
5925 }
5926
5927 dev_kfree_skb(skb);
5928 return NETDEV_TX_OK;
1da177e4
LT		 5929}
5930
5931static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5932 int new_mtu)
5933{
5934 dev->mtu = new_mtu;
5935
ef7f5ec0 5936 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5937 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5938 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5939 ethtool_op_set_tso(dev, 0);
5940 }
5941 else
5942 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5943 } else {
a4e2b347 5944 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5945 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5946 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5947 }
1da177e4
LT		 5948}
5949
5950static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5951{
5952 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5953 int err;
1da177e4
LT		 5954
5955 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5956 return -EINVAL;
5957
5958 if (!netif_running(dev)) {
5959 /* We'll just catch it later when the
5960 * device is up'd.
5961 */
5962 tg3_set_mtu(dev, tp, new_mtu);
5963 return 0;
5964 }
5965
b02fd9e3
MC		 5966 tg3_phy_stop(tp);
5967
1da177e4 5968 tg3_netif_stop(tp);
f47c11ee
DM		 5969
5970 tg3_full_lock(tp, 1);
1da177e4 5971
944d980e 5972 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5973
5974 tg3_set_mtu(dev, tp, new_mtu);
5975
b9ec6c1b 5976 err = tg3_restart_hw(tp, 0);
1da177e4 5977
b9ec6c1b
MC		 5978 if (!err)
5979 tg3_netif_start(tp);
1da177e4 5980
f47c11ee 5981 tg3_full_unlock(tp);
1da177e4 5982
b02fd9e3
MC		 5983 if (!err)
5984 tg3_phy_start(tp);
5985
b9ec6c1b 5986 return err;
1da177e4
LT		 5987}
5988
21f581a5
MC		 5989static void tg3_rx_prodring_free(struct tg3 *tp,
5990 struct tg3_rx_prodring_set *tpr)
1da177e4 5991{
1da177e4
LT		 5992 int i;
5993
b196c7e4
MC		 5994 if (tpr != &tp->prodring[0]) {
5995 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5996 i = (i + 1) % TG3_RX_RING_SIZE)
5997 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5998 tp->rx_pkt_map_sz);
5999
6000 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6001 for (i = tpr->rx_jmb_cons_idx;
6002 i != tpr->rx_jmb_prod_idx;
6003 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6004 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6005 TG3_RX_JMB_MAP_SZ);
6006 }
6007 }
6008
2b2cdb65 6009 return;
b196c7e4 6010 }
1da177e4 6011
2b2cdb65
MC		 6012 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6013 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6014 tp->rx_pkt_map_sz);
1da177e4 6015
cf7a7298 6016 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 6017 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6018 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6019 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 6020 }
6021}
6022
6023/* Initialize tx/rx rings for packet processing.
6024 *
6025 * The chip has been shut down and the driver detached from
6026 * the networking, so no interrupts or new tx packets will
6027 * end up in the driver. tp->{tx,}lock are held and thus
6028 * we may not sleep.
6029 */
21f581a5
MC		 6030static int tg3_rx_prodring_alloc(struct tg3 *tp,
6031 struct tg3_rx_prodring_set *tpr)
1da177e4 6032{
287be12e 6033 u32 i, rx_pkt_dma_sz;
1da177e4 6034
b196c7e4
MC		 6035 tpr->rx_std_cons_idx = 0;
6036 tpr->rx_std_prod_idx = 0;
6037 tpr->rx_jmb_cons_idx = 0;
6038 tpr->rx_jmb_prod_idx = 0;
6039
2b2cdb65
MC		 6040 if (tpr != &tp->prodring[0]) {
6041 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6042 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6043 memset(&tpr->rx_jmb_buffers[0], 0,
6044 TG3_RX_JMB_BUFF_RING_SIZE);
6045 goto done;
6046 }
6047
1da177e4 6048 /* Zero out all descriptors. */
21f581a5 6049 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 6050
287be12e 6051 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 6052 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 6053 tp->dev->mtu > ETH_DATA_LEN)
6054 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6055 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 6056
1da177e4
LT		 6057 /* Initialize invariants of the rings, we only set this
6058 * stuff once. This works because the card does not
6059 * write into the rx buffer posting rings.
6060 */
6061 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6062 struct tg3_rx_buffer_desc *rxd;
6063
21f581a5 6064 rxd = &tpr->rx_std[i];
287be12e 6065 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6066 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6067 rxd->opaque = (RXD_OPAQUE_RING_STD |
6068 (i << RXD_OPAQUE_INDEX_SHIFT));
6069 }
6070
1da177e4
LT		 6071 /* Now allocate fresh SKBs for each rx ring. */
6072 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6073 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6074 printk(KERN_WARNING PFX
6075 "%s: Using a smaller RX standard ring, "
6076 "only %d out of %d buffers were allocated "
6077 "successfully.\n",
6078 tp->dev->name, i, tp->rx_pending);
6079 if (i == 0)
cf7a7298 6080 goto initfail;
32d8c572 6081 tp->rx_pending = i;
1da177e4 6082 break;
32d8c572 6083 }
1da177e4
LT		 6084 }
6085
cf7a7298
MC		 6086 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6087 goto done;
6088
21f581a5 6089 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6090
0d86df80
MC		 6091 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6092 goto done;
cf7a7298 6093
0d86df80
MC		 6094 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6095 struct tg3_rx_buffer_desc *rxd;
6096
6097 rxd = &tpr->rx_jmb[i].std;
6098 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6099 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6100 RXD_FLAG_JUMBO;
6101 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6102 (i << RXD_OPAQUE_INDEX_SHIFT));
6103 }
6104
6105 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6106 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6107 printk(KERN_WARNING PFX
6108 "%s: Using a smaller RX jumbo ring, "
6109 "only %d out of %d buffers were "
6110 "allocated successfully.\n",
6111 tp->dev->name, i, tp->rx_jumbo_pending);
6112 if (i == 0)
6113 goto initfail;
6114 tp->rx_jumbo_pending = i;
6115 break;
1da177e4
LT		 6116 }
6117 }
cf7a7298
MC		 6118
6119done:
32d8c572 6120 return 0;
cf7a7298
MC		 6121
6122initfail:
21f581a5 6123 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6124 return -ENOMEM;
1da177e4
LT		 6125}
6126
21f581a5
MC		 6127static void tg3_rx_prodring_fini(struct tg3 *tp,
6128 struct tg3_rx_prodring_set *tpr)
1da177e4 6129{
21f581a5
MC		 6130 kfree(tpr->rx_std_buffers);
6131 tpr->rx_std_buffers = NULL;
6132 kfree(tpr->rx_jmb_buffers);
6133 tpr->rx_jmb_buffers = NULL;
6134 if (tpr->rx_std) {
1da177e4 6135 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6136 tpr->rx_std, tpr->rx_std_mapping);
6137 tpr->rx_std = NULL;
1da177e4 6138 }
21f581a5 6139 if (tpr->rx_jmb) {
1da177e4 6140 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6141 tpr->rx_jmb, tpr->rx_jmb_mapping);
6142 tpr->rx_jmb = NULL;
1da177e4 6143 }
cf7a7298
MC		 6144}
6145
21f581a5
MC		 6146static int tg3_rx_prodring_init(struct tg3 *tp,
6147 struct tg3_rx_prodring_set *tpr)
cf7a7298 6148{
2b2cdb65 6149 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6150 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6151 return -ENOMEM;
6152
21f581a5
MC		 6153 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6154 &tpr->rx_std_mapping);
6155 if (!tpr->rx_std)
cf7a7298
MC		 6156 goto err_out;
6157
6158 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6159 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6160 GFP_KERNEL);
6161 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6162 goto err_out;
6163
21f581a5
MC		 6164 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6165 TG3_RX_JUMBO_RING_BYTES,
6166 &tpr->rx_jmb_mapping);
6167 if (!tpr->rx_jmb)
cf7a7298
MC		 6168 goto err_out;
6169 }
6170
6171 return 0;
6172
6173err_out:
21f581a5 6174 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6175 return -ENOMEM;
6176}
6177
6178/* Free up pending packets in all rx/tx rings.
6179 *
6180 * The chip has been shut down and the driver detached from
6181 * the networking, so no interrupts or new tx packets will
6182 * end up in the driver. tp->{tx,}lock is not held and we are not
6183 * in an interrupt context and thus may sleep.
6184 */
6185static void tg3_free_rings(struct tg3 *tp)
6186{
f77a6a8e 6187 int i, j;
cf7a7298 6188
f77a6a8e
MC		 6189 for (j = 0; j < tp->irq_cnt; j++) {
6190 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6191
0c1d0e2b
MC		 6192 if (!tnapi->tx_buffers)
6193 continue;
6194
f77a6a8e 6195 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6196 struct ring_info *txp;
f77a6a8e 6197 struct sk_buff *skb;
f4188d8a 6198 unsigned int k;
cf7a7298 6199
f77a6a8e
MC		 6200 txp = &tnapi->tx_buffers[i];
6201 skb = txp->skb;
cf7a7298 6202
f77a6a8e
MC		 6203 if (skb == NULL) {
6204 i++;
6205 continue;
6206 }
cf7a7298 6207
f4188d8a
AD		 6208 pci_unmap_single(tp->pdev,
6209 pci_unmap_addr(txp, mapping),
6210 skb_headlen(skb),
6211 PCI_DMA_TODEVICE);
f77a6a8e 6212 txp->skb = NULL;
cf7a7298 6213
f4188d8a
AD		 6214 i++;
6215
6216 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6217 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6218 pci_unmap_page(tp->pdev,
6219 pci_unmap_addr(txp, mapping),
6220 skb_shinfo(skb)->frags[k].size,
6221 PCI_DMA_TODEVICE);
6222 i++;
6223 }
f77a6a8e
MC		 6224
6225 dev_kfree_skb_any(skb);
6226 }
cf7a7298 6227
e4af1af9 6228 tg3_rx_prodring_free(tp, &tp->prodring[j]);
2b2cdb65 6229 }
cf7a7298
MC		 6230}
6231
6232/* Initialize tx/rx rings for packet processing.
6233 *
6234 * The chip has been shut down and the driver detached from
6235 * the networking, so no interrupts or new tx packets will
6236 * end up in the driver. tp->{tx,}lock are held and thus
6237 * we may not sleep.
6238 */
6239static int tg3_init_rings(struct tg3 *tp)
6240{
f77a6a8e 6241 int i;
72334482 6242
cf7a7298
MC		 6243 /* Free up all the SKBs. */
6244 tg3_free_rings(tp);
6245
f77a6a8e
MC		 6246 for (i = 0; i < tp->irq_cnt; i++) {
6247 struct tg3_napi *tnapi = &tp->napi[i];
6248
6249 tnapi->last_tag = 0;
6250 tnapi->last_irq_tag = 0;
6251 tnapi->hw_status->status = 0;
6252 tnapi->hw_status->status_tag = 0;
6253 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6254
f77a6a8e
MC		 6255 tnapi->tx_prod = 0;
6256 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6257 if (tnapi->tx_ring)
6258 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6259
6260 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6261 if (tnapi->rx_rcb)
6262 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 6263
e4af1af9
MC		 6264 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6265 tg3_free_rings(tp);
2b2cdb65 6266 return -ENOMEM;
e4af1af9 6267 }
f77a6a8e 6268 }
72334482 6269
2b2cdb65 6270 return 0;
cf7a7298
MC		 6271}
6272
6273/*
6274 * Must not be invoked with interrupt sources disabled and
6275 * the hardware shutdown down.
6276 */
6277static void tg3_free_consistent(struct tg3 *tp)
6278{
f77a6a8e 6279 int i;
898a56f8 6280
f77a6a8e
MC		 6281 for (i = 0; i < tp->irq_cnt; i++) {
6282 struct tg3_napi *tnapi = &tp->napi[i];
6283
6284 if (tnapi->tx_ring) {
6285 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6286 tnapi->tx_ring, tnapi->tx_desc_mapping);
6287 tnapi->tx_ring = NULL;
6288 }
6289
6290 kfree(tnapi->tx_buffers);
6291 tnapi->tx_buffers = NULL;
6292
6293 if (tnapi->rx_rcb) {
6294 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6295 tnapi->rx_rcb,
6296 tnapi->rx_rcb_mapping);
6297 tnapi->rx_rcb = NULL;
6298 }
6299
6300 if (tnapi->hw_status) {
6301 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6302 tnapi->hw_status,
6303 tnapi->status_mapping);
6304 tnapi->hw_status = NULL;
6305 }
1da177e4 6306 }
f77a6a8e 6307
1da177e4
LT		 6308 if (tp->hw_stats) {
6309 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6310 tp->hw_stats, tp->stats_mapping);
6311 tp->hw_stats = NULL;
6312 }
f77a6a8e 6313
e4af1af9 6314 for (i = 0; i < tp->irq_cnt; i++)
2b2cdb65 6315 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6316}
6317
6318/*
6319 * Must not be invoked with interrupt sources disabled and
6320 * the hardware shutdown down. Can sleep.
6321 */
6322static int tg3_alloc_consistent(struct tg3 *tp)
6323{
f77a6a8e 6324 int i;
898a56f8 6325
e4af1af9 6326 for (i = 0; i < tp->irq_cnt; i++) {
2b2cdb65
MC		 6327 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6328 goto err_out;
6329 }
1da177e4 6330
f77a6a8e
MC		 6331 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6332 sizeof(struct tg3_hw_stats),
6333 &tp->stats_mapping);
6334 if (!tp->hw_stats)
1da177e4
LT		 6335 goto err_out;
6336
f77a6a8e 6337 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6338
f77a6a8e
MC		 6339 for (i = 0; i < tp->irq_cnt; i++) {
6340 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6341 struct tg3_hw_status *sblk;
1da177e4 6342
f77a6a8e
MC		 6343 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6344 TG3_HW_STATUS_SIZE,
6345 &tnapi->status_mapping);
6346 if (!tnapi->hw_status)
6347 goto err_out;
898a56f8 6348
f77a6a8e 6349 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6350 sblk = tnapi->hw_status;
6351
19cfaecc
MC		 6352 /* If multivector TSS is enabled, vector 0 does not handle
6353 * tx interrupts. Don't allocate any resources for it.
6354 */
6355 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6356 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6357 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6358 TG3_TX_RING_SIZE,
6359 GFP_KERNEL);
6360 if (!tnapi->tx_buffers)
6361 goto err_out;
6362
6363 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6364 TG3_TX_RING_BYTES,
6365 &tnapi->tx_desc_mapping);
6366 if (!tnapi->tx_ring)
6367 goto err_out;
6368 }
6369
8d9d7cfc
MC		 6370 /*
6371 * When RSS is enabled, the status block format changes
6372 * slightly. The "rx_jumbo_consumer", "reserved",
6373 * and "rx_mini_consumer" members get mapped to the
6374 * other three rx return ring producer indexes.
6375 */
6376 switch (i) {
6377 default:
6378 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6379 break;
6380 case 2:
6381 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6382 break;
6383 case 3:
6384 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6385 break;
6386 case 4:
6387 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6388 break;
6389 }
72334482 6390
e4af1af9 6391 tnapi->prodring = &tp->prodring[i];
b196c7e4 6392
0c1d0e2b
MC		 6393 /*
6394 * If multivector RSS is enabled, vector 0 does not handle
6395 * rx or tx interrupts. Don't allocate any resources for it.
6396 */
6397 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6398 continue;
6399
f77a6a8e
MC		 6400 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6401 TG3_RX_RCB_RING_BYTES(tp),
6402 &tnapi->rx_rcb_mapping);
6403 if (!tnapi->rx_rcb)
6404 goto err_out;
72334482 6405
f77a6a8e 6406 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6407 }
1da177e4
LT		 6408
6409 return 0;
6410
6411err_out:
6412 tg3_free_consistent(tp);
6413 return -ENOMEM;
6414}
6415
6416#define MAX_WAIT_CNT 1000
6417
6418/* To stop a block, clear the enable bit and poll till it
6419 * clears. tp->lock is held.
6420 */
b3b7d6be 6421static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6422{
6423 unsigned int i;
6424 u32 val;
6425
6426 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6427 switch (ofs) {
6428 case RCVLSC_MODE:
6429 case DMAC_MODE:
6430 case MBFREE_MODE:
6431 case BUFMGR_MODE:
6432 case MEMARB_MODE:
6433 /* We can't enable/disable these bits of the
6434 * 5705/5750, just say success.
6435 */
6436 return 0;
6437
6438 default:
6439 break;
855e1111 6440 }
1da177e4
LT		 6441 }
6442
6443 val = tr32(ofs);
6444 val &= ~enable_bit;
6445 tw32_f(ofs, val);
6446
6447 for (i = 0; i < MAX_WAIT_CNT; i++) {
6448 udelay(100);
6449 val = tr32(ofs);
6450 if ((val & enable_bit) == 0)
6451 break;
6452 }
6453
b3b7d6be 6454 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6455 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6456 "ofs=%lx enable_bit=%x\n",
6457 ofs, enable_bit);
6458 return -ENODEV;
6459 }
6460
6461 return 0;
6462}
6463
6464/* tp->lock is held. */
b3b7d6be 6465static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6466{
6467 int i, err;
6468
6469 tg3_disable_ints(tp);
6470
6471 tp->rx_mode &= ~RX_MODE_ENABLE;
6472 tw32_f(MAC_RX_MODE, tp->rx_mode);
6473 udelay(10);
6474
b3b7d6be
DM		 6475 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6476 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6480 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6481
6482 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6483 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6484 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6485 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6486 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6487 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6488 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6489
6490 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6491 tw32_f(MAC_MODE, tp->mac_mode);
6492 udelay(40);
6493
6494 tp->tx_mode &= ~TX_MODE_ENABLE;
6495 tw32_f(MAC_TX_MODE, tp->tx_mode);
6496
6497 for (i = 0; i < MAX_WAIT_CNT; i++) {
6498 udelay(100);
6499 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6500 break;
6501 }
6502 if (i >= MAX_WAIT_CNT) {
6503 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6504 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6505 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6506 err |= -ENODEV;
1da177e4
LT		 6507 }
6508
e6de8ad1 6509 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6510 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6511 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6512
6513 tw32(FTQ_RESET, 0xffffffff);
6514 tw32(FTQ_RESET, 0x00000000);
6515
b3b7d6be
DM		 6516 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6517 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6518
f77a6a8e
MC		 6519 for (i = 0; i < tp->irq_cnt; i++) {
6520 struct tg3_napi *tnapi = &tp->napi[i];
6521 if (tnapi->hw_status)
6522 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6523 }
1da177e4
LT		 6524 if (tp->hw_stats)
6525 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6526
1da177e4
LT		 6527 return err;
6528}
6529
0d3031d9
MC		 6530static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6531{
6532 int i;
6533 u32 apedata;
6534
6535 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6536 if (apedata != APE_SEG_SIG_MAGIC)
6537 return;
6538
6539 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6540 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6541 return;
6542
6543 /* Wait for up to 1 millisecond for APE to service previous event. */
6544 for (i = 0; i < 10; i++) {
6545 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6546 return;
6547
6548 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6549
6550 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6551 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6552 event | APE_EVENT_STATUS_EVENT_PENDING);
6553
6554 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6555
6556 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6557 break;
6558
6559 udelay(100);
6560 }
6561
6562 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6563 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6564}
6565
6566static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6567{
6568 u32 event;
6569 u32 apedata;
6570
6571 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6572 return;
6573
6574 switch (kind) {
6575 case RESET_KIND_INIT:
6576 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6577 APE_HOST_SEG_SIG_MAGIC);
6578 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6579 APE_HOST_SEG_LEN_MAGIC);
6580 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6581 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6582 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6583 APE_HOST_DRIVER_ID_MAGIC);
6584 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6585 APE_HOST_BEHAV_NO_PHYLOCK);
6586
6587 event = APE_EVENT_STATUS_STATE_START;
6588 break;
6589 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6590 /* With the interface we are currently using,
6591 * APE does not track driver state. Wiping
6592 * out the HOST SEGMENT SIGNATURE forces
6593 * the APE to assume OS absent status.
6594 */
6595 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6596
0d3031d9
MC		 6597 event = APE_EVENT_STATUS_STATE_UNLOAD;
6598 break;
6599 case RESET_KIND_SUSPEND:
6600 event = APE_EVENT_STATUS_STATE_SUSPEND;
6601 break;
6602 default:
6603 return;
6604 }
6605
6606 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6607
6608 tg3_ape_send_event(tp, event);
6609}
6610
1da177e4
LT		 6611/* tp->lock is held. */
6612static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6613{
f49639e6
DM		 6614 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6615 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6616
6617 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6618 switch (kind) {
6619 case RESET_KIND_INIT:
6620 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6621 DRV_STATE_START);
6622 break;
6623
6624 case RESET_KIND_SHUTDOWN:
6625 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6626 DRV_STATE_UNLOAD);
6627 break;
6628
6629 case RESET_KIND_SUSPEND:
6630 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6631 DRV_STATE_SUSPEND);
6632 break;
6633
6634 default:
6635 break;
855e1111 6636 }
1da177e4 6637 }
0d3031d9
MC		 6638
6639 if (kind == RESET_KIND_INIT ||
6640 kind == RESET_KIND_SUSPEND)
6641 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6642}
6643
6644/* tp->lock is held. */
6645static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6646{
6647 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6648 switch (kind) {
6649 case RESET_KIND_INIT:
6650 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6651 DRV_STATE_START_DONE);
6652 break;
6653
6654 case RESET_KIND_SHUTDOWN:
6655 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6656 DRV_STATE_UNLOAD_DONE);
6657 break;
6658
6659 default:
6660 break;
855e1111 6661 }
1da177e4 6662 }
0d3031d9
MC		 6663
6664 if (kind == RESET_KIND_SHUTDOWN)
6665 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6666}
6667
6668/* tp->lock is held. */
6669static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6670{
6671 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6672 switch (kind) {
6673 case RESET_KIND_INIT:
6674 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6675 DRV_STATE_START);
6676 break;
6677
6678 case RESET_KIND_SHUTDOWN:
6679 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6680 DRV_STATE_UNLOAD);
6681 break;
6682
6683 case RESET_KIND_SUSPEND:
6684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6685 DRV_STATE_SUSPEND);
6686 break;
6687
6688 default:
6689 break;
855e1111 6690 }
1da177e4
LT		 6691 }
6692}
6693
7a6f4369
MC		 6694static int tg3_poll_fw(struct tg3 *tp)
6695{
6696 int i;
6697 u32 val;
6698
b5d3772c 6699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6700 /* Wait up to 20ms for init done. */
6701 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6702 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6703 return 0;
0ccead18 6704 udelay(100);
b5d3772c
MC		 6705 }
6706 return -ENODEV;
6707 }
6708
7a6f4369
MC		 6709 /* Wait for firmware initialization to complete. */
6710 for (i = 0; i < 100000; i++) {
6711 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6712 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6713 break;
6714 udelay(10);
6715 }
6716
6717 /* Chip might not be fitted with firmware. Some Sun onboard
6718 * parts are configured like that. So don't signal the timeout
6719 * of the above loop as an error, but do report the lack of
6720 * running firmware once.
6721 */
6722 if (i >= 100000 &&
6723 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6724 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6725
6726 printk(KERN_INFO PFX "%s: No firmware running.\n",
6727 tp->dev->name);
6728 }
6729
6b10c165
MC		 6730 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6731 /* The 57765 A0 needs a little more
6732 * time to do some important work.
6733 */
6734 mdelay(10);
6735 }
6736
7a6f4369
MC		 6737 return 0;
6738}
6739
ee6a99b5
MC		 6740/* Save PCI command register before chip reset */
6741static void tg3_save_pci_state(struct tg3 *tp)
6742{
8a6eac90 6743 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6744}
6745
6746/* Restore PCI state after chip reset */
6747static void tg3_restore_pci_state(struct tg3 *tp)
6748{
6749 u32 val;
6750
6751 /* Re-enable indirect register accesses. */
6752 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6753 tp->misc_host_ctrl);
6754
6755 /* Set MAX PCI retry to zero. */
6756 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6757 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6758 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6759 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6760 /* Allow reads and writes to the APE register and memory space. */
6761 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6762 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6763 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6764 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6765
8a6eac90 6766 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6767
fcb389df
MC		 6768 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6769 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6770 pcie_set_readrq(tp->pdev, 4096);
6771 else {
6772 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6773 tp->pci_cacheline_sz);
6774 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6775 tp->pci_lat_timer);
6776 }
114342f2 6777 }
5f5c51e3 6778
ee6a99b5 6779 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6780 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6781 u16 pcix_cmd;
6782
6783 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6784 &pcix_cmd);
6785 pcix_cmd &= ~PCI_X_CMD_ERO;
6786 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6787 pcix_cmd);
6788 }
ee6a99b5
MC		 6789
6790 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6791
6792 /* Chip reset on 5780 will reset MSI enable bit,
6793 * so need to restore it.
6794 */
6795 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6796 u16 ctrl;
6797
6798 pci_read_config_word(tp->pdev,
6799 tp->msi_cap + PCI_MSI_FLAGS,
6800 &ctrl);
6801 pci_write_config_word(tp->pdev,
6802 tp->msi_cap + PCI_MSI_FLAGS,
6803 ctrl | PCI_MSI_FLAGS_ENABLE);
6804 val = tr32(MSGINT_MODE);
6805 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6806 }
6807 }
6808}
6809
1da177e4
LT		 6810static void tg3_stop_fw(struct tg3 *);
6811
6812/* tp->lock is held. */
6813static int tg3_chip_reset(struct tg3 *tp)
6814{
6815 u32 val;
1ee582d8 6816 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6817 int i, err;
1da177e4 6818
f49639e6
DM		 6819 tg3_nvram_lock(tp);
6820
77b483f1
MC		 6821 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6822
f49639e6
DM		 6823 /* No matching tg3_nvram_unlock() after this because
6824 * chip reset below will undo the nvram lock.
6825 */
6826 tp->nvram_lock_cnt = 0;
1da177e4 6827
ee6a99b5
MC		 6828 /* GRC_MISC_CFG core clock reset will clear the memory
6829 * enable bit in PCI register 4 and the MSI enable bit
6830 * on some chips, so we save relevant registers here.
6831 */
6832 tg3_save_pci_state(tp);
6833
d9ab5ad1 6834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6835 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6836 tw32(GRC_FASTBOOT_PC, 0);
6837
1da177e4
LT		 6838 /*
6839 * We must avoid the readl() that normally takes place.
6840 * It locks machines, causes machine checks, and other
6841 * fun things. So, temporarily disable the 5701
6842 * hardware workaround, while we do the reset.
6843 */
1ee582d8
MC		 6844 write_op = tp->write32;
6845 if (write_op == tg3_write_flush_reg32)
6846 tp->write32 = tg3_write32;
1da177e4 6847
d18edcb2
MC		 6848 /* Prevent the irq handler from reading or writing PCI registers
6849 * during chip reset when the memory enable bit in the PCI command
6850 * register may be cleared. The chip does not generate interrupt
6851 * at this time, but the irq handler may still be called due to irq
6852 * sharing or irqpoll.
6853 */
6854 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6855 for (i = 0; i < tp->irq_cnt; i++) {
6856 struct tg3_napi *tnapi = &tp->napi[i];
6857 if (tnapi->hw_status) {
6858 tnapi->hw_status->status = 0;
6859 tnapi->hw_status->status_tag = 0;
6860 }
6861 tnapi->last_tag = 0;
6862 tnapi->last_irq_tag = 0;
b8fa2f3a 6863 }
d18edcb2 6864 smp_mb();
4f125f42
MC		 6865
6866 for (i = 0; i < tp->irq_cnt; i++)
6867 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6868
255ca311
MC		 6869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6870 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6871 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6872 }
6873
1da177e4
LT		 6874 /* do the reset */
6875 val = GRC_MISC_CFG_CORECLK_RESET;
6876
6877 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6878 if (tr32(0x7e2c) == 0x60) {
6879 tw32(0x7e2c, 0x20);
6880 }
6881 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6882 tw32(GRC_MISC_CFG, (1 << 29));
6883 val |= (1 << 29);
6884 }
6885 }
6886
b5d3772c
MC		 6887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6888 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6889 tw32(GRC_VCPU_EXT_CTRL,
6890 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6891 }
6892
1da177e4
LT		 6893 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6894 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6895 tw32(GRC_MISC_CFG, val);
6896
1ee582d8
MC		 6897 /* restore 5701 hardware bug workaround write method */
6898 tp->write32 = write_op;
1da177e4
LT		 6899
6900 /* Unfortunately, we have to delay before the PCI read back.
6901 * Some 575X chips even will not respond to a PCI cfg access
6902 * when the reset command is given to the chip.
6903 *
6904 * How do these hardware designers expect things to work
6905 * properly if the PCI write is posted for a long period
6906 * of time? It is always necessary to have some method by
6907 * which a register read back can occur to push the write
6908 * out which does the reset.
6909 *
6910 * For most tg3 variants the trick below was working.
6911 * Ho hum...
6912 */
6913 udelay(120);
6914
6915 /* Flush PCI posted writes. The normal MMIO registers
6916 * are inaccessible at this time so this is the only
6917 * way to make this reliably (actually, this is no longer
6918 * the case, see above). I tried to use indirect
6919 * register read/write but this upset some 5701 variants.
6920 */
6921 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6922
6923 udelay(120);
6924
5e7dfd0f 6925 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6926 u16 val16;
6927
1da177e4
LT		 6928 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6929 int i;
6930 u32 cfg_val;
6931
6932 /* Wait for link training to complete. */
6933 for (i = 0; i < 5000; i++)
6934 udelay(100);
6935
6936 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6937 pci_write_config_dword(tp->pdev, 0xc4,
6938 cfg_val | (1 << 15));
6939 }
5e7dfd0f 6940
e7126997
MC		 6941 /* Clear the "no snoop" and "relaxed ordering" bits. */
6942 pci_read_config_word(tp->pdev,
6943 tp->pcie_cap + PCI_EXP_DEVCTL,
6944 &val16);
6945 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6946 PCI_EXP_DEVCTL_NOSNOOP_EN);
6947 /*
6948 * Older PCIe devices only support the 128 byte
6949 * MPS setting. Enforce the restriction.
5e7dfd0f 6950 */
e7126997
MC		 6951 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6953 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6954 pci_write_config_word(tp->pdev,
6955 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6956 val16);
5e7dfd0f
MC		 6957
6958 pcie_set_readrq(tp->pdev, 4096);
6959
6960 /* Clear error status */
6961 pci_write_config_word(tp->pdev,
6962 tp->pcie_cap + PCI_EXP_DEVSTA,
6963 PCI_EXP_DEVSTA_CED |
6964 PCI_EXP_DEVSTA_NFED |
6965 PCI_EXP_DEVSTA_FED |
6966 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6967 }
6968
ee6a99b5 6969 tg3_restore_pci_state(tp);
1da177e4 6970
d18edcb2
MC		 6971 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6972
ee6a99b5
MC		 6973 val = 0;
6974 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6975 val = tr32(MEMARB_MODE);
ee6a99b5 6976 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6977
6978 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6979 tg3_stop_fw(tp);
6980 tw32(0x5000, 0x400);
6981 }
6982
6983 tw32(GRC_MODE, tp->grc_mode);
6984
6985 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6986 val = tr32(0xc4);
1da177e4
LT		 6987
6988 tw32(0xc4, val | (1 << 15));
6989 }
6990
6991 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6993 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6994 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6995 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6996 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6997 }
6998
6999 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7000 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7001 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 7002 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7003 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7004 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 7005 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7006 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7007 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7008 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7009 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 7010 } else
7011 tw32_f(MAC_MODE, 0);
7012 udelay(40);
7013
77b483f1
MC		 7014 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7015
7a6f4369
MC		 7016 err = tg3_poll_fw(tp);
7017 if (err)
7018 return err;
1da177e4 7019
0a9140cf
MC		 7020 tg3_mdio_start(tp);
7021
52cdf852
MC		 7022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7023 u8 phy_addr;
7024
7025 phy_addr = tp->phy_addr;
7026 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7027
7028 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7029 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7030 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7031 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7032 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7033 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7034 udelay(10);
7035
7036 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7037 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7038 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7039 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7040 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7041 udelay(10);
7042
7043 tp->phy_addr = phy_addr;
7044 }
7045
1da177e4 7046 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 7047 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7048 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 7049 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7050 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 7051 val = tr32(0x7c00);
1da177e4
LT		 7052
7053 tw32(0x7c00, val | (1 << 25));
7054 }
7055
7056 /* Reprobe ASF enable state. */
7057 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7058 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7059 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7060 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7061 u32 nic_cfg;
7062
7063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7064 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7065 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 7066 tp->last_event_jiffies = jiffies;
cbf46853 7067 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7068 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7069 }
7070 }
7071
7072 return 0;
7073}
7074
7075/* tp->lock is held. */
7076static void tg3_stop_fw(struct tg3 *tp)
7077{
0d3031d9
MC		 7078 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7079 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7080 /* Wait for RX cpu to ACK the previous event. */
7081 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7082
7083 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7084
7085 tg3_generate_fw_event(tp);
1da177e4 7086
7c5026aa
MC		 7087 /* Wait for RX cpu to ACK this event. */
7088 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7089 }
7090}
7091
7092/* tp->lock is held. */
944d980e 7093static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7094{
7095 int err;
7096
7097 tg3_stop_fw(tp);
7098
944d980e 7099 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7100
b3b7d6be 7101 tg3_abort_hw(tp, silent);
1da177e4
LT		 7102 err = tg3_chip_reset(tp);
7103
daba2a63
MC		 7104 __tg3_set_mac_addr(tp, 0);
7105
944d980e
MC		 7106 tg3_write_sig_legacy(tp, kind);
7107 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7108
7109 if (err)
7110 return err;
7111
7112 return 0;
7113}
7114
1da177e4
LT		 7115#define RX_CPU_SCRATCH_BASE 0x30000
7116#define RX_CPU_SCRATCH_SIZE 0x04000
7117#define TX_CPU_SCRATCH_BASE 0x34000
7118#define TX_CPU_SCRATCH_SIZE 0x04000
7119
7120/* tp->lock is held. */
7121static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7122{
7123 int i;
7124
5d9428de
ES		 7125 BUG_ON(offset == TX_CPU_BASE &&
7126 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7127
b5d3772c
MC		 7128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7129 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7130
7131 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7132 return 0;
7133 }
1da177e4
LT		 7134 if (offset == RX_CPU_BASE) {
7135 for (i = 0; i < 10000; i++) {
7136 tw32(offset + CPU_STATE, 0xffffffff);
7137 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7138 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7139 break;
7140 }
7141
7142 tw32(offset + CPU_STATE, 0xffffffff);
7143 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7144 udelay(10);
7145 } else {
7146 for (i = 0; i < 10000; i++) {
7147 tw32(offset + CPU_STATE, 0xffffffff);
7148 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7149 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7150 break;
7151 }
7152 }
7153
7154 if (i >= 10000) {
7155 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7156 "and %s CPU\n",
7157 tp->dev->name,
7158 (offset == RX_CPU_BASE ? "RX" : "TX"));
7159 return -ENODEV;
7160 }
ec41c7df
MC		 7161
7162 /* Clear firmware's nvram arbitration. */
7163 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7164 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7165 return 0;
7166}
7167
7168struct fw_info {
077f849d
JSR		 7169 unsigned int fw_base;
7170 unsigned int fw_len;
7171 const __be32 *fw_data;
1da177e4
LT		 7172};
7173
7174/* tp->lock is held. */
7175static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7176 int cpu_scratch_size, struct fw_info *info)
7177{
ec41c7df 7178 int err, lock_err, i;
1da177e4
LT		 7179 void (*write_op)(struct tg3 *, u32, u32);
7180
7181 if (cpu_base == TX_CPU_BASE &&
7182 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7183 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7184 "TX cpu firmware on %s which is 5705.\n",
7185 tp->dev->name);
7186 return -EINVAL;
7187 }
7188
7189 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7190 write_op = tg3_write_mem;
7191 else
7192 write_op = tg3_write_indirect_reg32;
7193
1b628151
MC		 7194 /* It is possible that bootcode is still loading at this point.
7195 * Get the nvram lock first before halting the cpu.
7196 */
ec41c7df 7197 lock_err = tg3_nvram_lock(tp);
1da177e4 7198 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7199 if (!lock_err)
7200 tg3_nvram_unlock(tp);
1da177e4
LT		 7201 if (err)
7202 goto out;
7203
7204 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7205 write_op(tp, cpu_scratch_base + i, 0);
7206 tw32(cpu_base + CPU_STATE, 0xffffffff);
7207 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7208 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7209 write_op(tp, (cpu_scratch_base +
077f849d 7210 (info->fw_base & 0xffff) +
1da177e4 7211 (i * sizeof(u32))),
077f849d 7212 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7213
7214 err = 0;
7215
7216out:
1da177e4
LT		 7217 return err;
7218}
7219
7220/* tp->lock is held. */
7221static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7222{
7223 struct fw_info info;
077f849d 7224 const __be32 *fw_data;
1da177e4
LT		 7225 int err, i;
7226
077f849d
JSR		 7227 fw_data = (void *)tp->fw->data;
7228
7229 /* Firmware blob starts with version numbers, followed by
7230 start address and length. We are setting complete length.
7231 length = end_address_of_bss - start_address_of_text.
7232 Remainder is the blob to be loaded contiguously
7233 from start address. */
7234
7235 info.fw_base = be32_to_cpu(fw_data[1]);
7236 info.fw_len = tp->fw->size - 12;
7237 info.fw_data = &fw_data[3];
1da177e4
LT		 7238
7239 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7240 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7241 &info);
7242 if (err)
7243 return err;
7244
7245 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7246 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7247 &info);
7248 if (err)
7249 return err;
7250
7251 /* Now startup only the RX cpu. */
7252 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7253 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7254
7255 for (i = 0; i < 5; i++) {
077f849d 7256 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7257 break;
7258 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7259 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7260 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7261 udelay(1000);
7262 }
7263 if (i >= 5) {
7264 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7265 "to set RX CPU PC, is %08x should be %08x\n",
7266 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7267 info.fw_base);
1da177e4
LT		 7268 return -ENODEV;
7269 }
7270 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7271 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7272
7273 return 0;
7274}
7275
1da177e4 7276/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7277
7278/* tp->lock is held. */
7279static int tg3_load_tso_firmware(struct tg3 *tp)
7280{
7281 struct fw_info info;
077f849d 7282 const __be32 *fw_data;
1da177e4
LT		 7283 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7284 int err, i;
7285
7286 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7287 return 0;
7288
077f849d
JSR		 7289 fw_data = (void *)tp->fw->data;
7290
7291 /* Firmware blob starts with version numbers, followed by
7292 start address and length. We are setting complete length.
7293 length = end_address_of_bss - start_address_of_text.
7294 Remainder is the blob to be loaded contiguously
7295 from start address. */
7296
7297 info.fw_base = be32_to_cpu(fw_data[1]);
7298 cpu_scratch_size = tp->fw_len;
7299 info.fw_len = tp->fw->size - 12;
7300 info.fw_data = &fw_data[3];
7301
1da177e4 7302 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7303 cpu_base = RX_CPU_BASE;
7304 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7305 } else {
1da177e4
LT		 7306 cpu_base = TX_CPU_BASE;
7307 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7308 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7309 }
7310
7311 err = tg3_load_firmware_cpu(tp, cpu_base,
7312 cpu_scratch_base, cpu_scratch_size,
7313 &info);
7314 if (err)
7315 return err;
7316
7317 /* Now startup the cpu. */
7318 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7319 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7320
7321 for (i = 0; i < 5; i++) {
077f849d 7322 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7323 break;
7324 tw32(cpu_base + CPU_STATE, 0xffffffff);
7325 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7326 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7327 udelay(1000);
7328 }
7329 if (i >= 5) {
7330 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7331 "to set CPU PC, is %08x should be %08x\n",
7332 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7333 info.fw_base);
1da177e4
LT		 7334 return -ENODEV;
7335 }
7336 tw32(cpu_base + CPU_STATE, 0xffffffff);
7337 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7338 return 0;
7339}
7340
1da177e4 7341
1da177e4
LT		 7342static int tg3_set_mac_addr(struct net_device *dev, void *p)
7343{
7344 struct tg3 *tp = netdev_priv(dev);
7345 struct sockaddr *addr = p;
986e0aeb 7346 int err = 0, skip_mac_1 = 0;
1da177e4 7347
f9804ddb
MC		 7348 if (!is_valid_ether_addr(addr->sa_data))
7349 return -EINVAL;
7350
1da177e4
LT		 7351 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7352
e75f7c90
MC		 7353 if (!netif_running(dev))
7354 return 0;
7355
58712ef9 7356 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7357 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7358
986e0aeb
MC		 7359 addr0_high = tr32(MAC_ADDR_0_HIGH);
7360 addr0_low = tr32(MAC_ADDR_0_LOW);
7361 addr1_high = tr32(MAC_ADDR_1_HIGH);
7362 addr1_low = tr32(MAC_ADDR_1_LOW);
7363
7364 /* Skip MAC addr 1 if ASF is using it. */
7365 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7366 !(addr1_high == 0 && addr1_low == 0))
7367 skip_mac_1 = 1;
58712ef9 7368 }
986e0aeb
MC		 7369 spin_lock_bh(&tp->lock);
7370 __tg3_set_mac_addr(tp, skip_mac_1);
7371 spin_unlock_bh(&tp->lock);
1da177e4 7372
b9ec6c1b 7373 return err;
1da177e4
LT		 7374}
7375
7376/* tp->lock is held. */
7377static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7378 dma_addr_t mapping, u32 maxlen_flags,
7379 u32 nic_addr)
7380{
7381 tg3_write_mem(tp,
7382 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7383 ((u64) mapping >> 32));
7384 tg3_write_mem(tp,
7385 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7386 ((u64) mapping & 0xffffffff));
7387 tg3_write_mem(tp,
7388 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7389 maxlen_flags);
7390
7391 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7392 tg3_write_mem(tp,
7393 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7394 nic_addr);
7395}
7396
7397static void __tg3_set_rx_mode(struct net_device *);
d244c892 7398static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7399{
b6080e12
MC		 7400 int i;
7401
19cfaecc 7402 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7403 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7404 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7405 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7406 } else {
7407 tw32(HOSTCC_TXCOL_TICKS, 0);
7408 tw32(HOSTCC_TXMAX_FRAMES, 0);
7409 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7410 }
b6080e12 7411
19cfaecc
MC		 7412 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7413 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7414 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7415 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7416 } else {
b6080e12
MC		 7417 tw32(HOSTCC_RXCOL_TICKS, 0);
7418 tw32(HOSTCC_RXMAX_FRAMES, 0);
7419 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7420 }
b6080e12 7421
15f9850d
DM		 7422 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7423 u32 val = ec->stats_block_coalesce_usecs;
7424
b6080e12
MC		 7425 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7426 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7427
15f9850d
DM		 7428 if (!netif_carrier_ok(tp->dev))
7429 val = 0;
7430
7431 tw32(HOSTCC_STAT_COAL_TICKS, val);
7432 }
b6080e12
MC		 7433
7434 for (i = 0; i < tp->irq_cnt - 1; i++) {
7435 u32 reg;
7436
7437 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7438 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7439 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7440 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7441 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7442 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7443
7444 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7445 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7446 tw32(reg, ec->tx_coalesce_usecs);
7447 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7448 tw32(reg, ec->tx_max_coalesced_frames);
7449 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7450 tw32(reg, ec->tx_max_coalesced_frames_irq);
7451 }
b6080e12
MC		 7452 }
7453
7454 for (; i < tp->irq_max - 1; i++) {
7455 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7456 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7457 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7458
7459 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7460 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7461 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7462 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7463 }
b6080e12 7464 }
15f9850d 7465}
1da177e4 7466
2d31ecaf
MC		 7467/* tp->lock is held. */
7468static void tg3_rings_reset(struct tg3 *tp)
7469{
7470 int i;
f77a6a8e 7471 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7472 struct tg3_napi *tnapi = &tp->napi[0];
7473
7474 /* Disable all transmit rings but the first. */
7475 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7476 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7477 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7478 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7479 else
7480 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7481
7482 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7483 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7484 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7485 BDINFO_FLAGS_DISABLED);
7486
7487
7488 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7489 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7490 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7491 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7492 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7493 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7495 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7496 else
7497 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7498
7499 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7500 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7501 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7502 BDINFO_FLAGS_DISABLED);
7503
7504 /* Disable interrupts */
7505 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7506
7507 /* Zero mailbox registers. */
f77a6a8e
MC		 7508 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7509 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7510 tp->napi[i].tx_prod = 0;
7511 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7512 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7513 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7514 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7515 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7516 }
c2353a32
MC		 7517 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7518 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7519 } else {
7520 tp->napi[0].tx_prod = 0;
7521 tp->napi[0].tx_cons = 0;
7522 tw32_mailbox(tp->napi[0].prodmbox, 0);
7523 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7524 }
2d31ecaf
MC		 7525
7526 /* Make sure the NIC-based send BD rings are disabled. */
7527 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7528 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7529 for (i = 0; i < 16; i++)
7530 tw32_tx_mbox(mbox + i * 8, 0);
7531 }
7532
7533 txrcb = NIC_SRAM_SEND_RCB;
7534 rxrcb = NIC_SRAM_RCV_RET_RCB;
7535
7536 /* Clear status block in ram. */
7537 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7538
7539 /* Set status block DMA address */
7540 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7541 ((u64) tnapi->status_mapping >> 32));
7542 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7543 ((u64) tnapi->status_mapping & 0xffffffff));
7544
f77a6a8e
MC		 7545 if (tnapi->tx_ring) {
7546 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7547 (TG3_TX_RING_SIZE <<
7548 BDINFO_FLAGS_MAXLEN_SHIFT),
7549 NIC_SRAM_TX_BUFFER_DESC);
7550 txrcb += TG3_BDINFO_SIZE;
7551 }
7552
7553 if (tnapi->rx_rcb) {
7554 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7555 (TG3_RX_RCB_RING_SIZE(tp) <<
7556 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7557 rxrcb += TG3_BDINFO_SIZE;
7558 }
7559
7560 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7561
f77a6a8e
MC		 7562 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7563 u64 mapping = (u64)tnapi->status_mapping;
7564 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7565 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7566
7567 /* Clear status block in ram. */
7568 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7569
19cfaecc
MC		 7570 if (tnapi->tx_ring) {
7571 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7572 (TG3_TX_RING_SIZE <<
7573 BDINFO_FLAGS_MAXLEN_SHIFT),
7574 NIC_SRAM_TX_BUFFER_DESC);
7575 txrcb += TG3_BDINFO_SIZE;
7576 }
f77a6a8e
MC		 7577
7578 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7579 (TG3_RX_RCB_RING_SIZE(tp) <<
7580 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7581
7582 stblk += 8;
f77a6a8e
MC		 7583 rxrcb += TG3_BDINFO_SIZE;
7584 }
2d31ecaf
MC		 7585}
7586
1da177e4 7587/* tp->lock is held. */
8e7a22e3 7588static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7589{
7590 u32 val, rdmac_mode;
7591 int i, err, limit;
21f581a5 7592 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7593
7594 tg3_disable_ints(tp);
7595
7596 tg3_stop_fw(tp);
7597
7598 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7599
7600 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7601 tg3_abort_hw(tp, 1);
1da177e4
LT		 7602 }
7603
603f1173 7604 if (reset_phy)
d4d2c558
MC		 7605 tg3_phy_reset(tp);
7606
1da177e4
LT		 7607 err = tg3_chip_reset(tp);
7608 if (err)
7609 return err;
7610
7611 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7612
bcb37f6c 7613 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7614 val = tr32(TG3_CPMU_CTRL);
7615 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7616 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7617
7618 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7619 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7620 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7621 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7622
7623 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7624 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7625 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7626 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7627
7628 val = tr32(TG3_CPMU_HST_ACC);
7629 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7630 val |= CPMU_HST_ACC_MACCLK_6_25;
7631 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7632 }
7633
33466d93
MC		 7634 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7635 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7636 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7637 PCIE_PWR_MGMT_L1_THRESH_4MS;
7638 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7639
7640 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7641 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7642
7643 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7644
f40386c8
MC		 7645 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7646 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7647 }
7648
614b0590
MC		 7649 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7650 u32 grc_mode = tr32(GRC_MODE);
7651
7652 /* Access the lower 1K of PL PCIE block registers. */
7653 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7654 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7655
7656 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7657 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7658 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7659
7660 tw32(GRC_MODE, grc_mode);
7661 }
7662
1da177e4
LT		 7663 /* This works around an issue with Athlon chipsets on
7664 * B3 tigon3 silicon. This bit has no effect on any
7665 * other revision. But do not set this on PCI Express
795d01c5 7666 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7667 */
795d01c5
MC		 7668 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7669 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7670 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7671 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7672 }
1da177e4
LT		 7673
7674 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7675 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7676 val = tr32(TG3PCI_PCISTATE);
7677 val |= PCISTATE_RETRY_SAME_DMA;
7678 tw32(TG3PCI_PCISTATE, val);
7679 }
7680
0d3031d9
MC		 7681 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7682 /* Allow reads and writes to the
7683 * APE register and memory space.
7684 */
7685 val = tr32(TG3PCI_PCISTATE);
7686 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7687 PCISTATE_ALLOW_APE_SHMEM_WR;
7688 tw32(TG3PCI_PCISTATE, val);
7689 }
7690
1da177e4
LT		 7691 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7692 /* Enable some hw fixes. */
7693 val = tr32(TG3PCI_MSI_DATA);
7694 val |= (1 << 26) | (1 << 28) | (1 << 29);
7695 tw32(TG3PCI_MSI_DATA, val);
7696 }
7697
7698 /* Descriptor ring init may make accesses to the
7699 * NIC SRAM area to setup the TX descriptors, so we
7700 * can only do this after the hardware has been
7701 * successfully reset.
7702 */
32d8c572
MC		 7703 err = tg3_init_rings(tp);
7704 if (err)
7705 return err;
1da177e4 7706
b703df6f
MC		 7707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7709 val = tr32(TG3PCI_DMA_RW_CTRL) &
7710 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7711 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7712 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7713 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7714 /* This value is determined during the probe time DMA
7715 * engine test, tg3_test_dma.
7716 */
7717 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7718 }
1da177e4
LT		 7719
7720 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7721 GRC_MODE_4X_NIC_SEND_RINGS |
7722 GRC_MODE_NO_TX_PHDR_CSUM |
7723 GRC_MODE_NO_RX_PHDR_CSUM);
7724 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7725
7726 /* Pseudo-header checksum is done by hardware logic and not
7727 * the offload processers, so make the chip do the pseudo-
7728 * header checksums on receive. For transmit it is more
7729 * convenient to do the pseudo-header checksum in software
7730 * as Linux does that on transmit for us in all cases.
7731 */
7732 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7733
7734 tw32(GRC_MODE,
7735 tp->grc_mode |
7736 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7737
7738 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7739 val = tr32(GRC_MISC_CFG);
7740 val &= ~0xff;
7741 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7742 tw32(GRC_MISC_CFG, val);
7743
7744 /* Initialize MBUF/DESC pool. */
cbf46853 7745 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7746 /* Do nothing. */
7747 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7748 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7750 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7751 else
7752 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7753 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7754 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7755 }
1da177e4
LT		 7756 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7757 int fw_len;
7758
077f849d 7759 fw_len = tp->fw_len;
1da177e4
LT		 7760 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7761 tw32(BUFMGR_MB_POOL_ADDR,
7762 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7763 tw32(BUFMGR_MB_POOL_SIZE,
7764 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7765 }
1da177e4 7766
0f893dc6 7767 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7768 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7769 tp->bufmgr_config.mbuf_read_dma_low_water);
7770 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7771 tp->bufmgr_config.mbuf_mac_rx_low_water);
7772 tw32(BUFMGR_MB_HIGH_WATER,
7773 tp->bufmgr_config.mbuf_high_water);
7774 } else {
7775 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7776 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7777 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7778 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7779 tw32(BUFMGR_MB_HIGH_WATER,
7780 tp->bufmgr_config.mbuf_high_water_jumbo);
7781 }
7782 tw32(BUFMGR_DMA_LOW_WATER,
7783 tp->bufmgr_config.dma_low_water);
7784 tw32(BUFMGR_DMA_HIGH_WATER,
7785 tp->bufmgr_config.dma_high_water);
7786
7787 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7788 for (i = 0; i < 2000; i++) {
7789 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7790 break;
7791 udelay(10);
7792 }
7793 if (i >= 2000) {
7794 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7795 tp->dev->name);
7796 return -ENODEV;
7797 }
7798
7799 /* Setup replenish threshold. */
f92905de
MC		 7800 val = tp->rx_pending / 8;
7801 if (val == 0)
7802 val = 1;
7803 else if (val > tp->rx_std_max_post)
7804 val = tp->rx_std_max_post;
b5d3772c
MC		 7805 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7806 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7807 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7808
7809 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7810 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7811 }
f92905de
MC		 7812
7813 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7814
7815 /* Initialize TG3_BDINFO's at:
7816 * RCVDBDI_STD_BD: standard eth size rx ring
7817 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7818 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7819 *
7820 * like so:
7821 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7822 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7823 * ring attribute flags
7824 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7825 *
7826 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7827 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7828 *
7829 * The size of each ring is fixed in the firmware, but the location is
7830 * configurable.
7831 */
7832 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7833 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7834 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7835 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7836 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7837 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7838 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7839
fdb72b38
MC		 7840 /* Disable the mini ring */
7841 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7842 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7843 BDINFO_FLAGS_DISABLED);
7844
fdb72b38
MC		 7845 /* Program the jumbo buffer descriptor ring control
7846 * blocks on those devices that have them.
7847 */
8f666b07 7848 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7849 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7850 /* Setup replenish threshold. */
7851 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7852
0f893dc6 7853 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7854 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7855 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7856 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7857 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7858 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7859 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7860 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7861 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7862 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7863 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7864 } else {
7865 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7866 BDINFO_FLAGS_DISABLED);
7867 }
7868
b703df6f
MC		 7869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7871 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7872 (RX_STD_MAX_SIZE << 2);
7873 else
7874 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7875 } else
7876 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7877
7878 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7879
411da640 7880 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7881 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7882
411da640 7883 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7884 tp->rx_jumbo_pending : 0;
66711e66 7885 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7886
b703df6f
MC		 7887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7889 tw32(STD_REPLENISH_LWM, 32);
7890 tw32(JMB_REPLENISH_LWM, 16);
7891 }
7892
2d31ecaf
MC		 7893 tg3_rings_reset(tp);
7894
1da177e4 7895 /* Initialize MAC address and backoff seed. */
986e0aeb 7896 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7897
7898 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7899 tw32(MAC_RX_MTU_SIZE,
7900 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7901
7902 /* The slot time is changed by tg3_setup_phy if we
7903 * run at gigabit with half duplex.
7904 */
7905 tw32(MAC_TX_LENGTHS,
7906 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7907 (6 << TX_LENGTHS_IPG_SHIFT) |
7908 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7909
7910 /* Receive rules. */
7911 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7912 tw32(RCVLPC_CONFIG, 0x0181);
7913
7914 /* Calculate RDMAC_MODE setting early, we need it to determine
7915 * the RCVLPC_STATE_ENABLE mask.
7916 */
7917 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7918 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7919 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7920 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7921 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7922
0339e4e3
MC		 7923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7924 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7925
57e6983c 7926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7929 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7930 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7931 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7932
85e94ced
MC		 7933 /* If statement applies to 5705 and 5750 PCI devices only */
7934 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7935 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7936 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7937 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7939 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7940 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7941 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7942 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7943 }
7944 }
7945
85e94ced
MC		 7946 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7947 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7948
1da177e4 7949 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7950 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7951
e849cdc3
MC		 7952 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7955 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7956
7957 /* Receive/send statistics. */
1661394e
MC		 7958 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7959 val = tr32(RCVLPC_STATS_ENABLE);
7960 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7961 tw32(RCVLPC_STATS_ENABLE, val);
7962 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7963 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7964 val = tr32(RCVLPC_STATS_ENABLE);
7965 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7966 tw32(RCVLPC_STATS_ENABLE, val);
7967 } else {
7968 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7969 }
7970 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7971 tw32(SNDDATAI_STATSENAB, 0xffffff);
7972 tw32(SNDDATAI_STATSCTRL,
7973 (SNDDATAI_SCTRL_ENABLE |
7974 SNDDATAI_SCTRL_FASTUPD));
7975
7976 /* Setup host coalescing engine. */
7977 tw32(HOSTCC_MODE, 0);
7978 for (i = 0; i < 2000; i++) {
7979 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7980 break;
7981 udelay(10);
7982 }
7983
d244c892 7984 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7985
1da177e4
LT		 7986 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7987 /* Status/statistics block address. See tg3_timer,
7988 * the tg3_periodic_fetch_stats call there, and
7989 * tg3_get_stats to see how this works for 5705/5750 chips.
7990 */
1da177e4
LT		 7991 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7992 ((u64) tp->stats_mapping >> 32));
7993 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7994 ((u64) tp->stats_mapping & 0xffffffff));
7995 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7996
1da177e4 7997 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7998
7999 /* Clear statistics and status block memory areas */
8000 for (i = NIC_SRAM_STATS_BLK;
8001 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8002 i += sizeof(u32)) {
8003 tg3_write_mem(tp, i, 0);
8004 udelay(40);
8005 }
1da177e4
LT		 8006 }
8007
8008 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8009
8010 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8011 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8012 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8013 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8014
c94e3941
MC		 8015 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8016 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8017 /* reset to prevent losing 1st rx packet intermittently */
8018 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8019 udelay(10);
8020 }
8021
3bda1258
MC		 8022 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8023 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8024 else
8025 tp->mac_mode = 0;
8026 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 8027 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 8028 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8029 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8030 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8031 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 8032 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8033 udelay(40);
8034
314fba34 8035 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 8036 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 8037 * register to preserve the GPIO settings for LOMs. The GPIOs,
8038 * whether used as inputs or outputs, are set by boot code after
8039 * reset.
8040 */
9d26e213 8041 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 8042 u32 gpio_mask;
8043
9d26e213
MC		 8044 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8045 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8046 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 8047
8048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8049 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8050 GRC_LCLCTRL_GPIO_OUTPUT3;
8051
af36e6b6
MC		 8052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8053 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8054
aaf84465 8055 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 8056 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8057
8058 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 8059 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8060 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8061 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 8062 }
1da177e4
LT		 8063 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8064 udelay(100);
8065
baf8a94a
MC		 8066 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8067 val = tr32(MSGINT_MODE);
8068 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8069 tw32(MSGINT_MODE, val);
8070 }
8071
1da177e4
LT		 8072 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8073 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8074 udelay(40);
8075 }
8076
8077 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8078 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8079 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8080 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8081 WDMAC_MODE_LNGREAD_ENAB);
8082
85e94ced
MC		 8083 /* If statement applies to 5705 and 5750 PCI devices only */
8084 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8085 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8087 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8088 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8089 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8090 /* nothing */
8091 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8092 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8093 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8094 val |= WDMAC_MODE_RX_ACCEL;
8095 }
8096 }
8097
d9ab5ad1 8098 /* Enable host coalescing bug fix */
321d32a0 8099 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8100 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8101
788a035e
MC		 8102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8103 val |= WDMAC_MODE_BURST_ALL_DATA;
8104
1da177e4
LT		 8105 tw32_f(WDMAC_MODE, val);
8106 udelay(40);
8107
9974a356
MC		 8108 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8109 u16 pcix_cmd;
8110
8111 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8112 &pcix_cmd);
1da177e4 8113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8114 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8115 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8116 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8117 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8118 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8119 }
9974a356
MC		 8120 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8121 pcix_cmd);
1da177e4
LT		 8122 }
8123
8124 tw32_f(RDMAC_MODE, rdmac_mode);
8125 udelay(40);
8126
8127 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8128 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8129 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8130
8131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8132 tw32(SNDDATAC_MODE,
8133 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8134 else
8135 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8136
1da177e4
LT		 8137 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8138 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8139 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8140 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8141 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8142 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8143 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8144 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8145 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8146 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8147 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8148
8149 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8150 err = tg3_load_5701_a0_firmware_fix(tp);
8151 if (err)
8152 return err;
8153 }
8154
1da177e4
LT		 8155 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8156 err = tg3_load_tso_firmware(tp);
8157 if (err)
8158 return err;
8159 }
1da177e4
LT		 8160
8161 tp->tx_mode = TX_MODE_ENABLE;
8162 tw32_f(MAC_TX_MODE, tp->tx_mode);
8163 udelay(100);
8164
baf8a94a
MC		 8165 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8166 u32 reg = MAC_RSS_INDIR_TBL_0;
8167 u8 *ent = (u8 *)&val;
8168
8169 /* Setup the indirection table */
8170 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8171 int idx = i % sizeof(val);
8172
8173 ent[idx] = i % (tp->irq_cnt - 1);
8174 if (idx == sizeof(val) - 1) {
8175 tw32(reg, val);
8176 reg += 4;
8177 }
8178 }
8179
8180 /* Setup the "secret" hash key. */
8181 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8182 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8183 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8184 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8185 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8186 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8187 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8188 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8189 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8190 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8191 }
8192
1da177e4 8193 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8194 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8195 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8196
baf8a94a
MC		 8197 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8198 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8199 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8200 RX_MODE_RSS_IPV6_HASH_EN |
8201 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8202 RX_MODE_RSS_IPV4_HASH_EN |
8203 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8204
1da177e4
LT		 8205 tw32_f(MAC_RX_MODE, tp->rx_mode);
8206 udelay(10);
8207
1da177e4
LT		 8208 tw32(MAC_LED_CTRL, tp->led_ctrl);
8209
8210 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8211 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8212 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8213 udelay(10);
8214 }
8215 tw32_f(MAC_RX_MODE, tp->rx_mode);
8216 udelay(10);
8217
8218 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8219 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8220 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8221 /* Set drive transmission level to 1.2V */
8222 /* only if the signal pre-emphasis bit is not set */
8223 val = tr32(MAC_SERDES_CFG);
8224 val &= 0xfffff000;
8225 val |= 0x880;
8226 tw32(MAC_SERDES_CFG, val);
8227 }
8228 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8229 tw32(MAC_SERDES_CFG, 0x616000);
8230 }
8231
8232 /* Prevent chip from dropping frames when flow control
8233 * is enabled.
8234 */
666bc831
MC		 8235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8236 val = 1;
8237 else
8238 val = 2;
8239 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8240
8241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8242 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8243 /* Use hardware link auto-negotiation */
8244 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8245 }
8246
d4d2c558
MC		 8247 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8248 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8249 u32 tmp;
8250
8251 tmp = tr32(SERDES_RX_CTRL);
8252 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8253 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8254 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8255 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8256 }
8257
dd477003
MC		 8258 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8259 if (tp->link_config.phy_is_low_power) {
8260 tp->link_config.phy_is_low_power = 0;
8261 tp->link_config.speed = tp->link_config.orig_speed;
8262 tp->link_config.duplex = tp->link_config.orig_duplex;
8263 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8264 }
1da177e4 8265
dd477003
MC		 8266 err = tg3_setup_phy(tp, 0);
8267 if (err)
8268 return err;
1da177e4 8269
dd477003 8270 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8271 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8272 u32 tmp;
8273
8274 /* Clear CRC stats. */
8275 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8276 tg3_writephy(tp, MII_TG3_TEST1,
8277 tmp | MII_TG3_TEST1_CRC_EN);
8278 tg3_readphy(tp, 0x14, &tmp);
8279 }
1da177e4
LT		 8280 }
8281 }
8282
8283 __tg3_set_rx_mode(tp->dev);
8284
8285 /* Initialize receive rules. */
8286 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8287 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8288 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8289 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8290
4cf78e4f 8291 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8292 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8293 limit = 8;
8294 else
8295 limit = 16;
8296 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8297 limit -= 4;
8298 switch (limit) {
8299 case 16:
8300 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8301 case 15:
8302 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8303 case 14:
8304 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8305 case 13:
8306 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8307 case 12:
8308 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8309 case 11:
8310 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8311 case 10:
8312 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8313 case 9:
8314 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8315 case 8:
8316 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8317 case 7:
8318 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8319 case 6:
8320 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8321 case 5:
8322 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8323 case 4:
8324 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8325 case 3:
8326 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8327 case 2:
8328 case 1:
8329
8330 default:
8331 break;
855e1111 8332 }
1da177e4 8333
9ce768ea
MC		 8334 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8335 /* Write our heartbeat update interval to APE. */
8336 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8337 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8338
1da177e4
LT		 8339 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8340
1da177e4
LT		 8341 return 0;
8342}
8343
8344/* Called at device open time to get the chip ready for
8345 * packet processing. Invoked with tp->lock held.
8346 */
8e7a22e3 8347static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8348{
1da177e4
LT		 8349 tg3_switch_clocks(tp);
8350
8351 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8352
2f751b67 8353 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8354}
8355
8356#define TG3_STAT_ADD32(PSTAT, REG) \
8357do { u32 __val = tr32(REG); \
8358 (PSTAT)->low += __val; \
8359 if ((PSTAT)->low < __val) \
8360 (PSTAT)->high += 1; \
8361} while (0)
8362
8363static void tg3_periodic_fetch_stats(struct tg3 *tp)
8364{
8365 struct tg3_hw_stats *sp = tp->hw_stats;
8366
8367 if (!netif_carrier_ok(tp->dev))
8368 return;
8369
8370 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8371 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8372 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8373 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8374 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8375 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8376 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8377 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8378 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8379 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8380 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8381 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8382 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8383
8384 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8385 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8386 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8387 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8388 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8389 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8390 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8391 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8392 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8393 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8394 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8395 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8396 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8397 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8398
8399 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8400 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8401 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8402}
8403
8404static void tg3_timer(unsigned long __opaque)
8405{
8406 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8407
f475f163
MC		 8408 if (tp->irq_sync)
8409 goto restart_timer;
8410
f47c11ee 8411 spin_lock(&tp->lock);
1da177e4 8412
fac9b83e
DM		 8413 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8414 /* All of this garbage is because when using non-tagged
8415 * IRQ status the mailbox/status_block protocol the chip
8416 * uses with the cpu is race prone.
8417 */
898a56f8 8418 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8419 tw32(GRC_LOCAL_CTRL,
8420 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8421 } else {
8422 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8423 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8424 }
1da177e4 8425
fac9b83e
DM		 8426 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8427 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8428 spin_unlock(&tp->lock);
fac9b83e
DM		 8429 schedule_work(&tp->reset_task);
8430 return;
8431 }
1da177e4
LT		 8432 }
8433
1da177e4
LT		 8434 /* This part only runs once per second. */
8435 if (!--tp->timer_counter) {
fac9b83e
DM		 8436 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8437 tg3_periodic_fetch_stats(tp);
8438
1da177e4
LT		 8439 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8440 u32 mac_stat;
8441 int phy_event;
8442
8443 mac_stat = tr32(MAC_STATUS);
8444
8445 phy_event = 0;
8446 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8447 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8448 phy_event = 1;
8449 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8450 phy_event = 1;
8451
8452 if (phy_event)
8453 tg3_setup_phy(tp, 0);
8454 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8455 u32 mac_stat = tr32(MAC_STATUS);
8456 int need_setup = 0;
8457
8458 if (netif_carrier_ok(tp->dev) &&
8459 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8460 need_setup = 1;
8461 }
8462 if (! netif_carrier_ok(tp->dev) &&
8463 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8464 MAC_STATUS_SIGNAL_DET))) {
8465 need_setup = 1;
8466 }
8467 if (need_setup) {
3d3ebe74
MC		 8468 if (!tp->serdes_counter) {
8469 tw32_f(MAC_MODE,
8470 (tp->mac_mode &
8471 ~MAC_MODE_PORT_MODE_MASK));
8472 udelay(40);
8473 tw32_f(MAC_MODE, tp->mac_mode);
8474 udelay(40);
8475 }
1da177e4
LT		 8476 tg3_setup_phy(tp, 0);
8477 }
747e8f8b
MC		 8478 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8479 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8480
8481 tp->timer_counter = tp->timer_multiplier;
8482 }
8483
130b8e4d
MC		 8484 /* Heartbeat is only sent once every 2 seconds.
8485 *
8486 * The heartbeat is to tell the ASF firmware that the host
8487 * driver is still alive. In the event that the OS crashes,
8488 * ASF needs to reset the hardware to free up the FIFO space
8489 * that may be filled with rx packets destined for the host.
8490 * If the FIFO is full, ASF will no longer function properly.
8491 *
8492 * Unintended resets have been reported on real time kernels
8493 * where the timer doesn't run on time. Netpoll will also have
8494 * same problem.
8495 *
8496 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8497 * to check the ring condition when the heartbeat is expiring
8498 * before doing the reset. This will prevent most unintended
8499 * resets.
8500 */
1da177e4 8501 if (!--tp->asf_counter) {
bc7959b2
MC		 8502 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8503 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8504 tg3_wait_for_event_ack(tp);
8505
bbadf503 8506 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8507 FWCMD_NICDRV_ALIVE3);
bbadf503 8508 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8509 /* 5 seconds timeout */
bbadf503 8510 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8511
8512 tg3_generate_fw_event(tp);
1da177e4
LT		 8513 }
8514 tp->asf_counter = tp->asf_multiplier;
8515 }
8516
f47c11ee 8517 spin_unlock(&tp->lock);
1da177e4 8518
f475f163 8519restart_timer:
1da177e4
LT		 8520 tp->timer.expires = jiffies + tp->timer_offset;
8521 add_timer(&tp->timer);
8522}
8523
4f125f42 8524static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8525{
7d12e780 8526 irq_handler_t fn;
fcfa0a32 8527 unsigned long flags;
4f125f42
MC		 8528 char *name;
8529 struct tg3_napi *tnapi = &tp->napi[irq_num];
8530
8531 if (tp->irq_cnt == 1)
8532 name = tp->dev->name;
8533 else {
8534 name = &tnapi->irq_lbl[0];
8535 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8536 name[IFNAMSIZ-1] = 0;
8537 }
fcfa0a32 8538
679563f4 8539 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8540 fn = tg3_msi;
8541 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8542 fn = tg3_msi_1shot;
1fb9df5d 8543 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8544 } else {
8545 fn = tg3_interrupt;
8546 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8547 fn = tg3_interrupt_tagged;
1fb9df5d 8548 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8549 }
4f125f42
MC		 8550
8551 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8552}
8553
7938109f
MC		 8554static int tg3_test_interrupt(struct tg3 *tp)
8555{
09943a18 8556 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8557 struct net_device *dev = tp->dev;
b16250e3 8558 int err, i, intr_ok = 0;
f6eb9b1f 8559 u32 val;
7938109f 8560
d4bc3927
MC		 8561 if (!netif_running(dev))
8562 return -ENODEV;
8563
7938109f
MC		 8564 tg3_disable_ints(tp);
8565
4f125f42 8566 free_irq(tnapi->irq_vec, tnapi);
7938109f 8567
f6eb9b1f
MC		 8568 /*
8569 * Turn off MSI one shot mode. Otherwise this test has no
8570 * observable way to know whether the interrupt was delivered.
8571 */
b703df6f
MC		 8572 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8574 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8575 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8576 tw32(MSGINT_MODE, val);
8577 }
8578
4f125f42 8579 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8580 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8581 if (err)
8582 return err;
8583
898a56f8 8584 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8585 tg3_enable_ints(tp);
8586
8587 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8588 tnapi->coal_now);
7938109f
MC		 8589
8590 for (i = 0; i < 5; i++) {
b16250e3
MC		 8591 u32 int_mbox, misc_host_ctrl;
8592
898a56f8 8593 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8594 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8595
8596 if ((int_mbox != 0) ||
8597 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8598 intr_ok = 1;
7938109f 8599 break;
b16250e3
MC		 8600 }
8601
7938109f
MC		 8602 msleep(10);
8603 }
8604
8605 tg3_disable_ints(tp);
8606
4f125f42 8607 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8608
4f125f42 8609 err = tg3_request_irq(tp, 0);
7938109f
MC		 8610
8611 if (err)
8612 return err;
8613
f6eb9b1f
MC		 8614 if (intr_ok) {
8615 /* Reenable MSI one shot mode. */
b703df6f
MC		 8616 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8618 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8619 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8620 tw32(MSGINT_MODE, val);
8621 }
7938109f 8622 return 0;
f6eb9b1f 8623 }
7938109f
MC		 8624
8625 return -EIO;
8626}
8627
8628/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8629 * successfully restored
8630 */
8631static int tg3_test_msi(struct tg3 *tp)
8632{
7938109f
MC		 8633 int err;
8634 u16 pci_cmd;
8635
8636 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8637 return 0;
8638
8639 /* Turn off SERR reporting in case MSI terminates with Master
8640 * Abort.
8641 */
8642 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8643 pci_write_config_word(tp->pdev, PCI_COMMAND,
8644 pci_cmd & ~PCI_COMMAND_SERR);
8645
8646 err = tg3_test_interrupt(tp);
8647
8648 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8649
8650 if (!err)
8651 return 0;
8652
8653 /* other failures */
8654 if (err != -EIO)
8655 return err;
8656
8657 /* MSI test failed, go back to INTx mode */
8658 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8659 "switching to INTx mode. Please report this failure to "
8660 "the PCI maintainer and include system chipset information.\n",
8661 tp->dev->name);
8662
4f125f42 8663 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8664
7938109f
MC		 8665 pci_disable_msi(tp->pdev);
8666
8667 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8668
4f125f42 8669 err = tg3_request_irq(tp, 0);
7938109f
MC		 8670 if (err)
8671 return err;
8672
8673 /* Need to reset the chip because the MSI cycle may have terminated
8674 * with Master Abort.
8675 */
f47c11ee 8676 tg3_full_lock(tp, 1);
7938109f 8677
944d980e 8678 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8679 err = tg3_init_hw(tp, 1);
7938109f 8680
f47c11ee 8681 tg3_full_unlock(tp);
7938109f
MC		 8682
8683 if (err)
4f125f42 8684 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8685
8686 return err;
8687}
8688
9e9fd12d
MC		 8689static int tg3_request_firmware(struct tg3 *tp)
8690{
8691 const __be32 *fw_data;
8692
8693 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8694 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8695 tp->dev->name, tp->fw_needed);
8696 return -ENOENT;
8697 }
8698
8699 fw_data = (void *)tp->fw->data;
8700
8701 /* Firmware blob starts with version numbers, followed by
8702 * start address and _full_ length including BSS sections
8703 * (which must be longer than the actual data, of course
8704 */
8705
8706 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8707 if (tp->fw_len < (tp->fw->size - 12)) {
8708 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8709 tp->dev->name, tp->fw_len, tp->fw_needed);
8710 release_firmware(tp->fw);
8711 tp->fw = NULL;
8712 return -EINVAL;
8713 }
8714
8715 /* We no longer need firmware; we have it. */
8716 tp->fw_needed = NULL;
8717 return 0;
8718}
8719
679563f4
MC		 8720static bool tg3_enable_msix(struct tg3 *tp)
8721{
8722 int i, rc, cpus = num_online_cpus();
8723 struct msix_entry msix_ent[tp->irq_max];
8724
8725 if (cpus == 1)
8726 /* Just fallback to the simpler MSI mode. */
8727 return false;
8728
8729 /*
8730 * We want as many rx rings enabled as there are cpus.
8731 * The first MSIX vector only deals with link interrupts, etc,
8732 * so we add one to the number of vectors we are requesting.
8733 */
8734 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8735
8736 for (i = 0; i < tp->irq_max; i++) {
8737 msix_ent[i].entry = i;
8738 msix_ent[i].vector = 0;
8739 }
8740
8741 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8742 if (rc != 0) {
8743 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8744 return false;
8745 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8746 return false;
8747 printk(KERN_NOTICE
8748 "%s: Requested %d MSI-X vectors, received %d\n",
8749 tp->dev->name, tp->irq_cnt, rc);
8750 tp->irq_cnt = rc;
8751 }
8752
baf8a94a
MC		 8753 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8754
679563f4
MC		 8755 for (i = 0; i < tp->irq_max; i++)
8756 tp->napi[i].irq_vec = msix_ent[i].vector;
8757
19cfaecc
MC		 8758 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8759 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8760 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8761 } else
8762 tp->dev->real_num_tx_queues = 1;
fe5f5787 8763
679563f4
MC		 8764 return true;
8765}
8766
07b0173c
MC		 8767static void tg3_ints_init(struct tg3 *tp)
8768{
679563f4
MC		 8769 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8770 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8771 /* All MSI supporting chips should support tagged
8772 * status. Assert that this is the case.
8773 */
679563f4
MC		 8774 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8775 "Not using MSI.\n", tp->dev->name);
8776 goto defcfg;
07b0173c 8777 }
4f125f42 8778
679563f4
MC		 8779 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8780 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8781 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8782 pci_enable_msi(tp->pdev) == 0)
8783 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8784
8785 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8786 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8787 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8788 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8789 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8790 }
8791defcfg:
8792 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8793 tp->irq_cnt = 1;
8794 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8795 tp->dev->real_num_tx_queues = 1;
679563f4 8796 }
07b0173c
MC		 8797}
8798
8799static void tg3_ints_fini(struct tg3 *tp)
8800{
679563f4
MC		 8801 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8802 pci_disable_msix(tp->pdev);
8803 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8804 pci_disable_msi(tp->pdev);
8805 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8806 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8807}
8808
1da177e4
LT		 8809static int tg3_open(struct net_device *dev)
8810{
8811 struct tg3 *tp = netdev_priv(dev);
4f125f42 8812 int i, err;
1da177e4 8813
9e9fd12d
MC		 8814 if (tp->fw_needed) {
8815 err = tg3_request_firmware(tp);
8816 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8817 if (err)
8818 return err;
8819 } else if (err) {
8820 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8821 tp->dev->name);
8822 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8823 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8824 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8825 tp->dev->name);
8826 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8827 }
8828 }
8829
c49a1561
MC		 8830 netif_carrier_off(tp->dev);
8831
bc1c7567 8832 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8833 if (err)
bc1c7567 8834 return err;
2f751b67
MC		 8835
8836 tg3_full_lock(tp, 0);
bc1c7567 8837
1da177e4
LT		 8838 tg3_disable_ints(tp);
8839 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8840
f47c11ee 8841 tg3_full_unlock(tp);
1da177e4 8842
679563f4
MC		 8843 /*
8844 * Setup interrupts first so we know how
8845 * many NAPI resources to allocate
8846 */
8847 tg3_ints_init(tp);
8848
1da177e4
LT		 8849 /* The placement of this call is tied
8850 * to the setup and use of Host TX descriptors.
8851 */
8852 err = tg3_alloc_consistent(tp);
8853 if (err)
679563f4 8854 goto err_out1;
88b06bc2 8855
fed97810 8856 tg3_napi_enable(tp);
1da177e4 8857
4f125f42
MC		 8858 for (i = 0; i < tp->irq_cnt; i++) {
8859 struct tg3_napi *tnapi = &tp->napi[i];
8860 err = tg3_request_irq(tp, i);
8861 if (err) {
8862 for (i--; i >= 0; i--)
8863 free_irq(tnapi->irq_vec, tnapi);
8864 break;
8865 }
8866 }
1da177e4 8867
07b0173c 8868 if (err)
679563f4 8869 goto err_out2;
bea3348e 8870
f47c11ee 8871 tg3_full_lock(tp, 0);
1da177e4 8872
8e7a22e3 8873 err = tg3_init_hw(tp, 1);
1da177e4 8874 if (err) {
944d980e 8875 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8876 tg3_free_rings(tp);
8877 } else {
fac9b83e
DM		 8878 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8879 tp->timer_offset = HZ;
8880 else
8881 tp->timer_offset = HZ / 10;
8882
8883 BUG_ON(tp->timer_offset > HZ);
8884 tp->timer_counter = tp->timer_multiplier =
8885 (HZ / tp->timer_offset);
8886 tp->asf_counter = tp->asf_multiplier =
28fbef78 8887 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8888
8889 init_timer(&tp->timer);
8890 tp->timer.expires = jiffies + tp->timer_offset;
8891 tp->timer.data = (unsigned long) tp;
8892 tp->timer.function = tg3_timer;
1da177e4
LT		 8893 }
8894
f47c11ee 8895 tg3_full_unlock(tp);
1da177e4 8896
07b0173c 8897 if (err)
679563f4 8898 goto err_out3;
1da177e4 8899
7938109f
MC		 8900 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8901 err = tg3_test_msi(tp);
fac9b83e 8902
7938109f 8903 if (err) {
f47c11ee 8904 tg3_full_lock(tp, 0);
944d980e 8905 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8906 tg3_free_rings(tp);
f47c11ee 8907 tg3_full_unlock(tp);
7938109f 8908
679563f4 8909 goto err_out2;
7938109f 8910 }
fcfa0a32 8911
f6eb9b1f 8912 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8913 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8914 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8915 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8916 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8917
f6eb9b1f
MC		 8918 tw32(PCIE_TRANSACTION_CFG,
8919 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8920 }
7938109f
MC		 8921 }
8922
b02fd9e3
MC		 8923 tg3_phy_start(tp);
8924
f47c11ee 8925 tg3_full_lock(tp, 0);
1da177e4 8926
7938109f
MC		 8927 add_timer(&tp->timer);
8928 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8929 tg3_enable_ints(tp);
8930
f47c11ee 8931 tg3_full_unlock(tp);
1da177e4 8932
fe5f5787 8933 netif_tx_start_all_queues(dev);
1da177e4
LT		 8934
8935 return 0;
07b0173c 8936
679563f4 8937err_out3:
4f125f42
MC		 8938 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8939 struct tg3_napi *tnapi = &tp->napi[i];
8940 free_irq(tnapi->irq_vec, tnapi);
8941 }
07b0173c 8942
679563f4 8943err_out2:
fed97810 8944 tg3_napi_disable(tp);
07b0173c 8945 tg3_free_consistent(tp);
679563f4
MC		 8946
8947err_out1:
8948 tg3_ints_fini(tp);
07b0173c 8949 return err;
1da177e4
LT		 8950}
8951
8952#if 0
8953/*static*/ void tg3_dump_state(struct tg3 *tp)
8954{
8955 u32 val32, val32_2, val32_3, val32_4, val32_5;
8956 u16 val16;
8957 int i;
898a56f8 8958 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8959
8960 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8961 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8962 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8963 val16, val32);
8964
8965 /* MAC block */
8966 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8967 tr32(MAC_MODE), tr32(MAC_STATUS));
8968 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8969 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8970 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8971 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8972 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8973 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8974
8975 /* Send data initiator control block */
8976 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8977 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8978 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8979 tr32(SNDDATAI_STATSCTRL));
8980
8981 /* Send data completion control block */
8982 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8983
8984 /* Send BD ring selector block */
8985 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8986 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8987
8988 /* Send BD initiator control block */
8989 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8990 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8991
8992 /* Send BD completion control block */
8993 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8994
8995 /* Receive list placement control block */
8996 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8997 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8998 printk(" RCVLPC_STATSCTRL[%08x]\n",
8999 tr32(RCVLPC_STATSCTRL));
9000
9001 /* Receive data and receive BD initiator control block */
9002 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
9003 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
9004
9005 /* Receive data completion control block */
9006 printk("DEBUG: RCVDCC_MODE[%08x]\n",
9007 tr32(RCVDCC_MODE));
9008
9009 /* Receive BD initiator control block */
9010 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
9011 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
9012
9013 /* Receive BD completion control block */
9014 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
9015 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
9016
9017 /* Receive list selector control block */
9018 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9019 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9020
9021 /* Mbuf cluster free block */
9022 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9023 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9024
9025 /* Host coalescing control block */
9026 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9027 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9028 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9029 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9030 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9031 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9032 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9033 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9034 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9035 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9036 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9037 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9038
9039 /* Memory arbiter control block */
9040 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9041 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9042
9043 /* Buffer manager control block */
9044 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9045 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9046 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9047 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9048 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9049 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9050 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9051 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9052
9053 /* Read DMA control block */
9054 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9055 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9056
9057 /* Write DMA control block */
9058 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9059 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9060
9061 /* DMA completion block */
9062 printk("DEBUG: DMAC_MODE[%08x]\n",
9063 tr32(DMAC_MODE));
9064
9065 /* GRC block */
9066 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9067 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9068 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9069 tr32(GRC_LOCAL_CTRL));
9070
9071 /* TG3_BDINFOs */
9072 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9073 tr32(RCVDBDI_JUMBO_BD + 0x0),
9074 tr32(RCVDBDI_JUMBO_BD + 0x4),
9075 tr32(RCVDBDI_JUMBO_BD + 0x8),
9076 tr32(RCVDBDI_JUMBO_BD + 0xc));
9077 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9078 tr32(RCVDBDI_STD_BD + 0x0),
9079 tr32(RCVDBDI_STD_BD + 0x4),
9080 tr32(RCVDBDI_STD_BD + 0x8),
9081 tr32(RCVDBDI_STD_BD + 0xc));
9082 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9083 tr32(RCVDBDI_MINI_BD + 0x0),
9084 tr32(RCVDBDI_MINI_BD + 0x4),
9085 tr32(RCVDBDI_MINI_BD + 0x8),
9086 tr32(RCVDBDI_MINI_BD + 0xc));
9087
9088 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9089 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9090 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9091 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9092 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9093 val32, val32_2, val32_3, val32_4);
9094
9095 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9096 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9097 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9098 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9099 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9100 val32, val32_2, val32_3, val32_4);
9101
9102 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9103 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9104 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9105 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9106 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9107 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9108 val32, val32_2, val32_3, val32_4, val32_5);
9109
9110 /* SW status block */
898a56f8
MC		 9111 printk(KERN_DEBUG
9112 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9113 sblk->status,
9114 sblk->status_tag,
9115 sblk->rx_jumbo_consumer,
9116 sblk->rx_consumer,
9117 sblk->rx_mini_consumer,
9118 sblk->idx[0].rx_producer,
9119 sblk->idx[0].tx_consumer);
1da177e4
LT		 9120
9121 /* SW statistics block */
9122 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9123 ((u32 *)tp->hw_stats)[0],
9124 ((u32 *)tp->hw_stats)[1],
9125 ((u32 *)tp->hw_stats)[2],
9126 ((u32 *)tp->hw_stats)[3]);
9127
9128 /* Mailboxes */
9129 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9130 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9131 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9132 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9133 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9134
9135 /* NIC side send descriptors. */
9136 for (i = 0; i < 6; i++) {
9137 unsigned long txd;
9138
9139 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9140 + (i * sizeof(struct tg3_tx_buffer_desc));
9141 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9142 i,
9143 readl(txd + 0x0), readl(txd + 0x4),
9144 readl(txd + 0x8), readl(txd + 0xc));
9145 }
9146
9147 /* NIC side RX descriptors. */
9148 for (i = 0; i < 6; i++) {
9149 unsigned long rxd;
9150
9151 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9152 + (i * sizeof(struct tg3_rx_buffer_desc));
9153 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9154 i,
9155 readl(rxd + 0x0), readl(rxd + 0x4),
9156 readl(rxd + 0x8), readl(rxd + 0xc));
9157 rxd += (4 * sizeof(u32));
9158 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9159 i,
9160 readl(rxd + 0x0), readl(rxd + 0x4),
9161 readl(rxd + 0x8), readl(rxd + 0xc));
9162 }
9163
9164 for (i = 0; i < 6; i++) {
9165 unsigned long rxd;
9166
9167 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9168 + (i * sizeof(struct tg3_rx_buffer_desc));
9169 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9170 i,
9171 readl(rxd + 0x0), readl(rxd + 0x4),
9172 readl(rxd + 0x8), readl(rxd + 0xc));
9173 rxd += (4 * sizeof(u32));
9174 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9175 i,
9176 readl(rxd + 0x0), readl(rxd + 0x4),
9177 readl(rxd + 0x8), readl(rxd + 0xc));
9178 }
9179}
9180#endif
9181
9182static struct net_device_stats *tg3_get_stats(struct net_device *);
9183static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9184
9185static int tg3_close(struct net_device *dev)
9186{
4f125f42 9187 int i;
1da177e4
LT		 9188 struct tg3 *tp = netdev_priv(dev);
9189
fed97810 9190 tg3_napi_disable(tp);
28e53bdd 9191 cancel_work_sync(&tp->reset_task);
7faa006f 9192
fe5f5787 9193 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9194
9195 del_timer_sync(&tp->timer);
9196
24bb4fb6
MC		 9197 tg3_phy_stop(tp);
9198
f47c11ee 9199 tg3_full_lock(tp, 1);
1da177e4
LT		 9200#if 0
9201 tg3_dump_state(tp);
9202#endif
9203
9204 tg3_disable_ints(tp);
9205
944d980e 9206 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9207 tg3_free_rings(tp);
5cf64b8a 9208 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9209
f47c11ee 9210 tg3_full_unlock(tp);
1da177e4 9211
4f125f42
MC		 9212 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9213 struct tg3_napi *tnapi = &tp->napi[i];
9214 free_irq(tnapi->irq_vec, tnapi);
9215 }
07b0173c
MC		 9216
9217 tg3_ints_fini(tp);
1da177e4
LT		 9218
9219 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9220 sizeof(tp->net_stats_prev));
9221 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9222 sizeof(tp->estats_prev));
9223
9224 tg3_free_consistent(tp);
9225
bc1c7567
MC		 9226 tg3_set_power_state(tp, PCI_D3hot);
9227
9228 netif_carrier_off(tp->dev);
9229
1da177e4
LT		 9230 return 0;
9231}
9232
9233static inline unsigned long get_stat64(tg3_stat64_t *val)
9234{
9235 unsigned long ret;
9236
9237#if (BITS_PER_LONG == 32)
9238 ret = val->low;
9239#else
9240 ret = ((u64)val->high << 32) | ((u64)val->low);
9241#endif
9242 return ret;
9243}
9244
816f8b86
SB		 9245static inline u64 get_estat64(tg3_stat64_t *val)
9246{
9247 return ((u64)val->high << 32) | ((u64)val->low);
9248}
9249
1da177e4
LT		 9250static unsigned long calc_crc_errors(struct tg3 *tp)
9251{
9252 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9253
9254 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9255 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9257 u32 val;
9258
f47c11ee 9259 spin_lock_bh(&tp->lock);
569a5df8
MC		 9260 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9261 tg3_writephy(tp, MII_TG3_TEST1,
9262 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9263 tg3_readphy(tp, 0x14, &val);
9264 } else
9265 val = 0;
f47c11ee 9266 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9267
9268 tp->phy_crc_errors += val;
9269
9270 return tp->phy_crc_errors;
9271 }
9272
9273 return get_stat64(&hw_stats->rx_fcs_errors);
9274}
9275
9276#define ESTAT_ADD(member) \
9277 estats->member = old_estats->member + \
816f8b86 9278 get_estat64(&hw_stats->member)
1da177e4
LT		 9279
9280static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9281{
9282 struct tg3_ethtool_stats *estats = &tp->estats;
9283 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9284 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9285
9286 if (!hw_stats)
9287 return old_estats;
9288
9289 ESTAT_ADD(rx_octets);
9290 ESTAT_ADD(rx_fragments);
9291 ESTAT_ADD(rx_ucast_packets);
9292 ESTAT_ADD(rx_mcast_packets);
9293 ESTAT_ADD(rx_bcast_packets);
9294 ESTAT_ADD(rx_fcs_errors);
9295 ESTAT_ADD(rx_align_errors);
9296 ESTAT_ADD(rx_xon_pause_rcvd);
9297 ESTAT_ADD(rx_xoff_pause_rcvd);
9298 ESTAT_ADD(rx_mac_ctrl_rcvd);
9299 ESTAT_ADD(rx_xoff_entered);
9300 ESTAT_ADD(rx_frame_too_long_errors);
9301 ESTAT_ADD(rx_jabbers);
9302 ESTAT_ADD(rx_undersize_packets);
9303 ESTAT_ADD(rx_in_length_errors);
9304 ESTAT_ADD(rx_out_length_errors);
9305 ESTAT_ADD(rx_64_or_less_octet_packets);
9306 ESTAT_ADD(rx_65_to_127_octet_packets);
9307 ESTAT_ADD(rx_128_to_255_octet_packets);
9308 ESTAT_ADD(rx_256_to_511_octet_packets);
9309 ESTAT_ADD(rx_512_to_1023_octet_packets);
9310 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9311 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9312 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9313 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9314 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9315
9316 ESTAT_ADD(tx_octets);
9317 ESTAT_ADD(tx_collisions);
9318 ESTAT_ADD(tx_xon_sent);
9319 ESTAT_ADD(tx_xoff_sent);
9320 ESTAT_ADD(tx_flow_control);
9321 ESTAT_ADD(tx_mac_errors);
9322 ESTAT_ADD(tx_single_collisions);
9323 ESTAT_ADD(tx_mult_collisions);
9324 ESTAT_ADD(tx_deferred);
9325 ESTAT_ADD(tx_excessive_collisions);
9326 ESTAT_ADD(tx_late_collisions);
9327 ESTAT_ADD(tx_collide_2times);
9328 ESTAT_ADD(tx_collide_3times);
9329 ESTAT_ADD(tx_collide_4times);
9330 ESTAT_ADD(tx_collide_5times);
9331 ESTAT_ADD(tx_collide_6times);
9332 ESTAT_ADD(tx_collide_7times);
9333 ESTAT_ADD(tx_collide_8times);
9334 ESTAT_ADD(tx_collide_9times);
9335 ESTAT_ADD(tx_collide_10times);
9336 ESTAT_ADD(tx_collide_11times);
9337 ESTAT_ADD(tx_collide_12times);
9338 ESTAT_ADD(tx_collide_13times);
9339 ESTAT_ADD(tx_collide_14times);
9340 ESTAT_ADD(tx_collide_15times);
9341 ESTAT_ADD(tx_ucast_packets);
9342 ESTAT_ADD(tx_mcast_packets);
9343 ESTAT_ADD(tx_bcast_packets);
9344 ESTAT_ADD(tx_carrier_sense_errors);
9345 ESTAT_ADD(tx_discards);
9346 ESTAT_ADD(tx_errors);
9347
9348 ESTAT_ADD(dma_writeq_full);
9349 ESTAT_ADD(dma_write_prioq_full);
9350 ESTAT_ADD(rxbds_empty);
9351 ESTAT_ADD(rx_discards);
9352 ESTAT_ADD(rx_errors);
9353 ESTAT_ADD(rx_threshold_hit);
9354
9355 ESTAT_ADD(dma_readq_full);
9356 ESTAT_ADD(dma_read_prioq_full);
9357 ESTAT_ADD(tx_comp_queue_full);
9358
9359 ESTAT_ADD(ring_set_send_prod_index);
9360 ESTAT_ADD(ring_status_update);
9361 ESTAT_ADD(nic_irqs);
9362 ESTAT_ADD(nic_avoided_irqs);
9363 ESTAT_ADD(nic_tx_threshold_hit);
9364
9365 return estats;
9366}
9367
9368static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9369{
9370 struct tg3 *tp = netdev_priv(dev);
9371 struct net_device_stats *stats = &tp->net_stats;
9372 struct net_device_stats *old_stats = &tp->net_stats_prev;
9373 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9374
9375 if (!hw_stats)
9376 return old_stats;
9377
9378 stats->rx_packets = old_stats->rx_packets +
9379 get_stat64(&hw_stats->rx_ucast_packets) +
9380 get_stat64(&hw_stats->rx_mcast_packets) +
9381 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9382
1da177e4
LT		 9383 stats->tx_packets = old_stats->tx_packets +
9384 get_stat64(&hw_stats->tx_ucast_packets) +
9385 get_stat64(&hw_stats->tx_mcast_packets) +
9386 get_stat64(&hw_stats->tx_bcast_packets);
9387
9388 stats->rx_bytes = old_stats->rx_bytes +
9389 get_stat64(&hw_stats->rx_octets);
9390 stats->tx_bytes = old_stats->tx_bytes +
9391 get_stat64(&hw_stats->tx_octets);
9392
9393 stats->rx_errors = old_stats->rx_errors +
4f63b877 9394 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9395 stats->tx_errors = old_stats->tx_errors +
9396 get_stat64(&hw_stats->tx_errors) +
9397 get_stat64(&hw_stats->tx_mac_errors) +
9398 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9399 get_stat64(&hw_stats->tx_discards);
9400
9401 stats->multicast = old_stats->multicast +
9402 get_stat64(&hw_stats->rx_mcast_packets);
9403 stats->collisions = old_stats->collisions +
9404 get_stat64(&hw_stats->tx_collisions);
9405
9406 stats->rx_length_errors = old_stats->rx_length_errors +
9407 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9408 get_stat64(&hw_stats->rx_undersize_packets);
9409
9410 stats->rx_over_errors = old_stats->rx_over_errors +
9411 get_stat64(&hw_stats->rxbds_empty);
9412 stats->rx_frame_errors = old_stats->rx_frame_errors +
9413 get_stat64(&hw_stats->rx_align_errors);
9414 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9415 get_stat64(&hw_stats->tx_discards);
9416 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9417 get_stat64(&hw_stats->tx_carrier_sense_errors);
9418
9419 stats->rx_crc_errors = old_stats->rx_crc_errors +
9420 calc_crc_errors(tp);
9421
4f63b877
JL		 9422 stats->rx_missed_errors = old_stats->rx_missed_errors +
9423 get_stat64(&hw_stats->rx_discards);
9424
1da177e4
LT		 9425 return stats;
9426}
9427
9428static inline u32 calc_crc(unsigned char *buf, int len)
9429{
9430 u32 reg;
9431 u32 tmp;
9432 int j, k;
9433
9434 reg = 0xffffffff;
9435
9436 for (j = 0; j < len; j++) {
9437 reg ^= buf[j];
9438
9439 for (k = 0; k < 8; k++) {
9440 tmp = reg & 0x01;
9441
9442 reg >>= 1;
9443
9444 if (tmp) {
9445 reg ^= 0xedb88320;
9446 }
9447 }
9448 }
9449
9450 return ~reg;
9451}
9452
9453static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9454{
9455 /* accept or reject all multicast frames */
9456 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9457 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9458 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9459 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9460}
9461
9462static void __tg3_set_rx_mode(struct net_device *dev)
9463{
9464 struct tg3 *tp = netdev_priv(dev);
9465 u32 rx_mode;
9466
9467 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9468 RX_MODE_KEEP_VLAN_TAG);
9469
9470 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9471 * flag clear.
9472 */
9473#if TG3_VLAN_TAG_USED
9474 if (!tp->vlgrp &&
9475 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9476 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9477#else
9478 /* By definition, VLAN is disabled always in this
9479 * case.
9480 */
9481 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9482 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9483#endif
9484
9485 if (dev->flags & IFF_PROMISC) {
9486 /* Promiscuous mode. */
9487 rx_mode |= RX_MODE_PROMISC;
9488 } else if (dev->flags & IFF_ALLMULTI) {
9489 /* Accept all multicast. */
9490 tg3_set_multi (tp, 1);
4cd24eaf 9491 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 9492 /* Reject all multicast. */
9493 tg3_set_multi (tp, 0);
9494 } else {
9495 /* Accept one or more multicast(s). */
9496 struct dev_mc_list *mclist;
9497 unsigned int i;
9498 u32 mc_filter[4] = { 0, };
9499 u32 regidx;
9500 u32 bit;
9501 u32 crc;
9502
4cd24eaf 9503 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
1da177e4
LT		 9504 i++, mclist = mclist->next) {
9505
9506 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9507 bit = ~crc & 0x7f;
9508 regidx = (bit & 0x60) >> 5;
9509 bit &= 0x1f;
9510 mc_filter[regidx] |= (1 << bit);
9511 }
9512
9513 tw32(MAC_HASH_REG_0, mc_filter[0]);
9514 tw32(MAC_HASH_REG_1, mc_filter[1]);
9515 tw32(MAC_HASH_REG_2, mc_filter[2]);
9516 tw32(MAC_HASH_REG_3, mc_filter[3]);
9517 }
9518
9519 if (rx_mode != tp->rx_mode) {
9520 tp->rx_mode = rx_mode;
9521 tw32_f(MAC_RX_MODE, rx_mode);
9522 udelay(10);
9523 }
9524}
9525
9526static void tg3_set_rx_mode(struct net_device *dev)
9527{
9528 struct tg3 *tp = netdev_priv(dev);
9529
e75f7c90
MC		 9530 if (!netif_running(dev))
9531 return;
9532
f47c11ee 9533 tg3_full_lock(tp, 0);
1da177e4 9534 __tg3_set_rx_mode(dev);
f47c11ee 9535 tg3_full_unlock(tp);
1da177e4
LT		 9536}
9537
9538#define TG3_REGDUMP_LEN (32 * 1024)
9539
9540static int tg3_get_regs_len(struct net_device *dev)
9541{
9542 return TG3_REGDUMP_LEN;
9543}
9544
9545static void tg3_get_regs(struct net_device *dev,
9546 struct ethtool_regs *regs, void *_p)
9547{
9548 u32 *p = _p;
9549 struct tg3 *tp = netdev_priv(dev);
9550 u8 *orig_p = _p;
9551 int i;
9552
9553 regs->version = 0;
9554
9555 memset(p, 0, TG3_REGDUMP_LEN);
9556
bc1c7567
MC		 9557 if (tp->link_config.phy_is_low_power)
9558 return;
9559
f47c11ee 9560 tg3_full_lock(tp, 0);
1da177e4
LT		 9561
9562#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9563#define GET_REG32_LOOP(base,len) \
9564do { p = (u32 *)(orig_p + (base)); \
9565 for (i = 0; i < len; i += 4) \
9566 __GET_REG32((base) + i); \
9567} while (0)
9568#define GET_REG32_1(reg) \
9569do { p = (u32 *)(orig_p + (reg)); \
9570 __GET_REG32((reg)); \
9571} while (0)
9572
9573 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9574 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9575 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9576 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9577 GET_REG32_1(SNDDATAC_MODE);
9578 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9579 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9580 GET_REG32_1(SNDBDC_MODE);
9581 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9582 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9583 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9584 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9585 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9586 GET_REG32_1(RCVDCC_MODE);
9587 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9588 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9589 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9590 GET_REG32_1(MBFREE_MODE);
9591 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9592 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9593 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9594 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9595 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9596 GET_REG32_1(RX_CPU_MODE);
9597 GET_REG32_1(RX_CPU_STATE);
9598 GET_REG32_1(RX_CPU_PGMCTR);
9599 GET_REG32_1(RX_CPU_HWBKPT);
9600 GET_REG32_1(TX_CPU_MODE);
9601 GET_REG32_1(TX_CPU_STATE);
9602 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9603 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9604 GET_REG32_LOOP(FTQ_RESET, 0x120);
9605 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9606 GET_REG32_1(DMAC_MODE);
9607 GET_REG32_LOOP(GRC_MODE, 0x4c);
9608 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9609 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9610
9611#undef __GET_REG32
9612#undef GET_REG32_LOOP
9613#undef GET_REG32_1
9614
f47c11ee 9615 tg3_full_unlock(tp);
1da177e4
LT		 9616}
9617
9618static int tg3_get_eeprom_len(struct net_device *dev)
9619{
9620 struct tg3 *tp = netdev_priv(dev);
9621
9622 return tp->nvram_size;
9623}
9624
1da177e4
LT		 9625static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9626{
9627 struct tg3 *tp = netdev_priv(dev);
9628 int ret;
9629 u8 *pd;
b9fc7dc5 9630 u32 i, offset, len, b_offset, b_count;
a9dc529d 9631 __be32 val;
1da177e4 9632
df259d8c
MC		 9633 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9634 return -EINVAL;
9635
bc1c7567
MC		 9636 if (tp->link_config.phy_is_low_power)
9637 return -EAGAIN;
9638
1da177e4
LT		 9639 offset = eeprom->offset;
9640 len = eeprom->len;
9641 eeprom->len = 0;
9642
9643 eeprom->magic = TG3_EEPROM_MAGIC;
9644
9645 if (offset & 3) {
9646 /* adjustments to start on required 4 byte boundary */
9647 b_offset = offset & 3;
9648 b_count = 4 - b_offset;
9649 if (b_count > len) {
9650 /* i.e. offset=1 len=2 */
9651 b_count = len;
9652 }
a9dc529d 9653 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9654 if (ret)
9655 return ret;
1da177e4
LT		 9656 memcpy(data, ((char*)&val) + b_offset, b_count);
9657 len -= b_count;
9658 offset += b_count;
9659 eeprom->len += b_count;
9660 }
9661
9662 /* read bytes upto the last 4 byte boundary */
9663 pd = &data[eeprom->len];
9664 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9665 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9666 if (ret) {
9667 eeprom->len += i;
9668 return ret;
9669 }
1da177e4
LT		 9670 memcpy(pd + i, &val, 4);
9671 }
9672 eeprom->len += i;
9673
9674 if (len & 3) {
9675 /* read last bytes not ending on 4 byte boundary */
9676 pd = &data[eeprom->len];
9677 b_count = len & 3;
9678 b_offset = offset + len - b_count;
a9dc529d 9679 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9680 if (ret)
9681 return ret;
b9fc7dc5 9682 memcpy(pd, &val, b_count);
1da177e4
LT		 9683 eeprom->len += b_count;
9684 }
9685 return 0;
9686}
9687
6aa20a22 9688static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9689
9690static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9691{
9692 struct tg3 *tp = netdev_priv(dev);
9693 int ret;
b9fc7dc5 9694 u32 offset, len, b_offset, odd_len;
1da177e4 9695 u8 *buf;
a9dc529d 9696 __be32 start, end;
1da177e4 9697
bc1c7567
MC		 9698 if (tp->link_config.phy_is_low_power)
9699 return -EAGAIN;
9700
df259d8c
MC		 9701 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9702 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9703 return -EINVAL;
9704
9705 offset = eeprom->offset;
9706 len = eeprom->len;
9707
9708 if ((b_offset = (offset & 3))) {
9709 /* adjustments to start on required 4 byte boundary */
a9dc529d 9710 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9711 if (ret)
9712 return ret;
1da177e4
LT		 9713 len += b_offset;
9714 offset &= ~3;
1c8594b4
MC		 9715 if (len < 4)
9716 len = 4;
1da177e4
LT		 9717 }
9718
9719 odd_len = 0;
1c8594b4 9720 if (len & 3) {
1da177e4
LT		 9721 /* adjustments to end on required 4 byte boundary */
9722 odd_len = 1;
9723 len = (len + 3) & ~3;
a9dc529d 9724 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9725 if (ret)
9726 return ret;
1da177e4
LT		 9727 }
9728
9729 buf = data;
9730 if (b_offset || odd_len) {
9731 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9732 if (!buf)
1da177e4
LT		 9733 return -ENOMEM;
9734 if (b_offset)
9735 memcpy(buf, &start, 4);
9736 if (odd_len)
9737 memcpy(buf+len-4, &end, 4);
9738 memcpy(buf + b_offset, data, eeprom->len);
9739 }
9740
9741 ret = tg3_nvram_write_block(tp, offset, len, buf);
9742
9743 if (buf != data)
9744 kfree(buf);
9745
9746 return ret;
9747}
9748
9749static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9750{
b02fd9e3
MC		 9751 struct tg3 *tp = netdev_priv(dev);
9752
9753 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9754 struct phy_device *phydev;
b02fd9e3
MC		 9755 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9756 return -EAGAIN;
3f0e3ad7
MC		 9757 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9758 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9759 }
6aa20a22 9760
1da177e4
LT		 9761 cmd->supported = (SUPPORTED_Autoneg);
9762
9763 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9764 cmd->supported |= (SUPPORTED_1000baseT_Half |
9765 SUPPORTED_1000baseT_Full);
9766
ef348144 9767 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9768 cmd->supported |= (SUPPORTED_100baseT_Half |
9769 SUPPORTED_100baseT_Full |
9770 SUPPORTED_10baseT_Half |
9771 SUPPORTED_10baseT_Full |
3bebab59 9772 SUPPORTED_TP);
ef348144
KK		 9773 cmd->port = PORT_TP;
9774 } else {
1da177e4 9775 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9776 cmd->port = PORT_FIBRE;
9777 }
6aa20a22 9778
1da177e4
LT		 9779 cmd->advertising = tp->link_config.advertising;
9780 if (netif_running(dev)) {
9781 cmd->speed = tp->link_config.active_speed;
9782 cmd->duplex = tp->link_config.active_duplex;
9783 }
882e9793 9784 cmd->phy_address = tp->phy_addr;
7e5856bd 9785 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9786 cmd->autoneg = tp->link_config.autoneg;
9787 cmd->maxtxpkt = 0;
9788 cmd->maxrxpkt = 0;
9789 return 0;
9790}
6aa20a22 9791
1da177e4
LT		 9792static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9793{
9794 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9795
b02fd9e3 9796 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9797 struct phy_device *phydev;
b02fd9e3
MC		 9798 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9799 return -EAGAIN;
3f0e3ad7
MC		 9800 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9801 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9802 }
9803
7e5856bd
MC		 9804 if (cmd->autoneg != AUTONEG_ENABLE &&
9805 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9806 return -EINVAL;
7e5856bd
MC		 9807
9808 if (cmd->autoneg == AUTONEG_DISABLE &&
9809 cmd->duplex != DUPLEX_FULL &&
9810 cmd->duplex != DUPLEX_HALF)
37ff238d 9811 return -EINVAL;
1da177e4 9812
7e5856bd
MC		 9813 if (cmd->autoneg == AUTONEG_ENABLE) {
9814 u32 mask = ADVERTISED_Autoneg |
9815 ADVERTISED_Pause |
9816 ADVERTISED_Asym_Pause;
9817
9818 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9819 mask |= ADVERTISED_1000baseT_Half |
9820 ADVERTISED_1000baseT_Full;
9821
9822 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9823 mask |= ADVERTISED_100baseT_Half |
9824 ADVERTISED_100baseT_Full |
9825 ADVERTISED_10baseT_Half |
9826 ADVERTISED_10baseT_Full |
9827 ADVERTISED_TP;
9828 else
9829 mask |= ADVERTISED_FIBRE;
9830
9831 if (cmd->advertising & ~mask)
9832 return -EINVAL;
9833
9834 mask &= (ADVERTISED_1000baseT_Half |
9835 ADVERTISED_1000baseT_Full |
9836 ADVERTISED_100baseT_Half |
9837 ADVERTISED_100baseT_Full |
9838 ADVERTISED_10baseT_Half |
9839 ADVERTISED_10baseT_Full);
9840
9841 cmd->advertising &= mask;
9842 } else {
9843 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9844 if (cmd->speed != SPEED_1000)
9845 return -EINVAL;
9846
9847 if (cmd->duplex != DUPLEX_FULL)
9848 return -EINVAL;
9849 } else {
9850 if (cmd->speed != SPEED_100 &&
9851 cmd->speed != SPEED_10)
9852 return -EINVAL;
9853 }
9854 }
9855
f47c11ee 9856 tg3_full_lock(tp, 0);
1da177e4
LT		 9857
9858 tp->link_config.autoneg = cmd->autoneg;
9859 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9860 tp->link_config.advertising = (cmd->advertising |
9861 ADVERTISED_Autoneg);
1da177e4
LT		 9862 tp->link_config.speed = SPEED_INVALID;
9863 tp->link_config.duplex = DUPLEX_INVALID;
9864 } else {
9865 tp->link_config.advertising = 0;
9866 tp->link_config.speed = cmd->speed;
9867 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9868 }
6aa20a22 9869
24fcad6b
MC		 9870 tp->link_config.orig_speed = tp->link_config.speed;
9871 tp->link_config.orig_duplex = tp->link_config.duplex;
9872 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9873
1da177e4
LT		 9874 if (netif_running(dev))
9875 tg3_setup_phy(tp, 1);
9876
f47c11ee 9877 tg3_full_unlock(tp);
6aa20a22 9878
1da177e4
LT		 9879 return 0;
9880}
6aa20a22 9881
1da177e4
LT		 9882static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9883{
9884 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9885
1da177e4
LT		 9886 strcpy(info->driver, DRV_MODULE_NAME);
9887 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9888 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9889 strcpy(info->bus_info, pci_name(tp->pdev));
9890}
6aa20a22 9891
1da177e4
LT		 9892static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9893{
9894 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9895
12dac075
RW		 9896 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9897 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9898 wol->supported = WAKE_MAGIC;
9899 else
9900 wol->supported = 0;
1da177e4 9901 wol->wolopts = 0;
05ac4cb7
MC		 9902 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9903 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9904 wol->wolopts = WAKE_MAGIC;
9905 memset(&wol->sopass, 0, sizeof(wol->sopass));
9906}
6aa20a22 9907
1da177e4
LT		 9908static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9909{
9910 struct tg3 *tp = netdev_priv(dev);
12dac075 9911 struct device *dp = &tp->pdev->dev;
6aa20a22 9912
1da177e4
LT		 9913 if (wol->wolopts & ~WAKE_MAGIC)
9914 return -EINVAL;
9915 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9916 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9917 return -EINVAL;
6aa20a22 9918
f47c11ee 9919 spin_lock_bh(&tp->lock);
12dac075 9920 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9921 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9922 device_set_wakeup_enable(dp, true);
9923 } else {
1da177e4 9924 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9925 device_set_wakeup_enable(dp, false);
9926 }
f47c11ee 9927 spin_unlock_bh(&tp->lock);
6aa20a22 9928
1da177e4
LT		 9929 return 0;
9930}
6aa20a22 9931
1da177e4
LT		 9932static u32 tg3_get_msglevel(struct net_device *dev)
9933{
9934 struct tg3 *tp = netdev_priv(dev);
9935 return tp->msg_enable;
9936}
6aa20a22 9937
1da177e4
LT		 9938static void tg3_set_msglevel(struct net_device *dev, u32 value)
9939{
9940 struct tg3 *tp = netdev_priv(dev);
9941 tp->msg_enable = value;
9942}
6aa20a22 9943
1da177e4
LT		 9944static int tg3_set_tso(struct net_device *dev, u32 value)
9945{
9946 struct tg3 *tp = netdev_priv(dev);
9947
9948 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9949 if (value)
9950 return -EINVAL;
9951 return 0;
9952 }
027455ad 9953 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9954 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9955 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9956 if (value) {
b0026624 9957 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9958 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9960 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9961 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9964 dev->features |= NETIF_F_TSO_ECN;
9965 } else
9966 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9967 }
1da177e4
LT		 9968 return ethtool_op_set_tso(dev, value);
9969}
6aa20a22 9970
1da177e4
LT		 9971static int tg3_nway_reset(struct net_device *dev)
9972{
9973 struct tg3 *tp = netdev_priv(dev);
1da177e4 9974 int r;
6aa20a22 9975
1da177e4
LT		 9976 if (!netif_running(dev))
9977 return -EAGAIN;
9978
c94e3941
MC		 9979 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9980 return -EINVAL;
9981
b02fd9e3
MC		 9982 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9983 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9984 return -EAGAIN;
3f0e3ad7 9985 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9986 } else {
9987 u32 bmcr;
9988
9989 spin_lock_bh(&tp->lock);
9990 r = -EINVAL;
9991 tg3_readphy(tp, MII_BMCR, &bmcr);
9992 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9993 ((bmcr & BMCR_ANENABLE) ||
9994 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9995 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9996 BMCR_ANENABLE);
9997 r = 0;
9998 }
9999 spin_unlock_bh(&tp->lock);
1da177e4 10000 }
6aa20a22 10001
1da177e4
LT		 10002 return r;
10003}
6aa20a22 10004
1da177e4
LT		 10005static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10006{
10007 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10008
1da177e4
LT		 10009 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
10010 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 10011 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10012 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
10013 else
10014 ering->rx_jumbo_max_pending = 0;
10015
10016 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 10017
10018 ering->rx_pending = tp->rx_pending;
10019 ering->rx_mini_pending = 0;
4f81c32b
MC		 10020 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10021 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10022 else
10023 ering->rx_jumbo_pending = 0;
10024
f3f3f27e 10025 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 10026}
6aa20a22 10027
1da177e4
LT		 10028static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10029{
10030 struct tg3 *tp = netdev_priv(dev);
646c9edd 10031 int i, irq_sync = 0, err = 0;
6aa20a22 10032
1da177e4
LT		 10033 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10034 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 10035 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10036 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 10037 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 10038 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 10039 return -EINVAL;
6aa20a22 10040
bbe832c0 10041 if (netif_running(dev)) {
b02fd9e3 10042 tg3_phy_stop(tp);
1da177e4 10043 tg3_netif_stop(tp);
bbe832c0
MC		 10044 irq_sync = 1;
10045 }
1da177e4 10046
bbe832c0 10047 tg3_full_lock(tp, irq_sync);
6aa20a22 10048
1da177e4
LT		 10049 tp->rx_pending = ering->rx_pending;
10050
10051 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10052 tp->rx_pending > 63)
10053 tp->rx_pending = 63;
10054 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 10055
10056 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10057 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 10058
10059 if (netif_running(dev)) {
944d980e 10060 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 10061 err = tg3_restart_hw(tp, 1);
10062 if (!err)
10063 tg3_netif_start(tp);
1da177e4
LT		 10064 }
10065
f47c11ee 10066 tg3_full_unlock(tp);
6aa20a22 10067
b02fd9e3
MC		 10068 if (irq_sync && !err)
10069 tg3_phy_start(tp);
10070
b9ec6c1b 10071 return err;
1da177e4 10072}
6aa20a22 10073
1da177e4
LT		 10074static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10075{
10076 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10077
1da177e4 10078 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 10079
e18ce346 10080 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 10081 epause->rx_pause = 1;
10082 else
10083 epause->rx_pause = 0;
10084
e18ce346 10085 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10086 epause->tx_pause = 1;
10087 else
10088 epause->tx_pause = 0;
1da177e4 10089}
6aa20a22 10090
1da177e4
LT		 10091static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10092{
10093 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10094 int err = 0;
6aa20a22 10095
b02fd9e3 10096 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2712168f
MC		 10097 u32 newadv;
10098 struct phy_device *phydev;
1da177e4 10099
2712168f 10100 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 10101
2712168f
MC		 10102 if (!(phydev->supported & SUPPORTED_Pause) ||
10103 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10104 ((epause->rx_pause && !epause->tx_pause) ||
10105 (!epause->rx_pause && epause->tx_pause))))
10106 return -EINVAL;
1da177e4 10107
2712168f
MC		 10108 tp->link_config.flowctrl = 0;
10109 if (epause->rx_pause) {
10110 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10111
10112 if (epause->tx_pause) {
10113 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10114 newadv = ADVERTISED_Pause;
b02fd9e3 10115 } else
2712168f
MC		 10116 newadv = ADVERTISED_Pause |
10117 ADVERTISED_Asym_Pause;
10118 } else if (epause->tx_pause) {
10119 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10120 newadv = ADVERTISED_Asym_Pause;
10121 } else
10122 newadv = 0;
10123
10124 if (epause->autoneg)
10125 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10126 else
10127 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10128
10129 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10130 u32 oldadv = phydev->advertising &
10131 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10132 if (oldadv != newadv) {
10133 phydev->advertising &=
10134 ~(ADVERTISED_Pause |
10135 ADVERTISED_Asym_Pause);
10136 phydev->advertising |= newadv;
10137 if (phydev->autoneg) {
10138 /*
10139 * Always renegotiate the link to
10140 * inform our link partner of our
10141 * flow control settings, even if the
10142 * flow control is forced. Let
10143 * tg3_adjust_link() do the final
10144 * flow control setup.
10145 */
10146 return phy_start_aneg(phydev);
b02fd9e3 10147 }
b02fd9e3 10148 }
b02fd9e3 10149
2712168f 10150 if (!epause->autoneg)
b02fd9e3 10151 tg3_setup_flow_control(tp, 0, 0);
2712168f
MC		 10152 } else {
10153 tp->link_config.orig_advertising &=
10154 ~(ADVERTISED_Pause |
10155 ADVERTISED_Asym_Pause);
10156 tp->link_config.orig_advertising |= newadv;
b02fd9e3
MC		 10157 }
10158 } else {
10159 int irq_sync = 0;
10160
10161 if (netif_running(dev)) {
10162 tg3_netif_stop(tp);
10163 irq_sync = 1;
10164 }
10165
10166 tg3_full_lock(tp, irq_sync);
10167
10168 if (epause->autoneg)
10169 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10170 else
10171 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10172 if (epause->rx_pause)
e18ce346 10173 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10174 else
e18ce346 10175 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10176 if (epause->tx_pause)
e18ce346 10177 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10178 else
e18ce346 10179 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10180
10181 if (netif_running(dev)) {
10182 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10183 err = tg3_restart_hw(tp, 1);
10184 if (!err)
10185 tg3_netif_start(tp);
10186 }
10187
10188 tg3_full_unlock(tp);
10189 }
6aa20a22 10190
b9ec6c1b 10191 return err;
1da177e4 10192}
6aa20a22 10193
1da177e4
LT		 10194static u32 tg3_get_rx_csum(struct net_device *dev)
10195{
10196 struct tg3 *tp = netdev_priv(dev);
10197 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10198}
6aa20a22 10199
1da177e4
LT		 10200static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10201{
10202 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10203
1da177e4
LT		 10204 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10205 if (data != 0)
10206 return -EINVAL;
10207 return 0;
10208 }
6aa20a22 10209
f47c11ee 10210 spin_lock_bh(&tp->lock);
1da177e4
LT		 10211 if (data)
10212 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10213 else
10214 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10215 spin_unlock_bh(&tp->lock);
6aa20a22 10216
1da177e4
LT		 10217 return 0;
10218}
6aa20a22 10219
1da177e4
LT		 10220static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10221{
10222 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10223
1da177e4
LT		 10224 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10225 if (data != 0)
10226 return -EINVAL;
10227 return 0;
10228 }
6aa20a22 10229
321d32a0 10230 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10231 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10232 else
9c27dbdf 10233 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10234
10235 return 0;
10236}
10237
b9f2c044 10238static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10239{
b9f2c044
JG		 10240 switch (sset) {
10241 case ETH_SS_TEST:
10242 return TG3_NUM_TEST;
10243 case ETH_SS_STATS:
10244 return TG3_NUM_STATS;
10245 default:
10246 return -EOPNOTSUPP;
10247 }
4cafd3f5
MC		 10248}
10249
1da177e4
LT		 10250static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10251{
10252 switch (stringset) {
10253 case ETH_SS_STATS:
10254 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10255 break;
4cafd3f5
MC		 10256 case ETH_SS_TEST:
10257 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10258 break;
1da177e4
LT		 10259 default:
10260 WARN_ON(1); /* we need a WARN() */
10261 break;
10262 }
10263}
10264
4009a93d
MC		 10265static int tg3_phys_id(struct net_device *dev, u32 data)
10266{
10267 struct tg3 *tp = netdev_priv(dev);
10268 int i;
10269
10270 if (!netif_running(tp->dev))
10271 return -EAGAIN;
10272
10273 if (data == 0)
759afc31 10274 data = UINT_MAX / 2;
4009a93d
MC		 10275
10276 for (i = 0; i < (data * 2); i++) {
10277 if ((i % 2) == 0)
10278 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10279 LED_CTRL_1000MBPS_ON |
10280 LED_CTRL_100MBPS_ON |
10281 LED_CTRL_10MBPS_ON |
10282 LED_CTRL_TRAFFIC_OVERRIDE |
10283 LED_CTRL_TRAFFIC_BLINK |
10284 LED_CTRL_TRAFFIC_LED);
6aa20a22 10285
4009a93d
MC		 10286 else
10287 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10288 LED_CTRL_TRAFFIC_OVERRIDE);
10289
10290 if (msleep_interruptible(500))
10291 break;
10292 }
10293 tw32(MAC_LED_CTRL, tp->led_ctrl);
10294 return 0;
10295}
10296
1da177e4
LT		 10297static void tg3_get_ethtool_stats (struct net_device *dev,
10298 struct ethtool_stats *estats, u64 *tmp_stats)
10299{
10300 struct tg3 *tp = netdev_priv(dev);
10301 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10302}
10303
566f86ad 10304#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10305#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10306#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10307#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10308#define NVRAM_SELFBOOT_HW_SIZE 0x20
10309#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10310
10311static int tg3_test_nvram(struct tg3 *tp)
10312{
b9fc7dc5 10313 u32 csum, magic;
a9dc529d 10314 __be32 *buf;
ab0049b4 10315 int i, j, k, err = 0, size;
566f86ad 10316
df259d8c
MC		 10317 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10318 return 0;
10319
e4f34110 10320 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10321 return -EIO;
10322
1b27777a
MC		 10323 if (magic == TG3_EEPROM_MAGIC)
10324 size = NVRAM_TEST_SIZE;
b16250e3 10325 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10326 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10327 TG3_EEPROM_SB_FORMAT_1) {
10328 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10329 case TG3_EEPROM_SB_REVISION_0:
10330 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10331 break;
10332 case TG3_EEPROM_SB_REVISION_2:
10333 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10334 break;
10335 case TG3_EEPROM_SB_REVISION_3:
10336 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10337 break;
10338 default:
10339 return 0;
10340 }
10341 } else
1b27777a 10342 return 0;
b16250e3
MC		 10343 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10344 size = NVRAM_SELFBOOT_HW_SIZE;
10345 else
1b27777a
MC		 10346 return -EIO;
10347
10348 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10349 if (buf == NULL)
10350 return -ENOMEM;
10351
1b27777a
MC		 10352 err = -EIO;
10353 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10354 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10355 if (err)
566f86ad 10356 break;
566f86ad 10357 }
1b27777a 10358 if (i < size)
566f86ad
MC		 10359 goto out;
10360
1b27777a 10361 /* Selfboot format */
a9dc529d 10362 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10363 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10364 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10365 u8 *buf8 = (u8 *) buf, csum8 = 0;
10366
b9fc7dc5 10367 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10368 TG3_EEPROM_SB_REVISION_2) {
10369 /* For rev 2, the csum doesn't include the MBA. */
10370 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10371 csum8 += buf8[i];
10372 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10373 csum8 += buf8[i];
10374 } else {
10375 for (i = 0; i < size; i++)
10376 csum8 += buf8[i];
10377 }
1b27777a 10378
ad96b485
AB		 10379 if (csum8 == 0) {
10380 err = 0;
10381 goto out;
10382 }
10383
10384 err = -EIO;
10385 goto out;
1b27777a 10386 }
566f86ad 10387
b9fc7dc5 10388 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10389 TG3_EEPROM_MAGIC_HW) {
10390 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10391 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10392 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10393
10394 /* Separate the parity bits and the data bytes. */
10395 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10396 if ((i == 0) || (i == 8)) {
10397 int l;
10398 u8 msk;
10399
10400 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10401 parity[k++] = buf8[i] & msk;
10402 i++;
10403 }
10404 else if (i == 16) {
10405 int l;
10406 u8 msk;
10407
10408 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10409 parity[k++] = buf8[i] & msk;
10410 i++;
10411
10412 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10413 parity[k++] = buf8[i] & msk;
10414 i++;
10415 }
10416 data[j++] = buf8[i];
10417 }
10418
10419 err = -EIO;
10420 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10421 u8 hw8 = hweight8(data[i]);
10422
10423 if ((hw8 & 0x1) && parity[i])
10424 goto out;
10425 else if (!(hw8 & 0x1) && !parity[i])
10426 goto out;
10427 }
10428 err = 0;
10429 goto out;
10430 }
10431
566f86ad
MC		 10432 /* Bootstrap checksum at offset 0x10 */
10433 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10434 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10435 goto out;
10436
10437 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10438 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10439 if (csum != be32_to_cpu(buf[0xfc/4]))
10440 goto out;
566f86ad
MC		 10441
10442 err = 0;
10443
10444out:
10445 kfree(buf);
10446 return err;
10447}
10448
ca43007a
MC		 10449#define TG3_SERDES_TIMEOUT_SEC 2
10450#define TG3_COPPER_TIMEOUT_SEC 6
10451
10452static int tg3_test_link(struct tg3 *tp)
10453{
10454 int i, max;
10455
10456 if (!netif_running(tp->dev))
10457 return -ENODEV;
10458
4c987487 10459 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10460 max = TG3_SERDES_TIMEOUT_SEC;
10461 else
10462 max = TG3_COPPER_TIMEOUT_SEC;
10463
10464 for (i = 0; i < max; i++) {
10465 if (netif_carrier_ok(tp->dev))
10466 return 0;
10467
10468 if (msleep_interruptible(1000))
10469 break;
10470 }
10471
10472 return -EIO;
10473}
10474
a71116d1 10475/* Only test the commonly used registers */
30ca3e37 10476static int tg3_test_registers(struct tg3 *tp)
a71116d1 10477{
b16250e3 10478 int i, is_5705, is_5750;
a71116d1
MC		 10479 u32 offset, read_mask, write_mask, val, save_val, read_val;
10480 static struct {
10481 u16 offset;
10482 u16 flags;
10483#define TG3_FL_5705 0x1
10484#define TG3_FL_NOT_5705 0x2
10485#define TG3_FL_NOT_5788 0x4
b16250e3 10486#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10487 u32 read_mask;
10488 u32 write_mask;
10489 } reg_tbl[] = {
10490 /* MAC Control Registers */
10491 { MAC_MODE, TG3_FL_NOT_5705,
10492 0x00000000, 0x00ef6f8c },
10493 { MAC_MODE, TG3_FL_5705,
10494 0x00000000, 0x01ef6b8c },
10495 { MAC_STATUS, TG3_FL_NOT_5705,
10496 0x03800107, 0x00000000 },
10497 { MAC_STATUS, TG3_FL_5705,
10498 0x03800100, 0x00000000 },
10499 { MAC_ADDR_0_HIGH, 0x0000,
10500 0x00000000, 0x0000ffff },
10501 { MAC_ADDR_0_LOW, 0x0000,
10502 0x00000000, 0xffffffff },
10503 { MAC_RX_MTU_SIZE, 0x0000,
10504 0x00000000, 0x0000ffff },
10505 { MAC_TX_MODE, 0x0000,
10506 0x00000000, 0x00000070 },
10507 { MAC_TX_LENGTHS, 0x0000,
10508 0x00000000, 0x00003fff },
10509 { MAC_RX_MODE, TG3_FL_NOT_5705,
10510 0x00000000, 0x000007fc },
10511 { MAC_RX_MODE, TG3_FL_5705,
10512 0x00000000, 0x000007dc },
10513 { MAC_HASH_REG_0, 0x0000,
10514 0x00000000, 0xffffffff },
10515 { MAC_HASH_REG_1, 0x0000,
10516 0x00000000, 0xffffffff },
10517 { MAC_HASH_REG_2, 0x0000,
10518 0x00000000, 0xffffffff },
10519 { MAC_HASH_REG_3, 0x0000,
10520 0x00000000, 0xffffffff },
10521
10522 /* Receive Data and Receive BD Initiator Control Registers. */
10523 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10524 0x00000000, 0xffffffff },
10525 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10526 0x00000000, 0xffffffff },
10527 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10528 0x00000000, 0x00000003 },
10529 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10530 0x00000000, 0xffffffff },
10531 { RCVDBDI_STD_BD+0, 0x0000,
10532 0x00000000, 0xffffffff },
10533 { RCVDBDI_STD_BD+4, 0x0000,
10534 0x00000000, 0xffffffff },
10535 { RCVDBDI_STD_BD+8, 0x0000,
10536 0x00000000, 0xffff0002 },
10537 { RCVDBDI_STD_BD+0xc, 0x0000,
10538 0x00000000, 0xffffffff },
6aa20a22 10539
a71116d1
MC		 10540 /* Receive BD Initiator Control Registers. */
10541 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10542 0x00000000, 0xffffffff },
10543 { RCVBDI_STD_THRESH, TG3_FL_5705,
10544 0x00000000, 0x000003ff },
10545 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10546 0x00000000, 0xffffffff },
6aa20a22 10547
a71116d1
MC		 10548 /* Host Coalescing Control Registers. */
10549 { HOSTCC_MODE, TG3_FL_NOT_5705,
10550 0x00000000, 0x00000004 },
10551 { HOSTCC_MODE, TG3_FL_5705,
10552 0x00000000, 0x000000f6 },
10553 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10554 0x00000000, 0xffffffff },
10555 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10556 0x00000000, 0x000003ff },
10557 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10558 0x00000000, 0xffffffff },
10559 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10560 0x00000000, 0x000003ff },
10561 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10562 0x00000000, 0xffffffff },
10563 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10564 0x00000000, 0x000000ff },
10565 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10566 0x00000000, 0xffffffff },
10567 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10568 0x00000000, 0x000000ff },
10569 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10570 0x00000000, 0xffffffff },
10571 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10572 0x00000000, 0xffffffff },
10573 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10574 0x00000000, 0xffffffff },
10575 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10576 0x00000000, 0x000000ff },
10577 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10578 0x00000000, 0xffffffff },
10579 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10580 0x00000000, 0x000000ff },
10581 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10582 0x00000000, 0xffffffff },
10583 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10584 0x00000000, 0xffffffff },
10585 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10586 0x00000000, 0xffffffff },
10587 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10588 0x00000000, 0xffffffff },
10589 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10590 0x00000000, 0xffffffff },
10591 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10592 0xffffffff, 0x00000000 },
10593 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10594 0xffffffff, 0x00000000 },
10595
10596 /* Buffer Manager Control Registers. */
b16250e3 10597 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10598 0x00000000, 0x007fff80 },
b16250e3 10599 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10600 0x00000000, 0x007fffff },
10601 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10602 0x00000000, 0x0000003f },
10603 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10604 0x00000000, 0x000001ff },
10605 { BUFMGR_MB_HIGH_WATER, 0x0000,
10606 0x00000000, 0x000001ff },
10607 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10608 0xffffffff, 0x00000000 },
10609 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10610 0xffffffff, 0x00000000 },
6aa20a22 10611
a71116d1
MC		 10612 /* Mailbox Registers */
10613 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10614 0x00000000, 0x000001ff },
10615 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10616 0x00000000, 0x000001ff },
10617 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10618 0x00000000, 0x000007ff },
10619 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10620 0x00000000, 0x000001ff },
10621
10622 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10623 };
10624
b16250e3
MC		 10625 is_5705 = is_5750 = 0;
10626 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10627 is_5705 = 1;
b16250e3
MC		 10628 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10629 is_5750 = 1;
10630 }
a71116d1
MC		 10631
10632 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10633 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10634 continue;
10635
10636 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10637 continue;
10638
10639 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10640 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10641 continue;
10642
b16250e3
MC		 10643 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10644 continue;
10645
a71116d1
MC		 10646 offset = (u32) reg_tbl[i].offset;
10647 read_mask = reg_tbl[i].read_mask;
10648 write_mask = reg_tbl[i].write_mask;
10649
10650 /* Save the original register content */
10651 save_val = tr32(offset);
10652
10653 /* Determine the read-only value. */
10654 read_val = save_val & read_mask;
10655
10656 /* Write zero to the register, then make sure the read-only bits
10657 * are not changed and the read/write bits are all zeros.
10658 */
10659 tw32(offset, 0);
10660
10661 val = tr32(offset);
10662
10663 /* Test the read-only and read/write bits. */
10664 if (((val & read_mask) != read_val) || (val & write_mask))
10665 goto out;
10666
10667 /* Write ones to all the bits defined by RdMask and WrMask, then
10668 * make sure the read-only bits are not changed and the
10669 * read/write bits are all ones.
10670 */
10671 tw32(offset, read_mask | write_mask);
10672
10673 val = tr32(offset);
10674
10675 /* Test the read-only bits. */
10676 if ((val & read_mask) != read_val)
10677 goto out;
10678
10679 /* Test the read/write bits. */
10680 if ((val & write_mask) != write_mask)
10681 goto out;
10682
10683 tw32(offset, save_val);
10684 }
10685
10686 return 0;
10687
10688out:
9f88f29f
MC		 10689 if (netif_msg_hw(tp))
10690 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10691 offset);
a71116d1
MC		 10692 tw32(offset, save_val);
10693 return -EIO;
10694}
10695
7942e1db
MC		 10696static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10697{
f71e1309 10698 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10699 int i;
10700 u32 j;
10701
e9edda69 10702 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10703 for (j = 0; j < len; j += 4) {
10704 u32 val;
10705
10706 tg3_write_mem(tp, offset + j, test_pattern[i]);
10707 tg3_read_mem(tp, offset + j, &val);
10708 if (val != test_pattern[i])
10709 return -EIO;
10710 }
10711 }
10712 return 0;
10713}
10714
10715static int tg3_test_memory(struct tg3 *tp)
10716{
10717 static struct mem_entry {
10718 u32 offset;
10719 u32 len;
10720 } mem_tbl_570x[] = {
38690194 10721 { 0x00000000, 0x00b50},
7942e1db
MC		 10722 { 0x00002000, 0x1c000},
10723 { 0xffffffff, 0x00000}
10724 }, mem_tbl_5705[] = {
10725 { 0x00000100, 0x0000c},
10726 { 0x00000200, 0x00008},
7942e1db
MC		 10727 { 0x00004000, 0x00800},
10728 { 0x00006000, 0x01000},
10729 { 0x00008000, 0x02000},
10730 { 0x00010000, 0x0e000},
10731 { 0xffffffff, 0x00000}
79f4d13a
MC		 10732 }, mem_tbl_5755[] = {
10733 { 0x00000200, 0x00008},
10734 { 0x00004000, 0x00800},
10735 { 0x00006000, 0x00800},
10736 { 0x00008000, 0x02000},
10737 { 0x00010000, 0x0c000},
10738 { 0xffffffff, 0x00000}
b16250e3
MC		 10739 }, mem_tbl_5906[] = {
10740 { 0x00000200, 0x00008},
10741 { 0x00004000, 0x00400},
10742 { 0x00006000, 0x00400},
10743 { 0x00008000, 0x01000},
10744 { 0x00010000, 0x01000},
10745 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10746 }, mem_tbl_5717[] = {
10747 { 0x00000200, 0x00008},
10748 { 0x00010000, 0x0a000},
10749 { 0x00020000, 0x13c00},
10750 { 0xffffffff, 0x00000}
10751 }, mem_tbl_57765[] = {
10752 { 0x00000200, 0x00008},
10753 { 0x00004000, 0x00800},
10754 { 0x00006000, 0x09800},
10755 { 0x00010000, 0x0a000},
10756 { 0xffffffff, 0x00000}
7942e1db
MC		 10757 };
10758 struct mem_entry *mem_tbl;
10759 int err = 0;
10760 int i;
10761
8b5a6c42
MC		 10762 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10763 mem_tbl = mem_tbl_5717;
10764 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10765 mem_tbl = mem_tbl_57765;
10766 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10767 mem_tbl = mem_tbl_5755;
10768 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10769 mem_tbl = mem_tbl_5906;
10770 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10771 mem_tbl = mem_tbl_5705;
10772 else
7942e1db
MC		 10773 mem_tbl = mem_tbl_570x;
10774
10775 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10776 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10777 mem_tbl[i].len)) != 0)
10778 break;
10779 }
6aa20a22 10780
7942e1db
MC		 10781 return err;
10782}
10783
9f40dead
MC		 10784#define TG3_MAC_LOOPBACK 0
10785#define TG3_PHY_LOOPBACK 1
10786
10787static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10788{
9f40dead 10789 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10790 u32 desc_idx, coal_now;
c76949a6
MC		 10791 struct sk_buff *skb, *rx_skb;
10792 u8 *tx_data;
10793 dma_addr_t map;
10794 int num_pkts, tx_len, rx_len, i, err;
10795 struct tg3_rx_buffer_desc *desc;
898a56f8 10796 struct tg3_napi *tnapi, *rnapi;
21f581a5 10797 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10798
c8873405
MC		 10799 tnapi = &tp->napi[0];
10800 rnapi = &tp->napi[0];
0c1d0e2b 10801 if (tp->irq_cnt > 1) {
0c1d0e2b 10802 rnapi = &tp->napi[1];
c8873405
MC		 10803 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10804 tnapi = &tp->napi[1];
0c1d0e2b 10805 }
fd2ce37f 10806 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10807
9f40dead 10808 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10809 /* HW errata - mac loopback fails in some cases on 5780.
10810 * Normal traffic and PHY loopback are not affected by
10811 * errata.
10812 */
10813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10814 return 0;
10815
9f40dead 10816 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10817 MAC_MODE_PORT_INT_LPBACK;
10818 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10819 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10820 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10821 mac_mode |= MAC_MODE_PORT_MODE_MII;
10822 else
10823 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10824 tw32(MAC_MODE, mac_mode);
10825 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10826 u32 val;
10827
7f97a4bd
MC		 10828 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10829 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10830 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10831 } else
10832 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10833
9ef8ca99
MC		 10834 tg3_phy_toggle_automdix(tp, 0);
10835
3f7045c1 10836 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10837 udelay(40);
5d64ad34 10838
e8f3f6ca 10839 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd 10840 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1061b7c5
MC		 10841 tg3_writephy(tp, MII_TG3_FET_PTEST,
10842 MII_TG3_FET_PTEST_FRC_TX_LINK |
10843 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10844 /* The write needs to be flushed for the AC131 */
10845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10846 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
5d64ad34
MC		 10847 mac_mode |= MAC_MODE_PORT_MODE_MII;
10848 } else
10849 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10850
c94e3941
MC		 10851 /* reset to prevent losing 1st rx packet intermittently */
10852 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10853 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10854 udelay(10);
10855 tw32_f(MAC_RX_MODE, tp->rx_mode);
10856 }
e8f3f6ca 10857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
79eb6904
MC		 10858 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10859 if (masked_phy_id == TG3_PHY_ID_BCM5401)
e8f3f6ca 10860 mac_mode &= ~MAC_MODE_LINK_POLARITY;
79eb6904 10861 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
e8f3f6ca 10862 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10863 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10864 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10865 }
9f40dead 10866 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10867 }
10868 else
10869 return -EINVAL;
c76949a6
MC		 10870
10871 err = -EIO;
10872
c76949a6 10873 tx_len = 1514;
a20e9c62 10874 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10875 if (!skb)
10876 return -ENOMEM;
10877
c76949a6
MC		 10878 tx_data = skb_put(skb, tx_len);
10879 memcpy(tx_data, tp->dev->dev_addr, 6);
10880 memset(tx_data + 6, 0x0, 8);
10881
10882 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10883
10884 for (i = 14; i < tx_len; i++)
10885 tx_data[i] = (u8) (i & 0xff);
10886
f4188d8a
AD		 10887 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10888 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10889 dev_kfree_skb(skb);
10890 return -EIO;
10891 }
c76949a6
MC		 10892
10893 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10894 rnapi->coal_now);
c76949a6
MC		 10895
10896 udelay(10);
10897
898a56f8 10898 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10899
c76949a6
MC		 10900 num_pkts = 0;
10901
f4188d8a 10902 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10903
f3f3f27e 10904 tnapi->tx_prod++;
c76949a6
MC		 10905 num_pkts++;
10906
f3f3f27e
MC		 10907 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10908 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10909
10910 udelay(10);
10911
303fc921
MC		 10912 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10913 for (i = 0; i < 35; i++) {
c76949a6 10914 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10915 coal_now);
c76949a6
MC		 10916
10917 udelay(10);
10918
898a56f8
MC		 10919 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10920 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10921 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10922 (rx_idx == (rx_start_idx + num_pkts)))
10923 break;
10924 }
10925
f4188d8a 10926 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10927 dev_kfree_skb(skb);
10928
f3f3f27e 10929 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10930 goto out;
10931
10932 if (rx_idx != rx_start_idx + num_pkts)
10933 goto out;
10934
72334482 10935 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10936 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10937 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10938 if (opaque_key != RXD_OPAQUE_RING_STD)
10939 goto out;
10940
10941 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10942 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10943 goto out;
10944
10945 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10946 if (rx_len != tx_len)
10947 goto out;
10948
21f581a5 10949 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10950
21f581a5 10951 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10952 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10953
10954 for (i = 14; i < tx_len; i++) {
10955 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10956 goto out;
10957 }
10958 err = 0;
6aa20a22 10959
c76949a6
MC		 10960 /* tg3_free_rings will unmap and free the rx_skb */
10961out:
10962 return err;
10963}
10964
9f40dead
MC		 10965#define TG3_MAC_LOOPBACK_FAILED 1
10966#define TG3_PHY_LOOPBACK_FAILED 2
10967#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10968 TG3_PHY_LOOPBACK_FAILED)
10969
10970static int tg3_test_loopback(struct tg3 *tp)
10971{
10972 int err = 0;
9936bcf6 10973 u32 cpmuctrl = 0;
9f40dead
MC		 10974
10975 if (!netif_running(tp->dev))
10976 return TG3_LOOPBACK_FAILED;
10977
b9ec6c1b
MC		 10978 err = tg3_reset_hw(tp, 1);
10979 if (err)
10980 return TG3_LOOPBACK_FAILED;
9f40dead 10981
6833c043
MC		 10982 /* Turn off gphy autopowerdown. */
10983 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10984 tg3_phy_toggle_apd(tp, false);
10985
321d32a0 10986 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10987 int i;
10988 u32 status;
10989
10990 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10991
10992 /* Wait for up to 40 microseconds to acquire lock. */
10993 for (i = 0; i < 4; i++) {
10994 status = tr32(TG3_CPMU_MUTEX_GNT);
10995 if (status == CPMU_MUTEX_GNT_DRIVER)
10996 break;
10997 udelay(10);
10998 }
10999
11000 if (status != CPMU_MUTEX_GNT_DRIVER)
11001 return TG3_LOOPBACK_FAILED;
11002
b2a5c19c 11003 /* Turn off link-based power management. */
e875093c 11004 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 11005 tw32(TG3_CPMU_CTRL,
11006 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11007 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 11008 }
11009
9f40dead
MC		 11010 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11011 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 11012
321d32a0 11013 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 11014 tw32(TG3_CPMU_CTRL, cpmuctrl);
11015
11016 /* Release the mutex */
11017 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11018 }
11019
dd477003
MC		 11020 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
11021 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 11022 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11023 err |= TG3_PHY_LOOPBACK_FAILED;
11024 }
11025
6833c043
MC		 11026 /* Re-enable gphy autopowerdown. */
11027 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
11028 tg3_phy_toggle_apd(tp, true);
11029
9f40dead
MC		 11030 return err;
11031}
11032
4cafd3f5
MC		 11033static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11034 u64 *data)
11035{
566f86ad
MC		 11036 struct tg3 *tp = netdev_priv(dev);
11037
bc1c7567
MC		 11038 if (tp->link_config.phy_is_low_power)
11039 tg3_set_power_state(tp, PCI_D0);
11040
566f86ad
MC		 11041 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11042
11043 if (tg3_test_nvram(tp) != 0) {
11044 etest->flags |= ETH_TEST_FL_FAILED;
11045 data[0] = 1;
11046 }
ca43007a
MC		 11047 if (tg3_test_link(tp) != 0) {
11048 etest->flags |= ETH_TEST_FL_FAILED;
11049 data[1] = 1;
11050 }
a71116d1 11051 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 11052 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 11053
11054 if (netif_running(dev)) {
b02fd9e3 11055 tg3_phy_stop(tp);
a71116d1 11056 tg3_netif_stop(tp);
bbe832c0
MC		 11057 irq_sync = 1;
11058 }
a71116d1 11059
bbe832c0 11060 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 11061
11062 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 11063 err = tg3_nvram_lock(tp);
a71116d1
MC		 11064 tg3_halt_cpu(tp, RX_CPU_BASE);
11065 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11066 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 11067 if (!err)
11068 tg3_nvram_unlock(tp);
a71116d1 11069
d9ab5ad1
MC		 11070 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11071 tg3_phy_reset(tp);
11072
a71116d1
MC		 11073 if (tg3_test_registers(tp) != 0) {
11074 etest->flags |= ETH_TEST_FL_FAILED;
11075 data[2] = 1;
11076 }
7942e1db
MC		 11077 if (tg3_test_memory(tp) != 0) {
11078 etest->flags |= ETH_TEST_FL_FAILED;
11079 data[3] = 1;
11080 }
9f40dead 11081 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 11082 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 11083
f47c11ee
DM		 11084 tg3_full_unlock(tp);
11085
d4bc3927
MC		 11086 if (tg3_test_interrupt(tp) != 0) {
11087 etest->flags |= ETH_TEST_FL_FAILED;
11088 data[5] = 1;
11089 }
f47c11ee
DM		 11090
11091 tg3_full_lock(tp, 0);
d4bc3927 11092
a71116d1
MC		 11093 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11094 if (netif_running(dev)) {
11095 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 11096 err2 = tg3_restart_hw(tp, 1);
11097 if (!err2)
b9ec6c1b 11098 tg3_netif_start(tp);
a71116d1 11099 }
f47c11ee
DM		 11100
11101 tg3_full_unlock(tp);
b02fd9e3
MC		 11102
11103 if (irq_sync && !err2)
11104 tg3_phy_start(tp);
a71116d1 11105 }
bc1c7567
MC		 11106 if (tp->link_config.phy_is_low_power)
11107 tg3_set_power_state(tp, PCI_D3hot);
11108
4cafd3f5
MC		 11109}
11110
1da177e4
LT		 11111static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11112{
11113 struct mii_ioctl_data *data = if_mii(ifr);
11114 struct tg3 *tp = netdev_priv(dev);
11115 int err;
11116
b02fd9e3 11117 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11118 struct phy_device *phydev;
b02fd9e3
MC		 11119 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11120 return -EAGAIN;
3f0e3ad7
MC		 11121 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11122 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11123 }
11124
1da177e4
LT		 11125 switch(cmd) {
11126 case SIOCGMIIPHY:
882e9793 11127 data->phy_id = tp->phy_addr;
1da177e4
LT		 11128
11129 /* fallthru */
11130 case SIOCGMIIREG: {
11131 u32 mii_regval;
11132
11133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11134 break; /* We have no PHY */
11135
bc1c7567
MC		 11136 if (tp->link_config.phy_is_low_power)
11137 return -EAGAIN;
11138
f47c11ee 11139 spin_lock_bh(&tp->lock);
1da177e4 11140 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11141 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11142
11143 data->val_out = mii_regval;
11144
11145 return err;
11146 }
11147
11148 case SIOCSMIIREG:
11149 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11150 break; /* We have no PHY */
11151
bc1c7567
MC		 11152 if (tp->link_config.phy_is_low_power)
11153 return -EAGAIN;
11154
f47c11ee 11155 spin_lock_bh(&tp->lock);
1da177e4 11156 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11157 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11158
11159 return err;
11160
11161 default:
11162 /* do nothing */
11163 break;
11164 }
11165 return -EOPNOTSUPP;
11166}
11167
11168#if TG3_VLAN_TAG_USED
11169static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11170{
11171 struct tg3 *tp = netdev_priv(dev);
11172
844b3eed
MC		 11173 if (!netif_running(dev)) {
11174 tp->vlgrp = grp;
11175 return;
11176 }
11177
11178 tg3_netif_stop(tp);
29315e87 11179
f47c11ee 11180 tg3_full_lock(tp, 0);
1da177e4
LT		 11181
11182 tp->vlgrp = grp;
11183
11184 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11185 __tg3_set_rx_mode(dev);
11186
844b3eed 11187 tg3_netif_start(tp);
46966545
MC		 11188
11189 tg3_full_unlock(tp);
1da177e4 11190}
1da177e4
LT		 11191#endif
11192
15f9850d
DM		 11193static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11194{
11195 struct tg3 *tp = netdev_priv(dev);
11196
11197 memcpy(ec, &tp->coal, sizeof(*ec));
11198 return 0;
11199}
11200
d244c892
MC		 11201static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11202{
11203 struct tg3 *tp = netdev_priv(dev);
11204 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11205 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11206
11207 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11208 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11209 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11210 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11211 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11212 }
11213
11214 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11215 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11216 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11217 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11218 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11219 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11220 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11221 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11222 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11223 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11224 return -EINVAL;
11225
11226 /* No rx interrupts will be generated if both are zero */
11227 if ((ec->rx_coalesce_usecs == 0) &&
11228 (ec->rx_max_coalesced_frames == 0))
11229 return -EINVAL;
11230
11231 /* No tx interrupts will be generated if both are zero */
11232 if ((ec->tx_coalesce_usecs == 0) &&
11233 (ec->tx_max_coalesced_frames == 0))
11234 return -EINVAL;
11235
11236 /* Only copy relevant parameters, ignore all others. */
11237 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11238 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11239 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11240 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11241 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11242 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11243 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11244 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11245 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11246
11247 if (netif_running(dev)) {
11248 tg3_full_lock(tp, 0);
11249 __tg3_set_coalesce(tp, &tp->coal);
11250 tg3_full_unlock(tp);
11251 }
11252 return 0;
11253}
11254
7282d491 11255static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11256 .get_settings = tg3_get_settings,
11257 .set_settings = tg3_set_settings,
11258 .get_drvinfo = tg3_get_drvinfo,
11259 .get_regs_len = tg3_get_regs_len,
11260 .get_regs = tg3_get_regs,
11261 .get_wol = tg3_get_wol,
11262 .set_wol = tg3_set_wol,
11263 .get_msglevel = tg3_get_msglevel,
11264 .set_msglevel = tg3_set_msglevel,
11265 .nway_reset = tg3_nway_reset,
11266 .get_link = ethtool_op_get_link,
11267 .get_eeprom_len = tg3_get_eeprom_len,
11268 .get_eeprom = tg3_get_eeprom,
11269 .set_eeprom = tg3_set_eeprom,
11270 .get_ringparam = tg3_get_ringparam,
11271 .set_ringparam = tg3_set_ringparam,
11272 .get_pauseparam = tg3_get_pauseparam,
11273 .set_pauseparam = tg3_set_pauseparam,
11274 .get_rx_csum = tg3_get_rx_csum,
11275 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11276 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11277 .set_sg = ethtool_op_set_sg,
1da177e4 11278 .set_tso = tg3_set_tso,
4cafd3f5 11279 .self_test = tg3_self_test,
1da177e4 11280 .get_strings = tg3_get_strings,
4009a93d 11281 .phys_id = tg3_phys_id,
1da177e4 11282 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11283 .get_coalesce = tg3_get_coalesce,
d244c892 11284 .set_coalesce = tg3_set_coalesce,
b9f2c044 11285 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11286};
11287
11288static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11289{
1b27777a 11290 u32 cursize, val, magic;
1da177e4
LT		 11291
11292 tp->nvram_size = EEPROM_CHIP_SIZE;
11293
e4f34110 11294 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11295 return;
11296
b16250e3
MC		 11297 if ((magic != TG3_EEPROM_MAGIC) &&
11298 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11299 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11300 return;
11301
11302 /*
11303 * Size the chip by reading offsets at increasing powers of two.
11304 * When we encounter our validation signature, we know the addressing
11305 * has wrapped around, and thus have our chip size.
11306 */
1b27777a 11307 cursize = 0x10;
1da177e4
LT		 11308
11309 while (cursize < tp->nvram_size) {
e4f34110 11310 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11311 return;
11312
1820180b 11313 if (val == magic)
1da177e4
LT		 11314 break;
11315
11316 cursize <<= 1;
11317 }
11318
11319 tp->nvram_size = cursize;
11320}
6aa20a22 11321
1da177e4
LT		 11322static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11323{
11324 u32 val;
11325
df259d8c
MC		 11326 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11327 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11328 return;
11329
11330 /* Selfboot format */
1820180b 11331 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11332 tg3_get_eeprom_size(tp);
11333 return;
11334 }
11335
6d348f2c 11336 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11337 if (val != 0) {
6d348f2c
MC		 11338 /* This is confusing. We want to operate on the
11339 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11340 * call will read from NVRAM and byteswap the data
11341 * according to the byteswapping settings for all
11342 * other register accesses. This ensures the data we
11343 * want will always reside in the lower 16-bits.
11344 * However, the data in NVRAM is in LE format, which
11345 * means the data from the NVRAM read will always be
11346 * opposite the endianness of the CPU. The 16-bit
11347 * byteswap then brings the data to CPU endianness.
11348 */
11349 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11350 return;
11351 }
11352 }
fd1122a2 11353 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11354}
11355
11356static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11357{
11358 u32 nvcfg1;
11359
11360 nvcfg1 = tr32(NVRAM_CFG1);
11361 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11362 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11363 } else {
1da177e4
LT		 11364 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11365 tw32(NVRAM_CFG1, nvcfg1);
11366 }
11367
4c987487 11368 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11369 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11370 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11371 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11372 tp->nvram_jedecnum = JEDEC_ATMEL;
11373 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375 break;
11376 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11377 tp->nvram_jedecnum = JEDEC_ATMEL;
11378 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11379 break;
11380 case FLASH_VENDOR_ATMEL_EEPROM:
11381 tp->nvram_jedecnum = JEDEC_ATMEL;
11382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11383 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11384 break;
11385 case FLASH_VENDOR_ST:
11386 tp->nvram_jedecnum = JEDEC_ST;
11387 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11388 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11389 break;
11390 case FLASH_VENDOR_SAIFUN:
11391 tp->nvram_jedecnum = JEDEC_SAIFUN;
11392 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11393 break;
11394 case FLASH_VENDOR_SST_SMALL:
11395 case FLASH_VENDOR_SST_LARGE:
11396 tp->nvram_jedecnum = JEDEC_SST;
11397 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11398 break;
1da177e4 11399 }
8590a603 11400 } else {
1da177e4
LT		 11401 tp->nvram_jedecnum = JEDEC_ATMEL;
11402 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11403 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11404 }
11405}
11406
a1b950d5
MC		 11407static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11408{
11409 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11410 case FLASH_5752PAGE_SIZE_256:
11411 tp->nvram_pagesize = 256;
11412 break;
11413 case FLASH_5752PAGE_SIZE_512:
11414 tp->nvram_pagesize = 512;
11415 break;
11416 case FLASH_5752PAGE_SIZE_1K:
11417 tp->nvram_pagesize = 1024;
11418 break;
11419 case FLASH_5752PAGE_SIZE_2K:
11420 tp->nvram_pagesize = 2048;
11421 break;
11422 case FLASH_5752PAGE_SIZE_4K:
11423 tp->nvram_pagesize = 4096;
11424 break;
11425 case FLASH_5752PAGE_SIZE_264:
11426 tp->nvram_pagesize = 264;
11427 break;
11428 case FLASH_5752PAGE_SIZE_528:
11429 tp->nvram_pagesize = 528;
11430 break;
11431 }
11432}
11433
361b4ac2
MC		 11434static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11435{
11436 u32 nvcfg1;
11437
11438 nvcfg1 = tr32(NVRAM_CFG1);
11439
e6af301b
MC		 11440 /* NVRAM protection for TPM */
11441 if (nvcfg1 & (1 << 27))
f66a29b0 11442 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11443
361b4ac2 11444 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11445 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11446 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11447 tp->nvram_jedecnum = JEDEC_ATMEL;
11448 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449 break;
11450 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11451 tp->nvram_jedecnum = JEDEC_ATMEL;
11452 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11453 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11454 break;
11455 case FLASH_5752VENDOR_ST_M45PE10:
11456 case FLASH_5752VENDOR_ST_M45PE20:
11457 case FLASH_5752VENDOR_ST_M45PE40:
11458 tp->nvram_jedecnum = JEDEC_ST;
11459 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11461 break;
361b4ac2
MC		 11462 }
11463
11464 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11465 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11466 } else {
361b4ac2
MC		 11467 /* For eeprom, set pagesize to maximum eeprom size */
11468 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11469
11470 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11471 tw32(NVRAM_CFG1, nvcfg1);
11472 }
11473}
11474
d3c7b886
MC		 11475static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11476{
989a9d23 11477 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11478
11479 nvcfg1 = tr32(NVRAM_CFG1);
11480
11481 /* NVRAM protection for TPM */
989a9d23 11482 if (nvcfg1 & (1 << 27)) {
f66a29b0 11483 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11484 protect = 1;
11485 }
d3c7b886 11486
989a9d23
MC		 11487 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11488 switch (nvcfg1) {
8590a603
MC		 11489 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11490 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11491 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11492 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11493 tp->nvram_jedecnum = JEDEC_ATMEL;
11494 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11495 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11496 tp->nvram_pagesize = 264;
11497 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11498 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11499 tp->nvram_size = (protect ? 0x3e200 :
11500 TG3_NVRAM_SIZE_512KB);
11501 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11502 tp->nvram_size = (protect ? 0x1f200 :
11503 TG3_NVRAM_SIZE_256KB);
11504 else
11505 tp->nvram_size = (protect ? 0x1f200 :
11506 TG3_NVRAM_SIZE_128KB);
11507 break;
11508 case FLASH_5752VENDOR_ST_M45PE10:
11509 case FLASH_5752VENDOR_ST_M45PE20:
11510 case FLASH_5752VENDOR_ST_M45PE40:
11511 tp->nvram_jedecnum = JEDEC_ST;
11512 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11513 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11514 tp->nvram_pagesize = 256;
11515 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11516 tp->nvram_size = (protect ?
11517 TG3_NVRAM_SIZE_64KB :
11518 TG3_NVRAM_SIZE_128KB);
11519 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11520 tp->nvram_size = (protect ?
11521 TG3_NVRAM_SIZE_64KB :
11522 TG3_NVRAM_SIZE_256KB);
11523 else
11524 tp->nvram_size = (protect ?
11525 TG3_NVRAM_SIZE_128KB :
11526 TG3_NVRAM_SIZE_512KB);
11527 break;
d3c7b886
MC		 11528 }
11529}
11530
1b27777a
MC		 11531static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11532{
11533 u32 nvcfg1;
11534
11535 nvcfg1 = tr32(NVRAM_CFG1);
11536
11537 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11538 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11539 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11540 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11541 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11542 tp->nvram_jedecnum = JEDEC_ATMEL;
11543 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11544 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11545
8590a603
MC		 11546 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11547 tw32(NVRAM_CFG1, nvcfg1);
11548 break;
11549 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11550 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11551 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11552 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11553 tp->nvram_jedecnum = JEDEC_ATMEL;
11554 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11555 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11556 tp->nvram_pagesize = 264;
11557 break;
11558 case FLASH_5752VENDOR_ST_M45PE10:
11559 case FLASH_5752VENDOR_ST_M45PE20:
11560 case FLASH_5752VENDOR_ST_M45PE40:
11561 tp->nvram_jedecnum = JEDEC_ST;
11562 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11563 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11564 tp->nvram_pagesize = 256;
11565 break;
1b27777a
MC		 11566 }
11567}
11568
6b91fa02
MC		 11569static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11570{
11571 u32 nvcfg1, protect = 0;
11572
11573 nvcfg1 = tr32(NVRAM_CFG1);
11574
11575 /* NVRAM protection for TPM */
11576 if (nvcfg1 & (1 << 27)) {
f66a29b0 11577 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11578 protect = 1;
11579 }
11580
11581 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11582 switch (nvcfg1) {
8590a603
MC		 11583 case FLASH_5761VENDOR_ATMEL_ADB021D:
11584 case FLASH_5761VENDOR_ATMEL_ADB041D:
11585 case FLASH_5761VENDOR_ATMEL_ADB081D:
11586 case FLASH_5761VENDOR_ATMEL_ADB161D:
11587 case FLASH_5761VENDOR_ATMEL_MDB021D:
11588 case FLASH_5761VENDOR_ATMEL_MDB041D:
11589 case FLASH_5761VENDOR_ATMEL_MDB081D:
11590 case FLASH_5761VENDOR_ATMEL_MDB161D:
11591 tp->nvram_jedecnum = JEDEC_ATMEL;
11592 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11593 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11594 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11595 tp->nvram_pagesize = 256;
11596 break;
11597 case FLASH_5761VENDOR_ST_A_M45PE20:
11598 case FLASH_5761VENDOR_ST_A_M45PE40:
11599 case FLASH_5761VENDOR_ST_A_M45PE80:
11600 case FLASH_5761VENDOR_ST_A_M45PE16:
11601 case FLASH_5761VENDOR_ST_M_M45PE20:
11602 case FLASH_5761VENDOR_ST_M_M45PE40:
11603 case FLASH_5761VENDOR_ST_M_M45PE80:
11604 case FLASH_5761VENDOR_ST_M_M45PE16:
11605 tp->nvram_jedecnum = JEDEC_ST;
11606 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11607 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11608 tp->nvram_pagesize = 256;
11609 break;
6b91fa02
MC		 11610 }
11611
11612 if (protect) {
11613 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11614 } else {
11615 switch (nvcfg1) {
8590a603
MC		 11616 case FLASH_5761VENDOR_ATMEL_ADB161D:
11617 case FLASH_5761VENDOR_ATMEL_MDB161D:
11618 case FLASH_5761VENDOR_ST_A_M45PE16:
11619 case FLASH_5761VENDOR_ST_M_M45PE16:
11620 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11621 break;
11622 case FLASH_5761VENDOR_ATMEL_ADB081D:
11623 case FLASH_5761VENDOR_ATMEL_MDB081D:
11624 case FLASH_5761VENDOR_ST_A_M45PE80:
11625 case FLASH_5761VENDOR_ST_M_M45PE80:
11626 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11627 break;
11628 case FLASH_5761VENDOR_ATMEL_ADB041D:
11629 case FLASH_5761VENDOR_ATMEL_MDB041D:
11630 case FLASH_5761VENDOR_ST_A_M45PE40:
11631 case FLASH_5761VENDOR_ST_M_M45PE40:
11632 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11633 break;
11634 case FLASH_5761VENDOR_ATMEL_ADB021D:
11635 case FLASH_5761VENDOR_ATMEL_MDB021D:
11636 case FLASH_5761VENDOR_ST_A_M45PE20:
11637 case FLASH_5761VENDOR_ST_M_M45PE20:
11638 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11639 break;
6b91fa02
MC		 11640 }
11641 }
11642}
11643
b5d3772c
MC		 11644static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11645{
11646 tp->nvram_jedecnum = JEDEC_ATMEL;
11647 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11648 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11649}
11650
321d32a0
MC		 11651static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11652{
11653 u32 nvcfg1;
11654
11655 nvcfg1 = tr32(NVRAM_CFG1);
11656
11657 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11658 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11659 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11660 tp->nvram_jedecnum = JEDEC_ATMEL;
11661 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11662 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11663
11664 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11665 tw32(NVRAM_CFG1, nvcfg1);
11666 return;
11667 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11668 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11669 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11670 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11671 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11672 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11673 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11674 tp->nvram_jedecnum = JEDEC_ATMEL;
11675 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11676 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11677
11678 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11679 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11680 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11681 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11682 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11683 break;
11684 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11685 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11686 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11687 break;
11688 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11689 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11690 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11691 break;
11692 }
11693 break;
11694 case FLASH_5752VENDOR_ST_M45PE10:
11695 case FLASH_5752VENDOR_ST_M45PE20:
11696 case FLASH_5752VENDOR_ST_M45PE40:
11697 tp->nvram_jedecnum = JEDEC_ST;
11698 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11699 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11700
11701 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11702 case FLASH_5752VENDOR_ST_M45PE10:
11703 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11704 break;
11705 case FLASH_5752VENDOR_ST_M45PE20:
11706 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11707 break;
11708 case FLASH_5752VENDOR_ST_M45PE40:
11709 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11710 break;
11711 }
11712 break;
11713 default:
df259d8c 11714 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11715 return;
11716 }
11717
a1b950d5
MC		 11718 tg3_nvram_get_pagesize(tp, nvcfg1);
11719 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11720 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11721}
11722
11723
11724static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11725{
11726 u32 nvcfg1;
11727
11728 nvcfg1 = tr32(NVRAM_CFG1);
11729
11730 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11731 case FLASH_5717VENDOR_ATMEL_EEPROM:
11732 case FLASH_5717VENDOR_MICRO_EEPROM:
11733 tp->nvram_jedecnum = JEDEC_ATMEL;
11734 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11735 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11736
11737 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11738 tw32(NVRAM_CFG1, nvcfg1);
11739 return;
11740 case FLASH_5717VENDOR_ATMEL_MDB011D:
11741 case FLASH_5717VENDOR_ATMEL_ADB011B:
11742 case FLASH_5717VENDOR_ATMEL_ADB011D:
11743 case FLASH_5717VENDOR_ATMEL_MDB021D:
11744 case FLASH_5717VENDOR_ATMEL_ADB021B:
11745 case FLASH_5717VENDOR_ATMEL_ADB021D:
11746 case FLASH_5717VENDOR_ATMEL_45USPT:
11747 tp->nvram_jedecnum = JEDEC_ATMEL;
11748 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11749 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11750
11751 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11752 case FLASH_5717VENDOR_ATMEL_MDB021D:
11753 case FLASH_5717VENDOR_ATMEL_ADB021B:
11754 case FLASH_5717VENDOR_ATMEL_ADB021D:
11755 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11756 break;
11757 default:
11758 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11759 break;
11760 }
321d32a0 11761 break;
a1b950d5
MC		 11762 case FLASH_5717VENDOR_ST_M_M25PE10:
11763 case FLASH_5717VENDOR_ST_A_M25PE10:
11764 case FLASH_5717VENDOR_ST_M_M45PE10:
11765 case FLASH_5717VENDOR_ST_A_M45PE10:
11766 case FLASH_5717VENDOR_ST_M_M25PE20:
11767 case FLASH_5717VENDOR_ST_A_M25PE20:
11768 case FLASH_5717VENDOR_ST_M_M45PE20:
11769 case FLASH_5717VENDOR_ST_A_M45PE20:
11770 case FLASH_5717VENDOR_ST_25USPT:
11771 case FLASH_5717VENDOR_ST_45USPT:
11772 tp->nvram_jedecnum = JEDEC_ST;
11773 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11774 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11775
11776 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11777 case FLASH_5717VENDOR_ST_M_M25PE20:
11778 case FLASH_5717VENDOR_ST_A_M25PE20:
11779 case FLASH_5717VENDOR_ST_M_M45PE20:
11780 case FLASH_5717VENDOR_ST_A_M45PE20:
11781 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11782 break;
11783 default:
11784 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11785 break;
11786 }
321d32a0 11787 break;
a1b950d5
MC		 11788 default:
11789 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11790 return;
321d32a0 11791 }
a1b950d5
MC		 11792
11793 tg3_nvram_get_pagesize(tp, nvcfg1);
11794 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11795 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11796}
11797
1da177e4
LT		 11798/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11799static void __devinit tg3_nvram_init(struct tg3 *tp)
11800{
1da177e4
LT		 11801 tw32_f(GRC_EEPROM_ADDR,
11802 (EEPROM_ADDR_FSM_RESET |
11803 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11804 EEPROM_ADDR_CLKPERD_SHIFT)));
11805
9d57f01c 11806 msleep(1);
1da177e4
LT		 11807
11808 /* Enable seeprom accesses. */
11809 tw32_f(GRC_LOCAL_CTRL,
11810 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11811 udelay(100);
11812
11813 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11814 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11815 tp->tg3_flags |= TG3_FLAG_NVRAM;
11816
ec41c7df
MC		 11817 if (tg3_nvram_lock(tp)) {
11818 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11819 "tg3_nvram_init failed.\n", tp->dev->name);
11820 return;
11821 }
e6af301b 11822 tg3_enable_nvram_access(tp);
1da177e4 11823
989a9d23
MC		 11824 tp->nvram_size = 0;
11825
361b4ac2
MC		 11826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11827 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11828 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11829 tg3_get_5755_nvram_info(tp);
d30cdd28 11830 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11831 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11832 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11833 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11834 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11835 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11836 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11837 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11838 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11840 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11841 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11842 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11843 else
11844 tg3_get_nvram_info(tp);
11845
989a9d23
MC		 11846 if (tp->nvram_size == 0)
11847 tg3_get_nvram_size(tp);
1da177e4 11848
e6af301b 11849 tg3_disable_nvram_access(tp);
381291b7 11850 tg3_nvram_unlock(tp);
1da177e4
LT		 11851
11852 } else {
11853 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11854
11855 tg3_get_eeprom_size(tp);
11856 }
11857}
11858
1da177e4
LT		 11859static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11860 u32 offset, u32 len, u8 *buf)
11861{
11862 int i, j, rc = 0;
11863 u32 val;
11864
11865 for (i = 0; i < len; i += 4) {
b9fc7dc5 11866 u32 addr;
a9dc529d 11867 __be32 data;
1da177e4
LT		 11868
11869 addr = offset + i;
11870
11871 memcpy(&data, buf + i, 4);
11872
62cedd11
MC		 11873 /*
11874 * The SEEPROM interface expects the data to always be opposite
11875 * the native endian format. We accomplish this by reversing
11876 * all the operations that would have been performed on the
11877 * data from a call to tg3_nvram_read_be32().
11878 */
11879 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11880
11881 val = tr32(GRC_EEPROM_ADDR);
11882 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11883
11884 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11885 EEPROM_ADDR_READ);
11886 tw32(GRC_EEPROM_ADDR, val |
11887 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11888 (addr & EEPROM_ADDR_ADDR_MASK) |
11889 EEPROM_ADDR_START |
11890 EEPROM_ADDR_WRITE);
6aa20a22 11891
9d57f01c 11892 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11893 val = tr32(GRC_EEPROM_ADDR);
11894
11895 if (val & EEPROM_ADDR_COMPLETE)
11896 break;
9d57f01c 11897 msleep(1);
1da177e4
LT		 11898 }
11899 if (!(val & EEPROM_ADDR_COMPLETE)) {
11900 rc = -EBUSY;
11901 break;
11902 }
11903 }
11904
11905 return rc;
11906}
11907
11908/* offset and length are dword aligned */
11909static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11910 u8 *buf)
11911{
11912 int ret = 0;
11913 u32 pagesize = tp->nvram_pagesize;
11914 u32 pagemask = pagesize - 1;
11915 u32 nvram_cmd;
11916 u8 *tmp;
11917
11918 tmp = kmalloc(pagesize, GFP_KERNEL);
11919 if (tmp == NULL)
11920 return -ENOMEM;
11921
11922 while (len) {
11923 int j;
e6af301b 11924 u32 phy_addr, page_off, size;
1da177e4
LT		 11925
11926 phy_addr = offset & ~pagemask;
6aa20a22 11927
1da177e4 11928 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11929 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11930 (__be32 *) (tmp + j));
11931 if (ret)
1da177e4
LT		 11932 break;
11933 }
11934 if (ret)
11935 break;
11936
11937 page_off = offset & pagemask;
11938 size = pagesize;
11939 if (len < size)
11940 size = len;
11941
11942 len -= size;
11943
11944 memcpy(tmp + page_off, buf, size);
11945
11946 offset = offset + (pagesize - page_off);
11947
e6af301b 11948 tg3_enable_nvram_access(tp);
1da177e4
LT		 11949
11950 /*
11951 * Before we can erase the flash page, we need
11952 * to issue a special "write enable" command.
11953 */
11954 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11955
11956 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11957 break;
11958
11959 /* Erase the target page */
11960 tw32(NVRAM_ADDR, phy_addr);
11961
11962 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11963 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11964
11965 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11966 break;
11967
11968 /* Issue another write enable to start the write. */
11969 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11970
11971 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11972 break;
11973
11974 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11975 __be32 data;
1da177e4 11976
b9fc7dc5 11977 data = *((__be32 *) (tmp + j));
a9dc529d 11978
b9fc7dc5 11979 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11980
11981 tw32(NVRAM_ADDR, phy_addr + j);
11982
11983 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11984 NVRAM_CMD_WR;
11985
11986 if (j == 0)
11987 nvram_cmd |= NVRAM_CMD_FIRST;
11988 else if (j == (pagesize - 4))
11989 nvram_cmd |= NVRAM_CMD_LAST;
11990
11991 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11992 break;
11993 }
11994 if (ret)
11995 break;
11996 }
11997
11998 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11999 tg3_nvram_exec_cmd(tp, nvram_cmd);
12000
12001 kfree(tmp);
12002
12003 return ret;
12004}
12005
12006/* offset and length are dword aligned */
12007static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12008 u8 *buf)
12009{
12010 int i, ret = 0;
12011
12012 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 12013 u32 page_off, phy_addr, nvram_cmd;
12014 __be32 data;
1da177e4
LT		 12015
12016 memcpy(&data, buf + i, 4);
b9fc7dc5 12017 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 12018
12019 page_off = offset % tp->nvram_pagesize;
12020
1820180b 12021 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 12022
12023 tw32(NVRAM_ADDR, phy_addr);
12024
12025 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12026
12027 if ((page_off == 0) || (i == 0))
12028 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 12029 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 12030 nvram_cmd |= NVRAM_CMD_LAST;
12031
12032 if (i == (len - 4))
12033 nvram_cmd |= NVRAM_CMD_LAST;
12034
321d32a0
MC		 12035 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12036 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 12037 (tp->nvram_jedecnum == JEDEC_ST) &&
12038 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 12039
12040 if ((ret = tg3_nvram_exec_cmd(tp,
12041 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12042 NVRAM_CMD_DONE)))
12043
12044 break;
12045 }
12046 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12047 /* We always do complete word writes to eeprom. */
12048 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12049 }
12050
12051 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12052 break;
12053 }
12054 return ret;
12055}
12056
12057/* offset and length are dword aligned */
12058static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12059{
12060 int ret;
12061
1da177e4 12062 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 12063 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12064 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 12065 udelay(40);
12066 }
12067
12068 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12069 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12070 }
12071 else {
12072 u32 grc_mode;
12073
ec41c7df
MC		 12074 ret = tg3_nvram_lock(tp);
12075 if (ret)
12076 return ret;
1da177e4 12077
e6af301b
MC		 12078 tg3_enable_nvram_access(tp);
12079 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 12080 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 12081 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 12082
12083 grc_mode = tr32(GRC_MODE);
12084 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12085
12086 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12087 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12088
12089 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12090 buf);
12091 }
12092 else {
12093 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12094 buf);
12095 }
12096
12097 grc_mode = tr32(GRC_MODE);
12098 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12099
e6af301b 12100 tg3_disable_nvram_access(tp);
1da177e4
LT		 12101 tg3_nvram_unlock(tp);
12102 }
12103
12104 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 12105 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 12106 udelay(40);
12107 }
12108
12109 return ret;
12110}
12111
12112struct subsys_tbl_ent {
12113 u16 subsys_vendor, subsys_devid;
12114 u32 phy_id;
12115};
12116
24daf2b0 12117static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
1da177e4 12118 /* Broadcom boards. */
24daf2b0 12119 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12120 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 12121 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12122 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 12123 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12124 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 12125 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12126 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12127 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12128 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 12129 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12130 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12131 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12132 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12133 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12134 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 12135 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12136 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 12137 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12138 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 12139 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12140 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 12141
12142 /* 3com boards. */
24daf2b0 12143 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12144 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 12145 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12146 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12147 { TG3PCI_SUBVENDOR_ID_3COM,
12148 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12149 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12150 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 12151 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12152 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 12153
12154 /* DELL boards. */
24daf2b0 12155 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12156 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 12157 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12158 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 12159 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12160 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 12161 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12162 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 12163
12164 /* Compaq boards. */
24daf2b0 12165 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12166 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 12167 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12168 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12169 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12170 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12171 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12172 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 12173 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12174 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 12175
12176 /* IBM boards. */
24daf2b0
MC		 12177 { TG3PCI_SUBVENDOR_ID_IBM,
12178 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 12179};
12180
24daf2b0 12181static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 12182{
12183 int i;
12184
12185 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12186 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12187 tp->pdev->subsystem_vendor) &&
12188 (subsys_id_to_phy_id[i].subsys_devid ==
12189 tp->pdev->subsystem_device))
12190 return &subsys_id_to_phy_id[i];
12191 }
12192 return NULL;
12193}
12194
7d0c41ef 12195static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12196{
1da177e4 12197 u32 val;
caf636c7
MC		 12198 u16 pmcsr;
12199
12200 /* On some early chips the SRAM cannot be accessed in D3hot state,
12201 * so need make sure we're in D0.
12202 */
12203 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12204 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12205 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12206 msleep(1);
7d0c41ef
MC		 12207
12208 /* Make sure register accesses (indirect or otherwise)
12209 * will function correctly.
12210 */
12211 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12212 tp->misc_host_ctrl);
1da177e4 12213
f49639e6
DM		 12214 /* The memory arbiter has to be enabled in order for SRAM accesses
12215 * to succeed. Normally on powerup the tg3 chip firmware will make
12216 * sure it is enabled, but other entities such as system netboot
12217 * code might disable it.
12218 */
12219 val = tr32(MEMARB_MODE);
12220 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12221
79eb6904 12222 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 12223 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12224
a85feb8c
GZ		 12225 /* Assume an onboard device and WOL capable by default. */
12226 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12227
b5d3772c 12228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12229 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12230 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12231 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12232 }
0527ba35
MC		 12233 val = tr32(VCPU_CFGSHDW);
12234 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12235 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12236 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12237 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12238 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12239 goto done;
b5d3772c
MC		 12240 }
12241
1da177e4
LT		 12242 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12243 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12244 u32 nic_cfg, led_cfg;
a9daf367 12245 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12246 int eeprom_phy_serdes = 0;
1da177e4
LT		 12247
12248 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12249 tp->nic_sram_data_cfg = nic_cfg;
12250
12251 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12252 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12253 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12254 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12255 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12256 (ver > 0) && (ver < 0x100))
12257 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12258
a9daf367
MC		 12259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12260 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12261
1da177e4
LT		 12262 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12263 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12264 eeprom_phy_serdes = 1;
12265
12266 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12267 if (nic_phy_id != 0) {
12268 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12269 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12270
12271 eeprom_phy_id = (id1 >> 16) << 10;
12272 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12273 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12274 } else
12275 eeprom_phy_id = 0;
12276
7d0c41ef 12277 tp->phy_id = eeprom_phy_id;
747e8f8b 12278 if (eeprom_phy_serdes) {
d1ec96af
MC		 12279 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12280 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12281 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12282 else
12283 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12284 }
7d0c41ef 12285
cbf46853 12286 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12287 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12288 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12289 else
1da177e4
LT		 12290 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12291
12292 switch (led_cfg) {
12293 default:
12294 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12295 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12296 break;
12297
12298 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12299 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12300 break;
12301
12302 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12303 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12304
12305 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12306 * read on some older 5700/5701 bootcode.
12307 */
12308 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12309 ASIC_REV_5700 ||
12310 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12311 ASIC_REV_5701)
12312 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12313
1da177e4
LT		 12314 break;
12315
12316 case SHASTA_EXT_LED_SHARED:
12317 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12318 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12319 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12320 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12321 LED_CTRL_MODE_PHY_2);
12322 break;
12323
12324 case SHASTA_EXT_LED_MAC:
12325 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12326 break;
12327
12328 case SHASTA_EXT_LED_COMBO:
12329 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12330 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12331 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12332 LED_CTRL_MODE_PHY_2);
12333 break;
12334
855e1111 12335 }
1da177e4
LT		 12336
12337 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12338 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12339 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12340 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12341
b2a5c19c
MC		 12342 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12343 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12344
9d26e213 12345 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12346 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12347 if ((tp->pdev->subsystem_vendor ==
12348 PCI_VENDOR_ID_ARIMA) &&
12349 (tp->pdev->subsystem_device == 0x205a ||
12350 tp->pdev->subsystem_device == 0x2063))
12351 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12352 } else {
f49639e6 12353 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12354 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12355 }
1da177e4
LT		 12356
12357 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12358 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12359 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12360 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12361 }
b2b98d4a
MC		 12362
12363 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12364 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12365 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12366
a85feb8c
GZ		 12367 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12368 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12369 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12370
12dac075 12371 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12372 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12373 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12374
1da177e4
LT		 12375 if (cfg2 & (1 << 17))
12376 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12377
12378 /* serdes signal pre-emphasis in register 0x590 set by */
12379 /* bootcode if bit 18 is set */
12380 if (cfg2 & (1 << 18))
12381 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12382
321d32a0
MC		 12383 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12384 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12385 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12386 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12387
8ed5d97e
MC		 12388 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12389 u32 cfg3;
12390
12391 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12392 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12393 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12394 }
a9daf367 12395
14417063
MC		 12396 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12397 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
a9daf367
MC		 12398 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12399 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12400 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12401 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12402 }
05ac4cb7
MC		 12403done:
12404 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12405 device_set_wakeup_enable(&tp->pdev->dev,
12406 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12407}
12408
b2a5c19c
MC		 12409static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12410{
12411 int i;
12412 u32 val;
12413
12414 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12415 tw32(OTP_CTRL, cmd);
12416
12417 /* Wait for up to 1 ms for command to execute. */
12418 for (i = 0; i < 100; i++) {
12419 val = tr32(OTP_STATUS);
12420 if (val & OTP_STATUS_CMD_DONE)
12421 break;
12422 udelay(10);
12423 }
12424
12425 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12426}
12427
12428/* Read the gphy configuration from the OTP region of the chip. The gphy
12429 * configuration is a 32-bit value that straddles the alignment boundary.
12430 * We do two 32-bit reads and then shift and merge the results.
12431 */
12432static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12433{
12434 u32 bhalf_otp, thalf_otp;
12435
12436 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12437
12438 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12439 return 0;
12440
12441 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12442
12443 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12444 return 0;
12445
12446 thalf_otp = tr32(OTP_READ_DATA);
12447
12448 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12449
12450 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12451 return 0;
12452
12453 bhalf_otp = tr32(OTP_READ_DATA);
12454
12455 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12456}
12457
7d0c41ef
MC		 12458static int __devinit tg3_phy_probe(struct tg3 *tp)
12459{
12460 u32 hw_phy_id_1, hw_phy_id_2;
12461 u32 hw_phy_id, hw_phy_id_masked;
12462 int err;
1da177e4 12463
b02fd9e3
MC		 12464 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12465 return tg3_phy_init(tp);
12466
1da177e4 12467 /* Reading the PHY ID register can conflict with ASF
877d0310 12468 * firmware access to the PHY hardware.
1da177e4
LT		 12469 */
12470 err = 0;
0d3031d9
MC		 12471 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12472 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
79eb6904 12473 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 12474 } else {
12475 /* Now read the physical PHY_ID from the chip and verify
12476 * that it is sane. If it doesn't look good, we fall back
12477 * to either the hard-coded table based PHY_ID and failing
12478 * that the value found in the eeprom area.
12479 */
12480 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12481 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12482
12483 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12484 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12485 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12486
79eb6904 12487 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 12488 }
12489
79eb6904 12490 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 12491 tp->phy_id = hw_phy_id;
79eb6904 12492 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
1da177e4 12493 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12494 else
12495 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12496 } else {
79eb6904 12497 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 12498 /* Do nothing, phy ID already set up in
12499 * tg3_get_eeprom_hw_cfg().
12500 */
1da177e4
LT		 12501 } else {
12502 struct subsys_tbl_ent *p;
12503
12504 /* No eeprom signature? Try the hardcoded
12505 * subsys device table.
12506 */
24daf2b0 12507 p = tg3_lookup_by_subsys(tp);
1da177e4
LT		 12508 if (!p)
12509 return -ENODEV;
12510
12511 tp->phy_id = p->phy_id;
12512 if (!tp->phy_id ||
79eb6904 12513 tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 12514 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12515 }
12516 }
12517
747e8f8b 12518 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12519 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12520 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12521 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12522
12523 tg3_readphy(tp, MII_BMSR, &bmsr);
12524 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12525 (bmsr & BMSR_LSTATUS))
12526 goto skip_phy_reset;
6aa20a22 12527
1da177e4
LT		 12528 err = tg3_phy_reset(tp);
12529 if (err)
12530 return err;
12531
12532 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12533 ADVERTISE_100HALF | ADVERTISE_100FULL |
12534 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12535 tg3_ctrl = 0;
12536 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12537 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12538 MII_TG3_CTRL_ADV_1000_FULL);
12539 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12540 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12541 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12542 MII_TG3_CTRL_ENABLE_AS_MASTER);
12543 }
12544
3600d918
MC		 12545 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12546 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12547 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12548 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12549 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12550
12551 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12552 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12553
12554 tg3_writephy(tp, MII_BMCR,
12555 BMCR_ANENABLE | BMCR_ANRESTART);
12556 }
12557 tg3_phy_set_wirespeed(tp);
12558
12559 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12560 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12561 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12562 }
12563
12564skip_phy_reset:
79eb6904 12565 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 12566 err = tg3_init_5401phy_dsp(tp);
12567 if (err)
12568 return err;
1da177e4 12569
1da177e4
LT		 12570 err = tg3_init_5401phy_dsp(tp);
12571 }
12572
747e8f8b 12573 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12574 tp->link_config.advertising =
12575 (ADVERTISED_1000baseT_Half |
12576 ADVERTISED_1000baseT_Full |
12577 ADVERTISED_Autoneg |
12578 ADVERTISED_FIBRE);
12579 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12580 tp->link_config.advertising &=
12581 ~(ADVERTISED_1000baseT_Half |
12582 ADVERTISED_1000baseT_Full);
12583
12584 return err;
12585}
12586
12587static void __devinit tg3_read_partno(struct tg3 *tp)
12588{
141518c9 12589 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12590 unsigned int i;
1b27777a 12591 u32 magic;
1da177e4 12592
df259d8c
MC		 12593 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12594 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12595 goto out_not_found;
1da177e4 12596
1820180b 12597 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12598 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12599 u32 tmp;
1da177e4 12600
6d348f2c
MC		 12601 /* The data is in little-endian format in NVRAM.
12602 * Use the big-endian read routines to preserve
12603 * the byte order as it exists in NVRAM.
12604 */
141518c9 12605 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12606 goto out_not_found;
12607
6d348f2c 12608 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12609 }
12610 } else {
94c982bd
MC		 12611 ssize_t cnt;
12612 unsigned int pos = 0, i = 0;
12613
12614 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12615 cnt = pci_read_vpd(tp->pdev, pos,
12616 TG3_NVM_VPD_LEN - pos,
12617 &vpd_data[pos]);
12618 if (cnt == -ETIMEDOUT || -EINTR)
12619 cnt = 0;
12620 else if (cnt < 0)
f49639e6 12621 goto out_not_found;
1b27777a 12622 }
94c982bd
MC		 12623 if (pos != TG3_NVM_VPD_LEN)
12624 goto out_not_found;
1da177e4
LT		 12625 }
12626
12627 /* Now parse and find the part number. */
141518c9 12628 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12629 unsigned char val = vpd_data[i];
af2c6a4a 12630 unsigned int block_end;
1da177e4
LT		 12631
12632 if (val == 0x82 || val == 0x91) {
12633 i = (i + 3 +
12634 (vpd_data[i + 1] +
12635 (vpd_data[i + 2] << 8)));
12636 continue;
12637 }
12638
12639 if (val != 0x90)
12640 goto out_not_found;
12641
12642 block_end = (i + 3 +
12643 (vpd_data[i + 1] +
12644 (vpd_data[i + 2] << 8)));
12645 i += 3;
af2c6a4a 12646
141518c9 12647 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12648 goto out_not_found;
12649
12650 while (i < (block_end - 2)) {
1da177e4
LT		 12651 if (vpd_data[i + 0] == 'P' &&
12652 vpd_data[i + 1] == 'N') {
12653 int partno_len = vpd_data[i + 2];
12654
af2c6a4a 12655 i += 3;
141518c9
MC		 12656 if (partno_len > TG3_BPN_SIZE ||
12657 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12658 goto out_not_found;
12659
12660 memcpy(tp->board_part_number,
af2c6a4a 12661 &vpd_data[i], partno_len);
1da177e4
LT		 12662
12663 /* Success. */
12664 return;
12665 }
af2c6a4a 12666 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12667 }
12668
12669 /* Part number not found. */
12670 goto out_not_found;
12671 }
12672
12673out_not_found:
b5d3772c
MC		 12674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12675 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12676 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12677 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12678 strcpy(tp->board_part_number, "BCM57780");
12679 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12681 strcpy(tp->board_part_number, "BCM57760");
12682 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12684 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12685 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12687 strcpy(tp->board_part_number, "BCM57788");
b474eca7
MC		 12688 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12690 strcpy(tp->board_part_number, "BCM57761");
12691 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12692 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
b703df6f 12693 strcpy(tp->board_part_number, "BCM57765");
b474eca7
MC		 12694 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12695 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12696 strcpy(tp->board_part_number, "BCM57781");
12697 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12698 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12699 strcpy(tp->board_part_number, "BCM57785");
12700 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12701 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12702 strcpy(tp->board_part_number, "BCM57791");
12703 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12704 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12705 strcpy(tp->board_part_number, "BCM57795");
b5d3772c
MC		 12706 else
12707 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12708}
12709
9c8a620e
MC		 12710static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12711{
12712 u32 val;
12713
e4f34110 12714 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12715 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12716 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12717 val != 0)
12718 return 0;
12719
12720 return 1;
12721}
12722
acd9c119
MC		 12723static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12724{
ff3a7cb2 12725 u32 val, offset, start, ver_offset;
acd9c119 12726 int i;
ff3a7cb2 12727 bool newver = false;
acd9c119
MC		 12728
12729 if (tg3_nvram_read(tp, 0xc, &offset) ||
12730 tg3_nvram_read(tp, 0x4, &start))
12731 return;
12732
12733 offset = tg3_nvram_logical_addr(tp, offset);
12734
ff3a7cb2 12735 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12736 return;
12737
ff3a7cb2
MC		 12738 if ((val & 0xfc000000) == 0x0c000000) {
12739 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12740 return;
12741
ff3a7cb2
MC		 12742 if (val == 0)
12743 newver = true;
12744 }
12745
12746 if (newver) {
12747 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12748 return;
12749
12750 offset = offset + ver_offset - start;
12751 for (i = 0; i < 16; i += 4) {
12752 __be32 v;
12753 if (tg3_nvram_read_be32(tp, offset + i, &v))
12754 return;
12755
12756 memcpy(tp->fw_ver + i, &v, sizeof(v));
12757 }
12758 } else {
12759 u32 major, minor;
12760
12761 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12762 return;
12763
12764 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12765 TG3_NVM_BCVER_MAJSFT;
12766 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12767 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12768 }
12769}
12770
a6f6cb1c
MC		 12771static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12772{
12773 u32 val, major, minor;
12774
12775 /* Use native endian representation */
12776 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12777 return;
12778
12779 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12780 TG3_NVM_HWSB_CFG1_MAJSFT;
12781 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12782 TG3_NVM_HWSB_CFG1_MINSFT;
12783
12784 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12785}
12786
dfe00d7d
MC		 12787static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12788{
12789 u32 offset, major, minor, build;
12790
12791 tp->fw_ver[0] = 's';
12792 tp->fw_ver[1] = 'b';
12793 tp->fw_ver[2] = '\0';
12794
12795 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12796 return;
12797
12798 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12799 case TG3_EEPROM_SB_REVISION_0:
12800 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12801 break;
12802 case TG3_EEPROM_SB_REVISION_2:
12803 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12804 break;
12805 case TG3_EEPROM_SB_REVISION_3:
12806 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12807 break;
a4153d40
MC		 12808 case TG3_EEPROM_SB_REVISION_4:
12809 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12810 break;
12811 case TG3_EEPROM_SB_REVISION_5:
12812 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12813 break;
dfe00d7d
MC		 12814 default:
12815 return;
12816 }
12817
e4f34110 12818 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12819 return;
12820
12821 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12822 TG3_EEPROM_SB_EDH_BLD_SHFT;
12823 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12824 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12825 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12826
12827 if (minor > 99 || build > 26)
12828 return;
12829
12830 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12831
12832 if (build > 0) {
12833 tp->fw_ver[8] = 'a' + build - 1;
12834 tp->fw_ver[9] = '\0';
12835 }
12836}
12837
acd9c119 12838static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12839{
12840 u32 val, offset, start;
acd9c119 12841 int i, vlen;
9c8a620e
MC		 12842
12843 for (offset = TG3_NVM_DIR_START;
12844 offset < TG3_NVM_DIR_END;
12845 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12846 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12847 return;
12848
9c8a620e
MC		 12849 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12850 break;
12851 }
12852
12853 if (offset == TG3_NVM_DIR_END)
12854 return;
12855
12856 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12857 start = 0x08000000;
e4f34110 12858 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12859 return;
12860
e4f34110 12861 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12862 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12863 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12864 return;
12865
12866 offset += val - start;
12867
acd9c119 12868 vlen = strlen(tp->fw_ver);
9c8a620e 12869
acd9c119
MC		 12870 tp->fw_ver[vlen++] = ',';
12871 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12872
12873 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12874 __be32 v;
12875 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12876 return;
12877
b9fc7dc5 12878 offset += sizeof(v);
c4e6575c 12879
acd9c119
MC		 12880 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12881 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12882 break;
c4e6575c 12883 }
9c8a620e 12884
acd9c119
MC		 12885 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12886 vlen += sizeof(v);
c4e6575c 12887 }
acd9c119
MC		 12888}
12889
7fd76445
MC		 12890static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12891{
12892 int vlen;
12893 u32 apedata;
12894
12895 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12896 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12897 return;
12898
12899 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12900 if (apedata != APE_SEG_SIG_MAGIC)
12901 return;
12902
12903 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12904 if (!(apedata & APE_FW_STATUS_READY))
12905 return;
12906
12907 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12908
12909 vlen = strlen(tp->fw_ver);
12910
12911 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12912 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12913 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12914 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12915 (apedata & APE_FW_VERSION_BLDMSK));
12916}
12917
acd9c119
MC		 12918static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12919{
12920 u32 val;
12921
df259d8c
MC		 12922 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12923 tp->fw_ver[0] = 's';
12924 tp->fw_ver[1] = 'b';
12925 tp->fw_ver[2] = '\0';
12926
12927 return;
12928 }
12929
acd9c119
MC		 12930 if (tg3_nvram_read(tp, 0, &val))
12931 return;
12932
12933 if (val == TG3_EEPROM_MAGIC)
12934 tg3_read_bc_ver(tp);
12935 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12936 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12937 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12938 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12939 else
12940 return;
12941
12942 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12943 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12944 return;
12945
12946 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12947
12948 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12949}
12950
7544b097
MC		 12951static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12952
1da177e4
LT		 12953static int __devinit tg3_get_invariants(struct tg3 *tp)
12954{
12955 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12956 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12957 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12958 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12959 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12960 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12961 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12962 { },
12963 };
12964 u32 misc_ctrl_reg;
1da177e4
LT		 12965 u32 pci_state_reg, grc_misc_cfg;
12966 u32 val;
12967 u16 pci_cmd;
5e7dfd0f 12968 int err;
1da177e4 12969
1da177e4
LT		 12970 /* Force memory write invalidate off. If we leave it on,
12971 * then on 5700_BX chips we have to enable a workaround.
12972 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12973 * to match the cacheline size. The Broadcom driver have this
12974 * workaround but turns MWI off all the times so never uses
12975 * it. This seems to suggest that the workaround is insufficient.
12976 */
12977 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12978 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12979 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12980
12981 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12982 * has the register indirect write enable bit set before
12983 * we try to access any of the MMIO registers. It is also
12984 * critical that the PCI-X hw workaround situation is decided
12985 * before that as well.
12986 */
12987 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12988 &misc_ctrl_reg);
12989
12990 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12991 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12993 u32 prod_id_asic_rev;
12994
5001e2f6
MC		 12995 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12997 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12998 pci_read_config_dword(tp->pdev,
12999 TG3PCI_GEN2_PRODID_ASICREV,
13000 &prod_id_asic_rev);
b703df6f
MC		 13001 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13002 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13003 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13004 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13005 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13006 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13007 pci_read_config_dword(tp->pdev,
13008 TG3PCI_GEN15_PRODID_ASICREV,
13009 &prod_id_asic_rev);
f6eb9b1f
MC		 13010 else
13011 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13012 &prod_id_asic_rev);
13013
321d32a0 13014 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 13015 }
1da177e4 13016
ff645bec
MC		 13017 /* Wrong chip ID in 5752 A0. This code can be removed later
13018 * as A0 is not in production.
13019 */
13020 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13021 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13022
6892914f
MC		 13023 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13024 * we need to disable memory and use config. cycles
13025 * only to access all registers. The 5702/03 chips
13026 * can mistakenly decode the special cycles from the
13027 * ICH chipsets as memory write cycles, causing corruption
13028 * of register and memory space. Only certain ICH bridges
13029 * will drive special cycles with non-zero data during the
13030 * address phase which can fall within the 5703's address
13031 * range. This is not an ICH bug as the PCI spec allows
13032 * non-zero address during special cycles. However, only
13033 * these ICH bridges are known to drive non-zero addresses
13034 * during special cycles.
13035 *
13036 * Since special cycles do not cross PCI bridges, we only
13037 * enable this workaround if the 5703 is on the secondary
13038 * bus of these ICH bridges.
13039 */
13040 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13041 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13042 static struct tg3_dev_id {
13043 u32 vendor;
13044 u32 device;
13045 u32 rev;
13046 } ich_chipsets[] = {
13047 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13048 PCI_ANY_ID },
13049 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13050 PCI_ANY_ID },
13051 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13052 0xa },
13053 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13054 PCI_ANY_ID },
13055 { },
13056 };
13057 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13058 struct pci_dev *bridge = NULL;
13059
13060 while (pci_id->vendor != 0) {
13061 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13062 bridge);
13063 if (!bridge) {
13064 pci_id++;
13065 continue;
13066 }
13067 if (pci_id->rev != PCI_ANY_ID) {
44c10138 13068 if (bridge->revision > pci_id->rev)
6892914f
MC		 13069 continue;
13070 }
13071 if (bridge->subordinate &&
13072 (bridge->subordinate->number ==
13073 tp->pdev->bus->number)) {
13074
13075 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13076 pci_dev_put(bridge);
13077 break;
13078 }
13079 }
13080 }
13081
41588ba1
MC		 13082 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13083 static struct tg3_dev_id {
13084 u32 vendor;
13085 u32 device;
13086 } bridge_chipsets[] = {
13087 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13088 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13089 { },
13090 };
13091 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13092 struct pci_dev *bridge = NULL;
13093
13094 while (pci_id->vendor != 0) {
13095 bridge = pci_get_device(pci_id->vendor,
13096 pci_id->device,
13097 bridge);
13098 if (!bridge) {
13099 pci_id++;
13100 continue;
13101 }
13102 if (bridge->subordinate &&
13103 (bridge->subordinate->number <=
13104 tp->pdev->bus->number) &&
13105 (bridge->subordinate->subordinate >=
13106 tp->pdev->bus->number)) {
13107 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13108 pci_dev_put(bridge);
13109 break;
13110 }
13111 }
13112 }
13113
4a29cc2e
MC		 13114 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13115 * DMA addresses > 40-bit. This bridge may have other additional
13116 * 57xx devices behind it in some 4-port NIC designs for example.
13117 * Any tg3 device found behind the bridge will also need the 40-bit
13118 * DMA workaround.
13119 */
a4e2b347
MC		 13120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13122 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 13123 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 13124 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 13125 }
4a29cc2e
MC		 13126 else {
13127 struct pci_dev *bridge = NULL;
13128
13129 do {
13130 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13131 PCI_DEVICE_ID_SERVERWORKS_EPB,
13132 bridge);
13133 if (bridge && bridge->subordinate &&
13134 (bridge->subordinate->number <=
13135 tp->pdev->bus->number) &&
13136 (bridge->subordinate->subordinate >=
13137 tp->pdev->bus->number)) {
13138 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13139 pci_dev_put(bridge);
13140 break;
13141 }
13142 } while (bridge);
13143 }
4cf78e4f 13144
1da177e4
LT		 13145 /* Initialize misc host control in PCI block. */
13146 tp->misc_host_ctrl |= (misc_ctrl_reg &
13147 MISC_HOST_CTRL_CHIPREV);
13148 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13149 tp->misc_host_ctrl);
13150
f6eb9b1f
MC		 13151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 13154 tp->pdev_peer = tg3_find_peer(tp);
13155
321d32a0
MC		 13156 /* Intentionally exclude ASIC_REV_5906 */
13157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 13158 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 13159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 13160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13165 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13166
13167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13170 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13171 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13172 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13173
1b440c56
JL		 13174 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13175 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13176 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13177
027455ad
MC		 13178 /* 5700 B0 chips do not support checksumming correctly due
13179 * to hardware bugs.
13180 */
13181 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13182 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13183 else {
13184 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13185 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13186 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13187 tp->dev->features |= NETIF_F_IPV6_CSUM;
13188 }
13189
507399f1 13190 /* Determine TSO capabilities */
b703df6f
MC		 13191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13193 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13194 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13195 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13196 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13197 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13198 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13199 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13200 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13201 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13202 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13203 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13204 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13205 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13207 tp->fw_needed = FIRMWARE_TG3TSO5;
13208 else
13209 tp->fw_needed = FIRMWARE_TG3TSO;
13210 }
13211
13212 tp->irq_max = 1;
13213
5a6f3074 13214 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13215 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13216 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13217 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13218 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13219 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13220 tp->pdev_peer == tp->pdev))
13221 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13222
321d32a0 13223 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13225 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13226 }
4f125f42 13227
b703df6f
MC		 13228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13230 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13231 tp->irq_max = TG3_IRQ_MAX_VECS;
13232 }
f6eb9b1f 13233 }
0e1406dd 13234
615774fe
MC		 13235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13237 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13238 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13239 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13240 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13241 }
f6eb9b1f 13242
b703df6f
MC		 13243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13244 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13245 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13246
f51f3562 13247 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13248 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13249 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13250 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13251
52f4490c
MC		 13252 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13253 &pci_state_reg);
13254
5e7dfd0f
MC		 13255 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13256 if (tp->pcie_cap != 0) {
13257 u16 lnkctl;
13258
1da177e4 13259 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13260
13261 pcie_set_readrq(tp->pdev, 4096);
13262
5e7dfd0f
MC		 13263 pci_read_config_word(tp->pdev,
13264 tp->pcie_cap + PCI_EXP_LNKCTL,
13265 &lnkctl);
13266 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13268 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13271 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13272 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13273 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13274 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13275 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13276 }
52f4490c 13277 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13278 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13279 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13280 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13281 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13282 if (!tp->pcix_cap) {
13283 printk(KERN_ERR PFX "Cannot find PCI-X "
13284 "capability, aborting.\n");
13285 return -EIO;
13286 }
13287
13288 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13289 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13290 }
1da177e4 13291
399de50b
MC		 13292 /* If we have an AMD 762 or VIA K8T800 chipset, write
13293 * reordering to the mailbox registers done by the host
13294 * controller can cause major troubles. We read back from
13295 * every mailbox register write to force the writes to be
13296 * posted to the chip in order.
13297 */
13298 if (pci_dev_present(write_reorder_chipsets) &&
13299 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13300 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13301
69fc4053
MC		 13302 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13303 &tp->pci_cacheline_sz);
13304 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13305 &tp->pci_lat_timer);
1da177e4
LT		 13306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13307 tp->pci_lat_timer < 64) {
13308 tp->pci_lat_timer = 64;
69fc4053
MC		 13309 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13310 tp->pci_lat_timer);
1da177e4
LT		 13311 }
13312
52f4490c
MC		 13313 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13314 /* 5700 BX chips need to have their TX producer index
13315 * mailboxes written twice to workaround a bug.
13316 */
13317 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13318
52f4490c 13319 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13320 *
13321 * The workaround is to use indirect register accesses
13322 * for all chip writes not to mailbox registers.
13323 */
52f4490c 13324 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13325 u32 pm_reg;
1da177e4
LT		 13326
13327 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13328
13329 /* The chip can have it's power management PCI config
13330 * space registers clobbered due to this bug.
13331 * So explicitly force the chip into D0 here.
13332 */
9974a356
MC		 13333 pci_read_config_dword(tp->pdev,
13334 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13335 &pm_reg);
13336 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13337 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13338 pci_write_config_dword(tp->pdev,
13339 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13340 pm_reg);
13341
13342 /* Also, force SERR#/PERR# in PCI command. */
13343 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13344 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13345 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13346 }
13347 }
13348
1da177e4
LT		 13349 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13350 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13351 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13352 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13353
13354 /* Chip-specific fixup from Broadcom driver */
13355 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13356 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13357 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13358 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13359 }
13360
1ee582d8 13361 /* Default fast path register access methods */
20094930 13362 tp->read32 = tg3_read32;
1ee582d8 13363 tp->write32 = tg3_write32;
09ee929c 13364 tp->read32_mbox = tg3_read32;
20094930 13365 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13366 tp->write32_tx_mbox = tg3_write32;
13367 tp->write32_rx_mbox = tg3_write32;
13368
13369 /* Various workaround register access methods */
13370 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13371 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13372 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13373 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13374 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13375 /*
13376 * Back to back register writes can cause problems on these
13377 * chips, the workaround is to read back all reg writes
13378 * except those to mailbox regs.
13379 *
13380 * See tg3_write_indirect_reg32().
13381 */
1ee582d8 13382 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13383 }
13384
1ee582d8
MC		 13385 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13386 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13387 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13388 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13389 tp->write32_rx_mbox = tg3_write_flush_reg32;
13390 }
20094930 13391
6892914f
MC		 13392 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13393 tp->read32 = tg3_read_indirect_reg32;
13394 tp->write32 = tg3_write_indirect_reg32;
13395 tp->read32_mbox = tg3_read_indirect_mbox;
13396 tp->write32_mbox = tg3_write_indirect_mbox;
13397 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13398 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13399
13400 iounmap(tp->regs);
22abe310 13401 tp->regs = NULL;
6892914f
MC		 13402
13403 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13404 pci_cmd &= ~PCI_COMMAND_MEMORY;
13405 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13406 }
b5d3772c
MC		 13407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13408 tp->read32_mbox = tg3_read32_mbox_5906;
13409 tp->write32_mbox = tg3_write32_mbox_5906;
13410 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13411 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13412 }
6892914f 13413
bbadf503
MC		 13414 if (tp->write32 == tg3_write_indirect_reg32 ||
13415 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13416 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13417 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13418 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13419
7d0c41ef 13420 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13421 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13422 * determined before calling tg3_set_power_state() so that
13423 * we know whether or not to switch out of Vaux power.
13424 * When the flag is set, it means that GPIO1 is used for eeprom
13425 * write protect and also implies that it is a LOM where GPIOs
13426 * are not used to switch power.
6aa20a22 13427 */
7d0c41ef
MC		 13428 tg3_get_eeprom_hw_cfg(tp);
13429
0d3031d9
MC		 13430 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13431 /* Allow reads and writes to the
13432 * APE register and memory space.
13433 */
13434 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13435 PCISTATE_ALLOW_APE_SHMEM_WR;
13436 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13437 pci_state_reg);
13438 }
13439
9936bcf6 13440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13443 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13445 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13446 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13447
314fba34
MC		 13448 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13449 * GPIO1 driven high will bring 5700's external PHY out of reset.
13450 * It is also used as eeprom write protect on LOMs.
13451 */
13452 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13454 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13455 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13456 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13457 /* Unused GPIO3 must be driven as output on 5752 because there
13458 * are no pull-up resistors on unused GPIO pins.
13459 */
13460 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13461 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13462
321d32a0 13463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13466 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13467
8d519ab2
MC		 13468 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13469 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13470 /* Turn off the debug UART. */
13471 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13472 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13473 /* Keep VMain power. */
13474 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13475 GRC_LCLCTRL_GPIO_OUTPUT0;
13476 }
13477
1da177e4 13478 /* Force the chip into D0. */
bc1c7567 13479 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13480 if (err) {
13481 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13482 pci_name(tp->pdev));
13483 return err;
13484 }
13485
1da177e4
LT		 13486 /* Derive initial jumbo mode from MTU assigned in
13487 * ether_setup() via the alloc_etherdev() call
13488 */
0f893dc6 13489 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13490 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13491 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13492
13493 /* Determine WakeOnLan speed to use. */
13494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13495 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13496 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13497 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13498 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13499 } else {
13500 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13501 }
13502
7f97a4bd
MC		 13503 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13504 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13505
1da177e4
LT		 13506 /* A few boards don't want Ethernet@WireSpeed phy feature */
13507 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13508 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13509 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13510 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13511 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13512 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13513 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13514
13515 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13516 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13517 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13518 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13519 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13520
321d32a0 13521 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13522 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13523 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13524 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13525 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13526 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13529 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13531 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13532 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13533 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13534 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13535 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13536 } else
c424cb24
MC		 13537 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13538 }
1da177e4 13539
b2a5c19c
MC		 13540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13541 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13542 tp->phy_otp = tg3_read_otp_phycfg(tp);
13543 if (tp->phy_otp == 0)
13544 tp->phy_otp = TG3_OTP_DEFAULT;
13545 }
13546
f51f3562 13547 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13548 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13549 else
13550 tp->mi_mode = MAC_MI_MODE_BASE;
13551
1da177e4 13552 tp->coalesce_mode = 0;
1da177e4
LT		 13553 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13554 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13555 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13556
321d32a0
MC		 13557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13559 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13560
158d7abd
MC		 13561 err = tg3_mdio_init(tp);
13562 if (err)
13563 return err;
1da177e4 13564
55dffe79
MC		 13565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13566 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13567 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13568 return -ENOTSUPP;
13569
1da177e4
LT		 13570 /* Initialize data/descriptor byte/word swapping. */
13571 val = tr32(GRC_MODE);
13572 val &= GRC_MODE_HOST_STACKUP;
13573 tw32(GRC_MODE, val | tp->grc_mode);
13574
13575 tg3_switch_clocks(tp);
13576
13577 /* Clear this out for sanity. */
13578 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13579
13580 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13581 &pci_state_reg);
13582 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13583 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13584 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13585
13586 if (chiprevid == CHIPREV_ID_5701_A0 ||
13587 chiprevid == CHIPREV_ID_5701_B0 ||
13588 chiprevid == CHIPREV_ID_5701_B2 ||
13589 chiprevid == CHIPREV_ID_5701_B5) {
13590 void __iomem *sram_base;
13591
13592 /* Write some dummy words into the SRAM status block
13593 * area, see if it reads back correctly. If the return
13594 * value is bad, force enable the PCIX workaround.
13595 */
13596 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13597
13598 writel(0x00000000, sram_base);
13599 writel(0x00000000, sram_base + 4);
13600 writel(0xffffffff, sram_base + 4);
13601 if (readl(sram_base) != 0x00000000)
13602 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13603 }
13604 }
13605
13606 udelay(50);
13607 tg3_nvram_init(tp);
13608
13609 grc_misc_cfg = tr32(GRC_MISC_CFG);
13610 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13611
1da177e4
LT		 13612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13613 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13614 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13615 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13616
fac9b83e
DM		 13617 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13618 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13619 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13620 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13621 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13622 HOSTCC_MODE_CLRTICK_TXBD);
13623
13624 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13625 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13626 tp->misc_host_ctrl);
13627 }
13628
3bda1258
MC		 13629 /* Preserve the APE MAC_MODE bits */
13630 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13631 tp->mac_mode = tr32(MAC_MODE) |
13632 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13633 else
13634 tp->mac_mode = TG3_DEF_MAC_MODE;
13635
1da177e4
LT		 13636 /* these are limited to 10/100 only */
13637 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13638 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13639 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13640 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13641 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13642 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13643 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13644 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13645 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13646 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13647 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
d1101142
MC		 13649 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
7f97a4bd 13651 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13652 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13653
13654 err = tg3_phy_probe(tp);
13655 if (err) {
13656 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13657 pci_name(tp->pdev), err);
13658 /* ... but do not return immediately ... */
b02fd9e3 13659 tg3_mdio_fini(tp);
1da177e4
LT		 13660 }
13661
13662 tg3_read_partno(tp);
c4e6575c 13663 tg3_read_fw_ver(tp);
1da177e4
LT		 13664
13665 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13666 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13667 } else {
13668 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13669 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13670 else
13671 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13672 }
13673
13674 /* 5700 {AX,BX} chips have a broken status block link
13675 * change bit implementation, so we must use the
13676 * status register in those cases.
13677 */
13678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13679 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13680 else
13681 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13682
13683 /* The led_ctrl is set during tg3_phy_probe, here we might
13684 * have to force the link status polling mechanism based
13685 * upon subsystem IDs.
13686 */
13687 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13689 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13690 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13691 TG3_FLAG_USE_LINKCHG_REG);
13692 }
13693
13694 /* For all SERDES we poll the MAC status register. */
13695 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13696 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13697 else
13698 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13699
ad829268 13700 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13702 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13703 tp->rx_offset = 0;
13704
f92905de
MC		 13705 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13706
13707 /* Increment the rx prod index on the rx std ring by at most
13708 * 8 for these chips to workaround hw errata.
13709 */
13710 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13711 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13712 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13713 tp->rx_std_max_post = 8;
13714
8ed5d97e
MC		 13715 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13716 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13717 PCIE_PWR_MGMT_L1_THRESH_MSK;
13718
1da177e4
LT		 13719 return err;
13720}
13721
49b6e95f 13722#ifdef CONFIG_SPARC
1da177e4
LT		 13723static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13724{
13725 struct net_device *dev = tp->dev;
13726 struct pci_dev *pdev = tp->pdev;
49b6e95f 13727 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13728 const unsigned char *addr;
49b6e95f
DM		 13729 int len;
13730
13731 addr = of_get_property(dp, "local-mac-address", &len);
13732 if (addr && len == 6) {
13733 memcpy(dev->dev_addr, addr, 6);
13734 memcpy(dev->perm_addr, dev->dev_addr, 6);
13735 return 0;
1da177e4
LT		 13736 }
13737 return -ENODEV;
13738}
13739
13740static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13741{
13742 struct net_device *dev = tp->dev;
13743
13744 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13745 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13746 return 0;
13747}
13748#endif
13749
13750static int __devinit tg3_get_device_address(struct tg3 *tp)
13751{
13752 struct net_device *dev = tp->dev;
13753 u32 hi, lo, mac_offset;
008652b3 13754 int addr_ok = 0;
1da177e4 13755
49b6e95f 13756#ifdef CONFIG_SPARC
1da177e4
LT		 13757 if (!tg3_get_macaddr_sparc(tp))
13758 return 0;
13759#endif
13760
13761 mac_offset = 0x7c;
f49639e6 13762 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13763 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13764 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13765 mac_offset = 0xcc;
13766 if (tg3_nvram_lock(tp))
13767 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13768 else
13769 tg3_nvram_unlock(tp);
a1b950d5
MC		 13770 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13771 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13772 mac_offset = 0xcc;
13773 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13774 mac_offset = 0x10;
1da177e4
LT		 13775
13776 /* First try to get it from MAC address mailbox. */
13777 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13778 if ((hi >> 16) == 0x484b) {
13779 dev->dev_addr[0] = (hi >> 8) & 0xff;
13780 dev->dev_addr[1] = (hi >> 0) & 0xff;
13781
13782 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13783 dev->dev_addr[2] = (lo >> 24) & 0xff;
13784 dev->dev_addr[3] = (lo >> 16) & 0xff;
13785 dev->dev_addr[4] = (lo >> 8) & 0xff;
13786 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13787
008652b3
MC		 13788 /* Some old bootcode may report a 0 MAC address in SRAM */
13789 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13790 }
13791 if (!addr_ok) {
13792 /* Next, try NVRAM. */
df259d8c
MC		 13793 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13794 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13795 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13796 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13797 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13798 }
13799 /* Finally just fetch it out of the MAC control regs. */
13800 else {
13801 hi = tr32(MAC_ADDR_0_HIGH);
13802 lo = tr32(MAC_ADDR_0_LOW);
13803
13804 dev->dev_addr[5] = lo & 0xff;
13805 dev->dev_addr[4] = (lo >> 8) & 0xff;
13806 dev->dev_addr[3] = (lo >> 16) & 0xff;
13807 dev->dev_addr[2] = (lo >> 24) & 0xff;
13808 dev->dev_addr[1] = hi & 0xff;
13809 dev->dev_addr[0] = (hi >> 8) & 0xff;
13810 }
1da177e4
LT		 13811 }
13812
13813 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13814#ifdef CONFIG_SPARC
1da177e4
LT		 13815 if (!tg3_get_default_macaddr_sparc(tp))
13816 return 0;
13817#endif
13818 return -EINVAL;
13819 }
2ff43697 13820 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13821 return 0;
13822}
13823
59e6b434
DM		 13824#define BOUNDARY_SINGLE_CACHELINE 1
13825#define BOUNDARY_MULTI_CACHELINE 2
13826
13827static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13828{
13829 int cacheline_size;
13830 u8 byte;
13831 int goal;
13832
13833 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13834 if (byte == 0)
13835 cacheline_size = 1024;
13836 else
13837 cacheline_size = (int) byte * 4;
13838
13839 /* On 5703 and later chips, the boundary bits have no
13840 * effect.
13841 */
13842 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13843 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13844 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13845 goto out;
13846
13847#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13848 goal = BOUNDARY_MULTI_CACHELINE;
13849#else
13850#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13851 goal = BOUNDARY_SINGLE_CACHELINE;
13852#else
13853 goal = 0;
13854#endif
13855#endif
13856
b703df6f
MC		 13857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13859 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13860 goto out;
13861 }
13862
59e6b434
DM		 13863 if (!goal)
13864 goto out;
13865
13866 /* PCI controllers on most RISC systems tend to disconnect
13867 * when a device tries to burst across a cache-line boundary.
13868 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13869 *
13870 * Unfortunately, for PCI-E there are only limited
13871 * write-side controls for this, and thus for reads
13872 * we will still get the disconnects. We'll also waste
13873 * these PCI cycles for both read and write for chips
13874 * other than 5700 and 5701 which do not implement the
13875 * boundary bits.
13876 */
13877 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13878 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13879 switch (cacheline_size) {
13880 case 16:
13881 case 32:
13882 case 64:
13883 case 128:
13884 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13885 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13886 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13887 } else {
13888 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13889 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13890 }
13891 break;
13892
13893 case 256:
13894 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13895 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13896 break;
13897
13898 default:
13899 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13900 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13901 break;
855e1111 13902 }
59e6b434
DM		 13903 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13904 switch (cacheline_size) {
13905 case 16:
13906 case 32:
13907 case 64:
13908 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13909 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13910 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13911 break;
13912 }
13913 /* fallthrough */
13914 case 128:
13915 default:
13916 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13917 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13918 break;
855e1111 13919 }
59e6b434
DM		 13920 } else {
13921 switch (cacheline_size) {
13922 case 16:
13923 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13924 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13925 DMA_RWCTRL_WRITE_BNDRY_16);
13926 break;
13927 }
13928 /* fallthrough */
13929 case 32:
13930 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13931 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13932 DMA_RWCTRL_WRITE_BNDRY_32);
13933 break;
13934 }
13935 /* fallthrough */
13936 case 64:
13937 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13938 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13939 DMA_RWCTRL_WRITE_BNDRY_64);
13940 break;
13941 }
13942 /* fallthrough */
13943 case 128:
13944 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13945 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13946 DMA_RWCTRL_WRITE_BNDRY_128);
13947 break;
13948 }
13949 /* fallthrough */
13950 case 256:
13951 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13952 DMA_RWCTRL_WRITE_BNDRY_256);
13953 break;
13954 case 512:
13955 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13956 DMA_RWCTRL_WRITE_BNDRY_512);
13957 break;
13958 case 1024:
13959 default:
13960 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13961 DMA_RWCTRL_WRITE_BNDRY_1024);
13962 break;
855e1111 13963 }
59e6b434
DM		 13964 }
13965
13966out:
13967 return val;
13968}
13969
1da177e4
LT		 13970static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13971{
13972 struct tg3_internal_buffer_desc test_desc;
13973 u32 sram_dma_descs;
13974 int i, ret;
13975
13976 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13977
13978 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13979 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13980 tw32(RDMAC_STATUS, 0);
13981 tw32(WDMAC_STATUS, 0);
13982
13983 tw32(BUFMGR_MODE, 0);
13984 tw32(FTQ_RESET, 0);
13985
13986 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13987 test_desc.addr_lo = buf_dma & 0xffffffff;
13988 test_desc.nic_mbuf = 0x00002100;
13989 test_desc.len = size;
13990
13991 /*
13992 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13993 * the *second* time the tg3 driver was getting loaded after an
13994 * initial scan.
13995 *
13996 * Broadcom tells me:
13997 * ...the DMA engine is connected to the GRC block and a DMA
13998 * reset may affect the GRC block in some unpredictable way...
13999 * The behavior of resets to individual blocks has not been tested.
14000 *
14001 * Broadcom noted the GRC reset will also reset all sub-components.
14002 */
14003 if (to_device) {
14004 test_desc.cqid_sqid = (13 << 8) | 2;
14005
14006 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14007 udelay(40);
14008 } else {
14009 test_desc.cqid_sqid = (16 << 8) | 7;
14010
14011 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14012 udelay(40);
14013 }
14014 test_desc.flags = 0x00000005;
14015
14016 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14017 u32 val;
14018
14019 val = *(((u32 *)&test_desc) + i);
14020 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14021 sram_dma_descs + (i * sizeof(u32)));
14022 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14023 }
14024 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14025
14026 if (to_device) {
14027 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14028 } else {
14029 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14030 }
14031
14032 ret = -ENODEV;
14033 for (i = 0; i < 40; i++) {
14034 u32 val;
14035
14036 if (to_device)
14037 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14038 else
14039 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14040 if ((val & 0xffff) == sram_dma_descs) {
14041 ret = 0;
14042 break;
14043 }
14044
14045 udelay(100);
14046 }
14047
14048 return ret;
14049}
14050
ded7340d 14051#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 14052
14053static int __devinit tg3_test_dma(struct tg3 *tp)
14054{
14055 dma_addr_t buf_dma;
59e6b434 14056 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 14057 int ret = 0;
1da177e4
LT		 14058
14059 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14060 if (!buf) {
14061 ret = -ENOMEM;
14062 goto out_nofree;
14063 }
14064
14065 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14066 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14067
59e6b434 14068 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 14069
b703df6f
MC		 14070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 14072 goto out;
14073
1da177e4
LT		 14074 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14075 /* DMA read watermark not used on PCIE */
14076 tp->dma_rwctrl |= 0x00180000;
14077 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 14078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 14080 tp->dma_rwctrl |= 0x003f0000;
14081 else
14082 tp->dma_rwctrl |= 0x003f000f;
14083 } else {
14084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14086 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 14087 u32 read_water = 0x7;
1da177e4 14088
4a29cc2e
MC		 14089 /* If the 5704 is behind the EPB bridge, we can
14090 * do the less restrictive ONE_DMA workaround for
14091 * better performance.
14092 */
14093 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14094 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14095 tp->dma_rwctrl |= 0x8000;
14096 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 14097 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14098
49afdeb6
MC		 14099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14100 read_water = 4;
59e6b434 14101 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 14102 tp->dma_rwctrl |=
14103 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14104 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14105 (1 << 23);
4cf78e4f
MC		 14106 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14107 /* 5780 always in PCIX mode */
14108 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 14109 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14110 /* 5714 always in PCIX mode */
14111 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 14112 } else {
14113 tp->dma_rwctrl |= 0x001b000f;
14114 }
14115 }
14116
14117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14118 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14119 tp->dma_rwctrl &= 0xfffffff0;
14120
14121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14123 /* Remove this if it causes problems for some boards. */
14124 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14125
14126 /* On 5700/5701 chips, we need to set this bit.
14127 * Otherwise the chip will issue cacheline transactions
14128 * to streamable DMA memory with not all the byte
14129 * enables turned on. This is an error on several
14130 * RISC PCI controllers, in particular sparc64.
14131 *
14132 * On 5703/5704 chips, this bit has been reassigned
14133 * a different meaning. In particular, it is used
14134 * on those chips to enable a PCI-X workaround.
14135 */
14136 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14137 }
14138
14139 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14140
14141#if 0
14142 /* Unneeded, already done by tg3_get_invariants. */
14143 tg3_switch_clocks(tp);
14144#endif
14145
1da177e4
LT		 14146 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14147 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14148 goto out;
14149
59e6b434
DM		 14150 /* It is best to perform DMA test with maximum write burst size
14151 * to expose the 5700/5701 write DMA bug.
14152 */
14153 saved_dma_rwctrl = tp->dma_rwctrl;
14154 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14155 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14156
1da177e4
LT		 14157 while (1) {
14158 u32 *p = buf, i;
14159
14160 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14161 p[i] = i;
14162
14163 /* Send the buffer to the chip. */
14164 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14165 if (ret) {
14166 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14167 break;
14168 }
14169
14170#if 0
14171 /* validate data reached card RAM correctly. */
14172 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14173 u32 val;
14174 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14175 if (le32_to_cpu(val) != p[i]) {
14176 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14177 /* ret = -ENODEV here? */
14178 }
14179 p[i] = 0;
14180 }
14181#endif
14182 /* Now read it back. */
14183 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14184 if (ret) {
14185 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14186
14187 break;
14188 }
14189
14190 /* Verify it. */
14191 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14192 if (p[i] == i)
14193 continue;
14194
59e6b434
DM		 14195 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14196 DMA_RWCTRL_WRITE_BNDRY_16) {
14197 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14198 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14199 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14200 break;
14201 } else {
14202 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14203 ret = -ENODEV;
14204 goto out;
14205 }
14206 }
14207
14208 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14209 /* Success. */
14210 ret = 0;
14211 break;
14212 }
14213 }
59e6b434
DM		 14214 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14215 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14216 static struct pci_device_id dma_wait_state_chipsets[] = {
14217 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14218 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14219 { },
14220 };
14221
59e6b434 14222 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14223 * now look for chipsets that are known to expose the
14224 * DMA bug without failing the test.
59e6b434 14225 */
6d1cfbab
MC		 14226 if (pci_dev_present(dma_wait_state_chipsets)) {
14227 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14228 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14229 }
14230 else
14231 /* Safe to use the calculated DMA boundary. */
14232 tp->dma_rwctrl = saved_dma_rwctrl;
14233
59e6b434
DM		 14234 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14235 }
1da177e4
LT		 14236
14237out:
14238 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14239out_nofree:
14240 return ret;
14241}
14242
14243static void __devinit tg3_init_link_config(struct tg3 *tp)
14244{
14245 tp->link_config.advertising =
14246 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14247 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14248 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14249 ADVERTISED_Autoneg | ADVERTISED_MII);
14250 tp->link_config.speed = SPEED_INVALID;
14251 tp->link_config.duplex = DUPLEX_INVALID;
14252 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14253 tp->link_config.active_speed = SPEED_INVALID;
14254 tp->link_config.active_duplex = DUPLEX_INVALID;
14255 tp->link_config.phy_is_low_power = 0;
14256 tp->link_config.orig_speed = SPEED_INVALID;
14257 tp->link_config.orig_duplex = DUPLEX_INVALID;
14258 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14259}
14260
14261static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14262{
666bc831
MC		 14263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14265 tp->bufmgr_config.mbuf_read_dma_low_water =
14266 DEFAULT_MB_RDMA_LOW_WATER_5705;
14267 tp->bufmgr_config.mbuf_mac_rx_low_water =
14268 DEFAULT_MB_MACRX_LOW_WATER_57765;
14269 tp->bufmgr_config.mbuf_high_water =
14270 DEFAULT_MB_HIGH_WATER_57765;
14271
14272 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14273 DEFAULT_MB_RDMA_LOW_WATER_5705;
14274 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14275 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14276 tp->bufmgr_config.mbuf_high_water_jumbo =
14277 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14278 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14279 tp->bufmgr_config.mbuf_read_dma_low_water =
14280 DEFAULT_MB_RDMA_LOW_WATER_5705;
14281 tp->bufmgr_config.mbuf_mac_rx_low_water =
14282 DEFAULT_MB_MACRX_LOW_WATER_5705;
14283 tp->bufmgr_config.mbuf_high_water =
14284 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14286 tp->bufmgr_config.mbuf_mac_rx_low_water =
14287 DEFAULT_MB_MACRX_LOW_WATER_5906;
14288 tp->bufmgr_config.mbuf_high_water =
14289 DEFAULT_MB_HIGH_WATER_5906;
14290 }
fdfec172
MC		 14291
14292 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14293 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14294 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14295 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14296 tp->bufmgr_config.mbuf_high_water_jumbo =
14297 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14298 } else {
14299 tp->bufmgr_config.mbuf_read_dma_low_water =
14300 DEFAULT_MB_RDMA_LOW_WATER;
14301 tp->bufmgr_config.mbuf_mac_rx_low_water =
14302 DEFAULT_MB_MACRX_LOW_WATER;
14303 tp->bufmgr_config.mbuf_high_water =
14304 DEFAULT_MB_HIGH_WATER;
14305
14306 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14307 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14308 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14309 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14310 tp->bufmgr_config.mbuf_high_water_jumbo =
14311 DEFAULT_MB_HIGH_WATER_JUMBO;
14312 }
1da177e4
LT		 14313
14314 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14315 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14316}
14317
14318static char * __devinit tg3_phy_string(struct tg3 *tp)
14319{
79eb6904
MC		 14320 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14321 case TG3_PHY_ID_BCM5400: return "5400";
14322 case TG3_PHY_ID_BCM5401: return "5401";
14323 case TG3_PHY_ID_BCM5411: return "5411";
14324 case TG3_PHY_ID_BCM5701: return "5701";
14325 case TG3_PHY_ID_BCM5703: return "5703";
14326 case TG3_PHY_ID_BCM5704: return "5704";
14327 case TG3_PHY_ID_BCM5705: return "5705";
14328 case TG3_PHY_ID_BCM5750: return "5750";
14329 case TG3_PHY_ID_BCM5752: return "5752";
14330 case TG3_PHY_ID_BCM5714: return "5714";
14331 case TG3_PHY_ID_BCM5780: return "5780";
14332 case TG3_PHY_ID_BCM5755: return "5755";
14333 case TG3_PHY_ID_BCM5787: return "5787";
14334 case TG3_PHY_ID_BCM5784: return "5784";
14335 case TG3_PHY_ID_BCM5756: return "5722/5756";
14336 case TG3_PHY_ID_BCM5906: return "5906";
14337 case TG3_PHY_ID_BCM5761: return "5761";
14338 case TG3_PHY_ID_BCM5718C: return "5718C";
14339 case TG3_PHY_ID_BCM5718S: return "5718S";
14340 case TG3_PHY_ID_BCM57765: return "57765";
14341 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 14342 case 0: return "serdes";
14343 default: return "unknown";
855e1111 14344 }
1da177e4
LT		 14345}
14346
f9804ddb
MC		 14347static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14348{
14349 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14350 strcpy(str, "PCI Express");
14351 return str;
14352 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14353 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14354
14355 strcpy(str, "PCIX:");
14356
14357 if ((clock_ctrl == 7) ||
14358 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14359 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14360 strcat(str, "133MHz");
14361 else if (clock_ctrl == 0)
14362 strcat(str, "33MHz");
14363 else if (clock_ctrl == 2)
14364 strcat(str, "50MHz");
14365 else if (clock_ctrl == 4)
14366 strcat(str, "66MHz");
14367 else if (clock_ctrl == 6)
14368 strcat(str, "100MHz");
f9804ddb
MC		 14369 } else {
14370 strcpy(str, "PCI:");
14371 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14372 strcat(str, "66MHz");
14373 else
14374 strcat(str, "33MHz");
14375 }
14376 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14377 strcat(str, ":32-bit");
14378 else
14379 strcat(str, ":64-bit");
14380 return str;
14381}
14382
8c2dc7e1 14383static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14384{
14385 struct pci_dev *peer;
14386 unsigned int func, devnr = tp->pdev->devfn & ~7;
14387
14388 for (func = 0; func < 8; func++) {
14389 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14390 if (peer && peer != tp->pdev)
14391 break;
14392 pci_dev_put(peer);
14393 }
16fe9d74
MC		 14394 /* 5704 can be configured in single-port mode, set peer to
14395 * tp->pdev in that case.
14396 */
14397 if (!peer) {
14398 peer = tp->pdev;
14399 return peer;
14400 }
1da177e4
LT		 14401
14402 /*
14403 * We don't need to keep the refcount elevated; there's no way
14404 * to remove one half of this device without removing the other
14405 */
14406 pci_dev_put(peer);
14407
14408 return peer;
14409}
14410
15f9850d
DM		 14411static void __devinit tg3_init_coal(struct tg3 *tp)
14412{
14413 struct ethtool_coalesce *ec = &tp->coal;
14414
14415 memset(ec, 0, sizeof(*ec));
14416 ec->cmd = ETHTOOL_GCOALESCE;
14417 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14418 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14419 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14420 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14421 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14422 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14423 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14424 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14425 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14426
14427 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14428 HOSTCC_MODE_CLRTICK_TXBD)) {
14429 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14430 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14431 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14432 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14433 }
d244c892
MC		 14434
14435 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14436 ec->rx_coalesce_usecs_irq = 0;
14437 ec->tx_coalesce_usecs_irq = 0;
14438 ec->stats_block_coalesce_usecs = 0;
14439 }
15f9850d
DM		 14440}
14441
7c7d64b8
SH		 14442static const struct net_device_ops tg3_netdev_ops = {
14443 .ndo_open = tg3_open,
14444 .ndo_stop = tg3_close,
00829823
SH		 14445 .ndo_start_xmit = tg3_start_xmit,
14446 .ndo_get_stats = tg3_get_stats,
14447 .ndo_validate_addr = eth_validate_addr,
14448 .ndo_set_multicast_list = tg3_set_rx_mode,
14449 .ndo_set_mac_address = tg3_set_mac_addr,
14450 .ndo_do_ioctl = tg3_ioctl,
14451 .ndo_tx_timeout = tg3_tx_timeout,
14452 .ndo_change_mtu = tg3_change_mtu,
14453#if TG3_VLAN_TAG_USED
14454 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14455#endif
14456#ifdef CONFIG_NET_POLL_CONTROLLER
14457 .ndo_poll_controller = tg3_poll_controller,
14458#endif
14459};
14460
14461static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14462 .ndo_open = tg3_open,
14463 .ndo_stop = tg3_close,
14464 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14465 .ndo_get_stats = tg3_get_stats,
14466 .ndo_validate_addr = eth_validate_addr,
14467 .ndo_set_multicast_list = tg3_set_rx_mode,
14468 .ndo_set_mac_address = tg3_set_mac_addr,
14469 .ndo_do_ioctl = tg3_ioctl,
14470 .ndo_tx_timeout = tg3_tx_timeout,
14471 .ndo_change_mtu = tg3_change_mtu,
14472#if TG3_VLAN_TAG_USED
14473 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14474#endif
14475#ifdef CONFIG_NET_POLL_CONTROLLER
14476 .ndo_poll_controller = tg3_poll_controller,
14477#endif
14478};
14479
1da177e4
LT		 14480static int __devinit tg3_init_one(struct pci_dev *pdev,
14481 const struct pci_device_id *ent)
14482{
14483 static int tg3_version_printed = 0;
1da177e4
LT		 14484 struct net_device *dev;
14485 struct tg3 *tp;
646c9edd
MC		 14486 int i, err, pm_cap;
14487 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14488 char str[40];
72f2afb8 14489 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14490
14491 if (tg3_version_printed++ == 0)
14492 printk(KERN_INFO "%s", version);
14493
14494 err = pci_enable_device(pdev);
14495 if (err) {
14496 printk(KERN_ERR PFX "Cannot enable PCI device, "
14497 "aborting.\n");
14498 return err;
14499 }
14500
1da177e4
LT		 14501 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14502 if (err) {
14503 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14504 "aborting.\n");
14505 goto err_out_disable_pdev;
14506 }
14507
14508 pci_set_master(pdev);
14509
14510 /* Find power-management capability. */
14511 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14512 if (pm_cap == 0) {
14513 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14514 "aborting.\n");
14515 err = -EIO;
14516 goto err_out_free_res;
14517 }
14518
fe5f5787 14519 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14520 if (!dev) {
14521 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14522 err = -ENOMEM;
14523 goto err_out_free_res;
14524 }
14525
1da177e4
LT		 14526 SET_NETDEV_DEV(dev, &pdev->dev);
14527
1da177e4
LT		 14528#if TG3_VLAN_TAG_USED
14529 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14530#endif
14531
14532 tp = netdev_priv(dev);
14533 tp->pdev = pdev;
14534 tp->dev = dev;
14535 tp->pm_cap = pm_cap;
1da177e4
LT		 14536 tp->rx_mode = TG3_DEF_RX_MODE;
14537 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14538
1da177e4
LT		 14539 if (tg3_debug > 0)
14540 tp->msg_enable = tg3_debug;
14541 else
14542 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14543
14544 /* The word/byte swap controls here control register access byte
14545 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14546 * setting below.
14547 */
14548 tp->misc_host_ctrl =
14549 MISC_HOST_CTRL_MASK_PCI_INT |
14550 MISC_HOST_CTRL_WORD_SWAP |
14551 MISC_HOST_CTRL_INDIR_ACCESS |
14552 MISC_HOST_CTRL_PCISTATE_RW;
14553
14554 /* The NONFRM (non-frame) byte/word swap controls take effect
14555 * on descriptor entries, anything which isn't packet data.
14556 *
14557 * The StrongARM chips on the board (one for tx, one for rx)
14558 * are running in big-endian mode.
14559 */
14560 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14561 GRC_MODE_WSWAP_NONFRM_DATA);
14562#ifdef __BIG_ENDIAN
14563 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14564#endif
14565 spin_lock_init(&tp->lock);
1da177e4 14566 spin_lock_init(&tp->indirect_lock);
c4028958 14567 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14568
d5fe488a 14569 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14570 if (!tp->regs) {
1da177e4
LT		 14571 printk(KERN_ERR PFX "Cannot map device registers, "
14572 "aborting.\n");
14573 err = -ENOMEM;
14574 goto err_out_free_dev;
14575 }
14576
14577 tg3_init_link_config(tp);
14578
1da177e4
LT		 14579 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14580 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14581
1da177e4 14582 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14583 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14584 dev->irq = pdev->irq;
1da177e4
LT		 14585
14586 err = tg3_get_invariants(tp);
14587 if (err) {
14588 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14589 "aborting.\n");
14590 goto err_out_iounmap;
14591 }
14592
615774fe
MC		 14593 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14594 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14595 dev->netdev_ops = &tg3_netdev_ops;
14596 else
14597 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14598
14599
4a29cc2e
MC		 14600 /* The EPB bridge inside 5714, 5715, and 5780 and any
14601 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14602 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14603 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14604 * do DMA address check in tg3_start_xmit().
14605 */
4a29cc2e 14606 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14607 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14608 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14609 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14610#ifdef CONFIG_HIGHMEM
6a35528a 14611 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14612#endif
4a29cc2e 14613 } else
6a35528a 14614 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14615
14616 /* Configure DMA attributes. */
284901a9 14617 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14618 err = pci_set_dma_mask(pdev, dma_mask);
14619 if (!err) {
14620 dev->features |= NETIF_F_HIGHDMA;
14621 err = pci_set_consistent_dma_mask(pdev,
14622 persist_dma_mask);
14623 if (err < 0) {
14624 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14625 "DMA for consistent allocations\n");
14626 goto err_out_iounmap;
14627 }
14628 }
14629 }
284901a9
YH		 14630 if (err || dma_mask == DMA_BIT_MASK(32)) {
14631 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14632 if (err) {
14633 printk(KERN_ERR PFX "No usable DMA configuration, "
14634 "aborting.\n");
14635 goto err_out_iounmap;
14636 }
14637 }
14638
fdfec172 14639 tg3_init_bufmgr_config(tp);
1da177e4 14640
507399f1
MC		 14641 /* Selectively allow TSO based on operating conditions */
14642 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14643 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14644 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14645 else {
14646 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14647 tp->fw_needed = NULL;
1da177e4 14648 }
507399f1
MC		 14649
14650 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14651 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14652
4e3a7aaa
MC		 14653 /* TSO is on by default on chips that support hardware TSO.
14654 * Firmware TSO on older chips gives lower performance, so it
14655 * is off by default, but can be enabled using ethtool.
14656 */
e849cdc3
MC		 14657 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14658 (dev->features & NETIF_F_IP_CSUM))
14659 dev->features |= NETIF_F_TSO;
14660
14661 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14662 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14663 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14664 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14665 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14666 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14667 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14668 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14670 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14671 dev->features |= NETIF_F_TSO_ECN;
b0026624 14672 }
1da177e4 14673
1da177e4
LT		 14674 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14675 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14676 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14677 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14678 tp->rx_pending = 63;
14679 }
14680
1da177e4
LT		 14681 err = tg3_get_device_address(tp);
14682 if (err) {
14683 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14684 "aborting.\n");
026a6c21 14685 goto err_out_iounmap;
1da177e4
LT		 14686 }
14687
c88864df 14688 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14689 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14690 if (!tp->aperegs) {
c88864df
MC		 14691 printk(KERN_ERR PFX "Cannot map APE registers, "
14692 "aborting.\n");
14693 err = -ENOMEM;
026a6c21 14694 goto err_out_iounmap;
c88864df
MC		 14695 }
14696
14697 tg3_ape_lock_init(tp);
7fd76445
MC		 14698
14699 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14700 tg3_read_dash_ver(tp);
c88864df
MC		 14701 }
14702
1da177e4
LT		 14703 /*
14704 * Reset chip in case UNDI or EFI driver did not shutdown
14705 * DMA self test will enable WDMAC and we'll see (spurious)
14706 * pending DMA on the PCI bus at that point.
14707 */
14708 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14709 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14710 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14711 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14712 }
14713
14714 err = tg3_test_dma(tp);
14715 if (err) {
14716 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14717 goto err_out_apeunmap;
1da177e4
LT		 14718 }
14719
1da177e4
LT		 14720 /* flow control autonegotiation is default behavior */
14721 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14722 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14723
78f90dcf
MC		 14724 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14725 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14726 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14727 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14728 struct tg3_napi *tnapi = &tp->napi[i];
14729
14730 tnapi->tp = tp;
14731 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14732
14733 tnapi->int_mbox = intmbx;
14734 if (i < 4)
14735 intmbx += 0x8;
14736 else
14737 intmbx += 0x4;
14738
14739 tnapi->consmbox = rcvmbx;
14740 tnapi->prodmbox = sndmbx;
14741
14742 if (i) {
14743 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14744 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14745 } else {
14746 tnapi->coal_now = HOSTCC_MODE_NOW;
14747 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14748 }
14749
14750 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14751 break;
14752
14753 /*
14754 * If we support MSIX, we'll be using RSS. If we're using
14755 * RSS, the first vector only handles link interrupts and the
14756 * remaining vectors handle rx and tx interrupts. Reuse the
14757 * mailbox values for the next iteration. The values we setup
14758 * above are still useful for the single vectored mode.
14759 */
14760 if (!i)
14761 continue;
14762
14763 rcvmbx += 0x8;
14764
14765 if (sndmbx & 0x4)
14766 sndmbx -= 0x4;
14767 else
14768 sndmbx += 0xc;
14769 }
14770
15f9850d
DM		 14771 tg3_init_coal(tp);
14772
c49a1561
MC		 14773 pci_set_drvdata(pdev, dev);
14774
1da177e4
LT		 14775 err = register_netdev(dev);
14776 if (err) {
14777 printk(KERN_ERR PFX "Cannot register net device, "
14778 "aborting.\n");
0d3031d9 14779 goto err_out_apeunmap;
1da177e4
LT		 14780 }
14781
df59c940 14782 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14783 dev->name,
14784 tp->board_part_number,
14785 tp->pci_chip_rev_id,
f9804ddb 14786 tg3_bus_string(tp, str),
e174961c 14787 dev->dev_addr);
1da177e4 14788
3f0e3ad7
MC		 14789 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14790 struct phy_device *phydev;
14791 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14792 printk(KERN_INFO
14793 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14794 tp->dev->name, phydev->drv->name,
14795 dev_name(&phydev->dev));
14796 } else
df59c940
MC		 14797 printk(KERN_INFO
14798 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14799 tp->dev->name, tg3_phy_string(tp),
14800 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14801 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14802 "10/100/1000Base-T")),
14803 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14804
14805 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14806 dev->name,
14807 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14808 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14809 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14810 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14811 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14812 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14813 dev->name, tp->dma_rwctrl,
284901a9 14814 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14815 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14816
14817 return 0;
14818
0d3031d9
MC		 14819err_out_apeunmap:
14820 if (tp->aperegs) {
14821 iounmap(tp->aperegs);
14822 tp->aperegs = NULL;
14823 }
14824
1da177e4 14825err_out_iounmap:
6892914f
MC		 14826 if (tp->regs) {
14827 iounmap(tp->regs);
22abe310 14828 tp->regs = NULL;
6892914f 14829 }
1da177e4
LT		 14830
14831err_out_free_dev:
14832 free_netdev(dev);
14833
14834err_out_free_res:
14835 pci_release_regions(pdev);
14836
14837err_out_disable_pdev:
14838 pci_disable_device(pdev);
14839 pci_set_drvdata(pdev, NULL);
14840 return err;
14841}
14842
14843static void __devexit tg3_remove_one(struct pci_dev *pdev)
14844{
14845 struct net_device *dev = pci_get_drvdata(pdev);
14846
14847 if (dev) {
14848 struct tg3 *tp = netdev_priv(dev);
14849
077f849d
JSR		 14850 if (tp->fw)
14851 release_firmware(tp->fw);
14852
7faa006f 14853 flush_scheduled_work();
158d7abd 14854
b02fd9e3
MC		 14855 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14856 tg3_phy_fini(tp);
158d7abd 14857 tg3_mdio_fini(tp);
b02fd9e3 14858 }
158d7abd 14859
1da177e4 14860 unregister_netdev(dev);
0d3031d9
MC		 14861 if (tp->aperegs) {
14862 iounmap(tp->aperegs);
14863 tp->aperegs = NULL;
14864 }
6892914f
MC		 14865 if (tp->regs) {
14866 iounmap(tp->regs);
22abe310 14867 tp->regs = NULL;
6892914f 14868 }
1da177e4
LT		 14869 free_netdev(dev);
14870 pci_release_regions(pdev);
14871 pci_disable_device(pdev);
14872 pci_set_drvdata(pdev, NULL);
14873 }
14874}
14875
14876static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14877{
14878 struct net_device *dev = pci_get_drvdata(pdev);
14879 struct tg3 *tp = netdev_priv(dev);
12dac075 14880 pci_power_t target_state;
1da177e4
LT		 14881 int err;
14882
3e0c95fd
MC		 14883 /* PCI register 4 needs to be saved whether netif_running() or not.
14884 * MSI address and data need to be saved if using MSI and
14885 * netif_running().
14886 */
14887 pci_save_state(pdev);
14888
1da177e4
LT		 14889 if (!netif_running(dev))
14890 return 0;
14891
7faa006f 14892 flush_scheduled_work();
b02fd9e3 14893 tg3_phy_stop(tp);
1da177e4
LT		 14894 tg3_netif_stop(tp);
14895
14896 del_timer_sync(&tp->timer);
14897
f47c11ee 14898 tg3_full_lock(tp, 1);
1da177e4 14899 tg3_disable_ints(tp);
f47c11ee 14900 tg3_full_unlock(tp);
1da177e4
LT		 14901
14902 netif_device_detach(dev);
14903
f47c11ee 14904 tg3_full_lock(tp, 0);
944d980e 14905 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14906 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14907 tg3_full_unlock(tp);
1da177e4 14908
12dac075
RW		 14909 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14910
14911 err = tg3_set_power_state(tp, target_state);
1da177e4 14912 if (err) {
b02fd9e3
MC		 14913 int err2;
14914
f47c11ee 14915 tg3_full_lock(tp, 0);
1da177e4 14916
6a9eba15 14917 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14918 err2 = tg3_restart_hw(tp, 1);
14919 if (err2)
b9ec6c1b 14920 goto out;
1da177e4
LT		 14921
14922 tp->timer.expires = jiffies + tp->timer_offset;
14923 add_timer(&tp->timer);
14924
14925 netif_device_attach(dev);
14926 tg3_netif_start(tp);
14927
b9ec6c1b 14928out:
f47c11ee 14929 tg3_full_unlock(tp);
b02fd9e3
MC		 14930
14931 if (!err2)
14932 tg3_phy_start(tp);
1da177e4
LT		 14933 }
14934
14935 return err;
14936}
14937
14938static int tg3_resume(struct pci_dev *pdev)
14939{
14940 struct net_device *dev = pci_get_drvdata(pdev);
14941 struct tg3 *tp = netdev_priv(dev);
14942 int err;
14943
3e0c95fd
MC		 14944 pci_restore_state(tp->pdev);
14945
1da177e4
LT		 14946 if (!netif_running(dev))
14947 return 0;
14948
bc1c7567 14949 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14950 if (err)
14951 return err;
14952
14953 netif_device_attach(dev);
14954
f47c11ee 14955 tg3_full_lock(tp, 0);
1da177e4 14956
6a9eba15 14957 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14958 err = tg3_restart_hw(tp, 1);
14959 if (err)
14960 goto out;
1da177e4
LT		 14961
14962 tp->timer.expires = jiffies + tp->timer_offset;
14963 add_timer(&tp->timer);
14964
1da177e4
LT		 14965 tg3_netif_start(tp);
14966
b9ec6c1b 14967out:
f47c11ee 14968 tg3_full_unlock(tp);
1da177e4 14969
b02fd9e3
MC		 14970 if (!err)
14971 tg3_phy_start(tp);
14972
b9ec6c1b 14973 return err;
1da177e4
LT		 14974}
14975
14976static struct pci_driver tg3_driver = {
14977 .name = DRV_MODULE_NAME,
14978 .id_table = tg3_pci_tbl,
14979 .probe = tg3_init_one,
14980 .remove = __devexit_p(tg3_remove_one),
14981 .suspend = tg3_suspend,
14982 .resume = tg3_resume
14983};
14984
14985static int __init tg3_init(void)
14986{
29917620 14987 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14988}
14989
14990static void __exit tg3_cleanup(void)
14991{
14992 pci_unregister_driver(&tg3_driver);
14993}
14994
14995module_init(tg3_init);
14996module_exit(tg3_cleanup);
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