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tg3: Optimize rx double copy test
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
ba5b0bfa 7 * Copyright (C) 2005-2010 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
7ae554e5
MC		 70#define DRV_MODULE_VERSION "3.109"
71#define DRV_MODULE_RELDATE "April 2, 2010"
1da177e4
LT		 72
73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0
75#define TG3_DEF_TX_MODE 0
76#define TG3_DEF_MSG_ENABLE \
77 (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86/* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
88 */
89#define TG3_TX_TIMEOUT (5 * HZ)
90
91/* hardware minimum and maximum for a single frame's data payload */
92#define TG3_MIN_MTU 60
93#define TG3_MAX_MTU(tp) \
8f666b07 94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 95
96/* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
99 */
100#define TG3_RX_RING_SIZE 512
101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
c6cdf436 104#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
79ed5ac7
MC		 121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
1da177e4 123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 124 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
1da177e4
LT		 127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
287be12e
MC		 129#define TG3_DMA_BYTE_ENAB 64
130
131#define TG3_RX_STD_DMA_SZ 1536
132#define TG3_RX_JMB_DMA_SZ 9046
133
134#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135
136#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 138
2b2cdb65
MC		 139#define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
141
142#define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144
c6cdf436
MC		 145#define TG3_RSS_MIN_NUM_MSIX_VECS 2
146
d2757fc4
MC		 147/* Due to a hardware bug, the 5701 can only DMA to memory addresses
148 * that are at least dword aligned when used in PCIX mode. The driver
149 * works around this bug by double copying the packet. This workaround
150 * is built into the normal double copy length check for efficiency.
151 *
152 * However, the double copy is only necessary on those architectures
153 * where unaligned memory accesses are inefficient. For those architectures
154 * where unaligned memory accesses incur little penalty, we can reintegrate
155 * the 5701 in the normal rx path. Doing so saves a device structure
156 * dereference by hardcoding the double copy threshold in place.
157 */
158#define TG3_RX_COPY_THRESHOLD 256
159#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
160 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
161#else
162 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
163#endif
164
1da177e4 165/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 166#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 167
ad829268
MC		 168#define TG3_RAW_IP_ALIGN 2
169
1da177e4
LT		 170/* number of ETHTOOL_GSTATS u64's */
171#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
172
4cafd3f5
MC		 173#define TG3_NUM_TEST 6
174
c6cdf436
MC		 175#define TG3_FW_UPDATE_TIMEOUT_SEC 5
176
077f849d
JSR		 177#define FIRMWARE_TG3 "tigon/tg3.bin"
178#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
179#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
180
1da177e4 181static char version[] __devinitdata =
05dbe005 182 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 183
184MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
185MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
186MODULE_LICENSE("GPL");
187MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 188MODULE_FIRMWARE(FIRMWARE_TG3);
189MODULE_FIRMWARE(FIRMWARE_TG3TSO);
190MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
191
1da177e4
LT		 192static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
193module_param(tg3_debug, int, 0);
194MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
195
a3aa1884 196static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
b0f75221
MC		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
13185217
HK		 272 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
273 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
274 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
275 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
276 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
278 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
279 {}
1da177e4
LT		 280};
281
282MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
283
50da859d 284static const struct {
1da177e4
LT		 285 const char string[ETH_GSTRING_LEN];
286} ethtool_stats_keys[TG3_NUM_STATS] = {
287 { "rx_octets" },
288 { "rx_fragments" },
289 { "rx_ucast_packets" },
290 { "rx_mcast_packets" },
291 { "rx_bcast_packets" },
292 { "rx_fcs_errors" },
293 { "rx_align_errors" },
294 { "rx_xon_pause_rcvd" },
295 { "rx_xoff_pause_rcvd" },
296 { "rx_mac_ctrl_rcvd" },
297 { "rx_xoff_entered" },
298 { "rx_frame_too_long_errors" },
299 { "rx_jabbers" },
300 { "rx_undersize_packets" },
301 { "rx_in_length_errors" },
302 { "rx_out_length_errors" },
303 { "rx_64_or_less_octet_packets" },
304 { "rx_65_to_127_octet_packets" },
305 { "rx_128_to_255_octet_packets" },
306 { "rx_256_to_511_octet_packets" },
307 { "rx_512_to_1023_octet_packets" },
308 { "rx_1024_to_1522_octet_packets" },
309 { "rx_1523_to_2047_octet_packets" },
310 { "rx_2048_to_4095_octet_packets" },
311 { "rx_4096_to_8191_octet_packets" },
312 { "rx_8192_to_9022_octet_packets" },
313
314 { "tx_octets" },
315 { "tx_collisions" },
316
317 { "tx_xon_sent" },
318 { "tx_xoff_sent" },
319 { "tx_flow_control" },
320 { "tx_mac_errors" },
321 { "tx_single_collisions" },
322 { "tx_mult_collisions" },
323 { "tx_deferred" },
324 { "tx_excessive_collisions" },
325 { "tx_late_collisions" },
326 { "tx_collide_2times" },
327 { "tx_collide_3times" },
328 { "tx_collide_4times" },
329 { "tx_collide_5times" },
330 { "tx_collide_6times" },
331 { "tx_collide_7times" },
332 { "tx_collide_8times" },
333 { "tx_collide_9times" },
334 { "tx_collide_10times" },
335 { "tx_collide_11times" },
336 { "tx_collide_12times" },
337 { "tx_collide_13times" },
338 { "tx_collide_14times" },
339 { "tx_collide_15times" },
340 { "tx_ucast_packets" },
341 { "tx_mcast_packets" },
342 { "tx_bcast_packets" },
343 { "tx_carrier_sense_errors" },
344 { "tx_discards" },
345 { "tx_errors" },
346
347 { "dma_writeq_full" },
348 { "dma_write_prioq_full" },
349 { "rxbds_empty" },
350 { "rx_discards" },
351 { "rx_errors" },
352 { "rx_threshold_hit" },
353
354 { "dma_readq_full" },
355 { "dma_read_prioq_full" },
356 { "tx_comp_queue_full" },
357
358 { "ring_set_send_prod_index" },
359 { "ring_status_update" },
360 { "nic_irqs" },
361 { "nic_avoided_irqs" },
362 { "nic_tx_threshold_hit" }
363};
364
50da859d 365static const struct {
4cafd3f5
MC		 366 const char string[ETH_GSTRING_LEN];
367} ethtool_test_keys[TG3_NUM_TEST] = {
368 { "nvram test (online) " },
369 { "link test (online) " },
370 { "register test (offline)" },
371 { "memory test (offline)" },
372 { "loopback test (offline)" },
373 { "interrupt test (offline)" },
374};
375
b401e9e2
MC		 376static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
377{
378 writel(val, tp->regs + off);
379}
380
381static u32 tg3_read32(struct tg3 *tp, u32 off)
382{
6aa20a22 383 return (readl(tp->regs + off));
b401e9e2
MC		 384}
385
0d3031d9
MC		 386static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
387{
388 writel(val, tp->aperegs + off);
389}
390
391static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
392{
393 return (readl(tp->aperegs + off));
394}
395
1da177e4
LT		 396static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
397{
6892914f
MC		 398 unsigned long flags;
399
400 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 401 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
402 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 403 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 404}
405
406static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
407{
408 writel(val, tp->regs + off);
409 readl(tp->regs + off);
1da177e4
LT		 410}
411
6892914f 412static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 413{
6892914f
MC		 414 unsigned long flags;
415 u32 val;
416
417 spin_lock_irqsave(&tp->indirect_lock, flags);
418 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
419 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
420 spin_unlock_irqrestore(&tp->indirect_lock, flags);
421 return val;
422}
423
424static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
425{
426 unsigned long flags;
427
428 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
429 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
430 TG3_64BIT_REG_LOW, val);
431 return;
432 }
66711e66 433 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 434 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
435 TG3_64BIT_REG_LOW, val);
436 return;
1da177e4 437 }
6892914f
MC		 438
439 spin_lock_irqsave(&tp->indirect_lock, flags);
440 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
442 spin_unlock_irqrestore(&tp->indirect_lock, flags);
443
444 /* In indirect mode when disabling interrupts, we also need
445 * to clear the interrupt bit in the GRC local ctrl register.
446 */
447 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
448 (val == 0x1)) {
449 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
450 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
451 }
452}
453
454static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
455{
456 unsigned long flags;
457 u32 val;
458
459 spin_lock_irqsave(&tp->indirect_lock, flags);
460 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
461 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
462 spin_unlock_irqrestore(&tp->indirect_lock, flags);
463 return val;
464}
465
b401e9e2
MC		 466/* usec_wait specifies the wait time in usec when writing to certain registers
467 * where it is unsafe to read back the register without some delay.
468 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
469 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
470 */
471static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 472{
b401e9e2
MC		 473 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
474 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
475 /* Non-posted methods */
476 tp->write32(tp, off, val);
477 else {
478 /* Posted method */
479 tg3_write32(tp, off, val);
480 if (usec_wait)
481 udelay(usec_wait);
482 tp->read32(tp, off);
483 }
484 /* Wait again after the read for the posted method to guarantee that
485 * the wait time is met.
486 */
487 if (usec_wait)
488 udelay(usec_wait);
1da177e4
LT		 489}
490
09ee929c
MC		 491static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
492{
493 tp->write32_mbox(tp, off, val);
6892914f
MC		 494 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
495 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
496 tp->read32_mbox(tp, off);
09ee929c
MC		 497}
498
20094930 499static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 500{
501 void __iomem *mbox = tp->regs + off;
502 writel(val, mbox);
503 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
504 writel(val, mbox);
505 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
506 readl(mbox);
507}
508
b5d3772c
MC		 509static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
510{
511 return (readl(tp->regs + off + GRCMBOX_BASE));
512}
513
514static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
515{
516 writel(val, tp->regs + off + GRCMBOX_BASE);
517}
518
c6cdf436 519#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 520#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 521#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
522#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
523#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 524
c6cdf436
MC		 525#define tw32(reg, val) tp->write32(tp, reg, val)
526#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
527#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
528#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 529
530static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
536 return;
537
6892914f 538 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 539 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
540 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
541 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 542
bbadf503
MC		 543 /* Always leave this as zero. */
544 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
545 } else {
546 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
547 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 548
bbadf503
MC		 549 /* Always leave this as zero. */
550 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
551 }
552 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 553}
554
1da177e4
LT		 555static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
556{
6892914f
MC		 557 unsigned long flags;
558
b5d3772c
MC		 559 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
560 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
561 *val = 0;
562 return;
563 }
564
6892914f 565 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 566 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
567 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
568 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 569
bbadf503
MC		 570 /* Always leave this as zero. */
571 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
572 } else {
573 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
574 *val = tr32(TG3PCI_MEM_WIN_DATA);
575
576 /* Always leave this as zero. */
577 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
578 }
6892914f 579 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 580}
581
0d3031d9
MC		 582static void tg3_ape_lock_init(struct tg3 *tp)
583{
584 int i;
585
586 /* Make sure the driver hasn't any stale locks. */
587 for (i = 0; i < 8; i++)
588 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
589 APE_LOCK_GRANT_DRIVER);
590}
591
592static int tg3_ape_lock(struct tg3 *tp, int locknum)
593{
594 int i, off;
595 int ret = 0;
596 u32 status;
597
598 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
599 return 0;
600
601 switch (locknum) {
33f401ae
MC		 602 case TG3_APE_LOCK_GRC:
603 case TG3_APE_LOCK_MEM:
604 break;
605 default:
606 return -EINVAL;
0d3031d9
MC		 607 }
608
609 off = 4 * locknum;
610
611 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
612
613 /* Wait for up to 1 millisecond to acquire lock. */
614 for (i = 0; i < 100; i++) {
615 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
616 if (status == APE_LOCK_GRANT_DRIVER)
617 break;
618 udelay(10);
619 }
620
621 if (status != APE_LOCK_GRANT_DRIVER) {
622 /* Revoke the lock request. */
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
624 APE_LOCK_GRANT_DRIVER);
625
626 ret = -EBUSY;
627 }
628
629 return ret;
630}
631
632static void tg3_ape_unlock(struct tg3 *tp, int locknum)
633{
634 int off;
635
636 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
637 return;
638
639 switch (locknum) {
33f401ae
MC		 640 case TG3_APE_LOCK_GRC:
641 case TG3_APE_LOCK_MEM:
642 break;
643 default:
644 return;
0d3031d9
MC		 645 }
646
647 off = 4 * locknum;
648 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
649}
650
1da177e4
LT		 651static void tg3_disable_ints(struct tg3 *tp)
652{
89aeb3bc
MC		 653 int i;
654
1da177e4
LT		 655 tw32(TG3PCI_MISC_HOST_CTRL,
656 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 657 for (i = 0; i < tp->irq_max; i++)
658 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 659}
660
1da177e4
LT		 661static void tg3_enable_ints(struct tg3 *tp)
662{
89aeb3bc 663 int i;
89aeb3bc 664
bbe832c0
MC		 665 tp->irq_sync = 0;
666 wmb();
667
1da177e4
LT		 668 tw32(TG3PCI_MISC_HOST_CTRL,
669 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 670
f89f38b8 671 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 672 for (i = 0; i < tp->irq_cnt; i++) {
673 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 674
898a56f8 675 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 676 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
677 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 678
f89f38b8 679 tp->coal_now |= tnapi->coal_now;
89aeb3bc 680 }
f19af9c2
MC		 681
682 /* Force an initial interrupt */
683 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
684 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
685 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
686 else
f89f38b8
MC		 687 tw32(HOSTCC_MODE, tp->coal_now);
688
689 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 690}
691
17375d25 692static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 693{
17375d25 694 struct tg3 *tp = tnapi->tp;
898a56f8 695 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 696 unsigned int work_exists = 0;
697
698 /* check for phy events */
699 if (!(tp->tg3_flags &
700 (TG3_FLAG_USE_LINKCHG_REG |
701 TG3_FLAG_POLL_SERDES))) {
702 if (sblk->status & SD_STATUS_LINK_CHG)
703 work_exists = 1;
704 }
705 /* check for RX/TX work to do */
f3f3f27e 706 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 707 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 708 work_exists = 1;
709
710 return work_exists;
711}
712
17375d25 713/* tg3_int_reenable
04237ddd
MC		 714 * similar to tg3_enable_ints, but it accurately determines whether there
715 * is new work pending and can return without flushing the PIO write
6aa20a22 716 * which reenables interrupts
1da177e4 717 */
17375d25 718static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 719{
17375d25
MC		 720 struct tg3 *tp = tnapi->tp;
721
898a56f8 722 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 723 mmiowb();
724
fac9b83e
DM		 725 /* When doing tagged status, this work check is unnecessary.
726 * The last_tag we write above tells the chip which piece of
727 * work we've completed.
728 */
729 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 730 tg3_has_work(tnapi))
04237ddd 731 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 732 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 733}
734
fed97810
MC		 735static void tg3_napi_disable(struct tg3 *tp)
736{
737 int i;
738
739 for (i = tp->irq_cnt - 1; i >= 0; i--)
740 napi_disable(&tp->napi[i].napi);
741}
742
743static void tg3_napi_enable(struct tg3 *tp)
744{
745 int i;
746
747 for (i = 0; i < tp->irq_cnt; i++)
748 napi_enable(&tp->napi[i].napi);
749}
750
1da177e4
LT		 751static inline void tg3_netif_stop(struct tg3 *tp)
752{
bbe832c0 753 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 754 tg3_napi_disable(tp);
1da177e4
LT		 755 netif_tx_disable(tp->dev);
756}
757
758static inline void tg3_netif_start(struct tg3 *tp)
759{
fe5f5787
MC		 760 /* NOTE: unconditional netif_tx_wake_all_queues is only
761 * appropriate so long as all callers are assured to
762 * have free tx slots (such as after tg3_init_hw)
1da177e4 763 */
fe5f5787
MC		 764 netif_tx_wake_all_queues(tp->dev);
765
fed97810
MC		 766 tg3_napi_enable(tp);
767 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 768 tg3_enable_ints(tp);
1da177e4
LT		 769}
770
771static void tg3_switch_clocks(struct tg3 *tp)
772{
f6eb9b1f 773 u32 clock_ctrl;
1da177e4
LT		 774 u32 orig_clock_ctrl;
775
795d01c5
MC		 776 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
777 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 778 return;
779
f6eb9b1f
MC		 780 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
781
1da177e4
LT		 782 orig_clock_ctrl = clock_ctrl;
783 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
784 CLOCK_CTRL_CLKRUN_OENABLE |
785 0x1f);
786 tp->pci_clock_ctrl = clock_ctrl;
787
788 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
789 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 790 tw32_wait_f(TG3PCI_CLOCK_CTRL,
791 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 792 }
793 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 794 tw32_wait_f(TG3PCI_CLOCK_CTRL,
795 clock_ctrl |
796 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
797 40);
798 tw32_wait_f(TG3PCI_CLOCK_CTRL,
799 clock_ctrl | (CLOCK_CTRL_ALTCLK),
800 40);
1da177e4 801 }
b401e9e2 802 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 803}
804
805#define PHY_BUSY_LOOPS 5000
806
807static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
808{
809 u32 frame_val;
810 unsigned int loops;
811 int ret;
812
813 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
814 tw32_f(MAC_MI_MODE,
815 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
816 udelay(80);
817 }
818
819 *val = 0x0;
820
882e9793 821 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 822 MI_COM_PHY_ADDR_MASK);
823 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
824 MI_COM_REG_ADDR_MASK);
825 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 826
1da177e4
LT		 827 tw32_f(MAC_MI_COM, frame_val);
828
829 loops = PHY_BUSY_LOOPS;
830 while (loops != 0) {
831 udelay(10);
832 frame_val = tr32(MAC_MI_COM);
833
834 if ((frame_val & MI_COM_BUSY) == 0) {
835 udelay(5);
836 frame_val = tr32(MAC_MI_COM);
837 break;
838 }
839 loops -= 1;
840 }
841
842 ret = -EBUSY;
843 if (loops != 0) {
844 *val = frame_val & MI_COM_DATA_MASK;
845 ret = 0;
846 }
847
848 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
849 tw32_f(MAC_MI_MODE, tp->mi_mode);
850 udelay(80);
851 }
852
853 return ret;
854}
855
856static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
857{
858 u32 frame_val;
859 unsigned int loops;
860 int ret;
861
7f97a4bd 862 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 863 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
864 return 0;
865
1da177e4
LT		 866 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
867 tw32_f(MAC_MI_MODE,
868 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
869 udelay(80);
870 }
871
882e9793 872 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 873 MI_COM_PHY_ADDR_MASK);
874 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
875 MI_COM_REG_ADDR_MASK);
876 frame_val |= (val & MI_COM_DATA_MASK);
877 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 878
1da177e4
LT		 879 tw32_f(MAC_MI_COM, frame_val);
880
881 loops = PHY_BUSY_LOOPS;
882 while (loops != 0) {
883 udelay(10);
884 frame_val = tr32(MAC_MI_COM);
885 if ((frame_val & MI_COM_BUSY) == 0) {
886 udelay(5);
887 frame_val = tr32(MAC_MI_COM);
888 break;
889 }
890 loops -= 1;
891 }
892
893 ret = -EBUSY;
894 if (loops != 0)
895 ret = 0;
896
897 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
898 tw32_f(MAC_MI_MODE, tp->mi_mode);
899 udelay(80);
900 }
901
902 return ret;
903}
904
95e2869a
MC		 905static int tg3_bmcr_reset(struct tg3 *tp)
906{
907 u32 phy_control;
908 int limit, err;
909
910 /* OK, reset it, and poll the BMCR_RESET bit until it
911 * clears or we time out.
912 */
913 phy_control = BMCR_RESET;
914 err = tg3_writephy(tp, MII_BMCR, phy_control);
915 if (err != 0)
916 return -EBUSY;
917
918 limit = 5000;
919 while (limit--) {
920 err = tg3_readphy(tp, MII_BMCR, &phy_control);
921 if (err != 0)
922 return -EBUSY;
923
924 if ((phy_control & BMCR_RESET) == 0) {
925 udelay(40);
926 break;
927 }
928 udelay(10);
929 }
d4675b52 930 if (limit < 0)
95e2869a
MC		 931 return -EBUSY;
932
933 return 0;
934}
935
158d7abd
MC		 936static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
937{
3d16543d 938 struct tg3 *tp = bp->priv;
158d7abd
MC		 939 u32 val;
940
24bb4fb6 941 spin_lock_bh(&tp->lock);
158d7abd
MC		 942
943 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 944 val = -EIO;
945
946 spin_unlock_bh(&tp->lock);
158d7abd
MC		 947
948 return val;
949}
950
951static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
952{
3d16543d 953 struct tg3 *tp = bp->priv;
24bb4fb6 954 u32 ret = 0;
158d7abd 955
24bb4fb6 956 spin_lock_bh(&tp->lock);
158d7abd
MC		 957
958 if (tg3_writephy(tp, reg, val))
24bb4fb6 959 ret = -EIO;
158d7abd 960
24bb4fb6
MC		 961 spin_unlock_bh(&tp->lock);
962
963 return ret;
158d7abd
MC		 964}
965
966static int tg3_mdio_reset(struct mii_bus *bp)
967{
968 return 0;
969}
970
9c61d6bc 971static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 972{
973 u32 val;
fcb389df 974 struct phy_device *phydev;
a9daf367 975
3f0e3ad7 976 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 977 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 978 case PHY_ID_BCM50610:
979 case PHY_ID_BCM50610M:
fcb389df
MC		 980 val = MAC_PHYCFG2_50610_LED_MODES;
981 break;
6a443a0f 982 case PHY_ID_BCMAC131:
fcb389df
MC		 983 val = MAC_PHYCFG2_AC131_LED_MODES;
984 break;
6a443a0f 985 case PHY_ID_RTL8211C:
fcb389df
MC		 986 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
987 break;
6a443a0f 988 case PHY_ID_RTL8201E:
fcb389df
MC		 989 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
990 break;
991 default:
a9daf367 992 return;
fcb389df
MC		 993 }
994
995 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
996 tw32(MAC_PHYCFG2, val);
997
998 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 999 val &= ~(MAC_PHYCFG1_RGMII_INT |
1000 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1001 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1002 tw32(MAC_PHYCFG1, val);
1003
1004 return;
1005 }
1006
14417063 1007 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
fcb389df
MC		 1008 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1009 MAC_PHYCFG2_FMODE_MASK_MASK |
1010 MAC_PHYCFG2_GMODE_MASK_MASK |
1011 MAC_PHYCFG2_ACT_MASK_MASK |
1012 MAC_PHYCFG2_QUAL_MASK_MASK |
1013 MAC_PHYCFG2_INBAND_ENABLE;
1014
1015 tw32(MAC_PHYCFG2, val);
a9daf367 1016
bb85fbb6
MC		 1017 val = tr32(MAC_PHYCFG1);
1018 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1019 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
14417063 1020 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1021 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1022 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1023 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1025 }
bb85fbb6
MC		 1026 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1027 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1028 tw32(MAC_PHYCFG1, val);
a9daf367 1029
a9daf367
MC		 1030 val = tr32(MAC_EXT_RGMII_MODE);
1031 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1032 MAC_RGMII_MODE_RX_QUALITY |
1033 MAC_RGMII_MODE_RX_ACTIVITY |
1034 MAC_RGMII_MODE_RX_ENG_DET |
1035 MAC_RGMII_MODE_TX_ENABLE |
1036 MAC_RGMII_MODE_TX_LOWPWR |
1037 MAC_RGMII_MODE_TX_RESET);
14417063 1038 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1039 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1040 val |= MAC_RGMII_MODE_RX_INT_B |
1041 MAC_RGMII_MODE_RX_QUALITY |
1042 MAC_RGMII_MODE_RX_ACTIVITY |
1043 MAC_RGMII_MODE_RX_ENG_DET;
1044 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1045 val |= MAC_RGMII_MODE_TX_ENABLE |
1046 MAC_RGMII_MODE_TX_LOWPWR |
1047 MAC_RGMII_MODE_TX_RESET;
1048 }
1049 tw32(MAC_EXT_RGMII_MODE, val);
1050}
1051
158d7abd
MC		 1052static void tg3_mdio_start(struct tg3 *tp)
1053{
158d7abd
MC		 1054 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1055 tw32_f(MAC_MI_MODE, tp->mi_mode);
1056 udelay(80);
a9daf367 1057
9ea4818d
MC		 1058 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1060 tg3_mdio_config_5785(tp);
1061}
1062
1063static int tg3_mdio_init(struct tg3 *tp)
1064{
1065 int i;
1066 u32 reg;
1067 struct phy_device *phydev;
1068
882e9793
MC		 1069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1070 u32 funcnum, is_serdes;
1071
1072 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1073 if (funcnum)
1074 tp->phy_addr = 2;
1075 else
1076 tp->phy_addr = 1;
1077
d1ec96af
MC		 1078 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1079 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1080 else
1081 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1082 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1083 if (is_serdes)
1084 tp->phy_addr += 7;
1085 } else
3f0e3ad7 1086 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1087
158d7abd
MC		 1088 tg3_mdio_start(tp);
1089
1090 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1091 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1092 return 0;
1093
298cf9be
LB		 1094 tp->mdio_bus = mdiobus_alloc();
1095 if (tp->mdio_bus == NULL)
1096 return -ENOMEM;
158d7abd 1097
298cf9be
LB		 1098 tp->mdio_bus->name = "tg3 mdio bus";
1099 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1100 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1101 tp->mdio_bus->priv = tp;
1102 tp->mdio_bus->parent = &tp->pdev->dev;
1103 tp->mdio_bus->read = &tg3_mdio_read;
1104 tp->mdio_bus->write = &tg3_mdio_write;
1105 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1106 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1107 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1108
1109 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1110 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1111
1112 /* The bus registration will look for all the PHYs on the mdio bus.
1113 * Unfortunately, it does not ensure the PHY is powered up before
1114 * accessing the PHY ID registers. A chip reset is the
1115 * quickest way to bring the device back to an operational state..
1116 */
1117 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1118 tg3_bmcr_reset(tp);
1119
298cf9be 1120 i = mdiobus_register(tp->mdio_bus);
a9daf367 1121 if (i) {
ab96b241 1122 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1123 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1124 return i;
1125 }
158d7abd 1126
3f0e3ad7 1127 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1128
9c61d6bc 1129 if (!phydev || !phydev->drv) {
ab96b241 1130 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1131 mdiobus_unregister(tp->mdio_bus);
1132 mdiobus_free(tp->mdio_bus);
1133 return -ENODEV;
1134 }
1135
1136 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1137 case PHY_ID_BCM57780:
321d32a0 1138 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1139 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1140 break;
6a443a0f
MC		 1141 case PHY_ID_BCM50610:
1142 case PHY_ID_BCM50610M:
32e5a8d6 1143 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1144 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1145 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1146 PHY_BRCM_AUTO_PWRDWN_ENABLE;
14417063 1147 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
a9daf367
MC		 1148 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1149 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1150 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1151 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1152 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1153 /* fallthru */
6a443a0f 1154 case PHY_ID_RTL8211C:
fcb389df 1155 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1156 break;
6a443a0f
MC		 1157 case PHY_ID_RTL8201E:
1158 case PHY_ID_BCMAC131:
a9daf367 1159 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1160 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1161 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1162 break;
1163 }
1164
9c61d6bc
MC		 1165 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1166
1167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1168 tg3_mdio_config_5785(tp);
a9daf367
MC		 1169
1170 return 0;
158d7abd
MC		 1171}
1172
1173static void tg3_mdio_fini(struct tg3 *tp)
1174{
1175 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1176 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1177 mdiobus_unregister(tp->mdio_bus);
1178 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1179 }
1180}
1181
4ba526ce
MC		 1182/* tp->lock is held. */
1183static inline void tg3_generate_fw_event(struct tg3 *tp)
1184{
1185 u32 val;
1186
1187 val = tr32(GRC_RX_CPU_EVENT);
1188 val |= GRC_RX_CPU_DRIVER_EVENT;
1189 tw32_f(GRC_RX_CPU_EVENT, val);
1190
1191 tp->last_event_jiffies = jiffies;
1192}
1193
1194#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1195
95e2869a
MC		 1196/* tp->lock is held. */
1197static void tg3_wait_for_event_ack(struct tg3 *tp)
1198{
1199 int i;
4ba526ce
MC		 1200 unsigned int delay_cnt;
1201 long time_remain;
1202
1203 /* If enough time has passed, no wait is necessary. */
1204 time_remain = (long)(tp->last_event_jiffies + 1 +
1205 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1206 (long)jiffies;
1207 if (time_remain < 0)
1208 return;
1209
1210 /* Check if we can shorten the wait time. */
1211 delay_cnt = jiffies_to_usecs(time_remain);
1212 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1213 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1214 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1215
4ba526ce 1216 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1217 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1218 break;
4ba526ce 1219 udelay(8);
95e2869a
MC		 1220 }
1221}
1222
1223/* tp->lock is held. */
1224static void tg3_ump_link_report(struct tg3 *tp)
1225{
1226 u32 reg;
1227 u32 val;
1228
1229 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1230 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1231 return;
1232
1233 tg3_wait_for_event_ack(tp);
1234
1235 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1236
1237 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1238
1239 val = 0;
1240 if (!tg3_readphy(tp, MII_BMCR, &reg))
1241 val = reg << 16;
1242 if (!tg3_readphy(tp, MII_BMSR, &reg))
1243 val |= (reg & 0xffff);
1244 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1245
1246 val = 0;
1247 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1248 val = reg << 16;
1249 if (!tg3_readphy(tp, MII_LPA, &reg))
1250 val |= (reg & 0xffff);
1251 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1252
1253 val = 0;
1254 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1255 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1256 val = reg << 16;
1257 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1258 val |= (reg & 0xffff);
1259 }
1260 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1261
1262 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1263 val = reg << 16;
1264 else
1265 val = 0;
1266 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1267
4ba526ce 1268 tg3_generate_fw_event(tp);
95e2869a
MC		 1269}
1270
1271static void tg3_link_report(struct tg3 *tp)
1272{
1273 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1274 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1275 tg3_ump_link_report(tp);
1276 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1277 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1278 (tp->link_config.active_speed == SPEED_1000 ?
1279 1000 :
1280 (tp->link_config.active_speed == SPEED_100 ?
1281 100 : 10)),
1282 (tp->link_config.active_duplex == DUPLEX_FULL ?
1283 "full" : "half"));
1284
1285 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1286 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1287 "on" : "off",
1288 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1289 "on" : "off");
95e2869a
MC		 1290 tg3_ump_link_report(tp);
1291 }
1292}
1293
1294static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1295{
1296 u16 miireg;
1297
e18ce346 1298 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1299 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1300 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1301 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1302 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1303 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1304 else
1305 miireg = 0;
1306
1307 return miireg;
1308}
1309
1310static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1311{
1312 u16 miireg;
1313
e18ce346 1314 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1315 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1316 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1317 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1318 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1319 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1320 else
1321 miireg = 0;
1322
1323 return miireg;
1324}
1325
95e2869a
MC		 1326static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1327{
1328 u8 cap = 0;
1329
1330 if (lcladv & ADVERTISE_1000XPAUSE) {
1331 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1332 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1333 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1334 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1335 cap = FLOW_CTRL_RX;
95e2869a
MC		 1336 } else {
1337 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1338 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1339 }
1340 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1341 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1342 cap = FLOW_CTRL_TX;
95e2869a
MC		 1343 }
1344
1345 return cap;
1346}
1347
f51f3562 1348static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1349{
b02fd9e3 1350 u8 autoneg;
f51f3562 1351 u8 flowctrl = 0;
95e2869a
MC		 1352 u32 old_rx_mode = tp->rx_mode;
1353 u32 old_tx_mode = tp->tx_mode;
1354
b02fd9e3 1355 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1356 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1357 else
1358 autoneg = tp->link_config.autoneg;
1359
1360 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1361 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1362 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1363 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1364 else
bc02ff95 1365 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1366 } else
1367 flowctrl = tp->link_config.flowctrl;
95e2869a 1368
f51f3562 1369 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1370
e18ce346 1371 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1372 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1373 else
1374 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1375
f51f3562 1376 if (old_rx_mode != tp->rx_mode)
95e2869a 1377 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1378
e18ce346 1379 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1380 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1381 else
1382 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1383
f51f3562 1384 if (old_tx_mode != tp->tx_mode)
95e2869a 1385 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1386}
1387
b02fd9e3
MC		 1388static void tg3_adjust_link(struct net_device *dev)
1389{
1390 u8 oldflowctrl, linkmesg = 0;
1391 u32 mac_mode, lcl_adv, rmt_adv;
1392 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1393 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1394
24bb4fb6 1395 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1396
1397 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1398 MAC_MODE_HALF_DUPLEX);
1399
1400 oldflowctrl = tp->link_config.active_flowctrl;
1401
1402 if (phydev->link) {
1403 lcl_adv = 0;
1404 rmt_adv = 0;
1405
1406 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1407 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1408 else if (phydev->speed == SPEED_1000 ||
1409 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1410 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1411 else
1412 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1413
1414 if (phydev->duplex == DUPLEX_HALF)
1415 mac_mode |= MAC_MODE_HALF_DUPLEX;
1416 else {
1417 lcl_adv = tg3_advert_flowctrl_1000T(
1418 tp->link_config.flowctrl);
1419
1420 if (phydev->pause)
1421 rmt_adv = LPA_PAUSE_CAP;
1422 if (phydev->asym_pause)
1423 rmt_adv |= LPA_PAUSE_ASYM;
1424 }
1425
1426 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1427 } else
1428 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1429
1430 if (mac_mode != tp->mac_mode) {
1431 tp->mac_mode = mac_mode;
1432 tw32_f(MAC_MODE, tp->mac_mode);
1433 udelay(40);
1434 }
1435
fcb389df
MC		 1436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1437 if (phydev->speed == SPEED_10)
1438 tw32(MAC_MI_STAT,
1439 MAC_MI_STAT_10MBPS_MODE |
1440 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1441 else
1442 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1443 }
1444
b02fd9e3
MC		 1445 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1446 tw32(MAC_TX_LENGTHS,
1447 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1448 (6 << TX_LENGTHS_IPG_SHIFT) |
1449 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1450 else
1451 tw32(MAC_TX_LENGTHS,
1452 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1453 (6 << TX_LENGTHS_IPG_SHIFT) |
1454 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1455
1456 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1457 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1458 phydev->speed != tp->link_config.active_speed ||
1459 phydev->duplex != tp->link_config.active_duplex ||
1460 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 1461 linkmesg = 1;
b02fd9e3
MC		 1462
1463 tp->link_config.active_speed = phydev->speed;
1464 tp->link_config.active_duplex = phydev->duplex;
1465
24bb4fb6 1466 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1467
1468 if (linkmesg)
1469 tg3_link_report(tp);
1470}
1471
1472static int tg3_phy_init(struct tg3 *tp)
1473{
1474 struct phy_device *phydev;
1475
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1477 return 0;
1478
1479 /* Bring the PHY back to a known state. */
1480 tg3_bmcr_reset(tp);
1481
3f0e3ad7 1482 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1483
1484 /* Attach the MAC to the PHY. */
fb28ad35 1485 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1486 phydev->dev_flags, phydev->interface);
b02fd9e3 1487 if (IS_ERR(phydev)) {
ab96b241 1488 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 1489 return PTR_ERR(phydev);
1490 }
1491
b02fd9e3 1492 /* Mask with MAC supported features. */
9c61d6bc
MC		 1493 switch (phydev->interface) {
1494 case PHY_INTERFACE_MODE_GMII:
1495 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1496 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1497 phydev->supported &= (PHY_GBIT_FEATURES |
1498 SUPPORTED_Pause |
1499 SUPPORTED_Asym_Pause);
1500 break;
1501 }
1502 /* fallthru */
9c61d6bc
MC		 1503 case PHY_INTERFACE_MODE_MII:
1504 phydev->supported &= (PHY_BASIC_FEATURES |
1505 SUPPORTED_Pause |
1506 SUPPORTED_Asym_Pause);
1507 break;
1508 default:
3f0e3ad7 1509 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1510 return -EINVAL;
1511 }
1512
1513 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1514
1515 phydev->advertising = phydev->supported;
1516
b02fd9e3
MC		 1517 return 0;
1518}
1519
1520static void tg3_phy_start(struct tg3 *tp)
1521{
1522 struct phy_device *phydev;
1523
1524 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1525 return;
1526
3f0e3ad7 1527 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1528
1529 if (tp->link_config.phy_is_low_power) {
1530 tp->link_config.phy_is_low_power = 0;
1531 phydev->speed = tp->link_config.orig_speed;
1532 phydev->duplex = tp->link_config.orig_duplex;
1533 phydev->autoneg = tp->link_config.orig_autoneg;
1534 phydev->advertising = tp->link_config.orig_advertising;
1535 }
1536
1537 phy_start(phydev);
1538
1539 phy_start_aneg(phydev);
1540}
1541
1542static void tg3_phy_stop(struct tg3 *tp)
1543{
1544 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1545 return;
1546
3f0e3ad7 1547 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1548}
1549
1550static void tg3_phy_fini(struct tg3 *tp)
1551{
1552 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1553 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1554 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1555 }
1556}
1557
b2a5c19c
MC		 1558static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1559{
1560 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1561 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1562}
1563
7f97a4bd
MC		 1564static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1565{
1566 u32 phytest;
1567
1568 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1569 u32 phy;
1570
1571 tg3_writephy(tp, MII_TG3_FET_TEST,
1572 phytest | MII_TG3_FET_SHADOW_EN);
1573 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1574 if (enable)
1575 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1576 else
1577 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1578 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1579 }
1580 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1581 }
1582}
1583
6833c043
MC		 1584static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1585{
1586 u32 reg;
1587
ecf1410b
MC		 1588 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1590 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1591 return;
1592
7f97a4bd
MC		 1593 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1594 tg3_phy_fet_toggle_apd(tp, enable);
1595 return;
1596 }
1597
6833c043
MC		 1598 reg = MII_TG3_MISC_SHDW_WREN |
1599 MII_TG3_MISC_SHDW_SCR5_SEL |
1600 MII_TG3_MISC_SHDW_SCR5_LPED |
1601 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1602 MII_TG3_MISC_SHDW_SCR5_SDTL |
1603 MII_TG3_MISC_SHDW_SCR5_C125OE;
1604 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1605 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1606
1607 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1608
1609
1610 reg = MII_TG3_MISC_SHDW_WREN |
1611 MII_TG3_MISC_SHDW_APD_SEL |
1612 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1613 if (enable)
1614 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1615
1616 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1617}
1618
9ef8ca99
MC		 1619static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1620{
1621 u32 phy;
1622
1623 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1624 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1625 return;
1626
7f97a4bd 1627 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1628 u32 ephy;
1629
535ef6e1
MC		 1630 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1631 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1632
1633 tg3_writephy(tp, MII_TG3_FET_TEST,
1634 ephy | MII_TG3_FET_SHADOW_EN);
1635 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1636 if (enable)
535ef6e1 1637 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1638 else
535ef6e1
MC		 1639 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1640 tg3_writephy(tp, reg, phy);
9ef8ca99 1641 }
535ef6e1 1642 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1643 }
1644 } else {
1645 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1646 MII_TG3_AUXCTL_SHDWSEL_MISC;
1647 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1648 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1649 if (enable)
1650 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1651 else
1652 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1653 phy |= MII_TG3_AUXCTL_MISC_WREN;
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1655 }
1656 }
1657}
1658
1da177e4
LT		 1659static void tg3_phy_set_wirespeed(struct tg3 *tp)
1660{
1661 u32 val;
1662
1663 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1664 return;
1665
1666 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1667 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1668 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1669 (val | (1 << 15) | (1 << 4)));
1670}
1671
b2a5c19c
MC		 1672static void tg3_phy_apply_otp(struct tg3 *tp)
1673{
1674 u32 otp, phy;
1675
1676 if (!tp->phy_otp)
1677 return;
1678
1679 otp = tp->phy_otp;
1680
1681 /* Enable SM_DSP clock and tx 6dB coding. */
1682 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1683 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686
1687 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1688 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1689 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1690
1691 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1692 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1694
1695 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1696 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1697 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1698
1699 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1700 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1701
1702 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1703 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1704
1705 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1706 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1707 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1708
1709 /* Turn off SM_DSP clock. */
1710 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1711 MII_TG3_AUXCTL_ACTL_TX_6DB;
1712 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1713}
1714
1da177e4
LT		 1715static int tg3_wait_macro_done(struct tg3 *tp)
1716{
1717 int limit = 100;
1718
1719 while (limit--) {
1720 u32 tmp32;
1721
1722 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1723 if ((tmp32 & 0x1000) == 0)
1724 break;
1725 }
1726 }
d4675b52 1727 if (limit < 0)
1da177e4
LT		 1728 return -EBUSY;
1729
1730 return 0;
1731}
1732
1733static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1734{
1735 static const u32 test_pat[4][6] = {
1736 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1737 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1738 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1739 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1740 };
1741 int chan;
1742
1743 for (chan = 0; chan < 4; chan++) {
1744 int i;
1745
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, 0x16, 0x0002);
1749
1750 for (i = 0; i < 6; i++)
1751 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1752 test_pat[chan][i]);
1753
1754 tg3_writephy(tp, 0x16, 0x0202);
1755 if (tg3_wait_macro_done(tp)) {
1756 *resetp = 1;
1757 return -EBUSY;
1758 }
1759
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1761 (chan * 0x2000) | 0x0200);
1762 tg3_writephy(tp, 0x16, 0x0082);
1763 if (tg3_wait_macro_done(tp)) {
1764 *resetp = 1;
1765 return -EBUSY;
1766 }
1767
1768 tg3_writephy(tp, 0x16, 0x0802);
1769 if (tg3_wait_macro_done(tp)) {
1770 *resetp = 1;
1771 return -EBUSY;
1772 }
1773
1774 for (i = 0; i < 6; i += 2) {
1775 u32 low, high;
1776
1777 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1778 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1779 tg3_wait_macro_done(tp)) {
1780 *resetp = 1;
1781 return -EBUSY;
1782 }
1783 low &= 0x7fff;
1784 high &= 0x000f;
1785 if (low != test_pat[chan][i] ||
1786 high != test_pat[chan][i+1]) {
1787 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1788 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1789 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1790
1791 return -EBUSY;
1792 }
1793 }
1794 }
1795
1796 return 0;
1797}
1798
1799static int tg3_phy_reset_chanpat(struct tg3 *tp)
1800{
1801 int chan;
1802
1803 for (chan = 0; chan < 4; chan++) {
1804 int i;
1805
1806 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1807 (chan * 0x2000) | 0x0200);
1808 tg3_writephy(tp, 0x16, 0x0002);
1809 for (i = 0; i < 6; i++)
1810 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1811 tg3_writephy(tp, 0x16, 0x0202);
1812 if (tg3_wait_macro_done(tp))
1813 return -EBUSY;
1814 }
1815
1816 return 0;
1817}
1818
1819static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1820{
1821 u32 reg32, phy9_orig;
1822 int retries, do_phy_reset, err;
1823
1824 retries = 10;
1825 do_phy_reset = 1;
1826 do {
1827 if (do_phy_reset) {
1828 err = tg3_bmcr_reset(tp);
1829 if (err)
1830 return err;
1831 do_phy_reset = 0;
1832 }
1833
1834 /* Disable transmitter and interrupt. */
1835 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1836 continue;
1837
1838 reg32 |= 0x3000;
1839 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1840
1841 /* Set full-duplex, 1000 mbps. */
1842 tg3_writephy(tp, MII_BMCR,
1843 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1844
1845 /* Set to master mode. */
1846 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1847 continue;
1848
1849 tg3_writephy(tp, MII_TG3_CTRL,
1850 (MII_TG3_CTRL_AS_MASTER |
1851 MII_TG3_CTRL_ENABLE_AS_MASTER));
1852
1853 /* Enable SM_DSP_CLOCK and 6dB. */
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855
1856 /* Block the PHY control access. */
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1859
1860 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1861 if (!err)
1862 break;
1863 } while (--retries);
1864
1865 err = tg3_phy_reset_chanpat(tp);
1866 if (err)
1867 return err;
1868
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1871
1872 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1873 tg3_writephy(tp, 0x16, 0x0000);
1874
1875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1877 /* Set Extended packet length bit for jumbo frames */
1878 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
859a5887 1879 } else {
1da177e4
LT		 1880 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1881 }
1882
1883 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1884
1885 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1886 reg32 &= ~0x3000;
1887 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1888 } else if (!err)
1889 err = -EBUSY;
1890
1891 return err;
1892}
1893
1894/* This will reset the tigon3 PHY if there is no valid
1895 * link unless the FORCE argument is non-zero.
1896 */
1897static int tg3_phy_reset(struct tg3 *tp)
1898{
b2a5c19c 1899 u32 cpmuctrl;
1da177e4
LT		 1900 u32 phy_status;
1901 int err;
1902
60189ddf
MC		 1903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1904 u32 val;
1905
1906 val = tr32(GRC_MISC_CFG);
1907 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1908 udelay(40);
1909 }
1da177e4
LT		 1910 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1911 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1912 if (err != 0)
1913 return -EBUSY;
1914
c8e1e82b
MC		 1915 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1916 netif_carrier_off(tp->dev);
1917 tg3_link_report(tp);
1918 }
1919
1da177e4
LT		 1920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1923 err = tg3_phy_reset_5703_4_5(tp);
1924 if (err)
1925 return err;
1926 goto out;
1927 }
1928
b2a5c19c
MC		 1929 cpmuctrl = 0;
1930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1931 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1932 cpmuctrl = tr32(TG3_CPMU_CTRL);
1933 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1934 tw32(TG3_CPMU_CTRL,
1935 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1936 }
1937
1da177e4
LT		 1938 err = tg3_bmcr_reset(tp);
1939 if (err)
1940 return err;
1941
b2a5c19c
MC		 1942 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1943 u32 phy;
1944
1945 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1946 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1947
1948 tw32(TG3_CPMU_CTRL, cpmuctrl);
1949 }
1950
bcb37f6c
MC		 1951 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1952 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1953 u32 val;
1954
1955 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1956 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1957 CPMU_LSPD_1000MB_MACCLK_12_5) {
1958 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1959 udelay(40);
1960 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1961 }
1962 }
1963
ecf1410b
MC		 1964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1965 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1966 return 0;
1967
b2a5c19c
MC		 1968 tg3_phy_apply_otp(tp);
1969
6833c043
MC		 1970 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1971 tg3_phy_toggle_apd(tp, true);
1972 else
1973 tg3_phy_toggle_apd(tp, false);
1974
1da177e4
LT		 1975out:
1976 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1978 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1979 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1981 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1982 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1983 }
1984 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1985 tg3_writephy(tp, 0x1c, 0x8d68);
1986 tg3_writephy(tp, 0x1c, 0x8d68);
1987 }
1988 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1989 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1990 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1991 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1992 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1994 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1995 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1996 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
859a5887 1997 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
c424cb24
MC		 1998 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1999 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 2000 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2001 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2002 tg3_writephy(tp, MII_TG3_TEST1,
2003 MII_TG3_TEST1_TRIM_EN | 0x4);
2004 } else
2005 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 2006 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2007 }
1da177e4
LT		 2008 /* Set Extended packet length bit (bit 14) on all chips that */
2009 /* support jumbo frames */
79eb6904 2010 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 2011 /* Cannot do read-modify-write on 5401 */
2012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 2013 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2014 u32 phy_reg;
2015
2016 /* Set bit 14 with read-modify-write to preserve other bits */
2017 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2018 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2019 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2020 }
2021
2022 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2023 * jumbo frames transmission.
2024 */
8f666b07 2025 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2026 u32 phy_reg;
2027
2028 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
c6cdf436
MC		 2029 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2030 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2031 }
2032
715116a1 2033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2034 /* adjust output voltage */
535ef6e1 2035 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2036 }
2037
9ef8ca99 2038 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2039 tg3_phy_set_wirespeed(tp);
2040 return 0;
2041}
2042
2043static void tg3_frob_aux_power(struct tg3 *tp)
2044{
2045 struct tg3 *tp_peer = tp;
2046
334355aa
MC		 2047 /* The GPIOs do something completely different on 57765. */
2048 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2050 return;
2051
f6eb9b1f
MC		 2052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2055 struct net_device *dev_peer;
2056
2057 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2058 /* remove_one() may have been run on the peer. */
8c2dc7e1 2059 if (!dev_peer)
bc1c7567
MC		 2060 tp_peer = tp;
2061 else
2062 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2063 }
2064
1da177e4 2065 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2066 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2067 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2068 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2071 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2072 (GRC_LCLCTRL_GPIO_OE0 |
2073 GRC_LCLCTRL_GPIO_OE1 |
2074 GRC_LCLCTRL_GPIO_OE2 |
2075 GRC_LCLCTRL_GPIO_OUTPUT0 |
2076 GRC_LCLCTRL_GPIO_OUTPUT1),
2077 100);
8d519ab2
MC		 2078 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2079 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2080 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2081 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2082 GRC_LCLCTRL_GPIO_OE1 |
2083 GRC_LCLCTRL_GPIO_OE2 |
2084 GRC_LCLCTRL_GPIO_OUTPUT0 |
2085 GRC_LCLCTRL_GPIO_OUTPUT1 |
2086 tp->grc_local_ctrl;
2087 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2088
2089 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2090 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2091
2092 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2093 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2094 } else {
2095 u32 no_gpio2;
dc56b7d4 2096 u32 grc_local_ctrl = 0;
1da177e4
LT		 2097
2098 if (tp_peer != tp &&
2099 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2100 return;
2101
dc56b7d4
MC		 2102 /* Workaround to prevent overdrawing Amps. */
2103 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2104 ASIC_REV_5714) {
2105 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2106 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107 grc_local_ctrl, 100);
dc56b7d4
MC		 2108 }
2109
1da177e4
LT		 2110 /* On 5753 and variants, GPIO2 cannot be used. */
2111 no_gpio2 = tp->nic_sram_data_cfg &
2112 NIC_SRAM_DATA_CFG_NO_GPIO2;
2113
dc56b7d4 2114 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2115 GRC_LCLCTRL_GPIO_OE1 |
2116 GRC_LCLCTRL_GPIO_OE2 |
2117 GRC_LCLCTRL_GPIO_OUTPUT1 |
2118 GRC_LCLCTRL_GPIO_OUTPUT2;
2119 if (no_gpio2) {
2120 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2121 GRC_LCLCTRL_GPIO_OUTPUT2);
2122 }
b401e9e2
MC		 2123 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2124 grc_local_ctrl, 100);
1da177e4
LT		 2125
2126 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2127
b401e9e2
MC		 2128 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2129 grc_local_ctrl, 100);
1da177e4
LT		 2130
2131 if (!no_gpio2) {
2132 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2133 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2134 grc_local_ctrl, 100);
1da177e4
LT		 2135 }
2136 }
2137 } else {
2138 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2139 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2140 if (tp_peer != tp &&
2141 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2142 return;
2143
b401e9e2
MC		 2144 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2145 (GRC_LCLCTRL_GPIO_OE1 |
2146 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2147
b401e9e2
MC		 2148 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2149 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2150
b401e9e2
MC		 2151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152 (GRC_LCLCTRL_GPIO_OE1 |
2153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2154 }
2155 }
2156}
2157
e8f3f6ca
MC		 2158static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2159{
2160 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2161 return 1;
79eb6904 2162 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 2163 if (speed != SPEED_10)
2164 return 1;
2165 } else if (speed == SPEED_10)
2166 return 1;
2167
2168 return 0;
2169}
2170
1da177e4
LT		 2171static int tg3_setup_phy(struct tg3 *, int);
2172
2173#define RESET_KIND_SHUTDOWN 0
2174#define RESET_KIND_INIT 1
2175#define RESET_KIND_SUSPEND 2
2176
2177static void tg3_write_sig_post_reset(struct tg3 *, int);
2178static int tg3_halt_cpu(struct tg3 *, u32);
2179
0a459aac 2180static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2181{
ce057f01
MC		 2182 u32 val;
2183
5129724a
MC		 2184 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2186 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2187 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2188
2189 sg_dig_ctrl |=
2190 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2191 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2192 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2193 }
3f7045c1 2194 return;
5129724a 2195 }
3f7045c1 2196
60189ddf 2197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2198 tg3_bmcr_reset(tp);
2199 val = tr32(GRC_MISC_CFG);
2200 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2201 udelay(40);
2202 return;
0e5f784c
MC		 2203 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2204 u32 phytest;
2205 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2206 u32 phy;
2207
2208 tg3_writephy(tp, MII_ADVERTISE, 0);
2209 tg3_writephy(tp, MII_BMCR,
2210 BMCR_ANENABLE | BMCR_ANRESTART);
2211
2212 tg3_writephy(tp, MII_TG3_FET_TEST,
2213 phytest | MII_TG3_FET_SHADOW_EN);
2214 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2215 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2216 tg3_writephy(tp,
2217 MII_TG3_FET_SHDW_AUXMODE4,
2218 phy);
2219 }
2220 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2221 }
2222 return;
0a459aac 2223 } else if (do_low_power) {
715116a1
MC		 2224 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2225 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2226
2227 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2228 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2229 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2230 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2231 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2232 }
3f7045c1 2233
15c3b696
MC		 2234 /* The PHY should not be powered down on some chips because
2235 * of bugs.
2236 */
2237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2239 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2240 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2241 return;
ce057f01 2242
bcb37f6c
MC		 2243 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2244 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2245 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2246 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2247 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2248 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2249 }
2250
15c3b696
MC		 2251 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2252}
2253
ffbcfed4
MC		 2254/* tp->lock is held. */
2255static int tg3_nvram_lock(struct tg3 *tp)
2256{
2257 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2258 int i;
2259
2260 if (tp->nvram_lock_cnt == 0) {
2261 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2262 for (i = 0; i < 8000; i++) {
2263 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2264 break;
2265 udelay(20);
2266 }
2267 if (i == 8000) {
2268 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2269 return -ENODEV;
2270 }
2271 }
2272 tp->nvram_lock_cnt++;
2273 }
2274 return 0;
2275}
2276
2277/* tp->lock is held. */
2278static void tg3_nvram_unlock(struct tg3 *tp)
2279{
2280 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2281 if (tp->nvram_lock_cnt > 0)
2282 tp->nvram_lock_cnt--;
2283 if (tp->nvram_lock_cnt == 0)
2284 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2285 }
2286}
2287
2288/* tp->lock is held. */
2289static void tg3_enable_nvram_access(struct tg3 *tp)
2290{
2291 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2292 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2293 u32 nvaccess = tr32(NVRAM_ACCESS);
2294
2295 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2296 }
2297}
2298
2299/* tp->lock is held. */
2300static void tg3_disable_nvram_access(struct tg3 *tp)
2301{
2302 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2303 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2304 u32 nvaccess = tr32(NVRAM_ACCESS);
2305
2306 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2307 }
2308}
2309
2310static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2311 u32 offset, u32 *val)
2312{
2313 u32 tmp;
2314 int i;
2315
2316 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2317 return -EINVAL;
2318
2319 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2320 EEPROM_ADDR_DEVID_MASK |
2321 EEPROM_ADDR_READ);
2322 tw32(GRC_EEPROM_ADDR,
2323 tmp |
2324 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2325 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2326 EEPROM_ADDR_ADDR_MASK) |
2327 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2328
2329 for (i = 0; i < 1000; i++) {
2330 tmp = tr32(GRC_EEPROM_ADDR);
2331
2332 if (tmp & EEPROM_ADDR_COMPLETE)
2333 break;
2334 msleep(1);
2335 }
2336 if (!(tmp & EEPROM_ADDR_COMPLETE))
2337 return -EBUSY;
2338
62cedd11
MC		 2339 tmp = tr32(GRC_EEPROM_DATA);
2340
2341 /*
2342 * The data will always be opposite the native endian
2343 * format. Perform a blind byteswap to compensate.
2344 */
2345 *val = swab32(tmp);
2346
ffbcfed4
MC		 2347 return 0;
2348}
2349
2350#define NVRAM_CMD_TIMEOUT 10000
2351
2352static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2353{
2354 int i;
2355
2356 tw32(NVRAM_CMD, nvram_cmd);
2357 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2358 udelay(10);
2359 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2360 udelay(10);
2361 break;
2362 }
2363 }
2364
2365 if (i == NVRAM_CMD_TIMEOUT)
2366 return -EBUSY;
2367
2368 return 0;
2369}
2370
2371static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2372{
2373 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2374 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2375 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2376 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2377 (tp->nvram_jedecnum == JEDEC_ATMEL))
2378
2379 addr = ((addr / tp->nvram_pagesize) <<
2380 ATMEL_AT45DB0X1B_PAGE_POS) +
2381 (addr % tp->nvram_pagesize);
2382
2383 return addr;
2384}
2385
2386static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2387{
2388 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2389 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2390 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2391 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2392 (tp->nvram_jedecnum == JEDEC_ATMEL))
2393
2394 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2395 tp->nvram_pagesize) +
2396 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2397
2398 return addr;
2399}
2400
e4f34110
MC		 2401/* NOTE: Data read in from NVRAM is byteswapped according to
2402 * the byteswapping settings for all other register accesses.
2403 * tg3 devices are BE devices, so on a BE machine, the data
2404 * returned will be exactly as it is seen in NVRAM. On a LE
2405 * machine, the 32-bit value will be byteswapped.
2406 */
ffbcfed4
MC		 2407static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2408{
2409 int ret;
2410
2411 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2412 return tg3_nvram_read_using_eeprom(tp, offset, val);
2413
2414 offset = tg3_nvram_phys_addr(tp, offset);
2415
2416 if (offset > NVRAM_ADDR_MSK)
2417 return -EINVAL;
2418
2419 ret = tg3_nvram_lock(tp);
2420 if (ret)
2421 return ret;
2422
2423 tg3_enable_nvram_access(tp);
2424
2425 tw32(NVRAM_ADDR, offset);
2426 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2427 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2428
2429 if (ret == 0)
e4f34110 2430 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2431
2432 tg3_disable_nvram_access(tp);
2433
2434 tg3_nvram_unlock(tp);
2435
2436 return ret;
2437}
2438
a9dc529d
MC		 2439/* Ensures NVRAM data is in bytestream format. */
2440static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2441{
2442 u32 v;
a9dc529d 2443 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2444 if (!res)
a9dc529d 2445 *val = cpu_to_be32(v);
ffbcfed4
MC		 2446 return res;
2447}
2448
3f007891
MC		 2449/* tp->lock is held. */
2450static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2451{
2452 u32 addr_high, addr_low;
2453 int i;
2454
2455 addr_high = ((tp->dev->dev_addr[0] << 8) |
2456 tp->dev->dev_addr[1]);
2457 addr_low = ((tp->dev->dev_addr[2] << 24) |
2458 (tp->dev->dev_addr[3] << 16) |
2459 (tp->dev->dev_addr[4] << 8) |
2460 (tp->dev->dev_addr[5] << 0));
2461 for (i = 0; i < 4; i++) {
2462 if (i == 1 && skip_mac_1)
2463 continue;
2464 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2465 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2466 }
2467
2468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2469 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2470 for (i = 0; i < 12; i++) {
2471 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2472 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2473 }
2474 }
2475
2476 addr_high = (tp->dev->dev_addr[0] +
2477 tp->dev->dev_addr[1] +
2478 tp->dev->dev_addr[2] +
2479 tp->dev->dev_addr[3] +
2480 tp->dev->dev_addr[4] +
2481 tp->dev->dev_addr[5]) &
2482 TX_BACKOFF_SEED_MASK;
2483 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2484}
2485
bc1c7567 2486static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2487{
2488 u32 misc_host_ctrl;
0a459aac 2489 bool device_should_wake, do_low_power;
1da177e4
LT		 2490
2491 /* Make sure register accesses (indirect or otherwise)
2492 * will function correctly.
2493 */
2494 pci_write_config_dword(tp->pdev,
2495 TG3PCI_MISC_HOST_CTRL,
2496 tp->misc_host_ctrl);
2497
1da177e4 2498 switch (state) {
bc1c7567 2499 case PCI_D0:
12dac075
RW		 2500 pci_enable_wake(tp->pdev, state, false);
2501 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2502
9d26e213
MC		 2503 /* Switch out of Vaux if it is a NIC */
2504 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2505 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2506
2507 return 0;
2508
bc1c7567 2509 case PCI_D1:
bc1c7567 2510 case PCI_D2:
bc1c7567 2511 case PCI_D3hot:
1da177e4
LT		 2512 break;
2513
2514 default:
05dbe005
JP		 2515 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2516 state);
1da177e4 2517 return -EINVAL;
855e1111 2518 }
5e7dfd0f
MC		 2519
2520 /* Restore the CLKREQ setting. */
2521 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2522 u16 lnkctl;
2523
2524 pci_read_config_word(tp->pdev,
2525 tp->pcie_cap + PCI_EXP_LNKCTL,
2526 &lnkctl);
2527 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2528 pci_write_config_word(tp->pdev,
2529 tp->pcie_cap + PCI_EXP_LNKCTL,
2530 lnkctl);
2531 }
2532
1da177e4
LT		 2533 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2534 tw32(TG3PCI_MISC_HOST_CTRL,
2535 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2536
05ac4cb7
MC		 2537 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2538 device_may_wakeup(&tp->pdev->dev) &&
2539 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2540
dd477003 2541 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2542 do_low_power = false;
b02fd9e3
MC		 2543 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2544 !tp->link_config.phy_is_low_power) {
2545 struct phy_device *phydev;
0a459aac 2546 u32 phyid, advertising;
b02fd9e3 2547
3f0e3ad7 2548 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2549
2550 tp->link_config.phy_is_low_power = 1;
2551
2552 tp->link_config.orig_speed = phydev->speed;
2553 tp->link_config.orig_duplex = phydev->duplex;
2554 tp->link_config.orig_autoneg = phydev->autoneg;
2555 tp->link_config.orig_advertising = phydev->advertising;
2556
2557 advertising = ADVERTISED_TP |
2558 ADVERTISED_Pause |
2559 ADVERTISED_Autoneg |
2560 ADVERTISED_10baseT_Half;
2561
2562 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2563 device_should_wake) {
b02fd9e3
MC		 2564 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2565 advertising |=
2566 ADVERTISED_100baseT_Half |
2567 ADVERTISED_100baseT_Full |
2568 ADVERTISED_10baseT_Full;
2569 else
2570 advertising |= ADVERTISED_10baseT_Full;
2571 }
2572
2573 phydev->advertising = advertising;
2574
2575 phy_start_aneg(phydev);
0a459aac
MC		 2576
2577 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 2578 if (phyid != PHY_ID_BCMAC131) {
2579 phyid &= PHY_BCM_OUI_MASK;
2580 if (phyid == PHY_BCM_OUI_1 ||
2581 phyid == PHY_BCM_OUI_2 ||
2582 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 2583 do_low_power = true;
2584 }
b02fd9e3 2585 }
dd477003 2586 } else {
2023276e 2587 do_low_power = true;
0a459aac 2588
dd477003
MC		 2589 if (tp->link_config.phy_is_low_power == 0) {
2590 tp->link_config.phy_is_low_power = 1;
2591 tp->link_config.orig_speed = tp->link_config.speed;
2592 tp->link_config.orig_duplex = tp->link_config.duplex;
2593 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2594 }
1da177e4 2595
dd477003
MC		 2596 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2597 tp->link_config.speed = SPEED_10;
2598 tp->link_config.duplex = DUPLEX_HALF;
2599 tp->link_config.autoneg = AUTONEG_ENABLE;
2600 tg3_setup_phy(tp, 0);
2601 }
1da177e4
LT		 2602 }
2603
b5d3772c
MC		 2604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2605 u32 val;
2606
2607 val = tr32(GRC_VCPU_EXT_CTRL);
2608 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2609 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2610 int i;
2611 u32 val;
2612
2613 for (i = 0; i < 200; i++) {
2614 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2615 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2616 break;
2617 msleep(1);
2618 }
2619 }
a85feb8c
GZ		 2620 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2621 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2622 WOL_DRV_STATE_SHUTDOWN |
2623 WOL_DRV_WOL |
2624 WOL_SET_MAGIC_PKT);
6921d201 2625
05ac4cb7 2626 if (device_should_wake) {
1da177e4
LT		 2627 u32 mac_mode;
2628
2629 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2630 if (do_low_power) {
dd477003
MC		 2631 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2632 udelay(40);
2633 }
1da177e4 2634
3f7045c1
MC		 2635 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2636 mac_mode = MAC_MODE_PORT_MODE_GMII;
2637 else
2638 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2639
e8f3f6ca
MC		 2640 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2641 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2642 ASIC_REV_5700) {
2643 u32 speed = (tp->tg3_flags &
2644 TG3_FLAG_WOL_SPEED_100MB) ?
2645 SPEED_100 : SPEED_10;
2646 if (tg3_5700_link_polarity(tp, speed))
2647 mac_mode |= MAC_MODE_LINK_POLARITY;
2648 else
2649 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2650 }
1da177e4
LT		 2651 } else {
2652 mac_mode = MAC_MODE_PORT_MODE_TBI;
2653 }
2654
cbf46853 2655 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2656 tw32(MAC_LED_CTRL, tp->led_ctrl);
2657
05ac4cb7
MC		 2658 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2659 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2660 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2661 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2662 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2663 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2664
3bda1258
MC		 2665 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2666 mac_mode |= tp->mac_mode &
2667 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2668 if (mac_mode & MAC_MODE_APE_TX_EN)
2669 mac_mode |= MAC_MODE_TDE_ENABLE;
2670 }
2671
1da177e4
LT		 2672 tw32_f(MAC_MODE, mac_mode);
2673 udelay(100);
2674
2675 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2676 udelay(10);
2677 }
2678
2679 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2680 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2682 u32 base_val;
2683
2684 base_val = tp->pci_clock_ctrl;
2685 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2686 CLOCK_CTRL_TXCLK_DISABLE);
2687
b401e9e2
MC		 2688 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2689 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2690 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2691 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2692 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2693 /* do nothing */
85e94ced 2694 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2695 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2696 u32 newbits1, newbits2;
2697
2698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2700 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2701 CLOCK_CTRL_TXCLK_DISABLE |
2702 CLOCK_CTRL_ALTCLK);
2703 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2704 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2705 newbits1 = CLOCK_CTRL_625_CORE;
2706 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2707 } else {
2708 newbits1 = CLOCK_CTRL_ALTCLK;
2709 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2710 }
2711
b401e9e2
MC		 2712 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2713 40);
1da177e4 2714
b401e9e2
MC		 2715 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2716 40);
1da177e4
LT		 2717
2718 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2719 u32 newbits3;
2720
2721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2723 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2724 CLOCK_CTRL_TXCLK_DISABLE |
2725 CLOCK_CTRL_44MHZ_CORE);
2726 } else {
2727 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2728 }
2729
b401e9e2
MC		 2730 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2731 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2732 }
2733 }
2734
05ac4cb7 2735 if (!(device_should_wake) &&
22435849 2736 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2737 tg3_power_down_phy(tp, do_low_power);
6921d201 2738
1da177e4
LT		 2739 tg3_frob_aux_power(tp);
2740
2741 /* Workaround for unstable PLL clock */
2742 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2743 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2744 u32 val = tr32(0x7d00);
2745
2746 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2747 tw32(0x7d00, val);
6921d201 2748 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2749 int err;
2750
2751 err = tg3_nvram_lock(tp);
1da177e4 2752 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2753 if (!err)
2754 tg3_nvram_unlock(tp);
6921d201 2755 }
1da177e4
LT		 2756 }
2757
bbadf503
MC		 2758 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2759
05ac4cb7 2760 if (device_should_wake)
12dac075
RW		 2761 pci_enable_wake(tp->pdev, state, true);
2762
1da177e4 2763 /* Finally, set the new power state. */
12dac075 2764 pci_set_power_state(tp->pdev, state);
1da177e4 2765
1da177e4
LT		 2766 return 0;
2767}
2768
1da177e4
LT		 2769static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2770{
2771 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2772 case MII_TG3_AUX_STAT_10HALF:
2773 *speed = SPEED_10;
2774 *duplex = DUPLEX_HALF;
2775 break;
2776
2777 case MII_TG3_AUX_STAT_10FULL:
2778 *speed = SPEED_10;
2779 *duplex = DUPLEX_FULL;
2780 break;
2781
2782 case MII_TG3_AUX_STAT_100HALF:
2783 *speed = SPEED_100;
2784 *duplex = DUPLEX_HALF;
2785 break;
2786
2787 case MII_TG3_AUX_STAT_100FULL:
2788 *speed = SPEED_100;
2789 *duplex = DUPLEX_FULL;
2790 break;
2791
2792 case MII_TG3_AUX_STAT_1000HALF:
2793 *speed = SPEED_1000;
2794 *duplex = DUPLEX_HALF;
2795 break;
2796
2797 case MII_TG3_AUX_STAT_1000FULL:
2798 *speed = SPEED_1000;
2799 *duplex = DUPLEX_FULL;
2800 break;
2801
2802 default:
7f97a4bd 2803 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2804 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2805 SPEED_10;
2806 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2807 DUPLEX_HALF;
2808 break;
2809 }
1da177e4
LT		 2810 *speed = SPEED_INVALID;
2811 *duplex = DUPLEX_INVALID;
2812 break;
855e1111 2813 }
1da177e4
LT		 2814}
2815
2816static void tg3_phy_copper_begin(struct tg3 *tp)
2817{
2818 u32 new_adv;
2819 int i;
2820
2821 if (tp->link_config.phy_is_low_power) {
2822 /* Entering low power mode. Disable gigabit and
2823 * 100baseT advertisements.
2824 */
2825 tg3_writephy(tp, MII_TG3_CTRL, 0);
2826
2827 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2828 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2829 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2830 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2831
2832 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2833 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2834 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2835 tp->link_config.advertising &=
2836 ~(ADVERTISED_1000baseT_Half |
2837 ADVERTISED_1000baseT_Full);
2838
ba4d07a8 2839 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2840 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2841 new_adv |= ADVERTISE_10HALF;
2842 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2843 new_adv |= ADVERTISE_10FULL;
2844 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2845 new_adv |= ADVERTISE_100HALF;
2846 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2847 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2848
2849 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2850
1da177e4
LT		 2851 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852
2853 if (tp->link_config.advertising &
2854 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2855 new_adv = 0;
2856 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2857 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2858 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2859 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2860 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2861 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2862 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2863 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2864 MII_TG3_CTRL_ENABLE_AS_MASTER);
2865 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2866 } else {
2867 tg3_writephy(tp, MII_TG3_CTRL, 0);
2868 }
2869 } else {
ba4d07a8
MC		 2870 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2871 new_adv |= ADVERTISE_CSMA;
2872
1da177e4
LT		 2873 /* Asking for a specific link mode. */
2874 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2875 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2876
2877 if (tp->link_config.duplex == DUPLEX_FULL)
2878 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2879 else
2880 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2881 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2882 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2883 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2884 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2885 } else {
1da177e4
LT		 2886 if (tp->link_config.speed == SPEED_100) {
2887 if (tp->link_config.duplex == DUPLEX_FULL)
2888 new_adv |= ADVERTISE_100FULL;
2889 else
2890 new_adv |= ADVERTISE_100HALF;
2891 } else {
2892 if (tp->link_config.duplex == DUPLEX_FULL)
2893 new_adv |= ADVERTISE_10FULL;
2894 else
2895 new_adv |= ADVERTISE_10HALF;
2896 }
2897 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2898
2899 new_adv = 0;
1da177e4 2900 }
ba4d07a8
MC		 2901
2902 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2903 }
2904
2905 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2906 tp->link_config.speed != SPEED_INVALID) {
2907 u32 bmcr, orig_bmcr;
2908
2909 tp->link_config.active_speed = tp->link_config.speed;
2910 tp->link_config.active_duplex = tp->link_config.duplex;
2911
2912 bmcr = 0;
2913 switch (tp->link_config.speed) {
2914 default:
2915 case SPEED_10:
2916 break;
2917
2918 case SPEED_100:
2919 bmcr |= BMCR_SPEED100;
2920 break;
2921
2922 case SPEED_1000:
2923 bmcr |= TG3_BMCR_SPEED1000;
2924 break;
855e1111 2925 }
1da177e4
LT		 2926
2927 if (tp->link_config.duplex == DUPLEX_FULL)
2928 bmcr |= BMCR_FULLDPLX;
2929
2930 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2931 (bmcr != orig_bmcr)) {
2932 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2933 for (i = 0; i < 1500; i++) {
2934 u32 tmp;
2935
2936 udelay(10);
2937 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2938 tg3_readphy(tp, MII_BMSR, &tmp))
2939 continue;
2940 if (!(tmp & BMSR_LSTATUS)) {
2941 udelay(40);
2942 break;
2943 }
2944 }
2945 tg3_writephy(tp, MII_BMCR, bmcr);
2946 udelay(40);
2947 }
2948 } else {
2949 tg3_writephy(tp, MII_BMCR,
2950 BMCR_ANENABLE | BMCR_ANRESTART);
2951 }
2952}
2953
2954static int tg3_init_5401phy_dsp(struct tg3 *tp)
2955{
2956 int err;
2957
2958 /* Turn off tap power management. */
2959 /* Set Extended packet length bit */
2960 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2961
2962 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2963 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2964
2965 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2966 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2967
2968 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2969 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2970
2971 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2972 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2973
2974 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2975 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2976
2977 udelay(40);
2978
2979 return err;
2980}
2981
3600d918 2982static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2983{
3600d918
MC		 2984 u32 adv_reg, all_mask = 0;
2985
2986 if (mask & ADVERTISED_10baseT_Half)
2987 all_mask |= ADVERTISE_10HALF;
2988 if (mask & ADVERTISED_10baseT_Full)
2989 all_mask |= ADVERTISE_10FULL;
2990 if (mask & ADVERTISED_100baseT_Half)
2991 all_mask |= ADVERTISE_100HALF;
2992 if (mask & ADVERTISED_100baseT_Full)
2993 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2994
2995 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2996 return 0;
2997
1da177e4
LT		 2998 if ((adv_reg & all_mask) != all_mask)
2999 return 0;
3000 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3001 u32 tg3_ctrl;
3002
3600d918
MC		 3003 all_mask = 0;
3004 if (mask & ADVERTISED_1000baseT_Half)
3005 all_mask |= ADVERTISE_1000HALF;
3006 if (mask & ADVERTISED_1000baseT_Full)
3007 all_mask |= ADVERTISE_1000FULL;
3008
1da177e4
LT		 3009 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3010 return 0;
3011
1da177e4
LT		 3012 if ((tg3_ctrl & all_mask) != all_mask)
3013 return 0;
3014 }
3015 return 1;
3016}
3017
ef167e27
MC		 3018static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3019{
3020 u32 curadv, reqadv;
3021
3022 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3023 return 1;
3024
3025 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3026 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3027
3028 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3029 if (curadv != reqadv)
3030 return 0;
3031
3032 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3033 tg3_readphy(tp, MII_LPA, rmtadv);
3034 } else {
3035 /* Reprogram the advertisement register, even if it
3036 * does not affect the current link. If the link
3037 * gets renegotiated in the future, we can save an
3038 * additional renegotiation cycle by advertising
3039 * it correctly in the first place.
3040 */
3041 if (curadv != reqadv) {
3042 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3043 ADVERTISE_PAUSE_ASYM);
3044 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3045 }
3046 }
3047
3048 return 1;
3049}
3050
1da177e4
LT		 3051static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3052{
3053 int current_link_up;
3054 u32 bmsr, dummy;
ef167e27 3055 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3056 u16 current_speed;
3057 u8 current_duplex;
3058 int i, err;
3059
3060 tw32(MAC_EVENT, 0);
3061
3062 tw32_f(MAC_STATUS,
3063 (MAC_STATUS_SYNC_CHANGED |
3064 MAC_STATUS_CFG_CHANGED |
3065 MAC_STATUS_MI_COMPLETION |
3066 MAC_STATUS_LNKSTATE_CHANGED));
3067 udelay(40);
3068
8ef21428
MC		 3069 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3070 tw32_f(MAC_MI_MODE,
3071 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3072 udelay(80);
3073 }
1da177e4
LT		 3074
3075 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3076
3077 /* Some third-party PHYs need to be reset on link going
3078 * down.
3079 */
3080 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3082 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3083 netif_carrier_ok(tp->dev)) {
3084 tg3_readphy(tp, MII_BMSR, &bmsr);
3085 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3086 !(bmsr & BMSR_LSTATUS))
3087 force_reset = 1;
3088 }
3089 if (force_reset)
3090 tg3_phy_reset(tp);
3091
79eb6904 3092 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 3093 tg3_readphy(tp, MII_BMSR, &bmsr);
3094 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3095 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3096 bmsr = 0;
3097
3098 if (!(bmsr & BMSR_LSTATUS)) {
3099 err = tg3_init_5401phy_dsp(tp);
3100 if (err)
3101 return err;
3102
3103 tg3_readphy(tp, MII_BMSR, &bmsr);
3104 for (i = 0; i < 1000; i++) {
3105 udelay(10);
3106 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3107 (bmsr & BMSR_LSTATUS)) {
3108 udelay(40);
3109 break;
3110 }
3111 }
3112
79eb6904
MC		 3113 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3114 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 3115 !(bmsr & BMSR_LSTATUS) &&
3116 tp->link_config.active_speed == SPEED_1000) {
3117 err = tg3_phy_reset(tp);
3118 if (!err)
3119 err = tg3_init_5401phy_dsp(tp);
3120 if (err)
3121 return err;
3122 }
3123 }
3124 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3125 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3126 /* 5701 {A0,B0} CRC bug workaround */
3127 tg3_writephy(tp, 0x15, 0x0a75);
3128 tg3_writephy(tp, 0x1c, 0x8c68);
3129 tg3_writephy(tp, 0x1c, 0x8d68);
3130 tg3_writephy(tp, 0x1c, 0x8c68);
3131 }
3132
3133 /* Clear pending interrupts... */
3134 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3135 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3136
3137 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3138 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3139 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3140 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3141
3142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3144 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3145 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3146 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3147 else
3148 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3149 }
3150
3151 current_link_up = 0;
3152 current_speed = SPEED_INVALID;
3153 current_duplex = DUPLEX_INVALID;
3154
3155 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3156 u32 val;
3157
3158 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3159 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3160 if (!(val & (1 << 10))) {
3161 val |= (1 << 10);
3162 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3163 goto relink;
3164 }
3165 }
3166
3167 bmsr = 0;
3168 for (i = 0; i < 100; i++) {
3169 tg3_readphy(tp, MII_BMSR, &bmsr);
3170 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3171 (bmsr & BMSR_LSTATUS))
3172 break;
3173 udelay(40);
3174 }
3175
3176 if (bmsr & BMSR_LSTATUS) {
3177 u32 aux_stat, bmcr;
3178
3179 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3180 for (i = 0; i < 2000; i++) {
3181 udelay(10);
3182 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3183 aux_stat)
3184 break;
3185 }
3186
3187 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3188 &current_speed,
3189 &current_duplex);
3190
3191 bmcr = 0;
3192 for (i = 0; i < 200; i++) {
3193 tg3_readphy(tp, MII_BMCR, &bmcr);
3194 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3195 continue;
3196 if (bmcr && bmcr != 0x7fff)
3197 break;
3198 udelay(10);
3199 }
3200
ef167e27
MC		 3201 lcl_adv = 0;
3202 rmt_adv = 0;
1da177e4 3203
ef167e27
MC		 3204 tp->link_config.active_speed = current_speed;
3205 tp->link_config.active_duplex = current_duplex;
3206
3207 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3208 if ((bmcr & BMCR_ANENABLE) &&
3209 tg3_copper_is_advertising_all(tp,
3210 tp->link_config.advertising)) {
3211 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3212 &rmt_adv))
3213 current_link_up = 1;
1da177e4
LT		 3214 }
3215 } else {
3216 if (!(bmcr & BMCR_ANENABLE) &&
3217 tp->link_config.speed == current_speed &&
ef167e27
MC		 3218 tp->link_config.duplex == current_duplex &&
3219 tp->link_config.flowctrl ==
3220 tp->link_config.active_flowctrl) {
1da177e4 3221 current_link_up = 1;
1da177e4
LT		 3222 }
3223 }
3224
ef167e27
MC		 3225 if (current_link_up == 1 &&
3226 tp->link_config.active_duplex == DUPLEX_FULL)
3227 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3228 }
3229
1da177e4 3230relink:
6921d201 3231 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3232 u32 tmp;
3233
3234 tg3_phy_copper_begin(tp);
3235
3236 tg3_readphy(tp, MII_BMSR, &tmp);
3237 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3238 (tmp & BMSR_LSTATUS))
3239 current_link_up = 1;
3240 }
3241
3242 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3243 if (current_link_up == 1) {
3244 if (tp->link_config.active_speed == SPEED_100 ||
3245 tp->link_config.active_speed == SPEED_10)
3246 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3247 else
3248 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3249 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3250 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3251 else
1da177e4
LT		 3252 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3253
3254 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3255 if (tp->link_config.active_duplex == DUPLEX_HALF)
3256 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3257
1da177e4 3258 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3259 if (current_link_up == 1 &&
3260 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3261 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3262 else
3263 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3264 }
3265
3266 /* ??? Without this setting Netgear GA302T PHY does not
3267 * ??? send/receive packets...
3268 */
79eb6904 3269 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1da177e4
LT		 3270 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3271 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3272 tw32_f(MAC_MI_MODE, tp->mi_mode);
3273 udelay(80);
3274 }
3275
3276 tw32_f(MAC_MODE, tp->mac_mode);
3277 udelay(40);
3278
3279 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3280 /* Polled via timer. */
3281 tw32_f(MAC_EVENT, 0);
3282 } else {
3283 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3284 }
3285 udelay(40);
3286
3287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3288 current_link_up == 1 &&
3289 tp->link_config.active_speed == SPEED_1000 &&
3290 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3291 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3292 udelay(120);
3293 tw32_f(MAC_STATUS,
3294 (MAC_STATUS_SYNC_CHANGED |
3295 MAC_STATUS_CFG_CHANGED));
3296 udelay(40);
3297 tg3_write_mem(tp,
3298 NIC_SRAM_FIRMWARE_MBOX,
3299 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3300 }
3301
5e7dfd0f
MC		 3302 /* Prevent send BD corruption. */
3303 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3304 u16 oldlnkctl, newlnkctl;
3305
3306 pci_read_config_word(tp->pdev,
3307 tp->pcie_cap + PCI_EXP_LNKCTL,
3308 &oldlnkctl);
3309 if (tp->link_config.active_speed == SPEED_100 ||
3310 tp->link_config.active_speed == SPEED_10)
3311 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3312 else
3313 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3314 if (newlnkctl != oldlnkctl)
3315 pci_write_config_word(tp->pdev,
3316 tp->pcie_cap + PCI_EXP_LNKCTL,
3317 newlnkctl);
3318 }
3319
1da177e4
LT		 3320 if (current_link_up != netif_carrier_ok(tp->dev)) {
3321 if (current_link_up)
3322 netif_carrier_on(tp->dev);
3323 else
3324 netif_carrier_off(tp->dev);
3325 tg3_link_report(tp);
3326 }
3327
3328 return 0;
3329}
3330
3331struct tg3_fiber_aneginfo {
3332 int state;
3333#define ANEG_STATE_UNKNOWN 0
3334#define ANEG_STATE_AN_ENABLE 1
3335#define ANEG_STATE_RESTART_INIT 2
3336#define ANEG_STATE_RESTART 3
3337#define ANEG_STATE_DISABLE_LINK_OK 4
3338#define ANEG_STATE_ABILITY_DETECT_INIT 5
3339#define ANEG_STATE_ABILITY_DETECT 6
3340#define ANEG_STATE_ACK_DETECT_INIT 7
3341#define ANEG_STATE_ACK_DETECT 8
3342#define ANEG_STATE_COMPLETE_ACK_INIT 9
3343#define ANEG_STATE_COMPLETE_ACK 10
3344#define ANEG_STATE_IDLE_DETECT_INIT 11
3345#define ANEG_STATE_IDLE_DETECT 12
3346#define ANEG_STATE_LINK_OK 13
3347#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3348#define ANEG_STATE_NEXT_PAGE_WAIT 15
3349
3350 u32 flags;
3351#define MR_AN_ENABLE 0x00000001
3352#define MR_RESTART_AN 0x00000002
3353#define MR_AN_COMPLETE 0x00000004
3354#define MR_PAGE_RX 0x00000008
3355#define MR_NP_LOADED 0x00000010
3356#define MR_TOGGLE_TX 0x00000020
3357#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3358#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3359#define MR_LP_ADV_SYM_PAUSE 0x00000100
3360#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3361#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3362#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3363#define MR_LP_ADV_NEXT_PAGE 0x00001000
3364#define MR_TOGGLE_RX 0x00002000
3365#define MR_NP_RX 0x00004000
3366
3367#define MR_LINK_OK 0x80000000
3368
3369 unsigned long link_time, cur_time;
3370
3371 u32 ability_match_cfg;
3372 int ability_match_count;
3373
3374 char ability_match, idle_match, ack_match;
3375
3376 u32 txconfig, rxconfig;
3377#define ANEG_CFG_NP 0x00000080
3378#define ANEG_CFG_ACK 0x00000040
3379#define ANEG_CFG_RF2 0x00000020
3380#define ANEG_CFG_RF1 0x00000010
3381#define ANEG_CFG_PS2 0x00000001
3382#define ANEG_CFG_PS1 0x00008000
3383#define ANEG_CFG_HD 0x00004000
3384#define ANEG_CFG_FD 0x00002000
3385#define ANEG_CFG_INVAL 0x00001f06
3386
3387};
3388#define ANEG_OK 0
3389#define ANEG_DONE 1
3390#define ANEG_TIMER_ENAB 2
3391#define ANEG_FAILED -1
3392
3393#define ANEG_STATE_SETTLE_TIME 10000
3394
3395static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3396 struct tg3_fiber_aneginfo *ap)
3397{
5be73b47 3398 u16 flowctrl;
1da177e4
LT		 3399 unsigned long delta;
3400 u32 rx_cfg_reg;
3401 int ret;
3402
3403 if (ap->state == ANEG_STATE_UNKNOWN) {
3404 ap->rxconfig = 0;
3405 ap->link_time = 0;
3406 ap->cur_time = 0;
3407 ap->ability_match_cfg = 0;
3408 ap->ability_match_count = 0;
3409 ap->ability_match = 0;
3410 ap->idle_match = 0;
3411 ap->ack_match = 0;
3412 }
3413 ap->cur_time++;
3414
3415 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3416 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3417
3418 if (rx_cfg_reg != ap->ability_match_cfg) {
3419 ap->ability_match_cfg = rx_cfg_reg;
3420 ap->ability_match = 0;
3421 ap->ability_match_count = 0;
3422 } else {
3423 if (++ap->ability_match_count > 1) {
3424 ap->ability_match = 1;
3425 ap->ability_match_cfg = rx_cfg_reg;
3426 }
3427 }
3428 if (rx_cfg_reg & ANEG_CFG_ACK)
3429 ap->ack_match = 1;
3430 else
3431 ap->ack_match = 0;
3432
3433 ap->idle_match = 0;
3434 } else {
3435 ap->idle_match = 1;
3436 ap->ability_match_cfg = 0;
3437 ap->ability_match_count = 0;
3438 ap->ability_match = 0;
3439 ap->ack_match = 0;
3440
3441 rx_cfg_reg = 0;
3442 }
3443
3444 ap->rxconfig = rx_cfg_reg;
3445 ret = ANEG_OK;
3446
33f401ae 3447 switch (ap->state) {
1da177e4
LT		 3448 case ANEG_STATE_UNKNOWN:
3449 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3450 ap->state = ANEG_STATE_AN_ENABLE;
3451
3452 /* fallthru */
3453 case ANEG_STATE_AN_ENABLE:
3454 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3455 if (ap->flags & MR_AN_ENABLE) {
3456 ap->link_time = 0;
3457 ap->cur_time = 0;
3458 ap->ability_match_cfg = 0;
3459 ap->ability_match_count = 0;
3460 ap->ability_match = 0;
3461 ap->idle_match = 0;
3462 ap->ack_match = 0;
3463
3464 ap->state = ANEG_STATE_RESTART_INIT;
3465 } else {
3466 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3467 }
3468 break;
3469
3470 case ANEG_STATE_RESTART_INIT:
3471 ap->link_time = ap->cur_time;
3472 ap->flags &= ~(MR_NP_LOADED);
3473 ap->txconfig = 0;
3474 tw32(MAC_TX_AUTO_NEG, 0);
3475 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3476 tw32_f(MAC_MODE, tp->mac_mode);
3477 udelay(40);
3478
3479 ret = ANEG_TIMER_ENAB;
3480 ap->state = ANEG_STATE_RESTART;
3481
3482 /* fallthru */
3483 case ANEG_STATE_RESTART:
3484 delta = ap->cur_time - ap->link_time;
859a5887 3485 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 3486 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 3487 else
1da177e4 3488 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 3489 break;
3490
3491 case ANEG_STATE_DISABLE_LINK_OK:
3492 ret = ANEG_DONE;
3493 break;
3494
3495 case ANEG_STATE_ABILITY_DETECT_INIT:
3496 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3497 ap->txconfig = ANEG_CFG_FD;
3498 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3499 if (flowctrl & ADVERTISE_1000XPAUSE)
3500 ap->txconfig |= ANEG_CFG_PS1;
3501 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3502 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3503 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3504 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3505 tw32_f(MAC_MODE, tp->mac_mode);
3506 udelay(40);
3507
3508 ap->state = ANEG_STATE_ABILITY_DETECT;
3509 break;
3510
3511 case ANEG_STATE_ABILITY_DETECT:
859a5887 3512 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 3513 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 3514 break;
3515
3516 case ANEG_STATE_ACK_DETECT_INIT:
3517 ap->txconfig |= ANEG_CFG_ACK;
3518 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3519 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3520 tw32_f(MAC_MODE, tp->mac_mode);
3521 udelay(40);
3522
3523 ap->state = ANEG_STATE_ACK_DETECT;
3524
3525 /* fallthru */
3526 case ANEG_STATE_ACK_DETECT:
3527 if (ap->ack_match != 0) {
3528 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3529 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3530 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3531 } else {
3532 ap->state = ANEG_STATE_AN_ENABLE;
3533 }
3534 } else if (ap->ability_match != 0 &&
3535 ap->rxconfig == 0) {
3536 ap->state = ANEG_STATE_AN_ENABLE;
3537 }
3538 break;
3539
3540 case ANEG_STATE_COMPLETE_ACK_INIT:
3541 if (ap->rxconfig & ANEG_CFG_INVAL) {
3542 ret = ANEG_FAILED;
3543 break;
3544 }
3545 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3546 MR_LP_ADV_HALF_DUPLEX |
3547 MR_LP_ADV_SYM_PAUSE |
3548 MR_LP_ADV_ASYM_PAUSE |
3549 MR_LP_ADV_REMOTE_FAULT1 |
3550 MR_LP_ADV_REMOTE_FAULT2 |
3551 MR_LP_ADV_NEXT_PAGE |
3552 MR_TOGGLE_RX |
3553 MR_NP_RX);
3554 if (ap->rxconfig & ANEG_CFG_FD)
3555 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3556 if (ap->rxconfig & ANEG_CFG_HD)
3557 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3558 if (ap->rxconfig & ANEG_CFG_PS1)
3559 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3560 if (ap->rxconfig & ANEG_CFG_PS2)
3561 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3562 if (ap->rxconfig & ANEG_CFG_RF1)
3563 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3564 if (ap->rxconfig & ANEG_CFG_RF2)
3565 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3566 if (ap->rxconfig & ANEG_CFG_NP)
3567 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3568
3569 ap->link_time = ap->cur_time;
3570
3571 ap->flags ^= (MR_TOGGLE_TX);
3572 if (ap->rxconfig & 0x0008)
3573 ap->flags |= MR_TOGGLE_RX;
3574 if (ap->rxconfig & ANEG_CFG_NP)
3575 ap->flags |= MR_NP_RX;
3576 ap->flags |= MR_PAGE_RX;
3577
3578 ap->state = ANEG_STATE_COMPLETE_ACK;
3579 ret = ANEG_TIMER_ENAB;
3580 break;
3581
3582 case ANEG_STATE_COMPLETE_ACK:
3583 if (ap->ability_match != 0 &&
3584 ap->rxconfig == 0) {
3585 ap->state = ANEG_STATE_AN_ENABLE;
3586 break;
3587 }
3588 delta = ap->cur_time - ap->link_time;
3589 if (delta > ANEG_STATE_SETTLE_TIME) {
3590 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3591 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3592 } else {
3593 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3594 !(ap->flags & MR_NP_RX)) {
3595 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3596 } else {
3597 ret = ANEG_FAILED;
3598 }
3599 }
3600 }
3601 break;
3602
3603 case ANEG_STATE_IDLE_DETECT_INIT:
3604 ap->link_time = ap->cur_time;
3605 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3606 tw32_f(MAC_MODE, tp->mac_mode);
3607 udelay(40);
3608
3609 ap->state = ANEG_STATE_IDLE_DETECT;
3610 ret = ANEG_TIMER_ENAB;
3611 break;
3612
3613 case ANEG_STATE_IDLE_DETECT:
3614 if (ap->ability_match != 0 &&
3615 ap->rxconfig == 0) {
3616 ap->state = ANEG_STATE_AN_ENABLE;
3617 break;
3618 }
3619 delta = ap->cur_time - ap->link_time;
3620 if (delta > ANEG_STATE_SETTLE_TIME) {
3621 /* XXX another gem from the Broadcom driver :( */
3622 ap->state = ANEG_STATE_LINK_OK;
3623 }
3624 break;
3625
3626 case ANEG_STATE_LINK_OK:
3627 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3628 ret = ANEG_DONE;
3629 break;
3630
3631 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3632 /* ??? unimplemented */
3633 break;
3634
3635 case ANEG_STATE_NEXT_PAGE_WAIT:
3636 /* ??? unimplemented */
3637 break;
3638
3639 default:
3640 ret = ANEG_FAILED;
3641 break;
855e1111 3642 }
1da177e4
LT		 3643
3644 return ret;
3645}
3646
5be73b47 3647static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3648{
3649 int res = 0;
3650 struct tg3_fiber_aneginfo aninfo;
3651 int status = ANEG_FAILED;
3652 unsigned int tick;
3653 u32 tmp;
3654
3655 tw32_f(MAC_TX_AUTO_NEG, 0);
3656
3657 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3658 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3659 udelay(40);
3660
3661 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3662 udelay(40);
3663
3664 memset(&aninfo, 0, sizeof(aninfo));
3665 aninfo.flags |= MR_AN_ENABLE;
3666 aninfo.state = ANEG_STATE_UNKNOWN;
3667 aninfo.cur_time = 0;
3668 tick = 0;
3669 while (++tick < 195000) {
3670 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3671 if (status == ANEG_DONE || status == ANEG_FAILED)
3672 break;
3673
3674 udelay(1);
3675 }
3676
3677 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3678 tw32_f(MAC_MODE, tp->mac_mode);
3679 udelay(40);
3680
5be73b47
MC		 3681 *txflags = aninfo.txconfig;
3682 *rxflags = aninfo.flags;
1da177e4
LT		 3683
3684 if (status == ANEG_DONE &&
3685 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3686 MR_LP_ADV_FULL_DUPLEX)))
3687 res = 1;
3688
3689 return res;
3690}
3691
3692static void tg3_init_bcm8002(struct tg3 *tp)
3693{
3694 u32 mac_status = tr32(MAC_STATUS);
3695 int i;
3696
3697 /* Reset when initting first time or we have a link. */
3698 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3699 !(mac_status & MAC_STATUS_PCS_SYNCED))
3700 return;
3701
3702 /* Set PLL lock range. */
3703 tg3_writephy(tp, 0x16, 0x8007);
3704
3705 /* SW reset */
3706 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3707
3708 /* Wait for reset to complete. */
3709 /* XXX schedule_timeout() ... */
3710 for (i = 0; i < 500; i++)
3711 udelay(10);
3712
3713 /* Config mode; select PMA/Ch 1 regs. */
3714 tg3_writephy(tp, 0x10, 0x8411);
3715
3716 /* Enable auto-lock and comdet, select txclk for tx. */
3717 tg3_writephy(tp, 0x11, 0x0a10);
3718
3719 tg3_writephy(tp, 0x18, 0x00a0);
3720 tg3_writephy(tp, 0x16, 0x41ff);
3721
3722 /* Assert and deassert POR. */
3723 tg3_writephy(tp, 0x13, 0x0400);
3724 udelay(40);
3725 tg3_writephy(tp, 0x13, 0x0000);
3726
3727 tg3_writephy(tp, 0x11, 0x0a50);
3728 udelay(40);
3729 tg3_writephy(tp, 0x11, 0x0a10);
3730
3731 /* Wait for signal to stabilize */
3732 /* XXX schedule_timeout() ... */
3733 for (i = 0; i < 15000; i++)
3734 udelay(10);
3735
3736 /* Deselect the channel register so we can read the PHYID
3737 * later.
3738 */
3739 tg3_writephy(tp, 0x10, 0x8011);
3740}
3741
3742static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3743{
82cd3d11 3744 u16 flowctrl;
1da177e4
LT		 3745 u32 sg_dig_ctrl, sg_dig_status;
3746 u32 serdes_cfg, expected_sg_dig_ctrl;
3747 int workaround, port_a;
3748 int current_link_up;
3749
3750 serdes_cfg = 0;
3751 expected_sg_dig_ctrl = 0;
3752 workaround = 0;
3753 port_a = 1;
3754 current_link_up = 0;
3755
3756 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3757 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3758 workaround = 1;
3759 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3760 port_a = 0;
3761
3762 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3763 /* preserve bits 20-23 for voltage regulator */
3764 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3765 }
3766
3767 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3768
3769 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3770 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3771 if (workaround) {
3772 u32 val = serdes_cfg;
3773
3774 if (port_a)
3775 val |= 0xc010000;
3776 else
3777 val |= 0x4010000;
3778 tw32_f(MAC_SERDES_CFG, val);
3779 }
c98f6e3b
MC		 3780
3781 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3782 }
3783 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3784 tg3_setup_flow_control(tp, 0, 0);
3785 current_link_up = 1;
3786 }
3787 goto out;
3788 }
3789
3790 /* Want auto-negotiation. */
c98f6e3b 3791 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3792
82cd3d11
MC		 3793 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3794 if (flowctrl & ADVERTISE_1000XPAUSE)
3795 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3796 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3797 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3798
3799 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3800 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3801 tp->serdes_counter &&
3802 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3803 MAC_STATUS_RCVD_CFG)) ==
3804 MAC_STATUS_PCS_SYNCED)) {
3805 tp->serdes_counter--;
3806 current_link_up = 1;
3807 goto out;
3808 }
3809restart_autoneg:
1da177e4
LT		 3810 if (workaround)
3811 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3812 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3813 udelay(5);
3814 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3815
3d3ebe74
MC		 3816 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3817 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3818 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3819 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3820 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3821 mac_status = tr32(MAC_STATUS);
3822
c98f6e3b 3823 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3824 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3825 u32 local_adv = 0, remote_adv = 0;
3826
3827 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3828 local_adv |= ADVERTISE_1000XPAUSE;
3829 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3830 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3831
c98f6e3b 3832 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3833 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3834 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3835 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3836
3837 tg3_setup_flow_control(tp, local_adv, remote_adv);
3838 current_link_up = 1;
3d3ebe74
MC		 3839 tp->serdes_counter = 0;
3840 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3841 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3842 if (tp->serdes_counter)
3843 tp->serdes_counter--;
1da177e4
LT		 3844 else {
3845 if (workaround) {
3846 u32 val = serdes_cfg;
3847
3848 if (port_a)
3849 val |= 0xc010000;
3850 else
3851 val |= 0x4010000;
3852
3853 tw32_f(MAC_SERDES_CFG, val);
3854 }
3855
c98f6e3b 3856 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3857 udelay(40);
3858
3859 /* Link parallel detection - link is up */
3860 /* only if we have PCS_SYNC and not */
3861 /* receiving config code words */
3862 mac_status = tr32(MAC_STATUS);
3863 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3864 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3865 tg3_setup_flow_control(tp, 0, 0);
3866 current_link_up = 1;
3d3ebe74
MC		 3867 tp->tg3_flags2 |=
3868 TG3_FLG2_PARALLEL_DETECT;
3869 tp->serdes_counter =
3870 SERDES_PARALLEL_DET_TIMEOUT;
3871 } else
3872 goto restart_autoneg;
1da177e4
LT		 3873 }
3874 }
3d3ebe74
MC		 3875 } else {
3876 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3877 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3878 }
3879
3880out:
3881 return current_link_up;
3882}
3883
3884static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3885{
3886 int current_link_up = 0;
3887
5cf64b8a 3888 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3889 goto out;
1da177e4
LT		 3890
3891 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3892 u32 txflags, rxflags;
1da177e4 3893 int i;
6aa20a22 3894
5be73b47
MC		 3895 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3896 u32 local_adv = 0, remote_adv = 0;
1da177e4 3897
5be73b47
MC		 3898 if (txflags & ANEG_CFG_PS1)
3899 local_adv |= ADVERTISE_1000XPAUSE;
3900 if (txflags & ANEG_CFG_PS2)
3901 local_adv |= ADVERTISE_1000XPSE_ASYM;
3902
3903 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3904 remote_adv |= LPA_1000XPAUSE;
3905 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3906 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3907
3908 tg3_setup_flow_control(tp, local_adv, remote_adv);
3909
1da177e4
LT		 3910 current_link_up = 1;
3911 }
3912 for (i = 0; i < 30; i++) {
3913 udelay(20);
3914 tw32_f(MAC_STATUS,
3915 (MAC_STATUS_SYNC_CHANGED |
3916 MAC_STATUS_CFG_CHANGED));
3917 udelay(40);
3918 if ((tr32(MAC_STATUS) &
3919 (MAC_STATUS_SYNC_CHANGED |
3920 MAC_STATUS_CFG_CHANGED)) == 0)
3921 break;
3922 }
3923
3924 mac_status = tr32(MAC_STATUS);
3925 if (current_link_up == 0 &&
3926 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3927 !(mac_status & MAC_STATUS_RCVD_CFG))
3928 current_link_up = 1;
3929 } else {
5be73b47
MC		 3930 tg3_setup_flow_control(tp, 0, 0);
3931
1da177e4
LT		 3932 /* Forcing 1000FD link up. */
3933 current_link_up = 1;
1da177e4
LT		 3934
3935 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3936 udelay(40);
e8f3f6ca
MC		 3937
3938 tw32_f(MAC_MODE, tp->mac_mode);
3939 udelay(40);
1da177e4
LT		 3940 }
3941
3942out:
3943 return current_link_up;
3944}
3945
3946static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3947{
3948 u32 orig_pause_cfg;
3949 u16 orig_active_speed;
3950 u8 orig_active_duplex;
3951 u32 mac_status;
3952 int current_link_up;
3953 int i;
3954
8d018621 3955 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3956 orig_active_speed = tp->link_config.active_speed;
3957 orig_active_duplex = tp->link_config.active_duplex;
3958
3959 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3960 netif_carrier_ok(tp->dev) &&
3961 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3962 mac_status = tr32(MAC_STATUS);
3963 mac_status &= (MAC_STATUS_PCS_SYNCED |
3964 MAC_STATUS_SIGNAL_DET |
3965 MAC_STATUS_CFG_CHANGED |
3966 MAC_STATUS_RCVD_CFG);
3967 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3968 MAC_STATUS_SIGNAL_DET)) {
3969 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3970 MAC_STATUS_CFG_CHANGED));
3971 return 0;
3972 }
3973 }
3974
3975 tw32_f(MAC_TX_AUTO_NEG, 0);
3976
3977 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3978 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3979 tw32_f(MAC_MODE, tp->mac_mode);
3980 udelay(40);
3981
79eb6904 3982 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 3983 tg3_init_bcm8002(tp);
3984
3985 /* Enable link change event even when serdes polling. */
3986 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3987 udelay(40);
3988
3989 current_link_up = 0;
3990 mac_status = tr32(MAC_STATUS);
3991
3992 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3993 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3994 else
3995 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3996
898a56f8 3997 tp->napi[0].hw_status->status =
1da177e4 3998 (SD_STATUS_UPDATED |
898a56f8 3999 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 4000
4001 for (i = 0; i < 100; i++) {
4002 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4003 MAC_STATUS_CFG_CHANGED));
4004 udelay(5);
4005 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 4006 MAC_STATUS_CFG_CHANGED |
4007 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 4008 break;
4009 }
4010
4011 mac_status = tr32(MAC_STATUS);
4012 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4013 current_link_up = 0;
3d3ebe74
MC		 4014 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4015 tp->serdes_counter == 0) {
1da177e4
LT		 4016 tw32_f(MAC_MODE, (tp->mac_mode |
4017 MAC_MODE_SEND_CONFIGS));
4018 udelay(1);
4019 tw32_f(MAC_MODE, tp->mac_mode);
4020 }
4021 }
4022
4023 if (current_link_up == 1) {
4024 tp->link_config.active_speed = SPEED_1000;
4025 tp->link_config.active_duplex = DUPLEX_FULL;
4026 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4027 LED_CTRL_LNKLED_OVERRIDE |
4028 LED_CTRL_1000MBPS_ON));
4029 } else {
4030 tp->link_config.active_speed = SPEED_INVALID;
4031 tp->link_config.active_duplex = DUPLEX_INVALID;
4032 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4033 LED_CTRL_LNKLED_OVERRIDE |
4034 LED_CTRL_TRAFFIC_OVERRIDE));
4035 }
4036
4037 if (current_link_up != netif_carrier_ok(tp->dev)) {
4038 if (current_link_up)
4039 netif_carrier_on(tp->dev);
4040 else
4041 netif_carrier_off(tp->dev);
4042 tg3_link_report(tp);
4043 } else {
8d018621 4044 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4045 if (orig_pause_cfg != now_pause_cfg ||
4046 orig_active_speed != tp->link_config.active_speed ||
4047 orig_active_duplex != tp->link_config.active_duplex)
4048 tg3_link_report(tp);
4049 }
4050
4051 return 0;
4052}
4053
747e8f8b
MC		 4054static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4055{
4056 int current_link_up, err = 0;
4057 u32 bmsr, bmcr;
4058 u16 current_speed;
4059 u8 current_duplex;
ef167e27 4060 u32 local_adv, remote_adv;
747e8f8b
MC		 4061
4062 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4063 tw32_f(MAC_MODE, tp->mac_mode);
4064 udelay(40);
4065
4066 tw32(MAC_EVENT, 0);
4067
4068 tw32_f(MAC_STATUS,
4069 (MAC_STATUS_SYNC_CHANGED |
4070 MAC_STATUS_CFG_CHANGED |
4071 MAC_STATUS_MI_COMPLETION |
4072 MAC_STATUS_LNKSTATE_CHANGED));
4073 udelay(40);
4074
4075 if (force_reset)
4076 tg3_phy_reset(tp);
4077
4078 current_link_up = 0;
4079 current_speed = SPEED_INVALID;
4080 current_duplex = DUPLEX_INVALID;
4081
4082 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4083 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4085 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4086 bmsr |= BMSR_LSTATUS;
4087 else
4088 bmsr &= ~BMSR_LSTATUS;
4089 }
747e8f8b
MC		 4090
4091 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4092
4093 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4094 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4095 /* do nothing, just check for link up at the end */
4096 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4097 u32 adv, new_adv;
4098
4099 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4101 ADVERTISE_1000XPAUSE |
4102 ADVERTISE_1000XPSE_ASYM |
4103 ADVERTISE_SLCT);
4104
ba4d07a8 4105 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4106
4107 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4108 new_adv |= ADVERTISE_1000XHALF;
4109 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4110 new_adv |= ADVERTISE_1000XFULL;
4111
4112 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4113 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4114 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4115 tg3_writephy(tp, MII_BMCR, bmcr);
4116
4117 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4118 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4119 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4120
4121 return err;
4122 }
4123 } else {
4124 u32 new_bmcr;
4125
4126 bmcr &= ~BMCR_SPEED1000;
4127 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4128
4129 if (tp->link_config.duplex == DUPLEX_FULL)
4130 new_bmcr |= BMCR_FULLDPLX;
4131
4132 if (new_bmcr != bmcr) {
4133 /* BMCR_SPEED1000 is a reserved bit that needs
4134 * to be set on write.
4135 */
4136 new_bmcr |= BMCR_SPEED1000;
4137
4138 /* Force a linkdown */
4139 if (netif_carrier_ok(tp->dev)) {
4140 u32 adv;
4141
4142 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4143 adv &= ~(ADVERTISE_1000XFULL |
4144 ADVERTISE_1000XHALF |
4145 ADVERTISE_SLCT);
4146 tg3_writephy(tp, MII_ADVERTISE, adv);
4147 tg3_writephy(tp, MII_BMCR, bmcr |
4148 BMCR_ANRESTART |
4149 BMCR_ANENABLE);
4150 udelay(10);
4151 netif_carrier_off(tp->dev);
4152 }
4153 tg3_writephy(tp, MII_BMCR, new_bmcr);
4154 bmcr = new_bmcr;
4155 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4156 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4157 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4158 ASIC_REV_5714) {
4159 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4160 bmsr |= BMSR_LSTATUS;
4161 else
4162 bmsr &= ~BMSR_LSTATUS;
4163 }
747e8f8b
MC		 4164 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4165 }
4166 }
4167
4168 if (bmsr & BMSR_LSTATUS) {
4169 current_speed = SPEED_1000;
4170 current_link_up = 1;
4171 if (bmcr & BMCR_FULLDPLX)
4172 current_duplex = DUPLEX_FULL;
4173 else
4174 current_duplex = DUPLEX_HALF;
4175
ef167e27
MC		 4176 local_adv = 0;
4177 remote_adv = 0;
4178
747e8f8b 4179 if (bmcr & BMCR_ANENABLE) {
ef167e27 4180 u32 common;
747e8f8b
MC		 4181
4182 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4183 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4184 common = local_adv & remote_adv;
4185 if (common & (ADVERTISE_1000XHALF |
4186 ADVERTISE_1000XFULL)) {
4187 if (common & ADVERTISE_1000XFULL)
4188 current_duplex = DUPLEX_FULL;
4189 else
4190 current_duplex = DUPLEX_HALF;
859a5887 4191 } else {
747e8f8b 4192 current_link_up = 0;
859a5887 4193 }
747e8f8b
MC		 4194 }
4195 }
4196
ef167e27
MC		 4197 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4198 tg3_setup_flow_control(tp, local_adv, remote_adv);
4199
747e8f8b
MC		 4200 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4201 if (tp->link_config.active_duplex == DUPLEX_HALF)
4202 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4203
4204 tw32_f(MAC_MODE, tp->mac_mode);
4205 udelay(40);
4206
4207 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4208
4209 tp->link_config.active_speed = current_speed;
4210 tp->link_config.active_duplex = current_duplex;
4211
4212 if (current_link_up != netif_carrier_ok(tp->dev)) {
4213 if (current_link_up)
4214 netif_carrier_on(tp->dev);
4215 else {
4216 netif_carrier_off(tp->dev);
4217 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4218 }
4219 tg3_link_report(tp);
4220 }
4221 return err;
4222}
4223
4224static void tg3_serdes_parallel_detect(struct tg3 *tp)
4225{
3d3ebe74 4226 if (tp->serdes_counter) {
747e8f8b 4227 /* Give autoneg time to complete. */
3d3ebe74 4228 tp->serdes_counter--;
747e8f8b
MC		 4229 return;
4230 }
c6cdf436 4231
747e8f8b
MC		 4232 if (!netif_carrier_ok(tp->dev) &&
4233 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4234 u32 bmcr;
4235
4236 tg3_readphy(tp, MII_BMCR, &bmcr);
4237 if (bmcr & BMCR_ANENABLE) {
4238 u32 phy1, phy2;
4239
4240 /* Select shadow register 0x1f */
4241 tg3_writephy(tp, 0x1c, 0x7c00);
4242 tg3_readphy(tp, 0x1c, &phy1);
4243
4244 /* Select expansion interrupt status register */
4245 tg3_writephy(tp, 0x17, 0x0f01);
4246 tg3_readphy(tp, 0x15, &phy2);
4247 tg3_readphy(tp, 0x15, &phy2);
4248
4249 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4250 /* We have signal detect and not receiving
4251 * config code words, link is up by parallel
4252 * detection.
4253 */
4254
4255 bmcr &= ~BMCR_ANENABLE;
4256 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4257 tg3_writephy(tp, MII_BMCR, bmcr);
4258 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4259 }
4260 }
859a5887
MC		 4261 } else if (netif_carrier_ok(tp->dev) &&
4262 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4263 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4264 u32 phy2;
4265
4266 /* Select expansion interrupt status register */
4267 tg3_writephy(tp, 0x17, 0x0f01);
4268 tg3_readphy(tp, 0x15, &phy2);
4269 if (phy2 & 0x20) {
4270 u32 bmcr;
4271
4272 /* Config code words received, turn on autoneg. */
4273 tg3_readphy(tp, MII_BMCR, &bmcr);
4274 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4275
4276 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4277
4278 }
4279 }
4280}
4281
1da177e4
LT		 4282static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4283{
4284 int err;
4285
859a5887 4286 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1da177e4 4287 err = tg3_setup_fiber_phy(tp, force_reset);
859a5887 4288 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
747e8f8b 4289 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 4290 else
1da177e4 4291 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 4292
bcb37f6c 4293 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4294 u32 val, scale;
4295
4296 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4297 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4298 scale = 65;
4299 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4300 scale = 6;
4301 else
4302 scale = 12;
4303
4304 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4305 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4306 tw32(GRC_MISC_CFG, val);
4307 }
4308
1da177e4
LT		 4309 if (tp->link_config.active_speed == SPEED_1000 &&
4310 tp->link_config.active_duplex == DUPLEX_HALF)
4311 tw32(MAC_TX_LENGTHS,
4312 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4313 (6 << TX_LENGTHS_IPG_SHIFT) |
4314 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4315 else
4316 tw32(MAC_TX_LENGTHS,
4317 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4318 (6 << TX_LENGTHS_IPG_SHIFT) |
4319 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4320
4321 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4322 if (netif_carrier_ok(tp->dev)) {
4323 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4324 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4325 } else {
4326 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4327 }
4328 }
4329
8ed5d97e
MC		 4330 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4331 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4332 if (!netif_carrier_ok(tp->dev))
4333 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4334 tp->pwrmgmt_thresh;
4335 else
4336 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4337 tw32(PCIE_PWR_MGMT_THRESH, val);
4338 }
4339
1da177e4
LT		 4340 return err;
4341}
4342
df3e6548
MC		 4343/* This is called whenever we suspect that the system chipset is re-
4344 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4345 * is bogus tx completions. We try to recover by setting the
4346 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4347 * in the workqueue.
4348 */
4349static void tg3_tx_recover(struct tg3 *tp)
4350{
4351 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4352 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4353
5129c3a3
MC		 4354 netdev_warn(tp->dev,
4355 "The system may be re-ordering memory-mapped I/O "
4356 "cycles to the network device, attempting to recover. "
4357 "Please report the problem to the driver maintainer "
4358 "and include system chipset information.\n");
df3e6548
MC		 4359
4360 spin_lock(&tp->lock);
df3e6548 4361 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4362 spin_unlock(&tp->lock);
4363}
4364
f3f3f27e 4365static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4366{
4367 smp_mb();
f3f3f27e
MC		 4368 return tnapi->tx_pending -
4369 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4370}
4371
1da177e4
LT		 4372/* Tigon3 never reports partial packet sends. So we do not
4373 * need special logic to handle SKBs that have not had all
4374 * of their frags sent yet, like SunGEM does.
4375 */
17375d25 4376static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4377{
17375d25 4378 struct tg3 *tp = tnapi->tp;
898a56f8 4379 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4380 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4381 struct netdev_queue *txq;
4382 int index = tnapi - tp->napi;
4383
19cfaecc 4384 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4385 index--;
4386
4387 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4388
4389 while (sw_idx != hw_idx) {
f4188d8a 4390 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4391 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4392 int i, tx_bug = 0;
4393
4394 if (unlikely(skb == NULL)) {
4395 tg3_tx_recover(tp);
4396 return;
4397 }
1da177e4 4398
f4188d8a
AD		 4399 pci_unmap_single(tp->pdev,
4400 pci_unmap_addr(ri, mapping),
4401 skb_headlen(skb),
4402 PCI_DMA_TODEVICE);
1da177e4
LT		 4403
4404 ri->skb = NULL;
4405
4406 sw_idx = NEXT_TX(sw_idx);
4407
4408 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4409 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4410 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4411 tx_bug = 1;
f4188d8a
AD		 4412
4413 pci_unmap_page(tp->pdev,
4414 pci_unmap_addr(ri, mapping),
4415 skb_shinfo(skb)->frags[i].size,
4416 PCI_DMA_TODEVICE);
1da177e4
LT		 4417 sw_idx = NEXT_TX(sw_idx);
4418 }
4419
f47c11ee 4420 dev_kfree_skb(skb);
df3e6548
MC		 4421
4422 if (unlikely(tx_bug)) {
4423 tg3_tx_recover(tp);
4424 return;
4425 }
1da177e4
LT		 4426 }
4427
f3f3f27e 4428 tnapi->tx_cons = sw_idx;
1da177e4 4429
1b2a7205
MC		 4430 /* Need to make the tx_cons update visible to tg3_start_xmit()
4431 * before checking for netif_queue_stopped(). Without the
4432 * memory barrier, there is a small possibility that tg3_start_xmit()
4433 * will miss it and cause the queue to be stopped forever.
4434 */
4435 smp_mb();
4436
fe5f5787 4437 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4438 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4439 __netif_tx_lock(txq, smp_processor_id());
4440 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4441 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4442 netif_tx_wake_queue(txq);
4443 __netif_tx_unlock(txq);
51b91468 4444 }
1da177e4
LT		 4445}
4446
2b2cdb65
MC		 4447static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4448{
4449 if (!ri->skb)
4450 return;
4451
4452 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4453 map_sz, PCI_DMA_FROMDEVICE);
4454 dev_kfree_skb_any(ri->skb);
4455 ri->skb = NULL;
4456}
4457
1da177e4
LT		 4458/* Returns size of skb allocated or < 0 on error.
4459 *
4460 * We only need to fill in the address because the other members
4461 * of the RX descriptor are invariant, see tg3_init_rings.
4462 *
4463 * Note the purposeful assymetry of cpu vs. chip accesses. For
4464 * posting buffers we only dirty the first cache line of the RX
4465 * descriptor (containing the address). Whereas for the RX status
4466 * buffers the cpu only reads the last cacheline of the RX descriptor
4467 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4468 */
86b21e59 4469static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4470 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4471{
4472 struct tg3_rx_buffer_desc *desc;
4473 struct ring_info *map, *src_map;
4474 struct sk_buff *skb;
4475 dma_addr_t mapping;
4476 int skb_size, dest_idx;
4477
4478 src_map = NULL;
4479 switch (opaque_key) {
4480 case RXD_OPAQUE_RING_STD:
4481 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4482 desc = &tpr->rx_std[dest_idx];
4483 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4484 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4485 break;
4486
4487 case RXD_OPAQUE_RING_JUMBO:
4488 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4489 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4490 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4491 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4492 break;
4493
4494 default:
4495 return -EINVAL;
855e1111 4496 }
1da177e4
LT		 4497
4498 /* Do not overwrite any of the map or rp information
4499 * until we are sure we can commit to a new buffer.
4500 *
4501 * Callers depend upon this behavior and assume that
4502 * we leave everything unchanged if we fail.
4503 */
287be12e 4504 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4505 if (skb == NULL)
4506 return -ENOMEM;
4507
1da177e4
LT		 4508 skb_reserve(skb, tp->rx_offset);
4509
287be12e 4510 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4511 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4512 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4513 dev_kfree_skb(skb);
4514 return -EIO;
4515 }
1da177e4
LT		 4516
4517 map->skb = skb;
4518 pci_unmap_addr_set(map, mapping, mapping);
4519
1da177e4
LT		 4520 desc->addr_hi = ((u64)mapping >> 32);
4521 desc->addr_lo = ((u64)mapping & 0xffffffff);
4522
4523 return skb_size;
4524}
4525
4526/* We only need to move over in the address because the other
4527 * members of the RX descriptor are invariant. See notes above
4528 * tg3_alloc_rx_skb for full details.
4529 */
a3896167
MC		 4530static void tg3_recycle_rx(struct tg3_napi *tnapi,
4531 struct tg3_rx_prodring_set *dpr,
4532 u32 opaque_key, int src_idx,
4533 u32 dest_idx_unmasked)
1da177e4 4534{
17375d25 4535 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4536 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4537 struct ring_info *src_map, *dest_map;
a3896167 4538 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
c6cdf436 4539 int dest_idx;
1da177e4
LT		 4540
4541 switch (opaque_key) {
4542 case RXD_OPAQUE_RING_STD:
4543 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4544 dest_desc = &dpr->rx_std[dest_idx];
4545 dest_map = &dpr->rx_std_buffers[dest_idx];
4546 src_desc = &spr->rx_std[src_idx];
4547 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4548 break;
4549
4550 case RXD_OPAQUE_RING_JUMBO:
4551 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4552 dest_desc = &dpr->rx_jmb[dest_idx].std;
4553 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4554 src_desc = &spr->rx_jmb[src_idx].std;
4555 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4556 break;
4557
4558 default:
4559 return;
855e1111 4560 }
1da177e4
LT		 4561
4562 dest_map->skb = src_map->skb;
4563 pci_unmap_addr_set(dest_map, mapping,
4564 pci_unmap_addr(src_map, mapping));
4565 dest_desc->addr_hi = src_desc->addr_hi;
4566 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 4567
4568 /* Ensure that the update to the skb happens after the physical
4569 * addresses have been transferred to the new BD location.
4570 */
4571 smp_wmb();
4572
1da177e4
LT		 4573 src_map->skb = NULL;
4574}
4575
1da177e4
LT		 4576/* The RX ring scheme is composed of multiple rings which post fresh
4577 * buffers to the chip, and one special ring the chip uses to report
4578 * status back to the host.
4579 *
4580 * The special ring reports the status of received packets to the
4581 * host. The chip does not write into the original descriptor the
4582 * RX buffer was obtained from. The chip simply takes the original
4583 * descriptor as provided by the host, updates the status and length
4584 * field, then writes this into the next status ring entry.
4585 *
4586 * Each ring the host uses to post buffers to the chip is described
4587 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4588 * it is first placed into the on-chip ram. When the packet's length
4589 * is known, it walks down the TG3_BDINFO entries to select the ring.
4590 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4591 * which is within the range of the new packet's length is chosen.
4592 *
4593 * The "separate ring for rx status" scheme may sound queer, but it makes
4594 * sense from a cache coherency perspective. If only the host writes
4595 * to the buffer post rings, and only the chip writes to the rx status
4596 * rings, then cache lines never move beyond shared-modified state.
4597 * If both the host and chip were to write into the same ring, cache line
4598 * eviction could occur since both entities want it in an exclusive state.
4599 */
17375d25 4600static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4601{
17375d25 4602 struct tg3 *tp = tnapi->tp;
f92905de 4603 u32 work_mask, rx_std_posted = 0;
4361935a 4604 u32 std_prod_idx, jmb_prod_idx;
72334482 4605 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4606 u16 hw_idx;
1da177e4 4607 int received;
b196c7e4 4608 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4609
8d9d7cfc 4610 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4611 /*
4612 * We need to order the read of hw_idx and the read of
4613 * the opaque cookie.
4614 */
4615 rmb();
1da177e4
LT		 4616 work_mask = 0;
4617 received = 0;
4361935a
MC		 4618 std_prod_idx = tpr->rx_std_prod_idx;
4619 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4620 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4621 struct ring_info *ri;
72334482 4622 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4623 unsigned int len;
4624 struct sk_buff *skb;
4625 dma_addr_t dma_addr;
4626 u32 opaque_key, desc_idx, *post_ptr;
4627
4628 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4629 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4630 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4631 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4632 dma_addr = pci_unmap_addr(ri, mapping);
4633 skb = ri->skb;
4361935a 4634 post_ptr = &std_prod_idx;
f92905de 4635 rx_std_posted++;
1da177e4 4636 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4637 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4638 dma_addr = pci_unmap_addr(ri, mapping);
4639 skb = ri->skb;
4361935a 4640 post_ptr = &jmb_prod_idx;
21f581a5 4641 } else
1da177e4 4642 goto next_pkt_nopost;
1da177e4
LT		 4643
4644 work_mask |= opaque_key;
4645
4646 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4647 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4648 drop_it:
a3896167 4649 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4650 desc_idx, *post_ptr);
4651 drop_it_no_recycle:
4652 /* Other statistics kept track of by card. */
4653 tp->net_stats.rx_dropped++;
4654 goto next_pkt;
4655 }
4656
ad829268
MC		 4657 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4658 ETH_FCS_LEN;
1da177e4 4659
d2757fc4 4660 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4
LT		 4661 int skb_size;
4662
86b21e59 4663 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4664 *post_ptr);
1da177e4
LT		 4665 if (skb_size < 0)
4666 goto drop_it;
4667
287be12e 4668 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4669 PCI_DMA_FROMDEVICE);
4670
61e800cf
MC		 4671 /* Ensure that the update to the skb happens
4672 * after the usage of the old DMA mapping.
4673 */
4674 smp_wmb();
4675
4676 ri->skb = NULL;
4677
1da177e4
LT		 4678 skb_put(skb, len);
4679 } else {
4680 struct sk_buff *copy_skb;
4681
a3896167 4682 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4683 desc_idx, *post_ptr);
4684
ad829268
MC		 4685 copy_skb = netdev_alloc_skb(tp->dev,
4686 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4687 if (copy_skb == NULL)
4688 goto drop_it_no_recycle;
4689
ad829268 4690 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4691 skb_put(copy_skb, len);
4692 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4693 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4694 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4695
4696 /* We'll reuse the original ring buffer. */
4697 skb = copy_skb;
4698 }
4699
4700 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4701 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4702 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4703 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4704 skb->ip_summed = CHECKSUM_UNNECESSARY;
4705 else
4706 skb->ip_summed = CHECKSUM_NONE;
4707
4708 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4709
4710 if (len > (tp->dev->mtu + ETH_HLEN) &&
4711 skb->protocol != htons(ETH_P_8021Q)) {
4712 dev_kfree_skb(skb);
4713 goto next_pkt;
4714 }
4715
1da177e4
LT		 4716#if TG3_VLAN_TAG_USED
4717 if (tp->vlgrp != NULL &&
4718 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4719 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4720 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4721 } else
4722#endif
17375d25 4723 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4724
1da177e4
LT		 4725 received++;
4726 budget--;
4727
4728next_pkt:
4729 (*post_ptr)++;
f92905de
MC		 4730
4731 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4732 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4733 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4734 tpr->rx_std_prod_idx);
f92905de
MC		 4735 work_mask &= ~RXD_OPAQUE_RING_STD;
4736 rx_std_posted = 0;
4737 }
1da177e4 4738next_pkt_nopost:
483ba50b 4739 sw_idx++;
6b31a515 4740 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4741
4742 /* Refresh hw_idx to see if there is new work */
4743 if (sw_idx == hw_idx) {
8d9d7cfc 4744 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4745 rmb();
4746 }
1da177e4
LT		 4747 }
4748
4749 /* ACK the status ring. */
72334482
MC		 4750 tnapi->rx_rcb_ptr = sw_idx;
4751 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4752
4753 /* Refill RX ring(s). */
e4af1af9 4754 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
b196c7e4
MC		 4755 if (work_mask & RXD_OPAQUE_RING_STD) {
4756 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4757 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4758 tpr->rx_std_prod_idx);
4759 }
4760 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4761 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4762 TG3_RX_JUMBO_RING_SIZE;
4763 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4764 tpr->rx_jmb_prod_idx);
4765 }
4766 mmiowb();
4767 } else if (work_mask) {
4768 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4769 * updated before the producer indices can be updated.
4770 */
4771 smp_wmb();
4772
4361935a 4773 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4774 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4 4775
e4af1af9
MC		 4776 if (tnapi != &tp->napi[1])
4777 napi_schedule(&tp->napi[1].napi);
1da177e4 4778 }
1da177e4
LT		 4779
4780 return received;
4781}
4782
35f2d7d0 4783static void tg3_poll_link(struct tg3 *tp)
1da177e4 4784{
1da177e4
LT		 4785 /* handle link change and other phy events */
4786 if (!(tp->tg3_flags &
4787 (TG3_FLAG_USE_LINKCHG_REG |
4788 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4789 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4790
1da177e4
LT		 4791 if (sblk->status & SD_STATUS_LINK_CHG) {
4792 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4793 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4794 spin_lock(&tp->lock);
dd477003
MC		 4795 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4796 tw32_f(MAC_STATUS,
4797 (MAC_STATUS_SYNC_CHANGED |
4798 MAC_STATUS_CFG_CHANGED |
4799 MAC_STATUS_MI_COMPLETION |
4800 MAC_STATUS_LNKSTATE_CHANGED));
4801 udelay(40);
4802 } else
4803 tg3_setup_phy(tp, 0);
f47c11ee 4804 spin_unlock(&tp->lock);
1da177e4
LT		 4805 }
4806 }
35f2d7d0
MC		 4807}
4808
f89f38b8
MC		 4809static int tg3_rx_prodring_xfer(struct tg3 *tp,
4810 struct tg3_rx_prodring_set *dpr,
4811 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 4812{
4813 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 4814 int i, err = 0;
b196c7e4
MC		 4815
4816 while (1) {
4817 src_prod_idx = spr->rx_std_prod_idx;
4818
4819 /* Make sure updates to the rx_std_buffers[] entries and the
4820 * standard producer index are seen in the correct order.
4821 */
4822 smp_rmb();
4823
4824 if (spr->rx_std_cons_idx == src_prod_idx)
4825 break;
4826
4827 if (spr->rx_std_cons_idx < src_prod_idx)
4828 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4829 else
4830 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4831
4832 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4833
4834 si = spr->rx_std_cons_idx;
4835 di = dpr->rx_std_prod_idx;
4836
e92967bf
MC		 4837 for (i = di; i < di + cpycnt; i++) {
4838 if (dpr->rx_std_buffers[i].skb) {
4839 cpycnt = i - di;
f89f38b8 4840 err = -ENOSPC;
e92967bf
MC		 4841 break;
4842 }
4843 }
4844
4845 if (!cpycnt)
4846 break;
4847
4848 /* Ensure that updates to the rx_std_buffers ring and the
4849 * shadowed hardware producer ring from tg3_recycle_skb() are
4850 * ordered correctly WRT the skb check above.
4851 */
4852 smp_rmb();
4853
b196c7e4
MC		 4854 memcpy(&dpr->rx_std_buffers[di],
4855 &spr->rx_std_buffers[si],
4856 cpycnt * sizeof(struct ring_info));
4857
4858 for (i = 0; i < cpycnt; i++, di++, si++) {
4859 struct tg3_rx_buffer_desc *sbd, *dbd;
4860 sbd = &spr->rx_std[si];
4861 dbd = &dpr->rx_std[di];
4862 dbd->addr_hi = sbd->addr_hi;
4863 dbd->addr_lo = sbd->addr_lo;
4864 }
4865
4866 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4867 TG3_RX_RING_SIZE;
4868 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4869 TG3_RX_RING_SIZE;
4870 }
4871
4872 while (1) {
4873 src_prod_idx = spr->rx_jmb_prod_idx;
4874
4875 /* Make sure updates to the rx_jmb_buffers[] entries and
4876 * the jumbo producer index are seen in the correct order.
4877 */
4878 smp_rmb();
4879
4880 if (spr->rx_jmb_cons_idx == src_prod_idx)
4881 break;
4882
4883 if (spr->rx_jmb_cons_idx < src_prod_idx)
4884 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4885 else
4886 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4887
4888 cpycnt = min(cpycnt,
4889 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4890
4891 si = spr->rx_jmb_cons_idx;
4892 di = dpr->rx_jmb_prod_idx;
4893
e92967bf
MC		 4894 for (i = di; i < di + cpycnt; i++) {
4895 if (dpr->rx_jmb_buffers[i].skb) {
4896 cpycnt = i - di;
f89f38b8 4897 err = -ENOSPC;
e92967bf
MC		 4898 break;
4899 }
4900 }
4901
4902 if (!cpycnt)
4903 break;
4904
4905 /* Ensure that updates to the rx_jmb_buffers ring and the
4906 * shadowed hardware producer ring from tg3_recycle_skb() are
4907 * ordered correctly WRT the skb check above.
4908 */
4909 smp_rmb();
4910
b196c7e4
MC		 4911 memcpy(&dpr->rx_jmb_buffers[di],
4912 &spr->rx_jmb_buffers[si],
4913 cpycnt * sizeof(struct ring_info));
4914
4915 for (i = 0; i < cpycnt; i++, di++, si++) {
4916 struct tg3_rx_buffer_desc *sbd, *dbd;
4917 sbd = &spr->rx_jmb[si].std;
4918 dbd = &dpr->rx_jmb[di].std;
4919 dbd->addr_hi = sbd->addr_hi;
4920 dbd->addr_lo = sbd->addr_lo;
4921 }
4922
4923 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4924 TG3_RX_JUMBO_RING_SIZE;
4925 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4926 TG3_RX_JUMBO_RING_SIZE;
4927 }
f89f38b8
MC		 4928
4929 return err;
b196c7e4
MC		 4930}
4931
35f2d7d0
MC		 4932static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4933{
4934 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4935
4936 /* run TX completion thread */
f3f3f27e 4937 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4938 tg3_tx(tnapi);
6f535763 4939 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4940 return work_done;
1da177e4
LT		 4941 }
4942
1da177e4
LT		 4943 /* run RX thread, within the bounds set by NAPI.
4944 * All RX "locking" is done by ensuring outside
bea3348e 4945 * code synchronizes with tg3->napi.poll()
1da177e4 4946 */
8d9d7cfc 4947 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4948 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4949
b196c7e4 4950 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
e4af1af9 4951 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
f89f38b8 4952 int i, err = 0;
e4af1af9
MC		 4953 u32 std_prod_idx = dpr->rx_std_prod_idx;
4954 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 4955
e4af1af9 4956 for (i = 1; i < tp->irq_cnt; i++)
f89f38b8
MC		 4957 err |= tg3_rx_prodring_xfer(tp, dpr,
4958 tp->napi[i].prodring);
b196c7e4
MC		 4959
4960 wmb();
4961
e4af1af9
MC		 4962 if (std_prod_idx != dpr->rx_std_prod_idx)
4963 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4964 dpr->rx_std_prod_idx);
b196c7e4 4965
e4af1af9
MC		 4966 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4967 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4968 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 4969
4970 mmiowb();
f89f38b8
MC		 4971
4972 if (err)
4973 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 4974 }
4975
6f535763
DM		 4976 return work_done;
4977}
4978
35f2d7d0
MC		 4979static int tg3_poll_msix(struct napi_struct *napi, int budget)
4980{
4981 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4982 struct tg3 *tp = tnapi->tp;
4983 int work_done = 0;
4984 struct tg3_hw_status *sblk = tnapi->hw_status;
4985
4986 while (1) {
4987 work_done = tg3_poll_work(tnapi, work_done, budget);
4988
4989 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4990 goto tx_recovery;
4991
4992 if (unlikely(work_done >= budget))
4993 break;
4994
c6cdf436 4995 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 4996 * to tell the hw how much work has been processed,
4997 * so we must read it before checking for more work.
4998 */
4999 tnapi->last_tag = sblk->status_tag;
5000 tnapi->last_irq_tag = tnapi->last_tag;
5001 rmb();
5002
5003 /* check for RX/TX work to do */
6d40db7b
MC		 5004 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5005 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
35f2d7d0
MC		 5006 napi_complete(napi);
5007 /* Reenable interrupts. */
5008 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5009 mmiowb();
5010 break;
5011 }
5012 }
5013
5014 return work_done;
5015
5016tx_recovery:
5017 /* work_done is guaranteed to be less than budget. */
5018 napi_complete(napi);
5019 schedule_work(&tp->reset_task);
5020 return work_done;
5021}
5022
6f535763
DM		 5023static int tg3_poll(struct napi_struct *napi, int budget)
5024{
8ef0442f
MC		 5025 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5026 struct tg3 *tp = tnapi->tp;
6f535763 5027 int work_done = 0;
898a56f8 5028 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 5029
5030 while (1) {
35f2d7d0
MC		 5031 tg3_poll_link(tp);
5032
17375d25 5033 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 5034
5035 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5036 goto tx_recovery;
5037
5038 if (unlikely(work_done >= budget))
5039 break;
5040
4fd7ab59 5041 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 5042 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 5043 * to tell the hw how much work has been processed,
5044 * so we must read it before checking for more work.
5045 */
898a56f8
MC		 5046 tnapi->last_tag = sblk->status_tag;
5047 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 5048 rmb();
5049 } else
5050 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 5051
17375d25 5052 if (likely(!tg3_has_work(tnapi))) {
288379f0 5053 napi_complete(napi);
17375d25 5054 tg3_int_reenable(tnapi);
6f535763
DM		 5055 break;
5056 }
1da177e4
LT		 5057 }
5058
bea3348e 5059 return work_done;
6f535763
DM		 5060
5061tx_recovery:
4fd7ab59 5062 /* work_done is guaranteed to be less than budget. */
288379f0 5063 napi_complete(napi);
6f535763 5064 schedule_work(&tp->reset_task);
4fd7ab59 5065 return work_done;
1da177e4
LT		 5066}
5067
f47c11ee
DM		 5068static void tg3_irq_quiesce(struct tg3 *tp)
5069{
4f125f42
MC		 5070 int i;
5071
f47c11ee
DM		 5072 BUG_ON(tp->irq_sync);
5073
5074 tp->irq_sync = 1;
5075 smp_mb();
5076
4f125f42
MC		 5077 for (i = 0; i < tp->irq_cnt; i++)
5078 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5079}
5080
5081static inline int tg3_irq_sync(struct tg3 *tp)
5082{
5083 return tp->irq_sync;
5084}
5085
5086/* Fully shutdown all tg3 driver activity elsewhere in the system.
5087 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5088 * with as well. Most of the time, this is not necessary except when
5089 * shutting down the device.
5090 */
5091static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5092{
46966545 5093 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5094 if (irq_sync)
5095 tg3_irq_quiesce(tp);
f47c11ee
DM		 5096}
5097
5098static inline void tg3_full_unlock(struct tg3 *tp)
5099{
f47c11ee
DM		 5100 spin_unlock_bh(&tp->lock);
5101}
5102
fcfa0a32
MC		 5103/* One-shot MSI handler - Chip automatically disables interrupt
5104 * after sending MSI so driver doesn't have to do it.
5105 */
7d12e780 5106static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5107{
09943a18
MC		 5108 struct tg3_napi *tnapi = dev_id;
5109 struct tg3 *tp = tnapi->tp;
fcfa0a32 5110
898a56f8 5111 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5112 if (tnapi->rx_rcb)
5113 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5114
5115 if (likely(!tg3_irq_sync(tp)))
09943a18 5116 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5117
5118 return IRQ_HANDLED;
5119}
5120
88b06bc2
MC		 5121/* MSI ISR - No need to check for interrupt sharing and no need to
5122 * flush status block and interrupt mailbox. PCI ordering rules
5123 * guarantee that MSI will arrive after the status block.
5124 */
7d12e780 5125static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5126{
09943a18
MC		 5127 struct tg3_napi *tnapi = dev_id;
5128 struct tg3 *tp = tnapi->tp;
88b06bc2 5129
898a56f8 5130 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5131 if (tnapi->rx_rcb)
5132 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5133 /*
fac9b83e 5134 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5135 * chip-internal interrupt pending events.
fac9b83e 5136 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5137 * NIC to stop sending us irqs, engaging "in-intr-handler"
5138 * event coalescing.
5139 */
5140 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5141 if (likely(!tg3_irq_sync(tp)))
09943a18 5142 napi_schedule(&tnapi->napi);
61487480 5143
88b06bc2
MC		 5144 return IRQ_RETVAL(1);
5145}
5146
7d12e780 5147static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5148{
09943a18
MC		 5149 struct tg3_napi *tnapi = dev_id;
5150 struct tg3 *tp = tnapi->tp;
898a56f8 5151 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5152 unsigned int handled = 1;
5153
1da177e4
LT		 5154 /* In INTx mode, it is possible for the interrupt to arrive at
5155 * the CPU before the status block posted prior to the interrupt.
5156 * Reading the PCI State register will confirm whether the
5157 * interrupt is ours and will flush the status block.
5158 */
d18edcb2
MC		 5159 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5160 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5161 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5162 handled = 0;
f47c11ee 5163 goto out;
fac9b83e 5164 }
d18edcb2
MC		 5165 }
5166
5167 /*
5168 * Writing any value to intr-mbox-0 clears PCI INTA# and
5169 * chip-internal interrupt pending events.
5170 * Writing non-zero to intr-mbox-0 additional tells the
5171 * NIC to stop sending us irqs, engaging "in-intr-handler"
5172 * event coalescing.
c04cb347
MC		 5173 *
5174 * Flush the mailbox to de-assert the IRQ immediately to prevent
5175 * spurious interrupts. The flush impacts performance but
5176 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5177 */
c04cb347 5178 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5179 if (tg3_irq_sync(tp))
5180 goto out;
5181 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5182 if (likely(tg3_has_work(tnapi))) {
72334482 5183 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5184 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5185 } else {
5186 /* No work, shared interrupt perhaps? re-enable
5187 * interrupts, and flush that PCI write
5188 */
5189 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5190 0x00000000);
fac9b83e 5191 }
f47c11ee 5192out:
fac9b83e
DM		 5193 return IRQ_RETVAL(handled);
5194}
5195
7d12e780 5196static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5197{
09943a18
MC		 5198 struct tg3_napi *tnapi = dev_id;
5199 struct tg3 *tp = tnapi->tp;
898a56f8 5200 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5201 unsigned int handled = 1;
5202
fac9b83e
DM		 5203 /* In INTx mode, it is possible for the interrupt to arrive at
5204 * the CPU before the status block posted prior to the interrupt.
5205 * Reading the PCI State register will confirm whether the
5206 * interrupt is ours and will flush the status block.
5207 */
898a56f8 5208 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5209 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5210 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5211 handled = 0;
f47c11ee 5212 goto out;
1da177e4 5213 }
d18edcb2
MC		 5214 }
5215
5216 /*
5217 * writing any value to intr-mbox-0 clears PCI INTA# and
5218 * chip-internal interrupt pending events.
5219 * writing non-zero to intr-mbox-0 additional tells the
5220 * NIC to stop sending us irqs, engaging "in-intr-handler"
5221 * event coalescing.
c04cb347
MC		 5222 *
5223 * Flush the mailbox to de-assert the IRQ immediately to prevent
5224 * spurious interrupts. The flush impacts performance but
5225 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5226 */
c04cb347 5227 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5228
5229 /*
5230 * In a shared interrupt configuration, sometimes other devices'
5231 * interrupts will scream. We record the current status tag here
5232 * so that the above check can report that the screaming interrupts
5233 * are unhandled. Eventually they will be silenced.
5234 */
898a56f8 5235 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5236
d18edcb2
MC		 5237 if (tg3_irq_sync(tp))
5238 goto out;
624f8e50 5239
72334482 5240 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5241
09943a18 5242 napi_schedule(&tnapi->napi);
624f8e50 5243
f47c11ee 5244out:
1da177e4
LT		 5245 return IRQ_RETVAL(handled);
5246}
5247
7938109f 5248/* ISR for interrupt test */
7d12e780 5249static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5250{
09943a18
MC		 5251 struct tg3_napi *tnapi = dev_id;
5252 struct tg3 *tp = tnapi->tp;
898a56f8 5253 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5254
f9804ddb
MC		 5255 if ((sblk->status & SD_STATUS_UPDATED) ||
5256 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5257 tg3_disable_ints(tp);
7938109f
MC		 5258 return IRQ_RETVAL(1);
5259 }
5260 return IRQ_RETVAL(0);
5261}
5262
8e7a22e3 5263static int tg3_init_hw(struct tg3 *, int);
944d980e 5264static int tg3_halt(struct tg3 *, int, int);
1da177e4 5265
b9ec6c1b
MC		 5266/* Restart hardware after configuration changes, self-test, etc.
5267 * Invoked with tp->lock held.
5268 */
5269static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5270 __releases(tp->lock)
5271 __acquires(tp->lock)
b9ec6c1b
MC		 5272{
5273 int err;
5274
5275 err = tg3_init_hw(tp, reset_phy);
5276 if (err) {
5129c3a3
MC		 5277 netdev_err(tp->dev,
5278 "Failed to re-initialize device, aborting\n");
b9ec6c1b
MC		 5279 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5280 tg3_full_unlock(tp);
5281 del_timer_sync(&tp->timer);
5282 tp->irq_sync = 0;
fed97810 5283 tg3_napi_enable(tp);
b9ec6c1b
MC		 5284 dev_close(tp->dev);
5285 tg3_full_lock(tp, 0);
5286 }
5287 return err;
5288}
5289
1da177e4
LT		 5290#ifdef CONFIG_NET_POLL_CONTROLLER
5291static void tg3_poll_controller(struct net_device *dev)
5292{
4f125f42 5293 int i;
88b06bc2
MC		 5294 struct tg3 *tp = netdev_priv(dev);
5295
4f125f42 5296 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 5297 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 5298}
5299#endif
5300
c4028958 5301static void tg3_reset_task(struct work_struct *work)
1da177e4 5302{
c4028958 5303 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5304 int err;
1da177e4
LT		 5305 unsigned int restart_timer;
5306
7faa006f 5307 tg3_full_lock(tp, 0);
7faa006f
MC		 5308
5309 if (!netif_running(tp->dev)) {
7faa006f
MC		 5310 tg3_full_unlock(tp);
5311 return;
5312 }
5313
5314 tg3_full_unlock(tp);
5315
b02fd9e3
MC		 5316 tg3_phy_stop(tp);
5317
1da177e4
LT		 5318 tg3_netif_stop(tp);
5319
f47c11ee 5320 tg3_full_lock(tp, 1);
1da177e4
LT		 5321
5322 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5323 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5324
df3e6548
MC		 5325 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5326 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5327 tp->write32_rx_mbox = tg3_write_flush_reg32;
5328 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5329 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5330 }
5331
944d980e 5332 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5333 err = tg3_init_hw(tp, 1);
5334 if (err)
b9ec6c1b 5335 goto out;
1da177e4
LT		 5336
5337 tg3_netif_start(tp);
5338
1da177e4
LT		 5339 if (restart_timer)
5340 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5341
b9ec6c1b 5342out:
7faa006f 5343 tg3_full_unlock(tp);
b02fd9e3
MC		 5344
5345 if (!err)
5346 tg3_phy_start(tp);
1da177e4
LT		 5347}
5348
b0408751
MC		 5349static void tg3_dump_short_state(struct tg3 *tp)
5350{
05dbe005
JP		 5351 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5352 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5353 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5354 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
b0408751
MC		 5355}
5356
1da177e4
LT		 5357static void tg3_tx_timeout(struct net_device *dev)
5358{
5359 struct tg3 *tp = netdev_priv(dev);
5360
b0408751 5361 if (netif_msg_tx_err(tp)) {
05dbe005 5362 netdev_err(dev, "transmit timed out, resetting\n");
b0408751
MC		 5363 tg3_dump_short_state(tp);
5364 }
1da177e4
LT		 5365
5366 schedule_work(&tp->reset_task);
5367}
5368
c58ec932
MC		 5369/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5370static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5371{
5372 u32 base = (u32) mapping & 0xffffffff;
5373
5374 return ((base > 0xffffdcc0) &&
5375 (base + len + 8 < base));
5376}
5377
72f2afb8
MC		 5378/* Test for DMA addresses > 40-bit */
5379static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5380 int len)
5381{
5382#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5383 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5384 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5385 return 0;
5386#else
5387 return 0;
5388#endif
5389}
5390
f3f3f27e 5391static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5392
72f2afb8 5393/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5394static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5395 struct sk_buff *skb, u32 last_plus_one,
5396 u32 *start, u32 base_flags, u32 mss)
1da177e4 5397{
24f4efd4 5398 struct tg3 *tp = tnapi->tp;
41588ba1 5399 struct sk_buff *new_skb;
c58ec932 5400 dma_addr_t new_addr = 0;
1da177e4 5401 u32 entry = *start;
c58ec932 5402 int i, ret = 0;
1da177e4 5403
41588ba1
MC		 5404 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5405 new_skb = skb_copy(skb, GFP_ATOMIC);
5406 else {
5407 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5408
5409 new_skb = skb_copy_expand(skb,
5410 skb_headroom(skb) + more_headroom,
5411 skb_tailroom(skb), GFP_ATOMIC);
5412 }
5413
1da177e4 5414 if (!new_skb) {
c58ec932
MC		 5415 ret = -1;
5416 } else {
5417 /* New SKB is guaranteed to be linear. */
5418 entry = *start;
f4188d8a
AD		 5419 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5420 PCI_DMA_TODEVICE);
5421 /* Make sure the mapping succeeded */
5422 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5423 ret = -1;
5424 dev_kfree_skb(new_skb);
5425 new_skb = NULL;
90079ce8 5426
c58ec932
MC		 5427 /* Make sure new skb does not cross any 4G boundaries.
5428 * Drop the packet if it does.
5429 */
f4188d8a
AD		 5430 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5431 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5432 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5433 PCI_DMA_TODEVICE);
c58ec932
MC		 5434 ret = -1;
5435 dev_kfree_skb(new_skb);
5436 new_skb = NULL;
5437 } else {
f3f3f27e 5438 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5439 base_flags, 1 | (mss << 1));
5440 *start = NEXT_TX(entry);
5441 }
1da177e4
LT		 5442 }
5443
1da177e4
LT		 5444 /* Now clean up the sw ring entries. */
5445 i = 0;
5446 while (entry != last_plus_one) {
f4188d8a
AD		 5447 int len;
5448
f3f3f27e 5449 if (i == 0)
f4188d8a 5450 len = skb_headlen(skb);
f3f3f27e 5451 else
f4188d8a
AD		 5452 len = skb_shinfo(skb)->frags[i-1].size;
5453
5454 pci_unmap_single(tp->pdev,
5455 pci_unmap_addr(&tnapi->tx_buffers[entry],
5456 mapping),
5457 len, PCI_DMA_TODEVICE);
5458 if (i == 0) {
5459 tnapi->tx_buffers[entry].skb = new_skb;
5460 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5461 new_addr);
5462 } else {
f3f3f27e 5463 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5464 }
1da177e4
LT		 5465 entry = NEXT_TX(entry);
5466 i++;
5467 }
5468
5469 dev_kfree_skb(skb);
5470
c58ec932 5471 return ret;
1da177e4
LT		 5472}
5473
f3f3f27e 5474static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5475 dma_addr_t mapping, int len, u32 flags,
5476 u32 mss_and_is_end)
5477{
f3f3f27e 5478 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5479 int is_end = (mss_and_is_end & 0x1);
5480 u32 mss = (mss_and_is_end >> 1);
5481 u32 vlan_tag = 0;
5482
5483 if (is_end)
5484 flags |= TXD_FLAG_END;
5485 if (flags & TXD_FLAG_VLAN) {
5486 vlan_tag = flags >> 16;
5487 flags &= 0xffff;
5488 }
5489 vlan_tag |= (mss << TXD_MSS_SHIFT);
5490
5491 txd->addr_hi = ((u64) mapping >> 32);
5492 txd->addr_lo = ((u64) mapping & 0xffffffff);
5493 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5494 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5495}
5496
5a6f3074 5497/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5498 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5499 */
61357325
SH		 5500static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5501 struct net_device *dev)
5a6f3074
MC		 5502{
5503 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5504 u32 len, entry, base_flags, mss;
90079ce8 5505 dma_addr_t mapping;
fe5f5787
MC		 5506 struct tg3_napi *tnapi;
5507 struct netdev_queue *txq;
f4188d8a
AD		 5508 unsigned int i, last;
5509
fe5f5787
MC		 5510 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5511 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5512 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5513 tnapi++;
5a6f3074 5514
00b70504 5515 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5516 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5517 * interrupt. Furthermore, IRQ processing runs lockless so we have
5518 * no IRQ context deadlocks to worry about either. Rejoice!
5519 */
f3f3f27e 5520 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5521 if (!netif_tx_queue_stopped(txq)) {
5522 netif_tx_stop_queue(txq);
5a6f3074
MC		 5523
5524 /* This is a hard error, log it. */
5129c3a3
MC		 5525 netdev_err(dev,
5526 "BUG! Tx Ring full when queue awake!\n");
5a6f3074 5527 }
5a6f3074
MC		 5528 return NETDEV_TX_BUSY;
5529 }
5530
f3f3f27e 5531 entry = tnapi->tx_prod;
5a6f3074 5532 base_flags = 0;
5a6f3074 5533 mss = 0;
c13e3713 5534 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5535 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5536 u32 hdrlen;
5a6f3074
MC		 5537
5538 if (skb_header_cloned(skb) &&
5539 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5540 dev_kfree_skb(skb);
5541 goto out_unlock;
5542 }
5543
b0026624 5544 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5545 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5546 else {
eddc9ec5
ACM		 5547 struct iphdr *iph = ip_hdr(skb);
5548
ab6a5bb6 5549 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5550 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5551
eddc9ec5
ACM		 5552 iph->check = 0;
5553 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5554 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5555 }
5a6f3074 5556
e849cdc3 5557 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5558 mss |= (hdrlen & 0xc) << 12;
5559 if (hdrlen & 0x10)
5560 base_flags |= 0x00000010;
5561 base_flags |= (hdrlen & 0x3e0) << 5;
5562 } else
5563 mss |= hdrlen << 9;
5564
5a6f3074
MC		 5565 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5566 TXD_FLAG_CPU_POST_DMA);
5567
aa8223c7 5568 tcp_hdr(skb)->check = 0;
5a6f3074 5569
859a5887 5570 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5a6f3074 5571 base_flags |= TXD_FLAG_TCPUDP_CSUM;
859a5887
MC		 5572 }
5573
5a6f3074
MC		 5574#if TG3_VLAN_TAG_USED
5575 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5576 base_flags |= (TXD_FLAG_VLAN |
5577 (vlan_tx_tag_get(skb) << 16));
5578#endif
5579
f4188d8a
AD		 5580 len = skb_headlen(skb);
5581
5582 /* Queue skb data, a.k.a. the main skb fragment. */
5583 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5584 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5585 dev_kfree_skb(skb);
5586 goto out_unlock;
5587 }
5588
f3f3f27e 5589 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5590 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5591
b703df6f 5592 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5593 !mss && skb->len > ETH_DATA_LEN)
5594 base_flags |= TXD_FLAG_JMB_PKT;
5595
f3f3f27e 5596 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5597 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5598
5599 entry = NEXT_TX(entry);
5600
5601 /* Now loop through additional data fragments, and queue them. */
5602 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5603 last = skb_shinfo(skb)->nr_frags - 1;
5604 for (i = 0; i <= last; i++) {
5605 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5606
5607 len = frag->size;
f4188d8a
AD		 5608 mapping = pci_map_page(tp->pdev,
5609 frag->page,
5610 frag->page_offset,
5611 len, PCI_DMA_TODEVICE);
5612 if (pci_dma_mapping_error(tp->pdev, mapping))
5613 goto dma_error;
5614
f3f3f27e 5615 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5616 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5617 mapping);
5a6f3074 5618
f3f3f27e 5619 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5620 base_flags, (i == last) | (mss << 1));
5621
5622 entry = NEXT_TX(entry);
5623 }
5624 }
5625
5626 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5627 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5628
f3f3f27e
MC		 5629 tnapi->tx_prod = entry;
5630 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5631 netif_tx_stop_queue(txq);
f3f3f27e 5632 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5633 netif_tx_wake_queue(txq);
5a6f3074
MC		 5634 }
5635
5636out_unlock:
cdd0db05 5637 mmiowb();
5a6f3074
MC		 5638
5639 return NETDEV_TX_OK;
f4188d8a
AD		 5640
5641dma_error:
5642 last = i;
5643 entry = tnapi->tx_prod;
5644 tnapi->tx_buffers[entry].skb = NULL;
5645 pci_unmap_single(tp->pdev,
5646 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5647 skb_headlen(skb),
5648 PCI_DMA_TODEVICE);
5649 for (i = 0; i <= last; i++) {
5650 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5651 entry = NEXT_TX(entry);
5652
5653 pci_unmap_page(tp->pdev,
5654 pci_unmap_addr(&tnapi->tx_buffers[entry],
5655 mapping),
5656 frag->size, PCI_DMA_TODEVICE);
5657 }
5658
5659 dev_kfree_skb(skb);
5660 return NETDEV_TX_OK;
5a6f3074
MC		 5661}
5662
61357325
SH		 5663static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5664 struct net_device *);
52c0fd83
MC		 5665
5666/* Use GSO to workaround a rare TSO bug that may be triggered when the
5667 * TSO header is greater than 80 bytes.
5668 */
5669static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5670{
5671 struct sk_buff *segs, *nskb;
f3f3f27e 5672 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5673
5674 /* Estimate the number of fragments in the worst case */
f3f3f27e 5675 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5676 netif_stop_queue(tp->dev);
f3f3f27e 5677 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5678 return NETDEV_TX_BUSY;
5679
5680 netif_wake_queue(tp->dev);
52c0fd83
MC		 5681 }
5682
5683 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5684 if (IS_ERR(segs))
52c0fd83
MC		 5685 goto tg3_tso_bug_end;
5686
5687 do {
5688 nskb = segs;
5689 segs = segs->next;
5690 nskb->next = NULL;
5691 tg3_start_xmit_dma_bug(nskb, tp->dev);
5692 } while (segs);
5693
5694tg3_tso_bug_end:
5695 dev_kfree_skb(skb);
5696
5697 return NETDEV_TX_OK;
5698}
52c0fd83 5699
5a6f3074
MC		 5700/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5701 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5702 */
61357325
SH		 5703static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5704 struct net_device *dev)
1da177e4
LT		 5705{
5706 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5707 u32 len, entry, base_flags, mss;
5708 int would_hit_hwbug;
90079ce8 5709 dma_addr_t mapping;
24f4efd4
MC		 5710 struct tg3_napi *tnapi;
5711 struct netdev_queue *txq;
f4188d8a
AD		 5712 unsigned int i, last;
5713
24f4efd4
MC		 5714 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5715 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5716 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5717 tnapi++;
1da177e4 5718
00b70504 5719 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5720 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5721 * interrupt. Furthermore, IRQ processing runs lockless so we have
5722 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5723 */
f3f3f27e 5724 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5725 if (!netif_tx_queue_stopped(txq)) {
5726 netif_tx_stop_queue(txq);
1f064a87
SH		 5727
5728 /* This is a hard error, log it. */
5129c3a3
MC		 5729 netdev_err(dev,
5730 "BUG! Tx Ring full when queue awake!\n");
1f064a87 5731 }
1da177e4
LT		 5732 return NETDEV_TX_BUSY;
5733 }
5734
f3f3f27e 5735 entry = tnapi->tx_prod;
1da177e4 5736 base_flags = 0;
84fa7933 5737 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5738 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5739
c13e3713 5740 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5741 struct iphdr *iph;
92c6b8d1 5742 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5743
5744 if (skb_header_cloned(skb) &&
5745 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5746 dev_kfree_skb(skb);
5747 goto out_unlock;
5748 }
5749
ab6a5bb6 5750 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5751 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5752
52c0fd83
MC		 5753 hdr_len = ip_tcp_len + tcp_opt_len;
5754 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5755 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5756 return (tg3_tso_bug(tp, skb));
5757
1da177e4
LT		 5758 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5759 TXD_FLAG_CPU_POST_DMA);
5760
eddc9ec5
ACM		 5761 iph = ip_hdr(skb);
5762 iph->check = 0;
5763 iph->tot_len = htons(mss + hdr_len);
1da177e4 5764 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5765 tcp_hdr(skb)->check = 0;
1da177e4 5766 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5767 } else
5768 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5769 iph->daddr, 0,
5770 IPPROTO_TCP,
5771 0);
1da177e4 5772
615774fe
MC		 5773 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5774 mss |= (hdr_len & 0xc) << 12;
5775 if (hdr_len & 0x10)
5776 base_flags |= 0x00000010;
5777 base_flags |= (hdr_len & 0x3e0) << 5;
5778 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5779 mss |= hdr_len << 9;
5780 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5782 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5783 int tsflags;
5784
eddc9ec5 5785 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5786 mss |= (tsflags << 11);
5787 }
5788 } else {
eddc9ec5 5789 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5790 int tsflags;
5791
eddc9ec5 5792 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5793 base_flags |= tsflags << 12;
5794 }
5795 }
5796 }
1da177e4
LT		 5797#if TG3_VLAN_TAG_USED
5798 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5799 base_flags |= (TXD_FLAG_VLAN |
5800 (vlan_tx_tag_get(skb) << 16));
5801#endif
5802
b703df6f 5803 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5804 !mss && skb->len > ETH_DATA_LEN)
5805 base_flags |= TXD_FLAG_JMB_PKT;
5806
f4188d8a
AD		 5807 len = skb_headlen(skb);
5808
5809 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5810 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5811 dev_kfree_skb(skb);
5812 goto out_unlock;
5813 }
5814
f3f3f27e 5815 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5816 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5817
5818 would_hit_hwbug = 0;
5819
92c6b8d1
MC		 5820 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5821 would_hit_hwbug = 1;
5822
0e1406dd
MC		 5823 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5824 tg3_4g_overflow_test(mapping, len))
5825 would_hit_hwbug = 1;
5826
5827 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5828 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5829 would_hit_hwbug = 1;
0e1406dd
MC		 5830
5831 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5832 would_hit_hwbug = 1;
1da177e4 5833
f3f3f27e 5834 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5835 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5836
5837 entry = NEXT_TX(entry);
5838
5839 /* Now loop through additional data fragments, and queue them. */
5840 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5841 last = skb_shinfo(skb)->nr_frags - 1;
5842 for (i = 0; i <= last; i++) {
5843 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5844
5845 len = frag->size;
f4188d8a
AD		 5846 mapping = pci_map_page(tp->pdev,
5847 frag->page,
5848 frag->page_offset,
5849 len, PCI_DMA_TODEVICE);
1da177e4 5850
f3f3f27e 5851 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5852 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5853 mapping);
5854 if (pci_dma_mapping_error(tp->pdev, mapping))
5855 goto dma_error;
1da177e4 5856
92c6b8d1
MC		 5857 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5858 len <= 8)
5859 would_hit_hwbug = 1;
5860
0e1406dd
MC		 5861 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5862 tg3_4g_overflow_test(mapping, len))
c58ec932 5863 would_hit_hwbug = 1;
1da177e4 5864
0e1406dd
MC		 5865 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5866 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5867 would_hit_hwbug = 1;
5868
1da177e4 5869 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5870 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5871 base_flags, (i == last)|(mss << 1));
5872 else
f3f3f27e 5873 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5874 base_flags, (i == last));
5875
5876 entry = NEXT_TX(entry);
5877 }
5878 }
5879
5880 if (would_hit_hwbug) {
5881 u32 last_plus_one = entry;
5882 u32 start;
1da177e4 5883
c58ec932
MC		 5884 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5885 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5886
5887 /* If the workaround fails due to memory/mapping
5888 * failure, silently drop this packet.
5889 */
24f4efd4 5890 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5891 &start, base_flags, mss))
1da177e4
LT		 5892 goto out_unlock;
5893
5894 entry = start;
5895 }
5896
5897 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5898 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5899
f3f3f27e
MC		 5900 tnapi->tx_prod = entry;
5901 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5902 netif_tx_stop_queue(txq);
f3f3f27e 5903 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5904 netif_tx_wake_queue(txq);
51b91468 5905 }
1da177e4
LT		 5906
5907out_unlock:
cdd0db05 5908 mmiowb();
1da177e4
LT		 5909
5910 return NETDEV_TX_OK;
f4188d8a
AD		 5911
5912dma_error:
5913 last = i;
5914 entry = tnapi->tx_prod;
5915 tnapi->tx_buffers[entry].skb = NULL;
5916 pci_unmap_single(tp->pdev,
5917 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5918 skb_headlen(skb),
5919 PCI_DMA_TODEVICE);
5920 for (i = 0; i <= last; i++) {
5921 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5922 entry = NEXT_TX(entry);
5923
5924 pci_unmap_page(tp->pdev,
5925 pci_unmap_addr(&tnapi->tx_buffers[entry],
5926 mapping),
5927 frag->size, PCI_DMA_TODEVICE);
5928 }
5929
5930 dev_kfree_skb(skb);
5931 return NETDEV_TX_OK;
1da177e4
LT		 5932}
5933
5934static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5935 int new_mtu)
5936{
5937 dev->mtu = new_mtu;
5938
ef7f5ec0 5939 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5940 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5941 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5942 ethtool_op_set_tso(dev, 0);
859a5887 5943 } else {
ef7f5ec0 5944 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
859a5887 5945 }
ef7f5ec0 5946 } else {
a4e2b347 5947 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5948 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5949 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5950 }
1da177e4
LT		 5951}
5952
5953static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5954{
5955 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5956 int err;
1da177e4
LT		 5957
5958 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5959 return -EINVAL;
5960
5961 if (!netif_running(dev)) {
5962 /* We'll just catch it later when the
5963 * device is up'd.
5964 */
5965 tg3_set_mtu(dev, tp, new_mtu);
5966 return 0;
5967 }
5968
b02fd9e3
MC		 5969 tg3_phy_stop(tp);
5970
1da177e4 5971 tg3_netif_stop(tp);
f47c11ee
DM		 5972
5973 tg3_full_lock(tp, 1);
1da177e4 5974
944d980e 5975 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5976
5977 tg3_set_mtu(dev, tp, new_mtu);
5978
b9ec6c1b 5979 err = tg3_restart_hw(tp, 0);
1da177e4 5980
b9ec6c1b
MC		 5981 if (!err)
5982 tg3_netif_start(tp);
1da177e4 5983
f47c11ee 5984 tg3_full_unlock(tp);
1da177e4 5985
b02fd9e3
MC		 5986 if (!err)
5987 tg3_phy_start(tp);
5988
b9ec6c1b 5989 return err;
1da177e4
LT		 5990}
5991
21f581a5
MC		 5992static void tg3_rx_prodring_free(struct tg3 *tp,
5993 struct tg3_rx_prodring_set *tpr)
1da177e4 5994{
1da177e4
LT		 5995 int i;
5996
b196c7e4
MC		 5997 if (tpr != &tp->prodring[0]) {
5998 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5999 i = (i + 1) % TG3_RX_RING_SIZE)
6000 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6001 tp->rx_pkt_map_sz);
6002
6003 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6004 for (i = tpr->rx_jmb_cons_idx;
6005 i != tpr->rx_jmb_prod_idx;
6006 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6007 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6008 TG3_RX_JMB_MAP_SZ);
6009 }
6010 }
6011
2b2cdb65 6012 return;
b196c7e4 6013 }
1da177e4 6014
2b2cdb65
MC		 6015 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6016 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6017 tp->rx_pkt_map_sz);
1da177e4 6018
cf7a7298 6019 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 6020 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6021 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6022 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 6023 }
6024}
6025
c6cdf436 6026/* Initialize rx rings for packet processing.
1da177e4
LT		 6027 *
6028 * The chip has been shut down and the driver detached from
6029 * the networking, so no interrupts or new tx packets will
6030 * end up in the driver. tp->{tx,}lock are held and thus
6031 * we may not sleep.
6032 */
21f581a5
MC		 6033static int tg3_rx_prodring_alloc(struct tg3 *tp,
6034 struct tg3_rx_prodring_set *tpr)
1da177e4 6035{
287be12e 6036 u32 i, rx_pkt_dma_sz;
1da177e4 6037
b196c7e4
MC		 6038 tpr->rx_std_cons_idx = 0;
6039 tpr->rx_std_prod_idx = 0;
6040 tpr->rx_jmb_cons_idx = 0;
6041 tpr->rx_jmb_prod_idx = 0;
6042
2b2cdb65
MC		 6043 if (tpr != &tp->prodring[0]) {
6044 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6045 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6046 memset(&tpr->rx_jmb_buffers[0], 0,
6047 TG3_RX_JMB_BUFF_RING_SIZE);
6048 goto done;
6049 }
6050
1da177e4 6051 /* Zero out all descriptors. */
21f581a5 6052 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 6053
287be12e 6054 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 6055 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 6056 tp->dev->mtu > ETH_DATA_LEN)
6057 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6058 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 6059
1da177e4
LT		 6060 /* Initialize invariants of the rings, we only set this
6061 * stuff once. This works because the card does not
6062 * write into the rx buffer posting rings.
6063 */
6064 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6065 struct tg3_rx_buffer_desc *rxd;
6066
21f581a5 6067 rxd = &tpr->rx_std[i];
287be12e 6068 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6069 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6070 rxd->opaque = (RXD_OPAQUE_RING_STD |
6071 (i << RXD_OPAQUE_INDEX_SHIFT));
6072 }
6073
1da177e4
LT		 6074 /* Now allocate fresh SKBs for each rx ring. */
6075 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6076 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
5129c3a3
MC		 6077 netdev_warn(tp->dev,
6078 "Using a smaller RX standard ring. Only "
6079 "%d out of %d buffers were allocated "
6080 "successfully\n", i, tp->rx_pending);
32d8c572 6081 if (i == 0)
cf7a7298 6082 goto initfail;
32d8c572 6083 tp->rx_pending = i;
1da177e4 6084 break;
32d8c572 6085 }
1da177e4
LT		 6086 }
6087
cf7a7298
MC		 6088 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6089 goto done;
6090
21f581a5 6091 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6092
0d86df80
MC		 6093 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6094 goto done;
cf7a7298 6095
0d86df80
MC		 6096 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6097 struct tg3_rx_buffer_desc *rxd;
6098
6099 rxd = &tpr->rx_jmb[i].std;
6100 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6101 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6102 RXD_FLAG_JUMBO;
6103 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6104 (i << RXD_OPAQUE_INDEX_SHIFT));
6105 }
6106
6107 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6108 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
5129c3a3
MC		 6109 netdev_warn(tp->dev,
6110 "Using a smaller RX jumbo ring. Only %d "
6111 "out of %d buffers were allocated "
6112 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 6113 if (i == 0)
6114 goto initfail;
6115 tp->rx_jumbo_pending = i;
6116 break;
1da177e4
LT		 6117 }
6118 }
cf7a7298
MC		 6119
6120done:
32d8c572 6121 return 0;
cf7a7298
MC		 6122
6123initfail:
21f581a5 6124 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6125 return -ENOMEM;
1da177e4
LT		 6126}
6127
21f581a5
MC		 6128static void tg3_rx_prodring_fini(struct tg3 *tp,
6129 struct tg3_rx_prodring_set *tpr)
1da177e4 6130{
21f581a5
MC		 6131 kfree(tpr->rx_std_buffers);
6132 tpr->rx_std_buffers = NULL;
6133 kfree(tpr->rx_jmb_buffers);
6134 tpr->rx_jmb_buffers = NULL;
6135 if (tpr->rx_std) {
1da177e4 6136 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6137 tpr->rx_std, tpr->rx_std_mapping);
6138 tpr->rx_std = NULL;
1da177e4 6139 }
21f581a5 6140 if (tpr->rx_jmb) {
1da177e4 6141 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6142 tpr->rx_jmb, tpr->rx_jmb_mapping);
6143 tpr->rx_jmb = NULL;
1da177e4 6144 }
cf7a7298
MC		 6145}
6146
21f581a5
MC		 6147static int tg3_rx_prodring_init(struct tg3 *tp,
6148 struct tg3_rx_prodring_set *tpr)
cf7a7298 6149{
2b2cdb65 6150 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6151 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6152 return -ENOMEM;
6153
21f581a5
MC		 6154 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6155 &tpr->rx_std_mapping);
6156 if (!tpr->rx_std)
cf7a7298
MC		 6157 goto err_out;
6158
6159 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6160 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6161 GFP_KERNEL);
6162 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6163 goto err_out;
6164
21f581a5
MC		 6165 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6166 TG3_RX_JUMBO_RING_BYTES,
6167 &tpr->rx_jmb_mapping);
6168 if (!tpr->rx_jmb)
cf7a7298
MC		 6169 goto err_out;
6170 }
6171
6172 return 0;
6173
6174err_out:
21f581a5 6175 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6176 return -ENOMEM;
6177}
6178
6179/* Free up pending packets in all rx/tx rings.
6180 *
6181 * The chip has been shut down and the driver detached from
6182 * the networking, so no interrupts or new tx packets will
6183 * end up in the driver. tp->{tx,}lock is not held and we are not
6184 * in an interrupt context and thus may sleep.
6185 */
6186static void tg3_free_rings(struct tg3 *tp)
6187{
f77a6a8e 6188 int i, j;
cf7a7298 6189
f77a6a8e
MC		 6190 for (j = 0; j < tp->irq_cnt; j++) {
6191 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6192
0c1d0e2b
MC		 6193 if (!tnapi->tx_buffers)
6194 continue;
6195
f77a6a8e 6196 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6197 struct ring_info *txp;
f77a6a8e 6198 struct sk_buff *skb;
f4188d8a 6199 unsigned int k;
cf7a7298 6200
f77a6a8e
MC		 6201 txp = &tnapi->tx_buffers[i];
6202 skb = txp->skb;
cf7a7298 6203
f77a6a8e
MC		 6204 if (skb == NULL) {
6205 i++;
6206 continue;
6207 }
cf7a7298 6208
f4188d8a
AD		 6209 pci_unmap_single(tp->pdev,
6210 pci_unmap_addr(txp, mapping),
6211 skb_headlen(skb),
6212 PCI_DMA_TODEVICE);
f77a6a8e 6213 txp->skb = NULL;
cf7a7298 6214
f4188d8a
AD		 6215 i++;
6216
6217 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6218 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6219 pci_unmap_page(tp->pdev,
6220 pci_unmap_addr(txp, mapping),
6221 skb_shinfo(skb)->frags[k].size,
6222 PCI_DMA_TODEVICE);
6223 i++;
6224 }
f77a6a8e
MC		 6225
6226 dev_kfree_skb_any(skb);
6227 }
cf7a7298 6228
e4af1af9 6229 tg3_rx_prodring_free(tp, &tp->prodring[j]);
2b2cdb65 6230 }
cf7a7298
MC		 6231}
6232
6233/* Initialize tx/rx rings for packet processing.
6234 *
6235 * The chip has been shut down and the driver detached from
6236 * the networking, so no interrupts or new tx packets will
6237 * end up in the driver. tp->{tx,}lock are held and thus
6238 * we may not sleep.
6239 */
6240static int tg3_init_rings(struct tg3 *tp)
6241{
f77a6a8e 6242 int i;
72334482 6243
cf7a7298
MC		 6244 /* Free up all the SKBs. */
6245 tg3_free_rings(tp);
6246
f77a6a8e
MC		 6247 for (i = 0; i < tp->irq_cnt; i++) {
6248 struct tg3_napi *tnapi = &tp->napi[i];
6249
6250 tnapi->last_tag = 0;
6251 tnapi->last_irq_tag = 0;
6252 tnapi->hw_status->status = 0;
6253 tnapi->hw_status->status_tag = 0;
6254 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6255
f77a6a8e
MC		 6256 tnapi->tx_prod = 0;
6257 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6258 if (tnapi->tx_ring)
6259 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6260
6261 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6262 if (tnapi->rx_rcb)
6263 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 6264
e4af1af9
MC		 6265 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6266 tg3_free_rings(tp);
2b2cdb65 6267 return -ENOMEM;
e4af1af9 6268 }
f77a6a8e 6269 }
72334482 6270
2b2cdb65 6271 return 0;
cf7a7298
MC		 6272}
6273
6274/*
6275 * Must not be invoked with interrupt sources disabled and
6276 * the hardware shutdown down.
6277 */
6278static void tg3_free_consistent(struct tg3 *tp)
6279{
f77a6a8e 6280 int i;
898a56f8 6281
f77a6a8e
MC		 6282 for (i = 0; i < tp->irq_cnt; i++) {
6283 struct tg3_napi *tnapi = &tp->napi[i];
6284
6285 if (tnapi->tx_ring) {
6286 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6287 tnapi->tx_ring, tnapi->tx_desc_mapping);
6288 tnapi->tx_ring = NULL;
6289 }
6290
6291 kfree(tnapi->tx_buffers);
6292 tnapi->tx_buffers = NULL;
6293
6294 if (tnapi->rx_rcb) {
6295 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6296 tnapi->rx_rcb,
6297 tnapi->rx_rcb_mapping);
6298 tnapi->rx_rcb = NULL;
6299 }
6300
6301 if (tnapi->hw_status) {
6302 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6303 tnapi->hw_status,
6304 tnapi->status_mapping);
6305 tnapi->hw_status = NULL;
6306 }
1da177e4 6307 }
f77a6a8e 6308
1da177e4
LT		 6309 if (tp->hw_stats) {
6310 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6311 tp->hw_stats, tp->stats_mapping);
6312 tp->hw_stats = NULL;
6313 }
f77a6a8e 6314
e4af1af9 6315 for (i = 0; i < tp->irq_cnt; i++)
2b2cdb65 6316 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6317}
6318
6319/*
6320 * Must not be invoked with interrupt sources disabled and
6321 * the hardware shutdown down. Can sleep.
6322 */
6323static int tg3_alloc_consistent(struct tg3 *tp)
6324{
f77a6a8e 6325 int i;
898a56f8 6326
e4af1af9 6327 for (i = 0; i < tp->irq_cnt; i++) {
2b2cdb65
MC		 6328 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6329 goto err_out;
6330 }
1da177e4 6331
f77a6a8e
MC		 6332 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6333 sizeof(struct tg3_hw_stats),
6334 &tp->stats_mapping);
6335 if (!tp->hw_stats)
1da177e4
LT		 6336 goto err_out;
6337
f77a6a8e 6338 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6339
f77a6a8e
MC		 6340 for (i = 0; i < tp->irq_cnt; i++) {
6341 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6342 struct tg3_hw_status *sblk;
1da177e4 6343
f77a6a8e
MC		 6344 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6345 TG3_HW_STATUS_SIZE,
6346 &tnapi->status_mapping);
6347 if (!tnapi->hw_status)
6348 goto err_out;
898a56f8 6349
f77a6a8e 6350 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6351 sblk = tnapi->hw_status;
6352
19cfaecc
MC		 6353 /* If multivector TSS is enabled, vector 0 does not handle
6354 * tx interrupts. Don't allocate any resources for it.
6355 */
6356 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6357 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6358 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6359 TG3_TX_RING_SIZE,
6360 GFP_KERNEL);
6361 if (!tnapi->tx_buffers)
6362 goto err_out;
6363
6364 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6365 TG3_TX_RING_BYTES,
6366 &tnapi->tx_desc_mapping);
6367 if (!tnapi->tx_ring)
6368 goto err_out;
6369 }
6370
8d9d7cfc
MC		 6371 /*
6372 * When RSS is enabled, the status block format changes
6373 * slightly. The "rx_jumbo_consumer", "reserved",
6374 * and "rx_mini_consumer" members get mapped to the
6375 * other three rx return ring producer indexes.
6376 */
6377 switch (i) {
6378 default:
6379 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6380 break;
6381 case 2:
6382 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6383 break;
6384 case 3:
6385 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6386 break;
6387 case 4:
6388 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6389 break;
6390 }
72334482 6391
e4af1af9 6392 tnapi->prodring = &tp->prodring[i];
b196c7e4 6393
0c1d0e2b
MC		 6394 /*
6395 * If multivector RSS is enabled, vector 0 does not handle
6396 * rx or tx interrupts. Don't allocate any resources for it.
6397 */
6398 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6399 continue;
6400
f77a6a8e
MC		 6401 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6402 TG3_RX_RCB_RING_BYTES(tp),
6403 &tnapi->rx_rcb_mapping);
6404 if (!tnapi->rx_rcb)
6405 goto err_out;
72334482 6406
f77a6a8e 6407 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6408 }
1da177e4
LT		 6409
6410 return 0;
6411
6412err_out:
6413 tg3_free_consistent(tp);
6414 return -ENOMEM;
6415}
6416
6417#define MAX_WAIT_CNT 1000
6418
6419/* To stop a block, clear the enable bit and poll till it
6420 * clears. tp->lock is held.
6421 */
b3b7d6be 6422static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6423{
6424 unsigned int i;
6425 u32 val;
6426
6427 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6428 switch (ofs) {
6429 case RCVLSC_MODE:
6430 case DMAC_MODE:
6431 case MBFREE_MODE:
6432 case BUFMGR_MODE:
6433 case MEMARB_MODE:
6434 /* We can't enable/disable these bits of the
6435 * 5705/5750, just say success.
6436 */
6437 return 0;
6438
6439 default:
6440 break;
855e1111 6441 }
1da177e4
LT		 6442 }
6443
6444 val = tr32(ofs);
6445 val &= ~enable_bit;
6446 tw32_f(ofs, val);
6447
6448 for (i = 0; i < MAX_WAIT_CNT; i++) {
6449 udelay(100);
6450 val = tr32(ofs);
6451 if ((val & enable_bit) == 0)
6452 break;
6453 }
6454
b3b7d6be 6455 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 6456 dev_err(&tp->pdev->dev,
6457 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6458 ofs, enable_bit);
1da177e4
LT		 6459 return -ENODEV;
6460 }
6461
6462 return 0;
6463}
6464
6465/* tp->lock is held. */
b3b7d6be 6466static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6467{
6468 int i, err;
6469
6470 tg3_disable_ints(tp);
6471
6472 tp->rx_mode &= ~RX_MODE_ENABLE;
6473 tw32_f(MAC_RX_MODE, tp->rx_mode);
6474 udelay(10);
6475
b3b7d6be
DM		 6476 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6480 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6481 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6482
6483 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6484 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6485 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6486 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6487 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6488 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6489 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6490
6491 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6492 tw32_f(MAC_MODE, tp->mac_mode);
6493 udelay(40);
6494
6495 tp->tx_mode &= ~TX_MODE_ENABLE;
6496 tw32_f(MAC_TX_MODE, tp->tx_mode);
6497
6498 for (i = 0; i < MAX_WAIT_CNT; i++) {
6499 udelay(100);
6500 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6501 break;
6502 }
6503 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 6504 dev_err(&tp->pdev->dev,
6505 "%s timed out, TX_MODE_ENABLE will not clear "
6506 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 6507 err |= -ENODEV;
1da177e4
LT		 6508 }
6509
e6de8ad1 6510 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6511 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6512 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6513
6514 tw32(FTQ_RESET, 0xffffffff);
6515 tw32(FTQ_RESET, 0x00000000);
6516
b3b7d6be
DM		 6517 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6518 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6519
f77a6a8e
MC		 6520 for (i = 0; i < tp->irq_cnt; i++) {
6521 struct tg3_napi *tnapi = &tp->napi[i];
6522 if (tnapi->hw_status)
6523 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6524 }
1da177e4
LT		 6525 if (tp->hw_stats)
6526 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6527
1da177e4
LT		 6528 return err;
6529}
6530
0d3031d9
MC		 6531static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6532{
6533 int i;
6534 u32 apedata;
6535
6536 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6537 if (apedata != APE_SEG_SIG_MAGIC)
6538 return;
6539
6540 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6541 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6542 return;
6543
6544 /* Wait for up to 1 millisecond for APE to service previous event. */
6545 for (i = 0; i < 10; i++) {
6546 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6547 return;
6548
6549 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6550
6551 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6552 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6553 event | APE_EVENT_STATUS_EVENT_PENDING);
6554
6555 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6556
6557 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6558 break;
6559
6560 udelay(100);
6561 }
6562
6563 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6564 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6565}
6566
6567static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6568{
6569 u32 event;
6570 u32 apedata;
6571
6572 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6573 return;
6574
6575 switch (kind) {
33f401ae
MC		 6576 case RESET_KIND_INIT:
6577 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6578 APE_HOST_SEG_SIG_MAGIC);
6579 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6580 APE_HOST_SEG_LEN_MAGIC);
6581 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6582 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6583 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6584 APE_HOST_DRIVER_ID_MAGIC);
6585 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6586 APE_HOST_BEHAV_NO_PHYLOCK);
6587
6588 event = APE_EVENT_STATUS_STATE_START;
6589 break;
6590 case RESET_KIND_SHUTDOWN:
6591 /* With the interface we are currently using,
6592 * APE does not track driver state. Wiping
6593 * out the HOST SEGMENT SIGNATURE forces
6594 * the APE to assume OS absent status.
6595 */
6596 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
b2aee154 6597
33f401ae
MC		 6598 event = APE_EVENT_STATUS_STATE_UNLOAD;
6599 break;
6600 case RESET_KIND_SUSPEND:
6601 event = APE_EVENT_STATUS_STATE_SUSPEND;
6602 break;
6603 default:
6604 return;
0d3031d9
MC		 6605 }
6606
6607 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6608
6609 tg3_ape_send_event(tp, event);
6610}
6611
1da177e4
LT		 6612/* tp->lock is held. */
6613static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6614{
f49639e6
DM		 6615 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6616 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6617
6618 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6619 switch (kind) {
6620 case RESET_KIND_INIT:
6621 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6622 DRV_STATE_START);
6623 break;
6624
6625 case RESET_KIND_SHUTDOWN:
6626 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6627 DRV_STATE_UNLOAD);
6628 break;
6629
6630 case RESET_KIND_SUSPEND:
6631 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6632 DRV_STATE_SUSPEND);
6633 break;
6634
6635 default:
6636 break;
855e1111 6637 }
1da177e4 6638 }
0d3031d9
MC		 6639
6640 if (kind == RESET_KIND_INIT ||
6641 kind == RESET_KIND_SUSPEND)
6642 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6643}
6644
6645/* tp->lock is held. */
6646static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6647{
6648 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6649 switch (kind) {
6650 case RESET_KIND_INIT:
6651 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6652 DRV_STATE_START_DONE);
6653 break;
6654
6655 case RESET_KIND_SHUTDOWN:
6656 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6657 DRV_STATE_UNLOAD_DONE);
6658 break;
6659
6660 default:
6661 break;
855e1111 6662 }
1da177e4 6663 }
0d3031d9
MC		 6664
6665 if (kind == RESET_KIND_SHUTDOWN)
6666 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6667}
6668
6669/* tp->lock is held. */
6670static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6671{
6672 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6673 switch (kind) {
6674 case RESET_KIND_INIT:
6675 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6676 DRV_STATE_START);
6677 break;
6678
6679 case RESET_KIND_SHUTDOWN:
6680 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6681 DRV_STATE_UNLOAD);
6682 break;
6683
6684 case RESET_KIND_SUSPEND:
6685 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6686 DRV_STATE_SUSPEND);
6687 break;
6688
6689 default:
6690 break;
855e1111 6691 }
1da177e4
LT		 6692 }
6693}
6694
7a6f4369
MC		 6695static int tg3_poll_fw(struct tg3 *tp)
6696{
6697 int i;
6698 u32 val;
6699
b5d3772c 6700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6701 /* Wait up to 20ms for init done. */
6702 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6703 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6704 return 0;
0ccead18 6705 udelay(100);
b5d3772c
MC		 6706 }
6707 return -ENODEV;
6708 }
6709
7a6f4369
MC		 6710 /* Wait for firmware initialization to complete. */
6711 for (i = 0; i < 100000; i++) {
6712 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6713 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6714 break;
6715 udelay(10);
6716 }
6717
6718 /* Chip might not be fitted with firmware. Some Sun onboard
6719 * parts are configured like that. So don't signal the timeout
6720 * of the above loop as an error, but do report the lack of
6721 * running firmware once.
6722 */
6723 if (i >= 100000 &&
6724 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6725 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6726
05dbe005 6727 netdev_info(tp->dev, "No firmware running\n");
7a6f4369
MC		 6728 }
6729
6b10c165
MC		 6730 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6731 /* The 57765 A0 needs a little more
6732 * time to do some important work.
6733 */
6734 mdelay(10);
6735 }
6736
7a6f4369
MC		 6737 return 0;
6738}
6739
ee6a99b5
MC		 6740/* Save PCI command register before chip reset */
6741static void tg3_save_pci_state(struct tg3 *tp)
6742{
8a6eac90 6743 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6744}
6745
6746/* Restore PCI state after chip reset */
6747static void tg3_restore_pci_state(struct tg3 *tp)
6748{
6749 u32 val;
6750
6751 /* Re-enable indirect register accesses. */
6752 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6753 tp->misc_host_ctrl);
6754
6755 /* Set MAX PCI retry to zero. */
6756 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6757 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6758 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6759 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6760 /* Allow reads and writes to the APE register and memory space. */
6761 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6762 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6763 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6764 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6765
8a6eac90 6766 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6767
fcb389df
MC		 6768 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6769 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6770 pcie_set_readrq(tp->pdev, 4096);
6771 else {
6772 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6773 tp->pci_cacheline_sz);
6774 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6775 tp->pci_lat_timer);
6776 }
114342f2 6777 }
5f5c51e3 6778
ee6a99b5 6779 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6780 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6781 u16 pcix_cmd;
6782
6783 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6784 &pcix_cmd);
6785 pcix_cmd &= ~PCI_X_CMD_ERO;
6786 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6787 pcix_cmd);
6788 }
ee6a99b5
MC		 6789
6790 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6791
6792 /* Chip reset on 5780 will reset MSI enable bit,
6793 * so need to restore it.
6794 */
6795 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6796 u16 ctrl;
6797
6798 pci_read_config_word(tp->pdev,
6799 tp->msi_cap + PCI_MSI_FLAGS,
6800 &ctrl);
6801 pci_write_config_word(tp->pdev,
6802 tp->msi_cap + PCI_MSI_FLAGS,
6803 ctrl | PCI_MSI_FLAGS_ENABLE);
6804 val = tr32(MSGINT_MODE);
6805 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6806 }
6807 }
6808}
6809
1da177e4
LT		 6810static void tg3_stop_fw(struct tg3 *);
6811
6812/* tp->lock is held. */
6813static int tg3_chip_reset(struct tg3 *tp)
6814{
6815 u32 val;
1ee582d8 6816 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6817 int i, err;
1da177e4 6818
f49639e6
DM		 6819 tg3_nvram_lock(tp);
6820
77b483f1
MC		 6821 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6822
f49639e6
DM		 6823 /* No matching tg3_nvram_unlock() after this because
6824 * chip reset below will undo the nvram lock.
6825 */
6826 tp->nvram_lock_cnt = 0;
1da177e4 6827
ee6a99b5
MC		 6828 /* GRC_MISC_CFG core clock reset will clear the memory
6829 * enable bit in PCI register 4 and the MSI enable bit
6830 * on some chips, so we save relevant registers here.
6831 */
6832 tg3_save_pci_state(tp);
6833
d9ab5ad1 6834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6835 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6836 tw32(GRC_FASTBOOT_PC, 0);
6837
1da177e4
LT		 6838 /*
6839 * We must avoid the readl() that normally takes place.
6840 * It locks machines, causes machine checks, and other
6841 * fun things. So, temporarily disable the 5701
6842 * hardware workaround, while we do the reset.
6843 */
1ee582d8
MC		 6844 write_op = tp->write32;
6845 if (write_op == tg3_write_flush_reg32)
6846 tp->write32 = tg3_write32;
1da177e4 6847
d18edcb2
MC		 6848 /* Prevent the irq handler from reading or writing PCI registers
6849 * during chip reset when the memory enable bit in the PCI command
6850 * register may be cleared. The chip does not generate interrupt
6851 * at this time, but the irq handler may still be called due to irq
6852 * sharing or irqpoll.
6853 */
6854 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6855 for (i = 0; i < tp->irq_cnt; i++) {
6856 struct tg3_napi *tnapi = &tp->napi[i];
6857 if (tnapi->hw_status) {
6858 tnapi->hw_status->status = 0;
6859 tnapi->hw_status->status_tag = 0;
6860 }
6861 tnapi->last_tag = 0;
6862 tnapi->last_irq_tag = 0;
b8fa2f3a 6863 }
d18edcb2 6864 smp_mb();
4f125f42
MC		 6865
6866 for (i = 0; i < tp->irq_cnt; i++)
6867 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6868
255ca311
MC		 6869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6870 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6871 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6872 }
6873
1da177e4
LT		 6874 /* do the reset */
6875 val = GRC_MISC_CFG_CORECLK_RESET;
6876
6877 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6878 if (tr32(0x7e2c) == 0x60) {
6879 tw32(0x7e2c, 0x20);
6880 }
6881 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6882 tw32(GRC_MISC_CFG, (1 << 29));
6883 val |= (1 << 29);
6884 }
6885 }
6886
b5d3772c
MC		 6887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6888 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6889 tw32(GRC_VCPU_EXT_CTRL,
6890 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6891 }
6892
1da177e4
LT		 6893 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6894 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6895 tw32(GRC_MISC_CFG, val);
6896
1ee582d8
MC		 6897 /* restore 5701 hardware bug workaround write method */
6898 tp->write32 = write_op;
1da177e4
LT		 6899
6900 /* Unfortunately, we have to delay before the PCI read back.
6901 * Some 575X chips even will not respond to a PCI cfg access
6902 * when the reset command is given to the chip.
6903 *
6904 * How do these hardware designers expect things to work
6905 * properly if the PCI write is posted for a long period
6906 * of time? It is always necessary to have some method by
6907 * which a register read back can occur to push the write
6908 * out which does the reset.
6909 *
6910 * For most tg3 variants the trick below was working.
6911 * Ho hum...
6912 */
6913 udelay(120);
6914
6915 /* Flush PCI posted writes. The normal MMIO registers
6916 * are inaccessible at this time so this is the only
6917 * way to make this reliably (actually, this is no longer
6918 * the case, see above). I tried to use indirect
6919 * register read/write but this upset some 5701 variants.
6920 */
6921 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6922
6923 udelay(120);
6924
5e7dfd0f 6925 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6926 u16 val16;
6927
1da177e4
LT		 6928 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6929 int i;
6930 u32 cfg_val;
6931
6932 /* Wait for link training to complete. */
6933 for (i = 0; i < 5000; i++)
6934 udelay(100);
6935
6936 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6937 pci_write_config_dword(tp->pdev, 0xc4,
6938 cfg_val | (1 << 15));
6939 }
5e7dfd0f 6940
e7126997
MC		 6941 /* Clear the "no snoop" and "relaxed ordering" bits. */
6942 pci_read_config_word(tp->pdev,
6943 tp->pcie_cap + PCI_EXP_DEVCTL,
6944 &val16);
6945 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6946 PCI_EXP_DEVCTL_NOSNOOP_EN);
6947 /*
6948 * Older PCIe devices only support the 128 byte
6949 * MPS setting. Enforce the restriction.
5e7dfd0f 6950 */
e7126997
MC		 6951 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6953 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6954 pci_write_config_word(tp->pdev,
6955 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6956 val16);
5e7dfd0f
MC		 6957
6958 pcie_set_readrq(tp->pdev, 4096);
6959
6960 /* Clear error status */
6961 pci_write_config_word(tp->pdev,
6962 tp->pcie_cap + PCI_EXP_DEVSTA,
6963 PCI_EXP_DEVSTA_CED |
6964 PCI_EXP_DEVSTA_NFED |
6965 PCI_EXP_DEVSTA_FED |
6966 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6967 }
6968
ee6a99b5 6969 tg3_restore_pci_state(tp);
1da177e4 6970
d18edcb2
MC		 6971 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6972
ee6a99b5
MC		 6973 val = 0;
6974 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6975 val = tr32(MEMARB_MODE);
ee6a99b5 6976 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6977
6978 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6979 tg3_stop_fw(tp);
6980 tw32(0x5000, 0x400);
6981 }
6982
6983 tw32(GRC_MODE, tp->grc_mode);
6984
6985 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6986 val = tr32(0xc4);
1da177e4
LT		 6987
6988 tw32(0xc4, val | (1 << 15));
6989 }
6990
6991 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6993 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6994 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6995 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6996 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6997 }
6998
6999 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7000 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7001 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 7002 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7003 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7004 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 7005 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7006 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7007 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7008 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7009 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 7010 } else
7011 tw32_f(MAC_MODE, 0);
7012 udelay(40);
7013
77b483f1
MC		 7014 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7015
7a6f4369
MC		 7016 err = tg3_poll_fw(tp);
7017 if (err)
7018 return err;
1da177e4 7019
0a9140cf
MC		 7020 tg3_mdio_start(tp);
7021
52cdf852
MC		 7022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7023 u8 phy_addr;
7024
7025 phy_addr = tp->phy_addr;
7026 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7027
7028 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7029 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7030 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7031 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7032 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7033 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7034 udelay(10);
7035
7036 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7037 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7038 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7039 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7040 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7041 udelay(10);
7042
7043 tp->phy_addr = phy_addr;
7044 }
7045
1da177e4 7046 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 7047 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7048 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 7049 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7050 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 7051 val = tr32(0x7c00);
1da177e4
LT		 7052
7053 tw32(0x7c00, val | (1 << 25));
7054 }
7055
7056 /* Reprobe ASF enable state. */
7057 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7058 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7059 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7060 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7061 u32 nic_cfg;
7062
7063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7064 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7065 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 7066 tp->last_event_jiffies = jiffies;
cbf46853 7067 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7068 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7069 }
7070 }
7071
7072 return 0;
7073}
7074
7075/* tp->lock is held. */
7076static void tg3_stop_fw(struct tg3 *tp)
7077{
0d3031d9
MC		 7078 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7079 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7080 /* Wait for RX cpu to ACK the previous event. */
7081 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7082
7083 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7084
7085 tg3_generate_fw_event(tp);
1da177e4 7086
7c5026aa
MC		 7087 /* Wait for RX cpu to ACK this event. */
7088 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7089 }
7090}
7091
7092/* tp->lock is held. */
944d980e 7093static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7094{
7095 int err;
7096
7097 tg3_stop_fw(tp);
7098
944d980e 7099 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7100
b3b7d6be 7101 tg3_abort_hw(tp, silent);
1da177e4
LT		 7102 err = tg3_chip_reset(tp);
7103
daba2a63
MC		 7104 __tg3_set_mac_addr(tp, 0);
7105
944d980e
MC		 7106 tg3_write_sig_legacy(tp, kind);
7107 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7108
7109 if (err)
7110 return err;
7111
7112 return 0;
7113}
7114
1da177e4
LT		 7115#define RX_CPU_SCRATCH_BASE 0x30000
7116#define RX_CPU_SCRATCH_SIZE 0x04000
7117#define TX_CPU_SCRATCH_BASE 0x34000
7118#define TX_CPU_SCRATCH_SIZE 0x04000
7119
7120/* tp->lock is held. */
7121static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7122{
7123 int i;
7124
5d9428de
ES		 7125 BUG_ON(offset == TX_CPU_BASE &&
7126 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7127
b5d3772c
MC		 7128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7129 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7130
7131 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7132 return 0;
7133 }
1da177e4
LT		 7134 if (offset == RX_CPU_BASE) {
7135 for (i = 0; i < 10000; i++) {
7136 tw32(offset + CPU_STATE, 0xffffffff);
7137 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7138 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7139 break;
7140 }
7141
7142 tw32(offset + CPU_STATE, 0xffffffff);
7143 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7144 udelay(10);
7145 } else {
7146 for (i = 0; i < 10000; i++) {
7147 tw32(offset + CPU_STATE, 0xffffffff);
7148 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7149 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7150 break;
7151 }
7152 }
7153
7154 if (i >= 10000) {
05dbe005
JP		 7155 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7156 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
1da177e4
LT		 7157 return -ENODEV;
7158 }
ec41c7df
MC		 7159
7160 /* Clear firmware's nvram arbitration. */
7161 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7162 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7163 return 0;
7164}
7165
7166struct fw_info {
077f849d
JSR		 7167 unsigned int fw_base;
7168 unsigned int fw_len;
7169 const __be32 *fw_data;
1da177e4
LT		 7170};
7171
7172/* tp->lock is held. */
7173static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7174 int cpu_scratch_size, struct fw_info *info)
7175{
ec41c7df 7176 int err, lock_err, i;
1da177e4
LT		 7177 void (*write_op)(struct tg3 *, u32, u32);
7178
7179 if (cpu_base == TX_CPU_BASE &&
7180 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5129c3a3
MC		 7181 netdev_err(tp->dev,
7182 "%s: Trying to load TX cpu firmware which is 5705\n",
05dbe005 7183 __func__);
1da177e4
LT		 7184 return -EINVAL;
7185 }
7186
7187 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7188 write_op = tg3_write_mem;
7189 else
7190 write_op = tg3_write_indirect_reg32;
7191
1b628151
MC		 7192 /* It is possible that bootcode is still loading at this point.
7193 * Get the nvram lock first before halting the cpu.
7194 */
ec41c7df 7195 lock_err = tg3_nvram_lock(tp);
1da177e4 7196 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7197 if (!lock_err)
7198 tg3_nvram_unlock(tp);
1da177e4
LT		 7199 if (err)
7200 goto out;
7201
7202 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7203 write_op(tp, cpu_scratch_base + i, 0);
7204 tw32(cpu_base + CPU_STATE, 0xffffffff);
7205 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7206 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7207 write_op(tp, (cpu_scratch_base +
077f849d 7208 (info->fw_base & 0xffff) +
1da177e4 7209 (i * sizeof(u32))),
077f849d 7210 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7211
7212 err = 0;
7213
7214out:
1da177e4
LT		 7215 return err;
7216}
7217
7218/* tp->lock is held. */
7219static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7220{
7221 struct fw_info info;
077f849d 7222 const __be32 *fw_data;
1da177e4
LT		 7223 int err, i;
7224
077f849d
JSR		 7225 fw_data = (void *)tp->fw->data;
7226
7227 /* Firmware blob starts with version numbers, followed by
7228 start address and length. We are setting complete length.
7229 length = end_address_of_bss - start_address_of_text.
7230 Remainder is the blob to be loaded contiguously
7231 from start address. */
7232
7233 info.fw_base = be32_to_cpu(fw_data[1]);
7234 info.fw_len = tp->fw->size - 12;
7235 info.fw_data = &fw_data[3];
1da177e4
LT		 7236
7237 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7238 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7239 &info);
7240 if (err)
7241 return err;
7242
7243 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7244 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7245 &info);
7246 if (err)
7247 return err;
7248
7249 /* Now startup only the RX cpu. */
7250 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7251 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7252
7253 for (i = 0; i < 5; i++) {
077f849d 7254 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7255 break;
7256 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7257 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7258 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7259 udelay(1000);
7260 }
7261 if (i >= 5) {
5129c3a3
MC		 7262 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7263 "should be %08x\n", __func__,
05dbe005 7264 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
1da177e4
LT		 7265 return -ENODEV;
7266 }
7267 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7268 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7269
7270 return 0;
7271}
7272
1da177e4 7273/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7274
7275/* tp->lock is held. */
7276static int tg3_load_tso_firmware(struct tg3 *tp)
7277{
7278 struct fw_info info;
077f849d 7279 const __be32 *fw_data;
1da177e4
LT		 7280 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7281 int err, i;
7282
7283 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7284 return 0;
7285
077f849d
JSR		 7286 fw_data = (void *)tp->fw->data;
7287
7288 /* Firmware blob starts with version numbers, followed by
7289 start address and length. We are setting complete length.
7290 length = end_address_of_bss - start_address_of_text.
7291 Remainder is the blob to be loaded contiguously
7292 from start address. */
7293
7294 info.fw_base = be32_to_cpu(fw_data[1]);
7295 cpu_scratch_size = tp->fw_len;
7296 info.fw_len = tp->fw->size - 12;
7297 info.fw_data = &fw_data[3];
7298
1da177e4 7299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7300 cpu_base = RX_CPU_BASE;
7301 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7302 } else {
1da177e4
LT		 7303 cpu_base = TX_CPU_BASE;
7304 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7305 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7306 }
7307
7308 err = tg3_load_firmware_cpu(tp, cpu_base,
7309 cpu_scratch_base, cpu_scratch_size,
7310 &info);
7311 if (err)
7312 return err;
7313
7314 /* Now startup the cpu. */
7315 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7316 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7317
7318 for (i = 0; i < 5; i++) {
077f849d 7319 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7320 break;
7321 tw32(cpu_base + CPU_STATE, 0xffffffff);
7322 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7323 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7324 udelay(1000);
7325 }
7326 if (i >= 5) {
5129c3a3
MC		 7327 netdev_err(tp->dev,
7328 "%s fails to set CPU PC, is %08x should be %08x\n",
05dbe005 7329 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
1da177e4
LT		 7330 return -ENODEV;
7331 }
7332 tw32(cpu_base + CPU_STATE, 0xffffffff);
7333 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7334 return 0;
7335}
7336
1da177e4 7337
1da177e4
LT		 7338static int tg3_set_mac_addr(struct net_device *dev, void *p)
7339{
7340 struct tg3 *tp = netdev_priv(dev);
7341 struct sockaddr *addr = p;
986e0aeb 7342 int err = 0, skip_mac_1 = 0;
1da177e4 7343
f9804ddb
MC		 7344 if (!is_valid_ether_addr(addr->sa_data))
7345 return -EINVAL;
7346
1da177e4
LT		 7347 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7348
e75f7c90
MC		 7349 if (!netif_running(dev))
7350 return 0;
7351
58712ef9 7352 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7353 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7354
986e0aeb
MC		 7355 addr0_high = tr32(MAC_ADDR_0_HIGH);
7356 addr0_low = tr32(MAC_ADDR_0_LOW);
7357 addr1_high = tr32(MAC_ADDR_1_HIGH);
7358 addr1_low = tr32(MAC_ADDR_1_LOW);
7359
7360 /* Skip MAC addr 1 if ASF is using it. */
7361 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7362 !(addr1_high == 0 && addr1_low == 0))
7363 skip_mac_1 = 1;
58712ef9 7364 }
986e0aeb
MC		 7365 spin_lock_bh(&tp->lock);
7366 __tg3_set_mac_addr(tp, skip_mac_1);
7367 spin_unlock_bh(&tp->lock);
1da177e4 7368
b9ec6c1b 7369 return err;
1da177e4
LT		 7370}
7371
7372/* tp->lock is held. */
7373static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7374 dma_addr_t mapping, u32 maxlen_flags,
7375 u32 nic_addr)
7376{
7377 tg3_write_mem(tp,
7378 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7379 ((u64) mapping >> 32));
7380 tg3_write_mem(tp,
7381 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7382 ((u64) mapping & 0xffffffff));
7383 tg3_write_mem(tp,
7384 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7385 maxlen_flags);
7386
7387 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7388 tg3_write_mem(tp,
7389 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7390 nic_addr);
7391}
7392
7393static void __tg3_set_rx_mode(struct net_device *);
d244c892 7394static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7395{
b6080e12
MC		 7396 int i;
7397
19cfaecc 7398 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7399 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7400 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7401 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7402 } else {
7403 tw32(HOSTCC_TXCOL_TICKS, 0);
7404 tw32(HOSTCC_TXMAX_FRAMES, 0);
7405 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7406 }
b6080e12 7407
19cfaecc
MC		 7408 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7409 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7410 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7411 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7412 } else {
b6080e12
MC		 7413 tw32(HOSTCC_RXCOL_TICKS, 0);
7414 tw32(HOSTCC_RXMAX_FRAMES, 0);
7415 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7416 }
b6080e12 7417
15f9850d
DM		 7418 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7419 u32 val = ec->stats_block_coalesce_usecs;
7420
b6080e12
MC		 7421 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7422 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7423
15f9850d
DM		 7424 if (!netif_carrier_ok(tp->dev))
7425 val = 0;
7426
7427 tw32(HOSTCC_STAT_COAL_TICKS, val);
7428 }
b6080e12
MC		 7429
7430 for (i = 0; i < tp->irq_cnt - 1; i++) {
7431 u32 reg;
7432
7433 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7434 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7435 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7436 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7437 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7438 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7439
7440 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7441 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7442 tw32(reg, ec->tx_coalesce_usecs);
7443 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7444 tw32(reg, ec->tx_max_coalesced_frames);
7445 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7446 tw32(reg, ec->tx_max_coalesced_frames_irq);
7447 }
b6080e12
MC		 7448 }
7449
7450 for (; i < tp->irq_max - 1; i++) {
7451 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7452 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7453 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7454
7455 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7456 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7457 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7458 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7459 }
b6080e12 7460 }
15f9850d 7461}
1da177e4 7462
2d31ecaf
MC		 7463/* tp->lock is held. */
7464static void tg3_rings_reset(struct tg3 *tp)
7465{
7466 int i;
f77a6a8e 7467 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7468 struct tg3_napi *tnapi = &tp->napi[0];
7469
7470 /* Disable all transmit rings but the first. */
7471 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7472 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7473 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7474 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7475 else
7476 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7477
7478 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7479 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7480 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7481 BDINFO_FLAGS_DISABLED);
7482
7483
7484 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7486 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7487 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7488 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7489 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7491 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7492 else
7493 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7494
7495 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7496 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7497 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7498 BDINFO_FLAGS_DISABLED);
7499
7500 /* Disable interrupts */
7501 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7502
7503 /* Zero mailbox registers. */
f77a6a8e
MC		 7504 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7505 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7506 tp->napi[i].tx_prod = 0;
7507 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7508 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7509 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7510 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7511 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7512 }
c2353a32
MC		 7513 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7514 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7515 } else {
7516 tp->napi[0].tx_prod = 0;
7517 tp->napi[0].tx_cons = 0;
7518 tw32_mailbox(tp->napi[0].prodmbox, 0);
7519 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7520 }
2d31ecaf
MC		 7521
7522 /* Make sure the NIC-based send BD rings are disabled. */
7523 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7524 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7525 for (i = 0; i < 16; i++)
7526 tw32_tx_mbox(mbox + i * 8, 0);
7527 }
7528
7529 txrcb = NIC_SRAM_SEND_RCB;
7530 rxrcb = NIC_SRAM_RCV_RET_RCB;
7531
7532 /* Clear status block in ram. */
7533 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7534
7535 /* Set status block DMA address */
7536 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7537 ((u64) tnapi->status_mapping >> 32));
7538 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7539 ((u64) tnapi->status_mapping & 0xffffffff));
7540
f77a6a8e
MC		 7541 if (tnapi->tx_ring) {
7542 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7543 (TG3_TX_RING_SIZE <<
7544 BDINFO_FLAGS_MAXLEN_SHIFT),
7545 NIC_SRAM_TX_BUFFER_DESC);
7546 txrcb += TG3_BDINFO_SIZE;
7547 }
7548
7549 if (tnapi->rx_rcb) {
7550 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7551 (TG3_RX_RCB_RING_SIZE(tp) <<
7552 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7553 rxrcb += TG3_BDINFO_SIZE;
7554 }
7555
7556 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7557
f77a6a8e
MC		 7558 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7559 u64 mapping = (u64)tnapi->status_mapping;
7560 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7561 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7562
7563 /* Clear status block in ram. */
7564 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7565
19cfaecc
MC		 7566 if (tnapi->tx_ring) {
7567 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7568 (TG3_TX_RING_SIZE <<
7569 BDINFO_FLAGS_MAXLEN_SHIFT),
7570 NIC_SRAM_TX_BUFFER_DESC);
7571 txrcb += TG3_BDINFO_SIZE;
7572 }
f77a6a8e
MC		 7573
7574 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7575 (TG3_RX_RCB_RING_SIZE(tp) <<
7576 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7577
7578 stblk += 8;
f77a6a8e
MC		 7579 rxrcb += TG3_BDINFO_SIZE;
7580 }
2d31ecaf
MC		 7581}
7582
1da177e4 7583/* tp->lock is held. */
8e7a22e3 7584static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7585{
7586 u32 val, rdmac_mode;
7587 int i, err, limit;
21f581a5 7588 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7589
7590 tg3_disable_ints(tp);
7591
7592 tg3_stop_fw(tp);
7593
7594 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7595
859a5887 7596 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
e6de8ad1 7597 tg3_abort_hw(tp, 1);
1da177e4 7598
603f1173 7599 if (reset_phy)
d4d2c558
MC		 7600 tg3_phy_reset(tp);
7601
1da177e4
LT		 7602 err = tg3_chip_reset(tp);
7603 if (err)
7604 return err;
7605
7606 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7607
bcb37f6c 7608 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7609 val = tr32(TG3_CPMU_CTRL);
7610 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7611 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7612
7613 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7614 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7615 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7616 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7617
7618 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7619 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7620 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7621 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7622
7623 val = tr32(TG3_CPMU_HST_ACC);
7624 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7625 val |= CPMU_HST_ACC_MACCLK_6_25;
7626 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7627 }
7628
33466d93
MC		 7629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7630 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7631 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7632 PCIE_PWR_MGMT_L1_THRESH_4MS;
7633 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7634
7635 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7636 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7637
7638 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7639
f40386c8
MC		 7640 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7641 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7642 }
7643
614b0590
MC		 7644 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7645 u32 grc_mode = tr32(GRC_MODE);
7646
7647 /* Access the lower 1K of PL PCIE block registers. */
7648 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7649 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7650
7651 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7652 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7653 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7654
7655 tw32(GRC_MODE, grc_mode);
7656 }
7657
cea46462
MC		 7658 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7659 u32 grc_mode = tr32(GRC_MODE);
7660
7661 /* Access the lower 1K of PL PCIE block registers. */
7662 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7663 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7664
7665 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7666 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7667 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7668
7669 tw32(GRC_MODE, grc_mode);
a977dbe8
MC		 7670
7671 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7672 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7673 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7674 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 7675 }
7676
1da177e4
LT		 7677 /* This works around an issue with Athlon chipsets on
7678 * B3 tigon3 silicon. This bit has no effect on any
7679 * other revision. But do not set this on PCI Express
795d01c5 7680 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7681 */
795d01c5
MC		 7682 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7683 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7684 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7685 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7686 }
1da177e4
LT		 7687
7688 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7689 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7690 val = tr32(TG3PCI_PCISTATE);
7691 val |= PCISTATE_RETRY_SAME_DMA;
7692 tw32(TG3PCI_PCISTATE, val);
7693 }
7694
0d3031d9
MC		 7695 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7696 /* Allow reads and writes to the
7697 * APE register and memory space.
7698 */
7699 val = tr32(TG3PCI_PCISTATE);
7700 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7701 PCISTATE_ALLOW_APE_SHMEM_WR;
7702 tw32(TG3PCI_PCISTATE, val);
7703 }
7704
1da177e4
LT		 7705 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7706 /* Enable some hw fixes. */
7707 val = tr32(TG3PCI_MSI_DATA);
7708 val |= (1 << 26) | (1 << 28) | (1 << 29);
7709 tw32(TG3PCI_MSI_DATA, val);
7710 }
7711
7712 /* Descriptor ring init may make accesses to the
7713 * NIC SRAM area to setup the TX descriptors, so we
7714 * can only do this after the hardware has been
7715 * successfully reset.
7716 */
32d8c572
MC		 7717 err = tg3_init_rings(tp);
7718 if (err)
7719 return err;
1da177e4 7720
b703df6f
MC		 7721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7723 val = tr32(TG3PCI_DMA_RW_CTRL) &
7724 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
1a319025
MC		 7725 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7726 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
cbf9ca6c
MC		 7727 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7728 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7729 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7730 /* This value is determined during the probe time DMA
7731 * engine test, tg3_test_dma.
7732 */
7733 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7734 }
1da177e4
LT		 7735
7736 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7737 GRC_MODE_4X_NIC_SEND_RINGS |
7738 GRC_MODE_NO_TX_PHDR_CSUM |
7739 GRC_MODE_NO_RX_PHDR_CSUM);
7740 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7741
7742 /* Pseudo-header checksum is done by hardware logic and not
7743 * the offload processers, so make the chip do the pseudo-
7744 * header checksums on receive. For transmit it is more
7745 * convenient to do the pseudo-header checksum in software
7746 * as Linux does that on transmit for us in all cases.
7747 */
7748 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7749
7750 tw32(GRC_MODE,
7751 tp->grc_mode |
7752 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7753
7754 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7755 val = tr32(GRC_MISC_CFG);
7756 val &= ~0xff;
7757 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7758 tw32(GRC_MISC_CFG, val);
7759
7760 /* Initialize MBUF/DESC pool. */
cbf46853 7761 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7762 /* Do nothing. */
7763 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7764 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7765 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7766 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7767 else
7768 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7769 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7770 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
859a5887 7771 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
1da177e4
LT		 7772 int fw_len;
7773
077f849d 7774 fw_len = tp->fw_len;
1da177e4
LT		 7775 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7776 tw32(BUFMGR_MB_POOL_ADDR,
7777 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7778 tw32(BUFMGR_MB_POOL_SIZE,
7779 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7780 }
1da177e4 7781
0f893dc6 7782 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7783 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7784 tp->bufmgr_config.mbuf_read_dma_low_water);
7785 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7786 tp->bufmgr_config.mbuf_mac_rx_low_water);
7787 tw32(BUFMGR_MB_HIGH_WATER,
7788 tp->bufmgr_config.mbuf_high_water);
7789 } else {
7790 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7791 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7792 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7793 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7794 tw32(BUFMGR_MB_HIGH_WATER,
7795 tp->bufmgr_config.mbuf_high_water_jumbo);
7796 }
7797 tw32(BUFMGR_DMA_LOW_WATER,
7798 tp->bufmgr_config.dma_low_water);
7799 tw32(BUFMGR_DMA_HIGH_WATER,
7800 tp->bufmgr_config.dma_high_water);
7801
7802 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7803 for (i = 0; i < 2000; i++) {
7804 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7805 break;
7806 udelay(10);
7807 }
7808 if (i >= 2000) {
05dbe005 7809 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 7810 return -ENODEV;
7811 }
7812
7813 /* Setup replenish threshold. */
f92905de
MC		 7814 val = tp->rx_pending / 8;
7815 if (val == 0)
7816 val = 1;
7817 else if (val > tp->rx_std_max_post)
7818 val = tp->rx_std_max_post;
b5d3772c
MC		 7819 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7820 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7821 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7822
7823 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7824 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7825 }
f92905de
MC		 7826
7827 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7828
7829 /* Initialize TG3_BDINFO's at:
7830 * RCVDBDI_STD_BD: standard eth size rx ring
7831 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7832 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7833 *
7834 * like so:
7835 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7836 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7837 * ring attribute flags
7838 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7839 *
7840 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7841 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7842 *
7843 * The size of each ring is fixed in the firmware, but the location is
7844 * configurable.
7845 */
7846 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7847 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7848 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7849 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7850 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7851 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7852 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7853
fdb72b38
MC		 7854 /* Disable the mini ring */
7855 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7856 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7857 BDINFO_FLAGS_DISABLED);
7858
fdb72b38
MC		 7859 /* Program the jumbo buffer descriptor ring control
7860 * blocks on those devices that have them.
7861 */
8f666b07 7862 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7863 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7864 /* Setup replenish threshold. */
7865 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7866
0f893dc6 7867 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7868 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7869 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7870 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7871 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7872 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7873 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7874 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7875 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7876 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7877 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7878 } else {
7879 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7880 BDINFO_FLAGS_DISABLED);
7881 }
7882
b703df6f
MC		 7883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7885 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7886 (RX_STD_MAX_SIZE << 2);
7887 else
7888 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7889 } else
7890 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7891
7892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7893
411da640 7894 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7895 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7896
411da640 7897 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7898 tp->rx_jumbo_pending : 0;
66711e66 7899 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7900
b703df6f
MC		 7901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7903 tw32(STD_REPLENISH_LWM, 32);
7904 tw32(JMB_REPLENISH_LWM, 16);
7905 }
7906
2d31ecaf
MC		 7907 tg3_rings_reset(tp);
7908
1da177e4 7909 /* Initialize MAC address and backoff seed. */
986e0aeb 7910 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7911
7912 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7913 tw32(MAC_RX_MTU_SIZE,
7914 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7915
7916 /* The slot time is changed by tg3_setup_phy if we
7917 * run at gigabit with half duplex.
7918 */
7919 tw32(MAC_TX_LENGTHS,
7920 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7921 (6 << TX_LENGTHS_IPG_SHIFT) |
7922 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7923
7924 /* Receive rules. */
7925 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7926 tw32(RCVLPC_CONFIG, 0x0181);
7927
7928 /* Calculate RDMAC_MODE setting early, we need it to determine
7929 * the RCVLPC_STATE_ENABLE mask.
7930 */
7931 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7932 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7933 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7934 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7935 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7936
0339e4e3
MC		 7937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7938 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7939
57e6983c 7940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7943 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7944 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7945 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7946
85e94ced
MC		 7947 /* If statement applies to 5705 and 5750 PCI devices only */
7948 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7949 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7950 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7951 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7953 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7954 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7955 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7956 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7957 }
7958 }
7959
85e94ced
MC		 7960 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7961 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7962
1da177e4 7963 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7964 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7965
e849cdc3
MC		 7966 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7969 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7970
7971 /* Receive/send statistics. */
1661394e
MC		 7972 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7973 val = tr32(RCVLPC_STATS_ENABLE);
7974 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7975 tw32(RCVLPC_STATS_ENABLE, val);
7976 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7977 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7978 val = tr32(RCVLPC_STATS_ENABLE);
7979 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7980 tw32(RCVLPC_STATS_ENABLE, val);
7981 } else {
7982 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7983 }
7984 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7985 tw32(SNDDATAI_STATSENAB, 0xffffff);
7986 tw32(SNDDATAI_STATSCTRL,
7987 (SNDDATAI_SCTRL_ENABLE |
7988 SNDDATAI_SCTRL_FASTUPD));
7989
7990 /* Setup host coalescing engine. */
7991 tw32(HOSTCC_MODE, 0);
7992 for (i = 0; i < 2000; i++) {
7993 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7994 break;
7995 udelay(10);
7996 }
7997
d244c892 7998 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7999
1da177e4
LT		 8000 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8001 /* Status/statistics block address. See tg3_timer,
8002 * the tg3_periodic_fetch_stats call there, and
8003 * tg3_get_stats to see how this works for 5705/5750 chips.
8004 */
1da177e4
LT		 8005 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8006 ((u64) tp->stats_mapping >> 32));
8007 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8008 ((u64) tp->stats_mapping & 0xffffffff));
8009 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 8010
1da177e4 8011 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 8012
8013 /* Clear statistics and status block memory areas */
8014 for (i = NIC_SRAM_STATS_BLK;
8015 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8016 i += sizeof(u32)) {
8017 tg3_write_mem(tp, i, 0);
8018 udelay(40);
8019 }
1da177e4
LT		 8020 }
8021
8022 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8023
8024 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8025 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8026 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8027 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8028
c94e3941
MC		 8029 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8030 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8031 /* reset to prevent losing 1st rx packet intermittently */
8032 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8033 udelay(10);
8034 }
8035
3bda1258
MC		 8036 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8037 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8038 else
8039 tp->mac_mode = 0;
8040 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 8041 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 8042 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8043 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8044 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8045 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 8046 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8047 udelay(40);
8048
314fba34 8049 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 8050 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 8051 * register to preserve the GPIO settings for LOMs. The GPIOs,
8052 * whether used as inputs or outputs, are set by boot code after
8053 * reset.
8054 */
9d26e213 8055 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 8056 u32 gpio_mask;
8057
9d26e213
MC		 8058 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8059 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8060 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 8061
8062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8063 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8064 GRC_LCLCTRL_GPIO_OUTPUT3;
8065
af36e6b6
MC		 8066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8067 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8068
aaf84465 8069 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 8070 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8071
8072 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 8073 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8074 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8075 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 8076 }
1da177e4
LT		 8077 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8078 udelay(100);
8079
baf8a94a
MC		 8080 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8081 val = tr32(MSGINT_MODE);
8082 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8083 tw32(MSGINT_MODE, val);
8084 }
8085
1da177e4
LT		 8086 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8087 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8088 udelay(40);
8089 }
8090
8091 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8092 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8093 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8094 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8095 WDMAC_MODE_LNGREAD_ENAB);
8096
85e94ced
MC		 8097 /* If statement applies to 5705 and 5750 PCI devices only */
8098 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8099 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8101 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8102 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8103 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8104 /* nothing */
8105 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8106 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8107 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8108 val |= WDMAC_MODE_RX_ACCEL;
8109 }
8110 }
8111
d9ab5ad1 8112 /* Enable host coalescing bug fix */
321d32a0 8113 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8114 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8115
788a035e
MC		 8116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8117 val |= WDMAC_MODE_BURST_ALL_DATA;
8118
1da177e4
LT		 8119 tw32_f(WDMAC_MODE, val);
8120 udelay(40);
8121
9974a356
MC		 8122 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8123 u16 pcix_cmd;
8124
8125 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8126 &pcix_cmd);
1da177e4 8127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8128 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8129 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8130 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8131 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8132 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8133 }
9974a356
MC		 8134 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8135 pcix_cmd);
1da177e4
LT		 8136 }
8137
8138 tw32_f(RDMAC_MODE, rdmac_mode);
8139 udelay(40);
8140
8141 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8142 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8143 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8144
8145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8146 tw32(SNDDATAC_MODE,
8147 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8148 else
8149 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8150
1da177e4
LT		 8151 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8152 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8153 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8154 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8155 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8156 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8157 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8158 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8159 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8160 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8161 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8162
8163 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8164 err = tg3_load_5701_a0_firmware_fix(tp);
8165 if (err)
8166 return err;
8167 }
8168
1da177e4
LT		 8169 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8170 err = tg3_load_tso_firmware(tp);
8171 if (err)
8172 return err;
8173 }
1da177e4
LT		 8174
8175 tp->tx_mode = TX_MODE_ENABLE;
8176 tw32_f(MAC_TX_MODE, tp->tx_mode);
8177 udelay(100);
8178
baf8a94a
MC		 8179 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8180 u32 reg = MAC_RSS_INDIR_TBL_0;
8181 u8 *ent = (u8 *)&val;
8182
8183 /* Setup the indirection table */
8184 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8185 int idx = i % sizeof(val);
8186
8187 ent[idx] = i % (tp->irq_cnt - 1);
8188 if (idx == sizeof(val) - 1) {
8189 tw32(reg, val);
8190 reg += 4;
8191 }
8192 }
8193
8194 /* Setup the "secret" hash key. */
8195 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8196 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8197 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8198 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8199 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8200 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8201 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8202 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8203 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8204 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8205 }
8206
1da177e4 8207 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8208 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8209 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8210
baf8a94a
MC		 8211 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8212 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8213 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8214 RX_MODE_RSS_IPV6_HASH_EN |
8215 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8216 RX_MODE_RSS_IPV4_HASH_EN |
8217 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8218
1da177e4
LT		 8219 tw32_f(MAC_RX_MODE, tp->rx_mode);
8220 udelay(10);
8221
1da177e4
LT		 8222 tw32(MAC_LED_CTRL, tp->led_ctrl);
8223
8224 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8225 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8226 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8227 udelay(10);
8228 }
8229 tw32_f(MAC_RX_MODE, tp->rx_mode);
8230 udelay(10);
8231
8232 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8233 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8234 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8235 /* Set drive transmission level to 1.2V */
8236 /* only if the signal pre-emphasis bit is not set */
8237 val = tr32(MAC_SERDES_CFG);
8238 val &= 0xfffff000;
8239 val |= 0x880;
8240 tw32(MAC_SERDES_CFG, val);
8241 }
8242 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8243 tw32(MAC_SERDES_CFG, 0x616000);
8244 }
8245
8246 /* Prevent chip from dropping frames when flow control
8247 * is enabled.
8248 */
666bc831
MC		 8249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8250 val = 1;
8251 else
8252 val = 2;
8253 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8254
8255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8256 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8257 /* Use hardware link auto-negotiation */
8258 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8259 }
8260
d4d2c558
MC		 8261 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8262 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8263 u32 tmp;
8264
8265 tmp = tr32(SERDES_RX_CTRL);
8266 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8267 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8268 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8269 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8270 }
8271
dd477003
MC		 8272 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8273 if (tp->link_config.phy_is_low_power) {
8274 tp->link_config.phy_is_low_power = 0;
8275 tp->link_config.speed = tp->link_config.orig_speed;
8276 tp->link_config.duplex = tp->link_config.orig_duplex;
8277 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8278 }
1da177e4 8279
dd477003
MC		 8280 err = tg3_setup_phy(tp, 0);
8281 if (err)
8282 return err;
1da177e4 8283
dd477003 8284 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8285 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8286 u32 tmp;
8287
8288 /* Clear CRC stats. */
8289 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8290 tg3_writephy(tp, MII_TG3_TEST1,
8291 tmp | MII_TG3_TEST1_CRC_EN);
8292 tg3_readphy(tp, 0x14, &tmp);
8293 }
1da177e4
LT		 8294 }
8295 }
8296
8297 __tg3_set_rx_mode(tp->dev);
8298
8299 /* Initialize receive rules. */
8300 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8301 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8302 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8303 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8304
4cf78e4f 8305 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8306 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8307 limit = 8;
8308 else
8309 limit = 16;
8310 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8311 limit -= 4;
8312 switch (limit) {
8313 case 16:
8314 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8315 case 15:
8316 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8317 case 14:
8318 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8319 case 13:
8320 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8321 case 12:
8322 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8323 case 11:
8324 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8325 case 10:
8326 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8327 case 9:
8328 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8329 case 8:
8330 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8331 case 7:
8332 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8333 case 6:
8334 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8335 case 5:
8336 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8337 case 4:
8338 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8339 case 3:
8340 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8341 case 2:
8342 case 1:
8343
8344 default:
8345 break;
855e1111 8346 }
1da177e4 8347
9ce768ea
MC		 8348 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8349 /* Write our heartbeat update interval to APE. */
8350 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8351 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8352
1da177e4
LT		 8353 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8354
1da177e4
LT		 8355 return 0;
8356}
8357
8358/* Called at device open time to get the chip ready for
8359 * packet processing. Invoked with tp->lock held.
8360 */
8e7a22e3 8361static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8362{
1da177e4
LT		 8363 tg3_switch_clocks(tp);
8364
8365 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8366
2f751b67 8367 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8368}
8369
8370#define TG3_STAT_ADD32(PSTAT, REG) \
8371do { u32 __val = tr32(REG); \
8372 (PSTAT)->low += __val; \
8373 if ((PSTAT)->low < __val) \
8374 (PSTAT)->high += 1; \
8375} while (0)
8376
8377static void tg3_periodic_fetch_stats(struct tg3 *tp)
8378{
8379 struct tg3_hw_stats *sp = tp->hw_stats;
8380
8381 if (!netif_carrier_ok(tp->dev))
8382 return;
8383
8384 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8385 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8386 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8387 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8388 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8389 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8390 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8391 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8392 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8393 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8394 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8395 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8396 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8397
8398 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8399 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8400 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8401 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8402 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8403 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8404 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8405 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8406 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8407 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8408 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8409 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8410 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8411 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8412
8413 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8414 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8415 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8416}
8417
8418static void tg3_timer(unsigned long __opaque)
8419{
8420 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8421
f475f163
MC		 8422 if (tp->irq_sync)
8423 goto restart_timer;
8424
f47c11ee 8425 spin_lock(&tp->lock);
1da177e4 8426
fac9b83e
DM		 8427 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8428 /* All of this garbage is because when using non-tagged
8429 * IRQ status the mailbox/status_block protocol the chip
8430 * uses with the cpu is race prone.
8431 */
898a56f8 8432 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8433 tw32(GRC_LOCAL_CTRL,
8434 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8435 } else {
8436 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8437 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8438 }
1da177e4 8439
fac9b83e
DM		 8440 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8441 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8442 spin_unlock(&tp->lock);
fac9b83e
DM		 8443 schedule_work(&tp->reset_task);
8444 return;
8445 }
1da177e4
LT		 8446 }
8447
1da177e4
LT		 8448 /* This part only runs once per second. */
8449 if (!--tp->timer_counter) {
fac9b83e
DM		 8450 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8451 tg3_periodic_fetch_stats(tp);
8452
1da177e4
LT		 8453 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8454 u32 mac_stat;
8455 int phy_event;
8456
8457 mac_stat = tr32(MAC_STATUS);
8458
8459 phy_event = 0;
8460 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8461 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8462 phy_event = 1;
8463 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8464 phy_event = 1;
8465
8466 if (phy_event)
8467 tg3_setup_phy(tp, 0);
8468 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8469 u32 mac_stat = tr32(MAC_STATUS);
8470 int need_setup = 0;
8471
8472 if (netif_carrier_ok(tp->dev) &&
8473 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8474 need_setup = 1;
8475 }
8476 if (! netif_carrier_ok(tp->dev) &&
8477 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8478 MAC_STATUS_SIGNAL_DET))) {
8479 need_setup = 1;
8480 }
8481 if (need_setup) {
3d3ebe74
MC		 8482 if (!tp->serdes_counter) {
8483 tw32_f(MAC_MODE,
8484 (tp->mac_mode &
8485 ~MAC_MODE_PORT_MODE_MASK));
8486 udelay(40);
8487 tw32_f(MAC_MODE, tp->mac_mode);
8488 udelay(40);
8489 }
1da177e4
LT		 8490 tg3_setup_phy(tp, 0);
8491 }
747e8f8b
MC		 8492 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8493 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8494
8495 tp->timer_counter = tp->timer_multiplier;
8496 }
8497
130b8e4d
MC		 8498 /* Heartbeat is only sent once every 2 seconds.
8499 *
8500 * The heartbeat is to tell the ASF firmware that the host
8501 * driver is still alive. In the event that the OS crashes,
8502 * ASF needs to reset the hardware to free up the FIFO space
8503 * that may be filled with rx packets destined for the host.
8504 * If the FIFO is full, ASF will no longer function properly.
8505 *
8506 * Unintended resets have been reported on real time kernels
8507 * where the timer doesn't run on time. Netpoll will also have
8508 * same problem.
8509 *
8510 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8511 * to check the ring condition when the heartbeat is expiring
8512 * before doing the reset. This will prevent most unintended
8513 * resets.
8514 */
1da177e4 8515 if (!--tp->asf_counter) {
bc7959b2
MC		 8516 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8517 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8518 tg3_wait_for_event_ack(tp);
8519
bbadf503 8520 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8521 FWCMD_NICDRV_ALIVE3);
bbadf503 8522 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 8523 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8524 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 8525
8526 tg3_generate_fw_event(tp);
1da177e4
LT		 8527 }
8528 tp->asf_counter = tp->asf_multiplier;
8529 }
8530
f47c11ee 8531 spin_unlock(&tp->lock);
1da177e4 8532
f475f163 8533restart_timer:
1da177e4
LT		 8534 tp->timer.expires = jiffies + tp->timer_offset;
8535 add_timer(&tp->timer);
8536}
8537
4f125f42 8538static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8539{
7d12e780 8540 irq_handler_t fn;
fcfa0a32 8541 unsigned long flags;
4f125f42
MC		 8542 char *name;
8543 struct tg3_napi *tnapi = &tp->napi[irq_num];
8544
8545 if (tp->irq_cnt == 1)
8546 name = tp->dev->name;
8547 else {
8548 name = &tnapi->irq_lbl[0];
8549 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8550 name[IFNAMSIZ-1] = 0;
8551 }
fcfa0a32 8552
679563f4 8553 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8554 fn = tg3_msi;
8555 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8556 fn = tg3_msi_1shot;
1fb9df5d 8557 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8558 } else {
8559 fn = tg3_interrupt;
8560 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8561 fn = tg3_interrupt_tagged;
1fb9df5d 8562 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8563 }
4f125f42
MC		 8564
8565 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8566}
8567
7938109f
MC		 8568static int tg3_test_interrupt(struct tg3 *tp)
8569{
09943a18 8570 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8571 struct net_device *dev = tp->dev;
b16250e3 8572 int err, i, intr_ok = 0;
f6eb9b1f 8573 u32 val;
7938109f 8574
d4bc3927
MC		 8575 if (!netif_running(dev))
8576 return -ENODEV;
8577
7938109f
MC		 8578 tg3_disable_ints(tp);
8579
4f125f42 8580 free_irq(tnapi->irq_vec, tnapi);
7938109f 8581
f6eb9b1f
MC		 8582 /*
8583 * Turn off MSI one shot mode. Otherwise this test has no
8584 * observable way to know whether the interrupt was delivered.
8585 */
b703df6f
MC		 8586 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8588 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8589 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8590 tw32(MSGINT_MODE, val);
8591 }
8592
4f125f42 8593 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8594 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8595 if (err)
8596 return err;
8597
898a56f8 8598 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8599 tg3_enable_ints(tp);
8600
8601 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8602 tnapi->coal_now);
7938109f
MC		 8603
8604 for (i = 0; i < 5; i++) {
b16250e3
MC		 8605 u32 int_mbox, misc_host_ctrl;
8606
898a56f8 8607 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8608 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8609
8610 if ((int_mbox != 0) ||
8611 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8612 intr_ok = 1;
7938109f 8613 break;
b16250e3
MC		 8614 }
8615
7938109f
MC		 8616 msleep(10);
8617 }
8618
8619 tg3_disable_ints(tp);
8620
4f125f42 8621 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8622
4f125f42 8623 err = tg3_request_irq(tp, 0);
7938109f
MC		 8624
8625 if (err)
8626 return err;
8627
f6eb9b1f
MC		 8628 if (intr_ok) {
8629 /* Reenable MSI one shot mode. */
b703df6f
MC		 8630 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8632 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8633 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8634 tw32(MSGINT_MODE, val);
8635 }
7938109f 8636 return 0;
f6eb9b1f 8637 }
7938109f
MC		 8638
8639 return -EIO;
8640}
8641
8642/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8643 * successfully restored
8644 */
8645static int tg3_test_msi(struct tg3 *tp)
8646{
7938109f
MC		 8647 int err;
8648 u16 pci_cmd;
8649
8650 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8651 return 0;
8652
8653 /* Turn off SERR reporting in case MSI terminates with Master
8654 * Abort.
8655 */
8656 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8657 pci_write_config_word(tp->pdev, PCI_COMMAND,
8658 pci_cmd & ~PCI_COMMAND_SERR);
8659
8660 err = tg3_test_interrupt(tp);
8661
8662 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8663
8664 if (!err)
8665 return 0;
8666
8667 /* other failures */
8668 if (err != -EIO)
8669 return err;
8670
8671 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 8672 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8673 "to INTx mode. Please report this failure to the PCI "
8674 "maintainer and include system chipset information\n");
7938109f 8675
4f125f42 8676 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8677
7938109f
MC		 8678 pci_disable_msi(tp->pdev);
8679
8680 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8681
4f125f42 8682 err = tg3_request_irq(tp, 0);
7938109f
MC		 8683 if (err)
8684 return err;
8685
8686 /* Need to reset the chip because the MSI cycle may have terminated
8687 * with Master Abort.
8688 */
f47c11ee 8689 tg3_full_lock(tp, 1);
7938109f 8690
944d980e 8691 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8692 err = tg3_init_hw(tp, 1);
7938109f 8693
f47c11ee 8694 tg3_full_unlock(tp);
7938109f
MC		 8695
8696 if (err)
4f125f42 8697 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8698
8699 return err;
8700}
8701
9e9fd12d
MC		 8702static int tg3_request_firmware(struct tg3 *tp)
8703{
8704 const __be32 *fw_data;
8705
8706 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 8707 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8708 tp->fw_needed);
9e9fd12d
MC		 8709 return -ENOENT;
8710 }
8711
8712 fw_data = (void *)tp->fw->data;
8713
8714 /* Firmware blob starts with version numbers, followed by
8715 * start address and _full_ length including BSS sections
8716 * (which must be longer than the actual data, of course
8717 */
8718
8719 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8720 if (tp->fw_len < (tp->fw->size - 12)) {
05dbe005
JP		 8721 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8722 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 8723 release_firmware(tp->fw);
8724 tp->fw = NULL;
8725 return -EINVAL;
8726 }
8727
8728 /* We no longer need firmware; we have it. */
8729 tp->fw_needed = NULL;
8730 return 0;
8731}
8732
679563f4
MC		 8733static bool tg3_enable_msix(struct tg3 *tp)
8734{
8735 int i, rc, cpus = num_online_cpus();
8736 struct msix_entry msix_ent[tp->irq_max];
8737
8738 if (cpus == 1)
8739 /* Just fallback to the simpler MSI mode. */
8740 return false;
8741
8742 /*
8743 * We want as many rx rings enabled as there are cpus.
8744 * The first MSIX vector only deals with link interrupts, etc,
8745 * so we add one to the number of vectors we are requesting.
8746 */
8747 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8748
8749 for (i = 0; i < tp->irq_max; i++) {
8750 msix_ent[i].entry = i;
8751 msix_ent[i].vector = 0;
8752 }
8753
8754 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8755 if (rc != 0) {
8756 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8757 return false;
8758 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8759 return false;
05dbe005
JP		 8760 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8761 tp->irq_cnt, rc);
679563f4
MC		 8762 tp->irq_cnt = rc;
8763 }
8764
baf8a94a
MC		 8765 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8766
679563f4
MC		 8767 for (i = 0; i < tp->irq_max; i++)
8768 tp->napi[i].irq_vec = msix_ent[i].vector;
8769
19cfaecc
MC		 8770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8771 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8772 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8773 } else
8774 tp->dev->real_num_tx_queues = 1;
fe5f5787 8775
679563f4
MC		 8776 return true;
8777}
8778
07b0173c
MC		 8779static void tg3_ints_init(struct tg3 *tp)
8780{
679563f4
MC		 8781 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8782 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8783 /* All MSI supporting chips should support tagged
8784 * status. Assert that this is the case.
8785 */
5129c3a3
MC		 8786 netdev_warn(tp->dev,
8787 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 8788 goto defcfg;
07b0173c 8789 }
4f125f42 8790
679563f4
MC		 8791 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8792 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8793 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8794 pci_enable_msi(tp->pdev) == 0)
8795 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8796
8797 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8798 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8799 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8800 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8801 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8802 }
8803defcfg:
8804 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8805 tp->irq_cnt = 1;
8806 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8807 tp->dev->real_num_tx_queues = 1;
679563f4 8808 }
07b0173c
MC		 8809}
8810
8811static void tg3_ints_fini(struct tg3 *tp)
8812{
679563f4
MC		 8813 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8814 pci_disable_msix(tp->pdev);
8815 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8816 pci_disable_msi(tp->pdev);
8817 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8818 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8819}
8820
1da177e4
LT		 8821static int tg3_open(struct net_device *dev)
8822{
8823 struct tg3 *tp = netdev_priv(dev);
4f125f42 8824 int i, err;
1da177e4 8825
9e9fd12d
MC		 8826 if (tp->fw_needed) {
8827 err = tg3_request_firmware(tp);
8828 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8829 if (err)
8830 return err;
8831 } else if (err) {
05dbe005 8832 netdev_warn(tp->dev, "TSO capability disabled\n");
9e9fd12d
MC		 8833 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8834 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
05dbe005 8835 netdev_notice(tp->dev, "TSO capability restored\n");
9e9fd12d
MC		 8836 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8837 }
8838 }
8839
c49a1561
MC		 8840 netif_carrier_off(tp->dev);
8841
bc1c7567 8842 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8843 if (err)
bc1c7567 8844 return err;
2f751b67
MC		 8845
8846 tg3_full_lock(tp, 0);
bc1c7567 8847
1da177e4
LT		 8848 tg3_disable_ints(tp);
8849 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8850
f47c11ee 8851 tg3_full_unlock(tp);
1da177e4 8852
679563f4
MC		 8853 /*
8854 * Setup interrupts first so we know how
8855 * many NAPI resources to allocate
8856 */
8857 tg3_ints_init(tp);
8858
1da177e4
LT		 8859 /* The placement of this call is tied
8860 * to the setup and use of Host TX descriptors.
8861 */
8862 err = tg3_alloc_consistent(tp);
8863 if (err)
679563f4 8864 goto err_out1;
88b06bc2 8865
fed97810 8866 tg3_napi_enable(tp);
1da177e4 8867
4f125f42
MC		 8868 for (i = 0; i < tp->irq_cnt; i++) {
8869 struct tg3_napi *tnapi = &tp->napi[i];
8870 err = tg3_request_irq(tp, i);
8871 if (err) {
8872 for (i--; i >= 0; i--)
8873 free_irq(tnapi->irq_vec, tnapi);
8874 break;
8875 }
8876 }
1da177e4 8877
07b0173c 8878 if (err)
679563f4 8879 goto err_out2;
bea3348e 8880
f47c11ee 8881 tg3_full_lock(tp, 0);
1da177e4 8882
8e7a22e3 8883 err = tg3_init_hw(tp, 1);
1da177e4 8884 if (err) {
944d980e 8885 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8886 tg3_free_rings(tp);
8887 } else {
fac9b83e
DM		 8888 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8889 tp->timer_offset = HZ;
8890 else
8891 tp->timer_offset = HZ / 10;
8892
8893 BUG_ON(tp->timer_offset > HZ);
8894 tp->timer_counter = tp->timer_multiplier =
8895 (HZ / tp->timer_offset);
8896 tp->asf_counter = tp->asf_multiplier =
28fbef78 8897 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8898
8899 init_timer(&tp->timer);
8900 tp->timer.expires = jiffies + tp->timer_offset;
8901 tp->timer.data = (unsigned long) tp;
8902 tp->timer.function = tg3_timer;
1da177e4
LT		 8903 }
8904
f47c11ee 8905 tg3_full_unlock(tp);
1da177e4 8906
07b0173c 8907 if (err)
679563f4 8908 goto err_out3;
1da177e4 8909
7938109f
MC		 8910 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8911 err = tg3_test_msi(tp);
fac9b83e 8912
7938109f 8913 if (err) {
f47c11ee 8914 tg3_full_lock(tp, 0);
944d980e 8915 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8916 tg3_free_rings(tp);
f47c11ee 8917 tg3_full_unlock(tp);
7938109f 8918
679563f4 8919 goto err_out2;
7938109f 8920 }
fcfa0a32 8921
f6eb9b1f 8922 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8923 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8924 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8925 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8926 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8927
f6eb9b1f
MC		 8928 tw32(PCIE_TRANSACTION_CFG,
8929 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8930 }
7938109f
MC		 8931 }
8932
b02fd9e3
MC		 8933 tg3_phy_start(tp);
8934
f47c11ee 8935 tg3_full_lock(tp, 0);
1da177e4 8936
7938109f
MC		 8937 add_timer(&tp->timer);
8938 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8939 tg3_enable_ints(tp);
8940
f47c11ee 8941 tg3_full_unlock(tp);
1da177e4 8942
fe5f5787 8943 netif_tx_start_all_queues(dev);
1da177e4
LT		 8944
8945 return 0;
07b0173c 8946
679563f4 8947err_out3:
4f125f42
MC		 8948 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8949 struct tg3_napi *tnapi = &tp->napi[i];
8950 free_irq(tnapi->irq_vec, tnapi);
8951 }
07b0173c 8952
679563f4 8953err_out2:
fed97810 8954 tg3_napi_disable(tp);
07b0173c 8955 tg3_free_consistent(tp);
679563f4
MC		 8956
8957err_out1:
8958 tg3_ints_fini(tp);
07b0173c 8959 return err;
1da177e4
LT		 8960}
8961
1da177e4
LT		 8962static struct net_device_stats *tg3_get_stats(struct net_device *);
8963static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8964
8965static int tg3_close(struct net_device *dev)
8966{
4f125f42 8967 int i;
1da177e4
LT		 8968 struct tg3 *tp = netdev_priv(dev);
8969
fed97810 8970 tg3_napi_disable(tp);
28e53bdd 8971 cancel_work_sync(&tp->reset_task);
7faa006f 8972
fe5f5787 8973 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8974
8975 del_timer_sync(&tp->timer);
8976
24bb4fb6
MC		 8977 tg3_phy_stop(tp);
8978
f47c11ee 8979 tg3_full_lock(tp, 1);
1da177e4
LT		 8980
8981 tg3_disable_ints(tp);
8982
944d980e 8983 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8984 tg3_free_rings(tp);
5cf64b8a 8985 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8986
f47c11ee 8987 tg3_full_unlock(tp);
1da177e4 8988
4f125f42
MC		 8989 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8990 struct tg3_napi *tnapi = &tp->napi[i];
8991 free_irq(tnapi->irq_vec, tnapi);
8992 }
07b0173c
MC		 8993
8994 tg3_ints_fini(tp);
1da177e4
LT		 8995
8996 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8997 sizeof(tp->net_stats_prev));
8998 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8999 sizeof(tp->estats_prev));
9000
9001 tg3_free_consistent(tp);
9002
bc1c7567
MC		 9003 tg3_set_power_state(tp, PCI_D3hot);
9004
9005 netif_carrier_off(tp->dev);
9006
1da177e4
LT		 9007 return 0;
9008}
9009
9010static inline unsigned long get_stat64(tg3_stat64_t *val)
9011{
9012 unsigned long ret;
9013
9014#if (BITS_PER_LONG == 32)
9015 ret = val->low;
9016#else
9017 ret = ((u64)val->high << 32) | ((u64)val->low);
9018#endif
9019 return ret;
9020}
9021
816f8b86
SB		 9022static inline u64 get_estat64(tg3_stat64_t *val)
9023{
9024 return ((u64)val->high << 32) | ((u64)val->low);
9025}
9026
1da177e4
LT		 9027static unsigned long calc_crc_errors(struct tg3 *tp)
9028{
9029 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9030
9031 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9032 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9034 u32 val;
9035
f47c11ee 9036 spin_lock_bh(&tp->lock);
569a5df8
MC		 9037 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9038 tg3_writephy(tp, MII_TG3_TEST1,
9039 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9040 tg3_readphy(tp, 0x14, &val);
9041 } else
9042 val = 0;
f47c11ee 9043 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9044
9045 tp->phy_crc_errors += val;
9046
9047 return tp->phy_crc_errors;
9048 }
9049
9050 return get_stat64(&hw_stats->rx_fcs_errors);
9051}
9052
9053#define ESTAT_ADD(member) \
9054 estats->member = old_estats->member + \
816f8b86 9055 get_estat64(&hw_stats->member)
1da177e4
LT		 9056
9057static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9058{
9059 struct tg3_ethtool_stats *estats = &tp->estats;
9060 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9061 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9062
9063 if (!hw_stats)
9064 return old_estats;
9065
9066 ESTAT_ADD(rx_octets);
9067 ESTAT_ADD(rx_fragments);
9068 ESTAT_ADD(rx_ucast_packets);
9069 ESTAT_ADD(rx_mcast_packets);
9070 ESTAT_ADD(rx_bcast_packets);
9071 ESTAT_ADD(rx_fcs_errors);
9072 ESTAT_ADD(rx_align_errors);
9073 ESTAT_ADD(rx_xon_pause_rcvd);
9074 ESTAT_ADD(rx_xoff_pause_rcvd);
9075 ESTAT_ADD(rx_mac_ctrl_rcvd);
9076 ESTAT_ADD(rx_xoff_entered);
9077 ESTAT_ADD(rx_frame_too_long_errors);
9078 ESTAT_ADD(rx_jabbers);
9079 ESTAT_ADD(rx_undersize_packets);
9080 ESTAT_ADD(rx_in_length_errors);
9081 ESTAT_ADD(rx_out_length_errors);
9082 ESTAT_ADD(rx_64_or_less_octet_packets);
9083 ESTAT_ADD(rx_65_to_127_octet_packets);
9084 ESTAT_ADD(rx_128_to_255_octet_packets);
9085 ESTAT_ADD(rx_256_to_511_octet_packets);
9086 ESTAT_ADD(rx_512_to_1023_octet_packets);
9087 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9088 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9089 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9090 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9091 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9092
9093 ESTAT_ADD(tx_octets);
9094 ESTAT_ADD(tx_collisions);
9095 ESTAT_ADD(tx_xon_sent);
9096 ESTAT_ADD(tx_xoff_sent);
9097 ESTAT_ADD(tx_flow_control);
9098 ESTAT_ADD(tx_mac_errors);
9099 ESTAT_ADD(tx_single_collisions);
9100 ESTAT_ADD(tx_mult_collisions);
9101 ESTAT_ADD(tx_deferred);
9102 ESTAT_ADD(tx_excessive_collisions);
9103 ESTAT_ADD(tx_late_collisions);
9104 ESTAT_ADD(tx_collide_2times);
9105 ESTAT_ADD(tx_collide_3times);
9106 ESTAT_ADD(tx_collide_4times);
9107 ESTAT_ADD(tx_collide_5times);
9108 ESTAT_ADD(tx_collide_6times);
9109 ESTAT_ADD(tx_collide_7times);
9110 ESTAT_ADD(tx_collide_8times);
9111 ESTAT_ADD(tx_collide_9times);
9112 ESTAT_ADD(tx_collide_10times);
9113 ESTAT_ADD(tx_collide_11times);
9114 ESTAT_ADD(tx_collide_12times);
9115 ESTAT_ADD(tx_collide_13times);
9116 ESTAT_ADD(tx_collide_14times);
9117 ESTAT_ADD(tx_collide_15times);
9118 ESTAT_ADD(tx_ucast_packets);
9119 ESTAT_ADD(tx_mcast_packets);
9120 ESTAT_ADD(tx_bcast_packets);
9121 ESTAT_ADD(tx_carrier_sense_errors);
9122 ESTAT_ADD(tx_discards);
9123 ESTAT_ADD(tx_errors);
9124
9125 ESTAT_ADD(dma_writeq_full);
9126 ESTAT_ADD(dma_write_prioq_full);
9127 ESTAT_ADD(rxbds_empty);
9128 ESTAT_ADD(rx_discards);
9129 ESTAT_ADD(rx_errors);
9130 ESTAT_ADD(rx_threshold_hit);
9131
9132 ESTAT_ADD(dma_readq_full);
9133 ESTAT_ADD(dma_read_prioq_full);
9134 ESTAT_ADD(tx_comp_queue_full);
9135
9136 ESTAT_ADD(ring_set_send_prod_index);
9137 ESTAT_ADD(ring_status_update);
9138 ESTAT_ADD(nic_irqs);
9139 ESTAT_ADD(nic_avoided_irqs);
9140 ESTAT_ADD(nic_tx_threshold_hit);
9141
9142 return estats;
9143}
9144
9145static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9146{
9147 struct tg3 *tp = netdev_priv(dev);
9148 struct net_device_stats *stats = &tp->net_stats;
9149 struct net_device_stats *old_stats = &tp->net_stats_prev;
9150 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9151
9152 if (!hw_stats)
9153 return old_stats;
9154
9155 stats->rx_packets = old_stats->rx_packets +
9156 get_stat64(&hw_stats->rx_ucast_packets) +
9157 get_stat64(&hw_stats->rx_mcast_packets) +
9158 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9159
1da177e4
LT		 9160 stats->tx_packets = old_stats->tx_packets +
9161 get_stat64(&hw_stats->tx_ucast_packets) +
9162 get_stat64(&hw_stats->tx_mcast_packets) +
9163 get_stat64(&hw_stats->tx_bcast_packets);
9164
9165 stats->rx_bytes = old_stats->rx_bytes +
9166 get_stat64(&hw_stats->rx_octets);
9167 stats->tx_bytes = old_stats->tx_bytes +
9168 get_stat64(&hw_stats->tx_octets);
9169
9170 stats->rx_errors = old_stats->rx_errors +
4f63b877 9171 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9172 stats->tx_errors = old_stats->tx_errors +
9173 get_stat64(&hw_stats->tx_errors) +
9174 get_stat64(&hw_stats->tx_mac_errors) +
9175 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9176 get_stat64(&hw_stats->tx_discards);
9177
9178 stats->multicast = old_stats->multicast +
9179 get_stat64(&hw_stats->rx_mcast_packets);
9180 stats->collisions = old_stats->collisions +
9181 get_stat64(&hw_stats->tx_collisions);
9182
9183 stats->rx_length_errors = old_stats->rx_length_errors +
9184 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9185 get_stat64(&hw_stats->rx_undersize_packets);
9186
9187 stats->rx_over_errors = old_stats->rx_over_errors +
9188 get_stat64(&hw_stats->rxbds_empty);
9189 stats->rx_frame_errors = old_stats->rx_frame_errors +
9190 get_stat64(&hw_stats->rx_align_errors);
9191 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9192 get_stat64(&hw_stats->tx_discards);
9193 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9194 get_stat64(&hw_stats->tx_carrier_sense_errors);
9195
9196 stats->rx_crc_errors = old_stats->rx_crc_errors +
9197 calc_crc_errors(tp);
9198
4f63b877
JL		 9199 stats->rx_missed_errors = old_stats->rx_missed_errors +
9200 get_stat64(&hw_stats->rx_discards);
9201
1da177e4
LT		 9202 return stats;
9203}
9204
9205static inline u32 calc_crc(unsigned char *buf, int len)
9206{
9207 u32 reg;
9208 u32 tmp;
9209 int j, k;
9210
9211 reg = 0xffffffff;
9212
9213 for (j = 0; j < len; j++) {
9214 reg ^= buf[j];
9215
9216 for (k = 0; k < 8; k++) {
9217 tmp = reg & 0x01;
9218
9219 reg >>= 1;
9220
859a5887 9221 if (tmp)
1da177e4 9222 reg ^= 0xedb88320;
1da177e4
LT		 9223 }
9224 }
9225
9226 return ~reg;
9227}
9228
9229static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9230{
9231 /* accept or reject all multicast frames */
9232 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9233 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9234 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9235 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9236}
9237
9238static void __tg3_set_rx_mode(struct net_device *dev)
9239{
9240 struct tg3 *tp = netdev_priv(dev);
9241 u32 rx_mode;
9242
9243 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9244 RX_MODE_KEEP_VLAN_TAG);
9245
9246 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9247 * flag clear.
9248 */
9249#if TG3_VLAN_TAG_USED
9250 if (!tp->vlgrp &&
9251 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9252 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9253#else
9254 /* By definition, VLAN is disabled always in this
9255 * case.
9256 */
9257 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9258 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9259#endif
9260
9261 if (dev->flags & IFF_PROMISC) {
9262 /* Promiscuous mode. */
9263 rx_mode |= RX_MODE_PROMISC;
9264 } else if (dev->flags & IFF_ALLMULTI) {
9265 /* Accept all multicast. */
9266 tg3_set_multi (tp, 1);
4cd24eaf 9267 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 9268 /* Reject all multicast. */
9269 tg3_set_multi (tp, 0);
9270 } else {
9271 /* Accept one or more multicast(s). */
22bedad3 9272 struct netdev_hw_addr *ha;
1da177e4
LT		 9273 u32 mc_filter[4] = { 0, };
9274 u32 regidx;
9275 u32 bit;
9276 u32 crc;
9277
22bedad3
JP		 9278 netdev_for_each_mc_addr(ha, dev) {
9279 crc = calc_crc(ha->addr, ETH_ALEN);
1da177e4
LT		 9280 bit = ~crc & 0x7f;
9281 regidx = (bit & 0x60) >> 5;
9282 bit &= 0x1f;
9283 mc_filter[regidx] |= (1 << bit);
9284 }
9285
9286 tw32(MAC_HASH_REG_0, mc_filter[0]);
9287 tw32(MAC_HASH_REG_1, mc_filter[1]);
9288 tw32(MAC_HASH_REG_2, mc_filter[2]);
9289 tw32(MAC_HASH_REG_3, mc_filter[3]);
9290 }
9291
9292 if (rx_mode != tp->rx_mode) {
9293 tp->rx_mode = rx_mode;
9294 tw32_f(MAC_RX_MODE, rx_mode);
9295 udelay(10);
9296 }
9297}
9298
9299static void tg3_set_rx_mode(struct net_device *dev)
9300{
9301 struct tg3 *tp = netdev_priv(dev);
9302
e75f7c90
MC		 9303 if (!netif_running(dev))
9304 return;
9305
f47c11ee 9306 tg3_full_lock(tp, 0);
1da177e4 9307 __tg3_set_rx_mode(dev);
f47c11ee 9308 tg3_full_unlock(tp);
1da177e4
LT		 9309}
9310
9311#define TG3_REGDUMP_LEN (32 * 1024)
9312
9313static int tg3_get_regs_len(struct net_device *dev)
9314{
9315 return TG3_REGDUMP_LEN;
9316}
9317
9318static void tg3_get_regs(struct net_device *dev,
9319 struct ethtool_regs *regs, void *_p)
9320{
9321 u32 *p = _p;
9322 struct tg3 *tp = netdev_priv(dev);
9323 u8 *orig_p = _p;
9324 int i;
9325
9326 regs->version = 0;
9327
9328 memset(p, 0, TG3_REGDUMP_LEN);
9329
bc1c7567
MC		 9330 if (tp->link_config.phy_is_low_power)
9331 return;
9332
f47c11ee 9333 tg3_full_lock(tp, 0);
1da177e4
LT		 9334
9335#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9336#define GET_REG32_LOOP(base,len) \
9337do { p = (u32 *)(orig_p + (base)); \
9338 for (i = 0; i < len; i += 4) \
9339 __GET_REG32((base) + i); \
9340} while (0)
9341#define GET_REG32_1(reg) \
9342do { p = (u32 *)(orig_p + (reg)); \
9343 __GET_REG32((reg)); \
9344} while (0)
9345
9346 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9347 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9348 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9349 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9350 GET_REG32_1(SNDDATAC_MODE);
9351 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9352 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9353 GET_REG32_1(SNDBDC_MODE);
9354 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9355 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9356 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9357 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9358 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9359 GET_REG32_1(RCVDCC_MODE);
9360 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9361 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9362 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9363 GET_REG32_1(MBFREE_MODE);
9364 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9365 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9366 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9367 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9368 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9369 GET_REG32_1(RX_CPU_MODE);
9370 GET_REG32_1(RX_CPU_STATE);
9371 GET_REG32_1(RX_CPU_PGMCTR);
9372 GET_REG32_1(RX_CPU_HWBKPT);
9373 GET_REG32_1(TX_CPU_MODE);
9374 GET_REG32_1(TX_CPU_STATE);
9375 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9376 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9377 GET_REG32_LOOP(FTQ_RESET, 0x120);
9378 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9379 GET_REG32_1(DMAC_MODE);
9380 GET_REG32_LOOP(GRC_MODE, 0x4c);
9381 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9382 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9383
9384#undef __GET_REG32
9385#undef GET_REG32_LOOP
9386#undef GET_REG32_1
9387
f47c11ee 9388 tg3_full_unlock(tp);
1da177e4
LT		 9389}
9390
9391static int tg3_get_eeprom_len(struct net_device *dev)
9392{
9393 struct tg3 *tp = netdev_priv(dev);
9394
9395 return tp->nvram_size;
9396}
9397
1da177e4
LT		 9398static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9399{
9400 struct tg3 *tp = netdev_priv(dev);
9401 int ret;
9402 u8 *pd;
b9fc7dc5 9403 u32 i, offset, len, b_offset, b_count;
a9dc529d 9404 __be32 val;
1da177e4 9405
df259d8c
MC		 9406 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9407 return -EINVAL;
9408
bc1c7567
MC		 9409 if (tp->link_config.phy_is_low_power)
9410 return -EAGAIN;
9411
1da177e4
LT		 9412 offset = eeprom->offset;
9413 len = eeprom->len;
9414 eeprom->len = 0;
9415
9416 eeprom->magic = TG3_EEPROM_MAGIC;
9417
9418 if (offset & 3) {
9419 /* adjustments to start on required 4 byte boundary */
9420 b_offset = offset & 3;
9421 b_count = 4 - b_offset;
9422 if (b_count > len) {
9423 /* i.e. offset=1 len=2 */
9424 b_count = len;
9425 }
a9dc529d 9426 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9427 if (ret)
9428 return ret;
1da177e4
LT		 9429 memcpy(data, ((char*)&val) + b_offset, b_count);
9430 len -= b_count;
9431 offset += b_count;
c6cdf436 9432 eeprom->len += b_count;
1da177e4
LT		 9433 }
9434
9435 /* read bytes upto the last 4 byte boundary */
9436 pd = &data[eeprom->len];
9437 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9438 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9439 if (ret) {
9440 eeprom->len += i;
9441 return ret;
9442 }
1da177e4
LT		 9443 memcpy(pd + i, &val, 4);
9444 }
9445 eeprom->len += i;
9446
9447 if (len & 3) {
9448 /* read last bytes not ending on 4 byte boundary */
9449 pd = &data[eeprom->len];
9450 b_count = len & 3;
9451 b_offset = offset + len - b_count;
a9dc529d 9452 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9453 if (ret)
9454 return ret;
b9fc7dc5 9455 memcpy(pd, &val, b_count);
1da177e4
LT		 9456 eeprom->len += b_count;
9457 }
9458 return 0;
9459}
9460
6aa20a22 9461static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9462
9463static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9464{
9465 struct tg3 *tp = netdev_priv(dev);
9466 int ret;
b9fc7dc5 9467 u32 offset, len, b_offset, odd_len;
1da177e4 9468 u8 *buf;
a9dc529d 9469 __be32 start, end;
1da177e4 9470
bc1c7567
MC		 9471 if (tp->link_config.phy_is_low_power)
9472 return -EAGAIN;
9473
df259d8c
MC		 9474 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9475 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9476 return -EINVAL;
9477
9478 offset = eeprom->offset;
9479 len = eeprom->len;
9480
9481 if ((b_offset = (offset & 3))) {
9482 /* adjustments to start on required 4 byte boundary */
a9dc529d 9483 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9484 if (ret)
9485 return ret;
1da177e4
LT		 9486 len += b_offset;
9487 offset &= ~3;
1c8594b4
MC		 9488 if (len < 4)
9489 len = 4;
1da177e4
LT		 9490 }
9491
9492 odd_len = 0;
1c8594b4 9493 if (len & 3) {
1da177e4
LT		 9494 /* adjustments to end on required 4 byte boundary */
9495 odd_len = 1;
9496 len = (len + 3) & ~3;
a9dc529d 9497 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9498 if (ret)
9499 return ret;
1da177e4
LT		 9500 }
9501
9502 buf = data;
9503 if (b_offset || odd_len) {
9504 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9505 if (!buf)
1da177e4
LT		 9506 return -ENOMEM;
9507 if (b_offset)
9508 memcpy(buf, &start, 4);
9509 if (odd_len)
9510 memcpy(buf+len-4, &end, 4);
9511 memcpy(buf + b_offset, data, eeprom->len);
9512 }
9513
9514 ret = tg3_nvram_write_block(tp, offset, len, buf);
9515
9516 if (buf != data)
9517 kfree(buf);
9518
9519 return ret;
9520}
9521
9522static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9523{
b02fd9e3
MC		 9524 struct tg3 *tp = netdev_priv(dev);
9525
9526 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9527 struct phy_device *phydev;
b02fd9e3
MC		 9528 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9529 return -EAGAIN;
3f0e3ad7
MC		 9530 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9531 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9532 }
6aa20a22 9533
1da177e4
LT		 9534 cmd->supported = (SUPPORTED_Autoneg);
9535
9536 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9537 cmd->supported |= (SUPPORTED_1000baseT_Half |
9538 SUPPORTED_1000baseT_Full);
9539
ef348144 9540 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9541 cmd->supported |= (SUPPORTED_100baseT_Half |
9542 SUPPORTED_100baseT_Full |
9543 SUPPORTED_10baseT_Half |
9544 SUPPORTED_10baseT_Full |
3bebab59 9545 SUPPORTED_TP);
ef348144
KK		 9546 cmd->port = PORT_TP;
9547 } else {
1da177e4 9548 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9549 cmd->port = PORT_FIBRE;
9550 }
6aa20a22 9551
1da177e4
LT		 9552 cmd->advertising = tp->link_config.advertising;
9553 if (netif_running(dev)) {
9554 cmd->speed = tp->link_config.active_speed;
9555 cmd->duplex = tp->link_config.active_duplex;
9556 }
882e9793 9557 cmd->phy_address = tp->phy_addr;
7e5856bd 9558 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9559 cmd->autoneg = tp->link_config.autoneg;
9560 cmd->maxtxpkt = 0;
9561 cmd->maxrxpkt = 0;
9562 return 0;
9563}
6aa20a22 9564
1da177e4
LT		 9565static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9566{
9567 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9568
b02fd9e3 9569 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9570 struct phy_device *phydev;
b02fd9e3
MC		 9571 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9572 return -EAGAIN;
3f0e3ad7
MC		 9573 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9574 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9575 }
9576
7e5856bd
MC		 9577 if (cmd->autoneg != AUTONEG_ENABLE &&
9578 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9579 return -EINVAL;
7e5856bd
MC		 9580
9581 if (cmd->autoneg == AUTONEG_DISABLE &&
9582 cmd->duplex != DUPLEX_FULL &&
9583 cmd->duplex != DUPLEX_HALF)
37ff238d 9584 return -EINVAL;
1da177e4 9585
7e5856bd
MC		 9586 if (cmd->autoneg == AUTONEG_ENABLE) {
9587 u32 mask = ADVERTISED_Autoneg |
9588 ADVERTISED_Pause |
9589 ADVERTISED_Asym_Pause;
9590
3f07d129 9591 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7e5856bd
MC		 9592 mask |= ADVERTISED_1000baseT_Half |
9593 ADVERTISED_1000baseT_Full;
9594
9595 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9596 mask |= ADVERTISED_100baseT_Half |
9597 ADVERTISED_100baseT_Full |
9598 ADVERTISED_10baseT_Half |
9599 ADVERTISED_10baseT_Full |
9600 ADVERTISED_TP;
9601 else
9602 mask |= ADVERTISED_FIBRE;
9603
9604 if (cmd->advertising & ~mask)
9605 return -EINVAL;
9606
9607 mask &= (ADVERTISED_1000baseT_Half |
9608 ADVERTISED_1000baseT_Full |
9609 ADVERTISED_100baseT_Half |
9610 ADVERTISED_100baseT_Full |
9611 ADVERTISED_10baseT_Half |
9612 ADVERTISED_10baseT_Full);
9613
9614 cmd->advertising &= mask;
9615 } else {
9616 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9617 if (cmd->speed != SPEED_1000)
9618 return -EINVAL;
9619
9620 if (cmd->duplex != DUPLEX_FULL)
9621 return -EINVAL;
9622 } else {
9623 if (cmd->speed != SPEED_100 &&
9624 cmd->speed != SPEED_10)
9625 return -EINVAL;
9626 }
9627 }
9628
f47c11ee 9629 tg3_full_lock(tp, 0);
1da177e4
LT		 9630
9631 tp->link_config.autoneg = cmd->autoneg;
9632 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9633 tp->link_config.advertising = (cmd->advertising |
9634 ADVERTISED_Autoneg);
1da177e4
LT		 9635 tp->link_config.speed = SPEED_INVALID;
9636 tp->link_config.duplex = DUPLEX_INVALID;
9637 } else {
9638 tp->link_config.advertising = 0;
9639 tp->link_config.speed = cmd->speed;
9640 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9641 }
6aa20a22 9642
24fcad6b
MC		 9643 tp->link_config.orig_speed = tp->link_config.speed;
9644 tp->link_config.orig_duplex = tp->link_config.duplex;
9645 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9646
1da177e4
LT		 9647 if (netif_running(dev))
9648 tg3_setup_phy(tp, 1);
9649
f47c11ee 9650 tg3_full_unlock(tp);
6aa20a22 9651
1da177e4
LT		 9652 return 0;
9653}
6aa20a22 9654
1da177e4
LT		 9655static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9656{
9657 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9658
1da177e4
LT		 9659 strcpy(info->driver, DRV_MODULE_NAME);
9660 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9661 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9662 strcpy(info->bus_info, pci_name(tp->pdev));
9663}
6aa20a22 9664
1da177e4
LT		 9665static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9666{
9667 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9668
12dac075
RW		 9669 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9670 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9671 wol->supported = WAKE_MAGIC;
9672 else
9673 wol->supported = 0;
1da177e4 9674 wol->wolopts = 0;
05ac4cb7
MC		 9675 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9676 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9677 wol->wolopts = WAKE_MAGIC;
9678 memset(&wol->sopass, 0, sizeof(wol->sopass));
9679}
6aa20a22 9680
1da177e4
LT		 9681static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9682{
9683 struct tg3 *tp = netdev_priv(dev);
12dac075 9684 struct device *dp = &tp->pdev->dev;
6aa20a22 9685
1da177e4
LT		 9686 if (wol->wolopts & ~WAKE_MAGIC)
9687 return -EINVAL;
9688 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9689 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9690 return -EINVAL;
6aa20a22 9691
f47c11ee 9692 spin_lock_bh(&tp->lock);
12dac075 9693 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9694 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9695 device_set_wakeup_enable(dp, true);
9696 } else {
1da177e4 9697 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9698 device_set_wakeup_enable(dp, false);
9699 }
f47c11ee 9700 spin_unlock_bh(&tp->lock);
6aa20a22 9701
1da177e4
LT		 9702 return 0;
9703}
6aa20a22 9704
1da177e4
LT		 9705static u32 tg3_get_msglevel(struct net_device *dev)
9706{
9707 struct tg3 *tp = netdev_priv(dev);
9708 return tp->msg_enable;
9709}
6aa20a22 9710
1da177e4
LT		 9711static void tg3_set_msglevel(struct net_device *dev, u32 value)
9712{
9713 struct tg3 *tp = netdev_priv(dev);
9714 tp->msg_enable = value;
9715}
6aa20a22 9716
1da177e4
LT		 9717static int tg3_set_tso(struct net_device *dev, u32 value)
9718{
9719 struct tg3 *tp = netdev_priv(dev);
9720
9721 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9722 if (value)
9723 return -EINVAL;
9724 return 0;
9725 }
027455ad 9726 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9727 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9728 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9729 if (value) {
b0026624 9730 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9731 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9732 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9733 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9734 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9735 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9736 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9737 dev->features |= NETIF_F_TSO_ECN;
9738 } else
9739 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9740 }
1da177e4
LT		 9741 return ethtool_op_set_tso(dev, value);
9742}
6aa20a22 9743
1da177e4
LT		 9744static int tg3_nway_reset(struct net_device *dev)
9745{
9746 struct tg3 *tp = netdev_priv(dev);
1da177e4 9747 int r;
6aa20a22 9748
1da177e4
LT		 9749 if (!netif_running(dev))
9750 return -EAGAIN;
9751
c94e3941
MC		 9752 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9753 return -EINVAL;
9754
b02fd9e3
MC		 9755 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9756 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9757 return -EAGAIN;
3f0e3ad7 9758 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9759 } else {
9760 u32 bmcr;
9761
9762 spin_lock_bh(&tp->lock);
9763 r = -EINVAL;
9764 tg3_readphy(tp, MII_BMCR, &bmcr);
9765 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9766 ((bmcr & BMCR_ANENABLE) ||
9767 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9768 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9769 BMCR_ANENABLE);
9770 r = 0;
9771 }
9772 spin_unlock_bh(&tp->lock);
1da177e4 9773 }
6aa20a22 9774
1da177e4
LT		 9775 return r;
9776}
6aa20a22 9777
1da177e4
LT		 9778static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9779{
9780 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9781
1da177e4
LT		 9782 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9783 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9784 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9785 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9786 else
9787 ering->rx_jumbo_max_pending = 0;
9788
9789 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9790
9791 ering->rx_pending = tp->rx_pending;
9792 ering->rx_mini_pending = 0;
4f81c32b
MC		 9793 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9794 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9795 else
9796 ering->rx_jumbo_pending = 0;
9797
f3f3f27e 9798 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9799}
6aa20a22 9800
1da177e4
LT		 9801static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9802{
9803 struct tg3 *tp = netdev_priv(dev);
646c9edd 9804 int i, irq_sync = 0, err = 0;
6aa20a22 9805
1da177e4
LT		 9806 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9807 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9808 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9809 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9810 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9811 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9812 return -EINVAL;
6aa20a22 9813
bbe832c0 9814 if (netif_running(dev)) {
b02fd9e3 9815 tg3_phy_stop(tp);
1da177e4 9816 tg3_netif_stop(tp);
bbe832c0
MC		 9817 irq_sync = 1;
9818 }
1da177e4 9819
bbe832c0 9820 tg3_full_lock(tp, irq_sync);
6aa20a22 9821
1da177e4
LT		 9822 tp->rx_pending = ering->rx_pending;
9823
9824 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9825 tp->rx_pending > 63)
9826 tp->rx_pending = 63;
9827 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9828
9829 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9830 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9831
9832 if (netif_running(dev)) {
944d980e 9833 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9834 err = tg3_restart_hw(tp, 1);
9835 if (!err)
9836 tg3_netif_start(tp);
1da177e4
LT		 9837 }
9838
f47c11ee 9839 tg3_full_unlock(tp);
6aa20a22 9840
b02fd9e3
MC		 9841 if (irq_sync && !err)
9842 tg3_phy_start(tp);
9843
b9ec6c1b 9844 return err;
1da177e4 9845}
6aa20a22 9846
1da177e4
LT		 9847static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9848{
9849 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9850
1da177e4 9851 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9852
e18ce346 9853 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9854 epause->rx_pause = 1;
9855 else
9856 epause->rx_pause = 0;
9857
e18ce346 9858 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9859 epause->tx_pause = 1;
9860 else
9861 epause->tx_pause = 0;
1da177e4 9862}
6aa20a22 9863
1da177e4
LT		 9864static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9865{
9866 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9867 int err = 0;
6aa20a22 9868
b02fd9e3 9869 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2712168f
MC		 9870 u32 newadv;
9871 struct phy_device *phydev;
1da177e4 9872
2712168f 9873 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 9874
2712168f
MC		 9875 if (!(phydev->supported & SUPPORTED_Pause) ||
9876 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9877 ((epause->rx_pause && !epause->tx_pause) ||
9878 (!epause->rx_pause && epause->tx_pause))))
9879 return -EINVAL;
1da177e4 9880
2712168f
MC		 9881 tp->link_config.flowctrl = 0;
9882 if (epause->rx_pause) {
9883 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9884
9885 if (epause->tx_pause) {
9886 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9887 newadv = ADVERTISED_Pause;
b02fd9e3 9888 } else
2712168f
MC		 9889 newadv = ADVERTISED_Pause |
9890 ADVERTISED_Asym_Pause;
9891 } else if (epause->tx_pause) {
9892 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9893 newadv = ADVERTISED_Asym_Pause;
9894 } else
9895 newadv = 0;
9896
9897 if (epause->autoneg)
9898 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9899 else
9900 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9901
9902 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9903 u32 oldadv = phydev->advertising &
9904 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9905 if (oldadv != newadv) {
9906 phydev->advertising &=
9907 ~(ADVERTISED_Pause |
9908 ADVERTISED_Asym_Pause);
9909 phydev->advertising |= newadv;
9910 if (phydev->autoneg) {
9911 /*
9912 * Always renegotiate the link to
9913 * inform our link partner of our
9914 * flow control settings, even if the
9915 * flow control is forced. Let
9916 * tg3_adjust_link() do the final
9917 * flow control setup.
9918 */
9919 return phy_start_aneg(phydev);
b02fd9e3 9920 }
b02fd9e3 9921 }
b02fd9e3 9922
2712168f 9923 if (!epause->autoneg)
b02fd9e3 9924 tg3_setup_flow_control(tp, 0, 0);
2712168f
MC		 9925 } else {
9926 tp->link_config.orig_advertising &=
9927 ~(ADVERTISED_Pause |
9928 ADVERTISED_Asym_Pause);
9929 tp->link_config.orig_advertising |= newadv;
b02fd9e3
MC		 9930 }
9931 } else {
9932 int irq_sync = 0;
9933
9934 if (netif_running(dev)) {
9935 tg3_netif_stop(tp);
9936 irq_sync = 1;
9937 }
9938
9939 tg3_full_lock(tp, irq_sync);
9940
9941 if (epause->autoneg)
9942 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9943 else
9944 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9945 if (epause->rx_pause)
e18ce346 9946 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9947 else
e18ce346 9948 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9949 if (epause->tx_pause)
e18ce346 9950 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9951 else
e18ce346 9952 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9953
9954 if (netif_running(dev)) {
9955 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9956 err = tg3_restart_hw(tp, 1);
9957 if (!err)
9958 tg3_netif_start(tp);
9959 }
9960
9961 tg3_full_unlock(tp);
9962 }
6aa20a22 9963
b9ec6c1b 9964 return err;
1da177e4 9965}
6aa20a22 9966
1da177e4
LT		 9967static u32 tg3_get_rx_csum(struct net_device *dev)
9968{
9969 struct tg3 *tp = netdev_priv(dev);
9970 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9971}
6aa20a22 9972
1da177e4
LT		 9973static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9974{
9975 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9976
1da177e4
LT		 9977 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9978 if (data != 0)
9979 return -EINVAL;
c6cdf436
MC		 9980 return 0;
9981 }
6aa20a22 9982
f47c11ee 9983 spin_lock_bh(&tp->lock);
1da177e4
LT		 9984 if (data)
9985 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9986 else
9987 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9988 spin_unlock_bh(&tp->lock);
6aa20a22 9989
1da177e4
LT		 9990 return 0;
9991}
6aa20a22 9992
1da177e4
LT		 9993static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9994{
9995 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9996
1da177e4
LT		 9997 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9998 if (data != 0)
9999 return -EINVAL;
c6cdf436
MC		 10000 return 0;
10001 }
6aa20a22 10002
321d32a0 10003 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10004 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10005 else
9c27dbdf 10006 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10007
10008 return 0;
10009}
10010
b9f2c044 10011static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10012{
b9f2c044
JG		 10013 switch (sset) {
10014 case ETH_SS_TEST:
10015 return TG3_NUM_TEST;
10016 case ETH_SS_STATS:
10017 return TG3_NUM_STATS;
10018 default:
10019 return -EOPNOTSUPP;
10020 }
4cafd3f5
MC		 10021}
10022
1da177e4
LT		 10023static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10024{
10025 switch (stringset) {
10026 case ETH_SS_STATS:
10027 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10028 break;
4cafd3f5
MC		 10029 case ETH_SS_TEST:
10030 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10031 break;
1da177e4
LT		 10032 default:
10033 WARN_ON(1); /* we need a WARN() */
10034 break;
10035 }
10036}
10037
4009a93d
MC		 10038static int tg3_phys_id(struct net_device *dev, u32 data)
10039{
10040 struct tg3 *tp = netdev_priv(dev);
10041 int i;
10042
10043 if (!netif_running(tp->dev))
10044 return -EAGAIN;
10045
10046 if (data == 0)
759afc31 10047 data = UINT_MAX / 2;
4009a93d
MC		 10048
10049 for (i = 0; i < (data * 2); i++) {
10050 if ((i % 2) == 0)
10051 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10052 LED_CTRL_1000MBPS_ON |
10053 LED_CTRL_100MBPS_ON |
10054 LED_CTRL_10MBPS_ON |
10055 LED_CTRL_TRAFFIC_OVERRIDE |
10056 LED_CTRL_TRAFFIC_BLINK |
10057 LED_CTRL_TRAFFIC_LED);
6aa20a22 10058
4009a93d
MC		 10059 else
10060 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10061 LED_CTRL_TRAFFIC_OVERRIDE);
10062
10063 if (msleep_interruptible(500))
10064 break;
10065 }
10066 tw32(MAC_LED_CTRL, tp->led_ctrl);
10067 return 0;
10068}
10069
1da177e4
LT		 10070static void tg3_get_ethtool_stats (struct net_device *dev,
10071 struct ethtool_stats *estats, u64 *tmp_stats)
10072{
10073 struct tg3 *tp = netdev_priv(dev);
10074 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10075}
10076
566f86ad 10077#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10078#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10079#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10080#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10081#define NVRAM_SELFBOOT_HW_SIZE 0x20
10082#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10083
10084static int tg3_test_nvram(struct tg3 *tp)
10085{
b9fc7dc5 10086 u32 csum, magic;
a9dc529d 10087 __be32 *buf;
ab0049b4 10088 int i, j, k, err = 0, size;
566f86ad 10089
df259d8c
MC		 10090 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10091 return 0;
10092
e4f34110 10093 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10094 return -EIO;
10095
1b27777a
MC		 10096 if (magic == TG3_EEPROM_MAGIC)
10097 size = NVRAM_TEST_SIZE;
b16250e3 10098 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10099 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10100 TG3_EEPROM_SB_FORMAT_1) {
10101 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10102 case TG3_EEPROM_SB_REVISION_0:
10103 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10104 break;
10105 case TG3_EEPROM_SB_REVISION_2:
10106 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10107 break;
10108 case TG3_EEPROM_SB_REVISION_3:
10109 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10110 break;
10111 default:
10112 return 0;
10113 }
10114 } else
1b27777a 10115 return 0;
b16250e3
MC		 10116 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10117 size = NVRAM_SELFBOOT_HW_SIZE;
10118 else
1b27777a
MC		 10119 return -EIO;
10120
10121 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10122 if (buf == NULL)
10123 return -ENOMEM;
10124
1b27777a
MC		 10125 err = -EIO;
10126 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10127 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10128 if (err)
566f86ad 10129 break;
566f86ad 10130 }
1b27777a 10131 if (i < size)
566f86ad
MC		 10132 goto out;
10133
1b27777a 10134 /* Selfboot format */
a9dc529d 10135 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10136 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10137 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10138 u8 *buf8 = (u8 *) buf, csum8 = 0;
10139
b9fc7dc5 10140 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10141 TG3_EEPROM_SB_REVISION_2) {
10142 /* For rev 2, the csum doesn't include the MBA. */
10143 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10144 csum8 += buf8[i];
10145 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10146 csum8 += buf8[i];
10147 } else {
10148 for (i = 0; i < size; i++)
10149 csum8 += buf8[i];
10150 }
1b27777a 10151
ad96b485
AB		 10152 if (csum8 == 0) {
10153 err = 0;
10154 goto out;
10155 }
10156
10157 err = -EIO;
10158 goto out;
1b27777a 10159 }
566f86ad 10160
b9fc7dc5 10161 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10162 TG3_EEPROM_MAGIC_HW) {
10163 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10164 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10165 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10166
10167 /* Separate the parity bits and the data bytes. */
10168 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10169 if ((i == 0) || (i == 8)) {
10170 int l;
10171 u8 msk;
10172
10173 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10174 parity[k++] = buf8[i] & msk;
10175 i++;
859a5887 10176 } else if (i == 16) {
b16250e3
MC		 10177 int l;
10178 u8 msk;
10179
10180 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10181 parity[k++] = buf8[i] & msk;
10182 i++;
10183
10184 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10185 parity[k++] = buf8[i] & msk;
10186 i++;
10187 }
10188 data[j++] = buf8[i];
10189 }
10190
10191 err = -EIO;
10192 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10193 u8 hw8 = hweight8(data[i]);
10194
10195 if ((hw8 & 0x1) && parity[i])
10196 goto out;
10197 else if (!(hw8 & 0x1) && !parity[i])
10198 goto out;
10199 }
10200 err = 0;
10201 goto out;
10202 }
10203
566f86ad
MC		 10204 /* Bootstrap checksum at offset 0x10 */
10205 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10206 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10207 goto out;
10208
10209 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10210 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10211 if (csum != be32_to_cpu(buf[0xfc/4]))
10212 goto out;
566f86ad
MC		 10213
10214 err = 0;
10215
10216out:
10217 kfree(buf);
10218 return err;
10219}
10220
ca43007a
MC		 10221#define TG3_SERDES_TIMEOUT_SEC 2
10222#define TG3_COPPER_TIMEOUT_SEC 6
10223
10224static int tg3_test_link(struct tg3 *tp)
10225{
10226 int i, max;
10227
10228 if (!netif_running(tp->dev))
10229 return -ENODEV;
10230
4c987487 10231 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10232 max = TG3_SERDES_TIMEOUT_SEC;
10233 else
10234 max = TG3_COPPER_TIMEOUT_SEC;
10235
10236 for (i = 0; i < max; i++) {
10237 if (netif_carrier_ok(tp->dev))
10238 return 0;
10239
10240 if (msleep_interruptible(1000))
10241 break;
10242 }
10243
10244 return -EIO;
10245}
10246
a71116d1 10247/* Only test the commonly used registers */
30ca3e37 10248static int tg3_test_registers(struct tg3 *tp)
a71116d1 10249{
b16250e3 10250 int i, is_5705, is_5750;
a71116d1
MC		 10251 u32 offset, read_mask, write_mask, val, save_val, read_val;
10252 static struct {
10253 u16 offset;
10254 u16 flags;
10255#define TG3_FL_5705 0x1
10256#define TG3_FL_NOT_5705 0x2
10257#define TG3_FL_NOT_5788 0x4
b16250e3 10258#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10259 u32 read_mask;
10260 u32 write_mask;
10261 } reg_tbl[] = {
10262 /* MAC Control Registers */
10263 { MAC_MODE, TG3_FL_NOT_5705,
10264 0x00000000, 0x00ef6f8c },
10265 { MAC_MODE, TG3_FL_5705,
10266 0x00000000, 0x01ef6b8c },
10267 { MAC_STATUS, TG3_FL_NOT_5705,
10268 0x03800107, 0x00000000 },
10269 { MAC_STATUS, TG3_FL_5705,
10270 0x03800100, 0x00000000 },
10271 { MAC_ADDR_0_HIGH, 0x0000,
10272 0x00000000, 0x0000ffff },
10273 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 10274 0x00000000, 0xffffffff },
a71116d1
MC		 10275 { MAC_RX_MTU_SIZE, 0x0000,
10276 0x00000000, 0x0000ffff },
10277 { MAC_TX_MODE, 0x0000,
10278 0x00000000, 0x00000070 },
10279 { MAC_TX_LENGTHS, 0x0000,
10280 0x00000000, 0x00003fff },
10281 { MAC_RX_MODE, TG3_FL_NOT_5705,
10282 0x00000000, 0x000007fc },
10283 { MAC_RX_MODE, TG3_FL_5705,
10284 0x00000000, 0x000007dc },
10285 { MAC_HASH_REG_0, 0x0000,
10286 0x00000000, 0xffffffff },
10287 { MAC_HASH_REG_1, 0x0000,
10288 0x00000000, 0xffffffff },
10289 { MAC_HASH_REG_2, 0x0000,
10290 0x00000000, 0xffffffff },
10291 { MAC_HASH_REG_3, 0x0000,
10292 0x00000000, 0xffffffff },
10293
10294 /* Receive Data and Receive BD Initiator Control Registers. */
10295 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10296 0x00000000, 0xffffffff },
10297 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10298 0x00000000, 0xffffffff },
10299 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10300 0x00000000, 0x00000003 },
10301 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10302 0x00000000, 0xffffffff },
10303 { RCVDBDI_STD_BD+0, 0x0000,
10304 0x00000000, 0xffffffff },
10305 { RCVDBDI_STD_BD+4, 0x0000,
10306 0x00000000, 0xffffffff },
10307 { RCVDBDI_STD_BD+8, 0x0000,
10308 0x00000000, 0xffff0002 },
10309 { RCVDBDI_STD_BD+0xc, 0x0000,
10310 0x00000000, 0xffffffff },
6aa20a22 10311
a71116d1
MC		 10312 /* Receive BD Initiator Control Registers. */
10313 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10314 0x00000000, 0xffffffff },
10315 { RCVBDI_STD_THRESH, TG3_FL_5705,
10316 0x00000000, 0x000003ff },
10317 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10318 0x00000000, 0xffffffff },
6aa20a22 10319
a71116d1
MC		 10320 /* Host Coalescing Control Registers. */
10321 { HOSTCC_MODE, TG3_FL_NOT_5705,
10322 0x00000000, 0x00000004 },
10323 { HOSTCC_MODE, TG3_FL_5705,
10324 0x00000000, 0x000000f6 },
10325 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10326 0x00000000, 0xffffffff },
10327 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10328 0x00000000, 0x000003ff },
10329 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10330 0x00000000, 0xffffffff },
10331 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10332 0x00000000, 0x000003ff },
10333 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10334 0x00000000, 0xffffffff },
10335 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10336 0x00000000, 0x000000ff },
10337 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10338 0x00000000, 0xffffffff },
10339 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10340 0x00000000, 0x000000ff },
10341 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10342 0x00000000, 0xffffffff },
10343 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10344 0x00000000, 0xffffffff },
10345 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10346 0x00000000, 0xffffffff },
10347 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10348 0x00000000, 0x000000ff },
10349 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10350 0x00000000, 0xffffffff },
10351 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10352 0x00000000, 0x000000ff },
10353 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10354 0x00000000, 0xffffffff },
10355 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10356 0x00000000, 0xffffffff },
10357 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10358 0x00000000, 0xffffffff },
10359 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10360 0x00000000, 0xffffffff },
10361 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10362 0x00000000, 0xffffffff },
10363 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10364 0xffffffff, 0x00000000 },
10365 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10366 0xffffffff, 0x00000000 },
10367
10368 /* Buffer Manager Control Registers. */
b16250e3 10369 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10370 0x00000000, 0x007fff80 },
b16250e3 10371 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10372 0x00000000, 0x007fffff },
10373 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10374 0x00000000, 0x0000003f },
10375 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10376 0x00000000, 0x000001ff },
10377 { BUFMGR_MB_HIGH_WATER, 0x0000,
10378 0x00000000, 0x000001ff },
10379 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10380 0xffffffff, 0x00000000 },
10381 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10382 0xffffffff, 0x00000000 },
6aa20a22 10383
a71116d1
MC		 10384 /* Mailbox Registers */
10385 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10386 0x00000000, 0x000001ff },
10387 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10388 0x00000000, 0x000001ff },
10389 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10390 0x00000000, 0x000007ff },
10391 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10392 0x00000000, 0x000001ff },
10393
10394 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10395 };
10396
b16250e3
MC		 10397 is_5705 = is_5750 = 0;
10398 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10399 is_5705 = 1;
b16250e3
MC		 10400 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10401 is_5750 = 1;
10402 }
a71116d1
MC		 10403
10404 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10405 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10406 continue;
10407
10408 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10409 continue;
10410
10411 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10412 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10413 continue;
10414
b16250e3
MC		 10415 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10416 continue;
10417
a71116d1
MC		 10418 offset = (u32) reg_tbl[i].offset;
10419 read_mask = reg_tbl[i].read_mask;
10420 write_mask = reg_tbl[i].write_mask;
10421
10422 /* Save the original register content */
10423 save_val = tr32(offset);
10424
10425 /* Determine the read-only value. */
10426 read_val = save_val & read_mask;
10427
10428 /* Write zero to the register, then make sure the read-only bits
10429 * are not changed and the read/write bits are all zeros.
10430 */
10431 tw32(offset, 0);
10432
10433 val = tr32(offset);
10434
10435 /* Test the read-only and read/write bits. */
10436 if (((val & read_mask) != read_val) || (val & write_mask))
10437 goto out;
10438
10439 /* Write ones to all the bits defined by RdMask and WrMask, then
10440 * make sure the read-only bits are not changed and the
10441 * read/write bits are all ones.
10442 */
10443 tw32(offset, read_mask | write_mask);
10444
10445 val = tr32(offset);
10446
10447 /* Test the read-only bits. */
10448 if ((val & read_mask) != read_val)
10449 goto out;
10450
10451 /* Test the read/write bits. */
10452 if ((val & write_mask) != write_mask)
10453 goto out;
10454
10455 tw32(offset, save_val);
10456 }
10457
10458 return 0;
10459
10460out:
9f88f29f 10461 if (netif_msg_hw(tp))
2445e461
MC		 10462 netdev_err(tp->dev,
10463 "Register test failed at offset %x\n", offset);
a71116d1
MC		 10464 tw32(offset, save_val);
10465 return -EIO;
10466}
10467
7942e1db
MC		 10468static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10469{
f71e1309 10470 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10471 int i;
10472 u32 j;
10473
e9edda69 10474 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10475 for (j = 0; j < len; j += 4) {
10476 u32 val;
10477
10478 tg3_write_mem(tp, offset + j, test_pattern[i]);
10479 tg3_read_mem(tp, offset + j, &val);
10480 if (val != test_pattern[i])
10481 return -EIO;
10482 }
10483 }
10484 return 0;
10485}
10486
10487static int tg3_test_memory(struct tg3 *tp)
10488{
10489 static struct mem_entry {
10490 u32 offset;
10491 u32 len;
10492 } mem_tbl_570x[] = {
38690194 10493 { 0x00000000, 0x00b50},
7942e1db
MC		 10494 { 0x00002000, 0x1c000},
10495 { 0xffffffff, 0x00000}
10496 }, mem_tbl_5705[] = {
10497 { 0x00000100, 0x0000c},
10498 { 0x00000200, 0x00008},
7942e1db
MC		 10499 { 0x00004000, 0x00800},
10500 { 0x00006000, 0x01000},
10501 { 0x00008000, 0x02000},
10502 { 0x00010000, 0x0e000},
10503 { 0xffffffff, 0x00000}
79f4d13a
MC		 10504 }, mem_tbl_5755[] = {
10505 { 0x00000200, 0x00008},
10506 { 0x00004000, 0x00800},
10507 { 0x00006000, 0x00800},
10508 { 0x00008000, 0x02000},
10509 { 0x00010000, 0x0c000},
10510 { 0xffffffff, 0x00000}
b16250e3
MC		 10511 }, mem_tbl_5906[] = {
10512 { 0x00000200, 0x00008},
10513 { 0x00004000, 0x00400},
10514 { 0x00006000, 0x00400},
10515 { 0x00008000, 0x01000},
10516 { 0x00010000, 0x01000},
10517 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10518 }, mem_tbl_5717[] = {
10519 { 0x00000200, 0x00008},
10520 { 0x00010000, 0x0a000},
10521 { 0x00020000, 0x13c00},
10522 { 0xffffffff, 0x00000}
10523 }, mem_tbl_57765[] = {
10524 { 0x00000200, 0x00008},
10525 { 0x00004000, 0x00800},
10526 { 0x00006000, 0x09800},
10527 { 0x00010000, 0x0a000},
10528 { 0xffffffff, 0x00000}
7942e1db
MC		 10529 };
10530 struct mem_entry *mem_tbl;
10531 int err = 0;
10532 int i;
10533
8b5a6c42
MC		 10534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10535 mem_tbl = mem_tbl_5717;
10536 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10537 mem_tbl = mem_tbl_57765;
10538 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10539 mem_tbl = mem_tbl_5755;
10540 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10541 mem_tbl = mem_tbl_5906;
10542 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10543 mem_tbl = mem_tbl_5705;
10544 else
7942e1db
MC		 10545 mem_tbl = mem_tbl_570x;
10546
10547 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10548 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10549 mem_tbl[i].len)) != 0)
10550 break;
10551 }
6aa20a22 10552
7942e1db
MC		 10553 return err;
10554}
10555
9f40dead
MC		 10556#define TG3_MAC_LOOPBACK 0
10557#define TG3_PHY_LOOPBACK 1
10558
10559static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10560{
9f40dead 10561 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10562 u32 desc_idx, coal_now;
c76949a6
MC		 10563 struct sk_buff *skb, *rx_skb;
10564 u8 *tx_data;
10565 dma_addr_t map;
10566 int num_pkts, tx_len, rx_len, i, err;
10567 struct tg3_rx_buffer_desc *desc;
898a56f8 10568 struct tg3_napi *tnapi, *rnapi;
21f581a5 10569 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10570
c8873405
MC		 10571 tnapi = &tp->napi[0];
10572 rnapi = &tp->napi[0];
0c1d0e2b 10573 if (tp->irq_cnt > 1) {
0c1d0e2b 10574 rnapi = &tp->napi[1];
c8873405
MC		 10575 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10576 tnapi = &tp->napi[1];
0c1d0e2b 10577 }
fd2ce37f 10578 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10579
9f40dead 10580 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10581 /* HW errata - mac loopback fails in some cases on 5780.
10582 * Normal traffic and PHY loopback are not affected by
10583 * errata.
10584 */
10585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10586 return 0;
10587
9f40dead 10588 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10589 MAC_MODE_PORT_INT_LPBACK;
10590 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10591 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10592 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10593 mac_mode |= MAC_MODE_PORT_MODE_MII;
10594 else
10595 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10596 tw32(MAC_MODE, mac_mode);
10597 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10598 u32 val;
10599
7f97a4bd
MC		 10600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10601 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10602 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10603 } else
10604 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10605
9ef8ca99
MC		 10606 tg3_phy_toggle_automdix(tp, 0);
10607
3f7045c1 10608 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10609 udelay(40);
5d64ad34 10610
e8f3f6ca 10611 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd 10612 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1061b7c5
MC		 10613 tg3_writephy(tp, MII_TG3_FET_PTEST,
10614 MII_TG3_FET_PTEST_FRC_TX_LINK |
10615 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10616 /* The write needs to be flushed for the AC131 */
10617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10618 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
5d64ad34
MC		 10619 mac_mode |= MAC_MODE_PORT_MODE_MII;
10620 } else
10621 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10622
c94e3941
MC		 10623 /* reset to prevent losing 1st rx packet intermittently */
10624 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10625 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10626 udelay(10);
10627 tw32_f(MAC_RX_MODE, tp->rx_mode);
10628 }
e8f3f6ca 10629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
79eb6904
MC		 10630 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10631 if (masked_phy_id == TG3_PHY_ID_BCM5401)
e8f3f6ca 10632 mac_mode &= ~MAC_MODE_LINK_POLARITY;
79eb6904 10633 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
e8f3f6ca 10634 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10635 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10636 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10637 }
9f40dead 10638 tw32(MAC_MODE, mac_mode);
859a5887 10639 } else {
9f40dead 10640 return -EINVAL;
859a5887 10641 }
c76949a6
MC		 10642
10643 err = -EIO;
10644
c76949a6 10645 tx_len = 1514;
a20e9c62 10646 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10647 if (!skb)
10648 return -ENOMEM;
10649
c76949a6
MC		 10650 tx_data = skb_put(skb, tx_len);
10651 memcpy(tx_data, tp->dev->dev_addr, 6);
10652 memset(tx_data + 6, 0x0, 8);
10653
10654 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10655
10656 for (i = 14; i < tx_len; i++)
10657 tx_data[i] = (u8) (i & 0xff);
10658
f4188d8a
AD		 10659 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10660 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10661 dev_kfree_skb(skb);
10662 return -EIO;
10663 }
c76949a6
MC		 10664
10665 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10666 rnapi->coal_now);
c76949a6
MC		 10667
10668 udelay(10);
10669
898a56f8 10670 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10671
c76949a6
MC		 10672 num_pkts = 0;
10673
f4188d8a 10674 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10675
f3f3f27e 10676 tnapi->tx_prod++;
c76949a6
MC		 10677 num_pkts++;
10678
f3f3f27e
MC		 10679 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10680 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10681
10682 udelay(10);
10683
303fc921
MC		 10684 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10685 for (i = 0; i < 35; i++) {
c76949a6 10686 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10687 coal_now);
c76949a6
MC		 10688
10689 udelay(10);
10690
898a56f8
MC		 10691 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10692 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10693 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10694 (rx_idx == (rx_start_idx + num_pkts)))
10695 break;
10696 }
10697
f4188d8a 10698 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10699 dev_kfree_skb(skb);
10700
f3f3f27e 10701 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10702 goto out;
10703
10704 if (rx_idx != rx_start_idx + num_pkts)
10705 goto out;
10706
72334482 10707 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10708 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10709 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10710 if (opaque_key != RXD_OPAQUE_RING_STD)
10711 goto out;
10712
10713 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10714 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10715 goto out;
10716
10717 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10718 if (rx_len != tx_len)
10719 goto out;
10720
21f581a5 10721 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10722
21f581a5 10723 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10724 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10725
10726 for (i = 14; i < tx_len; i++) {
10727 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10728 goto out;
10729 }
10730 err = 0;
6aa20a22 10731
c76949a6
MC		 10732 /* tg3_free_rings will unmap and free the rx_skb */
10733out:
10734 return err;
10735}
10736
9f40dead
MC		 10737#define TG3_MAC_LOOPBACK_FAILED 1
10738#define TG3_PHY_LOOPBACK_FAILED 2
10739#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10740 TG3_PHY_LOOPBACK_FAILED)
10741
10742static int tg3_test_loopback(struct tg3 *tp)
10743{
10744 int err = 0;
9936bcf6 10745 u32 cpmuctrl = 0;
9f40dead
MC		 10746
10747 if (!netif_running(tp->dev))
10748 return TG3_LOOPBACK_FAILED;
10749
b9ec6c1b
MC		 10750 err = tg3_reset_hw(tp, 1);
10751 if (err)
10752 return TG3_LOOPBACK_FAILED;
9f40dead 10753
6833c043
MC		 10754 /* Turn off gphy autopowerdown. */
10755 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10756 tg3_phy_toggle_apd(tp, false);
10757
321d32a0 10758 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10759 int i;
10760 u32 status;
10761
10762 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10763
10764 /* Wait for up to 40 microseconds to acquire lock. */
10765 for (i = 0; i < 4; i++) {
10766 status = tr32(TG3_CPMU_MUTEX_GNT);
10767 if (status == CPMU_MUTEX_GNT_DRIVER)
10768 break;
10769 udelay(10);
10770 }
10771
10772 if (status != CPMU_MUTEX_GNT_DRIVER)
10773 return TG3_LOOPBACK_FAILED;
10774
b2a5c19c 10775 /* Turn off link-based power management. */
e875093c 10776 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10777 tw32(TG3_CPMU_CTRL,
10778 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10779 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10780 }
10781
9f40dead
MC		 10782 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10783 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10784
321d32a0 10785 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10786 tw32(TG3_CPMU_CTRL, cpmuctrl);
10787
10788 /* Release the mutex */
10789 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10790 }
10791
dd477003
MC		 10792 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10793 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10794 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10795 err |= TG3_PHY_LOOPBACK_FAILED;
10796 }
10797
6833c043
MC		 10798 /* Re-enable gphy autopowerdown. */
10799 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10800 tg3_phy_toggle_apd(tp, true);
10801
9f40dead
MC		 10802 return err;
10803}
10804
4cafd3f5
MC		 10805static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10806 u64 *data)
10807{
566f86ad
MC		 10808 struct tg3 *tp = netdev_priv(dev);
10809
bc1c7567
MC		 10810 if (tp->link_config.phy_is_low_power)
10811 tg3_set_power_state(tp, PCI_D0);
10812
566f86ad
MC		 10813 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10814
10815 if (tg3_test_nvram(tp) != 0) {
10816 etest->flags |= ETH_TEST_FL_FAILED;
10817 data[0] = 1;
10818 }
ca43007a
MC		 10819 if (tg3_test_link(tp) != 0) {
10820 etest->flags |= ETH_TEST_FL_FAILED;
10821 data[1] = 1;
10822 }
a71116d1 10823 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10824 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10825
10826 if (netif_running(dev)) {
b02fd9e3 10827 tg3_phy_stop(tp);
a71116d1 10828 tg3_netif_stop(tp);
bbe832c0
MC		 10829 irq_sync = 1;
10830 }
a71116d1 10831
bbe832c0 10832 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10833
10834 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10835 err = tg3_nvram_lock(tp);
a71116d1
MC		 10836 tg3_halt_cpu(tp, RX_CPU_BASE);
10837 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10838 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10839 if (!err)
10840 tg3_nvram_unlock(tp);
a71116d1 10841
d9ab5ad1
MC		 10842 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10843 tg3_phy_reset(tp);
10844
a71116d1
MC		 10845 if (tg3_test_registers(tp) != 0) {
10846 etest->flags |= ETH_TEST_FL_FAILED;
10847 data[2] = 1;
10848 }
7942e1db
MC		 10849 if (tg3_test_memory(tp) != 0) {
10850 etest->flags |= ETH_TEST_FL_FAILED;
10851 data[3] = 1;
10852 }
9f40dead 10853 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10854 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10855
f47c11ee
DM		 10856 tg3_full_unlock(tp);
10857
d4bc3927
MC		 10858 if (tg3_test_interrupt(tp) != 0) {
10859 etest->flags |= ETH_TEST_FL_FAILED;
10860 data[5] = 1;
10861 }
f47c11ee
DM		 10862
10863 tg3_full_lock(tp, 0);
d4bc3927 10864
a71116d1
MC		 10865 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10866 if (netif_running(dev)) {
10867 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10868 err2 = tg3_restart_hw(tp, 1);
10869 if (!err2)
b9ec6c1b 10870 tg3_netif_start(tp);
a71116d1 10871 }
f47c11ee
DM		 10872
10873 tg3_full_unlock(tp);
b02fd9e3
MC		 10874
10875 if (irq_sync && !err2)
10876 tg3_phy_start(tp);
a71116d1 10877 }
bc1c7567
MC		 10878 if (tp->link_config.phy_is_low_power)
10879 tg3_set_power_state(tp, PCI_D3hot);
10880
4cafd3f5
MC		 10881}
10882
1da177e4
LT		 10883static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10884{
10885 struct mii_ioctl_data *data = if_mii(ifr);
10886 struct tg3 *tp = netdev_priv(dev);
10887 int err;
10888
b02fd9e3 10889 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10890 struct phy_device *phydev;
b02fd9e3
MC		 10891 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10892 return -EAGAIN;
3f0e3ad7
MC		 10893 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10894 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10895 }
10896
33f401ae 10897 switch (cmd) {
1da177e4 10898 case SIOCGMIIPHY:
882e9793 10899 data->phy_id = tp->phy_addr;
1da177e4
LT		 10900
10901 /* fallthru */
10902 case SIOCGMIIREG: {
10903 u32 mii_regval;
10904
10905 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10906 break; /* We have no PHY */
10907
bc1c7567
MC		 10908 if (tp->link_config.phy_is_low_power)
10909 return -EAGAIN;
10910
f47c11ee 10911 spin_lock_bh(&tp->lock);
1da177e4 10912 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10913 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10914
10915 data->val_out = mii_regval;
10916
10917 return err;
10918 }
10919
10920 case SIOCSMIIREG:
10921 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10922 break; /* We have no PHY */
10923
bc1c7567
MC		 10924 if (tp->link_config.phy_is_low_power)
10925 return -EAGAIN;
10926
f47c11ee 10927 spin_lock_bh(&tp->lock);
1da177e4 10928 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10929 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10930
10931 return err;
10932
10933 default:
10934 /* do nothing */
10935 break;
10936 }
10937 return -EOPNOTSUPP;
10938}
10939
10940#if TG3_VLAN_TAG_USED
10941static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10942{
10943 struct tg3 *tp = netdev_priv(dev);
10944
844b3eed
MC		 10945 if (!netif_running(dev)) {
10946 tp->vlgrp = grp;
10947 return;
10948 }
10949
10950 tg3_netif_stop(tp);
29315e87 10951
f47c11ee 10952 tg3_full_lock(tp, 0);
1da177e4
LT		 10953
10954 tp->vlgrp = grp;
10955
10956 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10957 __tg3_set_rx_mode(dev);
10958
844b3eed 10959 tg3_netif_start(tp);
46966545
MC		 10960
10961 tg3_full_unlock(tp);
1da177e4 10962}
1da177e4
LT		 10963#endif
10964
15f9850d
DM		 10965static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10966{
10967 struct tg3 *tp = netdev_priv(dev);
10968
10969 memcpy(ec, &tp->coal, sizeof(*ec));
10970 return 0;
10971}
10972
d244c892
MC		 10973static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10974{
10975 struct tg3 *tp = netdev_priv(dev);
10976 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10977 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10978
10979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10980 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10981 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10982 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10983 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10984 }
10985
10986 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10987 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10988 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10989 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10990 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10991 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10992 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10993 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10994 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10995 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10996 return -EINVAL;
10997
10998 /* No rx interrupts will be generated if both are zero */
10999 if ((ec->rx_coalesce_usecs == 0) &&
11000 (ec->rx_max_coalesced_frames == 0))
11001 return -EINVAL;
11002
11003 /* No tx interrupts will be generated if both are zero */
11004 if ((ec->tx_coalesce_usecs == 0) &&
11005 (ec->tx_max_coalesced_frames == 0))
11006 return -EINVAL;
11007
11008 /* Only copy relevant parameters, ignore all others. */
11009 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11010 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11011 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11012 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11013 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11014 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11015 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11016 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11017 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11018
11019 if (netif_running(dev)) {
11020 tg3_full_lock(tp, 0);
11021 __tg3_set_coalesce(tp, &tp->coal);
11022 tg3_full_unlock(tp);
11023 }
11024 return 0;
11025}
11026
7282d491 11027static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11028 .get_settings = tg3_get_settings,
11029 .set_settings = tg3_set_settings,
11030 .get_drvinfo = tg3_get_drvinfo,
11031 .get_regs_len = tg3_get_regs_len,
11032 .get_regs = tg3_get_regs,
11033 .get_wol = tg3_get_wol,
11034 .set_wol = tg3_set_wol,
11035 .get_msglevel = tg3_get_msglevel,
11036 .set_msglevel = tg3_set_msglevel,
11037 .nway_reset = tg3_nway_reset,
11038 .get_link = ethtool_op_get_link,
11039 .get_eeprom_len = tg3_get_eeprom_len,
11040 .get_eeprom = tg3_get_eeprom,
11041 .set_eeprom = tg3_set_eeprom,
11042 .get_ringparam = tg3_get_ringparam,
11043 .set_ringparam = tg3_set_ringparam,
11044 .get_pauseparam = tg3_get_pauseparam,
11045 .set_pauseparam = tg3_set_pauseparam,
11046 .get_rx_csum = tg3_get_rx_csum,
11047 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11048 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11049 .set_sg = ethtool_op_set_sg,
1da177e4 11050 .set_tso = tg3_set_tso,
4cafd3f5 11051 .self_test = tg3_self_test,
1da177e4 11052 .get_strings = tg3_get_strings,
4009a93d 11053 .phys_id = tg3_phys_id,
1da177e4 11054 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11055 .get_coalesce = tg3_get_coalesce,
d244c892 11056 .set_coalesce = tg3_set_coalesce,
b9f2c044 11057 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11058};
11059
11060static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11061{
1b27777a 11062 u32 cursize, val, magic;
1da177e4
LT		 11063
11064 tp->nvram_size = EEPROM_CHIP_SIZE;
11065
e4f34110 11066 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11067 return;
11068
b16250e3
MC		 11069 if ((magic != TG3_EEPROM_MAGIC) &&
11070 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11071 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11072 return;
11073
11074 /*
11075 * Size the chip by reading offsets at increasing powers of two.
11076 * When we encounter our validation signature, we know the addressing
11077 * has wrapped around, and thus have our chip size.
11078 */
1b27777a 11079 cursize = 0x10;
1da177e4
LT		 11080
11081 while (cursize < tp->nvram_size) {
e4f34110 11082 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11083 return;
11084
1820180b 11085 if (val == magic)
1da177e4
LT		 11086 break;
11087
11088 cursize <<= 1;
11089 }
11090
11091 tp->nvram_size = cursize;
11092}
6aa20a22 11093
1da177e4
LT		 11094static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11095{
11096 u32 val;
11097
df259d8c
MC		 11098 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11099 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11100 return;
11101
11102 /* Selfboot format */
1820180b 11103 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11104 tg3_get_eeprom_size(tp);
11105 return;
11106 }
11107
6d348f2c 11108 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11109 if (val != 0) {
6d348f2c
MC		 11110 /* This is confusing. We want to operate on the
11111 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11112 * call will read from NVRAM and byteswap the data
11113 * according to the byteswapping settings for all
11114 * other register accesses. This ensures the data we
11115 * want will always reside in the lower 16-bits.
11116 * However, the data in NVRAM is in LE format, which
11117 * means the data from the NVRAM read will always be
11118 * opposite the endianness of the CPU. The 16-bit
11119 * byteswap then brings the data to CPU endianness.
11120 */
11121 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11122 return;
11123 }
11124 }
fd1122a2 11125 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11126}
11127
11128static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11129{
11130 u32 nvcfg1;
11131
11132 nvcfg1 = tr32(NVRAM_CFG1);
11133 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11134 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11135 } else {
1da177e4
LT		 11136 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11137 tw32(NVRAM_CFG1, nvcfg1);
11138 }
11139
4c987487 11140 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11141 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11142 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11143 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11144 tp->nvram_jedecnum = JEDEC_ATMEL;
11145 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11146 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11147 break;
11148 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11149 tp->nvram_jedecnum = JEDEC_ATMEL;
11150 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11151 break;
11152 case FLASH_VENDOR_ATMEL_EEPROM:
11153 tp->nvram_jedecnum = JEDEC_ATMEL;
11154 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11155 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11156 break;
11157 case FLASH_VENDOR_ST:
11158 tp->nvram_jedecnum = JEDEC_ST;
11159 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11160 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11161 break;
11162 case FLASH_VENDOR_SAIFUN:
11163 tp->nvram_jedecnum = JEDEC_SAIFUN;
11164 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11165 break;
11166 case FLASH_VENDOR_SST_SMALL:
11167 case FLASH_VENDOR_SST_LARGE:
11168 tp->nvram_jedecnum = JEDEC_SST;
11169 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11170 break;
1da177e4 11171 }
8590a603 11172 } else {
1da177e4
LT		 11173 tp->nvram_jedecnum = JEDEC_ATMEL;
11174 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11175 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11176 }
11177}
11178
a1b950d5
MC		 11179static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11180{
11181 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11182 case FLASH_5752PAGE_SIZE_256:
11183 tp->nvram_pagesize = 256;
11184 break;
11185 case FLASH_5752PAGE_SIZE_512:
11186 tp->nvram_pagesize = 512;
11187 break;
11188 case FLASH_5752PAGE_SIZE_1K:
11189 tp->nvram_pagesize = 1024;
11190 break;
11191 case FLASH_5752PAGE_SIZE_2K:
11192 tp->nvram_pagesize = 2048;
11193 break;
11194 case FLASH_5752PAGE_SIZE_4K:
11195 tp->nvram_pagesize = 4096;
11196 break;
11197 case FLASH_5752PAGE_SIZE_264:
11198 tp->nvram_pagesize = 264;
11199 break;
11200 case FLASH_5752PAGE_SIZE_528:
11201 tp->nvram_pagesize = 528;
11202 break;
11203 }
11204}
11205
361b4ac2
MC		 11206static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11207{
11208 u32 nvcfg1;
11209
11210 nvcfg1 = tr32(NVRAM_CFG1);
11211
e6af301b
MC		 11212 /* NVRAM protection for TPM */
11213 if (nvcfg1 & (1 << 27))
f66a29b0 11214 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11215
361b4ac2 11216 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11217 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11218 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11219 tp->nvram_jedecnum = JEDEC_ATMEL;
11220 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11221 break;
11222 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11223 tp->nvram_jedecnum = JEDEC_ATMEL;
11224 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11225 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11226 break;
11227 case FLASH_5752VENDOR_ST_M45PE10:
11228 case FLASH_5752VENDOR_ST_M45PE20:
11229 case FLASH_5752VENDOR_ST_M45PE40:
11230 tp->nvram_jedecnum = JEDEC_ST;
11231 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11232 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11233 break;
361b4ac2
MC		 11234 }
11235
11236 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11237 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11238 } else {
361b4ac2
MC		 11239 /* For eeprom, set pagesize to maximum eeprom size */
11240 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11241
11242 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11243 tw32(NVRAM_CFG1, nvcfg1);
11244 }
11245}
11246
d3c7b886
MC		 11247static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11248{
989a9d23 11249 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11250
11251 nvcfg1 = tr32(NVRAM_CFG1);
11252
11253 /* NVRAM protection for TPM */
989a9d23 11254 if (nvcfg1 & (1 << 27)) {
f66a29b0 11255 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11256 protect = 1;
11257 }
d3c7b886 11258
989a9d23
MC		 11259 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11260 switch (nvcfg1) {
8590a603
MC		 11261 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11262 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11263 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11264 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11265 tp->nvram_jedecnum = JEDEC_ATMEL;
11266 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11267 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11268 tp->nvram_pagesize = 264;
11269 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11270 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11271 tp->nvram_size = (protect ? 0x3e200 :
11272 TG3_NVRAM_SIZE_512KB);
11273 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11274 tp->nvram_size = (protect ? 0x1f200 :
11275 TG3_NVRAM_SIZE_256KB);
11276 else
11277 tp->nvram_size = (protect ? 0x1f200 :
11278 TG3_NVRAM_SIZE_128KB);
11279 break;
11280 case FLASH_5752VENDOR_ST_M45PE10:
11281 case FLASH_5752VENDOR_ST_M45PE20:
11282 case FLASH_5752VENDOR_ST_M45PE40:
11283 tp->nvram_jedecnum = JEDEC_ST;
11284 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11285 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11286 tp->nvram_pagesize = 256;
11287 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11288 tp->nvram_size = (protect ?
11289 TG3_NVRAM_SIZE_64KB :
11290 TG3_NVRAM_SIZE_128KB);
11291 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11292 tp->nvram_size = (protect ?
11293 TG3_NVRAM_SIZE_64KB :
11294 TG3_NVRAM_SIZE_256KB);
11295 else
11296 tp->nvram_size = (protect ?
11297 TG3_NVRAM_SIZE_128KB :
11298 TG3_NVRAM_SIZE_512KB);
11299 break;
d3c7b886
MC		 11300 }
11301}
11302
1b27777a
MC		 11303static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11304{
11305 u32 nvcfg1;
11306
11307 nvcfg1 = tr32(NVRAM_CFG1);
11308
11309 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11310 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11311 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11312 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11313 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11314 tp->nvram_jedecnum = JEDEC_ATMEL;
11315 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11316 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11317
8590a603
MC		 11318 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11319 tw32(NVRAM_CFG1, nvcfg1);
11320 break;
11321 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11322 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11323 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11324 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11325 tp->nvram_jedecnum = JEDEC_ATMEL;
11326 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11327 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11328 tp->nvram_pagesize = 264;
11329 break;
11330 case FLASH_5752VENDOR_ST_M45PE10:
11331 case FLASH_5752VENDOR_ST_M45PE20:
11332 case FLASH_5752VENDOR_ST_M45PE40:
11333 tp->nvram_jedecnum = JEDEC_ST;
11334 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11335 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11336 tp->nvram_pagesize = 256;
11337 break;
1b27777a
MC		 11338 }
11339}
11340
6b91fa02
MC		 11341static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11342{
11343 u32 nvcfg1, protect = 0;
11344
11345 nvcfg1 = tr32(NVRAM_CFG1);
11346
11347 /* NVRAM protection for TPM */
11348 if (nvcfg1 & (1 << 27)) {
f66a29b0 11349 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11350 protect = 1;
11351 }
11352
11353 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11354 switch (nvcfg1) {
8590a603
MC		 11355 case FLASH_5761VENDOR_ATMEL_ADB021D:
11356 case FLASH_5761VENDOR_ATMEL_ADB041D:
11357 case FLASH_5761VENDOR_ATMEL_ADB081D:
11358 case FLASH_5761VENDOR_ATMEL_ADB161D:
11359 case FLASH_5761VENDOR_ATMEL_MDB021D:
11360 case FLASH_5761VENDOR_ATMEL_MDB041D:
11361 case FLASH_5761VENDOR_ATMEL_MDB081D:
11362 case FLASH_5761VENDOR_ATMEL_MDB161D:
11363 tp->nvram_jedecnum = JEDEC_ATMEL;
11364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11366 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11367 tp->nvram_pagesize = 256;
11368 break;
11369 case FLASH_5761VENDOR_ST_A_M45PE20:
11370 case FLASH_5761VENDOR_ST_A_M45PE40:
11371 case FLASH_5761VENDOR_ST_A_M45PE80:
11372 case FLASH_5761VENDOR_ST_A_M45PE16:
11373 case FLASH_5761VENDOR_ST_M_M45PE20:
11374 case FLASH_5761VENDOR_ST_M_M45PE40:
11375 case FLASH_5761VENDOR_ST_M_M45PE80:
11376 case FLASH_5761VENDOR_ST_M_M45PE16:
11377 tp->nvram_jedecnum = JEDEC_ST;
11378 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11379 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11380 tp->nvram_pagesize = 256;
11381 break;
6b91fa02
MC		 11382 }
11383
11384 if (protect) {
11385 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11386 } else {
11387 switch (nvcfg1) {
8590a603
MC		 11388 case FLASH_5761VENDOR_ATMEL_ADB161D:
11389 case FLASH_5761VENDOR_ATMEL_MDB161D:
11390 case FLASH_5761VENDOR_ST_A_M45PE16:
11391 case FLASH_5761VENDOR_ST_M_M45PE16:
11392 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11393 break;
11394 case FLASH_5761VENDOR_ATMEL_ADB081D:
11395 case FLASH_5761VENDOR_ATMEL_MDB081D:
11396 case FLASH_5761VENDOR_ST_A_M45PE80:
11397 case FLASH_5761VENDOR_ST_M_M45PE80:
11398 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11399 break;
11400 case FLASH_5761VENDOR_ATMEL_ADB041D:
11401 case FLASH_5761VENDOR_ATMEL_MDB041D:
11402 case FLASH_5761VENDOR_ST_A_M45PE40:
11403 case FLASH_5761VENDOR_ST_M_M45PE40:
11404 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11405 break;
11406 case FLASH_5761VENDOR_ATMEL_ADB021D:
11407 case FLASH_5761VENDOR_ATMEL_MDB021D:
11408 case FLASH_5761VENDOR_ST_A_M45PE20:
11409 case FLASH_5761VENDOR_ST_M_M45PE20:
11410 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11411 break;
6b91fa02
MC		 11412 }
11413 }
11414}
11415
b5d3772c
MC		 11416static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11417{
11418 tp->nvram_jedecnum = JEDEC_ATMEL;
11419 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11420 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11421}
11422
321d32a0
MC		 11423static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11424{
11425 u32 nvcfg1;
11426
11427 nvcfg1 = tr32(NVRAM_CFG1);
11428
11429 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11430 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11431 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11432 tp->nvram_jedecnum = JEDEC_ATMEL;
11433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11434 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11435
11436 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11437 tw32(NVRAM_CFG1, nvcfg1);
11438 return;
11439 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11440 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11441 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11442 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11443 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11444 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11445 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11446 tp->nvram_jedecnum = JEDEC_ATMEL;
11447 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11448 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11449
11450 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11451 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11452 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11453 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11454 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11455 break;
11456 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11457 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11458 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11459 break;
11460 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11461 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11462 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11463 break;
11464 }
11465 break;
11466 case FLASH_5752VENDOR_ST_M45PE10:
11467 case FLASH_5752VENDOR_ST_M45PE20:
11468 case FLASH_5752VENDOR_ST_M45PE40:
11469 tp->nvram_jedecnum = JEDEC_ST;
11470 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11471 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11472
11473 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11474 case FLASH_5752VENDOR_ST_M45PE10:
11475 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11476 break;
11477 case FLASH_5752VENDOR_ST_M45PE20:
11478 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11479 break;
11480 case FLASH_5752VENDOR_ST_M45PE40:
11481 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11482 break;
11483 }
11484 break;
11485 default:
df259d8c 11486 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11487 return;
11488 }
11489
a1b950d5
MC		 11490 tg3_nvram_get_pagesize(tp, nvcfg1);
11491 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11492 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11493}
11494
11495
11496static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11497{
11498 u32 nvcfg1;
11499
11500 nvcfg1 = tr32(NVRAM_CFG1);
11501
11502 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11503 case FLASH_5717VENDOR_ATMEL_EEPROM:
11504 case FLASH_5717VENDOR_MICRO_EEPROM:
11505 tp->nvram_jedecnum = JEDEC_ATMEL;
11506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11507 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11508
11509 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11510 tw32(NVRAM_CFG1, nvcfg1);
11511 return;
11512 case FLASH_5717VENDOR_ATMEL_MDB011D:
11513 case FLASH_5717VENDOR_ATMEL_ADB011B:
11514 case FLASH_5717VENDOR_ATMEL_ADB011D:
11515 case FLASH_5717VENDOR_ATMEL_MDB021D:
11516 case FLASH_5717VENDOR_ATMEL_ADB021B:
11517 case FLASH_5717VENDOR_ATMEL_ADB021D:
11518 case FLASH_5717VENDOR_ATMEL_45USPT:
11519 tp->nvram_jedecnum = JEDEC_ATMEL;
11520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11522
11523 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11524 case FLASH_5717VENDOR_ATMEL_MDB021D:
11525 case FLASH_5717VENDOR_ATMEL_ADB021B:
11526 case FLASH_5717VENDOR_ATMEL_ADB021D:
11527 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11528 break;
11529 default:
11530 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11531 break;
11532 }
321d32a0 11533 break;
a1b950d5
MC		 11534 case FLASH_5717VENDOR_ST_M_M25PE10:
11535 case FLASH_5717VENDOR_ST_A_M25PE10:
11536 case FLASH_5717VENDOR_ST_M_M45PE10:
11537 case FLASH_5717VENDOR_ST_A_M45PE10:
11538 case FLASH_5717VENDOR_ST_M_M25PE20:
11539 case FLASH_5717VENDOR_ST_A_M25PE20:
11540 case FLASH_5717VENDOR_ST_M_M45PE20:
11541 case FLASH_5717VENDOR_ST_A_M45PE20:
11542 case FLASH_5717VENDOR_ST_25USPT:
11543 case FLASH_5717VENDOR_ST_45USPT:
11544 tp->nvram_jedecnum = JEDEC_ST;
11545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11547
11548 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11549 case FLASH_5717VENDOR_ST_M_M25PE20:
11550 case FLASH_5717VENDOR_ST_A_M25PE20:
11551 case FLASH_5717VENDOR_ST_M_M45PE20:
11552 case FLASH_5717VENDOR_ST_A_M45PE20:
11553 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11554 break;
11555 default:
11556 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11557 break;
11558 }
321d32a0 11559 break;
a1b950d5
MC		 11560 default:
11561 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11562 return;
321d32a0 11563 }
a1b950d5
MC		 11564
11565 tg3_nvram_get_pagesize(tp, nvcfg1);
11566 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11567 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11568}
11569
1da177e4
LT		 11570/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11571static void __devinit tg3_nvram_init(struct tg3 *tp)
11572{
1da177e4
LT		 11573 tw32_f(GRC_EEPROM_ADDR,
11574 (EEPROM_ADDR_FSM_RESET |
11575 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11576 EEPROM_ADDR_CLKPERD_SHIFT)));
11577
9d57f01c 11578 msleep(1);
1da177e4
LT		 11579
11580 /* Enable seeprom accesses. */
11581 tw32_f(GRC_LOCAL_CTRL,
11582 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11583 udelay(100);
11584
11585 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11586 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11587 tp->tg3_flags |= TG3_FLAG_NVRAM;
11588
ec41c7df 11589 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 11590 netdev_warn(tp->dev,
11591 "Cannot get nvram lock, %s failed\n",
05dbe005 11592 __func__);
ec41c7df
MC		 11593 return;
11594 }
e6af301b 11595 tg3_enable_nvram_access(tp);
1da177e4 11596
989a9d23
MC		 11597 tp->nvram_size = 0;
11598
361b4ac2
MC		 11599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11600 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11601 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11602 tg3_get_5755_nvram_info(tp);
d30cdd28 11603 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11604 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11605 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11606 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11608 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11609 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11610 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11611 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11613 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11614 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11615 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11616 else
11617 tg3_get_nvram_info(tp);
11618
989a9d23
MC		 11619 if (tp->nvram_size == 0)
11620 tg3_get_nvram_size(tp);
1da177e4 11621
e6af301b 11622 tg3_disable_nvram_access(tp);
381291b7 11623 tg3_nvram_unlock(tp);
1da177e4
LT		 11624
11625 } else {
11626 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11627
11628 tg3_get_eeprom_size(tp);
11629 }
11630}
11631
1da177e4
LT		 11632static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11633 u32 offset, u32 len, u8 *buf)
11634{
11635 int i, j, rc = 0;
11636 u32 val;
11637
11638 for (i = 0; i < len; i += 4) {
b9fc7dc5 11639 u32 addr;
a9dc529d 11640 __be32 data;
1da177e4
LT		 11641
11642 addr = offset + i;
11643
11644 memcpy(&data, buf + i, 4);
11645
62cedd11
MC		 11646 /*
11647 * The SEEPROM interface expects the data to always be opposite
11648 * the native endian format. We accomplish this by reversing
11649 * all the operations that would have been performed on the
11650 * data from a call to tg3_nvram_read_be32().
11651 */
11652 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11653
11654 val = tr32(GRC_EEPROM_ADDR);
11655 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11656
11657 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11658 EEPROM_ADDR_READ);
11659 tw32(GRC_EEPROM_ADDR, val |
11660 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11661 (addr & EEPROM_ADDR_ADDR_MASK) |
11662 EEPROM_ADDR_START |
11663 EEPROM_ADDR_WRITE);
6aa20a22 11664
9d57f01c 11665 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11666 val = tr32(GRC_EEPROM_ADDR);
11667
11668 if (val & EEPROM_ADDR_COMPLETE)
11669 break;
9d57f01c 11670 msleep(1);
1da177e4
LT		 11671 }
11672 if (!(val & EEPROM_ADDR_COMPLETE)) {
11673 rc = -EBUSY;
11674 break;
11675 }
11676 }
11677
11678 return rc;
11679}
11680
11681/* offset and length are dword aligned */
11682static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11683 u8 *buf)
11684{
11685 int ret = 0;
11686 u32 pagesize = tp->nvram_pagesize;
11687 u32 pagemask = pagesize - 1;
11688 u32 nvram_cmd;
11689 u8 *tmp;
11690
11691 tmp = kmalloc(pagesize, GFP_KERNEL);
11692 if (tmp == NULL)
11693 return -ENOMEM;
11694
11695 while (len) {
11696 int j;
e6af301b 11697 u32 phy_addr, page_off, size;
1da177e4
LT		 11698
11699 phy_addr = offset & ~pagemask;
6aa20a22 11700
1da177e4 11701 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11702 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11703 (__be32 *) (tmp + j));
11704 if (ret)
1da177e4
LT		 11705 break;
11706 }
11707 if (ret)
11708 break;
11709
c6cdf436 11710 page_off = offset & pagemask;
1da177e4
LT		 11711 size = pagesize;
11712 if (len < size)
11713 size = len;
11714
11715 len -= size;
11716
11717 memcpy(tmp + page_off, buf, size);
11718
11719 offset = offset + (pagesize - page_off);
11720
e6af301b 11721 tg3_enable_nvram_access(tp);
1da177e4
LT		 11722
11723 /*
11724 * Before we can erase the flash page, we need
11725 * to issue a special "write enable" command.
11726 */
11727 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11728
11729 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11730 break;
11731
11732 /* Erase the target page */
11733 tw32(NVRAM_ADDR, phy_addr);
11734
11735 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11736 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11737
c6cdf436 11738 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
1da177e4
LT		 11739 break;
11740
11741 /* Issue another write enable to start the write. */
11742 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11743
11744 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11745 break;
11746
11747 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11748 __be32 data;
1da177e4 11749
b9fc7dc5 11750 data = *((__be32 *) (tmp + j));
a9dc529d 11751
b9fc7dc5 11752 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11753
11754 tw32(NVRAM_ADDR, phy_addr + j);
11755
11756 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11757 NVRAM_CMD_WR;
11758
11759 if (j == 0)
11760 nvram_cmd |= NVRAM_CMD_FIRST;
11761 else if (j == (pagesize - 4))
11762 nvram_cmd |= NVRAM_CMD_LAST;
11763
11764 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11765 break;
11766 }
11767 if (ret)
11768 break;
11769 }
11770
11771 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11772 tg3_nvram_exec_cmd(tp, nvram_cmd);
11773
11774 kfree(tmp);
11775
11776 return ret;
11777}
11778
11779/* offset and length are dword aligned */
11780static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11781 u8 *buf)
11782{
11783 int i, ret = 0;
11784
11785 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11786 u32 page_off, phy_addr, nvram_cmd;
11787 __be32 data;
1da177e4
LT		 11788
11789 memcpy(&data, buf + i, 4);
b9fc7dc5 11790 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4 11791
c6cdf436 11792 page_off = offset % tp->nvram_pagesize;
1da177e4 11793
1820180b 11794 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11795
11796 tw32(NVRAM_ADDR, phy_addr);
11797
11798 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11799
c6cdf436 11800 if (page_off == 0 || i == 0)
1da177e4 11801 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11802 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11803 nvram_cmd |= NVRAM_CMD_LAST;
11804
11805 if (i == (len - 4))
11806 nvram_cmd |= NVRAM_CMD_LAST;
11807
321d32a0
MC		 11808 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11809 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11810 (tp->nvram_jedecnum == JEDEC_ST) &&
11811 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11812
11813 if ((ret = tg3_nvram_exec_cmd(tp,
11814 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11815 NVRAM_CMD_DONE)))
11816
11817 break;
11818 }
11819 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11820 /* We always do complete word writes to eeprom. */
11821 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11822 }
11823
11824 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11825 break;
11826 }
11827 return ret;
11828}
11829
11830/* offset and length are dword aligned */
11831static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11832{
11833 int ret;
11834
1da177e4 11835 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11836 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11837 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11838 udelay(40);
11839 }
11840
11841 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11842 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
859a5887 11843 } else {
1da177e4
LT		 11844 u32 grc_mode;
11845
ec41c7df
MC		 11846 ret = tg3_nvram_lock(tp);
11847 if (ret)
11848 return ret;
1da177e4 11849
e6af301b
MC		 11850 tg3_enable_nvram_access(tp);
11851 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11852 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11853 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11854
11855 grc_mode = tr32(GRC_MODE);
11856 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11857
11858 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11859 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11860
11861 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11862 buf);
859a5887 11863 } else {
1da177e4
LT		 11864 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11865 buf);
11866 }
11867
11868 grc_mode = tr32(GRC_MODE);
11869 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11870
e6af301b 11871 tg3_disable_nvram_access(tp);
1da177e4
LT		 11872 tg3_nvram_unlock(tp);
11873 }
11874
11875 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11876 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11877 udelay(40);
11878 }
11879
11880 return ret;
11881}
11882
11883struct subsys_tbl_ent {
11884 u16 subsys_vendor, subsys_devid;
11885 u32 phy_id;
11886};
11887
24daf2b0 11888static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
1da177e4 11889 /* Broadcom boards. */
24daf2b0 11890 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11891 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 11892 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11893 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 11894 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11895 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 11896 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11897 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11898 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11899 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 11900 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11901 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 11902 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11903 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11904 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11905 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 11906 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11907 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 11908 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11909 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 11910 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11911 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 11912
11913 /* 3com boards. */
24daf2b0 11914 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11915 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 11916 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11917 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 11918 { TG3PCI_SUBVENDOR_ID_3COM,
11919 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11920 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11921 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 11922 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11923 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 11924
11925 /* DELL boards. */
24daf2b0 11926 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11927 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 11928 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11929 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 11930 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11931 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 11932 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11933 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 11934
11935 /* Compaq boards. */
24daf2b0 11936 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11937 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 11938 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11939 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 11940 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11941 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11942 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11943 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 11944 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11945 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 11946
11947 /* IBM boards. */
24daf2b0
MC		 11948 { TG3PCI_SUBVENDOR_ID_IBM,
11949 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 11950};
11951
24daf2b0 11952static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 11953{
11954 int i;
11955
11956 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11957 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11958 tp->pdev->subsystem_vendor) &&
11959 (subsys_id_to_phy_id[i].subsys_devid ==
11960 tp->pdev->subsystem_device))
11961 return &subsys_id_to_phy_id[i];
11962 }
11963 return NULL;
11964}
11965
7d0c41ef 11966static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11967{
1da177e4 11968 u32 val;
caf636c7
MC		 11969 u16 pmcsr;
11970
11971 /* On some early chips the SRAM cannot be accessed in D3hot state,
11972 * so need make sure we're in D0.
11973 */
11974 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11975 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11976 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11977 msleep(1);
7d0c41ef
MC		 11978
11979 /* Make sure register accesses (indirect or otherwise)
11980 * will function correctly.
11981 */
11982 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11983 tp->misc_host_ctrl);
1da177e4 11984
f49639e6
DM		 11985 /* The memory arbiter has to be enabled in order for SRAM accesses
11986 * to succeed. Normally on powerup the tg3 chip firmware will make
11987 * sure it is enabled, but other entities such as system netboot
11988 * code might disable it.
11989 */
11990 val = tr32(MEMARB_MODE);
11991 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11992
79eb6904 11993 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 11994 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11995
a85feb8c
GZ		 11996 /* Assume an onboard device and WOL capable by default. */
11997 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11998
b5d3772c 11999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12000 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12001 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12002 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12003 }
0527ba35
MC		 12004 val = tr32(VCPU_CFGSHDW);
12005 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12006 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12007 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12008 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12009 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12010 goto done;
b5d3772c
MC		 12011 }
12012
1da177e4
LT		 12013 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12014 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12015 u32 nic_cfg, led_cfg;
a9daf367 12016 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12017 int eeprom_phy_serdes = 0;
1da177e4
LT		 12018
12019 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12020 tp->nic_sram_data_cfg = nic_cfg;
12021
12022 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12023 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12024 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12025 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12026 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12027 (ver > 0) && (ver < 0x100))
12028 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12029
a9daf367
MC		 12030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12031 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12032
1da177e4
LT		 12033 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12034 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12035 eeprom_phy_serdes = 1;
12036
12037 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12038 if (nic_phy_id != 0) {
12039 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12040 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12041
12042 eeprom_phy_id = (id1 >> 16) << 10;
12043 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12044 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12045 } else
12046 eeprom_phy_id = 0;
12047
7d0c41ef 12048 tp->phy_id = eeprom_phy_id;
747e8f8b 12049 if (eeprom_phy_serdes) {
d1ec96af
MC		 12050 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12052 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12053 else
12054 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12055 }
7d0c41ef 12056
cbf46853 12057 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12058 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12059 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12060 else
1da177e4
LT		 12061 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12062
12063 switch (led_cfg) {
12064 default:
12065 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12066 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12067 break;
12068
12069 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12070 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12071 break;
12072
12073 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12074 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12075
12076 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12077 * read on some older 5700/5701 bootcode.
12078 */
12079 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12080 ASIC_REV_5700 ||
12081 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12082 ASIC_REV_5701)
12083 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12084
1da177e4
LT		 12085 break;
12086
12087 case SHASTA_EXT_LED_SHARED:
12088 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12089 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12090 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12091 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12092 LED_CTRL_MODE_PHY_2);
12093 break;
12094
12095 case SHASTA_EXT_LED_MAC:
12096 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12097 break;
12098
12099 case SHASTA_EXT_LED_COMBO:
12100 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12101 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12102 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12103 LED_CTRL_MODE_PHY_2);
12104 break;
12105
855e1111 12106 }
1da177e4
LT		 12107
12108 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12110 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12111 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12112
b2a5c19c
MC		 12113 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12114 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12115
9d26e213 12116 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12117 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12118 if ((tp->pdev->subsystem_vendor ==
12119 PCI_VENDOR_ID_ARIMA) &&
12120 (tp->pdev->subsystem_device == 0x205a ||
12121 tp->pdev->subsystem_device == 0x2063))
12122 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12123 } else {
f49639e6 12124 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12125 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12126 }
1da177e4
LT		 12127
12128 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12129 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12130 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12131 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12132 }
b2b98d4a
MC		 12133
12134 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12135 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12136 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12137
a85feb8c
GZ		 12138 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12139 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12140 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12141
12dac075 12142 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12143 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12144 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12145
1da177e4
LT		 12146 if (cfg2 & (1 << 17))
12147 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12148
12149 /* serdes signal pre-emphasis in register 0x590 set by */
12150 /* bootcode if bit 18 is set */
12151 if (cfg2 & (1 << 18))
12152 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12153
321d32a0
MC		 12154 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12155 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12156 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12157 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12158
8ed5d97e
MC		 12159 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12160 u32 cfg3;
12161
12162 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12163 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12164 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12165 }
a9daf367 12166
14417063
MC		 12167 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12168 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
a9daf367
MC		 12169 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12170 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12171 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12172 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12173 }
05ac4cb7
MC		 12174done:
12175 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12176 device_set_wakeup_enable(&tp->pdev->dev,
12177 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12178}
12179
b2a5c19c
MC		 12180static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12181{
12182 int i;
12183 u32 val;
12184
12185 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12186 tw32(OTP_CTRL, cmd);
12187
12188 /* Wait for up to 1 ms for command to execute. */
12189 for (i = 0; i < 100; i++) {
12190 val = tr32(OTP_STATUS);
12191 if (val & OTP_STATUS_CMD_DONE)
12192 break;
12193 udelay(10);
12194 }
12195
12196 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12197}
12198
12199/* Read the gphy configuration from the OTP region of the chip. The gphy
12200 * configuration is a 32-bit value that straddles the alignment boundary.
12201 * We do two 32-bit reads and then shift and merge the results.
12202 */
12203static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12204{
12205 u32 bhalf_otp, thalf_otp;
12206
12207 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12208
12209 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12210 return 0;
12211
12212 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12213
12214 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12215 return 0;
12216
12217 thalf_otp = tr32(OTP_READ_DATA);
12218
12219 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12220
12221 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12222 return 0;
12223
12224 bhalf_otp = tr32(OTP_READ_DATA);
12225
12226 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12227}
12228
7d0c41ef
MC		 12229static int __devinit tg3_phy_probe(struct tg3 *tp)
12230{
12231 u32 hw_phy_id_1, hw_phy_id_2;
12232 u32 hw_phy_id, hw_phy_id_masked;
12233 int err;
1da177e4 12234
b02fd9e3
MC		 12235 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12236 return tg3_phy_init(tp);
12237
1da177e4 12238 /* Reading the PHY ID register can conflict with ASF
877d0310 12239 * firmware access to the PHY hardware.
1da177e4
LT		 12240 */
12241 err = 0;
0d3031d9
MC		 12242 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12243 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
79eb6904 12244 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 12245 } else {
12246 /* Now read the physical PHY_ID from the chip and verify
12247 * that it is sane. If it doesn't look good, we fall back
12248 * to either the hard-coded table based PHY_ID and failing
12249 * that the value found in the eeprom area.
12250 */
12251 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12252 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12253
12254 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12255 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12256 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12257
79eb6904 12258 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 12259 }
12260
79eb6904 12261 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 12262 tp->phy_id = hw_phy_id;
79eb6904 12263 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
1da177e4 12264 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12265 else
12266 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12267 } else {
79eb6904 12268 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 12269 /* Do nothing, phy ID already set up in
12270 * tg3_get_eeprom_hw_cfg().
12271 */
1da177e4
LT		 12272 } else {
12273 struct subsys_tbl_ent *p;
12274
12275 /* No eeprom signature? Try the hardcoded
12276 * subsys device table.
12277 */
24daf2b0 12278 p = tg3_lookup_by_subsys(tp);
1da177e4
LT		 12279 if (!p)
12280 return -ENODEV;
12281
12282 tp->phy_id = p->phy_id;
12283 if (!tp->phy_id ||
79eb6904 12284 tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 12285 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12286 }
12287 }
12288
747e8f8b 12289 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12290 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12291 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12292 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12293
12294 tg3_readphy(tp, MII_BMSR, &bmsr);
12295 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12296 (bmsr & BMSR_LSTATUS))
12297 goto skip_phy_reset;
6aa20a22 12298
1da177e4
LT		 12299 err = tg3_phy_reset(tp);
12300 if (err)
12301 return err;
12302
12303 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12304 ADVERTISE_100HALF | ADVERTISE_100FULL |
12305 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12306 tg3_ctrl = 0;
12307 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12308 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12309 MII_TG3_CTRL_ADV_1000_FULL);
12310 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12311 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12312 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12313 MII_TG3_CTRL_ENABLE_AS_MASTER);
12314 }
12315
3600d918
MC		 12316 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12317 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12318 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12319 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12320 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12321
12322 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12323 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12324
12325 tg3_writephy(tp, MII_BMCR,
12326 BMCR_ANENABLE | BMCR_ANRESTART);
12327 }
12328 tg3_phy_set_wirespeed(tp);
12329
12330 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12331 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12332 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12333 }
12334
12335skip_phy_reset:
79eb6904 12336 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 12337 err = tg3_init_5401phy_dsp(tp);
12338 if (err)
12339 return err;
1da177e4 12340
1da177e4
LT		 12341 err = tg3_init_5401phy_dsp(tp);
12342 }
12343
747e8f8b 12344 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12345 tp->link_config.advertising =
12346 (ADVERTISED_1000baseT_Half |
12347 ADVERTISED_1000baseT_Full |
12348 ADVERTISED_Autoneg |
12349 ADVERTISED_FIBRE);
12350 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12351 tp->link_config.advertising &=
12352 ~(ADVERTISED_1000baseT_Half |
12353 ADVERTISED_1000baseT_Full);
12354
12355 return err;
12356}
12357
184b8904 12358static void __devinit tg3_read_vpd(struct tg3 *tp)
1da177e4 12359{
184b8904 12360 u8 vpd_data[TG3_NVM_VPD_LEN];
4181b2c8 12361 unsigned int block_end, rosize, len;
184b8904 12362 int j, i = 0;
1b27777a 12363 u32 magic;
1da177e4 12364
df259d8c
MC		 12365 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12366 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12367 goto out_not_found;
1da177e4 12368
1820180b 12369 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12370 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12371 u32 tmp;
1da177e4 12372
6d348f2c
MC		 12373 /* The data is in little-endian format in NVRAM.
12374 * Use the big-endian read routines to preserve
12375 * the byte order as it exists in NVRAM.
12376 */
141518c9 12377 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12378 goto out_not_found;
12379
6d348f2c 12380 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12381 }
12382 } else {
94c982bd 12383 ssize_t cnt;
4181b2c8 12384 unsigned int pos = 0;
94c982bd
MC		 12385
12386 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12387 cnt = pci_read_vpd(tp->pdev, pos,
12388 TG3_NVM_VPD_LEN - pos,
12389 &vpd_data[pos]);
12390 if (cnt == -ETIMEDOUT || -EINTR)
12391 cnt = 0;
12392 else if (cnt < 0)
f49639e6 12393 goto out_not_found;
1b27777a 12394 }
94c982bd
MC		 12395 if (pos != TG3_NVM_VPD_LEN)
12396 goto out_not_found;
1da177e4
LT		 12397 }
12398
4181b2c8
MC		 12399 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12400 PCI_VPD_LRDT_RO_DATA);
12401 if (i < 0)
12402 goto out_not_found;
1da177e4 12403
4181b2c8
MC		 12404 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12405 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12406 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 12407
4181b2c8
MC		 12408 if (block_end > TG3_NVM_VPD_LEN)
12409 goto out_not_found;
af2c6a4a 12410
184b8904
MC		 12411 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12412 PCI_VPD_RO_KEYWORD_MFR_ID);
12413 if (j > 0) {
12414 len = pci_vpd_info_field_size(&vpd_data[j]);
12415
12416 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12417 if (j + len > block_end || len != 4 ||
12418 memcmp(&vpd_data[j], "1028", 4))
12419 goto partno;
12420
12421 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12422 PCI_VPD_RO_KEYWORD_VENDOR0);
12423 if (j < 0)
12424 goto partno;
12425
12426 len = pci_vpd_info_field_size(&vpd_data[j]);
12427
12428 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12429 if (j + len > block_end)
12430 goto partno;
12431
12432 memcpy(tp->fw_ver, &vpd_data[j], len);
12433 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12434 }
12435
12436partno:
4181b2c8
MC		 12437 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12438 PCI_VPD_RO_KEYWORD_PARTNO);
12439 if (i < 0)
12440 goto out_not_found;
af2c6a4a 12441
4181b2c8 12442 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 12443
4181b2c8
MC		 12444 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12445 if (len > TG3_BPN_SIZE ||
12446 (len + i) > TG3_NVM_VPD_LEN)
12447 goto out_not_found;
1da177e4 12448
4181b2c8 12449 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 12450
4181b2c8 12451 return;
1da177e4
LT		 12452
12453out_not_found:
b5d3772c
MC		 12454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12455 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12456 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12457 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12458 strcpy(tp->board_part_number, "BCM57780");
12459 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12460 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12461 strcpy(tp->board_part_number, "BCM57760");
12462 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12463 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12464 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12465 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12466 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12467 strcpy(tp->board_part_number, "BCM57788");
b474eca7
MC		 12468 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12469 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12470 strcpy(tp->board_part_number, "BCM57761");
12471 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12472 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
b703df6f 12473 strcpy(tp->board_part_number, "BCM57765");
b474eca7
MC		 12474 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12476 strcpy(tp->board_part_number, "BCM57781");
12477 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12478 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12479 strcpy(tp->board_part_number, "BCM57785");
12480 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12481 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12482 strcpy(tp->board_part_number, "BCM57791");
12483 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12484 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12485 strcpy(tp->board_part_number, "BCM57795");
b5d3772c
MC		 12486 else
12487 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12488}
12489
9c8a620e
MC		 12490static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12491{
12492 u32 val;
12493
e4f34110 12494 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12495 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12496 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12497 val != 0)
12498 return 0;
12499
12500 return 1;
12501}
12502
acd9c119
MC		 12503static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12504{
ff3a7cb2 12505 u32 val, offset, start, ver_offset;
75f9936e 12506 int i, dst_off;
ff3a7cb2 12507 bool newver = false;
acd9c119
MC		 12508
12509 if (tg3_nvram_read(tp, 0xc, &offset) ||
12510 tg3_nvram_read(tp, 0x4, &start))
12511 return;
12512
12513 offset = tg3_nvram_logical_addr(tp, offset);
12514
ff3a7cb2 12515 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12516 return;
12517
ff3a7cb2
MC		 12518 if ((val & 0xfc000000) == 0x0c000000) {
12519 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12520 return;
12521
ff3a7cb2
MC		 12522 if (val == 0)
12523 newver = true;
12524 }
12525
75f9936e
MC		 12526 dst_off = strlen(tp->fw_ver);
12527
ff3a7cb2 12528 if (newver) {
75f9936e
MC		 12529 if (TG3_VER_SIZE - dst_off < 16 ||
12530 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 12531 return;
12532
12533 offset = offset + ver_offset - start;
12534 for (i = 0; i < 16; i += 4) {
12535 __be32 v;
12536 if (tg3_nvram_read_be32(tp, offset + i, &v))
12537 return;
12538
75f9936e 12539 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 12540 }
12541 } else {
12542 u32 major, minor;
12543
12544 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12545 return;
12546
12547 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12548 TG3_NVM_BCVER_MAJSFT;
12549 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 12550 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12551 "v%d.%02d", major, minor);
acd9c119
MC		 12552 }
12553}
12554
a6f6cb1c
MC		 12555static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12556{
12557 u32 val, major, minor;
12558
12559 /* Use native endian representation */
12560 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12561 return;
12562
12563 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12564 TG3_NVM_HWSB_CFG1_MAJSFT;
12565 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12566 TG3_NVM_HWSB_CFG1_MINSFT;
12567
12568 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12569}
12570
dfe00d7d
MC		 12571static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12572{
12573 u32 offset, major, minor, build;
12574
75f9936e 12575 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 12576
12577 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12578 return;
12579
12580 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12581 case TG3_EEPROM_SB_REVISION_0:
12582 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12583 break;
12584 case TG3_EEPROM_SB_REVISION_2:
12585 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12586 break;
12587 case TG3_EEPROM_SB_REVISION_3:
12588 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12589 break;
a4153d40
MC		 12590 case TG3_EEPROM_SB_REVISION_4:
12591 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12592 break;
12593 case TG3_EEPROM_SB_REVISION_5:
12594 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12595 break;
dfe00d7d
MC		 12596 default:
12597 return;
12598 }
12599
e4f34110 12600 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12601 return;
12602
12603 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12604 TG3_EEPROM_SB_EDH_BLD_SHFT;
12605 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12606 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12607 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12608
12609 if (minor > 99 || build > 26)
12610 return;
12611
75f9936e
MC		 12612 offset = strlen(tp->fw_ver);
12613 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12614 " v%d.%02d", major, minor);
dfe00d7d
MC		 12615
12616 if (build > 0) {
75f9936e
MC		 12617 offset = strlen(tp->fw_ver);
12618 if (offset < TG3_VER_SIZE - 1)
12619 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 12620 }
12621}
12622
acd9c119 12623static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12624{
12625 u32 val, offset, start;
acd9c119 12626 int i, vlen;
9c8a620e
MC		 12627
12628 for (offset = TG3_NVM_DIR_START;
12629 offset < TG3_NVM_DIR_END;
12630 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12631 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12632 return;
12633
9c8a620e
MC		 12634 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12635 break;
12636 }
12637
12638 if (offset == TG3_NVM_DIR_END)
12639 return;
12640
12641 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12642 start = 0x08000000;
e4f34110 12643 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12644 return;
12645
e4f34110 12646 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12647 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12648 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12649 return;
12650
12651 offset += val - start;
12652
acd9c119 12653 vlen = strlen(tp->fw_ver);
9c8a620e 12654
acd9c119
MC		 12655 tp->fw_ver[vlen++] = ',';
12656 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12657
12658 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12659 __be32 v;
12660 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12661 return;
12662
b9fc7dc5 12663 offset += sizeof(v);
c4e6575c 12664
acd9c119
MC		 12665 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12666 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12667 break;
c4e6575c 12668 }
9c8a620e 12669
acd9c119
MC		 12670 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12671 vlen += sizeof(v);
c4e6575c 12672 }
acd9c119
MC		 12673}
12674
7fd76445
MC		 12675static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12676{
12677 int vlen;
12678 u32 apedata;
12679
12680 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12681 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12682 return;
12683
12684 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12685 if (apedata != APE_SEG_SIG_MAGIC)
12686 return;
12687
12688 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12689 if (!(apedata & APE_FW_STATUS_READY))
12690 return;
12691
12692 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12693
12694 vlen = strlen(tp->fw_ver);
12695
12696 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12697 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12698 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12699 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12700 (apedata & APE_FW_VERSION_BLDMSK));
12701}
12702
acd9c119
MC		 12703static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12704{
12705 u32 val;
75f9936e 12706 bool vpd_vers = false;
acd9c119 12707
75f9936e
MC		 12708 if (tp->fw_ver[0] != 0)
12709 vpd_vers = true;
df259d8c 12710
75f9936e
MC		 12711 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12712 strcat(tp->fw_ver, "sb");
df259d8c
MC		 12713 return;
12714 }
12715
acd9c119
MC		 12716 if (tg3_nvram_read(tp, 0, &val))
12717 return;
12718
12719 if (val == TG3_EEPROM_MAGIC)
12720 tg3_read_bc_ver(tp);
12721 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12722 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12723 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12724 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12725 else
12726 return;
12727
12728 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
75f9936e
MC		 12729 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12730 goto done;
acd9c119
MC		 12731
12732 tg3_read_mgmtfw_ver(tp);
9c8a620e 12733
75f9936e 12734done:
9c8a620e 12735 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12736}
12737
7544b097
MC		 12738static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12739
1da177e4
LT		 12740static int __devinit tg3_get_invariants(struct tg3 *tp)
12741{
12742 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4 12743 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
c6cdf436 12744 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004 12745 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
c6cdf436 12746 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12747 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12748 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12749 { },
12750 };
12751 u32 misc_ctrl_reg;
1da177e4
LT		 12752 u32 pci_state_reg, grc_misc_cfg;
12753 u32 val;
12754 u16 pci_cmd;
5e7dfd0f 12755 int err;
1da177e4 12756
1da177e4
LT		 12757 /* Force memory write invalidate off. If we leave it on,
12758 * then on 5700_BX chips we have to enable a workaround.
12759 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12760 * to match the cacheline size. The Broadcom driver have this
12761 * workaround but turns MWI off all the times so never uses
12762 * it. This seems to suggest that the workaround is insufficient.
12763 */
12764 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12765 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12766 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12767
12768 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12769 * has the register indirect write enable bit set before
12770 * we try to access any of the MMIO registers. It is also
12771 * critical that the PCI-X hw workaround situation is decided
12772 * before that as well.
12773 */
12774 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12775 &misc_ctrl_reg);
12776
12777 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12778 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12780 u32 prod_id_asic_rev;
12781
5001e2f6
MC		 12782 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12785 pci_read_config_dword(tp->pdev,
12786 TG3PCI_GEN2_PRODID_ASICREV,
12787 &prod_id_asic_rev);
b703df6f
MC		 12788 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12789 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12790 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12791 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12793 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12794 pci_read_config_dword(tp->pdev,
12795 TG3PCI_GEN15_PRODID_ASICREV,
12796 &prod_id_asic_rev);
f6eb9b1f
MC		 12797 else
12798 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12799 &prod_id_asic_rev);
12800
321d32a0 12801 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12802 }
1da177e4 12803
ff645bec
MC		 12804 /* Wrong chip ID in 5752 A0. This code can be removed later
12805 * as A0 is not in production.
12806 */
12807 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12808 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12809
6892914f
MC		 12810 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12811 * we need to disable memory and use config. cycles
12812 * only to access all registers. The 5702/03 chips
12813 * can mistakenly decode the special cycles from the
12814 * ICH chipsets as memory write cycles, causing corruption
12815 * of register and memory space. Only certain ICH bridges
12816 * will drive special cycles with non-zero data during the
12817 * address phase which can fall within the 5703's address
12818 * range. This is not an ICH bug as the PCI spec allows
12819 * non-zero address during special cycles. However, only
12820 * these ICH bridges are known to drive non-zero addresses
12821 * during special cycles.
12822 *
12823 * Since special cycles do not cross PCI bridges, we only
12824 * enable this workaround if the 5703 is on the secondary
12825 * bus of these ICH bridges.
12826 */
12827 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12828 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12829 static struct tg3_dev_id {
12830 u32 vendor;
12831 u32 device;
12832 u32 rev;
12833 } ich_chipsets[] = {
12834 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12835 PCI_ANY_ID },
12836 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12837 PCI_ANY_ID },
12838 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12839 0xa },
12840 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12841 PCI_ANY_ID },
12842 { },
12843 };
12844 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12845 struct pci_dev *bridge = NULL;
12846
12847 while (pci_id->vendor != 0) {
12848 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12849 bridge);
12850 if (!bridge) {
12851 pci_id++;
12852 continue;
12853 }
12854 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12855 if (bridge->revision > pci_id->rev)
6892914f
MC		 12856 continue;
12857 }
12858 if (bridge->subordinate &&
12859 (bridge->subordinate->number ==
12860 tp->pdev->bus->number)) {
12861
12862 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12863 pci_dev_put(bridge);
12864 break;
12865 }
12866 }
12867 }
12868
41588ba1
MC		 12869 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12870 static struct tg3_dev_id {
12871 u32 vendor;
12872 u32 device;
12873 } bridge_chipsets[] = {
12874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12875 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12876 { },
12877 };
12878 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12879 struct pci_dev *bridge = NULL;
12880
12881 while (pci_id->vendor != 0) {
12882 bridge = pci_get_device(pci_id->vendor,
12883 pci_id->device,
12884 bridge);
12885 if (!bridge) {
12886 pci_id++;
12887 continue;
12888 }
12889 if (bridge->subordinate &&
12890 (bridge->subordinate->number <=
12891 tp->pdev->bus->number) &&
12892 (bridge->subordinate->subordinate >=
12893 tp->pdev->bus->number)) {
12894 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12895 pci_dev_put(bridge);
12896 break;
12897 }
12898 }
12899 }
12900
4a29cc2e
MC		 12901 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12902 * DMA addresses > 40-bit. This bridge may have other additional
12903 * 57xx devices behind it in some 4-port NIC designs for example.
12904 * Any tg3 device found behind the bridge will also need the 40-bit
12905 * DMA workaround.
12906 */
a4e2b347
MC		 12907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12909 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12910 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12911 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
859a5887 12912 } else {
4a29cc2e
MC		 12913 struct pci_dev *bridge = NULL;
12914
12915 do {
12916 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12917 PCI_DEVICE_ID_SERVERWORKS_EPB,
12918 bridge);
12919 if (bridge && bridge->subordinate &&
12920 (bridge->subordinate->number <=
12921 tp->pdev->bus->number) &&
12922 (bridge->subordinate->subordinate >=
12923 tp->pdev->bus->number)) {
12924 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12925 pci_dev_put(bridge);
12926 break;
12927 }
12928 } while (bridge);
12929 }
4cf78e4f 12930
1da177e4
LT		 12931 /* Initialize misc host control in PCI block. */
12932 tp->misc_host_ctrl |= (misc_ctrl_reg &
12933 MISC_HOST_CTRL_CHIPREV);
12934 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12935 tp->misc_host_ctrl);
12936
f6eb9b1f
MC		 12937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12940 tp->pdev_peer = tg3_find_peer(tp);
12941
321d32a0
MC		 12942 /* Intentionally exclude ASIC_REV_5906 */
12943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 12948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 12951 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12952
12953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12956 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12957 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12958 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12959
1b440c56
JL		 12960 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12961 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12962 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12963
027455ad
MC		 12964 /* 5700 B0 chips do not support checksumming correctly due
12965 * to hardware bugs.
12966 */
12967 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12968 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12969 else {
12970 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12971 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12972 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12973 tp->dev->features |= NETIF_F_IPV6_CSUM;
12974 }
12975
507399f1 12976 /* Determine TSO capabilities */
b703df6f
MC		 12977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 12979 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12980 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 12982 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12983 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12984 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12986 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12987 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12988 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12989 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12990 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12991 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12993 tp->fw_needed = FIRMWARE_TG3TSO5;
12994 else
12995 tp->fw_needed = FIRMWARE_TG3TSO;
12996 }
12997
12998 tp->irq_max = 1;
12999
5a6f3074 13000 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13001 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13002 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13003 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13004 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13005 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13006 tp->pdev_peer == tp->pdev))
13007 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13008
321d32a0 13009 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13011 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13012 }
4f125f42 13013
b703df6f
MC		 13014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13016 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13017 tp->irq_max = TG3_IRQ_MAX_VECS;
13018 }
f6eb9b1f 13019 }
0e1406dd 13020
615774fe
MC		 13021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13023 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13024 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13025 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13026 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13027 }
f6eb9b1f 13028
b703df6f
MC		 13029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13031 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13032
f51f3562 13033 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
c6cdf436
MC		 13034 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13035 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13036 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13037
52f4490c
MC		 13038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13039 &pci_state_reg);
13040
5e7dfd0f
MC		 13041 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13042 if (tp->pcie_cap != 0) {
13043 u16 lnkctl;
13044
1da177e4 13045 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13046
13047 pcie_set_readrq(tp->pdev, 4096);
13048
5e7dfd0f
MC		 13049 pci_read_config_word(tp->pdev,
13050 tp->pcie_cap + PCI_EXP_LNKCTL,
13051 &lnkctl);
13052 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13054 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13057 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13058 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13059 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13060 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13061 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13062 }
52f4490c 13063 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13064 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13065 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13066 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13067 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13068 if (!tp->pcix_cap) {
2445e461
MC		 13069 dev_err(&tp->pdev->dev,
13070 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 13071 return -EIO;
13072 }
13073
13074 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13075 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13076 }
1da177e4 13077
399de50b
MC		 13078 /* If we have an AMD 762 or VIA K8T800 chipset, write
13079 * reordering to the mailbox registers done by the host
13080 * controller can cause major troubles. We read back from
13081 * every mailbox register write to force the writes to be
13082 * posted to the chip in order.
13083 */
13084 if (pci_dev_present(write_reorder_chipsets) &&
13085 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13086 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13087
69fc4053
MC		 13088 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13089 &tp->pci_cacheline_sz);
13090 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13091 &tp->pci_lat_timer);
1da177e4
LT		 13092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13093 tp->pci_lat_timer < 64) {
13094 tp->pci_lat_timer = 64;
69fc4053
MC		 13095 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13096 tp->pci_lat_timer);
1da177e4
LT		 13097 }
13098
52f4490c
MC		 13099 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13100 /* 5700 BX chips need to have their TX producer index
13101 * mailboxes written twice to workaround a bug.
13102 */
13103 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13104
52f4490c 13105 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13106 *
13107 * The workaround is to use indirect register accesses
13108 * for all chip writes not to mailbox registers.
13109 */
52f4490c 13110 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13111 u32 pm_reg;
1da177e4
LT		 13112
13113 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13114
13115 /* The chip can have it's power management PCI config
13116 * space registers clobbered due to this bug.
13117 * So explicitly force the chip into D0 here.
13118 */
9974a356
MC		 13119 pci_read_config_dword(tp->pdev,
13120 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13121 &pm_reg);
13122 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13123 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13124 pci_write_config_dword(tp->pdev,
13125 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13126 pm_reg);
13127
13128 /* Also, force SERR#/PERR# in PCI command. */
13129 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13130 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13131 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13132 }
13133 }
13134
1da177e4
LT		 13135 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13136 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13137 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13138 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13139
13140 /* Chip-specific fixup from Broadcom driver */
13141 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13142 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13143 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13144 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13145 }
13146
1ee582d8 13147 /* Default fast path register access methods */
20094930 13148 tp->read32 = tg3_read32;
1ee582d8 13149 tp->write32 = tg3_write32;
09ee929c 13150 tp->read32_mbox = tg3_read32;
20094930 13151 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13152 tp->write32_tx_mbox = tg3_write32;
13153 tp->write32_rx_mbox = tg3_write32;
13154
13155 /* Various workaround register access methods */
13156 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13157 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13158 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13159 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13160 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13161 /*
13162 * Back to back register writes can cause problems on these
13163 * chips, the workaround is to read back all reg writes
13164 * except those to mailbox regs.
13165 *
13166 * See tg3_write_indirect_reg32().
13167 */
1ee582d8 13168 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13169 }
13170
1ee582d8
MC		 13171 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13172 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13173 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13174 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13175 tp->write32_rx_mbox = tg3_write_flush_reg32;
13176 }
20094930 13177
6892914f
MC		 13178 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13179 tp->read32 = tg3_read_indirect_reg32;
13180 tp->write32 = tg3_write_indirect_reg32;
13181 tp->read32_mbox = tg3_read_indirect_mbox;
13182 tp->write32_mbox = tg3_write_indirect_mbox;
13183 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13184 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13185
13186 iounmap(tp->regs);
22abe310 13187 tp->regs = NULL;
6892914f
MC		 13188
13189 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13190 pci_cmd &= ~PCI_COMMAND_MEMORY;
13191 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13192 }
b5d3772c
MC		 13193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13194 tp->read32_mbox = tg3_read32_mbox_5906;
13195 tp->write32_mbox = tg3_write32_mbox_5906;
13196 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13197 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13198 }
6892914f 13199
bbadf503
MC		 13200 if (tp->write32 == tg3_write_indirect_reg32 ||
13201 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13202 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13204 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13205
7d0c41ef 13206 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13207 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13208 * determined before calling tg3_set_power_state() so that
13209 * we know whether or not to switch out of Vaux power.
13210 * When the flag is set, it means that GPIO1 is used for eeprom
13211 * write protect and also implies that it is a LOM where GPIOs
13212 * are not used to switch power.
6aa20a22 13213 */
7d0c41ef
MC		 13214 tg3_get_eeprom_hw_cfg(tp);
13215
0d3031d9
MC		 13216 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13217 /* Allow reads and writes to the
13218 * APE register and memory space.
13219 */
13220 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13221 PCISTATE_ALLOW_APE_SHMEM_WR;
13222 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13223 pci_state_reg);
13224 }
13225
9936bcf6 13226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13232 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13233
314fba34
MC		 13234 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13235 * GPIO1 driven high will bring 5700's external PHY out of reset.
13236 * It is also used as eeprom write protect on LOMs.
13237 */
13238 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13239 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13240 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13241 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13242 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13243 /* Unused GPIO3 must be driven as output on 5752 because there
13244 * are no pull-up resistors on unused GPIO pins.
13245 */
13246 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13247 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13248
321d32a0 13249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13252 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13253
8d519ab2
MC		 13254 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13255 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13256 /* Turn off the debug UART. */
13257 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13258 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13259 /* Keep VMain power. */
13260 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13261 GRC_LCLCTRL_GPIO_OUTPUT0;
13262 }
13263
1da177e4 13264 /* Force the chip into D0. */
bc1c7567 13265 err = tg3_set_power_state(tp, PCI_D0);
1da177e4 13266 if (err) {
2445e461 13267 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
1da177e4
LT		 13268 return err;
13269 }
13270
1da177e4
LT		 13271 /* Derive initial jumbo mode from MTU assigned in
13272 * ether_setup() via the alloc_etherdev() call
13273 */
0f893dc6 13274 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13275 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13276 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13277
13278 /* Determine WakeOnLan speed to use. */
13279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13280 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13281 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13282 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13283 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13284 } else {
13285 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13286 }
13287
7f97a4bd
MC		 13288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13289 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13290
1da177e4
LT		 13291 /* A few boards don't want Ethernet@WireSpeed phy feature */
13292 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13293 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13294 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13295 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13296 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13297 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13298 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13299
13300 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13301 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13302 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13303 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13304 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13305
321d32a0 13306 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13307 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13308 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13309 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13310 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13311 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13316 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13317 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13318 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13319 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13320 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13321 } else
c424cb24
MC		 13322 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13323 }
1da177e4 13324
b2a5c19c
MC		 13325 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13326 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13327 tp->phy_otp = tg3_read_otp_phycfg(tp);
13328 if (tp->phy_otp == 0)
13329 tp->phy_otp = TG3_OTP_DEFAULT;
13330 }
13331
f51f3562 13332 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13333 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13334 else
13335 tp->mi_mode = MAC_MI_MODE_BASE;
13336
1da177e4 13337 tp->coalesce_mode = 0;
1da177e4
LT		 13338 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13339 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13340 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13341
321d32a0
MC		 13342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13344 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13345
158d7abd
MC		 13346 err = tg3_mdio_init(tp);
13347 if (err)
13348 return err;
1da177e4 13349
55dffe79
MC		 13350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13351 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13352 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13353 return -ENOTSUPP;
13354
1da177e4
LT		 13355 /* Initialize data/descriptor byte/word swapping. */
13356 val = tr32(GRC_MODE);
13357 val &= GRC_MODE_HOST_STACKUP;
13358 tw32(GRC_MODE, val | tp->grc_mode);
13359
13360 tg3_switch_clocks(tp);
13361
13362 /* Clear this out for sanity. */
13363 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13364
13365 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13366 &pci_state_reg);
13367 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13368 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13369 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13370
13371 if (chiprevid == CHIPREV_ID_5701_A0 ||
13372 chiprevid == CHIPREV_ID_5701_B0 ||
13373 chiprevid == CHIPREV_ID_5701_B2 ||
13374 chiprevid == CHIPREV_ID_5701_B5) {
13375 void __iomem *sram_base;
13376
13377 /* Write some dummy words into the SRAM status block
13378 * area, see if it reads back correctly. If the return
13379 * value is bad, force enable the PCIX workaround.
13380 */
13381 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13382
13383 writel(0x00000000, sram_base);
13384 writel(0x00000000, sram_base + 4);
13385 writel(0xffffffff, sram_base + 4);
13386 if (readl(sram_base) != 0x00000000)
13387 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13388 }
13389 }
13390
13391 udelay(50);
13392 tg3_nvram_init(tp);
13393
13394 grc_misc_cfg = tr32(GRC_MISC_CFG);
13395 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13396
1da177e4
LT		 13397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13398 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13399 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13400 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13401
fac9b83e
DM		 13402 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13403 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13404 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13405 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13406 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13407 HOSTCC_MODE_CLRTICK_TXBD);
13408
13409 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13410 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13411 tp->misc_host_ctrl);
13412 }
13413
3bda1258
MC		 13414 /* Preserve the APE MAC_MODE bits */
13415 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13416 tp->mac_mode = tr32(MAC_MODE) |
13417 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13418 else
13419 tp->mac_mode = TG3_DEF_MAC_MODE;
13420
1da177e4
LT		 13421 /* these are limited to 10/100 only */
13422 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13423 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13424 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13425 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13426 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13427 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13428 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13429 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13430 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13431 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13432 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13433 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
d1101142
MC		 13434 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13435 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
7f97a4bd 13436 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13437 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13438
13439 err = tg3_phy_probe(tp);
13440 if (err) {
2445e461 13441 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 13442 /* ... but do not return immediately ... */
b02fd9e3 13443 tg3_mdio_fini(tp);
1da177e4
LT		 13444 }
13445
184b8904 13446 tg3_read_vpd(tp);
c4e6575c 13447 tg3_read_fw_ver(tp);
1da177e4
LT		 13448
13449 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13450 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13451 } else {
13452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13453 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13454 else
13455 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13456 }
13457
13458 /* 5700 {AX,BX} chips have a broken status block link
13459 * change bit implementation, so we must use the
13460 * status register in those cases.
13461 */
13462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13463 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13464 else
13465 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13466
13467 /* The led_ctrl is set during tg3_phy_probe, here we might
13468 * have to force the link status polling mechanism based
13469 * upon subsystem IDs.
13470 */
13471 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13473 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13474 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13475 TG3_FLAG_USE_LINKCHG_REG);
13476 }
13477
13478 /* For all SERDES we poll the MAC status register. */
13479 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13480 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13481 else
13482 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13483
ad829268 13484 tp->rx_offset = NET_IP_ALIGN;
d2757fc4 13485 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
1da177e4 13486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
d2757fc4 13487 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
1da177e4 13488 tp->rx_offset = 0;
d2757fc4
MC		 13489#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13490 tp->rx_copy_thresh = ~0;
13491#endif
13492 }
1da177e4 13493
f92905de
MC		 13494 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13495
13496 /* Increment the rx prod index on the rx std ring by at most
13497 * 8 for these chips to workaround hw errata.
13498 */
13499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13502 tp->rx_std_max_post = 8;
13503
8ed5d97e
MC		 13504 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13505 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13506 PCIE_PWR_MGMT_L1_THRESH_MSK;
13507
1da177e4
LT		 13508 return err;
13509}
13510
49b6e95f 13511#ifdef CONFIG_SPARC
1da177e4
LT		 13512static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13513{
13514 struct net_device *dev = tp->dev;
13515 struct pci_dev *pdev = tp->pdev;
49b6e95f 13516 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13517 const unsigned char *addr;
49b6e95f
DM		 13518 int len;
13519
13520 addr = of_get_property(dp, "local-mac-address", &len);
13521 if (addr && len == 6) {
13522 memcpy(dev->dev_addr, addr, 6);
13523 memcpy(dev->perm_addr, dev->dev_addr, 6);
13524 return 0;
1da177e4
LT		 13525 }
13526 return -ENODEV;
13527}
13528
13529static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13530{
13531 struct net_device *dev = tp->dev;
13532
13533 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13534 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13535 return 0;
13536}
13537#endif
13538
13539static int __devinit tg3_get_device_address(struct tg3 *tp)
13540{
13541 struct net_device *dev = tp->dev;
13542 u32 hi, lo, mac_offset;
008652b3 13543 int addr_ok = 0;
1da177e4 13544
49b6e95f 13545#ifdef CONFIG_SPARC
1da177e4
LT		 13546 if (!tg3_get_macaddr_sparc(tp))
13547 return 0;
13548#endif
13549
13550 mac_offset = 0x7c;
f49639e6 13551 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13552 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13553 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13554 mac_offset = 0xcc;
13555 if (tg3_nvram_lock(tp))
13556 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13557 else
13558 tg3_nvram_unlock(tp);
a1b950d5
MC		 13559 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13560 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13561 mac_offset = 0xcc;
13562 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13563 mac_offset = 0x10;
1da177e4
LT		 13564
13565 /* First try to get it from MAC address mailbox. */
13566 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13567 if ((hi >> 16) == 0x484b) {
13568 dev->dev_addr[0] = (hi >> 8) & 0xff;
13569 dev->dev_addr[1] = (hi >> 0) & 0xff;
13570
13571 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13572 dev->dev_addr[2] = (lo >> 24) & 0xff;
13573 dev->dev_addr[3] = (lo >> 16) & 0xff;
13574 dev->dev_addr[4] = (lo >> 8) & 0xff;
13575 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13576
008652b3
MC		 13577 /* Some old bootcode may report a 0 MAC address in SRAM */
13578 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13579 }
13580 if (!addr_ok) {
13581 /* Next, try NVRAM. */
df259d8c
MC		 13582 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13583 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13584 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13585 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13586 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13587 }
13588 /* Finally just fetch it out of the MAC control regs. */
13589 else {
13590 hi = tr32(MAC_ADDR_0_HIGH);
13591 lo = tr32(MAC_ADDR_0_LOW);
13592
13593 dev->dev_addr[5] = lo & 0xff;
13594 dev->dev_addr[4] = (lo >> 8) & 0xff;
13595 dev->dev_addr[3] = (lo >> 16) & 0xff;
13596 dev->dev_addr[2] = (lo >> 24) & 0xff;
13597 dev->dev_addr[1] = hi & 0xff;
13598 dev->dev_addr[0] = (hi >> 8) & 0xff;
13599 }
1da177e4
LT		 13600 }
13601
13602 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13603#ifdef CONFIG_SPARC
1da177e4
LT		 13604 if (!tg3_get_default_macaddr_sparc(tp))
13605 return 0;
13606#endif
13607 return -EINVAL;
13608 }
2ff43697 13609 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13610 return 0;
13611}
13612
59e6b434
DM		 13613#define BOUNDARY_SINGLE_CACHELINE 1
13614#define BOUNDARY_MULTI_CACHELINE 2
13615
13616static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13617{
13618 int cacheline_size;
13619 u8 byte;
13620 int goal;
13621
13622 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13623 if (byte == 0)
13624 cacheline_size = 1024;
13625 else
13626 cacheline_size = (int) byte * 4;
13627
13628 /* On 5703 and later chips, the boundary bits have no
13629 * effect.
13630 */
13631 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13632 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13633 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13634 goto out;
13635
13636#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13637 goal = BOUNDARY_MULTI_CACHELINE;
13638#else
13639#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13640 goal = BOUNDARY_SINGLE_CACHELINE;
13641#else
13642 goal = 0;
13643#endif
13644#endif
13645
b703df6f
MC		 13646 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13648 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13649 goto out;
13650 }
13651
59e6b434
DM		 13652 if (!goal)
13653 goto out;
13654
13655 /* PCI controllers on most RISC systems tend to disconnect
13656 * when a device tries to burst across a cache-line boundary.
13657 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13658 *
13659 * Unfortunately, for PCI-E there are only limited
13660 * write-side controls for this, and thus for reads
13661 * we will still get the disconnects. We'll also waste
13662 * these PCI cycles for both read and write for chips
13663 * other than 5700 and 5701 which do not implement the
13664 * boundary bits.
13665 */
13666 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13667 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13668 switch (cacheline_size) {
13669 case 16:
13670 case 32:
13671 case 64:
13672 case 128:
13673 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13674 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13675 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13676 } else {
13677 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13678 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13679 }
13680 break;
13681
13682 case 256:
13683 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13684 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13685 break;
13686
13687 default:
13688 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13689 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13690 break;
855e1111 13691 }
59e6b434
DM		 13692 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13693 switch (cacheline_size) {
13694 case 16:
13695 case 32:
13696 case 64:
13697 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13698 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13699 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13700 break;
13701 }
13702 /* fallthrough */
13703 case 128:
13704 default:
13705 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13706 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13707 break;
855e1111 13708 }
59e6b434
DM		 13709 } else {
13710 switch (cacheline_size) {
13711 case 16:
13712 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13713 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13714 DMA_RWCTRL_WRITE_BNDRY_16);
13715 break;
13716 }
13717 /* fallthrough */
13718 case 32:
13719 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13720 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13721 DMA_RWCTRL_WRITE_BNDRY_32);
13722 break;
13723 }
13724 /* fallthrough */
13725 case 64:
13726 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13727 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13728 DMA_RWCTRL_WRITE_BNDRY_64);
13729 break;
13730 }
13731 /* fallthrough */
13732 case 128:
13733 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13734 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13735 DMA_RWCTRL_WRITE_BNDRY_128);
13736 break;
13737 }
13738 /* fallthrough */
13739 case 256:
13740 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13741 DMA_RWCTRL_WRITE_BNDRY_256);
13742 break;
13743 case 512:
13744 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13745 DMA_RWCTRL_WRITE_BNDRY_512);
13746 break;
13747 case 1024:
13748 default:
13749 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13750 DMA_RWCTRL_WRITE_BNDRY_1024);
13751 break;
855e1111 13752 }
59e6b434
DM		 13753 }
13754
13755out:
13756 return val;
13757}
13758
1da177e4
LT		 13759static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13760{
13761 struct tg3_internal_buffer_desc test_desc;
13762 u32 sram_dma_descs;
13763 int i, ret;
13764
13765 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13766
13767 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13768 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13769 tw32(RDMAC_STATUS, 0);
13770 tw32(WDMAC_STATUS, 0);
13771
13772 tw32(BUFMGR_MODE, 0);
13773 tw32(FTQ_RESET, 0);
13774
13775 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13776 test_desc.addr_lo = buf_dma & 0xffffffff;
13777 test_desc.nic_mbuf = 0x00002100;
13778 test_desc.len = size;
13779
13780 /*
13781 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13782 * the *second* time the tg3 driver was getting loaded after an
13783 * initial scan.
13784 *
13785 * Broadcom tells me:
13786 * ...the DMA engine is connected to the GRC block and a DMA
13787 * reset may affect the GRC block in some unpredictable way...
13788 * The behavior of resets to individual blocks has not been tested.
13789 *
13790 * Broadcom noted the GRC reset will also reset all sub-components.
13791 */
13792 if (to_device) {
13793 test_desc.cqid_sqid = (13 << 8) | 2;
13794
13795 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13796 udelay(40);
13797 } else {
13798 test_desc.cqid_sqid = (16 << 8) | 7;
13799
13800 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13801 udelay(40);
13802 }
13803 test_desc.flags = 0x00000005;
13804
13805 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13806 u32 val;
13807
13808 val = *(((u32 *)&test_desc) + i);
13809 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13810 sram_dma_descs + (i * sizeof(u32)));
13811 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13812 }
13813 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13814
859a5887 13815 if (to_device)
1da177e4 13816 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 13817 else
1da177e4 13818 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 13819
13820 ret = -ENODEV;
13821 for (i = 0; i < 40; i++) {
13822 u32 val;
13823
13824 if (to_device)
13825 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13826 else
13827 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13828 if ((val & 0xffff) == sram_dma_descs) {
13829 ret = 0;
13830 break;
13831 }
13832
13833 udelay(100);
13834 }
13835
13836 return ret;
13837}
13838
ded7340d 13839#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13840
13841static int __devinit tg3_test_dma(struct tg3 *tp)
13842{
13843 dma_addr_t buf_dma;
59e6b434 13844 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13845 int ret = 0;
1da177e4
LT		 13846
13847 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13848 if (!buf) {
13849 ret = -ENOMEM;
13850 goto out_nofree;
13851 }
13852
13853 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13854 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13855
59e6b434 13856 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13857
b703df6f
MC		 13858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13860 goto out;
13861
1da177e4
LT		 13862 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13863 /* DMA read watermark not used on PCIE */
13864 tp->dma_rwctrl |= 0x00180000;
13865 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13868 tp->dma_rwctrl |= 0x003f0000;
13869 else
13870 tp->dma_rwctrl |= 0x003f000f;
13871 } else {
13872 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13873 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13874 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13875 u32 read_water = 0x7;
1da177e4 13876
4a29cc2e
MC		 13877 /* If the 5704 is behind the EPB bridge, we can
13878 * do the less restrictive ONE_DMA workaround for
13879 * better performance.
13880 */
13881 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13883 tp->dma_rwctrl |= 0x8000;
13884 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13885 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13886
49afdeb6
MC		 13887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13888 read_water = 4;
59e6b434 13889 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13890 tp->dma_rwctrl |=
13891 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13892 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13893 (1 << 23);
4cf78e4f
MC		 13894 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13895 /* 5780 always in PCIX mode */
13896 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13897 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13898 /* 5714 always in PCIX mode */
13899 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13900 } else {
13901 tp->dma_rwctrl |= 0x001b000f;
13902 }
13903 }
13904
13905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13907 tp->dma_rwctrl &= 0xfffffff0;
13908
13909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13911 /* Remove this if it causes problems for some boards. */
13912 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13913
13914 /* On 5700/5701 chips, we need to set this bit.
13915 * Otherwise the chip will issue cacheline transactions
13916 * to streamable DMA memory with not all the byte
13917 * enables turned on. This is an error on several
13918 * RISC PCI controllers, in particular sparc64.
13919 *
13920 * On 5703/5704 chips, this bit has been reassigned
13921 * a different meaning. In particular, it is used
13922 * on those chips to enable a PCI-X workaround.
13923 */
13924 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13925 }
13926
13927 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13928
13929#if 0
13930 /* Unneeded, already done by tg3_get_invariants. */
13931 tg3_switch_clocks(tp);
13932#endif
13933
1da177e4
LT		 13934 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13935 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13936 goto out;
13937
59e6b434
DM		 13938 /* It is best to perform DMA test with maximum write burst size
13939 * to expose the 5700/5701 write DMA bug.
13940 */
13941 saved_dma_rwctrl = tp->dma_rwctrl;
13942 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13943 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13944
1da177e4
LT		 13945 while (1) {
13946 u32 *p = buf, i;
13947
13948 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13949 p[i] = i;
13950
13951 /* Send the buffer to the chip. */
13952 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13953 if (ret) {
2445e461
MC		 13954 dev_err(&tp->pdev->dev,
13955 "%s: Buffer write failed. err = %d\n",
13956 __func__, ret);
1da177e4
LT		 13957 break;
13958 }
13959
13960#if 0
13961 /* validate data reached card RAM correctly. */
13962 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13963 u32 val;
13964 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13965 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 13966 dev_err(&tp->pdev->dev,
13967 "%s: Buffer corrupted on device! "
13968 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 13969 /* ret = -ENODEV here? */
13970 }
13971 p[i] = 0;
13972 }
13973#endif
13974 /* Now read it back. */
13975 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13976 if (ret) {
5129c3a3
MC		 13977 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
13978 "err = %d\n", __func__, ret);
1da177e4
LT		 13979 break;
13980 }
13981
13982 /* Verify it. */
13983 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13984 if (p[i] == i)
13985 continue;
13986
59e6b434
DM		 13987 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13988 DMA_RWCTRL_WRITE_BNDRY_16) {
13989 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13990 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13991 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13992 break;
13993 } else {
2445e461
MC		 13994 dev_err(&tp->pdev->dev,
13995 "%s: Buffer corrupted on read back! "
13996 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 13997 ret = -ENODEV;
13998 goto out;
13999 }
14000 }
14001
14002 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14003 /* Success. */
14004 ret = 0;
14005 break;
14006 }
14007 }
59e6b434
DM		 14008 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14009 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14010 static struct pci_device_id dma_wait_state_chipsets[] = {
14011 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14012 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14013 { },
14014 };
14015
59e6b434 14016 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14017 * now look for chipsets that are known to expose the
14018 * DMA bug without failing the test.
59e6b434 14019 */
6d1cfbab
MC		 14020 if (pci_dev_present(dma_wait_state_chipsets)) {
14021 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14022 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 14023 } else {
6d1cfbab
MC		 14024 /* Safe to use the calculated DMA boundary. */
14025 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 14026 }
6d1cfbab 14027
59e6b434
DM		 14028 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14029 }
1da177e4
LT		 14030
14031out:
14032 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14033out_nofree:
14034 return ret;
14035}
14036
14037static void __devinit tg3_init_link_config(struct tg3 *tp)
14038{
14039 tp->link_config.advertising =
14040 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14041 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14042 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14043 ADVERTISED_Autoneg | ADVERTISED_MII);
14044 tp->link_config.speed = SPEED_INVALID;
14045 tp->link_config.duplex = DUPLEX_INVALID;
14046 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14047 tp->link_config.active_speed = SPEED_INVALID;
14048 tp->link_config.active_duplex = DUPLEX_INVALID;
14049 tp->link_config.phy_is_low_power = 0;
14050 tp->link_config.orig_speed = SPEED_INVALID;
14051 tp->link_config.orig_duplex = DUPLEX_INVALID;
14052 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14053}
14054
14055static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14056{
666bc831
MC		 14057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14059 tp->bufmgr_config.mbuf_read_dma_low_water =
14060 DEFAULT_MB_RDMA_LOW_WATER_5705;
14061 tp->bufmgr_config.mbuf_mac_rx_low_water =
14062 DEFAULT_MB_MACRX_LOW_WATER_57765;
14063 tp->bufmgr_config.mbuf_high_water =
14064 DEFAULT_MB_HIGH_WATER_57765;
14065
14066 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14067 DEFAULT_MB_RDMA_LOW_WATER_5705;
14068 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14069 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14070 tp->bufmgr_config.mbuf_high_water_jumbo =
14071 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14072 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14073 tp->bufmgr_config.mbuf_read_dma_low_water =
14074 DEFAULT_MB_RDMA_LOW_WATER_5705;
14075 tp->bufmgr_config.mbuf_mac_rx_low_water =
14076 DEFAULT_MB_MACRX_LOW_WATER_5705;
14077 tp->bufmgr_config.mbuf_high_water =
14078 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14080 tp->bufmgr_config.mbuf_mac_rx_low_water =
14081 DEFAULT_MB_MACRX_LOW_WATER_5906;
14082 tp->bufmgr_config.mbuf_high_water =
14083 DEFAULT_MB_HIGH_WATER_5906;
14084 }
fdfec172
MC		 14085
14086 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14087 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14088 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14089 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14090 tp->bufmgr_config.mbuf_high_water_jumbo =
14091 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14092 } else {
14093 tp->bufmgr_config.mbuf_read_dma_low_water =
14094 DEFAULT_MB_RDMA_LOW_WATER;
14095 tp->bufmgr_config.mbuf_mac_rx_low_water =
14096 DEFAULT_MB_MACRX_LOW_WATER;
14097 tp->bufmgr_config.mbuf_high_water =
14098 DEFAULT_MB_HIGH_WATER;
14099
14100 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14101 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14102 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14103 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14104 tp->bufmgr_config.mbuf_high_water_jumbo =
14105 DEFAULT_MB_HIGH_WATER_JUMBO;
14106 }
1da177e4
LT		 14107
14108 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14109 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14110}
14111
14112static char * __devinit tg3_phy_string(struct tg3 *tp)
14113{
79eb6904
MC		 14114 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14115 case TG3_PHY_ID_BCM5400: return "5400";
14116 case TG3_PHY_ID_BCM5401: return "5401";
14117 case TG3_PHY_ID_BCM5411: return "5411";
14118 case TG3_PHY_ID_BCM5701: return "5701";
14119 case TG3_PHY_ID_BCM5703: return "5703";
14120 case TG3_PHY_ID_BCM5704: return "5704";
14121 case TG3_PHY_ID_BCM5705: return "5705";
14122 case TG3_PHY_ID_BCM5750: return "5750";
14123 case TG3_PHY_ID_BCM5752: return "5752";
14124 case TG3_PHY_ID_BCM5714: return "5714";
14125 case TG3_PHY_ID_BCM5780: return "5780";
14126 case TG3_PHY_ID_BCM5755: return "5755";
14127 case TG3_PHY_ID_BCM5787: return "5787";
14128 case TG3_PHY_ID_BCM5784: return "5784";
14129 case TG3_PHY_ID_BCM5756: return "5722/5756";
14130 case TG3_PHY_ID_BCM5906: return "5906";
14131 case TG3_PHY_ID_BCM5761: return "5761";
14132 case TG3_PHY_ID_BCM5718C: return "5718C";
14133 case TG3_PHY_ID_BCM5718S: return "5718S";
14134 case TG3_PHY_ID_BCM57765: return "57765";
14135 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 14136 case 0: return "serdes";
14137 default: return "unknown";
855e1111 14138 }
1da177e4
LT		 14139}
14140
f9804ddb
MC		 14141static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14142{
14143 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14144 strcpy(str, "PCI Express");
14145 return str;
14146 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14147 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14148
14149 strcpy(str, "PCIX:");
14150
14151 if ((clock_ctrl == 7) ||
14152 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14153 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14154 strcat(str, "133MHz");
14155 else if (clock_ctrl == 0)
14156 strcat(str, "33MHz");
14157 else if (clock_ctrl == 2)
14158 strcat(str, "50MHz");
14159 else if (clock_ctrl == 4)
14160 strcat(str, "66MHz");
14161 else if (clock_ctrl == 6)
14162 strcat(str, "100MHz");
f9804ddb
MC		 14163 } else {
14164 strcpy(str, "PCI:");
14165 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14166 strcat(str, "66MHz");
14167 else
14168 strcat(str, "33MHz");
14169 }
14170 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14171 strcat(str, ":32-bit");
14172 else
14173 strcat(str, ":64-bit");
14174 return str;
14175}
14176
8c2dc7e1 14177static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14178{
14179 struct pci_dev *peer;
14180 unsigned int func, devnr = tp->pdev->devfn & ~7;
14181
14182 for (func = 0; func < 8; func++) {
14183 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14184 if (peer && peer != tp->pdev)
14185 break;
14186 pci_dev_put(peer);
14187 }
16fe9d74
MC		 14188 /* 5704 can be configured in single-port mode, set peer to
14189 * tp->pdev in that case.
14190 */
14191 if (!peer) {
14192 peer = tp->pdev;
14193 return peer;
14194 }
1da177e4
LT		 14195
14196 /*
14197 * We don't need to keep the refcount elevated; there's no way
14198 * to remove one half of this device without removing the other
14199 */
14200 pci_dev_put(peer);
14201
14202 return peer;
14203}
14204
15f9850d
DM		 14205static void __devinit tg3_init_coal(struct tg3 *tp)
14206{
14207 struct ethtool_coalesce *ec = &tp->coal;
14208
14209 memset(ec, 0, sizeof(*ec));
14210 ec->cmd = ETHTOOL_GCOALESCE;
14211 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14212 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14213 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14214 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14215 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14216 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14217 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14218 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14219 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14220
14221 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14222 HOSTCC_MODE_CLRTICK_TXBD)) {
14223 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14224 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14225 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14226 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14227 }
d244c892
MC		 14228
14229 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14230 ec->rx_coalesce_usecs_irq = 0;
14231 ec->tx_coalesce_usecs_irq = 0;
14232 ec->stats_block_coalesce_usecs = 0;
14233 }
15f9850d
DM		 14234}
14235
7c7d64b8
SH		 14236static const struct net_device_ops tg3_netdev_ops = {
14237 .ndo_open = tg3_open,
14238 .ndo_stop = tg3_close,
00829823
SH		 14239 .ndo_start_xmit = tg3_start_xmit,
14240 .ndo_get_stats = tg3_get_stats,
14241 .ndo_validate_addr = eth_validate_addr,
14242 .ndo_set_multicast_list = tg3_set_rx_mode,
14243 .ndo_set_mac_address = tg3_set_mac_addr,
14244 .ndo_do_ioctl = tg3_ioctl,
14245 .ndo_tx_timeout = tg3_tx_timeout,
14246 .ndo_change_mtu = tg3_change_mtu,
14247#if TG3_VLAN_TAG_USED
14248 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14249#endif
14250#ifdef CONFIG_NET_POLL_CONTROLLER
14251 .ndo_poll_controller = tg3_poll_controller,
14252#endif
14253};
14254
14255static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14256 .ndo_open = tg3_open,
14257 .ndo_stop = tg3_close,
14258 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14259 .ndo_get_stats = tg3_get_stats,
14260 .ndo_validate_addr = eth_validate_addr,
14261 .ndo_set_multicast_list = tg3_set_rx_mode,
14262 .ndo_set_mac_address = tg3_set_mac_addr,
14263 .ndo_do_ioctl = tg3_ioctl,
14264 .ndo_tx_timeout = tg3_tx_timeout,
14265 .ndo_change_mtu = tg3_change_mtu,
14266#if TG3_VLAN_TAG_USED
14267 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14268#endif
14269#ifdef CONFIG_NET_POLL_CONTROLLER
14270 .ndo_poll_controller = tg3_poll_controller,
14271#endif
14272};
14273
1da177e4
LT		 14274static int __devinit tg3_init_one(struct pci_dev *pdev,
14275 const struct pci_device_id *ent)
14276{
1da177e4
LT		 14277 struct net_device *dev;
14278 struct tg3 *tp;
646c9edd
MC		 14279 int i, err, pm_cap;
14280 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14281 char str[40];
72f2afb8 14282 u64 dma_mask, persist_dma_mask;
1da177e4 14283
05dbe005 14284 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 14285
14286 err = pci_enable_device(pdev);
14287 if (err) {
2445e461 14288 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 14289 return err;
14290 }
14291
1da177e4
LT		 14292 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14293 if (err) {
2445e461 14294 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 14295 goto err_out_disable_pdev;
14296 }
14297
14298 pci_set_master(pdev);
14299
14300 /* Find power-management capability. */
14301 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14302 if (pm_cap == 0) {
2445e461
MC		 14303 dev_err(&pdev->dev,
14304 "Cannot find Power Management capability, aborting\n");
1da177e4
LT		 14305 err = -EIO;
14306 goto err_out_free_res;
14307 }
14308
fe5f5787 14309 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 14310 if (!dev) {
2445e461 14311 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4
LT		 14312 err = -ENOMEM;
14313 goto err_out_free_res;
14314 }
14315
1da177e4
LT		 14316 SET_NETDEV_DEV(dev, &pdev->dev);
14317
1da177e4
LT		 14318#if TG3_VLAN_TAG_USED
14319 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14320#endif
14321
14322 tp = netdev_priv(dev);
14323 tp->pdev = pdev;
14324 tp->dev = dev;
14325 tp->pm_cap = pm_cap;
1da177e4
LT		 14326 tp->rx_mode = TG3_DEF_RX_MODE;
14327 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14328
1da177e4
LT		 14329 if (tg3_debug > 0)
14330 tp->msg_enable = tg3_debug;
14331 else
14332 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14333
14334 /* The word/byte swap controls here control register access byte
14335 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14336 * setting below.
14337 */
14338 tp->misc_host_ctrl =
14339 MISC_HOST_CTRL_MASK_PCI_INT |
14340 MISC_HOST_CTRL_WORD_SWAP |
14341 MISC_HOST_CTRL_INDIR_ACCESS |
14342 MISC_HOST_CTRL_PCISTATE_RW;
14343
14344 /* The NONFRM (non-frame) byte/word swap controls take effect
14345 * on descriptor entries, anything which isn't packet data.
14346 *
14347 * The StrongARM chips on the board (one for tx, one for rx)
14348 * are running in big-endian mode.
14349 */
14350 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14351 GRC_MODE_WSWAP_NONFRM_DATA);
14352#ifdef __BIG_ENDIAN
14353 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14354#endif
14355 spin_lock_init(&tp->lock);
1da177e4 14356 spin_lock_init(&tp->indirect_lock);
c4028958 14357 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14358
d5fe488a 14359 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14360 if (!tp->regs) {
ab96b241 14361 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 14362 err = -ENOMEM;
14363 goto err_out_free_dev;
14364 }
14365
14366 tg3_init_link_config(tp);
14367
1da177e4
LT		 14368 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14369 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14370
1da177e4 14371 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14372 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14373 dev->irq = pdev->irq;
1da177e4
LT		 14374
14375 err = tg3_get_invariants(tp);
14376 if (err) {
ab96b241
MC		 14377 dev_err(&pdev->dev,
14378 "Problem fetching invariants of chip, aborting\n");
1da177e4
LT		 14379 goto err_out_iounmap;
14380 }
14381
615774fe
MC		 14382 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14383 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14384 dev->netdev_ops = &tg3_netdev_ops;
14385 else
14386 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14387
14388
4a29cc2e
MC		 14389 /* The EPB bridge inside 5714, 5715, and 5780 and any
14390 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14391 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14392 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14393 * do DMA address check in tg3_start_xmit().
14394 */
4a29cc2e 14395 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14396 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14397 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14398 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14399#ifdef CONFIG_HIGHMEM
6a35528a 14400 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14401#endif
4a29cc2e 14402 } else
6a35528a 14403 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14404
14405 /* Configure DMA attributes. */
284901a9 14406 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14407 err = pci_set_dma_mask(pdev, dma_mask);
14408 if (!err) {
14409 dev->features |= NETIF_F_HIGHDMA;
14410 err = pci_set_consistent_dma_mask(pdev,
14411 persist_dma_mask);
14412 if (err < 0) {
ab96b241
MC		 14413 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14414 "DMA for consistent allocations\n");
72f2afb8
MC		 14415 goto err_out_iounmap;
14416 }
14417 }
14418 }
284901a9
YH		 14419 if (err || dma_mask == DMA_BIT_MASK(32)) {
14420 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 14421 if (err) {
ab96b241
MC		 14422 dev_err(&pdev->dev,
14423 "No usable DMA configuration, aborting\n");
72f2afb8
MC		 14424 goto err_out_iounmap;
14425 }
14426 }
14427
fdfec172 14428 tg3_init_bufmgr_config(tp);
1da177e4 14429
507399f1
MC		 14430 /* Selectively allow TSO based on operating conditions */
14431 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14432 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14433 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14434 else {
14435 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14436 tp->fw_needed = NULL;
1da177e4 14437 }
507399f1
MC		 14438
14439 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14440 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14441
4e3a7aaa
MC		 14442 /* TSO is on by default on chips that support hardware TSO.
14443 * Firmware TSO on older chips gives lower performance, so it
14444 * is off by default, but can be enabled using ethtool.
14445 */
e849cdc3
MC		 14446 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14447 (dev->features & NETIF_F_IP_CSUM))
14448 dev->features |= NETIF_F_TSO;
14449
14450 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14451 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14452 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14453 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14454 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14456 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14457 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14458 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14459 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14460 dev->features |= NETIF_F_TSO_ECN;
b0026624 14461 }
1da177e4 14462
1da177e4
LT		 14463 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14464 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14465 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14466 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14467 tp->rx_pending = 63;
14468 }
14469
1da177e4
LT		 14470 err = tg3_get_device_address(tp);
14471 if (err) {
ab96b241
MC		 14472 dev_err(&pdev->dev,
14473 "Could not obtain valid ethernet address, aborting\n");
026a6c21 14474 goto err_out_iounmap;
1da177e4
LT		 14475 }
14476
c88864df 14477 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14478 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14479 if (!tp->aperegs) {
ab96b241
MC		 14480 dev_err(&pdev->dev,
14481 "Cannot map APE registers, aborting\n");
c88864df 14482 err = -ENOMEM;
026a6c21 14483 goto err_out_iounmap;
c88864df
MC		 14484 }
14485
14486 tg3_ape_lock_init(tp);
7fd76445
MC		 14487
14488 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14489 tg3_read_dash_ver(tp);
c88864df
MC		 14490 }
14491
1da177e4
LT		 14492 /*
14493 * Reset chip in case UNDI or EFI driver did not shutdown
14494 * DMA self test will enable WDMAC and we'll see (spurious)
14495 * pending DMA on the PCI bus at that point.
14496 */
14497 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14498 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14499 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14500 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14501 }
14502
14503 err = tg3_test_dma(tp);
14504 if (err) {
ab96b241 14505 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 14506 goto err_out_apeunmap;
1da177e4
LT		 14507 }
14508
1da177e4
LT		 14509 /* flow control autonegotiation is default behavior */
14510 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14511 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14512
78f90dcf
MC		 14513 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14514 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14515 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14516 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14517 struct tg3_napi *tnapi = &tp->napi[i];
14518
14519 tnapi->tp = tp;
14520 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14521
14522 tnapi->int_mbox = intmbx;
14523 if (i < 4)
14524 intmbx += 0x8;
14525 else
14526 intmbx += 0x4;
14527
14528 tnapi->consmbox = rcvmbx;
14529 tnapi->prodmbox = sndmbx;
14530
14531 if (i) {
14532 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14533 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14534 } else {
14535 tnapi->coal_now = HOSTCC_MODE_NOW;
14536 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14537 }
14538
14539 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14540 break;
14541
14542 /*
14543 * If we support MSIX, we'll be using RSS. If we're using
14544 * RSS, the first vector only handles link interrupts and the
14545 * remaining vectors handle rx and tx interrupts. Reuse the
14546 * mailbox values for the next iteration. The values we setup
14547 * above are still useful for the single vectored mode.
14548 */
14549 if (!i)
14550 continue;
14551
14552 rcvmbx += 0x8;
14553
14554 if (sndmbx & 0x4)
14555 sndmbx -= 0x4;
14556 else
14557 sndmbx += 0xc;
14558 }
14559
15f9850d
DM		 14560 tg3_init_coal(tp);
14561
c49a1561
MC		 14562 pci_set_drvdata(pdev, dev);
14563
1da177e4
LT		 14564 err = register_netdev(dev);
14565 if (err) {
ab96b241 14566 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 14567 goto err_out_apeunmap;
1da177e4
LT		 14568 }
14569
05dbe005
JP		 14570 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14571 tp->board_part_number,
14572 tp->pci_chip_rev_id,
14573 tg3_bus_string(tp, str),
14574 dev->dev_addr);
1da177e4 14575
3f0e3ad7
MC		 14576 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14577 struct phy_device *phydev;
14578 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 14579 netdev_info(dev,
14580 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 14581 phydev->drv->name, dev_name(&phydev->dev));
3f0e3ad7 14582 } else
5129c3a3
MC		 14583 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14584 "(WireSpeed[%d])\n", tg3_phy_string(tp),
05dbe005
JP		 14585 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14586 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14587 "10/100/1000Base-T")),
14588 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14589
14590 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14591 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14592 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14593 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14594 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14595 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14596 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14597 tp->dma_rwctrl,
14598 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14599 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4
LT		 14600
14601 return 0;
14602
0d3031d9
MC		 14603err_out_apeunmap:
14604 if (tp->aperegs) {
14605 iounmap(tp->aperegs);
14606 tp->aperegs = NULL;
14607 }
14608
1da177e4 14609err_out_iounmap:
6892914f
MC		 14610 if (tp->regs) {
14611 iounmap(tp->regs);
22abe310 14612 tp->regs = NULL;
6892914f 14613 }
1da177e4
LT		 14614
14615err_out_free_dev:
14616 free_netdev(dev);
14617
14618err_out_free_res:
14619 pci_release_regions(pdev);
14620
14621err_out_disable_pdev:
14622 pci_disable_device(pdev);
14623 pci_set_drvdata(pdev, NULL);
14624 return err;
14625}
14626
14627static void __devexit tg3_remove_one(struct pci_dev *pdev)
14628{
14629 struct net_device *dev = pci_get_drvdata(pdev);
14630
14631 if (dev) {
14632 struct tg3 *tp = netdev_priv(dev);
14633
077f849d
JSR		 14634 if (tp->fw)
14635 release_firmware(tp->fw);
14636
7faa006f 14637 flush_scheduled_work();
158d7abd 14638
b02fd9e3
MC		 14639 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14640 tg3_phy_fini(tp);
158d7abd 14641 tg3_mdio_fini(tp);
b02fd9e3 14642 }
158d7abd 14643
1da177e4 14644 unregister_netdev(dev);
0d3031d9
MC		 14645 if (tp->aperegs) {
14646 iounmap(tp->aperegs);
14647 tp->aperegs = NULL;
14648 }
6892914f
MC		 14649 if (tp->regs) {
14650 iounmap(tp->regs);
22abe310 14651 tp->regs = NULL;
6892914f 14652 }
1da177e4
LT		 14653 free_netdev(dev);
14654 pci_release_regions(pdev);
14655 pci_disable_device(pdev);
14656 pci_set_drvdata(pdev, NULL);
14657 }
14658}
14659
14660static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14661{
14662 struct net_device *dev = pci_get_drvdata(pdev);
14663 struct tg3 *tp = netdev_priv(dev);
12dac075 14664 pci_power_t target_state;
1da177e4
LT		 14665 int err;
14666
3e0c95fd
MC		 14667 /* PCI register 4 needs to be saved whether netif_running() or not.
14668 * MSI address and data need to be saved if using MSI and
14669 * netif_running().
14670 */
14671 pci_save_state(pdev);
14672
1da177e4
LT		 14673 if (!netif_running(dev))
14674 return 0;
14675
7faa006f 14676 flush_scheduled_work();
b02fd9e3 14677 tg3_phy_stop(tp);
1da177e4
LT		 14678 tg3_netif_stop(tp);
14679
14680 del_timer_sync(&tp->timer);
14681
f47c11ee 14682 tg3_full_lock(tp, 1);
1da177e4 14683 tg3_disable_ints(tp);
f47c11ee 14684 tg3_full_unlock(tp);
1da177e4
LT		 14685
14686 netif_device_detach(dev);
14687
f47c11ee 14688 tg3_full_lock(tp, 0);
944d980e 14689 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14690 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14691 tg3_full_unlock(tp);
1da177e4 14692
12dac075
RW		 14693 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14694
14695 err = tg3_set_power_state(tp, target_state);
1da177e4 14696 if (err) {
b02fd9e3
MC		 14697 int err2;
14698
f47c11ee 14699 tg3_full_lock(tp, 0);
1da177e4 14700
6a9eba15 14701 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14702 err2 = tg3_restart_hw(tp, 1);
14703 if (err2)
b9ec6c1b 14704 goto out;
1da177e4
LT		 14705
14706 tp->timer.expires = jiffies + tp->timer_offset;
14707 add_timer(&tp->timer);
14708
14709 netif_device_attach(dev);
14710 tg3_netif_start(tp);
14711
b9ec6c1b 14712out:
f47c11ee 14713 tg3_full_unlock(tp);
b02fd9e3
MC		 14714
14715 if (!err2)
14716 tg3_phy_start(tp);
1da177e4
LT		 14717 }
14718
14719 return err;
14720}
14721
14722static int tg3_resume(struct pci_dev *pdev)
14723{
14724 struct net_device *dev = pci_get_drvdata(pdev);
14725 struct tg3 *tp = netdev_priv(dev);
14726 int err;
14727
3e0c95fd
MC		 14728 pci_restore_state(tp->pdev);
14729
1da177e4
LT		 14730 if (!netif_running(dev))
14731 return 0;
14732
bc1c7567 14733 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14734 if (err)
14735 return err;
14736
14737 netif_device_attach(dev);
14738
f47c11ee 14739 tg3_full_lock(tp, 0);
1da177e4 14740
6a9eba15 14741 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14742 err = tg3_restart_hw(tp, 1);
14743 if (err)
14744 goto out;
1da177e4
LT		 14745
14746 tp->timer.expires = jiffies + tp->timer_offset;
14747 add_timer(&tp->timer);
14748
1da177e4
LT		 14749 tg3_netif_start(tp);
14750
b9ec6c1b 14751out:
f47c11ee 14752 tg3_full_unlock(tp);
1da177e4 14753
b02fd9e3
MC		 14754 if (!err)
14755 tg3_phy_start(tp);
14756
b9ec6c1b 14757 return err;
1da177e4
LT		 14758}
14759
14760static struct pci_driver tg3_driver = {
14761 .name = DRV_MODULE_NAME,
14762 .id_table = tg3_pci_tbl,
14763 .probe = tg3_init_one,
14764 .remove = __devexit_p(tg3_remove_one),
14765 .suspend = tg3_suspend,
14766 .resume = tg3_resume
14767};
14768
14769static int __init tg3_init(void)
14770{
29917620 14771 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14772}
14773
14774static void __exit tg3_cleanup(void)
14775{
14776 pci_unregister_driver(&tg3_driver);
14777}
14778
14779module_init(tg3_init);
14780module_exit(tg3_cleanup);
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