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tg3: Fix 5906 transmit hangs
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
daf09de8
MC		 71#define DRV_MODULE_VERSION "3.102"
72#define DRV_MODULE_RELDATE "September 1, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
fcb389df
MC		 940 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
943 val = MAC_PHYCFG2_50610_LED_MODES;
944 break;
945 case TG3_PHY_ID_BCMAC131:
946 val = MAC_PHYCFG2_AC131_LED_MODES;
947 break;
948 case TG3_PHY_ID_RTL8211C:
949 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
950 break;
951 case TG3_PHY_ID_RTL8201E:
952 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
953 break;
954 default:
a9daf367 955 return;
fcb389df
MC		 956 }
957
958 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
959 tw32(MAC_PHYCFG2, val);
960
961 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 962 val &= ~(MAC_PHYCFG1_RGMII_INT |
963 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
964 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 965 tw32(MAC_PHYCFG1, val);
966
967 return;
968 }
969
970 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
971 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
972 MAC_PHYCFG2_FMODE_MASK_MASK |
973 MAC_PHYCFG2_GMODE_MASK_MASK |
974 MAC_PHYCFG2_ACT_MASK_MASK |
975 MAC_PHYCFG2_QUAL_MASK_MASK |
976 MAC_PHYCFG2_INBAND_ENABLE;
977
978 tw32(MAC_PHYCFG2, val);
a9daf367 979
bb85fbb6
MC		 980 val = tr32(MAC_PHYCFG1);
981 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
982 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
983 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 984 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
985 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
986 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
987 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
988 }
bb85fbb6
MC		 989 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
990 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
991 tw32(MAC_PHYCFG1, val);
a9daf367 992
a9daf367
MC		 993 val = tr32(MAC_EXT_RGMII_MODE);
994 val &= ~(MAC_RGMII_MODE_RX_INT_B |
995 MAC_RGMII_MODE_RX_QUALITY |
996 MAC_RGMII_MODE_RX_ACTIVITY |
997 MAC_RGMII_MODE_RX_ENG_DET |
998 MAC_RGMII_MODE_TX_ENABLE |
999 MAC_RGMII_MODE_TX_LOWPWR |
1000 MAC_RGMII_MODE_TX_RESET);
fcb389df 1001 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1003 val |= MAC_RGMII_MODE_RX_INT_B |
1004 MAC_RGMII_MODE_RX_QUALITY |
1005 MAC_RGMII_MODE_RX_ACTIVITY |
1006 MAC_RGMII_MODE_RX_ENG_DET;
1007 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008 val |= MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET;
1011 }
1012 tw32(MAC_EXT_RGMII_MODE, val);
1013}
1014
158d7abd
MC		 1015static void tg3_mdio_start(struct tg3 *tp)
1016{
158d7abd
MC		 1017 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018 tw32_f(MAC_MI_MODE, tp->mi_mode);
1019 udelay(80);
a9daf367 1020
882e9793
MC		 1021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1022 u32 funcnum, is_serdes;
1023
1024 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1025 if (funcnum)
1026 tp->phy_addr = 2;
1027 else
1028 tp->phy_addr = 1;
1029
1030 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1031 if (is_serdes)
1032 tp->phy_addr += 7;
1033 } else
1034 tp->phy_addr = PHY_ADDR;
1035
9c61d6bc
MC		 1036 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038 tg3_mdio_config_5785(tp);
158d7abd
MC		 1039}
1040
158d7abd
MC		 1041static int tg3_mdio_init(struct tg3 *tp)
1042{
1043 int i;
1044 u32 reg;
a9daf367 1045 struct phy_device *phydev;
158d7abd
MC		 1046
1047 tg3_mdio_start(tp);
1048
1049 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1050 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1051 return 0;
1052
298cf9be
LB		 1053 tp->mdio_bus = mdiobus_alloc();
1054 if (tp->mdio_bus == NULL)
1055 return -ENOMEM;
158d7abd 1056
298cf9be
LB		 1057 tp->mdio_bus->name = "tg3 mdio bus";
1058 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1059 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1060 tp->mdio_bus->priv = tp;
1061 tp->mdio_bus->parent = &tp->pdev->dev;
1062 tp->mdio_bus->read = &tg3_mdio_read;
1063 tp->mdio_bus->write = &tg3_mdio_write;
1064 tp->mdio_bus->reset = &tg3_mdio_reset;
1065 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1066 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1067
1068 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1069 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1070
1071 /* The bus registration will look for all the PHYs on the mdio bus.
1072 * Unfortunately, it does not ensure the PHY is powered up before
1073 * accessing the PHY ID registers. A chip reset is the
1074 * quickest way to bring the device back to an operational state..
1075 */
1076 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1077 tg3_bmcr_reset(tp);
1078
298cf9be 1079 i = mdiobus_register(tp->mdio_bus);
a9daf367 1080 if (i) {
158d7abd
MC		 1081 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1082 tp->dev->name, i);
9c61d6bc 1083 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1084 return i;
1085 }
158d7abd 1086
298cf9be 1087 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1088
9c61d6bc
MC		 1089 if (!phydev || !phydev->drv) {
1090 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1091 mdiobus_unregister(tp->mdio_bus);
1092 mdiobus_free(tp->mdio_bus);
1093 return -ENODEV;
1094 }
1095
1096 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1097 case TG3_PHY_ID_BCM57780:
1098 phydev->interface = PHY_INTERFACE_MODE_GMII;
1099 break;
a9daf367 1100 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1101 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1102 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1103 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1104 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1105 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1106 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1107 /* fallthru */
1108 case TG3_PHY_ID_RTL8211C:
1109 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1110 break;
fcb389df 1111 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1112 case TG3_PHY_ID_BCMAC131:
1113 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1114 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1115 break;
1116 }
1117
9c61d6bc
MC		 1118 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1119
1120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1121 tg3_mdio_config_5785(tp);
a9daf367
MC		 1122
1123 return 0;
158d7abd
MC		 1124}
1125
1126static void tg3_mdio_fini(struct tg3 *tp)
1127{
1128 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1129 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1130 mdiobus_unregister(tp->mdio_bus);
1131 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1132 }
1133}
1134
4ba526ce
MC		 1135/* tp->lock is held. */
1136static inline void tg3_generate_fw_event(struct tg3 *tp)
1137{
1138 u32 val;
1139
1140 val = tr32(GRC_RX_CPU_EVENT);
1141 val |= GRC_RX_CPU_DRIVER_EVENT;
1142 tw32_f(GRC_RX_CPU_EVENT, val);
1143
1144 tp->last_event_jiffies = jiffies;
1145}
1146
1147#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1148
95e2869a
MC		 1149/* tp->lock is held. */
1150static void tg3_wait_for_event_ack(struct tg3 *tp)
1151{
1152 int i;
4ba526ce
MC		 1153 unsigned int delay_cnt;
1154 long time_remain;
1155
1156 /* If enough time has passed, no wait is necessary. */
1157 time_remain = (long)(tp->last_event_jiffies + 1 +
1158 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1159 (long)jiffies;
1160 if (time_remain < 0)
1161 return;
1162
1163 /* Check if we can shorten the wait time. */
1164 delay_cnt = jiffies_to_usecs(time_remain);
1165 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1166 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1167 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1168
4ba526ce 1169 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1170 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1171 break;
4ba526ce 1172 udelay(8);
95e2869a
MC		 1173 }
1174}
1175
1176/* tp->lock is held. */
1177static void tg3_ump_link_report(struct tg3 *tp)
1178{
1179 u32 reg;
1180 u32 val;
1181
1182 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1183 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1184 return;
1185
1186 tg3_wait_for_event_ack(tp);
1187
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1189
1190 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1191
1192 val = 0;
1193 if (!tg3_readphy(tp, MII_BMCR, &reg))
1194 val = reg << 16;
1195 if (!tg3_readphy(tp, MII_BMSR, &reg))
1196 val |= (reg & 0xffff);
1197 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1198
1199 val = 0;
1200 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1201 val = reg << 16;
1202 if (!tg3_readphy(tp, MII_LPA, &reg))
1203 val |= (reg & 0xffff);
1204 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1205
1206 val = 0;
1207 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1208 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1211 val |= (reg & 0xffff);
1212 }
1213 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1214
1215 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1216 val = reg << 16;
1217 else
1218 val = 0;
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1220
4ba526ce 1221 tg3_generate_fw_event(tp);
95e2869a
MC		 1222}
1223
1224static void tg3_link_report(struct tg3 *tp)
1225{
1226 if (!netif_carrier_ok(tp->dev)) {
1227 if (netif_msg_link(tp))
1228 printk(KERN_INFO PFX "%s: Link is down.\n",
1229 tp->dev->name);
1230 tg3_ump_link_report(tp);
1231 } else if (netif_msg_link(tp)) {
1232 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1233 tp->dev->name,
1234 (tp->link_config.active_speed == SPEED_1000 ?
1235 1000 :
1236 (tp->link_config.active_speed == SPEED_100 ?
1237 100 : 10)),
1238 (tp->link_config.active_duplex == DUPLEX_FULL ?
1239 "full" : "half"));
1240
1241 printk(KERN_INFO PFX
1242 "%s: Flow control is %s for TX and %s for RX.\n",
1243 tp->dev->name,
e18ce346 1244 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1245 "on" : "off",
e18ce346 1246 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1247 "on" : "off");
1248 tg3_ump_link_report(tp);
1249 }
1250}
1251
1252static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1253{
1254 u16 miireg;
1255
e18ce346 1256 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1257 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1258 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1259 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1260 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1261 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1262 else
1263 miireg = 0;
1264
1265 return miireg;
1266}
1267
1268static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1269{
1270 u16 miireg;
1271
e18ce346 1272 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1273 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1274 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1275 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1276 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1277 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1278 else
1279 miireg = 0;
1280
1281 return miireg;
1282}
1283
95e2869a
MC		 1284static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1285{
1286 u8 cap = 0;
1287
1288 if (lcladv & ADVERTISE_1000XPAUSE) {
1289 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1290 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1291 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1292 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1293 cap = FLOW_CTRL_RX;
95e2869a
MC		 1294 } else {
1295 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1296 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1297 }
1298 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1299 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1300 cap = FLOW_CTRL_TX;
95e2869a
MC		 1301 }
1302
1303 return cap;
1304}
1305
f51f3562 1306static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1307{
b02fd9e3 1308 u8 autoneg;
f51f3562 1309 u8 flowctrl = 0;
95e2869a
MC		 1310 u32 old_rx_mode = tp->rx_mode;
1311 u32 old_tx_mode = tp->tx_mode;
1312
b02fd9e3 1313 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1314 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1315 else
1316 autoneg = tp->link_config.autoneg;
1317
1318 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1319 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1320 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1321 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1322 else
bc02ff95 1323 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1324 } else
1325 flowctrl = tp->link_config.flowctrl;
95e2869a 1326
f51f3562 1327 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1328
e18ce346 1329 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1330 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1331 else
1332 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1333
f51f3562 1334 if (old_rx_mode != tp->rx_mode)
95e2869a 1335 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1336
e18ce346 1337 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1338 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1341
f51f3562 1342 if (old_tx_mode != tp->tx_mode)
95e2869a 1343 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1344}
1345
b02fd9e3
MC		 1346static void tg3_adjust_link(struct net_device *dev)
1347{
1348 u8 oldflowctrl, linkmesg = 0;
1349 u32 mac_mode, lcl_adv, rmt_adv;
1350 struct tg3 *tp = netdev_priv(dev);
298cf9be 1351 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3 1352
24bb4fb6 1353 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1354
1355 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1356 MAC_MODE_HALF_DUPLEX);
1357
1358 oldflowctrl = tp->link_config.active_flowctrl;
1359
1360 if (phydev->link) {
1361 lcl_adv = 0;
1362 rmt_adv = 0;
1363
1364 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1365 mac_mode |= MAC_MODE_PORT_MODE_MII;
1366 else
1367 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1368
1369 if (phydev->duplex == DUPLEX_HALF)
1370 mac_mode |= MAC_MODE_HALF_DUPLEX;
1371 else {
1372 lcl_adv = tg3_advert_flowctrl_1000T(
1373 tp->link_config.flowctrl);
1374
1375 if (phydev->pause)
1376 rmt_adv = LPA_PAUSE_CAP;
1377 if (phydev->asym_pause)
1378 rmt_adv |= LPA_PAUSE_ASYM;
1379 }
1380
1381 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1382 } else
1383 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1384
1385 if (mac_mode != tp->mac_mode) {
1386 tp->mac_mode = mac_mode;
1387 tw32_f(MAC_MODE, tp->mac_mode);
1388 udelay(40);
1389 }
1390
fcb389df
MC		 1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1392 if (phydev->speed == SPEED_10)
1393 tw32(MAC_MI_STAT,
1394 MAC_MI_STAT_10MBPS_MODE |
1395 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1396 else
1397 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1398 }
1399
b02fd9e3
MC		 1400 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1401 tw32(MAC_TX_LENGTHS,
1402 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403 (6 << TX_LENGTHS_IPG_SHIFT) |
1404 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405 else
1406 tw32(MAC_TX_LENGTHS,
1407 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1408 (6 << TX_LENGTHS_IPG_SHIFT) |
1409 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1410
1411 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1412 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1413 phydev->speed != tp->link_config.active_speed ||
1414 phydev->duplex != tp->link_config.active_duplex ||
1415 oldflowctrl != tp->link_config.active_flowctrl)
1416 linkmesg = 1;
1417
1418 tp->link_config.active_speed = phydev->speed;
1419 tp->link_config.active_duplex = phydev->duplex;
1420
24bb4fb6 1421 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1422
1423 if (linkmesg)
1424 tg3_link_report(tp);
1425}
1426
1427static int tg3_phy_init(struct tg3 *tp)
1428{
1429 struct phy_device *phydev;
1430
1431 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1432 return 0;
1433
1434 /* Bring the PHY back to a known state. */
1435 tg3_bmcr_reset(tp);
1436
298cf9be 1437 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1438
1439 /* Attach the MAC to the PHY. */
fb28ad35 1440 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1441 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1442 if (IS_ERR(phydev)) {
1443 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1444 return PTR_ERR(phydev);
1445 }
1446
b02fd9e3 1447 /* Mask with MAC supported features. */
9c61d6bc
MC		 1448 switch (phydev->interface) {
1449 case PHY_INTERFACE_MODE_GMII:
1450 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1451 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1452 phydev->supported &= (PHY_GBIT_FEATURES |
1453 SUPPORTED_Pause |
1454 SUPPORTED_Asym_Pause);
1455 break;
1456 }
1457 /* fallthru */
9c61d6bc
MC		 1458 case PHY_INTERFACE_MODE_MII:
1459 phydev->supported &= (PHY_BASIC_FEATURES |
1460 SUPPORTED_Pause |
1461 SUPPORTED_Asym_Pause);
1462 break;
1463 default:
1464 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1465 return -EINVAL;
1466 }
1467
1468 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1469
1470 phydev->advertising = phydev->supported;
1471
b02fd9e3
MC		 1472 return 0;
1473}
1474
1475static void tg3_phy_start(struct tg3 *tp)
1476{
1477 struct phy_device *phydev;
1478
1479 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1480 return;
1481
298cf9be 1482 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1483
1484 if (tp->link_config.phy_is_low_power) {
1485 tp->link_config.phy_is_low_power = 0;
1486 phydev->speed = tp->link_config.orig_speed;
1487 phydev->duplex = tp->link_config.orig_duplex;
1488 phydev->autoneg = tp->link_config.orig_autoneg;
1489 phydev->advertising = tp->link_config.orig_advertising;
1490 }
1491
1492 phy_start(phydev);
1493
1494 phy_start_aneg(phydev);
1495}
1496
1497static void tg3_phy_stop(struct tg3 *tp)
1498{
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
298cf9be 1502 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1503}
1504
1505static void tg3_phy_fini(struct tg3 *tp)
1506{
1507 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1508 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1509 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1510 }
1511}
1512
b2a5c19c
MC		 1513static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1514{
1515 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1516 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1517}
1518
7f97a4bd
MC		 1519static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1520{
1521 u32 phytest;
1522
1523 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1524 u32 phy;
1525
1526 tg3_writephy(tp, MII_TG3_FET_TEST,
1527 phytest | MII_TG3_FET_SHADOW_EN);
1528 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1531 else
1532 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1533 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1534 }
1535 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1536 }
1537}
1538
6833c043
MC		 1539static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 reg;
1542
7f97a4bd 1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1544 return;
1545
7f97a4bd
MC		 1546 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1547 tg3_phy_fet_toggle_apd(tp, enable);
1548 return;
1549 }
1550
6833c043
MC		 1551 reg = MII_TG3_MISC_SHDW_WREN |
1552 MII_TG3_MISC_SHDW_SCR5_SEL |
1553 MII_TG3_MISC_SHDW_SCR5_LPED |
1554 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1555 MII_TG3_MISC_SHDW_SCR5_SDTL |
1556 MII_TG3_MISC_SHDW_SCR5_C125OE;
1557 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1558 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1559
1560 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1561
1562
1563 reg = MII_TG3_MISC_SHDW_WREN |
1564 MII_TG3_MISC_SHDW_APD_SEL |
1565 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1566 if (enable)
1567 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1568
1569 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1570}
1571
9ef8ca99
MC		 1572static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1573{
1574 u32 phy;
1575
1576 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1577 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1578 return;
1579
7f97a4bd 1580 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1581 u32 ephy;
1582
535ef6e1
MC		 1583 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1584 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1585
1586 tg3_writephy(tp, MII_TG3_FET_TEST,
1587 ephy | MII_TG3_FET_SHADOW_EN);
1588 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1589 if (enable)
535ef6e1 1590 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1591 else
535ef6e1
MC		 1592 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1593 tg3_writephy(tp, reg, phy);
9ef8ca99 1594 }
535ef6e1 1595 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1596 }
1597 } else {
1598 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1599 MII_TG3_AUXCTL_SHDWSEL_MISC;
1600 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1601 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1602 if (enable)
1603 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1604 else
1605 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1606 phy |= MII_TG3_AUXCTL_MISC_WREN;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608 }
1609 }
1610}
1611
1da177e4
LT		 1612static void tg3_phy_set_wirespeed(struct tg3 *tp)
1613{
1614 u32 val;
1615
1616 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1617 return;
1618
1619 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1620 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1621 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1622 (val | (1 << 15) | (1 << 4)));
1623}
1624
b2a5c19c
MC		 1625static void tg3_phy_apply_otp(struct tg3 *tp)
1626{
1627 u32 otp, phy;
1628
1629 if (!tp->phy_otp)
1630 return;
1631
1632 otp = tp->phy_otp;
1633
1634 /* Enable SM_DSP clock and tx 6dB coding. */
1635 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1636 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1637 MII_TG3_AUXCTL_ACTL_TX_6DB;
1638 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1639
1640 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1641 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1642 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1643
1644 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1645 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1646 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1647
1648 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1649 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1650 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1651
1652 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1653 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1654
1655 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1656 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1657
1658 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1659 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1660 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1661
1662 /* Turn off SM_DSP clock. */
1663 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1664 MII_TG3_AUXCTL_ACTL_TX_6DB;
1665 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1666}
1667
1da177e4
LT		 1668static int tg3_wait_macro_done(struct tg3 *tp)
1669{
1670 int limit = 100;
1671
1672 while (limit--) {
1673 u32 tmp32;
1674
1675 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1676 if ((tmp32 & 0x1000) == 0)
1677 break;
1678 }
1679 }
d4675b52 1680 if (limit < 0)
1da177e4
LT		 1681 return -EBUSY;
1682
1683 return 0;
1684}
1685
1686static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1687{
1688 static const u32 test_pat[4][6] = {
1689 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1690 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1691 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1692 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1693 };
1694 int chan;
1695
1696 for (chan = 0; chan < 4; chan++) {
1697 int i;
1698
1699 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1700 (chan * 0x2000) | 0x0200);
1701 tg3_writephy(tp, 0x16, 0x0002);
1702
1703 for (i = 0; i < 6; i++)
1704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1705 test_pat[chan][i]);
1706
1707 tg3_writephy(tp, 0x16, 0x0202);
1708 if (tg3_wait_macro_done(tp)) {
1709 *resetp = 1;
1710 return -EBUSY;
1711 }
1712
1713 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1714 (chan * 0x2000) | 0x0200);
1715 tg3_writephy(tp, 0x16, 0x0082);
1716 if (tg3_wait_macro_done(tp)) {
1717 *resetp = 1;
1718 return -EBUSY;
1719 }
1720
1721 tg3_writephy(tp, 0x16, 0x0802);
1722 if (tg3_wait_macro_done(tp)) {
1723 *resetp = 1;
1724 return -EBUSY;
1725 }
1726
1727 for (i = 0; i < 6; i += 2) {
1728 u32 low, high;
1729
1730 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1731 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1732 tg3_wait_macro_done(tp)) {
1733 *resetp = 1;
1734 return -EBUSY;
1735 }
1736 low &= 0x7fff;
1737 high &= 0x000f;
1738 if (low != test_pat[chan][i] ||
1739 high != test_pat[chan][i+1]) {
1740 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1741 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1743
1744 return -EBUSY;
1745 }
1746 }
1747 }
1748
1749 return 0;
1750}
1751
1752static int tg3_phy_reset_chanpat(struct tg3 *tp)
1753{
1754 int chan;
1755
1756 for (chan = 0; chan < 4; chan++) {
1757 int i;
1758
1759 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1760 (chan * 0x2000) | 0x0200);
1761 tg3_writephy(tp, 0x16, 0x0002);
1762 for (i = 0; i < 6; i++)
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1764 tg3_writephy(tp, 0x16, 0x0202);
1765 if (tg3_wait_macro_done(tp))
1766 return -EBUSY;
1767 }
1768
1769 return 0;
1770}
1771
1772static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1773{
1774 u32 reg32, phy9_orig;
1775 int retries, do_phy_reset, err;
1776
1777 retries = 10;
1778 do_phy_reset = 1;
1779 do {
1780 if (do_phy_reset) {
1781 err = tg3_bmcr_reset(tp);
1782 if (err)
1783 return err;
1784 do_phy_reset = 0;
1785 }
1786
1787 /* Disable transmitter and interrupt. */
1788 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1789 continue;
1790
1791 reg32 |= 0x3000;
1792 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1793
1794 /* Set full-duplex, 1000 mbps. */
1795 tg3_writephy(tp, MII_BMCR,
1796 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1797
1798 /* Set to master mode. */
1799 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1800 continue;
1801
1802 tg3_writephy(tp, MII_TG3_CTRL,
1803 (MII_TG3_CTRL_AS_MASTER |
1804 MII_TG3_CTRL_ENABLE_AS_MASTER));
1805
1806 /* Enable SM_DSP_CLOCK and 6dB. */
1807 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1808
1809 /* Block the PHY control access. */
1810 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1811 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1812
1813 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1814 if (!err)
1815 break;
1816 } while (--retries);
1817
1818 err = tg3_phy_reset_chanpat(tp);
1819 if (err)
1820 return err;
1821
1822 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1823 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1824
1825 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1826 tg3_writephy(tp, 0x16, 0x0000);
1827
1828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1830 /* Set Extended packet length bit for jumbo frames */
1831 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1832 }
1833 else {
1834 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1835 }
1836
1837 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1838
1839 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1840 reg32 &= ~0x3000;
1841 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1842 } else if (!err)
1843 err = -EBUSY;
1844
1845 return err;
1846}
1847
1848/* This will reset the tigon3 PHY if there is no valid
1849 * link unless the FORCE argument is non-zero.
1850 */
1851static int tg3_phy_reset(struct tg3 *tp)
1852{
b2a5c19c 1853 u32 cpmuctrl;
1da177e4
LT		 1854 u32 phy_status;
1855 int err;
1856
60189ddf
MC		 1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1858 u32 val;
1859
1860 val = tr32(GRC_MISC_CFG);
1861 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1862 udelay(40);
1863 }
1da177e4
LT		 1864 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1865 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1866 if (err != 0)
1867 return -EBUSY;
1868
c8e1e82b
MC		 1869 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1870 netif_carrier_off(tp->dev);
1871 tg3_link_report(tp);
1872 }
1873
1da177e4
LT		 1874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1877 err = tg3_phy_reset_5703_4_5(tp);
1878 if (err)
1879 return err;
1880 goto out;
1881 }
1882
b2a5c19c
MC		 1883 cpmuctrl = 0;
1884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1885 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1886 cpmuctrl = tr32(TG3_CPMU_CTRL);
1887 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1888 tw32(TG3_CPMU_CTRL,
1889 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1890 }
1891
1da177e4
LT		 1892 err = tg3_bmcr_reset(tp);
1893 if (err)
1894 return err;
1895
b2a5c19c
MC		 1896 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1897 u32 phy;
1898
1899 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1900 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1901
1902 tw32(TG3_CPMU_CTRL, cpmuctrl);
1903 }
1904
bcb37f6c
MC		 1905 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1906 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1907 u32 val;
1908
1909 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1910 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1911 CPMU_LSPD_1000MB_MACCLK_12_5) {
1912 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1913 udelay(40);
1914 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1915 }
1916 }
1917
b2a5c19c
MC		 1918 tg3_phy_apply_otp(tp);
1919
6833c043
MC		 1920 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1921 tg3_phy_toggle_apd(tp, true);
1922 else
1923 tg3_phy_toggle_apd(tp, false);
1924
1da177e4
LT		 1925out:
1926 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1927 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1929 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1930 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1931 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1933 }
1934 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1935 tg3_writephy(tp, 0x1c, 0x8d68);
1936 tg3_writephy(tp, 0x1c, 0x8d68);
1937 }
1938 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1940 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1941 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1942 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1943 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1944 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1945 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1946 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1947 }
c424cb24
MC		 1948 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1951 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1953 tg3_writephy(tp, MII_TG3_TEST1,
1954 MII_TG3_TEST1_TRIM_EN | 0x4);
1955 } else
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
1da177e4
LT		 1959 /* Set Extended packet length bit (bit 14) on all chips that */
1960 /* support jumbo frames */
1961 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1962 /* Cannot do read-modify-write on 5401 */
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1964 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1965 u32 phy_reg;
1966
1967 /* Set bit 14 with read-modify-write to preserve other bits */
1968 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1969 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1971 }
1972
1973 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1974 * jumbo frames transmission.
1975 */
8f666b07 1976 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1977 u32 phy_reg;
1978
1979 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1980 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1981 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1982 }
1983
715116a1 1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1985 /* adjust output voltage */
535ef6e1 1986 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1987 }
1988
9ef8ca99 1989 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1990 tg3_phy_set_wirespeed(tp);
1991 return 0;
1992}
1993
1994static void tg3_frob_aux_power(struct tg3 *tp)
1995{
1996 struct tg3 *tp_peer = tp;
1997
9d26e213 1998 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1999 return;
2000
f6eb9b1f
MC		 2001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2004 struct net_device *dev_peer;
2005
2006 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2007 /* remove_one() may have been run on the peer. */
8c2dc7e1 2008 if (!dev_peer)
bc1c7567
MC		 2009 tp_peer = tp;
2010 else
2011 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2012 }
2013
1da177e4 2014 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2015 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2016 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2017 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2020 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2021 (GRC_LCLCTRL_GPIO_OE0 |
2022 GRC_LCLCTRL_GPIO_OE1 |
2023 GRC_LCLCTRL_GPIO_OE2 |
2024 GRC_LCLCTRL_GPIO_OUTPUT0 |
2025 GRC_LCLCTRL_GPIO_OUTPUT1),
2026 100);
8d519ab2
MC		 2027 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2029 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2030 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2031 GRC_LCLCTRL_GPIO_OE1 |
2032 GRC_LCLCTRL_GPIO_OE2 |
2033 GRC_LCLCTRL_GPIO_OUTPUT0 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 tp->grc_local_ctrl;
2036 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037
2038 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2039 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2040
2041 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2042 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2043 } else {
2044 u32 no_gpio2;
dc56b7d4 2045 u32 grc_local_ctrl = 0;
1da177e4
LT		 2046
2047 if (tp_peer != tp &&
2048 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2049 return;
2050
dc56b7d4
MC		 2051 /* Workaround to prevent overdrawing Amps. */
2052 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2053 ASIC_REV_5714) {
2054 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056 grc_local_ctrl, 100);
dc56b7d4
MC		 2057 }
2058
1da177e4
LT		 2059 /* On 5753 and variants, GPIO2 cannot be used. */
2060 no_gpio2 = tp->nic_sram_data_cfg &
2061 NIC_SRAM_DATA_CFG_NO_GPIO2;
2062
dc56b7d4 2063 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2064 GRC_LCLCTRL_GPIO_OE1 |
2065 GRC_LCLCTRL_GPIO_OE2 |
2066 GRC_LCLCTRL_GPIO_OUTPUT1 |
2067 GRC_LCLCTRL_GPIO_OUTPUT2;
2068 if (no_gpio2) {
2069 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2070 GRC_LCLCTRL_GPIO_OUTPUT2);
2071 }
b401e9e2
MC		 2072 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073 grc_local_ctrl, 100);
1da177e4
LT		 2074
2075 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2076
b401e9e2
MC		 2077 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078 grc_local_ctrl, 100);
1da177e4
LT		 2079
2080 if (!no_gpio2) {
2081 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083 grc_local_ctrl, 100);
1da177e4
LT		 2084 }
2085 }
2086 } else {
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2088 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2089 if (tp_peer != tp &&
2090 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2091 return;
2092
b401e9e2
MC		 2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 (GRC_LCLCTRL_GPIO_OE1 |
2095 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2096
b401e9e2
MC		 2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2099
b401e9e2
MC		 2100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101 (GRC_LCLCTRL_GPIO_OE1 |
2102 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2103 }
2104 }
2105}
2106
e8f3f6ca
MC		 2107static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2108{
2109 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2110 return 1;
2111 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2112 if (speed != SPEED_10)
2113 return 1;
2114 } else if (speed == SPEED_10)
2115 return 1;
2116
2117 return 0;
2118}
2119
1da177e4
LT		 2120static int tg3_setup_phy(struct tg3 *, int);
2121
2122#define RESET_KIND_SHUTDOWN 0
2123#define RESET_KIND_INIT 1
2124#define RESET_KIND_SUSPEND 2
2125
2126static void tg3_write_sig_post_reset(struct tg3 *, int);
2127static int tg3_halt_cpu(struct tg3 *, u32);
2128
0a459aac 2129static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2130{
ce057f01
MC		 2131 u32 val;
2132
5129724a
MC		 2133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2135 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2136 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2137
2138 sg_dig_ctrl |=
2139 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2140 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2141 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2142 }
3f7045c1 2143 return;
5129724a 2144 }
3f7045c1 2145
60189ddf 2146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2147 tg3_bmcr_reset(tp);
2148 val = tr32(GRC_MISC_CFG);
2149 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2150 udelay(40);
2151 return;
0a459aac 2152 } else if (do_low_power) {
715116a1
MC		 2153 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2154 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2155
2156 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2157 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2158 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2159 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2160 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2161 }
3f7045c1 2162
15c3b696
MC		 2163 /* The PHY should not be powered down on some chips because
2164 * of bugs.
2165 */
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2167 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2168 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2169 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2170 return;
ce057f01 2171
bcb37f6c
MC		 2172 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2173 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2174 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2175 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2176 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2177 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2178 }
2179
15c3b696
MC		 2180 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2181}
2182
ffbcfed4
MC		 2183/* tp->lock is held. */
2184static int tg3_nvram_lock(struct tg3 *tp)
2185{
2186 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2187 int i;
2188
2189 if (tp->nvram_lock_cnt == 0) {
2190 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2191 for (i = 0; i < 8000; i++) {
2192 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2193 break;
2194 udelay(20);
2195 }
2196 if (i == 8000) {
2197 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2198 return -ENODEV;
2199 }
2200 }
2201 tp->nvram_lock_cnt++;
2202 }
2203 return 0;
2204}
2205
2206/* tp->lock is held. */
2207static void tg3_nvram_unlock(struct tg3 *tp)
2208{
2209 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2210 if (tp->nvram_lock_cnt > 0)
2211 tp->nvram_lock_cnt--;
2212 if (tp->nvram_lock_cnt == 0)
2213 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2214 }
2215}
2216
2217/* tp->lock is held. */
2218static void tg3_enable_nvram_access(struct tg3 *tp)
2219{
2220 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2221 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2222 u32 nvaccess = tr32(NVRAM_ACCESS);
2223
2224 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2225 }
2226}
2227
2228/* tp->lock is held. */
2229static void tg3_disable_nvram_access(struct tg3 *tp)
2230{
2231 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2232 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2233 u32 nvaccess = tr32(NVRAM_ACCESS);
2234
2235 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2236 }
2237}
2238
2239static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2240 u32 offset, u32 *val)
2241{
2242 u32 tmp;
2243 int i;
2244
2245 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2246 return -EINVAL;
2247
2248 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2249 EEPROM_ADDR_DEVID_MASK |
2250 EEPROM_ADDR_READ);
2251 tw32(GRC_EEPROM_ADDR,
2252 tmp |
2253 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2254 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2255 EEPROM_ADDR_ADDR_MASK) |
2256 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2257
2258 for (i = 0; i < 1000; i++) {
2259 tmp = tr32(GRC_EEPROM_ADDR);
2260
2261 if (tmp & EEPROM_ADDR_COMPLETE)
2262 break;
2263 msleep(1);
2264 }
2265 if (!(tmp & EEPROM_ADDR_COMPLETE))
2266 return -EBUSY;
2267
62cedd11
MC		 2268 tmp = tr32(GRC_EEPROM_DATA);
2269
2270 /*
2271 * The data will always be opposite the native endian
2272 * format. Perform a blind byteswap to compensate.
2273 */
2274 *val = swab32(tmp);
2275
ffbcfed4
MC		 2276 return 0;
2277}
2278
2279#define NVRAM_CMD_TIMEOUT 10000
2280
2281static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2282{
2283 int i;
2284
2285 tw32(NVRAM_CMD, nvram_cmd);
2286 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2287 udelay(10);
2288 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2289 udelay(10);
2290 break;
2291 }
2292 }
2293
2294 if (i == NVRAM_CMD_TIMEOUT)
2295 return -EBUSY;
2296
2297 return 0;
2298}
2299
2300static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2301{
2302 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2303 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2304 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2305 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2306 (tp->nvram_jedecnum == JEDEC_ATMEL))
2307
2308 addr = ((addr / tp->nvram_pagesize) <<
2309 ATMEL_AT45DB0X1B_PAGE_POS) +
2310 (addr % tp->nvram_pagesize);
2311
2312 return addr;
2313}
2314
2315static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2316{
2317 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2318 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2319 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2320 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2321 (tp->nvram_jedecnum == JEDEC_ATMEL))
2322
2323 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2324 tp->nvram_pagesize) +
2325 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2326
2327 return addr;
2328}
2329
e4f34110
MC		 2330/* NOTE: Data read in from NVRAM is byteswapped according to
2331 * the byteswapping settings for all other register accesses.
2332 * tg3 devices are BE devices, so on a BE machine, the data
2333 * returned will be exactly as it is seen in NVRAM. On a LE
2334 * machine, the 32-bit value will be byteswapped.
2335 */
ffbcfed4
MC		 2336static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2337{
2338 int ret;
2339
2340 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2341 return tg3_nvram_read_using_eeprom(tp, offset, val);
2342
2343 offset = tg3_nvram_phys_addr(tp, offset);
2344
2345 if (offset > NVRAM_ADDR_MSK)
2346 return -EINVAL;
2347
2348 ret = tg3_nvram_lock(tp);
2349 if (ret)
2350 return ret;
2351
2352 tg3_enable_nvram_access(tp);
2353
2354 tw32(NVRAM_ADDR, offset);
2355 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2356 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2357
2358 if (ret == 0)
e4f34110 2359 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2360
2361 tg3_disable_nvram_access(tp);
2362
2363 tg3_nvram_unlock(tp);
2364
2365 return ret;
2366}
2367
a9dc529d
MC		 2368/* Ensures NVRAM data is in bytestream format. */
2369static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2370{
2371 u32 v;
a9dc529d 2372 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2373 if (!res)
a9dc529d 2374 *val = cpu_to_be32(v);
ffbcfed4
MC		 2375 return res;
2376}
2377
3f007891
MC		 2378/* tp->lock is held. */
2379static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2380{
2381 u32 addr_high, addr_low;
2382 int i;
2383
2384 addr_high = ((tp->dev->dev_addr[0] << 8) |
2385 tp->dev->dev_addr[1]);
2386 addr_low = ((tp->dev->dev_addr[2] << 24) |
2387 (tp->dev->dev_addr[3] << 16) |
2388 (tp->dev->dev_addr[4] << 8) |
2389 (tp->dev->dev_addr[5] << 0));
2390 for (i = 0; i < 4; i++) {
2391 if (i == 1 && skip_mac_1)
2392 continue;
2393 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2394 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2395 }
2396
2397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2399 for (i = 0; i < 12; i++) {
2400 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2401 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2402 }
2403 }
2404
2405 addr_high = (tp->dev->dev_addr[0] +
2406 tp->dev->dev_addr[1] +
2407 tp->dev->dev_addr[2] +
2408 tp->dev->dev_addr[3] +
2409 tp->dev->dev_addr[4] +
2410 tp->dev->dev_addr[5]) &
2411 TX_BACKOFF_SEED_MASK;
2412 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2413}
2414
bc1c7567 2415static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2416{
2417 u32 misc_host_ctrl;
0a459aac 2418 bool device_should_wake, do_low_power;
1da177e4
LT		 2419
2420 /* Make sure register accesses (indirect or otherwise)
2421 * will function correctly.
2422 */
2423 pci_write_config_dword(tp->pdev,
2424 TG3PCI_MISC_HOST_CTRL,
2425 tp->misc_host_ctrl);
2426
1da177e4 2427 switch (state) {
bc1c7567 2428 case PCI_D0:
12dac075
RW		 2429 pci_enable_wake(tp->pdev, state, false);
2430 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2431
9d26e213
MC		 2432 /* Switch out of Vaux if it is a NIC */
2433 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2434 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2435
2436 return 0;
2437
bc1c7567 2438 case PCI_D1:
bc1c7567 2439 case PCI_D2:
bc1c7567 2440 case PCI_D3hot:
1da177e4
LT		 2441 break;
2442
2443 default:
12dac075
RW		 2444 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2445 tp->dev->name, state);
1da177e4 2446 return -EINVAL;
855e1111 2447 }
5e7dfd0f
MC		 2448
2449 /* Restore the CLKREQ setting. */
2450 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2451 u16 lnkctl;
2452
2453 pci_read_config_word(tp->pdev,
2454 tp->pcie_cap + PCI_EXP_LNKCTL,
2455 &lnkctl);
2456 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2457 pci_write_config_word(tp->pdev,
2458 tp->pcie_cap + PCI_EXP_LNKCTL,
2459 lnkctl);
2460 }
2461
1da177e4
LT		 2462 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2463 tw32(TG3PCI_MISC_HOST_CTRL,
2464 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2465
05ac4cb7
MC		 2466 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2467 device_may_wakeup(&tp->pdev->dev) &&
2468 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2469
dd477003 2470 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2471 do_low_power = false;
b02fd9e3
MC		 2472 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2473 !tp->link_config.phy_is_low_power) {
2474 struct phy_device *phydev;
0a459aac 2475 u32 phyid, advertising;
b02fd9e3 2476
298cf9be 2477 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2478
2479 tp->link_config.phy_is_low_power = 1;
2480
2481 tp->link_config.orig_speed = phydev->speed;
2482 tp->link_config.orig_duplex = phydev->duplex;
2483 tp->link_config.orig_autoneg = phydev->autoneg;
2484 tp->link_config.orig_advertising = phydev->advertising;
2485
2486 advertising = ADVERTISED_TP |
2487 ADVERTISED_Pause |
2488 ADVERTISED_Autoneg |
2489 ADVERTISED_10baseT_Half;
2490
2491 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2492 device_should_wake) {
b02fd9e3
MC		 2493 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2494 advertising |=
2495 ADVERTISED_100baseT_Half |
2496 ADVERTISED_100baseT_Full |
2497 ADVERTISED_10baseT_Full;
2498 else
2499 advertising |= ADVERTISED_10baseT_Full;
2500 }
2501
2502 phydev->advertising = advertising;
2503
2504 phy_start_aneg(phydev);
0a459aac
MC		 2505
2506 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2507 if (phyid != TG3_PHY_ID_BCMAC131) {
2508 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2509 if (phyid == TG3_PHY_OUI_1 ||
2510 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2511 phyid == TG3_PHY_OUI_3)
2512 do_low_power = true;
2513 }
b02fd9e3 2514 }
dd477003 2515 } else {
2023276e 2516 do_low_power = true;
0a459aac 2517
dd477003
MC		 2518 if (tp->link_config.phy_is_low_power == 0) {
2519 tp->link_config.phy_is_low_power = 1;
2520 tp->link_config.orig_speed = tp->link_config.speed;
2521 tp->link_config.orig_duplex = tp->link_config.duplex;
2522 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2523 }
1da177e4 2524
dd477003
MC		 2525 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2526 tp->link_config.speed = SPEED_10;
2527 tp->link_config.duplex = DUPLEX_HALF;
2528 tp->link_config.autoneg = AUTONEG_ENABLE;
2529 tg3_setup_phy(tp, 0);
2530 }
1da177e4
LT		 2531 }
2532
b5d3772c
MC		 2533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2534 u32 val;
2535
2536 val = tr32(GRC_VCPU_EXT_CTRL);
2537 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2538 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2539 int i;
2540 u32 val;
2541
2542 for (i = 0; i < 200; i++) {
2543 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2544 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2545 break;
2546 msleep(1);
2547 }
2548 }
a85feb8c
GZ		 2549 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2550 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2551 WOL_DRV_STATE_SHUTDOWN |
2552 WOL_DRV_WOL |
2553 WOL_SET_MAGIC_PKT);
6921d201 2554
05ac4cb7 2555 if (device_should_wake) {
1da177e4
LT		 2556 u32 mac_mode;
2557
2558 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2559 if (do_low_power) {
dd477003
MC		 2560 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2561 udelay(40);
2562 }
1da177e4 2563
3f7045c1
MC		 2564 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2565 mac_mode = MAC_MODE_PORT_MODE_GMII;
2566 else
2567 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2568
e8f3f6ca
MC		 2569 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2570 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2571 ASIC_REV_5700) {
2572 u32 speed = (tp->tg3_flags &
2573 TG3_FLAG_WOL_SPEED_100MB) ?
2574 SPEED_100 : SPEED_10;
2575 if (tg3_5700_link_polarity(tp, speed))
2576 mac_mode |= MAC_MODE_LINK_POLARITY;
2577 else
2578 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2579 }
1da177e4
LT		 2580 } else {
2581 mac_mode = MAC_MODE_PORT_MODE_TBI;
2582 }
2583
cbf46853 2584 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2585 tw32(MAC_LED_CTRL, tp->led_ctrl);
2586
05ac4cb7
MC		 2587 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2588 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2589 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2590 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2591 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2592 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2593
3bda1258
MC		 2594 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2595 mac_mode |= tp->mac_mode &
2596 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2597 if (mac_mode & MAC_MODE_APE_TX_EN)
2598 mac_mode |= MAC_MODE_TDE_ENABLE;
2599 }
2600
1da177e4
LT		 2601 tw32_f(MAC_MODE, mac_mode);
2602 udelay(100);
2603
2604 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2605 udelay(10);
2606 }
2607
2608 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2609 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2611 u32 base_val;
2612
2613 base_val = tp->pci_clock_ctrl;
2614 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2615 CLOCK_CTRL_TXCLK_DISABLE);
2616
b401e9e2
MC		 2617 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2618 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2619 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2620 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2621 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2622 /* do nothing */
85e94ced 2623 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2624 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2625 u32 newbits1, newbits2;
2626
2627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2629 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2630 CLOCK_CTRL_TXCLK_DISABLE |
2631 CLOCK_CTRL_ALTCLK);
2632 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2633 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2634 newbits1 = CLOCK_CTRL_625_CORE;
2635 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2636 } else {
2637 newbits1 = CLOCK_CTRL_ALTCLK;
2638 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2639 }
2640
b401e9e2
MC		 2641 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2642 40);
1da177e4 2643
b401e9e2
MC		 2644 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2645 40);
1da177e4
LT		 2646
2647 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2648 u32 newbits3;
2649
2650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2652 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2653 CLOCK_CTRL_TXCLK_DISABLE |
2654 CLOCK_CTRL_44MHZ_CORE);
2655 } else {
2656 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2657 }
2658
b401e9e2
MC		 2659 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2660 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2661 }
2662 }
2663
05ac4cb7 2664 if (!(device_should_wake) &&
22435849 2665 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2666 tg3_power_down_phy(tp, do_low_power);
6921d201 2667
1da177e4
LT		 2668 tg3_frob_aux_power(tp);
2669
2670 /* Workaround for unstable PLL clock */
2671 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2672 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2673 u32 val = tr32(0x7d00);
2674
2675 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2676 tw32(0x7d00, val);
6921d201 2677 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2678 int err;
2679
2680 err = tg3_nvram_lock(tp);
1da177e4 2681 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2682 if (!err)
2683 tg3_nvram_unlock(tp);
6921d201 2684 }
1da177e4
LT		 2685 }
2686
bbadf503
MC		 2687 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2688
05ac4cb7 2689 if (device_should_wake)
12dac075
RW		 2690 pci_enable_wake(tp->pdev, state, true);
2691
1da177e4 2692 /* Finally, set the new power state. */
12dac075 2693 pci_set_power_state(tp->pdev, state);
1da177e4 2694
1da177e4
LT		 2695 return 0;
2696}
2697
1da177e4
LT		 2698static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2699{
2700 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2701 case MII_TG3_AUX_STAT_10HALF:
2702 *speed = SPEED_10;
2703 *duplex = DUPLEX_HALF;
2704 break;
2705
2706 case MII_TG3_AUX_STAT_10FULL:
2707 *speed = SPEED_10;
2708 *duplex = DUPLEX_FULL;
2709 break;
2710
2711 case MII_TG3_AUX_STAT_100HALF:
2712 *speed = SPEED_100;
2713 *duplex = DUPLEX_HALF;
2714 break;
2715
2716 case MII_TG3_AUX_STAT_100FULL:
2717 *speed = SPEED_100;
2718 *duplex = DUPLEX_FULL;
2719 break;
2720
2721 case MII_TG3_AUX_STAT_1000HALF:
2722 *speed = SPEED_1000;
2723 *duplex = DUPLEX_HALF;
2724 break;
2725
2726 case MII_TG3_AUX_STAT_1000FULL:
2727 *speed = SPEED_1000;
2728 *duplex = DUPLEX_FULL;
2729 break;
2730
2731 default:
7f97a4bd 2732 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2733 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2734 SPEED_10;
2735 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2736 DUPLEX_HALF;
2737 break;
2738 }
1da177e4
LT		 2739 *speed = SPEED_INVALID;
2740 *duplex = DUPLEX_INVALID;
2741 break;
855e1111 2742 }
1da177e4
LT		 2743}
2744
2745static void tg3_phy_copper_begin(struct tg3 *tp)
2746{
2747 u32 new_adv;
2748 int i;
2749
2750 if (tp->link_config.phy_is_low_power) {
2751 /* Entering low power mode. Disable gigabit and
2752 * 100baseT advertisements.
2753 */
2754 tg3_writephy(tp, MII_TG3_CTRL, 0);
2755
2756 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2757 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2758 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2759 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2760
2761 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2762 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2763 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2764 tp->link_config.advertising &=
2765 ~(ADVERTISED_1000baseT_Half |
2766 ADVERTISED_1000baseT_Full);
2767
ba4d07a8 2768 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2769 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2770 new_adv |= ADVERTISE_10HALF;
2771 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2772 new_adv |= ADVERTISE_10FULL;
2773 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2774 new_adv |= ADVERTISE_100HALF;
2775 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2776 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2777
2778 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2779
1da177e4
LT		 2780 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2781
2782 if (tp->link_config.advertising &
2783 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2784 new_adv = 0;
2785 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2786 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2787 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2788 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2789 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2790 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2791 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2792 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2793 MII_TG3_CTRL_ENABLE_AS_MASTER);
2794 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2795 } else {
2796 tg3_writephy(tp, MII_TG3_CTRL, 0);
2797 }
2798 } else {
ba4d07a8
MC		 2799 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2800 new_adv |= ADVERTISE_CSMA;
2801
1da177e4
LT		 2802 /* Asking for a specific link mode. */
2803 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2804 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2805
2806 if (tp->link_config.duplex == DUPLEX_FULL)
2807 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2808 else
2809 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2810 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2811 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2812 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2813 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2814 } else {
1da177e4
LT		 2815 if (tp->link_config.speed == SPEED_100) {
2816 if (tp->link_config.duplex == DUPLEX_FULL)
2817 new_adv |= ADVERTISE_100FULL;
2818 else
2819 new_adv |= ADVERTISE_100HALF;
2820 } else {
2821 if (tp->link_config.duplex == DUPLEX_FULL)
2822 new_adv |= ADVERTISE_10FULL;
2823 else
2824 new_adv |= ADVERTISE_10HALF;
2825 }
2826 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2827
2828 new_adv = 0;
1da177e4 2829 }
ba4d07a8
MC		 2830
2831 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2832 }
2833
2834 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2835 tp->link_config.speed != SPEED_INVALID) {
2836 u32 bmcr, orig_bmcr;
2837
2838 tp->link_config.active_speed = tp->link_config.speed;
2839 tp->link_config.active_duplex = tp->link_config.duplex;
2840
2841 bmcr = 0;
2842 switch (tp->link_config.speed) {
2843 default:
2844 case SPEED_10:
2845 break;
2846
2847 case SPEED_100:
2848 bmcr |= BMCR_SPEED100;
2849 break;
2850
2851 case SPEED_1000:
2852 bmcr |= TG3_BMCR_SPEED1000;
2853 break;
855e1111 2854 }
1da177e4
LT		 2855
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 bmcr |= BMCR_FULLDPLX;
2858
2859 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2860 (bmcr != orig_bmcr)) {
2861 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2862 for (i = 0; i < 1500; i++) {
2863 u32 tmp;
2864
2865 udelay(10);
2866 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2867 tg3_readphy(tp, MII_BMSR, &tmp))
2868 continue;
2869 if (!(tmp & BMSR_LSTATUS)) {
2870 udelay(40);
2871 break;
2872 }
2873 }
2874 tg3_writephy(tp, MII_BMCR, bmcr);
2875 udelay(40);
2876 }
2877 } else {
2878 tg3_writephy(tp, MII_BMCR,
2879 BMCR_ANENABLE | BMCR_ANRESTART);
2880 }
2881}
2882
2883static int tg3_init_5401phy_dsp(struct tg3 *tp)
2884{
2885 int err;
2886
2887 /* Turn off tap power management. */
2888 /* Set Extended packet length bit */
2889 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2890
2891 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2892 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2893
2894 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2895 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2896
2897 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2898 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2899
2900 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2901 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2902
2903 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2904 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2905
2906 udelay(40);
2907
2908 return err;
2909}
2910
3600d918 2911static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2912{
3600d918
MC		 2913 u32 adv_reg, all_mask = 0;
2914
2915 if (mask & ADVERTISED_10baseT_Half)
2916 all_mask |= ADVERTISE_10HALF;
2917 if (mask & ADVERTISED_10baseT_Full)
2918 all_mask |= ADVERTISE_10FULL;
2919 if (mask & ADVERTISED_100baseT_Half)
2920 all_mask |= ADVERTISE_100HALF;
2921 if (mask & ADVERTISED_100baseT_Full)
2922 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2923
2924 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2925 return 0;
2926
1da177e4
LT		 2927 if ((adv_reg & all_mask) != all_mask)
2928 return 0;
2929 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2930 u32 tg3_ctrl;
2931
3600d918
MC		 2932 all_mask = 0;
2933 if (mask & ADVERTISED_1000baseT_Half)
2934 all_mask |= ADVERTISE_1000HALF;
2935 if (mask & ADVERTISED_1000baseT_Full)
2936 all_mask |= ADVERTISE_1000FULL;
2937
1da177e4
LT		 2938 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2939 return 0;
2940
1da177e4
LT		 2941 if ((tg3_ctrl & all_mask) != all_mask)
2942 return 0;
2943 }
2944 return 1;
2945}
2946
ef167e27
MC		 2947static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2948{
2949 u32 curadv, reqadv;
2950
2951 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2952 return 1;
2953
2954 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2955 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2956
2957 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2958 if (curadv != reqadv)
2959 return 0;
2960
2961 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2962 tg3_readphy(tp, MII_LPA, rmtadv);
2963 } else {
2964 /* Reprogram the advertisement register, even if it
2965 * does not affect the current link. If the link
2966 * gets renegotiated in the future, we can save an
2967 * additional renegotiation cycle by advertising
2968 * it correctly in the first place.
2969 */
2970 if (curadv != reqadv) {
2971 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2972 ADVERTISE_PAUSE_ASYM);
2973 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2974 }
2975 }
2976
2977 return 1;
2978}
2979
1da177e4
LT		 2980static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2981{
2982 int current_link_up;
2983 u32 bmsr, dummy;
ef167e27 2984 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2985 u16 current_speed;
2986 u8 current_duplex;
2987 int i, err;
2988
2989 tw32(MAC_EVENT, 0);
2990
2991 tw32_f(MAC_STATUS,
2992 (MAC_STATUS_SYNC_CHANGED |
2993 MAC_STATUS_CFG_CHANGED |
2994 MAC_STATUS_MI_COMPLETION |
2995 MAC_STATUS_LNKSTATE_CHANGED));
2996 udelay(40);
2997
8ef21428
MC		 2998 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2999 tw32_f(MAC_MI_MODE,
3000 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3001 udelay(80);
3002 }
1da177e4
LT		 3003
3004 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3005
3006 /* Some third-party PHYs need to be reset on link going
3007 * down.
3008 */
3009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3012 netif_carrier_ok(tp->dev)) {
3013 tg3_readphy(tp, MII_BMSR, &bmsr);
3014 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3015 !(bmsr & BMSR_LSTATUS))
3016 force_reset = 1;
3017 }
3018 if (force_reset)
3019 tg3_phy_reset(tp);
3020
3021 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3022 tg3_readphy(tp, MII_BMSR, &bmsr);
3023 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3024 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3025 bmsr = 0;
3026
3027 if (!(bmsr & BMSR_LSTATUS)) {
3028 err = tg3_init_5401phy_dsp(tp);
3029 if (err)
3030 return err;
3031
3032 tg3_readphy(tp, MII_BMSR, &bmsr);
3033 for (i = 0; i < 1000; i++) {
3034 udelay(10);
3035 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3036 (bmsr & BMSR_LSTATUS)) {
3037 udelay(40);
3038 break;
3039 }
3040 }
3041
3042 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3043 !(bmsr & BMSR_LSTATUS) &&
3044 tp->link_config.active_speed == SPEED_1000) {
3045 err = tg3_phy_reset(tp);
3046 if (!err)
3047 err = tg3_init_5401phy_dsp(tp);
3048 if (err)
3049 return err;
3050 }
3051 }
3052 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3053 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3054 /* 5701 {A0,B0} CRC bug workaround */
3055 tg3_writephy(tp, 0x15, 0x0a75);
3056 tg3_writephy(tp, 0x1c, 0x8c68);
3057 tg3_writephy(tp, 0x1c, 0x8d68);
3058 tg3_writephy(tp, 0x1c, 0x8c68);
3059 }
3060
3061 /* Clear pending interrupts... */
3062 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3063 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3064
3065 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3066 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3067 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3068 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3069
3070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3072 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3073 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3074 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3075 else
3076 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3077 }
3078
3079 current_link_up = 0;
3080 current_speed = SPEED_INVALID;
3081 current_duplex = DUPLEX_INVALID;
3082
3083 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3084 u32 val;
3085
3086 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3087 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3088 if (!(val & (1 << 10))) {
3089 val |= (1 << 10);
3090 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3091 goto relink;
3092 }
3093 }
3094
3095 bmsr = 0;
3096 for (i = 0; i < 100; i++) {
3097 tg3_readphy(tp, MII_BMSR, &bmsr);
3098 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3099 (bmsr & BMSR_LSTATUS))
3100 break;
3101 udelay(40);
3102 }
3103
3104 if (bmsr & BMSR_LSTATUS) {
3105 u32 aux_stat, bmcr;
3106
3107 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3108 for (i = 0; i < 2000; i++) {
3109 udelay(10);
3110 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3111 aux_stat)
3112 break;
3113 }
3114
3115 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3116 &current_speed,
3117 &current_duplex);
3118
3119 bmcr = 0;
3120 for (i = 0; i < 200; i++) {
3121 tg3_readphy(tp, MII_BMCR, &bmcr);
3122 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3123 continue;
3124 if (bmcr && bmcr != 0x7fff)
3125 break;
3126 udelay(10);
3127 }
3128
ef167e27
MC		 3129 lcl_adv = 0;
3130 rmt_adv = 0;
1da177e4 3131
ef167e27
MC		 3132 tp->link_config.active_speed = current_speed;
3133 tp->link_config.active_duplex = current_duplex;
3134
3135 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3136 if ((bmcr & BMCR_ANENABLE) &&
3137 tg3_copper_is_advertising_all(tp,
3138 tp->link_config.advertising)) {
3139 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3140 &rmt_adv))
3141 current_link_up = 1;
1da177e4
LT		 3142 }
3143 } else {
3144 if (!(bmcr & BMCR_ANENABLE) &&
3145 tp->link_config.speed == current_speed &&
ef167e27
MC		 3146 tp->link_config.duplex == current_duplex &&
3147 tp->link_config.flowctrl ==
3148 tp->link_config.active_flowctrl) {
1da177e4 3149 current_link_up = 1;
1da177e4
LT		 3150 }
3151 }
3152
ef167e27
MC		 3153 if (current_link_up == 1 &&
3154 tp->link_config.active_duplex == DUPLEX_FULL)
3155 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3156 }
3157
1da177e4 3158relink:
6921d201 3159 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3160 u32 tmp;
3161
3162 tg3_phy_copper_begin(tp);
3163
3164 tg3_readphy(tp, MII_BMSR, &tmp);
3165 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3166 (tmp & BMSR_LSTATUS))
3167 current_link_up = 1;
3168 }
3169
3170 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3171 if (current_link_up == 1) {
3172 if (tp->link_config.active_speed == SPEED_100 ||
3173 tp->link_config.active_speed == SPEED_10)
3174 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3175 else
3176 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3177 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3178 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3179 else
1da177e4
LT		 3180 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3181
3182 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3183 if (tp->link_config.active_duplex == DUPLEX_HALF)
3184 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3185
1da177e4 3186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3187 if (current_link_up == 1 &&
3188 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3189 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3190 else
3191 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3192 }
3193
3194 /* ??? Without this setting Netgear GA302T PHY does not
3195 * ??? send/receive packets...
3196 */
3197 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3198 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3199 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3200 tw32_f(MAC_MI_MODE, tp->mi_mode);
3201 udelay(80);
3202 }
3203
3204 tw32_f(MAC_MODE, tp->mac_mode);
3205 udelay(40);
3206
3207 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3208 /* Polled via timer. */
3209 tw32_f(MAC_EVENT, 0);
3210 } else {
3211 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3212 }
3213 udelay(40);
3214
3215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3216 current_link_up == 1 &&
3217 tp->link_config.active_speed == SPEED_1000 &&
3218 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3219 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3220 udelay(120);
3221 tw32_f(MAC_STATUS,
3222 (MAC_STATUS_SYNC_CHANGED |
3223 MAC_STATUS_CFG_CHANGED));
3224 udelay(40);
3225 tg3_write_mem(tp,
3226 NIC_SRAM_FIRMWARE_MBOX,
3227 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3228 }
3229
5e7dfd0f
MC		 3230 /* Prevent send BD corruption. */
3231 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3232 u16 oldlnkctl, newlnkctl;
3233
3234 pci_read_config_word(tp->pdev,
3235 tp->pcie_cap + PCI_EXP_LNKCTL,
3236 &oldlnkctl);
3237 if (tp->link_config.active_speed == SPEED_100 ||
3238 tp->link_config.active_speed == SPEED_10)
3239 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3240 else
3241 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3242 if (newlnkctl != oldlnkctl)
3243 pci_write_config_word(tp->pdev,
3244 tp->pcie_cap + PCI_EXP_LNKCTL,
3245 newlnkctl);
255ca311
MC		 3246 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3247 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3248 if (tp->link_config.active_speed == SPEED_100 ||
3249 tp->link_config.active_speed == SPEED_10)
3250 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3251 else
3252 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3253 if (newreg != oldreg)
3254 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3255 }
3256
1da177e4
LT		 3257 if (current_link_up != netif_carrier_ok(tp->dev)) {
3258 if (current_link_up)
3259 netif_carrier_on(tp->dev);
3260 else
3261 netif_carrier_off(tp->dev);
3262 tg3_link_report(tp);
3263 }
3264
3265 return 0;
3266}
3267
3268struct tg3_fiber_aneginfo {
3269 int state;
3270#define ANEG_STATE_UNKNOWN 0
3271#define ANEG_STATE_AN_ENABLE 1
3272#define ANEG_STATE_RESTART_INIT 2
3273#define ANEG_STATE_RESTART 3
3274#define ANEG_STATE_DISABLE_LINK_OK 4
3275#define ANEG_STATE_ABILITY_DETECT_INIT 5
3276#define ANEG_STATE_ABILITY_DETECT 6
3277#define ANEG_STATE_ACK_DETECT_INIT 7
3278#define ANEG_STATE_ACK_DETECT 8
3279#define ANEG_STATE_COMPLETE_ACK_INIT 9
3280#define ANEG_STATE_COMPLETE_ACK 10
3281#define ANEG_STATE_IDLE_DETECT_INIT 11
3282#define ANEG_STATE_IDLE_DETECT 12
3283#define ANEG_STATE_LINK_OK 13
3284#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3285#define ANEG_STATE_NEXT_PAGE_WAIT 15
3286
3287 u32 flags;
3288#define MR_AN_ENABLE 0x00000001
3289#define MR_RESTART_AN 0x00000002
3290#define MR_AN_COMPLETE 0x00000004
3291#define MR_PAGE_RX 0x00000008
3292#define MR_NP_LOADED 0x00000010
3293#define MR_TOGGLE_TX 0x00000020
3294#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3295#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3296#define MR_LP_ADV_SYM_PAUSE 0x00000100
3297#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3298#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3299#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3300#define MR_LP_ADV_NEXT_PAGE 0x00001000
3301#define MR_TOGGLE_RX 0x00002000
3302#define MR_NP_RX 0x00004000
3303
3304#define MR_LINK_OK 0x80000000
3305
3306 unsigned long link_time, cur_time;
3307
3308 u32 ability_match_cfg;
3309 int ability_match_count;
3310
3311 char ability_match, idle_match, ack_match;
3312
3313 u32 txconfig, rxconfig;
3314#define ANEG_CFG_NP 0x00000080
3315#define ANEG_CFG_ACK 0x00000040
3316#define ANEG_CFG_RF2 0x00000020
3317#define ANEG_CFG_RF1 0x00000010
3318#define ANEG_CFG_PS2 0x00000001
3319#define ANEG_CFG_PS1 0x00008000
3320#define ANEG_CFG_HD 0x00004000
3321#define ANEG_CFG_FD 0x00002000
3322#define ANEG_CFG_INVAL 0x00001f06
3323
3324};
3325#define ANEG_OK 0
3326#define ANEG_DONE 1
3327#define ANEG_TIMER_ENAB 2
3328#define ANEG_FAILED -1
3329
3330#define ANEG_STATE_SETTLE_TIME 10000
3331
3332static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3333 struct tg3_fiber_aneginfo *ap)
3334{
5be73b47 3335 u16 flowctrl;
1da177e4
LT		 3336 unsigned long delta;
3337 u32 rx_cfg_reg;
3338 int ret;
3339
3340 if (ap->state == ANEG_STATE_UNKNOWN) {
3341 ap->rxconfig = 0;
3342 ap->link_time = 0;
3343 ap->cur_time = 0;
3344 ap->ability_match_cfg = 0;
3345 ap->ability_match_count = 0;
3346 ap->ability_match = 0;
3347 ap->idle_match = 0;
3348 ap->ack_match = 0;
3349 }
3350 ap->cur_time++;
3351
3352 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3353 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3354
3355 if (rx_cfg_reg != ap->ability_match_cfg) {
3356 ap->ability_match_cfg = rx_cfg_reg;
3357 ap->ability_match = 0;
3358 ap->ability_match_count = 0;
3359 } else {
3360 if (++ap->ability_match_count > 1) {
3361 ap->ability_match = 1;
3362 ap->ability_match_cfg = rx_cfg_reg;
3363 }
3364 }
3365 if (rx_cfg_reg & ANEG_CFG_ACK)
3366 ap->ack_match = 1;
3367 else
3368 ap->ack_match = 0;
3369
3370 ap->idle_match = 0;
3371 } else {
3372 ap->idle_match = 1;
3373 ap->ability_match_cfg = 0;
3374 ap->ability_match_count = 0;
3375 ap->ability_match = 0;
3376 ap->ack_match = 0;
3377
3378 rx_cfg_reg = 0;
3379 }
3380
3381 ap->rxconfig = rx_cfg_reg;
3382 ret = ANEG_OK;
3383
3384 switch(ap->state) {
3385 case ANEG_STATE_UNKNOWN:
3386 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3387 ap->state = ANEG_STATE_AN_ENABLE;
3388
3389 /* fallthru */
3390 case ANEG_STATE_AN_ENABLE:
3391 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3392 if (ap->flags & MR_AN_ENABLE) {
3393 ap->link_time = 0;
3394 ap->cur_time = 0;
3395 ap->ability_match_cfg = 0;
3396 ap->ability_match_count = 0;
3397 ap->ability_match = 0;
3398 ap->idle_match = 0;
3399 ap->ack_match = 0;
3400
3401 ap->state = ANEG_STATE_RESTART_INIT;
3402 } else {
3403 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3404 }
3405 break;
3406
3407 case ANEG_STATE_RESTART_INIT:
3408 ap->link_time = ap->cur_time;
3409 ap->flags &= ~(MR_NP_LOADED);
3410 ap->txconfig = 0;
3411 tw32(MAC_TX_AUTO_NEG, 0);
3412 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3413 tw32_f(MAC_MODE, tp->mac_mode);
3414 udelay(40);
3415
3416 ret = ANEG_TIMER_ENAB;
3417 ap->state = ANEG_STATE_RESTART;
3418
3419 /* fallthru */
3420 case ANEG_STATE_RESTART:
3421 delta = ap->cur_time - ap->link_time;
3422 if (delta > ANEG_STATE_SETTLE_TIME) {
3423 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3424 } else {
3425 ret = ANEG_TIMER_ENAB;
3426 }
3427 break;
3428
3429 case ANEG_STATE_DISABLE_LINK_OK:
3430 ret = ANEG_DONE;
3431 break;
3432
3433 case ANEG_STATE_ABILITY_DETECT_INIT:
3434 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3435 ap->txconfig = ANEG_CFG_FD;
3436 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3437 if (flowctrl & ADVERTISE_1000XPAUSE)
3438 ap->txconfig |= ANEG_CFG_PS1;
3439 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3440 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3441 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3442 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3443 tw32_f(MAC_MODE, tp->mac_mode);
3444 udelay(40);
3445
3446 ap->state = ANEG_STATE_ABILITY_DETECT;
3447 break;
3448
3449 case ANEG_STATE_ABILITY_DETECT:
3450 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3451 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3452 }
3453 break;
3454
3455 case ANEG_STATE_ACK_DETECT_INIT:
3456 ap->txconfig |= ANEG_CFG_ACK;
3457 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3458 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3459 tw32_f(MAC_MODE, tp->mac_mode);
3460 udelay(40);
3461
3462 ap->state = ANEG_STATE_ACK_DETECT;
3463
3464 /* fallthru */
3465 case ANEG_STATE_ACK_DETECT:
3466 if (ap->ack_match != 0) {
3467 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3468 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3469 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3470 } else {
3471 ap->state = ANEG_STATE_AN_ENABLE;
3472 }
3473 } else if (ap->ability_match != 0 &&
3474 ap->rxconfig == 0) {
3475 ap->state = ANEG_STATE_AN_ENABLE;
3476 }
3477 break;
3478
3479 case ANEG_STATE_COMPLETE_ACK_INIT:
3480 if (ap->rxconfig & ANEG_CFG_INVAL) {
3481 ret = ANEG_FAILED;
3482 break;
3483 }
3484 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3485 MR_LP_ADV_HALF_DUPLEX |
3486 MR_LP_ADV_SYM_PAUSE |
3487 MR_LP_ADV_ASYM_PAUSE |
3488 MR_LP_ADV_REMOTE_FAULT1 |
3489 MR_LP_ADV_REMOTE_FAULT2 |
3490 MR_LP_ADV_NEXT_PAGE |
3491 MR_TOGGLE_RX |
3492 MR_NP_RX);
3493 if (ap->rxconfig & ANEG_CFG_FD)
3494 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3495 if (ap->rxconfig & ANEG_CFG_HD)
3496 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3497 if (ap->rxconfig & ANEG_CFG_PS1)
3498 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3499 if (ap->rxconfig & ANEG_CFG_PS2)
3500 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3501 if (ap->rxconfig & ANEG_CFG_RF1)
3502 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3503 if (ap->rxconfig & ANEG_CFG_RF2)
3504 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3505 if (ap->rxconfig & ANEG_CFG_NP)
3506 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3507
3508 ap->link_time = ap->cur_time;
3509
3510 ap->flags ^= (MR_TOGGLE_TX);
3511 if (ap->rxconfig & 0x0008)
3512 ap->flags |= MR_TOGGLE_RX;
3513 if (ap->rxconfig & ANEG_CFG_NP)
3514 ap->flags |= MR_NP_RX;
3515 ap->flags |= MR_PAGE_RX;
3516
3517 ap->state = ANEG_STATE_COMPLETE_ACK;
3518 ret = ANEG_TIMER_ENAB;
3519 break;
3520
3521 case ANEG_STATE_COMPLETE_ACK:
3522 if (ap->ability_match != 0 &&
3523 ap->rxconfig == 0) {
3524 ap->state = ANEG_STATE_AN_ENABLE;
3525 break;
3526 }
3527 delta = ap->cur_time - ap->link_time;
3528 if (delta > ANEG_STATE_SETTLE_TIME) {
3529 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3530 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3531 } else {
3532 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3533 !(ap->flags & MR_NP_RX)) {
3534 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3535 } else {
3536 ret = ANEG_FAILED;
3537 }
3538 }
3539 }
3540 break;
3541
3542 case ANEG_STATE_IDLE_DETECT_INIT:
3543 ap->link_time = ap->cur_time;
3544 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3545 tw32_f(MAC_MODE, tp->mac_mode);
3546 udelay(40);
3547
3548 ap->state = ANEG_STATE_IDLE_DETECT;
3549 ret = ANEG_TIMER_ENAB;
3550 break;
3551
3552 case ANEG_STATE_IDLE_DETECT:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3556 break;
3557 }
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 /* XXX another gem from the Broadcom driver :( */
3561 ap->state = ANEG_STATE_LINK_OK;
3562 }
3563 break;
3564
3565 case ANEG_STATE_LINK_OK:
3566 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3567 ret = ANEG_DONE;
3568 break;
3569
3570 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3571 /* ??? unimplemented */
3572 break;
3573
3574 case ANEG_STATE_NEXT_PAGE_WAIT:
3575 /* ??? unimplemented */
3576 break;
3577
3578 default:
3579 ret = ANEG_FAILED;
3580 break;
855e1111 3581 }
1da177e4
LT		 3582
3583 return ret;
3584}
3585
5be73b47 3586static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3587{
3588 int res = 0;
3589 struct tg3_fiber_aneginfo aninfo;
3590 int status = ANEG_FAILED;
3591 unsigned int tick;
3592 u32 tmp;
3593
3594 tw32_f(MAC_TX_AUTO_NEG, 0);
3595
3596 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3597 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3598 udelay(40);
3599
3600 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3601 udelay(40);
3602
3603 memset(&aninfo, 0, sizeof(aninfo));
3604 aninfo.flags |= MR_AN_ENABLE;
3605 aninfo.state = ANEG_STATE_UNKNOWN;
3606 aninfo.cur_time = 0;
3607 tick = 0;
3608 while (++tick < 195000) {
3609 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3610 if (status == ANEG_DONE || status == ANEG_FAILED)
3611 break;
3612
3613 udelay(1);
3614 }
3615
3616 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3617 tw32_f(MAC_MODE, tp->mac_mode);
3618 udelay(40);
3619
5be73b47
MC		 3620 *txflags = aninfo.txconfig;
3621 *rxflags = aninfo.flags;
1da177e4
LT		 3622
3623 if (status == ANEG_DONE &&
3624 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3625 MR_LP_ADV_FULL_DUPLEX)))
3626 res = 1;
3627
3628 return res;
3629}
3630
3631static void tg3_init_bcm8002(struct tg3 *tp)
3632{
3633 u32 mac_status = tr32(MAC_STATUS);
3634 int i;
3635
3636 /* Reset when initting first time or we have a link. */
3637 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3638 !(mac_status & MAC_STATUS_PCS_SYNCED))
3639 return;
3640
3641 /* Set PLL lock range. */
3642 tg3_writephy(tp, 0x16, 0x8007);
3643
3644 /* SW reset */
3645 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3646
3647 /* Wait for reset to complete. */
3648 /* XXX schedule_timeout() ... */
3649 for (i = 0; i < 500; i++)
3650 udelay(10);
3651
3652 /* Config mode; select PMA/Ch 1 regs. */
3653 tg3_writephy(tp, 0x10, 0x8411);
3654
3655 /* Enable auto-lock and comdet, select txclk for tx. */
3656 tg3_writephy(tp, 0x11, 0x0a10);
3657
3658 tg3_writephy(tp, 0x18, 0x00a0);
3659 tg3_writephy(tp, 0x16, 0x41ff);
3660
3661 /* Assert and deassert POR. */
3662 tg3_writephy(tp, 0x13, 0x0400);
3663 udelay(40);
3664 tg3_writephy(tp, 0x13, 0x0000);
3665
3666 tg3_writephy(tp, 0x11, 0x0a50);
3667 udelay(40);
3668 tg3_writephy(tp, 0x11, 0x0a10);
3669
3670 /* Wait for signal to stabilize */
3671 /* XXX schedule_timeout() ... */
3672 for (i = 0; i < 15000; i++)
3673 udelay(10);
3674
3675 /* Deselect the channel register so we can read the PHYID
3676 * later.
3677 */
3678 tg3_writephy(tp, 0x10, 0x8011);
3679}
3680
3681static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3682{
82cd3d11 3683 u16 flowctrl;
1da177e4
LT		 3684 u32 sg_dig_ctrl, sg_dig_status;
3685 u32 serdes_cfg, expected_sg_dig_ctrl;
3686 int workaround, port_a;
3687 int current_link_up;
3688
3689 serdes_cfg = 0;
3690 expected_sg_dig_ctrl = 0;
3691 workaround = 0;
3692 port_a = 1;
3693 current_link_up = 0;
3694
3695 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3696 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3697 workaround = 1;
3698 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3699 port_a = 0;
3700
3701 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3702 /* preserve bits 20-23 for voltage regulator */
3703 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3704 }
3705
3706 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3707
3708 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3709 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3710 if (workaround) {
3711 u32 val = serdes_cfg;
3712
3713 if (port_a)
3714 val |= 0xc010000;
3715 else
3716 val |= 0x4010000;
3717 tw32_f(MAC_SERDES_CFG, val);
3718 }
c98f6e3b
MC		 3719
3720 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3721 }
3722 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3723 tg3_setup_flow_control(tp, 0, 0);
3724 current_link_up = 1;
3725 }
3726 goto out;
3727 }
3728
3729 /* Want auto-negotiation. */
c98f6e3b 3730 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3731
82cd3d11
MC		 3732 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3733 if (flowctrl & ADVERTISE_1000XPAUSE)
3734 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3735 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3736 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3737
3738 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3739 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3740 tp->serdes_counter &&
3741 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3742 MAC_STATUS_RCVD_CFG)) ==
3743 MAC_STATUS_PCS_SYNCED)) {
3744 tp->serdes_counter--;
3745 current_link_up = 1;
3746 goto out;
3747 }
3748restart_autoneg:
1da177e4
LT		 3749 if (workaround)
3750 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3751 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3752 udelay(5);
3753 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3754
3d3ebe74
MC		 3755 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3756 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3757 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3758 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3759 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3760 mac_status = tr32(MAC_STATUS);
3761
c98f6e3b 3762 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3763 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3764 u32 local_adv = 0, remote_adv = 0;
3765
3766 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3767 local_adv |= ADVERTISE_1000XPAUSE;
3768 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3769 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3770
c98f6e3b 3771 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3772 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3773 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3774 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3775
3776 tg3_setup_flow_control(tp, local_adv, remote_adv);
3777 current_link_up = 1;
3d3ebe74
MC		 3778 tp->serdes_counter = 0;
3779 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3780 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3781 if (tp->serdes_counter)
3782 tp->serdes_counter--;
1da177e4
LT		 3783 else {
3784 if (workaround) {
3785 u32 val = serdes_cfg;
3786
3787 if (port_a)
3788 val |= 0xc010000;
3789 else
3790 val |= 0x4010000;
3791
3792 tw32_f(MAC_SERDES_CFG, val);
3793 }
3794
c98f6e3b 3795 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3796 udelay(40);
3797
3798 /* Link parallel detection - link is up */
3799 /* only if we have PCS_SYNC and not */
3800 /* receiving config code words */
3801 mac_status = tr32(MAC_STATUS);
3802 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3803 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3804 tg3_setup_flow_control(tp, 0, 0);
3805 current_link_up = 1;
3d3ebe74
MC		 3806 tp->tg3_flags2 |=
3807 TG3_FLG2_PARALLEL_DETECT;
3808 tp->serdes_counter =
3809 SERDES_PARALLEL_DET_TIMEOUT;
3810 } else
3811 goto restart_autoneg;
1da177e4
LT		 3812 }
3813 }
3d3ebe74
MC		 3814 } else {
3815 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3816 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3817 }
3818
3819out:
3820 return current_link_up;
3821}
3822
3823static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3824{
3825 int current_link_up = 0;
3826
5cf64b8a 3827 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3828 goto out;
1da177e4
LT		 3829
3830 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3831 u32 txflags, rxflags;
1da177e4 3832 int i;
6aa20a22 3833
5be73b47
MC		 3834 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3835 u32 local_adv = 0, remote_adv = 0;
1da177e4 3836
5be73b47
MC		 3837 if (txflags & ANEG_CFG_PS1)
3838 local_adv |= ADVERTISE_1000XPAUSE;
3839 if (txflags & ANEG_CFG_PS2)
3840 local_adv |= ADVERTISE_1000XPSE_ASYM;
3841
3842 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3843 remote_adv |= LPA_1000XPAUSE;
3844 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3845 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3846
3847 tg3_setup_flow_control(tp, local_adv, remote_adv);
3848
1da177e4
LT		 3849 current_link_up = 1;
3850 }
3851 for (i = 0; i < 30; i++) {
3852 udelay(20);
3853 tw32_f(MAC_STATUS,
3854 (MAC_STATUS_SYNC_CHANGED |
3855 MAC_STATUS_CFG_CHANGED));
3856 udelay(40);
3857 if ((tr32(MAC_STATUS) &
3858 (MAC_STATUS_SYNC_CHANGED |
3859 MAC_STATUS_CFG_CHANGED)) == 0)
3860 break;
3861 }
3862
3863 mac_status = tr32(MAC_STATUS);
3864 if (current_link_up == 0 &&
3865 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3866 !(mac_status & MAC_STATUS_RCVD_CFG))
3867 current_link_up = 1;
3868 } else {
5be73b47
MC		 3869 tg3_setup_flow_control(tp, 0, 0);
3870
1da177e4
LT		 3871 /* Forcing 1000FD link up. */
3872 current_link_up = 1;
1da177e4
LT		 3873
3874 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3875 udelay(40);
e8f3f6ca
MC		 3876
3877 tw32_f(MAC_MODE, tp->mac_mode);
3878 udelay(40);
1da177e4
LT		 3879 }
3880
3881out:
3882 return current_link_up;
3883}
3884
3885static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3886{
3887 u32 orig_pause_cfg;
3888 u16 orig_active_speed;
3889 u8 orig_active_duplex;
3890 u32 mac_status;
3891 int current_link_up;
3892 int i;
3893
8d018621 3894 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3895 orig_active_speed = tp->link_config.active_speed;
3896 orig_active_duplex = tp->link_config.active_duplex;
3897
3898 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3899 netif_carrier_ok(tp->dev) &&
3900 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3901 mac_status = tr32(MAC_STATUS);
3902 mac_status &= (MAC_STATUS_PCS_SYNCED |
3903 MAC_STATUS_SIGNAL_DET |
3904 MAC_STATUS_CFG_CHANGED |
3905 MAC_STATUS_RCVD_CFG);
3906 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3907 MAC_STATUS_SIGNAL_DET)) {
3908 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3909 MAC_STATUS_CFG_CHANGED));
3910 return 0;
3911 }
3912 }
3913
3914 tw32_f(MAC_TX_AUTO_NEG, 0);
3915
3916 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3917 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3918 tw32_f(MAC_MODE, tp->mac_mode);
3919 udelay(40);
3920
3921 if (tp->phy_id == PHY_ID_BCM8002)
3922 tg3_init_bcm8002(tp);
3923
3924 /* Enable link change event even when serdes polling. */
3925 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3926 udelay(40);
3927
3928 current_link_up = 0;
3929 mac_status = tr32(MAC_STATUS);
3930
3931 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3932 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3933 else
3934 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3935
898a56f8 3936 tp->napi[0].hw_status->status =
1da177e4 3937 (SD_STATUS_UPDATED |
898a56f8 3938 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3939
3940 for (i = 0; i < 100; i++) {
3941 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3942 MAC_STATUS_CFG_CHANGED));
3943 udelay(5);
3944 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3945 MAC_STATUS_CFG_CHANGED |
3946 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3947 break;
3948 }
3949
3950 mac_status = tr32(MAC_STATUS);
3951 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3952 current_link_up = 0;
3d3ebe74
MC		 3953 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3954 tp->serdes_counter == 0) {
1da177e4
LT		 3955 tw32_f(MAC_MODE, (tp->mac_mode |
3956 MAC_MODE_SEND_CONFIGS));
3957 udelay(1);
3958 tw32_f(MAC_MODE, tp->mac_mode);
3959 }
3960 }
3961
3962 if (current_link_up == 1) {
3963 tp->link_config.active_speed = SPEED_1000;
3964 tp->link_config.active_duplex = DUPLEX_FULL;
3965 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3966 LED_CTRL_LNKLED_OVERRIDE |
3967 LED_CTRL_1000MBPS_ON));
3968 } else {
3969 tp->link_config.active_speed = SPEED_INVALID;
3970 tp->link_config.active_duplex = DUPLEX_INVALID;
3971 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3972 LED_CTRL_LNKLED_OVERRIDE |
3973 LED_CTRL_TRAFFIC_OVERRIDE));
3974 }
3975
3976 if (current_link_up != netif_carrier_ok(tp->dev)) {
3977 if (current_link_up)
3978 netif_carrier_on(tp->dev);
3979 else
3980 netif_carrier_off(tp->dev);
3981 tg3_link_report(tp);
3982 } else {
8d018621 3983 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3984 if (orig_pause_cfg != now_pause_cfg ||
3985 orig_active_speed != tp->link_config.active_speed ||
3986 orig_active_duplex != tp->link_config.active_duplex)
3987 tg3_link_report(tp);
3988 }
3989
3990 return 0;
3991}
3992
747e8f8b
MC		 3993static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3994{
3995 int current_link_up, err = 0;
3996 u32 bmsr, bmcr;
3997 u16 current_speed;
3998 u8 current_duplex;
ef167e27 3999 u32 local_adv, remote_adv;
747e8f8b
MC		 4000
4001 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4002 tw32_f(MAC_MODE, tp->mac_mode);
4003 udelay(40);
4004
4005 tw32(MAC_EVENT, 0);
4006
4007 tw32_f(MAC_STATUS,
4008 (MAC_STATUS_SYNC_CHANGED |
4009 MAC_STATUS_CFG_CHANGED |
4010 MAC_STATUS_MI_COMPLETION |
4011 MAC_STATUS_LNKSTATE_CHANGED));
4012 udelay(40);
4013
4014 if (force_reset)
4015 tg3_phy_reset(tp);
4016
4017 current_link_up = 0;
4018 current_speed = SPEED_INVALID;
4019 current_duplex = DUPLEX_INVALID;
4020
4021 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4022 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4024 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4025 bmsr |= BMSR_LSTATUS;
4026 else
4027 bmsr &= ~BMSR_LSTATUS;
4028 }
747e8f8b
MC		 4029
4030 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4031
4032 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4033 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4034 /* do nothing, just check for link up at the end */
4035 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4036 u32 adv, new_adv;
4037
4038 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4039 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4040 ADVERTISE_1000XPAUSE |
4041 ADVERTISE_1000XPSE_ASYM |
4042 ADVERTISE_SLCT);
4043
ba4d07a8 4044 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4045
4046 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4047 new_adv |= ADVERTISE_1000XHALF;
4048 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4049 new_adv |= ADVERTISE_1000XFULL;
4050
4051 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4052 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4053 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4054 tg3_writephy(tp, MII_BMCR, bmcr);
4055
4056 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4057 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4058 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4059
4060 return err;
4061 }
4062 } else {
4063 u32 new_bmcr;
4064
4065 bmcr &= ~BMCR_SPEED1000;
4066 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4067
4068 if (tp->link_config.duplex == DUPLEX_FULL)
4069 new_bmcr |= BMCR_FULLDPLX;
4070
4071 if (new_bmcr != bmcr) {
4072 /* BMCR_SPEED1000 is a reserved bit that needs
4073 * to be set on write.
4074 */
4075 new_bmcr |= BMCR_SPEED1000;
4076
4077 /* Force a linkdown */
4078 if (netif_carrier_ok(tp->dev)) {
4079 u32 adv;
4080
4081 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4082 adv &= ~(ADVERTISE_1000XFULL |
4083 ADVERTISE_1000XHALF |
4084 ADVERTISE_SLCT);
4085 tg3_writephy(tp, MII_ADVERTISE, adv);
4086 tg3_writephy(tp, MII_BMCR, bmcr |
4087 BMCR_ANRESTART |
4088 BMCR_ANENABLE);
4089 udelay(10);
4090 netif_carrier_off(tp->dev);
4091 }
4092 tg3_writephy(tp, MII_BMCR, new_bmcr);
4093 bmcr = new_bmcr;
4094 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4095 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4096 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4097 ASIC_REV_5714) {
4098 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4099 bmsr |= BMSR_LSTATUS;
4100 else
4101 bmsr &= ~BMSR_LSTATUS;
4102 }
747e8f8b
MC		 4103 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4104 }
4105 }
4106
4107 if (bmsr & BMSR_LSTATUS) {
4108 current_speed = SPEED_1000;
4109 current_link_up = 1;
4110 if (bmcr & BMCR_FULLDPLX)
4111 current_duplex = DUPLEX_FULL;
4112 else
4113 current_duplex = DUPLEX_HALF;
4114
ef167e27
MC		 4115 local_adv = 0;
4116 remote_adv = 0;
4117
747e8f8b 4118 if (bmcr & BMCR_ANENABLE) {
ef167e27 4119 u32 common;
747e8f8b
MC		 4120
4121 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4122 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4123 common = local_adv & remote_adv;
4124 if (common & (ADVERTISE_1000XHALF |
4125 ADVERTISE_1000XFULL)) {
4126 if (common & ADVERTISE_1000XFULL)
4127 current_duplex = DUPLEX_FULL;
4128 else
4129 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4130 }
4131 else
4132 current_link_up = 0;
4133 }
4134 }
4135
ef167e27
MC		 4136 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4137 tg3_setup_flow_control(tp, local_adv, remote_adv);
4138
747e8f8b
MC		 4139 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4140 if (tp->link_config.active_duplex == DUPLEX_HALF)
4141 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4142
4143 tw32_f(MAC_MODE, tp->mac_mode);
4144 udelay(40);
4145
4146 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4147
4148 tp->link_config.active_speed = current_speed;
4149 tp->link_config.active_duplex = current_duplex;
4150
4151 if (current_link_up != netif_carrier_ok(tp->dev)) {
4152 if (current_link_up)
4153 netif_carrier_on(tp->dev);
4154 else {
4155 netif_carrier_off(tp->dev);
4156 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4157 }
4158 tg3_link_report(tp);
4159 }
4160 return err;
4161}
4162
4163static void tg3_serdes_parallel_detect(struct tg3 *tp)
4164{
3d3ebe74 4165 if (tp->serdes_counter) {
747e8f8b 4166 /* Give autoneg time to complete. */
3d3ebe74 4167 tp->serdes_counter--;
747e8f8b
MC		 4168 return;
4169 }
4170 if (!netif_carrier_ok(tp->dev) &&
4171 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4172 u32 bmcr;
4173
4174 tg3_readphy(tp, MII_BMCR, &bmcr);
4175 if (bmcr & BMCR_ANENABLE) {
4176 u32 phy1, phy2;
4177
4178 /* Select shadow register 0x1f */
4179 tg3_writephy(tp, 0x1c, 0x7c00);
4180 tg3_readphy(tp, 0x1c, &phy1);
4181
4182 /* Select expansion interrupt status register */
4183 tg3_writephy(tp, 0x17, 0x0f01);
4184 tg3_readphy(tp, 0x15, &phy2);
4185 tg3_readphy(tp, 0x15, &phy2);
4186
4187 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4188 /* We have signal detect and not receiving
4189 * config code words, link is up by parallel
4190 * detection.
4191 */
4192
4193 bmcr &= ~BMCR_ANENABLE;
4194 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4195 tg3_writephy(tp, MII_BMCR, bmcr);
4196 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4197 }
4198 }
4199 }
4200 else if (netif_carrier_ok(tp->dev) &&
4201 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4202 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4203 u32 phy2;
4204
4205 /* Select expansion interrupt status register */
4206 tg3_writephy(tp, 0x17, 0x0f01);
4207 tg3_readphy(tp, 0x15, &phy2);
4208 if (phy2 & 0x20) {
4209 u32 bmcr;
4210
4211 /* Config code words received, turn on autoneg. */
4212 tg3_readphy(tp, MII_BMCR, &bmcr);
4213 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4214
4215 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4216
4217 }
4218 }
4219}
4220
1da177e4
LT		 4221static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4222{
4223 int err;
4224
4225 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4226 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4227 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4228 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4229 } else {
4230 err = tg3_setup_copper_phy(tp, force_reset);
4231 }
4232
bcb37f6c 4233 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4234 u32 val, scale;
4235
4236 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4237 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4238 scale = 65;
4239 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4240 scale = 6;
4241 else
4242 scale = 12;
4243
4244 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4245 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4246 tw32(GRC_MISC_CFG, val);
4247 }
4248
1da177e4
LT		 4249 if (tp->link_config.active_speed == SPEED_1000 &&
4250 tp->link_config.active_duplex == DUPLEX_HALF)
4251 tw32(MAC_TX_LENGTHS,
4252 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4253 (6 << TX_LENGTHS_IPG_SHIFT) |
4254 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4255 else
4256 tw32(MAC_TX_LENGTHS,
4257 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4258 (6 << TX_LENGTHS_IPG_SHIFT) |
4259 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4260
4261 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4262 if (netif_carrier_ok(tp->dev)) {
4263 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4264 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4265 } else {
4266 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4267 }
4268 }
4269
8ed5d97e
MC		 4270 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4271 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4272 if (!netif_carrier_ok(tp->dev))
4273 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4274 tp->pwrmgmt_thresh;
4275 else
4276 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4277 tw32(PCIE_PWR_MGMT_THRESH, val);
4278 }
4279
1da177e4
LT		 4280 return err;
4281}
4282
df3e6548
MC		 4283/* This is called whenever we suspect that the system chipset is re-
4284 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4285 * is bogus tx completions. We try to recover by setting the
4286 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4287 * in the workqueue.
4288 */
4289static void tg3_tx_recover(struct tg3 *tp)
4290{
4291 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4292 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4293
4294 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4295 "mapped I/O cycles to the network device, attempting to "
4296 "recover. Please report the problem to the driver maintainer "
4297 "and include system chipset information.\n", tp->dev->name);
4298
4299 spin_lock(&tp->lock);
df3e6548 4300 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4301 spin_unlock(&tp->lock);
4302}
4303
f3f3f27e 4304static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4305{
4306 smp_mb();
f3f3f27e
MC		 4307 return tnapi->tx_pending -
4308 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4309}
4310
1da177e4
LT		 4311/* Tigon3 never reports partial packet sends. So we do not
4312 * need special logic to handle SKBs that have not had all
4313 * of their frags sent yet, like SunGEM does.
4314 */
17375d25 4315static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4316{
17375d25 4317 struct tg3 *tp = tnapi->tp;
898a56f8 4318 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4319 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4320 struct netdev_queue *txq;
4321 int index = tnapi - tp->napi;
4322
4323 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4324 index--;
4325
4326 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4327
4328 while (sw_idx != hw_idx) {
f3f3f27e 4329 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4330 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4331 int i, tx_bug = 0;
4332
4333 if (unlikely(skb == NULL)) {
4334 tg3_tx_recover(tp);
4335 return;
4336 }
1da177e4 4337
90079ce8 4338 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4339
4340 ri->skb = NULL;
4341
4342 sw_idx = NEXT_TX(sw_idx);
4343
4344 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4345 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4346 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4347 tx_bug = 1;
1da177e4
LT		 4348 sw_idx = NEXT_TX(sw_idx);
4349 }
4350
f47c11ee 4351 dev_kfree_skb(skb);
df3e6548
MC		 4352
4353 if (unlikely(tx_bug)) {
4354 tg3_tx_recover(tp);
4355 return;
4356 }
1da177e4
LT		 4357 }
4358
f3f3f27e 4359 tnapi->tx_cons = sw_idx;
1da177e4 4360
1b2a7205
MC		 4361 /* Need to make the tx_cons update visible to tg3_start_xmit()
4362 * before checking for netif_queue_stopped(). Without the
4363 * memory barrier, there is a small possibility that tg3_start_xmit()
4364 * will miss it and cause the queue to be stopped forever.
4365 */
4366 smp_mb();
4367
fe5f5787 4368 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4369 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4370 __netif_tx_lock(txq, smp_processor_id());
4371 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4372 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4373 netif_tx_wake_queue(txq);
4374 __netif_tx_unlock(txq);
51b91468 4375 }
1da177e4
LT		 4376}
4377
4378/* Returns size of skb allocated or < 0 on error.
4379 *
4380 * We only need to fill in the address because the other members
4381 * of the RX descriptor are invariant, see tg3_init_rings.
4382 *
4383 * Note the purposeful assymetry of cpu vs. chip accesses. For
4384 * posting buffers we only dirty the first cache line of the RX
4385 * descriptor (containing the address). Whereas for the RX status
4386 * buffers the cpu only reads the last cacheline of the RX descriptor
4387 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4388 */
17375d25 4389static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4390 int src_idx, u32 dest_idx_unmasked)
4391{
17375d25 4392 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4393 struct tg3_rx_buffer_desc *desc;
4394 struct ring_info *map, *src_map;
4395 struct sk_buff *skb;
4396 dma_addr_t mapping;
4397 int skb_size, dest_idx;
21f581a5 4398 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4399
4400 src_map = NULL;
4401 switch (opaque_key) {
4402 case RXD_OPAQUE_RING_STD:
4403 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4404 desc = &tpr->rx_std[dest_idx];
4405 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4406 if (src_idx >= 0)
21f581a5 4407 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4408 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4409 break;
4410
4411 case RXD_OPAQUE_RING_JUMBO:
4412 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4413 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4414 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4415 if (src_idx >= 0)
21f581a5 4416 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4417 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4418 break;
4419
4420 default:
4421 return -EINVAL;
855e1111 4422 }
1da177e4
LT		 4423
4424 /* Do not overwrite any of the map or rp information
4425 * until we are sure we can commit to a new buffer.
4426 *
4427 * Callers depend upon this behavior and assume that
4428 * we leave everything unchanged if we fail.
4429 */
287be12e 4430 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4431 if (skb == NULL)
4432 return -ENOMEM;
4433
1da177e4
LT		 4434 skb_reserve(skb, tp->rx_offset);
4435
287be12e 4436 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4437 PCI_DMA_FROMDEVICE);
4438
4439 map->skb = skb;
4440 pci_unmap_addr_set(map, mapping, mapping);
4441
4442 if (src_map != NULL)
4443 src_map->skb = NULL;
4444
4445 desc->addr_hi = ((u64)mapping >> 32);
4446 desc->addr_lo = ((u64)mapping & 0xffffffff);
4447
4448 return skb_size;
4449}
4450
4451/* We only need to move over in the address because the other
4452 * members of the RX descriptor are invariant. See notes above
4453 * tg3_alloc_rx_skb for full details.
4454 */
17375d25 4455static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4456 int src_idx, u32 dest_idx_unmasked)
4457{
17375d25 4458 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4459 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4460 struct ring_info *src_map, *dest_map;
4461 int dest_idx;
21f581a5 4462 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4463
4464 switch (opaque_key) {
4465 case RXD_OPAQUE_RING_STD:
4466 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4467 dest_desc = &tpr->rx_std[dest_idx];
4468 dest_map = &tpr->rx_std_buffers[dest_idx];
4469 src_desc = &tpr->rx_std[src_idx];
4470 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4471 break;
4472
4473 case RXD_OPAQUE_RING_JUMBO:
4474 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4475 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4476 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4477 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4478 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4479 break;
4480
4481 default:
4482 return;
855e1111 4483 }
1da177e4
LT		 4484
4485 dest_map->skb = src_map->skb;
4486 pci_unmap_addr_set(dest_map, mapping,
4487 pci_unmap_addr(src_map, mapping));
4488 dest_desc->addr_hi = src_desc->addr_hi;
4489 dest_desc->addr_lo = src_desc->addr_lo;
4490
4491 src_map->skb = NULL;
4492}
4493
1da177e4
LT		 4494/* The RX ring scheme is composed of multiple rings which post fresh
4495 * buffers to the chip, and one special ring the chip uses to report
4496 * status back to the host.
4497 *
4498 * The special ring reports the status of received packets to the
4499 * host. The chip does not write into the original descriptor the
4500 * RX buffer was obtained from. The chip simply takes the original
4501 * descriptor as provided by the host, updates the status and length
4502 * field, then writes this into the next status ring entry.
4503 *
4504 * Each ring the host uses to post buffers to the chip is described
4505 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4506 * it is first placed into the on-chip ram. When the packet's length
4507 * is known, it walks down the TG3_BDINFO entries to select the ring.
4508 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4509 * which is within the range of the new packet's length is chosen.
4510 *
4511 * The "separate ring for rx status" scheme may sound queer, but it makes
4512 * sense from a cache coherency perspective. If only the host writes
4513 * to the buffer post rings, and only the chip writes to the rx status
4514 * rings, then cache lines never move beyond shared-modified state.
4515 * If both the host and chip were to write into the same ring, cache line
4516 * eviction could occur since both entities want it in an exclusive state.
4517 */
17375d25 4518static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4519{
17375d25 4520 struct tg3 *tp = tnapi->tp;
f92905de 4521 u32 work_mask, rx_std_posted = 0;
72334482 4522 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4523 u16 hw_idx;
1da177e4 4524 int received;
21f581a5 4525 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4526
8d9d7cfc 4527 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4528 /*
4529 * We need to order the read of hw_idx and the read of
4530 * the opaque cookie.
4531 */
4532 rmb();
1da177e4
LT		 4533 work_mask = 0;
4534 received = 0;
4535 while (sw_idx != hw_idx && budget > 0) {
72334482 4536 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4537 unsigned int len;
4538 struct sk_buff *skb;
4539 dma_addr_t dma_addr;
4540 u32 opaque_key, desc_idx, *post_ptr;
4541
4542 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4543 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4544 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4545 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4546 dma_addr = pci_unmap_addr(ri, mapping);
4547 skb = ri->skb;
4548 post_ptr = &tpr->rx_std_ptr;
f92905de 4549 rx_std_posted++;
1da177e4 4550 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4551 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4552 dma_addr = pci_unmap_addr(ri, mapping);
4553 skb = ri->skb;
4554 post_ptr = &tpr->rx_jmb_ptr;
4555 } else
1da177e4 4556 goto next_pkt_nopost;
1da177e4
LT		 4557
4558 work_mask |= opaque_key;
4559
4560 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4561 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4562 drop_it:
17375d25 4563 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4564 desc_idx, *post_ptr);
4565 drop_it_no_recycle:
4566 /* Other statistics kept track of by card. */
4567 tp->net_stats.rx_dropped++;
4568 goto next_pkt;
4569 }
4570
ad829268
MC		 4571 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4572 ETH_FCS_LEN;
1da177e4 4573
6aa20a22 4574 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4575 && tp->rx_offset == NET_IP_ALIGN
4576 /* rx_offset will likely not equal NET_IP_ALIGN
4577 * if this is a 5701 card running in PCI-X mode
4578 * [see tg3_get_invariants()]
4579 */
1da177e4
LT		 4580 ) {
4581 int skb_size;
4582
17375d25 4583 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4584 desc_idx, *post_ptr);
4585 if (skb_size < 0)
4586 goto drop_it;
4587
287be12e 4588 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4589 PCI_DMA_FROMDEVICE);
4590
4591 skb_put(skb, len);
4592 } else {
4593 struct sk_buff *copy_skb;
4594
17375d25 4595 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4596 desc_idx, *post_ptr);
4597
ad829268
MC		 4598 copy_skb = netdev_alloc_skb(tp->dev,
4599 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4600 if (copy_skb == NULL)
4601 goto drop_it_no_recycle;
4602
ad829268 4603 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4604 skb_put(copy_skb, len);
4605 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4606 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4607 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4608
4609 /* We'll reuse the original ring buffer. */
4610 skb = copy_skb;
4611 }
4612
4613 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4614 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4615 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4616 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4617 skb->ip_summed = CHECKSUM_UNNECESSARY;
4618 else
4619 skb->ip_summed = CHECKSUM_NONE;
4620
4621 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4622
4623 if (len > (tp->dev->mtu + ETH_HLEN) &&
4624 skb->protocol != htons(ETH_P_8021Q)) {
4625 dev_kfree_skb(skb);
4626 goto next_pkt;
4627 }
4628
1da177e4
LT		 4629#if TG3_VLAN_TAG_USED
4630 if (tp->vlgrp != NULL &&
4631 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4632 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4633 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4634 } else
4635#endif
17375d25 4636 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4637
1da177e4
LT		 4638 received++;
4639 budget--;
4640
4641next_pkt:
4642 (*post_ptr)++;
f92905de
MC		 4643
4644 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4645 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4646
4647 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4648 TG3_64BIT_REG_LOW, idx);
4649 work_mask &= ~RXD_OPAQUE_RING_STD;
4650 rx_std_posted = 0;
4651 }
1da177e4 4652next_pkt_nopost:
483ba50b 4653 sw_idx++;
6b31a515 4654 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4655
4656 /* Refresh hw_idx to see if there is new work */
4657 if (sw_idx == hw_idx) {
8d9d7cfc 4658 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4659 rmb();
4660 }
1da177e4
LT		 4661 }
4662
4663 /* ACK the status ring. */
72334482
MC		 4664 tnapi->rx_rcb_ptr = sw_idx;
4665 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4666
4667 /* Refill RX ring(s). */
4668 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4669 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4670 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4671 sw_idx);
4672 }
4673 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4674 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4675 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4676 sw_idx);
4677 }
4678 mmiowb();
4679
4680 return received;
4681}
4682
17375d25 4683static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4684{
17375d25 4685 struct tg3 *tp = tnapi->tp;
898a56f8 4686 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4687
1da177e4
LT		 4688 /* handle link change and other phy events */
4689 if (!(tp->tg3_flags &
4690 (TG3_FLAG_USE_LINKCHG_REG |
4691 TG3_FLAG_POLL_SERDES))) {
4692 if (sblk->status & SD_STATUS_LINK_CHG) {
4693 sblk->status = SD_STATUS_UPDATED |
4694 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4695 spin_lock(&tp->lock);
dd477003
MC		 4696 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4697 tw32_f(MAC_STATUS,
4698 (MAC_STATUS_SYNC_CHANGED |
4699 MAC_STATUS_CFG_CHANGED |
4700 MAC_STATUS_MI_COMPLETION |
4701 MAC_STATUS_LNKSTATE_CHANGED));
4702 udelay(40);
4703 } else
4704 tg3_setup_phy(tp, 0);
f47c11ee 4705 spin_unlock(&tp->lock);
1da177e4
LT		 4706 }
4707 }
4708
4709 /* run TX completion thread */
f3f3f27e 4710 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4711 tg3_tx(tnapi);
6f535763 4712 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4713 return work_done;
1da177e4
LT		 4714 }
4715
1da177e4
LT		 4716 /* run RX thread, within the bounds set by NAPI.
4717 * All RX "locking" is done by ensuring outside
bea3348e 4718 * code synchronizes with tg3->napi.poll()
1da177e4 4719 */
8d9d7cfc 4720 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4721 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4722
6f535763
DM		 4723 return work_done;
4724}
4725
4726static int tg3_poll(struct napi_struct *napi, int budget)
4727{
8ef0442f
MC		 4728 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4729 struct tg3 *tp = tnapi->tp;
6f535763 4730 int work_done = 0;
898a56f8 4731 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4732
4733 while (1) {
17375d25 4734 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4735
4736 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4737 goto tx_recovery;
4738
4739 if (unlikely(work_done >= budget))
4740 break;
4741
4fd7ab59 4742 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4743 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4744 * to tell the hw how much work has been processed,
4745 * so we must read it before checking for more work.
4746 */
898a56f8
MC		 4747 tnapi->last_tag = sblk->status_tag;
4748 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4749 rmb();
4750 } else
4751 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4752
17375d25 4753 if (likely(!tg3_has_work(tnapi))) {
288379f0 4754 napi_complete(napi);
17375d25 4755 tg3_int_reenable(tnapi);
6f535763
DM		 4756 break;
4757 }
1da177e4
LT		 4758 }
4759
bea3348e 4760 return work_done;
6f535763
DM		 4761
4762tx_recovery:
4fd7ab59 4763 /* work_done is guaranteed to be less than budget. */
288379f0 4764 napi_complete(napi);
6f535763 4765 schedule_work(&tp->reset_task);
4fd7ab59 4766 return work_done;
1da177e4
LT		 4767}
4768
f47c11ee
DM		 4769static void tg3_irq_quiesce(struct tg3 *tp)
4770{
4f125f42
MC		 4771 int i;
4772
f47c11ee
DM		 4773 BUG_ON(tp->irq_sync);
4774
4775 tp->irq_sync = 1;
4776 smp_mb();
4777
4f125f42
MC		 4778 for (i = 0; i < tp->irq_cnt; i++)
4779 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4780}
4781
4782static inline int tg3_irq_sync(struct tg3 *tp)
4783{
4784 return tp->irq_sync;
4785}
4786
4787/* Fully shutdown all tg3 driver activity elsewhere in the system.
4788 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4789 * with as well. Most of the time, this is not necessary except when
4790 * shutting down the device.
4791 */
4792static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4793{
46966545 4794 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4795 if (irq_sync)
4796 tg3_irq_quiesce(tp);
f47c11ee
DM		 4797}
4798
4799static inline void tg3_full_unlock(struct tg3 *tp)
4800{
f47c11ee
DM		 4801 spin_unlock_bh(&tp->lock);
4802}
4803
fcfa0a32
MC		 4804/* One-shot MSI handler - Chip automatically disables interrupt
4805 * after sending MSI so driver doesn't have to do it.
4806 */
7d12e780 4807static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4808{
09943a18
MC		 4809 struct tg3_napi *tnapi = dev_id;
4810 struct tg3 *tp = tnapi->tp;
fcfa0a32 4811
898a56f8 4812 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4813 if (tnapi->rx_rcb)
4814 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4815
4816 if (likely(!tg3_irq_sync(tp)))
09943a18 4817 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4818
4819 return IRQ_HANDLED;
4820}
4821
88b06bc2
MC		 4822/* MSI ISR - No need to check for interrupt sharing and no need to
4823 * flush status block and interrupt mailbox. PCI ordering rules
4824 * guarantee that MSI will arrive after the status block.
4825 */
7d12e780 4826static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4827{
09943a18
MC		 4828 struct tg3_napi *tnapi = dev_id;
4829 struct tg3 *tp = tnapi->tp;
88b06bc2 4830
898a56f8 4831 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4832 if (tnapi->rx_rcb)
4833 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4834 /*
fac9b83e 4835 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4836 * chip-internal interrupt pending events.
fac9b83e 4837 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4838 * NIC to stop sending us irqs, engaging "in-intr-handler"
4839 * event coalescing.
4840 */
4841 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4842 if (likely(!tg3_irq_sync(tp)))
09943a18 4843 napi_schedule(&tnapi->napi);
61487480 4844
88b06bc2
MC		 4845 return IRQ_RETVAL(1);
4846}
4847
7d12e780 4848static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4849{
09943a18
MC		 4850 struct tg3_napi *tnapi = dev_id;
4851 struct tg3 *tp = tnapi->tp;
898a56f8 4852 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4853 unsigned int handled = 1;
4854
1da177e4
LT		 4855 /* In INTx mode, it is possible for the interrupt to arrive at
4856 * the CPU before the status block posted prior to the interrupt.
4857 * Reading the PCI State register will confirm whether the
4858 * interrupt is ours and will flush the status block.
4859 */
d18edcb2
MC		 4860 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4861 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4862 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4863 handled = 0;
f47c11ee 4864 goto out;
fac9b83e 4865 }
d18edcb2
MC		 4866 }
4867
4868 /*
4869 * Writing any value to intr-mbox-0 clears PCI INTA# and
4870 * chip-internal interrupt pending events.
4871 * Writing non-zero to intr-mbox-0 additional tells the
4872 * NIC to stop sending us irqs, engaging "in-intr-handler"
4873 * event coalescing.
c04cb347
MC		 4874 *
4875 * Flush the mailbox to de-assert the IRQ immediately to prevent
4876 * spurious interrupts. The flush impacts performance but
4877 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4878 */
c04cb347 4879 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4880 if (tg3_irq_sync(tp))
4881 goto out;
4882 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4883 if (likely(tg3_has_work(tnapi))) {
72334482 4884 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4885 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4886 } else {
4887 /* No work, shared interrupt perhaps? re-enable
4888 * interrupts, and flush that PCI write
4889 */
4890 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4891 0x00000000);
fac9b83e 4892 }
f47c11ee 4893out:
fac9b83e
DM		 4894 return IRQ_RETVAL(handled);
4895}
4896
7d12e780 4897static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4898{
09943a18
MC		 4899 struct tg3_napi *tnapi = dev_id;
4900 struct tg3 *tp = tnapi->tp;
898a56f8 4901 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4902 unsigned int handled = 1;
4903
fac9b83e
DM		 4904 /* In INTx mode, it is possible for the interrupt to arrive at
4905 * the CPU before the status block posted prior to the interrupt.
4906 * Reading the PCI State register will confirm whether the
4907 * interrupt is ours and will flush the status block.
4908 */
898a56f8 4909 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4910 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4911 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4912 handled = 0;
f47c11ee 4913 goto out;
1da177e4 4914 }
d18edcb2
MC		 4915 }
4916
4917 /*
4918 * writing any value to intr-mbox-0 clears PCI INTA# and
4919 * chip-internal interrupt pending events.
4920 * writing non-zero to intr-mbox-0 additional tells the
4921 * NIC to stop sending us irqs, engaging "in-intr-handler"
4922 * event coalescing.
c04cb347
MC		 4923 *
4924 * Flush the mailbox to de-assert the IRQ immediately to prevent
4925 * spurious interrupts. The flush impacts performance but
4926 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4927 */
c04cb347 4928 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4929
4930 /*
4931 * In a shared interrupt configuration, sometimes other devices'
4932 * interrupts will scream. We record the current status tag here
4933 * so that the above check can report that the screaming interrupts
4934 * are unhandled. Eventually they will be silenced.
4935 */
898a56f8 4936 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4937
d18edcb2
MC		 4938 if (tg3_irq_sync(tp))
4939 goto out;
624f8e50 4940
72334482 4941 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4942
09943a18 4943 napi_schedule(&tnapi->napi);
624f8e50 4944
f47c11ee 4945out:
1da177e4
LT		 4946 return IRQ_RETVAL(handled);
4947}
4948
7938109f 4949/* ISR for interrupt test */
7d12e780 4950static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4951{
09943a18
MC		 4952 struct tg3_napi *tnapi = dev_id;
4953 struct tg3 *tp = tnapi->tp;
898a56f8 4954 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4955
f9804ddb
MC		 4956 if ((sblk->status & SD_STATUS_UPDATED) ||
4957 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4958 tg3_disable_ints(tp);
7938109f
MC		 4959 return IRQ_RETVAL(1);
4960 }
4961 return IRQ_RETVAL(0);
4962}
4963
8e7a22e3 4964static int tg3_init_hw(struct tg3 *, int);
944d980e 4965static int tg3_halt(struct tg3 *, int, int);
1da177e4 4966
b9ec6c1b
MC		 4967/* Restart hardware after configuration changes, self-test, etc.
4968 * Invoked with tp->lock held.
4969 */
4970static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4971 __releases(tp->lock)
4972 __acquires(tp->lock)
b9ec6c1b
MC		 4973{
4974 int err;
4975
4976 err = tg3_init_hw(tp, reset_phy);
4977 if (err) {
4978 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4979 "aborting.\n", tp->dev->name);
4980 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4981 tg3_full_unlock(tp);
4982 del_timer_sync(&tp->timer);
4983 tp->irq_sync = 0;
fed97810 4984 tg3_napi_enable(tp);
b9ec6c1b
MC		 4985 dev_close(tp->dev);
4986 tg3_full_lock(tp, 0);
4987 }
4988 return err;
4989}
4990
1da177e4
LT		 4991#ifdef CONFIG_NET_POLL_CONTROLLER
4992static void tg3_poll_controller(struct net_device *dev)
4993{
4f125f42 4994 int i;
88b06bc2
MC		 4995 struct tg3 *tp = netdev_priv(dev);
4996
4f125f42
MC		 4997 for (i = 0; i < tp->irq_cnt; i++)
4998 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 4999}
5000#endif
5001
c4028958 5002static void tg3_reset_task(struct work_struct *work)
1da177e4 5003{
c4028958 5004 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5005 int err;
1da177e4
LT		 5006 unsigned int restart_timer;
5007
7faa006f 5008 tg3_full_lock(tp, 0);
7faa006f
MC		 5009
5010 if (!netif_running(tp->dev)) {
7faa006f
MC		 5011 tg3_full_unlock(tp);
5012 return;
5013 }
5014
5015 tg3_full_unlock(tp);
5016
b02fd9e3
MC		 5017 tg3_phy_stop(tp);
5018
1da177e4
LT		 5019 tg3_netif_stop(tp);
5020
f47c11ee 5021 tg3_full_lock(tp, 1);
1da177e4
LT		 5022
5023 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5024 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5025
df3e6548
MC		 5026 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5027 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5028 tp->write32_rx_mbox = tg3_write_flush_reg32;
5029 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5030 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5031 }
5032
944d980e 5033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5034 err = tg3_init_hw(tp, 1);
5035 if (err)
b9ec6c1b 5036 goto out;
1da177e4
LT		 5037
5038 tg3_netif_start(tp);
5039
1da177e4
LT		 5040 if (restart_timer)
5041 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5042
b9ec6c1b 5043out:
7faa006f 5044 tg3_full_unlock(tp);
b02fd9e3
MC		 5045
5046 if (!err)
5047 tg3_phy_start(tp);
1da177e4
LT		 5048}
5049
b0408751
MC		 5050static void tg3_dump_short_state(struct tg3 *tp)
5051{
5052 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5053 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5054 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5055 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5056}
5057
1da177e4
LT		 5058static void tg3_tx_timeout(struct net_device *dev)
5059{
5060 struct tg3 *tp = netdev_priv(dev);
5061
b0408751 5062 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5063 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5064 dev->name);
b0408751
MC		 5065 tg3_dump_short_state(tp);
5066 }
1da177e4
LT		 5067
5068 schedule_work(&tp->reset_task);
5069}
5070
c58ec932
MC		 5071/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5072static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5073{
5074 u32 base = (u32) mapping & 0xffffffff;
5075
5076 return ((base > 0xffffdcc0) &&
5077 (base + len + 8 < base));
5078}
5079
72f2afb8
MC		 5080/* Test for DMA addresses > 40-bit */
5081static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5082 int len)
5083{
5084#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5085 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5086 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5087 return 0;
5088#else
5089 return 0;
5090#endif
5091}
5092
f3f3f27e 5093static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5094
72f2afb8
MC		 5095/* Workaround 4GB and 40-bit hardware DMA bugs. */
5096static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5097 u32 last_plus_one, u32 *start,
5098 u32 base_flags, u32 mss)
1da177e4 5099{
f3f3f27e 5100 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5101 struct sk_buff *new_skb;
c58ec932 5102 dma_addr_t new_addr = 0;
1da177e4 5103 u32 entry = *start;
c58ec932 5104 int i, ret = 0;
1da177e4 5105
41588ba1
MC		 5106 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5107 new_skb = skb_copy(skb, GFP_ATOMIC);
5108 else {
5109 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5110
5111 new_skb = skb_copy_expand(skb,
5112 skb_headroom(skb) + more_headroom,
5113 skb_tailroom(skb), GFP_ATOMIC);
5114 }
5115
1da177e4 5116 if (!new_skb) {
c58ec932
MC		 5117 ret = -1;
5118 } else {
5119 /* New SKB is guaranteed to be linear. */
5120 entry = *start;
90079ce8 5121 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5122 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5123
c58ec932
MC		 5124 /* Make sure new skb does not cross any 4G boundaries.
5125 * Drop the packet if it does.
5126 */
0e1406dd
MC		 5127 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5128 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5129 if (!ret)
5130 skb_dma_unmap(&tp->pdev->dev, new_skb,
5131 DMA_TO_DEVICE);
c58ec932
MC		 5132 ret = -1;
5133 dev_kfree_skb(new_skb);
5134 new_skb = NULL;
5135 } else {
f3f3f27e 5136 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5137 base_flags, 1 | (mss << 1));
5138 *start = NEXT_TX(entry);
5139 }
1da177e4
LT		 5140 }
5141
1da177e4
LT		 5142 /* Now clean up the sw ring entries. */
5143 i = 0;
5144 while (entry != last_plus_one) {
f3f3f27e
MC		 5145 if (i == 0)
5146 tnapi->tx_buffers[entry].skb = new_skb;
5147 else
5148 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5149 entry = NEXT_TX(entry);
5150 i++;
5151 }
5152
90079ce8 5153 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5154 dev_kfree_skb(skb);
5155
c58ec932 5156 return ret;
1da177e4
LT		 5157}
5158
f3f3f27e 5159static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5160 dma_addr_t mapping, int len, u32 flags,
5161 u32 mss_and_is_end)
5162{
f3f3f27e 5163 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5164 int is_end = (mss_and_is_end & 0x1);
5165 u32 mss = (mss_and_is_end >> 1);
5166 u32 vlan_tag = 0;
5167
5168 if (is_end)
5169 flags |= TXD_FLAG_END;
5170 if (flags & TXD_FLAG_VLAN) {
5171 vlan_tag = flags >> 16;
5172 flags &= 0xffff;
5173 }
5174 vlan_tag |= (mss << TXD_MSS_SHIFT);
5175
5176 txd->addr_hi = ((u64) mapping >> 32);
5177 txd->addr_lo = ((u64) mapping & 0xffffffff);
5178 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5179 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5180}
5181
5a6f3074
MC		 5182/* hard_start_xmit for devices that don't have any bugs and
5183 * support TG3_FLG2_HW_TSO_2 only.
5184 */
61357325
SH		 5185static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5186 struct net_device *dev)
5a6f3074
MC		 5187{
5188 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5189 u32 len, entry, base_flags, mss;
90079ce8
DM		 5190 struct skb_shared_info *sp;
5191 dma_addr_t mapping;
fe5f5787
MC		 5192 struct tg3_napi *tnapi;
5193 struct netdev_queue *txq;
5a6f3074 5194
fe5f5787
MC		 5195 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5196 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5197 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5198 tnapi++;
5a6f3074 5199
00b70504 5200 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5201 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5202 * interrupt. Furthermore, IRQ processing runs lockless so we have
5203 * no IRQ context deadlocks to worry about either. Rejoice!
5204 */
f3f3f27e 5205 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5206 if (!netif_tx_queue_stopped(txq)) {
5207 netif_tx_stop_queue(txq);
5a6f3074
MC		 5208
5209 /* This is a hard error, log it. */
5210 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5211 "queue awake!\n", dev->name);
5212 }
5a6f3074
MC		 5213 return NETDEV_TX_BUSY;
5214 }
5215
f3f3f27e 5216 entry = tnapi->tx_prod;
5a6f3074 5217 base_flags = 0;
5a6f3074 5218 mss = 0;
c13e3713 5219 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5220 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5221 u32 hdrlen;
5a6f3074
MC		 5222
5223 if (skb_header_cloned(skb) &&
5224 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5225 dev_kfree_skb(skb);
5226 goto out_unlock;
5227 }
5228
b0026624 5229 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5230 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5231 else {
eddc9ec5
ACM		 5232 struct iphdr *iph = ip_hdr(skb);
5233
ab6a5bb6 5234 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5235 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5236
eddc9ec5
ACM		 5237 iph->check = 0;
5238 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5239 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5240 }
5a6f3074 5241
f6eb9b1f
MC		 5242 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5243 mss |= (hdrlen & 0xc) << 12;
5244 if (hdrlen & 0x10)
5245 base_flags |= 0x00000010;
5246 base_flags |= (hdrlen & 0x3e0) << 5;
5247 } else
5248 mss |= hdrlen << 9;
5249
5a6f3074
MC		 5250 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5251 TXD_FLAG_CPU_POST_DMA);
5252
aa8223c7 5253 tcp_hdr(skb)->check = 0;
5a6f3074 5254
5a6f3074 5255 }
84fa7933 5256 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5257 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5258#if TG3_VLAN_TAG_USED
5259 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5260 base_flags |= (TXD_FLAG_VLAN |
5261 (vlan_tx_tag_get(skb) << 16));
5262#endif
5263
90079ce8
DM		 5264 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5265 dev_kfree_skb(skb);
5266 goto out_unlock;
5267 }
5268
5269 sp = skb_shinfo(skb);
5270
042a53a9 5271 mapping = sp->dma_head;
5a6f3074 5272
f3f3f27e 5273 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5274
fe5f5787
MC		 5275 len = skb_headlen(skb);
5276
f6eb9b1f
MC		 5277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5278 !mss && skb->len > ETH_DATA_LEN)
5279 base_flags |= TXD_FLAG_JMB_PKT;
5280
f3f3f27e 5281 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5282 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5283
5284 entry = NEXT_TX(entry);
5285
5286 /* Now loop through additional data fragments, and queue them. */
5287 if (skb_shinfo(skb)->nr_frags > 0) {
5288 unsigned int i, last;
5289
5290 last = skb_shinfo(skb)->nr_frags - 1;
5291 for (i = 0; i <= last; i++) {
5292 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5293
5294 len = frag->size;
042a53a9 5295 mapping = sp->dma_maps[i];
f3f3f27e 5296 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5297
f3f3f27e 5298 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5299 base_flags, (i == last) | (mss << 1));
5300
5301 entry = NEXT_TX(entry);
5302 }
5303 }
5304
5305 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5306 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5307
f3f3f27e
MC		 5308 tnapi->tx_prod = entry;
5309 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5310 netif_tx_stop_queue(txq);
f3f3f27e 5311 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5312 netif_tx_wake_queue(txq);
5a6f3074
MC		 5313 }
5314
5315out_unlock:
cdd0db05 5316 mmiowb();
5a6f3074
MC		 5317
5318 return NETDEV_TX_OK;
5319}
5320
61357325
SH		 5321static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5322 struct net_device *);
52c0fd83
MC		 5323
5324/* Use GSO to workaround a rare TSO bug that may be triggered when the
5325 * TSO header is greater than 80 bytes.
5326 */
5327static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5328{
5329 struct sk_buff *segs, *nskb;
f3f3f27e 5330 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5331
5332 /* Estimate the number of fragments in the worst case */
f3f3f27e 5333 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5334 netif_stop_queue(tp->dev);
f3f3f27e 5335 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5336 return NETDEV_TX_BUSY;
5337
5338 netif_wake_queue(tp->dev);
52c0fd83
MC		 5339 }
5340
5341 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5342 if (IS_ERR(segs))
52c0fd83
MC		 5343 goto tg3_tso_bug_end;
5344
5345 do {
5346 nskb = segs;
5347 segs = segs->next;
5348 nskb->next = NULL;
5349 tg3_start_xmit_dma_bug(nskb, tp->dev);
5350 } while (segs);
5351
5352tg3_tso_bug_end:
5353 dev_kfree_skb(skb);
5354
5355 return NETDEV_TX_OK;
5356}
52c0fd83 5357
5a6f3074
MC		 5358/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5359 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5360 */
61357325
SH		 5361static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5362 struct net_device *dev)
1da177e4
LT		 5363{
5364 struct tg3 *tp = netdev_priv(dev);
1da177e4 5365 u32 len, entry, base_flags, mss;
90079ce8 5366 struct skb_shared_info *sp;
1da177e4 5367 int would_hit_hwbug;
90079ce8 5368 dma_addr_t mapping;
f3f3f27e 5369 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5370
5371 len = skb_headlen(skb);
5372
00b70504 5373 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5374 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5375 * interrupt. Furthermore, IRQ processing runs lockless so we have
5376 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5377 */
f3f3f27e 5378 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5379 if (!netif_queue_stopped(dev)) {
5380 netif_stop_queue(dev);
5381
5382 /* This is a hard error, log it. */
5383 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5384 "queue awake!\n", dev->name);
5385 }
1da177e4
LT		 5386 return NETDEV_TX_BUSY;
5387 }
5388
f3f3f27e 5389 entry = tnapi->tx_prod;
1da177e4 5390 base_flags = 0;
84fa7933 5391 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5392 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5393 mss = 0;
c13e3713 5394 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5395 struct iphdr *iph;
92c6b8d1 5396 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5397
5398 if (skb_header_cloned(skb) &&
5399 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5400 dev_kfree_skb(skb);
5401 goto out_unlock;
5402 }
5403
ab6a5bb6 5404 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5405 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5406
52c0fd83
MC		 5407 hdr_len = ip_tcp_len + tcp_opt_len;
5408 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5409 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5410 return (tg3_tso_bug(tp, skb));
5411
1da177e4
LT		 5412 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5413 TXD_FLAG_CPU_POST_DMA);
5414
eddc9ec5
ACM		 5415 iph = ip_hdr(skb);
5416 iph->check = 0;
5417 iph->tot_len = htons(mss + hdr_len);
1da177e4 5418 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5419 tcp_hdr(skb)->check = 0;
1da177e4 5420 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5421 } else
5422 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5423 iph->daddr, 0,
5424 IPPROTO_TCP,
5425 0);
1da177e4 5426
92c6b8d1
MC		 5427 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5428 mss |= hdr_len << 9;
5429 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5431 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5432 int tsflags;
5433
eddc9ec5 5434 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5435 mss |= (tsflags << 11);
5436 }
5437 } else {
eddc9ec5 5438 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5439 int tsflags;
5440
eddc9ec5 5441 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5442 base_flags |= tsflags << 12;
5443 }
5444 }
5445 }
1da177e4
LT		 5446#if TG3_VLAN_TAG_USED
5447 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5448 base_flags |= (TXD_FLAG_VLAN |
5449 (vlan_tx_tag_get(skb) << 16));
5450#endif
5451
90079ce8
DM		 5452 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5453 dev_kfree_skb(skb);
5454 goto out_unlock;
5455 }
5456
5457 sp = skb_shinfo(skb);
5458
042a53a9 5459 mapping = sp->dma_head;
1da177e4 5460
f3f3f27e 5461 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5462
5463 would_hit_hwbug = 0;
5464
92c6b8d1
MC		 5465 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5466 would_hit_hwbug = 1;
5467
0e1406dd
MC		 5468 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5469 tg3_4g_overflow_test(mapping, len))
5470 would_hit_hwbug = 1;
5471
5472 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5473 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5474 would_hit_hwbug = 1;
0e1406dd
MC		 5475
5476 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5477 would_hit_hwbug = 1;
1da177e4 5478
f3f3f27e 5479 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5480 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5481
5482 entry = NEXT_TX(entry);
5483
5484 /* Now loop through additional data fragments, and queue them. */
5485 if (skb_shinfo(skb)->nr_frags > 0) {
5486 unsigned int i, last;
5487
5488 last = skb_shinfo(skb)->nr_frags - 1;
5489 for (i = 0; i <= last; i++) {
5490 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5491
5492 len = frag->size;
042a53a9 5493 mapping = sp->dma_maps[i];
1da177e4 5494
f3f3f27e 5495 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5496
92c6b8d1
MC		 5497 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5498 len <= 8)
5499 would_hit_hwbug = 1;
5500
0e1406dd
MC		 5501 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5502 tg3_4g_overflow_test(mapping, len))
c58ec932 5503 would_hit_hwbug = 1;
1da177e4 5504
0e1406dd
MC		 5505 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5506 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5507 would_hit_hwbug = 1;
5508
1da177e4 5509 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5510 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5511 base_flags, (i == last)|(mss << 1));
5512 else
f3f3f27e 5513 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5514 base_flags, (i == last));
5515
5516 entry = NEXT_TX(entry);
5517 }
5518 }
5519
5520 if (would_hit_hwbug) {
5521 u32 last_plus_one = entry;
5522 u32 start;
1da177e4 5523
c58ec932
MC		 5524 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5525 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5526
5527 /* If the workaround fails due to memory/mapping
5528 * failure, silently drop this packet.
5529 */
72f2afb8 5530 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5531 &start, base_flags, mss))
1da177e4
LT		 5532 goto out_unlock;
5533
5534 entry = start;
5535 }
5536
5537 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5538 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5539
f3f3f27e
MC		 5540 tnapi->tx_prod = entry;
5541 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5542 netif_stop_queue(dev);
f3f3f27e 5543 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5544 netif_wake_queue(tp->dev);
5545 }
1da177e4
LT		 5546
5547out_unlock:
cdd0db05 5548 mmiowb();
1da177e4
LT		 5549
5550 return NETDEV_TX_OK;
5551}
5552
5553static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5554 int new_mtu)
5555{
5556 dev->mtu = new_mtu;
5557
ef7f5ec0 5558 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5559 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5560 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5561 ethtool_op_set_tso(dev, 0);
5562 }
5563 else
5564 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5565 } else {
a4e2b347 5566 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5567 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5568 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5569 }
1da177e4
LT		 5570}
5571
5572static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5573{
5574 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5575 int err;
1da177e4
LT		 5576
5577 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5578 return -EINVAL;
5579
5580 if (!netif_running(dev)) {
5581 /* We'll just catch it later when the
5582 * device is up'd.
5583 */
5584 tg3_set_mtu(dev, tp, new_mtu);
5585 return 0;
5586 }
5587
b02fd9e3
MC		 5588 tg3_phy_stop(tp);
5589
1da177e4 5590 tg3_netif_stop(tp);
f47c11ee
DM		 5591
5592 tg3_full_lock(tp, 1);
1da177e4 5593
944d980e 5594 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5595
5596 tg3_set_mtu(dev, tp, new_mtu);
5597
b9ec6c1b 5598 err = tg3_restart_hw(tp, 0);
1da177e4 5599
b9ec6c1b
MC		 5600 if (!err)
5601 tg3_netif_start(tp);
1da177e4 5602
f47c11ee 5603 tg3_full_unlock(tp);
1da177e4 5604
b02fd9e3
MC		 5605 if (!err)
5606 tg3_phy_start(tp);
5607
b9ec6c1b 5608 return err;
1da177e4
LT		 5609}
5610
21f581a5
MC		 5611static void tg3_rx_prodring_free(struct tg3 *tp,
5612 struct tg3_rx_prodring_set *tpr)
1da177e4 5613{
1da177e4 5614 int i;
f3f3f27e 5615 struct ring_info *rxp;
1da177e4
LT		 5616
5617 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5618 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5619
5620 if (rxp->skb == NULL)
5621 continue;
1da177e4 5622
1da177e4
LT		 5623 pci_unmap_single(tp->pdev,
5624 pci_unmap_addr(rxp, mapping),
cf7a7298 5625 tp->rx_pkt_map_sz,
1da177e4
LT		 5626 PCI_DMA_FROMDEVICE);
5627 dev_kfree_skb_any(rxp->skb);
5628 rxp->skb = NULL;
5629 }
5630
cf7a7298
MC		 5631 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5632 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5633 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5634
cf7a7298
MC		 5635 if (rxp->skb == NULL)
5636 continue;
1da177e4 5637
cf7a7298
MC		 5638 pci_unmap_single(tp->pdev,
5639 pci_unmap_addr(rxp, mapping),
5640 TG3_RX_JMB_MAP_SZ,
5641 PCI_DMA_FROMDEVICE);
5642 dev_kfree_skb_any(rxp->skb);
5643 rxp->skb = NULL;
1da177e4 5644 }
1da177e4
LT		 5645 }
5646}
5647
5648/* Initialize tx/rx rings for packet processing.
5649 *
5650 * The chip has been shut down and the driver detached from
5651 * the networking, so no interrupts or new tx packets will
5652 * end up in the driver. tp->{tx,}lock are held and thus
5653 * we may not sleep.
5654 */
21f581a5
MC		 5655static int tg3_rx_prodring_alloc(struct tg3 *tp,
5656 struct tg3_rx_prodring_set *tpr)
1da177e4 5657{
287be12e 5658 u32 i, rx_pkt_dma_sz;
17375d25 5659 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5660
1da177e4 5661 /* Zero out all descriptors. */
21f581a5 5662 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5663
287be12e 5664 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5665 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5666 tp->dev->mtu > ETH_DATA_LEN)
5667 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5668 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5669
1da177e4
LT		 5670 /* Initialize invariants of the rings, we only set this
5671 * stuff once. This works because the card does not
5672 * write into the rx buffer posting rings.
5673 */
5674 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5675 struct tg3_rx_buffer_desc *rxd;
5676
21f581a5 5677 rxd = &tpr->rx_std[i];
287be12e 5678 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5679 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5680 rxd->opaque = (RXD_OPAQUE_RING_STD |
5681 (i << RXD_OPAQUE_INDEX_SHIFT));
5682 }
5683
1da177e4
LT		 5684 /* Now allocate fresh SKBs for each rx ring. */
5685 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5686 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5687 printk(KERN_WARNING PFX
5688 "%s: Using a smaller RX standard ring, "
5689 "only %d out of %d buffers were allocated "
5690 "successfully.\n",
5691 tp->dev->name, i, tp->rx_pending);
5692 if (i == 0)
cf7a7298 5693 goto initfail;
32d8c572 5694 tp->rx_pending = i;
1da177e4 5695 break;
32d8c572 5696 }
1da177e4
LT		 5697 }
5698
cf7a7298
MC		 5699 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5700 goto done;
5701
21f581a5 5702 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5703
0f893dc6 5704 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5705 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5706 struct tg3_rx_buffer_desc *rxd;
5707
79ed5ac7 5708 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5709 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5710 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5711 RXD_FLAG_JUMBO;
5712 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5713 (i << RXD_OPAQUE_INDEX_SHIFT));
5714 }
5715
1da177e4 5716 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5717 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5718 -1, i) < 0) {
5719 printk(KERN_WARNING PFX
5720 "%s: Using a smaller RX jumbo ring, "
5721 "only %d out of %d buffers were "
5722 "allocated successfully.\n",
5723 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5724 if (i == 0)
5725 goto initfail;
32d8c572 5726 tp->rx_jumbo_pending = i;
1da177e4 5727 break;
32d8c572 5728 }
1da177e4
LT		 5729 }
5730 }
cf7a7298
MC		 5731
5732done:
32d8c572 5733 return 0;
cf7a7298
MC		 5734
5735initfail:
21f581a5 5736 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5737 return -ENOMEM;
1da177e4
LT		 5738}
5739
21f581a5
MC		 5740static void tg3_rx_prodring_fini(struct tg3 *tp,
5741 struct tg3_rx_prodring_set *tpr)
1da177e4 5742{
21f581a5
MC		 5743 kfree(tpr->rx_std_buffers);
5744 tpr->rx_std_buffers = NULL;
5745 kfree(tpr->rx_jmb_buffers);
5746 tpr->rx_jmb_buffers = NULL;
5747 if (tpr->rx_std) {
1da177e4 5748 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5749 tpr->rx_std, tpr->rx_std_mapping);
5750 tpr->rx_std = NULL;
1da177e4 5751 }
21f581a5 5752 if (tpr->rx_jmb) {
1da177e4 5753 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5754 tpr->rx_jmb, tpr->rx_jmb_mapping);
5755 tpr->rx_jmb = NULL;
1da177e4 5756 }
cf7a7298
MC		 5757}
5758
21f581a5
MC		 5759static int tg3_rx_prodring_init(struct tg3 *tp,
5760 struct tg3_rx_prodring_set *tpr)
cf7a7298 5761{
21f581a5
MC		 5762 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5763 TG3_RX_RING_SIZE, GFP_KERNEL);
5764 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5765 return -ENOMEM;
5766
21f581a5
MC		 5767 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5768 &tpr->rx_std_mapping);
5769 if (!tpr->rx_std)
cf7a7298
MC		 5770 goto err_out;
5771
5772 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5773 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5774 TG3_RX_JUMBO_RING_SIZE,
5775 GFP_KERNEL);
5776 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5777 goto err_out;
5778
21f581a5
MC		 5779 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5780 TG3_RX_JUMBO_RING_BYTES,
5781 &tpr->rx_jmb_mapping);
5782 if (!tpr->rx_jmb)
cf7a7298
MC		 5783 goto err_out;
5784 }
5785
5786 return 0;
5787
5788err_out:
21f581a5 5789 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5790 return -ENOMEM;
5791}
5792
5793/* Free up pending packets in all rx/tx rings.
5794 *
5795 * The chip has been shut down and the driver detached from
5796 * the networking, so no interrupts or new tx packets will
5797 * end up in the driver. tp->{tx,}lock is not held and we are not
5798 * in an interrupt context and thus may sleep.
5799 */
5800static void tg3_free_rings(struct tg3 *tp)
5801{
f77a6a8e 5802 int i, j;
cf7a7298 5803
f77a6a8e
MC		 5804 for (j = 0; j < tp->irq_cnt; j++) {
5805 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5806
0c1d0e2b
MC		 5807 if (!tnapi->tx_buffers)
5808 continue;
5809
f77a6a8e
MC		 5810 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5811 struct tx_ring_info *txp;
5812 struct sk_buff *skb;
cf7a7298 5813
f77a6a8e
MC		 5814 txp = &tnapi->tx_buffers[i];
5815 skb = txp->skb;
cf7a7298 5816
f77a6a8e
MC		 5817 if (skb == NULL) {
5818 i++;
5819 continue;
5820 }
cf7a7298 5821
f77a6a8e 5822 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5823
f77a6a8e 5824 txp->skb = NULL;
cf7a7298 5825
f77a6a8e
MC		 5826 i += skb_shinfo(skb)->nr_frags + 1;
5827
5828 dev_kfree_skb_any(skb);
5829 }
cf7a7298
MC		 5830 }
5831
21f581a5 5832 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5833}
5834
5835/* Initialize tx/rx rings for packet processing.
5836 *
5837 * The chip has been shut down and the driver detached from
5838 * the networking, so no interrupts or new tx packets will
5839 * end up in the driver. tp->{tx,}lock are held and thus
5840 * we may not sleep.
5841 */
5842static int tg3_init_rings(struct tg3 *tp)
5843{
f77a6a8e 5844 int i;
72334482 5845
cf7a7298
MC		 5846 /* Free up all the SKBs. */
5847 tg3_free_rings(tp);
5848
f77a6a8e
MC		 5849 for (i = 0; i < tp->irq_cnt; i++) {
5850 struct tg3_napi *tnapi = &tp->napi[i];
5851
5852 tnapi->last_tag = 0;
5853 tnapi->last_irq_tag = 0;
5854 tnapi->hw_status->status = 0;
5855 tnapi->hw_status->status_tag = 0;
5856 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5857
f77a6a8e
MC		 5858 tnapi->tx_prod = 0;
5859 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5860 if (tnapi->tx_ring)
5861 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5862
5863 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5864 if (tnapi->rx_rcb)
5865 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5866 }
72334482 5867
21f581a5 5868 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5869}
5870
5871/*
5872 * Must not be invoked with interrupt sources disabled and
5873 * the hardware shutdown down.
5874 */
5875static void tg3_free_consistent(struct tg3 *tp)
5876{
f77a6a8e 5877 int i;
898a56f8 5878
f77a6a8e
MC		 5879 for (i = 0; i < tp->irq_cnt; i++) {
5880 struct tg3_napi *tnapi = &tp->napi[i];
5881
5882 if (tnapi->tx_ring) {
5883 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5884 tnapi->tx_ring, tnapi->tx_desc_mapping);
5885 tnapi->tx_ring = NULL;
5886 }
5887
5888 kfree(tnapi->tx_buffers);
5889 tnapi->tx_buffers = NULL;
5890
5891 if (tnapi->rx_rcb) {
5892 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5893 tnapi->rx_rcb,
5894 tnapi->rx_rcb_mapping);
5895 tnapi->rx_rcb = NULL;
5896 }
5897
5898 if (tnapi->hw_status) {
5899 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5900 tnapi->hw_status,
5901 tnapi->status_mapping);
5902 tnapi->hw_status = NULL;
5903 }
1da177e4 5904 }
f77a6a8e 5905
1da177e4
LT		 5906 if (tp->hw_stats) {
5907 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5908 tp->hw_stats, tp->stats_mapping);
5909 tp->hw_stats = NULL;
5910 }
f77a6a8e 5911
21f581a5 5912 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5913}
5914
5915/*
5916 * Must not be invoked with interrupt sources disabled and
5917 * the hardware shutdown down. Can sleep.
5918 */
5919static int tg3_alloc_consistent(struct tg3 *tp)
5920{
f77a6a8e 5921 int i;
898a56f8 5922
21f581a5 5923 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5924 return -ENOMEM;
5925
f77a6a8e
MC		 5926 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5927 sizeof(struct tg3_hw_stats),
5928 &tp->stats_mapping);
5929 if (!tp->hw_stats)
1da177e4
LT		 5930 goto err_out;
5931
f77a6a8e 5932 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 5933
f77a6a8e
MC		 5934 for (i = 0; i < tp->irq_cnt; i++) {
5935 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 5936 struct tg3_hw_status *sblk;
1da177e4 5937
f77a6a8e
MC		 5938 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5939 TG3_HW_STATUS_SIZE,
5940 &tnapi->status_mapping);
5941 if (!tnapi->hw_status)
5942 goto err_out;
898a56f8 5943
f77a6a8e 5944 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 5945 sblk = tnapi->hw_status;
5946
5947 /*
5948 * When RSS is enabled, the status block format changes
5949 * slightly. The "rx_jumbo_consumer", "reserved",
5950 * and "rx_mini_consumer" members get mapped to the
5951 * other three rx return ring producer indexes.
5952 */
5953 switch (i) {
5954 default:
5955 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5956 break;
5957 case 2:
5958 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5959 break;
5960 case 3:
5961 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5962 break;
5963 case 4:
5964 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5965 break;
5966 }
72334482 5967
0c1d0e2b
MC		 5968 /*
5969 * If multivector RSS is enabled, vector 0 does not handle
5970 * rx or tx interrupts. Don't allocate any resources for it.
5971 */
5972 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5973 continue;
5974
f77a6a8e
MC		 5975 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5976 TG3_RX_RCB_RING_BYTES(tp),
5977 &tnapi->rx_rcb_mapping);
5978 if (!tnapi->rx_rcb)
5979 goto err_out;
72334482 5980
f77a6a8e 5981 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 5982
f77a6a8e
MC		 5983 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5984 TG3_TX_RING_SIZE, GFP_KERNEL);
5985 if (!tnapi->tx_buffers)
5986 goto err_out;
5987
5988 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5989 TG3_TX_RING_BYTES,
5990 &tnapi->tx_desc_mapping);
5991 if (!tnapi->tx_ring)
5992 goto err_out;
5993 }
1da177e4
LT		 5994
5995 return 0;
5996
5997err_out:
5998 tg3_free_consistent(tp);
5999 return -ENOMEM;
6000}
6001
6002#define MAX_WAIT_CNT 1000
6003
6004/* To stop a block, clear the enable bit and poll till it
6005 * clears. tp->lock is held.
6006 */
b3b7d6be 6007static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6008{
6009 unsigned int i;
6010 u32 val;
6011
6012 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6013 switch (ofs) {
6014 case RCVLSC_MODE:
6015 case DMAC_MODE:
6016 case MBFREE_MODE:
6017 case BUFMGR_MODE:
6018 case MEMARB_MODE:
6019 /* We can't enable/disable these bits of the
6020 * 5705/5750, just say success.
6021 */
6022 return 0;
6023
6024 default:
6025 break;
855e1111 6026 }
1da177e4
LT		 6027 }
6028
6029 val = tr32(ofs);
6030 val &= ~enable_bit;
6031 tw32_f(ofs, val);
6032
6033 for (i = 0; i < MAX_WAIT_CNT; i++) {
6034 udelay(100);
6035 val = tr32(ofs);
6036 if ((val & enable_bit) == 0)
6037 break;
6038 }
6039
b3b7d6be 6040 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6041 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6042 "ofs=%lx enable_bit=%x\n",
6043 ofs, enable_bit);
6044 return -ENODEV;
6045 }
6046
6047 return 0;
6048}
6049
6050/* tp->lock is held. */
b3b7d6be 6051static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6052{
6053 int i, err;
6054
6055 tg3_disable_ints(tp);
6056
6057 tp->rx_mode &= ~RX_MODE_ENABLE;
6058 tw32_f(MAC_RX_MODE, tp->rx_mode);
6059 udelay(10);
6060
b3b7d6be
DM		 6061 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6062 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6063 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6064 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6065 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6066 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6067
6068 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6069 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6070 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6071 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6072 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6073 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6074 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6075
6076 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6077 tw32_f(MAC_MODE, tp->mac_mode);
6078 udelay(40);
6079
6080 tp->tx_mode &= ~TX_MODE_ENABLE;
6081 tw32_f(MAC_TX_MODE, tp->tx_mode);
6082
6083 for (i = 0; i < MAX_WAIT_CNT; i++) {
6084 udelay(100);
6085 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6086 break;
6087 }
6088 if (i >= MAX_WAIT_CNT) {
6089 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6090 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6091 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6092 err |= -ENODEV;
1da177e4
LT		 6093 }
6094
e6de8ad1 6095 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6096 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6097 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6098
6099 tw32(FTQ_RESET, 0xffffffff);
6100 tw32(FTQ_RESET, 0x00000000);
6101
b3b7d6be
DM		 6102 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6103 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6104
f77a6a8e
MC		 6105 for (i = 0; i < tp->irq_cnt; i++) {
6106 struct tg3_napi *tnapi = &tp->napi[i];
6107 if (tnapi->hw_status)
6108 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6109 }
1da177e4
LT		 6110 if (tp->hw_stats)
6111 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6112
1da177e4
LT		 6113 return err;
6114}
6115
0d3031d9
MC		 6116static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6117{
6118 int i;
6119 u32 apedata;
6120
6121 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6122 if (apedata != APE_SEG_SIG_MAGIC)
6123 return;
6124
6125 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6126 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6127 return;
6128
6129 /* Wait for up to 1 millisecond for APE to service previous event. */
6130 for (i = 0; i < 10; i++) {
6131 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6132 return;
6133
6134 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6135
6136 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6137 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6138 event | APE_EVENT_STATUS_EVENT_PENDING);
6139
6140 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6141
6142 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6143 break;
6144
6145 udelay(100);
6146 }
6147
6148 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6149 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6150}
6151
6152static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6153{
6154 u32 event;
6155 u32 apedata;
6156
6157 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6158 return;
6159
6160 switch (kind) {
6161 case RESET_KIND_INIT:
6162 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6163 APE_HOST_SEG_SIG_MAGIC);
6164 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6165 APE_HOST_SEG_LEN_MAGIC);
6166 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6167 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6168 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6169 APE_HOST_DRIVER_ID_MAGIC);
6170 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6171 APE_HOST_BEHAV_NO_PHYLOCK);
6172
6173 event = APE_EVENT_STATUS_STATE_START;
6174 break;
6175 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6176 /* With the interface we are currently using,
6177 * APE does not track driver state. Wiping
6178 * out the HOST SEGMENT SIGNATURE forces
6179 * the APE to assume OS absent status.
6180 */
6181 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6182
0d3031d9
MC		 6183 event = APE_EVENT_STATUS_STATE_UNLOAD;
6184 break;
6185 case RESET_KIND_SUSPEND:
6186 event = APE_EVENT_STATUS_STATE_SUSPEND;
6187 break;
6188 default:
6189 return;
6190 }
6191
6192 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6193
6194 tg3_ape_send_event(tp, event);
6195}
6196
1da177e4
LT		 6197/* tp->lock is held. */
6198static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6199{
f49639e6
DM		 6200 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6201 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6202
6203 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6204 switch (kind) {
6205 case RESET_KIND_INIT:
6206 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6207 DRV_STATE_START);
6208 break;
6209
6210 case RESET_KIND_SHUTDOWN:
6211 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6212 DRV_STATE_UNLOAD);
6213 break;
6214
6215 case RESET_KIND_SUSPEND:
6216 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6217 DRV_STATE_SUSPEND);
6218 break;
6219
6220 default:
6221 break;
855e1111 6222 }
1da177e4 6223 }
0d3031d9
MC		 6224
6225 if (kind == RESET_KIND_INIT ||
6226 kind == RESET_KIND_SUSPEND)
6227 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6228}
6229
6230/* tp->lock is held. */
6231static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6232{
6233 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6234 switch (kind) {
6235 case RESET_KIND_INIT:
6236 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6237 DRV_STATE_START_DONE);
6238 break;
6239
6240 case RESET_KIND_SHUTDOWN:
6241 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6242 DRV_STATE_UNLOAD_DONE);
6243 break;
6244
6245 default:
6246 break;
855e1111 6247 }
1da177e4 6248 }
0d3031d9
MC		 6249
6250 if (kind == RESET_KIND_SHUTDOWN)
6251 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6252}
6253
6254/* tp->lock is held. */
6255static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6256{
6257 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6258 switch (kind) {
6259 case RESET_KIND_INIT:
6260 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6261 DRV_STATE_START);
6262 break;
6263
6264 case RESET_KIND_SHUTDOWN:
6265 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6266 DRV_STATE_UNLOAD);
6267 break;
6268
6269 case RESET_KIND_SUSPEND:
6270 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6271 DRV_STATE_SUSPEND);
6272 break;
6273
6274 default:
6275 break;
855e1111 6276 }
1da177e4
LT		 6277 }
6278}
6279
7a6f4369
MC		 6280static int tg3_poll_fw(struct tg3 *tp)
6281{
6282 int i;
6283 u32 val;
6284
b5d3772c 6285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6286 /* Wait up to 20ms for init done. */
6287 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6288 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6289 return 0;
0ccead18 6290 udelay(100);
b5d3772c
MC		 6291 }
6292 return -ENODEV;
6293 }
6294
7a6f4369
MC		 6295 /* Wait for firmware initialization to complete. */
6296 for (i = 0; i < 100000; i++) {
6297 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6298 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6299 break;
6300 udelay(10);
6301 }
6302
6303 /* Chip might not be fitted with firmware. Some Sun onboard
6304 * parts are configured like that. So don't signal the timeout
6305 * of the above loop as an error, but do report the lack of
6306 * running firmware once.
6307 */
6308 if (i >= 100000 &&
6309 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6310 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6311
6312 printk(KERN_INFO PFX "%s: No firmware running.\n",
6313 tp->dev->name);
6314 }
6315
6316 return 0;
6317}
6318
ee6a99b5
MC		 6319/* Save PCI command register before chip reset */
6320static void tg3_save_pci_state(struct tg3 *tp)
6321{
8a6eac90 6322 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6323}
6324
6325/* Restore PCI state after chip reset */
6326static void tg3_restore_pci_state(struct tg3 *tp)
6327{
6328 u32 val;
6329
6330 /* Re-enable indirect register accesses. */
6331 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6332 tp->misc_host_ctrl);
6333
6334 /* Set MAX PCI retry to zero. */
6335 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6336 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6337 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6338 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6339 /* Allow reads and writes to the APE register and memory space. */
6340 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6341 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6342 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6343 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6344
8a6eac90 6345 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6346
fcb389df
MC		 6347 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6348 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6349 pcie_set_readrq(tp->pdev, 4096);
6350 else {
6351 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6352 tp->pci_cacheline_sz);
6353 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6354 tp->pci_lat_timer);
6355 }
114342f2 6356 }
5f5c51e3 6357
ee6a99b5 6358 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6359 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6360 u16 pcix_cmd;
6361
6362 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6363 &pcix_cmd);
6364 pcix_cmd &= ~PCI_X_CMD_ERO;
6365 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6366 pcix_cmd);
6367 }
ee6a99b5
MC		 6368
6369 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6370
6371 /* Chip reset on 5780 will reset MSI enable bit,
6372 * so need to restore it.
6373 */
6374 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6375 u16 ctrl;
6376
6377 pci_read_config_word(tp->pdev,
6378 tp->msi_cap + PCI_MSI_FLAGS,
6379 &ctrl);
6380 pci_write_config_word(tp->pdev,
6381 tp->msi_cap + PCI_MSI_FLAGS,
6382 ctrl | PCI_MSI_FLAGS_ENABLE);
6383 val = tr32(MSGINT_MODE);
6384 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6385 }
6386 }
6387}
6388
1da177e4
LT		 6389static void tg3_stop_fw(struct tg3 *);
6390
6391/* tp->lock is held. */
6392static int tg3_chip_reset(struct tg3 *tp)
6393{
6394 u32 val;
1ee582d8 6395 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6396 int i, err;
1da177e4 6397
f49639e6
DM		 6398 tg3_nvram_lock(tp);
6399
77b483f1
MC		 6400 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6401
f49639e6
DM		 6402 /* No matching tg3_nvram_unlock() after this because
6403 * chip reset below will undo the nvram lock.
6404 */
6405 tp->nvram_lock_cnt = 0;
1da177e4 6406
ee6a99b5
MC		 6407 /* GRC_MISC_CFG core clock reset will clear the memory
6408 * enable bit in PCI register 4 and the MSI enable bit
6409 * on some chips, so we save relevant registers here.
6410 */
6411 tg3_save_pci_state(tp);
6412
d9ab5ad1 6413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6414 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6415 tw32(GRC_FASTBOOT_PC, 0);
6416
1da177e4
LT		 6417 /*
6418 * We must avoid the readl() that normally takes place.
6419 * It locks machines, causes machine checks, and other
6420 * fun things. So, temporarily disable the 5701
6421 * hardware workaround, while we do the reset.
6422 */
1ee582d8
MC		 6423 write_op = tp->write32;
6424 if (write_op == tg3_write_flush_reg32)
6425 tp->write32 = tg3_write32;
1da177e4 6426
d18edcb2
MC		 6427 /* Prevent the irq handler from reading or writing PCI registers
6428 * during chip reset when the memory enable bit in the PCI command
6429 * register may be cleared. The chip does not generate interrupt
6430 * at this time, but the irq handler may still be called due to irq
6431 * sharing or irqpoll.
6432 */
6433 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6434 for (i = 0; i < tp->irq_cnt; i++) {
6435 struct tg3_napi *tnapi = &tp->napi[i];
6436 if (tnapi->hw_status) {
6437 tnapi->hw_status->status = 0;
6438 tnapi->hw_status->status_tag = 0;
6439 }
6440 tnapi->last_tag = 0;
6441 tnapi->last_irq_tag = 0;
b8fa2f3a 6442 }
d18edcb2 6443 smp_mb();
4f125f42
MC		 6444
6445 for (i = 0; i < tp->irq_cnt; i++)
6446 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6447
255ca311
MC		 6448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6449 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6450 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6451 }
6452
1da177e4
LT		 6453 /* do the reset */
6454 val = GRC_MISC_CFG_CORECLK_RESET;
6455
6456 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6457 if (tr32(0x7e2c) == 0x60) {
6458 tw32(0x7e2c, 0x20);
6459 }
6460 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6461 tw32(GRC_MISC_CFG, (1 << 29));
6462 val |= (1 << 29);
6463 }
6464 }
6465
b5d3772c
MC		 6466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6467 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6468 tw32(GRC_VCPU_EXT_CTRL,
6469 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6470 }
6471
1da177e4
LT		 6472 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6473 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6474 tw32(GRC_MISC_CFG, val);
6475
1ee582d8
MC		 6476 /* restore 5701 hardware bug workaround write method */
6477 tp->write32 = write_op;
1da177e4
LT		 6478
6479 /* Unfortunately, we have to delay before the PCI read back.
6480 * Some 575X chips even will not respond to a PCI cfg access
6481 * when the reset command is given to the chip.
6482 *
6483 * How do these hardware designers expect things to work
6484 * properly if the PCI write is posted for a long period
6485 * of time? It is always necessary to have some method by
6486 * which a register read back can occur to push the write
6487 * out which does the reset.
6488 *
6489 * For most tg3 variants the trick below was working.
6490 * Ho hum...
6491 */
6492 udelay(120);
6493
6494 /* Flush PCI posted writes. The normal MMIO registers
6495 * are inaccessible at this time so this is the only
6496 * way to make this reliably (actually, this is no longer
6497 * the case, see above). I tried to use indirect
6498 * register read/write but this upset some 5701 variants.
6499 */
6500 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6501
6502 udelay(120);
6503
5e7dfd0f 6504 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6505 u16 val16;
6506
1da177e4
LT		 6507 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6508 int i;
6509 u32 cfg_val;
6510
6511 /* Wait for link training to complete. */
6512 for (i = 0; i < 5000; i++)
6513 udelay(100);
6514
6515 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6516 pci_write_config_dword(tp->pdev, 0xc4,
6517 cfg_val | (1 << 15));
6518 }
5e7dfd0f 6519
e7126997
MC		 6520 /* Clear the "no snoop" and "relaxed ordering" bits. */
6521 pci_read_config_word(tp->pdev,
6522 tp->pcie_cap + PCI_EXP_DEVCTL,
6523 &val16);
6524 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6525 PCI_EXP_DEVCTL_NOSNOOP_EN);
6526 /*
6527 * Older PCIe devices only support the 128 byte
6528 * MPS setting. Enforce the restriction.
5e7dfd0f 6529 */
e7126997
MC		 6530 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6531 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6532 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6533 pci_write_config_word(tp->pdev,
6534 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6535 val16);
5e7dfd0f
MC		 6536
6537 pcie_set_readrq(tp->pdev, 4096);
6538
6539 /* Clear error status */
6540 pci_write_config_word(tp->pdev,
6541 tp->pcie_cap + PCI_EXP_DEVSTA,
6542 PCI_EXP_DEVSTA_CED |
6543 PCI_EXP_DEVSTA_NFED |
6544 PCI_EXP_DEVSTA_FED |
6545 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6546 }
6547
ee6a99b5 6548 tg3_restore_pci_state(tp);
1da177e4 6549
d18edcb2
MC		 6550 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6551
ee6a99b5
MC		 6552 val = 0;
6553 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6554 val = tr32(MEMARB_MODE);
ee6a99b5 6555 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6556
6557 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6558 tg3_stop_fw(tp);
6559 tw32(0x5000, 0x400);
6560 }
6561
6562 tw32(GRC_MODE, tp->grc_mode);
6563
6564 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6565 val = tr32(0xc4);
1da177e4
LT		 6566
6567 tw32(0xc4, val | (1 << 15));
6568 }
6569
6570 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6572 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6573 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6574 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6575 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6576 }
6577
6578 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6579 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6580 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6581 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6582 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6583 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6584 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6585 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6586 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6587 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6588 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6589 } else
6590 tw32_f(MAC_MODE, 0);
6591 udelay(40);
6592
77b483f1
MC		 6593 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6594
7a6f4369
MC		 6595 err = tg3_poll_fw(tp);
6596 if (err)
6597 return err;
1da177e4 6598
0a9140cf
MC		 6599 tg3_mdio_start(tp);
6600
1da177e4 6601 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6602 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6603 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6604 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6605 val = tr32(0x7c00);
1da177e4
LT		 6606
6607 tw32(0x7c00, val | (1 << 25));
6608 }
6609
6610 /* Reprobe ASF enable state. */
6611 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6612 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6613 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6614 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6615 u32 nic_cfg;
6616
6617 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6618 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6619 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6620 tp->last_event_jiffies = jiffies;
cbf46853 6621 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6622 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6623 }
6624 }
6625
6626 return 0;
6627}
6628
6629/* tp->lock is held. */
6630static void tg3_stop_fw(struct tg3 *tp)
6631{
0d3031d9
MC		 6632 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6633 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6634 /* Wait for RX cpu to ACK the previous event. */
6635 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6636
6637 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6638
6639 tg3_generate_fw_event(tp);
1da177e4 6640
7c5026aa
MC		 6641 /* Wait for RX cpu to ACK this event. */
6642 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6643 }
6644}
6645
6646/* tp->lock is held. */
944d980e 6647static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6648{
6649 int err;
6650
6651 tg3_stop_fw(tp);
6652
944d980e 6653 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6654
b3b7d6be 6655 tg3_abort_hw(tp, silent);
1da177e4
LT		 6656 err = tg3_chip_reset(tp);
6657
daba2a63
MC		 6658 __tg3_set_mac_addr(tp, 0);
6659
944d980e
MC		 6660 tg3_write_sig_legacy(tp, kind);
6661 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6662
6663 if (err)
6664 return err;
6665
6666 return 0;
6667}
6668
1da177e4
LT		 6669#define RX_CPU_SCRATCH_BASE 0x30000
6670#define RX_CPU_SCRATCH_SIZE 0x04000
6671#define TX_CPU_SCRATCH_BASE 0x34000
6672#define TX_CPU_SCRATCH_SIZE 0x04000
6673
6674/* tp->lock is held. */
6675static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6676{
6677 int i;
6678
5d9428de
ES		 6679 BUG_ON(offset == TX_CPU_BASE &&
6680 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6681
b5d3772c
MC		 6682 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6683 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6684
6685 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6686 return 0;
6687 }
1da177e4
LT		 6688 if (offset == RX_CPU_BASE) {
6689 for (i = 0; i < 10000; i++) {
6690 tw32(offset + CPU_STATE, 0xffffffff);
6691 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6692 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6693 break;
6694 }
6695
6696 tw32(offset + CPU_STATE, 0xffffffff);
6697 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6698 udelay(10);
6699 } else {
6700 for (i = 0; i < 10000; i++) {
6701 tw32(offset + CPU_STATE, 0xffffffff);
6702 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6703 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6704 break;
6705 }
6706 }
6707
6708 if (i >= 10000) {
6709 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6710 "and %s CPU\n",
6711 tp->dev->name,
6712 (offset == RX_CPU_BASE ? "RX" : "TX"));
6713 return -ENODEV;
6714 }
ec41c7df
MC		 6715
6716 /* Clear firmware's nvram arbitration. */
6717 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6718 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6719 return 0;
6720}
6721
6722struct fw_info {
077f849d
JSR		 6723 unsigned int fw_base;
6724 unsigned int fw_len;
6725 const __be32 *fw_data;
1da177e4
LT		 6726};
6727
6728/* tp->lock is held. */
6729static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6730 int cpu_scratch_size, struct fw_info *info)
6731{
ec41c7df 6732 int err, lock_err, i;
1da177e4
LT		 6733 void (*write_op)(struct tg3 *, u32, u32);
6734
6735 if (cpu_base == TX_CPU_BASE &&
6736 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6737 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6738 "TX cpu firmware on %s which is 5705.\n",
6739 tp->dev->name);
6740 return -EINVAL;
6741 }
6742
6743 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6744 write_op = tg3_write_mem;
6745 else
6746 write_op = tg3_write_indirect_reg32;
6747
1b628151
MC		 6748 /* It is possible that bootcode is still loading at this point.
6749 * Get the nvram lock first before halting the cpu.
6750 */
ec41c7df 6751 lock_err = tg3_nvram_lock(tp);
1da177e4 6752 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6753 if (!lock_err)
6754 tg3_nvram_unlock(tp);
1da177e4
LT		 6755 if (err)
6756 goto out;
6757
6758 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6759 write_op(tp, cpu_scratch_base + i, 0);
6760 tw32(cpu_base + CPU_STATE, 0xffffffff);
6761 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6762 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6763 write_op(tp, (cpu_scratch_base +
077f849d 6764 (info->fw_base & 0xffff) +
1da177e4 6765 (i * sizeof(u32))),
077f849d 6766 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6767
6768 err = 0;
6769
6770out:
1da177e4
LT		 6771 return err;
6772}
6773
6774/* tp->lock is held. */
6775static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6776{
6777 struct fw_info info;
077f849d 6778 const __be32 *fw_data;
1da177e4
LT		 6779 int err, i;
6780
077f849d
JSR		 6781 fw_data = (void *)tp->fw->data;
6782
6783 /* Firmware blob starts with version numbers, followed by
6784 start address and length. We are setting complete length.
6785 length = end_address_of_bss - start_address_of_text.
6786 Remainder is the blob to be loaded contiguously
6787 from start address. */
6788
6789 info.fw_base = be32_to_cpu(fw_data[1]);
6790 info.fw_len = tp->fw->size - 12;
6791 info.fw_data = &fw_data[3];
1da177e4
LT		 6792
6793 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6794 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6795 &info);
6796 if (err)
6797 return err;
6798
6799 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6800 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6801 &info);
6802 if (err)
6803 return err;
6804
6805 /* Now startup only the RX cpu. */
6806 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6807 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6808
6809 for (i = 0; i < 5; i++) {
077f849d 6810 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6811 break;
6812 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6813 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6814 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6815 udelay(1000);
6816 }
6817 if (i >= 5) {
6818 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6819 "to set RX CPU PC, is %08x should be %08x\n",
6820 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6821 info.fw_base);
1da177e4
LT		 6822 return -ENODEV;
6823 }
6824 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6825 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6826
6827 return 0;
6828}
6829
1da177e4 6830/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6831
6832/* tp->lock is held. */
6833static int tg3_load_tso_firmware(struct tg3 *tp)
6834{
6835 struct fw_info info;
077f849d 6836 const __be32 *fw_data;
1da177e4
LT		 6837 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6838 int err, i;
6839
6840 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6841 return 0;
6842
077f849d
JSR		 6843 fw_data = (void *)tp->fw->data;
6844
6845 /* Firmware blob starts with version numbers, followed by
6846 start address and length. We are setting complete length.
6847 length = end_address_of_bss - start_address_of_text.
6848 Remainder is the blob to be loaded contiguously
6849 from start address. */
6850
6851 info.fw_base = be32_to_cpu(fw_data[1]);
6852 cpu_scratch_size = tp->fw_len;
6853 info.fw_len = tp->fw->size - 12;
6854 info.fw_data = &fw_data[3];
6855
1da177e4 6856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6857 cpu_base = RX_CPU_BASE;
6858 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6859 } else {
1da177e4
LT		 6860 cpu_base = TX_CPU_BASE;
6861 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6862 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6863 }
6864
6865 err = tg3_load_firmware_cpu(tp, cpu_base,
6866 cpu_scratch_base, cpu_scratch_size,
6867 &info);
6868 if (err)
6869 return err;
6870
6871 /* Now startup the cpu. */
6872 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6873 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6874
6875 for (i = 0; i < 5; i++) {
077f849d 6876 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6877 break;
6878 tw32(cpu_base + CPU_STATE, 0xffffffff);
6879 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6880 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6881 udelay(1000);
6882 }
6883 if (i >= 5) {
6884 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6885 "to set CPU PC, is %08x should be %08x\n",
6886 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6887 info.fw_base);
1da177e4
LT		 6888 return -ENODEV;
6889 }
6890 tw32(cpu_base + CPU_STATE, 0xffffffff);
6891 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6892 return 0;
6893}
6894
1da177e4 6895
1da177e4
LT		 6896static int tg3_set_mac_addr(struct net_device *dev, void *p)
6897{
6898 struct tg3 *tp = netdev_priv(dev);
6899 struct sockaddr *addr = p;
986e0aeb 6900 int err = 0, skip_mac_1 = 0;
1da177e4 6901
f9804ddb
MC		 6902 if (!is_valid_ether_addr(addr->sa_data))
6903 return -EINVAL;
6904
1da177e4
LT		 6905 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6906
e75f7c90
MC		 6907 if (!netif_running(dev))
6908 return 0;
6909
58712ef9 6910 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6911 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6912
986e0aeb
MC		 6913 addr0_high = tr32(MAC_ADDR_0_HIGH);
6914 addr0_low = tr32(MAC_ADDR_0_LOW);
6915 addr1_high = tr32(MAC_ADDR_1_HIGH);
6916 addr1_low = tr32(MAC_ADDR_1_LOW);
6917
6918 /* Skip MAC addr 1 if ASF is using it. */
6919 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6920 !(addr1_high == 0 && addr1_low == 0))
6921 skip_mac_1 = 1;
58712ef9 6922 }
986e0aeb
MC		 6923 spin_lock_bh(&tp->lock);
6924 __tg3_set_mac_addr(tp, skip_mac_1);
6925 spin_unlock_bh(&tp->lock);
1da177e4 6926
b9ec6c1b 6927 return err;
1da177e4
LT		 6928}
6929
6930/* tp->lock is held. */
6931static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6932 dma_addr_t mapping, u32 maxlen_flags,
6933 u32 nic_addr)
6934{
6935 tg3_write_mem(tp,
6936 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6937 ((u64) mapping >> 32));
6938 tg3_write_mem(tp,
6939 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6940 ((u64) mapping & 0xffffffff));
6941 tg3_write_mem(tp,
6942 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6943 maxlen_flags);
6944
6945 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6946 tg3_write_mem(tp,
6947 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6948 nic_addr);
6949}
6950
6951static void __tg3_set_rx_mode(struct net_device *);
d244c892 6952static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 6953{
b6080e12
MC		 6954 int i;
6955
6956 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6957 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6958 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6959 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6960
6961 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6962 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6963 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6964 } else {
6965 tw32(HOSTCC_TXCOL_TICKS, 0);
6966 tw32(HOSTCC_TXMAX_FRAMES, 0);
6967 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6968
6969 tw32(HOSTCC_RXCOL_TICKS, 0);
6970 tw32(HOSTCC_RXMAX_FRAMES, 0);
6971 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 6972 }
b6080e12 6973
15f9850d
DM		 6974 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6975 u32 val = ec->stats_block_coalesce_usecs;
6976
b6080e12
MC		 6977 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6978 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6979
15f9850d
DM		 6980 if (!netif_carrier_ok(tp->dev))
6981 val = 0;
6982
6983 tw32(HOSTCC_STAT_COAL_TICKS, val);
6984 }
b6080e12
MC		 6985
6986 for (i = 0; i < tp->irq_cnt - 1; i++) {
6987 u32 reg;
6988
6989 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
6990 tw32(reg, ec->rx_coalesce_usecs);
6991 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
6992 tw32(reg, ec->tx_coalesce_usecs);
6993 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
6994 tw32(reg, ec->rx_max_coalesced_frames);
6995 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
6996 tw32(reg, ec->tx_max_coalesced_frames);
6997 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
6998 tw32(reg, ec->rx_max_coalesced_frames_irq);
6999 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7000 tw32(reg, ec->tx_max_coalesced_frames_irq);
7001 }
7002
7003 for (; i < tp->irq_max - 1; i++) {
7004 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7005 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7006 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7007 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7008 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7009 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7010 }
15f9850d 7011}
1da177e4 7012
2d31ecaf
MC		 7013/* tp->lock is held. */
7014static void tg3_rings_reset(struct tg3 *tp)
7015{
7016 int i;
f77a6a8e 7017 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7018 struct tg3_napi *tnapi = &tp->napi[0];
7019
7020 /* Disable all transmit rings but the first. */
7021 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7022 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7023 else
7024 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7025
7026 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7027 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7028 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7029 BDINFO_FLAGS_DISABLED);
7030
7031
7032 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7034 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7035 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7036 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7037 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7038 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7039 else
7040 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7041
7042 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7043 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7044 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7045 BDINFO_FLAGS_DISABLED);
7046
7047 /* Disable interrupts */
7048 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7049
7050 /* Zero mailbox registers. */
f77a6a8e
MC		 7051 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7052 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7053 tp->napi[i].tx_prod = 0;
7054 tp->napi[i].tx_cons = 0;
7055 tw32_mailbox(tp->napi[i].prodmbox, 0);
7056 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7057 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7058 }
7059 } else {
7060 tp->napi[0].tx_prod = 0;
7061 tp->napi[0].tx_cons = 0;
7062 tw32_mailbox(tp->napi[0].prodmbox, 0);
7063 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7064 }
2d31ecaf
MC		 7065
7066 /* Make sure the NIC-based send BD rings are disabled. */
7067 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7068 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7069 for (i = 0; i < 16; i++)
7070 tw32_tx_mbox(mbox + i * 8, 0);
7071 }
7072
7073 txrcb = NIC_SRAM_SEND_RCB;
7074 rxrcb = NIC_SRAM_RCV_RET_RCB;
7075
7076 /* Clear status block in ram. */
7077 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7078
7079 /* Set status block DMA address */
7080 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7081 ((u64) tnapi->status_mapping >> 32));
7082 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7083 ((u64) tnapi->status_mapping & 0xffffffff));
7084
f77a6a8e
MC		 7085 if (tnapi->tx_ring) {
7086 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7087 (TG3_TX_RING_SIZE <<
7088 BDINFO_FLAGS_MAXLEN_SHIFT),
7089 NIC_SRAM_TX_BUFFER_DESC);
7090 txrcb += TG3_BDINFO_SIZE;
7091 }
7092
7093 if (tnapi->rx_rcb) {
7094 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7095 (TG3_RX_RCB_RING_SIZE(tp) <<
7096 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7097 rxrcb += TG3_BDINFO_SIZE;
7098 }
7099
7100 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7101
f77a6a8e
MC		 7102 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7103 u64 mapping = (u64)tnapi->status_mapping;
7104 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7105 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7106
7107 /* Clear status block in ram. */
7108 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7109
7110 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7111 (TG3_TX_RING_SIZE <<
7112 BDINFO_FLAGS_MAXLEN_SHIFT),
7113 NIC_SRAM_TX_BUFFER_DESC);
7114
7115 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7116 (TG3_RX_RCB_RING_SIZE(tp) <<
7117 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7118
7119 stblk += 8;
7120 txrcb += TG3_BDINFO_SIZE;
7121 rxrcb += TG3_BDINFO_SIZE;
7122 }
2d31ecaf
MC		 7123}
7124
1da177e4 7125/* tp->lock is held. */
8e7a22e3 7126static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7127{
7128 u32 val, rdmac_mode;
7129 int i, err, limit;
21f581a5 7130 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7131
7132 tg3_disable_ints(tp);
7133
7134 tg3_stop_fw(tp);
7135
7136 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7137
7138 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7139 tg3_abort_hw(tp, 1);
1da177e4
LT		 7140 }
7141
dd477003
MC		 7142 if (reset_phy &&
7143 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7144 tg3_phy_reset(tp);
7145
1da177e4
LT		 7146 err = tg3_chip_reset(tp);
7147 if (err)
7148 return err;
7149
7150 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7151
bcb37f6c 7152 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7153 val = tr32(TG3_CPMU_CTRL);
7154 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7155 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7156
7157 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7158 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7159 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7160 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7161
7162 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7163 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7164 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7165 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7166
7167 val = tr32(TG3_CPMU_HST_ACC);
7168 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7169 val |= CPMU_HST_ACC_MACCLK_6_25;
7170 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7171 }
7172
33466d93
MC		 7173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7174 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7175 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7176 PCIE_PWR_MGMT_L1_THRESH_4MS;
7177 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7178
7179 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7180 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7181
7182 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 7183 }
7184
255ca311
MC		 7185 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7186 val = tr32(TG3_PCIE_LNKCTL);
7187 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7188 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7189 else
7190 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7191 tw32(TG3_PCIE_LNKCTL, val);
7192 }
7193
1da177e4
LT		 7194 /* This works around an issue with Athlon chipsets on
7195 * B3 tigon3 silicon. This bit has no effect on any
7196 * other revision. But do not set this on PCI Express
795d01c5 7197 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7198 */
795d01c5
MC		 7199 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7200 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7201 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7202 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7203 }
1da177e4
LT		 7204
7205 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7206 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7207 val = tr32(TG3PCI_PCISTATE);
7208 val |= PCISTATE_RETRY_SAME_DMA;
7209 tw32(TG3PCI_PCISTATE, val);
7210 }
7211
0d3031d9
MC		 7212 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7213 /* Allow reads and writes to the
7214 * APE register and memory space.
7215 */
7216 val = tr32(TG3PCI_PCISTATE);
7217 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7218 PCISTATE_ALLOW_APE_SHMEM_WR;
7219 tw32(TG3PCI_PCISTATE, val);
7220 }
7221
1da177e4
LT		 7222 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7223 /* Enable some hw fixes. */
7224 val = tr32(TG3PCI_MSI_DATA);
7225 val |= (1 << 26) | (1 << 28) | (1 << 29);
7226 tw32(TG3PCI_MSI_DATA, val);
7227 }
7228
7229 /* Descriptor ring init may make accesses to the
7230 * NIC SRAM area to setup the TX descriptors, so we
7231 * can only do this after the hardware has been
7232 * successfully reset.
7233 */
32d8c572
MC		 7234 err = tg3_init_rings(tp);
7235 if (err)
7236 return err;
1da177e4 7237
9936bcf6 7238 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
f6eb9b1f
MC		 7239 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7240 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
d30cdd28
MC		 7241 /* This value is determined during the probe time DMA
7242 * engine test, tg3_test_dma.
7243 */
7244 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7245 }
1da177e4
LT		 7246
7247 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7248 GRC_MODE_4X_NIC_SEND_RINGS |
7249 GRC_MODE_NO_TX_PHDR_CSUM |
7250 GRC_MODE_NO_RX_PHDR_CSUM);
7251 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7252
7253 /* Pseudo-header checksum is done by hardware logic and not
7254 * the offload processers, so make the chip do the pseudo-
7255 * header checksums on receive. For transmit it is more
7256 * convenient to do the pseudo-header checksum in software
7257 * as Linux does that on transmit for us in all cases.
7258 */
7259 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7260
7261 tw32(GRC_MODE,
7262 tp->grc_mode |
7263 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7264
7265 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7266 val = tr32(GRC_MISC_CFG);
7267 val &= ~0xff;
7268 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7269 tw32(GRC_MISC_CFG, val);
7270
7271 /* Initialize MBUF/DESC pool. */
cbf46853 7272 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7273 /* Do nothing. */
7274 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7275 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7277 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7278 else
7279 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7280 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7281 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7282 }
1da177e4
LT		 7283 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7284 int fw_len;
7285
077f849d 7286 fw_len = tp->fw_len;
1da177e4
LT		 7287 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7288 tw32(BUFMGR_MB_POOL_ADDR,
7289 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7290 tw32(BUFMGR_MB_POOL_SIZE,
7291 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7292 }
1da177e4 7293
0f893dc6 7294 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7295 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7296 tp->bufmgr_config.mbuf_read_dma_low_water);
7297 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7298 tp->bufmgr_config.mbuf_mac_rx_low_water);
7299 tw32(BUFMGR_MB_HIGH_WATER,
7300 tp->bufmgr_config.mbuf_high_water);
7301 } else {
7302 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7303 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7304 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7305 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7306 tw32(BUFMGR_MB_HIGH_WATER,
7307 tp->bufmgr_config.mbuf_high_water_jumbo);
7308 }
7309 tw32(BUFMGR_DMA_LOW_WATER,
7310 tp->bufmgr_config.dma_low_water);
7311 tw32(BUFMGR_DMA_HIGH_WATER,
7312 tp->bufmgr_config.dma_high_water);
7313
7314 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7315 for (i = 0; i < 2000; i++) {
7316 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7317 break;
7318 udelay(10);
7319 }
7320 if (i >= 2000) {
7321 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7322 tp->dev->name);
7323 return -ENODEV;
7324 }
7325
7326 /* Setup replenish threshold. */
f92905de
MC		 7327 val = tp->rx_pending / 8;
7328 if (val == 0)
7329 val = 1;
7330 else if (val > tp->rx_std_max_post)
7331 val = tp->rx_std_max_post;
b5d3772c
MC		 7332 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7333 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7334 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7335
7336 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7337 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7338 }
f92905de
MC		 7339
7340 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7341
7342 /* Initialize TG3_BDINFO's at:
7343 * RCVDBDI_STD_BD: standard eth size rx ring
7344 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7345 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7346 *
7347 * like so:
7348 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7349 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7350 * ring attribute flags
7351 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7352 *
7353 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7354 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7355 *
7356 * The size of each ring is fixed in the firmware, but the location is
7357 * configurable.
7358 */
7359 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7360 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7361 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7362 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7363 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7364 NIC_SRAM_RX_BUFFER_DESC);
7365
fdb72b38
MC		 7366 /* Disable the mini ring */
7367 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7368 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7369 BDINFO_FLAGS_DISABLED);
7370
fdb72b38
MC		 7371 /* Program the jumbo buffer descriptor ring control
7372 * blocks on those devices that have them.
7373 */
8f666b07 7374 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7375 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7376 /* Setup replenish threshold. */
7377 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7378
0f893dc6 7379 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7380 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7381 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7382 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7383 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7384 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7385 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7386 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7387 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7388 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7389 } else {
7390 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7391 BDINFO_FLAGS_DISABLED);
7392 }
7393
f6eb9b1f
MC		 7394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7395 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7396 (RX_STD_MAX_SIZE << 2);
7397 else
7398 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7399 } else
7400 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7401
7402 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7403
21f581a5 7404 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7405 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7406 tpr->rx_std_ptr);
1da177e4 7407
21f581a5
MC		 7408 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7409 tp->rx_jumbo_pending : 0;
1da177e4 7410 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7411 tpr->rx_jmb_ptr);
1da177e4 7412
f6eb9b1f
MC		 7413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7414 tw32(STD_REPLENISH_LWM, 32);
7415 tw32(JMB_REPLENISH_LWM, 16);
7416 }
7417
2d31ecaf
MC		 7418 tg3_rings_reset(tp);
7419
1da177e4 7420 /* Initialize MAC address and backoff seed. */
986e0aeb 7421 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7422
7423 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7424 tw32(MAC_RX_MTU_SIZE,
7425 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7426
7427 /* The slot time is changed by tg3_setup_phy if we
7428 * run at gigabit with half duplex.
7429 */
7430 tw32(MAC_TX_LENGTHS,
7431 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7432 (6 << TX_LENGTHS_IPG_SHIFT) |
7433 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7434
7435 /* Receive rules. */
7436 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7437 tw32(RCVLPC_CONFIG, 0x0181);
7438
7439 /* Calculate RDMAC_MODE setting early, we need it to determine
7440 * the RCVLPC_STATE_ENABLE mask.
7441 */
7442 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7443 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7444 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7445 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7446 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7447
57e6983c 7448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7451 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7452 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7453 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7454
85e94ced
MC		 7455 /* If statement applies to 5705 and 5750 PCI devices only */
7456 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7457 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7458 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7459 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7460 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7461 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7462 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7463 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7464 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7465 }
7466 }
7467
85e94ced
MC		 7468 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7469 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7470
1da177e4 7471 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7472 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7473
7474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7476 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7477
7478 /* Receive/send statistics. */
1661394e
MC		 7479 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7480 val = tr32(RCVLPC_STATS_ENABLE);
7481 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7482 tw32(RCVLPC_STATS_ENABLE, val);
7483 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7484 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7485 val = tr32(RCVLPC_STATS_ENABLE);
7486 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7487 tw32(RCVLPC_STATS_ENABLE, val);
7488 } else {
7489 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7490 }
7491 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7492 tw32(SNDDATAI_STATSENAB, 0xffffff);
7493 tw32(SNDDATAI_STATSCTRL,
7494 (SNDDATAI_SCTRL_ENABLE |
7495 SNDDATAI_SCTRL_FASTUPD));
7496
7497 /* Setup host coalescing engine. */
7498 tw32(HOSTCC_MODE, 0);
7499 for (i = 0; i < 2000; i++) {
7500 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7501 break;
7502 udelay(10);
7503 }
7504
d244c892 7505 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7506
1da177e4
LT		 7507 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7508 /* Status/statistics block address. See tg3_timer,
7509 * the tg3_periodic_fetch_stats call there, and
7510 * tg3_get_stats to see how this works for 5705/5750 chips.
7511 */
1da177e4
LT		 7512 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7513 ((u64) tp->stats_mapping >> 32));
7514 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7515 ((u64) tp->stats_mapping & 0xffffffff));
7516 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7517
1da177e4 7518 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7519
7520 /* Clear statistics and status block memory areas */
7521 for (i = NIC_SRAM_STATS_BLK;
7522 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7523 i += sizeof(u32)) {
7524 tg3_write_mem(tp, i, 0);
7525 udelay(40);
7526 }
1da177e4
LT		 7527 }
7528
7529 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7530
7531 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7532 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7533 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7534 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7535
c94e3941
MC		 7536 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7537 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7538 /* reset to prevent losing 1st rx packet intermittently */
7539 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7540 udelay(10);
7541 }
7542
3bda1258
MC		 7543 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7544 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7545 else
7546 tp->mac_mode = 0;
7547 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7548 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7549 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7550 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7551 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7552 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7553 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7554 udelay(40);
7555
314fba34 7556 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7557 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7558 * register to preserve the GPIO settings for LOMs. The GPIOs,
7559 * whether used as inputs or outputs, are set by boot code after
7560 * reset.
7561 */
9d26e213 7562 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7563 u32 gpio_mask;
7564
9d26e213
MC		 7565 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7566 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7567 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7568
7569 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7570 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7571 GRC_LCLCTRL_GPIO_OUTPUT3;
7572
af36e6b6
MC		 7573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7574 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7575
aaf84465 7576 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7577 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7578
7579 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7580 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7581 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7582 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7583 }
1da177e4
LT		 7584 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7585 udelay(100);
7586
baf8a94a
MC		 7587 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7588 val = tr32(MSGINT_MODE);
7589 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7590 tw32(MSGINT_MODE, val);
7591 }
7592
1da177e4
LT		 7593 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7594 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7595 udelay(40);
7596 }
7597
7598 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7599 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7600 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7601 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7602 WDMAC_MODE_LNGREAD_ENAB);
7603
85e94ced
MC		 7604 /* If statement applies to 5705 and 5750 PCI devices only */
7605 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7606 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7608 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7609 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7610 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7611 /* nothing */
7612 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7613 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7614 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7615 val |= WDMAC_MODE_RX_ACCEL;
7616 }
7617 }
7618
d9ab5ad1 7619 /* Enable host coalescing bug fix */
321d32a0 7620 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7621 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7622
1da177e4
LT		 7623 tw32_f(WDMAC_MODE, val);
7624 udelay(40);
7625
9974a356
MC		 7626 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7627 u16 pcix_cmd;
7628
7629 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7630 &pcix_cmd);
1da177e4 7631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7632 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7633 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7634 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7635 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7636 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7637 }
9974a356
MC		 7638 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7639 pcix_cmd);
1da177e4
LT		 7640 }
7641
7642 tw32_f(RDMAC_MODE, rdmac_mode);
7643 udelay(40);
7644
7645 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7646 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7647 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7648
7649 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7650 tw32(SNDDATAC_MODE,
7651 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7652 else
7653 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7654
1da177e4
LT		 7655 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7656 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7657 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7658 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7659 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7660 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7661 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7662 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7663 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7664 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7665 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7666
7667 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7668 err = tg3_load_5701_a0_firmware_fix(tp);
7669 if (err)
7670 return err;
7671 }
7672
1da177e4
LT		 7673 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7674 err = tg3_load_tso_firmware(tp);
7675 if (err)
7676 return err;
7677 }
1da177e4
LT		 7678
7679 tp->tx_mode = TX_MODE_ENABLE;
7680 tw32_f(MAC_TX_MODE, tp->tx_mode);
7681 udelay(100);
7682
baf8a94a
MC		 7683 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7684 u32 reg = MAC_RSS_INDIR_TBL_0;
7685 u8 *ent = (u8 *)&val;
7686
7687 /* Setup the indirection table */
7688 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7689 int idx = i % sizeof(val);
7690
7691 ent[idx] = i % (tp->irq_cnt - 1);
7692 if (idx == sizeof(val) - 1) {
7693 tw32(reg, val);
7694 reg += 4;
7695 }
7696 }
7697
7698 /* Setup the "secret" hash key. */
7699 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7700 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7701 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7702 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7703 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7704 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7705 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7706 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7707 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7708 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7709 }
7710
1da177e4 7711 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7712 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7713 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7714
baf8a94a
MC		 7715 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7716 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7717 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7718 RX_MODE_RSS_IPV6_HASH_EN |
7719 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7720 RX_MODE_RSS_IPV4_HASH_EN |
7721 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7722
1da177e4
LT		 7723 tw32_f(MAC_RX_MODE, tp->rx_mode);
7724 udelay(10);
7725
1da177e4
LT		 7726 tw32(MAC_LED_CTRL, tp->led_ctrl);
7727
7728 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7729 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7730 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7731 udelay(10);
7732 }
7733 tw32_f(MAC_RX_MODE, tp->rx_mode);
7734 udelay(10);
7735
7736 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7737 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7738 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7739 /* Set drive transmission level to 1.2V */
7740 /* only if the signal pre-emphasis bit is not set */
7741 val = tr32(MAC_SERDES_CFG);
7742 val &= 0xfffff000;
7743 val |= 0x880;
7744 tw32(MAC_SERDES_CFG, val);
7745 }
7746 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7747 tw32(MAC_SERDES_CFG, 0x616000);
7748 }
7749
7750 /* Prevent chip from dropping frames when flow control
7751 * is enabled.
7752 */
7753 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7754
7755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7756 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7757 /* Use hardware link auto-negotiation */
7758 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7759 }
7760
d4d2c558
MC		 7761 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7762 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7763 u32 tmp;
7764
7765 tmp = tr32(SERDES_RX_CTRL);
7766 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7767 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7768 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7769 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7770 }
7771
dd477003
MC		 7772 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7773 if (tp->link_config.phy_is_low_power) {
7774 tp->link_config.phy_is_low_power = 0;
7775 tp->link_config.speed = tp->link_config.orig_speed;
7776 tp->link_config.duplex = tp->link_config.orig_duplex;
7777 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7778 }
1da177e4 7779
dd477003
MC		 7780 err = tg3_setup_phy(tp, 0);
7781 if (err)
7782 return err;
1da177e4 7783
dd477003 7784 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7785 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7786 u32 tmp;
7787
7788 /* Clear CRC stats. */
7789 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7790 tg3_writephy(tp, MII_TG3_TEST1,
7791 tmp | MII_TG3_TEST1_CRC_EN);
7792 tg3_readphy(tp, 0x14, &tmp);
7793 }
1da177e4
LT		 7794 }
7795 }
7796
7797 __tg3_set_rx_mode(tp->dev);
7798
7799 /* Initialize receive rules. */
7800 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7801 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7802 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7803 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7804
4cf78e4f 7805 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7806 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7807 limit = 8;
7808 else
7809 limit = 16;
7810 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7811 limit -= 4;
7812 switch (limit) {
7813 case 16:
7814 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7815 case 15:
7816 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7817 case 14:
7818 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7819 case 13:
7820 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7821 case 12:
7822 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7823 case 11:
7824 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7825 case 10:
7826 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7827 case 9:
7828 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7829 case 8:
7830 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7831 case 7:
7832 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7833 case 6:
7834 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7835 case 5:
7836 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7837 case 4:
7838 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7839 case 3:
7840 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7841 case 2:
7842 case 1:
7843
7844 default:
7845 break;
855e1111 7846 }
1da177e4 7847
9ce768ea
MC		 7848 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7849 /* Write our heartbeat update interval to APE. */
7850 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7851 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7852
1da177e4
LT		 7853 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7854
1da177e4
LT		 7855 return 0;
7856}
7857
7858/* Called at device open time to get the chip ready for
7859 * packet processing. Invoked with tp->lock held.
7860 */
8e7a22e3 7861static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7862{
1da177e4
LT		 7863 tg3_switch_clocks(tp);
7864
7865 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7866
2f751b67 7867 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7868}
7869
7870#define TG3_STAT_ADD32(PSTAT, REG) \
7871do { u32 __val = tr32(REG); \
7872 (PSTAT)->low += __val; \
7873 if ((PSTAT)->low < __val) \
7874 (PSTAT)->high += 1; \
7875} while (0)
7876
7877static void tg3_periodic_fetch_stats(struct tg3 *tp)
7878{
7879 struct tg3_hw_stats *sp = tp->hw_stats;
7880
7881 if (!netif_carrier_ok(tp->dev))
7882 return;
7883
7884 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7885 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7886 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7887 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7888 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7889 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7890 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7891 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7892 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7893 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7894 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7895 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7896 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7897
7898 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7899 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7900 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7901 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7902 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7903 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7904 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7905 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7906 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7907 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7908 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7909 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7910 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7911 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7912
7913 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7914 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7915 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7916}
7917
7918static void tg3_timer(unsigned long __opaque)
7919{
7920 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7921
f475f163
MC		 7922 if (tp->irq_sync)
7923 goto restart_timer;
7924
f47c11ee 7925 spin_lock(&tp->lock);
1da177e4 7926
fac9b83e
DM		 7927 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7928 /* All of this garbage is because when using non-tagged
7929 * IRQ status the mailbox/status_block protocol the chip
7930 * uses with the cpu is race prone.
7931 */
898a56f8 7932 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7933 tw32(GRC_LOCAL_CTRL,
7934 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7935 } else {
7936 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7937 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7938 }
1da177e4 7939
fac9b83e
DM		 7940 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7941 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7942 spin_unlock(&tp->lock);
fac9b83e
DM		 7943 schedule_work(&tp->reset_task);
7944 return;
7945 }
1da177e4
LT		 7946 }
7947
1da177e4
LT		 7948 /* This part only runs once per second. */
7949 if (!--tp->timer_counter) {
fac9b83e
DM		 7950 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7951 tg3_periodic_fetch_stats(tp);
7952
1da177e4
LT		 7953 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7954 u32 mac_stat;
7955 int phy_event;
7956
7957 mac_stat = tr32(MAC_STATUS);
7958
7959 phy_event = 0;
7960 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7961 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7962 phy_event = 1;
7963 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7964 phy_event = 1;
7965
7966 if (phy_event)
7967 tg3_setup_phy(tp, 0);
7968 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7969 u32 mac_stat = tr32(MAC_STATUS);
7970 int need_setup = 0;
7971
7972 if (netif_carrier_ok(tp->dev) &&
7973 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7974 need_setup = 1;
7975 }
7976 if (! netif_carrier_ok(tp->dev) &&
7977 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7978 MAC_STATUS_SIGNAL_DET))) {
7979 need_setup = 1;
7980 }
7981 if (need_setup) {
3d3ebe74
MC		 7982 if (!tp->serdes_counter) {
7983 tw32_f(MAC_MODE,
7984 (tp->mac_mode &
7985 ~MAC_MODE_PORT_MODE_MASK));
7986 udelay(40);
7987 tw32_f(MAC_MODE, tp->mac_mode);
7988 udelay(40);
7989 }
1da177e4
LT		 7990 tg3_setup_phy(tp, 0);
7991 }
747e8f8b
MC		 7992 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7993 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7994
7995 tp->timer_counter = tp->timer_multiplier;
7996 }
7997
130b8e4d
MC		 7998 /* Heartbeat is only sent once every 2 seconds.
7999 *
8000 * The heartbeat is to tell the ASF firmware that the host
8001 * driver is still alive. In the event that the OS crashes,
8002 * ASF needs to reset the hardware to free up the FIFO space
8003 * that may be filled with rx packets destined for the host.
8004 * If the FIFO is full, ASF will no longer function properly.
8005 *
8006 * Unintended resets have been reported on real time kernels
8007 * where the timer doesn't run on time. Netpoll will also have
8008 * same problem.
8009 *
8010 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8011 * to check the ring condition when the heartbeat is expiring
8012 * before doing the reset. This will prevent most unintended
8013 * resets.
8014 */
1da177e4 8015 if (!--tp->asf_counter) {
bc7959b2
MC		 8016 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8017 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8018 tg3_wait_for_event_ack(tp);
8019
bbadf503 8020 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8021 FWCMD_NICDRV_ALIVE3);
bbadf503 8022 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8023 /* 5 seconds timeout */
bbadf503 8024 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8025
8026 tg3_generate_fw_event(tp);
1da177e4
LT		 8027 }
8028 tp->asf_counter = tp->asf_multiplier;
8029 }
8030
f47c11ee 8031 spin_unlock(&tp->lock);
1da177e4 8032
f475f163 8033restart_timer:
1da177e4
LT		 8034 tp->timer.expires = jiffies + tp->timer_offset;
8035 add_timer(&tp->timer);
8036}
8037
4f125f42 8038static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8039{
7d12e780 8040 irq_handler_t fn;
fcfa0a32 8041 unsigned long flags;
4f125f42
MC		 8042 char *name;
8043 struct tg3_napi *tnapi = &tp->napi[irq_num];
8044
8045 if (tp->irq_cnt == 1)
8046 name = tp->dev->name;
8047 else {
8048 name = &tnapi->irq_lbl[0];
8049 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8050 name[IFNAMSIZ-1] = 0;
8051 }
fcfa0a32 8052
679563f4 8053 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8054 fn = tg3_msi;
8055 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8056 fn = tg3_msi_1shot;
1fb9df5d 8057 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8058 } else {
8059 fn = tg3_interrupt;
8060 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8061 fn = tg3_interrupt_tagged;
1fb9df5d 8062 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8063 }
4f125f42
MC		 8064
8065 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8066}
8067
7938109f
MC		 8068static int tg3_test_interrupt(struct tg3 *tp)
8069{
09943a18 8070 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8071 struct net_device *dev = tp->dev;
b16250e3 8072 int err, i, intr_ok = 0;
f6eb9b1f 8073 u32 val;
7938109f 8074
d4bc3927
MC		 8075 if (!netif_running(dev))
8076 return -ENODEV;
8077
7938109f
MC		 8078 tg3_disable_ints(tp);
8079
4f125f42 8080 free_irq(tnapi->irq_vec, tnapi);
7938109f 8081
f6eb9b1f
MC		 8082 /*
8083 * Turn off MSI one shot mode. Otherwise this test has no
8084 * observable way to know whether the interrupt was delivered.
8085 */
8086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8087 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8088 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8089 tw32(MSGINT_MODE, val);
8090 }
8091
4f125f42 8092 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8093 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8094 if (err)
8095 return err;
8096
898a56f8 8097 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8098 tg3_enable_ints(tp);
8099
8100 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8101 tnapi->coal_now);
7938109f
MC		 8102
8103 for (i = 0; i < 5; i++) {
b16250e3
MC		 8104 u32 int_mbox, misc_host_ctrl;
8105
898a56f8 8106 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8107 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8108
8109 if ((int_mbox != 0) ||
8110 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8111 intr_ok = 1;
7938109f 8112 break;
b16250e3
MC		 8113 }
8114
7938109f
MC		 8115 msleep(10);
8116 }
8117
8118 tg3_disable_ints(tp);
8119
4f125f42 8120 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8121
4f125f42 8122 err = tg3_request_irq(tp, 0);
7938109f
MC		 8123
8124 if (err)
8125 return err;
8126
f6eb9b1f
MC		 8127 if (intr_ok) {
8128 /* Reenable MSI one shot mode. */
8129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8130 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8131 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8132 tw32(MSGINT_MODE, val);
8133 }
7938109f 8134 return 0;
f6eb9b1f 8135 }
7938109f
MC		 8136
8137 return -EIO;
8138}
8139
8140/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8141 * successfully restored
8142 */
8143static int tg3_test_msi(struct tg3 *tp)
8144{
7938109f
MC		 8145 int err;
8146 u16 pci_cmd;
8147
8148 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8149 return 0;
8150
8151 /* Turn off SERR reporting in case MSI terminates with Master
8152 * Abort.
8153 */
8154 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8155 pci_write_config_word(tp->pdev, PCI_COMMAND,
8156 pci_cmd & ~PCI_COMMAND_SERR);
8157
8158 err = tg3_test_interrupt(tp);
8159
8160 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8161
8162 if (!err)
8163 return 0;
8164
8165 /* other failures */
8166 if (err != -EIO)
8167 return err;
8168
8169 /* MSI test failed, go back to INTx mode */
8170 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8171 "switching to INTx mode. Please report this failure to "
8172 "the PCI maintainer and include system chipset information.\n",
8173 tp->dev->name);
8174
4f125f42 8175 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8176
7938109f
MC		 8177 pci_disable_msi(tp->pdev);
8178
8179 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8180
4f125f42 8181 err = tg3_request_irq(tp, 0);
7938109f
MC		 8182 if (err)
8183 return err;
8184
8185 /* Need to reset the chip because the MSI cycle may have terminated
8186 * with Master Abort.
8187 */
f47c11ee 8188 tg3_full_lock(tp, 1);
7938109f 8189
944d980e 8190 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8191 err = tg3_init_hw(tp, 1);
7938109f 8192
f47c11ee 8193 tg3_full_unlock(tp);
7938109f
MC		 8194
8195 if (err)
4f125f42 8196 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8197
8198 return err;
8199}
8200
9e9fd12d
MC		 8201static int tg3_request_firmware(struct tg3 *tp)
8202{
8203 const __be32 *fw_data;
8204
8205 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8206 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8207 tp->dev->name, tp->fw_needed);
8208 return -ENOENT;
8209 }
8210
8211 fw_data = (void *)tp->fw->data;
8212
8213 /* Firmware blob starts with version numbers, followed by
8214 * start address and _full_ length including BSS sections
8215 * (which must be longer than the actual data, of course
8216 */
8217
8218 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8219 if (tp->fw_len < (tp->fw->size - 12)) {
8220 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8221 tp->dev->name, tp->fw_len, tp->fw_needed);
8222 release_firmware(tp->fw);
8223 tp->fw = NULL;
8224 return -EINVAL;
8225 }
8226
8227 /* We no longer need firmware; we have it. */
8228 tp->fw_needed = NULL;
8229 return 0;
8230}
8231
679563f4
MC		 8232static bool tg3_enable_msix(struct tg3 *tp)
8233{
8234 int i, rc, cpus = num_online_cpus();
8235 struct msix_entry msix_ent[tp->irq_max];
8236
8237 if (cpus == 1)
8238 /* Just fallback to the simpler MSI mode. */
8239 return false;
8240
8241 /*
8242 * We want as many rx rings enabled as there are cpus.
8243 * The first MSIX vector only deals with link interrupts, etc,
8244 * so we add one to the number of vectors we are requesting.
8245 */
8246 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8247
8248 for (i = 0; i < tp->irq_max; i++) {
8249 msix_ent[i].entry = i;
8250 msix_ent[i].vector = 0;
8251 }
8252
8253 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8254 if (rc != 0) {
8255 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8256 return false;
8257 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8258 return false;
8259 printk(KERN_NOTICE
8260 "%s: Requested %d MSI-X vectors, received %d\n",
8261 tp->dev->name, tp->irq_cnt, rc);
8262 tp->irq_cnt = rc;
8263 }
8264
baf8a94a
MC		 8265 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8266
679563f4
MC		 8267 for (i = 0; i < tp->irq_max; i++)
8268 tp->napi[i].irq_vec = msix_ent[i].vector;
8269
fe5f5787
MC		 8270 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8271
679563f4
MC		 8272 return true;
8273}
8274
07b0173c
MC		 8275static void tg3_ints_init(struct tg3 *tp)
8276{
679563f4
MC		 8277 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8278 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8279 /* All MSI supporting chips should support tagged
8280 * status. Assert that this is the case.
8281 */
679563f4
MC		 8282 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8283 "Not using MSI.\n", tp->dev->name);
8284 goto defcfg;
07b0173c 8285 }
4f125f42 8286
679563f4
MC		 8287 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8288 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8289 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8290 pci_enable_msi(tp->pdev) == 0)
8291 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8292
8293 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8294 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8295 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8296 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8297 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8298 }
8299defcfg:
8300 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8301 tp->irq_cnt = 1;
8302 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8303 tp->dev->real_num_tx_queues = 1;
679563f4 8304 }
07b0173c
MC		 8305}
8306
8307static void tg3_ints_fini(struct tg3 *tp)
8308{
679563f4
MC		 8309 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8310 pci_disable_msix(tp->pdev);
8311 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8312 pci_disable_msi(tp->pdev);
8313 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8314 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8315}
8316
1da177e4
LT		 8317static int tg3_open(struct net_device *dev)
8318{
8319 struct tg3 *tp = netdev_priv(dev);
4f125f42 8320 int i, err;
1da177e4 8321
9e9fd12d
MC		 8322 if (tp->fw_needed) {
8323 err = tg3_request_firmware(tp);
8324 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8325 if (err)
8326 return err;
8327 } else if (err) {
8328 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8329 tp->dev->name);
8330 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8331 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8332 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8333 tp->dev->name);
8334 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8335 }
8336 }
8337
c49a1561
MC		 8338 netif_carrier_off(tp->dev);
8339
bc1c7567 8340 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8341 if (err)
bc1c7567 8342 return err;
2f751b67
MC		 8343
8344 tg3_full_lock(tp, 0);
bc1c7567 8345
1da177e4
LT		 8346 tg3_disable_ints(tp);
8347 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8348
f47c11ee 8349 tg3_full_unlock(tp);
1da177e4 8350
679563f4
MC		 8351 /*
8352 * Setup interrupts first so we know how
8353 * many NAPI resources to allocate
8354 */
8355 tg3_ints_init(tp);
8356
1da177e4
LT		 8357 /* The placement of this call is tied
8358 * to the setup and use of Host TX descriptors.
8359 */
8360 err = tg3_alloc_consistent(tp);
8361 if (err)
679563f4 8362 goto err_out1;
88b06bc2 8363
fed97810 8364 tg3_napi_enable(tp);
1da177e4 8365
4f125f42
MC		 8366 for (i = 0; i < tp->irq_cnt; i++) {
8367 struct tg3_napi *tnapi = &tp->napi[i];
8368 err = tg3_request_irq(tp, i);
8369 if (err) {
8370 for (i--; i >= 0; i--)
8371 free_irq(tnapi->irq_vec, tnapi);
8372 break;
8373 }
8374 }
1da177e4 8375
07b0173c 8376 if (err)
679563f4 8377 goto err_out2;
bea3348e 8378
f47c11ee 8379 tg3_full_lock(tp, 0);
1da177e4 8380
8e7a22e3 8381 err = tg3_init_hw(tp, 1);
1da177e4 8382 if (err) {
944d980e 8383 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8384 tg3_free_rings(tp);
8385 } else {
fac9b83e
DM		 8386 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8387 tp->timer_offset = HZ;
8388 else
8389 tp->timer_offset = HZ / 10;
8390
8391 BUG_ON(tp->timer_offset > HZ);
8392 tp->timer_counter = tp->timer_multiplier =
8393 (HZ / tp->timer_offset);
8394 tp->asf_counter = tp->asf_multiplier =
28fbef78 8395 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8396
8397 init_timer(&tp->timer);
8398 tp->timer.expires = jiffies + tp->timer_offset;
8399 tp->timer.data = (unsigned long) tp;
8400 tp->timer.function = tg3_timer;
1da177e4
LT		 8401 }
8402
f47c11ee 8403 tg3_full_unlock(tp);
1da177e4 8404
07b0173c 8405 if (err)
679563f4 8406 goto err_out3;
1da177e4 8407
7938109f
MC		 8408 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8409 err = tg3_test_msi(tp);
fac9b83e 8410
7938109f 8411 if (err) {
f47c11ee 8412 tg3_full_lock(tp, 0);
944d980e 8413 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8414 tg3_free_rings(tp);
f47c11ee 8415 tg3_full_unlock(tp);
7938109f 8416
679563f4 8417 goto err_out2;
7938109f 8418 }
fcfa0a32 8419
f6eb9b1f
MC		 8420 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8421 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8422 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8423 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8424
f6eb9b1f
MC		 8425 tw32(PCIE_TRANSACTION_CFG,
8426 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8427 }
7938109f
MC		 8428 }
8429
b02fd9e3
MC		 8430 tg3_phy_start(tp);
8431
f47c11ee 8432 tg3_full_lock(tp, 0);
1da177e4 8433
7938109f
MC		 8434 add_timer(&tp->timer);
8435 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8436 tg3_enable_ints(tp);
8437
f47c11ee 8438 tg3_full_unlock(tp);
1da177e4 8439
fe5f5787 8440 netif_tx_start_all_queues(dev);
1da177e4
LT		 8441
8442 return 0;
07b0173c 8443
679563f4 8444err_out3:
4f125f42
MC		 8445 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8446 struct tg3_napi *tnapi = &tp->napi[i];
8447 free_irq(tnapi->irq_vec, tnapi);
8448 }
07b0173c 8449
679563f4 8450err_out2:
fed97810 8451 tg3_napi_disable(tp);
07b0173c 8452 tg3_free_consistent(tp);
679563f4
MC		 8453
8454err_out1:
8455 tg3_ints_fini(tp);
07b0173c 8456 return err;
1da177e4
LT		 8457}
8458
8459#if 0
8460/*static*/ void tg3_dump_state(struct tg3 *tp)
8461{
8462 u32 val32, val32_2, val32_3, val32_4, val32_5;
8463 u16 val16;
8464 int i;
898a56f8 8465 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8466
8467 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8468 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8469 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8470 val16, val32);
8471
8472 /* MAC block */
8473 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8474 tr32(MAC_MODE), tr32(MAC_STATUS));
8475 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8476 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8477 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8478 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8479 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8480 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8481
8482 /* Send data initiator control block */
8483 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8484 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8485 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8486 tr32(SNDDATAI_STATSCTRL));
8487
8488 /* Send data completion control block */
8489 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8490
8491 /* Send BD ring selector block */
8492 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8493 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8494
8495 /* Send BD initiator control block */
8496 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8497 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8498
8499 /* Send BD completion control block */
8500 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8501
8502 /* Receive list placement control block */
8503 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8504 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8505 printk(" RCVLPC_STATSCTRL[%08x]\n",
8506 tr32(RCVLPC_STATSCTRL));
8507
8508 /* Receive data and receive BD initiator control block */
8509 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8510 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8511
8512 /* Receive data completion control block */
8513 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8514 tr32(RCVDCC_MODE));
8515
8516 /* Receive BD initiator control block */
8517 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8518 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8519
8520 /* Receive BD completion control block */
8521 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8522 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8523
8524 /* Receive list selector control block */
8525 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8526 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8527
8528 /* Mbuf cluster free block */
8529 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8530 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8531
8532 /* Host coalescing control block */
8533 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8534 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8535 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8536 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8537 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8538 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8539 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8540 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8541 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8542 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8543 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8544 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8545
8546 /* Memory arbiter control block */
8547 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8548 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8549
8550 /* Buffer manager control block */
8551 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8552 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8553 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8554 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8555 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8556 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8557 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8558 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8559
8560 /* Read DMA control block */
8561 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8562 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8563
8564 /* Write DMA control block */
8565 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8566 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8567
8568 /* DMA completion block */
8569 printk("DEBUG: DMAC_MODE[%08x]\n",
8570 tr32(DMAC_MODE));
8571
8572 /* GRC block */
8573 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8574 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8575 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8576 tr32(GRC_LOCAL_CTRL));
8577
8578 /* TG3_BDINFOs */
8579 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8580 tr32(RCVDBDI_JUMBO_BD + 0x0),
8581 tr32(RCVDBDI_JUMBO_BD + 0x4),
8582 tr32(RCVDBDI_JUMBO_BD + 0x8),
8583 tr32(RCVDBDI_JUMBO_BD + 0xc));
8584 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8585 tr32(RCVDBDI_STD_BD + 0x0),
8586 tr32(RCVDBDI_STD_BD + 0x4),
8587 tr32(RCVDBDI_STD_BD + 0x8),
8588 tr32(RCVDBDI_STD_BD + 0xc));
8589 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8590 tr32(RCVDBDI_MINI_BD + 0x0),
8591 tr32(RCVDBDI_MINI_BD + 0x4),
8592 tr32(RCVDBDI_MINI_BD + 0x8),
8593 tr32(RCVDBDI_MINI_BD + 0xc));
8594
8595 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8596 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8597 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8598 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8599 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8600 val32, val32_2, val32_3, val32_4);
8601
8602 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8603 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8604 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8605 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8606 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8607 val32, val32_2, val32_3, val32_4);
8608
8609 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8610 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8611 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8612 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8613 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8614 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8615 val32, val32_2, val32_3, val32_4, val32_5);
8616
8617 /* SW status block */
898a56f8
MC		 8618 printk(KERN_DEBUG
8619 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8620 sblk->status,
8621 sblk->status_tag,
8622 sblk->rx_jumbo_consumer,
8623 sblk->rx_consumer,
8624 sblk->rx_mini_consumer,
8625 sblk->idx[0].rx_producer,
8626 sblk->idx[0].tx_consumer);
1da177e4
LT		 8627
8628 /* SW statistics block */
8629 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8630 ((u32 *)tp->hw_stats)[0],
8631 ((u32 *)tp->hw_stats)[1],
8632 ((u32 *)tp->hw_stats)[2],
8633 ((u32 *)tp->hw_stats)[3]);
8634
8635 /* Mailboxes */
8636 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8637 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8638 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8639 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8640 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8641
8642 /* NIC side send descriptors. */
8643 for (i = 0; i < 6; i++) {
8644 unsigned long txd;
8645
8646 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8647 + (i * sizeof(struct tg3_tx_buffer_desc));
8648 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8649 i,
8650 readl(txd + 0x0), readl(txd + 0x4),
8651 readl(txd + 0x8), readl(txd + 0xc));
8652 }
8653
8654 /* NIC side RX descriptors. */
8655 for (i = 0; i < 6; i++) {
8656 unsigned long rxd;
8657
8658 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8659 + (i * sizeof(struct tg3_rx_buffer_desc));
8660 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8661 i,
8662 readl(rxd + 0x0), readl(rxd + 0x4),
8663 readl(rxd + 0x8), readl(rxd + 0xc));
8664 rxd += (4 * sizeof(u32));
8665 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8666 i,
8667 readl(rxd + 0x0), readl(rxd + 0x4),
8668 readl(rxd + 0x8), readl(rxd + 0xc));
8669 }
8670
8671 for (i = 0; i < 6; i++) {
8672 unsigned long rxd;
8673
8674 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8675 + (i * sizeof(struct tg3_rx_buffer_desc));
8676 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8677 i,
8678 readl(rxd + 0x0), readl(rxd + 0x4),
8679 readl(rxd + 0x8), readl(rxd + 0xc));
8680 rxd += (4 * sizeof(u32));
8681 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8682 i,
8683 readl(rxd + 0x0), readl(rxd + 0x4),
8684 readl(rxd + 0x8), readl(rxd + 0xc));
8685 }
8686}
8687#endif
8688
8689static struct net_device_stats *tg3_get_stats(struct net_device *);
8690static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8691
8692static int tg3_close(struct net_device *dev)
8693{
4f125f42 8694 int i;
1da177e4
LT		 8695 struct tg3 *tp = netdev_priv(dev);
8696
fed97810 8697 tg3_napi_disable(tp);
28e53bdd 8698 cancel_work_sync(&tp->reset_task);
7faa006f 8699
fe5f5787 8700 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8701
8702 del_timer_sync(&tp->timer);
8703
24bb4fb6
MC		 8704 tg3_phy_stop(tp);
8705
f47c11ee 8706 tg3_full_lock(tp, 1);
1da177e4
LT		 8707#if 0
8708 tg3_dump_state(tp);
8709#endif
8710
8711 tg3_disable_ints(tp);
8712
944d980e 8713 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8714 tg3_free_rings(tp);
5cf64b8a 8715 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8716
f47c11ee 8717 tg3_full_unlock(tp);
1da177e4 8718
4f125f42
MC		 8719 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8720 struct tg3_napi *tnapi = &tp->napi[i];
8721 free_irq(tnapi->irq_vec, tnapi);
8722 }
07b0173c
MC		 8723
8724 tg3_ints_fini(tp);
1da177e4
LT		 8725
8726 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8727 sizeof(tp->net_stats_prev));
8728 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8729 sizeof(tp->estats_prev));
8730
8731 tg3_free_consistent(tp);
8732
bc1c7567
MC		 8733 tg3_set_power_state(tp, PCI_D3hot);
8734
8735 netif_carrier_off(tp->dev);
8736
1da177e4
LT		 8737 return 0;
8738}
8739
8740static inline unsigned long get_stat64(tg3_stat64_t *val)
8741{
8742 unsigned long ret;
8743
8744#if (BITS_PER_LONG == 32)
8745 ret = val->low;
8746#else
8747 ret = ((u64)val->high << 32) | ((u64)val->low);
8748#endif
8749 return ret;
8750}
8751
816f8b86
SB		 8752static inline u64 get_estat64(tg3_stat64_t *val)
8753{
8754 return ((u64)val->high << 32) | ((u64)val->low);
8755}
8756
1da177e4
LT		 8757static unsigned long calc_crc_errors(struct tg3 *tp)
8758{
8759 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8760
8761 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8762 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8763 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8764 u32 val;
8765
f47c11ee 8766 spin_lock_bh(&tp->lock);
569a5df8
MC		 8767 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8768 tg3_writephy(tp, MII_TG3_TEST1,
8769 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8770 tg3_readphy(tp, 0x14, &val);
8771 } else
8772 val = 0;
f47c11ee 8773 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8774
8775 tp->phy_crc_errors += val;
8776
8777 return tp->phy_crc_errors;
8778 }
8779
8780 return get_stat64(&hw_stats->rx_fcs_errors);
8781}
8782
8783#define ESTAT_ADD(member) \
8784 estats->member = old_estats->member + \
816f8b86 8785 get_estat64(&hw_stats->member)
1da177e4
LT		 8786
8787static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8788{
8789 struct tg3_ethtool_stats *estats = &tp->estats;
8790 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8791 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8792
8793 if (!hw_stats)
8794 return old_estats;
8795
8796 ESTAT_ADD(rx_octets);
8797 ESTAT_ADD(rx_fragments);
8798 ESTAT_ADD(rx_ucast_packets);
8799 ESTAT_ADD(rx_mcast_packets);
8800 ESTAT_ADD(rx_bcast_packets);
8801 ESTAT_ADD(rx_fcs_errors);
8802 ESTAT_ADD(rx_align_errors);
8803 ESTAT_ADD(rx_xon_pause_rcvd);
8804 ESTAT_ADD(rx_xoff_pause_rcvd);
8805 ESTAT_ADD(rx_mac_ctrl_rcvd);
8806 ESTAT_ADD(rx_xoff_entered);
8807 ESTAT_ADD(rx_frame_too_long_errors);
8808 ESTAT_ADD(rx_jabbers);
8809 ESTAT_ADD(rx_undersize_packets);
8810 ESTAT_ADD(rx_in_length_errors);
8811 ESTAT_ADD(rx_out_length_errors);
8812 ESTAT_ADD(rx_64_or_less_octet_packets);
8813 ESTAT_ADD(rx_65_to_127_octet_packets);
8814 ESTAT_ADD(rx_128_to_255_octet_packets);
8815 ESTAT_ADD(rx_256_to_511_octet_packets);
8816 ESTAT_ADD(rx_512_to_1023_octet_packets);
8817 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8818 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8819 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8820 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8821 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8822
8823 ESTAT_ADD(tx_octets);
8824 ESTAT_ADD(tx_collisions);
8825 ESTAT_ADD(tx_xon_sent);
8826 ESTAT_ADD(tx_xoff_sent);
8827 ESTAT_ADD(tx_flow_control);
8828 ESTAT_ADD(tx_mac_errors);
8829 ESTAT_ADD(tx_single_collisions);
8830 ESTAT_ADD(tx_mult_collisions);
8831 ESTAT_ADD(tx_deferred);
8832 ESTAT_ADD(tx_excessive_collisions);
8833 ESTAT_ADD(tx_late_collisions);
8834 ESTAT_ADD(tx_collide_2times);
8835 ESTAT_ADD(tx_collide_3times);
8836 ESTAT_ADD(tx_collide_4times);
8837 ESTAT_ADD(tx_collide_5times);
8838 ESTAT_ADD(tx_collide_6times);
8839 ESTAT_ADD(tx_collide_7times);
8840 ESTAT_ADD(tx_collide_8times);
8841 ESTAT_ADD(tx_collide_9times);
8842 ESTAT_ADD(tx_collide_10times);
8843 ESTAT_ADD(tx_collide_11times);
8844 ESTAT_ADD(tx_collide_12times);
8845 ESTAT_ADD(tx_collide_13times);
8846 ESTAT_ADD(tx_collide_14times);
8847 ESTAT_ADD(tx_collide_15times);
8848 ESTAT_ADD(tx_ucast_packets);
8849 ESTAT_ADD(tx_mcast_packets);
8850 ESTAT_ADD(tx_bcast_packets);
8851 ESTAT_ADD(tx_carrier_sense_errors);
8852 ESTAT_ADD(tx_discards);
8853 ESTAT_ADD(tx_errors);
8854
8855 ESTAT_ADD(dma_writeq_full);
8856 ESTAT_ADD(dma_write_prioq_full);
8857 ESTAT_ADD(rxbds_empty);
8858 ESTAT_ADD(rx_discards);
8859 ESTAT_ADD(rx_errors);
8860 ESTAT_ADD(rx_threshold_hit);
8861
8862 ESTAT_ADD(dma_readq_full);
8863 ESTAT_ADD(dma_read_prioq_full);
8864 ESTAT_ADD(tx_comp_queue_full);
8865
8866 ESTAT_ADD(ring_set_send_prod_index);
8867 ESTAT_ADD(ring_status_update);
8868 ESTAT_ADD(nic_irqs);
8869 ESTAT_ADD(nic_avoided_irqs);
8870 ESTAT_ADD(nic_tx_threshold_hit);
8871
8872 return estats;
8873}
8874
8875static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8876{
8877 struct tg3 *tp = netdev_priv(dev);
8878 struct net_device_stats *stats = &tp->net_stats;
8879 struct net_device_stats *old_stats = &tp->net_stats_prev;
8880 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8881
8882 if (!hw_stats)
8883 return old_stats;
8884
8885 stats->rx_packets = old_stats->rx_packets +
8886 get_stat64(&hw_stats->rx_ucast_packets) +
8887 get_stat64(&hw_stats->rx_mcast_packets) +
8888 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8889
1da177e4
LT		 8890 stats->tx_packets = old_stats->tx_packets +
8891 get_stat64(&hw_stats->tx_ucast_packets) +
8892 get_stat64(&hw_stats->tx_mcast_packets) +
8893 get_stat64(&hw_stats->tx_bcast_packets);
8894
8895 stats->rx_bytes = old_stats->rx_bytes +
8896 get_stat64(&hw_stats->rx_octets);
8897 stats->tx_bytes = old_stats->tx_bytes +
8898 get_stat64(&hw_stats->tx_octets);
8899
8900 stats->rx_errors = old_stats->rx_errors +
4f63b877 8901 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8902 stats->tx_errors = old_stats->tx_errors +
8903 get_stat64(&hw_stats->tx_errors) +
8904 get_stat64(&hw_stats->tx_mac_errors) +
8905 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8906 get_stat64(&hw_stats->tx_discards);
8907
8908 stats->multicast = old_stats->multicast +
8909 get_stat64(&hw_stats->rx_mcast_packets);
8910 stats->collisions = old_stats->collisions +
8911 get_stat64(&hw_stats->tx_collisions);
8912
8913 stats->rx_length_errors = old_stats->rx_length_errors +
8914 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8915 get_stat64(&hw_stats->rx_undersize_packets);
8916
8917 stats->rx_over_errors = old_stats->rx_over_errors +
8918 get_stat64(&hw_stats->rxbds_empty);
8919 stats->rx_frame_errors = old_stats->rx_frame_errors +
8920 get_stat64(&hw_stats->rx_align_errors);
8921 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8922 get_stat64(&hw_stats->tx_discards);
8923 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8924 get_stat64(&hw_stats->tx_carrier_sense_errors);
8925
8926 stats->rx_crc_errors = old_stats->rx_crc_errors +
8927 calc_crc_errors(tp);
8928
4f63b877
JL		 8929 stats->rx_missed_errors = old_stats->rx_missed_errors +
8930 get_stat64(&hw_stats->rx_discards);
8931
1da177e4
LT		 8932 return stats;
8933}
8934
8935static inline u32 calc_crc(unsigned char *buf, int len)
8936{
8937 u32 reg;
8938 u32 tmp;
8939 int j, k;
8940
8941 reg = 0xffffffff;
8942
8943 for (j = 0; j < len; j++) {
8944 reg ^= buf[j];
8945
8946 for (k = 0; k < 8; k++) {
8947 tmp = reg & 0x01;
8948
8949 reg >>= 1;
8950
8951 if (tmp) {
8952 reg ^= 0xedb88320;
8953 }
8954 }
8955 }
8956
8957 return ~reg;
8958}
8959
8960static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8961{
8962 /* accept or reject all multicast frames */
8963 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8964 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8965 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8966 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8967}
8968
8969static void __tg3_set_rx_mode(struct net_device *dev)
8970{
8971 struct tg3 *tp = netdev_priv(dev);
8972 u32 rx_mode;
8973
8974 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8975 RX_MODE_KEEP_VLAN_TAG);
8976
8977 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8978 * flag clear.
8979 */
8980#if TG3_VLAN_TAG_USED
8981 if (!tp->vlgrp &&
8982 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8983 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8984#else
8985 /* By definition, VLAN is disabled always in this
8986 * case.
8987 */
8988 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8989 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8990#endif
8991
8992 if (dev->flags & IFF_PROMISC) {
8993 /* Promiscuous mode. */
8994 rx_mode |= RX_MODE_PROMISC;
8995 } else if (dev->flags & IFF_ALLMULTI) {
8996 /* Accept all multicast. */
8997 tg3_set_multi (tp, 1);
8998 } else if (dev->mc_count < 1) {
8999 /* Reject all multicast. */
9000 tg3_set_multi (tp, 0);
9001 } else {
9002 /* Accept one or more multicast(s). */
9003 struct dev_mc_list *mclist;
9004 unsigned int i;
9005 u32 mc_filter[4] = { 0, };
9006 u32 regidx;
9007 u32 bit;
9008 u32 crc;
9009
9010 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9011 i++, mclist = mclist->next) {
9012
9013 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9014 bit = ~crc & 0x7f;
9015 regidx = (bit & 0x60) >> 5;
9016 bit &= 0x1f;
9017 mc_filter[regidx] |= (1 << bit);
9018 }
9019
9020 tw32(MAC_HASH_REG_0, mc_filter[0]);
9021 tw32(MAC_HASH_REG_1, mc_filter[1]);
9022 tw32(MAC_HASH_REG_2, mc_filter[2]);
9023 tw32(MAC_HASH_REG_3, mc_filter[3]);
9024 }
9025
9026 if (rx_mode != tp->rx_mode) {
9027 tp->rx_mode = rx_mode;
9028 tw32_f(MAC_RX_MODE, rx_mode);
9029 udelay(10);
9030 }
9031}
9032
9033static void tg3_set_rx_mode(struct net_device *dev)
9034{
9035 struct tg3 *tp = netdev_priv(dev);
9036
e75f7c90
MC		 9037 if (!netif_running(dev))
9038 return;
9039
f47c11ee 9040 tg3_full_lock(tp, 0);
1da177e4 9041 __tg3_set_rx_mode(dev);
f47c11ee 9042 tg3_full_unlock(tp);
1da177e4
LT		 9043}
9044
9045#define TG3_REGDUMP_LEN (32 * 1024)
9046
9047static int tg3_get_regs_len(struct net_device *dev)
9048{
9049 return TG3_REGDUMP_LEN;
9050}
9051
9052static void tg3_get_regs(struct net_device *dev,
9053 struct ethtool_regs *regs, void *_p)
9054{
9055 u32 *p = _p;
9056 struct tg3 *tp = netdev_priv(dev);
9057 u8 *orig_p = _p;
9058 int i;
9059
9060 regs->version = 0;
9061
9062 memset(p, 0, TG3_REGDUMP_LEN);
9063
bc1c7567
MC		 9064 if (tp->link_config.phy_is_low_power)
9065 return;
9066
f47c11ee 9067 tg3_full_lock(tp, 0);
1da177e4
LT		 9068
9069#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9070#define GET_REG32_LOOP(base,len) \
9071do { p = (u32 *)(orig_p + (base)); \
9072 for (i = 0; i < len; i += 4) \
9073 __GET_REG32((base) + i); \
9074} while (0)
9075#define GET_REG32_1(reg) \
9076do { p = (u32 *)(orig_p + (reg)); \
9077 __GET_REG32((reg)); \
9078} while (0)
9079
9080 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9081 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9082 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9083 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9084 GET_REG32_1(SNDDATAC_MODE);
9085 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9086 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9087 GET_REG32_1(SNDBDC_MODE);
9088 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9089 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9090 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9091 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9092 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9093 GET_REG32_1(RCVDCC_MODE);
9094 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9095 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9096 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9097 GET_REG32_1(MBFREE_MODE);
9098 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9099 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9100 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9101 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9102 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9103 GET_REG32_1(RX_CPU_MODE);
9104 GET_REG32_1(RX_CPU_STATE);
9105 GET_REG32_1(RX_CPU_PGMCTR);
9106 GET_REG32_1(RX_CPU_HWBKPT);
9107 GET_REG32_1(TX_CPU_MODE);
9108 GET_REG32_1(TX_CPU_STATE);
9109 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9110 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9111 GET_REG32_LOOP(FTQ_RESET, 0x120);
9112 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9113 GET_REG32_1(DMAC_MODE);
9114 GET_REG32_LOOP(GRC_MODE, 0x4c);
9115 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9116 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9117
9118#undef __GET_REG32
9119#undef GET_REG32_LOOP
9120#undef GET_REG32_1
9121
f47c11ee 9122 tg3_full_unlock(tp);
1da177e4
LT		 9123}
9124
9125static int tg3_get_eeprom_len(struct net_device *dev)
9126{
9127 struct tg3 *tp = netdev_priv(dev);
9128
9129 return tp->nvram_size;
9130}
9131
1da177e4
LT		 9132static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9133{
9134 struct tg3 *tp = netdev_priv(dev);
9135 int ret;
9136 u8 *pd;
b9fc7dc5 9137 u32 i, offset, len, b_offset, b_count;
a9dc529d 9138 __be32 val;
1da177e4 9139
df259d8c
MC		 9140 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9141 return -EINVAL;
9142
bc1c7567
MC		 9143 if (tp->link_config.phy_is_low_power)
9144 return -EAGAIN;
9145
1da177e4
LT		 9146 offset = eeprom->offset;
9147 len = eeprom->len;
9148 eeprom->len = 0;
9149
9150 eeprom->magic = TG3_EEPROM_MAGIC;
9151
9152 if (offset & 3) {
9153 /* adjustments to start on required 4 byte boundary */
9154 b_offset = offset & 3;
9155 b_count = 4 - b_offset;
9156 if (b_count > len) {
9157 /* i.e. offset=1 len=2 */
9158 b_count = len;
9159 }
a9dc529d 9160 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9161 if (ret)
9162 return ret;
1da177e4
LT		 9163 memcpy(data, ((char*)&val) + b_offset, b_count);
9164 len -= b_count;
9165 offset += b_count;
9166 eeprom->len += b_count;
9167 }
9168
9169 /* read bytes upto the last 4 byte boundary */
9170 pd = &data[eeprom->len];
9171 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9172 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9173 if (ret) {
9174 eeprom->len += i;
9175 return ret;
9176 }
1da177e4
LT		 9177 memcpy(pd + i, &val, 4);
9178 }
9179 eeprom->len += i;
9180
9181 if (len & 3) {
9182 /* read last bytes not ending on 4 byte boundary */
9183 pd = &data[eeprom->len];
9184 b_count = len & 3;
9185 b_offset = offset + len - b_count;
a9dc529d 9186 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9187 if (ret)
9188 return ret;
b9fc7dc5 9189 memcpy(pd, &val, b_count);
1da177e4
LT		 9190 eeprom->len += b_count;
9191 }
9192 return 0;
9193}
9194
6aa20a22 9195static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9196
9197static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9198{
9199 struct tg3 *tp = netdev_priv(dev);
9200 int ret;
b9fc7dc5 9201 u32 offset, len, b_offset, odd_len;
1da177e4 9202 u8 *buf;
a9dc529d 9203 __be32 start, end;
1da177e4 9204
bc1c7567
MC		 9205 if (tp->link_config.phy_is_low_power)
9206 return -EAGAIN;
9207
df259d8c
MC		 9208 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9209 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9210 return -EINVAL;
9211
9212 offset = eeprom->offset;
9213 len = eeprom->len;
9214
9215 if ((b_offset = (offset & 3))) {
9216 /* adjustments to start on required 4 byte boundary */
a9dc529d 9217 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9218 if (ret)
9219 return ret;
1da177e4
LT		 9220 len += b_offset;
9221 offset &= ~3;
1c8594b4
MC		 9222 if (len < 4)
9223 len = 4;
1da177e4
LT		 9224 }
9225
9226 odd_len = 0;
1c8594b4 9227 if (len & 3) {
1da177e4
LT		 9228 /* adjustments to end on required 4 byte boundary */
9229 odd_len = 1;
9230 len = (len + 3) & ~3;
a9dc529d 9231 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9232 if (ret)
9233 return ret;
1da177e4
LT		 9234 }
9235
9236 buf = data;
9237 if (b_offset || odd_len) {
9238 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9239 if (!buf)
1da177e4
LT		 9240 return -ENOMEM;
9241 if (b_offset)
9242 memcpy(buf, &start, 4);
9243 if (odd_len)
9244 memcpy(buf+len-4, &end, 4);
9245 memcpy(buf + b_offset, data, eeprom->len);
9246 }
9247
9248 ret = tg3_nvram_write_block(tp, offset, len, buf);
9249
9250 if (buf != data)
9251 kfree(buf);
9252
9253 return ret;
9254}
9255
9256static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9257{
b02fd9e3
MC		 9258 struct tg3 *tp = netdev_priv(dev);
9259
9260 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9261 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9262 return -EAGAIN;
298cf9be 9263 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 9264 }
6aa20a22 9265
1da177e4
LT		 9266 cmd->supported = (SUPPORTED_Autoneg);
9267
9268 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9269 cmd->supported |= (SUPPORTED_1000baseT_Half |
9270 SUPPORTED_1000baseT_Full);
9271
ef348144 9272 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9273 cmd->supported |= (SUPPORTED_100baseT_Half |
9274 SUPPORTED_100baseT_Full |
9275 SUPPORTED_10baseT_Half |
9276 SUPPORTED_10baseT_Full |
3bebab59 9277 SUPPORTED_TP);
ef348144
KK		 9278 cmd->port = PORT_TP;
9279 } else {
1da177e4 9280 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9281 cmd->port = PORT_FIBRE;
9282 }
6aa20a22 9283
1da177e4
LT		 9284 cmd->advertising = tp->link_config.advertising;
9285 if (netif_running(dev)) {
9286 cmd->speed = tp->link_config.active_speed;
9287 cmd->duplex = tp->link_config.active_duplex;
9288 }
882e9793 9289 cmd->phy_address = tp->phy_addr;
7e5856bd 9290 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9291 cmd->autoneg = tp->link_config.autoneg;
9292 cmd->maxtxpkt = 0;
9293 cmd->maxrxpkt = 0;
9294 return 0;
9295}
6aa20a22 9296
1da177e4
LT		 9297static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9298{
9299 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9300
b02fd9e3
MC		 9301 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9302 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9303 return -EAGAIN;
298cf9be 9304 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 9305 }
9306
7e5856bd
MC		 9307 if (cmd->autoneg != AUTONEG_ENABLE &&
9308 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9309 return -EINVAL;
7e5856bd
MC		 9310
9311 if (cmd->autoneg == AUTONEG_DISABLE &&
9312 cmd->duplex != DUPLEX_FULL &&
9313 cmd->duplex != DUPLEX_HALF)
37ff238d 9314 return -EINVAL;
1da177e4 9315
7e5856bd
MC		 9316 if (cmd->autoneg == AUTONEG_ENABLE) {
9317 u32 mask = ADVERTISED_Autoneg |
9318 ADVERTISED_Pause |
9319 ADVERTISED_Asym_Pause;
9320
9321 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9322 mask |= ADVERTISED_1000baseT_Half |
9323 ADVERTISED_1000baseT_Full;
9324
9325 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9326 mask |= ADVERTISED_100baseT_Half |
9327 ADVERTISED_100baseT_Full |
9328 ADVERTISED_10baseT_Half |
9329 ADVERTISED_10baseT_Full |
9330 ADVERTISED_TP;
9331 else
9332 mask |= ADVERTISED_FIBRE;
9333
9334 if (cmd->advertising & ~mask)
9335 return -EINVAL;
9336
9337 mask &= (ADVERTISED_1000baseT_Half |
9338 ADVERTISED_1000baseT_Full |
9339 ADVERTISED_100baseT_Half |
9340 ADVERTISED_100baseT_Full |
9341 ADVERTISED_10baseT_Half |
9342 ADVERTISED_10baseT_Full);
9343
9344 cmd->advertising &= mask;
9345 } else {
9346 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9347 if (cmd->speed != SPEED_1000)
9348 return -EINVAL;
9349
9350 if (cmd->duplex != DUPLEX_FULL)
9351 return -EINVAL;
9352 } else {
9353 if (cmd->speed != SPEED_100 &&
9354 cmd->speed != SPEED_10)
9355 return -EINVAL;
9356 }
9357 }
9358
f47c11ee 9359 tg3_full_lock(tp, 0);
1da177e4
LT		 9360
9361 tp->link_config.autoneg = cmd->autoneg;
9362 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9363 tp->link_config.advertising = (cmd->advertising |
9364 ADVERTISED_Autoneg);
1da177e4
LT		 9365 tp->link_config.speed = SPEED_INVALID;
9366 tp->link_config.duplex = DUPLEX_INVALID;
9367 } else {
9368 tp->link_config.advertising = 0;
9369 tp->link_config.speed = cmd->speed;
9370 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9371 }
6aa20a22 9372
24fcad6b
MC		 9373 tp->link_config.orig_speed = tp->link_config.speed;
9374 tp->link_config.orig_duplex = tp->link_config.duplex;
9375 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9376
1da177e4
LT		 9377 if (netif_running(dev))
9378 tg3_setup_phy(tp, 1);
9379
f47c11ee 9380 tg3_full_unlock(tp);
6aa20a22 9381
1da177e4
LT		 9382 return 0;
9383}
6aa20a22 9384
1da177e4
LT		 9385static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9386{
9387 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9388
1da177e4
LT		 9389 strcpy(info->driver, DRV_MODULE_NAME);
9390 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9391 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9392 strcpy(info->bus_info, pci_name(tp->pdev));
9393}
6aa20a22 9394
1da177e4
LT		 9395static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9396{
9397 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9398
12dac075
RW		 9399 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9400 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9401 wol->supported = WAKE_MAGIC;
9402 else
9403 wol->supported = 0;
1da177e4 9404 wol->wolopts = 0;
05ac4cb7
MC		 9405 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9406 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9407 wol->wolopts = WAKE_MAGIC;
9408 memset(&wol->sopass, 0, sizeof(wol->sopass));
9409}
6aa20a22 9410
1da177e4
LT		 9411static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9412{
9413 struct tg3 *tp = netdev_priv(dev);
12dac075 9414 struct device *dp = &tp->pdev->dev;
6aa20a22 9415
1da177e4
LT		 9416 if (wol->wolopts & ~WAKE_MAGIC)
9417 return -EINVAL;
9418 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9419 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9420 return -EINVAL;
6aa20a22 9421
f47c11ee 9422 spin_lock_bh(&tp->lock);
12dac075 9423 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9424 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9425 device_set_wakeup_enable(dp, true);
9426 } else {
1da177e4 9427 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9428 device_set_wakeup_enable(dp, false);
9429 }
f47c11ee 9430 spin_unlock_bh(&tp->lock);
6aa20a22 9431
1da177e4
LT		 9432 return 0;
9433}
6aa20a22 9434
1da177e4
LT		 9435static u32 tg3_get_msglevel(struct net_device *dev)
9436{
9437 struct tg3 *tp = netdev_priv(dev);
9438 return tp->msg_enable;
9439}
6aa20a22 9440
1da177e4
LT		 9441static void tg3_set_msglevel(struct net_device *dev, u32 value)
9442{
9443 struct tg3 *tp = netdev_priv(dev);
9444 tp->msg_enable = value;
9445}
6aa20a22 9446
1da177e4
LT		 9447static int tg3_set_tso(struct net_device *dev, u32 value)
9448{
9449 struct tg3 *tp = netdev_priv(dev);
9450
9451 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9452 if (value)
9453 return -EINVAL;
9454 return 0;
9455 }
027455ad
MC		 9456 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9457 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9458 if (value) {
b0026624 9459 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9461 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9462 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9463 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 9464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6
MC		 9466 dev->features |= NETIF_F_TSO_ECN;
9467 } else
9468 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9469 }
1da177e4
LT		 9470 return ethtool_op_set_tso(dev, value);
9471}
6aa20a22 9472
1da177e4
LT		 9473static int tg3_nway_reset(struct net_device *dev)
9474{
9475 struct tg3 *tp = netdev_priv(dev);
1da177e4 9476 int r;
6aa20a22 9477
1da177e4
LT		 9478 if (!netif_running(dev))
9479 return -EAGAIN;
9480
c94e3941
MC		 9481 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9482 return -EINVAL;
9483
b02fd9e3
MC		 9484 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9485 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9486 return -EAGAIN;
298cf9be 9487 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9488 } else {
9489 u32 bmcr;
9490
9491 spin_lock_bh(&tp->lock);
9492 r = -EINVAL;
9493 tg3_readphy(tp, MII_BMCR, &bmcr);
9494 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9495 ((bmcr & BMCR_ANENABLE) ||
9496 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9497 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9498 BMCR_ANENABLE);
9499 r = 0;
9500 }
9501 spin_unlock_bh(&tp->lock);
1da177e4 9502 }
6aa20a22 9503
1da177e4
LT		 9504 return r;
9505}
6aa20a22 9506
1da177e4
LT		 9507static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9508{
9509 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9510
1da177e4
LT		 9511 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9512 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9513 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9514 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9515 else
9516 ering->rx_jumbo_max_pending = 0;
9517
9518 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9519
9520 ering->rx_pending = tp->rx_pending;
9521 ering->rx_mini_pending = 0;
4f81c32b
MC		 9522 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9523 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9524 else
9525 ering->rx_jumbo_pending = 0;
9526
f3f3f27e 9527 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9528}
6aa20a22 9529
1da177e4
LT		 9530static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9531{
9532 struct tg3 *tp = netdev_priv(dev);
646c9edd 9533 int i, irq_sync = 0, err = 0;
6aa20a22 9534
1da177e4
LT		 9535 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9536 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9537 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9538 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9539 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9540 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9541 return -EINVAL;
6aa20a22 9542
bbe832c0 9543 if (netif_running(dev)) {
b02fd9e3 9544 tg3_phy_stop(tp);
1da177e4 9545 tg3_netif_stop(tp);
bbe832c0
MC		 9546 irq_sync = 1;
9547 }
1da177e4 9548
bbe832c0 9549 tg3_full_lock(tp, irq_sync);
6aa20a22 9550
1da177e4
LT		 9551 tp->rx_pending = ering->rx_pending;
9552
9553 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9554 tp->rx_pending > 63)
9555 tp->rx_pending = 63;
9556 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9557
9558 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9559 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9560
9561 if (netif_running(dev)) {
944d980e 9562 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9563 err = tg3_restart_hw(tp, 1);
9564 if (!err)
9565 tg3_netif_start(tp);
1da177e4
LT		 9566 }
9567
f47c11ee 9568 tg3_full_unlock(tp);
6aa20a22 9569
b02fd9e3
MC		 9570 if (irq_sync && !err)
9571 tg3_phy_start(tp);
9572
b9ec6c1b 9573 return err;
1da177e4 9574}
6aa20a22 9575
1da177e4
LT		 9576static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9577{
9578 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9579
1da177e4 9580 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9581
e18ce346 9582 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9583 epause->rx_pause = 1;
9584 else
9585 epause->rx_pause = 0;
9586
e18ce346 9587 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9588 epause->tx_pause = 1;
9589 else
9590 epause->tx_pause = 0;
1da177e4 9591}
6aa20a22 9592
1da177e4
LT		 9593static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9594{
9595 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9596 int err = 0;
6aa20a22 9597
b02fd9e3
MC		 9598 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9599 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9600 return -EAGAIN;
1da177e4 9601
b02fd9e3
MC		 9602 if (epause->autoneg) {
9603 u32 newadv;
9604 struct phy_device *phydev;
f47c11ee 9605
298cf9be 9606 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9607
b02fd9e3
MC		 9608 if (epause->rx_pause) {
9609 if (epause->tx_pause)
9610 newadv = ADVERTISED_Pause;
9611 else
9612 newadv = ADVERTISED_Pause |
9613 ADVERTISED_Asym_Pause;
9614 } else if (epause->tx_pause) {
9615 newadv = ADVERTISED_Asym_Pause;
9616 } else
9617 newadv = 0;
9618
9619 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9620 u32 oldadv = phydev->advertising &
9621 (ADVERTISED_Pause |
9622 ADVERTISED_Asym_Pause);
9623 if (oldadv != newadv) {
9624 phydev->advertising &=
9625 ~(ADVERTISED_Pause |
9626 ADVERTISED_Asym_Pause);
9627 phydev->advertising |= newadv;
9628 err = phy_start_aneg(phydev);
9629 }
9630 } else {
9631 tp->link_config.advertising &=
9632 ~(ADVERTISED_Pause |
9633 ADVERTISED_Asym_Pause);
9634 tp->link_config.advertising |= newadv;
9635 }
9636 } else {
9637 if (epause->rx_pause)
e18ce346 9638 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9639 else
e18ce346 9640 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9641
b02fd9e3 9642 if (epause->tx_pause)
e18ce346 9643 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9644 else
e18ce346 9645 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9646
9647 if (netif_running(dev))
9648 tg3_setup_flow_control(tp, 0, 0);
9649 }
9650 } else {
9651 int irq_sync = 0;
9652
9653 if (netif_running(dev)) {
9654 tg3_netif_stop(tp);
9655 irq_sync = 1;
9656 }
9657
9658 tg3_full_lock(tp, irq_sync);
9659
9660 if (epause->autoneg)
9661 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9662 else
9663 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9664 if (epause->rx_pause)
e18ce346 9665 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9666 else
e18ce346 9667 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9668 if (epause->tx_pause)
e18ce346 9669 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9670 else
e18ce346 9671 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9672
9673 if (netif_running(dev)) {
9674 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9675 err = tg3_restart_hw(tp, 1);
9676 if (!err)
9677 tg3_netif_start(tp);
9678 }
9679
9680 tg3_full_unlock(tp);
9681 }
6aa20a22 9682
b9ec6c1b 9683 return err;
1da177e4 9684}
6aa20a22 9685
1da177e4
LT		 9686static u32 tg3_get_rx_csum(struct net_device *dev)
9687{
9688 struct tg3 *tp = netdev_priv(dev);
9689 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9690}
6aa20a22 9691
1da177e4
LT		 9692static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9693{
9694 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9695
1da177e4
LT		 9696 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9697 if (data != 0)
9698 return -EINVAL;
9699 return 0;
9700 }
6aa20a22 9701
f47c11ee 9702 spin_lock_bh(&tp->lock);
1da177e4
LT		 9703 if (data)
9704 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9705 else
9706 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9707 spin_unlock_bh(&tp->lock);
6aa20a22 9708
1da177e4
LT		 9709 return 0;
9710}
6aa20a22 9711
1da177e4
LT		 9712static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9713{
9714 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9715
1da177e4
LT		 9716 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9717 if (data != 0)
9718 return -EINVAL;
9719 return 0;
9720 }
6aa20a22 9721
321d32a0 9722 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9723 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9724 else
9c27dbdf 9725 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9726
9727 return 0;
9728}
9729
b9f2c044 9730static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9731{
b9f2c044
JG		 9732 switch (sset) {
9733 case ETH_SS_TEST:
9734 return TG3_NUM_TEST;
9735 case ETH_SS_STATS:
9736 return TG3_NUM_STATS;
9737 default:
9738 return -EOPNOTSUPP;
9739 }
4cafd3f5
MC		 9740}
9741
1da177e4
LT		 9742static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9743{
9744 switch (stringset) {
9745 case ETH_SS_STATS:
9746 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9747 break;
4cafd3f5
MC		 9748 case ETH_SS_TEST:
9749 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9750 break;
1da177e4
LT		 9751 default:
9752 WARN_ON(1); /* we need a WARN() */
9753 break;
9754 }
9755}
9756
4009a93d
MC		 9757static int tg3_phys_id(struct net_device *dev, u32 data)
9758{
9759 struct tg3 *tp = netdev_priv(dev);
9760 int i;
9761
9762 if (!netif_running(tp->dev))
9763 return -EAGAIN;
9764
9765 if (data == 0)
759afc31 9766 data = UINT_MAX / 2;
4009a93d
MC		 9767
9768 for (i = 0; i < (data * 2); i++) {
9769 if ((i % 2) == 0)
9770 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9771 LED_CTRL_1000MBPS_ON |
9772 LED_CTRL_100MBPS_ON |
9773 LED_CTRL_10MBPS_ON |
9774 LED_CTRL_TRAFFIC_OVERRIDE |
9775 LED_CTRL_TRAFFIC_BLINK |
9776 LED_CTRL_TRAFFIC_LED);
6aa20a22 9777
4009a93d
MC		 9778 else
9779 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9780 LED_CTRL_TRAFFIC_OVERRIDE);
9781
9782 if (msleep_interruptible(500))
9783 break;
9784 }
9785 tw32(MAC_LED_CTRL, tp->led_ctrl);
9786 return 0;
9787}
9788
1da177e4
LT		 9789static void tg3_get_ethtool_stats (struct net_device *dev,
9790 struct ethtool_stats *estats, u64 *tmp_stats)
9791{
9792 struct tg3 *tp = netdev_priv(dev);
9793 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9794}
9795
566f86ad 9796#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9797#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9798#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9799#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9800#define NVRAM_SELFBOOT_HW_SIZE 0x20
9801#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9802
9803static int tg3_test_nvram(struct tg3 *tp)
9804{
b9fc7dc5 9805 u32 csum, magic;
a9dc529d 9806 __be32 *buf;
ab0049b4 9807 int i, j, k, err = 0, size;
566f86ad 9808
df259d8c
MC		 9809 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9810 return 0;
9811
e4f34110 9812 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9813 return -EIO;
9814
1b27777a
MC		 9815 if (magic == TG3_EEPROM_MAGIC)
9816 size = NVRAM_TEST_SIZE;
b16250e3 9817 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9818 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9819 TG3_EEPROM_SB_FORMAT_1) {
9820 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9821 case TG3_EEPROM_SB_REVISION_0:
9822 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9823 break;
9824 case TG3_EEPROM_SB_REVISION_2:
9825 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9826 break;
9827 case TG3_EEPROM_SB_REVISION_3:
9828 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9829 break;
9830 default:
9831 return 0;
9832 }
9833 } else
1b27777a 9834 return 0;
b16250e3
MC		 9835 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9836 size = NVRAM_SELFBOOT_HW_SIZE;
9837 else
1b27777a
MC		 9838 return -EIO;
9839
9840 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9841 if (buf == NULL)
9842 return -ENOMEM;
9843
1b27777a
MC		 9844 err = -EIO;
9845 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9846 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9847 if (err)
566f86ad 9848 break;
566f86ad 9849 }
1b27777a 9850 if (i < size)
566f86ad
MC		 9851 goto out;
9852
1b27777a 9853 /* Selfboot format */
a9dc529d 9854 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9855 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9856 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9857 u8 *buf8 = (u8 *) buf, csum8 = 0;
9858
b9fc7dc5 9859 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9860 TG3_EEPROM_SB_REVISION_2) {
9861 /* For rev 2, the csum doesn't include the MBA. */
9862 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9863 csum8 += buf8[i];
9864 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9865 csum8 += buf8[i];
9866 } else {
9867 for (i = 0; i < size; i++)
9868 csum8 += buf8[i];
9869 }
1b27777a 9870
ad96b485
AB		 9871 if (csum8 == 0) {
9872 err = 0;
9873 goto out;
9874 }
9875
9876 err = -EIO;
9877 goto out;
1b27777a 9878 }
566f86ad 9879
b9fc7dc5 9880 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9881 TG3_EEPROM_MAGIC_HW) {
9882 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9883 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9884 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9885
9886 /* Separate the parity bits and the data bytes. */
9887 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9888 if ((i == 0) || (i == 8)) {
9889 int l;
9890 u8 msk;
9891
9892 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9893 parity[k++] = buf8[i] & msk;
9894 i++;
9895 }
9896 else if (i == 16) {
9897 int l;
9898 u8 msk;
9899
9900 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9901 parity[k++] = buf8[i] & msk;
9902 i++;
9903
9904 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9905 parity[k++] = buf8[i] & msk;
9906 i++;
9907 }
9908 data[j++] = buf8[i];
9909 }
9910
9911 err = -EIO;
9912 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9913 u8 hw8 = hweight8(data[i]);
9914
9915 if ((hw8 & 0x1) && parity[i])
9916 goto out;
9917 else if (!(hw8 & 0x1) && !parity[i])
9918 goto out;
9919 }
9920 err = 0;
9921 goto out;
9922 }
9923
566f86ad
MC		 9924 /* Bootstrap checksum at offset 0x10 */
9925 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9926 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9927 goto out;
9928
9929 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9930 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9931 if (csum != be32_to_cpu(buf[0xfc/4]))
9932 goto out;
566f86ad
MC		 9933
9934 err = 0;
9935
9936out:
9937 kfree(buf);
9938 return err;
9939}
9940
ca43007a
MC		 9941#define TG3_SERDES_TIMEOUT_SEC 2
9942#define TG3_COPPER_TIMEOUT_SEC 6
9943
9944static int tg3_test_link(struct tg3 *tp)
9945{
9946 int i, max;
9947
9948 if (!netif_running(tp->dev))
9949 return -ENODEV;
9950
4c987487 9951 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9952 max = TG3_SERDES_TIMEOUT_SEC;
9953 else
9954 max = TG3_COPPER_TIMEOUT_SEC;
9955
9956 for (i = 0; i < max; i++) {
9957 if (netif_carrier_ok(tp->dev))
9958 return 0;
9959
9960 if (msleep_interruptible(1000))
9961 break;
9962 }
9963
9964 return -EIO;
9965}
9966
a71116d1 9967/* Only test the commonly used registers */
30ca3e37 9968static int tg3_test_registers(struct tg3 *tp)
a71116d1 9969{
b16250e3 9970 int i, is_5705, is_5750;
a71116d1
MC		 9971 u32 offset, read_mask, write_mask, val, save_val, read_val;
9972 static struct {
9973 u16 offset;
9974 u16 flags;
9975#define TG3_FL_5705 0x1
9976#define TG3_FL_NOT_5705 0x2
9977#define TG3_FL_NOT_5788 0x4
b16250e3 9978#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9979 u32 read_mask;
9980 u32 write_mask;
9981 } reg_tbl[] = {
9982 /* MAC Control Registers */
9983 { MAC_MODE, TG3_FL_NOT_5705,
9984 0x00000000, 0x00ef6f8c },
9985 { MAC_MODE, TG3_FL_5705,
9986 0x00000000, 0x01ef6b8c },
9987 { MAC_STATUS, TG3_FL_NOT_5705,
9988 0x03800107, 0x00000000 },
9989 { MAC_STATUS, TG3_FL_5705,
9990 0x03800100, 0x00000000 },
9991 { MAC_ADDR_0_HIGH, 0x0000,
9992 0x00000000, 0x0000ffff },
9993 { MAC_ADDR_0_LOW, 0x0000,
9994 0x00000000, 0xffffffff },
9995 { MAC_RX_MTU_SIZE, 0x0000,
9996 0x00000000, 0x0000ffff },
9997 { MAC_TX_MODE, 0x0000,
9998 0x00000000, 0x00000070 },
9999 { MAC_TX_LENGTHS, 0x0000,
10000 0x00000000, 0x00003fff },
10001 { MAC_RX_MODE, TG3_FL_NOT_5705,
10002 0x00000000, 0x000007fc },
10003 { MAC_RX_MODE, TG3_FL_5705,
10004 0x00000000, 0x000007dc },
10005 { MAC_HASH_REG_0, 0x0000,
10006 0x00000000, 0xffffffff },
10007 { MAC_HASH_REG_1, 0x0000,
10008 0x00000000, 0xffffffff },
10009 { MAC_HASH_REG_2, 0x0000,
10010 0x00000000, 0xffffffff },
10011 { MAC_HASH_REG_3, 0x0000,
10012 0x00000000, 0xffffffff },
10013
10014 /* Receive Data and Receive BD Initiator Control Registers. */
10015 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10016 0x00000000, 0xffffffff },
10017 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10018 0x00000000, 0xffffffff },
10019 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10020 0x00000000, 0x00000003 },
10021 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10022 0x00000000, 0xffffffff },
10023 { RCVDBDI_STD_BD+0, 0x0000,
10024 0x00000000, 0xffffffff },
10025 { RCVDBDI_STD_BD+4, 0x0000,
10026 0x00000000, 0xffffffff },
10027 { RCVDBDI_STD_BD+8, 0x0000,
10028 0x00000000, 0xffff0002 },
10029 { RCVDBDI_STD_BD+0xc, 0x0000,
10030 0x00000000, 0xffffffff },
6aa20a22 10031
a71116d1
MC		 10032 /* Receive BD Initiator Control Registers. */
10033 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10034 0x00000000, 0xffffffff },
10035 { RCVBDI_STD_THRESH, TG3_FL_5705,
10036 0x00000000, 0x000003ff },
10037 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10038 0x00000000, 0xffffffff },
6aa20a22 10039
a71116d1
MC		 10040 /* Host Coalescing Control Registers. */
10041 { HOSTCC_MODE, TG3_FL_NOT_5705,
10042 0x00000000, 0x00000004 },
10043 { HOSTCC_MODE, TG3_FL_5705,
10044 0x00000000, 0x000000f6 },
10045 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10046 0x00000000, 0xffffffff },
10047 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10048 0x00000000, 0x000003ff },
10049 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10050 0x00000000, 0xffffffff },
10051 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10052 0x00000000, 0x000003ff },
10053 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10054 0x00000000, 0xffffffff },
10055 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10056 0x00000000, 0x000000ff },
10057 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10058 0x00000000, 0xffffffff },
10059 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10060 0x00000000, 0x000000ff },
10061 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10062 0x00000000, 0xffffffff },
10063 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10064 0x00000000, 0xffffffff },
10065 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10066 0x00000000, 0xffffffff },
10067 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10068 0x00000000, 0x000000ff },
10069 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10070 0x00000000, 0xffffffff },
10071 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10072 0x00000000, 0x000000ff },
10073 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10074 0x00000000, 0xffffffff },
10075 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10076 0x00000000, 0xffffffff },
10077 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10078 0x00000000, 0xffffffff },
10079 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10080 0x00000000, 0xffffffff },
10081 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10082 0x00000000, 0xffffffff },
10083 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10084 0xffffffff, 0x00000000 },
10085 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10086 0xffffffff, 0x00000000 },
10087
10088 /* Buffer Manager Control Registers. */
b16250e3 10089 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10090 0x00000000, 0x007fff80 },
b16250e3 10091 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10092 0x00000000, 0x007fffff },
10093 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10094 0x00000000, 0x0000003f },
10095 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10096 0x00000000, 0x000001ff },
10097 { BUFMGR_MB_HIGH_WATER, 0x0000,
10098 0x00000000, 0x000001ff },
10099 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10100 0xffffffff, 0x00000000 },
10101 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10102 0xffffffff, 0x00000000 },
6aa20a22 10103
a71116d1
MC		 10104 /* Mailbox Registers */
10105 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10106 0x00000000, 0x000001ff },
10107 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10108 0x00000000, 0x000001ff },
10109 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10110 0x00000000, 0x000007ff },
10111 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10112 0x00000000, 0x000001ff },
10113
10114 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10115 };
10116
b16250e3
MC		 10117 is_5705 = is_5750 = 0;
10118 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10119 is_5705 = 1;
b16250e3
MC		 10120 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10121 is_5750 = 1;
10122 }
a71116d1
MC		 10123
10124 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10125 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10126 continue;
10127
10128 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10129 continue;
10130
10131 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10132 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10133 continue;
10134
b16250e3
MC		 10135 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10136 continue;
10137
a71116d1
MC		 10138 offset = (u32) reg_tbl[i].offset;
10139 read_mask = reg_tbl[i].read_mask;
10140 write_mask = reg_tbl[i].write_mask;
10141
10142 /* Save the original register content */
10143 save_val = tr32(offset);
10144
10145 /* Determine the read-only value. */
10146 read_val = save_val & read_mask;
10147
10148 /* Write zero to the register, then make sure the read-only bits
10149 * are not changed and the read/write bits are all zeros.
10150 */
10151 tw32(offset, 0);
10152
10153 val = tr32(offset);
10154
10155 /* Test the read-only and read/write bits. */
10156 if (((val & read_mask) != read_val) || (val & write_mask))
10157 goto out;
10158
10159 /* Write ones to all the bits defined by RdMask and WrMask, then
10160 * make sure the read-only bits are not changed and the
10161 * read/write bits are all ones.
10162 */
10163 tw32(offset, read_mask | write_mask);
10164
10165 val = tr32(offset);
10166
10167 /* Test the read-only bits. */
10168 if ((val & read_mask) != read_val)
10169 goto out;
10170
10171 /* Test the read/write bits. */
10172 if ((val & write_mask) != write_mask)
10173 goto out;
10174
10175 tw32(offset, save_val);
10176 }
10177
10178 return 0;
10179
10180out:
9f88f29f
MC		 10181 if (netif_msg_hw(tp))
10182 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10183 offset);
a71116d1
MC		 10184 tw32(offset, save_val);
10185 return -EIO;
10186}
10187
7942e1db
MC		 10188static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10189{
f71e1309 10190 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10191 int i;
10192 u32 j;
10193
e9edda69 10194 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10195 for (j = 0; j < len; j += 4) {
10196 u32 val;
10197
10198 tg3_write_mem(tp, offset + j, test_pattern[i]);
10199 tg3_read_mem(tp, offset + j, &val);
10200 if (val != test_pattern[i])
10201 return -EIO;
10202 }
10203 }
10204 return 0;
10205}
10206
10207static int tg3_test_memory(struct tg3 *tp)
10208{
10209 static struct mem_entry {
10210 u32 offset;
10211 u32 len;
10212 } mem_tbl_570x[] = {
38690194 10213 { 0x00000000, 0x00b50},
7942e1db
MC		 10214 { 0x00002000, 0x1c000},
10215 { 0xffffffff, 0x00000}
10216 }, mem_tbl_5705[] = {
10217 { 0x00000100, 0x0000c},
10218 { 0x00000200, 0x00008},
7942e1db
MC		 10219 { 0x00004000, 0x00800},
10220 { 0x00006000, 0x01000},
10221 { 0x00008000, 0x02000},
10222 { 0x00010000, 0x0e000},
10223 { 0xffffffff, 0x00000}
79f4d13a
MC		 10224 }, mem_tbl_5755[] = {
10225 { 0x00000200, 0x00008},
10226 { 0x00004000, 0x00800},
10227 { 0x00006000, 0x00800},
10228 { 0x00008000, 0x02000},
10229 { 0x00010000, 0x0c000},
10230 { 0xffffffff, 0x00000}
b16250e3
MC		 10231 }, mem_tbl_5906[] = {
10232 { 0x00000200, 0x00008},
10233 { 0x00004000, 0x00400},
10234 { 0x00006000, 0x00400},
10235 { 0x00008000, 0x01000},
10236 { 0x00010000, 0x01000},
10237 { 0xffffffff, 0x00000}
7942e1db
MC		 10238 };
10239 struct mem_entry *mem_tbl;
10240 int err = 0;
10241 int i;
10242
321d32a0
MC		 10243 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10244 mem_tbl = mem_tbl_5755;
10245 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10246 mem_tbl = mem_tbl_5906;
10247 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10248 mem_tbl = mem_tbl_5705;
10249 else
7942e1db
MC		 10250 mem_tbl = mem_tbl_570x;
10251
10252 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10253 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10254 mem_tbl[i].len)) != 0)
10255 break;
10256 }
6aa20a22 10257
7942e1db
MC		 10258 return err;
10259}
10260
9f40dead
MC		 10261#define TG3_MAC_LOOPBACK 0
10262#define TG3_PHY_LOOPBACK 1
10263
10264static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10265{
9f40dead 10266 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10267 u32 desc_idx, coal_now;
c76949a6
MC		 10268 struct sk_buff *skb, *rx_skb;
10269 u8 *tx_data;
10270 dma_addr_t map;
10271 int num_pkts, tx_len, rx_len, i, err;
10272 struct tg3_rx_buffer_desc *desc;
898a56f8 10273 struct tg3_napi *tnapi, *rnapi;
21f581a5 10274 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10275
0c1d0e2b
MC		 10276 if (tp->irq_cnt > 1) {
10277 tnapi = &tp->napi[1];
10278 rnapi = &tp->napi[1];
10279 } else {
10280 tnapi = &tp->napi[0];
10281 rnapi = &tp->napi[0];
10282 }
fd2ce37f 10283 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10284
9f40dead 10285 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10286 /* HW errata - mac loopback fails in some cases on 5780.
10287 * Normal traffic and PHY loopback are not affected by
10288 * errata.
10289 */
10290 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10291 return 0;
10292
9f40dead 10293 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10294 MAC_MODE_PORT_INT_LPBACK;
10295 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10296 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10297 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10298 mac_mode |= MAC_MODE_PORT_MODE_MII;
10299 else
10300 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10301 tw32(MAC_MODE, mac_mode);
10302 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10303 u32 val;
10304
7f97a4bd
MC		 10305 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10306 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10307 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10308 } else
10309 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10310
9ef8ca99
MC		 10311 tg3_phy_toggle_automdix(tp, 0);
10312
3f7045c1 10313 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10314 udelay(40);
5d64ad34 10315
e8f3f6ca 10316 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10317 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10319 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10320 mac_mode |= MAC_MODE_PORT_MODE_MII;
10321 } else
10322 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10323
c94e3941
MC		 10324 /* reset to prevent losing 1st rx packet intermittently */
10325 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10326 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10327 udelay(10);
10328 tw32_f(MAC_RX_MODE, tp->rx_mode);
10329 }
e8f3f6ca
MC		 10330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10331 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10332 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10333 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10334 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10335 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10336 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10337 }
9f40dead 10338 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10339 }
10340 else
10341 return -EINVAL;
c76949a6
MC		 10342
10343 err = -EIO;
10344
c76949a6 10345 tx_len = 1514;
a20e9c62 10346 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10347 if (!skb)
10348 return -ENOMEM;
10349
c76949a6
MC		 10350 tx_data = skb_put(skb, tx_len);
10351 memcpy(tx_data, tp->dev->dev_addr, 6);
10352 memset(tx_data + 6, 0x0, 8);
10353
10354 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10355
10356 for (i = 14; i < tx_len; i++)
10357 tx_data[i] = (u8) (i & 0xff);
10358
10359 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10360
10361 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10362 rnapi->coal_now);
c76949a6
MC		 10363
10364 udelay(10);
10365
898a56f8 10366 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10367
c76949a6
MC		 10368 num_pkts = 0;
10369
f3f3f27e 10370 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10371
f3f3f27e 10372 tnapi->tx_prod++;
c76949a6
MC		 10373 num_pkts++;
10374
f3f3f27e
MC		 10375 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10376 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10377
10378 udelay(10);
10379
3f7045c1
MC		 10380 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10381 for (i = 0; i < 25; i++) {
c76949a6 10382 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10383 coal_now);
c76949a6
MC		 10384
10385 udelay(10);
10386
898a56f8
MC		 10387 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10388 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10389 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10390 (rx_idx == (rx_start_idx + num_pkts)))
10391 break;
10392 }
10393
10394 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10395 dev_kfree_skb(skb);
10396
f3f3f27e 10397 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10398 goto out;
10399
10400 if (rx_idx != rx_start_idx + num_pkts)
10401 goto out;
10402
72334482 10403 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10404 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10405 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10406 if (opaque_key != RXD_OPAQUE_RING_STD)
10407 goto out;
10408
10409 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10410 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10411 goto out;
10412
10413 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10414 if (rx_len != tx_len)
10415 goto out;
10416
21f581a5 10417 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10418
21f581a5 10419 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10420 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10421
10422 for (i = 14; i < tx_len; i++) {
10423 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10424 goto out;
10425 }
10426 err = 0;
6aa20a22 10427
c76949a6
MC		 10428 /* tg3_free_rings will unmap and free the rx_skb */
10429out:
10430 return err;
10431}
10432
9f40dead
MC		 10433#define TG3_MAC_LOOPBACK_FAILED 1
10434#define TG3_PHY_LOOPBACK_FAILED 2
10435#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10436 TG3_PHY_LOOPBACK_FAILED)
10437
10438static int tg3_test_loopback(struct tg3 *tp)
10439{
10440 int err = 0;
9936bcf6 10441 u32 cpmuctrl = 0;
9f40dead
MC		 10442
10443 if (!netif_running(tp->dev))
10444 return TG3_LOOPBACK_FAILED;
10445
b9ec6c1b
MC		 10446 err = tg3_reset_hw(tp, 1);
10447 if (err)
10448 return TG3_LOOPBACK_FAILED;
9f40dead 10449
6833c043
MC		 10450 /* Turn off gphy autopowerdown. */
10451 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10452 tg3_phy_toggle_apd(tp, false);
10453
321d32a0 10454 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10455 int i;
10456 u32 status;
10457
10458 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10459
10460 /* Wait for up to 40 microseconds to acquire lock. */
10461 for (i = 0; i < 4; i++) {
10462 status = tr32(TG3_CPMU_MUTEX_GNT);
10463 if (status == CPMU_MUTEX_GNT_DRIVER)
10464 break;
10465 udelay(10);
10466 }
10467
10468 if (status != CPMU_MUTEX_GNT_DRIVER)
10469 return TG3_LOOPBACK_FAILED;
10470
b2a5c19c 10471 /* Turn off link-based power management. */
e875093c 10472 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10473 tw32(TG3_CPMU_CTRL,
10474 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10475 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10476 }
10477
9f40dead
MC		 10478 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10479 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10480
321d32a0 10481 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10482 tw32(TG3_CPMU_CTRL, cpmuctrl);
10483
10484 /* Release the mutex */
10485 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10486 }
10487
dd477003
MC		 10488 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10489 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10490 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10491 err |= TG3_PHY_LOOPBACK_FAILED;
10492 }
10493
6833c043
MC		 10494 /* Re-enable gphy autopowerdown. */
10495 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10496 tg3_phy_toggle_apd(tp, true);
10497
9f40dead
MC		 10498 return err;
10499}
10500
4cafd3f5
MC		 10501static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10502 u64 *data)
10503{
566f86ad
MC		 10504 struct tg3 *tp = netdev_priv(dev);
10505
bc1c7567
MC		 10506 if (tp->link_config.phy_is_low_power)
10507 tg3_set_power_state(tp, PCI_D0);
10508
566f86ad
MC		 10509 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10510
10511 if (tg3_test_nvram(tp) != 0) {
10512 etest->flags |= ETH_TEST_FL_FAILED;
10513 data[0] = 1;
10514 }
ca43007a
MC		 10515 if (tg3_test_link(tp) != 0) {
10516 etest->flags |= ETH_TEST_FL_FAILED;
10517 data[1] = 1;
10518 }
a71116d1 10519 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10520 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10521
10522 if (netif_running(dev)) {
b02fd9e3 10523 tg3_phy_stop(tp);
a71116d1 10524 tg3_netif_stop(tp);
bbe832c0
MC		 10525 irq_sync = 1;
10526 }
a71116d1 10527
bbe832c0 10528 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10529
10530 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10531 err = tg3_nvram_lock(tp);
a71116d1
MC		 10532 tg3_halt_cpu(tp, RX_CPU_BASE);
10533 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10534 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10535 if (!err)
10536 tg3_nvram_unlock(tp);
a71116d1 10537
d9ab5ad1
MC		 10538 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10539 tg3_phy_reset(tp);
10540
a71116d1
MC		 10541 if (tg3_test_registers(tp) != 0) {
10542 etest->flags |= ETH_TEST_FL_FAILED;
10543 data[2] = 1;
10544 }
7942e1db
MC		 10545 if (tg3_test_memory(tp) != 0) {
10546 etest->flags |= ETH_TEST_FL_FAILED;
10547 data[3] = 1;
10548 }
9f40dead 10549 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10550 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10551
f47c11ee
DM		 10552 tg3_full_unlock(tp);
10553
d4bc3927
MC		 10554 if (tg3_test_interrupt(tp) != 0) {
10555 etest->flags |= ETH_TEST_FL_FAILED;
10556 data[5] = 1;
10557 }
f47c11ee
DM		 10558
10559 tg3_full_lock(tp, 0);
d4bc3927 10560
a71116d1
MC		 10561 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10562 if (netif_running(dev)) {
10563 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10564 err2 = tg3_restart_hw(tp, 1);
10565 if (!err2)
b9ec6c1b 10566 tg3_netif_start(tp);
a71116d1 10567 }
f47c11ee
DM		 10568
10569 tg3_full_unlock(tp);
b02fd9e3
MC		 10570
10571 if (irq_sync && !err2)
10572 tg3_phy_start(tp);
a71116d1 10573 }
bc1c7567
MC		 10574 if (tp->link_config.phy_is_low_power)
10575 tg3_set_power_state(tp, PCI_D3hot);
10576
4cafd3f5
MC		 10577}
10578
1da177e4
LT		 10579static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10580{
10581 struct mii_ioctl_data *data = if_mii(ifr);
10582 struct tg3 *tp = netdev_priv(dev);
10583 int err;
10584
b02fd9e3
MC		 10585 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10586 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10587 return -EAGAIN;
298cf9be 10588 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10589 }
10590
1da177e4
LT		 10591 switch(cmd) {
10592 case SIOCGMIIPHY:
882e9793 10593 data->phy_id = tp->phy_addr;
1da177e4
LT		 10594
10595 /* fallthru */
10596 case SIOCGMIIREG: {
10597 u32 mii_regval;
10598
10599 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10600 break; /* We have no PHY */
10601
bc1c7567
MC		 10602 if (tp->link_config.phy_is_low_power)
10603 return -EAGAIN;
10604
f47c11ee 10605 spin_lock_bh(&tp->lock);
1da177e4 10606 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10607 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10608
10609 data->val_out = mii_regval;
10610
10611 return err;
10612 }
10613
10614 case SIOCSMIIREG:
10615 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10616 break; /* We have no PHY */
10617
bc1c7567
MC		 10618 if (tp->link_config.phy_is_low_power)
10619 return -EAGAIN;
10620
f47c11ee 10621 spin_lock_bh(&tp->lock);
1da177e4 10622 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10623 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10624
10625 return err;
10626
10627 default:
10628 /* do nothing */
10629 break;
10630 }
10631 return -EOPNOTSUPP;
10632}
10633
10634#if TG3_VLAN_TAG_USED
10635static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10636{
10637 struct tg3 *tp = netdev_priv(dev);
10638
844b3eed
MC		 10639 if (!netif_running(dev)) {
10640 tp->vlgrp = grp;
10641 return;
10642 }
10643
10644 tg3_netif_stop(tp);
29315e87 10645
f47c11ee 10646 tg3_full_lock(tp, 0);
1da177e4
LT		 10647
10648 tp->vlgrp = grp;
10649
10650 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10651 __tg3_set_rx_mode(dev);
10652
844b3eed 10653 tg3_netif_start(tp);
46966545
MC		 10654
10655 tg3_full_unlock(tp);
1da177e4 10656}
1da177e4
LT		 10657#endif
10658
15f9850d
DM		 10659static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10660{
10661 struct tg3 *tp = netdev_priv(dev);
10662
10663 memcpy(ec, &tp->coal, sizeof(*ec));
10664 return 0;
10665}
10666
d244c892
MC		 10667static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10668{
10669 struct tg3 *tp = netdev_priv(dev);
10670 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10671 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10672
10673 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10674 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10675 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10676 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10677 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10678 }
10679
10680 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10681 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10682 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10683 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10684 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10685 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10686 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10687 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10688 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10689 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10690 return -EINVAL;
10691
10692 /* No rx interrupts will be generated if both are zero */
10693 if ((ec->rx_coalesce_usecs == 0) &&
10694 (ec->rx_max_coalesced_frames == 0))
10695 return -EINVAL;
10696
10697 /* No tx interrupts will be generated if both are zero */
10698 if ((ec->tx_coalesce_usecs == 0) &&
10699 (ec->tx_max_coalesced_frames == 0))
10700 return -EINVAL;
10701
10702 /* Only copy relevant parameters, ignore all others. */
10703 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10704 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10705 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10706 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10707 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10708 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10709 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10710 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10711 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10712
10713 if (netif_running(dev)) {
10714 tg3_full_lock(tp, 0);
10715 __tg3_set_coalesce(tp, &tp->coal);
10716 tg3_full_unlock(tp);
10717 }
10718 return 0;
10719}
10720
7282d491 10721static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10722 .get_settings = tg3_get_settings,
10723 .set_settings = tg3_set_settings,
10724 .get_drvinfo = tg3_get_drvinfo,
10725 .get_regs_len = tg3_get_regs_len,
10726 .get_regs = tg3_get_regs,
10727 .get_wol = tg3_get_wol,
10728 .set_wol = tg3_set_wol,
10729 .get_msglevel = tg3_get_msglevel,
10730 .set_msglevel = tg3_set_msglevel,
10731 .nway_reset = tg3_nway_reset,
10732 .get_link = ethtool_op_get_link,
10733 .get_eeprom_len = tg3_get_eeprom_len,
10734 .get_eeprom = tg3_get_eeprom,
10735 .set_eeprom = tg3_set_eeprom,
10736 .get_ringparam = tg3_get_ringparam,
10737 .set_ringparam = tg3_set_ringparam,
10738 .get_pauseparam = tg3_get_pauseparam,
10739 .set_pauseparam = tg3_set_pauseparam,
10740 .get_rx_csum = tg3_get_rx_csum,
10741 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10742 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10743 .set_sg = ethtool_op_set_sg,
1da177e4 10744 .set_tso = tg3_set_tso,
4cafd3f5 10745 .self_test = tg3_self_test,
1da177e4 10746 .get_strings = tg3_get_strings,
4009a93d 10747 .phys_id = tg3_phys_id,
1da177e4 10748 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10749 .get_coalesce = tg3_get_coalesce,
d244c892 10750 .set_coalesce = tg3_set_coalesce,
b9f2c044 10751 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10752};
10753
10754static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10755{
1b27777a 10756 u32 cursize, val, magic;
1da177e4
LT		 10757
10758 tp->nvram_size = EEPROM_CHIP_SIZE;
10759
e4f34110 10760 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10761 return;
10762
b16250e3
MC		 10763 if ((magic != TG3_EEPROM_MAGIC) &&
10764 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10765 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10766 return;
10767
10768 /*
10769 * Size the chip by reading offsets at increasing powers of two.
10770 * When we encounter our validation signature, we know the addressing
10771 * has wrapped around, and thus have our chip size.
10772 */
1b27777a 10773 cursize = 0x10;
1da177e4
LT		 10774
10775 while (cursize < tp->nvram_size) {
e4f34110 10776 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10777 return;
10778
1820180b 10779 if (val == magic)
1da177e4
LT		 10780 break;
10781
10782 cursize <<= 1;
10783 }
10784
10785 tp->nvram_size = cursize;
10786}
6aa20a22 10787
1da177e4
LT		 10788static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10789{
10790 u32 val;
10791
df259d8c
MC		 10792 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10793 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10794 return;
10795
10796 /* Selfboot format */
1820180b 10797 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10798 tg3_get_eeprom_size(tp);
10799 return;
10800 }
10801
6d348f2c 10802 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10803 if (val != 0) {
6d348f2c
MC		 10804 /* This is confusing. We want to operate on the
10805 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10806 * call will read from NVRAM and byteswap the data
10807 * according to the byteswapping settings for all
10808 * other register accesses. This ensures the data we
10809 * want will always reside in the lower 16-bits.
10810 * However, the data in NVRAM is in LE format, which
10811 * means the data from the NVRAM read will always be
10812 * opposite the endianness of the CPU. The 16-bit
10813 * byteswap then brings the data to CPU endianness.
10814 */
10815 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10816 return;
10817 }
10818 }
fd1122a2 10819 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10820}
10821
10822static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10823{
10824 u32 nvcfg1;
10825
10826 nvcfg1 = tr32(NVRAM_CFG1);
10827 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10828 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10829 } else {
1da177e4
LT		 10830 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10831 tw32(NVRAM_CFG1, nvcfg1);
10832 }
10833
4c987487 10834 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10835 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10836 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10837 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10838 tp->nvram_jedecnum = JEDEC_ATMEL;
10839 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10840 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10841 break;
10842 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10843 tp->nvram_jedecnum = JEDEC_ATMEL;
10844 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10845 break;
10846 case FLASH_VENDOR_ATMEL_EEPROM:
10847 tp->nvram_jedecnum = JEDEC_ATMEL;
10848 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10849 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10850 break;
10851 case FLASH_VENDOR_ST:
10852 tp->nvram_jedecnum = JEDEC_ST;
10853 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10854 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10855 break;
10856 case FLASH_VENDOR_SAIFUN:
10857 tp->nvram_jedecnum = JEDEC_SAIFUN;
10858 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10859 break;
10860 case FLASH_VENDOR_SST_SMALL:
10861 case FLASH_VENDOR_SST_LARGE:
10862 tp->nvram_jedecnum = JEDEC_SST;
10863 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10864 break;
1da177e4 10865 }
8590a603 10866 } else {
1da177e4
LT		 10867 tp->nvram_jedecnum = JEDEC_ATMEL;
10868 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10869 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10870 }
10871}
10872
a1b950d5
MC		 10873static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10874{
10875 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10876 case FLASH_5752PAGE_SIZE_256:
10877 tp->nvram_pagesize = 256;
10878 break;
10879 case FLASH_5752PAGE_SIZE_512:
10880 tp->nvram_pagesize = 512;
10881 break;
10882 case FLASH_5752PAGE_SIZE_1K:
10883 tp->nvram_pagesize = 1024;
10884 break;
10885 case FLASH_5752PAGE_SIZE_2K:
10886 tp->nvram_pagesize = 2048;
10887 break;
10888 case FLASH_5752PAGE_SIZE_4K:
10889 tp->nvram_pagesize = 4096;
10890 break;
10891 case FLASH_5752PAGE_SIZE_264:
10892 tp->nvram_pagesize = 264;
10893 break;
10894 case FLASH_5752PAGE_SIZE_528:
10895 tp->nvram_pagesize = 528;
10896 break;
10897 }
10898}
10899
361b4ac2
MC		 10900static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10901{
10902 u32 nvcfg1;
10903
10904 nvcfg1 = tr32(NVRAM_CFG1);
10905
e6af301b
MC		 10906 /* NVRAM protection for TPM */
10907 if (nvcfg1 & (1 << 27))
10908 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10909
361b4ac2 10910 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10911 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10912 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10913 tp->nvram_jedecnum = JEDEC_ATMEL;
10914 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10915 break;
10916 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10917 tp->nvram_jedecnum = JEDEC_ATMEL;
10918 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10919 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10920 break;
10921 case FLASH_5752VENDOR_ST_M45PE10:
10922 case FLASH_5752VENDOR_ST_M45PE20:
10923 case FLASH_5752VENDOR_ST_M45PE40:
10924 tp->nvram_jedecnum = JEDEC_ST;
10925 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10926 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10927 break;
361b4ac2
MC		 10928 }
10929
10930 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 10931 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 10932 } else {
361b4ac2
MC		 10933 /* For eeprom, set pagesize to maximum eeprom size */
10934 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10935
10936 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10937 tw32(NVRAM_CFG1, nvcfg1);
10938 }
10939}
10940
d3c7b886
MC		 10941static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10942{
989a9d23 10943 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10944
10945 nvcfg1 = tr32(NVRAM_CFG1);
10946
10947 /* NVRAM protection for TPM */
989a9d23 10948 if (nvcfg1 & (1 << 27)) {
d3c7b886 10949 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10950 protect = 1;
10951 }
d3c7b886 10952
989a9d23
MC		 10953 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10954 switch (nvcfg1) {
8590a603
MC		 10955 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10956 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10957 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10958 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10959 tp->nvram_jedecnum = JEDEC_ATMEL;
10960 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10961 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10962 tp->nvram_pagesize = 264;
10963 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10964 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10965 tp->nvram_size = (protect ? 0x3e200 :
10966 TG3_NVRAM_SIZE_512KB);
10967 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10968 tp->nvram_size = (protect ? 0x1f200 :
10969 TG3_NVRAM_SIZE_256KB);
10970 else
10971 tp->nvram_size = (protect ? 0x1f200 :
10972 TG3_NVRAM_SIZE_128KB);
10973 break;
10974 case FLASH_5752VENDOR_ST_M45PE10:
10975 case FLASH_5752VENDOR_ST_M45PE20:
10976 case FLASH_5752VENDOR_ST_M45PE40:
10977 tp->nvram_jedecnum = JEDEC_ST;
10978 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10979 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10980 tp->nvram_pagesize = 256;
10981 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10982 tp->nvram_size = (protect ?
10983 TG3_NVRAM_SIZE_64KB :
10984 TG3_NVRAM_SIZE_128KB);
10985 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10986 tp->nvram_size = (protect ?
10987 TG3_NVRAM_SIZE_64KB :
10988 TG3_NVRAM_SIZE_256KB);
10989 else
10990 tp->nvram_size = (protect ?
10991 TG3_NVRAM_SIZE_128KB :
10992 TG3_NVRAM_SIZE_512KB);
10993 break;
d3c7b886
MC		 10994 }
10995}
10996
1b27777a
MC		 10997static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10998{
10999 u32 nvcfg1;
11000
11001 nvcfg1 = tr32(NVRAM_CFG1);
11002
11003 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11004 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11005 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11006 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11007 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11008 tp->nvram_jedecnum = JEDEC_ATMEL;
11009 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11010 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11011
8590a603
MC		 11012 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11013 tw32(NVRAM_CFG1, nvcfg1);
11014 break;
11015 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11016 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11017 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11018 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11019 tp->nvram_jedecnum = JEDEC_ATMEL;
11020 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11021 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11022 tp->nvram_pagesize = 264;
11023 break;
11024 case FLASH_5752VENDOR_ST_M45PE10:
11025 case FLASH_5752VENDOR_ST_M45PE20:
11026 case FLASH_5752VENDOR_ST_M45PE40:
11027 tp->nvram_jedecnum = JEDEC_ST;
11028 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11029 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11030 tp->nvram_pagesize = 256;
11031 break;
1b27777a
MC		 11032 }
11033}
11034
6b91fa02
MC		 11035static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11036{
11037 u32 nvcfg1, protect = 0;
11038
11039 nvcfg1 = tr32(NVRAM_CFG1);
11040
11041 /* NVRAM protection for TPM */
11042 if (nvcfg1 & (1 << 27)) {
11043 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11044 protect = 1;
11045 }
11046
11047 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11048 switch (nvcfg1) {
8590a603
MC		 11049 case FLASH_5761VENDOR_ATMEL_ADB021D:
11050 case FLASH_5761VENDOR_ATMEL_ADB041D:
11051 case FLASH_5761VENDOR_ATMEL_ADB081D:
11052 case FLASH_5761VENDOR_ATMEL_ADB161D:
11053 case FLASH_5761VENDOR_ATMEL_MDB021D:
11054 case FLASH_5761VENDOR_ATMEL_MDB041D:
11055 case FLASH_5761VENDOR_ATMEL_MDB081D:
11056 case FLASH_5761VENDOR_ATMEL_MDB161D:
11057 tp->nvram_jedecnum = JEDEC_ATMEL;
11058 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11059 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11060 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11061 tp->nvram_pagesize = 256;
11062 break;
11063 case FLASH_5761VENDOR_ST_A_M45PE20:
11064 case FLASH_5761VENDOR_ST_A_M45PE40:
11065 case FLASH_5761VENDOR_ST_A_M45PE80:
11066 case FLASH_5761VENDOR_ST_A_M45PE16:
11067 case FLASH_5761VENDOR_ST_M_M45PE20:
11068 case FLASH_5761VENDOR_ST_M_M45PE40:
11069 case FLASH_5761VENDOR_ST_M_M45PE80:
11070 case FLASH_5761VENDOR_ST_M_M45PE16:
11071 tp->nvram_jedecnum = JEDEC_ST;
11072 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11073 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11074 tp->nvram_pagesize = 256;
11075 break;
6b91fa02
MC		 11076 }
11077
11078 if (protect) {
11079 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11080 } else {
11081 switch (nvcfg1) {
8590a603
MC		 11082 case FLASH_5761VENDOR_ATMEL_ADB161D:
11083 case FLASH_5761VENDOR_ATMEL_MDB161D:
11084 case FLASH_5761VENDOR_ST_A_M45PE16:
11085 case FLASH_5761VENDOR_ST_M_M45PE16:
11086 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11087 break;
11088 case FLASH_5761VENDOR_ATMEL_ADB081D:
11089 case FLASH_5761VENDOR_ATMEL_MDB081D:
11090 case FLASH_5761VENDOR_ST_A_M45PE80:
11091 case FLASH_5761VENDOR_ST_M_M45PE80:
11092 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11093 break;
11094 case FLASH_5761VENDOR_ATMEL_ADB041D:
11095 case FLASH_5761VENDOR_ATMEL_MDB041D:
11096 case FLASH_5761VENDOR_ST_A_M45PE40:
11097 case FLASH_5761VENDOR_ST_M_M45PE40:
11098 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11099 break;
11100 case FLASH_5761VENDOR_ATMEL_ADB021D:
11101 case FLASH_5761VENDOR_ATMEL_MDB021D:
11102 case FLASH_5761VENDOR_ST_A_M45PE20:
11103 case FLASH_5761VENDOR_ST_M_M45PE20:
11104 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11105 break;
6b91fa02
MC		 11106 }
11107 }
11108}
11109
b5d3772c
MC		 11110static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11111{
11112 tp->nvram_jedecnum = JEDEC_ATMEL;
11113 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11114 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11115}
11116
321d32a0
MC		 11117static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11118{
11119 u32 nvcfg1;
11120
11121 nvcfg1 = tr32(NVRAM_CFG1);
11122
11123 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11124 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11125 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11126 tp->nvram_jedecnum = JEDEC_ATMEL;
11127 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11128 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11129
11130 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11131 tw32(NVRAM_CFG1, nvcfg1);
11132 return;
11133 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11134 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11135 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11136 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11137 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11138 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11139 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11140 tp->nvram_jedecnum = JEDEC_ATMEL;
11141 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11142 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11143
11144 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11145 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11146 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11147 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11148 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11149 break;
11150 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11151 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11152 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11153 break;
11154 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11155 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11156 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11157 break;
11158 }
11159 break;
11160 case FLASH_5752VENDOR_ST_M45PE10:
11161 case FLASH_5752VENDOR_ST_M45PE20:
11162 case FLASH_5752VENDOR_ST_M45PE40:
11163 tp->nvram_jedecnum = JEDEC_ST;
11164 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11165 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11166
11167 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11168 case FLASH_5752VENDOR_ST_M45PE10:
11169 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11170 break;
11171 case FLASH_5752VENDOR_ST_M45PE20:
11172 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11173 break;
11174 case FLASH_5752VENDOR_ST_M45PE40:
11175 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11176 break;
11177 }
11178 break;
11179 default:
df259d8c 11180 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11181 return;
11182 }
11183
a1b950d5
MC		 11184 tg3_nvram_get_pagesize(tp, nvcfg1);
11185 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11186 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11187}
11188
11189
11190static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11191{
11192 u32 nvcfg1;
11193
11194 nvcfg1 = tr32(NVRAM_CFG1);
11195
11196 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11197 case FLASH_5717VENDOR_ATMEL_EEPROM:
11198 case FLASH_5717VENDOR_MICRO_EEPROM:
11199 tp->nvram_jedecnum = JEDEC_ATMEL;
11200 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11201 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11202
11203 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11204 tw32(NVRAM_CFG1, nvcfg1);
11205 return;
11206 case FLASH_5717VENDOR_ATMEL_MDB011D:
11207 case FLASH_5717VENDOR_ATMEL_ADB011B:
11208 case FLASH_5717VENDOR_ATMEL_ADB011D:
11209 case FLASH_5717VENDOR_ATMEL_MDB021D:
11210 case FLASH_5717VENDOR_ATMEL_ADB021B:
11211 case FLASH_5717VENDOR_ATMEL_ADB021D:
11212 case FLASH_5717VENDOR_ATMEL_45USPT:
11213 tp->nvram_jedecnum = JEDEC_ATMEL;
11214 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11215 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11216
11217 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11218 case FLASH_5717VENDOR_ATMEL_MDB021D:
11219 case FLASH_5717VENDOR_ATMEL_ADB021B:
11220 case FLASH_5717VENDOR_ATMEL_ADB021D:
11221 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11222 break;
11223 default:
11224 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11225 break;
11226 }
321d32a0 11227 break;
a1b950d5
MC		 11228 case FLASH_5717VENDOR_ST_M_M25PE10:
11229 case FLASH_5717VENDOR_ST_A_M25PE10:
11230 case FLASH_5717VENDOR_ST_M_M45PE10:
11231 case FLASH_5717VENDOR_ST_A_M45PE10:
11232 case FLASH_5717VENDOR_ST_M_M25PE20:
11233 case FLASH_5717VENDOR_ST_A_M25PE20:
11234 case FLASH_5717VENDOR_ST_M_M45PE20:
11235 case FLASH_5717VENDOR_ST_A_M45PE20:
11236 case FLASH_5717VENDOR_ST_25USPT:
11237 case FLASH_5717VENDOR_ST_45USPT:
11238 tp->nvram_jedecnum = JEDEC_ST;
11239 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11240 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11241
11242 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11243 case FLASH_5717VENDOR_ST_M_M25PE20:
11244 case FLASH_5717VENDOR_ST_A_M25PE20:
11245 case FLASH_5717VENDOR_ST_M_M45PE20:
11246 case FLASH_5717VENDOR_ST_A_M45PE20:
11247 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11248 break;
11249 default:
11250 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11251 break;
11252 }
321d32a0 11253 break;
a1b950d5
MC		 11254 default:
11255 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11256 return;
321d32a0 11257 }
a1b950d5
MC		 11258
11259 tg3_nvram_get_pagesize(tp, nvcfg1);
11260 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11261 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11262}
11263
1da177e4
LT		 11264/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11265static void __devinit tg3_nvram_init(struct tg3 *tp)
11266{
1da177e4
LT		 11267 tw32_f(GRC_EEPROM_ADDR,
11268 (EEPROM_ADDR_FSM_RESET |
11269 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11270 EEPROM_ADDR_CLKPERD_SHIFT)));
11271
9d57f01c 11272 msleep(1);
1da177e4
LT		 11273
11274 /* Enable seeprom accesses. */
11275 tw32_f(GRC_LOCAL_CTRL,
11276 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11277 udelay(100);
11278
11279 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11280 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11281 tp->tg3_flags |= TG3_FLAG_NVRAM;
11282
ec41c7df
MC		 11283 if (tg3_nvram_lock(tp)) {
11284 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11285 "tg3_nvram_init failed.\n", tp->dev->name);
11286 return;
11287 }
e6af301b 11288 tg3_enable_nvram_access(tp);
1da177e4 11289
989a9d23
MC		 11290 tp->nvram_size = 0;
11291
361b4ac2
MC		 11292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11293 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11294 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11295 tg3_get_5755_nvram_info(tp);
d30cdd28 11296 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11299 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11300 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11301 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11302 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11303 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11304 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11305 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11306 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11307 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11308 else
11309 tg3_get_nvram_info(tp);
11310
989a9d23
MC		 11311 if (tp->nvram_size == 0)
11312 tg3_get_nvram_size(tp);
1da177e4 11313
e6af301b 11314 tg3_disable_nvram_access(tp);
381291b7 11315 tg3_nvram_unlock(tp);
1da177e4
LT		 11316
11317 } else {
11318 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11319
11320 tg3_get_eeprom_size(tp);
11321 }
11322}
11323
1da177e4
LT		 11324static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11325 u32 offset, u32 len, u8 *buf)
11326{
11327 int i, j, rc = 0;
11328 u32 val;
11329
11330 for (i = 0; i < len; i += 4) {
b9fc7dc5 11331 u32 addr;
a9dc529d 11332 __be32 data;
1da177e4
LT		 11333
11334 addr = offset + i;
11335
11336 memcpy(&data, buf + i, 4);
11337
62cedd11
MC		 11338 /*
11339 * The SEEPROM interface expects the data to always be opposite
11340 * the native endian format. We accomplish this by reversing
11341 * all the operations that would have been performed on the
11342 * data from a call to tg3_nvram_read_be32().
11343 */
11344 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11345
11346 val = tr32(GRC_EEPROM_ADDR);
11347 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11348
11349 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11350 EEPROM_ADDR_READ);
11351 tw32(GRC_EEPROM_ADDR, val |
11352 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11353 (addr & EEPROM_ADDR_ADDR_MASK) |
11354 EEPROM_ADDR_START |
11355 EEPROM_ADDR_WRITE);
6aa20a22 11356
9d57f01c 11357 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11358 val = tr32(GRC_EEPROM_ADDR);
11359
11360 if (val & EEPROM_ADDR_COMPLETE)
11361 break;
9d57f01c 11362 msleep(1);
1da177e4
LT		 11363 }
11364 if (!(val & EEPROM_ADDR_COMPLETE)) {
11365 rc = -EBUSY;
11366 break;
11367 }
11368 }
11369
11370 return rc;
11371}
11372
11373/* offset and length are dword aligned */
11374static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11375 u8 *buf)
11376{
11377 int ret = 0;
11378 u32 pagesize = tp->nvram_pagesize;
11379 u32 pagemask = pagesize - 1;
11380 u32 nvram_cmd;
11381 u8 *tmp;
11382
11383 tmp = kmalloc(pagesize, GFP_KERNEL);
11384 if (tmp == NULL)
11385 return -ENOMEM;
11386
11387 while (len) {
11388 int j;
e6af301b 11389 u32 phy_addr, page_off, size;
1da177e4
LT		 11390
11391 phy_addr = offset & ~pagemask;
6aa20a22 11392
1da177e4 11393 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11394 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11395 (__be32 *) (tmp + j));
11396 if (ret)
1da177e4
LT		 11397 break;
11398 }
11399 if (ret)
11400 break;
11401
11402 page_off = offset & pagemask;
11403 size = pagesize;
11404 if (len < size)
11405 size = len;
11406
11407 len -= size;
11408
11409 memcpy(tmp + page_off, buf, size);
11410
11411 offset = offset + (pagesize - page_off);
11412
e6af301b 11413 tg3_enable_nvram_access(tp);
1da177e4
LT		 11414
11415 /*
11416 * Before we can erase the flash page, we need
11417 * to issue a special "write enable" command.
11418 */
11419 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11420
11421 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11422 break;
11423
11424 /* Erase the target page */
11425 tw32(NVRAM_ADDR, phy_addr);
11426
11427 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11428 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11429
11430 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11431 break;
11432
11433 /* Issue another write enable to start the write. */
11434 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11435
11436 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11437 break;
11438
11439 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11440 __be32 data;
1da177e4 11441
b9fc7dc5 11442 data = *((__be32 *) (tmp + j));
a9dc529d 11443
b9fc7dc5 11444 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11445
11446 tw32(NVRAM_ADDR, phy_addr + j);
11447
11448 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11449 NVRAM_CMD_WR;
11450
11451 if (j == 0)
11452 nvram_cmd |= NVRAM_CMD_FIRST;
11453 else if (j == (pagesize - 4))
11454 nvram_cmd |= NVRAM_CMD_LAST;
11455
11456 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11457 break;
11458 }
11459 if (ret)
11460 break;
11461 }
11462
11463 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11464 tg3_nvram_exec_cmd(tp, nvram_cmd);
11465
11466 kfree(tmp);
11467
11468 return ret;
11469}
11470
11471/* offset and length are dword aligned */
11472static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11473 u8 *buf)
11474{
11475 int i, ret = 0;
11476
11477 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11478 u32 page_off, phy_addr, nvram_cmd;
11479 __be32 data;
1da177e4
LT		 11480
11481 memcpy(&data, buf + i, 4);
b9fc7dc5 11482 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11483
11484 page_off = offset % tp->nvram_pagesize;
11485
1820180b 11486 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11487
11488 tw32(NVRAM_ADDR, phy_addr);
11489
11490 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11491
11492 if ((page_off == 0) || (i == 0))
11493 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11494 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11495 nvram_cmd |= NVRAM_CMD_LAST;
11496
11497 if (i == (len - 4))
11498 nvram_cmd |= NVRAM_CMD_LAST;
11499
321d32a0
MC		 11500 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11501 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11502 (tp->nvram_jedecnum == JEDEC_ST) &&
11503 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11504
11505 if ((ret = tg3_nvram_exec_cmd(tp,
11506 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11507 NVRAM_CMD_DONE)))
11508
11509 break;
11510 }
11511 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11512 /* We always do complete word writes to eeprom. */
11513 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11514 }
11515
11516 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11517 break;
11518 }
11519 return ret;
11520}
11521
11522/* offset and length are dword aligned */
11523static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11524{
11525 int ret;
11526
1da177e4 11527 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11528 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11529 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11530 udelay(40);
11531 }
11532
11533 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11534 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11535 }
11536 else {
11537 u32 grc_mode;
11538
ec41c7df
MC		 11539 ret = tg3_nvram_lock(tp);
11540 if (ret)
11541 return ret;
1da177e4 11542
e6af301b
MC		 11543 tg3_enable_nvram_access(tp);
11544 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11545 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11546 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11547
11548 grc_mode = tr32(GRC_MODE);
11549 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11550
11551 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11552 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11553
11554 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11555 buf);
11556 }
11557 else {
11558 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11559 buf);
11560 }
11561
11562 grc_mode = tr32(GRC_MODE);
11563 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11564
e6af301b 11565 tg3_disable_nvram_access(tp);
1da177e4
LT		 11566 tg3_nvram_unlock(tp);
11567 }
11568
11569 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11570 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11571 udelay(40);
11572 }
11573
11574 return ret;
11575}
11576
11577struct subsys_tbl_ent {
11578 u16 subsys_vendor, subsys_devid;
11579 u32 phy_id;
11580};
11581
11582static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11583 /* Broadcom boards. */
11584 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11585 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11586 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11587 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11588 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11589 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11590 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11591 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11592 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11593 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11594 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11595
11596 /* 3com boards. */
11597 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11598 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11599 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11600 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11601 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11602
11603 /* DELL boards. */
11604 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11605 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11606 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11607 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11608
11609 /* Compaq boards. */
11610 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11611 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11612 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11613 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11614 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11615
11616 /* IBM boards. */
11617 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11618};
11619
11620static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11621{
11622 int i;
11623
11624 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11625 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11626 tp->pdev->subsystem_vendor) &&
11627 (subsys_id_to_phy_id[i].subsys_devid ==
11628 tp->pdev->subsystem_device))
11629 return &subsys_id_to_phy_id[i];
11630 }
11631 return NULL;
11632}
11633
7d0c41ef 11634static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11635{
1da177e4 11636 u32 val;
caf636c7
MC		 11637 u16 pmcsr;
11638
11639 /* On some early chips the SRAM cannot be accessed in D3hot state,
11640 * so need make sure we're in D0.
11641 */
11642 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11643 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11644 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11645 msleep(1);
7d0c41ef
MC		 11646
11647 /* Make sure register accesses (indirect or otherwise)
11648 * will function correctly.
11649 */
11650 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11651 tp->misc_host_ctrl);
1da177e4 11652
f49639e6
DM		 11653 /* The memory arbiter has to be enabled in order for SRAM accesses
11654 * to succeed. Normally on powerup the tg3 chip firmware will make
11655 * sure it is enabled, but other entities such as system netboot
11656 * code might disable it.
11657 */
11658 val = tr32(MEMARB_MODE);
11659 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11660
1da177e4 11661 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11662 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11663
a85feb8c
GZ		 11664 /* Assume an onboard device and WOL capable by default. */
11665 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11666
b5d3772c 11667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11668 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11669 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11670 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11671 }
0527ba35
MC		 11672 val = tr32(VCPU_CFGSHDW);
11673 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11674 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11675 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11676 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11677 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11678 goto done;
b5d3772c
MC		 11679 }
11680
1da177e4
LT		 11681 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11682 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11683 u32 nic_cfg, led_cfg;
a9daf367 11684 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11685 int eeprom_phy_serdes = 0;
1da177e4
LT		 11686
11687 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11688 tp->nic_sram_data_cfg = nic_cfg;
11689
11690 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11691 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11692 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11693 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11694 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11695 (ver > 0) && (ver < 0x100))
11696 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11697
a9daf367
MC		 11698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11699 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11700
1da177e4
LT		 11701 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11702 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11703 eeprom_phy_serdes = 1;
11704
11705 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11706 if (nic_phy_id != 0) {
11707 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11708 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11709
11710 eeprom_phy_id = (id1 >> 16) << 10;
11711 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11712 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11713 } else
11714 eeprom_phy_id = 0;
11715
7d0c41ef 11716 tp->phy_id = eeprom_phy_id;
747e8f8b 11717 if (eeprom_phy_serdes) {
a4e2b347 11718 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11719 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11720 else
11721 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11722 }
7d0c41ef 11723
cbf46853 11724 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11725 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11726 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11727 else
1da177e4
LT		 11728 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11729
11730 switch (led_cfg) {
11731 default:
11732 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11733 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11734 break;
11735
11736 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11737 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11738 break;
11739
11740 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11741 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11742
11743 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11744 * read on some older 5700/5701 bootcode.
11745 */
11746 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11747 ASIC_REV_5700 ||
11748 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11749 ASIC_REV_5701)
11750 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11751
1da177e4
LT		 11752 break;
11753
11754 case SHASTA_EXT_LED_SHARED:
11755 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11756 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11757 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11758 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11759 LED_CTRL_MODE_PHY_2);
11760 break;
11761
11762 case SHASTA_EXT_LED_MAC:
11763 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11764 break;
11765
11766 case SHASTA_EXT_LED_COMBO:
11767 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11768 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11769 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11770 LED_CTRL_MODE_PHY_2);
11771 break;
11772
855e1111 11773 }
1da177e4
LT		 11774
11775 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11777 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11778 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11779
b2a5c19c
MC		 11780 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11781 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11782
9d26e213 11783 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11784 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11785 if ((tp->pdev->subsystem_vendor ==
11786 PCI_VENDOR_ID_ARIMA) &&
11787 (tp->pdev->subsystem_device == 0x205a ||
11788 tp->pdev->subsystem_device == 0x2063))
11789 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11790 } else {
f49639e6 11791 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11792 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11793 }
1da177e4
LT		 11794
11795 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11796 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11797 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11798 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11799 }
b2b98d4a
MC		 11800
11801 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11802 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11803 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11804
a85feb8c
GZ		 11805 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11806 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11807 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11808
12dac075 11809 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11810 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11811 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11812
1da177e4
LT		 11813 if (cfg2 & (1 << 17))
11814 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11815
11816 /* serdes signal pre-emphasis in register 0x590 set by */
11817 /* bootcode if bit 18 is set */
11818 if (cfg2 & (1 << 18))
11819 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11820
321d32a0
MC		 11821 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11822 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11823 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11824 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11825
8ed5d97e
MC		 11826 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11827 u32 cfg3;
11828
11829 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11830 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11831 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11832 }
a9daf367
MC		 11833
11834 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11835 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11836 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11837 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11838 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11839 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11840 }
05ac4cb7
MC		 11841done:
11842 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11843 device_set_wakeup_enable(&tp->pdev->dev,
11844 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11845}
11846
b2a5c19c
MC		 11847static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11848{
11849 int i;
11850 u32 val;
11851
11852 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11853 tw32(OTP_CTRL, cmd);
11854
11855 /* Wait for up to 1 ms for command to execute. */
11856 for (i = 0; i < 100; i++) {
11857 val = tr32(OTP_STATUS);
11858 if (val & OTP_STATUS_CMD_DONE)
11859 break;
11860 udelay(10);
11861 }
11862
11863 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11864}
11865
11866/* Read the gphy configuration from the OTP region of the chip. The gphy
11867 * configuration is a 32-bit value that straddles the alignment boundary.
11868 * We do two 32-bit reads and then shift and merge the results.
11869 */
11870static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11871{
11872 u32 bhalf_otp, thalf_otp;
11873
11874 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11875
11876 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11877 return 0;
11878
11879 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11880
11881 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11882 return 0;
11883
11884 thalf_otp = tr32(OTP_READ_DATA);
11885
11886 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11887
11888 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11889 return 0;
11890
11891 bhalf_otp = tr32(OTP_READ_DATA);
11892
11893 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11894}
11895
7d0c41ef
MC		 11896static int __devinit tg3_phy_probe(struct tg3 *tp)
11897{
11898 u32 hw_phy_id_1, hw_phy_id_2;
11899 u32 hw_phy_id, hw_phy_id_masked;
11900 int err;
1da177e4 11901
b02fd9e3
MC		 11902 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11903 return tg3_phy_init(tp);
11904
1da177e4 11905 /* Reading the PHY ID register can conflict with ASF
877d0310 11906 * firmware access to the PHY hardware.
1da177e4
LT		 11907 */
11908 err = 0;
0d3031d9
MC		 11909 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11910 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11911 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11912 } else {
11913 /* Now read the physical PHY_ID from the chip and verify
11914 * that it is sane. If it doesn't look good, we fall back
11915 * to either the hard-coded table based PHY_ID and failing
11916 * that the value found in the eeprom area.
11917 */
11918 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11919 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11920
11921 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11922 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11923 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11924
11925 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11926 }
11927
11928 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11929 tp->phy_id = hw_phy_id;
11930 if (hw_phy_id_masked == PHY_ID_BCM8002)
11931 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11932 else
11933 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11934 } else {
7d0c41ef
MC		 11935 if (tp->phy_id != PHY_ID_INVALID) {
11936 /* Do nothing, phy ID already set up in
11937 * tg3_get_eeprom_hw_cfg().
11938 */
1da177e4
LT		 11939 } else {
11940 struct subsys_tbl_ent *p;
11941
11942 /* No eeprom signature? Try the hardcoded
11943 * subsys device table.
11944 */
11945 p = lookup_by_subsys(tp);
11946 if (!p)
11947 return -ENODEV;
11948
11949 tp->phy_id = p->phy_id;
11950 if (!tp->phy_id ||
11951 tp->phy_id == PHY_ID_BCM8002)
11952 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11953 }
11954 }
11955
747e8f8b 11956 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11957 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11958 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11959 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11960
11961 tg3_readphy(tp, MII_BMSR, &bmsr);
11962 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11963 (bmsr & BMSR_LSTATUS))
11964 goto skip_phy_reset;
6aa20a22 11965
1da177e4
LT		 11966 err = tg3_phy_reset(tp);
11967 if (err)
11968 return err;
11969
11970 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11971 ADVERTISE_100HALF | ADVERTISE_100FULL |
11972 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11973 tg3_ctrl = 0;
11974 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11975 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11976 MII_TG3_CTRL_ADV_1000_FULL);
11977 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11978 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11979 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11980 MII_TG3_CTRL_ENABLE_AS_MASTER);
11981 }
11982
3600d918
MC		 11983 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11984 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11985 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11986 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11987 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11988
11989 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11990 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11991
11992 tg3_writephy(tp, MII_BMCR,
11993 BMCR_ANENABLE | BMCR_ANRESTART);
11994 }
11995 tg3_phy_set_wirespeed(tp);
11996
11997 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11998 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11999 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12000 }
12001
12002skip_phy_reset:
12003 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12004 err = tg3_init_5401phy_dsp(tp);
12005 if (err)
12006 return err;
12007 }
12008
12009 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12010 err = tg3_init_5401phy_dsp(tp);
12011 }
12012
747e8f8b 12013 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12014 tp->link_config.advertising =
12015 (ADVERTISED_1000baseT_Half |
12016 ADVERTISED_1000baseT_Full |
12017 ADVERTISED_Autoneg |
12018 ADVERTISED_FIBRE);
12019 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12020 tp->link_config.advertising &=
12021 ~(ADVERTISED_1000baseT_Half |
12022 ADVERTISED_1000baseT_Full);
12023
12024 return err;
12025}
12026
12027static void __devinit tg3_read_partno(struct tg3 *tp)
12028{
6d348f2c 12029 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12030 unsigned int i;
1b27777a 12031 u32 magic;
1da177e4 12032
df259d8c
MC		 12033 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12034 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12035 goto out_not_found;
1da177e4 12036
1820180b 12037 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12038 for (i = 0; i < 256; i += 4) {
12039 u32 tmp;
1da177e4 12040
6d348f2c
MC		 12041 /* The data is in little-endian format in NVRAM.
12042 * Use the big-endian read routines to preserve
12043 * the byte order as it exists in NVRAM.
12044 */
12045 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12046 goto out_not_found;
12047
6d348f2c 12048 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12049 }
12050 } else {
12051 int vpd_cap;
12052
12053 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12054 for (i = 0; i < 256; i += 4) {
12055 u32 tmp, j = 0;
b9fc7dc5 12056 __le32 v;
1b27777a
MC		 12057 u16 tmp16;
12058
12059 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12060 i);
12061 while (j++ < 100) {
12062 pci_read_config_word(tp->pdev, vpd_cap +
12063 PCI_VPD_ADDR, &tmp16);
12064 if (tmp16 & 0x8000)
12065 break;
12066 msleep(1);
12067 }
f49639e6
DM		 12068 if (!(tmp16 & 0x8000))
12069 goto out_not_found;
12070
1b27777a
MC		 12071 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12072 &tmp);
b9fc7dc5 12073 v = cpu_to_le32(tmp);
6d348f2c 12074 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12075 }
1da177e4
LT		 12076 }
12077
12078 /* Now parse and find the part number. */
af2c6a4a 12079 for (i = 0; i < 254; ) {
1da177e4 12080 unsigned char val = vpd_data[i];
af2c6a4a 12081 unsigned int block_end;
1da177e4
LT		 12082
12083 if (val == 0x82 || val == 0x91) {
12084 i = (i + 3 +
12085 (vpd_data[i + 1] +
12086 (vpd_data[i + 2] << 8)));
12087 continue;
12088 }
12089
12090 if (val != 0x90)
12091 goto out_not_found;
12092
12093 block_end = (i + 3 +
12094 (vpd_data[i + 1] +
12095 (vpd_data[i + 2] << 8)));
12096 i += 3;
af2c6a4a
MC		 12097
12098 if (block_end > 256)
12099 goto out_not_found;
12100
12101 while (i < (block_end - 2)) {
1da177e4
LT		 12102 if (vpd_data[i + 0] == 'P' &&
12103 vpd_data[i + 1] == 'N') {
12104 int partno_len = vpd_data[i + 2];
12105
af2c6a4a
MC		 12106 i += 3;
12107 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12108 goto out_not_found;
12109
12110 memcpy(tp->board_part_number,
af2c6a4a 12111 &vpd_data[i], partno_len);
1da177e4
LT		 12112
12113 /* Success. */
12114 return;
12115 }
af2c6a4a 12116 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12117 }
12118
12119 /* Part number not found. */
12120 goto out_not_found;
12121 }
12122
12123out_not_found:
b5d3772c
MC		 12124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12125 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12126 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12128 strcpy(tp->board_part_number, "BCM57780");
12129 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12130 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12131 strcpy(tp->board_part_number, "BCM57760");
12132 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12133 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12134 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12135 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12136 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12137 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12138 else
12139 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12140}
12141
9c8a620e
MC		 12142static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12143{
12144 u32 val;
12145
e4f34110 12146 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12147 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12148 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12149 val != 0)
12150 return 0;
12151
12152 return 1;
12153}
12154
acd9c119
MC		 12155static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12156{
ff3a7cb2 12157 u32 val, offset, start, ver_offset;
acd9c119 12158 int i;
ff3a7cb2 12159 bool newver = false;
acd9c119
MC		 12160
12161 if (tg3_nvram_read(tp, 0xc, &offset) ||
12162 tg3_nvram_read(tp, 0x4, &start))
12163 return;
12164
12165 offset = tg3_nvram_logical_addr(tp, offset);
12166
ff3a7cb2 12167 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12168 return;
12169
ff3a7cb2
MC		 12170 if ((val & 0xfc000000) == 0x0c000000) {
12171 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12172 return;
12173
ff3a7cb2
MC		 12174 if (val == 0)
12175 newver = true;
12176 }
12177
12178 if (newver) {
12179 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12180 return;
12181
12182 offset = offset + ver_offset - start;
12183 for (i = 0; i < 16; i += 4) {
12184 __be32 v;
12185 if (tg3_nvram_read_be32(tp, offset + i, &v))
12186 return;
12187
12188 memcpy(tp->fw_ver + i, &v, sizeof(v));
12189 }
12190 } else {
12191 u32 major, minor;
12192
12193 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12194 return;
12195
12196 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12197 TG3_NVM_BCVER_MAJSFT;
12198 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12199 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12200 }
12201}
12202
a6f6cb1c
MC		 12203static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12204{
12205 u32 val, major, minor;
12206
12207 /* Use native endian representation */
12208 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12209 return;
12210
12211 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12212 TG3_NVM_HWSB_CFG1_MAJSFT;
12213 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12214 TG3_NVM_HWSB_CFG1_MINSFT;
12215
12216 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12217}
12218
dfe00d7d
MC		 12219static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12220{
12221 u32 offset, major, minor, build;
12222
12223 tp->fw_ver[0] = 's';
12224 tp->fw_ver[1] = 'b';
12225 tp->fw_ver[2] = '\0';
12226
12227 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12228 return;
12229
12230 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12231 case TG3_EEPROM_SB_REVISION_0:
12232 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12233 break;
12234 case TG3_EEPROM_SB_REVISION_2:
12235 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12236 break;
12237 case TG3_EEPROM_SB_REVISION_3:
12238 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12239 break;
12240 default:
12241 return;
12242 }
12243
e4f34110 12244 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12245 return;
12246
12247 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12248 TG3_EEPROM_SB_EDH_BLD_SHFT;
12249 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12250 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12251 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12252
12253 if (minor > 99 || build > 26)
12254 return;
12255
12256 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12257
12258 if (build > 0) {
12259 tp->fw_ver[8] = 'a' + build - 1;
12260 tp->fw_ver[9] = '\0';
12261 }
12262}
12263
acd9c119 12264static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12265{
12266 u32 val, offset, start;
acd9c119 12267 int i, vlen;
9c8a620e
MC		 12268
12269 for (offset = TG3_NVM_DIR_START;
12270 offset < TG3_NVM_DIR_END;
12271 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12272 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12273 return;
12274
9c8a620e
MC		 12275 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12276 break;
12277 }
12278
12279 if (offset == TG3_NVM_DIR_END)
12280 return;
12281
12282 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12283 start = 0x08000000;
e4f34110 12284 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12285 return;
12286
e4f34110 12287 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12288 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12289 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12290 return;
12291
12292 offset += val - start;
12293
acd9c119 12294 vlen = strlen(tp->fw_ver);
9c8a620e 12295
acd9c119
MC		 12296 tp->fw_ver[vlen++] = ',';
12297 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12298
12299 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12300 __be32 v;
12301 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12302 return;
12303
b9fc7dc5 12304 offset += sizeof(v);
c4e6575c 12305
acd9c119
MC		 12306 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12307 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12308 break;
c4e6575c 12309 }
9c8a620e 12310
acd9c119
MC		 12311 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12312 vlen += sizeof(v);
c4e6575c 12313 }
acd9c119
MC		 12314}
12315
7fd76445
MC		 12316static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12317{
12318 int vlen;
12319 u32 apedata;
12320
12321 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12322 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12323 return;
12324
12325 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12326 if (apedata != APE_SEG_SIG_MAGIC)
12327 return;
12328
12329 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12330 if (!(apedata & APE_FW_STATUS_READY))
12331 return;
12332
12333 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12334
12335 vlen = strlen(tp->fw_ver);
12336
12337 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12338 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12339 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12340 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12341 (apedata & APE_FW_VERSION_BLDMSK));
12342}
12343
acd9c119
MC		 12344static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12345{
12346 u32 val;
12347
df259d8c
MC		 12348 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12349 tp->fw_ver[0] = 's';
12350 tp->fw_ver[1] = 'b';
12351 tp->fw_ver[2] = '\0';
12352
12353 return;
12354 }
12355
acd9c119
MC		 12356 if (tg3_nvram_read(tp, 0, &val))
12357 return;
12358
12359 if (val == TG3_EEPROM_MAGIC)
12360 tg3_read_bc_ver(tp);
12361 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12362 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12363 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12364 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12365 else
12366 return;
12367
12368 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12369 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12370 return;
12371
12372 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12373
12374 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12375}
12376
7544b097
MC		 12377static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12378
1da177e4
LT		 12379static int __devinit tg3_get_invariants(struct tg3 *tp)
12380{
12381 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12382 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12383 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12384 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12385 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12386 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12387 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12388 { },
12389 };
12390 u32 misc_ctrl_reg;
1da177e4
LT		 12391 u32 pci_state_reg, grc_misc_cfg;
12392 u32 val;
12393 u16 pci_cmd;
5e7dfd0f 12394 int err;
1da177e4 12395
1da177e4
LT		 12396 /* Force memory write invalidate off. If we leave it on,
12397 * then on 5700_BX chips we have to enable a workaround.
12398 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12399 * to match the cacheline size. The Broadcom driver have this
12400 * workaround but turns MWI off all the times so never uses
12401 * it. This seems to suggest that the workaround is insufficient.
12402 */
12403 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12404 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12405 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12406
12407 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12408 * has the register indirect write enable bit set before
12409 * we try to access any of the MMIO registers. It is also
12410 * critical that the PCI-X hw workaround situation is decided
12411 * before that as well.
12412 */
12413 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12414 &misc_ctrl_reg);
12415
12416 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12417 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12419 u32 prod_id_asic_rev;
12420
f6eb9b1f
MC		 12421 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12422 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12423 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12424 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12425 pci_read_config_dword(tp->pdev,
12426 TG3PCI_GEN2_PRODID_ASICREV,
12427 &prod_id_asic_rev);
12428 else
12429 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12430 &prod_id_asic_rev);
12431
321d32a0 12432 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12433 }
1da177e4 12434
ff645bec
MC		 12435 /* Wrong chip ID in 5752 A0. This code can be removed later
12436 * as A0 is not in production.
12437 */
12438 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12439 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12440
6892914f
MC		 12441 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12442 * we need to disable memory and use config. cycles
12443 * only to access all registers. The 5702/03 chips
12444 * can mistakenly decode the special cycles from the
12445 * ICH chipsets as memory write cycles, causing corruption
12446 * of register and memory space. Only certain ICH bridges
12447 * will drive special cycles with non-zero data during the
12448 * address phase which can fall within the 5703's address
12449 * range. This is not an ICH bug as the PCI spec allows
12450 * non-zero address during special cycles. However, only
12451 * these ICH bridges are known to drive non-zero addresses
12452 * during special cycles.
12453 *
12454 * Since special cycles do not cross PCI bridges, we only
12455 * enable this workaround if the 5703 is on the secondary
12456 * bus of these ICH bridges.
12457 */
12458 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12459 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12460 static struct tg3_dev_id {
12461 u32 vendor;
12462 u32 device;
12463 u32 rev;
12464 } ich_chipsets[] = {
12465 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12466 PCI_ANY_ID },
12467 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12468 PCI_ANY_ID },
12469 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12470 0xa },
12471 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12472 PCI_ANY_ID },
12473 { },
12474 };
12475 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12476 struct pci_dev *bridge = NULL;
12477
12478 while (pci_id->vendor != 0) {
12479 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12480 bridge);
12481 if (!bridge) {
12482 pci_id++;
12483 continue;
12484 }
12485 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12486 if (bridge->revision > pci_id->rev)
6892914f
MC		 12487 continue;
12488 }
12489 if (bridge->subordinate &&
12490 (bridge->subordinate->number ==
12491 tp->pdev->bus->number)) {
12492
12493 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12494 pci_dev_put(bridge);
12495 break;
12496 }
12497 }
12498 }
12499
41588ba1
MC		 12500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12501 static struct tg3_dev_id {
12502 u32 vendor;
12503 u32 device;
12504 } bridge_chipsets[] = {
12505 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12506 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12507 { },
12508 };
12509 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12510 struct pci_dev *bridge = NULL;
12511
12512 while (pci_id->vendor != 0) {
12513 bridge = pci_get_device(pci_id->vendor,
12514 pci_id->device,
12515 bridge);
12516 if (!bridge) {
12517 pci_id++;
12518 continue;
12519 }
12520 if (bridge->subordinate &&
12521 (bridge->subordinate->number <=
12522 tp->pdev->bus->number) &&
12523 (bridge->subordinate->subordinate >=
12524 tp->pdev->bus->number)) {
12525 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12526 pci_dev_put(bridge);
12527 break;
12528 }
12529 }
12530 }
12531
4a29cc2e
MC		 12532 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12533 * DMA addresses > 40-bit. This bridge may have other additional
12534 * 57xx devices behind it in some 4-port NIC designs for example.
12535 * Any tg3 device found behind the bridge will also need the 40-bit
12536 * DMA workaround.
12537 */
a4e2b347
MC		 12538 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12539 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12540 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12541 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12542 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12543 }
4a29cc2e
MC		 12544 else {
12545 struct pci_dev *bridge = NULL;
12546
12547 do {
12548 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12549 PCI_DEVICE_ID_SERVERWORKS_EPB,
12550 bridge);
12551 if (bridge && bridge->subordinate &&
12552 (bridge->subordinate->number <=
12553 tp->pdev->bus->number) &&
12554 (bridge->subordinate->subordinate >=
12555 tp->pdev->bus->number)) {
12556 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12557 pci_dev_put(bridge);
12558 break;
12559 }
12560 } while (bridge);
12561 }
4cf78e4f 12562
1da177e4
LT		 12563 /* Initialize misc host control in PCI block. */
12564 tp->misc_host_ctrl |= (misc_ctrl_reg &
12565 MISC_HOST_CTRL_CHIPREV);
12566 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12567 tp->misc_host_ctrl);
12568
f6eb9b1f
MC		 12569 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12572 tp->pdev_peer = tg3_find_peer(tp);
12573
321d32a0
MC		 12574 /* Intentionally exclude ASIC_REV_5906 */
12575 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12577 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12581 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12582 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12583
12584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12585 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12587 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12588 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12589 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12590
1b440c56
JL		 12591 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12592 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12593 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12594
027455ad
MC		 12595 /* 5700 B0 chips do not support checksumming correctly due
12596 * to hardware bugs.
12597 */
12598 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12599 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12600 else {
12601 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12602 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12603 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12604 tp->dev->features |= NETIF_F_IPV6_CSUM;
12605 }
12606
5a6f3074 12607 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12608 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12609 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12610 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12611 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12612 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12613 tp->pdev_peer == tp->pdev))
12614 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12615
321d32a0 12616 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12618 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12619 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12620 } else {
7f62ad5d 12621 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12622 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12623 ASIC_REV_5750 &&
12624 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12625 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12626 }
5a6f3074 12627 }
1da177e4 12628
4f125f42
MC		 12629 tp->irq_max = 1;
12630
f6eb9b1f
MC		 12631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12632 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12633 tp->irq_max = TG3_IRQ_MAX_VECS;
12634 }
0e1406dd
MC		 12635
12636 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
92c6b8d1
MC		 12637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12638 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12639 else {
12640 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12641 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12642 }
0e1406dd 12643 }
f6eb9b1f 12644
f51f3562 12645 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12646 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12648 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12649
52f4490c
MC		 12650 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12651 &pci_state_reg);
12652
5e7dfd0f
MC		 12653 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12654 if (tp->pcie_cap != 0) {
12655 u16 lnkctl;
12656
1da177e4 12657 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12658
12659 pcie_set_readrq(tp->pdev, 4096);
12660
5e7dfd0f
MC		 12661 pci_read_config_word(tp->pdev,
12662 tp->pcie_cap + PCI_EXP_LNKCTL,
12663 &lnkctl);
12664 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12666 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12669 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12670 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12671 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12672 }
52f4490c 12673 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12674 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12675 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12676 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12677 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12678 if (!tp->pcix_cap) {
12679 printk(KERN_ERR PFX "Cannot find PCI-X "
12680 "capability, aborting.\n");
12681 return -EIO;
12682 }
12683
12684 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12685 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12686 }
1da177e4 12687
399de50b
MC		 12688 /* If we have an AMD 762 or VIA K8T800 chipset, write
12689 * reordering to the mailbox registers done by the host
12690 * controller can cause major troubles. We read back from
12691 * every mailbox register write to force the writes to be
12692 * posted to the chip in order.
12693 */
12694 if (pci_dev_present(write_reorder_chipsets) &&
12695 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12696 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12697
69fc4053
MC		 12698 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12699 &tp->pci_cacheline_sz);
12700 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12701 &tp->pci_lat_timer);
1da177e4
LT		 12702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12703 tp->pci_lat_timer < 64) {
12704 tp->pci_lat_timer = 64;
69fc4053
MC		 12705 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12706 tp->pci_lat_timer);
1da177e4
LT		 12707 }
12708
52f4490c
MC		 12709 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12710 /* 5700 BX chips need to have their TX producer index
12711 * mailboxes written twice to workaround a bug.
12712 */
12713 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12714
52f4490c 12715 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12716 *
12717 * The workaround is to use indirect register accesses
12718 * for all chip writes not to mailbox registers.
12719 */
52f4490c 12720 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12721 u32 pm_reg;
1da177e4
LT		 12722
12723 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12724
12725 /* The chip can have it's power management PCI config
12726 * space registers clobbered due to this bug.
12727 * So explicitly force the chip into D0 here.
12728 */
9974a356
MC		 12729 pci_read_config_dword(tp->pdev,
12730 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12731 &pm_reg);
12732 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12733 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12734 pci_write_config_dword(tp->pdev,
12735 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12736 pm_reg);
12737
12738 /* Also, force SERR#/PERR# in PCI command. */
12739 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12740 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12741 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12742 }
12743 }
12744
1da177e4
LT		 12745 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12746 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12747 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12748 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12749
12750 /* Chip-specific fixup from Broadcom driver */
12751 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12752 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12753 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12754 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12755 }
12756
1ee582d8 12757 /* Default fast path register access methods */
20094930 12758 tp->read32 = tg3_read32;
1ee582d8 12759 tp->write32 = tg3_write32;
09ee929c 12760 tp->read32_mbox = tg3_read32;
20094930 12761 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12762 tp->write32_tx_mbox = tg3_write32;
12763 tp->write32_rx_mbox = tg3_write32;
12764
12765 /* Various workaround register access methods */
12766 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12767 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12768 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12769 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12770 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12771 /*
12772 * Back to back register writes can cause problems on these
12773 * chips, the workaround is to read back all reg writes
12774 * except those to mailbox regs.
12775 *
12776 * See tg3_write_indirect_reg32().
12777 */
1ee582d8 12778 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12779 }
12780
1ee582d8
MC		 12781 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12782 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12783 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12784 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12785 tp->write32_rx_mbox = tg3_write_flush_reg32;
12786 }
20094930 12787
6892914f
MC		 12788 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12789 tp->read32 = tg3_read_indirect_reg32;
12790 tp->write32 = tg3_write_indirect_reg32;
12791 tp->read32_mbox = tg3_read_indirect_mbox;
12792 tp->write32_mbox = tg3_write_indirect_mbox;
12793 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12794 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12795
12796 iounmap(tp->regs);
22abe310 12797 tp->regs = NULL;
6892914f
MC		 12798
12799 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12800 pci_cmd &= ~PCI_COMMAND_MEMORY;
12801 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12802 }
b5d3772c
MC		 12803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12804 tp->read32_mbox = tg3_read32_mbox_5906;
12805 tp->write32_mbox = tg3_write32_mbox_5906;
12806 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12807 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12808 }
6892914f 12809
bbadf503
MC		 12810 if (tp->write32 == tg3_write_indirect_reg32 ||
12811 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12812 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12814 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12815
7d0c41ef 12816 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12817 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12818 * determined before calling tg3_set_power_state() so that
12819 * we know whether or not to switch out of Vaux power.
12820 * When the flag is set, it means that GPIO1 is used for eeprom
12821 * write protect and also implies that it is a LOM where GPIOs
12822 * are not used to switch power.
6aa20a22 12823 */
7d0c41ef
MC		 12824 tg3_get_eeprom_hw_cfg(tp);
12825
0d3031d9
MC		 12826 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12827 /* Allow reads and writes to the
12828 * APE register and memory space.
12829 */
12830 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12831 PCISTATE_ALLOW_APE_SHMEM_WR;
12832 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12833 pci_state_reg);
12834 }
12835
9936bcf6 12836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12841 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12842
314fba34
MC		 12843 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12844 * GPIO1 driven high will bring 5700's external PHY out of reset.
12845 * It is also used as eeprom write protect on LOMs.
12846 */
12847 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12848 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12849 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12850 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12851 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12852 /* Unused GPIO3 must be driven as output on 5752 because there
12853 * are no pull-up resistors on unused GPIO pins.
12854 */
12855 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12856 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12857
321d32a0
MC		 12858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12860 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12861
8d519ab2
MC		 12862 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12863 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12864 /* Turn off the debug UART. */
12865 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12866 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12867 /* Keep VMain power. */
12868 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12869 GRC_LCLCTRL_GPIO_OUTPUT0;
12870 }
12871
1da177e4 12872 /* Force the chip into D0. */
bc1c7567 12873 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12874 if (err) {
12875 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12876 pci_name(tp->pdev));
12877 return err;
12878 }
12879
1da177e4
LT		 12880 /* Derive initial jumbo mode from MTU assigned in
12881 * ether_setup() via the alloc_etherdev() call
12882 */
0f893dc6 12883 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12884 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12885 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12886
12887 /* Determine WakeOnLan speed to use. */
12888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12889 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12890 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12891 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12892 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12893 } else {
12894 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12895 }
12896
7f97a4bd
MC		 12897 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12898 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12899
1da177e4
LT		 12900 /* A few boards don't want Ethernet@WireSpeed phy feature */
12901 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12902 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12903 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12904 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12905 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12906 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12907 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12908
12909 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12910 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12911 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12912 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12913 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12914
321d32a0 12915 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12916 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 12917 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 12918 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12919 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 12920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12924 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12925 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12926 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12927 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12928 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12929 } else
c424cb24
MC		 12930 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12931 }
1da177e4 12932
b2a5c19c
MC		 12933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12934 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12935 tp->phy_otp = tg3_read_otp_phycfg(tp);
12936 if (tp->phy_otp == 0)
12937 tp->phy_otp = TG3_OTP_DEFAULT;
12938 }
12939
f51f3562 12940 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12941 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12942 else
12943 tp->mi_mode = MAC_MI_MODE_BASE;
12944
1da177e4 12945 tp->coalesce_mode = 0;
1da177e4
LT		 12946 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12947 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12948 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12949
321d32a0
MC		 12950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12952 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12953
255ca311
MC		 12954 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12955 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12956 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12957 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12958
158d7abd
MC		 12959 err = tg3_mdio_init(tp);
12960 if (err)
12961 return err;
1da177e4
LT		 12962
12963 /* Initialize data/descriptor byte/word swapping. */
12964 val = tr32(GRC_MODE);
12965 val &= GRC_MODE_HOST_STACKUP;
12966 tw32(GRC_MODE, val | tp->grc_mode);
12967
12968 tg3_switch_clocks(tp);
12969
12970 /* Clear this out for sanity. */
12971 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12972
12973 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12974 &pci_state_reg);
12975 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12976 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12977 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12978
12979 if (chiprevid == CHIPREV_ID_5701_A0 ||
12980 chiprevid == CHIPREV_ID_5701_B0 ||
12981 chiprevid == CHIPREV_ID_5701_B2 ||
12982 chiprevid == CHIPREV_ID_5701_B5) {
12983 void __iomem *sram_base;
12984
12985 /* Write some dummy words into the SRAM status block
12986 * area, see if it reads back correctly. If the return
12987 * value is bad, force enable the PCIX workaround.
12988 */
12989 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12990
12991 writel(0x00000000, sram_base);
12992 writel(0x00000000, sram_base + 4);
12993 writel(0xffffffff, sram_base + 4);
12994 if (readl(sram_base) != 0x00000000)
12995 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12996 }
12997 }
12998
12999 udelay(50);
13000 tg3_nvram_init(tp);
13001
13002 grc_misc_cfg = tr32(GRC_MISC_CFG);
13003 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13004
1da177e4
LT		 13005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13006 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13007 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13008 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13009
fac9b83e
DM		 13010 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13011 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13012 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13013 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13014 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13015 HOSTCC_MODE_CLRTICK_TXBD);
13016
13017 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13018 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13019 tp->misc_host_ctrl);
13020 }
13021
3bda1258
MC		 13022 /* Preserve the APE MAC_MODE bits */
13023 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13024 tp->mac_mode = tr32(MAC_MODE) |
13025 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13026 else
13027 tp->mac_mode = TG3_DEF_MAC_MODE;
13028
1da177e4
LT		 13029 /* these are limited to 10/100 only */
13030 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13031 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13032 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13033 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13034 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13035 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13036 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13037 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13038 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13039 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13040 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13042 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13043 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13044
13045 err = tg3_phy_probe(tp);
13046 if (err) {
13047 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13048 pci_name(tp->pdev), err);
13049 /* ... but do not return immediately ... */
b02fd9e3 13050 tg3_mdio_fini(tp);
1da177e4
LT		 13051 }
13052
13053 tg3_read_partno(tp);
c4e6575c 13054 tg3_read_fw_ver(tp);
1da177e4
LT		 13055
13056 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13057 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13058 } else {
13059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13060 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13061 else
13062 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13063 }
13064
13065 /* 5700 {AX,BX} chips have a broken status block link
13066 * change bit implementation, so we must use the
13067 * status register in those cases.
13068 */
13069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13070 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13071 else
13072 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13073
13074 /* The led_ctrl is set during tg3_phy_probe, here we might
13075 * have to force the link status polling mechanism based
13076 * upon subsystem IDs.
13077 */
13078 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13080 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13081 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13082 TG3_FLAG_USE_LINKCHG_REG);
13083 }
13084
13085 /* For all SERDES we poll the MAC status register. */
13086 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13087 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13088 else
13089 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13090
ad829268 13091 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13093 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13094 tp->rx_offset = 0;
13095
f92905de
MC		 13096 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13097
13098 /* Increment the rx prod index on the rx std ring by at most
13099 * 8 for these chips to workaround hw errata.
13100 */
13101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13104 tp->rx_std_max_post = 8;
13105
8ed5d97e
MC		 13106 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13107 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13108 PCIE_PWR_MGMT_L1_THRESH_MSK;
13109
1da177e4
LT		 13110 return err;
13111}
13112
49b6e95f 13113#ifdef CONFIG_SPARC
1da177e4
LT		 13114static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13115{
13116 struct net_device *dev = tp->dev;
13117 struct pci_dev *pdev = tp->pdev;
49b6e95f 13118 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13119 const unsigned char *addr;
49b6e95f
DM		 13120 int len;
13121
13122 addr = of_get_property(dp, "local-mac-address", &len);
13123 if (addr && len == 6) {
13124 memcpy(dev->dev_addr, addr, 6);
13125 memcpy(dev->perm_addr, dev->dev_addr, 6);
13126 return 0;
1da177e4
LT		 13127 }
13128 return -ENODEV;
13129}
13130
13131static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13132{
13133 struct net_device *dev = tp->dev;
13134
13135 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13136 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13137 return 0;
13138}
13139#endif
13140
13141static int __devinit tg3_get_device_address(struct tg3 *tp)
13142{
13143 struct net_device *dev = tp->dev;
13144 u32 hi, lo, mac_offset;
008652b3 13145 int addr_ok = 0;
1da177e4 13146
49b6e95f 13147#ifdef CONFIG_SPARC
1da177e4
LT		 13148 if (!tg3_get_macaddr_sparc(tp))
13149 return 0;
13150#endif
13151
13152 mac_offset = 0x7c;
f49639e6 13153 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13154 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13155 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13156 mac_offset = 0xcc;
13157 if (tg3_nvram_lock(tp))
13158 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13159 else
13160 tg3_nvram_unlock(tp);
a1b950d5
MC		 13161 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13162 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13163 mac_offset = 0xcc;
13164 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13165 mac_offset = 0x10;
1da177e4
LT		 13166
13167 /* First try to get it from MAC address mailbox. */
13168 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13169 if ((hi >> 16) == 0x484b) {
13170 dev->dev_addr[0] = (hi >> 8) & 0xff;
13171 dev->dev_addr[1] = (hi >> 0) & 0xff;
13172
13173 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13174 dev->dev_addr[2] = (lo >> 24) & 0xff;
13175 dev->dev_addr[3] = (lo >> 16) & 0xff;
13176 dev->dev_addr[4] = (lo >> 8) & 0xff;
13177 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13178
008652b3
MC		 13179 /* Some old bootcode may report a 0 MAC address in SRAM */
13180 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13181 }
13182 if (!addr_ok) {
13183 /* Next, try NVRAM. */
df259d8c
MC		 13184 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13185 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13186 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13187 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13188 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13189 }
13190 /* Finally just fetch it out of the MAC control regs. */
13191 else {
13192 hi = tr32(MAC_ADDR_0_HIGH);
13193 lo = tr32(MAC_ADDR_0_LOW);
13194
13195 dev->dev_addr[5] = lo & 0xff;
13196 dev->dev_addr[4] = (lo >> 8) & 0xff;
13197 dev->dev_addr[3] = (lo >> 16) & 0xff;
13198 dev->dev_addr[2] = (lo >> 24) & 0xff;
13199 dev->dev_addr[1] = hi & 0xff;
13200 dev->dev_addr[0] = (hi >> 8) & 0xff;
13201 }
1da177e4
LT		 13202 }
13203
13204 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13205#ifdef CONFIG_SPARC
1da177e4
LT		 13206 if (!tg3_get_default_macaddr_sparc(tp))
13207 return 0;
13208#endif
13209 return -EINVAL;
13210 }
2ff43697 13211 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13212 return 0;
13213}
13214
59e6b434
DM		 13215#define BOUNDARY_SINGLE_CACHELINE 1
13216#define BOUNDARY_MULTI_CACHELINE 2
13217
13218static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13219{
13220 int cacheline_size;
13221 u8 byte;
13222 int goal;
13223
13224 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13225 if (byte == 0)
13226 cacheline_size = 1024;
13227 else
13228 cacheline_size = (int) byte * 4;
13229
13230 /* On 5703 and later chips, the boundary bits have no
13231 * effect.
13232 */
13233 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13234 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13235 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13236 goto out;
13237
13238#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13239 goal = BOUNDARY_MULTI_CACHELINE;
13240#else
13241#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13242 goal = BOUNDARY_SINGLE_CACHELINE;
13243#else
13244 goal = 0;
13245#endif
13246#endif
13247
13248 if (!goal)
13249 goto out;
13250
13251 /* PCI controllers on most RISC systems tend to disconnect
13252 * when a device tries to burst across a cache-line boundary.
13253 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13254 *
13255 * Unfortunately, for PCI-E there are only limited
13256 * write-side controls for this, and thus for reads
13257 * we will still get the disconnects. We'll also waste
13258 * these PCI cycles for both read and write for chips
13259 * other than 5700 and 5701 which do not implement the
13260 * boundary bits.
13261 */
13262 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13263 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13264 switch (cacheline_size) {
13265 case 16:
13266 case 32:
13267 case 64:
13268 case 128:
13269 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13270 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13271 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13272 } else {
13273 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13274 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13275 }
13276 break;
13277
13278 case 256:
13279 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13280 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13281 break;
13282
13283 default:
13284 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13285 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13286 break;
855e1111 13287 }
59e6b434
DM		 13288 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13289 switch (cacheline_size) {
13290 case 16:
13291 case 32:
13292 case 64:
13293 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13294 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13295 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13296 break;
13297 }
13298 /* fallthrough */
13299 case 128:
13300 default:
13301 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13302 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13303 break;
855e1111 13304 }
59e6b434
DM		 13305 } else {
13306 switch (cacheline_size) {
13307 case 16:
13308 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13309 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13310 DMA_RWCTRL_WRITE_BNDRY_16);
13311 break;
13312 }
13313 /* fallthrough */
13314 case 32:
13315 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13316 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13317 DMA_RWCTRL_WRITE_BNDRY_32);
13318 break;
13319 }
13320 /* fallthrough */
13321 case 64:
13322 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13323 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13324 DMA_RWCTRL_WRITE_BNDRY_64);
13325 break;
13326 }
13327 /* fallthrough */
13328 case 128:
13329 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13330 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13331 DMA_RWCTRL_WRITE_BNDRY_128);
13332 break;
13333 }
13334 /* fallthrough */
13335 case 256:
13336 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13337 DMA_RWCTRL_WRITE_BNDRY_256);
13338 break;
13339 case 512:
13340 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13341 DMA_RWCTRL_WRITE_BNDRY_512);
13342 break;
13343 case 1024:
13344 default:
13345 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13346 DMA_RWCTRL_WRITE_BNDRY_1024);
13347 break;
855e1111 13348 }
59e6b434
DM		 13349 }
13350
13351out:
13352 return val;
13353}
13354
1da177e4
LT		 13355static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13356{
13357 struct tg3_internal_buffer_desc test_desc;
13358 u32 sram_dma_descs;
13359 int i, ret;
13360
13361 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13362
13363 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13364 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13365 tw32(RDMAC_STATUS, 0);
13366 tw32(WDMAC_STATUS, 0);
13367
13368 tw32(BUFMGR_MODE, 0);
13369 tw32(FTQ_RESET, 0);
13370
13371 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13372 test_desc.addr_lo = buf_dma & 0xffffffff;
13373 test_desc.nic_mbuf = 0x00002100;
13374 test_desc.len = size;
13375
13376 /*
13377 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13378 * the *second* time the tg3 driver was getting loaded after an
13379 * initial scan.
13380 *
13381 * Broadcom tells me:
13382 * ...the DMA engine is connected to the GRC block and a DMA
13383 * reset may affect the GRC block in some unpredictable way...
13384 * The behavior of resets to individual blocks has not been tested.
13385 *
13386 * Broadcom noted the GRC reset will also reset all sub-components.
13387 */
13388 if (to_device) {
13389 test_desc.cqid_sqid = (13 << 8) | 2;
13390
13391 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13392 udelay(40);
13393 } else {
13394 test_desc.cqid_sqid = (16 << 8) | 7;
13395
13396 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13397 udelay(40);
13398 }
13399 test_desc.flags = 0x00000005;
13400
13401 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13402 u32 val;
13403
13404 val = *(((u32 *)&test_desc) + i);
13405 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13406 sram_dma_descs + (i * sizeof(u32)));
13407 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13408 }
13409 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13410
13411 if (to_device) {
13412 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13413 } else {
13414 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13415 }
13416
13417 ret = -ENODEV;
13418 for (i = 0; i < 40; i++) {
13419 u32 val;
13420
13421 if (to_device)
13422 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13423 else
13424 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13425 if ((val & 0xffff) == sram_dma_descs) {
13426 ret = 0;
13427 break;
13428 }
13429
13430 udelay(100);
13431 }
13432
13433 return ret;
13434}
13435
ded7340d 13436#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13437
13438static int __devinit tg3_test_dma(struct tg3 *tp)
13439{
13440 dma_addr_t buf_dma;
59e6b434 13441 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13442 int ret;
13443
13444 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13445 if (!buf) {
13446 ret = -ENOMEM;
13447 goto out_nofree;
13448 }
13449
13450 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13451 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13452
59e6b434 13453 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13454
13455 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13456 /* DMA read watermark not used on PCIE */
13457 tp->dma_rwctrl |= 0x00180000;
13458 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13460 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13461 tp->dma_rwctrl |= 0x003f0000;
13462 else
13463 tp->dma_rwctrl |= 0x003f000f;
13464 } else {
13465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13467 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13468 u32 read_water = 0x7;
1da177e4 13469
4a29cc2e
MC		 13470 /* If the 5704 is behind the EPB bridge, we can
13471 * do the less restrictive ONE_DMA workaround for
13472 * better performance.
13473 */
13474 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13476 tp->dma_rwctrl |= 0x8000;
13477 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13478 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13479
49afdeb6
MC		 13480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13481 read_water = 4;
59e6b434 13482 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13483 tp->dma_rwctrl |=
13484 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13485 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13486 (1 << 23);
4cf78e4f
MC		 13487 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13488 /* 5780 always in PCIX mode */
13489 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13490 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13491 /* 5714 always in PCIX mode */
13492 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13493 } else {
13494 tp->dma_rwctrl |= 0x001b000f;
13495 }
13496 }
13497
13498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13499 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13500 tp->dma_rwctrl &= 0xfffffff0;
13501
13502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13504 /* Remove this if it causes problems for some boards. */
13505 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13506
13507 /* On 5700/5701 chips, we need to set this bit.
13508 * Otherwise the chip will issue cacheline transactions
13509 * to streamable DMA memory with not all the byte
13510 * enables turned on. This is an error on several
13511 * RISC PCI controllers, in particular sparc64.
13512 *
13513 * On 5703/5704 chips, this bit has been reassigned
13514 * a different meaning. In particular, it is used
13515 * on those chips to enable a PCI-X workaround.
13516 */
13517 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13518 }
13519
13520 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13521
13522#if 0
13523 /* Unneeded, already done by tg3_get_invariants. */
13524 tg3_switch_clocks(tp);
13525#endif
13526
13527 ret = 0;
13528 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13529 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13530 goto out;
13531
59e6b434
DM		 13532 /* It is best to perform DMA test with maximum write burst size
13533 * to expose the 5700/5701 write DMA bug.
13534 */
13535 saved_dma_rwctrl = tp->dma_rwctrl;
13536 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13537 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13538
1da177e4
LT		 13539 while (1) {
13540 u32 *p = buf, i;
13541
13542 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13543 p[i] = i;
13544
13545 /* Send the buffer to the chip. */
13546 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13547 if (ret) {
13548 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13549 break;
13550 }
13551
13552#if 0
13553 /* validate data reached card RAM correctly. */
13554 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13555 u32 val;
13556 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13557 if (le32_to_cpu(val) != p[i]) {
13558 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13559 /* ret = -ENODEV here? */
13560 }
13561 p[i] = 0;
13562 }
13563#endif
13564 /* Now read it back. */
13565 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13566 if (ret) {
13567 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13568
13569 break;
13570 }
13571
13572 /* Verify it. */
13573 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13574 if (p[i] == i)
13575 continue;
13576
59e6b434
DM		 13577 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13578 DMA_RWCTRL_WRITE_BNDRY_16) {
13579 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13580 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13581 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13582 break;
13583 } else {
13584 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13585 ret = -ENODEV;
13586 goto out;
13587 }
13588 }
13589
13590 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13591 /* Success. */
13592 ret = 0;
13593 break;
13594 }
13595 }
59e6b434
DM		 13596 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13597 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13598 static struct pci_device_id dma_wait_state_chipsets[] = {
13599 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13600 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13601 { },
13602 };
13603
59e6b434 13604 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13605 * now look for chipsets that are known to expose the
13606 * DMA bug without failing the test.
59e6b434 13607 */
6d1cfbab
MC		 13608 if (pci_dev_present(dma_wait_state_chipsets)) {
13609 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13610 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13611 }
13612 else
13613 /* Safe to use the calculated DMA boundary. */
13614 tp->dma_rwctrl = saved_dma_rwctrl;
13615
59e6b434
DM		 13616 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13617 }
1da177e4
LT		 13618
13619out:
13620 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13621out_nofree:
13622 return ret;
13623}
13624
13625static void __devinit tg3_init_link_config(struct tg3 *tp)
13626{
13627 tp->link_config.advertising =
13628 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13629 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13630 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13631 ADVERTISED_Autoneg | ADVERTISED_MII);
13632 tp->link_config.speed = SPEED_INVALID;
13633 tp->link_config.duplex = DUPLEX_INVALID;
13634 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13635 tp->link_config.active_speed = SPEED_INVALID;
13636 tp->link_config.active_duplex = DUPLEX_INVALID;
13637 tp->link_config.phy_is_low_power = 0;
13638 tp->link_config.orig_speed = SPEED_INVALID;
13639 tp->link_config.orig_duplex = DUPLEX_INVALID;
13640 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13641}
13642
13643static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13644{
f6eb9b1f
MC		 13645 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13646 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13647 tp->bufmgr_config.mbuf_read_dma_low_water =
13648 DEFAULT_MB_RDMA_LOW_WATER_5705;
13649 tp->bufmgr_config.mbuf_mac_rx_low_water =
13650 DEFAULT_MB_MACRX_LOW_WATER_5705;
13651 tp->bufmgr_config.mbuf_high_water =
13652 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13653 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13654 tp->bufmgr_config.mbuf_mac_rx_low_water =
13655 DEFAULT_MB_MACRX_LOW_WATER_5906;
13656 tp->bufmgr_config.mbuf_high_water =
13657 DEFAULT_MB_HIGH_WATER_5906;
13658 }
fdfec172
MC		 13659
13660 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13661 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13662 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13663 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13664 tp->bufmgr_config.mbuf_high_water_jumbo =
13665 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13666 } else {
13667 tp->bufmgr_config.mbuf_read_dma_low_water =
13668 DEFAULT_MB_RDMA_LOW_WATER;
13669 tp->bufmgr_config.mbuf_mac_rx_low_water =
13670 DEFAULT_MB_MACRX_LOW_WATER;
13671 tp->bufmgr_config.mbuf_high_water =
13672 DEFAULT_MB_HIGH_WATER;
13673
13674 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13675 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13676 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13677 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13678 tp->bufmgr_config.mbuf_high_water_jumbo =
13679 DEFAULT_MB_HIGH_WATER_JUMBO;
13680 }
1da177e4
LT		 13681
13682 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13683 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13684}
13685
13686static char * __devinit tg3_phy_string(struct tg3 *tp)
13687{
13688 switch (tp->phy_id & PHY_ID_MASK) {
13689 case PHY_ID_BCM5400: return "5400";
13690 case PHY_ID_BCM5401: return "5401";
13691 case PHY_ID_BCM5411: return "5411";
13692 case PHY_ID_BCM5701: return "5701";
13693 case PHY_ID_BCM5703: return "5703";
13694 case PHY_ID_BCM5704: return "5704";
13695 case PHY_ID_BCM5705: return "5705";
13696 case PHY_ID_BCM5750: return "5750";
85e94ced 13697 case PHY_ID_BCM5752: return "5752";
a4e2b347 13698 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13699 case PHY_ID_BCM5780: return "5780";
af36e6b6 13700 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13701 case PHY_ID_BCM5787: return "5787";
d30cdd28 13702 case PHY_ID_BCM5784: return "5784";
126a3368 13703 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13704 case PHY_ID_BCM5906: return "5906";
9936bcf6 13705 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13706 case PHY_ID_BCM8002: return "8002/serdes";
13707 case 0: return "serdes";
13708 default: return "unknown";
855e1111 13709 }
1da177e4
LT		 13710}
13711
f9804ddb
MC		 13712static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13713{
13714 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13715 strcpy(str, "PCI Express");
13716 return str;
13717 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13718 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13719
13720 strcpy(str, "PCIX:");
13721
13722 if ((clock_ctrl == 7) ||
13723 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13724 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13725 strcat(str, "133MHz");
13726 else if (clock_ctrl == 0)
13727 strcat(str, "33MHz");
13728 else if (clock_ctrl == 2)
13729 strcat(str, "50MHz");
13730 else if (clock_ctrl == 4)
13731 strcat(str, "66MHz");
13732 else if (clock_ctrl == 6)
13733 strcat(str, "100MHz");
f9804ddb
MC		 13734 } else {
13735 strcpy(str, "PCI:");
13736 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13737 strcat(str, "66MHz");
13738 else
13739 strcat(str, "33MHz");
13740 }
13741 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13742 strcat(str, ":32-bit");
13743 else
13744 strcat(str, ":64-bit");
13745 return str;
13746}
13747
8c2dc7e1 13748static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13749{
13750 struct pci_dev *peer;
13751 unsigned int func, devnr = tp->pdev->devfn & ~7;
13752
13753 for (func = 0; func < 8; func++) {
13754 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13755 if (peer && peer != tp->pdev)
13756 break;
13757 pci_dev_put(peer);
13758 }
16fe9d74
MC		 13759 /* 5704 can be configured in single-port mode, set peer to
13760 * tp->pdev in that case.
13761 */
13762 if (!peer) {
13763 peer = tp->pdev;
13764 return peer;
13765 }
1da177e4
LT		 13766
13767 /*
13768 * We don't need to keep the refcount elevated; there's no way
13769 * to remove one half of this device without removing the other
13770 */
13771 pci_dev_put(peer);
13772
13773 return peer;
13774}
13775
15f9850d
DM		 13776static void __devinit tg3_init_coal(struct tg3 *tp)
13777{
13778 struct ethtool_coalesce *ec = &tp->coal;
13779
13780 memset(ec, 0, sizeof(*ec));
13781 ec->cmd = ETHTOOL_GCOALESCE;
13782 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13783 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13784 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13785 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13786 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13787 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13788 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13789 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13790 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13791
13792 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13793 HOSTCC_MODE_CLRTICK_TXBD)) {
13794 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13795 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13796 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13797 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13798 }
d244c892
MC		 13799
13800 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13801 ec->rx_coalesce_usecs_irq = 0;
13802 ec->tx_coalesce_usecs_irq = 0;
13803 ec->stats_block_coalesce_usecs = 0;
13804 }
15f9850d
DM		 13805}
13806
7c7d64b8
SH		 13807static const struct net_device_ops tg3_netdev_ops = {
13808 .ndo_open = tg3_open,
13809 .ndo_stop = tg3_close,
00829823
SH		 13810 .ndo_start_xmit = tg3_start_xmit,
13811 .ndo_get_stats = tg3_get_stats,
13812 .ndo_validate_addr = eth_validate_addr,
13813 .ndo_set_multicast_list = tg3_set_rx_mode,
13814 .ndo_set_mac_address = tg3_set_mac_addr,
13815 .ndo_do_ioctl = tg3_ioctl,
13816 .ndo_tx_timeout = tg3_tx_timeout,
13817 .ndo_change_mtu = tg3_change_mtu,
13818#if TG3_VLAN_TAG_USED
13819 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13820#endif
13821#ifdef CONFIG_NET_POLL_CONTROLLER
13822 .ndo_poll_controller = tg3_poll_controller,
13823#endif
13824};
13825
13826static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13827 .ndo_open = tg3_open,
13828 .ndo_stop = tg3_close,
13829 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13830 .ndo_get_stats = tg3_get_stats,
13831 .ndo_validate_addr = eth_validate_addr,
13832 .ndo_set_multicast_list = tg3_set_rx_mode,
13833 .ndo_set_mac_address = tg3_set_mac_addr,
13834 .ndo_do_ioctl = tg3_ioctl,
13835 .ndo_tx_timeout = tg3_tx_timeout,
13836 .ndo_change_mtu = tg3_change_mtu,
13837#if TG3_VLAN_TAG_USED
13838 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13839#endif
13840#ifdef CONFIG_NET_POLL_CONTROLLER
13841 .ndo_poll_controller = tg3_poll_controller,
13842#endif
13843};
13844
1da177e4
LT		 13845static int __devinit tg3_init_one(struct pci_dev *pdev,
13846 const struct pci_device_id *ent)
13847{
13848 static int tg3_version_printed = 0;
1da177e4
LT		 13849 struct net_device *dev;
13850 struct tg3 *tp;
646c9edd
MC		 13851 int i, err, pm_cap;
13852 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13853 char str[40];
72f2afb8 13854 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13855
13856 if (tg3_version_printed++ == 0)
13857 printk(KERN_INFO "%s", version);
13858
13859 err = pci_enable_device(pdev);
13860 if (err) {
13861 printk(KERN_ERR PFX "Cannot enable PCI device, "
13862 "aborting.\n");
13863 return err;
13864 }
13865
1da177e4
LT		 13866 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13867 if (err) {
13868 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13869 "aborting.\n");
13870 goto err_out_disable_pdev;
13871 }
13872
13873 pci_set_master(pdev);
13874
13875 /* Find power-management capability. */
13876 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13877 if (pm_cap == 0) {
13878 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13879 "aborting.\n");
13880 err = -EIO;
13881 goto err_out_free_res;
13882 }
13883
fe5f5787 13884 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 13885 if (!dev) {
13886 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13887 err = -ENOMEM;
13888 goto err_out_free_res;
13889 }
13890
1da177e4
LT		 13891 SET_NETDEV_DEV(dev, &pdev->dev);
13892
1da177e4
LT		 13893#if TG3_VLAN_TAG_USED
13894 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13895#endif
13896
13897 tp = netdev_priv(dev);
13898 tp->pdev = pdev;
13899 tp->dev = dev;
13900 tp->pm_cap = pm_cap;
1da177e4
LT		 13901 tp->rx_mode = TG3_DEF_RX_MODE;
13902 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13903
1da177e4
LT		 13904 if (tg3_debug > 0)
13905 tp->msg_enable = tg3_debug;
13906 else
13907 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13908
13909 /* The word/byte swap controls here control register access byte
13910 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13911 * setting below.
13912 */
13913 tp->misc_host_ctrl =
13914 MISC_HOST_CTRL_MASK_PCI_INT |
13915 MISC_HOST_CTRL_WORD_SWAP |
13916 MISC_HOST_CTRL_INDIR_ACCESS |
13917 MISC_HOST_CTRL_PCISTATE_RW;
13918
13919 /* The NONFRM (non-frame) byte/word swap controls take effect
13920 * on descriptor entries, anything which isn't packet data.
13921 *
13922 * The StrongARM chips on the board (one for tx, one for rx)
13923 * are running in big-endian mode.
13924 */
13925 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13926 GRC_MODE_WSWAP_NONFRM_DATA);
13927#ifdef __BIG_ENDIAN
13928 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13929#endif
13930 spin_lock_init(&tp->lock);
1da177e4 13931 spin_lock_init(&tp->indirect_lock);
c4028958 13932 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13933
d5fe488a 13934 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13935 if (!tp->regs) {
1da177e4
LT		 13936 printk(KERN_ERR PFX "Cannot map device registers, "
13937 "aborting.\n");
13938 err = -ENOMEM;
13939 goto err_out_free_dev;
13940 }
13941
13942 tg3_init_link_config(tp);
13943
1da177e4
LT		 13944 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13945 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13946
646c9edd
MC		 13947 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13948 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13949 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13950 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13951 struct tg3_napi *tnapi = &tp->napi[i];
13952
13953 tnapi->tp = tp;
13954 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13955
13956 tnapi->int_mbox = intmbx;
13957 if (i < 4)
13958 intmbx += 0x8;
13959 else
13960 intmbx += 0x4;
13961
13962 tnapi->consmbox = rcvmbx;
13963 tnapi->prodmbox = sndmbx;
13964
13965 if (i)
13966 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13967 else
13968 tnapi->coal_now = HOSTCC_MODE_NOW;
13969
13970 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13971 break;
13972
13973 /*
13974 * If we support MSIX, we'll be using RSS. If we're using
13975 * RSS, the first vector only handles link interrupts and the
13976 * remaining vectors handle rx and tx interrupts. Reuse the
13977 * mailbox values for the next iteration. The values we setup
13978 * above are still useful for the single vectored mode.
13979 */
13980 if (!i)
13981 continue;
13982
13983 rcvmbx += 0x8;
13984
13985 if (sndmbx & 0x4)
13986 sndmbx -= 0x4;
13987 else
13988 sndmbx += 0xc;
13989 }
13990
8ef0442f 13991 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 13992 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13993 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13994 dev->irq = pdev->irq;
1da177e4
LT		 13995
13996 err = tg3_get_invariants(tp);
13997 if (err) {
13998 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13999 "aborting.\n");
14000 goto err_out_iounmap;
14001 }
14002
92c6b8d1 14003 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
00829823
SH		 14004 dev->netdev_ops = &tg3_netdev_ops;
14005 else
14006 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14007
14008
4a29cc2e
MC		 14009 /* The EPB bridge inside 5714, 5715, and 5780 and any
14010 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14011 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14012 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14013 * do DMA address check in tg3_start_xmit().
14014 */
4a29cc2e 14015 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14016 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14017 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14018 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14019#ifdef CONFIG_HIGHMEM
6a35528a 14020 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14021#endif
4a29cc2e 14022 } else
6a35528a 14023 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14024
14025 /* Configure DMA attributes. */
284901a9 14026 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14027 err = pci_set_dma_mask(pdev, dma_mask);
14028 if (!err) {
14029 dev->features |= NETIF_F_HIGHDMA;
14030 err = pci_set_consistent_dma_mask(pdev,
14031 persist_dma_mask);
14032 if (err < 0) {
14033 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14034 "DMA for consistent allocations\n");
14035 goto err_out_iounmap;
14036 }
14037 }
14038 }
284901a9
YH		 14039 if (err || dma_mask == DMA_BIT_MASK(32)) {
14040 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14041 if (err) {
14042 printk(KERN_ERR PFX "No usable DMA configuration, "
14043 "aborting.\n");
14044 goto err_out_iounmap;
14045 }
14046 }
14047
fdfec172 14048 tg3_init_bufmgr_config(tp);
1da177e4 14049
077f849d 14050 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 14051 tp->fw_needed = FIRMWARE_TG3;
077f849d 14052
1da177e4
LT		 14053 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14054 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14055 }
14056 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14058 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 14059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 14060 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14061 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14062 } else {
7f62ad5d 14063 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 14064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 14065 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 14066 else
9e9fd12d 14067 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 14068 }
1da177e4 14069
4e3a7aaa
MC		 14070 /* TSO is on by default on chips that support hardware TSO.
14071 * Firmware TSO on older chips gives lower performance, so it
14072 * is off by default, but can be enabled using ethtool.
14073 */
b0026624 14074 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 14075 if (dev->features & NETIF_F_IP_CSUM)
14076 dev->features |= NETIF_F_TSO;
14077 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14078 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 14079 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 14080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14081 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14082 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14083 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 14084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6 14086 dev->features |= NETIF_F_TSO_ECN;
b0026624 14087 }
1da177e4 14088
1da177e4
LT		 14089
14090 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14091 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14092 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14093 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14094 tp->rx_pending = 63;
14095 }
14096
1da177e4
LT		 14097 err = tg3_get_device_address(tp);
14098 if (err) {
14099 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14100 "aborting.\n");
077f849d 14101 goto err_out_fw;
1da177e4
LT		 14102 }
14103
c88864df 14104 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14105 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14106 if (!tp->aperegs) {
c88864df
MC		 14107 printk(KERN_ERR PFX "Cannot map APE registers, "
14108 "aborting.\n");
14109 err = -ENOMEM;
077f849d 14110 goto err_out_fw;
c88864df
MC		 14111 }
14112
14113 tg3_ape_lock_init(tp);
7fd76445
MC		 14114
14115 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14116 tg3_read_dash_ver(tp);
c88864df
MC		 14117 }
14118
1da177e4
LT		 14119 /*
14120 * Reset chip in case UNDI or EFI driver did not shutdown
14121 * DMA self test will enable WDMAC and we'll see (spurious)
14122 * pending DMA on the PCI bus at that point.
14123 */
14124 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14125 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14126 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14127 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14128 }
14129
14130 err = tg3_test_dma(tp);
14131 if (err) {
14132 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14133 goto err_out_apeunmap;
1da177e4
LT		 14134 }
14135
1da177e4
LT		 14136 /* flow control autonegotiation is default behavior */
14137 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14138 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14139
15f9850d
DM		 14140 tg3_init_coal(tp);
14141
c49a1561
MC		 14142 pci_set_drvdata(pdev, dev);
14143
1da177e4
LT		 14144 err = register_netdev(dev);
14145 if (err) {
14146 printk(KERN_ERR PFX "Cannot register net device, "
14147 "aborting.\n");
0d3031d9 14148 goto err_out_apeunmap;
1da177e4
LT		 14149 }
14150
df59c940 14151 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14152 dev->name,
14153 tp->board_part_number,
14154 tp->pci_chip_rev_id,
f9804ddb 14155 tg3_bus_string(tp, str),
e174961c 14156 dev->dev_addr);
1da177e4 14157
df59c940
MC		 14158 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
14159 printk(KERN_INFO
14160 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14161 tp->dev->name,
14162 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 14163 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 14164 else
14165 printk(KERN_INFO
14166 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14167 tp->dev->name, tg3_phy_string(tp),
14168 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14169 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14170 "10/100/1000Base-T")),
14171 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14172
14173 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14174 dev->name,
14175 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14176 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14177 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14178 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14179 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14180 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14181 dev->name, tp->dma_rwctrl,
284901a9 14182 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14183 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14184
14185 return 0;
14186
0d3031d9
MC		 14187err_out_apeunmap:
14188 if (tp->aperegs) {
14189 iounmap(tp->aperegs);
14190 tp->aperegs = NULL;
14191 }
14192
077f849d
JSR		 14193err_out_fw:
14194 if (tp->fw)
14195 release_firmware(tp->fw);
14196
1da177e4 14197err_out_iounmap:
6892914f
MC		 14198 if (tp->regs) {
14199 iounmap(tp->regs);
22abe310 14200 tp->regs = NULL;
6892914f 14201 }
1da177e4
LT		 14202
14203err_out_free_dev:
14204 free_netdev(dev);
14205
14206err_out_free_res:
14207 pci_release_regions(pdev);
14208
14209err_out_disable_pdev:
14210 pci_disable_device(pdev);
14211 pci_set_drvdata(pdev, NULL);
14212 return err;
14213}
14214
14215static void __devexit tg3_remove_one(struct pci_dev *pdev)
14216{
14217 struct net_device *dev = pci_get_drvdata(pdev);
14218
14219 if (dev) {
14220 struct tg3 *tp = netdev_priv(dev);
14221
077f849d
JSR		 14222 if (tp->fw)
14223 release_firmware(tp->fw);
14224
7faa006f 14225 flush_scheduled_work();
158d7abd 14226
b02fd9e3
MC		 14227 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14228 tg3_phy_fini(tp);
158d7abd 14229 tg3_mdio_fini(tp);
b02fd9e3 14230 }
158d7abd 14231
1da177e4 14232 unregister_netdev(dev);
0d3031d9
MC		 14233 if (tp->aperegs) {
14234 iounmap(tp->aperegs);
14235 tp->aperegs = NULL;
14236 }
6892914f
MC		 14237 if (tp->regs) {
14238 iounmap(tp->regs);
22abe310 14239 tp->regs = NULL;
6892914f 14240 }
1da177e4
LT		 14241 free_netdev(dev);
14242 pci_release_regions(pdev);
14243 pci_disable_device(pdev);
14244 pci_set_drvdata(pdev, NULL);
14245 }
14246}
14247
14248static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14249{
14250 struct net_device *dev = pci_get_drvdata(pdev);
14251 struct tg3 *tp = netdev_priv(dev);
12dac075 14252 pci_power_t target_state;
1da177e4
LT		 14253 int err;
14254
3e0c95fd
MC		 14255 /* PCI register 4 needs to be saved whether netif_running() or not.
14256 * MSI address and data need to be saved if using MSI and
14257 * netif_running().
14258 */
14259 pci_save_state(pdev);
14260
1da177e4
LT		 14261 if (!netif_running(dev))
14262 return 0;
14263
7faa006f 14264 flush_scheduled_work();
b02fd9e3 14265 tg3_phy_stop(tp);
1da177e4
LT		 14266 tg3_netif_stop(tp);
14267
14268 del_timer_sync(&tp->timer);
14269
f47c11ee 14270 tg3_full_lock(tp, 1);
1da177e4 14271 tg3_disable_ints(tp);
f47c11ee 14272 tg3_full_unlock(tp);
1da177e4
LT		 14273
14274 netif_device_detach(dev);
14275
f47c11ee 14276 tg3_full_lock(tp, 0);
944d980e 14277 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14278 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14279 tg3_full_unlock(tp);
1da177e4 14280
12dac075
RW		 14281 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14282
14283 err = tg3_set_power_state(tp, target_state);
1da177e4 14284 if (err) {
b02fd9e3
MC		 14285 int err2;
14286
f47c11ee 14287 tg3_full_lock(tp, 0);
1da177e4 14288
6a9eba15 14289 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14290 err2 = tg3_restart_hw(tp, 1);
14291 if (err2)
b9ec6c1b 14292 goto out;
1da177e4
LT		 14293
14294 tp->timer.expires = jiffies + tp->timer_offset;
14295 add_timer(&tp->timer);
14296
14297 netif_device_attach(dev);
14298 tg3_netif_start(tp);
14299
b9ec6c1b 14300out:
f47c11ee 14301 tg3_full_unlock(tp);
b02fd9e3
MC		 14302
14303 if (!err2)
14304 tg3_phy_start(tp);
1da177e4
LT		 14305 }
14306
14307 return err;
14308}
14309
14310static int tg3_resume(struct pci_dev *pdev)
14311{
14312 struct net_device *dev = pci_get_drvdata(pdev);
14313 struct tg3 *tp = netdev_priv(dev);
14314 int err;
14315
3e0c95fd
MC		 14316 pci_restore_state(tp->pdev);
14317
1da177e4
LT		 14318 if (!netif_running(dev))
14319 return 0;
14320
bc1c7567 14321 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14322 if (err)
14323 return err;
14324
14325 netif_device_attach(dev);
14326
f47c11ee 14327 tg3_full_lock(tp, 0);
1da177e4 14328
6a9eba15 14329 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14330 err = tg3_restart_hw(tp, 1);
14331 if (err)
14332 goto out;
1da177e4
LT		 14333
14334 tp->timer.expires = jiffies + tp->timer_offset;
14335 add_timer(&tp->timer);
14336
1da177e4
LT		 14337 tg3_netif_start(tp);
14338
b9ec6c1b 14339out:
f47c11ee 14340 tg3_full_unlock(tp);
1da177e4 14341
b02fd9e3
MC		 14342 if (!err)
14343 tg3_phy_start(tp);
14344
b9ec6c1b 14345 return err;
1da177e4
LT		 14346}
14347
14348static struct pci_driver tg3_driver = {
14349 .name = DRV_MODULE_NAME,
14350 .id_table = tg3_pci_tbl,
14351 .probe = tg3_init_one,
14352 .remove = __devexit_p(tg3_remove_one),
14353 .suspend = tg3_suspend,
14354 .resume = tg3_resume
14355};
14356
14357static int __init tg3_init(void)
14358{
29917620 14359 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14360}
14361
14362static void __exit tg3_cleanup(void)
14363{
14364 pci_unregister_driver(&tg3_driver);
14365}
14366
14367module_init(tg3_init);
14368module_exit(tg3_cleanup);
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