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tg3: Invert nvram_read() and nvram_read_swab()
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
d3d31709
MC		 71#define DRV_MODULE_VERSION "3.97"
72#define DRV_MODULE_RELDATE "December 10, 2008"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
1da177e4
LT		 235};
236
237MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
50da859d 239static const struct {
1da177e4
LT		 240 const char string[ETH_GSTRING_LEN];
241} ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318};
319
50da859d 320static const struct {
4cafd3f5
MC		 321 const char string[ETH_GSTRING_LEN];
322} ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329};
330
b401e9e2
MC		 331static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332{
333 writel(val, tp->regs + off);
334}
335
336static u32 tg3_read32(struct tg3 *tp, u32 off)
337{
6aa20a22 338 return (readl(tp->regs + off));
b401e9e2
MC		 339}
340
0d3031d9
MC		 341static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342{
343 writel(val, tp->aperegs + off);
344}
345
346static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347{
348 return (readl(tp->aperegs + off));
349}
350
1da177e4
LT		 351static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352{
6892914f
MC		 353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 359}
360
361static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
1da177e4
LT		 365}
366
6892914f 367static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 368{
6892914f
MC		 369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377}
378
379static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
1da177e4 392 }
6892914f
MC		 393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407}
408
409static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410{
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419}
420
b401e9e2
MC		 421/* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 427{
b401e9e2
MC		 428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
1da177e4
LT		 444}
445
09ee929c
MC		 446static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447{
448 tp->write32_mbox(tp, off, val);
6892914f
MC		 449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
09ee929c
MC		 452}
453
20094930 454static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 455{
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462}
463
b5d3772c
MC		 464static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465{
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467}
468
469static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472}
473
20094930 474#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 475#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 476#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 478#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 479
480#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 481#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 483#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 484
485static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486{
6892914f
MC		 487 unsigned long flags;
488
b5d3772c
MC		 489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
6892914f 493 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 497
bbadf503
MC		 498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 508}
509
1da177e4
LT		 510static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
6892914f 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 535}
536
0d3031d9
MC		 537static void tg3_ape_lock_init(struct tg3 *tp)
538{
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545}
546
547static int tg3_ape_lock(struct tg3 *tp, int locknum)
548{
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
77b483f1 557 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585}
586
587static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588{
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
77b483f1 595 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604}
605
1da177e4
LT		 606static void tg3_disable_ints(struct tg3 *tp)
607{
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 611}
612
613static inline void tg3_cond_int(struct tg3 *tp)
614{
38f3843e
MC		 615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 621}
622
623static void tg3_enable_ints(struct tg3 *tp)
624{
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
fcfa0a32
MC		 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
1da177e4
LT		 635 tg3_cond_int(tp);
636}
637
04237ddd
MC		 638static inline unsigned int tg3_has_work(struct tg3 *tp)
639{
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656}
657
1da177e4 658/* tg3_restart_ints
04237ddd
MC		 659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
6aa20a22 661 * which reenables interrupts
1da177e4
LT		 662 */
663static void tg3_restart_ints(struct tg3 *tp)
664{
fac9b83e
DM		 665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
1da177e4
LT		 667 mmiowb();
668
fac9b83e
DM		 669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
04237ddd
MC		 675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 677}
678
679static inline void tg3_netif_stop(struct tg3 *tp)
680{
bbe832c0 681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 682 napi_disable(&tp->napi);
1da177e4
LT		 683 netif_tx_disable(tp->dev);
684}
685
686static inline void tg3_netif_start(struct tg3 *tp)
687{
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
bea3348e 693 napi_enable(&tp->napi);
f47c11ee
DM		 694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
1da177e4
LT		 696}
697
698static void tg3_switch_clocks(struct tg3 *tp)
699{
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
795d01c5
MC		 703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 705 return;
706
1da177e4
LT		 707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
1da177e4 726 }
b401e9e2 727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 728}
729
730#define PHY_BUSY_LOOPS 5000
731
732static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733{
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 751
1da177e4
LT		 752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779}
780
781static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782{
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
b5d3772c
MC		 787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
1da177e4
LT		 791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 803
1da177e4
LT		 804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828}
829
95e2869a
MC		 830static int tg3_bmcr_reset(struct tg3 *tp)
831{
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
d4675b52 855 if (limit < 0)
95e2869a
MC		 856 return -EBUSY;
857
858 return 0;
859}
860
158d7abd
MC		 861static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862{
3d16543d 863 struct tg3 *tp = bp->priv;
158d7abd
MC		 864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873}
874
875static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876{
3d16543d 877 struct tg3 *tp = bp->priv;
158d7abd
MC		 878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886}
887
888static int tg3_mdio_reset(struct mii_bus *bp)
889{
890 return 0;
891}
892
9c61d6bc 893static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 894{
895 u32 val;
fcb389df 896 struct phy_device *phydev;
a9daf367 897
fcb389df
MC		 898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
a9daf367 913 return;
fcb389df
MC		 914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
a9daf367
MC		 946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
fcb389df 954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966}
967
158d7abd
MC		 968static void tg3_mdio_start(struct tg3 *tp)
969{
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 971 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 973 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
a9daf367 979
9c61d6bc
MC		 980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
158d7abd
MC		 983}
984
985static void tg3_mdio_stop(struct tg3 *tp)
986{
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 988 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 990 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 991 }
992}
993
994static int tg3_mdio_init(struct tg3 *tp)
995{
996 int i;
997 u32 reg;
a9daf367 998 struct phy_device *phydev;
158d7abd
MC		 999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
298cf9be
LB		 1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
158d7abd 1009
298cf9be
LB		 1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1022 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
298cf9be 1032 i = mdiobus_register(tp->mdio_bus);
a9daf367 1033 if (i) {
158d7abd
MC		 1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
9c61d6bc 1036 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1037 return i;
1038 }
158d7abd 1039
298cf9be 1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1041
9c61d6bc
MC		 1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
a9daf367 1053 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1063 break;
fcb389df 1064 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
9c61d6bc
MC		 1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
a9daf367
MC		 1074
1075 return 0;
158d7abd
MC		 1076}
1077
1078static void tg3_mdio_fini(struct tg3 *tp)
1079{
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086}
1087
4ba526ce
MC		 1088/* tp->lock is held. */
1089static inline void tg3_generate_fw_event(struct tg3 *tp)
1090{
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098}
1099
1100#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
95e2869a
MC		 1102/* tp->lock is held. */
1103static void tg3_wait_for_event_ack(struct tg3 *tp)
1104{
1105 int i;
4ba526ce
MC		 1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1121
4ba526ce 1122 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
4ba526ce 1125 udelay(8);
95e2869a
MC		 1126 }
1127}
1128
1129/* tp->lock is held. */
1130static void tg3_ump_link_report(struct tg3 *tp)
1131{
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
4ba526ce 1174 tg3_generate_fw_event(tp);
95e2869a
MC		 1175}
1176
1177static void tg3_link_report(struct tg3 *tp)
1178{
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
e18ce346 1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1198 "on" : "off",
e18ce346 1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203}
1204
1205static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206{
1207 u16 miireg;
1208
e18ce346 1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1210 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1211 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1212 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1213 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219}
1220
1221static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
95e2869a
MC		 1237static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238{
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1246 cap = FLOW_CTRL_RX;
95e2869a
MC		 1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1253 cap = FLOW_CTRL_TX;
95e2869a
MC		 1254 }
1255
1256 return cap;
1257}
1258
f51f3562 1259static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1260{
b02fd9e3 1261 u8 autoneg;
f51f3562 1262 u8 flowctrl = 0;
95e2869a
MC		 1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
b02fd9e3 1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1275 else
bc02ff95 1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1277 } else
1278 flowctrl = tp->link_config.flowctrl;
95e2869a 1279
f51f3562 1280 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1281
e18ce346 1282 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
f51f3562 1287 if (old_rx_mode != tp->rx_mode)
95e2869a 1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1289
e18ce346 1290 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
f51f3562 1295 if (old_tx_mode != tp->tx_mode)
95e2869a 1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1297}
1298
b02fd9e3
MC		 1299static void tg3_adjust_link(struct net_device *dev)
1300{
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
298cf9be 1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
fcb389df
MC		 1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
b02fd9e3
MC		 1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378}
1379
1380static int tg3_phy_init(struct tg3 *tp)
1381{
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
298cf9be 1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1391
1392 /* Attach the MAC to the PHY. */
fb28ad35 1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1394 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
b02fd9e3 1400 /* Mask with MAC supported features. */
9c61d6bc
MC		 1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
9c61d6bc
MC		 1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1422
1423 phydev->advertising = phydev->supported;
1424
b02fd9e3
MC		 1425 return 0;
1426}
1427
1428static void tg3_phy_start(struct tg3 *tp)
1429{
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
298cf9be 1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448}
1449
1450static void tg3_phy_stop(struct tg3 *tp)
1451{
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
298cf9be 1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1456}
1457
1458static void tg3_phy_fini(struct tg3 *tp)
1459{
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464}
1465
b2a5c19c
MC		 1466static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467{
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470}
1471
6833c043
MC		 1472static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473{
1474 u32 reg;
1475
a6435f3a
MC		 1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6833c043
MC		 1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499}
1500
9ef8ca99
MC		 1501static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502{
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537}
1538
1da177e4
LT		 1539static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540{
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550}
1551
b2a5c19c
MC		 1552static void tg3_phy_apply_otp(struct tg3 *tp)
1553{
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593}
1594
1da177e4
LT		 1595static int tg3_wait_macro_done(struct tg3 *tp)
1596{
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
d4675b52 1607 if (limit < 0)
1da177e4
LT		 1608 return -EBUSY;
1609
1610 return 0;
1611}
1612
1613static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614{
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680{
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697}
1698
1699static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700{
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773}
1774
1775/* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778static int tg3_phy_reset(struct tg3 *tp)
1779{
b2a5c19c 1780 u32 cpmuctrl;
1da177e4
LT		 1781 u32 phy_status;
1782 int err;
1783
60189ddf
MC		 1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1da177e4
LT		 1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
c8e1e82b
MC		 1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1da177e4
LT		 1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
b2a5c19c
MC		 1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1da177e4
LT		 1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
b2a5c19c
MC		 1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
bcb37f6c
MC		 1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
b2a5c19c
MC		 1845 tg3_phy_apply_otp(tp);
1846
6833c043
MC		 1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1da177e4
LT		 1852out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
c424cb24
MC		 1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1da177e4
LT		 1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
0f893dc6 1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
715116a1 1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1914 }
1915
9ef8ca99 1916 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919}
1920
1921static void tg3_frob_aux_power(struct tg3 *tp)
1922{
1923 struct tg3 *tp_peer = tp;
1924
9d26e213 1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1926 return;
1927
8c2dc7e1
MC		 1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1933 /* remove_one() may have been run on the peer. */
8c2dc7e1 1934 if (!dev_peer)
bc1c7567
MC		 1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1938 }
1939
1da177e4 1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
5f0c4a3c
MC		 1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956 GRC_LCLCTRL_GPIO_OE1 |
1957 GRC_LCLCTRL_GPIO_OE2 |
1958 GRC_LCLCTRL_GPIO_OUTPUT0 |
1959 GRC_LCLCTRL_GPIO_OUTPUT1 |
1960 tp->grc_local_ctrl;
1961 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1968 } else {
1969 u32 no_gpio2;
dc56b7d4 1970 u32 grc_local_ctrl = 0;
1da177e4
LT		 1971
1972 if (tp_peer != tp &&
1973 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974 return;
1975
dc56b7d4
MC		 1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978 ASIC_REV_5714) {
1979 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1980 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981 grc_local_ctrl, 100);
dc56b7d4
MC		 1982 }
1983
1da177e4
LT		 1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2 = tp->nic_sram_data_cfg &
1986 NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
dc56b7d4 1988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1 |
1992 GRC_LCLCTRL_GPIO_OUTPUT2;
1993 if (no_gpio2) {
1994 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995 GRC_LCLCTRL_GPIO_OUTPUT2);
1996 }
b401e9e2
MC		 1997 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998 grc_local_ctrl, 100);
1da177e4
LT		 1999
2000 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
b401e9e2
MC		 2002 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003 grc_local_ctrl, 100);
1da177e4
LT		 2004
2005 if (!no_gpio2) {
2006 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2007 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008 grc_local_ctrl, 100);
1da177e4
LT		 2009 }
2010 }
2011 } else {
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014 if (tp_peer != tp &&
2015 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016 return;
2017
b401e9e2
MC		 2018 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019 (GRC_LCLCTRL_GPIO_OE1 |
2020 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2021
b401e9e2
MC		 2022 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2024
b401e9e2
MC		 2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE1 |
2027 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2028 }
2029 }
2030}
2031
e8f3f6ca
MC		 2032static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033{
2034 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035 return 1;
2036 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037 if (speed != SPEED_10)
2038 return 1;
2039 } else if (speed == SPEED_10)
2040 return 1;
2041
2042 return 0;
2043}
2044
1da177e4
LT		 2045static int tg3_setup_phy(struct tg3 *, int);
2046
2047#define RESET_KIND_SHUTDOWN 0
2048#define RESET_KIND_INIT 1
2049#define RESET_KIND_SUSPEND 2
2050
2051static void tg3_write_sig_post_reset(struct tg3 *, int);
2052static int tg3_halt_cpu(struct tg3 *, u32);
2053
0a459aac 2054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2055{
ce057f01
MC		 2056 u32 val;
2057
5129724a
MC		 2058 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063 sg_dig_ctrl |=
2064 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067 }
3f7045c1 2068 return;
5129724a 2069 }
3f7045c1 2070
60189ddf 2071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2072 tg3_bmcr_reset(tp);
2073 val = tr32(GRC_MISC_CFG);
2074 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075 udelay(40);
2076 return;
0a459aac 2077 } else if (do_low_power) {
715116a1
MC		 2078 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2080
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2086 }
3f7045c1 2087
15c3b696
MC		 2088 /* The PHY should not be powered down on some chips because
2089 * of bugs.
2090 */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095 return;
ce057f01 2096
bcb37f6c
MC		 2097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2099 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103 }
2104
15c3b696
MC		 2105 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106}
2107
ffbcfed4
MC		 2108/* tp->lock is held. */
2109static int tg3_nvram_lock(struct tg3 *tp)
2110{
2111 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112 int i;
2113
2114 if (tp->nvram_lock_cnt == 0) {
2115 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116 for (i = 0; i < 8000; i++) {
2117 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118 break;
2119 udelay(20);
2120 }
2121 if (i == 8000) {
2122 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123 return -ENODEV;
2124 }
2125 }
2126 tp->nvram_lock_cnt++;
2127 }
2128 return 0;
2129}
2130
2131/* tp->lock is held. */
2132static void tg3_nvram_unlock(struct tg3 *tp)
2133{
2134 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135 if (tp->nvram_lock_cnt > 0)
2136 tp->nvram_lock_cnt--;
2137 if (tp->nvram_lock_cnt == 0)
2138 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139 }
2140}
2141
2142/* tp->lock is held. */
2143static void tg3_enable_nvram_access(struct tg3 *tp)
2144{
2145 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150 }
2151}
2152
2153/* tp->lock is held. */
2154static void tg3_disable_nvram_access(struct tg3 *tp)
2155{
2156 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161 }
2162}
2163
2164static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165 u32 offset, u32 *val)
2166{
2167 u32 tmp;
2168 int i;
2169
2170 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171 return -EINVAL;
2172
2173 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174 EEPROM_ADDR_DEVID_MASK |
2175 EEPROM_ADDR_READ);
2176 tw32(GRC_EEPROM_ADDR,
2177 tmp |
2178 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180 EEPROM_ADDR_ADDR_MASK) |
2181 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183 for (i = 0; i < 1000; i++) {
2184 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186 if (tmp & EEPROM_ADDR_COMPLETE)
2187 break;
2188 msleep(1);
2189 }
2190 if (!(tmp & EEPROM_ADDR_COMPLETE))
2191 return -EBUSY;
2192
2193 *val = tr32(GRC_EEPROM_DATA);
2194 return 0;
2195}
2196
2197#define NVRAM_CMD_TIMEOUT 10000
2198
2199static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2200{
2201 int i;
2202
2203 tw32(NVRAM_CMD, nvram_cmd);
2204 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2205 udelay(10);
2206 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2207 udelay(10);
2208 break;
2209 }
2210 }
2211
2212 if (i == NVRAM_CMD_TIMEOUT)
2213 return -EBUSY;
2214
2215 return 0;
2216}
2217
2218static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2219{
2220 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2221 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2222 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2223 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2224 (tp->nvram_jedecnum == JEDEC_ATMEL))
2225
2226 addr = ((addr / tp->nvram_pagesize) <<
2227 ATMEL_AT45DB0X1B_PAGE_POS) +
2228 (addr % tp->nvram_pagesize);
2229
2230 return addr;
2231}
2232
2233static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2234{
2235 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2236 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2237 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2238 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2239 (tp->nvram_jedecnum == JEDEC_ATMEL))
2240
2241 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2242 tp->nvram_pagesize) +
2243 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2244
2245 return addr;
2246}
2247
e4f34110
MC		 2248/* NOTE: Data read in from NVRAM is byteswapped according to
2249 * the byteswapping settings for all other register accesses.
2250 * tg3 devices are BE devices, so on a BE machine, the data
2251 * returned will be exactly as it is seen in NVRAM. On a LE
2252 * machine, the 32-bit value will be byteswapped.
2253 */
ffbcfed4
MC		 2254static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2255{
2256 int ret;
2257
2258 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2259 return tg3_nvram_read_using_eeprom(tp, offset, val);
2260
2261 offset = tg3_nvram_phys_addr(tp, offset);
2262
2263 if (offset > NVRAM_ADDR_MSK)
2264 return -EINVAL;
2265
2266 ret = tg3_nvram_lock(tp);
2267 if (ret)
2268 return ret;
2269
2270 tg3_enable_nvram_access(tp);
2271
2272 tw32(NVRAM_ADDR, offset);
2273 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2274 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2275
2276 if (ret == 0)
e4f34110 2277 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2278
2279 tg3_disable_nvram_access(tp);
2280
2281 tg3_nvram_unlock(tp);
2282
2283 return ret;
2284}
2285
2286static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
2287{
2288 int err;
2289 u32 tmp;
2290
2291 err = tg3_nvram_read(tp, offset, &tmp);
2292 *val = swab32(tmp);
2293 return err;
2294}
2295
2296static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
2297{
2298 u32 v;
e4f34110 2299 int res = tg3_nvram_read_swab(tp, offset, &v);
ffbcfed4
MC		 2300 if (!res)
2301 *val = cpu_to_le32(v);
2302 return res;
2303}
2304
3f007891
MC		 2305/* tp->lock is held. */
2306static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2307{
2308 u32 addr_high, addr_low;
2309 int i;
2310
2311 addr_high = ((tp->dev->dev_addr[0] << 8) |
2312 tp->dev->dev_addr[1]);
2313 addr_low = ((tp->dev->dev_addr[2] << 24) |
2314 (tp->dev->dev_addr[3] << 16) |
2315 (tp->dev->dev_addr[4] << 8) |
2316 (tp->dev->dev_addr[5] << 0));
2317 for (i = 0; i < 4; i++) {
2318 if (i == 1 && skip_mac_1)
2319 continue;
2320 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2321 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2322 }
2323
2324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2325 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2326 for (i = 0; i < 12; i++) {
2327 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2328 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2329 }
2330 }
2331
2332 addr_high = (tp->dev->dev_addr[0] +
2333 tp->dev->dev_addr[1] +
2334 tp->dev->dev_addr[2] +
2335 tp->dev->dev_addr[3] +
2336 tp->dev->dev_addr[4] +
2337 tp->dev->dev_addr[5]) &
2338 TX_BACKOFF_SEED_MASK;
2339 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2340}
2341
bc1c7567 2342static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2343{
2344 u32 misc_host_ctrl;
0a459aac 2345 bool device_should_wake, do_low_power;
1da177e4
LT		 2346
2347 /* Make sure register accesses (indirect or otherwise)
2348 * will function correctly.
2349 */
2350 pci_write_config_dword(tp->pdev,
2351 TG3PCI_MISC_HOST_CTRL,
2352 tp->misc_host_ctrl);
2353
1da177e4 2354 switch (state) {
bc1c7567 2355 case PCI_D0:
12dac075
RW		 2356 pci_enable_wake(tp->pdev, state, false);
2357 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2358
9d26e213
MC		 2359 /* Switch out of Vaux if it is a NIC */
2360 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2361 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2362
2363 return 0;
2364
bc1c7567 2365 case PCI_D1:
bc1c7567 2366 case PCI_D2:
bc1c7567 2367 case PCI_D3hot:
1da177e4
LT		 2368 break;
2369
2370 default:
12dac075
RW		 2371 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2372 tp->dev->name, state);
1da177e4 2373 return -EINVAL;
855e1111 2374 }
5e7dfd0f
MC		 2375
2376 /* Restore the CLKREQ setting. */
2377 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2378 u16 lnkctl;
2379
2380 pci_read_config_word(tp->pdev,
2381 tp->pcie_cap + PCI_EXP_LNKCTL,
2382 &lnkctl);
2383 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2384 pci_write_config_word(tp->pdev,
2385 tp->pcie_cap + PCI_EXP_LNKCTL,
2386 lnkctl);
2387 }
2388
1da177e4
LT		 2389 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2390 tw32(TG3PCI_MISC_HOST_CTRL,
2391 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2392
05ac4cb7
MC		 2393 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2394 device_may_wakeup(&tp->pdev->dev) &&
2395 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2396
dd477003 2397 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2398 do_low_power = false;
b02fd9e3
MC		 2399 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2400 !tp->link_config.phy_is_low_power) {
2401 struct phy_device *phydev;
0a459aac 2402 u32 phyid, advertising;
b02fd9e3 2403
298cf9be 2404 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2405
2406 tp->link_config.phy_is_low_power = 1;
2407
2408 tp->link_config.orig_speed = phydev->speed;
2409 tp->link_config.orig_duplex = phydev->duplex;
2410 tp->link_config.orig_autoneg = phydev->autoneg;
2411 tp->link_config.orig_advertising = phydev->advertising;
2412
2413 advertising = ADVERTISED_TP |
2414 ADVERTISED_Pause |
2415 ADVERTISED_Autoneg |
2416 ADVERTISED_10baseT_Half;
2417
2418 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2419 device_should_wake) {
b02fd9e3
MC		 2420 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2421 advertising |=
2422 ADVERTISED_100baseT_Half |
2423 ADVERTISED_100baseT_Full |
2424 ADVERTISED_10baseT_Full;
2425 else
2426 advertising |= ADVERTISED_10baseT_Full;
2427 }
2428
2429 phydev->advertising = advertising;
2430
2431 phy_start_aneg(phydev);
0a459aac
MC		 2432
2433 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2434 if (phyid != TG3_PHY_ID_BCMAC131) {
2435 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2436 if (phyid == TG3_PHY_OUI_1 ||
2437 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2438 phyid == TG3_PHY_OUI_3)
2439 do_low_power = true;
2440 }
b02fd9e3 2441 }
dd477003 2442 } else {
2023276e 2443 do_low_power = true;
0a459aac 2444
dd477003
MC		 2445 if (tp->link_config.phy_is_low_power == 0) {
2446 tp->link_config.phy_is_low_power = 1;
2447 tp->link_config.orig_speed = tp->link_config.speed;
2448 tp->link_config.orig_duplex = tp->link_config.duplex;
2449 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2450 }
1da177e4 2451
dd477003
MC		 2452 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2453 tp->link_config.speed = SPEED_10;
2454 tp->link_config.duplex = DUPLEX_HALF;
2455 tp->link_config.autoneg = AUTONEG_ENABLE;
2456 tg3_setup_phy(tp, 0);
2457 }
1da177e4
LT		 2458 }
2459
3f007891
MC		 2460 __tg3_set_mac_addr(tp, 0);
2461
b5d3772c
MC		 2462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2463 u32 val;
2464
2465 val = tr32(GRC_VCPU_EXT_CTRL);
2466 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2467 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2468 int i;
2469 u32 val;
2470
2471 for (i = 0; i < 200; i++) {
2472 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2473 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2474 break;
2475 msleep(1);
2476 }
2477 }
a85feb8c
GZ		 2478 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2479 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2480 WOL_DRV_STATE_SHUTDOWN |
2481 WOL_DRV_WOL |
2482 WOL_SET_MAGIC_PKT);
6921d201 2483
05ac4cb7 2484 if (device_should_wake) {
1da177e4
LT		 2485 u32 mac_mode;
2486
2487 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2488 if (do_low_power) {
dd477003
MC		 2489 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2490 udelay(40);
2491 }
1da177e4 2492
3f7045c1
MC		 2493 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2494 mac_mode = MAC_MODE_PORT_MODE_GMII;
2495 else
2496 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2497
e8f3f6ca
MC		 2498 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2499 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2500 ASIC_REV_5700) {
2501 u32 speed = (tp->tg3_flags &
2502 TG3_FLAG_WOL_SPEED_100MB) ?
2503 SPEED_100 : SPEED_10;
2504 if (tg3_5700_link_polarity(tp, speed))
2505 mac_mode |= MAC_MODE_LINK_POLARITY;
2506 else
2507 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2508 }
1da177e4
LT		 2509 } else {
2510 mac_mode = MAC_MODE_PORT_MODE_TBI;
2511 }
2512
cbf46853 2513 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2514 tw32(MAC_LED_CTRL, tp->led_ctrl);
2515
05ac4cb7
MC		 2516 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2517 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2518 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2519 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2520 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2521 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2522
3bda1258
MC		 2523 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2524 mac_mode |= tp->mac_mode &
2525 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2526 if (mac_mode & MAC_MODE_APE_TX_EN)
2527 mac_mode |= MAC_MODE_TDE_ENABLE;
2528 }
2529
1da177e4
LT		 2530 tw32_f(MAC_MODE, mac_mode);
2531 udelay(100);
2532
2533 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2534 udelay(10);
2535 }
2536
2537 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2538 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2539 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2540 u32 base_val;
2541
2542 base_val = tp->pci_clock_ctrl;
2543 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2544 CLOCK_CTRL_TXCLK_DISABLE);
2545
b401e9e2
MC		 2546 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2547 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2548 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2549 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2550 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2551 /* do nothing */
85e94ced 2552 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2553 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2554 u32 newbits1, newbits2;
2555
2556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2558 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2559 CLOCK_CTRL_TXCLK_DISABLE |
2560 CLOCK_CTRL_ALTCLK);
2561 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2562 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2563 newbits1 = CLOCK_CTRL_625_CORE;
2564 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2565 } else {
2566 newbits1 = CLOCK_CTRL_ALTCLK;
2567 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2568 }
2569
b401e9e2
MC		 2570 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2571 40);
1da177e4 2572
b401e9e2
MC		 2573 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2574 40);
1da177e4
LT		 2575
2576 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2577 u32 newbits3;
2578
2579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2581 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2582 CLOCK_CTRL_TXCLK_DISABLE |
2583 CLOCK_CTRL_44MHZ_CORE);
2584 } else {
2585 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2586 }
2587
b401e9e2
MC		 2588 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2589 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2590 }
2591 }
2592
05ac4cb7 2593 if (!(device_should_wake) &&
22435849 2594 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2595 tg3_power_down_phy(tp, do_low_power);
6921d201 2596
1da177e4
LT		 2597 tg3_frob_aux_power(tp);
2598
2599 /* Workaround for unstable PLL clock */
2600 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2601 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2602 u32 val = tr32(0x7d00);
2603
2604 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2605 tw32(0x7d00, val);
6921d201 2606 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2607 int err;
2608
2609 err = tg3_nvram_lock(tp);
1da177e4 2610 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2611 if (!err)
2612 tg3_nvram_unlock(tp);
6921d201 2613 }
1da177e4
LT		 2614 }
2615
bbadf503
MC		 2616 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2617
05ac4cb7 2618 if (device_should_wake)
12dac075
RW		 2619 pci_enable_wake(tp->pdev, state, true);
2620
1da177e4 2621 /* Finally, set the new power state. */
12dac075 2622 pci_set_power_state(tp->pdev, state);
1da177e4 2623
1da177e4
LT		 2624 return 0;
2625}
2626
1da177e4
LT		 2627static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2628{
2629 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2630 case MII_TG3_AUX_STAT_10HALF:
2631 *speed = SPEED_10;
2632 *duplex = DUPLEX_HALF;
2633 break;
2634
2635 case MII_TG3_AUX_STAT_10FULL:
2636 *speed = SPEED_10;
2637 *duplex = DUPLEX_FULL;
2638 break;
2639
2640 case MII_TG3_AUX_STAT_100HALF:
2641 *speed = SPEED_100;
2642 *duplex = DUPLEX_HALF;
2643 break;
2644
2645 case MII_TG3_AUX_STAT_100FULL:
2646 *speed = SPEED_100;
2647 *duplex = DUPLEX_FULL;
2648 break;
2649
2650 case MII_TG3_AUX_STAT_1000HALF:
2651 *speed = SPEED_1000;
2652 *duplex = DUPLEX_HALF;
2653 break;
2654
2655 case MII_TG3_AUX_STAT_1000FULL:
2656 *speed = SPEED_1000;
2657 *duplex = DUPLEX_FULL;
2658 break;
2659
2660 default:
715116a1
MC		 2661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2662 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2663 SPEED_10;
2664 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2665 DUPLEX_HALF;
2666 break;
2667 }
1da177e4
LT		 2668 *speed = SPEED_INVALID;
2669 *duplex = DUPLEX_INVALID;
2670 break;
855e1111 2671 }
1da177e4
LT		 2672}
2673
2674static void tg3_phy_copper_begin(struct tg3 *tp)
2675{
2676 u32 new_adv;
2677 int i;
2678
2679 if (tp->link_config.phy_is_low_power) {
2680 /* Entering low power mode. Disable gigabit and
2681 * 100baseT advertisements.
2682 */
2683 tg3_writephy(tp, MII_TG3_CTRL, 0);
2684
2685 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2686 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2687 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2688 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2689
2690 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2691 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2692 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2693 tp->link_config.advertising &=
2694 ~(ADVERTISED_1000baseT_Half |
2695 ADVERTISED_1000baseT_Full);
2696
ba4d07a8 2697 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2698 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2699 new_adv |= ADVERTISE_10HALF;
2700 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2701 new_adv |= ADVERTISE_10FULL;
2702 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2703 new_adv |= ADVERTISE_100HALF;
2704 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2705 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2706
2707 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2708
1da177e4
LT		 2709 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2710
2711 if (tp->link_config.advertising &
2712 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2713 new_adv = 0;
2714 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2715 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2716 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2717 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2718 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2719 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2720 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2721 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2722 MII_TG3_CTRL_ENABLE_AS_MASTER);
2723 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2724 } else {
2725 tg3_writephy(tp, MII_TG3_CTRL, 0);
2726 }
2727 } else {
ba4d07a8
MC		 2728 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2729 new_adv |= ADVERTISE_CSMA;
2730
1da177e4
LT		 2731 /* Asking for a specific link mode. */
2732 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2733 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2734
2735 if (tp->link_config.duplex == DUPLEX_FULL)
2736 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2737 else
2738 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2739 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2740 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2741 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2742 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2743 } else {
1da177e4
LT		 2744 if (tp->link_config.speed == SPEED_100) {
2745 if (tp->link_config.duplex == DUPLEX_FULL)
2746 new_adv |= ADVERTISE_100FULL;
2747 else
2748 new_adv |= ADVERTISE_100HALF;
2749 } else {
2750 if (tp->link_config.duplex == DUPLEX_FULL)
2751 new_adv |= ADVERTISE_10FULL;
2752 else
2753 new_adv |= ADVERTISE_10HALF;
2754 }
2755 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2756
2757 new_adv = 0;
1da177e4 2758 }
ba4d07a8
MC		 2759
2760 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2761 }
2762
2763 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2764 tp->link_config.speed != SPEED_INVALID) {
2765 u32 bmcr, orig_bmcr;
2766
2767 tp->link_config.active_speed = tp->link_config.speed;
2768 tp->link_config.active_duplex = tp->link_config.duplex;
2769
2770 bmcr = 0;
2771 switch (tp->link_config.speed) {
2772 default:
2773 case SPEED_10:
2774 break;
2775
2776 case SPEED_100:
2777 bmcr |= BMCR_SPEED100;
2778 break;
2779
2780 case SPEED_1000:
2781 bmcr |= TG3_BMCR_SPEED1000;
2782 break;
855e1111 2783 }
1da177e4
LT		 2784
2785 if (tp->link_config.duplex == DUPLEX_FULL)
2786 bmcr |= BMCR_FULLDPLX;
2787
2788 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2789 (bmcr != orig_bmcr)) {
2790 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2791 for (i = 0; i < 1500; i++) {
2792 u32 tmp;
2793
2794 udelay(10);
2795 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2796 tg3_readphy(tp, MII_BMSR, &tmp))
2797 continue;
2798 if (!(tmp & BMSR_LSTATUS)) {
2799 udelay(40);
2800 break;
2801 }
2802 }
2803 tg3_writephy(tp, MII_BMCR, bmcr);
2804 udelay(40);
2805 }
2806 } else {
2807 tg3_writephy(tp, MII_BMCR,
2808 BMCR_ANENABLE | BMCR_ANRESTART);
2809 }
2810}
2811
2812static int tg3_init_5401phy_dsp(struct tg3 *tp)
2813{
2814 int err;
2815
2816 /* Turn off tap power management. */
2817 /* Set Extended packet length bit */
2818 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2819
2820 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2821 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2822
2823 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2824 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2825
2826 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2827 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2828
2829 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2830 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2831
2832 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2833 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2834
2835 udelay(40);
2836
2837 return err;
2838}
2839
3600d918 2840static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2841{
3600d918
MC		 2842 u32 adv_reg, all_mask = 0;
2843
2844 if (mask & ADVERTISED_10baseT_Half)
2845 all_mask |= ADVERTISE_10HALF;
2846 if (mask & ADVERTISED_10baseT_Full)
2847 all_mask |= ADVERTISE_10FULL;
2848 if (mask & ADVERTISED_100baseT_Half)
2849 all_mask |= ADVERTISE_100HALF;
2850 if (mask & ADVERTISED_100baseT_Full)
2851 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2852
2853 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2854 return 0;
2855
1da177e4
LT		 2856 if ((adv_reg & all_mask) != all_mask)
2857 return 0;
2858 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2859 u32 tg3_ctrl;
2860
3600d918
MC		 2861 all_mask = 0;
2862 if (mask & ADVERTISED_1000baseT_Half)
2863 all_mask |= ADVERTISE_1000HALF;
2864 if (mask & ADVERTISED_1000baseT_Full)
2865 all_mask |= ADVERTISE_1000FULL;
2866
1da177e4
LT		 2867 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2868 return 0;
2869
1da177e4
LT		 2870 if ((tg3_ctrl & all_mask) != all_mask)
2871 return 0;
2872 }
2873 return 1;
2874}
2875
ef167e27
MC		 2876static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2877{
2878 u32 curadv, reqadv;
2879
2880 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2881 return 1;
2882
2883 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2884 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2885
2886 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2887 if (curadv != reqadv)
2888 return 0;
2889
2890 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2891 tg3_readphy(tp, MII_LPA, rmtadv);
2892 } else {
2893 /* Reprogram the advertisement register, even if it
2894 * does not affect the current link. If the link
2895 * gets renegotiated in the future, we can save an
2896 * additional renegotiation cycle by advertising
2897 * it correctly in the first place.
2898 */
2899 if (curadv != reqadv) {
2900 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2901 ADVERTISE_PAUSE_ASYM);
2902 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2903 }
2904 }
2905
2906 return 1;
2907}
2908
1da177e4
LT		 2909static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2910{
2911 int current_link_up;
2912 u32 bmsr, dummy;
ef167e27 2913 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2914 u16 current_speed;
2915 u8 current_duplex;
2916 int i, err;
2917
2918 tw32(MAC_EVENT, 0);
2919
2920 tw32_f(MAC_STATUS,
2921 (MAC_STATUS_SYNC_CHANGED |
2922 MAC_STATUS_CFG_CHANGED |
2923 MAC_STATUS_MI_COMPLETION |
2924 MAC_STATUS_LNKSTATE_CHANGED));
2925 udelay(40);
2926
8ef21428
MC		 2927 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2928 tw32_f(MAC_MI_MODE,
2929 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2930 udelay(80);
2931 }
1da177e4
LT		 2932
2933 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2934
2935 /* Some third-party PHYs need to be reset on link going
2936 * down.
2937 */
2938 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2941 netif_carrier_ok(tp->dev)) {
2942 tg3_readphy(tp, MII_BMSR, &bmsr);
2943 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2944 !(bmsr & BMSR_LSTATUS))
2945 force_reset = 1;
2946 }
2947 if (force_reset)
2948 tg3_phy_reset(tp);
2949
2950 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2951 tg3_readphy(tp, MII_BMSR, &bmsr);
2952 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2953 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2954 bmsr = 0;
2955
2956 if (!(bmsr & BMSR_LSTATUS)) {
2957 err = tg3_init_5401phy_dsp(tp);
2958 if (err)
2959 return err;
2960
2961 tg3_readphy(tp, MII_BMSR, &bmsr);
2962 for (i = 0; i < 1000; i++) {
2963 udelay(10);
2964 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2965 (bmsr & BMSR_LSTATUS)) {
2966 udelay(40);
2967 break;
2968 }
2969 }
2970
2971 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2972 !(bmsr & BMSR_LSTATUS) &&
2973 tp->link_config.active_speed == SPEED_1000) {
2974 err = tg3_phy_reset(tp);
2975 if (!err)
2976 err = tg3_init_5401phy_dsp(tp);
2977 if (err)
2978 return err;
2979 }
2980 }
2981 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2982 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2983 /* 5701 {A0,B0} CRC bug workaround */
2984 tg3_writephy(tp, 0x15, 0x0a75);
2985 tg3_writephy(tp, 0x1c, 0x8c68);
2986 tg3_writephy(tp, 0x1c, 0x8d68);
2987 tg3_writephy(tp, 0x1c, 0x8c68);
2988 }
2989
2990 /* Clear pending interrupts... */
2991 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2992 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2993
2994 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2995 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2996 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2997 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2998
2999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3001 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3002 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3003 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3004 else
3005 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3006 }
3007
3008 current_link_up = 0;
3009 current_speed = SPEED_INVALID;
3010 current_duplex = DUPLEX_INVALID;
3011
3012 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3013 u32 val;
3014
3015 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3016 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3017 if (!(val & (1 << 10))) {
3018 val |= (1 << 10);
3019 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3020 goto relink;
3021 }
3022 }
3023
3024 bmsr = 0;
3025 for (i = 0; i < 100; i++) {
3026 tg3_readphy(tp, MII_BMSR, &bmsr);
3027 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3028 (bmsr & BMSR_LSTATUS))
3029 break;
3030 udelay(40);
3031 }
3032
3033 if (bmsr & BMSR_LSTATUS) {
3034 u32 aux_stat, bmcr;
3035
3036 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3037 for (i = 0; i < 2000; i++) {
3038 udelay(10);
3039 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3040 aux_stat)
3041 break;
3042 }
3043
3044 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3045 &current_speed,
3046 &current_duplex);
3047
3048 bmcr = 0;
3049 for (i = 0; i < 200; i++) {
3050 tg3_readphy(tp, MII_BMCR, &bmcr);
3051 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3052 continue;
3053 if (bmcr && bmcr != 0x7fff)
3054 break;
3055 udelay(10);
3056 }
3057
ef167e27
MC		 3058 lcl_adv = 0;
3059 rmt_adv = 0;
1da177e4 3060
ef167e27
MC		 3061 tp->link_config.active_speed = current_speed;
3062 tp->link_config.active_duplex = current_duplex;
3063
3064 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3065 if ((bmcr & BMCR_ANENABLE) &&
3066 tg3_copper_is_advertising_all(tp,
3067 tp->link_config.advertising)) {
3068 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3069 &rmt_adv))
3070 current_link_up = 1;
1da177e4
LT		 3071 }
3072 } else {
3073 if (!(bmcr & BMCR_ANENABLE) &&
3074 tp->link_config.speed == current_speed &&
ef167e27
MC		 3075 tp->link_config.duplex == current_duplex &&
3076 tp->link_config.flowctrl ==
3077 tp->link_config.active_flowctrl) {
1da177e4 3078 current_link_up = 1;
1da177e4
LT		 3079 }
3080 }
3081
ef167e27
MC		 3082 if (current_link_up == 1 &&
3083 tp->link_config.active_duplex == DUPLEX_FULL)
3084 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3085 }
3086
1da177e4 3087relink:
6921d201 3088 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3089 u32 tmp;
3090
3091 tg3_phy_copper_begin(tp);
3092
3093 tg3_readphy(tp, MII_BMSR, &tmp);
3094 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3095 (tmp & BMSR_LSTATUS))
3096 current_link_up = 1;
3097 }
3098
3099 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3100 if (current_link_up == 1) {
3101 if (tp->link_config.active_speed == SPEED_100 ||
3102 tp->link_config.active_speed == SPEED_10)
3103 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3104 else
3105 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3106 } else
3107 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3108
3109 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3110 if (tp->link_config.active_duplex == DUPLEX_HALF)
3111 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3112
1da177e4 3113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3114 if (current_link_up == 1 &&
3115 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3116 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3117 else
3118 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3119 }
3120
3121 /* ??? Without this setting Netgear GA302T PHY does not
3122 * ??? send/receive packets...
3123 */
3124 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3125 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3126 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3127 tw32_f(MAC_MI_MODE, tp->mi_mode);
3128 udelay(80);
3129 }
3130
3131 tw32_f(MAC_MODE, tp->mac_mode);
3132 udelay(40);
3133
3134 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3135 /* Polled via timer. */
3136 tw32_f(MAC_EVENT, 0);
3137 } else {
3138 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3139 }
3140 udelay(40);
3141
3142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3143 current_link_up == 1 &&
3144 tp->link_config.active_speed == SPEED_1000 &&
3145 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3146 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3147 udelay(120);
3148 tw32_f(MAC_STATUS,
3149 (MAC_STATUS_SYNC_CHANGED |
3150 MAC_STATUS_CFG_CHANGED));
3151 udelay(40);
3152 tg3_write_mem(tp,
3153 NIC_SRAM_FIRMWARE_MBOX,
3154 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3155 }
3156
5e7dfd0f
MC		 3157 /* Prevent send BD corruption. */
3158 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3159 u16 oldlnkctl, newlnkctl;
3160
3161 pci_read_config_word(tp->pdev,
3162 tp->pcie_cap + PCI_EXP_LNKCTL,
3163 &oldlnkctl);
3164 if (tp->link_config.active_speed == SPEED_100 ||
3165 tp->link_config.active_speed == SPEED_10)
3166 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3167 else
3168 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3169 if (newlnkctl != oldlnkctl)
3170 pci_write_config_word(tp->pdev,
3171 tp->pcie_cap + PCI_EXP_LNKCTL,
3172 newlnkctl);
3173 }
3174
1da177e4
LT		 3175 if (current_link_up != netif_carrier_ok(tp->dev)) {
3176 if (current_link_up)
3177 netif_carrier_on(tp->dev);
3178 else
3179 netif_carrier_off(tp->dev);
3180 tg3_link_report(tp);
3181 }
3182
3183 return 0;
3184}
3185
3186struct tg3_fiber_aneginfo {
3187 int state;
3188#define ANEG_STATE_UNKNOWN 0
3189#define ANEG_STATE_AN_ENABLE 1
3190#define ANEG_STATE_RESTART_INIT 2
3191#define ANEG_STATE_RESTART 3
3192#define ANEG_STATE_DISABLE_LINK_OK 4
3193#define ANEG_STATE_ABILITY_DETECT_INIT 5
3194#define ANEG_STATE_ABILITY_DETECT 6
3195#define ANEG_STATE_ACK_DETECT_INIT 7
3196#define ANEG_STATE_ACK_DETECT 8
3197#define ANEG_STATE_COMPLETE_ACK_INIT 9
3198#define ANEG_STATE_COMPLETE_ACK 10
3199#define ANEG_STATE_IDLE_DETECT_INIT 11
3200#define ANEG_STATE_IDLE_DETECT 12
3201#define ANEG_STATE_LINK_OK 13
3202#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3203#define ANEG_STATE_NEXT_PAGE_WAIT 15
3204
3205 u32 flags;
3206#define MR_AN_ENABLE 0x00000001
3207#define MR_RESTART_AN 0x00000002
3208#define MR_AN_COMPLETE 0x00000004
3209#define MR_PAGE_RX 0x00000008
3210#define MR_NP_LOADED 0x00000010
3211#define MR_TOGGLE_TX 0x00000020
3212#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3213#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3214#define MR_LP_ADV_SYM_PAUSE 0x00000100
3215#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3216#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3217#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3218#define MR_LP_ADV_NEXT_PAGE 0x00001000
3219#define MR_TOGGLE_RX 0x00002000
3220#define MR_NP_RX 0x00004000
3221
3222#define MR_LINK_OK 0x80000000
3223
3224 unsigned long link_time, cur_time;
3225
3226 u32 ability_match_cfg;
3227 int ability_match_count;
3228
3229 char ability_match, idle_match, ack_match;
3230
3231 u32 txconfig, rxconfig;
3232#define ANEG_CFG_NP 0x00000080
3233#define ANEG_CFG_ACK 0x00000040
3234#define ANEG_CFG_RF2 0x00000020
3235#define ANEG_CFG_RF1 0x00000010
3236#define ANEG_CFG_PS2 0x00000001
3237#define ANEG_CFG_PS1 0x00008000
3238#define ANEG_CFG_HD 0x00004000
3239#define ANEG_CFG_FD 0x00002000
3240#define ANEG_CFG_INVAL 0x00001f06
3241
3242};
3243#define ANEG_OK 0
3244#define ANEG_DONE 1
3245#define ANEG_TIMER_ENAB 2
3246#define ANEG_FAILED -1
3247
3248#define ANEG_STATE_SETTLE_TIME 10000
3249
3250static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3251 struct tg3_fiber_aneginfo *ap)
3252{
5be73b47 3253 u16 flowctrl;
1da177e4
LT		 3254 unsigned long delta;
3255 u32 rx_cfg_reg;
3256 int ret;
3257
3258 if (ap->state == ANEG_STATE_UNKNOWN) {
3259 ap->rxconfig = 0;
3260 ap->link_time = 0;
3261 ap->cur_time = 0;
3262 ap->ability_match_cfg = 0;
3263 ap->ability_match_count = 0;
3264 ap->ability_match = 0;
3265 ap->idle_match = 0;
3266 ap->ack_match = 0;
3267 }
3268 ap->cur_time++;
3269
3270 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3271 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3272
3273 if (rx_cfg_reg != ap->ability_match_cfg) {
3274 ap->ability_match_cfg = rx_cfg_reg;
3275 ap->ability_match = 0;
3276 ap->ability_match_count = 0;
3277 } else {
3278 if (++ap->ability_match_count > 1) {
3279 ap->ability_match = 1;
3280 ap->ability_match_cfg = rx_cfg_reg;
3281 }
3282 }
3283 if (rx_cfg_reg & ANEG_CFG_ACK)
3284 ap->ack_match = 1;
3285 else
3286 ap->ack_match = 0;
3287
3288 ap->idle_match = 0;
3289 } else {
3290 ap->idle_match = 1;
3291 ap->ability_match_cfg = 0;
3292 ap->ability_match_count = 0;
3293 ap->ability_match = 0;
3294 ap->ack_match = 0;
3295
3296 rx_cfg_reg = 0;
3297 }
3298
3299 ap->rxconfig = rx_cfg_reg;
3300 ret = ANEG_OK;
3301
3302 switch(ap->state) {
3303 case ANEG_STATE_UNKNOWN:
3304 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3305 ap->state = ANEG_STATE_AN_ENABLE;
3306
3307 /* fallthru */
3308 case ANEG_STATE_AN_ENABLE:
3309 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3310 if (ap->flags & MR_AN_ENABLE) {
3311 ap->link_time = 0;
3312 ap->cur_time = 0;
3313 ap->ability_match_cfg = 0;
3314 ap->ability_match_count = 0;
3315 ap->ability_match = 0;
3316 ap->idle_match = 0;
3317 ap->ack_match = 0;
3318
3319 ap->state = ANEG_STATE_RESTART_INIT;
3320 } else {
3321 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3322 }
3323 break;
3324
3325 case ANEG_STATE_RESTART_INIT:
3326 ap->link_time = ap->cur_time;
3327 ap->flags &= ~(MR_NP_LOADED);
3328 ap->txconfig = 0;
3329 tw32(MAC_TX_AUTO_NEG, 0);
3330 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3331 tw32_f(MAC_MODE, tp->mac_mode);
3332 udelay(40);
3333
3334 ret = ANEG_TIMER_ENAB;
3335 ap->state = ANEG_STATE_RESTART;
3336
3337 /* fallthru */
3338 case ANEG_STATE_RESTART:
3339 delta = ap->cur_time - ap->link_time;
3340 if (delta > ANEG_STATE_SETTLE_TIME) {
3341 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3342 } else {
3343 ret = ANEG_TIMER_ENAB;
3344 }
3345 break;
3346
3347 case ANEG_STATE_DISABLE_LINK_OK:
3348 ret = ANEG_DONE;
3349 break;
3350
3351 case ANEG_STATE_ABILITY_DETECT_INIT:
3352 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3353 ap->txconfig = ANEG_CFG_FD;
3354 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3355 if (flowctrl & ADVERTISE_1000XPAUSE)
3356 ap->txconfig |= ANEG_CFG_PS1;
3357 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3358 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3359 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3360 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3361 tw32_f(MAC_MODE, tp->mac_mode);
3362 udelay(40);
3363
3364 ap->state = ANEG_STATE_ABILITY_DETECT;
3365 break;
3366
3367 case ANEG_STATE_ABILITY_DETECT:
3368 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3369 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3370 }
3371 break;
3372
3373 case ANEG_STATE_ACK_DETECT_INIT:
3374 ap->txconfig |= ANEG_CFG_ACK;
3375 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3376 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3377 tw32_f(MAC_MODE, tp->mac_mode);
3378 udelay(40);
3379
3380 ap->state = ANEG_STATE_ACK_DETECT;
3381
3382 /* fallthru */
3383 case ANEG_STATE_ACK_DETECT:
3384 if (ap->ack_match != 0) {
3385 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3386 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3387 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3388 } else {
3389 ap->state = ANEG_STATE_AN_ENABLE;
3390 }
3391 } else if (ap->ability_match != 0 &&
3392 ap->rxconfig == 0) {
3393 ap->state = ANEG_STATE_AN_ENABLE;
3394 }
3395 break;
3396
3397 case ANEG_STATE_COMPLETE_ACK_INIT:
3398 if (ap->rxconfig & ANEG_CFG_INVAL) {
3399 ret = ANEG_FAILED;
3400 break;
3401 }
3402 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3403 MR_LP_ADV_HALF_DUPLEX |
3404 MR_LP_ADV_SYM_PAUSE |
3405 MR_LP_ADV_ASYM_PAUSE |
3406 MR_LP_ADV_REMOTE_FAULT1 |
3407 MR_LP_ADV_REMOTE_FAULT2 |
3408 MR_LP_ADV_NEXT_PAGE |
3409 MR_TOGGLE_RX |
3410 MR_NP_RX);
3411 if (ap->rxconfig & ANEG_CFG_FD)
3412 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3413 if (ap->rxconfig & ANEG_CFG_HD)
3414 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3415 if (ap->rxconfig & ANEG_CFG_PS1)
3416 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3417 if (ap->rxconfig & ANEG_CFG_PS2)
3418 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3419 if (ap->rxconfig & ANEG_CFG_RF1)
3420 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3421 if (ap->rxconfig & ANEG_CFG_RF2)
3422 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3423 if (ap->rxconfig & ANEG_CFG_NP)
3424 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3425
3426 ap->link_time = ap->cur_time;
3427
3428 ap->flags ^= (MR_TOGGLE_TX);
3429 if (ap->rxconfig & 0x0008)
3430 ap->flags |= MR_TOGGLE_RX;
3431 if (ap->rxconfig & ANEG_CFG_NP)
3432 ap->flags |= MR_NP_RX;
3433 ap->flags |= MR_PAGE_RX;
3434
3435 ap->state = ANEG_STATE_COMPLETE_ACK;
3436 ret = ANEG_TIMER_ENAB;
3437 break;
3438
3439 case ANEG_STATE_COMPLETE_ACK:
3440 if (ap->ability_match != 0 &&
3441 ap->rxconfig == 0) {
3442 ap->state = ANEG_STATE_AN_ENABLE;
3443 break;
3444 }
3445 delta = ap->cur_time - ap->link_time;
3446 if (delta > ANEG_STATE_SETTLE_TIME) {
3447 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3448 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3449 } else {
3450 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3451 !(ap->flags & MR_NP_RX)) {
3452 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3453 } else {
3454 ret = ANEG_FAILED;
3455 }
3456 }
3457 }
3458 break;
3459
3460 case ANEG_STATE_IDLE_DETECT_INIT:
3461 ap->link_time = ap->cur_time;
3462 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3463 tw32_f(MAC_MODE, tp->mac_mode);
3464 udelay(40);
3465
3466 ap->state = ANEG_STATE_IDLE_DETECT;
3467 ret = ANEG_TIMER_ENAB;
3468 break;
3469
3470 case ANEG_STATE_IDLE_DETECT:
3471 if (ap->ability_match != 0 &&
3472 ap->rxconfig == 0) {
3473 ap->state = ANEG_STATE_AN_ENABLE;
3474 break;
3475 }
3476 delta = ap->cur_time - ap->link_time;
3477 if (delta > ANEG_STATE_SETTLE_TIME) {
3478 /* XXX another gem from the Broadcom driver :( */
3479 ap->state = ANEG_STATE_LINK_OK;
3480 }
3481 break;
3482
3483 case ANEG_STATE_LINK_OK:
3484 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3485 ret = ANEG_DONE;
3486 break;
3487
3488 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3489 /* ??? unimplemented */
3490 break;
3491
3492 case ANEG_STATE_NEXT_PAGE_WAIT:
3493 /* ??? unimplemented */
3494 break;
3495
3496 default:
3497 ret = ANEG_FAILED;
3498 break;
855e1111 3499 }
1da177e4
LT		 3500
3501 return ret;
3502}
3503
5be73b47 3504static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3505{
3506 int res = 0;
3507 struct tg3_fiber_aneginfo aninfo;
3508 int status = ANEG_FAILED;
3509 unsigned int tick;
3510 u32 tmp;
3511
3512 tw32_f(MAC_TX_AUTO_NEG, 0);
3513
3514 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3515 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3516 udelay(40);
3517
3518 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3519 udelay(40);
3520
3521 memset(&aninfo, 0, sizeof(aninfo));
3522 aninfo.flags |= MR_AN_ENABLE;
3523 aninfo.state = ANEG_STATE_UNKNOWN;
3524 aninfo.cur_time = 0;
3525 tick = 0;
3526 while (++tick < 195000) {
3527 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3528 if (status == ANEG_DONE || status == ANEG_FAILED)
3529 break;
3530
3531 udelay(1);
3532 }
3533
3534 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3535 tw32_f(MAC_MODE, tp->mac_mode);
3536 udelay(40);
3537
5be73b47
MC		 3538 *txflags = aninfo.txconfig;
3539 *rxflags = aninfo.flags;
1da177e4
LT		 3540
3541 if (status == ANEG_DONE &&
3542 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3543 MR_LP_ADV_FULL_DUPLEX)))
3544 res = 1;
3545
3546 return res;
3547}
3548
3549static void tg3_init_bcm8002(struct tg3 *tp)
3550{
3551 u32 mac_status = tr32(MAC_STATUS);
3552 int i;
3553
3554 /* Reset when initting first time or we have a link. */
3555 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3556 !(mac_status & MAC_STATUS_PCS_SYNCED))
3557 return;
3558
3559 /* Set PLL lock range. */
3560 tg3_writephy(tp, 0x16, 0x8007);
3561
3562 /* SW reset */
3563 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3564
3565 /* Wait for reset to complete. */
3566 /* XXX schedule_timeout() ... */
3567 for (i = 0; i < 500; i++)
3568 udelay(10);
3569
3570 /* Config mode; select PMA/Ch 1 regs. */
3571 tg3_writephy(tp, 0x10, 0x8411);
3572
3573 /* Enable auto-lock and comdet, select txclk for tx. */
3574 tg3_writephy(tp, 0x11, 0x0a10);
3575
3576 tg3_writephy(tp, 0x18, 0x00a0);
3577 tg3_writephy(tp, 0x16, 0x41ff);
3578
3579 /* Assert and deassert POR. */
3580 tg3_writephy(tp, 0x13, 0x0400);
3581 udelay(40);
3582 tg3_writephy(tp, 0x13, 0x0000);
3583
3584 tg3_writephy(tp, 0x11, 0x0a50);
3585 udelay(40);
3586 tg3_writephy(tp, 0x11, 0x0a10);
3587
3588 /* Wait for signal to stabilize */
3589 /* XXX schedule_timeout() ... */
3590 for (i = 0; i < 15000; i++)
3591 udelay(10);
3592
3593 /* Deselect the channel register so we can read the PHYID
3594 * later.
3595 */
3596 tg3_writephy(tp, 0x10, 0x8011);
3597}
3598
3599static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3600{
82cd3d11 3601 u16 flowctrl;
1da177e4
LT		 3602 u32 sg_dig_ctrl, sg_dig_status;
3603 u32 serdes_cfg, expected_sg_dig_ctrl;
3604 int workaround, port_a;
3605 int current_link_up;
3606
3607 serdes_cfg = 0;
3608 expected_sg_dig_ctrl = 0;
3609 workaround = 0;
3610 port_a = 1;
3611 current_link_up = 0;
3612
3613 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3614 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3615 workaround = 1;
3616 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3617 port_a = 0;
3618
3619 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3620 /* preserve bits 20-23 for voltage regulator */
3621 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3622 }
3623
3624 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3625
3626 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3627 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3628 if (workaround) {
3629 u32 val = serdes_cfg;
3630
3631 if (port_a)
3632 val |= 0xc010000;
3633 else
3634 val |= 0x4010000;
3635 tw32_f(MAC_SERDES_CFG, val);
3636 }
c98f6e3b
MC		 3637
3638 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3639 }
3640 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3641 tg3_setup_flow_control(tp, 0, 0);
3642 current_link_up = 1;
3643 }
3644 goto out;
3645 }
3646
3647 /* Want auto-negotiation. */
c98f6e3b 3648 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3649
82cd3d11
MC		 3650 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3651 if (flowctrl & ADVERTISE_1000XPAUSE)
3652 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3653 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3654 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3655
3656 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3657 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3658 tp->serdes_counter &&
3659 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3660 MAC_STATUS_RCVD_CFG)) ==
3661 MAC_STATUS_PCS_SYNCED)) {
3662 tp->serdes_counter--;
3663 current_link_up = 1;
3664 goto out;
3665 }
3666restart_autoneg:
1da177e4
LT		 3667 if (workaround)
3668 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3669 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3670 udelay(5);
3671 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3672
3d3ebe74
MC		 3673 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3674 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3675 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3676 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3677 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3678 mac_status = tr32(MAC_STATUS);
3679
c98f6e3b 3680 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3681 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3682 u32 local_adv = 0, remote_adv = 0;
3683
3684 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3685 local_adv |= ADVERTISE_1000XPAUSE;
3686 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3687 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3688
c98f6e3b 3689 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3690 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3691 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3692 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3693
3694 tg3_setup_flow_control(tp, local_adv, remote_adv);
3695 current_link_up = 1;
3d3ebe74
MC		 3696 tp->serdes_counter = 0;
3697 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3698 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3699 if (tp->serdes_counter)
3700 tp->serdes_counter--;
1da177e4
LT		 3701 else {
3702 if (workaround) {
3703 u32 val = serdes_cfg;
3704
3705 if (port_a)
3706 val |= 0xc010000;
3707 else
3708 val |= 0x4010000;
3709
3710 tw32_f(MAC_SERDES_CFG, val);
3711 }
3712
c98f6e3b 3713 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3714 udelay(40);
3715
3716 /* Link parallel detection - link is up */
3717 /* only if we have PCS_SYNC and not */
3718 /* receiving config code words */
3719 mac_status = tr32(MAC_STATUS);
3720 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3721 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3722 tg3_setup_flow_control(tp, 0, 0);
3723 current_link_up = 1;
3d3ebe74
MC		 3724 tp->tg3_flags2 |=
3725 TG3_FLG2_PARALLEL_DETECT;
3726 tp->serdes_counter =
3727 SERDES_PARALLEL_DET_TIMEOUT;
3728 } else
3729 goto restart_autoneg;
1da177e4
LT		 3730 }
3731 }
3d3ebe74
MC		 3732 } else {
3733 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3734 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3735 }
3736
3737out:
3738 return current_link_up;
3739}
3740
3741static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3742{
3743 int current_link_up = 0;
3744
5cf64b8a 3745 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3746 goto out;
1da177e4
LT		 3747
3748 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3749 u32 txflags, rxflags;
1da177e4 3750 int i;
6aa20a22 3751
5be73b47
MC		 3752 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3753 u32 local_adv = 0, remote_adv = 0;
1da177e4 3754
5be73b47
MC		 3755 if (txflags & ANEG_CFG_PS1)
3756 local_adv |= ADVERTISE_1000XPAUSE;
3757 if (txflags & ANEG_CFG_PS2)
3758 local_adv |= ADVERTISE_1000XPSE_ASYM;
3759
3760 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3761 remote_adv |= LPA_1000XPAUSE;
3762 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3763 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3764
3765 tg3_setup_flow_control(tp, local_adv, remote_adv);
3766
1da177e4
LT		 3767 current_link_up = 1;
3768 }
3769 for (i = 0; i < 30; i++) {
3770 udelay(20);
3771 tw32_f(MAC_STATUS,
3772 (MAC_STATUS_SYNC_CHANGED |
3773 MAC_STATUS_CFG_CHANGED));
3774 udelay(40);
3775 if ((tr32(MAC_STATUS) &
3776 (MAC_STATUS_SYNC_CHANGED |
3777 MAC_STATUS_CFG_CHANGED)) == 0)
3778 break;
3779 }
3780
3781 mac_status = tr32(MAC_STATUS);
3782 if (current_link_up == 0 &&
3783 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3784 !(mac_status & MAC_STATUS_RCVD_CFG))
3785 current_link_up = 1;
3786 } else {
5be73b47
MC		 3787 tg3_setup_flow_control(tp, 0, 0);
3788
1da177e4
LT		 3789 /* Forcing 1000FD link up. */
3790 current_link_up = 1;
1da177e4
LT		 3791
3792 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3793 udelay(40);
e8f3f6ca
MC		 3794
3795 tw32_f(MAC_MODE, tp->mac_mode);
3796 udelay(40);
1da177e4
LT		 3797 }
3798
3799out:
3800 return current_link_up;
3801}
3802
3803static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3804{
3805 u32 orig_pause_cfg;
3806 u16 orig_active_speed;
3807 u8 orig_active_duplex;
3808 u32 mac_status;
3809 int current_link_up;
3810 int i;
3811
8d018621 3812 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3813 orig_active_speed = tp->link_config.active_speed;
3814 orig_active_duplex = tp->link_config.active_duplex;
3815
3816 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3817 netif_carrier_ok(tp->dev) &&
3818 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3819 mac_status = tr32(MAC_STATUS);
3820 mac_status &= (MAC_STATUS_PCS_SYNCED |
3821 MAC_STATUS_SIGNAL_DET |
3822 MAC_STATUS_CFG_CHANGED |
3823 MAC_STATUS_RCVD_CFG);
3824 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3825 MAC_STATUS_SIGNAL_DET)) {
3826 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3827 MAC_STATUS_CFG_CHANGED));
3828 return 0;
3829 }
3830 }
3831
3832 tw32_f(MAC_TX_AUTO_NEG, 0);
3833
3834 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3835 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3836 tw32_f(MAC_MODE, tp->mac_mode);
3837 udelay(40);
3838
3839 if (tp->phy_id == PHY_ID_BCM8002)
3840 tg3_init_bcm8002(tp);
3841
3842 /* Enable link change event even when serdes polling. */
3843 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3844 udelay(40);
3845
3846 current_link_up = 0;
3847 mac_status = tr32(MAC_STATUS);
3848
3849 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3850 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3851 else
3852 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3853
1da177e4
LT		 3854 tp->hw_status->status =
3855 (SD_STATUS_UPDATED |
3856 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3857
3858 for (i = 0; i < 100; i++) {
3859 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3860 MAC_STATUS_CFG_CHANGED));
3861 udelay(5);
3862 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3863 MAC_STATUS_CFG_CHANGED |
3864 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3865 break;
3866 }
3867
3868 mac_status = tr32(MAC_STATUS);
3869 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3870 current_link_up = 0;
3d3ebe74
MC		 3871 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3872 tp->serdes_counter == 0) {
1da177e4
LT		 3873 tw32_f(MAC_MODE, (tp->mac_mode |
3874 MAC_MODE_SEND_CONFIGS));
3875 udelay(1);
3876 tw32_f(MAC_MODE, tp->mac_mode);
3877 }
3878 }
3879
3880 if (current_link_up == 1) {
3881 tp->link_config.active_speed = SPEED_1000;
3882 tp->link_config.active_duplex = DUPLEX_FULL;
3883 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3884 LED_CTRL_LNKLED_OVERRIDE |
3885 LED_CTRL_1000MBPS_ON));
3886 } else {
3887 tp->link_config.active_speed = SPEED_INVALID;
3888 tp->link_config.active_duplex = DUPLEX_INVALID;
3889 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3890 LED_CTRL_LNKLED_OVERRIDE |
3891 LED_CTRL_TRAFFIC_OVERRIDE));
3892 }
3893
3894 if (current_link_up != netif_carrier_ok(tp->dev)) {
3895 if (current_link_up)
3896 netif_carrier_on(tp->dev);
3897 else
3898 netif_carrier_off(tp->dev);
3899 tg3_link_report(tp);
3900 } else {
8d018621 3901 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3902 if (orig_pause_cfg != now_pause_cfg ||
3903 orig_active_speed != tp->link_config.active_speed ||
3904 orig_active_duplex != tp->link_config.active_duplex)
3905 tg3_link_report(tp);
3906 }
3907
3908 return 0;
3909}
3910
747e8f8b
MC		 3911static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3912{
3913 int current_link_up, err = 0;
3914 u32 bmsr, bmcr;
3915 u16 current_speed;
3916 u8 current_duplex;
ef167e27 3917 u32 local_adv, remote_adv;
747e8f8b
MC		 3918
3919 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3920 tw32_f(MAC_MODE, tp->mac_mode);
3921 udelay(40);
3922
3923 tw32(MAC_EVENT, 0);
3924
3925 tw32_f(MAC_STATUS,
3926 (MAC_STATUS_SYNC_CHANGED |
3927 MAC_STATUS_CFG_CHANGED |
3928 MAC_STATUS_MI_COMPLETION |
3929 MAC_STATUS_LNKSTATE_CHANGED));
3930 udelay(40);
3931
3932 if (force_reset)
3933 tg3_phy_reset(tp);
3934
3935 current_link_up = 0;
3936 current_speed = SPEED_INVALID;
3937 current_duplex = DUPLEX_INVALID;
3938
3939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3940 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3942 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3943 bmsr |= BMSR_LSTATUS;
3944 else
3945 bmsr &= ~BMSR_LSTATUS;
3946 }
747e8f8b
MC		 3947
3948 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3949
3950 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3951 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3952 /* do nothing, just check for link up at the end */
3953 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3954 u32 adv, new_adv;
3955
3956 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3957 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3958 ADVERTISE_1000XPAUSE |
3959 ADVERTISE_1000XPSE_ASYM |
3960 ADVERTISE_SLCT);
3961
ba4d07a8 3962 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3963
3964 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3965 new_adv |= ADVERTISE_1000XHALF;
3966 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3967 new_adv |= ADVERTISE_1000XFULL;
3968
3969 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3970 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3971 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3972 tg3_writephy(tp, MII_BMCR, bmcr);
3973
3974 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3975 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3976 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3977
3978 return err;
3979 }
3980 } else {
3981 u32 new_bmcr;
3982
3983 bmcr &= ~BMCR_SPEED1000;
3984 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3985
3986 if (tp->link_config.duplex == DUPLEX_FULL)
3987 new_bmcr |= BMCR_FULLDPLX;
3988
3989 if (new_bmcr != bmcr) {
3990 /* BMCR_SPEED1000 is a reserved bit that needs
3991 * to be set on write.
3992 */
3993 new_bmcr |= BMCR_SPEED1000;
3994
3995 /* Force a linkdown */
3996 if (netif_carrier_ok(tp->dev)) {
3997 u32 adv;
3998
3999 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4000 adv &= ~(ADVERTISE_1000XFULL |
4001 ADVERTISE_1000XHALF |
4002 ADVERTISE_SLCT);
4003 tg3_writephy(tp, MII_ADVERTISE, adv);
4004 tg3_writephy(tp, MII_BMCR, bmcr |
4005 BMCR_ANRESTART |
4006 BMCR_ANENABLE);
4007 udelay(10);
4008 netif_carrier_off(tp->dev);
4009 }
4010 tg3_writephy(tp, MII_BMCR, new_bmcr);
4011 bmcr = new_bmcr;
4012 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4013 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4014 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4015 ASIC_REV_5714) {
4016 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4017 bmsr |= BMSR_LSTATUS;
4018 else
4019 bmsr &= ~BMSR_LSTATUS;
4020 }
747e8f8b
MC		 4021 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4022 }
4023 }
4024
4025 if (bmsr & BMSR_LSTATUS) {
4026 current_speed = SPEED_1000;
4027 current_link_up = 1;
4028 if (bmcr & BMCR_FULLDPLX)
4029 current_duplex = DUPLEX_FULL;
4030 else
4031 current_duplex = DUPLEX_HALF;
4032
ef167e27
MC		 4033 local_adv = 0;
4034 remote_adv = 0;
4035
747e8f8b 4036 if (bmcr & BMCR_ANENABLE) {
ef167e27 4037 u32 common;
747e8f8b
MC		 4038
4039 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4040 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4041 common = local_adv & remote_adv;
4042 if (common & (ADVERTISE_1000XHALF |
4043 ADVERTISE_1000XFULL)) {
4044 if (common & ADVERTISE_1000XFULL)
4045 current_duplex = DUPLEX_FULL;
4046 else
4047 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4048 }
4049 else
4050 current_link_up = 0;
4051 }
4052 }
4053
ef167e27
MC		 4054 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4055 tg3_setup_flow_control(tp, local_adv, remote_adv);
4056
747e8f8b
MC		 4057 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4058 if (tp->link_config.active_duplex == DUPLEX_HALF)
4059 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4060
4061 tw32_f(MAC_MODE, tp->mac_mode);
4062 udelay(40);
4063
4064 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4065
4066 tp->link_config.active_speed = current_speed;
4067 tp->link_config.active_duplex = current_duplex;
4068
4069 if (current_link_up != netif_carrier_ok(tp->dev)) {
4070 if (current_link_up)
4071 netif_carrier_on(tp->dev);
4072 else {
4073 netif_carrier_off(tp->dev);
4074 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4075 }
4076 tg3_link_report(tp);
4077 }
4078 return err;
4079}
4080
4081static void tg3_serdes_parallel_detect(struct tg3 *tp)
4082{
3d3ebe74 4083 if (tp->serdes_counter) {
747e8f8b 4084 /* Give autoneg time to complete. */
3d3ebe74 4085 tp->serdes_counter--;
747e8f8b
MC		 4086 return;
4087 }
4088 if (!netif_carrier_ok(tp->dev) &&
4089 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4090 u32 bmcr;
4091
4092 tg3_readphy(tp, MII_BMCR, &bmcr);
4093 if (bmcr & BMCR_ANENABLE) {
4094 u32 phy1, phy2;
4095
4096 /* Select shadow register 0x1f */
4097 tg3_writephy(tp, 0x1c, 0x7c00);
4098 tg3_readphy(tp, 0x1c, &phy1);
4099
4100 /* Select expansion interrupt status register */
4101 tg3_writephy(tp, 0x17, 0x0f01);
4102 tg3_readphy(tp, 0x15, &phy2);
4103 tg3_readphy(tp, 0x15, &phy2);
4104
4105 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4106 /* We have signal detect and not receiving
4107 * config code words, link is up by parallel
4108 * detection.
4109 */
4110
4111 bmcr &= ~BMCR_ANENABLE;
4112 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4113 tg3_writephy(tp, MII_BMCR, bmcr);
4114 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4115 }
4116 }
4117 }
4118 else if (netif_carrier_ok(tp->dev) &&
4119 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4120 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4121 u32 phy2;
4122
4123 /* Select expansion interrupt status register */
4124 tg3_writephy(tp, 0x17, 0x0f01);
4125 tg3_readphy(tp, 0x15, &phy2);
4126 if (phy2 & 0x20) {
4127 u32 bmcr;
4128
4129 /* Config code words received, turn on autoneg. */
4130 tg3_readphy(tp, MII_BMCR, &bmcr);
4131 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4132
4133 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4134
4135 }
4136 }
4137}
4138
1da177e4
LT		 4139static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4140{
4141 int err;
4142
4143 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4144 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4145 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4146 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4147 } else {
4148 err = tg3_setup_copper_phy(tp, force_reset);
4149 }
4150
bcb37f6c 4151 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4152 u32 val, scale;
4153
4154 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4155 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4156 scale = 65;
4157 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4158 scale = 6;
4159 else
4160 scale = 12;
4161
4162 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4163 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4164 tw32(GRC_MISC_CFG, val);
4165 }
4166
1da177e4
LT		 4167 if (tp->link_config.active_speed == SPEED_1000 &&
4168 tp->link_config.active_duplex == DUPLEX_HALF)
4169 tw32(MAC_TX_LENGTHS,
4170 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4171 (6 << TX_LENGTHS_IPG_SHIFT) |
4172 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4173 else
4174 tw32(MAC_TX_LENGTHS,
4175 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4176 (6 << TX_LENGTHS_IPG_SHIFT) |
4177 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4178
4179 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4180 if (netif_carrier_ok(tp->dev)) {
4181 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4182 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4183 } else {
4184 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4185 }
4186 }
4187
8ed5d97e
MC		 4188 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4189 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4190 if (!netif_carrier_ok(tp->dev))
4191 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4192 tp->pwrmgmt_thresh;
4193 else
4194 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4195 tw32(PCIE_PWR_MGMT_THRESH, val);
4196 }
4197
1da177e4
LT		 4198 return err;
4199}
4200
df3e6548
MC		 4201/* This is called whenever we suspect that the system chipset is re-
4202 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4203 * is bogus tx completions. We try to recover by setting the
4204 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4205 * in the workqueue.
4206 */
4207static void tg3_tx_recover(struct tg3 *tp)
4208{
4209 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4210 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4211
4212 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4213 "mapped I/O cycles to the network device, attempting to "
4214 "recover. Please report the problem to the driver maintainer "
4215 "and include system chipset information.\n", tp->dev->name);
4216
4217 spin_lock(&tp->lock);
df3e6548 4218 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4219 spin_unlock(&tp->lock);
4220}
4221
1b2a7205
MC		 4222static inline u32 tg3_tx_avail(struct tg3 *tp)
4223{
4224 smp_mb();
4225 return (tp->tx_pending -
4226 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4227}
4228
1da177e4
LT		 4229/* Tigon3 never reports partial packet sends. So we do not
4230 * need special logic to handle SKBs that have not had all
4231 * of their frags sent yet, like SunGEM does.
4232 */
4233static void tg3_tx(struct tg3 *tp)
4234{
4235 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4236 u32 sw_idx = tp->tx_cons;
4237
4238 while (sw_idx != hw_idx) {
4239 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4240 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4241 int i, tx_bug = 0;
4242
4243 if (unlikely(skb == NULL)) {
4244 tg3_tx_recover(tp);
4245 return;
4246 }
1da177e4 4247
90079ce8 4248 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4249
4250 ri->skb = NULL;
4251
4252 sw_idx = NEXT_TX(sw_idx);
4253
4254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4255 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4256 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4257 tx_bug = 1;
1da177e4
LT		 4258 sw_idx = NEXT_TX(sw_idx);
4259 }
4260
f47c11ee 4261 dev_kfree_skb(skb);
df3e6548
MC		 4262
4263 if (unlikely(tx_bug)) {
4264 tg3_tx_recover(tp);
4265 return;
4266 }
1da177e4
LT		 4267 }
4268
4269 tp->tx_cons = sw_idx;
4270
1b2a7205
MC		 4271 /* Need to make the tx_cons update visible to tg3_start_xmit()
4272 * before checking for netif_queue_stopped(). Without the
4273 * memory barrier, there is a small possibility that tg3_start_xmit()
4274 * will miss it and cause the queue to be stopped forever.
4275 */
4276 smp_mb();
4277
4278 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4279 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4280 netif_tx_lock(tp->dev);
51b91468 4281 if (netif_queue_stopped(tp->dev) &&
42952231 4282 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4283 netif_wake_queue(tp->dev);
1b2a7205 4284 netif_tx_unlock(tp->dev);
51b91468 4285 }
1da177e4
LT		 4286}
4287
4288/* Returns size of skb allocated or < 0 on error.
4289 *
4290 * We only need to fill in the address because the other members
4291 * of the RX descriptor are invariant, see tg3_init_rings.
4292 *
4293 * Note the purposeful assymetry of cpu vs. chip accesses. For
4294 * posting buffers we only dirty the first cache line of the RX
4295 * descriptor (containing the address). Whereas for the RX status
4296 * buffers the cpu only reads the last cacheline of the RX descriptor
4297 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4298 */
4299static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4300 int src_idx, u32 dest_idx_unmasked)
4301{
4302 struct tg3_rx_buffer_desc *desc;
4303 struct ring_info *map, *src_map;
4304 struct sk_buff *skb;
4305 dma_addr_t mapping;
4306 int skb_size, dest_idx;
4307
4308 src_map = NULL;
4309 switch (opaque_key) {
4310 case RXD_OPAQUE_RING_STD:
4311 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4312 desc = &tp->rx_std[dest_idx];
4313 map = &tp->rx_std_buffers[dest_idx];
4314 if (src_idx >= 0)
4315 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4316 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4317 break;
4318
4319 case RXD_OPAQUE_RING_JUMBO:
4320 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4321 desc = &tp->rx_jumbo[dest_idx];
4322 map = &tp->rx_jumbo_buffers[dest_idx];
4323 if (src_idx >= 0)
4324 src_map = &tp->rx_jumbo_buffers[src_idx];
4325 skb_size = RX_JUMBO_PKT_BUF_SZ;
4326 break;
4327
4328 default:
4329 return -EINVAL;
855e1111 4330 }
1da177e4
LT		 4331
4332 /* Do not overwrite any of the map or rp information
4333 * until we are sure we can commit to a new buffer.
4334 *
4335 * Callers depend upon this behavior and assume that
4336 * we leave everything unchanged if we fail.
4337 */
a20e9c62 4338 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4339 if (skb == NULL)
4340 return -ENOMEM;
4341
1da177e4
LT		 4342 skb_reserve(skb, tp->rx_offset);
4343
4344 mapping = pci_map_single(tp->pdev, skb->data,
4345 skb_size - tp->rx_offset,
4346 PCI_DMA_FROMDEVICE);
4347
4348 map->skb = skb;
4349 pci_unmap_addr_set(map, mapping, mapping);
4350
4351 if (src_map != NULL)
4352 src_map->skb = NULL;
4353
4354 desc->addr_hi = ((u64)mapping >> 32);
4355 desc->addr_lo = ((u64)mapping & 0xffffffff);
4356
4357 return skb_size;
4358}
4359
4360/* We only need to move over in the address because the other
4361 * members of the RX descriptor are invariant. See notes above
4362 * tg3_alloc_rx_skb for full details.
4363 */
4364static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4365 int src_idx, u32 dest_idx_unmasked)
4366{
4367 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4368 struct ring_info *src_map, *dest_map;
4369 int dest_idx;
4370
4371 switch (opaque_key) {
4372 case RXD_OPAQUE_RING_STD:
4373 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4374 dest_desc = &tp->rx_std[dest_idx];
4375 dest_map = &tp->rx_std_buffers[dest_idx];
4376 src_desc = &tp->rx_std[src_idx];
4377 src_map = &tp->rx_std_buffers[src_idx];
4378 break;
4379
4380 case RXD_OPAQUE_RING_JUMBO:
4381 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4382 dest_desc = &tp->rx_jumbo[dest_idx];
4383 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4384 src_desc = &tp->rx_jumbo[src_idx];
4385 src_map = &tp->rx_jumbo_buffers[src_idx];
4386 break;
4387
4388 default:
4389 return;
855e1111 4390 }
1da177e4
LT		 4391
4392 dest_map->skb = src_map->skb;
4393 pci_unmap_addr_set(dest_map, mapping,
4394 pci_unmap_addr(src_map, mapping));
4395 dest_desc->addr_hi = src_desc->addr_hi;
4396 dest_desc->addr_lo = src_desc->addr_lo;
4397
4398 src_map->skb = NULL;
4399}
4400
4401#if TG3_VLAN_TAG_USED
4402static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4403{
4404 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4405}
4406#endif
4407
4408/* The RX ring scheme is composed of multiple rings which post fresh
4409 * buffers to the chip, and one special ring the chip uses to report
4410 * status back to the host.
4411 *
4412 * The special ring reports the status of received packets to the
4413 * host. The chip does not write into the original descriptor the
4414 * RX buffer was obtained from. The chip simply takes the original
4415 * descriptor as provided by the host, updates the status and length
4416 * field, then writes this into the next status ring entry.
4417 *
4418 * Each ring the host uses to post buffers to the chip is described
4419 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4420 * it is first placed into the on-chip ram. When the packet's length
4421 * is known, it walks down the TG3_BDINFO entries to select the ring.
4422 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4423 * which is within the range of the new packet's length is chosen.
4424 *
4425 * The "separate ring for rx status" scheme may sound queer, but it makes
4426 * sense from a cache coherency perspective. If only the host writes
4427 * to the buffer post rings, and only the chip writes to the rx status
4428 * rings, then cache lines never move beyond shared-modified state.
4429 * If both the host and chip were to write into the same ring, cache line
4430 * eviction could occur since both entities want it in an exclusive state.
4431 */
4432static int tg3_rx(struct tg3 *tp, int budget)
4433{
f92905de 4434 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4435 u32 sw_idx = tp->rx_rcb_ptr;
4436 u16 hw_idx;
1da177e4
LT		 4437 int received;
4438
4439 hw_idx = tp->hw_status->idx[0].rx_producer;
4440 /*
4441 * We need to order the read of hw_idx and the read of
4442 * the opaque cookie.
4443 */
4444 rmb();
1da177e4
LT		 4445 work_mask = 0;
4446 received = 0;
4447 while (sw_idx != hw_idx && budget > 0) {
4448 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4449 unsigned int len;
4450 struct sk_buff *skb;
4451 dma_addr_t dma_addr;
4452 u32 opaque_key, desc_idx, *post_ptr;
4453
4454 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4455 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4456 if (opaque_key == RXD_OPAQUE_RING_STD) {
4457 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4458 mapping);
4459 skb = tp->rx_std_buffers[desc_idx].skb;
4460 post_ptr = &tp->rx_std_ptr;
f92905de 4461 rx_std_posted++;
1da177e4
LT		 4462 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4463 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4464 mapping);
4465 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4466 post_ptr = &tp->rx_jumbo_ptr;
4467 }
4468 else {
4469 goto next_pkt_nopost;
4470 }
4471
4472 work_mask |= opaque_key;
4473
4474 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4475 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4476 drop_it:
4477 tg3_recycle_rx(tp, opaque_key,
4478 desc_idx, *post_ptr);
4479 drop_it_no_recycle:
4480 /* Other statistics kept track of by card. */
4481 tp->net_stats.rx_dropped++;
4482 goto next_pkt;
4483 }
4484
ad829268
MC		 4485 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4486 ETH_FCS_LEN;
1da177e4 4487
6aa20a22 4488 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4489 && tp->rx_offset == NET_IP_ALIGN
4490 /* rx_offset will likely not equal NET_IP_ALIGN
4491 * if this is a 5701 card running in PCI-X mode
4492 * [see tg3_get_invariants()]
4493 */
1da177e4
LT		 4494 ) {
4495 int skb_size;
4496
4497 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4498 desc_idx, *post_ptr);
4499 if (skb_size < 0)
4500 goto drop_it;
4501
4502 pci_unmap_single(tp->pdev, dma_addr,
4503 skb_size - tp->rx_offset,
4504 PCI_DMA_FROMDEVICE);
4505
4506 skb_put(skb, len);
4507 } else {
4508 struct sk_buff *copy_skb;
4509
4510 tg3_recycle_rx(tp, opaque_key,
4511 desc_idx, *post_ptr);
4512
ad829268
MC		 4513 copy_skb = netdev_alloc_skb(tp->dev,
4514 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4515 if (copy_skb == NULL)
4516 goto drop_it_no_recycle;
4517
ad829268 4518 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4519 skb_put(copy_skb, len);
4520 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4521 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4522 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4523
4524 /* We'll reuse the original ring buffer. */
4525 skb = copy_skb;
4526 }
4527
4528 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4529 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4530 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4531 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4532 skb->ip_summed = CHECKSUM_UNNECESSARY;
4533 else
4534 skb->ip_summed = CHECKSUM_NONE;
4535
4536 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4537
4538 if (len > (tp->dev->mtu + ETH_HLEN) &&
4539 skb->protocol != htons(ETH_P_8021Q)) {
4540 dev_kfree_skb(skb);
4541 goto next_pkt;
4542 }
4543
1da177e4
LT		 4544#if TG3_VLAN_TAG_USED
4545 if (tp->vlgrp != NULL &&
4546 desc->type_flags & RXD_FLAG_VLAN) {
4547 tg3_vlan_rx(tp, skb,
4548 desc->err_vlan & RXD_VLAN_MASK);
4549 } else
4550#endif
4551 netif_receive_skb(skb);
4552
1da177e4
LT		 4553 received++;
4554 budget--;
4555
4556next_pkt:
4557 (*post_ptr)++;
f92905de
MC		 4558
4559 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4560 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4561
4562 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4563 TG3_64BIT_REG_LOW, idx);
4564 work_mask &= ~RXD_OPAQUE_RING_STD;
4565 rx_std_posted = 0;
4566 }
1da177e4 4567next_pkt_nopost:
483ba50b 4568 sw_idx++;
6b31a515 4569 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4570
4571 /* Refresh hw_idx to see if there is new work */
4572 if (sw_idx == hw_idx) {
4573 hw_idx = tp->hw_status->idx[0].rx_producer;
4574 rmb();
4575 }
1da177e4
LT		 4576 }
4577
4578 /* ACK the status ring. */
483ba50b
MC		 4579 tp->rx_rcb_ptr = sw_idx;
4580 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4581
4582 /* Refill RX ring(s). */
4583 if (work_mask & RXD_OPAQUE_RING_STD) {
4584 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4585 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4586 sw_idx);
4587 }
4588 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4589 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4590 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4591 sw_idx);
4592 }
4593 mmiowb();
4594
4595 return received;
4596}
4597
6f535763 4598static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4599{
1da177e4 4600 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4601
1da177e4
LT		 4602 /* handle link change and other phy events */
4603 if (!(tp->tg3_flags &
4604 (TG3_FLAG_USE_LINKCHG_REG |
4605 TG3_FLAG_POLL_SERDES))) {
4606 if (sblk->status & SD_STATUS_LINK_CHG) {
4607 sblk->status = SD_STATUS_UPDATED |
4608 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4609 spin_lock(&tp->lock);
dd477003
MC		 4610 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4611 tw32_f(MAC_STATUS,
4612 (MAC_STATUS_SYNC_CHANGED |
4613 MAC_STATUS_CFG_CHANGED |
4614 MAC_STATUS_MI_COMPLETION |
4615 MAC_STATUS_LNKSTATE_CHANGED));
4616 udelay(40);
4617 } else
4618 tg3_setup_phy(tp, 0);
f47c11ee 4619 spin_unlock(&tp->lock);
1da177e4
LT		 4620 }
4621 }
4622
4623 /* run TX completion thread */
4624 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4625 tg3_tx(tp);
6f535763 4626 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4627 return work_done;
1da177e4
LT		 4628 }
4629
1da177e4
LT		 4630 /* run RX thread, within the bounds set by NAPI.
4631 * All RX "locking" is done by ensuring outside
bea3348e 4632 * code synchronizes with tg3->napi.poll()
1da177e4 4633 */
bea3348e 4634 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4635 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4636
6f535763
DM		 4637 return work_done;
4638}
4639
4640static int tg3_poll(struct napi_struct *napi, int budget)
4641{
4642 struct tg3 *tp = container_of(napi, struct tg3, napi);
4643 int work_done = 0;
4fd7ab59 4644 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4645
4646 while (1) {
4647 work_done = tg3_poll_work(tp, work_done, budget);
4648
4649 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4650 goto tx_recovery;
4651
4652 if (unlikely(work_done >= budget))
4653 break;
4654
4fd7ab59
MC		 4655 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4656 /* tp->last_tag is used in tg3_restart_ints() below
4657 * to tell the hw how much work has been processed,
4658 * so we must read it before checking for more work.
4659 */
4660 tp->last_tag = sblk->status_tag;
4661 rmb();
4662 } else
4663 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4664
4fd7ab59 4665 if (likely(!tg3_has_work(tp))) {
288379f0 4666 napi_complete(napi);
6f535763
DM		 4667 tg3_restart_ints(tp);
4668 break;
4669 }
1da177e4
LT		 4670 }
4671
bea3348e 4672 return work_done;
6f535763
DM		 4673
4674tx_recovery:
4fd7ab59 4675 /* work_done is guaranteed to be less than budget. */
288379f0 4676 napi_complete(napi);
6f535763 4677 schedule_work(&tp->reset_task);
4fd7ab59 4678 return work_done;
1da177e4
LT		 4679}
4680
f47c11ee
DM		 4681static void tg3_irq_quiesce(struct tg3 *tp)
4682{
4683 BUG_ON(tp->irq_sync);
4684
4685 tp->irq_sync = 1;
4686 smp_mb();
4687
4688 synchronize_irq(tp->pdev->irq);
4689}
4690
4691static inline int tg3_irq_sync(struct tg3 *tp)
4692{
4693 return tp->irq_sync;
4694}
4695
4696/* Fully shutdown all tg3 driver activity elsewhere in the system.
4697 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4698 * with as well. Most of the time, this is not necessary except when
4699 * shutting down the device.
4700 */
4701static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4702{
46966545 4703 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4704 if (irq_sync)
4705 tg3_irq_quiesce(tp);
f47c11ee
DM		 4706}
4707
4708static inline void tg3_full_unlock(struct tg3 *tp)
4709{
f47c11ee
DM		 4710 spin_unlock_bh(&tp->lock);
4711}
4712
fcfa0a32
MC		 4713/* One-shot MSI handler - Chip automatically disables interrupt
4714 * after sending MSI so driver doesn't have to do it.
4715 */
7d12e780 4716static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4717{
4718 struct net_device *dev = dev_id;
4719 struct tg3 *tp = netdev_priv(dev);
4720
4721 prefetch(tp->hw_status);
4722 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4723
4724 if (likely(!tg3_irq_sync(tp)))
288379f0 4725 napi_schedule(&tp->napi);
fcfa0a32
MC		 4726
4727 return IRQ_HANDLED;
4728}
4729
88b06bc2
MC		 4730/* MSI ISR - No need to check for interrupt sharing and no need to
4731 * flush status block and interrupt mailbox. PCI ordering rules
4732 * guarantee that MSI will arrive after the status block.
4733 */
7d12e780 4734static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4735{
4736 struct net_device *dev = dev_id;
4737 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4738
61487480
MC		 4739 prefetch(tp->hw_status);
4740 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4741 /*
fac9b83e 4742 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4743 * chip-internal interrupt pending events.
fac9b83e 4744 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4745 * NIC to stop sending us irqs, engaging "in-intr-handler"
4746 * event coalescing.
4747 */
4748 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4749 if (likely(!tg3_irq_sync(tp)))
288379f0 4750 napi_schedule(&tp->napi);
61487480 4751
88b06bc2
MC		 4752 return IRQ_RETVAL(1);
4753}
4754
7d12e780 4755static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4756{
4757 struct net_device *dev = dev_id;
4758 struct tg3 *tp = netdev_priv(dev);
4759 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4760 unsigned int handled = 1;
4761
1da177e4
LT		 4762 /* In INTx mode, it is possible for the interrupt to arrive at
4763 * the CPU before the status block posted prior to the interrupt.
4764 * Reading the PCI State register will confirm whether the
4765 * interrupt is ours and will flush the status block.
4766 */
d18edcb2
MC		 4767 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4768 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4769 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4770 handled = 0;
f47c11ee 4771 goto out;
fac9b83e 4772 }
d18edcb2
MC		 4773 }
4774
4775 /*
4776 * Writing any value to intr-mbox-0 clears PCI INTA# and
4777 * chip-internal interrupt pending events.
4778 * Writing non-zero to intr-mbox-0 additional tells the
4779 * NIC to stop sending us irqs, engaging "in-intr-handler"
4780 * event coalescing.
c04cb347
MC		 4781 *
4782 * Flush the mailbox to de-assert the IRQ immediately to prevent
4783 * spurious interrupts. The flush impacts performance but
4784 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4785 */
c04cb347 4786 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4787 if (tg3_irq_sync(tp))
4788 goto out;
4789 sblk->status &= ~SD_STATUS_UPDATED;
4790 if (likely(tg3_has_work(tp))) {
4791 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4792 napi_schedule(&tp->napi);
d18edcb2
MC		 4793 } else {
4794 /* No work, shared interrupt perhaps? re-enable
4795 * interrupts, and flush that PCI write
4796 */
4797 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4798 0x00000000);
fac9b83e 4799 }
f47c11ee 4800out:
fac9b83e
DM		 4801 return IRQ_RETVAL(handled);
4802}
4803
7d12e780 4804static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4805{
4806 struct net_device *dev = dev_id;
4807 struct tg3 *tp = netdev_priv(dev);
4808 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4809 unsigned int handled = 1;
4810
fac9b83e
DM		 4811 /* In INTx mode, it is possible for the interrupt to arrive at
4812 * the CPU before the status block posted prior to the interrupt.
4813 * Reading the PCI State register will confirm whether the
4814 * interrupt is ours and will flush the status block.
4815 */
d18edcb2
MC		 4816 if (unlikely(sblk->status_tag == tp->last_tag)) {
4817 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4818 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4819 handled = 0;
f47c11ee 4820 goto out;
1da177e4 4821 }
d18edcb2
MC		 4822 }
4823
4824 /*
4825 * writing any value to intr-mbox-0 clears PCI INTA# and
4826 * chip-internal interrupt pending events.
4827 * writing non-zero to intr-mbox-0 additional tells the
4828 * NIC to stop sending us irqs, engaging "in-intr-handler"
4829 * event coalescing.
c04cb347
MC		 4830 *
4831 * Flush the mailbox to de-assert the IRQ immediately to prevent
4832 * spurious interrupts. The flush impacts performance but
4833 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4834 */
c04cb347 4835 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4836 if (tg3_irq_sync(tp))
4837 goto out;
288379f0 4838 if (napi_schedule_prep(&tp->napi)) {
d18edcb2
MC		 4839 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4840 /* Update last_tag to mark that this status has been
4841 * seen. Because interrupt may be shared, we may be
4842 * racing with tg3_poll(), so only update last_tag
4843 * if tg3_poll() is not scheduled.
4844 */
4845 tp->last_tag = sblk->status_tag;
288379f0 4846 __napi_schedule(&tp->napi);
1da177e4 4847 }
f47c11ee 4848out:
1da177e4
LT		 4849 return IRQ_RETVAL(handled);
4850}
4851
7938109f 4852/* ISR for interrupt test */
7d12e780 4853static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4854{
4855 struct net_device *dev = dev_id;
4856 struct tg3 *tp = netdev_priv(dev);
4857 struct tg3_hw_status *sblk = tp->hw_status;
4858
f9804ddb
MC		 4859 if ((sblk->status & SD_STATUS_UPDATED) ||
4860 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4861 tg3_disable_ints(tp);
7938109f
MC		 4862 return IRQ_RETVAL(1);
4863 }
4864 return IRQ_RETVAL(0);
4865}
4866
8e7a22e3 4867static int tg3_init_hw(struct tg3 *, int);
944d980e 4868static int tg3_halt(struct tg3 *, int, int);
1da177e4 4869
b9ec6c1b
MC		 4870/* Restart hardware after configuration changes, self-test, etc.
4871 * Invoked with tp->lock held.
4872 */
4873static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4874 __releases(tp->lock)
4875 __acquires(tp->lock)
b9ec6c1b
MC		 4876{
4877 int err;
4878
4879 err = tg3_init_hw(tp, reset_phy);
4880 if (err) {
4881 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4882 "aborting.\n", tp->dev->name);
4883 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4884 tg3_full_unlock(tp);
4885 del_timer_sync(&tp->timer);
4886 tp->irq_sync = 0;
bea3348e 4887 napi_enable(&tp->napi);
b9ec6c1b
MC		 4888 dev_close(tp->dev);
4889 tg3_full_lock(tp, 0);
4890 }
4891 return err;
4892}
4893
1da177e4
LT		 4894#ifdef CONFIG_NET_POLL_CONTROLLER
4895static void tg3_poll_controller(struct net_device *dev)
4896{
88b06bc2
MC		 4897 struct tg3 *tp = netdev_priv(dev);
4898
7d12e780 4899 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4900}
4901#endif
4902
c4028958 4903static void tg3_reset_task(struct work_struct *work)
1da177e4 4904{
c4028958 4905 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4906 int err;
1da177e4
LT		 4907 unsigned int restart_timer;
4908
7faa006f 4909 tg3_full_lock(tp, 0);
7faa006f
MC		 4910
4911 if (!netif_running(tp->dev)) {
7faa006f
MC		 4912 tg3_full_unlock(tp);
4913 return;
4914 }
4915
4916 tg3_full_unlock(tp);
4917
b02fd9e3
MC		 4918 tg3_phy_stop(tp);
4919
1da177e4
LT		 4920 tg3_netif_stop(tp);
4921
f47c11ee 4922 tg3_full_lock(tp, 1);
1da177e4
LT		 4923
4924 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4925 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4926
df3e6548
MC		 4927 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4928 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4929 tp->write32_rx_mbox = tg3_write_flush_reg32;
4930 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4931 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4932 }
4933
944d980e 4934 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4935 err = tg3_init_hw(tp, 1);
4936 if (err)
b9ec6c1b 4937 goto out;
1da177e4
LT		 4938
4939 tg3_netif_start(tp);
4940
1da177e4
LT		 4941 if (restart_timer)
4942 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4943
b9ec6c1b 4944out:
7faa006f 4945 tg3_full_unlock(tp);
b02fd9e3
MC		 4946
4947 if (!err)
4948 tg3_phy_start(tp);
1da177e4
LT		 4949}
4950
b0408751
MC		 4951static void tg3_dump_short_state(struct tg3 *tp)
4952{
4953 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4954 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4955 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4956 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4957}
4958
1da177e4
LT		 4959static void tg3_tx_timeout(struct net_device *dev)
4960{
4961 struct tg3 *tp = netdev_priv(dev);
4962
b0408751 4963 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4964 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4965 dev->name);
b0408751
MC		 4966 tg3_dump_short_state(tp);
4967 }
1da177e4
LT		 4968
4969 schedule_work(&tp->reset_task);
4970}
4971
c58ec932
MC		 4972/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4973static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4974{
4975 u32 base = (u32) mapping & 0xffffffff;
4976
4977 return ((base > 0xffffdcc0) &&
4978 (base + len + 8 < base));
4979}
4980
72f2afb8
MC		 4981/* Test for DMA addresses > 40-bit */
4982static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4983 int len)
4984{
4985#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4986 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 4987 return (((u64) mapping + len) > DMA_40BIT_MASK);
4988 return 0;
4989#else
4990 return 0;
4991#endif
4992}
4993
1da177e4
LT		 4994static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4995
72f2afb8
MC		 4996/* Workaround 4GB and 40-bit hardware DMA bugs. */
4997static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 4998 u32 last_plus_one, u32 *start,
4999 u32 base_flags, u32 mss)
1da177e4 5000{
41588ba1 5001 struct sk_buff *new_skb;
c58ec932 5002 dma_addr_t new_addr = 0;
1da177e4 5003 u32 entry = *start;
c58ec932 5004 int i, ret = 0;
1da177e4 5005
41588ba1
MC		 5006 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5007 new_skb = skb_copy(skb, GFP_ATOMIC);
5008 else {
5009 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5010
5011 new_skb = skb_copy_expand(skb,
5012 skb_headroom(skb) + more_headroom,
5013 skb_tailroom(skb), GFP_ATOMIC);
5014 }
5015
1da177e4 5016 if (!new_skb) {
c58ec932
MC		 5017 ret = -1;
5018 } else {
5019 /* New SKB is guaranteed to be linear. */
5020 entry = *start;
90079ce8
DM		 5021 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5022 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5023
c58ec932
MC		 5024 /* Make sure new skb does not cross any 4G boundaries.
5025 * Drop the packet if it does.
5026 */
90079ce8 5027 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5028 if (!ret)
5029 skb_dma_unmap(&tp->pdev->dev, new_skb,
5030 DMA_TO_DEVICE);
c58ec932
MC		 5031 ret = -1;
5032 dev_kfree_skb(new_skb);
5033 new_skb = NULL;
5034 } else {
5035 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5036 base_flags, 1 | (mss << 1));
5037 *start = NEXT_TX(entry);
5038 }
1da177e4
LT		 5039 }
5040
1da177e4
LT		 5041 /* Now clean up the sw ring entries. */
5042 i = 0;
5043 while (entry != last_plus_one) {
1da177e4
LT		 5044 if (i == 0) {
5045 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5046 } else {
5047 tp->tx_buffers[entry].skb = NULL;
5048 }
5049 entry = NEXT_TX(entry);
5050 i++;
5051 }
5052
90079ce8 5053 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5054 dev_kfree_skb(skb);
5055
c58ec932 5056 return ret;
1da177e4
LT		 5057}
5058
5059static void tg3_set_txd(struct tg3 *tp, int entry,
5060 dma_addr_t mapping, int len, u32 flags,
5061 u32 mss_and_is_end)
5062{
5063 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5064 int is_end = (mss_and_is_end & 0x1);
5065 u32 mss = (mss_and_is_end >> 1);
5066 u32 vlan_tag = 0;
5067
5068 if (is_end)
5069 flags |= TXD_FLAG_END;
5070 if (flags & TXD_FLAG_VLAN) {
5071 vlan_tag = flags >> 16;
5072 flags &= 0xffff;
5073 }
5074 vlan_tag |= (mss << TXD_MSS_SHIFT);
5075
5076 txd->addr_hi = ((u64) mapping >> 32);
5077 txd->addr_lo = ((u64) mapping & 0xffffffff);
5078 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5079 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5080}
5081
5a6f3074
MC		 5082/* hard_start_xmit for devices that don't have any bugs and
5083 * support TG3_FLG2_HW_TSO_2 only.
5084 */
1da177e4 5085static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5086{
5087 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5088 u32 len, entry, base_flags, mss;
90079ce8
DM		 5089 struct skb_shared_info *sp;
5090 dma_addr_t mapping;
5a6f3074
MC		 5091
5092 len = skb_headlen(skb);
5093
00b70504 5094 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5095 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5096 * interrupt. Furthermore, IRQ processing runs lockless so we have
5097 * no IRQ context deadlocks to worry about either. Rejoice!
5098 */
1b2a7205 5099 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5100 if (!netif_queue_stopped(dev)) {
5101 netif_stop_queue(dev);
5102
5103 /* This is a hard error, log it. */
5104 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5105 "queue awake!\n", dev->name);
5106 }
5a6f3074
MC		 5107 return NETDEV_TX_BUSY;
5108 }
5109
5110 entry = tp->tx_prod;
5111 base_flags = 0;
5a6f3074 5112 mss = 0;
c13e3713 5113 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5114 int tcp_opt_len, ip_tcp_len;
5115
5116 if (skb_header_cloned(skb) &&
5117 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5118 dev_kfree_skb(skb);
5119 goto out_unlock;
5120 }
5121
b0026624
MC		 5122 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5123 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5124 else {
eddc9ec5
ACM		 5125 struct iphdr *iph = ip_hdr(skb);
5126
ab6a5bb6 5127 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5128 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5129
eddc9ec5
ACM		 5130 iph->check = 0;
5131 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5132 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5133 }
5a6f3074
MC		 5134
5135 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5136 TXD_FLAG_CPU_POST_DMA);
5137
aa8223c7 5138 tcp_hdr(skb)->check = 0;
5a6f3074 5139
5a6f3074 5140 }
84fa7933 5141 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5142 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5143#if TG3_VLAN_TAG_USED
5144 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5145 base_flags |= (TXD_FLAG_VLAN |
5146 (vlan_tx_tag_get(skb) << 16));
5147#endif
5148
90079ce8
DM		 5149 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5150 dev_kfree_skb(skb);
5151 goto out_unlock;
5152 }
5153
5154 sp = skb_shinfo(skb);
5155
5156 mapping = sp->dma_maps[0];
5a6f3074
MC		 5157
5158 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5159
5160 tg3_set_txd(tp, entry, mapping, len, base_flags,
5161 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5162
5163 entry = NEXT_TX(entry);
5164
5165 /* Now loop through additional data fragments, and queue them. */
5166 if (skb_shinfo(skb)->nr_frags > 0) {
5167 unsigned int i, last;
5168
5169 last = skb_shinfo(skb)->nr_frags - 1;
5170 for (i = 0; i <= last; i++) {
5171 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5172
5173 len = frag->size;
90079ce8 5174 mapping = sp->dma_maps[i + 1];
5a6f3074 5175 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5176
5177 tg3_set_txd(tp, entry, mapping, len,
5178 base_flags, (i == last) | (mss << 1));
5179
5180 entry = NEXT_TX(entry);
5181 }
5182 }
5183
5184 /* Packets are ready, update Tx producer idx local and on card. */
5185 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5186
5187 tp->tx_prod = entry;
1b2a7205 5188 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5189 netif_stop_queue(dev);
42952231 5190 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5191 netif_wake_queue(tp->dev);
5192 }
5193
5194out_unlock:
5195 mmiowb();
5a6f3074
MC		 5196
5197 dev->trans_start = jiffies;
5198
5199 return NETDEV_TX_OK;
5200}
5201
52c0fd83
MC		 5202static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5203
5204/* Use GSO to workaround a rare TSO bug that may be triggered when the
5205 * TSO header is greater than 80 bytes.
5206 */
5207static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5208{
5209 struct sk_buff *segs, *nskb;
5210
5211 /* Estimate the number of fragments in the worst case */
1b2a7205 5212 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5213 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5214 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5215 return NETDEV_TX_BUSY;
5216
5217 netif_wake_queue(tp->dev);
52c0fd83
MC		 5218 }
5219
5220 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5221 if (IS_ERR(segs))
52c0fd83
MC		 5222 goto tg3_tso_bug_end;
5223
5224 do {
5225 nskb = segs;
5226 segs = segs->next;
5227 nskb->next = NULL;
5228 tg3_start_xmit_dma_bug(nskb, tp->dev);
5229 } while (segs);
5230
5231tg3_tso_bug_end:
5232 dev_kfree_skb(skb);
5233
5234 return NETDEV_TX_OK;
5235}
52c0fd83 5236
5a6f3074
MC		 5237/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5238 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5239 */
5240static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5241{
5242 struct tg3 *tp = netdev_priv(dev);
1da177e4 5243 u32 len, entry, base_flags, mss;
90079ce8 5244 struct skb_shared_info *sp;
1da177e4 5245 int would_hit_hwbug;
90079ce8 5246 dma_addr_t mapping;
1da177e4
LT		 5247
5248 len = skb_headlen(skb);
5249
00b70504 5250 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5251 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5252 * interrupt. Furthermore, IRQ processing runs lockless so we have
5253 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5254 */
1b2a7205 5255 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5256 if (!netif_queue_stopped(dev)) {
5257 netif_stop_queue(dev);
5258
5259 /* This is a hard error, log it. */
5260 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5261 "queue awake!\n", dev->name);
5262 }
1da177e4
LT		 5263 return NETDEV_TX_BUSY;
5264 }
5265
5266 entry = tp->tx_prod;
5267 base_flags = 0;
84fa7933 5268 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5269 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5270 mss = 0;
c13e3713 5271 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5272 struct iphdr *iph;
52c0fd83 5273 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5274
5275 if (skb_header_cloned(skb) &&
5276 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5277 dev_kfree_skb(skb);
5278 goto out_unlock;
5279 }
5280
ab6a5bb6 5281 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5282 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5283
52c0fd83
MC		 5284 hdr_len = ip_tcp_len + tcp_opt_len;
5285 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5286 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5287 return (tg3_tso_bug(tp, skb));
5288
1da177e4
LT		 5289 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5290 TXD_FLAG_CPU_POST_DMA);
5291
eddc9ec5
ACM		 5292 iph = ip_hdr(skb);
5293 iph->check = 0;
5294 iph->tot_len = htons(mss + hdr_len);
1da177e4 5295 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5296 tcp_hdr(skb)->check = 0;
1da177e4 5297 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5298 } else
5299 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5300 iph->daddr, 0,
5301 IPPROTO_TCP,
5302 0);
1da177e4
LT		 5303
5304 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5305 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5306 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5307 int tsflags;
5308
eddc9ec5 5309 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5310 mss |= (tsflags << 11);
5311 }
5312 } else {
eddc9ec5 5313 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5314 int tsflags;
5315
eddc9ec5 5316 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5317 base_flags |= tsflags << 12;
5318 }
5319 }
5320 }
1da177e4
LT		 5321#if TG3_VLAN_TAG_USED
5322 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5323 base_flags |= (TXD_FLAG_VLAN |
5324 (vlan_tx_tag_get(skb) << 16));
5325#endif
5326
90079ce8
DM		 5327 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5328 dev_kfree_skb(skb);
5329 goto out_unlock;
5330 }
5331
5332 sp = skb_shinfo(skb);
5333
5334 mapping = sp->dma_maps[0];
1da177e4
LT		 5335
5336 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5337
5338 would_hit_hwbug = 0;
5339
41588ba1
MC		 5340 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5341 would_hit_hwbug = 1;
5342 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5343 would_hit_hwbug = 1;
1da177e4
LT		 5344
5345 tg3_set_txd(tp, entry, mapping, len, base_flags,
5346 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5347
5348 entry = NEXT_TX(entry);
5349
5350 /* Now loop through additional data fragments, and queue them. */
5351 if (skb_shinfo(skb)->nr_frags > 0) {
5352 unsigned int i, last;
5353
5354 last = skb_shinfo(skb)->nr_frags - 1;
5355 for (i = 0; i <= last; i++) {
5356 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5357
5358 len = frag->size;
90079ce8 5359 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5360
5361 tp->tx_buffers[entry].skb = NULL;
1da177e4 5362
c58ec932
MC		 5363 if (tg3_4g_overflow_test(mapping, len))
5364 would_hit_hwbug = 1;
1da177e4 5365
72f2afb8
MC		 5366 if (tg3_40bit_overflow_test(tp, mapping, len))
5367 would_hit_hwbug = 1;
5368
1da177e4
LT		 5369 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5370 tg3_set_txd(tp, entry, mapping, len,
5371 base_flags, (i == last)|(mss << 1));
5372 else
5373 tg3_set_txd(tp, entry, mapping, len,
5374 base_flags, (i == last));
5375
5376 entry = NEXT_TX(entry);
5377 }
5378 }
5379
5380 if (would_hit_hwbug) {
5381 u32 last_plus_one = entry;
5382 u32 start;
1da177e4 5383
c58ec932
MC		 5384 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5385 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5386
5387 /* If the workaround fails due to memory/mapping
5388 * failure, silently drop this packet.
5389 */
72f2afb8 5390 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5391 &start, base_flags, mss))
1da177e4
LT		 5392 goto out_unlock;
5393
5394 entry = start;
5395 }
5396
5397 /* Packets are ready, update Tx producer idx local and on card. */
5398 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5399
5400 tp->tx_prod = entry;
1b2a7205 5401 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5402 netif_stop_queue(dev);
42952231 5403 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5404 netif_wake_queue(tp->dev);
5405 }
1da177e4
LT		 5406
5407out_unlock:
5408 mmiowb();
1da177e4
LT		 5409
5410 dev->trans_start = jiffies;
5411
5412 return NETDEV_TX_OK;
5413}
5414
5415static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5416 int new_mtu)
5417{
5418 dev->mtu = new_mtu;
5419
ef7f5ec0 5420 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5421 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5422 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5423 ethtool_op_set_tso(dev, 0);
5424 }
5425 else
5426 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5427 } else {
a4e2b347 5428 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5429 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5430 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5431 }
1da177e4
LT		 5432}
5433
5434static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5435{
5436 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5437 int err;
1da177e4
LT		 5438
5439 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5440 return -EINVAL;
5441
5442 if (!netif_running(dev)) {
5443 /* We'll just catch it later when the
5444 * device is up'd.
5445 */
5446 tg3_set_mtu(dev, tp, new_mtu);
5447 return 0;
5448 }
5449
b02fd9e3
MC		 5450 tg3_phy_stop(tp);
5451
1da177e4 5452 tg3_netif_stop(tp);
f47c11ee
DM		 5453
5454 tg3_full_lock(tp, 1);
1da177e4 5455
944d980e 5456 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5457
5458 tg3_set_mtu(dev, tp, new_mtu);
5459
b9ec6c1b 5460 err = tg3_restart_hw(tp, 0);
1da177e4 5461
b9ec6c1b
MC		 5462 if (!err)
5463 tg3_netif_start(tp);
1da177e4 5464
f47c11ee 5465 tg3_full_unlock(tp);
1da177e4 5466
b02fd9e3
MC		 5467 if (!err)
5468 tg3_phy_start(tp);
5469
b9ec6c1b 5470 return err;
1da177e4
LT		 5471}
5472
5473/* Free up pending packets in all rx/tx rings.
5474 *
5475 * The chip has been shut down and the driver detached from
5476 * the networking, so no interrupts or new tx packets will
5477 * end up in the driver. tp->{tx,}lock is not held and we are not
5478 * in an interrupt context and thus may sleep.
5479 */
5480static void tg3_free_rings(struct tg3 *tp)
5481{
5482 struct ring_info *rxp;
5483 int i;
5484
5485 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5486 rxp = &tp->rx_std_buffers[i];
5487
5488 if (rxp->skb == NULL)
5489 continue;
5490 pci_unmap_single(tp->pdev,
5491 pci_unmap_addr(rxp, mapping),
7e72aad4 5492 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5493 PCI_DMA_FROMDEVICE);
5494 dev_kfree_skb_any(rxp->skb);
5495 rxp->skb = NULL;
5496 }
5497
5498 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5499 rxp = &tp->rx_jumbo_buffers[i];
5500
5501 if (rxp->skb == NULL)
5502 continue;
5503 pci_unmap_single(tp->pdev,
5504 pci_unmap_addr(rxp, mapping),
5505 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5506 PCI_DMA_FROMDEVICE);
5507 dev_kfree_skb_any(rxp->skb);
5508 rxp->skb = NULL;
5509 }
5510
5511 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5512 struct tx_ring_info *txp;
5513 struct sk_buff *skb;
1da177e4
LT		 5514
5515 txp = &tp->tx_buffers[i];
5516 skb = txp->skb;
5517
5518 if (skb == NULL) {
5519 i++;
5520 continue;
5521 }
5522
90079ce8 5523 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5524
90079ce8 5525 txp->skb = NULL;
1da177e4 5526
90079ce8 5527 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5528
5529 dev_kfree_skb_any(skb);
5530 }
5531}
5532
5533/* Initialize tx/rx rings for packet processing.
5534 *
5535 * The chip has been shut down and the driver detached from
5536 * the networking, so no interrupts or new tx packets will
5537 * end up in the driver. tp->{tx,}lock are held and thus
5538 * we may not sleep.
5539 */
32d8c572 5540static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5541{
5542 u32 i;
5543
5544 /* Free up all the SKBs. */
5545 tg3_free_rings(tp);
5546
5547 /* Zero out all descriptors. */
5548 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5549 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5550 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5551 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5552
7e72aad4 5553 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5554 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5555 (tp->dev->mtu > ETH_DATA_LEN))
5556 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5557
1da177e4
LT		 5558 /* Initialize invariants of the rings, we only set this
5559 * stuff once. This works because the card does not
5560 * write into the rx buffer posting rings.
5561 */
5562 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5563 struct tg3_rx_buffer_desc *rxd;
5564
5565 rxd = &tp->rx_std[i];
7e72aad4 5566 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5567 << RXD_LEN_SHIFT;
5568 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5569 rxd->opaque = (RXD_OPAQUE_RING_STD |
5570 (i << RXD_OPAQUE_INDEX_SHIFT));
5571 }
5572
0f893dc6 5573 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5574 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5575 struct tg3_rx_buffer_desc *rxd;
5576
5577 rxd = &tp->rx_jumbo[i];
5578 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5579 << RXD_LEN_SHIFT;
5580 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5581 RXD_FLAG_JUMBO;
5582 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5583 (i << RXD_OPAQUE_INDEX_SHIFT));
5584 }
5585 }
5586
5587 /* Now allocate fresh SKBs for each rx ring. */
5588 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5589 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5590 printk(KERN_WARNING PFX
5591 "%s: Using a smaller RX standard ring, "
5592 "only %d out of %d buffers were allocated "
5593 "successfully.\n",
5594 tp->dev->name, i, tp->rx_pending);
5595 if (i == 0)
5596 return -ENOMEM;
5597 tp->rx_pending = i;
1da177e4 5598 break;
32d8c572 5599 }
1da177e4
LT		 5600 }
5601
0f893dc6 5602 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5603 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5604 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5605 -1, i) < 0) {
5606 printk(KERN_WARNING PFX
5607 "%s: Using a smaller RX jumbo ring, "
5608 "only %d out of %d buffers were "
5609 "allocated successfully.\n",
5610 tp->dev->name, i, tp->rx_jumbo_pending);
5611 if (i == 0) {
5612 tg3_free_rings(tp);
5613 return -ENOMEM;
5614 }
5615 tp->rx_jumbo_pending = i;
1da177e4 5616 break;
32d8c572 5617 }
1da177e4
LT		 5618 }
5619 }
32d8c572 5620 return 0;
1da177e4
LT		 5621}
5622
5623/*
5624 * Must not be invoked with interrupt sources disabled and
5625 * the hardware shutdown down.
5626 */
5627static void tg3_free_consistent(struct tg3 *tp)
5628{
b4558ea9
JJ		 5629 kfree(tp->rx_std_buffers);
5630 tp->rx_std_buffers = NULL;
1da177e4
LT		 5631 if (tp->rx_std) {
5632 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5633 tp->rx_std, tp->rx_std_mapping);
5634 tp->rx_std = NULL;
5635 }
5636 if (tp->rx_jumbo) {
5637 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5638 tp->rx_jumbo, tp->rx_jumbo_mapping);
5639 tp->rx_jumbo = NULL;
5640 }
5641 if (tp->rx_rcb) {
5642 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5643 tp->rx_rcb, tp->rx_rcb_mapping);
5644 tp->rx_rcb = NULL;
5645 }
5646 if (tp->tx_ring) {
5647 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5648 tp->tx_ring, tp->tx_desc_mapping);
5649 tp->tx_ring = NULL;
5650 }
5651 if (tp->hw_status) {
5652 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5653 tp->hw_status, tp->status_mapping);
5654 tp->hw_status = NULL;
5655 }
5656 if (tp->hw_stats) {
5657 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5658 tp->hw_stats, tp->stats_mapping);
5659 tp->hw_stats = NULL;
5660 }
5661}
5662
5663/*
5664 * Must not be invoked with interrupt sources disabled and
5665 * the hardware shutdown down. Can sleep.
5666 */
5667static int tg3_alloc_consistent(struct tg3 *tp)
5668{
bd2b3343 5669 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5670 (TG3_RX_RING_SIZE +
5671 TG3_RX_JUMBO_RING_SIZE)) +
5672 (sizeof(struct tx_ring_info) *
5673 TG3_TX_RING_SIZE),
5674 GFP_KERNEL);
5675 if (!tp->rx_std_buffers)
5676 return -ENOMEM;
5677
1da177e4
LT		 5678 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5679 tp->tx_buffers = (struct tx_ring_info *)
5680 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5681
5682 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5683 &tp->rx_std_mapping);
5684 if (!tp->rx_std)
5685 goto err_out;
5686
5687 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5688 &tp->rx_jumbo_mapping);
5689
5690 if (!tp->rx_jumbo)
5691 goto err_out;
5692
5693 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5694 &tp->rx_rcb_mapping);
5695 if (!tp->rx_rcb)
5696 goto err_out;
5697
5698 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5699 &tp->tx_desc_mapping);
5700 if (!tp->tx_ring)
5701 goto err_out;
5702
5703 tp->hw_status = pci_alloc_consistent(tp->pdev,
5704 TG3_HW_STATUS_SIZE,
5705 &tp->status_mapping);
5706 if (!tp->hw_status)
5707 goto err_out;
5708
5709 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5710 sizeof(struct tg3_hw_stats),
5711 &tp->stats_mapping);
5712 if (!tp->hw_stats)
5713 goto err_out;
5714
5715 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5716 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5717
5718 return 0;
5719
5720err_out:
5721 tg3_free_consistent(tp);
5722 return -ENOMEM;
5723}
5724
5725#define MAX_WAIT_CNT 1000
5726
5727/* To stop a block, clear the enable bit and poll till it
5728 * clears. tp->lock is held.
5729 */
b3b7d6be 5730static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5731{
5732 unsigned int i;
5733 u32 val;
5734
5735 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5736 switch (ofs) {
5737 case RCVLSC_MODE:
5738 case DMAC_MODE:
5739 case MBFREE_MODE:
5740 case BUFMGR_MODE:
5741 case MEMARB_MODE:
5742 /* We can't enable/disable these bits of the
5743 * 5705/5750, just say success.
5744 */
5745 return 0;
5746
5747 default:
5748 break;
855e1111 5749 }
1da177e4
LT		 5750 }
5751
5752 val = tr32(ofs);
5753 val &= ~enable_bit;
5754 tw32_f(ofs, val);
5755
5756 for (i = 0; i < MAX_WAIT_CNT; i++) {
5757 udelay(100);
5758 val = tr32(ofs);
5759 if ((val & enable_bit) == 0)
5760 break;
5761 }
5762
b3b7d6be 5763 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5764 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5765 "ofs=%lx enable_bit=%x\n",
5766 ofs, enable_bit);
5767 return -ENODEV;
5768 }
5769
5770 return 0;
5771}
5772
5773/* tp->lock is held. */
b3b7d6be 5774static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5775{
5776 int i, err;
5777
5778 tg3_disable_ints(tp);
5779
5780 tp->rx_mode &= ~RX_MODE_ENABLE;
5781 tw32_f(MAC_RX_MODE, tp->rx_mode);
5782 udelay(10);
5783
b3b7d6be
DM		 5784 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5785 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5786 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5787 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5788 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5789 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5790
5791 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5792 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5793 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5794 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5795 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5796 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5797 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5798
5799 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5800 tw32_f(MAC_MODE, tp->mac_mode);
5801 udelay(40);
5802
5803 tp->tx_mode &= ~TX_MODE_ENABLE;
5804 tw32_f(MAC_TX_MODE, tp->tx_mode);
5805
5806 for (i = 0; i < MAX_WAIT_CNT; i++) {
5807 udelay(100);
5808 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5809 break;
5810 }
5811 if (i >= MAX_WAIT_CNT) {
5812 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5813 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5814 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5815 err |= -ENODEV;
1da177e4
LT		 5816 }
5817
e6de8ad1 5818 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5819 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5820 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5821
5822 tw32(FTQ_RESET, 0xffffffff);
5823 tw32(FTQ_RESET, 0x00000000);
5824
b3b7d6be
DM		 5825 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5826 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5827
5828 if (tp->hw_status)
5829 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5830 if (tp->hw_stats)
5831 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5832
1da177e4
LT		 5833 return err;
5834}
5835
0d3031d9
MC		 5836static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5837{
5838 int i;
5839 u32 apedata;
5840
5841 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5842 if (apedata != APE_SEG_SIG_MAGIC)
5843 return;
5844
5845 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5846 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5847 return;
5848
5849 /* Wait for up to 1 millisecond for APE to service previous event. */
5850 for (i = 0; i < 10; i++) {
5851 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5852 return;
5853
5854 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5855
5856 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5857 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5858 event | APE_EVENT_STATUS_EVENT_PENDING);
5859
5860 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5861
5862 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5863 break;
5864
5865 udelay(100);
5866 }
5867
5868 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5869 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5870}
5871
5872static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5873{
5874 u32 event;
5875 u32 apedata;
5876
5877 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5878 return;
5879
5880 switch (kind) {
5881 case RESET_KIND_INIT:
5882 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5883 APE_HOST_SEG_SIG_MAGIC);
5884 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5885 APE_HOST_SEG_LEN_MAGIC);
5886 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5887 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5888 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5889 APE_HOST_DRIVER_ID_MAGIC);
5890 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5891 APE_HOST_BEHAV_NO_PHYLOCK);
5892
5893 event = APE_EVENT_STATUS_STATE_START;
5894 break;
5895 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5896 /* With the interface we are currently using,
5897 * APE does not track driver state. Wiping
5898 * out the HOST SEGMENT SIGNATURE forces
5899 * the APE to assume OS absent status.
5900 */
5901 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5902
0d3031d9
MC		 5903 event = APE_EVENT_STATUS_STATE_UNLOAD;
5904 break;
5905 case RESET_KIND_SUSPEND:
5906 event = APE_EVENT_STATUS_STATE_SUSPEND;
5907 break;
5908 default:
5909 return;
5910 }
5911
5912 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5913
5914 tg3_ape_send_event(tp, event);
5915}
5916
1da177e4
LT		 5917/* tp->lock is held. */
5918static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5919{
f49639e6
DM		 5920 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5921 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5922
5923 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5924 switch (kind) {
5925 case RESET_KIND_INIT:
5926 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5927 DRV_STATE_START);
5928 break;
5929
5930 case RESET_KIND_SHUTDOWN:
5931 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5932 DRV_STATE_UNLOAD);
5933 break;
5934
5935 case RESET_KIND_SUSPEND:
5936 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5937 DRV_STATE_SUSPEND);
5938 break;
5939
5940 default:
5941 break;
855e1111 5942 }
1da177e4 5943 }
0d3031d9
MC		 5944
5945 if (kind == RESET_KIND_INIT ||
5946 kind == RESET_KIND_SUSPEND)
5947 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5948}
5949
5950/* tp->lock is held. */
5951static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5952{
5953 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5954 switch (kind) {
5955 case RESET_KIND_INIT:
5956 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5957 DRV_STATE_START_DONE);
5958 break;
5959
5960 case RESET_KIND_SHUTDOWN:
5961 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5962 DRV_STATE_UNLOAD_DONE);
5963 break;
5964
5965 default:
5966 break;
855e1111 5967 }
1da177e4 5968 }
0d3031d9
MC		 5969
5970 if (kind == RESET_KIND_SHUTDOWN)
5971 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5972}
5973
5974/* tp->lock is held. */
5975static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5976{
5977 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5978 switch (kind) {
5979 case RESET_KIND_INIT:
5980 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5981 DRV_STATE_START);
5982 break;
5983
5984 case RESET_KIND_SHUTDOWN:
5985 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5986 DRV_STATE_UNLOAD);
5987 break;
5988
5989 case RESET_KIND_SUSPEND:
5990 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5991 DRV_STATE_SUSPEND);
5992 break;
5993
5994 default:
5995 break;
855e1111 5996 }
1da177e4
LT		 5997 }
5998}
5999
7a6f4369
MC		 6000static int tg3_poll_fw(struct tg3 *tp)
6001{
6002 int i;
6003 u32 val;
6004
b5d3772c 6005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6006 /* Wait up to 20ms for init done. */
6007 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6008 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6009 return 0;
0ccead18 6010 udelay(100);
b5d3772c
MC		 6011 }
6012 return -ENODEV;
6013 }
6014
7a6f4369
MC		 6015 /* Wait for firmware initialization to complete. */
6016 for (i = 0; i < 100000; i++) {
6017 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6018 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6019 break;
6020 udelay(10);
6021 }
6022
6023 /* Chip might not be fitted with firmware. Some Sun onboard
6024 * parts are configured like that. So don't signal the timeout
6025 * of the above loop as an error, but do report the lack of
6026 * running firmware once.
6027 */
6028 if (i >= 100000 &&
6029 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6030 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6031
6032 printk(KERN_INFO PFX "%s: No firmware running.\n",
6033 tp->dev->name);
6034 }
6035
6036 return 0;
6037}
6038
ee6a99b5
MC		 6039/* Save PCI command register before chip reset */
6040static void tg3_save_pci_state(struct tg3 *tp)
6041{
8a6eac90 6042 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6043}
6044
6045/* Restore PCI state after chip reset */
6046static void tg3_restore_pci_state(struct tg3 *tp)
6047{
6048 u32 val;
6049
6050 /* Re-enable indirect register accesses. */
6051 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6052 tp->misc_host_ctrl);
6053
6054 /* Set MAX PCI retry to zero. */
6055 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6056 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6057 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6058 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6059 /* Allow reads and writes to the APE register and memory space. */
6060 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6061 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6062 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6063 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6064
8a6eac90 6065 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6066
fcb389df
MC		 6067 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6068 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6069 pcie_set_readrq(tp->pdev, 4096);
6070 else {
6071 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6072 tp->pci_cacheline_sz);
6073 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6074 tp->pci_lat_timer);
6075 }
114342f2 6076 }
5f5c51e3 6077
ee6a99b5 6078 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6079 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6080 u16 pcix_cmd;
6081
6082 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6083 &pcix_cmd);
6084 pcix_cmd &= ~PCI_X_CMD_ERO;
6085 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6086 pcix_cmd);
6087 }
ee6a99b5
MC		 6088
6089 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6090
6091 /* Chip reset on 5780 will reset MSI enable bit,
6092 * so need to restore it.
6093 */
6094 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6095 u16 ctrl;
6096
6097 pci_read_config_word(tp->pdev,
6098 tp->msi_cap + PCI_MSI_FLAGS,
6099 &ctrl);
6100 pci_write_config_word(tp->pdev,
6101 tp->msi_cap + PCI_MSI_FLAGS,
6102 ctrl | PCI_MSI_FLAGS_ENABLE);
6103 val = tr32(MSGINT_MODE);
6104 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6105 }
6106 }
6107}
6108
1da177e4
LT		 6109static void tg3_stop_fw(struct tg3 *);
6110
6111/* tp->lock is held. */
6112static int tg3_chip_reset(struct tg3 *tp)
6113{
6114 u32 val;
1ee582d8 6115 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6116 int err;
1da177e4 6117
f49639e6
DM		 6118 tg3_nvram_lock(tp);
6119
158d7abd
MC		 6120 tg3_mdio_stop(tp);
6121
77b483f1
MC		 6122 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6123
f49639e6
DM		 6124 /* No matching tg3_nvram_unlock() after this because
6125 * chip reset below will undo the nvram lock.
6126 */
6127 tp->nvram_lock_cnt = 0;
1da177e4 6128
ee6a99b5
MC		 6129 /* GRC_MISC_CFG core clock reset will clear the memory
6130 * enable bit in PCI register 4 and the MSI enable bit
6131 * on some chips, so we save relevant registers here.
6132 */
6133 tg3_save_pci_state(tp);
6134
d9ab5ad1 6135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6136 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6137 tw32(GRC_FASTBOOT_PC, 0);
6138
1da177e4
LT		 6139 /*
6140 * We must avoid the readl() that normally takes place.
6141 * It locks machines, causes machine checks, and other
6142 * fun things. So, temporarily disable the 5701
6143 * hardware workaround, while we do the reset.
6144 */
1ee582d8
MC		 6145 write_op = tp->write32;
6146 if (write_op == tg3_write_flush_reg32)
6147 tp->write32 = tg3_write32;
1da177e4 6148
d18edcb2
MC		 6149 /* Prevent the irq handler from reading or writing PCI registers
6150 * during chip reset when the memory enable bit in the PCI command
6151 * register may be cleared. The chip does not generate interrupt
6152 * at this time, but the irq handler may still be called due to irq
6153 * sharing or irqpoll.
6154 */
6155 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6156 if (tp->hw_status) {
6157 tp->hw_status->status = 0;
6158 tp->hw_status->status_tag = 0;
6159 }
d18edcb2
MC		 6160 tp->last_tag = 0;
6161 smp_mb();
6162 synchronize_irq(tp->pdev->irq);
6163
1da177e4
LT		 6164 /* do the reset */
6165 val = GRC_MISC_CFG_CORECLK_RESET;
6166
6167 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6168 if (tr32(0x7e2c) == 0x60) {
6169 tw32(0x7e2c, 0x20);
6170 }
6171 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6172 tw32(GRC_MISC_CFG, (1 << 29));
6173 val |= (1 << 29);
6174 }
6175 }
6176
b5d3772c
MC		 6177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6178 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6179 tw32(GRC_VCPU_EXT_CTRL,
6180 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6181 }
6182
1da177e4
LT		 6183 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6184 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6185 tw32(GRC_MISC_CFG, val);
6186
1ee582d8
MC		 6187 /* restore 5701 hardware bug workaround write method */
6188 tp->write32 = write_op;
1da177e4
LT		 6189
6190 /* Unfortunately, we have to delay before the PCI read back.
6191 * Some 575X chips even will not respond to a PCI cfg access
6192 * when the reset command is given to the chip.
6193 *
6194 * How do these hardware designers expect things to work
6195 * properly if the PCI write is posted for a long period
6196 * of time? It is always necessary to have some method by
6197 * which a register read back can occur to push the write
6198 * out which does the reset.
6199 *
6200 * For most tg3 variants the trick below was working.
6201 * Ho hum...
6202 */
6203 udelay(120);
6204
6205 /* Flush PCI posted writes. The normal MMIO registers
6206 * are inaccessible at this time so this is the only
6207 * way to make this reliably (actually, this is no longer
6208 * the case, see above). I tried to use indirect
6209 * register read/write but this upset some 5701 variants.
6210 */
6211 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6212
6213 udelay(120);
6214
5e7dfd0f 6215 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6216 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6217 int i;
6218 u32 cfg_val;
6219
6220 /* Wait for link training to complete. */
6221 for (i = 0; i < 5000; i++)
6222 udelay(100);
6223
6224 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6225 pci_write_config_dword(tp->pdev, 0xc4,
6226 cfg_val | (1 << 15));
6227 }
5e7dfd0f
MC		 6228
6229 /* Set PCIE max payload size to 128 bytes and
6230 * clear the "no snoop" and "relaxed ordering" bits.
6231 */
6232 pci_write_config_word(tp->pdev,
6233 tp->pcie_cap + PCI_EXP_DEVCTL,
6234 0);
6235
6236 pcie_set_readrq(tp->pdev, 4096);
6237
6238 /* Clear error status */
6239 pci_write_config_word(tp->pdev,
6240 tp->pcie_cap + PCI_EXP_DEVSTA,
6241 PCI_EXP_DEVSTA_CED |
6242 PCI_EXP_DEVSTA_NFED |
6243 PCI_EXP_DEVSTA_FED |
6244 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6245 }
6246
ee6a99b5 6247 tg3_restore_pci_state(tp);
1da177e4 6248
d18edcb2
MC		 6249 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6250
ee6a99b5
MC		 6251 val = 0;
6252 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6253 val = tr32(MEMARB_MODE);
ee6a99b5 6254 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6255
6256 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6257 tg3_stop_fw(tp);
6258 tw32(0x5000, 0x400);
6259 }
6260
6261 tw32(GRC_MODE, tp->grc_mode);
6262
6263 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6264 val = tr32(0xc4);
1da177e4
LT		 6265
6266 tw32(0xc4, val | (1 << 15));
6267 }
6268
6269 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6271 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6272 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6273 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6274 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6275 }
6276
6277 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6278 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6279 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6280 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6281 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6282 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6283 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6284 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6285 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6286 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6287 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6288 } else
6289 tw32_f(MAC_MODE, 0);
6290 udelay(40);
6291
158d7abd
MC		 6292 tg3_mdio_start(tp);
6293
77b483f1
MC		 6294 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6295
7a6f4369
MC		 6296 err = tg3_poll_fw(tp);
6297 if (err)
6298 return err;
1da177e4
LT		 6299
6300 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6301 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6302 val = tr32(0x7c00);
1da177e4
LT		 6303
6304 tw32(0x7c00, val | (1 << 25));
6305 }
6306
6307 /* Reprobe ASF enable state. */
6308 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6309 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6310 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6311 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6312 u32 nic_cfg;
6313
6314 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6315 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6316 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6317 tp->last_event_jiffies = jiffies;
cbf46853 6318 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6319 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6320 }
6321 }
6322
6323 return 0;
6324}
6325
6326/* tp->lock is held. */
6327static void tg3_stop_fw(struct tg3 *tp)
6328{
0d3031d9
MC		 6329 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6330 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6331 /* Wait for RX cpu to ACK the previous event. */
6332 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6333
6334 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6335
6336 tg3_generate_fw_event(tp);
1da177e4 6337
7c5026aa
MC		 6338 /* Wait for RX cpu to ACK this event. */
6339 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6340 }
6341}
6342
6343/* tp->lock is held. */
944d980e 6344static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6345{
6346 int err;
6347
6348 tg3_stop_fw(tp);
6349
944d980e 6350 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6351
b3b7d6be 6352 tg3_abort_hw(tp, silent);
1da177e4
LT		 6353 err = tg3_chip_reset(tp);
6354
944d980e
MC		 6355 tg3_write_sig_legacy(tp, kind);
6356 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6357
6358 if (err)
6359 return err;
6360
6361 return 0;
6362}
6363
1da177e4
LT		 6364#define RX_CPU_SCRATCH_BASE 0x30000
6365#define RX_CPU_SCRATCH_SIZE 0x04000
6366#define TX_CPU_SCRATCH_BASE 0x34000
6367#define TX_CPU_SCRATCH_SIZE 0x04000
6368
6369/* tp->lock is held. */
6370static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6371{
6372 int i;
6373
5d9428de
ES		 6374 BUG_ON(offset == TX_CPU_BASE &&
6375 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6376
b5d3772c
MC		 6377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6378 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6379
6380 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6381 return 0;
6382 }
1da177e4
LT		 6383 if (offset == RX_CPU_BASE) {
6384 for (i = 0; i < 10000; i++) {
6385 tw32(offset + CPU_STATE, 0xffffffff);
6386 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6387 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6388 break;
6389 }
6390
6391 tw32(offset + CPU_STATE, 0xffffffff);
6392 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6393 udelay(10);
6394 } else {
6395 for (i = 0; i < 10000; i++) {
6396 tw32(offset + CPU_STATE, 0xffffffff);
6397 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6398 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6399 break;
6400 }
6401 }
6402
6403 if (i >= 10000) {
6404 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6405 "and %s CPU\n",
6406 tp->dev->name,
6407 (offset == RX_CPU_BASE ? "RX" : "TX"));
6408 return -ENODEV;
6409 }
ec41c7df
MC		 6410
6411 /* Clear firmware's nvram arbitration. */
6412 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6413 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6414 return 0;
6415}
6416
6417struct fw_info {
077f849d
JSR		 6418 unsigned int fw_base;
6419 unsigned int fw_len;
6420 const __be32 *fw_data;
1da177e4
LT		 6421};
6422
6423/* tp->lock is held. */
6424static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6425 int cpu_scratch_size, struct fw_info *info)
6426{
ec41c7df 6427 int err, lock_err, i;
1da177e4
LT		 6428 void (*write_op)(struct tg3 *, u32, u32);
6429
6430 if (cpu_base == TX_CPU_BASE &&
6431 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6432 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6433 "TX cpu firmware on %s which is 5705.\n",
6434 tp->dev->name);
6435 return -EINVAL;
6436 }
6437
6438 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6439 write_op = tg3_write_mem;
6440 else
6441 write_op = tg3_write_indirect_reg32;
6442
1b628151
MC		 6443 /* It is possible that bootcode is still loading at this point.
6444 * Get the nvram lock first before halting the cpu.
6445 */
ec41c7df 6446 lock_err = tg3_nvram_lock(tp);
1da177e4 6447 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6448 if (!lock_err)
6449 tg3_nvram_unlock(tp);
1da177e4
LT		 6450 if (err)
6451 goto out;
6452
6453 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6454 write_op(tp, cpu_scratch_base + i, 0);
6455 tw32(cpu_base + CPU_STATE, 0xffffffff);
6456 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6457 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6458 write_op(tp, (cpu_scratch_base +
077f849d 6459 (info->fw_base & 0xffff) +
1da177e4 6460 (i * sizeof(u32))),
077f849d 6461 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6462
6463 err = 0;
6464
6465out:
1da177e4
LT		 6466 return err;
6467}
6468
6469/* tp->lock is held. */
6470static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6471{
6472 struct fw_info info;
077f849d 6473 const __be32 *fw_data;
1da177e4
LT		 6474 int err, i;
6475
077f849d
JSR		 6476 fw_data = (void *)tp->fw->data;
6477
6478 /* Firmware blob starts with version numbers, followed by
6479 start address and length. We are setting complete length.
6480 length = end_address_of_bss - start_address_of_text.
6481 Remainder is the blob to be loaded contiguously
6482 from start address. */
6483
6484 info.fw_base = be32_to_cpu(fw_data[1]);
6485 info.fw_len = tp->fw->size - 12;
6486 info.fw_data = &fw_data[3];
1da177e4
LT		 6487
6488 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6489 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6490 &info);
6491 if (err)
6492 return err;
6493
6494 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6495 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6496 &info);
6497 if (err)
6498 return err;
6499
6500 /* Now startup only the RX cpu. */
6501 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6502 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6503
6504 for (i = 0; i < 5; i++) {
077f849d 6505 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6506 break;
6507 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6508 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6509 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6510 udelay(1000);
6511 }
6512 if (i >= 5) {
6513 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6514 "to set RX CPU PC, is %08x should be %08x\n",
6515 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6516 info.fw_base);
1da177e4
LT		 6517 return -ENODEV;
6518 }
6519 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6520 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6521
6522 return 0;
6523}
6524
1da177e4 6525/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6526
6527/* tp->lock is held. */
6528static int tg3_load_tso_firmware(struct tg3 *tp)
6529{
6530 struct fw_info info;
077f849d 6531 const __be32 *fw_data;
1da177e4
LT		 6532 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6533 int err, i;
6534
6535 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6536 return 0;
6537
077f849d
JSR		 6538 fw_data = (void *)tp->fw->data;
6539
6540 /* Firmware blob starts with version numbers, followed by
6541 start address and length. We are setting complete length.
6542 length = end_address_of_bss - start_address_of_text.
6543 Remainder is the blob to be loaded contiguously
6544 from start address. */
6545
6546 info.fw_base = be32_to_cpu(fw_data[1]);
6547 cpu_scratch_size = tp->fw_len;
6548 info.fw_len = tp->fw->size - 12;
6549 info.fw_data = &fw_data[3];
6550
1da177e4 6551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6552 cpu_base = RX_CPU_BASE;
6553 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6554 } else {
1da177e4
LT		 6555 cpu_base = TX_CPU_BASE;
6556 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6557 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6558 }
6559
6560 err = tg3_load_firmware_cpu(tp, cpu_base,
6561 cpu_scratch_base, cpu_scratch_size,
6562 &info);
6563 if (err)
6564 return err;
6565
6566 /* Now startup the cpu. */
6567 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6568 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6569
6570 for (i = 0; i < 5; i++) {
077f849d 6571 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6572 break;
6573 tw32(cpu_base + CPU_STATE, 0xffffffff);
6574 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6575 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6576 udelay(1000);
6577 }
6578 if (i >= 5) {
6579 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6580 "to set CPU PC, is %08x should be %08x\n",
6581 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6582 info.fw_base);
1da177e4
LT		 6583 return -ENODEV;
6584 }
6585 tw32(cpu_base + CPU_STATE, 0xffffffff);
6586 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6587 return 0;
6588}
6589
1da177e4 6590
1da177e4
LT		 6591static int tg3_set_mac_addr(struct net_device *dev, void *p)
6592{
6593 struct tg3 *tp = netdev_priv(dev);
6594 struct sockaddr *addr = p;
986e0aeb 6595 int err = 0, skip_mac_1 = 0;
1da177e4 6596
f9804ddb
MC		 6597 if (!is_valid_ether_addr(addr->sa_data))
6598 return -EINVAL;
6599
1da177e4
LT		 6600 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6601
e75f7c90
MC		 6602 if (!netif_running(dev))
6603 return 0;
6604
58712ef9 6605 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6606 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6607
986e0aeb
MC		 6608 addr0_high = tr32(MAC_ADDR_0_HIGH);
6609 addr0_low = tr32(MAC_ADDR_0_LOW);
6610 addr1_high = tr32(MAC_ADDR_1_HIGH);
6611 addr1_low = tr32(MAC_ADDR_1_LOW);
6612
6613 /* Skip MAC addr 1 if ASF is using it. */
6614 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6615 !(addr1_high == 0 && addr1_low == 0))
6616 skip_mac_1 = 1;
58712ef9 6617 }
986e0aeb
MC		 6618 spin_lock_bh(&tp->lock);
6619 __tg3_set_mac_addr(tp, skip_mac_1);
6620 spin_unlock_bh(&tp->lock);
1da177e4 6621
b9ec6c1b 6622 return err;
1da177e4
LT		 6623}
6624
6625/* tp->lock is held. */
6626static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6627 dma_addr_t mapping, u32 maxlen_flags,
6628 u32 nic_addr)
6629{
6630 tg3_write_mem(tp,
6631 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6632 ((u64) mapping >> 32));
6633 tg3_write_mem(tp,
6634 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6635 ((u64) mapping & 0xffffffff));
6636 tg3_write_mem(tp,
6637 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6638 maxlen_flags);
6639
6640 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6641 tg3_write_mem(tp,
6642 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6643 nic_addr);
6644}
6645
6646static void __tg3_set_rx_mode(struct net_device *);
d244c892 6647static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6648{
6649 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6650 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6651 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6652 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6653 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6654 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6655 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6656 }
6657 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6658 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6659 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6660 u32 val = ec->stats_block_coalesce_usecs;
6661
6662 if (!netif_carrier_ok(tp->dev))
6663 val = 0;
6664
6665 tw32(HOSTCC_STAT_COAL_TICKS, val);
6666 }
6667}
1da177e4
LT		 6668
6669/* tp->lock is held. */
8e7a22e3 6670static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6671{
6672 u32 val, rdmac_mode;
6673 int i, err, limit;
6674
6675 tg3_disable_ints(tp);
6676
6677 tg3_stop_fw(tp);
6678
6679 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6680
6681 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6682 tg3_abort_hw(tp, 1);
1da177e4
LT		 6683 }
6684
dd477003
MC		 6685 if (reset_phy &&
6686 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6687 tg3_phy_reset(tp);
6688
1da177e4
LT		 6689 err = tg3_chip_reset(tp);
6690 if (err)
6691 return err;
6692
6693 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6694
bcb37f6c 6695 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6696 val = tr32(TG3_CPMU_CTRL);
6697 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6698 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6699
6700 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6701 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6702 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6703 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6704
6705 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6706 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6707 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6708 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6709
6710 val = tr32(TG3_CPMU_HST_ACC);
6711 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6712 val |= CPMU_HST_ACC_MACCLK_6_25;
6713 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6714 }
6715
1da177e4
LT		 6716 /* This works around an issue with Athlon chipsets on
6717 * B3 tigon3 silicon. This bit has no effect on any
6718 * other revision. But do not set this on PCI Express
795d01c5 6719 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6720 */
795d01c5
MC		 6721 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6722 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6723 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6724 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6725 }
1da177e4
LT		 6726
6727 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6728 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6729 val = tr32(TG3PCI_PCISTATE);
6730 val |= PCISTATE_RETRY_SAME_DMA;
6731 tw32(TG3PCI_PCISTATE, val);
6732 }
6733
0d3031d9
MC		 6734 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6735 /* Allow reads and writes to the
6736 * APE register and memory space.
6737 */
6738 val = tr32(TG3PCI_PCISTATE);
6739 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6740 PCISTATE_ALLOW_APE_SHMEM_WR;
6741 tw32(TG3PCI_PCISTATE, val);
6742 }
6743
1da177e4
LT		 6744 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6745 /* Enable some hw fixes. */
6746 val = tr32(TG3PCI_MSI_DATA);
6747 val |= (1 << 26) | (1 << 28) | (1 << 29);
6748 tw32(TG3PCI_MSI_DATA, val);
6749 }
6750
6751 /* Descriptor ring init may make accesses to the
6752 * NIC SRAM area to setup the TX descriptors, so we
6753 * can only do this after the hardware has been
6754 * successfully reset.
6755 */
32d8c572
MC		 6756 err = tg3_init_rings(tp);
6757 if (err)
6758 return err;
1da177e4 6759
9936bcf6 6760 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6761 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6762 /* This value is determined during the probe time DMA
6763 * engine test, tg3_test_dma.
6764 */
6765 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6766 }
1da177e4
LT		 6767
6768 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6769 GRC_MODE_4X_NIC_SEND_RINGS |
6770 GRC_MODE_NO_TX_PHDR_CSUM |
6771 GRC_MODE_NO_RX_PHDR_CSUM);
6772 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6773
6774 /* Pseudo-header checksum is done by hardware logic and not
6775 * the offload processers, so make the chip do the pseudo-
6776 * header checksums on receive. For transmit it is more
6777 * convenient to do the pseudo-header checksum in software
6778 * as Linux does that on transmit for us in all cases.
6779 */
6780 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6781
6782 tw32(GRC_MODE,
6783 tp->grc_mode |
6784 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6785
6786 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6787 val = tr32(GRC_MISC_CFG);
6788 val &= ~0xff;
6789 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6790 tw32(GRC_MISC_CFG, val);
6791
6792 /* Initialize MBUF/DESC pool. */
cbf46853 6793 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6794 /* Do nothing. */
6795 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6796 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6798 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6799 else
6800 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6801 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6802 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6803 }
1da177e4
LT		 6804 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6805 int fw_len;
6806
077f849d 6807 fw_len = tp->fw_len;
1da177e4
LT		 6808 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6809 tw32(BUFMGR_MB_POOL_ADDR,
6810 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6811 tw32(BUFMGR_MB_POOL_SIZE,
6812 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6813 }
1da177e4 6814
0f893dc6 6815 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6816 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6817 tp->bufmgr_config.mbuf_read_dma_low_water);
6818 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6819 tp->bufmgr_config.mbuf_mac_rx_low_water);
6820 tw32(BUFMGR_MB_HIGH_WATER,
6821 tp->bufmgr_config.mbuf_high_water);
6822 } else {
6823 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6824 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6825 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6826 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6827 tw32(BUFMGR_MB_HIGH_WATER,
6828 tp->bufmgr_config.mbuf_high_water_jumbo);
6829 }
6830 tw32(BUFMGR_DMA_LOW_WATER,
6831 tp->bufmgr_config.dma_low_water);
6832 tw32(BUFMGR_DMA_HIGH_WATER,
6833 tp->bufmgr_config.dma_high_water);
6834
6835 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6836 for (i = 0; i < 2000; i++) {
6837 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6838 break;
6839 udelay(10);
6840 }
6841 if (i >= 2000) {
6842 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6843 tp->dev->name);
6844 return -ENODEV;
6845 }
6846
6847 /* Setup replenish threshold. */
f92905de
MC		 6848 val = tp->rx_pending / 8;
6849 if (val == 0)
6850 val = 1;
6851 else if (val > tp->rx_std_max_post)
6852 val = tp->rx_std_max_post;
b5d3772c
MC		 6853 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6854 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6855 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6856
6857 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6858 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6859 }
f92905de
MC		 6860
6861 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6862
6863 /* Initialize TG3_BDINFO's at:
6864 * RCVDBDI_STD_BD: standard eth size rx ring
6865 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6866 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6867 *
6868 * like so:
6869 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6870 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6871 * ring attribute flags
6872 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6873 *
6874 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6875 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6876 *
6877 * The size of each ring is fixed in the firmware, but the location is
6878 * configurable.
6879 */
6880 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6881 ((u64) tp->rx_std_mapping >> 32));
6882 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6883 ((u64) tp->rx_std_mapping & 0xffffffff));
6884 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6885 NIC_SRAM_RX_BUFFER_DESC);
6886
6887 /* Don't even try to program the JUMBO/MINI buffer descriptor
6888 * configs on 5705.
6889 */
6890 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6891 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6892 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6893 } else {
6894 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6895 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6896
6897 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6898 BDINFO_FLAGS_DISABLED);
6899
6900 /* Setup replenish threshold. */
6901 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6902
0f893dc6 6903 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6904 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6905 ((u64) tp->rx_jumbo_mapping >> 32));
6906 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6907 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6908 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6909 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6910 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6911 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6912 } else {
6913 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6914 BDINFO_FLAGS_DISABLED);
6915 }
6916
6917 }
6918
6919 /* There is only one send ring on 5705/5750, no need to explicitly
6920 * disable the others.
6921 */
6922 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6923 /* Clear out send RCB ring in SRAM. */
6924 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6925 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6926 BDINFO_FLAGS_DISABLED);
6927 }
6928
6929 tp->tx_prod = 0;
6930 tp->tx_cons = 0;
6931 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6932 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6933
6934 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6935 tp->tx_desc_mapping,
6936 (TG3_TX_RING_SIZE <<
6937 BDINFO_FLAGS_MAXLEN_SHIFT),
6938 NIC_SRAM_TX_BUFFER_DESC);
6939
6940 /* There is only one receive return ring on 5705/5750, no need
6941 * to explicitly disable the others.
6942 */
6943 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6944 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6945 i += TG3_BDINFO_SIZE) {
6946 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6947 BDINFO_FLAGS_DISABLED);
6948 }
6949 }
6950
6951 tp->rx_rcb_ptr = 0;
6952 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6953
6954 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6955 tp->rx_rcb_mapping,
6956 (TG3_RX_RCB_RING_SIZE(tp) <<
6957 BDINFO_FLAGS_MAXLEN_SHIFT),
6958 0);
6959
6960 tp->rx_std_ptr = tp->rx_pending;
6961 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6962 tp->rx_std_ptr);
6963
0f893dc6 6964 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6965 tp->rx_jumbo_pending : 0;
6966 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6967 tp->rx_jumbo_ptr);
6968
6969 /* Initialize MAC address and backoff seed. */
986e0aeb 6970 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6971
6972 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 6973 tw32(MAC_RX_MTU_SIZE,
6974 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 6975
6976 /* The slot time is changed by tg3_setup_phy if we
6977 * run at gigabit with half duplex.
6978 */
6979 tw32(MAC_TX_LENGTHS,
6980 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6981 (6 << TX_LENGTHS_IPG_SHIFT) |
6982 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6983
6984 /* Receive rules. */
6985 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6986 tw32(RCVLPC_CONFIG, 0x0181);
6987
6988 /* Calculate RDMAC_MODE setting early, we need it to determine
6989 * the RCVLPC_STATE_ENABLE mask.
6990 */
6991 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6992 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6993 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6994 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6995 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6996
57e6983c 6997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 6998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7000 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7001 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7002 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7003
85e94ced
MC		 7004 /* If statement applies to 5705 and 5750 PCI devices only */
7005 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7006 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7007 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7008 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7010 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7011 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7012 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7013 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7014 }
7015 }
7016
85e94ced
MC		 7017 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7018 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7019
1da177e4 7020 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7021 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7022
7023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7025 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7026
7027 /* Receive/send statistics. */
1661394e
MC		 7028 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7029 val = tr32(RCVLPC_STATS_ENABLE);
7030 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7031 tw32(RCVLPC_STATS_ENABLE, val);
7032 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7033 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7034 val = tr32(RCVLPC_STATS_ENABLE);
7035 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7036 tw32(RCVLPC_STATS_ENABLE, val);
7037 } else {
7038 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7039 }
7040 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7041 tw32(SNDDATAI_STATSENAB, 0xffffff);
7042 tw32(SNDDATAI_STATSCTRL,
7043 (SNDDATAI_SCTRL_ENABLE |
7044 SNDDATAI_SCTRL_FASTUPD));
7045
7046 /* Setup host coalescing engine. */
7047 tw32(HOSTCC_MODE, 0);
7048 for (i = 0; i < 2000; i++) {
7049 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7050 break;
7051 udelay(10);
7052 }
7053
d244c892 7054 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7055
7056 /* set status block DMA address */
7057 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7058 ((u64) tp->status_mapping >> 32));
7059 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7060 ((u64) tp->status_mapping & 0xffffffff));
7061
7062 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7063 /* Status/statistics block address. See tg3_timer,
7064 * the tg3_periodic_fetch_stats call there, and
7065 * tg3_get_stats to see how this works for 5705/5750 chips.
7066 */
1da177e4
LT		 7067 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7068 ((u64) tp->stats_mapping >> 32));
7069 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7070 ((u64) tp->stats_mapping & 0xffffffff));
7071 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7072 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7073 }
7074
7075 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7076
7077 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7078 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7079 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7080 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7081
7082 /* Clear statistics/status block in chip, and status block in ram. */
7083 for (i = NIC_SRAM_STATS_BLK;
7084 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7085 i += sizeof(u32)) {
7086 tg3_write_mem(tp, i, 0);
7087 udelay(40);
7088 }
7089 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7090
c94e3941
MC		 7091 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7092 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7093 /* reset to prevent losing 1st rx packet intermittently */
7094 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7095 udelay(10);
7096 }
7097
3bda1258
MC		 7098 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7099 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7100 else
7101 tp->mac_mode = 0;
7102 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7103 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7105 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7106 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7107 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7108 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7109 udelay(40);
7110
314fba34 7111 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7112 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7113 * register to preserve the GPIO settings for LOMs. The GPIOs,
7114 * whether used as inputs or outputs, are set by boot code after
7115 * reset.
7116 */
9d26e213 7117 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7118 u32 gpio_mask;
7119
9d26e213
MC		 7120 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7121 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7122 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7123
7124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7125 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7126 GRC_LCLCTRL_GPIO_OUTPUT3;
7127
af36e6b6
MC		 7128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7129 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7130
aaf84465 7131 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7132 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7133
7134 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7135 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7136 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7137 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7138 }
1da177e4
LT		 7139 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7140 udelay(100);
7141
09ee929c 7142 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 7143 tp->last_tag = 0;
1da177e4
LT		 7144
7145 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7146 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7147 udelay(40);
7148 }
7149
7150 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7151 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7152 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7153 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7154 WDMAC_MODE_LNGREAD_ENAB);
7155
85e94ced
MC		 7156 /* If statement applies to 5705 and 5750 PCI devices only */
7157 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7158 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7160 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7161 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7162 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7163 /* nothing */
7164 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7165 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7166 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7167 val |= WDMAC_MODE_RX_ACCEL;
7168 }
7169 }
7170
d9ab5ad1 7171 /* Enable host coalescing bug fix */
321d32a0 7172 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7173 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7174
1da177e4
LT		 7175 tw32_f(WDMAC_MODE, val);
7176 udelay(40);
7177
9974a356
MC		 7178 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7179 u16 pcix_cmd;
7180
7181 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7182 &pcix_cmd);
1da177e4 7183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7184 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7185 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7186 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7187 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7188 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7189 }
9974a356
MC		 7190 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7191 pcix_cmd);
1da177e4
LT		 7192 }
7193
7194 tw32_f(RDMAC_MODE, rdmac_mode);
7195 udelay(40);
7196
7197 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7198 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7199 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7200
7201 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7202 tw32(SNDDATAC_MODE,
7203 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7204 else
7205 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7206
1da177e4
LT		 7207 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7208 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7209 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7210 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7211 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7212 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7213 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7214 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7215
7216 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7217 err = tg3_load_5701_a0_firmware_fix(tp);
7218 if (err)
7219 return err;
7220 }
7221
1da177e4
LT		 7222 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7223 err = tg3_load_tso_firmware(tp);
7224 if (err)
7225 return err;
7226 }
1da177e4
LT		 7227
7228 tp->tx_mode = TX_MODE_ENABLE;
7229 tw32_f(MAC_TX_MODE, tp->tx_mode);
7230 udelay(100);
7231
7232 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7233 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7234 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7235
1da177e4
LT		 7236 tw32_f(MAC_RX_MODE, tp->rx_mode);
7237 udelay(10);
7238
1da177e4
LT		 7239 tw32(MAC_LED_CTRL, tp->led_ctrl);
7240
7241 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7242 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7243 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7244 udelay(10);
7245 }
7246 tw32_f(MAC_RX_MODE, tp->rx_mode);
7247 udelay(10);
7248
7249 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7250 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7251 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7252 /* Set drive transmission level to 1.2V */
7253 /* only if the signal pre-emphasis bit is not set */
7254 val = tr32(MAC_SERDES_CFG);
7255 val &= 0xfffff000;
7256 val |= 0x880;
7257 tw32(MAC_SERDES_CFG, val);
7258 }
7259 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7260 tw32(MAC_SERDES_CFG, 0x616000);
7261 }
7262
7263 /* Prevent chip from dropping frames when flow control
7264 * is enabled.
7265 */
7266 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7267
7268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7269 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7270 /* Use hardware link auto-negotiation */
7271 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7272 }
7273
d4d2c558
MC		 7274 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7275 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7276 u32 tmp;
7277
7278 tmp = tr32(SERDES_RX_CTRL);
7279 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7280 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7281 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7282 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7283 }
7284
dd477003
MC		 7285 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7286 if (tp->link_config.phy_is_low_power) {
7287 tp->link_config.phy_is_low_power = 0;
7288 tp->link_config.speed = tp->link_config.orig_speed;
7289 tp->link_config.duplex = tp->link_config.orig_duplex;
7290 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7291 }
1da177e4 7292
dd477003
MC		 7293 err = tg3_setup_phy(tp, 0);
7294 if (err)
7295 return err;
1da177e4 7296
dd477003
MC		 7297 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7298 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7299 u32 tmp;
7300
7301 /* Clear CRC stats. */
7302 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7303 tg3_writephy(tp, MII_TG3_TEST1,
7304 tmp | MII_TG3_TEST1_CRC_EN);
7305 tg3_readphy(tp, 0x14, &tmp);
7306 }
1da177e4
LT		 7307 }
7308 }
7309
7310 __tg3_set_rx_mode(tp->dev);
7311
7312 /* Initialize receive rules. */
7313 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7314 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7315 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7316 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7317
4cf78e4f 7318 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7319 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7320 limit = 8;
7321 else
7322 limit = 16;
7323 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7324 limit -= 4;
7325 switch (limit) {
7326 case 16:
7327 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7328 case 15:
7329 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7330 case 14:
7331 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7332 case 13:
7333 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7334 case 12:
7335 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7336 case 11:
7337 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7338 case 10:
7339 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7340 case 9:
7341 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7342 case 8:
7343 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7344 case 7:
7345 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7346 case 6:
7347 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7348 case 5:
7349 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7350 case 4:
7351 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7352 case 3:
7353 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7354 case 2:
7355 case 1:
7356
7357 default:
7358 break;
855e1111 7359 }
1da177e4 7360
9ce768ea
MC		 7361 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7362 /* Write our heartbeat update interval to APE. */
7363 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7364 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7365
1da177e4
LT		 7366 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7367
1da177e4
LT		 7368 return 0;
7369}
7370
7371/* Called at device open time to get the chip ready for
7372 * packet processing. Invoked with tp->lock held.
7373 */
8e7a22e3 7374static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7375{
1da177e4
LT		 7376 tg3_switch_clocks(tp);
7377
7378 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7379
2f751b67 7380 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7381}
7382
7383#define TG3_STAT_ADD32(PSTAT, REG) \
7384do { u32 __val = tr32(REG); \
7385 (PSTAT)->low += __val; \
7386 if ((PSTAT)->low < __val) \
7387 (PSTAT)->high += 1; \
7388} while (0)
7389
7390static void tg3_periodic_fetch_stats(struct tg3 *tp)
7391{
7392 struct tg3_hw_stats *sp = tp->hw_stats;
7393
7394 if (!netif_carrier_ok(tp->dev))
7395 return;
7396
7397 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7398 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7399 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7400 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7401 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7402 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7403 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7404 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7405 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7406 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7407 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7408 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7409 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7410
7411 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7412 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7413 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7414 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7415 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7416 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7417 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7418 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7419 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7420 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7421 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7422 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7423 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7424 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7425
7426 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7427 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7428 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7429}
7430
7431static void tg3_timer(unsigned long __opaque)
7432{
7433 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7434
f475f163
MC		 7435 if (tp->irq_sync)
7436 goto restart_timer;
7437
f47c11ee 7438 spin_lock(&tp->lock);
1da177e4 7439
fac9b83e
DM		 7440 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7441 /* All of this garbage is because when using non-tagged
7442 * IRQ status the mailbox/status_block protocol the chip
7443 * uses with the cpu is race prone.
7444 */
7445 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7446 tw32(GRC_LOCAL_CTRL,
7447 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7448 } else {
7449 tw32(HOSTCC_MODE, tp->coalesce_mode |
7450 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7451 }
1da177e4 7452
fac9b83e
DM		 7453 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7454 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7455 spin_unlock(&tp->lock);
fac9b83e
DM		 7456 schedule_work(&tp->reset_task);
7457 return;
7458 }
1da177e4
LT		 7459 }
7460
1da177e4
LT		 7461 /* This part only runs once per second. */
7462 if (!--tp->timer_counter) {
fac9b83e
DM		 7463 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7464 tg3_periodic_fetch_stats(tp);
7465
1da177e4
LT		 7466 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7467 u32 mac_stat;
7468 int phy_event;
7469
7470 mac_stat = tr32(MAC_STATUS);
7471
7472 phy_event = 0;
7473 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7474 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7475 phy_event = 1;
7476 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7477 phy_event = 1;
7478
7479 if (phy_event)
7480 tg3_setup_phy(tp, 0);
7481 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7482 u32 mac_stat = tr32(MAC_STATUS);
7483 int need_setup = 0;
7484
7485 if (netif_carrier_ok(tp->dev) &&
7486 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7487 need_setup = 1;
7488 }
7489 if (! netif_carrier_ok(tp->dev) &&
7490 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7491 MAC_STATUS_SIGNAL_DET))) {
7492 need_setup = 1;
7493 }
7494 if (need_setup) {
3d3ebe74
MC		 7495 if (!tp->serdes_counter) {
7496 tw32_f(MAC_MODE,
7497 (tp->mac_mode &
7498 ~MAC_MODE_PORT_MODE_MASK));
7499 udelay(40);
7500 tw32_f(MAC_MODE, tp->mac_mode);
7501 udelay(40);
7502 }
1da177e4
LT		 7503 tg3_setup_phy(tp, 0);
7504 }
747e8f8b
MC		 7505 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7506 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7507
7508 tp->timer_counter = tp->timer_multiplier;
7509 }
7510
130b8e4d
MC		 7511 /* Heartbeat is only sent once every 2 seconds.
7512 *
7513 * The heartbeat is to tell the ASF firmware that the host
7514 * driver is still alive. In the event that the OS crashes,
7515 * ASF needs to reset the hardware to free up the FIFO space
7516 * that may be filled with rx packets destined for the host.
7517 * If the FIFO is full, ASF will no longer function properly.
7518 *
7519 * Unintended resets have been reported on real time kernels
7520 * where the timer doesn't run on time. Netpoll will also have
7521 * same problem.
7522 *
7523 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7524 * to check the ring condition when the heartbeat is expiring
7525 * before doing the reset. This will prevent most unintended
7526 * resets.
7527 */
1da177e4 7528 if (!--tp->asf_counter) {
bc7959b2
MC		 7529 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7530 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7531 tg3_wait_for_event_ack(tp);
7532
bbadf503 7533 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7534 FWCMD_NICDRV_ALIVE3);
bbadf503 7535 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7536 /* 5 seconds timeout */
bbadf503 7537 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7538
7539 tg3_generate_fw_event(tp);
1da177e4
LT		 7540 }
7541 tp->asf_counter = tp->asf_multiplier;
7542 }
7543
f47c11ee 7544 spin_unlock(&tp->lock);
1da177e4 7545
f475f163 7546restart_timer:
1da177e4
LT		 7547 tp->timer.expires = jiffies + tp->timer_offset;
7548 add_timer(&tp->timer);
7549}
7550
81789ef5 7551static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7552{
7d12e780 7553 irq_handler_t fn;
fcfa0a32
MC		 7554 unsigned long flags;
7555 struct net_device *dev = tp->dev;
7556
7557 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7558 fn = tg3_msi;
7559 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7560 fn = tg3_msi_1shot;
1fb9df5d 7561 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7562 } else {
7563 fn = tg3_interrupt;
7564 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7565 fn = tg3_interrupt_tagged;
1fb9df5d 7566 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7567 }
7568 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7569}
7570
7938109f
MC		 7571static int tg3_test_interrupt(struct tg3 *tp)
7572{
7573 struct net_device *dev = tp->dev;
b16250e3 7574 int err, i, intr_ok = 0;
7938109f 7575
d4bc3927
MC		 7576 if (!netif_running(dev))
7577 return -ENODEV;
7578
7938109f
MC		 7579 tg3_disable_ints(tp);
7580
7581 free_irq(tp->pdev->irq, dev);
7582
7583 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7584 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7585 if (err)
7586 return err;
7587
38f3843e 7588 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7589 tg3_enable_ints(tp);
7590
7591 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7592 HOSTCC_MODE_NOW);
7593
7594 for (i = 0; i < 5; i++) {
b16250e3
MC		 7595 u32 int_mbox, misc_host_ctrl;
7596
09ee929c
MC		 7597 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7598 TG3_64BIT_REG_LOW);
b16250e3
MC		 7599 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7600
7601 if ((int_mbox != 0) ||
7602 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7603 intr_ok = 1;
7938109f 7604 break;
b16250e3
MC		 7605 }
7606
7938109f
MC		 7607 msleep(10);
7608 }
7609
7610 tg3_disable_ints(tp);
7611
7612 free_irq(tp->pdev->irq, dev);
6aa20a22 7613
fcfa0a32 7614 err = tg3_request_irq(tp);
7938109f
MC		 7615
7616 if (err)
7617 return err;
7618
b16250e3 7619 if (intr_ok)
7938109f
MC		 7620 return 0;
7621
7622 return -EIO;
7623}
7624
7625/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7626 * successfully restored
7627 */
7628static int tg3_test_msi(struct tg3 *tp)
7629{
7630 struct net_device *dev = tp->dev;
7631 int err;
7632 u16 pci_cmd;
7633
7634 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7635 return 0;
7636
7637 /* Turn off SERR reporting in case MSI terminates with Master
7638 * Abort.
7639 */
7640 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7641 pci_write_config_word(tp->pdev, PCI_COMMAND,
7642 pci_cmd & ~PCI_COMMAND_SERR);
7643
7644 err = tg3_test_interrupt(tp);
7645
7646 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7647
7648 if (!err)
7649 return 0;
7650
7651 /* other failures */
7652 if (err != -EIO)
7653 return err;
7654
7655 /* MSI test failed, go back to INTx mode */
7656 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7657 "switching to INTx mode. Please report this failure to "
7658 "the PCI maintainer and include system chipset information.\n",
7659 tp->dev->name);
7660
7661 free_irq(tp->pdev->irq, dev);
7662 pci_disable_msi(tp->pdev);
7663
7664 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7665
fcfa0a32 7666 err = tg3_request_irq(tp);
7938109f
MC		 7667 if (err)
7668 return err;
7669
7670 /* Need to reset the chip because the MSI cycle may have terminated
7671 * with Master Abort.
7672 */
f47c11ee 7673 tg3_full_lock(tp, 1);
7938109f 7674
944d980e 7675 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7676 err = tg3_init_hw(tp, 1);
7938109f 7677
f47c11ee 7678 tg3_full_unlock(tp);
7938109f
MC		 7679
7680 if (err)
7681 free_irq(tp->pdev->irq, dev);
7682
7683 return err;
7684}
7685
9e9fd12d
MC		 7686static int tg3_request_firmware(struct tg3 *tp)
7687{
7688 const __be32 *fw_data;
7689
7690 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7691 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7692 tp->dev->name, tp->fw_needed);
7693 return -ENOENT;
7694 }
7695
7696 fw_data = (void *)tp->fw->data;
7697
7698 /* Firmware blob starts with version numbers, followed by
7699 * start address and _full_ length including BSS sections
7700 * (which must be longer than the actual data, of course
7701 */
7702
7703 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7704 if (tp->fw_len < (tp->fw->size - 12)) {
7705 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7706 tp->dev->name, tp->fw_len, tp->fw_needed);
7707 release_firmware(tp->fw);
7708 tp->fw = NULL;
7709 return -EINVAL;
7710 }
7711
7712 /* We no longer need firmware; we have it. */
7713 tp->fw_needed = NULL;
7714 return 0;
7715}
7716
1da177e4
LT		 7717static int tg3_open(struct net_device *dev)
7718{
7719 struct tg3 *tp = netdev_priv(dev);
7720 int err;
7721
9e9fd12d
MC		 7722 if (tp->fw_needed) {
7723 err = tg3_request_firmware(tp);
7724 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7725 if (err)
7726 return err;
7727 } else if (err) {
7728 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7729 tp->dev->name);
7730 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7731 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7732 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7733 tp->dev->name);
7734 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7735 }
7736 }
7737
c49a1561
MC		 7738 netif_carrier_off(tp->dev);
7739
bc1c7567 7740 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7741 if (err)
bc1c7567 7742 return err;
2f751b67
MC		 7743
7744 tg3_full_lock(tp, 0);
bc1c7567 7745
1da177e4
LT		 7746 tg3_disable_ints(tp);
7747 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7748
f47c11ee 7749 tg3_full_unlock(tp);
1da177e4
LT		 7750
7751 /* The placement of this call is tied
7752 * to the setup and use of Host TX descriptors.
7753 */
7754 err = tg3_alloc_consistent(tp);
7755 if (err)
7756 return err;
7757
7544b097 7758 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7759 /* All MSI supporting chips should support tagged
7760 * status. Assert that this is the case.
7761 */
7762 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7763 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7764 "Not using MSI.\n", tp->dev->name);
7765 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7766 u32 msi_mode;
7767
7768 msi_mode = tr32(MSGINT_MODE);
7769 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7770 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7771 }
7772 }
fcfa0a32 7773 err = tg3_request_irq(tp);
1da177e4
LT		 7774
7775 if (err) {
88b06bc2
MC		 7776 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7777 pci_disable_msi(tp->pdev);
7778 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7779 }
1da177e4
LT		 7780 tg3_free_consistent(tp);
7781 return err;
7782 }
7783
bea3348e
SH		 7784 napi_enable(&tp->napi);
7785
f47c11ee 7786 tg3_full_lock(tp, 0);
1da177e4 7787
8e7a22e3 7788 err = tg3_init_hw(tp, 1);
1da177e4 7789 if (err) {
944d980e 7790 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7791 tg3_free_rings(tp);
7792 } else {
fac9b83e
DM		 7793 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7794 tp->timer_offset = HZ;
7795 else
7796 tp->timer_offset = HZ / 10;
7797
7798 BUG_ON(tp->timer_offset > HZ);
7799 tp->timer_counter = tp->timer_multiplier =
7800 (HZ / tp->timer_offset);
7801 tp->asf_counter = tp->asf_multiplier =
28fbef78 7802 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7803
7804 init_timer(&tp->timer);
7805 tp->timer.expires = jiffies + tp->timer_offset;
7806 tp->timer.data = (unsigned long) tp;
7807 tp->timer.function = tg3_timer;
1da177e4
LT		 7808 }
7809
f47c11ee 7810 tg3_full_unlock(tp);
1da177e4
LT		 7811
7812 if (err) {
bea3348e 7813 napi_disable(&tp->napi);
88b06bc2
MC		 7814 free_irq(tp->pdev->irq, dev);
7815 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7816 pci_disable_msi(tp->pdev);
7817 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7818 }
1da177e4
LT		 7819 tg3_free_consistent(tp);
7820 return err;
7821 }
7822
7938109f
MC		 7823 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7824 err = tg3_test_msi(tp);
fac9b83e 7825
7938109f 7826 if (err) {
f47c11ee 7827 tg3_full_lock(tp, 0);
7938109f
MC		 7828
7829 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7830 pci_disable_msi(tp->pdev);
7831 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7832 }
944d980e 7833 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7834 tg3_free_rings(tp);
7835 tg3_free_consistent(tp);
7836
f47c11ee 7837 tg3_full_unlock(tp);
7938109f 7838
bea3348e
SH		 7839 napi_disable(&tp->napi);
7840
7938109f
MC		 7841 return err;
7842 }
fcfa0a32
MC		 7843
7844 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7845 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7846 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7847
b5d3772c
MC		 7848 tw32(PCIE_TRANSACTION_CFG,
7849 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7850 }
7851 }
7938109f
MC		 7852 }
7853
b02fd9e3
MC		 7854 tg3_phy_start(tp);
7855
f47c11ee 7856 tg3_full_lock(tp, 0);
1da177e4 7857
7938109f
MC		 7858 add_timer(&tp->timer);
7859 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7860 tg3_enable_ints(tp);
7861
f47c11ee 7862 tg3_full_unlock(tp);
1da177e4
LT		 7863
7864 netif_start_queue(dev);
7865
7866 return 0;
7867}
7868
7869#if 0
7870/*static*/ void tg3_dump_state(struct tg3 *tp)
7871{
7872 u32 val32, val32_2, val32_3, val32_4, val32_5;
7873 u16 val16;
7874 int i;
7875
7876 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7877 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7878 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7879 val16, val32);
7880
7881 /* MAC block */
7882 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7883 tr32(MAC_MODE), tr32(MAC_STATUS));
7884 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7885 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7886 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7887 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7888 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7889 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7890
7891 /* Send data initiator control block */
7892 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7893 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7894 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7895 tr32(SNDDATAI_STATSCTRL));
7896
7897 /* Send data completion control block */
7898 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7899
7900 /* Send BD ring selector block */
7901 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7902 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7903
7904 /* Send BD initiator control block */
7905 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7906 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7907
7908 /* Send BD completion control block */
7909 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7910
7911 /* Receive list placement control block */
7912 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7913 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7914 printk(" RCVLPC_STATSCTRL[%08x]\n",
7915 tr32(RCVLPC_STATSCTRL));
7916
7917 /* Receive data and receive BD initiator control block */
7918 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7919 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7920
7921 /* Receive data completion control block */
7922 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7923 tr32(RCVDCC_MODE));
7924
7925 /* Receive BD initiator control block */
7926 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7927 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7928
7929 /* Receive BD completion control block */
7930 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7931 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7932
7933 /* Receive list selector control block */
7934 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7935 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7936
7937 /* Mbuf cluster free block */
7938 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7939 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7940
7941 /* Host coalescing control block */
7942 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7943 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7944 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7945 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7946 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7947 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7948 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7949 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7950 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7951 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7952 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7953 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7954
7955 /* Memory arbiter control block */
7956 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7957 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7958
7959 /* Buffer manager control block */
7960 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7961 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7962 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7963 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7964 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7965 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7966 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7967 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7968
7969 /* Read DMA control block */
7970 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7971 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7972
7973 /* Write DMA control block */
7974 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7975 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7976
7977 /* DMA completion block */
7978 printk("DEBUG: DMAC_MODE[%08x]\n",
7979 tr32(DMAC_MODE));
7980
7981 /* GRC block */
7982 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7983 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7984 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7985 tr32(GRC_LOCAL_CTRL));
7986
7987 /* TG3_BDINFOs */
7988 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7989 tr32(RCVDBDI_JUMBO_BD + 0x0),
7990 tr32(RCVDBDI_JUMBO_BD + 0x4),
7991 tr32(RCVDBDI_JUMBO_BD + 0x8),
7992 tr32(RCVDBDI_JUMBO_BD + 0xc));
7993 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7994 tr32(RCVDBDI_STD_BD + 0x0),
7995 tr32(RCVDBDI_STD_BD + 0x4),
7996 tr32(RCVDBDI_STD_BD + 0x8),
7997 tr32(RCVDBDI_STD_BD + 0xc));
7998 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7999 tr32(RCVDBDI_MINI_BD + 0x0),
8000 tr32(RCVDBDI_MINI_BD + 0x4),
8001 tr32(RCVDBDI_MINI_BD + 0x8),
8002 tr32(RCVDBDI_MINI_BD + 0xc));
8003
8004 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8005 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8006 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8007 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8008 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8009 val32, val32_2, val32_3, val32_4);
8010
8011 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8012 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8013 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8014 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8015 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8016 val32, val32_2, val32_3, val32_4);
8017
8018 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8019 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8020 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8021 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8022 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8023 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8024 val32, val32_2, val32_3, val32_4, val32_5);
8025
8026 /* SW status block */
8027 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8028 tp->hw_status->status,
8029 tp->hw_status->status_tag,
8030 tp->hw_status->rx_jumbo_consumer,
8031 tp->hw_status->rx_consumer,
8032 tp->hw_status->rx_mini_consumer,
8033 tp->hw_status->idx[0].rx_producer,
8034 tp->hw_status->idx[0].tx_consumer);
8035
8036 /* SW statistics block */
8037 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8038 ((u32 *)tp->hw_stats)[0],
8039 ((u32 *)tp->hw_stats)[1],
8040 ((u32 *)tp->hw_stats)[2],
8041 ((u32 *)tp->hw_stats)[3]);
8042
8043 /* Mailboxes */
8044 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8045 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8046 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8047 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8048 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8049
8050 /* NIC side send descriptors. */
8051 for (i = 0; i < 6; i++) {
8052 unsigned long txd;
8053
8054 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8055 + (i * sizeof(struct tg3_tx_buffer_desc));
8056 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8057 i,
8058 readl(txd + 0x0), readl(txd + 0x4),
8059 readl(txd + 0x8), readl(txd + 0xc));
8060 }
8061
8062 /* NIC side RX descriptors. */
8063 for (i = 0; i < 6; i++) {
8064 unsigned long rxd;
8065
8066 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8067 + (i * sizeof(struct tg3_rx_buffer_desc));
8068 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8069 i,
8070 readl(rxd + 0x0), readl(rxd + 0x4),
8071 readl(rxd + 0x8), readl(rxd + 0xc));
8072 rxd += (4 * sizeof(u32));
8073 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8074 i,
8075 readl(rxd + 0x0), readl(rxd + 0x4),
8076 readl(rxd + 0x8), readl(rxd + 0xc));
8077 }
8078
8079 for (i = 0; i < 6; i++) {
8080 unsigned long rxd;
8081
8082 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8083 + (i * sizeof(struct tg3_rx_buffer_desc));
8084 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8085 i,
8086 readl(rxd + 0x0), readl(rxd + 0x4),
8087 readl(rxd + 0x8), readl(rxd + 0xc));
8088 rxd += (4 * sizeof(u32));
8089 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8090 i,
8091 readl(rxd + 0x0), readl(rxd + 0x4),
8092 readl(rxd + 0x8), readl(rxd + 0xc));
8093 }
8094}
8095#endif
8096
8097static struct net_device_stats *tg3_get_stats(struct net_device *);
8098static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8099
8100static int tg3_close(struct net_device *dev)
8101{
8102 struct tg3 *tp = netdev_priv(dev);
8103
bea3348e 8104 napi_disable(&tp->napi);
28e53bdd 8105 cancel_work_sync(&tp->reset_task);
7faa006f 8106
1da177e4
LT		 8107 netif_stop_queue(dev);
8108
8109 del_timer_sync(&tp->timer);
8110
f47c11ee 8111 tg3_full_lock(tp, 1);
1da177e4
LT		 8112#if 0
8113 tg3_dump_state(tp);
8114#endif
8115
8116 tg3_disable_ints(tp);
8117
944d980e 8118 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8119 tg3_free_rings(tp);
5cf64b8a 8120 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8121
f47c11ee 8122 tg3_full_unlock(tp);
1da177e4 8123
88b06bc2
MC		 8124 free_irq(tp->pdev->irq, dev);
8125 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8126 pci_disable_msi(tp->pdev);
8127 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8128 }
1da177e4
LT		 8129
8130 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8131 sizeof(tp->net_stats_prev));
8132 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8133 sizeof(tp->estats_prev));
8134
8135 tg3_free_consistent(tp);
8136
bc1c7567
MC		 8137 tg3_set_power_state(tp, PCI_D3hot);
8138
8139 netif_carrier_off(tp->dev);
8140
1da177e4
LT		 8141 return 0;
8142}
8143
8144static inline unsigned long get_stat64(tg3_stat64_t *val)
8145{
8146 unsigned long ret;
8147
8148#if (BITS_PER_LONG == 32)
8149 ret = val->low;
8150#else
8151 ret = ((u64)val->high << 32) | ((u64)val->low);
8152#endif
8153 return ret;
8154}
8155
816f8b86
SB		 8156static inline u64 get_estat64(tg3_stat64_t *val)
8157{
8158 return ((u64)val->high << 32) | ((u64)val->low);
8159}
8160
1da177e4
LT		 8161static unsigned long calc_crc_errors(struct tg3 *tp)
8162{
8163 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8164
8165 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8166 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8167 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8168 u32 val;
8169
f47c11ee 8170 spin_lock_bh(&tp->lock);
569a5df8
MC		 8171 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8172 tg3_writephy(tp, MII_TG3_TEST1,
8173 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8174 tg3_readphy(tp, 0x14, &val);
8175 } else
8176 val = 0;
f47c11ee 8177 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8178
8179 tp->phy_crc_errors += val;
8180
8181 return tp->phy_crc_errors;
8182 }
8183
8184 return get_stat64(&hw_stats->rx_fcs_errors);
8185}
8186
8187#define ESTAT_ADD(member) \
8188 estats->member = old_estats->member + \
816f8b86 8189 get_estat64(&hw_stats->member)
1da177e4
LT		 8190
8191static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8192{
8193 struct tg3_ethtool_stats *estats = &tp->estats;
8194 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8195 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8196
8197 if (!hw_stats)
8198 return old_estats;
8199
8200 ESTAT_ADD(rx_octets);
8201 ESTAT_ADD(rx_fragments);
8202 ESTAT_ADD(rx_ucast_packets);
8203 ESTAT_ADD(rx_mcast_packets);
8204 ESTAT_ADD(rx_bcast_packets);
8205 ESTAT_ADD(rx_fcs_errors);
8206 ESTAT_ADD(rx_align_errors);
8207 ESTAT_ADD(rx_xon_pause_rcvd);
8208 ESTAT_ADD(rx_xoff_pause_rcvd);
8209 ESTAT_ADD(rx_mac_ctrl_rcvd);
8210 ESTAT_ADD(rx_xoff_entered);
8211 ESTAT_ADD(rx_frame_too_long_errors);
8212 ESTAT_ADD(rx_jabbers);
8213 ESTAT_ADD(rx_undersize_packets);
8214 ESTAT_ADD(rx_in_length_errors);
8215 ESTAT_ADD(rx_out_length_errors);
8216 ESTAT_ADD(rx_64_or_less_octet_packets);
8217 ESTAT_ADD(rx_65_to_127_octet_packets);
8218 ESTAT_ADD(rx_128_to_255_octet_packets);
8219 ESTAT_ADD(rx_256_to_511_octet_packets);
8220 ESTAT_ADD(rx_512_to_1023_octet_packets);
8221 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8222 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8223 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8224 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8225 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8226
8227 ESTAT_ADD(tx_octets);
8228 ESTAT_ADD(tx_collisions);
8229 ESTAT_ADD(tx_xon_sent);
8230 ESTAT_ADD(tx_xoff_sent);
8231 ESTAT_ADD(tx_flow_control);
8232 ESTAT_ADD(tx_mac_errors);
8233 ESTAT_ADD(tx_single_collisions);
8234 ESTAT_ADD(tx_mult_collisions);
8235 ESTAT_ADD(tx_deferred);
8236 ESTAT_ADD(tx_excessive_collisions);
8237 ESTAT_ADD(tx_late_collisions);
8238 ESTAT_ADD(tx_collide_2times);
8239 ESTAT_ADD(tx_collide_3times);
8240 ESTAT_ADD(tx_collide_4times);
8241 ESTAT_ADD(tx_collide_5times);
8242 ESTAT_ADD(tx_collide_6times);
8243 ESTAT_ADD(tx_collide_7times);
8244 ESTAT_ADD(tx_collide_8times);
8245 ESTAT_ADD(tx_collide_9times);
8246 ESTAT_ADD(tx_collide_10times);
8247 ESTAT_ADD(tx_collide_11times);
8248 ESTAT_ADD(tx_collide_12times);
8249 ESTAT_ADD(tx_collide_13times);
8250 ESTAT_ADD(tx_collide_14times);
8251 ESTAT_ADD(tx_collide_15times);
8252 ESTAT_ADD(tx_ucast_packets);
8253 ESTAT_ADD(tx_mcast_packets);
8254 ESTAT_ADD(tx_bcast_packets);
8255 ESTAT_ADD(tx_carrier_sense_errors);
8256 ESTAT_ADD(tx_discards);
8257 ESTAT_ADD(tx_errors);
8258
8259 ESTAT_ADD(dma_writeq_full);
8260 ESTAT_ADD(dma_write_prioq_full);
8261 ESTAT_ADD(rxbds_empty);
8262 ESTAT_ADD(rx_discards);
8263 ESTAT_ADD(rx_errors);
8264 ESTAT_ADD(rx_threshold_hit);
8265
8266 ESTAT_ADD(dma_readq_full);
8267 ESTAT_ADD(dma_read_prioq_full);
8268 ESTAT_ADD(tx_comp_queue_full);
8269
8270 ESTAT_ADD(ring_set_send_prod_index);
8271 ESTAT_ADD(ring_status_update);
8272 ESTAT_ADD(nic_irqs);
8273 ESTAT_ADD(nic_avoided_irqs);
8274 ESTAT_ADD(nic_tx_threshold_hit);
8275
8276 return estats;
8277}
8278
8279static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8280{
8281 struct tg3 *tp = netdev_priv(dev);
8282 struct net_device_stats *stats = &tp->net_stats;
8283 struct net_device_stats *old_stats = &tp->net_stats_prev;
8284 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8285
8286 if (!hw_stats)
8287 return old_stats;
8288
8289 stats->rx_packets = old_stats->rx_packets +
8290 get_stat64(&hw_stats->rx_ucast_packets) +
8291 get_stat64(&hw_stats->rx_mcast_packets) +
8292 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8293
1da177e4
LT		 8294 stats->tx_packets = old_stats->tx_packets +
8295 get_stat64(&hw_stats->tx_ucast_packets) +
8296 get_stat64(&hw_stats->tx_mcast_packets) +
8297 get_stat64(&hw_stats->tx_bcast_packets);
8298
8299 stats->rx_bytes = old_stats->rx_bytes +
8300 get_stat64(&hw_stats->rx_octets);
8301 stats->tx_bytes = old_stats->tx_bytes +
8302 get_stat64(&hw_stats->tx_octets);
8303
8304 stats->rx_errors = old_stats->rx_errors +
4f63b877 8305 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8306 stats->tx_errors = old_stats->tx_errors +
8307 get_stat64(&hw_stats->tx_errors) +
8308 get_stat64(&hw_stats->tx_mac_errors) +
8309 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8310 get_stat64(&hw_stats->tx_discards);
8311
8312 stats->multicast = old_stats->multicast +
8313 get_stat64(&hw_stats->rx_mcast_packets);
8314 stats->collisions = old_stats->collisions +
8315 get_stat64(&hw_stats->tx_collisions);
8316
8317 stats->rx_length_errors = old_stats->rx_length_errors +
8318 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8319 get_stat64(&hw_stats->rx_undersize_packets);
8320
8321 stats->rx_over_errors = old_stats->rx_over_errors +
8322 get_stat64(&hw_stats->rxbds_empty);
8323 stats->rx_frame_errors = old_stats->rx_frame_errors +
8324 get_stat64(&hw_stats->rx_align_errors);
8325 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8326 get_stat64(&hw_stats->tx_discards);
8327 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8328 get_stat64(&hw_stats->tx_carrier_sense_errors);
8329
8330 stats->rx_crc_errors = old_stats->rx_crc_errors +
8331 calc_crc_errors(tp);
8332
4f63b877
JL		 8333 stats->rx_missed_errors = old_stats->rx_missed_errors +
8334 get_stat64(&hw_stats->rx_discards);
8335
1da177e4
LT		 8336 return stats;
8337}
8338
8339static inline u32 calc_crc(unsigned char *buf, int len)
8340{
8341 u32 reg;
8342 u32 tmp;
8343 int j, k;
8344
8345 reg = 0xffffffff;
8346
8347 for (j = 0; j < len; j++) {
8348 reg ^= buf[j];
8349
8350 for (k = 0; k < 8; k++) {
8351 tmp = reg & 0x01;
8352
8353 reg >>= 1;
8354
8355 if (tmp) {
8356 reg ^= 0xedb88320;
8357 }
8358 }
8359 }
8360
8361 return ~reg;
8362}
8363
8364static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8365{
8366 /* accept or reject all multicast frames */
8367 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8368 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8369 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8370 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8371}
8372
8373static void __tg3_set_rx_mode(struct net_device *dev)
8374{
8375 struct tg3 *tp = netdev_priv(dev);
8376 u32 rx_mode;
8377
8378 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8379 RX_MODE_KEEP_VLAN_TAG);
8380
8381 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8382 * flag clear.
8383 */
8384#if TG3_VLAN_TAG_USED
8385 if (!tp->vlgrp &&
8386 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8387 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8388#else
8389 /* By definition, VLAN is disabled always in this
8390 * case.
8391 */
8392 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8393 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8394#endif
8395
8396 if (dev->flags & IFF_PROMISC) {
8397 /* Promiscuous mode. */
8398 rx_mode |= RX_MODE_PROMISC;
8399 } else if (dev->flags & IFF_ALLMULTI) {
8400 /* Accept all multicast. */
8401 tg3_set_multi (tp, 1);
8402 } else if (dev->mc_count < 1) {
8403 /* Reject all multicast. */
8404 tg3_set_multi (tp, 0);
8405 } else {
8406 /* Accept one or more multicast(s). */
8407 struct dev_mc_list *mclist;
8408 unsigned int i;
8409 u32 mc_filter[4] = { 0, };
8410 u32 regidx;
8411 u32 bit;
8412 u32 crc;
8413
8414 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8415 i++, mclist = mclist->next) {
8416
8417 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8418 bit = ~crc & 0x7f;
8419 regidx = (bit & 0x60) >> 5;
8420 bit &= 0x1f;
8421 mc_filter[regidx] |= (1 << bit);
8422 }
8423
8424 tw32(MAC_HASH_REG_0, mc_filter[0]);
8425 tw32(MAC_HASH_REG_1, mc_filter[1]);
8426 tw32(MAC_HASH_REG_2, mc_filter[2]);
8427 tw32(MAC_HASH_REG_3, mc_filter[3]);
8428 }
8429
8430 if (rx_mode != tp->rx_mode) {
8431 tp->rx_mode = rx_mode;
8432 tw32_f(MAC_RX_MODE, rx_mode);
8433 udelay(10);
8434 }
8435}
8436
8437static void tg3_set_rx_mode(struct net_device *dev)
8438{
8439 struct tg3 *tp = netdev_priv(dev);
8440
e75f7c90
MC		 8441 if (!netif_running(dev))
8442 return;
8443
f47c11ee 8444 tg3_full_lock(tp, 0);
1da177e4 8445 __tg3_set_rx_mode(dev);
f47c11ee 8446 tg3_full_unlock(tp);
1da177e4
LT		 8447}
8448
8449#define TG3_REGDUMP_LEN (32 * 1024)
8450
8451static int tg3_get_regs_len(struct net_device *dev)
8452{
8453 return TG3_REGDUMP_LEN;
8454}
8455
8456static void tg3_get_regs(struct net_device *dev,
8457 struct ethtool_regs *regs, void *_p)
8458{
8459 u32 *p = _p;
8460 struct tg3 *tp = netdev_priv(dev);
8461 u8 *orig_p = _p;
8462 int i;
8463
8464 regs->version = 0;
8465
8466 memset(p, 0, TG3_REGDUMP_LEN);
8467
bc1c7567
MC		 8468 if (tp->link_config.phy_is_low_power)
8469 return;
8470
f47c11ee 8471 tg3_full_lock(tp, 0);
1da177e4
LT		 8472
8473#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8474#define GET_REG32_LOOP(base,len) \
8475do { p = (u32 *)(orig_p + (base)); \
8476 for (i = 0; i < len; i += 4) \
8477 __GET_REG32((base) + i); \
8478} while (0)
8479#define GET_REG32_1(reg) \
8480do { p = (u32 *)(orig_p + (reg)); \
8481 __GET_REG32((reg)); \
8482} while (0)
8483
8484 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8485 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8486 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8487 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8488 GET_REG32_1(SNDDATAC_MODE);
8489 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8490 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8491 GET_REG32_1(SNDBDC_MODE);
8492 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8493 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8494 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8495 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8496 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8497 GET_REG32_1(RCVDCC_MODE);
8498 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8499 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8500 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8501 GET_REG32_1(MBFREE_MODE);
8502 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8503 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8504 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8505 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8506 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8507 GET_REG32_1(RX_CPU_MODE);
8508 GET_REG32_1(RX_CPU_STATE);
8509 GET_REG32_1(RX_CPU_PGMCTR);
8510 GET_REG32_1(RX_CPU_HWBKPT);
8511 GET_REG32_1(TX_CPU_MODE);
8512 GET_REG32_1(TX_CPU_STATE);
8513 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8514 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8515 GET_REG32_LOOP(FTQ_RESET, 0x120);
8516 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8517 GET_REG32_1(DMAC_MODE);
8518 GET_REG32_LOOP(GRC_MODE, 0x4c);
8519 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8520 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8521
8522#undef __GET_REG32
8523#undef GET_REG32_LOOP
8524#undef GET_REG32_1
8525
f47c11ee 8526 tg3_full_unlock(tp);
1da177e4
LT		 8527}
8528
8529static int tg3_get_eeprom_len(struct net_device *dev)
8530{
8531 struct tg3 *tp = netdev_priv(dev);
8532
8533 return tp->nvram_size;
8534}
8535
1da177e4
LT		 8536static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8537{
8538 struct tg3 *tp = netdev_priv(dev);
8539 int ret;
8540 u8 *pd;
b9fc7dc5
AV		 8541 u32 i, offset, len, b_offset, b_count;
8542 __le32 val;
1da177e4 8543
bc1c7567
MC		 8544 if (tp->link_config.phy_is_low_power)
8545 return -EAGAIN;
8546
1da177e4
LT		 8547 offset = eeprom->offset;
8548 len = eeprom->len;
8549 eeprom->len = 0;
8550
8551 eeprom->magic = TG3_EEPROM_MAGIC;
8552
8553 if (offset & 3) {
8554 /* adjustments to start on required 4 byte boundary */
8555 b_offset = offset & 3;
8556 b_count = 4 - b_offset;
8557 if (b_count > len) {
8558 /* i.e. offset=1 len=2 */
8559 b_count = len;
8560 }
b9fc7dc5 8561 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
1da177e4
LT		 8562 if (ret)
8563 return ret;
1da177e4
LT		 8564 memcpy(data, ((char*)&val) + b_offset, b_count);
8565 len -= b_count;
8566 offset += b_count;
8567 eeprom->len += b_count;
8568 }
8569
8570 /* read bytes upto the last 4 byte boundary */
8571 pd = &data[eeprom->len];
8572 for (i = 0; i < (len - (len & 3)); i += 4) {
b9fc7dc5 8573 ret = tg3_nvram_read_le(tp, offset + i, &val);
1da177e4
LT		 8574 if (ret) {
8575 eeprom->len += i;
8576 return ret;
8577 }
1da177e4
LT		 8578 memcpy(pd + i, &val, 4);
8579 }
8580 eeprom->len += i;
8581
8582 if (len & 3) {
8583 /* read last bytes not ending on 4 byte boundary */
8584 pd = &data[eeprom->len];
8585 b_count = len & 3;
8586 b_offset = offset + len - b_count;
b9fc7dc5 8587 ret = tg3_nvram_read_le(tp, b_offset, &val);
1da177e4
LT		 8588 if (ret)
8589 return ret;
b9fc7dc5 8590 memcpy(pd, &val, b_count);
1da177e4
LT		 8591 eeprom->len += b_count;
8592 }
8593 return 0;
8594}
8595
6aa20a22 8596static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8597
8598static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8599{
8600 struct tg3 *tp = netdev_priv(dev);
8601 int ret;
b9fc7dc5 8602 u32 offset, len, b_offset, odd_len;
1da177e4 8603 u8 *buf;
b9fc7dc5 8604 __le32 start, end;
1da177e4 8605
bc1c7567
MC		 8606 if (tp->link_config.phy_is_low_power)
8607 return -EAGAIN;
8608
1da177e4
LT		 8609 if (eeprom->magic != TG3_EEPROM_MAGIC)
8610 return -EINVAL;
8611
8612 offset = eeprom->offset;
8613 len = eeprom->len;
8614
8615 if ((b_offset = (offset & 3))) {
8616 /* adjustments to start on required 4 byte boundary */
b9fc7dc5 8617 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
1da177e4
LT		 8618 if (ret)
8619 return ret;
1da177e4
LT		 8620 len += b_offset;
8621 offset &= ~3;
1c8594b4
MC		 8622 if (len < 4)
8623 len = 4;
1da177e4
LT		 8624 }
8625
8626 odd_len = 0;
1c8594b4 8627 if (len & 3) {
1da177e4
LT		 8628 /* adjustments to end on required 4 byte boundary */
8629 odd_len = 1;
8630 len = (len + 3) & ~3;
b9fc7dc5 8631 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
1da177e4
LT		 8632 if (ret)
8633 return ret;
1da177e4
LT		 8634 }
8635
8636 buf = data;
8637 if (b_offset || odd_len) {
8638 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8639 if (!buf)
1da177e4
LT		 8640 return -ENOMEM;
8641 if (b_offset)
8642 memcpy(buf, &start, 4);
8643 if (odd_len)
8644 memcpy(buf+len-4, &end, 4);
8645 memcpy(buf + b_offset, data, eeprom->len);
8646 }
8647
8648 ret = tg3_nvram_write_block(tp, offset, len, buf);
8649
8650 if (buf != data)
8651 kfree(buf);
8652
8653 return ret;
8654}
8655
8656static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8657{
b02fd9e3
MC		 8658 struct tg3 *tp = netdev_priv(dev);
8659
8660 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8661 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8662 return -EAGAIN;
298cf9be 8663 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8664 }
6aa20a22 8665
1da177e4
LT		 8666 cmd->supported = (SUPPORTED_Autoneg);
8667
8668 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8669 cmd->supported |= (SUPPORTED_1000baseT_Half |
8670 SUPPORTED_1000baseT_Full);
8671
ef348144 8672 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8673 cmd->supported |= (SUPPORTED_100baseT_Half |
8674 SUPPORTED_100baseT_Full |
8675 SUPPORTED_10baseT_Half |
8676 SUPPORTED_10baseT_Full |
3bebab59 8677 SUPPORTED_TP);
ef348144
KK		 8678 cmd->port = PORT_TP;
8679 } else {
1da177e4 8680 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8681 cmd->port = PORT_FIBRE;
8682 }
6aa20a22 8683
1da177e4
LT		 8684 cmd->advertising = tp->link_config.advertising;
8685 if (netif_running(dev)) {
8686 cmd->speed = tp->link_config.active_speed;
8687 cmd->duplex = tp->link_config.active_duplex;
8688 }
1da177e4 8689 cmd->phy_address = PHY_ADDR;
7e5856bd 8690 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8691 cmd->autoneg = tp->link_config.autoneg;
8692 cmd->maxtxpkt = 0;
8693 cmd->maxrxpkt = 0;
8694 return 0;
8695}
6aa20a22 8696
1da177e4
LT		 8697static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8698{
8699 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8700
b02fd9e3
MC		 8701 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8702 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8703 return -EAGAIN;
298cf9be 8704 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8705 }
8706
7e5856bd
MC		 8707 if (cmd->autoneg != AUTONEG_ENABLE &&
8708 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8709 return -EINVAL;
7e5856bd
MC		 8710
8711 if (cmd->autoneg == AUTONEG_DISABLE &&
8712 cmd->duplex != DUPLEX_FULL &&
8713 cmd->duplex != DUPLEX_HALF)
37ff238d 8714 return -EINVAL;
1da177e4 8715
7e5856bd
MC		 8716 if (cmd->autoneg == AUTONEG_ENABLE) {
8717 u32 mask = ADVERTISED_Autoneg |
8718 ADVERTISED_Pause |
8719 ADVERTISED_Asym_Pause;
8720
8721 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8722 mask |= ADVERTISED_1000baseT_Half |
8723 ADVERTISED_1000baseT_Full;
8724
8725 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8726 mask |= ADVERTISED_100baseT_Half |
8727 ADVERTISED_100baseT_Full |
8728 ADVERTISED_10baseT_Half |
8729 ADVERTISED_10baseT_Full |
8730 ADVERTISED_TP;
8731 else
8732 mask |= ADVERTISED_FIBRE;
8733
8734 if (cmd->advertising & ~mask)
8735 return -EINVAL;
8736
8737 mask &= (ADVERTISED_1000baseT_Half |
8738 ADVERTISED_1000baseT_Full |
8739 ADVERTISED_100baseT_Half |
8740 ADVERTISED_100baseT_Full |
8741 ADVERTISED_10baseT_Half |
8742 ADVERTISED_10baseT_Full);
8743
8744 cmd->advertising &= mask;
8745 } else {
8746 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8747 if (cmd->speed != SPEED_1000)
8748 return -EINVAL;
8749
8750 if (cmd->duplex != DUPLEX_FULL)
8751 return -EINVAL;
8752 } else {
8753 if (cmd->speed != SPEED_100 &&
8754 cmd->speed != SPEED_10)
8755 return -EINVAL;
8756 }
8757 }
8758
f47c11ee 8759 tg3_full_lock(tp, 0);
1da177e4
LT		 8760
8761 tp->link_config.autoneg = cmd->autoneg;
8762 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8763 tp->link_config.advertising = (cmd->advertising |
8764 ADVERTISED_Autoneg);
1da177e4
LT		 8765 tp->link_config.speed = SPEED_INVALID;
8766 tp->link_config.duplex = DUPLEX_INVALID;
8767 } else {
8768 tp->link_config.advertising = 0;
8769 tp->link_config.speed = cmd->speed;
8770 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8771 }
6aa20a22 8772
24fcad6b
MC		 8773 tp->link_config.orig_speed = tp->link_config.speed;
8774 tp->link_config.orig_duplex = tp->link_config.duplex;
8775 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8776
1da177e4
LT		 8777 if (netif_running(dev))
8778 tg3_setup_phy(tp, 1);
8779
f47c11ee 8780 tg3_full_unlock(tp);
6aa20a22 8781
1da177e4
LT		 8782 return 0;
8783}
6aa20a22 8784
1da177e4
LT		 8785static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8786{
8787 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8788
1da177e4
LT		 8789 strcpy(info->driver, DRV_MODULE_NAME);
8790 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8791 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8792 strcpy(info->bus_info, pci_name(tp->pdev));
8793}
6aa20a22 8794
1da177e4
LT		 8795static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8796{
8797 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8798
12dac075
RW		 8799 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8800 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8801 wol->supported = WAKE_MAGIC;
8802 else
8803 wol->supported = 0;
1da177e4 8804 wol->wolopts = 0;
05ac4cb7
MC		 8805 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8806 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8807 wol->wolopts = WAKE_MAGIC;
8808 memset(&wol->sopass, 0, sizeof(wol->sopass));
8809}
6aa20a22 8810
1da177e4
LT		 8811static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8812{
8813 struct tg3 *tp = netdev_priv(dev);
12dac075 8814 struct device *dp = &tp->pdev->dev;
6aa20a22 8815
1da177e4
LT		 8816 if (wol->wolopts & ~WAKE_MAGIC)
8817 return -EINVAL;
8818 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8819 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8820 return -EINVAL;
6aa20a22 8821
f47c11ee 8822 spin_lock_bh(&tp->lock);
12dac075 8823 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8824 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8825 device_set_wakeup_enable(dp, true);
8826 } else {
1da177e4 8827 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8828 device_set_wakeup_enable(dp, false);
8829 }
f47c11ee 8830 spin_unlock_bh(&tp->lock);
6aa20a22 8831
1da177e4
LT		 8832 return 0;
8833}
6aa20a22 8834
1da177e4
LT		 8835static u32 tg3_get_msglevel(struct net_device *dev)
8836{
8837 struct tg3 *tp = netdev_priv(dev);
8838 return tp->msg_enable;
8839}
6aa20a22 8840
1da177e4
LT		 8841static void tg3_set_msglevel(struct net_device *dev, u32 value)
8842{
8843 struct tg3 *tp = netdev_priv(dev);
8844 tp->msg_enable = value;
8845}
6aa20a22 8846
1da177e4
LT		 8847static int tg3_set_tso(struct net_device *dev, u32 value)
8848{
8849 struct tg3 *tp = netdev_priv(dev);
8850
8851 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8852 if (value)
8853 return -EINVAL;
8854 return 0;
8855 }
027455ad
MC		 8856 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8857 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8858 if (value) {
b0026624 8859 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8861 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8862 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8863 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8865 dev->features |= NETIF_F_TSO_ECN;
8866 } else
8867 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8868 }
1da177e4
LT		 8869 return ethtool_op_set_tso(dev, value);
8870}
6aa20a22 8871
1da177e4
LT		 8872static int tg3_nway_reset(struct net_device *dev)
8873{
8874 struct tg3 *tp = netdev_priv(dev);
1da177e4 8875 int r;
6aa20a22 8876
1da177e4
LT		 8877 if (!netif_running(dev))
8878 return -EAGAIN;
8879
c94e3941
MC		 8880 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8881 return -EINVAL;
8882
b02fd9e3
MC		 8883 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8884 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8885 return -EAGAIN;
298cf9be 8886 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8887 } else {
8888 u32 bmcr;
8889
8890 spin_lock_bh(&tp->lock);
8891 r = -EINVAL;
8892 tg3_readphy(tp, MII_BMCR, &bmcr);
8893 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8894 ((bmcr & BMCR_ANENABLE) ||
8895 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8896 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8897 BMCR_ANENABLE);
8898 r = 0;
8899 }
8900 spin_unlock_bh(&tp->lock);
1da177e4 8901 }
6aa20a22 8902
1da177e4
LT		 8903 return r;
8904}
6aa20a22 8905
1da177e4
LT		 8906static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8907{
8908 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8909
1da177e4
LT		 8910 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8911 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8912 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8913 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8914 else
8915 ering->rx_jumbo_max_pending = 0;
8916
8917 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8918
8919 ering->rx_pending = tp->rx_pending;
8920 ering->rx_mini_pending = 0;
4f81c32b
MC		 8921 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8922 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8923 else
8924 ering->rx_jumbo_pending = 0;
8925
1da177e4
LT		 8926 ering->tx_pending = tp->tx_pending;
8927}
6aa20a22 8928
1da177e4
LT		 8929static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8930{
8931 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8932 int irq_sync = 0, err = 0;
6aa20a22 8933
1da177e4
LT		 8934 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8935 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8936 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8937 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8938 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8939 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8940 return -EINVAL;
6aa20a22 8941
bbe832c0 8942 if (netif_running(dev)) {
b02fd9e3 8943 tg3_phy_stop(tp);
1da177e4 8944 tg3_netif_stop(tp);
bbe832c0
MC		 8945 irq_sync = 1;
8946 }
1da177e4 8947
bbe832c0 8948 tg3_full_lock(tp, irq_sync);
6aa20a22 8949
1da177e4
LT		 8950 tp->rx_pending = ering->rx_pending;
8951
8952 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8953 tp->rx_pending > 63)
8954 tp->rx_pending = 63;
8955 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8956 tp->tx_pending = ering->tx_pending;
8957
8958 if (netif_running(dev)) {
944d980e 8959 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8960 err = tg3_restart_hw(tp, 1);
8961 if (!err)
8962 tg3_netif_start(tp);
1da177e4
LT		 8963 }
8964
f47c11ee 8965 tg3_full_unlock(tp);
6aa20a22 8966
b02fd9e3
MC		 8967 if (irq_sync && !err)
8968 tg3_phy_start(tp);
8969
b9ec6c1b 8970 return err;
1da177e4 8971}
6aa20a22 8972
1da177e4
LT		 8973static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8974{
8975 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8976
1da177e4 8977 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 8978
e18ce346 8979 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 8980 epause->rx_pause = 1;
8981 else
8982 epause->rx_pause = 0;
8983
e18ce346 8984 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 8985 epause->tx_pause = 1;
8986 else
8987 epause->tx_pause = 0;
1da177e4 8988}
6aa20a22 8989
1da177e4
LT		 8990static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8991{
8992 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 8993 int err = 0;
6aa20a22 8994
b02fd9e3
MC		 8995 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8996 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8997 return -EAGAIN;
1da177e4 8998
b02fd9e3
MC		 8999 if (epause->autoneg) {
9000 u32 newadv;
9001 struct phy_device *phydev;
f47c11ee 9002
298cf9be 9003 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9004
b02fd9e3
MC		 9005 if (epause->rx_pause) {
9006 if (epause->tx_pause)
9007 newadv = ADVERTISED_Pause;
9008 else
9009 newadv = ADVERTISED_Pause |
9010 ADVERTISED_Asym_Pause;
9011 } else if (epause->tx_pause) {
9012 newadv = ADVERTISED_Asym_Pause;
9013 } else
9014 newadv = 0;
9015
9016 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9017 u32 oldadv = phydev->advertising &
9018 (ADVERTISED_Pause |
9019 ADVERTISED_Asym_Pause);
9020 if (oldadv != newadv) {
9021 phydev->advertising &=
9022 ~(ADVERTISED_Pause |
9023 ADVERTISED_Asym_Pause);
9024 phydev->advertising |= newadv;
9025 err = phy_start_aneg(phydev);
9026 }
9027 } else {
9028 tp->link_config.advertising &=
9029 ~(ADVERTISED_Pause |
9030 ADVERTISED_Asym_Pause);
9031 tp->link_config.advertising |= newadv;
9032 }
9033 } else {
9034 if (epause->rx_pause)
e18ce346 9035 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9036 else
e18ce346 9037 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9038
b02fd9e3 9039 if (epause->tx_pause)
e18ce346 9040 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9041 else
e18ce346 9042 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9043
9044 if (netif_running(dev))
9045 tg3_setup_flow_control(tp, 0, 0);
9046 }
9047 } else {
9048 int irq_sync = 0;
9049
9050 if (netif_running(dev)) {
9051 tg3_netif_stop(tp);
9052 irq_sync = 1;
9053 }
9054
9055 tg3_full_lock(tp, irq_sync);
9056
9057 if (epause->autoneg)
9058 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9059 else
9060 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9061 if (epause->rx_pause)
e18ce346 9062 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9063 else
e18ce346 9064 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9065 if (epause->tx_pause)
e18ce346 9066 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9067 else
e18ce346 9068 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9069
9070 if (netif_running(dev)) {
9071 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9072 err = tg3_restart_hw(tp, 1);
9073 if (!err)
9074 tg3_netif_start(tp);
9075 }
9076
9077 tg3_full_unlock(tp);
9078 }
6aa20a22 9079
b9ec6c1b 9080 return err;
1da177e4 9081}
6aa20a22 9082
1da177e4
LT		 9083static u32 tg3_get_rx_csum(struct net_device *dev)
9084{
9085 struct tg3 *tp = netdev_priv(dev);
9086 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9087}
6aa20a22 9088
1da177e4
LT		 9089static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9090{
9091 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9092
1da177e4
LT		 9093 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9094 if (data != 0)
9095 return -EINVAL;
9096 return 0;
9097 }
6aa20a22 9098
f47c11ee 9099 spin_lock_bh(&tp->lock);
1da177e4
LT		 9100 if (data)
9101 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9102 else
9103 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9104 spin_unlock_bh(&tp->lock);
6aa20a22 9105
1da177e4
LT		 9106 return 0;
9107}
6aa20a22 9108
1da177e4
LT		 9109static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9110{
9111 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9112
1da177e4
LT		 9113 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9114 if (data != 0)
9115 return -EINVAL;
9116 return 0;
9117 }
6aa20a22 9118
321d32a0 9119 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9120 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9121 else
9c27dbdf 9122 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9123
9124 return 0;
9125}
9126
b9f2c044 9127static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9128{
b9f2c044
JG		 9129 switch (sset) {
9130 case ETH_SS_TEST:
9131 return TG3_NUM_TEST;
9132 case ETH_SS_STATS:
9133 return TG3_NUM_STATS;
9134 default:
9135 return -EOPNOTSUPP;
9136 }
4cafd3f5
MC		 9137}
9138
1da177e4
LT		 9139static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9140{
9141 switch (stringset) {
9142 case ETH_SS_STATS:
9143 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9144 break;
4cafd3f5
MC		 9145 case ETH_SS_TEST:
9146 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9147 break;
1da177e4
LT		 9148 default:
9149 WARN_ON(1); /* we need a WARN() */
9150 break;
9151 }
9152}
9153
4009a93d
MC		 9154static int tg3_phys_id(struct net_device *dev, u32 data)
9155{
9156 struct tg3 *tp = netdev_priv(dev);
9157 int i;
9158
9159 if (!netif_running(tp->dev))
9160 return -EAGAIN;
9161
9162 if (data == 0)
759afc31 9163 data = UINT_MAX / 2;
4009a93d
MC		 9164
9165 for (i = 0; i < (data * 2); i++) {
9166 if ((i % 2) == 0)
9167 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9168 LED_CTRL_1000MBPS_ON |
9169 LED_CTRL_100MBPS_ON |
9170 LED_CTRL_10MBPS_ON |
9171 LED_CTRL_TRAFFIC_OVERRIDE |
9172 LED_CTRL_TRAFFIC_BLINK |
9173 LED_CTRL_TRAFFIC_LED);
6aa20a22 9174
4009a93d
MC		 9175 else
9176 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9177 LED_CTRL_TRAFFIC_OVERRIDE);
9178
9179 if (msleep_interruptible(500))
9180 break;
9181 }
9182 tw32(MAC_LED_CTRL, tp->led_ctrl);
9183 return 0;
9184}
9185
1da177e4
LT		 9186static void tg3_get_ethtool_stats (struct net_device *dev,
9187 struct ethtool_stats *estats, u64 *tmp_stats)
9188{
9189 struct tg3 *tp = netdev_priv(dev);
9190 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9191}
9192
566f86ad 9193#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9194#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9195#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9196#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9197#define NVRAM_SELFBOOT_HW_SIZE 0x20
9198#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9199
9200static int tg3_test_nvram(struct tg3 *tp)
9201{
b9fc7dc5
AV		 9202 u32 csum, magic;
9203 __le32 *buf;
ab0049b4 9204 int i, j, k, err = 0, size;
566f86ad 9205
e4f34110 9206 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9207 return -EIO;
9208
1b27777a
MC		 9209 if (magic == TG3_EEPROM_MAGIC)
9210 size = NVRAM_TEST_SIZE;
b16250e3 9211 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9212 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9213 TG3_EEPROM_SB_FORMAT_1) {
9214 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9215 case TG3_EEPROM_SB_REVISION_0:
9216 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9217 break;
9218 case TG3_EEPROM_SB_REVISION_2:
9219 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9220 break;
9221 case TG3_EEPROM_SB_REVISION_3:
9222 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9223 break;
9224 default:
9225 return 0;
9226 }
9227 } else
1b27777a 9228 return 0;
b16250e3
MC		 9229 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9230 size = NVRAM_SELFBOOT_HW_SIZE;
9231 else
1b27777a
MC		 9232 return -EIO;
9233
9234 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9235 if (buf == NULL)
9236 return -ENOMEM;
9237
1b27777a
MC		 9238 err = -EIO;
9239 for (i = 0, j = 0; i < size; i += 4, j++) {
b9fc7dc5 9240 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
566f86ad 9241 break;
566f86ad 9242 }
1b27777a 9243 if (i < size)
566f86ad
MC		 9244 goto out;
9245
1b27777a 9246 /* Selfboot format */
b9fc7dc5
AV		 9247 magic = swab32(le32_to_cpu(buf[0]));
9248 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9249 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9250 u8 *buf8 = (u8 *) buf, csum8 = 0;
9251
b9fc7dc5 9252 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9253 TG3_EEPROM_SB_REVISION_2) {
9254 /* For rev 2, the csum doesn't include the MBA. */
9255 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9256 csum8 += buf8[i];
9257 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9258 csum8 += buf8[i];
9259 } else {
9260 for (i = 0; i < size; i++)
9261 csum8 += buf8[i];
9262 }
1b27777a 9263
ad96b485
AB		 9264 if (csum8 == 0) {
9265 err = 0;
9266 goto out;
9267 }
9268
9269 err = -EIO;
9270 goto out;
1b27777a 9271 }
566f86ad 9272
b9fc7dc5 9273 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9274 TG3_EEPROM_MAGIC_HW) {
9275 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9276 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9277 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9278
9279 /* Separate the parity bits and the data bytes. */
9280 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9281 if ((i == 0) || (i == 8)) {
9282 int l;
9283 u8 msk;
9284
9285 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9286 parity[k++] = buf8[i] & msk;
9287 i++;
9288 }
9289 else if (i == 16) {
9290 int l;
9291 u8 msk;
9292
9293 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9294 parity[k++] = buf8[i] & msk;
9295 i++;
9296
9297 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9298 parity[k++] = buf8[i] & msk;
9299 i++;
9300 }
9301 data[j++] = buf8[i];
9302 }
9303
9304 err = -EIO;
9305 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9306 u8 hw8 = hweight8(data[i]);
9307
9308 if ((hw8 & 0x1) && parity[i])
9309 goto out;
9310 else if (!(hw8 & 0x1) && !parity[i])
9311 goto out;
9312 }
9313 err = 0;
9314 goto out;
9315 }
9316
566f86ad
MC		 9317 /* Bootstrap checksum at offset 0x10 */
9318 csum = calc_crc((unsigned char *) buf, 0x10);
b9fc7dc5 9319 if(csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9320 goto out;
9321
9322 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9323 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
b9fc7dc5 9324 if (csum != le32_to_cpu(buf[0xfc/4]))
566f86ad
MC		 9325 goto out;
9326
9327 err = 0;
9328
9329out:
9330 kfree(buf);
9331 return err;
9332}
9333
ca43007a
MC		 9334#define TG3_SERDES_TIMEOUT_SEC 2
9335#define TG3_COPPER_TIMEOUT_SEC 6
9336
9337static int tg3_test_link(struct tg3 *tp)
9338{
9339 int i, max;
9340
9341 if (!netif_running(tp->dev))
9342 return -ENODEV;
9343
4c987487 9344 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9345 max = TG3_SERDES_TIMEOUT_SEC;
9346 else
9347 max = TG3_COPPER_TIMEOUT_SEC;
9348
9349 for (i = 0; i < max; i++) {
9350 if (netif_carrier_ok(tp->dev))
9351 return 0;
9352
9353 if (msleep_interruptible(1000))
9354 break;
9355 }
9356
9357 return -EIO;
9358}
9359
a71116d1 9360/* Only test the commonly used registers */
30ca3e37 9361static int tg3_test_registers(struct tg3 *tp)
a71116d1 9362{
b16250e3 9363 int i, is_5705, is_5750;
a71116d1
MC		 9364 u32 offset, read_mask, write_mask, val, save_val, read_val;
9365 static struct {
9366 u16 offset;
9367 u16 flags;
9368#define TG3_FL_5705 0x1
9369#define TG3_FL_NOT_5705 0x2
9370#define TG3_FL_NOT_5788 0x4
b16250e3 9371#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9372 u32 read_mask;
9373 u32 write_mask;
9374 } reg_tbl[] = {
9375 /* MAC Control Registers */
9376 { MAC_MODE, TG3_FL_NOT_5705,
9377 0x00000000, 0x00ef6f8c },
9378 { MAC_MODE, TG3_FL_5705,
9379 0x00000000, 0x01ef6b8c },
9380 { MAC_STATUS, TG3_FL_NOT_5705,
9381 0x03800107, 0x00000000 },
9382 { MAC_STATUS, TG3_FL_5705,
9383 0x03800100, 0x00000000 },
9384 { MAC_ADDR_0_HIGH, 0x0000,
9385 0x00000000, 0x0000ffff },
9386 { MAC_ADDR_0_LOW, 0x0000,
9387 0x00000000, 0xffffffff },
9388 { MAC_RX_MTU_SIZE, 0x0000,
9389 0x00000000, 0x0000ffff },
9390 { MAC_TX_MODE, 0x0000,
9391 0x00000000, 0x00000070 },
9392 { MAC_TX_LENGTHS, 0x0000,
9393 0x00000000, 0x00003fff },
9394 { MAC_RX_MODE, TG3_FL_NOT_5705,
9395 0x00000000, 0x000007fc },
9396 { MAC_RX_MODE, TG3_FL_5705,
9397 0x00000000, 0x000007dc },
9398 { MAC_HASH_REG_0, 0x0000,
9399 0x00000000, 0xffffffff },
9400 { MAC_HASH_REG_1, 0x0000,
9401 0x00000000, 0xffffffff },
9402 { MAC_HASH_REG_2, 0x0000,
9403 0x00000000, 0xffffffff },
9404 { MAC_HASH_REG_3, 0x0000,
9405 0x00000000, 0xffffffff },
9406
9407 /* Receive Data and Receive BD Initiator Control Registers. */
9408 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9409 0x00000000, 0xffffffff },
9410 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9411 0x00000000, 0xffffffff },
9412 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9413 0x00000000, 0x00000003 },
9414 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9415 0x00000000, 0xffffffff },
9416 { RCVDBDI_STD_BD+0, 0x0000,
9417 0x00000000, 0xffffffff },
9418 { RCVDBDI_STD_BD+4, 0x0000,
9419 0x00000000, 0xffffffff },
9420 { RCVDBDI_STD_BD+8, 0x0000,
9421 0x00000000, 0xffff0002 },
9422 { RCVDBDI_STD_BD+0xc, 0x0000,
9423 0x00000000, 0xffffffff },
6aa20a22 9424
a71116d1
MC		 9425 /* Receive BD Initiator Control Registers. */
9426 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9427 0x00000000, 0xffffffff },
9428 { RCVBDI_STD_THRESH, TG3_FL_5705,
9429 0x00000000, 0x000003ff },
9430 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9431 0x00000000, 0xffffffff },
6aa20a22 9432
a71116d1
MC		 9433 /* Host Coalescing Control Registers. */
9434 { HOSTCC_MODE, TG3_FL_NOT_5705,
9435 0x00000000, 0x00000004 },
9436 { HOSTCC_MODE, TG3_FL_5705,
9437 0x00000000, 0x000000f6 },
9438 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9439 0x00000000, 0xffffffff },
9440 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9441 0x00000000, 0x000003ff },
9442 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9443 0x00000000, 0xffffffff },
9444 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9445 0x00000000, 0x000003ff },
9446 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9447 0x00000000, 0xffffffff },
9448 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9449 0x00000000, 0x000000ff },
9450 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9451 0x00000000, 0xffffffff },
9452 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9453 0x00000000, 0x000000ff },
9454 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9455 0x00000000, 0xffffffff },
9456 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9457 0x00000000, 0xffffffff },
9458 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9459 0x00000000, 0xffffffff },
9460 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9461 0x00000000, 0x000000ff },
9462 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9463 0x00000000, 0xffffffff },
9464 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9465 0x00000000, 0x000000ff },
9466 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9467 0x00000000, 0xffffffff },
9468 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9469 0x00000000, 0xffffffff },
9470 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9471 0x00000000, 0xffffffff },
9472 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9473 0x00000000, 0xffffffff },
9474 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9475 0x00000000, 0xffffffff },
9476 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9477 0xffffffff, 0x00000000 },
9478 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9479 0xffffffff, 0x00000000 },
9480
9481 /* Buffer Manager Control Registers. */
b16250e3 9482 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9483 0x00000000, 0x007fff80 },
b16250e3 9484 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9485 0x00000000, 0x007fffff },
9486 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9487 0x00000000, 0x0000003f },
9488 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9489 0x00000000, 0x000001ff },
9490 { BUFMGR_MB_HIGH_WATER, 0x0000,
9491 0x00000000, 0x000001ff },
9492 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9493 0xffffffff, 0x00000000 },
9494 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9495 0xffffffff, 0x00000000 },
6aa20a22 9496
a71116d1
MC		 9497 /* Mailbox Registers */
9498 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9499 0x00000000, 0x000001ff },
9500 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9501 0x00000000, 0x000001ff },
9502 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9503 0x00000000, 0x000007ff },
9504 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9505 0x00000000, 0x000001ff },
9506
9507 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9508 };
9509
b16250e3
MC		 9510 is_5705 = is_5750 = 0;
9511 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9512 is_5705 = 1;
b16250e3
MC		 9513 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9514 is_5750 = 1;
9515 }
a71116d1
MC		 9516
9517 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9518 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9519 continue;
9520
9521 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9522 continue;
9523
9524 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9525 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9526 continue;
9527
b16250e3
MC		 9528 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9529 continue;
9530
a71116d1
MC		 9531 offset = (u32) reg_tbl[i].offset;
9532 read_mask = reg_tbl[i].read_mask;
9533 write_mask = reg_tbl[i].write_mask;
9534
9535 /* Save the original register content */
9536 save_val = tr32(offset);
9537
9538 /* Determine the read-only value. */
9539 read_val = save_val & read_mask;
9540
9541 /* Write zero to the register, then make sure the read-only bits
9542 * are not changed and the read/write bits are all zeros.
9543 */
9544 tw32(offset, 0);
9545
9546 val = tr32(offset);
9547
9548 /* Test the read-only and read/write bits. */
9549 if (((val & read_mask) != read_val) || (val & write_mask))
9550 goto out;
9551
9552 /* Write ones to all the bits defined by RdMask and WrMask, then
9553 * make sure the read-only bits are not changed and the
9554 * read/write bits are all ones.
9555 */
9556 tw32(offset, read_mask | write_mask);
9557
9558 val = tr32(offset);
9559
9560 /* Test the read-only bits. */
9561 if ((val & read_mask) != read_val)
9562 goto out;
9563
9564 /* Test the read/write bits. */
9565 if ((val & write_mask) != write_mask)
9566 goto out;
9567
9568 tw32(offset, save_val);
9569 }
9570
9571 return 0;
9572
9573out:
9f88f29f
MC		 9574 if (netif_msg_hw(tp))
9575 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9576 offset);
a71116d1
MC		 9577 tw32(offset, save_val);
9578 return -EIO;
9579}
9580
7942e1db
MC		 9581static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9582{
f71e1309 9583 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9584 int i;
9585 u32 j;
9586
e9edda69 9587 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9588 for (j = 0; j < len; j += 4) {
9589 u32 val;
9590
9591 tg3_write_mem(tp, offset + j, test_pattern[i]);
9592 tg3_read_mem(tp, offset + j, &val);
9593 if (val != test_pattern[i])
9594 return -EIO;
9595 }
9596 }
9597 return 0;
9598}
9599
9600static int tg3_test_memory(struct tg3 *tp)
9601{
9602 static struct mem_entry {
9603 u32 offset;
9604 u32 len;
9605 } mem_tbl_570x[] = {
38690194 9606 { 0x00000000, 0x00b50},
7942e1db
MC		 9607 { 0x00002000, 0x1c000},
9608 { 0xffffffff, 0x00000}
9609 }, mem_tbl_5705[] = {
9610 { 0x00000100, 0x0000c},
9611 { 0x00000200, 0x00008},
7942e1db
MC		 9612 { 0x00004000, 0x00800},
9613 { 0x00006000, 0x01000},
9614 { 0x00008000, 0x02000},
9615 { 0x00010000, 0x0e000},
9616 { 0xffffffff, 0x00000}
79f4d13a
MC		 9617 }, mem_tbl_5755[] = {
9618 { 0x00000200, 0x00008},
9619 { 0x00004000, 0x00800},
9620 { 0x00006000, 0x00800},
9621 { 0x00008000, 0x02000},
9622 { 0x00010000, 0x0c000},
9623 { 0xffffffff, 0x00000}
b16250e3
MC		 9624 }, mem_tbl_5906[] = {
9625 { 0x00000200, 0x00008},
9626 { 0x00004000, 0x00400},
9627 { 0x00006000, 0x00400},
9628 { 0x00008000, 0x01000},
9629 { 0x00010000, 0x01000},
9630 { 0xffffffff, 0x00000}
7942e1db
MC		 9631 };
9632 struct mem_entry *mem_tbl;
9633 int err = 0;
9634 int i;
9635
321d32a0
MC		 9636 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9637 mem_tbl = mem_tbl_5755;
9638 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9639 mem_tbl = mem_tbl_5906;
9640 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9641 mem_tbl = mem_tbl_5705;
9642 else
7942e1db
MC		 9643 mem_tbl = mem_tbl_570x;
9644
9645 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9646 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9647 mem_tbl[i].len)) != 0)
9648 break;
9649 }
6aa20a22 9650
7942e1db
MC		 9651 return err;
9652}
9653
9f40dead
MC		 9654#define TG3_MAC_LOOPBACK 0
9655#define TG3_PHY_LOOPBACK 1
9656
9657static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9658{
9f40dead 9659 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9660 u32 desc_idx;
9661 struct sk_buff *skb, *rx_skb;
9662 u8 *tx_data;
9663 dma_addr_t map;
9664 int num_pkts, tx_len, rx_len, i, err;
9665 struct tg3_rx_buffer_desc *desc;
9666
9f40dead 9667 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9668 /* HW errata - mac loopback fails in some cases on 5780.
9669 * Normal traffic and PHY loopback are not affected by
9670 * errata.
9671 */
9672 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9673 return 0;
9674
9f40dead 9675 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9676 MAC_MODE_PORT_INT_LPBACK;
9677 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9678 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9679 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9680 mac_mode |= MAC_MODE_PORT_MODE_MII;
9681 else
9682 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9683 tw32(MAC_MODE, mac_mode);
9684 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9685 u32 val;
9686
b16250e3
MC		 9687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9688 u32 phytest;
9689
9690 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9691 u32 phy;
9692
9693 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9694 phytest | MII_TG3_EPHY_SHADOW_EN);
9695 if (!tg3_readphy(tp, 0x1b, &phy))
9696 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9697 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9698 }
5d64ad34
MC		 9699 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9700 } else
9701 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9702
9ef8ca99
MC		 9703 tg3_phy_toggle_automdix(tp, 0);
9704
3f7045c1 9705 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9706 udelay(40);
5d64ad34 9707
e8f3f6ca 9708 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9710 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9711 mac_mode |= MAC_MODE_PORT_MODE_MII;
9712 } else
9713 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9714
c94e3941
MC		 9715 /* reset to prevent losing 1st rx packet intermittently */
9716 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9717 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9718 udelay(10);
9719 tw32_f(MAC_RX_MODE, tp->rx_mode);
9720 }
e8f3f6ca
MC		 9721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9722 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9723 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9724 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9725 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9726 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9727 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9728 }
9f40dead 9729 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9730 }
9731 else
9732 return -EINVAL;
c76949a6
MC		 9733
9734 err = -EIO;
9735
c76949a6 9736 tx_len = 1514;
a20e9c62 9737 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9738 if (!skb)
9739 return -ENOMEM;
9740
c76949a6
MC		 9741 tx_data = skb_put(skb, tx_len);
9742 memcpy(tx_data, tp->dev->dev_addr, 6);
9743 memset(tx_data + 6, 0x0, 8);
9744
9745 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9746
9747 for (i = 14; i < tx_len; i++)
9748 tx_data[i] = (u8) (i & 0xff);
9749
9750 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9751
9752 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9753 HOSTCC_MODE_NOW);
9754
9755 udelay(10);
9756
9757 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9758
c76949a6
MC		 9759 num_pkts = 0;
9760
9f40dead 9761 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9762
9f40dead 9763 tp->tx_prod++;
c76949a6
MC		 9764 num_pkts++;
9765
9f40dead
MC		 9766 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9767 tp->tx_prod);
09ee929c 9768 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9769
9770 udelay(10);
9771
3f7045c1
MC		 9772 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9773 for (i = 0; i < 25; i++) {
c76949a6
MC		 9774 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9775 HOSTCC_MODE_NOW);
9776
9777 udelay(10);
9778
9779 tx_idx = tp->hw_status->idx[0].tx_consumer;
9780 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9781 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9782 (rx_idx == (rx_start_idx + num_pkts)))
9783 break;
9784 }
9785
9786 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9787 dev_kfree_skb(skb);
9788
9f40dead 9789 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9790 goto out;
9791
9792 if (rx_idx != rx_start_idx + num_pkts)
9793 goto out;
9794
9795 desc = &tp->rx_rcb[rx_start_idx];
9796 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9797 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9798 if (opaque_key != RXD_OPAQUE_RING_STD)
9799 goto out;
9800
9801 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9802 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9803 goto out;
9804
9805 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9806 if (rx_len != tx_len)
9807 goto out;
9808
9809 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9810
9811 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9812 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9813
9814 for (i = 14; i < tx_len; i++) {
9815 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9816 goto out;
9817 }
9818 err = 0;
6aa20a22 9819
c76949a6
MC		 9820 /* tg3_free_rings will unmap and free the rx_skb */
9821out:
9822 return err;
9823}
9824
9f40dead
MC		 9825#define TG3_MAC_LOOPBACK_FAILED 1
9826#define TG3_PHY_LOOPBACK_FAILED 2
9827#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9828 TG3_PHY_LOOPBACK_FAILED)
9829
9830static int tg3_test_loopback(struct tg3 *tp)
9831{
9832 int err = 0;
9936bcf6 9833 u32 cpmuctrl = 0;
9f40dead
MC		 9834
9835 if (!netif_running(tp->dev))
9836 return TG3_LOOPBACK_FAILED;
9837
b9ec6c1b
MC		 9838 err = tg3_reset_hw(tp, 1);
9839 if (err)
9840 return TG3_LOOPBACK_FAILED;
9f40dead 9841
6833c043
MC		 9842 /* Turn off gphy autopowerdown. */
9843 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9844 tg3_phy_toggle_apd(tp, false);
9845
321d32a0 9846 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9847 int i;
9848 u32 status;
9849
9850 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9851
9852 /* Wait for up to 40 microseconds to acquire lock. */
9853 for (i = 0; i < 4; i++) {
9854 status = tr32(TG3_CPMU_MUTEX_GNT);
9855 if (status == CPMU_MUTEX_GNT_DRIVER)
9856 break;
9857 udelay(10);
9858 }
9859
9860 if (status != CPMU_MUTEX_GNT_DRIVER)
9861 return TG3_LOOPBACK_FAILED;
9862
b2a5c19c 9863 /* Turn off link-based power management. */
e875093c 9864 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9865 tw32(TG3_CPMU_CTRL,
9866 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9867 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9868 }
9869
9f40dead
MC		 9870 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9871 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9872
321d32a0 9873 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9874 tw32(TG3_CPMU_CTRL, cpmuctrl);
9875
9876 /* Release the mutex */
9877 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9878 }
9879
dd477003
MC		 9880 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9881 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9882 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9883 err |= TG3_PHY_LOOPBACK_FAILED;
9884 }
9885
6833c043
MC		 9886 /* Re-enable gphy autopowerdown. */
9887 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9888 tg3_phy_toggle_apd(tp, true);
9889
9f40dead
MC		 9890 return err;
9891}
9892
4cafd3f5
MC		 9893static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9894 u64 *data)
9895{
566f86ad
MC		 9896 struct tg3 *tp = netdev_priv(dev);
9897
bc1c7567
MC		 9898 if (tp->link_config.phy_is_low_power)
9899 tg3_set_power_state(tp, PCI_D0);
9900
566f86ad
MC		 9901 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9902
9903 if (tg3_test_nvram(tp) != 0) {
9904 etest->flags |= ETH_TEST_FL_FAILED;
9905 data[0] = 1;
9906 }
ca43007a
MC		 9907 if (tg3_test_link(tp) != 0) {
9908 etest->flags |= ETH_TEST_FL_FAILED;
9909 data[1] = 1;
9910 }
a71116d1 9911 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9912 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9913
9914 if (netif_running(dev)) {
b02fd9e3 9915 tg3_phy_stop(tp);
a71116d1 9916 tg3_netif_stop(tp);
bbe832c0
MC		 9917 irq_sync = 1;
9918 }
a71116d1 9919
bbe832c0 9920 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9921
9922 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9923 err = tg3_nvram_lock(tp);
a71116d1
MC		 9924 tg3_halt_cpu(tp, RX_CPU_BASE);
9925 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9926 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9927 if (!err)
9928 tg3_nvram_unlock(tp);
a71116d1 9929
d9ab5ad1
MC		 9930 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9931 tg3_phy_reset(tp);
9932
a71116d1
MC		 9933 if (tg3_test_registers(tp) != 0) {
9934 etest->flags |= ETH_TEST_FL_FAILED;
9935 data[2] = 1;
9936 }
7942e1db
MC		 9937 if (tg3_test_memory(tp) != 0) {
9938 etest->flags |= ETH_TEST_FL_FAILED;
9939 data[3] = 1;
9940 }
9f40dead 9941 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9942 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9943
f47c11ee
DM		 9944 tg3_full_unlock(tp);
9945
d4bc3927
MC		 9946 if (tg3_test_interrupt(tp) != 0) {
9947 etest->flags |= ETH_TEST_FL_FAILED;
9948 data[5] = 1;
9949 }
f47c11ee
DM		 9950
9951 tg3_full_lock(tp, 0);
d4bc3927 9952
a71116d1
MC		 9953 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9954 if (netif_running(dev)) {
9955 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 9956 err2 = tg3_restart_hw(tp, 1);
9957 if (!err2)
b9ec6c1b 9958 tg3_netif_start(tp);
a71116d1 9959 }
f47c11ee
DM		 9960
9961 tg3_full_unlock(tp);
b02fd9e3
MC		 9962
9963 if (irq_sync && !err2)
9964 tg3_phy_start(tp);
a71116d1 9965 }
bc1c7567
MC		 9966 if (tp->link_config.phy_is_low_power)
9967 tg3_set_power_state(tp, PCI_D3hot);
9968
4cafd3f5
MC		 9969}
9970
1da177e4
LT		 9971static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9972{
9973 struct mii_ioctl_data *data = if_mii(ifr);
9974 struct tg3 *tp = netdev_priv(dev);
9975 int err;
9976
b02fd9e3
MC		 9977 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9978 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9979 return -EAGAIN;
298cf9be 9980 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 9981 }
9982
1da177e4
LT		 9983 switch(cmd) {
9984 case SIOCGMIIPHY:
9985 data->phy_id = PHY_ADDR;
9986
9987 /* fallthru */
9988 case SIOCGMIIREG: {
9989 u32 mii_regval;
9990
9991 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9992 break; /* We have no PHY */
9993
bc1c7567
MC		 9994 if (tp->link_config.phy_is_low_power)
9995 return -EAGAIN;
9996
f47c11ee 9997 spin_lock_bh(&tp->lock);
1da177e4 9998 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9999 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10000
10001 data->val_out = mii_regval;
10002
10003 return err;
10004 }
10005
10006 case SIOCSMIIREG:
10007 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10008 break; /* We have no PHY */
10009
10010 if (!capable(CAP_NET_ADMIN))
10011 return -EPERM;
10012
bc1c7567
MC		 10013 if (tp->link_config.phy_is_low_power)
10014 return -EAGAIN;
10015
f47c11ee 10016 spin_lock_bh(&tp->lock);
1da177e4 10017 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10018 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10019
10020 return err;
10021
10022 default:
10023 /* do nothing */
10024 break;
10025 }
10026 return -EOPNOTSUPP;
10027}
10028
10029#if TG3_VLAN_TAG_USED
10030static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10031{
10032 struct tg3 *tp = netdev_priv(dev);
10033
844b3eed
MC		 10034 if (!netif_running(dev)) {
10035 tp->vlgrp = grp;
10036 return;
10037 }
10038
10039 tg3_netif_stop(tp);
29315e87 10040
f47c11ee 10041 tg3_full_lock(tp, 0);
1da177e4
LT		 10042
10043 tp->vlgrp = grp;
10044
10045 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10046 __tg3_set_rx_mode(dev);
10047
844b3eed 10048 tg3_netif_start(tp);
46966545
MC		 10049
10050 tg3_full_unlock(tp);
1da177e4 10051}
1da177e4
LT		 10052#endif
10053
15f9850d
DM		 10054static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10055{
10056 struct tg3 *tp = netdev_priv(dev);
10057
10058 memcpy(ec, &tp->coal, sizeof(*ec));
10059 return 0;
10060}
10061
d244c892
MC		 10062static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10063{
10064 struct tg3 *tp = netdev_priv(dev);
10065 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10066 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10067
10068 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10069 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10070 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10071 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10072 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10073 }
10074
10075 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10076 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10077 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10078 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10079 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10080 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10081 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10082 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10083 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10084 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10085 return -EINVAL;
10086
10087 /* No rx interrupts will be generated if both are zero */
10088 if ((ec->rx_coalesce_usecs == 0) &&
10089 (ec->rx_max_coalesced_frames == 0))
10090 return -EINVAL;
10091
10092 /* No tx interrupts will be generated if both are zero */
10093 if ((ec->tx_coalesce_usecs == 0) &&
10094 (ec->tx_max_coalesced_frames == 0))
10095 return -EINVAL;
10096
10097 /* Only copy relevant parameters, ignore all others. */
10098 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10099 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10100 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10101 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10102 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10103 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10104 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10105 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10106 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10107
10108 if (netif_running(dev)) {
10109 tg3_full_lock(tp, 0);
10110 __tg3_set_coalesce(tp, &tp->coal);
10111 tg3_full_unlock(tp);
10112 }
10113 return 0;
10114}
10115
7282d491 10116static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10117 .get_settings = tg3_get_settings,
10118 .set_settings = tg3_set_settings,
10119 .get_drvinfo = tg3_get_drvinfo,
10120 .get_regs_len = tg3_get_regs_len,
10121 .get_regs = tg3_get_regs,
10122 .get_wol = tg3_get_wol,
10123 .set_wol = tg3_set_wol,
10124 .get_msglevel = tg3_get_msglevel,
10125 .set_msglevel = tg3_set_msglevel,
10126 .nway_reset = tg3_nway_reset,
10127 .get_link = ethtool_op_get_link,
10128 .get_eeprom_len = tg3_get_eeprom_len,
10129 .get_eeprom = tg3_get_eeprom,
10130 .set_eeprom = tg3_set_eeprom,
10131 .get_ringparam = tg3_get_ringparam,
10132 .set_ringparam = tg3_set_ringparam,
10133 .get_pauseparam = tg3_get_pauseparam,
10134 .set_pauseparam = tg3_set_pauseparam,
10135 .get_rx_csum = tg3_get_rx_csum,
10136 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10137 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10138 .set_sg = ethtool_op_set_sg,
1da177e4 10139 .set_tso = tg3_set_tso,
4cafd3f5 10140 .self_test = tg3_self_test,
1da177e4 10141 .get_strings = tg3_get_strings,
4009a93d 10142 .phys_id = tg3_phys_id,
1da177e4 10143 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10144 .get_coalesce = tg3_get_coalesce,
d244c892 10145 .set_coalesce = tg3_set_coalesce,
b9f2c044 10146 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10147};
10148
10149static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10150{
1b27777a 10151 u32 cursize, val, magic;
1da177e4
LT		 10152
10153 tp->nvram_size = EEPROM_CHIP_SIZE;
10154
e4f34110 10155 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10156 return;
10157
b16250e3
MC		 10158 if ((magic != TG3_EEPROM_MAGIC) &&
10159 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10160 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10161 return;
10162
10163 /*
10164 * Size the chip by reading offsets at increasing powers of two.
10165 * When we encounter our validation signature, we know the addressing
10166 * has wrapped around, and thus have our chip size.
10167 */
1b27777a 10168 cursize = 0x10;
1da177e4
LT		 10169
10170 while (cursize < tp->nvram_size) {
e4f34110 10171 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10172 return;
10173
1820180b 10174 if (val == magic)
1da177e4
LT		 10175 break;
10176
10177 cursize <<= 1;
10178 }
10179
10180 tp->nvram_size = cursize;
10181}
6aa20a22 10182
1da177e4
LT		 10183static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10184{
10185 u32 val;
10186
e4f34110 10187 if (tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10188 return;
10189
10190 /* Selfboot format */
1820180b 10191 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10192 tg3_get_eeprom_size(tp);
10193 return;
10194 }
10195
e4f34110 10196 if (tg3_nvram_read_swab(tp, 0xf0, &val) == 0) {
1da177e4
LT		 10197 if (val != 0) {
10198 tp->nvram_size = (val >> 16) * 1024;
10199 return;
10200 }
10201 }
fd1122a2 10202 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10203}
10204
10205static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10206{
10207 u32 nvcfg1;
10208
10209 nvcfg1 = tr32(NVRAM_CFG1);
10210 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10211 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10212 }
10213 else {
10214 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10215 tw32(NVRAM_CFG1, nvcfg1);
10216 }
10217
4c987487 10218 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10219 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10220 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10221 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10222 tp->nvram_jedecnum = JEDEC_ATMEL;
10223 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10224 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10225 break;
10226 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10227 tp->nvram_jedecnum = JEDEC_ATMEL;
10228 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10229 break;
10230 case FLASH_VENDOR_ATMEL_EEPROM:
10231 tp->nvram_jedecnum = JEDEC_ATMEL;
10232 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10233 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10234 break;
10235 case FLASH_VENDOR_ST:
10236 tp->nvram_jedecnum = JEDEC_ST;
10237 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10238 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10239 break;
10240 case FLASH_VENDOR_SAIFUN:
10241 tp->nvram_jedecnum = JEDEC_SAIFUN;
10242 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10243 break;
10244 case FLASH_VENDOR_SST_SMALL:
10245 case FLASH_VENDOR_SST_LARGE:
10246 tp->nvram_jedecnum = JEDEC_SST;
10247 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10248 break;
10249 }
10250 }
10251 else {
10252 tp->nvram_jedecnum = JEDEC_ATMEL;
10253 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10254 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10255 }
10256}
10257
361b4ac2
MC		 10258static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10259{
10260 u32 nvcfg1;
10261
10262 nvcfg1 = tr32(NVRAM_CFG1);
10263
e6af301b
MC		 10264 /* NVRAM protection for TPM */
10265 if (nvcfg1 & (1 << 27))
10266 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10267
361b4ac2
MC		 10268 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10269 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10270 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10271 tp->nvram_jedecnum = JEDEC_ATMEL;
10272 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10273 break;
10274 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10275 tp->nvram_jedecnum = JEDEC_ATMEL;
10276 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10277 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10278 break;
10279 case FLASH_5752VENDOR_ST_M45PE10:
10280 case FLASH_5752VENDOR_ST_M45PE20:
10281 case FLASH_5752VENDOR_ST_M45PE40:
10282 tp->nvram_jedecnum = JEDEC_ST;
10283 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10284 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10285 break;
10286 }
10287
10288 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10289 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10290 case FLASH_5752PAGE_SIZE_256:
10291 tp->nvram_pagesize = 256;
10292 break;
10293 case FLASH_5752PAGE_SIZE_512:
10294 tp->nvram_pagesize = 512;
10295 break;
10296 case FLASH_5752PAGE_SIZE_1K:
10297 tp->nvram_pagesize = 1024;
10298 break;
10299 case FLASH_5752PAGE_SIZE_2K:
10300 tp->nvram_pagesize = 2048;
10301 break;
10302 case FLASH_5752PAGE_SIZE_4K:
10303 tp->nvram_pagesize = 4096;
10304 break;
10305 case FLASH_5752PAGE_SIZE_264:
10306 tp->nvram_pagesize = 264;
10307 break;
10308 }
10309 }
10310 else {
10311 /* For eeprom, set pagesize to maximum eeprom size */
10312 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10313
10314 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10315 tw32(NVRAM_CFG1, nvcfg1);
10316 }
10317}
10318
d3c7b886
MC		 10319static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10320{
989a9d23 10321 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10322
10323 nvcfg1 = tr32(NVRAM_CFG1);
10324
10325 /* NVRAM protection for TPM */
989a9d23 10326 if (nvcfg1 & (1 << 27)) {
d3c7b886 10327 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10328 protect = 1;
10329 }
d3c7b886 10330
989a9d23
MC		 10331 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10332 switch (nvcfg1) {
d3c7b886
MC		 10333 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10334 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10335 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10336 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10337 tp->nvram_jedecnum = JEDEC_ATMEL;
10338 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10339 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10340 tp->nvram_pagesize = 264;
70b65a2d
MC		 10341 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10342 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10343 tp->nvram_size = (protect ? 0x3e200 :
10344 TG3_NVRAM_SIZE_512KB);
989a9d23 10345 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10346 tp->nvram_size = (protect ? 0x1f200 :
10347 TG3_NVRAM_SIZE_256KB);
989a9d23 10348 else
fd1122a2
MC		 10349 tp->nvram_size = (protect ? 0x1f200 :
10350 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10351 break;
10352 case FLASH_5752VENDOR_ST_M45PE10:
10353 case FLASH_5752VENDOR_ST_M45PE20:
10354 case FLASH_5752VENDOR_ST_M45PE40:
10355 tp->nvram_jedecnum = JEDEC_ST;
10356 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10357 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10358 tp->nvram_pagesize = 256;
989a9d23 10359 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10360 tp->nvram_size = (protect ?
10361 TG3_NVRAM_SIZE_64KB :
10362 TG3_NVRAM_SIZE_128KB);
989a9d23 10363 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10364 tp->nvram_size = (protect ?
10365 TG3_NVRAM_SIZE_64KB :
10366 TG3_NVRAM_SIZE_256KB);
989a9d23 10367 else
fd1122a2
MC		 10368 tp->nvram_size = (protect ?
10369 TG3_NVRAM_SIZE_128KB :
10370 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10371 break;
10372 }
10373}
10374
1b27777a
MC		 10375static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10376{
10377 u32 nvcfg1;
10378
10379 nvcfg1 = tr32(NVRAM_CFG1);
10380
10381 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10382 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10383 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10384 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10385 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10386 tp->nvram_jedecnum = JEDEC_ATMEL;
10387 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10388 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10389
10390 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10391 tw32(NVRAM_CFG1, nvcfg1);
10392 break;
10393 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10394 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10395 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10396 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10397 tp->nvram_jedecnum = JEDEC_ATMEL;
10398 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10399 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10400 tp->nvram_pagesize = 264;
10401 break;
10402 case FLASH_5752VENDOR_ST_M45PE10:
10403 case FLASH_5752VENDOR_ST_M45PE20:
10404 case FLASH_5752VENDOR_ST_M45PE40:
10405 tp->nvram_jedecnum = JEDEC_ST;
10406 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10407 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10408 tp->nvram_pagesize = 256;
10409 break;
10410 }
10411}
10412
6b91fa02
MC		 10413static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10414{
10415 u32 nvcfg1, protect = 0;
10416
10417 nvcfg1 = tr32(NVRAM_CFG1);
10418
10419 /* NVRAM protection for TPM */
10420 if (nvcfg1 & (1 << 27)) {
10421 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10422 protect = 1;
10423 }
10424
10425 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10426 switch (nvcfg1) {
10427 case FLASH_5761VENDOR_ATMEL_ADB021D:
10428 case FLASH_5761VENDOR_ATMEL_ADB041D:
10429 case FLASH_5761VENDOR_ATMEL_ADB081D:
10430 case FLASH_5761VENDOR_ATMEL_ADB161D:
10431 case FLASH_5761VENDOR_ATMEL_MDB021D:
10432 case FLASH_5761VENDOR_ATMEL_MDB041D:
10433 case FLASH_5761VENDOR_ATMEL_MDB081D:
10434 case FLASH_5761VENDOR_ATMEL_MDB161D:
10435 tp->nvram_jedecnum = JEDEC_ATMEL;
10436 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10437 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10438 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10439 tp->nvram_pagesize = 256;
10440 break;
10441 case FLASH_5761VENDOR_ST_A_M45PE20:
10442 case FLASH_5761VENDOR_ST_A_M45PE40:
10443 case FLASH_5761VENDOR_ST_A_M45PE80:
10444 case FLASH_5761VENDOR_ST_A_M45PE16:
10445 case FLASH_5761VENDOR_ST_M_M45PE20:
10446 case FLASH_5761VENDOR_ST_M_M45PE40:
10447 case FLASH_5761VENDOR_ST_M_M45PE80:
10448 case FLASH_5761VENDOR_ST_M_M45PE16:
10449 tp->nvram_jedecnum = JEDEC_ST;
10450 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10451 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10452 tp->nvram_pagesize = 256;
10453 break;
10454 }
10455
10456 if (protect) {
10457 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10458 } else {
10459 switch (nvcfg1) {
10460 case FLASH_5761VENDOR_ATMEL_ADB161D:
10461 case FLASH_5761VENDOR_ATMEL_MDB161D:
10462 case FLASH_5761VENDOR_ST_A_M45PE16:
10463 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10464 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10465 break;
10466 case FLASH_5761VENDOR_ATMEL_ADB081D:
10467 case FLASH_5761VENDOR_ATMEL_MDB081D:
10468 case FLASH_5761VENDOR_ST_A_M45PE80:
10469 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10470 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10471 break;
10472 case FLASH_5761VENDOR_ATMEL_ADB041D:
10473 case FLASH_5761VENDOR_ATMEL_MDB041D:
10474 case FLASH_5761VENDOR_ST_A_M45PE40:
10475 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10476 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10477 break;
10478 case FLASH_5761VENDOR_ATMEL_ADB021D:
10479 case FLASH_5761VENDOR_ATMEL_MDB021D:
10480 case FLASH_5761VENDOR_ST_A_M45PE20:
10481 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10482 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10483 break;
10484 }
10485 }
10486}
10487
b5d3772c
MC		 10488static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10489{
10490 tp->nvram_jedecnum = JEDEC_ATMEL;
10491 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10492 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10493}
10494
321d32a0
MC		 10495static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10496{
10497 u32 nvcfg1;
10498
10499 nvcfg1 = tr32(NVRAM_CFG1);
10500
10501 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10502 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10503 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10504 tp->nvram_jedecnum = JEDEC_ATMEL;
10505 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10506 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10507
10508 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10509 tw32(NVRAM_CFG1, nvcfg1);
10510 return;
10511 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10512 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10513 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10514 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10515 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10516 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10517 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10518 tp->nvram_jedecnum = JEDEC_ATMEL;
10519 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10520 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10521
10522 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10523 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10524 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10525 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10526 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10527 break;
10528 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10529 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10530 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10531 break;
10532 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10533 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10534 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10535 break;
10536 }
10537 break;
10538 case FLASH_5752VENDOR_ST_M45PE10:
10539 case FLASH_5752VENDOR_ST_M45PE20:
10540 case FLASH_5752VENDOR_ST_M45PE40:
10541 tp->nvram_jedecnum = JEDEC_ST;
10542 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10543 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10544
10545 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10546 case FLASH_5752VENDOR_ST_M45PE10:
10547 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10548 break;
10549 case FLASH_5752VENDOR_ST_M45PE20:
10550 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10551 break;
10552 case FLASH_5752VENDOR_ST_M45PE40:
10553 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10554 break;
10555 }
10556 break;
10557 default:
10558 return;
10559 }
10560
10561 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10562 case FLASH_5752PAGE_SIZE_256:
10563 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10564 tp->nvram_pagesize = 256;
10565 break;
10566 case FLASH_5752PAGE_SIZE_512:
10567 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10568 tp->nvram_pagesize = 512;
10569 break;
10570 case FLASH_5752PAGE_SIZE_1K:
10571 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10572 tp->nvram_pagesize = 1024;
10573 break;
10574 case FLASH_5752PAGE_SIZE_2K:
10575 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10576 tp->nvram_pagesize = 2048;
10577 break;
10578 case FLASH_5752PAGE_SIZE_4K:
10579 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10580 tp->nvram_pagesize = 4096;
10581 break;
10582 case FLASH_5752PAGE_SIZE_264:
10583 tp->nvram_pagesize = 264;
10584 break;
10585 case FLASH_5752PAGE_SIZE_528:
10586 tp->nvram_pagesize = 528;
10587 break;
10588 }
10589}
10590
1da177e4
LT		 10591/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10592static void __devinit tg3_nvram_init(struct tg3 *tp)
10593{
1da177e4
LT		 10594 tw32_f(GRC_EEPROM_ADDR,
10595 (EEPROM_ADDR_FSM_RESET |
10596 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10597 EEPROM_ADDR_CLKPERD_SHIFT)));
10598
9d57f01c 10599 msleep(1);
1da177e4
LT		 10600
10601 /* Enable seeprom accesses. */
10602 tw32_f(GRC_LOCAL_CTRL,
10603 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10604 udelay(100);
10605
10606 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10607 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10608 tp->tg3_flags |= TG3_FLAG_NVRAM;
10609
ec41c7df
MC		 10610 if (tg3_nvram_lock(tp)) {
10611 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10612 "tg3_nvram_init failed.\n", tp->dev->name);
10613 return;
10614 }
e6af301b 10615 tg3_enable_nvram_access(tp);
1da177e4 10616
989a9d23
MC		 10617 tp->nvram_size = 0;
10618
361b4ac2
MC		 10619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10620 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10621 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10622 tg3_get_5755_nvram_info(tp);
d30cdd28 10623 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10624 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10626 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10627 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10628 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10629 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10630 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10631 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10632 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10633 else
10634 tg3_get_nvram_info(tp);
10635
989a9d23
MC		 10636 if (tp->nvram_size == 0)
10637 tg3_get_nvram_size(tp);
1da177e4 10638
e6af301b 10639 tg3_disable_nvram_access(tp);
381291b7 10640 tg3_nvram_unlock(tp);
1da177e4
LT		 10641
10642 } else {
10643 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10644
10645 tg3_get_eeprom_size(tp);
10646 }
10647}
10648
1da177e4
LT		 10649static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10650 u32 offset, u32 len, u8 *buf)
10651{
10652 int i, j, rc = 0;
10653 u32 val;
10654
10655 for (i = 0; i < len; i += 4) {
b9fc7dc5
AV		 10656 u32 addr;
10657 __le32 data;
1da177e4
LT		 10658
10659 addr = offset + i;
10660
10661 memcpy(&data, buf + i, 4);
10662
b9fc7dc5 10663 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
1da177e4
LT		 10664
10665 val = tr32(GRC_EEPROM_ADDR);
10666 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10667
10668 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10669 EEPROM_ADDR_READ);
10670 tw32(GRC_EEPROM_ADDR, val |
10671 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10672 (addr & EEPROM_ADDR_ADDR_MASK) |
10673 EEPROM_ADDR_START |
10674 EEPROM_ADDR_WRITE);
6aa20a22 10675
9d57f01c 10676 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10677 val = tr32(GRC_EEPROM_ADDR);
10678
10679 if (val & EEPROM_ADDR_COMPLETE)
10680 break;
9d57f01c 10681 msleep(1);
1da177e4
LT		 10682 }
10683 if (!(val & EEPROM_ADDR_COMPLETE)) {
10684 rc = -EBUSY;
10685 break;
10686 }
10687 }
10688
10689 return rc;
10690}
10691
10692/* offset and length are dword aligned */
10693static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10694 u8 *buf)
10695{
10696 int ret = 0;
10697 u32 pagesize = tp->nvram_pagesize;
10698 u32 pagemask = pagesize - 1;
10699 u32 nvram_cmd;
10700 u8 *tmp;
10701
10702 tmp = kmalloc(pagesize, GFP_KERNEL);
10703 if (tmp == NULL)
10704 return -ENOMEM;
10705
10706 while (len) {
10707 int j;
e6af301b 10708 u32 phy_addr, page_off, size;
1da177e4
LT		 10709
10710 phy_addr = offset & ~pagemask;
6aa20a22 10711
1da177e4 10712 for (j = 0; j < pagesize; j += 4) {
286e310f 10713 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
b9fc7dc5 10714 (__le32 *) (tmp + j))))
1da177e4
LT		 10715 break;
10716 }
10717 if (ret)
10718 break;
10719
10720 page_off = offset & pagemask;
10721 size = pagesize;
10722 if (len < size)
10723 size = len;
10724
10725 len -= size;
10726
10727 memcpy(tmp + page_off, buf, size);
10728
10729 offset = offset + (pagesize - page_off);
10730
e6af301b 10731 tg3_enable_nvram_access(tp);
1da177e4
LT		 10732
10733 /*
10734 * Before we can erase the flash page, we need
10735 * to issue a special "write enable" command.
10736 */
10737 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10738
10739 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10740 break;
10741
10742 /* Erase the target page */
10743 tw32(NVRAM_ADDR, phy_addr);
10744
10745 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10746 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10747
10748 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10749 break;
10750
10751 /* Issue another write enable to start the write. */
10752 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10753
10754 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10755 break;
10756
10757 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10758 __be32 data;
1da177e4 10759
b9fc7dc5
AV		 10760 data = *((__be32 *) (tmp + j));
10761 /* swab32(le32_to_cpu(data)), actually */
10762 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10763
10764 tw32(NVRAM_ADDR, phy_addr + j);
10765
10766 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10767 NVRAM_CMD_WR;
10768
10769 if (j == 0)
10770 nvram_cmd |= NVRAM_CMD_FIRST;
10771 else if (j == (pagesize - 4))
10772 nvram_cmd |= NVRAM_CMD_LAST;
10773
10774 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10775 break;
10776 }
10777 if (ret)
10778 break;
10779 }
10780
10781 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10782 tg3_nvram_exec_cmd(tp, nvram_cmd);
10783
10784 kfree(tmp);
10785
10786 return ret;
10787}
10788
10789/* offset and length are dword aligned */
10790static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10791 u8 *buf)
10792{
10793 int i, ret = 0;
10794
10795 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10796 u32 page_off, phy_addr, nvram_cmd;
10797 __be32 data;
1da177e4
LT		 10798
10799 memcpy(&data, buf + i, 4);
b9fc7dc5 10800 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10801
10802 page_off = offset % tp->nvram_pagesize;
10803
1820180b 10804 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10805
10806 tw32(NVRAM_ADDR, phy_addr);
10807
10808 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10809
10810 if ((page_off == 0) || (i == 0))
10811 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10812 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10813 nvram_cmd |= NVRAM_CMD_LAST;
10814
10815 if (i == (len - 4))
10816 nvram_cmd |= NVRAM_CMD_LAST;
10817
321d32a0
MC		 10818 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10819 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10820 (tp->nvram_jedecnum == JEDEC_ST) &&
10821 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10822
10823 if ((ret = tg3_nvram_exec_cmd(tp,
10824 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10825 NVRAM_CMD_DONE)))
10826
10827 break;
10828 }
10829 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10830 /* We always do complete word writes to eeprom. */
10831 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10832 }
10833
10834 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10835 break;
10836 }
10837 return ret;
10838}
10839
10840/* offset and length are dword aligned */
10841static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10842{
10843 int ret;
10844
1da177e4 10845 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10846 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10847 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10848 udelay(40);
10849 }
10850
10851 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10852 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10853 }
10854 else {
10855 u32 grc_mode;
10856
ec41c7df
MC		 10857 ret = tg3_nvram_lock(tp);
10858 if (ret)
10859 return ret;
1da177e4 10860
e6af301b
MC		 10861 tg3_enable_nvram_access(tp);
10862 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10863 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10864 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10865
10866 grc_mode = tr32(GRC_MODE);
10867 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10868
10869 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10870 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10871
10872 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10873 buf);
10874 }
10875 else {
10876 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10877 buf);
10878 }
10879
10880 grc_mode = tr32(GRC_MODE);
10881 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10882
e6af301b 10883 tg3_disable_nvram_access(tp);
1da177e4
LT		 10884 tg3_nvram_unlock(tp);
10885 }
10886
10887 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10888 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10889 udelay(40);
10890 }
10891
10892 return ret;
10893}
10894
10895struct subsys_tbl_ent {
10896 u16 subsys_vendor, subsys_devid;
10897 u32 phy_id;
10898};
10899
10900static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10901 /* Broadcom boards. */
10902 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10903 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10904 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10905 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10906 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10907 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10908 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10909 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10910 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10911 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10912 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10913
10914 /* 3com boards. */
10915 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10916 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10917 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10918 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10919 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10920
10921 /* DELL boards. */
10922 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10923 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10924 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10925 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10926
10927 /* Compaq boards. */
10928 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10929 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10930 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10931 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10932 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10933
10934 /* IBM boards. */
10935 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10936};
10937
10938static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10939{
10940 int i;
10941
10942 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10943 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10944 tp->pdev->subsystem_vendor) &&
10945 (subsys_id_to_phy_id[i].subsys_devid ==
10946 tp->pdev->subsystem_device))
10947 return &subsys_id_to_phy_id[i];
10948 }
10949 return NULL;
10950}
10951
7d0c41ef 10952static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10953{
1da177e4 10954 u32 val;
caf636c7
MC		 10955 u16 pmcsr;
10956
10957 /* On some early chips the SRAM cannot be accessed in D3hot state,
10958 * so need make sure we're in D0.
10959 */
10960 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10961 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10962 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10963 msleep(1);
7d0c41ef
MC		 10964
10965 /* Make sure register accesses (indirect or otherwise)
10966 * will function correctly.
10967 */
10968 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10969 tp->misc_host_ctrl);
1da177e4 10970
f49639e6
DM		 10971 /* The memory arbiter has to be enabled in order for SRAM accesses
10972 * to succeed. Normally on powerup the tg3 chip firmware will make
10973 * sure it is enabled, but other entities such as system netboot
10974 * code might disable it.
10975 */
10976 val = tr32(MEMARB_MODE);
10977 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10978
1da177e4 10979 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10980 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10981
a85feb8c
GZ		 10982 /* Assume an onboard device and WOL capable by default. */
10983 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10984
b5d3772c 10985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10986 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10987 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10988 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10989 }
0527ba35
MC		 10990 val = tr32(VCPU_CFGSHDW);
10991 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 10992 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 10993 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 10994 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 10995 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 10996 goto done;
b5d3772c
MC		 10997 }
10998
1da177e4
LT		 10999 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11000 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11001 u32 nic_cfg, led_cfg;
a9daf367 11002 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11003 int eeprom_phy_serdes = 0;
1da177e4
LT		 11004
11005 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11006 tp->nic_sram_data_cfg = nic_cfg;
11007
11008 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11009 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11010 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11011 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11012 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11013 (ver > 0) && (ver < 0x100))
11014 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11015
a9daf367
MC		 11016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11017 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11018
1da177e4
LT		 11019 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11020 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11021 eeprom_phy_serdes = 1;
11022
11023 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11024 if (nic_phy_id != 0) {
11025 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11026 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11027
11028 eeprom_phy_id = (id1 >> 16) << 10;
11029 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11030 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11031 } else
11032 eeprom_phy_id = 0;
11033
7d0c41ef 11034 tp->phy_id = eeprom_phy_id;
747e8f8b 11035 if (eeprom_phy_serdes) {
a4e2b347 11036 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11037 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11038 else
11039 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11040 }
7d0c41ef 11041
cbf46853 11042 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11043 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11044 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11045 else
1da177e4
LT		 11046 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11047
11048 switch (led_cfg) {
11049 default:
11050 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11051 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11052 break;
11053
11054 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11055 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11056 break;
11057
11058 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11059 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11060
11061 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11062 * read on some older 5700/5701 bootcode.
11063 */
11064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11065 ASIC_REV_5700 ||
11066 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11067 ASIC_REV_5701)
11068 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11069
1da177e4
LT		 11070 break;
11071
11072 case SHASTA_EXT_LED_SHARED:
11073 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11074 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11075 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11076 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11077 LED_CTRL_MODE_PHY_2);
11078 break;
11079
11080 case SHASTA_EXT_LED_MAC:
11081 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11082 break;
11083
11084 case SHASTA_EXT_LED_COMBO:
11085 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11086 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11087 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11088 LED_CTRL_MODE_PHY_2);
11089 break;
11090
855e1111 11091 }
1da177e4
LT		 11092
11093 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11094 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11095 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11096 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11097
b2a5c19c
MC		 11098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11099 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11100
9d26e213 11101 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11102 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11103 if ((tp->pdev->subsystem_vendor ==
11104 PCI_VENDOR_ID_ARIMA) &&
11105 (tp->pdev->subsystem_device == 0x205a ||
11106 tp->pdev->subsystem_device == 0x2063))
11107 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11108 } else {
f49639e6 11109 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11110 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11111 }
1da177e4
LT		 11112
11113 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11114 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11115 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11116 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11117 }
b2b98d4a
MC		 11118
11119 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11120 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11121 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11122
a85feb8c
GZ		 11123 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11124 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11125 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11126
12dac075 11127 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11128 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11129 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11130
1da177e4
LT		 11131 if (cfg2 & (1 << 17))
11132 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11133
11134 /* serdes signal pre-emphasis in register 0x590 set by */
11135 /* bootcode if bit 18 is set */
11136 if (cfg2 & (1 << 18))
11137 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11138
321d32a0
MC		 11139 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11140 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11141 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11142 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11143
8ed5d97e
MC		 11144 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11145 u32 cfg3;
11146
11147 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11148 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11149 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11150 }
a9daf367
MC		 11151
11152 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11153 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11154 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11155 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11156 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11157 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11158 }
05ac4cb7
MC		 11159done:
11160 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11161 device_set_wakeup_enable(&tp->pdev->dev,
11162 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11163}
11164
b2a5c19c
MC		 11165static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11166{
11167 int i;
11168 u32 val;
11169
11170 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11171 tw32(OTP_CTRL, cmd);
11172
11173 /* Wait for up to 1 ms for command to execute. */
11174 for (i = 0; i < 100; i++) {
11175 val = tr32(OTP_STATUS);
11176 if (val & OTP_STATUS_CMD_DONE)
11177 break;
11178 udelay(10);
11179 }
11180
11181 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11182}
11183
11184/* Read the gphy configuration from the OTP region of the chip. The gphy
11185 * configuration is a 32-bit value that straddles the alignment boundary.
11186 * We do two 32-bit reads and then shift and merge the results.
11187 */
11188static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11189{
11190 u32 bhalf_otp, thalf_otp;
11191
11192 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11193
11194 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11195 return 0;
11196
11197 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11198
11199 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11200 return 0;
11201
11202 thalf_otp = tr32(OTP_READ_DATA);
11203
11204 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11205
11206 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11207 return 0;
11208
11209 bhalf_otp = tr32(OTP_READ_DATA);
11210
11211 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11212}
11213
7d0c41ef
MC		 11214static int __devinit tg3_phy_probe(struct tg3 *tp)
11215{
11216 u32 hw_phy_id_1, hw_phy_id_2;
11217 u32 hw_phy_id, hw_phy_id_masked;
11218 int err;
1da177e4 11219
b02fd9e3
MC		 11220 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11221 return tg3_phy_init(tp);
11222
1da177e4
LT		 11223 /* Reading the PHY ID register can conflict with ASF
11224 * firwmare access to the PHY hardware.
11225 */
11226 err = 0;
0d3031d9
MC		 11227 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11228 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11229 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11230 } else {
11231 /* Now read the physical PHY_ID from the chip and verify
11232 * that it is sane. If it doesn't look good, we fall back
11233 * to either the hard-coded table based PHY_ID and failing
11234 * that the value found in the eeprom area.
11235 */
11236 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11237 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11238
11239 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11240 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11241 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11242
11243 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11244 }
11245
11246 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11247 tp->phy_id = hw_phy_id;
11248 if (hw_phy_id_masked == PHY_ID_BCM8002)
11249 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11250 else
11251 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11252 } else {
7d0c41ef
MC		 11253 if (tp->phy_id != PHY_ID_INVALID) {
11254 /* Do nothing, phy ID already set up in
11255 * tg3_get_eeprom_hw_cfg().
11256 */
1da177e4
LT		 11257 } else {
11258 struct subsys_tbl_ent *p;
11259
11260 /* No eeprom signature? Try the hardcoded
11261 * subsys device table.
11262 */
11263 p = lookup_by_subsys(tp);
11264 if (!p)
11265 return -ENODEV;
11266
11267 tp->phy_id = p->phy_id;
11268 if (!tp->phy_id ||
11269 tp->phy_id == PHY_ID_BCM8002)
11270 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11271 }
11272 }
11273
747e8f8b 11274 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11275 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11276 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11277 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11278
11279 tg3_readphy(tp, MII_BMSR, &bmsr);
11280 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11281 (bmsr & BMSR_LSTATUS))
11282 goto skip_phy_reset;
6aa20a22 11283
1da177e4
LT		 11284 err = tg3_phy_reset(tp);
11285 if (err)
11286 return err;
11287
11288 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11289 ADVERTISE_100HALF | ADVERTISE_100FULL |
11290 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11291 tg3_ctrl = 0;
11292 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11293 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11294 MII_TG3_CTRL_ADV_1000_FULL);
11295 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11296 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11297 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11298 MII_TG3_CTRL_ENABLE_AS_MASTER);
11299 }
11300
3600d918
MC		 11301 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11302 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11303 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11304 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11305 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11306
11307 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11308 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11309
11310 tg3_writephy(tp, MII_BMCR,
11311 BMCR_ANENABLE | BMCR_ANRESTART);
11312 }
11313 tg3_phy_set_wirespeed(tp);
11314
11315 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11316 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11317 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11318 }
11319
11320skip_phy_reset:
11321 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11322 err = tg3_init_5401phy_dsp(tp);
11323 if (err)
11324 return err;
11325 }
11326
11327 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11328 err = tg3_init_5401phy_dsp(tp);
11329 }
11330
747e8f8b 11331 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11332 tp->link_config.advertising =
11333 (ADVERTISED_1000baseT_Half |
11334 ADVERTISED_1000baseT_Full |
11335 ADVERTISED_Autoneg |
11336 ADVERTISED_FIBRE);
11337 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11338 tp->link_config.advertising &=
11339 ~(ADVERTISED_1000baseT_Half |
11340 ADVERTISED_1000baseT_Full);
11341
11342 return err;
11343}
11344
11345static void __devinit tg3_read_partno(struct tg3 *tp)
11346{
11347 unsigned char vpd_data[256];
af2c6a4a 11348 unsigned int i;
1b27777a 11349 u32 magic;
1da177e4 11350
e4f34110 11351 if (tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11352 goto out_not_found;
1da177e4 11353
1820180b 11354 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11355 for (i = 0; i < 256; i += 4) {
11356 u32 tmp;
1da177e4 11357
e4f34110 11358 if (tg3_nvram_read_swab(tp, 0x100 + i, &tmp))
1b27777a
MC		 11359 goto out_not_found;
11360
11361 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11362 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11363 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11364 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11365 }
11366 } else {
11367 int vpd_cap;
11368
11369 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11370 for (i = 0; i < 256; i += 4) {
11371 u32 tmp, j = 0;
b9fc7dc5 11372 __le32 v;
1b27777a
MC		 11373 u16 tmp16;
11374
11375 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11376 i);
11377 while (j++ < 100) {
11378 pci_read_config_word(tp->pdev, vpd_cap +
11379 PCI_VPD_ADDR, &tmp16);
11380 if (tmp16 & 0x8000)
11381 break;
11382 msleep(1);
11383 }
f49639e6
DM		 11384 if (!(tmp16 & 0x8000))
11385 goto out_not_found;
11386
1b27777a
MC		 11387 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11388 &tmp);
b9fc7dc5
AV		 11389 v = cpu_to_le32(tmp);
11390 memcpy(&vpd_data[i], &v, 4);
1b27777a 11391 }
1da177e4
LT		 11392 }
11393
11394 /* Now parse and find the part number. */
af2c6a4a 11395 for (i = 0; i < 254; ) {
1da177e4 11396 unsigned char val = vpd_data[i];
af2c6a4a 11397 unsigned int block_end;
1da177e4
LT		 11398
11399 if (val == 0x82 || val == 0x91) {
11400 i = (i + 3 +
11401 (vpd_data[i + 1] +
11402 (vpd_data[i + 2] << 8)));
11403 continue;
11404 }
11405
11406 if (val != 0x90)
11407 goto out_not_found;
11408
11409 block_end = (i + 3 +
11410 (vpd_data[i + 1] +
11411 (vpd_data[i + 2] << 8)));
11412 i += 3;
af2c6a4a
MC		 11413
11414 if (block_end > 256)
11415 goto out_not_found;
11416
11417 while (i < (block_end - 2)) {
1da177e4
LT		 11418 if (vpd_data[i + 0] == 'P' &&
11419 vpd_data[i + 1] == 'N') {
11420 int partno_len = vpd_data[i + 2];
11421
af2c6a4a
MC		 11422 i += 3;
11423 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11424 goto out_not_found;
11425
11426 memcpy(tp->board_part_number,
af2c6a4a 11427 &vpd_data[i], partno_len);
1da177e4
LT		 11428
11429 /* Success. */
11430 return;
11431 }
af2c6a4a 11432 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11433 }
11434
11435 /* Part number not found. */
11436 goto out_not_found;
11437 }
11438
11439out_not_found:
b5d3772c
MC		 11440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11441 strcpy(tp->board_part_number, "BCM95906");
11442 else
11443 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11444}
11445
9c8a620e
MC		 11446static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11447{
11448 u32 val;
11449
e4f34110 11450 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11451 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11452 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11453 val != 0)
11454 return 0;
11455
11456 return 1;
11457}
11458
dfe00d7d
MC		 11459static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11460{
11461 u32 offset, major, minor, build;
11462
11463 tp->fw_ver[0] = 's';
11464 tp->fw_ver[1] = 'b';
11465 tp->fw_ver[2] = '\0';
11466
11467 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11468 return;
11469
11470 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11471 case TG3_EEPROM_SB_REVISION_0:
11472 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11473 break;
11474 case TG3_EEPROM_SB_REVISION_2:
11475 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11476 break;
11477 case TG3_EEPROM_SB_REVISION_3:
11478 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11479 break;
11480 default:
11481 return;
11482 }
11483
e4f34110 11484 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11485 return;
11486
11487 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11488 TG3_EEPROM_SB_EDH_BLD_SHFT;
11489 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11490 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11491 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11492
11493 if (minor > 99 || build > 26)
11494 return;
11495
11496 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11497
11498 if (build > 0) {
11499 tp->fw_ver[8] = 'a' + build - 1;
11500 tp->fw_ver[9] = '\0';
11501 }
11502}
11503
c4e6575c
MC		 11504static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11505{
11506 u32 val, offset, start;
9c8a620e
MC		 11507 u32 ver_offset;
11508 int i, bcnt;
c4e6575c 11509
e4f34110 11510 if (tg3_nvram_read(tp, 0, &val))
c4e6575c
MC		 11511 return;
11512
dfe00d7d
MC		 11513 if (val != TG3_EEPROM_MAGIC) {
11514 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11515 tg3_read_sb_ver(tp, val);
11516
c4e6575c 11517 return;
dfe00d7d 11518 }
c4e6575c 11519
e4f34110
MC		 11520 if (tg3_nvram_read(tp, 0xc, &offset) ||
11521 tg3_nvram_read(tp, 0x4, &start))
c4e6575c
MC		 11522 return;
11523
11524 offset = tg3_nvram_logical_addr(tp, offset);
9c8a620e
MC		 11525
11526 if (!tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11527 tg3_nvram_read(tp, offset + 8, &ver_offset))
c4e6575c
MC		 11528 return;
11529
9c8a620e
MC		 11530 offset = offset + ver_offset - start;
11531 for (i = 0; i < 16; i += 4) {
b9fc7dc5
AV		 11532 __le32 v;
11533 if (tg3_nvram_read_le(tp, offset + i, &v))
9c8a620e
MC		 11534 return;
11535
b9fc7dc5 11536 memcpy(tp->fw_ver + i, &v, 4);
9c8a620e 11537 }
c4e6575c 11538
9c8a620e 11539 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
84af67fd 11540 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
9c8a620e
MC		 11541 return;
11542
11543 for (offset = TG3_NVM_DIR_START;
11544 offset < TG3_NVM_DIR_END;
11545 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11546 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11547 return;
11548
9c8a620e
MC		 11549 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11550 break;
11551 }
11552
11553 if (offset == TG3_NVM_DIR_END)
11554 return;
11555
11556 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11557 start = 0x08000000;
e4f34110 11558 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11559 return;
11560
e4f34110 11561 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11562 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11563 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11564 return;
11565
11566 offset += val - start;
11567
11568 bcnt = strlen(tp->fw_ver);
11569
11570 tp->fw_ver[bcnt++] = ',';
11571 tp->fw_ver[bcnt++] = ' ';
11572
11573 for (i = 0; i < 4; i++) {
b9fc7dc5
AV		 11574 __le32 v;
11575 if (tg3_nvram_read_le(tp, offset, &v))
c4e6575c
MC		 11576 return;
11577
b9fc7dc5 11578 offset += sizeof(v);
c4e6575c 11579
b9fc7dc5
AV		 11580 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11581 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
9c8a620e 11582 break;
c4e6575c 11583 }
9c8a620e 11584
b9fc7dc5
AV		 11585 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11586 bcnt += sizeof(v);
c4e6575c 11587 }
9c8a620e
MC		 11588
11589 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11590}
11591
7544b097
MC		 11592static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11593
1da177e4
LT		 11594static int __devinit tg3_get_invariants(struct tg3 *tp)
11595{
11596 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11597 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11598 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11599 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11600 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11601 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11602 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11603 { },
11604 };
11605 u32 misc_ctrl_reg;
1da177e4
LT		 11606 u32 pci_state_reg, grc_misc_cfg;
11607 u32 val;
11608 u16 pci_cmd;
5e7dfd0f 11609 int err;
1da177e4 11610
1da177e4
LT		 11611 /* Force memory write invalidate off. If we leave it on,
11612 * then on 5700_BX chips we have to enable a workaround.
11613 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11614 * to match the cacheline size. The Broadcom driver have this
11615 * workaround but turns MWI off all the times so never uses
11616 * it. This seems to suggest that the workaround is insufficient.
11617 */
11618 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11619 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11620 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11621
11622 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11623 * has the register indirect write enable bit set before
11624 * we try to access any of the MMIO registers. It is also
11625 * critical that the PCI-X hw workaround situation is decided
11626 * before that as well.
11627 */
11628 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11629 &misc_ctrl_reg);
11630
11631 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11632 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11634 u32 prod_id_asic_rev;
11635
11636 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11637 &prod_id_asic_rev);
321d32a0 11638 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11639 }
1da177e4 11640
ff645bec
MC		 11641 /* Wrong chip ID in 5752 A0. This code can be removed later
11642 * as A0 is not in production.
11643 */
11644 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11645 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11646
6892914f
MC		 11647 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11648 * we need to disable memory and use config. cycles
11649 * only to access all registers. The 5702/03 chips
11650 * can mistakenly decode the special cycles from the
11651 * ICH chipsets as memory write cycles, causing corruption
11652 * of register and memory space. Only certain ICH bridges
11653 * will drive special cycles with non-zero data during the
11654 * address phase which can fall within the 5703's address
11655 * range. This is not an ICH bug as the PCI spec allows
11656 * non-zero address during special cycles. However, only
11657 * these ICH bridges are known to drive non-zero addresses
11658 * during special cycles.
11659 *
11660 * Since special cycles do not cross PCI bridges, we only
11661 * enable this workaround if the 5703 is on the secondary
11662 * bus of these ICH bridges.
11663 */
11664 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11665 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11666 static struct tg3_dev_id {
11667 u32 vendor;
11668 u32 device;
11669 u32 rev;
11670 } ich_chipsets[] = {
11671 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11672 PCI_ANY_ID },
11673 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11674 PCI_ANY_ID },
11675 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11676 0xa },
11677 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11678 PCI_ANY_ID },
11679 { },
11680 };
11681 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11682 struct pci_dev *bridge = NULL;
11683
11684 while (pci_id->vendor != 0) {
11685 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11686 bridge);
11687 if (!bridge) {
11688 pci_id++;
11689 continue;
11690 }
11691 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11692 if (bridge->revision > pci_id->rev)
6892914f
MC		 11693 continue;
11694 }
11695 if (bridge->subordinate &&
11696 (bridge->subordinate->number ==
11697 tp->pdev->bus->number)) {
11698
11699 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11700 pci_dev_put(bridge);
11701 break;
11702 }
11703 }
11704 }
11705
41588ba1
MC		 11706 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11707 static struct tg3_dev_id {
11708 u32 vendor;
11709 u32 device;
11710 } bridge_chipsets[] = {
11711 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11712 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11713 { },
11714 };
11715 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11716 struct pci_dev *bridge = NULL;
11717
11718 while (pci_id->vendor != 0) {
11719 bridge = pci_get_device(pci_id->vendor,
11720 pci_id->device,
11721 bridge);
11722 if (!bridge) {
11723 pci_id++;
11724 continue;
11725 }
11726 if (bridge->subordinate &&
11727 (bridge->subordinate->number <=
11728 tp->pdev->bus->number) &&
11729 (bridge->subordinate->subordinate >=
11730 tp->pdev->bus->number)) {
11731 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11732 pci_dev_put(bridge);
11733 break;
11734 }
11735 }
11736 }
11737
4a29cc2e
MC		 11738 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11739 * DMA addresses > 40-bit. This bridge may have other additional
11740 * 57xx devices behind it in some 4-port NIC designs for example.
11741 * Any tg3 device found behind the bridge will also need the 40-bit
11742 * DMA workaround.
11743 */
a4e2b347
MC		 11744 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11746 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11747 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11748 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11749 }
4a29cc2e
MC		 11750 else {
11751 struct pci_dev *bridge = NULL;
11752
11753 do {
11754 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11755 PCI_DEVICE_ID_SERVERWORKS_EPB,
11756 bridge);
11757 if (bridge && bridge->subordinate &&
11758 (bridge->subordinate->number <=
11759 tp->pdev->bus->number) &&
11760 (bridge->subordinate->subordinate >=
11761 tp->pdev->bus->number)) {
11762 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11763 pci_dev_put(bridge);
11764 break;
11765 }
11766 } while (bridge);
11767 }
4cf78e4f 11768
1da177e4
LT		 11769 /* Initialize misc host control in PCI block. */
11770 tp->misc_host_ctrl |= (misc_ctrl_reg &
11771 MISC_HOST_CTRL_CHIPREV);
11772 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11773 tp->misc_host_ctrl);
11774
7544b097
MC		 11775 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11776 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11777 tp->pdev_peer = tg3_find_peer(tp);
11778
321d32a0
MC		 11779 /* Intentionally exclude ASIC_REV_5906 */
11780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11782 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11783 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11784 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11785 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11786 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11787
11788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11790 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11791 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11792 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11793 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11794
1b440c56
JL		 11795 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11796 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11797 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11798
027455ad
MC		 11799 /* 5700 B0 chips do not support checksumming correctly due
11800 * to hardware bugs.
11801 */
11802 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11803 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11804 else {
11805 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11806 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11807 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11808 tp->dev->features |= NETIF_F_IPV6_CSUM;
11809 }
11810
5a6f3074 11811 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11812 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11813 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11814 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11815 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11816 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11817 tp->pdev_peer == tp->pdev))
11818 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11819
321d32a0 11820 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 11821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11822 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11823 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11824 } else {
7f62ad5d 11825 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11826 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11827 ASIC_REV_5750 &&
11828 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11829 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11830 }
5a6f3074 11831 }
1da177e4 11832
f51f3562
MC		 11833 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11834 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 11835 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11836
52f4490c
MC		 11837 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11838 &pci_state_reg);
11839
5e7dfd0f
MC		 11840 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11841 if (tp->pcie_cap != 0) {
11842 u16 lnkctl;
11843
1da177e4 11844 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11845
11846 pcie_set_readrq(tp->pdev, 4096);
11847
5e7dfd0f
MC		 11848 pci_read_config_word(tp->pdev,
11849 tp->pcie_cap + PCI_EXP_LNKCTL,
11850 &lnkctl);
11851 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 11853 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 11854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 11855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11856 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
5e7dfd0f 11857 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 11858 }
52f4490c 11859 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 11860 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 11861 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11862 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11863 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11864 if (!tp->pcix_cap) {
11865 printk(KERN_ERR PFX "Cannot find PCI-X "
11866 "capability, aborting.\n");
11867 return -EIO;
11868 }
11869
11870 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11871 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11872 }
1da177e4 11873
399de50b
MC		 11874 /* If we have an AMD 762 or VIA K8T800 chipset, write
11875 * reordering to the mailbox registers done by the host
11876 * controller can cause major troubles. We read back from
11877 * every mailbox register write to force the writes to be
11878 * posted to the chip in order.
11879 */
11880 if (pci_dev_present(write_reorder_chipsets) &&
11881 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11882 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11883
69fc4053
MC		 11884 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11885 &tp->pci_cacheline_sz);
11886 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11887 &tp->pci_lat_timer);
1da177e4
LT		 11888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11889 tp->pci_lat_timer < 64) {
11890 tp->pci_lat_timer = 64;
69fc4053
MC		 11891 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11892 tp->pci_lat_timer);
1da177e4
LT		 11893 }
11894
52f4490c
MC		 11895 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11896 /* 5700 BX chips need to have their TX producer index
11897 * mailboxes written twice to workaround a bug.
11898 */
11899 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 11900
52f4490c 11901 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 11902 *
11903 * The workaround is to use indirect register accesses
11904 * for all chip writes not to mailbox registers.
11905 */
52f4490c 11906 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 11907 u32 pm_reg;
1da177e4
LT		 11908
11909 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11910
11911 /* The chip can have it's power management PCI config
11912 * space registers clobbered due to this bug.
11913 * So explicitly force the chip into D0 here.
11914 */
9974a356
MC		 11915 pci_read_config_dword(tp->pdev,
11916 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11917 &pm_reg);
11918 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11919 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 11920 pci_write_config_dword(tp->pdev,
11921 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11922 pm_reg);
11923
11924 /* Also, force SERR#/PERR# in PCI command. */
11925 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11926 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11927 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11928 }
11929 }
11930
1da177e4
LT		 11931 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11932 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11933 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11934 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11935
11936 /* Chip-specific fixup from Broadcom driver */
11937 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11938 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11939 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11940 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11941 }
11942
1ee582d8 11943 /* Default fast path register access methods */
20094930 11944 tp->read32 = tg3_read32;
1ee582d8 11945 tp->write32 = tg3_write32;
09ee929c 11946 tp->read32_mbox = tg3_read32;
20094930 11947 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 11948 tp->write32_tx_mbox = tg3_write32;
11949 tp->write32_rx_mbox = tg3_write32;
11950
11951 /* Various workaround register access methods */
11952 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11953 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 11954 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11955 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11956 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11957 /*
11958 * Back to back register writes can cause problems on these
11959 * chips, the workaround is to read back all reg writes
11960 * except those to mailbox regs.
11961 *
11962 * See tg3_write_indirect_reg32().
11963 */
1ee582d8 11964 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 11965 }
11966
1ee582d8
MC		 11967
11968 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11969 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11970 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11971 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11972 tp->write32_rx_mbox = tg3_write_flush_reg32;
11973 }
20094930 11974
6892914f
MC		 11975 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11976 tp->read32 = tg3_read_indirect_reg32;
11977 tp->write32 = tg3_write_indirect_reg32;
11978 tp->read32_mbox = tg3_read_indirect_mbox;
11979 tp->write32_mbox = tg3_write_indirect_mbox;
11980 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11981 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11982
11983 iounmap(tp->regs);
22abe310 11984 tp->regs = NULL;
6892914f
MC		 11985
11986 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11987 pci_cmd &= ~PCI_COMMAND_MEMORY;
11988 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11989 }
b5d3772c
MC		 11990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11991 tp->read32_mbox = tg3_read32_mbox_5906;
11992 tp->write32_mbox = tg3_write32_mbox_5906;
11993 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11994 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11995 }
6892914f 11996
bbadf503
MC		 11997 if (tp->write32 == tg3_write_indirect_reg32 ||
11998 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11999 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12001 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12002
7d0c41ef 12003 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12004 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12005 * determined before calling tg3_set_power_state() so that
12006 * we know whether or not to switch out of Vaux power.
12007 * When the flag is set, it means that GPIO1 is used for eeprom
12008 * write protect and also implies that it is a LOM where GPIOs
12009 * are not used to switch power.
6aa20a22 12010 */
7d0c41ef
MC		 12011 tg3_get_eeprom_hw_cfg(tp);
12012
0d3031d9
MC		 12013 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12014 /* Allow reads and writes to the
12015 * APE register and memory space.
12016 */
12017 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12018 PCISTATE_ALLOW_APE_SHMEM_WR;
12019 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12020 pci_state_reg);
12021 }
12022
9936bcf6 12023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12027 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12028
314fba34
MC		 12029 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12030 * GPIO1 driven high will bring 5700's external PHY out of reset.
12031 * It is also used as eeprom write protect on LOMs.
12032 */
12033 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12034 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12035 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12036 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12037 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12038 /* Unused GPIO3 must be driven as output on 5752 because there
12039 * are no pull-up resistors on unused GPIO pins.
12040 */
12041 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12042 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12043
321d32a0
MC		 12044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12046 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12047
5f0c4a3c
MC		 12048 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12049 /* Turn off the debug UART. */
12050 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12051 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12052 /* Keep VMain power. */
12053 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12054 GRC_LCLCTRL_GPIO_OUTPUT0;
12055 }
12056
1da177e4 12057 /* Force the chip into D0. */
bc1c7567 12058 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12059 if (err) {
12060 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12061 pci_name(tp->pdev));
12062 return err;
12063 }
12064
1da177e4
LT		 12065 /* Derive initial jumbo mode from MTU assigned in
12066 * ether_setup() via the alloc_etherdev() call
12067 */
0f893dc6 12068 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12069 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12070 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12071
12072 /* Determine WakeOnLan speed to use. */
12073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12074 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12075 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12076 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12077 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12078 } else {
12079 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12080 }
12081
12082 /* A few boards don't want Ethernet@WireSpeed phy feature */
12083 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12084 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12085 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12086 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12087 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12088 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12089 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12090
12091 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12092 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12093 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12094 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12095 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12096
321d32a0
MC		 12097 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12098 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12099 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12100 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12105 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12106 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12107 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12108 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12109 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12110 } else
c424cb24
MC		 12111 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12112 }
1da177e4 12113
b2a5c19c
MC		 12114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12115 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12116 tp->phy_otp = tg3_read_otp_phycfg(tp);
12117 if (tp->phy_otp == 0)
12118 tp->phy_otp = TG3_OTP_DEFAULT;
12119 }
12120
f51f3562 12121 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12122 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12123 else
12124 tp->mi_mode = MAC_MI_MODE_BASE;
12125
1da177e4 12126 tp->coalesce_mode = 0;
1da177e4
LT		 12127 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12128 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12129 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12130
321d32a0
MC		 12131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12133 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12134
158d7abd
MC		 12135 err = tg3_mdio_init(tp);
12136 if (err)
12137 return err;
1da177e4
LT		 12138
12139 /* Initialize data/descriptor byte/word swapping. */
12140 val = tr32(GRC_MODE);
12141 val &= GRC_MODE_HOST_STACKUP;
12142 tw32(GRC_MODE, val | tp->grc_mode);
12143
12144 tg3_switch_clocks(tp);
12145
12146 /* Clear this out for sanity. */
12147 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12148
12149 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12150 &pci_state_reg);
12151 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12152 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12153 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12154
12155 if (chiprevid == CHIPREV_ID_5701_A0 ||
12156 chiprevid == CHIPREV_ID_5701_B0 ||
12157 chiprevid == CHIPREV_ID_5701_B2 ||
12158 chiprevid == CHIPREV_ID_5701_B5) {
12159 void __iomem *sram_base;
12160
12161 /* Write some dummy words into the SRAM status block
12162 * area, see if it reads back correctly. If the return
12163 * value is bad, force enable the PCIX workaround.
12164 */
12165 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12166
12167 writel(0x00000000, sram_base);
12168 writel(0x00000000, sram_base + 4);
12169 writel(0xffffffff, sram_base + 4);
12170 if (readl(sram_base) != 0x00000000)
12171 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12172 }
12173 }
12174
12175 udelay(50);
12176 tg3_nvram_init(tp);
12177
12178 grc_misc_cfg = tr32(GRC_MISC_CFG);
12179 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12180
1da177e4
LT		 12181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12182 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12183 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12184 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12185
fac9b83e
DM		 12186 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12187 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12188 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12189 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12190 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12191 HOSTCC_MODE_CLRTICK_TXBD);
12192
12193 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12194 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12195 tp->misc_host_ctrl);
12196 }
12197
3bda1258
MC		 12198 /* Preserve the APE MAC_MODE bits */
12199 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12200 tp->mac_mode = tr32(MAC_MODE) |
12201 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12202 else
12203 tp->mac_mode = TG3_DEF_MAC_MODE;
12204
1da177e4
LT		 12205 /* these are limited to 10/100 only */
12206 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12207 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12209 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12210 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12211 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12212 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12213 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12214 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12215 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12216 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12217 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12219 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12220
12221 err = tg3_phy_probe(tp);
12222 if (err) {
12223 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12224 pci_name(tp->pdev), err);
12225 /* ... but do not return immediately ... */
b02fd9e3 12226 tg3_mdio_fini(tp);
1da177e4
LT		 12227 }
12228
12229 tg3_read_partno(tp);
c4e6575c 12230 tg3_read_fw_ver(tp);
1da177e4
LT		 12231
12232 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12233 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12234 } else {
12235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12236 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12237 else
12238 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12239 }
12240
12241 /* 5700 {AX,BX} chips have a broken status block link
12242 * change bit implementation, so we must use the
12243 * status register in those cases.
12244 */
12245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12246 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12247 else
12248 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12249
12250 /* The led_ctrl is set during tg3_phy_probe, here we might
12251 * have to force the link status polling mechanism based
12252 * upon subsystem IDs.
12253 */
12254 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12256 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12257 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12258 TG3_FLAG_USE_LINKCHG_REG);
12259 }
12260
12261 /* For all SERDES we poll the MAC status register. */
12262 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12263 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12264 else
12265 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12266
ad829268 12267 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12269 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12270 tp->rx_offset = 0;
12271
f92905de
MC		 12272 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12273
12274 /* Increment the rx prod index on the rx std ring by at most
12275 * 8 for these chips to workaround hw errata.
12276 */
12277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12278 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12279 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12280 tp->rx_std_max_post = 8;
12281
8ed5d97e
MC		 12282 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12283 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12284 PCIE_PWR_MGMT_L1_THRESH_MSK;
12285
1da177e4
LT		 12286 return err;
12287}
12288
49b6e95f 12289#ifdef CONFIG_SPARC
1da177e4
LT		 12290static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12291{
12292 struct net_device *dev = tp->dev;
12293 struct pci_dev *pdev = tp->pdev;
49b6e95f 12294 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12295 const unsigned char *addr;
49b6e95f
DM		 12296 int len;
12297
12298 addr = of_get_property(dp, "local-mac-address", &len);
12299 if (addr && len == 6) {
12300 memcpy(dev->dev_addr, addr, 6);
12301 memcpy(dev->perm_addr, dev->dev_addr, 6);
12302 return 0;
1da177e4
LT		 12303 }
12304 return -ENODEV;
12305}
12306
12307static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12308{
12309 struct net_device *dev = tp->dev;
12310
12311 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12312 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12313 return 0;
12314}
12315#endif
12316
12317static int __devinit tg3_get_device_address(struct tg3 *tp)
12318{
12319 struct net_device *dev = tp->dev;
12320 u32 hi, lo, mac_offset;
008652b3 12321 int addr_ok = 0;
1da177e4 12322
49b6e95f 12323#ifdef CONFIG_SPARC
1da177e4
LT		 12324 if (!tg3_get_macaddr_sparc(tp))
12325 return 0;
12326#endif
12327
12328 mac_offset = 0x7c;
f49639e6 12329 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12330 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12331 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12332 mac_offset = 0xcc;
12333 if (tg3_nvram_lock(tp))
12334 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12335 else
12336 tg3_nvram_unlock(tp);
12337 }
b5d3772c
MC		 12338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12339 mac_offset = 0x10;
1da177e4
LT		 12340
12341 /* First try to get it from MAC address mailbox. */
12342 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12343 if ((hi >> 16) == 0x484b) {
12344 dev->dev_addr[0] = (hi >> 8) & 0xff;
12345 dev->dev_addr[1] = (hi >> 0) & 0xff;
12346
12347 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12348 dev->dev_addr[2] = (lo >> 24) & 0xff;
12349 dev->dev_addr[3] = (lo >> 16) & 0xff;
12350 dev->dev_addr[4] = (lo >> 8) & 0xff;
12351 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12352
008652b3
MC		 12353 /* Some old bootcode may report a 0 MAC address in SRAM */
12354 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12355 }
12356 if (!addr_ok) {
12357 /* Next, try NVRAM. */
e4f34110
MC		 12358 if (!tg3_nvram_read_swab(tp, mac_offset + 0, &hi) &&
12359 !tg3_nvram_read_swab(tp, mac_offset + 4, &lo)) {
008652b3
MC		 12360 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12361 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12362 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12363 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12364 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12365 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12366 }
12367 /* Finally just fetch it out of the MAC control regs. */
12368 else {
12369 hi = tr32(MAC_ADDR_0_HIGH);
12370 lo = tr32(MAC_ADDR_0_LOW);
12371
12372 dev->dev_addr[5] = lo & 0xff;
12373 dev->dev_addr[4] = (lo >> 8) & 0xff;
12374 dev->dev_addr[3] = (lo >> 16) & 0xff;
12375 dev->dev_addr[2] = (lo >> 24) & 0xff;
12376 dev->dev_addr[1] = hi & 0xff;
12377 dev->dev_addr[0] = (hi >> 8) & 0xff;
12378 }
1da177e4
LT		 12379 }
12380
12381 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12382#ifdef CONFIG_SPARC
1da177e4
LT		 12383 if (!tg3_get_default_macaddr_sparc(tp))
12384 return 0;
12385#endif
12386 return -EINVAL;
12387 }
2ff43697 12388 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12389 return 0;
12390}
12391
59e6b434
DM		 12392#define BOUNDARY_SINGLE_CACHELINE 1
12393#define BOUNDARY_MULTI_CACHELINE 2
12394
12395static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12396{
12397 int cacheline_size;
12398 u8 byte;
12399 int goal;
12400
12401 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12402 if (byte == 0)
12403 cacheline_size = 1024;
12404 else
12405 cacheline_size = (int) byte * 4;
12406
12407 /* On 5703 and later chips, the boundary bits have no
12408 * effect.
12409 */
12410 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12411 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12412 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12413 goto out;
12414
12415#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12416 goal = BOUNDARY_MULTI_CACHELINE;
12417#else
12418#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12419 goal = BOUNDARY_SINGLE_CACHELINE;
12420#else
12421 goal = 0;
12422#endif
12423#endif
12424
12425 if (!goal)
12426 goto out;
12427
12428 /* PCI controllers on most RISC systems tend to disconnect
12429 * when a device tries to burst across a cache-line boundary.
12430 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12431 *
12432 * Unfortunately, for PCI-E there are only limited
12433 * write-side controls for this, and thus for reads
12434 * we will still get the disconnects. We'll also waste
12435 * these PCI cycles for both read and write for chips
12436 * other than 5700 and 5701 which do not implement the
12437 * boundary bits.
12438 */
12439 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12440 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12441 switch (cacheline_size) {
12442 case 16:
12443 case 32:
12444 case 64:
12445 case 128:
12446 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12447 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12448 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12449 } else {
12450 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12451 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12452 }
12453 break;
12454
12455 case 256:
12456 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12457 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12458 break;
12459
12460 default:
12461 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12462 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12463 break;
855e1111 12464 }
59e6b434
DM		 12465 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12466 switch (cacheline_size) {
12467 case 16:
12468 case 32:
12469 case 64:
12470 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12471 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12472 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12473 break;
12474 }
12475 /* fallthrough */
12476 case 128:
12477 default:
12478 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12479 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12480 break;
855e1111 12481 }
59e6b434
DM		 12482 } else {
12483 switch (cacheline_size) {
12484 case 16:
12485 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12486 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12487 DMA_RWCTRL_WRITE_BNDRY_16);
12488 break;
12489 }
12490 /* fallthrough */
12491 case 32:
12492 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12493 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12494 DMA_RWCTRL_WRITE_BNDRY_32);
12495 break;
12496 }
12497 /* fallthrough */
12498 case 64:
12499 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12500 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12501 DMA_RWCTRL_WRITE_BNDRY_64);
12502 break;
12503 }
12504 /* fallthrough */
12505 case 128:
12506 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12507 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12508 DMA_RWCTRL_WRITE_BNDRY_128);
12509 break;
12510 }
12511 /* fallthrough */
12512 case 256:
12513 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12514 DMA_RWCTRL_WRITE_BNDRY_256);
12515 break;
12516 case 512:
12517 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12518 DMA_RWCTRL_WRITE_BNDRY_512);
12519 break;
12520 case 1024:
12521 default:
12522 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12523 DMA_RWCTRL_WRITE_BNDRY_1024);
12524 break;
855e1111 12525 }
59e6b434
DM		 12526 }
12527
12528out:
12529 return val;
12530}
12531
1da177e4
LT		 12532static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12533{
12534 struct tg3_internal_buffer_desc test_desc;
12535 u32 sram_dma_descs;
12536 int i, ret;
12537
12538 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12539
12540 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12541 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12542 tw32(RDMAC_STATUS, 0);
12543 tw32(WDMAC_STATUS, 0);
12544
12545 tw32(BUFMGR_MODE, 0);
12546 tw32(FTQ_RESET, 0);
12547
12548 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12549 test_desc.addr_lo = buf_dma & 0xffffffff;
12550 test_desc.nic_mbuf = 0x00002100;
12551 test_desc.len = size;
12552
12553 /*
12554 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12555 * the *second* time the tg3 driver was getting loaded after an
12556 * initial scan.
12557 *
12558 * Broadcom tells me:
12559 * ...the DMA engine is connected to the GRC block and a DMA
12560 * reset may affect the GRC block in some unpredictable way...
12561 * The behavior of resets to individual blocks has not been tested.
12562 *
12563 * Broadcom noted the GRC reset will also reset all sub-components.
12564 */
12565 if (to_device) {
12566 test_desc.cqid_sqid = (13 << 8) | 2;
12567
12568 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12569 udelay(40);
12570 } else {
12571 test_desc.cqid_sqid = (16 << 8) | 7;
12572
12573 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12574 udelay(40);
12575 }
12576 test_desc.flags = 0x00000005;
12577
12578 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12579 u32 val;
12580
12581 val = *(((u32 *)&test_desc) + i);
12582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12583 sram_dma_descs + (i * sizeof(u32)));
12584 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12585 }
12586 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12587
12588 if (to_device) {
12589 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12590 } else {
12591 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12592 }
12593
12594 ret = -ENODEV;
12595 for (i = 0; i < 40; i++) {
12596 u32 val;
12597
12598 if (to_device)
12599 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12600 else
12601 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12602 if ((val & 0xffff) == sram_dma_descs) {
12603 ret = 0;
12604 break;
12605 }
12606
12607 udelay(100);
12608 }
12609
12610 return ret;
12611}
12612
ded7340d 12613#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12614
12615static int __devinit tg3_test_dma(struct tg3 *tp)
12616{
12617 dma_addr_t buf_dma;
59e6b434 12618 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12619 int ret;
12620
12621 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12622 if (!buf) {
12623 ret = -ENOMEM;
12624 goto out_nofree;
12625 }
12626
12627 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12628 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12629
59e6b434 12630 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12631
12632 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12633 /* DMA read watermark not used on PCIE */
12634 tp->dma_rwctrl |= 0x00180000;
12635 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12638 tp->dma_rwctrl |= 0x003f0000;
12639 else
12640 tp->dma_rwctrl |= 0x003f000f;
12641 } else {
12642 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12644 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12645 u32 read_water = 0x7;
1da177e4 12646
4a29cc2e
MC		 12647 /* If the 5704 is behind the EPB bridge, we can
12648 * do the less restrictive ONE_DMA workaround for
12649 * better performance.
12650 */
12651 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12653 tp->dma_rwctrl |= 0x8000;
12654 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12655 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12656
49afdeb6
MC		 12657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12658 read_water = 4;
59e6b434 12659 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12660 tp->dma_rwctrl |=
12661 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12662 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12663 (1 << 23);
4cf78e4f
MC		 12664 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12665 /* 5780 always in PCIX mode */
12666 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12667 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12668 /* 5714 always in PCIX mode */
12669 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12670 } else {
12671 tp->dma_rwctrl |= 0x001b000f;
12672 }
12673 }
12674
12675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12677 tp->dma_rwctrl &= 0xfffffff0;
12678
12679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12681 /* Remove this if it causes problems for some boards. */
12682 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12683
12684 /* On 5700/5701 chips, we need to set this bit.
12685 * Otherwise the chip will issue cacheline transactions
12686 * to streamable DMA memory with not all the byte
12687 * enables turned on. This is an error on several
12688 * RISC PCI controllers, in particular sparc64.
12689 *
12690 * On 5703/5704 chips, this bit has been reassigned
12691 * a different meaning. In particular, it is used
12692 * on those chips to enable a PCI-X workaround.
12693 */
12694 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12695 }
12696
12697 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12698
12699#if 0
12700 /* Unneeded, already done by tg3_get_invariants. */
12701 tg3_switch_clocks(tp);
12702#endif
12703
12704 ret = 0;
12705 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12706 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12707 goto out;
12708
59e6b434
DM		 12709 /* It is best to perform DMA test with maximum write burst size
12710 * to expose the 5700/5701 write DMA bug.
12711 */
12712 saved_dma_rwctrl = tp->dma_rwctrl;
12713 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12714 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12715
1da177e4
LT		 12716 while (1) {
12717 u32 *p = buf, i;
12718
12719 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12720 p[i] = i;
12721
12722 /* Send the buffer to the chip. */
12723 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12724 if (ret) {
12725 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12726 break;
12727 }
12728
12729#if 0
12730 /* validate data reached card RAM correctly. */
12731 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12732 u32 val;
12733 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12734 if (le32_to_cpu(val) != p[i]) {
12735 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12736 /* ret = -ENODEV here? */
12737 }
12738 p[i] = 0;
12739 }
12740#endif
12741 /* Now read it back. */
12742 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12743 if (ret) {
12744 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12745
12746 break;
12747 }
12748
12749 /* Verify it. */
12750 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12751 if (p[i] == i)
12752 continue;
12753
59e6b434
DM		 12754 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12755 DMA_RWCTRL_WRITE_BNDRY_16) {
12756 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12757 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12758 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12759 break;
12760 } else {
12761 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12762 ret = -ENODEV;
12763 goto out;
12764 }
12765 }
12766
12767 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12768 /* Success. */
12769 ret = 0;
12770 break;
12771 }
12772 }
59e6b434
DM		 12773 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12774 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12775 static struct pci_device_id dma_wait_state_chipsets[] = {
12776 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12777 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12778 { },
12779 };
12780
59e6b434 12781 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12782 * now look for chipsets that are known to expose the
12783 * DMA bug without failing the test.
59e6b434 12784 */
6d1cfbab
MC		 12785 if (pci_dev_present(dma_wait_state_chipsets)) {
12786 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12787 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12788 }
12789 else
12790 /* Safe to use the calculated DMA boundary. */
12791 tp->dma_rwctrl = saved_dma_rwctrl;
12792
59e6b434
DM		 12793 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12794 }
1da177e4
LT		 12795
12796out:
12797 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12798out_nofree:
12799 return ret;
12800}
12801
12802static void __devinit tg3_init_link_config(struct tg3 *tp)
12803{
12804 tp->link_config.advertising =
12805 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12806 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12807 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12808 ADVERTISED_Autoneg | ADVERTISED_MII);
12809 tp->link_config.speed = SPEED_INVALID;
12810 tp->link_config.duplex = DUPLEX_INVALID;
12811 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12812 tp->link_config.active_speed = SPEED_INVALID;
12813 tp->link_config.active_duplex = DUPLEX_INVALID;
12814 tp->link_config.phy_is_low_power = 0;
12815 tp->link_config.orig_speed = SPEED_INVALID;
12816 tp->link_config.orig_duplex = DUPLEX_INVALID;
12817 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12818}
12819
12820static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12821{
fdfec172
MC		 12822 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12823 tp->bufmgr_config.mbuf_read_dma_low_water =
12824 DEFAULT_MB_RDMA_LOW_WATER_5705;
12825 tp->bufmgr_config.mbuf_mac_rx_low_water =
12826 DEFAULT_MB_MACRX_LOW_WATER_5705;
12827 tp->bufmgr_config.mbuf_high_water =
12828 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12829 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12830 tp->bufmgr_config.mbuf_mac_rx_low_water =
12831 DEFAULT_MB_MACRX_LOW_WATER_5906;
12832 tp->bufmgr_config.mbuf_high_water =
12833 DEFAULT_MB_HIGH_WATER_5906;
12834 }
fdfec172
MC		 12835
12836 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12837 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12838 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12839 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12840 tp->bufmgr_config.mbuf_high_water_jumbo =
12841 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12842 } else {
12843 tp->bufmgr_config.mbuf_read_dma_low_water =
12844 DEFAULT_MB_RDMA_LOW_WATER;
12845 tp->bufmgr_config.mbuf_mac_rx_low_water =
12846 DEFAULT_MB_MACRX_LOW_WATER;
12847 tp->bufmgr_config.mbuf_high_water =
12848 DEFAULT_MB_HIGH_WATER;
12849
12850 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12851 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12852 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12853 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12854 tp->bufmgr_config.mbuf_high_water_jumbo =
12855 DEFAULT_MB_HIGH_WATER_JUMBO;
12856 }
1da177e4
LT		 12857
12858 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12859 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12860}
12861
12862static char * __devinit tg3_phy_string(struct tg3 *tp)
12863{
12864 switch (tp->phy_id & PHY_ID_MASK) {
12865 case PHY_ID_BCM5400: return "5400";
12866 case PHY_ID_BCM5401: return "5401";
12867 case PHY_ID_BCM5411: return "5411";
12868 case PHY_ID_BCM5701: return "5701";
12869 case PHY_ID_BCM5703: return "5703";
12870 case PHY_ID_BCM5704: return "5704";
12871 case PHY_ID_BCM5705: return "5705";
12872 case PHY_ID_BCM5750: return "5750";
85e94ced 12873 case PHY_ID_BCM5752: return "5752";
a4e2b347 12874 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12875 case PHY_ID_BCM5780: return "5780";
af36e6b6 12876 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12877 case PHY_ID_BCM5787: return "5787";
d30cdd28 12878 case PHY_ID_BCM5784: return "5784";
126a3368 12879 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12880 case PHY_ID_BCM5906: return "5906";
9936bcf6 12881 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12882 case PHY_ID_BCM8002: return "8002/serdes";
12883 case 0: return "serdes";
12884 default: return "unknown";
855e1111 12885 }
1da177e4
LT		 12886}
12887
f9804ddb
MC		 12888static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12889{
12890 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12891 strcpy(str, "PCI Express");
12892 return str;
12893 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12894 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12895
12896 strcpy(str, "PCIX:");
12897
12898 if ((clock_ctrl == 7) ||
12899 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12900 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12901 strcat(str, "133MHz");
12902 else if (clock_ctrl == 0)
12903 strcat(str, "33MHz");
12904 else if (clock_ctrl == 2)
12905 strcat(str, "50MHz");
12906 else if (clock_ctrl == 4)
12907 strcat(str, "66MHz");
12908 else if (clock_ctrl == 6)
12909 strcat(str, "100MHz");
f9804ddb
MC		 12910 } else {
12911 strcpy(str, "PCI:");
12912 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12913 strcat(str, "66MHz");
12914 else
12915 strcat(str, "33MHz");
12916 }
12917 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12918 strcat(str, ":32-bit");
12919 else
12920 strcat(str, ":64-bit");
12921 return str;
12922}
12923
8c2dc7e1 12924static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 12925{
12926 struct pci_dev *peer;
12927 unsigned int func, devnr = tp->pdev->devfn & ~7;
12928
12929 for (func = 0; func < 8; func++) {
12930 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12931 if (peer && peer != tp->pdev)
12932 break;
12933 pci_dev_put(peer);
12934 }
16fe9d74
MC		 12935 /* 5704 can be configured in single-port mode, set peer to
12936 * tp->pdev in that case.
12937 */
12938 if (!peer) {
12939 peer = tp->pdev;
12940 return peer;
12941 }
1da177e4
LT		 12942
12943 /*
12944 * We don't need to keep the refcount elevated; there's no way
12945 * to remove one half of this device without removing the other
12946 */
12947 pci_dev_put(peer);
12948
12949 return peer;
12950}
12951
15f9850d
DM		 12952static void __devinit tg3_init_coal(struct tg3 *tp)
12953{
12954 struct ethtool_coalesce *ec = &tp->coal;
12955
12956 memset(ec, 0, sizeof(*ec));
12957 ec->cmd = ETHTOOL_GCOALESCE;
12958 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12959 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12960 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12961 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12962 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12963 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12964 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12965 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12966 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12967
12968 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12969 HOSTCC_MODE_CLRTICK_TXBD)) {
12970 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12971 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12972 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12973 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12974 }
d244c892
MC		 12975
12976 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12977 ec->rx_coalesce_usecs_irq = 0;
12978 ec->tx_coalesce_usecs_irq = 0;
12979 ec->stats_block_coalesce_usecs = 0;
12980 }
15f9850d
DM		 12981}
12982
7c7d64b8
SH		 12983static const struct net_device_ops tg3_netdev_ops = {
12984 .ndo_open = tg3_open,
12985 .ndo_stop = tg3_close,
00829823
SH		 12986 .ndo_start_xmit = tg3_start_xmit,
12987 .ndo_get_stats = tg3_get_stats,
12988 .ndo_validate_addr = eth_validate_addr,
12989 .ndo_set_multicast_list = tg3_set_rx_mode,
12990 .ndo_set_mac_address = tg3_set_mac_addr,
12991 .ndo_do_ioctl = tg3_ioctl,
12992 .ndo_tx_timeout = tg3_tx_timeout,
12993 .ndo_change_mtu = tg3_change_mtu,
12994#if TG3_VLAN_TAG_USED
12995 .ndo_vlan_rx_register = tg3_vlan_rx_register,
12996#endif
12997#ifdef CONFIG_NET_POLL_CONTROLLER
12998 .ndo_poll_controller = tg3_poll_controller,
12999#endif
13000};
13001
13002static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13003 .ndo_open = tg3_open,
13004 .ndo_stop = tg3_close,
13005 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13006 .ndo_get_stats = tg3_get_stats,
13007 .ndo_validate_addr = eth_validate_addr,
13008 .ndo_set_multicast_list = tg3_set_rx_mode,
13009 .ndo_set_mac_address = tg3_set_mac_addr,
13010 .ndo_do_ioctl = tg3_ioctl,
13011 .ndo_tx_timeout = tg3_tx_timeout,
13012 .ndo_change_mtu = tg3_change_mtu,
13013#if TG3_VLAN_TAG_USED
13014 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13015#endif
13016#ifdef CONFIG_NET_POLL_CONTROLLER
13017 .ndo_poll_controller = tg3_poll_controller,
13018#endif
13019};
13020
1da177e4
LT		 13021static int __devinit tg3_init_one(struct pci_dev *pdev,
13022 const struct pci_device_id *ent)
13023{
13024 static int tg3_version_printed = 0;
1da177e4
LT		 13025 struct net_device *dev;
13026 struct tg3 *tp;
d6645372 13027 int err, pm_cap;
f9804ddb 13028 char str[40];
72f2afb8 13029 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13030
13031 if (tg3_version_printed++ == 0)
13032 printk(KERN_INFO "%s", version);
13033
13034 err = pci_enable_device(pdev);
13035 if (err) {
13036 printk(KERN_ERR PFX "Cannot enable PCI device, "
13037 "aborting.\n");
13038 return err;
13039 }
13040
1da177e4
LT		 13041 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13042 if (err) {
13043 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13044 "aborting.\n");
13045 goto err_out_disable_pdev;
13046 }
13047
13048 pci_set_master(pdev);
13049
13050 /* Find power-management capability. */
13051 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13052 if (pm_cap == 0) {
13053 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13054 "aborting.\n");
13055 err = -EIO;
13056 goto err_out_free_res;
13057 }
13058
1da177e4
LT		 13059 dev = alloc_etherdev(sizeof(*tp));
13060 if (!dev) {
13061 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13062 err = -ENOMEM;
13063 goto err_out_free_res;
13064 }
13065
1da177e4
LT		 13066 SET_NETDEV_DEV(dev, &pdev->dev);
13067
1da177e4
LT		 13068#if TG3_VLAN_TAG_USED
13069 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13070#endif
13071
13072 tp = netdev_priv(dev);
13073 tp->pdev = pdev;
13074 tp->dev = dev;
13075 tp->pm_cap = pm_cap;
1da177e4
LT		 13076 tp->rx_mode = TG3_DEF_RX_MODE;
13077 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13078
1da177e4
LT		 13079 if (tg3_debug > 0)
13080 tp->msg_enable = tg3_debug;
13081 else
13082 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13083
13084 /* The word/byte swap controls here control register access byte
13085 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13086 * setting below.
13087 */
13088 tp->misc_host_ctrl =
13089 MISC_HOST_CTRL_MASK_PCI_INT |
13090 MISC_HOST_CTRL_WORD_SWAP |
13091 MISC_HOST_CTRL_INDIR_ACCESS |
13092 MISC_HOST_CTRL_PCISTATE_RW;
13093
13094 /* The NONFRM (non-frame) byte/word swap controls take effect
13095 * on descriptor entries, anything which isn't packet data.
13096 *
13097 * The StrongARM chips on the board (one for tx, one for rx)
13098 * are running in big-endian mode.
13099 */
13100 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13101 GRC_MODE_WSWAP_NONFRM_DATA);
13102#ifdef __BIG_ENDIAN
13103 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13104#endif
13105 spin_lock_init(&tp->lock);
1da177e4 13106 spin_lock_init(&tp->indirect_lock);
c4028958 13107 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13108
d5fe488a 13109 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13110 if (!tp->regs) {
1da177e4
LT		 13111 printk(KERN_ERR PFX "Cannot map device registers, "
13112 "aborting.\n");
13113 err = -ENOMEM;
13114 goto err_out_free_dev;
13115 }
13116
13117 tg3_init_link_config(tp);
13118
1da177e4
LT		 13119 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13120 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13121 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13122
bea3348e 13123 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13124 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13125 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13126 dev->irq = pdev->irq;
1da177e4
LT		 13127
13128 err = tg3_get_invariants(tp);
13129 if (err) {
13130 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13131 "aborting.\n");
13132 goto err_out_iounmap;
13133 }
13134
321d32a0 13135 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13137 dev->netdev_ops = &tg3_netdev_ops;
13138 else
13139 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13140
13141
4a29cc2e
MC		 13142 /* The EPB bridge inside 5714, 5715, and 5780 and any
13143 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13144 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13145 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13146 * do DMA address check in tg3_start_xmit().
13147 */
4a29cc2e
MC		 13148 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13149 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13150 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 13151 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13152#ifdef CONFIG_HIGHMEM
13153 dma_mask = DMA_64BIT_MASK;
13154#endif
4a29cc2e 13155 } else
72f2afb8
MC		 13156 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13157
13158 /* Configure DMA attributes. */
13159 if (dma_mask > DMA_32BIT_MASK) {
13160 err = pci_set_dma_mask(pdev, dma_mask);
13161 if (!err) {
13162 dev->features |= NETIF_F_HIGHDMA;
13163 err = pci_set_consistent_dma_mask(pdev,
13164 persist_dma_mask);
13165 if (err < 0) {
13166 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13167 "DMA for consistent allocations\n");
13168 goto err_out_iounmap;
13169 }
13170 }
13171 }
13172 if (err || dma_mask == DMA_32BIT_MASK) {
13173 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13174 if (err) {
13175 printk(KERN_ERR PFX "No usable DMA configuration, "
13176 "aborting.\n");
13177 goto err_out_iounmap;
13178 }
13179 }
13180
fdfec172 13181 tg3_init_bufmgr_config(tp);
1da177e4 13182
077f849d 13183 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13184 tp->fw_needed = FIRMWARE_TG3;
077f849d 13185
1da177e4
LT		 13186 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13187 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13188 }
13189 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13191 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13193 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13194 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13195 } else {
7f62ad5d 13196 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13198 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13199 else
9e9fd12d 13200 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13201 }
1da177e4 13202
4e3a7aaa
MC		 13203 /* TSO is on by default on chips that support hardware TSO.
13204 * Firmware TSO on older chips gives lower performance, so it
13205 * is off by default, but can be enabled using ethtool.
13206 */
b0026624 13207 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13208 if (dev->features & NETIF_F_IP_CSUM)
13209 dev->features |= NETIF_F_TSO;
13210 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13211 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13212 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13214 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13215 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13216 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13217 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13218 dev->features |= NETIF_F_TSO_ECN;
b0026624 13219 }
1da177e4 13220
1da177e4
LT		 13221
13222 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13223 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13224 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13225 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13226 tp->rx_pending = 63;
13227 }
13228
1da177e4
LT		 13229 err = tg3_get_device_address(tp);
13230 if (err) {
13231 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13232 "aborting.\n");
077f849d 13233 goto err_out_fw;
1da177e4
LT		 13234 }
13235
c88864df 13236 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13237 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13238 if (!tp->aperegs) {
c88864df
MC		 13239 printk(KERN_ERR PFX "Cannot map APE registers, "
13240 "aborting.\n");
13241 err = -ENOMEM;
077f849d 13242 goto err_out_fw;
c88864df
MC		 13243 }
13244
13245 tg3_ape_lock_init(tp);
13246 }
13247
1da177e4
LT		 13248 /*
13249 * Reset chip in case UNDI or EFI driver did not shutdown
13250 * DMA self test will enable WDMAC and we'll see (spurious)
13251 * pending DMA on the PCI bus at that point.
13252 */
13253 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13254 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13255 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13256 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13257 }
13258
13259 err = tg3_test_dma(tp);
13260 if (err) {
13261 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13262 goto err_out_apeunmap;
1da177e4
LT		 13263 }
13264
1da177e4
LT		 13265 /* flow control autonegotiation is default behavior */
13266 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13267 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13268
15f9850d
DM		 13269 tg3_init_coal(tp);
13270
c49a1561
MC		 13271 pci_set_drvdata(pdev, dev);
13272
1da177e4
LT		 13273 err = register_netdev(dev);
13274 if (err) {
13275 printk(KERN_ERR PFX "Cannot register net device, "
13276 "aborting.\n");
0d3031d9 13277 goto err_out_apeunmap;
1da177e4
LT		 13278 }
13279
df59c940 13280 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13281 dev->name,
13282 tp->board_part_number,
13283 tp->pci_chip_rev_id,
f9804ddb 13284 tg3_bus_string(tp, str),
e174961c 13285 dev->dev_addr);
1da177e4 13286
df59c940
MC		 13287 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13288 printk(KERN_INFO
13289 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13290 tp->dev->name,
13291 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13292 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13293 else
13294 printk(KERN_INFO
13295 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13296 tp->dev->name, tg3_phy_string(tp),
13297 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13298 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13299 "10/100/1000Base-T")),
13300 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13301
13302 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13303 dev->name,
13304 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13305 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13306 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13307 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13308 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13309 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13310 dev->name, tp->dma_rwctrl,
13311 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13312 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 13313
13314 return 0;
13315
0d3031d9
MC		 13316err_out_apeunmap:
13317 if (tp->aperegs) {
13318 iounmap(tp->aperegs);
13319 tp->aperegs = NULL;
13320 }
13321
077f849d
JSR		 13322err_out_fw:
13323 if (tp->fw)
13324 release_firmware(tp->fw);
13325
1da177e4 13326err_out_iounmap:
6892914f
MC		 13327 if (tp->regs) {
13328 iounmap(tp->regs);
22abe310 13329 tp->regs = NULL;
6892914f 13330 }
1da177e4
LT		 13331
13332err_out_free_dev:
13333 free_netdev(dev);
13334
13335err_out_free_res:
13336 pci_release_regions(pdev);
13337
13338err_out_disable_pdev:
13339 pci_disable_device(pdev);
13340 pci_set_drvdata(pdev, NULL);
13341 return err;
13342}
13343
13344static void __devexit tg3_remove_one(struct pci_dev *pdev)
13345{
13346 struct net_device *dev = pci_get_drvdata(pdev);
13347
13348 if (dev) {
13349 struct tg3 *tp = netdev_priv(dev);
13350
077f849d
JSR		 13351 if (tp->fw)
13352 release_firmware(tp->fw);
13353
7faa006f 13354 flush_scheduled_work();
158d7abd 13355
b02fd9e3
MC		 13356 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13357 tg3_phy_fini(tp);
158d7abd 13358 tg3_mdio_fini(tp);
b02fd9e3 13359 }
158d7abd 13360
1da177e4 13361 unregister_netdev(dev);
0d3031d9
MC		 13362 if (tp->aperegs) {
13363 iounmap(tp->aperegs);
13364 tp->aperegs = NULL;
13365 }
6892914f
MC		 13366 if (tp->regs) {
13367 iounmap(tp->regs);
22abe310 13368 tp->regs = NULL;
6892914f 13369 }
1da177e4
LT		 13370 free_netdev(dev);
13371 pci_release_regions(pdev);
13372 pci_disable_device(pdev);
13373 pci_set_drvdata(pdev, NULL);
13374 }
13375}
13376
13377static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13378{
13379 struct net_device *dev = pci_get_drvdata(pdev);
13380 struct tg3 *tp = netdev_priv(dev);
12dac075 13381 pci_power_t target_state;
1da177e4
LT		 13382 int err;
13383
3e0c95fd
MC		 13384 /* PCI register 4 needs to be saved whether netif_running() or not.
13385 * MSI address and data need to be saved if using MSI and
13386 * netif_running().
13387 */
13388 pci_save_state(pdev);
13389
1da177e4
LT		 13390 if (!netif_running(dev))
13391 return 0;
13392
7faa006f 13393 flush_scheduled_work();
b02fd9e3 13394 tg3_phy_stop(tp);
1da177e4
LT		 13395 tg3_netif_stop(tp);
13396
13397 del_timer_sync(&tp->timer);
13398
f47c11ee 13399 tg3_full_lock(tp, 1);
1da177e4 13400 tg3_disable_ints(tp);
f47c11ee 13401 tg3_full_unlock(tp);
1da177e4
LT		 13402
13403 netif_device_detach(dev);
13404
f47c11ee 13405 tg3_full_lock(tp, 0);
944d980e 13406 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13407 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13408 tg3_full_unlock(tp);
1da177e4 13409
12dac075
RW		 13410 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13411
13412 err = tg3_set_power_state(tp, target_state);
1da177e4 13413 if (err) {
b02fd9e3
MC		 13414 int err2;
13415
f47c11ee 13416 tg3_full_lock(tp, 0);
1da177e4 13417
6a9eba15 13418 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13419 err2 = tg3_restart_hw(tp, 1);
13420 if (err2)
b9ec6c1b 13421 goto out;
1da177e4
LT		 13422
13423 tp->timer.expires = jiffies + tp->timer_offset;
13424 add_timer(&tp->timer);
13425
13426 netif_device_attach(dev);
13427 tg3_netif_start(tp);
13428
b9ec6c1b 13429out:
f47c11ee 13430 tg3_full_unlock(tp);
b02fd9e3
MC		 13431
13432 if (!err2)
13433 tg3_phy_start(tp);
1da177e4
LT		 13434 }
13435
13436 return err;
13437}
13438
13439static int tg3_resume(struct pci_dev *pdev)
13440{
13441 struct net_device *dev = pci_get_drvdata(pdev);
13442 struct tg3 *tp = netdev_priv(dev);
13443 int err;
13444
3e0c95fd
MC		 13445 pci_restore_state(tp->pdev);
13446
1da177e4
LT		 13447 if (!netif_running(dev))
13448 return 0;
13449
bc1c7567 13450 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13451 if (err)
13452 return err;
13453
13454 netif_device_attach(dev);
13455
f47c11ee 13456 tg3_full_lock(tp, 0);
1da177e4 13457
6a9eba15 13458 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13459 err = tg3_restart_hw(tp, 1);
13460 if (err)
13461 goto out;
1da177e4
LT		 13462
13463 tp->timer.expires = jiffies + tp->timer_offset;
13464 add_timer(&tp->timer);
13465
1da177e4
LT		 13466 tg3_netif_start(tp);
13467
b9ec6c1b 13468out:
f47c11ee 13469 tg3_full_unlock(tp);
1da177e4 13470
b02fd9e3
MC		 13471 if (!err)
13472 tg3_phy_start(tp);
13473
b9ec6c1b 13474 return err;
1da177e4
LT		 13475}
13476
13477static struct pci_driver tg3_driver = {
13478 .name = DRV_MODULE_NAME,
13479 .id_table = tg3_pci_tbl,
13480 .probe = tg3_init_one,
13481 .remove = __devexit_p(tg3_remove_one),
13482 .suspend = tg3_suspend,
13483 .resume = tg3_resume
13484};
13485
13486static int __init tg3_init(void)
13487{
29917620 13488 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13489}
13490
13491static void __exit tg3_cleanup(void)
13492{
13493 pci_unregister_driver(&tg3_driver);
13494}
13495
13496module_init(tg3_init);
13497module_exit(tg3_cleanup);
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