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[TG3]: Add nvram lock-out support for 5752 TPM
[net-next-2.6.git] / drivers / net / tg3.c
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1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Copyright (C) 2000-2003 Broadcom Corporation.
11 */
12
13#include <linux/config.h>
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/compiler.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/pci.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/ethtool.h>
29#include <linux/mii.h>
30#include <linux/if_vlan.h>
31#include <linux/ip.h>
32#include <linux/tcp.h>
33#include <linux/workqueue.h>
34
35#include <net/checksum.h>
36
37#include <asm/system.h>
38#include <asm/io.h>
39#include <asm/byteorder.h>
40#include <asm/uaccess.h>
41
42#ifdef CONFIG_SPARC64
43#include <asm/idprom.h>
44#include <asm/oplib.h>
45#include <asm/pbm.h>
46#endif
47
48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define TG3_VLAN_TAG_USED 1
50#else
51#define TG3_VLAN_TAG_USED 0
52#endif
53
54#ifdef NETIF_F_TSO
55#define TG3_TSO_SUPPORT 1
56#else
57#define TG3_TSO_SUPPORT 0
58#endif
59
60#include "tg3.h"
61
62#define DRV_MODULE_NAME "tg3"
63#define PFX DRV_MODULE_NAME ": "
64#define DRV_MODULE_VERSION "3.25"
65#define DRV_MODULE_RELDATE "March 24, 2005"
66
67#define TG3_DEF_MAC_MODE 0
68#define TG3_DEF_RX_MODE 0
69#define TG3_DEF_TX_MODE 0
70#define TG3_DEF_MSG_ENABLE \
71 (NETIF_MSG_DRV | \
72 NETIF_MSG_PROBE | \
73 NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | \
75 NETIF_MSG_IFDOWN | \
76 NETIF_MSG_IFUP | \
77 NETIF_MSG_RX_ERR | \
78 NETIF_MSG_TX_ERR)
79
80/* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
82 */
83#define TG3_TX_TIMEOUT (5 * HZ)
84
85/* hardware minimum and maximum for a single frame's data payload */
86#define TG3_MIN_MTU 60
87#define TG3_MAX_MTU(tp) \
fcf02693 88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
1da177e4
LT		 89
90/* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
93 */
94#define TG3_RX_RING_SIZE 512
95#define TG3_DEF_RX_RING_PENDING 200
96#define TG3_RX_JUMBO_RING_SIZE 256
97#define TG3_DEF_RX_JUMBO_RING_PENDING 100
98
99/* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
104 */
105#define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
107
108#define TG3_TX_RING_SIZE 512
109#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
110
111#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
112 TG3_RX_RING_SIZE)
113#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
118 TG3_TX_RING_SIZE)
119#define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121#define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
126
127#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
129
130/* minimum number of free TX descriptors required to wake up TX process */
131#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
132
133/* number of ETHTOOL_GSTATS u64's */
134#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
135
136static char version[] __devinitdata =
137 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138
139MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_MODULE_VERSION);
143
144static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
145module_param(tg3_debug, int, 0);
146MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147
148static struct pci_device_id tg3_pci_tbl[] = {
149 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
151 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
217 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
231 { 0, }
232};
233
234MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
235
236static struct {
237 const char string[ETH_GSTRING_LEN];
238} ethtool_stats_keys[TG3_NUM_STATS] = {
239 { "rx_octets" },
240 { "rx_fragments" },
241 { "rx_ucast_packets" },
242 { "rx_mcast_packets" },
243 { "rx_bcast_packets" },
244 { "rx_fcs_errors" },
245 { "rx_align_errors" },
246 { "rx_xon_pause_rcvd" },
247 { "rx_xoff_pause_rcvd" },
248 { "rx_mac_ctrl_rcvd" },
249 { "rx_xoff_entered" },
250 { "rx_frame_too_long_errors" },
251 { "rx_jabbers" },
252 { "rx_undersize_packets" },
253 { "rx_in_length_errors" },
254 { "rx_out_length_errors" },
255 { "rx_64_or_less_octet_packets" },
256 { "rx_65_to_127_octet_packets" },
257 { "rx_128_to_255_octet_packets" },
258 { "rx_256_to_511_octet_packets" },
259 { "rx_512_to_1023_octet_packets" },
260 { "rx_1024_to_1522_octet_packets" },
261 { "rx_1523_to_2047_octet_packets" },
262 { "rx_2048_to_4095_octet_packets" },
263 { "rx_4096_to_8191_octet_packets" },
264 { "rx_8192_to_9022_octet_packets" },
265
266 { "tx_octets" },
267 { "tx_collisions" },
268
269 { "tx_xon_sent" },
270 { "tx_xoff_sent" },
271 { "tx_flow_control" },
272 { "tx_mac_errors" },
273 { "tx_single_collisions" },
274 { "tx_mult_collisions" },
275 { "tx_deferred" },
276 { "tx_excessive_collisions" },
277 { "tx_late_collisions" },
278 { "tx_collide_2times" },
279 { "tx_collide_3times" },
280 { "tx_collide_4times" },
281 { "tx_collide_5times" },
282 { "tx_collide_6times" },
283 { "tx_collide_7times" },
284 { "tx_collide_8times" },
285 { "tx_collide_9times" },
286 { "tx_collide_10times" },
287 { "tx_collide_11times" },
288 { "tx_collide_12times" },
289 { "tx_collide_13times" },
290 { "tx_collide_14times" },
291 { "tx_collide_15times" },
292 { "tx_ucast_packets" },
293 { "tx_mcast_packets" },
294 { "tx_bcast_packets" },
295 { "tx_carrier_sense_errors" },
296 { "tx_discards" },
297 { "tx_errors" },
298
299 { "dma_writeq_full" },
300 { "dma_write_prioq_full" },
301 { "rxbds_empty" },
302 { "rx_discards" },
303 { "rx_errors" },
304 { "rx_threshold_hit" },
305
306 { "dma_readq_full" },
307 { "dma_read_prioq_full" },
308 { "tx_comp_queue_full" },
309
310 { "ring_set_send_prod_index" },
311 { "ring_status_update" },
312 { "nic_irqs" },
313 { "nic_avoided_irqs" },
314 { "nic_tx_threshold_hit" }
315};
316
317static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
318{
319 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
320 unsigned long flags;
321
322 spin_lock_irqsave(&tp->indirect_lock, flags);
323 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325 spin_unlock_irqrestore(&tp->indirect_lock, flags);
326 } else {
327 writel(val, tp->regs + off);
328 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
329 readl(tp->regs + off);
330 }
331}
332
333static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
334{
335 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
336 unsigned long flags;
337
338 spin_lock_irqsave(&tp->indirect_lock, flags);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
340 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
341 spin_unlock_irqrestore(&tp->indirect_lock, flags);
342 } else {
343 void __iomem *dest = tp->regs + off;
344 writel(val, dest);
345 readl(dest); /* always flush PCI write */
346 }
347}
348
349static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
350{
351 void __iomem *mbox = tp->regs + off;
352 writel(val, mbox);
353 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
354 readl(mbox);
355}
356
357static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
358{
359 void __iomem *mbox = tp->regs + off;
360 writel(val, mbox);
361 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
362 writel(val, mbox);
363 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
364 readl(mbox);
365}
366
367#define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
368#define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
369#define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
370
371#define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
372#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
373#define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
374#define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
375#define tr32(reg) readl(tp->regs + (reg))
376#define tr16(reg) readw(tp->regs + (reg))
377#define tr8(reg) readb(tp->regs + (reg))
378
379static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
385 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
386
387 /* Always leave this as zero. */
388 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
389 spin_unlock_irqrestore(&tp->indirect_lock, flags);
390}
391
392static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
393{
394 unsigned long flags;
395
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
398 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
399
400 /* Always leave this as zero. */
401 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
403}
404
405static void tg3_disable_ints(struct tg3 *tp)
406{
407 tw32(TG3PCI_MISC_HOST_CTRL,
408 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
409 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
410 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
411}
412
413static inline void tg3_cond_int(struct tg3 *tp)
414{
415 if (tp->hw_status->status & SD_STATUS_UPDATED)
416 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
417}
418
419static void tg3_enable_ints(struct tg3 *tp)
420{
421 tw32(TG3PCI_MISC_HOST_CTRL,
422 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
423 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
424 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
425
426 tg3_cond_int(tp);
427}
428
429/* tg3_restart_ints
430 * similar to tg3_enable_ints, but it can return without flushing the
431 * PIO write which reenables interrupts
432 */
433static void tg3_restart_ints(struct tg3 *tp)
434{
435 tw32(TG3PCI_MISC_HOST_CTRL,
436 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
437 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
438 mmiowb();
439
440 tg3_cond_int(tp);
441}
442
443static inline void tg3_netif_stop(struct tg3 *tp)
444{
445 netif_poll_disable(tp->dev);
446 netif_tx_disable(tp->dev);
447}
448
449static inline void tg3_netif_start(struct tg3 *tp)
450{
451 netif_wake_queue(tp->dev);
452 /* NOTE: unconditional netif_wake_queue is only appropriate
453 * so long as all callers are assured to have free tx slots
454 * (such as after tg3_init_hw)
455 */
456 netif_poll_enable(tp->dev);
457 tg3_cond_int(tp);
458}
459
460static void tg3_switch_clocks(struct tg3 *tp)
461{
462 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
463 u32 orig_clock_ctrl;
464
465 orig_clock_ctrl = clock_ctrl;
466 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
467 CLOCK_CTRL_CLKRUN_OENABLE |
468 0x1f);
469 tp->pci_clock_ctrl = clock_ctrl;
470
471 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
472 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
473 tw32_f(TG3PCI_CLOCK_CTRL,
474 clock_ctrl | CLOCK_CTRL_625_CORE);
475 udelay(40);
476 }
477 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
478 tw32_f(TG3PCI_CLOCK_CTRL,
479 clock_ctrl |
480 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
481 udelay(40);
482 tw32_f(TG3PCI_CLOCK_CTRL,
483 clock_ctrl | (CLOCK_CTRL_ALTCLK));
484 udelay(40);
485 }
486 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
487 udelay(40);
488}
489
490#define PHY_BUSY_LOOPS 5000
491
492static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
493{
494 u32 frame_val;
495 unsigned int loops;
496 int ret;
497
498 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
499 tw32_f(MAC_MI_MODE,
500 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
501 udelay(80);
502 }
503
504 *val = 0x0;
505
506 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
507 MI_COM_PHY_ADDR_MASK);
508 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
509 MI_COM_REG_ADDR_MASK);
510 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
511
512 tw32_f(MAC_MI_COM, frame_val);
513
514 loops = PHY_BUSY_LOOPS;
515 while (loops != 0) {
516 udelay(10);
517 frame_val = tr32(MAC_MI_COM);
518
519 if ((frame_val & MI_COM_BUSY) == 0) {
520 udelay(5);
521 frame_val = tr32(MAC_MI_COM);
522 break;
523 }
524 loops -= 1;
525 }
526
527 ret = -EBUSY;
528 if (loops != 0) {
529 *val = frame_val & MI_COM_DATA_MASK;
530 ret = 0;
531 }
532
533 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
534 tw32_f(MAC_MI_MODE, tp->mi_mode);
535 udelay(80);
536 }
537
538 return ret;
539}
540
541static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
542{
543 u32 frame_val;
544 unsigned int loops;
545 int ret;
546
547 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
548 tw32_f(MAC_MI_MODE,
549 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
550 udelay(80);
551 }
552
553 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
554 MI_COM_PHY_ADDR_MASK);
555 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
556 MI_COM_REG_ADDR_MASK);
557 frame_val |= (val & MI_COM_DATA_MASK);
558 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
559
560 tw32_f(MAC_MI_COM, frame_val);
561
562 loops = PHY_BUSY_LOOPS;
563 while (loops != 0) {
564 udelay(10);
565 frame_val = tr32(MAC_MI_COM);
566 if ((frame_val & MI_COM_BUSY) == 0) {
567 udelay(5);
568 frame_val = tr32(MAC_MI_COM);
569 break;
570 }
571 loops -= 1;
572 }
573
574 ret = -EBUSY;
575 if (loops != 0)
576 ret = 0;
577
578 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
579 tw32_f(MAC_MI_MODE, tp->mi_mode);
580 udelay(80);
581 }
582
583 return ret;
584}
585
586static void tg3_phy_set_wirespeed(struct tg3 *tp)
587{
588 u32 val;
589
590 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
591 return;
592
593 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
594 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
595 tg3_writephy(tp, MII_TG3_AUX_CTRL,
596 (val | (1 << 15) | (1 << 4)));
597}
598
599static int tg3_bmcr_reset(struct tg3 *tp)
600{
601 u32 phy_control;
602 int limit, err;
603
604 /* OK, reset it, and poll the BMCR_RESET bit until it
605 * clears or we time out.
606 */
607 phy_control = BMCR_RESET;
608 err = tg3_writephy(tp, MII_BMCR, phy_control);
609 if (err != 0)
610 return -EBUSY;
611
612 limit = 5000;
613 while (limit--) {
614 err = tg3_readphy(tp, MII_BMCR, &phy_control);
615 if (err != 0)
616 return -EBUSY;
617
618 if ((phy_control & BMCR_RESET) == 0) {
619 udelay(40);
620 break;
621 }
622 udelay(10);
623 }
624 if (limit <= 0)
625 return -EBUSY;
626
627 return 0;
628}
629
630static int tg3_wait_macro_done(struct tg3 *tp)
631{
632 int limit = 100;
633
634 while (limit--) {
635 u32 tmp32;
636
637 if (!tg3_readphy(tp, 0x16, &tmp32)) {
638 if ((tmp32 & 0x1000) == 0)
639 break;
640 }
641 }
642 if (limit <= 0)
643 return -EBUSY;
644
645 return 0;
646}
647
648static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
649{
650 static const u32 test_pat[4][6] = {
651 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
652 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
653 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
654 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
655 };
656 int chan;
657
658 for (chan = 0; chan < 4; chan++) {
659 int i;
660
661 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
662 (chan * 0x2000) | 0x0200);
663 tg3_writephy(tp, 0x16, 0x0002);
664
665 for (i = 0; i < 6; i++)
666 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
667 test_pat[chan][i]);
668
669 tg3_writephy(tp, 0x16, 0x0202);
670 if (tg3_wait_macro_done(tp)) {
671 *resetp = 1;
672 return -EBUSY;
673 }
674
675 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
676 (chan * 0x2000) | 0x0200);
677 tg3_writephy(tp, 0x16, 0x0082);
678 if (tg3_wait_macro_done(tp)) {
679 *resetp = 1;
680 return -EBUSY;
681 }
682
683 tg3_writephy(tp, 0x16, 0x0802);
684 if (tg3_wait_macro_done(tp)) {
685 *resetp = 1;
686 return -EBUSY;
687 }
688
689 for (i = 0; i < 6; i += 2) {
690 u32 low, high;
691
692 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
693 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
694 tg3_wait_macro_done(tp)) {
695 *resetp = 1;
696 return -EBUSY;
697 }
698 low &= 0x7fff;
699 high &= 0x000f;
700 if (low != test_pat[chan][i] ||
701 high != test_pat[chan][i+1]) {
702 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
703 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
705
706 return -EBUSY;
707 }
708 }
709 }
710
711 return 0;
712}
713
714static int tg3_phy_reset_chanpat(struct tg3 *tp)
715{
716 int chan;
717
718 for (chan = 0; chan < 4; chan++) {
719 int i;
720
721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
722 (chan * 0x2000) | 0x0200);
723 tg3_writephy(tp, 0x16, 0x0002);
724 for (i = 0; i < 6; i++)
725 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
726 tg3_writephy(tp, 0x16, 0x0202);
727 if (tg3_wait_macro_done(tp))
728 return -EBUSY;
729 }
730
731 return 0;
732}
733
734static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
735{
736 u32 reg32, phy9_orig;
737 int retries, do_phy_reset, err;
738
739 retries = 10;
740 do_phy_reset = 1;
741 do {
742 if (do_phy_reset) {
743 err = tg3_bmcr_reset(tp);
744 if (err)
745 return err;
746 do_phy_reset = 0;
747 }
748
749 /* Disable transmitter and interrupt. */
750 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
751 continue;
752
753 reg32 |= 0x3000;
754 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
755
756 /* Set full-duplex, 1000 mbps. */
757 tg3_writephy(tp, MII_BMCR,
758 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
759
760 /* Set to master mode. */
761 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
762 continue;
763
764 tg3_writephy(tp, MII_TG3_CTRL,
765 (MII_TG3_CTRL_AS_MASTER |
766 MII_TG3_CTRL_ENABLE_AS_MASTER));
767
768 /* Enable SM_DSP_CLOCK and 6dB. */
769 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
770
771 /* Block the PHY control access. */
772 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
773 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
774
775 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
776 if (!err)
777 break;
778 } while (--retries);
779
780 err = tg3_phy_reset_chanpat(tp);
781 if (err)
782 return err;
783
784 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
786
787 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
788 tg3_writephy(tp, 0x16, 0x0000);
789
790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
792 /* Set Extended packet length bit for jumbo frames */
793 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
794 }
795 else {
796 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
797 }
798
799 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
800
801 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
802 reg32 &= ~0x3000;
803 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
804 } else if (!err)
805 err = -EBUSY;
806
807 return err;
808}
809
810/* This will reset the tigon3 PHY if there is no valid
811 * link unless the FORCE argument is non-zero.
812 */
813static int tg3_phy_reset(struct tg3 *tp)
814{
815 u32 phy_status;
816 int err;
817
818 err = tg3_readphy(tp, MII_BMSR, &phy_status);
819 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
820 if (err != 0)
821 return -EBUSY;
822
823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
825 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
826 err = tg3_phy_reset_5703_4_5(tp);
827 if (err)
828 return err;
829 goto out;
830 }
831
832 err = tg3_bmcr_reset(tp);
833 if (err)
834 return err;
835
836out:
837 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
838 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
841 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
843 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
844 }
845 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
846 tg3_writephy(tp, 0x1c, 0x8d68);
847 tg3_writephy(tp, 0x1c, 0x8d68);
848 }
849 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
850 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
852 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
853 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
854 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
858 }
859 /* Set Extended packet length bit (bit 14) on all chips that */
860 /* support jumbo frames */
861 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
862 /* Cannot do read-modify-write on 5401 */
863 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
fcf02693 864 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 865 u32 phy_reg;
866
867 /* Set bit 14 with read-modify-write to preserve other bits */
868 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
869 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
870 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
871 }
872
873 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
874 * jumbo frames transmission.
875 */
fcf02693 876 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 877 u32 phy_reg;
878
879 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
880 tg3_writephy(tp, MII_TG3_EXT_CTRL,
881 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
882 }
883
884 tg3_phy_set_wirespeed(tp);
885 return 0;
886}
887
888static void tg3_frob_aux_power(struct tg3 *tp)
889{
890 struct tg3 *tp_peer = tp;
891
892 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
893 return;
894
895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
896 tp_peer = pci_get_drvdata(tp->pdev_peer);
897 if (!tp_peer)
898 BUG();
899 }
900
901
902 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
903 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
906 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
907 (GRC_LCLCTRL_GPIO_OE0 |
908 GRC_LCLCTRL_GPIO_OE1 |
909 GRC_LCLCTRL_GPIO_OE2 |
910 GRC_LCLCTRL_GPIO_OUTPUT0 |
911 GRC_LCLCTRL_GPIO_OUTPUT1));
912 udelay(100);
913 } else {
914 u32 no_gpio2;
915 u32 grc_local_ctrl;
916
917 if (tp_peer != tp &&
918 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
919 return;
920
921 /* On 5753 and variants, GPIO2 cannot be used. */
922 no_gpio2 = tp->nic_sram_data_cfg &
923 NIC_SRAM_DATA_CFG_NO_GPIO2;
924
925 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
926 GRC_LCLCTRL_GPIO_OE1 |
927 GRC_LCLCTRL_GPIO_OE2 |
928 GRC_LCLCTRL_GPIO_OUTPUT1 |
929 GRC_LCLCTRL_GPIO_OUTPUT2;
930 if (no_gpio2) {
931 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
932 GRC_LCLCTRL_GPIO_OUTPUT2);
933 }
934 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
935 grc_local_ctrl);
936 udelay(100);
937
938 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
939
940 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
941 grc_local_ctrl);
942 udelay(100);
943
944 if (!no_gpio2) {
945 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
947 grc_local_ctrl);
948 udelay(100);
949 }
950 }
951 } else {
952 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
953 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
954 if (tp_peer != tp &&
955 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
956 return;
957
958 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
959 (GRC_LCLCTRL_GPIO_OE1 |
960 GRC_LCLCTRL_GPIO_OUTPUT1));
961 udelay(100);
962
963 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
964 (GRC_LCLCTRL_GPIO_OE1));
965 udelay(100);
966
967 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
968 (GRC_LCLCTRL_GPIO_OE1 |
969 GRC_LCLCTRL_GPIO_OUTPUT1));
970 udelay(100);
971 }
972 }
973}
974
975static int tg3_setup_phy(struct tg3 *, int);
976
977#define RESET_KIND_SHUTDOWN 0
978#define RESET_KIND_INIT 1
979#define RESET_KIND_SUSPEND 2
980
981static void tg3_write_sig_post_reset(struct tg3 *, int);
982static int tg3_halt_cpu(struct tg3 *, u32);
983
984static int tg3_set_power_state(struct tg3 *tp, int state)
985{
986 u32 misc_host_ctrl;
987 u16 power_control, power_caps;
988 int pm = tp->pm_cap;
989
990 /* Make sure register accesses (indirect or otherwise)
991 * will function correctly.
992 */
993 pci_write_config_dword(tp->pdev,
994 TG3PCI_MISC_HOST_CTRL,
995 tp->misc_host_ctrl);
996
997 pci_read_config_word(tp->pdev,
998 pm + PCI_PM_CTRL,
999 &power_control);
1000 power_control |= PCI_PM_CTRL_PME_STATUS;
1001 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1002 switch (state) {
1003 case 0:
1004 power_control |= 0;
1005 pci_write_config_word(tp->pdev,
1006 pm + PCI_PM_CTRL,
1007 power_control);
8c6bda1a
MC		 1008 udelay(100); /* Delay after power state change */
1009
1010 /* Switch out of Vaux if it is not a LOM */
1011 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1012 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1013 udelay(100);
1014 }
1da177e4
LT		 1015
1016 return 0;
1017
1018 case 1:
1019 power_control |= 1;
1020 break;
1021
1022 case 2:
1023 power_control |= 2;
1024 break;
1025
1026 case 3:
1027 power_control |= 3;
1028 break;
1029
1030 default:
1031 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1032 "requested.\n",
1033 tp->dev->name, state);
1034 return -EINVAL;
1035 };
1036
1037 power_control |= PCI_PM_CTRL_PME_ENABLE;
1038
1039 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1040 tw32(TG3PCI_MISC_HOST_CTRL,
1041 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1042
1043 if (tp->link_config.phy_is_low_power == 0) {
1044 tp->link_config.phy_is_low_power = 1;
1045 tp->link_config.orig_speed = tp->link_config.speed;
1046 tp->link_config.orig_duplex = tp->link_config.duplex;
1047 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1048 }
1049
1050 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1051 tp->link_config.speed = SPEED_10;
1052 tp->link_config.duplex = DUPLEX_HALF;
1053 tp->link_config.autoneg = AUTONEG_ENABLE;
1054 tg3_setup_phy(tp, 0);
1055 }
1056
1057 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1058
1059 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1060 u32 mac_mode;
1061
1062 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1064 udelay(40);
1065
1066 mac_mode = MAC_MODE_PORT_MODE_MII;
1067
1068 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1069 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1070 mac_mode |= MAC_MODE_LINK_POLARITY;
1071 } else {
1072 mac_mode = MAC_MODE_PORT_MODE_TBI;
1073 }
1074
cbf46853 1075 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1076 tw32(MAC_LED_CTRL, tp->led_ctrl);
1077
1078 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1079 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1080 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1081
1082 tw32_f(MAC_MODE, mac_mode);
1083 udelay(100);
1084
1085 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1086 udelay(10);
1087 }
1088
1089 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1090 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1092 u32 base_val;
1093
1094 base_val = tp->pci_clock_ctrl;
1095 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1096 CLOCK_CTRL_TXCLK_DISABLE);
1097
1098 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1099 CLOCK_CTRL_ALTCLK |
1100 CLOCK_CTRL_PWRDOWN_PLL133);
1101 udelay(40);
85e94ced 1102 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1103 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1104 u32 newbits1, newbits2;
1105
1106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1108 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1109 CLOCK_CTRL_TXCLK_DISABLE |
1110 CLOCK_CTRL_ALTCLK);
1111 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1112 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1113 newbits1 = CLOCK_CTRL_625_CORE;
1114 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1115 } else {
1116 newbits1 = CLOCK_CTRL_ALTCLK;
1117 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1118 }
1119
1120 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1121 udelay(40);
1122
1123 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1124 udelay(40);
1125
1126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1127 u32 newbits3;
1128
1129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1131 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1132 CLOCK_CTRL_TXCLK_DISABLE |
1133 CLOCK_CTRL_44MHZ_CORE);
1134 } else {
1135 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1136 }
1137
1138 tw32_f(TG3PCI_CLOCK_CTRL,
1139 tp->pci_clock_ctrl | newbits3);
1140 udelay(40);
1141 }
1142 }
1143
1144 tg3_frob_aux_power(tp);
1145
1146 /* Workaround for unstable PLL clock */
1147 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1148 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1149 u32 val = tr32(0x7d00);
1150
1151 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1152 tw32(0x7d00, val);
1153 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1154 tg3_halt_cpu(tp, RX_CPU_BASE);
1155 }
1156
1157 /* Finally, set the new power state. */
1158 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1159 udelay(100); /* Delay after power state change */
1da177e4
LT		 1160
1161 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1162
1163 return 0;
1164}
1165
1166static void tg3_link_report(struct tg3 *tp)
1167{
1168 if (!netif_carrier_ok(tp->dev)) {
1169 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1170 } else {
1171 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1172 tp->dev->name,
1173 (tp->link_config.active_speed == SPEED_1000 ?
1174 1000 :
1175 (tp->link_config.active_speed == SPEED_100 ?
1176 100 : 10)),
1177 (tp->link_config.active_duplex == DUPLEX_FULL ?
1178 "full" : "half"));
1179
1180 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1181 "%s for RX.\n",
1182 tp->dev->name,
1183 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1184 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1185 }
1186}
1187
1188static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1189{
1190 u32 new_tg3_flags = 0;
1191 u32 old_rx_mode = tp->rx_mode;
1192 u32 old_tx_mode = tp->tx_mode;
1193
1194 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1195 if (local_adv & ADVERTISE_PAUSE_CAP) {
1196 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1197 if (remote_adv & LPA_PAUSE_CAP)
1198 new_tg3_flags |=
1199 (TG3_FLAG_RX_PAUSE |
1200 TG3_FLAG_TX_PAUSE);
1201 else if (remote_adv & LPA_PAUSE_ASYM)
1202 new_tg3_flags |=
1203 (TG3_FLAG_RX_PAUSE);
1204 } else {
1205 if (remote_adv & LPA_PAUSE_CAP)
1206 new_tg3_flags |=
1207 (TG3_FLAG_RX_PAUSE |
1208 TG3_FLAG_TX_PAUSE);
1209 }
1210 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1211 if ((remote_adv & LPA_PAUSE_CAP) &&
1212 (remote_adv & LPA_PAUSE_ASYM))
1213 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1214 }
1215
1216 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1217 tp->tg3_flags |= new_tg3_flags;
1218 } else {
1219 new_tg3_flags = tp->tg3_flags;
1220 }
1221
1222 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1223 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1224 else
1225 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1226
1227 if (old_rx_mode != tp->rx_mode) {
1228 tw32_f(MAC_RX_MODE, tp->rx_mode);
1229 }
1230
1231 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1232 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1233 else
1234 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1235
1236 if (old_tx_mode != tp->tx_mode) {
1237 tw32_f(MAC_TX_MODE, tp->tx_mode);
1238 }
1239}
1240
1241static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1242{
1243 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1244 case MII_TG3_AUX_STAT_10HALF:
1245 *speed = SPEED_10;
1246 *duplex = DUPLEX_HALF;
1247 break;
1248
1249 case MII_TG3_AUX_STAT_10FULL:
1250 *speed = SPEED_10;
1251 *duplex = DUPLEX_FULL;
1252 break;
1253
1254 case MII_TG3_AUX_STAT_100HALF:
1255 *speed = SPEED_100;
1256 *duplex = DUPLEX_HALF;
1257 break;
1258
1259 case MII_TG3_AUX_STAT_100FULL:
1260 *speed = SPEED_100;
1261 *duplex = DUPLEX_FULL;
1262 break;
1263
1264 case MII_TG3_AUX_STAT_1000HALF:
1265 *speed = SPEED_1000;
1266 *duplex = DUPLEX_HALF;
1267 break;
1268
1269 case MII_TG3_AUX_STAT_1000FULL:
1270 *speed = SPEED_1000;
1271 *duplex = DUPLEX_FULL;
1272 break;
1273
1274 default:
1275 *speed = SPEED_INVALID;
1276 *duplex = DUPLEX_INVALID;
1277 break;
1278 };
1279}
1280
1281static void tg3_phy_copper_begin(struct tg3 *tp)
1282{
1283 u32 new_adv;
1284 int i;
1285
1286 if (tp->link_config.phy_is_low_power) {
1287 /* Entering low power mode. Disable gigabit and
1288 * 100baseT advertisements.
1289 */
1290 tg3_writephy(tp, MII_TG3_CTRL, 0);
1291
1292 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1293 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1294 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1295 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1296
1297 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1298 } else if (tp->link_config.speed == SPEED_INVALID) {
1299 tp->link_config.advertising =
1300 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1301 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1302 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1303 ADVERTISED_Autoneg | ADVERTISED_MII);
1304
1305 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1306 tp->link_config.advertising &=
1307 ~(ADVERTISED_1000baseT_Half |
1308 ADVERTISED_1000baseT_Full);
1309
1310 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1311 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1312 new_adv |= ADVERTISE_10HALF;
1313 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1314 new_adv |= ADVERTISE_10FULL;
1315 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1316 new_adv |= ADVERTISE_100HALF;
1317 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1318 new_adv |= ADVERTISE_100FULL;
1319 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1320
1321 if (tp->link_config.advertising &
1322 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1323 new_adv = 0;
1324 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1325 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1326 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1327 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1328 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1329 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1330 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1331 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1332 MII_TG3_CTRL_ENABLE_AS_MASTER);
1333 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1334 } else {
1335 tg3_writephy(tp, MII_TG3_CTRL, 0);
1336 }
1337 } else {
1338 /* Asking for a specific link mode. */
1339 if (tp->link_config.speed == SPEED_1000) {
1340 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1341 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1342
1343 if (tp->link_config.duplex == DUPLEX_FULL)
1344 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1345 else
1346 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1347 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1348 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1349 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1350 MII_TG3_CTRL_ENABLE_AS_MASTER);
1351 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1352 } else {
1353 tg3_writephy(tp, MII_TG3_CTRL, 0);
1354
1355 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1356 if (tp->link_config.speed == SPEED_100) {
1357 if (tp->link_config.duplex == DUPLEX_FULL)
1358 new_adv |= ADVERTISE_100FULL;
1359 else
1360 new_adv |= ADVERTISE_100HALF;
1361 } else {
1362 if (tp->link_config.duplex == DUPLEX_FULL)
1363 new_adv |= ADVERTISE_10FULL;
1364 else
1365 new_adv |= ADVERTISE_10HALF;
1366 }
1367 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1368 }
1369 }
1370
1371 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1372 tp->link_config.speed != SPEED_INVALID) {
1373 u32 bmcr, orig_bmcr;
1374
1375 tp->link_config.active_speed = tp->link_config.speed;
1376 tp->link_config.active_duplex = tp->link_config.duplex;
1377
1378 bmcr = 0;
1379 switch (tp->link_config.speed) {
1380 default:
1381 case SPEED_10:
1382 break;
1383
1384 case SPEED_100:
1385 bmcr |= BMCR_SPEED100;
1386 break;
1387
1388 case SPEED_1000:
1389 bmcr |= TG3_BMCR_SPEED1000;
1390 break;
1391 };
1392
1393 if (tp->link_config.duplex == DUPLEX_FULL)
1394 bmcr |= BMCR_FULLDPLX;
1395
1396 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1397 (bmcr != orig_bmcr)) {
1398 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1399 for (i = 0; i < 1500; i++) {
1400 u32 tmp;
1401
1402 udelay(10);
1403 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1404 tg3_readphy(tp, MII_BMSR, &tmp))
1405 continue;
1406 if (!(tmp & BMSR_LSTATUS)) {
1407 udelay(40);
1408 break;
1409 }
1410 }
1411 tg3_writephy(tp, MII_BMCR, bmcr);
1412 udelay(40);
1413 }
1414 } else {
1415 tg3_writephy(tp, MII_BMCR,
1416 BMCR_ANENABLE | BMCR_ANRESTART);
1417 }
1418}
1419
1420static int tg3_init_5401phy_dsp(struct tg3 *tp)
1421{
1422 int err;
1423
1424 /* Turn off tap power management. */
1425 /* Set Extended packet length bit */
1426 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1427
1428 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1429 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1430
1431 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1432 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1433
1434 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1435 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1436
1437 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1438 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1439
1440 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1441 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1442
1443 udelay(40);
1444
1445 return err;
1446}
1447
1448static int tg3_copper_is_advertising_all(struct tg3 *tp)
1449{
1450 u32 adv_reg, all_mask;
1451
1452 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1453 return 0;
1454
1455 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1456 ADVERTISE_100HALF | ADVERTISE_100FULL);
1457 if ((adv_reg & all_mask) != all_mask)
1458 return 0;
1459 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1460 u32 tg3_ctrl;
1461
1462 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1463 return 0;
1464
1465 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1466 MII_TG3_CTRL_ADV_1000_FULL);
1467 if ((tg3_ctrl & all_mask) != all_mask)
1468 return 0;
1469 }
1470 return 1;
1471}
1472
1473static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1474{
1475 int current_link_up;
1476 u32 bmsr, dummy;
1477 u16 current_speed;
1478 u8 current_duplex;
1479 int i, err;
1480
1481 tw32(MAC_EVENT, 0);
1482
1483 tw32_f(MAC_STATUS,
1484 (MAC_STATUS_SYNC_CHANGED |
1485 MAC_STATUS_CFG_CHANGED |
1486 MAC_STATUS_MI_COMPLETION |
1487 MAC_STATUS_LNKSTATE_CHANGED));
1488 udelay(40);
1489
1490 tp->mi_mode = MAC_MI_MODE_BASE;
1491 tw32_f(MAC_MI_MODE, tp->mi_mode);
1492 udelay(80);
1493
1494 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1495
1496 /* Some third-party PHYs need to be reset on link going
1497 * down.
1498 */
1499 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1502 netif_carrier_ok(tp->dev)) {
1503 tg3_readphy(tp, MII_BMSR, &bmsr);
1504 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1505 !(bmsr & BMSR_LSTATUS))
1506 force_reset = 1;
1507 }
1508 if (force_reset)
1509 tg3_phy_reset(tp);
1510
1511 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1512 tg3_readphy(tp, MII_BMSR, &bmsr);
1513 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1514 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1515 bmsr = 0;
1516
1517 if (!(bmsr & BMSR_LSTATUS)) {
1518 err = tg3_init_5401phy_dsp(tp);
1519 if (err)
1520 return err;
1521
1522 tg3_readphy(tp, MII_BMSR, &bmsr);
1523 for (i = 0; i < 1000; i++) {
1524 udelay(10);
1525 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1526 (bmsr & BMSR_LSTATUS)) {
1527 udelay(40);
1528 break;
1529 }
1530 }
1531
1532 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1533 !(bmsr & BMSR_LSTATUS) &&
1534 tp->link_config.active_speed == SPEED_1000) {
1535 err = tg3_phy_reset(tp);
1536 if (!err)
1537 err = tg3_init_5401phy_dsp(tp);
1538 if (err)
1539 return err;
1540 }
1541 }
1542 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1543 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1544 /* 5701 {A0,B0} CRC bug workaround */
1545 tg3_writephy(tp, 0x15, 0x0a75);
1546 tg3_writephy(tp, 0x1c, 0x8c68);
1547 tg3_writephy(tp, 0x1c, 0x8d68);
1548 tg3_writephy(tp, 0x1c, 0x8c68);
1549 }
1550
1551 /* Clear pending interrupts... */
1552 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1553 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1554
1555 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1556 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1557 else
1558 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1559
1560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1562 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1563 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1564 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1565 else
1566 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1567 }
1568
1569 current_link_up = 0;
1570 current_speed = SPEED_INVALID;
1571 current_duplex = DUPLEX_INVALID;
1572
1573 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1574 u32 val;
1575
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1577 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1578 if (!(val & (1 << 10))) {
1579 val |= (1 << 10);
1580 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1581 goto relink;
1582 }
1583 }
1584
1585 bmsr = 0;
1586 for (i = 0; i < 100; i++) {
1587 tg3_readphy(tp, MII_BMSR, &bmsr);
1588 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1589 (bmsr & BMSR_LSTATUS))
1590 break;
1591 udelay(40);
1592 }
1593
1594 if (bmsr & BMSR_LSTATUS) {
1595 u32 aux_stat, bmcr;
1596
1597 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1598 for (i = 0; i < 2000; i++) {
1599 udelay(10);
1600 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1601 aux_stat)
1602 break;
1603 }
1604
1605 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1606 &current_speed,
1607 &current_duplex);
1608
1609 bmcr = 0;
1610 for (i = 0; i < 200; i++) {
1611 tg3_readphy(tp, MII_BMCR, &bmcr);
1612 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1613 continue;
1614 if (bmcr && bmcr != 0x7fff)
1615 break;
1616 udelay(10);
1617 }
1618
1619 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1620 if (bmcr & BMCR_ANENABLE) {
1621 current_link_up = 1;
1622
1623 /* Force autoneg restart if we are exiting
1624 * low power mode.
1625 */
1626 if (!tg3_copper_is_advertising_all(tp))
1627 current_link_up = 0;
1628 } else {
1629 current_link_up = 0;
1630 }
1631 } else {
1632 if (!(bmcr & BMCR_ANENABLE) &&
1633 tp->link_config.speed == current_speed &&
1634 tp->link_config.duplex == current_duplex) {
1635 current_link_up = 1;
1636 } else {
1637 current_link_up = 0;
1638 }
1639 }
1640
1641 tp->link_config.active_speed = current_speed;
1642 tp->link_config.active_duplex = current_duplex;
1643 }
1644
1645 if (current_link_up == 1 &&
1646 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1647 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1648 u32 local_adv, remote_adv;
1649
1650 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1651 local_adv = 0;
1652 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1653
1654 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1655 remote_adv = 0;
1656
1657 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1658
1659 /* If we are not advertising full pause capability,
1660 * something is wrong. Bring the link down and reconfigure.
1661 */
1662 if (local_adv != ADVERTISE_PAUSE_CAP) {
1663 current_link_up = 0;
1664 } else {
1665 tg3_setup_flow_control(tp, local_adv, remote_adv);
1666 }
1667 }
1668relink:
1669 if (current_link_up == 0) {
1670 u32 tmp;
1671
1672 tg3_phy_copper_begin(tp);
1673
1674 tg3_readphy(tp, MII_BMSR, &tmp);
1675 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1676 (tmp & BMSR_LSTATUS))
1677 current_link_up = 1;
1678 }
1679
1680 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1681 if (current_link_up == 1) {
1682 if (tp->link_config.active_speed == SPEED_100 ||
1683 tp->link_config.active_speed == SPEED_10)
1684 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1685 else
1686 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1687 } else
1688 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1689
1690 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1691 if (tp->link_config.active_duplex == DUPLEX_HALF)
1692 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1693
1694 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1696 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1697 (current_link_up == 1 &&
1698 tp->link_config.active_speed == SPEED_10))
1699 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1700 } else {
1701 if (current_link_up == 1)
1702 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1703 }
1704
1705 /* ??? Without this setting Netgear GA302T PHY does not
1706 * ??? send/receive packets...
1707 */
1708 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1709 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1710 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1711 tw32_f(MAC_MI_MODE, tp->mi_mode);
1712 udelay(80);
1713 }
1714
1715 tw32_f(MAC_MODE, tp->mac_mode);
1716 udelay(40);
1717
1718 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1719 /* Polled via timer. */
1720 tw32_f(MAC_EVENT, 0);
1721 } else {
1722 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1723 }
1724 udelay(40);
1725
1726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1727 current_link_up == 1 &&
1728 tp->link_config.active_speed == SPEED_1000 &&
1729 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1730 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1731 udelay(120);
1732 tw32_f(MAC_STATUS,
1733 (MAC_STATUS_SYNC_CHANGED |
1734 MAC_STATUS_CFG_CHANGED));
1735 udelay(40);
1736 tg3_write_mem(tp,
1737 NIC_SRAM_FIRMWARE_MBOX,
1738 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1739 }
1740
1741 if (current_link_up != netif_carrier_ok(tp->dev)) {
1742 if (current_link_up)
1743 netif_carrier_on(tp->dev);
1744 else
1745 netif_carrier_off(tp->dev);
1746 tg3_link_report(tp);
1747 }
1748
1749 return 0;
1750}
1751
1752struct tg3_fiber_aneginfo {
1753 int state;
1754#define ANEG_STATE_UNKNOWN 0
1755#define ANEG_STATE_AN_ENABLE 1
1756#define ANEG_STATE_RESTART_INIT 2
1757#define ANEG_STATE_RESTART 3
1758#define ANEG_STATE_DISABLE_LINK_OK 4
1759#define ANEG_STATE_ABILITY_DETECT_INIT 5
1760#define ANEG_STATE_ABILITY_DETECT 6
1761#define ANEG_STATE_ACK_DETECT_INIT 7
1762#define ANEG_STATE_ACK_DETECT 8
1763#define ANEG_STATE_COMPLETE_ACK_INIT 9
1764#define ANEG_STATE_COMPLETE_ACK 10
1765#define ANEG_STATE_IDLE_DETECT_INIT 11
1766#define ANEG_STATE_IDLE_DETECT 12
1767#define ANEG_STATE_LINK_OK 13
1768#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1769#define ANEG_STATE_NEXT_PAGE_WAIT 15
1770
1771 u32 flags;
1772#define MR_AN_ENABLE 0x00000001
1773#define MR_RESTART_AN 0x00000002
1774#define MR_AN_COMPLETE 0x00000004
1775#define MR_PAGE_RX 0x00000008
1776#define MR_NP_LOADED 0x00000010
1777#define MR_TOGGLE_TX 0x00000020
1778#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1779#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1780#define MR_LP_ADV_SYM_PAUSE 0x00000100
1781#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1782#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1783#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1784#define MR_LP_ADV_NEXT_PAGE 0x00001000
1785#define MR_TOGGLE_RX 0x00002000
1786#define MR_NP_RX 0x00004000
1787
1788#define MR_LINK_OK 0x80000000
1789
1790 unsigned long link_time, cur_time;
1791
1792 u32 ability_match_cfg;
1793 int ability_match_count;
1794
1795 char ability_match, idle_match, ack_match;
1796
1797 u32 txconfig, rxconfig;
1798#define ANEG_CFG_NP 0x00000080
1799#define ANEG_CFG_ACK 0x00000040
1800#define ANEG_CFG_RF2 0x00000020
1801#define ANEG_CFG_RF1 0x00000010
1802#define ANEG_CFG_PS2 0x00000001
1803#define ANEG_CFG_PS1 0x00008000
1804#define ANEG_CFG_HD 0x00004000
1805#define ANEG_CFG_FD 0x00002000
1806#define ANEG_CFG_INVAL 0x00001f06
1807
1808};
1809#define ANEG_OK 0
1810#define ANEG_DONE 1
1811#define ANEG_TIMER_ENAB 2
1812#define ANEG_FAILED -1
1813
1814#define ANEG_STATE_SETTLE_TIME 10000
1815
1816static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1817 struct tg3_fiber_aneginfo *ap)
1818{
1819 unsigned long delta;
1820 u32 rx_cfg_reg;
1821 int ret;
1822
1823 if (ap->state == ANEG_STATE_UNKNOWN) {
1824 ap->rxconfig = 0;
1825 ap->link_time = 0;
1826 ap->cur_time = 0;
1827 ap->ability_match_cfg = 0;
1828 ap->ability_match_count = 0;
1829 ap->ability_match = 0;
1830 ap->idle_match = 0;
1831 ap->ack_match = 0;
1832 }
1833 ap->cur_time++;
1834
1835 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1836 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1837
1838 if (rx_cfg_reg != ap->ability_match_cfg) {
1839 ap->ability_match_cfg = rx_cfg_reg;
1840 ap->ability_match = 0;
1841 ap->ability_match_count = 0;
1842 } else {
1843 if (++ap->ability_match_count > 1) {
1844 ap->ability_match = 1;
1845 ap->ability_match_cfg = rx_cfg_reg;
1846 }
1847 }
1848 if (rx_cfg_reg & ANEG_CFG_ACK)
1849 ap->ack_match = 1;
1850 else
1851 ap->ack_match = 0;
1852
1853 ap->idle_match = 0;
1854 } else {
1855 ap->idle_match = 1;
1856 ap->ability_match_cfg = 0;
1857 ap->ability_match_count = 0;
1858 ap->ability_match = 0;
1859 ap->ack_match = 0;
1860
1861 rx_cfg_reg = 0;
1862 }
1863
1864 ap->rxconfig = rx_cfg_reg;
1865 ret = ANEG_OK;
1866
1867 switch(ap->state) {
1868 case ANEG_STATE_UNKNOWN:
1869 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1870 ap->state = ANEG_STATE_AN_ENABLE;
1871
1872 /* fallthru */
1873 case ANEG_STATE_AN_ENABLE:
1874 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1875 if (ap->flags & MR_AN_ENABLE) {
1876 ap->link_time = 0;
1877 ap->cur_time = 0;
1878 ap->ability_match_cfg = 0;
1879 ap->ability_match_count = 0;
1880 ap->ability_match = 0;
1881 ap->idle_match = 0;
1882 ap->ack_match = 0;
1883
1884 ap->state = ANEG_STATE_RESTART_INIT;
1885 } else {
1886 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1887 }
1888 break;
1889
1890 case ANEG_STATE_RESTART_INIT:
1891 ap->link_time = ap->cur_time;
1892 ap->flags &= ~(MR_NP_LOADED);
1893 ap->txconfig = 0;
1894 tw32(MAC_TX_AUTO_NEG, 0);
1895 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1896 tw32_f(MAC_MODE, tp->mac_mode);
1897 udelay(40);
1898
1899 ret = ANEG_TIMER_ENAB;
1900 ap->state = ANEG_STATE_RESTART;
1901
1902 /* fallthru */
1903 case ANEG_STATE_RESTART:
1904 delta = ap->cur_time - ap->link_time;
1905 if (delta > ANEG_STATE_SETTLE_TIME) {
1906 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1907 } else {
1908 ret = ANEG_TIMER_ENAB;
1909 }
1910 break;
1911
1912 case ANEG_STATE_DISABLE_LINK_OK:
1913 ret = ANEG_DONE;
1914 break;
1915
1916 case ANEG_STATE_ABILITY_DETECT_INIT:
1917 ap->flags &= ~(MR_TOGGLE_TX);
1918 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1919 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1920 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1921 tw32_f(MAC_MODE, tp->mac_mode);
1922 udelay(40);
1923
1924 ap->state = ANEG_STATE_ABILITY_DETECT;
1925 break;
1926
1927 case ANEG_STATE_ABILITY_DETECT:
1928 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1929 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1930 }
1931 break;
1932
1933 case ANEG_STATE_ACK_DETECT_INIT:
1934 ap->txconfig |= ANEG_CFG_ACK;
1935 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1936 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1937 tw32_f(MAC_MODE, tp->mac_mode);
1938 udelay(40);
1939
1940 ap->state = ANEG_STATE_ACK_DETECT;
1941
1942 /* fallthru */
1943 case ANEG_STATE_ACK_DETECT:
1944 if (ap->ack_match != 0) {
1945 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1946 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1947 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1948 } else {
1949 ap->state = ANEG_STATE_AN_ENABLE;
1950 }
1951 } else if (ap->ability_match != 0 &&
1952 ap->rxconfig == 0) {
1953 ap->state = ANEG_STATE_AN_ENABLE;
1954 }
1955 break;
1956
1957 case ANEG_STATE_COMPLETE_ACK_INIT:
1958 if (ap->rxconfig & ANEG_CFG_INVAL) {
1959 ret = ANEG_FAILED;
1960 break;
1961 }
1962 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1963 MR_LP_ADV_HALF_DUPLEX |
1964 MR_LP_ADV_SYM_PAUSE |
1965 MR_LP_ADV_ASYM_PAUSE |
1966 MR_LP_ADV_REMOTE_FAULT1 |
1967 MR_LP_ADV_REMOTE_FAULT2 |
1968 MR_LP_ADV_NEXT_PAGE |
1969 MR_TOGGLE_RX |
1970 MR_NP_RX);
1971 if (ap->rxconfig & ANEG_CFG_FD)
1972 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1973 if (ap->rxconfig & ANEG_CFG_HD)
1974 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1975 if (ap->rxconfig & ANEG_CFG_PS1)
1976 ap->flags |= MR_LP_ADV_SYM_PAUSE;
1977 if (ap->rxconfig & ANEG_CFG_PS2)
1978 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1979 if (ap->rxconfig & ANEG_CFG_RF1)
1980 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1981 if (ap->rxconfig & ANEG_CFG_RF2)
1982 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1983 if (ap->rxconfig & ANEG_CFG_NP)
1984 ap->flags |= MR_LP_ADV_NEXT_PAGE;
1985
1986 ap->link_time = ap->cur_time;
1987
1988 ap->flags ^= (MR_TOGGLE_TX);
1989 if (ap->rxconfig & 0x0008)
1990 ap->flags |= MR_TOGGLE_RX;
1991 if (ap->rxconfig & ANEG_CFG_NP)
1992 ap->flags |= MR_NP_RX;
1993 ap->flags |= MR_PAGE_RX;
1994
1995 ap->state = ANEG_STATE_COMPLETE_ACK;
1996 ret = ANEG_TIMER_ENAB;
1997 break;
1998
1999 case ANEG_STATE_COMPLETE_ACK:
2000 if (ap->ability_match != 0 &&
2001 ap->rxconfig == 0) {
2002 ap->state = ANEG_STATE_AN_ENABLE;
2003 break;
2004 }
2005 delta = ap->cur_time - ap->link_time;
2006 if (delta > ANEG_STATE_SETTLE_TIME) {
2007 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2008 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2009 } else {
2010 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2011 !(ap->flags & MR_NP_RX)) {
2012 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2013 } else {
2014 ret = ANEG_FAILED;
2015 }
2016 }
2017 }
2018 break;
2019
2020 case ANEG_STATE_IDLE_DETECT_INIT:
2021 ap->link_time = ap->cur_time;
2022 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2023 tw32_f(MAC_MODE, tp->mac_mode);
2024 udelay(40);
2025
2026 ap->state = ANEG_STATE_IDLE_DETECT;
2027 ret = ANEG_TIMER_ENAB;
2028 break;
2029
2030 case ANEG_STATE_IDLE_DETECT:
2031 if (ap->ability_match != 0 &&
2032 ap->rxconfig == 0) {
2033 ap->state = ANEG_STATE_AN_ENABLE;
2034 break;
2035 }
2036 delta = ap->cur_time - ap->link_time;
2037 if (delta > ANEG_STATE_SETTLE_TIME) {
2038 /* XXX another gem from the Broadcom driver :( */
2039 ap->state = ANEG_STATE_LINK_OK;
2040 }
2041 break;
2042
2043 case ANEG_STATE_LINK_OK:
2044 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2045 ret = ANEG_DONE;
2046 break;
2047
2048 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2049 /* ??? unimplemented */
2050 break;
2051
2052 case ANEG_STATE_NEXT_PAGE_WAIT:
2053 /* ??? unimplemented */
2054 break;
2055
2056 default:
2057 ret = ANEG_FAILED;
2058 break;
2059 };
2060
2061 return ret;
2062}
2063
2064static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2065{
2066 int res = 0;
2067 struct tg3_fiber_aneginfo aninfo;
2068 int status = ANEG_FAILED;
2069 unsigned int tick;
2070 u32 tmp;
2071
2072 tw32_f(MAC_TX_AUTO_NEG, 0);
2073
2074 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2075 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2076 udelay(40);
2077
2078 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2079 udelay(40);
2080
2081 memset(&aninfo, 0, sizeof(aninfo));
2082 aninfo.flags |= MR_AN_ENABLE;
2083 aninfo.state = ANEG_STATE_UNKNOWN;
2084 aninfo.cur_time = 0;
2085 tick = 0;
2086 while (++tick < 195000) {
2087 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2088 if (status == ANEG_DONE || status == ANEG_FAILED)
2089 break;
2090
2091 udelay(1);
2092 }
2093
2094 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2095 tw32_f(MAC_MODE, tp->mac_mode);
2096 udelay(40);
2097
2098 *flags = aninfo.flags;
2099
2100 if (status == ANEG_DONE &&
2101 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2102 MR_LP_ADV_FULL_DUPLEX)))
2103 res = 1;
2104
2105 return res;
2106}
2107
2108static void tg3_init_bcm8002(struct tg3 *tp)
2109{
2110 u32 mac_status = tr32(MAC_STATUS);
2111 int i;
2112
2113 /* Reset when initting first time or we have a link. */
2114 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2115 !(mac_status & MAC_STATUS_PCS_SYNCED))
2116 return;
2117
2118 /* Set PLL lock range. */
2119 tg3_writephy(tp, 0x16, 0x8007);
2120
2121 /* SW reset */
2122 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2123
2124 /* Wait for reset to complete. */
2125 /* XXX schedule_timeout() ... */
2126 for (i = 0; i < 500; i++)
2127 udelay(10);
2128
2129 /* Config mode; select PMA/Ch 1 regs. */
2130 tg3_writephy(tp, 0x10, 0x8411);
2131
2132 /* Enable auto-lock and comdet, select txclk for tx. */
2133 tg3_writephy(tp, 0x11, 0x0a10);
2134
2135 tg3_writephy(tp, 0x18, 0x00a0);
2136 tg3_writephy(tp, 0x16, 0x41ff);
2137
2138 /* Assert and deassert POR. */
2139 tg3_writephy(tp, 0x13, 0x0400);
2140 udelay(40);
2141 tg3_writephy(tp, 0x13, 0x0000);
2142
2143 tg3_writephy(tp, 0x11, 0x0a50);
2144 udelay(40);
2145 tg3_writephy(tp, 0x11, 0x0a10);
2146
2147 /* Wait for signal to stabilize */
2148 /* XXX schedule_timeout() ... */
2149 for (i = 0; i < 15000; i++)
2150 udelay(10);
2151
2152 /* Deselect the channel register so we can read the PHYID
2153 * later.
2154 */
2155 tg3_writephy(tp, 0x10, 0x8011);
2156}
2157
2158static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2159{
2160 u32 sg_dig_ctrl, sg_dig_status;
2161 u32 serdes_cfg, expected_sg_dig_ctrl;
2162 int workaround, port_a;
2163 int current_link_up;
2164
2165 serdes_cfg = 0;
2166 expected_sg_dig_ctrl = 0;
2167 workaround = 0;
2168 port_a = 1;
2169 current_link_up = 0;
2170
2171 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2172 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2173 workaround = 1;
2174 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2175 port_a = 0;
2176
2177 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2178 /* preserve bits 20-23 for voltage regulator */
2179 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2180 }
2181
2182 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2183
2184 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2185 if (sg_dig_ctrl & (1 << 31)) {
2186 if (workaround) {
2187 u32 val = serdes_cfg;
2188
2189 if (port_a)
2190 val |= 0xc010000;
2191 else
2192 val |= 0x4010000;
2193 tw32_f(MAC_SERDES_CFG, val);
2194 }
2195 tw32_f(SG_DIG_CTRL, 0x01388400);
2196 }
2197 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2198 tg3_setup_flow_control(tp, 0, 0);
2199 current_link_up = 1;
2200 }
2201 goto out;
2202 }
2203
2204 /* Want auto-negotiation. */
2205 expected_sg_dig_ctrl = 0x81388400;
2206
2207 /* Pause capability */
2208 expected_sg_dig_ctrl |= (1 << 11);
2209
2210 /* Asymettric pause */
2211 expected_sg_dig_ctrl |= (1 << 12);
2212
2213 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2214 if (workaround)
2215 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2216 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2217 udelay(5);
2218 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2219
2220 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2221 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2222 MAC_STATUS_SIGNAL_DET)) {
2223 int i;
2224
2225 /* Giver time to negotiate (~200ms) */
2226 for (i = 0; i < 40000; i++) {
2227 sg_dig_status = tr32(SG_DIG_STATUS);
2228 if (sg_dig_status & (0x3))
2229 break;
2230 udelay(5);
2231 }
2232 mac_status = tr32(MAC_STATUS);
2233
2234 if ((sg_dig_status & (1 << 1)) &&
2235 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2236 u32 local_adv, remote_adv;
2237
2238 local_adv = ADVERTISE_PAUSE_CAP;
2239 remote_adv = 0;
2240 if (sg_dig_status & (1 << 19))
2241 remote_adv |= LPA_PAUSE_CAP;
2242 if (sg_dig_status & (1 << 20))
2243 remote_adv |= LPA_PAUSE_ASYM;
2244
2245 tg3_setup_flow_control(tp, local_adv, remote_adv);
2246 current_link_up = 1;
2247 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2248 } else if (!(sg_dig_status & (1 << 1))) {
2249 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2250 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2251 else {
2252 if (workaround) {
2253 u32 val = serdes_cfg;
2254
2255 if (port_a)
2256 val |= 0xc010000;
2257 else
2258 val |= 0x4010000;
2259
2260 tw32_f(MAC_SERDES_CFG, val);
2261 }
2262
2263 tw32_f(SG_DIG_CTRL, 0x01388400);
2264 udelay(40);
2265
2266 /* Link parallel detection - link is up */
2267 /* only if we have PCS_SYNC and not */
2268 /* receiving config code words */
2269 mac_status = tr32(MAC_STATUS);
2270 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2271 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2272 tg3_setup_flow_control(tp, 0, 0);
2273 current_link_up = 1;
2274 }
2275 }
2276 }
2277 }
2278
2279out:
2280 return current_link_up;
2281}
2282
2283static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2284{
2285 int current_link_up = 0;
2286
2287 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2288 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2289 goto out;
2290 }
2291
2292 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2293 u32 flags;
2294 int i;
2295
2296 if (fiber_autoneg(tp, &flags)) {
2297 u32 local_adv, remote_adv;
2298
2299 local_adv = ADVERTISE_PAUSE_CAP;
2300 remote_adv = 0;
2301 if (flags & MR_LP_ADV_SYM_PAUSE)
2302 remote_adv |= LPA_PAUSE_CAP;
2303 if (flags & MR_LP_ADV_ASYM_PAUSE)
2304 remote_adv |= LPA_PAUSE_ASYM;
2305
2306 tg3_setup_flow_control(tp, local_adv, remote_adv);
2307
2308 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2309 current_link_up = 1;
2310 }
2311 for (i = 0; i < 30; i++) {
2312 udelay(20);
2313 tw32_f(MAC_STATUS,
2314 (MAC_STATUS_SYNC_CHANGED |
2315 MAC_STATUS_CFG_CHANGED));
2316 udelay(40);
2317 if ((tr32(MAC_STATUS) &
2318 (MAC_STATUS_SYNC_CHANGED |
2319 MAC_STATUS_CFG_CHANGED)) == 0)
2320 break;
2321 }
2322
2323 mac_status = tr32(MAC_STATUS);
2324 if (current_link_up == 0 &&
2325 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2326 !(mac_status & MAC_STATUS_RCVD_CFG))
2327 current_link_up = 1;
2328 } else {
2329 /* Forcing 1000FD link up. */
2330 current_link_up = 1;
2331 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2332
2333 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2334 udelay(40);
2335 }
2336
2337out:
2338 return current_link_up;
2339}
2340
2341static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2342{
2343 u32 orig_pause_cfg;
2344 u16 orig_active_speed;
2345 u8 orig_active_duplex;
2346 u32 mac_status;
2347 int current_link_up;
2348 int i;
2349
2350 orig_pause_cfg =
2351 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2352 TG3_FLAG_TX_PAUSE));
2353 orig_active_speed = tp->link_config.active_speed;
2354 orig_active_duplex = tp->link_config.active_duplex;
2355
2356 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2357 netif_carrier_ok(tp->dev) &&
2358 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2359 mac_status = tr32(MAC_STATUS);
2360 mac_status &= (MAC_STATUS_PCS_SYNCED |
2361 MAC_STATUS_SIGNAL_DET |
2362 MAC_STATUS_CFG_CHANGED |
2363 MAC_STATUS_RCVD_CFG);
2364 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2365 MAC_STATUS_SIGNAL_DET)) {
2366 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2367 MAC_STATUS_CFG_CHANGED));
2368 return 0;
2369 }
2370 }
2371
2372 tw32_f(MAC_TX_AUTO_NEG, 0);
2373
2374 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2375 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2376 tw32_f(MAC_MODE, tp->mac_mode);
2377 udelay(40);
2378
2379 if (tp->phy_id == PHY_ID_BCM8002)
2380 tg3_init_bcm8002(tp);
2381
2382 /* Enable link change event even when serdes polling. */
2383 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2384 udelay(40);
2385
2386 current_link_up = 0;
2387 mac_status = tr32(MAC_STATUS);
2388
2389 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2390 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2391 else
2392 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2393
2394 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2395 tw32_f(MAC_MODE, tp->mac_mode);
2396 udelay(40);
2397
2398 tp->hw_status->status =
2399 (SD_STATUS_UPDATED |
2400 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2401
2402 for (i = 0; i < 100; i++) {
2403 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2404 MAC_STATUS_CFG_CHANGED));
2405 udelay(5);
2406 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2407 MAC_STATUS_CFG_CHANGED)) == 0)
2408 break;
2409 }
2410
2411 mac_status = tr32(MAC_STATUS);
2412 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2413 current_link_up = 0;
2414 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2415 tw32_f(MAC_MODE, (tp->mac_mode |
2416 MAC_MODE_SEND_CONFIGS));
2417 udelay(1);
2418 tw32_f(MAC_MODE, tp->mac_mode);
2419 }
2420 }
2421
2422 if (current_link_up == 1) {
2423 tp->link_config.active_speed = SPEED_1000;
2424 tp->link_config.active_duplex = DUPLEX_FULL;
2425 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2426 LED_CTRL_LNKLED_OVERRIDE |
2427 LED_CTRL_1000MBPS_ON));
2428 } else {
2429 tp->link_config.active_speed = SPEED_INVALID;
2430 tp->link_config.active_duplex = DUPLEX_INVALID;
2431 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2432 LED_CTRL_LNKLED_OVERRIDE |
2433 LED_CTRL_TRAFFIC_OVERRIDE));
2434 }
2435
2436 if (current_link_up != netif_carrier_ok(tp->dev)) {
2437 if (current_link_up)
2438 netif_carrier_on(tp->dev);
2439 else
2440 netif_carrier_off(tp->dev);
2441 tg3_link_report(tp);
2442 } else {
2443 u32 now_pause_cfg =
2444 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2445 TG3_FLAG_TX_PAUSE);
2446 if (orig_pause_cfg != now_pause_cfg ||
2447 orig_active_speed != tp->link_config.active_speed ||
2448 orig_active_duplex != tp->link_config.active_duplex)
2449 tg3_link_report(tp);
2450 }
2451
2452 return 0;
2453}
2454
2455static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2456{
2457 int err;
2458
2459 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2460 err = tg3_setup_fiber_phy(tp, force_reset);
2461 } else {
2462 err = tg3_setup_copper_phy(tp, force_reset);
2463 }
2464
2465 if (tp->link_config.active_speed == SPEED_1000 &&
2466 tp->link_config.active_duplex == DUPLEX_HALF)
2467 tw32(MAC_TX_LENGTHS,
2468 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2469 (6 << TX_LENGTHS_IPG_SHIFT) |
2470 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2471 else
2472 tw32(MAC_TX_LENGTHS,
2473 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2474 (6 << TX_LENGTHS_IPG_SHIFT) |
2475 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2476
2477 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2478 if (netif_carrier_ok(tp->dev)) {
2479 tw32(HOSTCC_STAT_COAL_TICKS,
2480 DEFAULT_STAT_COAL_TICKS);
2481 } else {
2482 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2483 }
2484 }
2485
2486 return err;
2487}
2488
2489/* Tigon3 never reports partial packet sends. So we do not
2490 * need special logic to handle SKBs that have not had all
2491 * of their frags sent yet, like SunGEM does.
2492 */
2493static void tg3_tx(struct tg3 *tp)
2494{
2495 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2496 u32 sw_idx = tp->tx_cons;
2497
2498 while (sw_idx != hw_idx) {
2499 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2500 struct sk_buff *skb = ri->skb;
2501 int i;
2502
2503 if (unlikely(skb == NULL))
2504 BUG();
2505
2506 pci_unmap_single(tp->pdev,
2507 pci_unmap_addr(ri, mapping),
2508 skb_headlen(skb),
2509 PCI_DMA_TODEVICE);
2510
2511 ri->skb = NULL;
2512
2513 sw_idx = NEXT_TX(sw_idx);
2514
2515 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2516 if (unlikely(sw_idx == hw_idx))
2517 BUG();
2518
2519 ri = &tp->tx_buffers[sw_idx];
2520 if (unlikely(ri->skb != NULL))
2521 BUG();
2522
2523 pci_unmap_page(tp->pdev,
2524 pci_unmap_addr(ri, mapping),
2525 skb_shinfo(skb)->frags[i].size,
2526 PCI_DMA_TODEVICE);
2527
2528 sw_idx = NEXT_TX(sw_idx);
2529 }
2530
2531 dev_kfree_skb_irq(skb);
2532 }
2533
2534 tp->tx_cons = sw_idx;
2535
2536 if (netif_queue_stopped(tp->dev) &&
2537 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2538 netif_wake_queue(tp->dev);
2539}
2540
2541/* Returns size of skb allocated or < 0 on error.
2542 *
2543 * We only need to fill in the address because the other members
2544 * of the RX descriptor are invariant, see tg3_init_rings.
2545 *
2546 * Note the purposeful assymetry of cpu vs. chip accesses. For
2547 * posting buffers we only dirty the first cache line of the RX
2548 * descriptor (containing the address). Whereas for the RX status
2549 * buffers the cpu only reads the last cacheline of the RX descriptor
2550 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2551 */
2552static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2553 int src_idx, u32 dest_idx_unmasked)
2554{
2555 struct tg3_rx_buffer_desc *desc;
2556 struct ring_info *map, *src_map;
2557 struct sk_buff *skb;
2558 dma_addr_t mapping;
2559 int skb_size, dest_idx;
2560
2561 src_map = NULL;
2562 switch (opaque_key) {
2563 case RXD_OPAQUE_RING_STD:
2564 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2565 desc = &tp->rx_std[dest_idx];
2566 map = &tp->rx_std_buffers[dest_idx];
2567 if (src_idx >= 0)
2568 src_map = &tp->rx_std_buffers[src_idx];
2569 skb_size = RX_PKT_BUF_SZ;
2570 break;
2571
2572 case RXD_OPAQUE_RING_JUMBO:
2573 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2574 desc = &tp->rx_jumbo[dest_idx];
2575 map = &tp->rx_jumbo_buffers[dest_idx];
2576 if (src_idx >= 0)
2577 src_map = &tp->rx_jumbo_buffers[src_idx];
2578 skb_size = RX_JUMBO_PKT_BUF_SZ;
2579 break;
2580
2581 default:
2582 return -EINVAL;
2583 };
2584
2585 /* Do not overwrite any of the map or rp information
2586 * until we are sure we can commit to a new buffer.
2587 *
2588 * Callers depend upon this behavior and assume that
2589 * we leave everything unchanged if we fail.
2590 */
2591 skb = dev_alloc_skb(skb_size);
2592 if (skb == NULL)
2593 return -ENOMEM;
2594
2595 skb->dev = tp->dev;
2596 skb_reserve(skb, tp->rx_offset);
2597
2598 mapping = pci_map_single(tp->pdev, skb->data,
2599 skb_size - tp->rx_offset,
2600 PCI_DMA_FROMDEVICE);
2601
2602 map->skb = skb;
2603 pci_unmap_addr_set(map, mapping, mapping);
2604
2605 if (src_map != NULL)
2606 src_map->skb = NULL;
2607
2608 desc->addr_hi = ((u64)mapping >> 32);
2609 desc->addr_lo = ((u64)mapping & 0xffffffff);
2610
2611 return skb_size;
2612}
2613
2614/* We only need to move over in the address because the other
2615 * members of the RX descriptor are invariant. See notes above
2616 * tg3_alloc_rx_skb for full details.
2617 */
2618static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2619 int src_idx, u32 dest_idx_unmasked)
2620{
2621 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2622 struct ring_info *src_map, *dest_map;
2623 int dest_idx;
2624
2625 switch (opaque_key) {
2626 case RXD_OPAQUE_RING_STD:
2627 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2628 dest_desc = &tp->rx_std[dest_idx];
2629 dest_map = &tp->rx_std_buffers[dest_idx];
2630 src_desc = &tp->rx_std[src_idx];
2631 src_map = &tp->rx_std_buffers[src_idx];
2632 break;
2633
2634 case RXD_OPAQUE_RING_JUMBO:
2635 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2636 dest_desc = &tp->rx_jumbo[dest_idx];
2637 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2638 src_desc = &tp->rx_jumbo[src_idx];
2639 src_map = &tp->rx_jumbo_buffers[src_idx];
2640 break;
2641
2642 default:
2643 return;
2644 };
2645
2646 dest_map->skb = src_map->skb;
2647 pci_unmap_addr_set(dest_map, mapping,
2648 pci_unmap_addr(src_map, mapping));
2649 dest_desc->addr_hi = src_desc->addr_hi;
2650 dest_desc->addr_lo = src_desc->addr_lo;
2651
2652 src_map->skb = NULL;
2653}
2654
2655#if TG3_VLAN_TAG_USED
2656static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2657{
2658 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2659}
2660#endif
2661
2662/* The RX ring scheme is composed of multiple rings which post fresh
2663 * buffers to the chip, and one special ring the chip uses to report
2664 * status back to the host.
2665 *
2666 * The special ring reports the status of received packets to the
2667 * host. The chip does not write into the original descriptor the
2668 * RX buffer was obtained from. The chip simply takes the original
2669 * descriptor as provided by the host, updates the status and length
2670 * field, then writes this into the next status ring entry.
2671 *
2672 * Each ring the host uses to post buffers to the chip is described
2673 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2674 * it is first placed into the on-chip ram. When the packet's length
2675 * is known, it walks down the TG3_BDINFO entries to select the ring.
2676 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2677 * which is within the range of the new packet's length is chosen.
2678 *
2679 * The "separate ring for rx status" scheme may sound queer, but it makes
2680 * sense from a cache coherency perspective. If only the host writes
2681 * to the buffer post rings, and only the chip writes to the rx status
2682 * rings, then cache lines never move beyond shared-modified state.
2683 * If both the host and chip were to write into the same ring, cache line
2684 * eviction could occur since both entities want it in an exclusive state.
2685 */
2686static int tg3_rx(struct tg3 *tp, int budget)
2687{
2688 u32 work_mask;
2689 u32 rx_rcb_ptr = tp->rx_rcb_ptr;
2690 u16 hw_idx, sw_idx;
2691 int received;
2692
2693 hw_idx = tp->hw_status->idx[0].rx_producer;
2694 /*
2695 * We need to order the read of hw_idx and the read of
2696 * the opaque cookie.
2697 */
2698 rmb();
2699 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2700 work_mask = 0;
2701 received = 0;
2702 while (sw_idx != hw_idx && budget > 0) {
2703 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2704 unsigned int len;
2705 struct sk_buff *skb;
2706 dma_addr_t dma_addr;
2707 u32 opaque_key, desc_idx, *post_ptr;
2708
2709 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2710 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2711 if (opaque_key == RXD_OPAQUE_RING_STD) {
2712 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2713 mapping);
2714 skb = tp->rx_std_buffers[desc_idx].skb;
2715 post_ptr = &tp->rx_std_ptr;
2716 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2717 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2718 mapping);
2719 skb = tp->rx_jumbo_buffers[desc_idx].skb;
2720 post_ptr = &tp->rx_jumbo_ptr;
2721 }
2722 else {
2723 goto next_pkt_nopost;
2724 }
2725
2726 work_mask |= opaque_key;
2727
2728 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2729 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2730 drop_it:
2731 tg3_recycle_rx(tp, opaque_key,
2732 desc_idx, *post_ptr);
2733 drop_it_no_recycle:
2734 /* Other statistics kept track of by card. */
2735 tp->net_stats.rx_dropped++;
2736 goto next_pkt;
2737 }
2738
2739 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2740
2741 if (len > RX_COPY_THRESHOLD
2742 && tp->rx_offset == 2
2743 /* rx_offset != 2 iff this is a 5701 card running
2744 * in PCI-X mode [see tg3_get_invariants()] */
2745 ) {
2746 int skb_size;
2747
2748 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2749 desc_idx, *post_ptr);
2750 if (skb_size < 0)
2751 goto drop_it;
2752
2753 pci_unmap_single(tp->pdev, dma_addr,
2754 skb_size - tp->rx_offset,
2755 PCI_DMA_FROMDEVICE);
2756
2757 skb_put(skb, len);
2758 } else {
2759 struct sk_buff *copy_skb;
2760
2761 tg3_recycle_rx(tp, opaque_key,
2762 desc_idx, *post_ptr);
2763
2764 copy_skb = dev_alloc_skb(len + 2);
2765 if (copy_skb == NULL)
2766 goto drop_it_no_recycle;
2767
2768 copy_skb->dev = tp->dev;
2769 skb_reserve(copy_skb, 2);
2770 skb_put(copy_skb, len);
2771 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2772 memcpy(copy_skb->data, skb->data, len);
2773 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2774
2775 /* We'll reuse the original ring buffer. */
2776 skb = copy_skb;
2777 }
2778
2779 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2780 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2781 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2782 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2783 skb->ip_summed = CHECKSUM_UNNECESSARY;
2784 else
2785 skb->ip_summed = CHECKSUM_NONE;
2786
2787 skb->protocol = eth_type_trans(skb, tp->dev);
2788#if TG3_VLAN_TAG_USED
2789 if (tp->vlgrp != NULL &&
2790 desc->type_flags & RXD_FLAG_VLAN) {
2791 tg3_vlan_rx(tp, skb,
2792 desc->err_vlan & RXD_VLAN_MASK);
2793 } else
2794#endif
2795 netif_receive_skb(skb);
2796
2797 tp->dev->last_rx = jiffies;
2798 received++;
2799 budget--;
2800
2801next_pkt:
2802 (*post_ptr)++;
2803next_pkt_nopost:
2804 rx_rcb_ptr++;
2805 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2806 }
2807
2808 /* ACK the status ring. */
2809 tp->rx_rcb_ptr = rx_rcb_ptr;
2810 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
2811 (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
2812
2813 /* Refill RX ring(s). */
2814 if (work_mask & RXD_OPAQUE_RING_STD) {
2815 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2816 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2817 sw_idx);
2818 }
2819 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2820 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2821 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2822 sw_idx);
2823 }
2824 mmiowb();
2825
2826 return received;
2827}
2828
2829static int tg3_poll(struct net_device *netdev, int *budget)
2830{
2831 struct tg3 *tp = netdev_priv(netdev);
2832 struct tg3_hw_status *sblk = tp->hw_status;
2833 unsigned long flags;
2834 int done;
2835
2836 spin_lock_irqsave(&tp->lock, flags);
2837
2838 /* handle link change and other phy events */
2839 if (!(tp->tg3_flags &
2840 (TG3_FLAG_USE_LINKCHG_REG |
2841 TG3_FLAG_POLL_SERDES))) {
2842 if (sblk->status & SD_STATUS_LINK_CHG) {
2843 sblk->status = SD_STATUS_UPDATED |
2844 (sblk->status & ~SD_STATUS_LINK_CHG);
2845 tg3_setup_phy(tp, 0);
2846 }
2847 }
2848
2849 /* run TX completion thread */
2850 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2851 spin_lock(&tp->tx_lock);
2852 tg3_tx(tp);
2853 spin_unlock(&tp->tx_lock);
2854 }
2855
2856 spin_unlock_irqrestore(&tp->lock, flags);
2857
2858 /* run RX thread, within the bounds set by NAPI.
2859 * All RX "locking" is done by ensuring outside
2860 * code synchronizes with dev->poll()
2861 */
2862 done = 1;
2863 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2864 int orig_budget = *budget;
2865 int work_done;
2866
2867 if (orig_budget > netdev->quota)
2868 orig_budget = netdev->quota;
2869
2870 work_done = tg3_rx(tp, orig_budget);
2871
2872 *budget -= work_done;
2873 netdev->quota -= work_done;
2874
2875 if (work_done >= orig_budget)
2876 done = 0;
2877 }
2878
2879 /* if no more work, tell net stack and NIC we're done */
2880 if (done) {
2881 spin_lock_irqsave(&tp->lock, flags);
2882 __netif_rx_complete(netdev);
2883 tg3_restart_ints(tp);
2884 spin_unlock_irqrestore(&tp->lock, flags);
2885 }
2886
2887 return (done ? 0 : 1);
2888}
2889
2890static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
2891{
2892 struct tg3_hw_status *sblk = tp->hw_status;
2893 unsigned int work_exists = 0;
2894
2895 /* check for phy events */
2896 if (!(tp->tg3_flags &
2897 (TG3_FLAG_USE_LINKCHG_REG |
2898 TG3_FLAG_POLL_SERDES))) {
2899 if (sblk->status & SD_STATUS_LINK_CHG)
2900 work_exists = 1;
2901 }
2902 /* check for RX/TX work to do */
2903 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
2904 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
2905 work_exists = 1;
2906
2907 return work_exists;
2908}
2909
2910static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2911{
2912 struct net_device *dev = dev_id;
2913 struct tg3 *tp = netdev_priv(dev);
2914 struct tg3_hw_status *sblk = tp->hw_status;
2915 unsigned long flags;
2916 unsigned int handled = 1;
2917
2918 spin_lock_irqsave(&tp->lock, flags);
2919
2920 /* In INTx mode, it is possible for the interrupt to arrive at
2921 * the CPU before the status block posted prior to the interrupt.
2922 * Reading the PCI State register will confirm whether the
2923 * interrupt is ours and will flush the status block.
2924 */
2925 if ((sblk->status & SD_STATUS_UPDATED) ||
2926 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2927 /*
2928 * writing any value to intr-mbox-0 clears PCI INTA# and
2929 * chip-internal interrupt pending events.
2930 * writing non-zero to intr-mbox-0 additional tells the
2931 * NIC to stop sending us irqs, engaging "in-intr-handler"
2932 * event coalescing.
2933 */
2934 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2935 0x00000001);
2936 /*
2937 * Flush PCI write. This also guarantees that our
2938 * status block has been flushed to host memory.
2939 */
2940 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2941 sblk->status &= ~SD_STATUS_UPDATED;
2942
2943 if (likely(tg3_has_work(dev, tp)))
2944 netif_rx_schedule(dev); /* schedule NAPI poll */
2945 else {
2946 /* no work, shared interrupt perhaps? re-enable
2947 * interrupts, and flush that PCI write
2948 */
2949 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2950 0x00000000);
2951 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2952 }
2953 } else { /* shared interrupt */
2954 handled = 0;
2955 }
2956
2957 spin_unlock_irqrestore(&tp->lock, flags);
2958
2959 return IRQ_RETVAL(handled);
2960}
2961
2962static int tg3_init_hw(struct tg3 *);
2963static int tg3_halt(struct tg3 *);
2964
2965#ifdef CONFIG_NET_POLL_CONTROLLER
2966static void tg3_poll_controller(struct net_device *dev)
2967{
2968 tg3_interrupt(dev->irq, dev, NULL);
2969}
2970#endif
2971
2972static void tg3_reset_task(void *_data)
2973{
2974 struct tg3 *tp = _data;
2975 unsigned int restart_timer;
2976
2977 tg3_netif_stop(tp);
2978
2979 spin_lock_irq(&tp->lock);
2980 spin_lock(&tp->tx_lock);
2981
2982 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
2983 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
2984
2985 tg3_halt(tp);
2986 tg3_init_hw(tp);
2987
2988 tg3_netif_start(tp);
2989
2990 spin_unlock(&tp->tx_lock);
2991 spin_unlock_irq(&tp->lock);
2992
2993 if (restart_timer)
2994 mod_timer(&tp->timer, jiffies + 1);
2995}
2996
2997static void tg3_tx_timeout(struct net_device *dev)
2998{
2999 struct tg3 *tp = netdev_priv(dev);
3000
3001 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3002 dev->name);
3003
3004 schedule_work(&tp->reset_task);
3005}
3006
3007static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3008
3009static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3010 u32 guilty_entry, int guilty_len,
3011 u32 last_plus_one, u32 *start, u32 mss)
3012{
3013 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3014 dma_addr_t new_addr;
3015 u32 entry = *start;
3016 int i;
3017
3018 if (!new_skb) {
3019 dev_kfree_skb(skb);
3020 return -1;
3021 }
3022
3023 /* New SKB is guaranteed to be linear. */
3024 entry = *start;
3025 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3026 PCI_DMA_TODEVICE);
3027 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3028 (skb->ip_summed == CHECKSUM_HW) ?
3029 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3030 *start = NEXT_TX(entry);
3031
3032 /* Now clean up the sw ring entries. */
3033 i = 0;
3034 while (entry != last_plus_one) {
3035 int len;
3036
3037 if (i == 0)
3038 len = skb_headlen(skb);
3039 else
3040 len = skb_shinfo(skb)->frags[i-1].size;
3041 pci_unmap_single(tp->pdev,
3042 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3043 len, PCI_DMA_TODEVICE);
3044 if (i == 0) {
3045 tp->tx_buffers[entry].skb = new_skb;
3046 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3047 } else {
3048 tp->tx_buffers[entry].skb = NULL;
3049 }
3050 entry = NEXT_TX(entry);
3051 i++;
3052 }
3053
3054 dev_kfree_skb(skb);
3055
3056 return 0;
3057}
3058
3059static void tg3_set_txd(struct tg3 *tp, int entry,
3060 dma_addr_t mapping, int len, u32 flags,
3061 u32 mss_and_is_end)
3062{
3063 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3064 int is_end = (mss_and_is_end & 0x1);
3065 u32 mss = (mss_and_is_end >> 1);
3066 u32 vlan_tag = 0;
3067
3068 if (is_end)
3069 flags |= TXD_FLAG_END;
3070 if (flags & TXD_FLAG_VLAN) {
3071 vlan_tag = flags >> 16;
3072 flags &= 0xffff;
3073 }
3074 vlan_tag |= (mss << TXD_MSS_SHIFT);
3075
3076 txd->addr_hi = ((u64) mapping >> 32);
3077 txd->addr_lo = ((u64) mapping & 0xffffffff);
3078 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3079 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3080}
3081
3082static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3083{
3084 u32 base = (u32) mapping & 0xffffffff;
3085
3086 return ((base > 0xffffdcc0) &&
3087 (base + len + 8 < base));
3088}
3089
3090static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3091{
3092 struct tg3 *tp = netdev_priv(dev);
3093 dma_addr_t mapping;
3094 unsigned int i;
3095 u32 len, entry, base_flags, mss;
3096 int would_hit_hwbug;
3097 unsigned long flags;
3098
3099 len = skb_headlen(skb);
3100
3101 /* No BH disabling for tx_lock here. We are running in BH disabled
3102 * context and TX reclaim runs via tp->poll inside of a software
3103 * interrupt. Rejoice!
3104 *
3105 * Actually, things are not so simple. If we are to take a hw
3106 * IRQ here, we can deadlock, consider:
3107 *
3108 * CPU1 CPU2
3109 * tg3_start_xmit
3110 * take tp->tx_lock
3111 * tg3_timer
3112 * take tp->lock
3113 * tg3_interrupt
3114 * spin on tp->lock
3115 * spin on tp->tx_lock
3116 *
3117 * So we really do need to disable interrupts when taking
3118 * tx_lock here.
3119 */
3120 local_irq_save(flags);
3121 if (!spin_trylock(&tp->tx_lock)) {
3122 local_irq_restore(flags);
3123 return NETDEV_TX_LOCKED;
3124 }
3125
3126 /* This is a hard error, log it. */
3127 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3128 netif_stop_queue(dev);
3129 spin_unlock_irqrestore(&tp->tx_lock, flags);
3130 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3131 dev->name);
3132 return NETDEV_TX_BUSY;
3133 }
3134
3135 entry = tp->tx_prod;
3136 base_flags = 0;
3137 if (skb->ip_summed == CHECKSUM_HW)
3138 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3139#if TG3_TSO_SUPPORT != 0
3140 mss = 0;
3141 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3142 (mss = skb_shinfo(skb)->tso_size) != 0) {
3143 int tcp_opt_len, ip_tcp_len;
3144
3145 if (skb_header_cloned(skb) &&
3146 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3147 dev_kfree_skb(skb);
3148 goto out_unlock;
3149 }
3150
3151 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3152 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3153
3154 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3155 TXD_FLAG_CPU_POST_DMA);
3156
3157 skb->nh.iph->check = 0;
3158 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3159 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3160 skb->h.th->check = 0;
3161 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3162 }
3163 else {
3164 skb->h.th->check =
3165 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3166 skb->nh.iph->daddr,
3167 0, IPPROTO_TCP, 0);
3168 }
3169
3170 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3171 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3172 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3173 int tsflags;
3174
3175 tsflags = ((skb->nh.iph->ihl - 5) +
3176 (tcp_opt_len >> 2));
3177 mss |= (tsflags << 11);
3178 }
3179 } else {
3180 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3181 int tsflags;
3182
3183 tsflags = ((skb->nh.iph->ihl - 5) +
3184 (tcp_opt_len >> 2));
3185 base_flags |= tsflags << 12;
3186 }
3187 }
3188 }
3189#else
3190 mss = 0;
3191#endif
3192#if TG3_VLAN_TAG_USED
3193 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3194 base_flags |= (TXD_FLAG_VLAN |
3195 (vlan_tx_tag_get(skb) << 16));
3196#endif
3197
3198 /* Queue skb data, a.k.a. the main skb fragment. */
3199 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3200
3201 tp->tx_buffers[entry].skb = skb;
3202 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3203
3204 would_hit_hwbug = 0;
3205
3206 if (tg3_4g_overflow_test(mapping, len))
3207 would_hit_hwbug = entry + 1;
3208
3209 tg3_set_txd(tp, entry, mapping, len, base_flags,
3210 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3211
3212 entry = NEXT_TX(entry);
3213
3214 /* Now loop through additional data fragments, and queue them. */
3215 if (skb_shinfo(skb)->nr_frags > 0) {
3216 unsigned int i, last;
3217
3218 last = skb_shinfo(skb)->nr_frags - 1;
3219 for (i = 0; i <= last; i++) {
3220 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3221
3222 len = frag->size;
3223 mapping = pci_map_page(tp->pdev,
3224 frag->page,
3225 frag->page_offset,
3226 len, PCI_DMA_TODEVICE);
3227
3228 tp->tx_buffers[entry].skb = NULL;
3229 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3230
3231 if (tg3_4g_overflow_test(mapping, len)) {
3232 /* Only one should match. */
3233 if (would_hit_hwbug)
3234 BUG();
3235 would_hit_hwbug = entry + 1;
3236 }
3237
3238 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3239 tg3_set_txd(tp, entry, mapping, len,
3240 base_flags, (i == last)|(mss << 1));
3241 else
3242 tg3_set_txd(tp, entry, mapping, len,
3243 base_flags, (i == last));
3244
3245 entry = NEXT_TX(entry);
3246 }
3247 }
3248
3249 if (would_hit_hwbug) {
3250 u32 last_plus_one = entry;
3251 u32 start;
3252 unsigned int len = 0;
3253
3254 would_hit_hwbug -= 1;
3255 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3256 entry &= (TG3_TX_RING_SIZE - 1);
3257 start = entry;
3258 i = 0;
3259 while (entry != last_plus_one) {
3260 if (i == 0)
3261 len = skb_headlen(skb);
3262 else
3263 len = skb_shinfo(skb)->frags[i-1].size;
3264
3265 if (entry == would_hit_hwbug)
3266 break;
3267
3268 i++;
3269 entry = NEXT_TX(entry);
3270
3271 }
3272
3273 /* If the workaround fails due to memory/mapping
3274 * failure, silently drop this packet.
3275 */
3276 if (tigon3_4gb_hwbug_workaround(tp, skb,
3277 entry, len,
3278 last_plus_one,
3279 &start, mss))
3280 goto out_unlock;
3281
3282 entry = start;
3283 }
3284
3285 /* Packets are ready, update Tx producer idx local and on card. */
3286 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3287
3288 tp->tx_prod = entry;
3289 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3290 netif_stop_queue(dev);
3291
3292out_unlock:
3293 mmiowb();
3294 spin_unlock_irqrestore(&tp->tx_lock, flags);
3295
3296 dev->trans_start = jiffies;
3297
3298 return NETDEV_TX_OK;
3299}
3300
3301static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3302 int new_mtu)
3303{
3304 dev->mtu = new_mtu;
3305
3306 if (new_mtu > ETH_DATA_LEN)
3307 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3308 else
3309 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3310}
3311
3312static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3313{
3314 struct tg3 *tp = netdev_priv(dev);
3315
3316 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3317 return -EINVAL;
3318
3319 if (!netif_running(dev)) {
3320 /* We'll just catch it later when the
3321 * device is up'd.
3322 */
3323 tg3_set_mtu(dev, tp, new_mtu);
3324 return 0;
3325 }
3326
3327 tg3_netif_stop(tp);
3328 spin_lock_irq(&tp->lock);
3329 spin_lock(&tp->tx_lock);
3330
3331 tg3_halt(tp);
3332
3333 tg3_set_mtu(dev, tp, new_mtu);
3334
3335 tg3_init_hw(tp);
3336
3337 tg3_netif_start(tp);
3338
3339 spin_unlock(&tp->tx_lock);
3340 spin_unlock_irq(&tp->lock);
3341
3342 return 0;
3343}
3344
3345/* Free up pending packets in all rx/tx rings.
3346 *
3347 * The chip has been shut down and the driver detached from
3348 * the networking, so no interrupts or new tx packets will
3349 * end up in the driver. tp->{tx,}lock is not held and we are not
3350 * in an interrupt context and thus may sleep.
3351 */
3352static void tg3_free_rings(struct tg3 *tp)
3353{
3354 struct ring_info *rxp;
3355 int i;
3356
3357 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3358 rxp = &tp->rx_std_buffers[i];
3359
3360 if (rxp->skb == NULL)
3361 continue;
3362 pci_unmap_single(tp->pdev,
3363 pci_unmap_addr(rxp, mapping),
3364 RX_PKT_BUF_SZ - tp->rx_offset,
3365 PCI_DMA_FROMDEVICE);
3366 dev_kfree_skb_any(rxp->skb);
3367 rxp->skb = NULL;
3368 }
3369
3370 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3371 rxp = &tp->rx_jumbo_buffers[i];
3372
3373 if (rxp->skb == NULL)
3374 continue;
3375 pci_unmap_single(tp->pdev,
3376 pci_unmap_addr(rxp, mapping),
3377 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3378 PCI_DMA_FROMDEVICE);
3379 dev_kfree_skb_any(rxp->skb);
3380 rxp->skb = NULL;
3381 }
3382
3383 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3384 struct tx_ring_info *txp;
3385 struct sk_buff *skb;
3386 int j;
3387
3388 txp = &tp->tx_buffers[i];
3389 skb = txp->skb;
3390
3391 if (skb == NULL) {
3392 i++;
3393 continue;
3394 }
3395
3396 pci_unmap_single(tp->pdev,
3397 pci_unmap_addr(txp, mapping),
3398 skb_headlen(skb),
3399 PCI_DMA_TODEVICE);
3400 txp->skb = NULL;
3401
3402 i++;
3403
3404 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3405 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3406 pci_unmap_page(tp->pdev,
3407 pci_unmap_addr(txp, mapping),
3408 skb_shinfo(skb)->frags[j].size,
3409 PCI_DMA_TODEVICE);
3410 i++;
3411 }
3412
3413 dev_kfree_skb_any(skb);
3414 }
3415}
3416
3417/* Initialize tx/rx rings for packet processing.
3418 *
3419 * The chip has been shut down and the driver detached from
3420 * the networking, so no interrupts or new tx packets will
3421 * end up in the driver. tp->{tx,}lock are held and thus
3422 * we may not sleep.
3423 */
3424static void tg3_init_rings(struct tg3 *tp)
3425{
3426 u32 i;
3427
3428 /* Free up all the SKBs. */
3429 tg3_free_rings(tp);
3430
3431 /* Zero out all descriptors. */
3432 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3433 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3434 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3435 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3436
3437 /* Initialize invariants of the rings, we only set this
3438 * stuff once. This works because the card does not
3439 * write into the rx buffer posting rings.
3440 */
3441 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3442 struct tg3_rx_buffer_desc *rxd;
3443
3444 rxd = &tp->rx_std[i];
3445 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3446 << RXD_LEN_SHIFT;
3447 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3448 rxd->opaque = (RXD_OPAQUE_RING_STD |
3449 (i << RXD_OPAQUE_INDEX_SHIFT));
3450 }
3451
3452 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3453 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3454 struct tg3_rx_buffer_desc *rxd;
3455
3456 rxd = &tp->rx_jumbo[i];
3457 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3458 << RXD_LEN_SHIFT;
3459 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3460 RXD_FLAG_JUMBO;
3461 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3462 (i << RXD_OPAQUE_INDEX_SHIFT));
3463 }
3464 }
3465
3466 /* Now allocate fresh SKBs for each rx ring. */
3467 for (i = 0; i < tp->rx_pending; i++) {
3468 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3469 -1, i) < 0)
3470 break;
3471 }
3472
3473 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3474 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3475 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3476 -1, i) < 0)
3477 break;
3478 }
3479 }
3480}
3481
3482/*
3483 * Must not be invoked with interrupt sources disabled and
3484 * the hardware shutdown down.
3485 */
3486static void tg3_free_consistent(struct tg3 *tp)
3487{
3488 if (tp->rx_std_buffers) {
3489 kfree(tp->rx_std_buffers);
3490 tp->rx_std_buffers = NULL;
3491 }
3492 if (tp->rx_std) {
3493 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3494 tp->rx_std, tp->rx_std_mapping);
3495 tp->rx_std = NULL;
3496 }
3497 if (tp->rx_jumbo) {
3498 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3499 tp->rx_jumbo, tp->rx_jumbo_mapping);
3500 tp->rx_jumbo = NULL;
3501 }
3502 if (tp->rx_rcb) {
3503 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3504 tp->rx_rcb, tp->rx_rcb_mapping);
3505 tp->rx_rcb = NULL;
3506 }
3507 if (tp->tx_ring) {
3508 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3509 tp->tx_ring, tp->tx_desc_mapping);
3510 tp->tx_ring = NULL;
3511 }
3512 if (tp->hw_status) {
3513 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3514 tp->hw_status, tp->status_mapping);
3515 tp->hw_status = NULL;
3516 }
3517 if (tp->hw_stats) {
3518 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3519 tp->hw_stats, tp->stats_mapping);
3520 tp->hw_stats = NULL;
3521 }
3522}
3523
3524/*
3525 * Must not be invoked with interrupt sources disabled and
3526 * the hardware shutdown down. Can sleep.
3527 */
3528static int tg3_alloc_consistent(struct tg3 *tp)
3529{
3530 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3531 (TG3_RX_RING_SIZE +
3532 TG3_RX_JUMBO_RING_SIZE)) +
3533 (sizeof(struct tx_ring_info) *
3534 TG3_TX_RING_SIZE),
3535 GFP_KERNEL);
3536 if (!tp->rx_std_buffers)
3537 return -ENOMEM;
3538
3539 memset(tp->rx_std_buffers, 0,
3540 (sizeof(struct ring_info) *
3541 (TG3_RX_RING_SIZE +
3542 TG3_RX_JUMBO_RING_SIZE)) +
3543 (sizeof(struct tx_ring_info) *
3544 TG3_TX_RING_SIZE));
3545
3546 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3547 tp->tx_buffers = (struct tx_ring_info *)
3548 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3549
3550 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3551 &tp->rx_std_mapping);
3552 if (!tp->rx_std)
3553 goto err_out;
3554
3555 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3556 &tp->rx_jumbo_mapping);
3557
3558 if (!tp->rx_jumbo)
3559 goto err_out;
3560
3561 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3562 &tp->rx_rcb_mapping);
3563 if (!tp->rx_rcb)
3564 goto err_out;
3565
3566 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3567 &tp->tx_desc_mapping);
3568 if (!tp->tx_ring)
3569 goto err_out;
3570
3571 tp->hw_status = pci_alloc_consistent(tp->pdev,
3572 TG3_HW_STATUS_SIZE,
3573 &tp->status_mapping);
3574 if (!tp->hw_status)
3575 goto err_out;
3576
3577 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3578 sizeof(struct tg3_hw_stats),
3579 &tp->stats_mapping);
3580 if (!tp->hw_stats)
3581 goto err_out;
3582
3583 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3584 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3585
3586 return 0;
3587
3588err_out:
3589 tg3_free_consistent(tp);
3590 return -ENOMEM;
3591}
3592
3593#define MAX_WAIT_CNT 1000
3594
3595/* To stop a block, clear the enable bit and poll till it
3596 * clears. tp->lock is held.
3597 */
3598static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
3599{
3600 unsigned int i;
3601 u32 val;
3602
3603 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3604 switch (ofs) {
3605 case RCVLSC_MODE:
3606 case DMAC_MODE:
3607 case MBFREE_MODE:
3608 case BUFMGR_MODE:
3609 case MEMARB_MODE:
3610 /* We can't enable/disable these bits of the
3611 * 5705/5750, just say success.
3612 */
3613 return 0;
3614
3615 default:
3616 break;
3617 };
3618 }
3619
3620 val = tr32(ofs);
3621 val &= ~enable_bit;
3622 tw32_f(ofs, val);
3623
3624 for (i = 0; i < MAX_WAIT_CNT; i++) {
3625 udelay(100);
3626 val = tr32(ofs);
3627 if ((val & enable_bit) == 0)
3628 break;
3629 }
3630
3631 if (i == MAX_WAIT_CNT) {
3632 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3633 "ofs=%lx enable_bit=%x\n",
3634 ofs, enable_bit);
3635 return -ENODEV;
3636 }
3637
3638 return 0;
3639}
3640
3641/* tp->lock is held. */
3642static int tg3_abort_hw(struct tg3 *tp)
3643{
3644 int i, err;
3645
3646 tg3_disable_ints(tp);
3647
3648 tp->rx_mode &= ~RX_MODE_ENABLE;
3649 tw32_f(MAC_RX_MODE, tp->rx_mode);
3650 udelay(10);
3651
3652 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
3653 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
3654 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
3655 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
3656 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
3657 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
3658
3659 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
3660 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
3661 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
3662 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
3663 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
3664 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
3665 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
3666 if (err)
3667 goto out;
3668
3669 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3670 tw32_f(MAC_MODE, tp->mac_mode);
3671 udelay(40);
3672
3673 tp->tx_mode &= ~TX_MODE_ENABLE;
3674 tw32_f(MAC_TX_MODE, tp->tx_mode);
3675
3676 for (i = 0; i < MAX_WAIT_CNT; i++) {
3677 udelay(100);
3678 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3679 break;
3680 }
3681 if (i >= MAX_WAIT_CNT) {
3682 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3683 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3684 tp->dev->name, tr32(MAC_TX_MODE));
3685 return -ENODEV;
3686 }
3687
3688 err = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
3689 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
3690 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
3691
3692 tw32(FTQ_RESET, 0xffffffff);
3693 tw32(FTQ_RESET, 0x00000000);
3694
3695 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
3696 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
3697 if (err)
3698 goto out;
3699
3700 if (tp->hw_status)
3701 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3702 if (tp->hw_stats)
3703 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3704
3705out:
3706 return err;
3707}
3708
3709/* tp->lock is held. */
3710static int tg3_nvram_lock(struct tg3 *tp)
3711{
3712 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3713 int i;
3714
3715 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3716 for (i = 0; i < 8000; i++) {
3717 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3718 break;
3719 udelay(20);
3720 }
3721 if (i == 8000)
3722 return -ENODEV;
3723 }
3724 return 0;
3725}
3726
3727/* tp->lock is held. */
3728static void tg3_nvram_unlock(struct tg3 *tp)
3729{
3730 if (tp->tg3_flags & TG3_FLAG_NVRAM)
3731 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3732}
3733
e6af301b
MC		 3734/* tp->lock is held. */
3735static void tg3_enable_nvram_access(struct tg3 *tp)
3736{
3737 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3738 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3739 u32 nvaccess = tr32(NVRAM_ACCESS);
3740
3741 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3742 }
3743}
3744
3745/* tp->lock is held. */
3746static void tg3_disable_nvram_access(struct tg3 *tp)
3747{
3748 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3749 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3750 u32 nvaccess = tr32(NVRAM_ACCESS);
3751
3752 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3753 }
3754}
3755
1da177e4
LT		 3756/* tp->lock is held. */
3757static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3758{
3759 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3760 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3761 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3762
3763 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3764 switch (kind) {
3765 case RESET_KIND_INIT:
3766 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3767 DRV_STATE_START);
3768 break;
3769
3770 case RESET_KIND_SHUTDOWN:
3771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3772 DRV_STATE_UNLOAD);
3773 break;
3774
3775 case RESET_KIND_SUSPEND:
3776 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3777 DRV_STATE_SUSPEND);
3778 break;
3779
3780 default:
3781 break;
3782 };
3783 }
3784}
3785
3786/* tp->lock is held. */
3787static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3788{
3789 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3790 switch (kind) {
3791 case RESET_KIND_INIT:
3792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3793 DRV_STATE_START_DONE);
3794 break;
3795
3796 case RESET_KIND_SHUTDOWN:
3797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3798 DRV_STATE_UNLOAD_DONE);
3799 break;
3800
3801 default:
3802 break;
3803 };
3804 }
3805}
3806
3807/* tp->lock is held. */
3808static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3809{
3810 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3811 switch (kind) {
3812 case RESET_KIND_INIT:
3813 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3814 DRV_STATE_START);
3815 break;
3816
3817 case RESET_KIND_SHUTDOWN:
3818 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3819 DRV_STATE_UNLOAD);
3820 break;
3821
3822 case RESET_KIND_SUSPEND:
3823 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3824 DRV_STATE_SUSPEND);
3825 break;
3826
3827 default:
3828 break;
3829 };
3830 }
3831}
3832
3833static void tg3_stop_fw(struct tg3 *);
3834
3835/* tp->lock is held. */
3836static int tg3_chip_reset(struct tg3 *tp)
3837{
3838 u32 val;
3839 u32 flags_save;
3840 int i;
3841
3842 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3843 tg3_nvram_lock(tp);
3844
3845 /*
3846 * We must avoid the readl() that normally takes place.
3847 * It locks machines, causes machine checks, and other
3848 * fun things. So, temporarily disable the 5701
3849 * hardware workaround, while we do the reset.
3850 */
3851 flags_save = tp->tg3_flags;
3852 tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3853
3854 /* do the reset */
3855 val = GRC_MISC_CFG_CORECLK_RESET;
3856
3857 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3858 if (tr32(0x7e2c) == 0x60) {
3859 tw32(0x7e2c, 0x20);
3860 }
3861 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3862 tw32(GRC_MISC_CFG, (1 << 29));
3863 val |= (1 << 29);
3864 }
3865 }
3866
3867 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3868 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3869 tw32(GRC_MISC_CFG, val);
3870
3871 /* restore 5701 hardware bug workaround flag */
3872 tp->tg3_flags = flags_save;
3873
3874 /* Unfortunately, we have to delay before the PCI read back.
3875 * Some 575X chips even will not respond to a PCI cfg access
3876 * when the reset command is given to the chip.
3877 *
3878 * How do these hardware designers expect things to work
3879 * properly if the PCI write is posted for a long period
3880 * of time? It is always necessary to have some method by
3881 * which a register read back can occur to push the write
3882 * out which does the reset.
3883 *
3884 * For most tg3 variants the trick below was working.
3885 * Ho hum...
3886 */
3887 udelay(120);
3888
3889 /* Flush PCI posted writes. The normal MMIO registers
3890 * are inaccessible at this time so this is the only
3891 * way to make this reliably (actually, this is no longer
3892 * the case, see above). I tried to use indirect
3893 * register read/write but this upset some 5701 variants.
3894 */
3895 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
3896
3897 udelay(120);
3898
3899 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3900 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
3901 int i;
3902 u32 cfg_val;
3903
3904 /* Wait for link training to complete. */
3905 for (i = 0; i < 5000; i++)
3906 udelay(100);
3907
3908 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
3909 pci_write_config_dword(tp->pdev, 0xc4,
3910 cfg_val | (1 << 15));
3911 }
3912 /* Set PCIE max payload size and clear error status. */
3913 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
3914 }
3915
3916 /* Re-enable indirect register accesses. */
3917 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
3918 tp->misc_host_ctrl);
3919
3920 /* Set MAX PCI retry to zero. */
3921 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
3922 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
3923 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
3924 val |= PCISTATE_RETRY_SAME_DMA;
3925 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
3926
3927 pci_restore_state(tp->pdev);
3928
3929 /* Make sure PCI-X relaxed ordering bit is clear. */
3930 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
3931 val &= ~PCIX_CAPS_RELAXED_ORDERING;
3932 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
3933
3934 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
3935
3936 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
3937 tg3_stop_fw(tp);
3938 tw32(0x5000, 0x400);
3939 }
3940
3941 tw32(GRC_MODE, tp->grc_mode);
3942
3943 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
3944 u32 val = tr32(0xc4);
3945
3946 tw32(0xc4, val | (1 << 15));
3947 }
3948
3949 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
3950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3951 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
3952 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
3953 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
3954 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
3955 }
3956
3957 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3958 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
3959 tw32_f(MAC_MODE, tp->mac_mode);
3960 } else
3961 tw32_f(MAC_MODE, 0);
3962 udelay(40);
3963
3964 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
3965 /* Wait for firmware initialization to complete. */
3966 for (i = 0; i < 100000; i++) {
3967 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
3968 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3969 break;
3970 udelay(10);
3971 }
3972 if (i >= 100000) {
3973 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
3974 "firmware will not restart magic=%08x\n",
3975 tp->dev->name, val);
3976 return -ENODEV;
3977 }
3978 }
3979
3980 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
3981 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3982 u32 val = tr32(0x7c00);
3983
3984 tw32(0x7c00, val | (1 << 25));
3985 }
3986
3987 /* Reprobe ASF enable state. */
3988 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
3989 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
3990 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
3991 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
3992 u32 nic_cfg;
3993
3994 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
3995 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
3996 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 3997 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 3998 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
3999 }
4000 }
4001
4002 return 0;
4003}
4004
4005/* tp->lock is held. */
4006static void tg3_stop_fw(struct tg3 *tp)
4007{
4008 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4009 u32 val;
4010 int i;
4011
4012 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4013 val = tr32(GRC_RX_CPU_EVENT);
4014 val |= (1 << 14);
4015 tw32(GRC_RX_CPU_EVENT, val);
4016
4017 /* Wait for RX cpu to ACK the event. */
4018 for (i = 0; i < 100; i++) {
4019 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4020 break;
4021 udelay(1);
4022 }
4023 }
4024}
4025
4026/* tp->lock is held. */
4027static int tg3_halt(struct tg3 *tp)
4028{
4029 int err;
4030
4031 tg3_stop_fw(tp);
4032
4033 tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN);
4034
4035 tg3_abort_hw(tp);
4036 err = tg3_chip_reset(tp);
4037
4038 tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN);
4039 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4040
4041 if (err)
4042 return err;
4043
4044 return 0;
4045}
4046
4047#define TG3_FW_RELEASE_MAJOR 0x0
4048#define TG3_FW_RELASE_MINOR 0x0
4049#define TG3_FW_RELEASE_FIX 0x0
4050#define TG3_FW_START_ADDR 0x08000000
4051#define TG3_FW_TEXT_ADDR 0x08000000
4052#define TG3_FW_TEXT_LEN 0x9c0
4053#define TG3_FW_RODATA_ADDR 0x080009c0
4054#define TG3_FW_RODATA_LEN 0x60
4055#define TG3_FW_DATA_ADDR 0x08000a40
4056#define TG3_FW_DATA_LEN 0x20
4057#define TG3_FW_SBSS_ADDR 0x08000a60
4058#define TG3_FW_SBSS_LEN 0xc
4059#define TG3_FW_BSS_ADDR 0x08000a70
4060#define TG3_FW_BSS_LEN 0x10
4061
4062static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4063 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4064 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4065 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4066 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4067 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4068 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4069 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4070 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4071 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4072 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4073 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4074 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4075 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4076 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4077 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4078 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4079 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4080 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4081 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4082 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4083 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4084 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4085 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4086 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4087 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4088 0, 0, 0, 0, 0, 0,
4089 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4090 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4091 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4092 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4093 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4094 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4095 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4096 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4097 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4098 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4099 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4101 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4103 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4104 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4105 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4106 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4107 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4108 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4109 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4110 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4111 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4112 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4113 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4114 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4115 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4116 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4117 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4118 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4119 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4120 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4121 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4122 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4123 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4124 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4125 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4126 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4127 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4128 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4129 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4130 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4131 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4132 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4133 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4134 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4135 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4136 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4137 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4138 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4139 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4140 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4141 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4142 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4143 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4144 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4145 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4146 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4147 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4148 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4149 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4150 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4151 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4152 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4153 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4154};
4155
4156static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4157 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4158 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4159 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4160 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4161 0x00000000
4162};
4163
4164#if 0 /* All zeros, don't eat up space with it. */
4165u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4166 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4167 0x00000000, 0x00000000, 0x00000000, 0x00000000
4168};
4169#endif
4170
4171#define RX_CPU_SCRATCH_BASE 0x30000
4172#define RX_CPU_SCRATCH_SIZE 0x04000
4173#define TX_CPU_SCRATCH_BASE 0x34000
4174#define TX_CPU_SCRATCH_SIZE 0x04000
4175
4176/* tp->lock is held. */
4177static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4178{
4179 int i;
4180
4181 if (offset == TX_CPU_BASE &&
4182 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4183 BUG();
4184
4185 if (offset == RX_CPU_BASE) {
4186 for (i = 0; i < 10000; i++) {
4187 tw32(offset + CPU_STATE, 0xffffffff);
4188 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4189 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4190 break;
4191 }
4192
4193 tw32(offset + CPU_STATE, 0xffffffff);
4194 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4195 udelay(10);
4196 } else {
4197 for (i = 0; i < 10000; i++) {
4198 tw32(offset + CPU_STATE, 0xffffffff);
4199 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4200 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4201 break;
4202 }
4203 }
4204
4205 if (i >= 10000) {
4206 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4207 "and %s CPU\n",
4208 tp->dev->name,
4209 (offset == RX_CPU_BASE ? "RX" : "TX"));
4210 return -ENODEV;
4211 }
4212 return 0;
4213}
4214
4215struct fw_info {
4216 unsigned int text_base;
4217 unsigned int text_len;
4218 u32 *text_data;
4219 unsigned int rodata_base;
4220 unsigned int rodata_len;
4221 u32 *rodata_data;
4222 unsigned int data_base;
4223 unsigned int data_len;
4224 u32 *data_data;
4225};
4226
4227/* tp->lock is held. */
4228static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4229 int cpu_scratch_size, struct fw_info *info)
4230{
4231 int err, i;
4232 u32 orig_tg3_flags = tp->tg3_flags;
4233 void (*write_op)(struct tg3 *, u32, u32);
4234
4235 if (cpu_base == TX_CPU_BASE &&
4236 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4237 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4238 "TX cpu firmware on %s which is 5705.\n",
4239 tp->dev->name);
4240 return -EINVAL;
4241 }
4242
4243 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4244 write_op = tg3_write_mem;
4245 else
4246 write_op = tg3_write_indirect_reg32;
4247
4248 /* Force use of PCI config space for indirect register
4249 * write calls.
4250 */
4251 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4252
4253 err = tg3_halt_cpu(tp, cpu_base);
4254 if (err)
4255 goto out;
4256
4257 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4258 write_op(tp, cpu_scratch_base + i, 0);
4259 tw32(cpu_base + CPU_STATE, 0xffffffff);
4260 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4261 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4262 write_op(tp, (cpu_scratch_base +
4263 (info->text_base & 0xffff) +
4264 (i * sizeof(u32))),
4265 (info->text_data ?
4266 info->text_data[i] : 0));
4267 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4268 write_op(tp, (cpu_scratch_base +
4269 (info->rodata_base & 0xffff) +
4270 (i * sizeof(u32))),
4271 (info->rodata_data ?
4272 info->rodata_data[i] : 0));
4273 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4274 write_op(tp, (cpu_scratch_base +
4275 (info->data_base & 0xffff) +
4276 (i * sizeof(u32))),
4277 (info->data_data ?
4278 info->data_data[i] : 0));
4279
4280 err = 0;
4281
4282out:
4283 tp->tg3_flags = orig_tg3_flags;
4284 return err;
4285}
4286
4287/* tp->lock is held. */
4288static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4289{
4290 struct fw_info info;
4291 int err, i;
4292
4293 info.text_base = TG3_FW_TEXT_ADDR;
4294 info.text_len = TG3_FW_TEXT_LEN;
4295 info.text_data = &tg3FwText[0];
4296 info.rodata_base = TG3_FW_RODATA_ADDR;
4297 info.rodata_len = TG3_FW_RODATA_LEN;
4298 info.rodata_data = &tg3FwRodata[0];
4299 info.data_base = TG3_FW_DATA_ADDR;
4300 info.data_len = TG3_FW_DATA_LEN;
4301 info.data_data = NULL;
4302
4303 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4304 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4305 &info);
4306 if (err)
4307 return err;
4308
4309 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4310 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4311 &info);
4312 if (err)
4313 return err;
4314
4315 /* Now startup only the RX cpu. */
4316 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4317 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4318
4319 for (i = 0; i < 5; i++) {
4320 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4321 break;
4322 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4323 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4324 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4325 udelay(1000);
4326 }
4327 if (i >= 5) {
4328 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4329 "to set RX CPU PC, is %08x should be %08x\n",
4330 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4331 TG3_FW_TEXT_ADDR);
4332 return -ENODEV;
4333 }
4334 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4335 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4336
4337 return 0;
4338}
4339
4340#if TG3_TSO_SUPPORT != 0
4341
4342#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4343#define TG3_TSO_FW_RELASE_MINOR 0x6
4344#define TG3_TSO_FW_RELEASE_FIX 0x0
4345#define TG3_TSO_FW_START_ADDR 0x08000000
4346#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4347#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4348#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4349#define TG3_TSO_FW_RODATA_LEN 0x60
4350#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4351#define TG3_TSO_FW_DATA_LEN 0x30
4352#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4353#define TG3_TSO_FW_SBSS_LEN 0x2c
4354#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4355#define TG3_TSO_FW_BSS_LEN 0x894
4356
4357static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4358 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4359 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4360 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4361 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4362 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4363 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4364 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4365 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4366 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4367 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4368 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4369 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4370 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4371 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4372 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4373 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4374 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4375 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4376 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4377 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4378 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4379 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4380 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4381 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4382 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4383 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4384 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4385 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4386 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4387 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4388 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4389 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4390 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4391 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4392 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4393 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4394 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4395 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4396 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4397 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4398 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4399 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4400 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4401 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4402 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4403 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4404 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4405 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4406 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4407 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4408 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4409 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4410 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4411 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4412 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4413 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4414 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4415 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4416 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4417 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4418 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4419 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4420 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4421 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4422 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4423 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4424 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4425 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4426 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4427 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4428 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4429 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4430 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4431 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4432 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4433 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4434 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4435 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4436 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4437 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4438 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4439 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4440 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4441 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4442 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4443 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4444 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4445 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4446 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4447 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4448 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4449 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4450 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4451 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4452 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4453 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4454 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4455 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4456 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4457 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4458 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4459 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4460 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4461 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4462 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4463 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4464 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4465 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4466 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4467 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4468 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4469 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4470 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4471 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4472 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4473 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4474 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4475 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4476 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4477 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4478 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4479 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4480 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4481 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4482 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4483 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4484 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4485 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4486 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4487 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4488 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4489 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4490 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4491 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4492 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4493 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4494 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4495 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4496 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4497 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4498 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4499 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4500 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4501 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4502 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4503 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4504 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4505 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4506 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4507 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4508 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4509 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4510 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4511 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4512 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4513 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4514 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4515 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4516 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4517 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4518 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4519 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4520 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4521 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4522 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4523 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4524 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4525 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4526 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4527 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4528 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4529 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4530 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4531 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4532 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4533 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4534 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4535 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4536 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4537 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4538 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4539 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4540 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4541 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4542 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4543 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4544 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4545 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4546 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4547 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4548 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4549 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4550 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4551 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4552 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4553 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4554 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4555 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4556 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4557 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4558 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4559 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4560 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4561 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4562 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4563 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4564 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4565 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4566 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4567 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4568 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4569 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4570 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4571 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4572 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4573 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4574 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4575 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4576 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4577 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4578 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4579 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4580 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4581 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4582 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4583 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4584 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4585 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4586 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4587 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4588 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4589 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4590 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4591 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4592 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4593 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4594 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4595 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4596 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4597 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4598 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4599 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4600 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4601 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4602 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4603 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4604 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4605 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4606 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4607 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4608 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4609 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4610 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4611 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4612 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4613 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4614 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4615 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4616 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4617 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4618 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4619 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4620 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4621 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4622 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4623 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4624 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4625 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4626 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4627 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4628 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4629 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4630 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4631 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4632 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4633 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4634 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4635 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4636 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4637 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4638 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4639 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4640 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4641 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4642};
4643
4644static u32 tg3TsoFwRodata[] = {
4645 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4646 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4647 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4648 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4649 0x00000000,
4650};
4651
4652static u32 tg3TsoFwData[] = {
4653 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4654 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4655 0x00000000,
4656};
4657
4658/* 5705 needs a special version of the TSO firmware. */
4659#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4660#define TG3_TSO5_FW_RELASE_MINOR 0x2
4661#define TG3_TSO5_FW_RELEASE_FIX 0x0
4662#define TG3_TSO5_FW_START_ADDR 0x00010000
4663#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4664#define TG3_TSO5_FW_TEXT_LEN 0xe90
4665#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4666#define TG3_TSO5_FW_RODATA_LEN 0x50
4667#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4668#define TG3_TSO5_FW_DATA_LEN 0x20
4669#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4670#define TG3_TSO5_FW_SBSS_LEN 0x28
4671#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4672#define TG3_TSO5_FW_BSS_LEN 0x88
4673
4674static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4675 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4676 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4677 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4678 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4679 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4680 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4681 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4682 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4683 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4684 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4685 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4686 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4687 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4688 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4689 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4690 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4691 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4692 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4693 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4694 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4695 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4696 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4697 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4698 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4699 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4700 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4701 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4702 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4703 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4704 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4705 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4706 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4707 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4708 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4709 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4710 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4711 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4712 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4713 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4714 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4715 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4716 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4717 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4718 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4719 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4720 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4721 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4722 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4723 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4724 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4725 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4726 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4727 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4728 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4729 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4730 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4731 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4732 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4733 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4734 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4735 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4736 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4737 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4738 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4739 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4740 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4741 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4742 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4743 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4744 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4745 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4746 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4747 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4748 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4749 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4750 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4751 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4752 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4753 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4754 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4755 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4756 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4757 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4758 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4759 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4760 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4761 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4762 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4763 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4764 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4765 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4766 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4767 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4768 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4769 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4770 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4771 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4772 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4773 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4774 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4775 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4776 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4777 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4778 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4779 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4780 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4781 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4782 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4783 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4784 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4785 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4786 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4787 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4788 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4789 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4790 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4791 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4792 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4793 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4794 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4795 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4796 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4797 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4798 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4799 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4800 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4801 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4802 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4803 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4804 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4805 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4806 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4807 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4808 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4809 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4810 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4811 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4812 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4813 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4814 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4815 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4816 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4817 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4818 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4819 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4820 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4821 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4822 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4823 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4824 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4825 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4826 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4827 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4828 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4829 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4830 0x00000000, 0x00000000, 0x00000000,
4831};
4832
4833static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4834 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4835 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4836 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4837 0x00000000, 0x00000000, 0x00000000,
4838};
4839
4840static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4841 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4842 0x00000000, 0x00000000, 0x00000000,
4843};
4844
4845/* tp->lock is held. */
4846static int tg3_load_tso_firmware(struct tg3 *tp)
4847{
4848 struct fw_info info;
4849 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4850 int err, i;
4851
4852 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4853 return 0;
4854
4855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4856 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4857 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4858 info.text_data = &tg3Tso5FwText[0];
4859 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4860 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4861 info.rodata_data = &tg3Tso5FwRodata[0];
4862 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4863 info.data_len = TG3_TSO5_FW_DATA_LEN;
4864 info.data_data = &tg3Tso5FwData[0];
4865 cpu_base = RX_CPU_BASE;
4866 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4867 cpu_scratch_size = (info.text_len +
4868 info.rodata_len +
4869 info.data_len +
4870 TG3_TSO5_FW_SBSS_LEN +
4871 TG3_TSO5_FW_BSS_LEN);
4872 } else {
4873 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4874 info.text_len = TG3_TSO_FW_TEXT_LEN;
4875 info.text_data = &tg3TsoFwText[0];
4876 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
4877 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
4878 info.rodata_data = &tg3TsoFwRodata[0];
4879 info.data_base = TG3_TSO_FW_DATA_ADDR;
4880 info.data_len = TG3_TSO_FW_DATA_LEN;
4881 info.data_data = &tg3TsoFwData[0];
4882 cpu_base = TX_CPU_BASE;
4883 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
4884 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
4885 }
4886
4887 err = tg3_load_firmware_cpu(tp, cpu_base,
4888 cpu_scratch_base, cpu_scratch_size,
4889 &info);
4890 if (err)
4891 return err;
4892
4893 /* Now startup the cpu. */
4894 tw32(cpu_base + CPU_STATE, 0xffffffff);
4895 tw32_f(cpu_base + CPU_PC, info.text_base);
4896
4897 for (i = 0; i < 5; i++) {
4898 if (tr32(cpu_base + CPU_PC) == info.text_base)
4899 break;
4900 tw32(cpu_base + CPU_STATE, 0xffffffff);
4901 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
4902 tw32_f(cpu_base + CPU_PC, info.text_base);
4903 udelay(1000);
4904 }
4905 if (i >= 5) {
4906 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
4907 "to set CPU PC, is %08x should be %08x\n",
4908 tp->dev->name, tr32(cpu_base + CPU_PC),
4909 info.text_base);
4910 return -ENODEV;
4911 }
4912 tw32(cpu_base + CPU_STATE, 0xffffffff);
4913 tw32_f(cpu_base + CPU_MODE, 0x00000000);
4914 return 0;
4915}
4916
4917#endif /* TG3_TSO_SUPPORT != 0 */
4918
4919/* tp->lock is held. */
4920static void __tg3_set_mac_addr(struct tg3 *tp)
4921{
4922 u32 addr_high, addr_low;
4923 int i;
4924
4925 addr_high = ((tp->dev->dev_addr[0] << 8) |
4926 tp->dev->dev_addr[1]);
4927 addr_low = ((tp->dev->dev_addr[2] << 24) |
4928 (tp->dev->dev_addr[3] << 16) |
4929 (tp->dev->dev_addr[4] << 8) |
4930 (tp->dev->dev_addr[5] << 0));
4931 for (i = 0; i < 4; i++) {
4932 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
4933 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
4934 }
4935
4936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
4938 for (i = 0; i < 12; i++) {
4939 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
4940 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
4941 }
4942 }
4943
4944 addr_high = (tp->dev->dev_addr[0] +
4945 tp->dev->dev_addr[1] +
4946 tp->dev->dev_addr[2] +
4947 tp->dev->dev_addr[3] +
4948 tp->dev->dev_addr[4] +
4949 tp->dev->dev_addr[5]) &
4950 TX_BACKOFF_SEED_MASK;
4951 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4952}
4953
4954static int tg3_set_mac_addr(struct net_device *dev, void *p)
4955{
4956 struct tg3 *tp = netdev_priv(dev);
4957 struct sockaddr *addr = p;
4958
4959 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4960
4961 spin_lock_irq(&tp->lock);
4962 __tg3_set_mac_addr(tp);
4963 spin_unlock_irq(&tp->lock);
4964
4965 return 0;
4966}
4967
4968/* tp->lock is held. */
4969static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
4970 dma_addr_t mapping, u32 maxlen_flags,
4971 u32 nic_addr)
4972{
4973 tg3_write_mem(tp,
4974 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
4975 ((u64) mapping >> 32));
4976 tg3_write_mem(tp,
4977 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
4978 ((u64) mapping & 0xffffffff));
4979 tg3_write_mem(tp,
4980 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
4981 maxlen_flags);
4982
4983 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4984 tg3_write_mem(tp,
4985 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
4986 nic_addr);
4987}
4988
4989static void __tg3_set_rx_mode(struct net_device *);
4990
4991/* tp->lock is held. */
4992static int tg3_reset_hw(struct tg3 *tp)
4993{
4994 u32 val, rdmac_mode;
4995 int i, err, limit;
4996
4997 tg3_disable_ints(tp);
4998
4999 tg3_stop_fw(tp);
5000
5001 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5002
5003 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5004 err = tg3_abort_hw(tp);
5005 if (err)
5006 return err;
5007 }
5008
5009 err = tg3_chip_reset(tp);
5010 if (err)
5011 return err;
5012
5013 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5014
5015 /* This works around an issue with Athlon chipsets on
5016 * B3 tigon3 silicon. This bit has no effect on any
5017 * other revision. But do not set this on PCI Express
5018 * chips.
5019 */
5020 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5021 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5022 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5023
5024 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5025 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5026 val = tr32(TG3PCI_PCISTATE);
5027 val |= PCISTATE_RETRY_SAME_DMA;
5028 tw32(TG3PCI_PCISTATE, val);
5029 }
5030
5031 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5032 /* Enable some hw fixes. */
5033 val = tr32(TG3PCI_MSI_DATA);
5034 val |= (1 << 26) | (1 << 28) | (1 << 29);
5035 tw32(TG3PCI_MSI_DATA, val);
5036 }
5037
5038 /* Descriptor ring init may make accesses to the
5039 * NIC SRAM area to setup the TX descriptors, so we
5040 * can only do this after the hardware has been
5041 * successfully reset.
5042 */
5043 tg3_init_rings(tp);
5044
5045 /* This value is determined during the probe time DMA
5046 * engine test, tg3_test_dma.
5047 */
5048 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5049
5050 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5051 GRC_MODE_4X_NIC_SEND_RINGS |
5052 GRC_MODE_NO_TX_PHDR_CSUM |
5053 GRC_MODE_NO_RX_PHDR_CSUM);
5054 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5055 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5056 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5057 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5058 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5059
5060 tw32(GRC_MODE,
5061 tp->grc_mode |
5062 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5063
5064 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5065 val = tr32(GRC_MISC_CFG);
5066 val &= ~0xff;
5067 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5068 tw32(GRC_MISC_CFG, val);
5069
5070 /* Initialize MBUF/DESC pool. */
cbf46853 5071 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5072 /* Do nothing. */
5073 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5074 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5076 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5077 else
5078 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5079 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5080 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5081 }
5082#if TG3_TSO_SUPPORT != 0
5083 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5084 int fw_len;
5085
5086 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5087 TG3_TSO5_FW_RODATA_LEN +
5088 TG3_TSO5_FW_DATA_LEN +
5089 TG3_TSO5_FW_SBSS_LEN +
5090 TG3_TSO5_FW_BSS_LEN);
5091 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5092 tw32(BUFMGR_MB_POOL_ADDR,
5093 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5094 tw32(BUFMGR_MB_POOL_SIZE,
5095 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5096 }
5097#endif
5098
5099 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5100 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5101 tp->bufmgr_config.mbuf_read_dma_low_water);
5102 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5103 tp->bufmgr_config.mbuf_mac_rx_low_water);
5104 tw32(BUFMGR_MB_HIGH_WATER,
5105 tp->bufmgr_config.mbuf_high_water);
5106 } else {
5107 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5108 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5109 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5110 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5111 tw32(BUFMGR_MB_HIGH_WATER,
5112 tp->bufmgr_config.mbuf_high_water_jumbo);
5113 }
5114 tw32(BUFMGR_DMA_LOW_WATER,
5115 tp->bufmgr_config.dma_low_water);
5116 tw32(BUFMGR_DMA_HIGH_WATER,
5117 tp->bufmgr_config.dma_high_water);
5118
5119 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5120 for (i = 0; i < 2000; i++) {
5121 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5122 break;
5123 udelay(10);
5124 }
5125 if (i >= 2000) {
5126 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5127 tp->dev->name);
5128 return -ENODEV;
5129 }
5130
5131 /* Setup replenish threshold. */
5132 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5133
5134 /* Initialize TG3_BDINFO's at:
5135 * RCVDBDI_STD_BD: standard eth size rx ring
5136 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5137 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5138 *
5139 * like so:
5140 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5141 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5142 * ring attribute flags
5143 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5144 *
5145 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5146 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5147 *
5148 * The size of each ring is fixed in the firmware, but the location is
5149 * configurable.
5150 */
5151 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5152 ((u64) tp->rx_std_mapping >> 32));
5153 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5154 ((u64) tp->rx_std_mapping & 0xffffffff));
5155 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5156 NIC_SRAM_RX_BUFFER_DESC);
5157
5158 /* Don't even try to program the JUMBO/MINI buffer descriptor
5159 * configs on 5705.
5160 */
5161 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5162 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5163 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5164 } else {
5165 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5166 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5167
5168 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5169 BDINFO_FLAGS_DISABLED);
5170
5171 /* Setup replenish threshold. */
5172 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5173
5174 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5175 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5176 ((u64) tp->rx_jumbo_mapping >> 32));
5177 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5178 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5179 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5180 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5181 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5182 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5183 } else {
5184 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5185 BDINFO_FLAGS_DISABLED);
5186 }
5187
5188 }
5189
5190 /* There is only one send ring on 5705/5750, no need to explicitly
5191 * disable the others.
5192 */
5193 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5194 /* Clear out send RCB ring in SRAM. */
5195 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5196 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5197 BDINFO_FLAGS_DISABLED);
5198 }
5199
5200 tp->tx_prod = 0;
5201 tp->tx_cons = 0;
5202 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5203 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5204
5205 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5206 tp->tx_desc_mapping,
5207 (TG3_TX_RING_SIZE <<
5208 BDINFO_FLAGS_MAXLEN_SHIFT),
5209 NIC_SRAM_TX_BUFFER_DESC);
5210
5211 /* There is only one receive return ring on 5705/5750, no need
5212 * to explicitly disable the others.
5213 */
5214 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5215 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5216 i += TG3_BDINFO_SIZE) {
5217 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5218 BDINFO_FLAGS_DISABLED);
5219 }
5220 }
5221
5222 tp->rx_rcb_ptr = 0;
5223 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5224
5225 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5226 tp->rx_rcb_mapping,
5227 (TG3_RX_RCB_RING_SIZE(tp) <<
5228 BDINFO_FLAGS_MAXLEN_SHIFT),
5229 0);
5230
5231 tp->rx_std_ptr = tp->rx_pending;
5232 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5233 tp->rx_std_ptr);
5234
5235 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5236 tp->rx_jumbo_pending : 0;
5237 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5238 tp->rx_jumbo_ptr);
5239
5240 /* Initialize MAC address and backoff seed. */
5241 __tg3_set_mac_addr(tp);
5242
5243 /* MTU + ethernet header + FCS + optional VLAN tag */
5244 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5245
5246 /* The slot time is changed by tg3_setup_phy if we
5247 * run at gigabit with half duplex.
5248 */
5249 tw32(MAC_TX_LENGTHS,
5250 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5251 (6 << TX_LENGTHS_IPG_SHIFT) |
5252 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5253
5254 /* Receive rules. */
5255 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5256 tw32(RCVLPC_CONFIG, 0x0181);
5257
5258 /* Calculate RDMAC_MODE setting early, we need it to determine
5259 * the RCVLPC_STATE_ENABLE mask.
5260 */
5261 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5262 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5263 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5264 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5265 RDMAC_MODE_LNGREAD_ENAB);
5266 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5267 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5268
5269 /* If statement applies to 5705 and 5750 PCI devices only */
5270 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5271 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5272 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5273 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5274 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5275 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5276 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5277 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5278 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5279 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5280 }
5281 }
5282
85e94ced
MC		 5283 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5284 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5285
1da177e4
LT		 5286#if TG3_TSO_SUPPORT != 0
5287 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5288 rdmac_mode |= (1 << 27);
5289#endif
5290
5291 /* Receive/send statistics. */
5292 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5293 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5294 val = tr32(RCVLPC_STATS_ENABLE);
5295 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5296 tw32(RCVLPC_STATS_ENABLE, val);
5297 } else {
5298 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5299 }
5300 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5301 tw32(SNDDATAI_STATSENAB, 0xffffff);
5302 tw32(SNDDATAI_STATSCTRL,
5303 (SNDDATAI_SCTRL_ENABLE |
5304 SNDDATAI_SCTRL_FASTUPD));
5305
5306 /* Setup host coalescing engine. */
5307 tw32(HOSTCC_MODE, 0);
5308 for (i = 0; i < 2000; i++) {
5309 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5310 break;
5311 udelay(10);
5312 }
5313
5314 tw32(HOSTCC_RXCOL_TICKS, 0);
5315 tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
5316 tw32(HOSTCC_RXMAX_FRAMES, 1);
5317 tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
5318 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5319 tw32(HOSTCC_RXCOAL_TICK_INT, 0);
5320 tw32(HOSTCC_TXCOAL_TICK_INT, 0);
5321 }
5322 tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
5323 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
5324
5325 /* set status block DMA address */
5326 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5327 ((u64) tp->status_mapping >> 32));
5328 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5329 ((u64) tp->status_mapping & 0xffffffff));
5330
5331 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5332 /* Status/statistics block address. See tg3_timer,
5333 * the tg3_periodic_fetch_stats call there, and
5334 * tg3_get_stats to see how this works for 5705/5750 chips.
5335 */
5336 tw32(HOSTCC_STAT_COAL_TICKS,
5337 DEFAULT_STAT_COAL_TICKS);
5338 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5339 ((u64) tp->stats_mapping >> 32));
5340 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5341 ((u64) tp->stats_mapping & 0xffffffff));
5342 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5343 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5344 }
5345
5346 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5347
5348 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5349 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5350 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5351 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5352
5353 /* Clear statistics/status block in chip, and status block in ram. */
5354 for (i = NIC_SRAM_STATS_BLK;
5355 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5356 i += sizeof(u32)) {
5357 tg3_write_mem(tp, i, 0);
5358 udelay(40);
5359 }
5360 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5361
5362 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5363 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5364 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5365 udelay(40);
5366
314fba34
MC		 5367 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5368 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5369 * register to preserve the GPIO settings for LOMs. The GPIOs,
5370 * whether used as inputs or outputs, are set by boot code after
5371 * reset.
5372 */
5373 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5374 u32 gpio_mask;
5375
5376 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5377 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5378
5379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5380 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5381 GRC_LCLCTRL_GPIO_OUTPUT3;
5382
314fba34
MC		 5383 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5384
5385 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5386 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5387 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5388 }
1da177e4
LT		 5389 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5390 udelay(100);
5391
5392 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5393 tr32(MAILBOX_INTERRUPT_0);
5394
5395 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5396 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5397 udelay(40);
5398 }
5399
5400 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5401 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5402 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5403 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5404 WDMAC_MODE_LNGREAD_ENAB);
5405
85e94ced
MC		 5406 /* If statement applies to 5705 and 5750 PCI devices only */
5407 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5408 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5410 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5411 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5412 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5413 /* nothing */
5414 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5415 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5416 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5417 val |= WDMAC_MODE_RX_ACCEL;
5418 }
5419 }
5420
5421 tw32_f(WDMAC_MODE, val);
5422 udelay(40);
5423
5424 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5425 val = tr32(TG3PCI_X_CAPS);
5426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5427 val &= ~PCIX_CAPS_BURST_MASK;
5428 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5429 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5430 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5431 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5432 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5433 val |= (tp->split_mode_max_reqs <<
5434 PCIX_CAPS_SPLIT_SHIFT);
5435 }
5436 tw32(TG3PCI_X_CAPS, val);
5437 }
5438
5439 tw32_f(RDMAC_MODE, rdmac_mode);
5440 udelay(40);
5441
5442 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5443 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5444 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5445 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5446 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5447 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5448 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5449 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5450#if TG3_TSO_SUPPORT != 0
5451 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5452 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5453#endif
5454 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5455 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5456
5457 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5458 err = tg3_load_5701_a0_firmware_fix(tp);
5459 if (err)
5460 return err;
5461 }
5462
5463#if TG3_TSO_SUPPORT != 0
5464 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5465 err = tg3_load_tso_firmware(tp);
5466 if (err)
5467 return err;
5468 }
5469#endif
5470
5471 tp->tx_mode = TX_MODE_ENABLE;
5472 tw32_f(MAC_TX_MODE, tp->tx_mode);
5473 udelay(100);
5474
5475 tp->rx_mode = RX_MODE_ENABLE;
5476 tw32_f(MAC_RX_MODE, tp->rx_mode);
5477 udelay(10);
5478
5479 if (tp->link_config.phy_is_low_power) {
5480 tp->link_config.phy_is_low_power = 0;
5481 tp->link_config.speed = tp->link_config.orig_speed;
5482 tp->link_config.duplex = tp->link_config.orig_duplex;
5483 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5484 }
5485
5486 tp->mi_mode = MAC_MI_MODE_BASE;
5487 tw32_f(MAC_MI_MODE, tp->mi_mode);
5488 udelay(80);
5489
5490 tw32(MAC_LED_CTRL, tp->led_ctrl);
5491
5492 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5493 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5494 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5495 udelay(10);
5496 }
5497 tw32_f(MAC_RX_MODE, tp->rx_mode);
5498 udelay(10);
5499
5500 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5501 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5502 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5503 /* Set drive transmission level to 1.2V */
5504 /* only if the signal pre-emphasis bit is not set */
5505 val = tr32(MAC_SERDES_CFG);
5506 val &= 0xfffff000;
5507 val |= 0x880;
5508 tw32(MAC_SERDES_CFG, val);
5509 }
5510 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5511 tw32(MAC_SERDES_CFG, 0x616000);
5512 }
5513
5514 /* Prevent chip from dropping frames when flow control
5515 * is enabled.
5516 */
5517 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5518
5519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5520 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5521 /* Use hardware link auto-negotiation */
5522 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5523 }
5524
5525 err = tg3_setup_phy(tp, 1);
5526 if (err)
5527 return err;
5528
5529 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5530 u32 tmp;
5531
5532 /* Clear CRC stats. */
5533 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5534 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5535 tg3_readphy(tp, 0x14, &tmp);
5536 }
5537 }
5538
5539 __tg3_set_rx_mode(tp->dev);
5540
5541 /* Initialize receive rules. */
5542 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
5543 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5544 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5545 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5546
5547 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5548 limit = 8;
5549 else
5550 limit = 16;
5551 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5552 limit -= 4;
5553 switch (limit) {
5554 case 16:
5555 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
5556 case 15:
5557 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
5558 case 14:
5559 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
5560 case 13:
5561 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
5562 case 12:
5563 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
5564 case 11:
5565 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
5566 case 10:
5567 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
5568 case 9:
5569 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
5570 case 8:
5571 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
5572 case 7:
5573 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
5574 case 6:
5575 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
5576 case 5:
5577 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
5578 case 4:
5579 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5580 case 3:
5581 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5582 case 2:
5583 case 1:
5584
5585 default:
5586 break;
5587 };
5588
5589 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5590
5591 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5592 tg3_enable_ints(tp);
5593
5594 return 0;
5595}
5596
5597/* Called at device open time to get the chip ready for
5598 * packet processing. Invoked with tp->lock held.
5599 */
5600static int tg3_init_hw(struct tg3 *tp)
5601{
5602 int err;
5603
5604 /* Force the chip into D0. */
5605 err = tg3_set_power_state(tp, 0);
5606 if (err)
5607 goto out;
5608
5609 tg3_switch_clocks(tp);
5610
5611 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5612
5613 err = tg3_reset_hw(tp);
5614
5615out:
5616 return err;
5617}
5618
5619#define TG3_STAT_ADD32(PSTAT, REG) \
5620do { u32 __val = tr32(REG); \
5621 (PSTAT)->low += __val; \
5622 if ((PSTAT)->low < __val) \
5623 (PSTAT)->high += 1; \
5624} while (0)
5625
5626static void tg3_periodic_fetch_stats(struct tg3 *tp)
5627{
5628 struct tg3_hw_stats *sp = tp->hw_stats;
5629
5630 if (!netif_carrier_ok(tp->dev))
5631 return;
5632
5633 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5634 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5635 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5636 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5637 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5638 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5639 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5640 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5641 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5642 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5643 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5644 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5645 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5646
5647 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5648 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5649 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5650 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5651 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5652 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5653 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5654 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5655 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5656 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5657 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5658 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5659 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5660 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5661}
5662
5663static void tg3_timer(unsigned long __opaque)
5664{
5665 struct tg3 *tp = (struct tg3 *) __opaque;
5666 unsigned long flags;
5667
5668 spin_lock_irqsave(&tp->lock, flags);
5669 spin_lock(&tp->tx_lock);
5670
5671 /* All of this garbage is because when using non-tagged
5672 * IRQ status the mailbox/status_block protocol the chip
5673 * uses with the cpu is race prone.
5674 */
5675 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5676 tw32(GRC_LOCAL_CTRL,
5677 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5678 } else {
5679 tw32(HOSTCC_MODE, tp->coalesce_mode |
5680 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5681 }
5682
5683 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5684 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5685 spin_unlock(&tp->tx_lock);
5686 spin_unlock_irqrestore(&tp->lock, flags);
5687 schedule_work(&tp->reset_task);
5688 return;
5689 }
5690
5691 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5692 tg3_periodic_fetch_stats(tp);
5693
5694 /* This part only runs once per second. */
5695 if (!--tp->timer_counter) {
5696 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5697 u32 mac_stat;
5698 int phy_event;
5699
5700 mac_stat = tr32(MAC_STATUS);
5701
5702 phy_event = 0;
5703 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5704 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5705 phy_event = 1;
5706 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5707 phy_event = 1;
5708
5709 if (phy_event)
5710 tg3_setup_phy(tp, 0);
5711 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5712 u32 mac_stat = tr32(MAC_STATUS);
5713 int need_setup = 0;
5714
5715 if (netif_carrier_ok(tp->dev) &&
5716 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5717 need_setup = 1;
5718 }
5719 if (! netif_carrier_ok(tp->dev) &&
5720 (mac_stat & (MAC_STATUS_PCS_SYNCED |
5721 MAC_STATUS_SIGNAL_DET))) {
5722 need_setup = 1;
5723 }
5724 if (need_setup) {
5725 tw32_f(MAC_MODE,
5726 (tp->mac_mode &
5727 ~MAC_MODE_PORT_MODE_MASK));
5728 udelay(40);
5729 tw32_f(MAC_MODE, tp->mac_mode);
5730 udelay(40);
5731 tg3_setup_phy(tp, 0);
5732 }
5733 }
5734
5735 tp->timer_counter = tp->timer_multiplier;
5736 }
5737
5738 /* Heartbeat is only sent once every 120 seconds. */
5739 if (!--tp->asf_counter) {
5740 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5741 u32 val;
5742
5743 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5744 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5745 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5746 val = tr32(GRC_RX_CPU_EVENT);
5747 val |= (1 << 14);
5748 tw32(GRC_RX_CPU_EVENT, val);
5749 }
5750 tp->asf_counter = tp->asf_multiplier;
5751 }
5752
5753 spin_unlock(&tp->tx_lock);
5754 spin_unlock_irqrestore(&tp->lock, flags);
5755
5756 tp->timer.expires = jiffies + tp->timer_offset;
5757 add_timer(&tp->timer);
5758}
5759
5760static int tg3_open(struct net_device *dev)
5761{
5762 struct tg3 *tp = netdev_priv(dev);
5763 int err;
5764
5765 spin_lock_irq(&tp->lock);
5766 spin_lock(&tp->tx_lock);
5767
5768 tg3_disable_ints(tp);
5769 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
5770
5771 spin_unlock(&tp->tx_lock);
5772 spin_unlock_irq(&tp->lock);
5773
5774 /* The placement of this call is tied
5775 * to the setup and use of Host TX descriptors.
5776 */
5777 err = tg3_alloc_consistent(tp);
5778 if (err)
5779 return err;
5780
5781 err = request_irq(dev->irq, tg3_interrupt,
5782 SA_SHIRQ, dev->name, dev);
5783
5784 if (err) {
5785 tg3_free_consistent(tp);
5786 return err;
5787 }
5788
5789 spin_lock_irq(&tp->lock);
5790 spin_lock(&tp->tx_lock);
5791
5792 err = tg3_init_hw(tp);
5793 if (err) {
5794 tg3_halt(tp);
5795 tg3_free_rings(tp);
5796 } else {
5797 tp->timer_offset = HZ / 10;
5798 tp->timer_counter = tp->timer_multiplier = 10;
5799 tp->asf_counter = tp->asf_multiplier = (10 * 120);
5800
5801 init_timer(&tp->timer);
5802 tp->timer.expires = jiffies + tp->timer_offset;
5803 tp->timer.data = (unsigned long) tp;
5804 tp->timer.function = tg3_timer;
5805 add_timer(&tp->timer);
5806
5807 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
5808 }
5809
5810 spin_unlock(&tp->tx_lock);
5811 spin_unlock_irq(&tp->lock);
5812
5813 if (err) {
5814 free_irq(dev->irq, dev);
5815 tg3_free_consistent(tp);
5816 return err;
5817 }
5818
5819 spin_lock_irq(&tp->lock);
5820 spin_lock(&tp->tx_lock);
5821
5822 tg3_enable_ints(tp);
5823
5824 spin_unlock(&tp->tx_lock);
5825 spin_unlock_irq(&tp->lock);
5826
5827 netif_start_queue(dev);
5828
5829 return 0;
5830}
5831
5832#if 0
5833/*static*/ void tg3_dump_state(struct tg3 *tp)
5834{
5835 u32 val32, val32_2, val32_3, val32_4, val32_5;
5836 u16 val16;
5837 int i;
5838
5839 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
5840 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
5841 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
5842 val16, val32);
5843
5844 /* MAC block */
5845 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
5846 tr32(MAC_MODE), tr32(MAC_STATUS));
5847 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
5848 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
5849 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
5850 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
5851 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
5852 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
5853
5854 /* Send data initiator control block */
5855 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
5856 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
5857 printk(" SNDDATAI_STATSCTRL[%08x]\n",
5858 tr32(SNDDATAI_STATSCTRL));
5859
5860 /* Send data completion control block */
5861 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
5862
5863 /* Send BD ring selector block */
5864 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
5865 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
5866
5867 /* Send BD initiator control block */
5868 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
5869 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
5870
5871 /* Send BD completion control block */
5872 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
5873
5874 /* Receive list placement control block */
5875 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
5876 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
5877 printk(" RCVLPC_STATSCTRL[%08x]\n",
5878 tr32(RCVLPC_STATSCTRL));
5879
5880 /* Receive data and receive BD initiator control block */
5881 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
5882 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
5883
5884 /* Receive data completion control block */
5885 printk("DEBUG: RCVDCC_MODE[%08x]\n",
5886 tr32(RCVDCC_MODE));
5887
5888 /* Receive BD initiator control block */
5889 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
5890 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
5891
5892 /* Receive BD completion control block */
5893 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
5894 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
5895
5896 /* Receive list selector control block */
5897 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
5898 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
5899
5900 /* Mbuf cluster free block */
5901 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
5902 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
5903
5904 /* Host coalescing control block */
5905 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
5906 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
5907 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
5908 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
5909 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
5910 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
5911 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
5912 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
5913 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
5914 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
5915 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
5916 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
5917
5918 /* Memory arbiter control block */
5919 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
5920 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
5921
5922 /* Buffer manager control block */
5923 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
5924 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
5925 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
5926 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
5927 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
5928 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
5929 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
5930 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
5931
5932 /* Read DMA control block */
5933 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
5934 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
5935
5936 /* Write DMA control block */
5937 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
5938 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
5939
5940 /* DMA completion block */
5941 printk("DEBUG: DMAC_MODE[%08x]\n",
5942 tr32(DMAC_MODE));
5943
5944 /* GRC block */
5945 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
5946 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
5947 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
5948 tr32(GRC_LOCAL_CTRL));
5949
5950 /* TG3_BDINFOs */
5951 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
5952 tr32(RCVDBDI_JUMBO_BD + 0x0),
5953 tr32(RCVDBDI_JUMBO_BD + 0x4),
5954 tr32(RCVDBDI_JUMBO_BD + 0x8),
5955 tr32(RCVDBDI_JUMBO_BD + 0xc));
5956 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
5957 tr32(RCVDBDI_STD_BD + 0x0),
5958 tr32(RCVDBDI_STD_BD + 0x4),
5959 tr32(RCVDBDI_STD_BD + 0x8),
5960 tr32(RCVDBDI_STD_BD + 0xc));
5961 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
5962 tr32(RCVDBDI_MINI_BD + 0x0),
5963 tr32(RCVDBDI_MINI_BD + 0x4),
5964 tr32(RCVDBDI_MINI_BD + 0x8),
5965 tr32(RCVDBDI_MINI_BD + 0xc));
5966
5967 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
5968 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
5969 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
5970 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
5971 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
5972 val32, val32_2, val32_3, val32_4);
5973
5974 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
5975 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
5976 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
5977 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
5978 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
5979 val32, val32_2, val32_3, val32_4);
5980
5981 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
5982 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
5983 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
5984 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
5985 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
5986 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
5987 val32, val32_2, val32_3, val32_4, val32_5);
5988
5989 /* SW status block */
5990 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5991 tp->hw_status->status,
5992 tp->hw_status->status_tag,
5993 tp->hw_status->rx_jumbo_consumer,
5994 tp->hw_status->rx_consumer,
5995 tp->hw_status->rx_mini_consumer,
5996 tp->hw_status->idx[0].rx_producer,
5997 tp->hw_status->idx[0].tx_consumer);
5998
5999 /* SW statistics block */
6000 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6001 ((u32 *)tp->hw_stats)[0],
6002 ((u32 *)tp->hw_stats)[1],
6003 ((u32 *)tp->hw_stats)[2],
6004 ((u32 *)tp->hw_stats)[3]);
6005
6006 /* Mailboxes */
6007 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6008 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6009 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6010 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6011 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6012
6013 /* NIC side send descriptors. */
6014 for (i = 0; i < 6; i++) {
6015 unsigned long txd;
6016
6017 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6018 + (i * sizeof(struct tg3_tx_buffer_desc));
6019 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6020 i,
6021 readl(txd + 0x0), readl(txd + 0x4),
6022 readl(txd + 0x8), readl(txd + 0xc));
6023 }
6024
6025 /* NIC side RX descriptors. */
6026 for (i = 0; i < 6; i++) {
6027 unsigned long rxd;
6028
6029 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6030 + (i * sizeof(struct tg3_rx_buffer_desc));
6031 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6032 i,
6033 readl(rxd + 0x0), readl(rxd + 0x4),
6034 readl(rxd + 0x8), readl(rxd + 0xc));
6035 rxd += (4 * sizeof(u32));
6036 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6037 i,
6038 readl(rxd + 0x0), readl(rxd + 0x4),
6039 readl(rxd + 0x8), readl(rxd + 0xc));
6040 }
6041
6042 for (i = 0; i < 6; i++) {
6043 unsigned long rxd;
6044
6045 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6046 + (i * sizeof(struct tg3_rx_buffer_desc));
6047 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6048 i,
6049 readl(rxd + 0x0), readl(rxd + 0x4),
6050 readl(rxd + 0x8), readl(rxd + 0xc));
6051 rxd += (4 * sizeof(u32));
6052 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6053 i,
6054 readl(rxd + 0x0), readl(rxd + 0x4),
6055 readl(rxd + 0x8), readl(rxd + 0xc));
6056 }
6057}
6058#endif
6059
6060static struct net_device_stats *tg3_get_stats(struct net_device *);
6061static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6062
6063static int tg3_close(struct net_device *dev)
6064{
6065 struct tg3 *tp = netdev_priv(dev);
6066
6067 netif_stop_queue(dev);
6068
6069 del_timer_sync(&tp->timer);
6070
6071 spin_lock_irq(&tp->lock);
6072 spin_lock(&tp->tx_lock);
6073#if 0
6074 tg3_dump_state(tp);
6075#endif
6076
6077 tg3_disable_ints(tp);
6078
6079 tg3_halt(tp);
6080 tg3_free_rings(tp);
6081 tp->tg3_flags &=
6082 ~(TG3_FLAG_INIT_COMPLETE |
6083 TG3_FLAG_GOT_SERDES_FLOWCTL);
6084 netif_carrier_off(tp->dev);
6085
6086 spin_unlock(&tp->tx_lock);
6087 spin_unlock_irq(&tp->lock);
6088
6089 free_irq(dev->irq, dev);
6090
6091 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6092 sizeof(tp->net_stats_prev));
6093 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6094 sizeof(tp->estats_prev));
6095
6096 tg3_free_consistent(tp);
6097
6098 return 0;
6099}
6100
6101static inline unsigned long get_stat64(tg3_stat64_t *val)
6102{
6103 unsigned long ret;
6104
6105#if (BITS_PER_LONG == 32)
6106 ret = val->low;
6107#else
6108 ret = ((u64)val->high << 32) | ((u64)val->low);
6109#endif
6110 return ret;
6111}
6112
6113static unsigned long calc_crc_errors(struct tg3 *tp)
6114{
6115 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6116
6117 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6118 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6120 unsigned long flags;
6121 u32 val;
6122
6123 spin_lock_irqsave(&tp->lock, flags);
6124 if (!tg3_readphy(tp, 0x1e, &val)) {
6125 tg3_writephy(tp, 0x1e, val | 0x8000);
6126 tg3_readphy(tp, 0x14, &val);
6127 } else
6128 val = 0;
6129 spin_unlock_irqrestore(&tp->lock, flags);
6130
6131 tp->phy_crc_errors += val;
6132
6133 return tp->phy_crc_errors;
6134 }
6135
6136 return get_stat64(&hw_stats->rx_fcs_errors);
6137}
6138
6139#define ESTAT_ADD(member) \
6140 estats->member = old_estats->member + \
6141 get_stat64(&hw_stats->member)
6142
6143static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6144{
6145 struct tg3_ethtool_stats *estats = &tp->estats;
6146 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6147 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6148
6149 if (!hw_stats)
6150 return old_estats;
6151
6152 ESTAT_ADD(rx_octets);
6153 ESTAT_ADD(rx_fragments);
6154 ESTAT_ADD(rx_ucast_packets);
6155 ESTAT_ADD(rx_mcast_packets);
6156 ESTAT_ADD(rx_bcast_packets);
6157 ESTAT_ADD(rx_fcs_errors);
6158 ESTAT_ADD(rx_align_errors);
6159 ESTAT_ADD(rx_xon_pause_rcvd);
6160 ESTAT_ADD(rx_xoff_pause_rcvd);
6161 ESTAT_ADD(rx_mac_ctrl_rcvd);
6162 ESTAT_ADD(rx_xoff_entered);
6163 ESTAT_ADD(rx_frame_too_long_errors);
6164 ESTAT_ADD(rx_jabbers);
6165 ESTAT_ADD(rx_undersize_packets);
6166 ESTAT_ADD(rx_in_length_errors);
6167 ESTAT_ADD(rx_out_length_errors);
6168 ESTAT_ADD(rx_64_or_less_octet_packets);
6169 ESTAT_ADD(rx_65_to_127_octet_packets);
6170 ESTAT_ADD(rx_128_to_255_octet_packets);
6171 ESTAT_ADD(rx_256_to_511_octet_packets);
6172 ESTAT_ADD(rx_512_to_1023_octet_packets);
6173 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6174 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6175 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6176 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6177 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6178
6179 ESTAT_ADD(tx_octets);
6180 ESTAT_ADD(tx_collisions);
6181 ESTAT_ADD(tx_xon_sent);
6182 ESTAT_ADD(tx_xoff_sent);
6183 ESTAT_ADD(tx_flow_control);
6184 ESTAT_ADD(tx_mac_errors);
6185 ESTAT_ADD(tx_single_collisions);
6186 ESTAT_ADD(tx_mult_collisions);
6187 ESTAT_ADD(tx_deferred);
6188 ESTAT_ADD(tx_excessive_collisions);
6189 ESTAT_ADD(tx_late_collisions);
6190 ESTAT_ADD(tx_collide_2times);
6191 ESTAT_ADD(tx_collide_3times);
6192 ESTAT_ADD(tx_collide_4times);
6193 ESTAT_ADD(tx_collide_5times);
6194 ESTAT_ADD(tx_collide_6times);
6195 ESTAT_ADD(tx_collide_7times);
6196 ESTAT_ADD(tx_collide_8times);
6197 ESTAT_ADD(tx_collide_9times);
6198 ESTAT_ADD(tx_collide_10times);
6199 ESTAT_ADD(tx_collide_11times);
6200 ESTAT_ADD(tx_collide_12times);
6201 ESTAT_ADD(tx_collide_13times);
6202 ESTAT_ADD(tx_collide_14times);
6203 ESTAT_ADD(tx_collide_15times);
6204 ESTAT_ADD(tx_ucast_packets);
6205 ESTAT_ADD(tx_mcast_packets);
6206 ESTAT_ADD(tx_bcast_packets);
6207 ESTAT_ADD(tx_carrier_sense_errors);
6208 ESTAT_ADD(tx_discards);
6209 ESTAT_ADD(tx_errors);
6210
6211 ESTAT_ADD(dma_writeq_full);
6212 ESTAT_ADD(dma_write_prioq_full);
6213 ESTAT_ADD(rxbds_empty);
6214 ESTAT_ADD(rx_discards);
6215 ESTAT_ADD(rx_errors);
6216 ESTAT_ADD(rx_threshold_hit);
6217
6218 ESTAT_ADD(dma_readq_full);
6219 ESTAT_ADD(dma_read_prioq_full);
6220 ESTAT_ADD(tx_comp_queue_full);
6221
6222 ESTAT_ADD(ring_set_send_prod_index);
6223 ESTAT_ADD(ring_status_update);
6224 ESTAT_ADD(nic_irqs);
6225 ESTAT_ADD(nic_avoided_irqs);
6226 ESTAT_ADD(nic_tx_threshold_hit);
6227
6228 return estats;
6229}
6230
6231static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6232{
6233 struct tg3 *tp = netdev_priv(dev);
6234 struct net_device_stats *stats = &tp->net_stats;
6235 struct net_device_stats *old_stats = &tp->net_stats_prev;
6236 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6237
6238 if (!hw_stats)
6239 return old_stats;
6240
6241 stats->rx_packets = old_stats->rx_packets +
6242 get_stat64(&hw_stats->rx_ucast_packets) +
6243 get_stat64(&hw_stats->rx_mcast_packets) +
6244 get_stat64(&hw_stats->rx_bcast_packets);
6245
6246 stats->tx_packets = old_stats->tx_packets +
6247 get_stat64(&hw_stats->tx_ucast_packets) +
6248 get_stat64(&hw_stats->tx_mcast_packets) +
6249 get_stat64(&hw_stats->tx_bcast_packets);
6250
6251 stats->rx_bytes = old_stats->rx_bytes +
6252 get_stat64(&hw_stats->rx_octets);
6253 stats->tx_bytes = old_stats->tx_bytes +
6254 get_stat64(&hw_stats->tx_octets);
6255
6256 stats->rx_errors = old_stats->rx_errors +
6257 get_stat64(&hw_stats->rx_errors) +
6258 get_stat64(&hw_stats->rx_discards);
6259 stats->tx_errors = old_stats->tx_errors +
6260 get_stat64(&hw_stats->tx_errors) +
6261 get_stat64(&hw_stats->tx_mac_errors) +
6262 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6263 get_stat64(&hw_stats->tx_discards);
6264
6265 stats->multicast = old_stats->multicast +
6266 get_stat64(&hw_stats->rx_mcast_packets);
6267 stats->collisions = old_stats->collisions +
6268 get_stat64(&hw_stats->tx_collisions);
6269
6270 stats->rx_length_errors = old_stats->rx_length_errors +
6271 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6272 get_stat64(&hw_stats->rx_undersize_packets);
6273
6274 stats->rx_over_errors = old_stats->rx_over_errors +
6275 get_stat64(&hw_stats->rxbds_empty);
6276 stats->rx_frame_errors = old_stats->rx_frame_errors +
6277 get_stat64(&hw_stats->rx_align_errors);
6278 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6279 get_stat64(&hw_stats->tx_discards);
6280 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6281 get_stat64(&hw_stats->tx_carrier_sense_errors);
6282
6283 stats->rx_crc_errors = old_stats->rx_crc_errors +
6284 calc_crc_errors(tp);
6285
6286 return stats;
6287}
6288
6289static inline u32 calc_crc(unsigned char *buf, int len)
6290{
6291 u32 reg;
6292 u32 tmp;
6293 int j, k;
6294
6295 reg = 0xffffffff;
6296
6297 for (j = 0; j < len; j++) {
6298 reg ^= buf[j];
6299
6300 for (k = 0; k < 8; k++) {
6301 tmp = reg & 0x01;
6302
6303 reg >>= 1;
6304
6305 if (tmp) {
6306 reg ^= 0xedb88320;
6307 }
6308 }
6309 }
6310
6311 return ~reg;
6312}
6313
6314static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6315{
6316 /* accept or reject all multicast frames */
6317 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6318 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6319 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6320 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6321}
6322
6323static void __tg3_set_rx_mode(struct net_device *dev)
6324{
6325 struct tg3 *tp = netdev_priv(dev);
6326 u32 rx_mode;
6327
6328 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6329 RX_MODE_KEEP_VLAN_TAG);
6330
6331 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6332 * flag clear.
6333 */
6334#if TG3_VLAN_TAG_USED
6335 if (!tp->vlgrp &&
6336 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6337 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6338#else
6339 /* By definition, VLAN is disabled always in this
6340 * case.
6341 */
6342 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6343 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6344#endif
6345
6346 if (dev->flags & IFF_PROMISC) {
6347 /* Promiscuous mode. */
6348 rx_mode |= RX_MODE_PROMISC;
6349 } else if (dev->flags & IFF_ALLMULTI) {
6350 /* Accept all multicast. */
6351 tg3_set_multi (tp, 1);
6352 } else if (dev->mc_count < 1) {
6353 /* Reject all multicast. */
6354 tg3_set_multi (tp, 0);
6355 } else {
6356 /* Accept one or more multicast(s). */
6357 struct dev_mc_list *mclist;
6358 unsigned int i;
6359 u32 mc_filter[4] = { 0, };
6360 u32 regidx;
6361 u32 bit;
6362 u32 crc;
6363
6364 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6365 i++, mclist = mclist->next) {
6366
6367 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6368 bit = ~crc & 0x7f;
6369 regidx = (bit & 0x60) >> 5;
6370 bit &= 0x1f;
6371 mc_filter[regidx] |= (1 << bit);
6372 }
6373
6374 tw32(MAC_HASH_REG_0, mc_filter[0]);
6375 tw32(MAC_HASH_REG_1, mc_filter[1]);
6376 tw32(MAC_HASH_REG_2, mc_filter[2]);
6377 tw32(MAC_HASH_REG_3, mc_filter[3]);
6378 }
6379
6380 if (rx_mode != tp->rx_mode) {
6381 tp->rx_mode = rx_mode;
6382 tw32_f(MAC_RX_MODE, rx_mode);
6383 udelay(10);
6384 }
6385}
6386
6387static void tg3_set_rx_mode(struct net_device *dev)
6388{
6389 struct tg3 *tp = netdev_priv(dev);
6390
6391 spin_lock_irq(&tp->lock);
6392 spin_lock(&tp->tx_lock);
6393 __tg3_set_rx_mode(dev);
6394 spin_unlock(&tp->tx_lock);
6395 spin_unlock_irq(&tp->lock);
6396}
6397
6398#define TG3_REGDUMP_LEN (32 * 1024)
6399
6400static int tg3_get_regs_len(struct net_device *dev)
6401{
6402 return TG3_REGDUMP_LEN;
6403}
6404
6405static void tg3_get_regs(struct net_device *dev,
6406 struct ethtool_regs *regs, void *_p)
6407{
6408 u32 *p = _p;
6409 struct tg3 *tp = netdev_priv(dev);
6410 u8 *orig_p = _p;
6411 int i;
6412
6413 regs->version = 0;
6414
6415 memset(p, 0, TG3_REGDUMP_LEN);
6416
6417 spin_lock_irq(&tp->lock);
6418 spin_lock(&tp->tx_lock);
6419
6420#define __GET_REG32(reg) (*(p)++ = tr32(reg))
6421#define GET_REG32_LOOP(base,len) \
6422do { p = (u32 *)(orig_p + (base)); \
6423 for (i = 0; i < len; i += 4) \
6424 __GET_REG32((base) + i); \
6425} while (0)
6426#define GET_REG32_1(reg) \
6427do { p = (u32 *)(orig_p + (reg)); \
6428 __GET_REG32((reg)); \
6429} while (0)
6430
6431 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6432 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6433 GET_REG32_LOOP(MAC_MODE, 0x4f0);
6434 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6435 GET_REG32_1(SNDDATAC_MODE);
6436 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6437 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6438 GET_REG32_1(SNDBDC_MODE);
6439 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6440 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6441 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6442 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6443 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6444 GET_REG32_1(RCVDCC_MODE);
6445 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6446 GET_REG32_LOOP(RCVCC_MODE, 0x14);
6447 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6448 GET_REG32_1(MBFREE_MODE);
6449 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6450 GET_REG32_LOOP(MEMARB_MODE, 0x10);
6451 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6452 GET_REG32_LOOP(RDMAC_MODE, 0x08);
6453 GET_REG32_LOOP(WDMAC_MODE, 0x08);
6454 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6455 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6456 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6457 GET_REG32_LOOP(FTQ_RESET, 0x120);
6458 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6459 GET_REG32_1(DMAC_MODE);
6460 GET_REG32_LOOP(GRC_MODE, 0x4c);
6461 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6462 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6463
6464#undef __GET_REG32
6465#undef GET_REG32_LOOP
6466#undef GET_REG32_1
6467
6468 spin_unlock(&tp->tx_lock);
6469 spin_unlock_irq(&tp->lock);
6470}
6471
6472static int tg3_get_eeprom_len(struct net_device *dev)
6473{
6474 struct tg3 *tp = netdev_priv(dev);
6475
6476 return tp->nvram_size;
6477}
6478
6479static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6480
6481static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6482{
6483 struct tg3 *tp = netdev_priv(dev);
6484 int ret;
6485 u8 *pd;
6486 u32 i, offset, len, val, b_offset, b_count;
6487
6488 offset = eeprom->offset;
6489 len = eeprom->len;
6490 eeprom->len = 0;
6491
6492 eeprom->magic = TG3_EEPROM_MAGIC;
6493
6494 if (offset & 3) {
6495 /* adjustments to start on required 4 byte boundary */
6496 b_offset = offset & 3;
6497 b_count = 4 - b_offset;
6498 if (b_count > len) {
6499 /* i.e. offset=1 len=2 */
6500 b_count = len;
6501 }
6502 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6503 if (ret)
6504 return ret;
6505 val = cpu_to_le32(val);
6506 memcpy(data, ((char*)&val) + b_offset, b_count);
6507 len -= b_count;
6508 offset += b_count;
6509 eeprom->len += b_count;
6510 }
6511
6512 /* read bytes upto the last 4 byte boundary */
6513 pd = &data[eeprom->len];
6514 for (i = 0; i < (len - (len & 3)); i += 4) {
6515 ret = tg3_nvram_read(tp, offset + i, &val);
6516 if (ret) {
6517 eeprom->len += i;
6518 return ret;
6519 }
6520 val = cpu_to_le32(val);
6521 memcpy(pd + i, &val, 4);
6522 }
6523 eeprom->len += i;
6524
6525 if (len & 3) {
6526 /* read last bytes not ending on 4 byte boundary */
6527 pd = &data[eeprom->len];
6528 b_count = len & 3;
6529 b_offset = offset + len - b_count;
6530 ret = tg3_nvram_read(tp, b_offset, &val);
6531 if (ret)
6532 return ret;
6533 val = cpu_to_le32(val);
6534 memcpy(pd, ((char*)&val), b_count);
6535 eeprom->len += b_count;
6536 }
6537 return 0;
6538}
6539
6540static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6541
6542static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6543{
6544 struct tg3 *tp = netdev_priv(dev);
6545 int ret;
6546 u32 offset, len, b_offset, odd_len, start, end;
6547 u8 *buf;
6548
6549 if (eeprom->magic != TG3_EEPROM_MAGIC)
6550 return -EINVAL;
6551
6552 offset = eeprom->offset;
6553 len = eeprom->len;
6554
6555 if ((b_offset = (offset & 3))) {
6556 /* adjustments to start on required 4 byte boundary */
6557 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6558 if (ret)
6559 return ret;
6560 start = cpu_to_le32(start);
6561 len += b_offset;
6562 offset &= ~3;
6563 }
6564
6565 odd_len = 0;
6566 if ((len & 3) && ((len > 4) || (b_offset == 0))) {
6567 /* adjustments to end on required 4 byte boundary */
6568 odd_len = 1;
6569 len = (len + 3) & ~3;
6570 ret = tg3_nvram_read(tp, offset+len-4, &end);
6571 if (ret)
6572 return ret;
6573 end = cpu_to_le32(end);
6574 }
6575
6576 buf = data;
6577 if (b_offset || odd_len) {
6578 buf = kmalloc(len, GFP_KERNEL);
6579 if (buf == 0)
6580 return -ENOMEM;
6581 if (b_offset)
6582 memcpy(buf, &start, 4);
6583 if (odd_len)
6584 memcpy(buf+len-4, &end, 4);
6585 memcpy(buf + b_offset, data, eeprom->len);
6586 }
6587
6588 ret = tg3_nvram_write_block(tp, offset, len, buf);
6589
6590 if (buf != data)
6591 kfree(buf);
6592
6593 return ret;
6594}
6595
6596static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6597{
6598 struct tg3 *tp = netdev_priv(dev);
6599
6600 cmd->supported = (SUPPORTED_Autoneg);
6601
6602 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6603 cmd->supported |= (SUPPORTED_1000baseT_Half |
6604 SUPPORTED_1000baseT_Full);
6605
6606 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6607 cmd->supported |= (SUPPORTED_100baseT_Half |
6608 SUPPORTED_100baseT_Full |
6609 SUPPORTED_10baseT_Half |
6610 SUPPORTED_10baseT_Full |
6611 SUPPORTED_MII);
6612 else
6613 cmd->supported |= SUPPORTED_FIBRE;
6614
6615 cmd->advertising = tp->link_config.advertising;
6616 if (netif_running(dev)) {
6617 cmd->speed = tp->link_config.active_speed;
6618 cmd->duplex = tp->link_config.active_duplex;
6619 }
6620 cmd->port = 0;
6621 cmd->phy_address = PHY_ADDR;
6622 cmd->transceiver = 0;
6623 cmd->autoneg = tp->link_config.autoneg;
6624 cmd->maxtxpkt = 0;
6625 cmd->maxrxpkt = 0;
6626 return 0;
6627}
6628
6629static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6630{
6631 struct tg3 *tp = netdev_priv(dev);
6632
6633 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6634 /* These are the only valid advertisement bits allowed. */
6635 if (cmd->autoneg == AUTONEG_ENABLE &&
6636 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6637 ADVERTISED_1000baseT_Full |
6638 ADVERTISED_Autoneg |
6639 ADVERTISED_FIBRE)))
6640 return -EINVAL;
6641 }
6642
6643 spin_lock_irq(&tp->lock);
6644 spin_lock(&tp->tx_lock);
6645
6646 tp->link_config.autoneg = cmd->autoneg;
6647 if (cmd->autoneg == AUTONEG_ENABLE) {
6648 tp->link_config.advertising = cmd->advertising;
6649 tp->link_config.speed = SPEED_INVALID;
6650 tp->link_config.duplex = DUPLEX_INVALID;
6651 } else {
6652 tp->link_config.advertising = 0;
6653 tp->link_config.speed = cmd->speed;
6654 tp->link_config.duplex = cmd->duplex;
6655 }
6656
6657 if (netif_running(dev))
6658 tg3_setup_phy(tp, 1);
6659
6660 spin_unlock(&tp->tx_lock);
6661 spin_unlock_irq(&tp->lock);
6662
6663 return 0;
6664}
6665
6666static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6667{
6668 struct tg3 *tp = netdev_priv(dev);
6669
6670 strcpy(info->driver, DRV_MODULE_NAME);
6671 strcpy(info->version, DRV_MODULE_VERSION);
6672 strcpy(info->bus_info, pci_name(tp->pdev));
6673}
6674
6675static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6676{
6677 struct tg3 *tp = netdev_priv(dev);
6678
6679 wol->supported = WAKE_MAGIC;
6680 wol->wolopts = 0;
6681 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6682 wol->wolopts = WAKE_MAGIC;
6683 memset(&wol->sopass, 0, sizeof(wol->sopass));
6684}
6685
6686static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6687{
6688 struct tg3 *tp = netdev_priv(dev);
6689
6690 if (wol->wolopts & ~WAKE_MAGIC)
6691 return -EINVAL;
6692 if ((wol->wolopts & WAKE_MAGIC) &&
6693 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
6694 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
6695 return -EINVAL;
6696
6697 spin_lock_irq(&tp->lock);
6698 if (wol->wolopts & WAKE_MAGIC)
6699 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6700 else
6701 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
6702 spin_unlock_irq(&tp->lock);
6703
6704 return 0;
6705}
6706
6707static u32 tg3_get_msglevel(struct net_device *dev)
6708{
6709 struct tg3 *tp = netdev_priv(dev);
6710 return tp->msg_enable;
6711}
6712
6713static void tg3_set_msglevel(struct net_device *dev, u32 value)
6714{
6715 struct tg3 *tp = netdev_priv(dev);
6716 tp->msg_enable = value;
6717}
6718
6719#if TG3_TSO_SUPPORT != 0
6720static int tg3_set_tso(struct net_device *dev, u32 value)
6721{
6722 struct tg3 *tp = netdev_priv(dev);
6723
6724 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6725 if (value)
6726 return -EINVAL;
6727 return 0;
6728 }
6729 return ethtool_op_set_tso(dev, value);
6730}
6731#endif
6732
6733static int tg3_nway_reset(struct net_device *dev)
6734{
6735 struct tg3 *tp = netdev_priv(dev);
6736 u32 bmcr;
6737 int r;
6738
6739 if (!netif_running(dev))
6740 return -EAGAIN;
6741
6742 spin_lock_irq(&tp->lock);
6743 r = -EINVAL;
6744 tg3_readphy(tp, MII_BMCR, &bmcr);
6745 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
6746 (bmcr & BMCR_ANENABLE)) {
6747 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
6748 r = 0;
6749 }
6750 spin_unlock_irq(&tp->lock);
6751
6752 return r;
6753}
6754
6755static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6756{
6757 struct tg3 *tp = netdev_priv(dev);
6758
6759 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
6760 ering->rx_mini_max_pending = 0;
6761 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
6762
6763 ering->rx_pending = tp->rx_pending;
6764 ering->rx_mini_pending = 0;
6765 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
6766 ering->tx_pending = tp->tx_pending;
6767}
6768
6769static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6770{
6771 struct tg3 *tp = netdev_priv(dev);
6772
6773 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
6774 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
6775 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
6776 return -EINVAL;
6777
6778 if (netif_running(dev))
6779 tg3_netif_stop(tp);
6780
6781 spin_lock_irq(&tp->lock);
6782 spin_lock(&tp->tx_lock);
6783
6784 tp->rx_pending = ering->rx_pending;
6785
6786 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
6787 tp->rx_pending > 63)
6788 tp->rx_pending = 63;
6789 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
6790 tp->tx_pending = ering->tx_pending;
6791
6792 if (netif_running(dev)) {
6793 tg3_halt(tp);
6794 tg3_init_hw(tp);
6795 tg3_netif_start(tp);
6796 }
6797
6798 spin_unlock(&tp->tx_lock);
6799 spin_unlock_irq(&tp->lock);
6800
6801 return 0;
6802}
6803
6804static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6805{
6806 struct tg3 *tp = netdev_priv(dev);
6807
6808 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
6809 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
6810 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
6811}
6812
6813static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6814{
6815 struct tg3 *tp = netdev_priv(dev);
6816
6817 if (netif_running(dev))
6818 tg3_netif_stop(tp);
6819
6820 spin_lock_irq(&tp->lock);
6821 spin_lock(&tp->tx_lock);
6822 if (epause->autoneg)
6823 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
6824 else
6825 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
6826 if (epause->rx_pause)
6827 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
6828 else
6829 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
6830 if (epause->tx_pause)
6831 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
6832 else
6833 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
6834
6835 if (netif_running(dev)) {
6836 tg3_halt(tp);
6837 tg3_init_hw(tp);
6838 tg3_netif_start(tp);
6839 }
6840 spin_unlock(&tp->tx_lock);
6841 spin_unlock_irq(&tp->lock);
6842
6843 return 0;
6844}
6845
6846static u32 tg3_get_rx_csum(struct net_device *dev)
6847{
6848 struct tg3 *tp = netdev_priv(dev);
6849 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
6850}
6851
6852static int tg3_set_rx_csum(struct net_device *dev, u32 data)
6853{
6854 struct tg3 *tp = netdev_priv(dev);
6855
6856 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
6857 if (data != 0)
6858 return -EINVAL;
6859 return 0;
6860 }
6861
6862 spin_lock_irq(&tp->lock);
6863 if (data)
6864 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
6865 else
6866 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
6867 spin_unlock_irq(&tp->lock);
6868
6869 return 0;
6870}
6871
6872static int tg3_set_tx_csum(struct net_device *dev, u32 data)
6873{
6874 struct tg3 *tp = netdev_priv(dev);
6875
6876 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
6877 if (data != 0)
6878 return -EINVAL;
6879 return 0;
6880 }
6881
6882 if (data)
6883 dev->features |= NETIF_F_IP_CSUM;
6884 else
6885 dev->features &= ~NETIF_F_IP_CSUM;
6886
6887 return 0;
6888}
6889
6890static int tg3_get_stats_count (struct net_device *dev)
6891{
6892 return TG3_NUM_STATS;
6893}
6894
6895static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
6896{
6897 switch (stringset) {
6898 case ETH_SS_STATS:
6899 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
6900 break;
6901 default:
6902 WARN_ON(1); /* we need a WARN() */
6903 break;
6904 }
6905}
6906
6907static void tg3_get_ethtool_stats (struct net_device *dev,
6908 struct ethtool_stats *estats, u64 *tmp_stats)
6909{
6910 struct tg3 *tp = netdev_priv(dev);
6911 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
6912}
6913
6914static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6915{
6916 struct mii_ioctl_data *data = if_mii(ifr);
6917 struct tg3 *tp = netdev_priv(dev);
6918 int err;
6919
6920 switch(cmd) {
6921 case SIOCGMIIPHY:
6922 data->phy_id = PHY_ADDR;
6923
6924 /* fallthru */
6925 case SIOCGMIIREG: {
6926 u32 mii_regval;
6927
6928 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
6929 break; /* We have no PHY */
6930
6931 spin_lock_irq(&tp->lock);
6932 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
6933 spin_unlock_irq(&tp->lock);
6934
6935 data->val_out = mii_regval;
6936
6937 return err;
6938 }
6939
6940 case SIOCSMIIREG:
6941 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
6942 break; /* We have no PHY */
6943
6944 if (!capable(CAP_NET_ADMIN))
6945 return -EPERM;
6946
6947 spin_lock_irq(&tp->lock);
6948 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
6949 spin_unlock_irq(&tp->lock);
6950
6951 return err;
6952
6953 default:
6954 /* do nothing */
6955 break;
6956 }
6957 return -EOPNOTSUPP;
6958}
6959
6960#if TG3_VLAN_TAG_USED
6961static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
6962{
6963 struct tg3 *tp = netdev_priv(dev);
6964
6965 spin_lock_irq(&tp->lock);
6966 spin_lock(&tp->tx_lock);
6967
6968 tp->vlgrp = grp;
6969
6970 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
6971 __tg3_set_rx_mode(dev);
6972
6973 spin_unlock(&tp->tx_lock);
6974 spin_unlock_irq(&tp->lock);
6975}
6976
6977static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
6978{
6979 struct tg3 *tp = netdev_priv(dev);
6980
6981 spin_lock_irq(&tp->lock);
6982 spin_lock(&tp->tx_lock);
6983 if (tp->vlgrp)
6984 tp->vlgrp->vlan_devices[vid] = NULL;
6985 spin_unlock(&tp->tx_lock);
6986 spin_unlock_irq(&tp->lock);
6987}
6988#endif
6989
6990static struct ethtool_ops tg3_ethtool_ops = {
6991 .get_settings = tg3_get_settings,
6992 .set_settings = tg3_set_settings,
6993 .get_drvinfo = tg3_get_drvinfo,
6994 .get_regs_len = tg3_get_regs_len,
6995 .get_regs = tg3_get_regs,
6996 .get_wol = tg3_get_wol,
6997 .set_wol = tg3_set_wol,
6998 .get_msglevel = tg3_get_msglevel,
6999 .set_msglevel = tg3_set_msglevel,
7000 .nway_reset = tg3_nway_reset,
7001 .get_link = ethtool_op_get_link,
7002 .get_eeprom_len = tg3_get_eeprom_len,
7003 .get_eeprom = tg3_get_eeprom,
7004 .set_eeprom = tg3_set_eeprom,
7005 .get_ringparam = tg3_get_ringparam,
7006 .set_ringparam = tg3_set_ringparam,
7007 .get_pauseparam = tg3_get_pauseparam,
7008 .set_pauseparam = tg3_set_pauseparam,
7009 .get_rx_csum = tg3_get_rx_csum,
7010 .set_rx_csum = tg3_set_rx_csum,
7011 .get_tx_csum = ethtool_op_get_tx_csum,
7012 .set_tx_csum = tg3_set_tx_csum,
7013 .get_sg = ethtool_op_get_sg,
7014 .set_sg = ethtool_op_set_sg,
7015#if TG3_TSO_SUPPORT != 0
7016 .get_tso = ethtool_op_get_tso,
7017 .set_tso = tg3_set_tso,
7018#endif
7019 .get_strings = tg3_get_strings,
7020 .get_stats_count = tg3_get_stats_count,
7021 .get_ethtool_stats = tg3_get_ethtool_stats,
7022};
7023
7024static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7025{
7026 u32 cursize, val;
7027
7028 tp->nvram_size = EEPROM_CHIP_SIZE;
7029
7030 if (tg3_nvram_read(tp, 0, &val) != 0)
7031 return;
7032
7033 if (swab32(val) != TG3_EEPROM_MAGIC)
7034 return;
7035
7036 /*
7037 * Size the chip by reading offsets at increasing powers of two.
7038 * When we encounter our validation signature, we know the addressing
7039 * has wrapped around, and thus have our chip size.
7040 */
7041 cursize = 0x800;
7042
7043 while (cursize < tp->nvram_size) {
7044 if (tg3_nvram_read(tp, cursize, &val) != 0)
7045 return;
7046
7047 if (swab32(val) == TG3_EEPROM_MAGIC)
7048 break;
7049
7050 cursize <<= 1;
7051 }
7052
7053 tp->nvram_size = cursize;
7054}
7055
7056static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7057{
7058 u32 val;
7059
7060 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7061 if (val != 0) {
7062 tp->nvram_size = (val >> 16) * 1024;
7063 return;
7064 }
7065 }
7066 tp->nvram_size = 0x20000;
7067}
7068
7069static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7070{
7071 u32 nvcfg1;
7072
7073 nvcfg1 = tr32(NVRAM_CFG1);
7074 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7075 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7076 }
7077 else {
7078 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7079 tw32(NVRAM_CFG1, nvcfg1);
7080 }
7081
85e94ced 7082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7083 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7084 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7085 tp->nvram_jedecnum = JEDEC_ATMEL;
7086 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7087 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7088 break;
7089 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7090 tp->nvram_jedecnum = JEDEC_ATMEL;
7091 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7092 break;
7093 case FLASH_VENDOR_ATMEL_EEPROM:
7094 tp->nvram_jedecnum = JEDEC_ATMEL;
7095 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7096 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7097 break;
7098 case FLASH_VENDOR_ST:
7099 tp->nvram_jedecnum = JEDEC_ST;
7100 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7101 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7102 break;
7103 case FLASH_VENDOR_SAIFUN:
7104 tp->nvram_jedecnum = JEDEC_SAIFUN;
7105 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7106 break;
7107 case FLASH_VENDOR_SST_SMALL:
7108 case FLASH_VENDOR_SST_LARGE:
7109 tp->nvram_jedecnum = JEDEC_SST;
7110 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7111 break;
7112 }
7113 }
7114 else {
7115 tp->nvram_jedecnum = JEDEC_ATMEL;
7116 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7117 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7118 }
7119}
7120
361b4ac2
MC		 7121static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7122{
7123 u32 nvcfg1;
7124
7125 nvcfg1 = tr32(NVRAM_CFG1);
7126
e6af301b
MC		 7127 /* NVRAM protection for TPM */
7128 if (nvcfg1 & (1 << 27))
7129 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7130
361b4ac2
MC		 7131 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7132 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7133 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7134 tp->nvram_jedecnum = JEDEC_ATMEL;
7135 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7136 break;
7137 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7138 tp->nvram_jedecnum = JEDEC_ATMEL;
7139 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7140 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7141 break;
7142 case FLASH_5752VENDOR_ST_M45PE10:
7143 case FLASH_5752VENDOR_ST_M45PE20:
7144 case FLASH_5752VENDOR_ST_M45PE40:
7145 tp->nvram_jedecnum = JEDEC_ST;
7146 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7147 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7148 break;
7149 }
7150
7151 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
7152 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
7153 case FLASH_5752PAGE_SIZE_256:
7154 tp->nvram_pagesize = 256;
7155 break;
7156 case FLASH_5752PAGE_SIZE_512:
7157 tp->nvram_pagesize = 512;
7158 break;
7159 case FLASH_5752PAGE_SIZE_1K:
7160 tp->nvram_pagesize = 1024;
7161 break;
7162 case FLASH_5752PAGE_SIZE_2K:
7163 tp->nvram_pagesize = 2048;
7164 break;
7165 case FLASH_5752PAGE_SIZE_4K:
7166 tp->nvram_pagesize = 4096;
7167 break;
7168 case FLASH_5752PAGE_SIZE_264:
7169 tp->nvram_pagesize = 264;
7170 break;
7171 }
7172 }
7173 else {
7174 /* For eeprom, set pagesize to maximum eeprom size */
7175 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7176
7177 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7178 tw32(NVRAM_CFG1, nvcfg1);
7179 }
7180}
7181
1da177e4
LT		 7182/* Chips other than 5700/5701 use the NVRAM for fetching info. */
7183static void __devinit tg3_nvram_init(struct tg3 *tp)
7184{
7185 int j;
7186
7187 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
7188 return;
7189
7190 tw32_f(GRC_EEPROM_ADDR,
7191 (EEPROM_ADDR_FSM_RESET |
7192 (EEPROM_DEFAULT_CLOCK_PERIOD <<
7193 EEPROM_ADDR_CLKPERD_SHIFT)));
7194
7195 /* XXX schedule_timeout() ... */
7196 for (j = 0; j < 100; j++)
7197 udelay(10);
7198
7199 /* Enable seeprom accesses. */
7200 tw32_f(GRC_LOCAL_CTRL,
7201 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
7202 udelay(100);
7203
7204 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
7205 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7206 tp->tg3_flags |= TG3_FLAG_NVRAM;
7207
e6af301b 7208 tg3_enable_nvram_access(tp);
1da177e4 7209
361b4ac2
MC		 7210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7211 tg3_get_5752_nvram_info(tp);
7212 else
7213 tg3_get_nvram_info(tp);
7214
1da177e4
LT		 7215 tg3_get_nvram_size(tp);
7216
e6af301b 7217 tg3_disable_nvram_access(tp);
1da177e4
LT		 7218
7219 } else {
7220 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
7221
7222 tg3_get_eeprom_size(tp);
7223 }
7224}
7225
7226static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
7227 u32 offset, u32 *val)
7228{
7229 u32 tmp;
7230 int i;
7231
7232 if (offset > EEPROM_ADDR_ADDR_MASK ||
7233 (offset % 4) != 0)
7234 return -EINVAL;
7235
7236 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
7237 EEPROM_ADDR_DEVID_MASK |
7238 EEPROM_ADDR_READ);
7239 tw32(GRC_EEPROM_ADDR,
7240 tmp |
7241 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7242 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
7243 EEPROM_ADDR_ADDR_MASK) |
7244 EEPROM_ADDR_READ | EEPROM_ADDR_START);
7245
7246 for (i = 0; i < 10000; i++) {
7247 tmp = tr32(GRC_EEPROM_ADDR);
7248
7249 if (tmp & EEPROM_ADDR_COMPLETE)
7250 break;
7251 udelay(100);
7252 }
7253 if (!(tmp & EEPROM_ADDR_COMPLETE))
7254 return -EBUSY;
7255
7256 *val = tr32(GRC_EEPROM_DATA);
7257 return 0;
7258}
7259
7260#define NVRAM_CMD_TIMEOUT 10000
7261
7262static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
7263{
7264 int i;
7265
7266 tw32(NVRAM_CMD, nvram_cmd);
7267 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
7268 udelay(10);
7269 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
7270 udelay(10);
7271 break;
7272 }
7273 }
7274 if (i == NVRAM_CMD_TIMEOUT) {
7275 return -EBUSY;
7276 }
7277 return 0;
7278}
7279
7280static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7281{
7282 int ret;
7283
7284 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7285 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
7286 return -EINVAL;
7287 }
7288
7289 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
7290 return tg3_nvram_read_using_eeprom(tp, offset, val);
7291
7292 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
7293 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7294 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7295
7296 offset = ((offset / tp->nvram_pagesize) <<
7297 ATMEL_AT45DB0X1B_PAGE_POS) +
7298 (offset % tp->nvram_pagesize);
7299 }
7300
7301 if (offset > NVRAM_ADDR_MSK)
7302 return -EINVAL;
7303
7304 tg3_nvram_lock(tp);
7305
e6af301b 7306 tg3_enable_nvram_access(tp);
1da177e4
LT		 7307
7308 tw32(NVRAM_ADDR, offset);
7309 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
7310 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
7311
7312 if (ret == 0)
7313 *val = swab32(tr32(NVRAM_RDDATA));
7314
7315 tg3_nvram_unlock(tp);
7316
e6af301b 7317 tg3_disable_nvram_access(tp);
1da177e4
LT		 7318
7319 return ret;
7320}
7321
7322static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
7323 u32 offset, u32 len, u8 *buf)
7324{
7325 int i, j, rc = 0;
7326 u32 val;
7327
7328 for (i = 0; i < len; i += 4) {
7329 u32 addr, data;
7330
7331 addr = offset + i;
7332
7333 memcpy(&data, buf + i, 4);
7334
7335 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
7336
7337 val = tr32(GRC_EEPROM_ADDR);
7338 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
7339
7340 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
7341 EEPROM_ADDR_READ);
7342 tw32(GRC_EEPROM_ADDR, val |
7343 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7344 (addr & EEPROM_ADDR_ADDR_MASK) |
7345 EEPROM_ADDR_START |
7346 EEPROM_ADDR_WRITE);
7347
7348 for (j = 0; j < 10000; j++) {
7349 val = tr32(GRC_EEPROM_ADDR);
7350
7351 if (val & EEPROM_ADDR_COMPLETE)
7352 break;
7353 udelay(100);
7354 }
7355 if (!(val & EEPROM_ADDR_COMPLETE)) {
7356 rc = -EBUSY;
7357 break;
7358 }
7359 }
7360
7361 return rc;
7362}
7363
7364/* offset and length are dword aligned */
7365static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
7366 u8 *buf)
7367{
7368 int ret = 0;
7369 u32 pagesize = tp->nvram_pagesize;
7370 u32 pagemask = pagesize - 1;
7371 u32 nvram_cmd;
7372 u8 *tmp;
7373
7374 tmp = kmalloc(pagesize, GFP_KERNEL);
7375 if (tmp == NULL)
7376 return -ENOMEM;
7377
7378 while (len) {
7379 int j;
e6af301b 7380 u32 phy_addr, page_off, size;
1da177e4
LT		 7381
7382 phy_addr = offset & ~pagemask;
7383
7384 for (j = 0; j < pagesize; j += 4) {
7385 if ((ret = tg3_nvram_read(tp, phy_addr + j,
7386 (u32 *) (tmp + j))))
7387 break;
7388 }
7389 if (ret)
7390 break;
7391
7392 page_off = offset & pagemask;
7393 size = pagesize;
7394 if (len < size)
7395 size = len;
7396
7397 len -= size;
7398
7399 memcpy(tmp + page_off, buf, size);
7400
7401 offset = offset + (pagesize - page_off);
7402
e6af301b 7403 tg3_enable_nvram_access(tp);
1da177e4
LT		 7404
7405 /*
7406 * Before we can erase the flash page, we need
7407 * to issue a special "write enable" command.
7408 */
7409 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7410
7411 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7412 break;
7413
7414 /* Erase the target page */
7415 tw32(NVRAM_ADDR, phy_addr);
7416
7417 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
7418 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
7419
7420 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7421 break;
7422
7423 /* Issue another write enable to start the write. */
7424 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7425
7426 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7427 break;
7428
7429 for (j = 0; j < pagesize; j += 4) {
7430 u32 data;
7431
7432 data = *((u32 *) (tmp + j));
7433 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7434
7435 tw32(NVRAM_ADDR, phy_addr + j);
7436
7437 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
7438 NVRAM_CMD_WR;
7439
7440 if (j == 0)
7441 nvram_cmd |= NVRAM_CMD_FIRST;
7442 else if (j == (pagesize - 4))
7443 nvram_cmd |= NVRAM_CMD_LAST;
7444
7445 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7446 break;
7447 }
7448 if (ret)
7449 break;
7450 }
7451
7452 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7453 tg3_nvram_exec_cmd(tp, nvram_cmd);
7454
7455 kfree(tmp);
7456
7457 return ret;
7458}
7459
7460/* offset and length are dword aligned */
7461static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
7462 u8 *buf)
7463{
7464 int i, ret = 0;
7465
7466 for (i = 0; i < len; i += 4, offset += 4) {
7467 u32 data, page_off, phy_addr, nvram_cmd;
7468
7469 memcpy(&data, buf + i, 4);
7470 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7471
7472 page_off = offset % tp->nvram_pagesize;
7473
7474 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7475 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7476
7477 phy_addr = ((offset / tp->nvram_pagesize) <<
7478 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
7479 }
7480 else {
7481 phy_addr = offset;
7482 }
7483
7484 tw32(NVRAM_ADDR, phy_addr);
7485
7486 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
7487
7488 if ((page_off == 0) || (i == 0))
7489 nvram_cmd |= NVRAM_CMD_FIRST;
7490 else if (page_off == (tp->nvram_pagesize - 4))
7491 nvram_cmd |= NVRAM_CMD_LAST;
7492
7493 if (i == (len - 4))
7494 nvram_cmd |= NVRAM_CMD_LAST;
7495
7496 if ((tp->nvram_jedecnum == JEDEC_ST) &&
7497 (nvram_cmd & NVRAM_CMD_FIRST)) {
7498
7499 if ((ret = tg3_nvram_exec_cmd(tp,
7500 NVRAM_CMD_WREN | NVRAM_CMD_GO |
7501 NVRAM_CMD_DONE)))
7502
7503 break;
7504 }
7505 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7506 /* We always do complete word writes to eeprom. */
7507 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
7508 }
7509
7510 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7511 break;
7512 }
7513 return ret;
7514}
7515
7516/* offset and length are dword aligned */
7517static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7518{
7519 int ret;
7520
7521 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7522 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
7523 return -EINVAL;
7524 }
7525
7526 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 7527 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
7528 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 7529 udelay(40);
7530 }
7531
7532 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
7533 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
7534 }
7535 else {
7536 u32 grc_mode;
7537
7538 tg3_nvram_lock(tp);
7539
e6af301b
MC		 7540 tg3_enable_nvram_access(tp);
7541 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7542 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 7543 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 7544
7545 grc_mode = tr32(GRC_MODE);
7546 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
7547
7548 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
7549 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7550
7551 ret = tg3_nvram_write_block_buffered(tp, offset, len,
7552 buf);
7553 }
7554 else {
7555 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
7556 buf);
7557 }
7558
7559 grc_mode = tr32(GRC_MODE);
7560 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7561
e6af301b 7562 tg3_disable_nvram_access(tp);
1da177e4
LT		 7563 tg3_nvram_unlock(tp);
7564 }
7565
7566 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 7567 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 7568 udelay(40);
7569 }
7570
7571 return ret;
7572}
7573
7574struct subsys_tbl_ent {
7575 u16 subsys_vendor, subsys_devid;
7576 u32 phy_id;
7577};
7578
7579static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
7580 /* Broadcom boards. */
7581 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
7582 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
7583 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
7584 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
7585 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
7586 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
7587 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
7588 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
7589 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
7590 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
7591 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
7592
7593 /* 3com boards. */
7594 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
7595 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
7596 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
7597 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
7598 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
7599
7600 /* DELL boards. */
7601 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
7602 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
7603 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
7604 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
7605
7606 /* Compaq boards. */
7607 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
7608 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
7609 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
7610 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
7611 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
7612
7613 /* IBM boards. */
7614 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
7615};
7616
7617static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
7618{
7619 int i;
7620
7621 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
7622 if ((subsys_id_to_phy_id[i].subsys_vendor ==
7623 tp->pdev->subsystem_vendor) &&
7624 (subsys_id_to_phy_id[i].subsys_devid ==
7625 tp->pdev->subsystem_device))
7626 return &subsys_id_to_phy_id[i];
7627 }
7628 return NULL;
7629}
7630
7d0c41ef
MC		 7631/* Since this function may be called in D3-hot power state during
7632 * tg3_init_one(), only config cycles are allowed.
7633 */
7634static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 7635{
1da177e4 7636 u32 val;
7d0c41ef
MC		 7637
7638 /* Make sure register accesses (indirect or otherwise)
7639 * will function correctly.
7640 */
7641 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7642 tp->misc_host_ctrl);
1da177e4
LT		 7643
7644 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 7645 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7646
1da177e4
LT		 7647 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7648 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7649 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 7650 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
7651 int eeprom_phy_serdes = 0;
1da177e4
LT		 7652
7653 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7654 tp->nic_sram_data_cfg = nic_cfg;
7655
7656 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
7657 ver >>= NIC_SRAM_DATA_VER_SHIFT;
7658 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7659 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7660 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
7661 (ver > 0) && (ver < 0x100))
7662 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
7663
1da177e4
LT		 7664 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
7665 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
7666 eeprom_phy_serdes = 1;
7667
7668 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
7669 if (nic_phy_id != 0) {
7670 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
7671 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
7672
7673 eeprom_phy_id = (id1 >> 16) << 10;
7674 eeprom_phy_id |= (id2 & 0xfc00) << 16;
7675 eeprom_phy_id |= (id2 & 0x03ff) << 0;
7676 } else
7677 eeprom_phy_id = 0;
7678
7d0c41ef
MC		 7679 tp->phy_id = eeprom_phy_id;
7680 if (eeprom_phy_serdes)
7681 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7682
cbf46853 7683 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7684 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7685 SHASTA_EXT_LED_MODE_MASK);
cbf46853 7686 else
1da177e4
LT		 7687 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
7688
7689 switch (led_cfg) {
7690 default:
7691 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
7692 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7693 break;
7694
7695 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
7696 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7697 break;
7698
7699 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
7700 tp->led_ctrl = LED_CTRL_MODE_MAC;
7701 break;
7702
7703 case SHASTA_EXT_LED_SHARED:
7704 tp->led_ctrl = LED_CTRL_MODE_SHARED;
7705 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7706 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
7707 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7708 LED_CTRL_MODE_PHY_2);
7709 break;
7710
7711 case SHASTA_EXT_LED_MAC:
7712 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
7713 break;
7714
7715 case SHASTA_EXT_LED_COMBO:
7716 tp->led_ctrl = LED_CTRL_MODE_COMBO;
7717 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
7718 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7719 LED_CTRL_MODE_PHY_2);
7720 break;
7721
7722 };
7723
7724 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7725 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
7726 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
7727 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7728
7729 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7730 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7731 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
7732 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
7733
7734 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7735 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 7736 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7737 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7738 }
7739 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
7740 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
7741
7742 if (cfg2 & (1 << 17))
7743 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
7744
7745 /* serdes signal pre-emphasis in register 0x590 set by */
7746 /* bootcode if bit 18 is set */
7747 if (cfg2 & (1 << 18))
7748 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
7749 }
7d0c41ef
MC		 7750}
7751
7752static int __devinit tg3_phy_probe(struct tg3 *tp)
7753{
7754 u32 hw_phy_id_1, hw_phy_id_2;
7755 u32 hw_phy_id, hw_phy_id_masked;
7756 int err;
1da177e4
LT		 7757
7758 /* Reading the PHY ID register can conflict with ASF
7759 * firwmare access to the PHY hardware.
7760 */
7761 err = 0;
7762 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7763 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
7764 } else {
7765 /* Now read the physical PHY_ID from the chip and verify
7766 * that it is sane. If it doesn't look good, we fall back
7767 * to either the hard-coded table based PHY_ID and failing
7768 * that the value found in the eeprom area.
7769 */
7770 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
7771 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
7772
7773 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
7774 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
7775 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
7776
7777 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
7778 }
7779
7780 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
7781 tp->phy_id = hw_phy_id;
7782 if (hw_phy_id_masked == PHY_ID_BCM8002)
7783 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7784 } else {
7d0c41ef
MC		 7785 if (tp->phy_id != PHY_ID_INVALID) {
7786 /* Do nothing, phy ID already set up in
7787 * tg3_get_eeprom_hw_cfg().
7788 */
1da177e4
LT		 7789 } else {
7790 struct subsys_tbl_ent *p;
7791
7792 /* No eeprom signature? Try the hardcoded
7793 * subsys device table.
7794 */
7795 p = lookup_by_subsys(tp);
7796 if (!p)
7797 return -ENODEV;
7798
7799 tp->phy_id = p->phy_id;
7800 if (!tp->phy_id ||
7801 tp->phy_id == PHY_ID_BCM8002)
7802 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7803 }
7804 }
7805
7806 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7807 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
7808 u32 bmsr, adv_reg, tg3_ctrl;
7809
7810 tg3_readphy(tp, MII_BMSR, &bmsr);
7811 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
7812 (bmsr & BMSR_LSTATUS))
7813 goto skip_phy_reset;
7814
7815 err = tg3_phy_reset(tp);
7816 if (err)
7817 return err;
7818
7819 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
7820 ADVERTISE_100HALF | ADVERTISE_100FULL |
7821 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
7822 tg3_ctrl = 0;
7823 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
7824 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
7825 MII_TG3_CTRL_ADV_1000_FULL);
7826 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
7827 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
7828 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
7829 MII_TG3_CTRL_ENABLE_AS_MASTER);
7830 }
7831
7832 if (!tg3_copper_is_advertising_all(tp)) {
7833 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
7834
7835 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7836 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
7837
7838 tg3_writephy(tp, MII_BMCR,
7839 BMCR_ANENABLE | BMCR_ANRESTART);
7840 }
7841 tg3_phy_set_wirespeed(tp);
7842
7843 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
7844 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7845 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
7846 }
7847
7848skip_phy_reset:
7849 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
7850 err = tg3_init_5401phy_dsp(tp);
7851 if (err)
7852 return err;
7853 }
7854
7855 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
7856 err = tg3_init_5401phy_dsp(tp);
7857 }
7858
1da177e4
LT		 7859 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7860 tp->link_config.advertising =
7861 (ADVERTISED_1000baseT_Half |
7862 ADVERTISED_1000baseT_Full |
7863 ADVERTISED_Autoneg |
7864 ADVERTISED_FIBRE);
7865 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
7866 tp->link_config.advertising &=
7867 ~(ADVERTISED_1000baseT_Half |
7868 ADVERTISED_1000baseT_Full);
7869
7870 return err;
7871}
7872
7873static void __devinit tg3_read_partno(struct tg3 *tp)
7874{
7875 unsigned char vpd_data[256];
7876 int i;
7877
7878 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7879 /* Sun decided not to put the necessary bits in the
7880 * NVRAM of their onboard tg3 parts :(
7881 */
7882 strcpy(tp->board_part_number, "Sun 570X");
7883 return;
7884 }
7885
7886 for (i = 0; i < 256; i += 4) {
7887 u32 tmp;
7888
7889 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
7890 goto out_not_found;
7891
7892 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
7893 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
7894 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
7895 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
7896 }
7897
7898 /* Now parse and find the part number. */
7899 for (i = 0; i < 256; ) {
7900 unsigned char val = vpd_data[i];
7901 int block_end;
7902
7903 if (val == 0x82 || val == 0x91) {
7904 i = (i + 3 +
7905 (vpd_data[i + 1] +
7906 (vpd_data[i + 2] << 8)));
7907 continue;
7908 }
7909
7910 if (val != 0x90)
7911 goto out_not_found;
7912
7913 block_end = (i + 3 +
7914 (vpd_data[i + 1] +
7915 (vpd_data[i + 2] << 8)));
7916 i += 3;
7917 while (i < block_end) {
7918 if (vpd_data[i + 0] == 'P' &&
7919 vpd_data[i + 1] == 'N') {
7920 int partno_len = vpd_data[i + 2];
7921
7922 if (partno_len > 24)
7923 goto out_not_found;
7924
7925 memcpy(tp->board_part_number,
7926 &vpd_data[i + 3],
7927 partno_len);
7928
7929 /* Success. */
7930 return;
7931 }
7932 }
7933
7934 /* Part number not found. */
7935 goto out_not_found;
7936 }
7937
7938out_not_found:
7939 strcpy(tp->board_part_number, "none");
7940}
7941
7942#ifdef CONFIG_SPARC64
7943static int __devinit tg3_is_sun_570X(struct tg3 *tp)
7944{
7945 struct pci_dev *pdev = tp->pdev;
7946 struct pcidev_cookie *pcp = pdev->sysdata;
7947
7948 if (pcp != NULL) {
7949 int node = pcp->prom_node;
7950 u32 venid;
7951 int err;
7952
7953 err = prom_getproperty(node, "subsystem-vendor-id",
7954 (char *) &venid, sizeof(venid));
7955 if (err == 0 || err == -1)
7956 return 0;
7957 if (venid == PCI_VENDOR_ID_SUN)
7958 return 1;
7959 }
7960 return 0;
7961}
7962#endif
7963
7964static int __devinit tg3_get_invariants(struct tg3 *tp)
7965{
7966 static struct pci_device_id write_reorder_chipsets[] = {
7967 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7968 PCI_DEVICE_ID_INTEL_82801AA_8) },
7969 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7970 PCI_DEVICE_ID_INTEL_82801AB_8) },
7971 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7972 PCI_DEVICE_ID_INTEL_82801BA_11) },
7973 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7974 PCI_DEVICE_ID_INTEL_82801BA_6) },
7975 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
7976 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
7977 { },
7978 };
7979 u32 misc_ctrl_reg;
7980 u32 cacheline_sz_reg;
7981 u32 pci_state_reg, grc_misc_cfg;
7982 u32 val;
7983 u16 pci_cmd;
7984 int err;
7985
7986#ifdef CONFIG_SPARC64
7987 if (tg3_is_sun_570X(tp))
7988 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
7989#endif
7990
7991 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
7992 * reordering to the mailbox registers done by the host
7993 * controller can cause major troubles. We read back from
7994 * every mailbox register write to force the writes to be
7995 * posted to the chip in order.
7996 */
7997 if (pci_dev_present(write_reorder_chipsets))
7998 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
7999
8000 /* Force memory write invalidate off. If we leave it on,
8001 * then on 5700_BX chips we have to enable a workaround.
8002 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8003 * to match the cacheline size. The Broadcom driver have this
8004 * workaround but turns MWI off all the times so never uses
8005 * it. This seems to suggest that the workaround is insufficient.
8006 */
8007 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8008 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8009 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8010
8011 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8012 * has the register indirect write enable bit set before
8013 * we try to access any of the MMIO registers. It is also
8014 * critical that the PCI-X hw workaround situation is decided
8015 * before that as well.
8016 */
8017 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8018 &misc_ctrl_reg);
8019
8020 tp->pci_chip_rev_id = (misc_ctrl_reg >>
8021 MISC_HOST_CTRL_CHIPREV_SHIFT);
8022
ff645bec
MC		 8023 /* Wrong chip ID in 5752 A0. This code can be removed later
8024 * as A0 is not in production.
8025 */
8026 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8027 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8028
1da177e4
LT		 8029 /* Initialize misc host control in PCI block. */
8030 tp->misc_host_ctrl |= (misc_ctrl_reg &
8031 MISC_HOST_CTRL_CHIPREV);
8032 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8033 tp->misc_host_ctrl);
8034
8035 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8036 &cacheline_sz_reg);
8037
8038 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
8039 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
8040 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
8041 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8042
6708e5cc 8043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
ff645bec 8044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6708e5cc
JL		 8045 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8046
1b440c56
JL		 8047 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8048 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8049 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8050
bb7064dc 8051 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8052 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8053
8054 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8055 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8056
8057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8058 tp->pci_lat_timer < 64) {
8059 tp->pci_lat_timer = 64;
8060
8061 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
8062 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
8063 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
8064 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
8065
8066 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8067 cacheline_sz_reg);
8068 }
8069
8070 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8071 &pci_state_reg);
8072
8073 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8074 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8075
8076 /* If this is a 5700 BX chipset, and we are in PCI-X
8077 * mode, enable register write workaround.
8078 *
8079 * The workaround is to use indirect register accesses
8080 * for all chip writes not to mailbox registers.
8081 */
8082 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8083 u32 pm_reg;
8084 u16 pci_cmd;
8085
8086 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8087
8088 /* The chip can have it's power management PCI config
8089 * space registers clobbered due to this bug.
8090 * So explicitly force the chip into D0 here.
8091 */
8092 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8093 &pm_reg);
8094 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8095 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8096 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8097 pm_reg);
8098
8099 /* Also, force SERR#/PERR# in PCI command. */
8100 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8101 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8102 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8103 }
8104 }
8105
8106 /* Back to back register writes can cause problems on this chip,
8107 * the workaround is to read back all reg writes except those to
8108 * mailbox regs. See tg3_write_indirect_reg32().
8109 *
8110 * PCI Express 5750_A0 rev chips need this workaround too.
8111 */
8112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8113 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8114 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8115 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8116
8117 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8118 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8119 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8120 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8121
8122 /* Chip-specific fixup from Broadcom driver */
8123 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8124 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8125 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8126 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8127 }
8128
7d0c41ef
MC		 8129 /* Get eeprom hw config before calling tg3_set_power_state().
8130 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8131 * determined before calling tg3_set_power_state() so that
8132 * we know whether or not to switch out of Vaux power.
8133 * When the flag is set, it means that GPIO1 is used for eeprom
8134 * write protect and also implies that it is a LOM where GPIOs
8135 * are not used to switch power.
8136 */
8137 tg3_get_eeprom_hw_cfg(tp);
8138
314fba34
MC		 8139 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8140 * GPIO1 driven high will bring 5700's external PHY out of reset.
8141 * It is also used as eeprom write protect on LOMs.
8142 */
8143 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8144 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8145 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8146 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8147 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 8148 /* Unused GPIO3 must be driven as output on 5752 because there
8149 * are no pull-up resistors on unused GPIO pins.
8150 */
8151 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8152 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 8153
1da177e4
LT		 8154 /* Force the chip into D0. */
8155 err = tg3_set_power_state(tp, 0);
8156 if (err) {
8157 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
8158 pci_name(tp->pdev));
8159 return err;
8160 }
8161
8162 /* 5700 B0 chips do not support checksumming correctly due
8163 * to hardware bugs.
8164 */
8165 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
8166 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
8167
8168 /* Pseudo-header checksum is done by hardware logic and not
8169 * the offload processers, so make the chip do the pseudo-
8170 * header checksums on receive. For transmit it is more
8171 * convenient to do the pseudo-header checksum in software
8172 * as Linux does that on transmit for us in all cases.
8173 */
8174 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
8175 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
8176
8177 /* Derive initial jumbo mode from MTU assigned in
8178 * ether_setup() via the alloc_etherdev() call
8179 */
8180 if (tp->dev->mtu > ETH_DATA_LEN)
8181 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
8182
8183 /* Determine WakeOnLan speed to use. */
8184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8185 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8186 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
8187 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
8188 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
8189 } else {
8190 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
8191 }
8192
8193 /* A few boards don't want Ethernet@WireSpeed phy feature */
8194 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8195 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
8196 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
8197 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
8198 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
8199
8200 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
8201 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
8202 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
8203 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
8204 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
8205
bb7064dc 8206 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 8207 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8208
8209 /* Only 5701 and later support tagged irq status mode.
8210 * Also, 5788 chips cannot use tagged irq status.
8211 *
8212 * However, since we are using NAPI avoid tagged irq status
8213 * because the interrupt condition is more difficult to
8214 * fully clear in that mode.
8215 */
8216 tp->coalesce_mode = 0;
8217
8218 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
8219 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
8220 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
8221
8222 /* Initialize MAC MI mode, polling disabled. */
8223 tw32_f(MAC_MI_MODE, tp->mi_mode);
8224 udelay(80);
8225
8226 /* Initialize data/descriptor byte/word swapping. */
8227 val = tr32(GRC_MODE);
8228 val &= GRC_MODE_HOST_STACKUP;
8229 tw32(GRC_MODE, val | tp->grc_mode);
8230
8231 tg3_switch_clocks(tp);
8232
8233 /* Clear this out for sanity. */
8234 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8235
8236 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8237 &pci_state_reg);
8238 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
8239 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
8240 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
8241
8242 if (chiprevid == CHIPREV_ID_5701_A0 ||
8243 chiprevid == CHIPREV_ID_5701_B0 ||
8244 chiprevid == CHIPREV_ID_5701_B2 ||
8245 chiprevid == CHIPREV_ID_5701_B5) {
8246 void __iomem *sram_base;
8247
8248 /* Write some dummy words into the SRAM status block
8249 * area, see if it reads back correctly. If the return
8250 * value is bad, force enable the PCIX workaround.
8251 */
8252 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
8253
8254 writel(0x00000000, sram_base);
8255 writel(0x00000000, sram_base + 4);
8256 writel(0xffffffff, sram_base + 4);
8257 if (readl(sram_base) != 0x00000000)
8258 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8259 }
8260 }
8261
8262 udelay(50);
8263 tg3_nvram_init(tp);
8264
8265 grc_misc_cfg = tr32(GRC_MISC_CFG);
8266 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
8267
8268 /* Broadcom's driver says that CIOBE multisplit has a bug */
8269#if 0
8270 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8271 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
8272 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
8273 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
8274 }
8275#endif
8276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8277 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
8278 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
8279 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
8280
8281 /* these are limited to 10/100 only */
8282 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8283 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
8284 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8285 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8286 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
8287 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
8288 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
8289 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8290 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
8291 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
8292 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
8293
8294 err = tg3_phy_probe(tp);
8295 if (err) {
8296 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
8297 pci_name(tp->pdev), err);
8298 /* ... but do not return immediately ... */
8299 }
8300
8301 tg3_read_partno(tp);
8302
8303 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8304 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8305 } else {
8306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8307 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
8308 else
8309 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8310 }
8311
8312 /* 5700 {AX,BX} chips have a broken status block link
8313 * change bit implementation, so we must use the
8314 * status register in those cases.
8315 */
8316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8317 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
8318 else
8319 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
8320
8321 /* The led_ctrl is set during tg3_phy_probe, here we might
8322 * have to force the link status polling mechanism based
8323 * upon subsystem IDs.
8324 */
8325 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
8326 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8327 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
8328 TG3_FLAG_USE_LINKCHG_REG);
8329 }
8330
8331 /* For all SERDES we poll the MAC status register. */
8332 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8333 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
8334 else
8335 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
8336
8337 /* 5700 BX chips need to have their TX producer index mailboxes
8338 * written twice to workaround a bug.
8339 */
8340 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
8341 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
8342 else
8343 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
8344
8345 /* It seems all chips can get confused if TX buffers
8346 * straddle the 4GB address boundary in some cases.
8347 */
8348 tp->dev->hard_start_xmit = tg3_start_xmit;
8349
8350 tp->rx_offset = 2;
8351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
8352 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
8353 tp->rx_offset = 0;
8354
8355 /* By default, disable wake-on-lan. User can change this
8356 * using ETHTOOL_SWOL.
8357 */
8358 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8359
8360 return err;
8361}
8362
8363#ifdef CONFIG_SPARC64
8364static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
8365{
8366 struct net_device *dev = tp->dev;
8367 struct pci_dev *pdev = tp->pdev;
8368 struct pcidev_cookie *pcp = pdev->sysdata;
8369
8370 if (pcp != NULL) {
8371 int node = pcp->prom_node;
8372
8373 if (prom_getproplen(node, "local-mac-address") == 6) {
8374 prom_getproperty(node, "local-mac-address",
8375 dev->dev_addr, 6);
8376 return 0;
8377 }
8378 }
8379 return -ENODEV;
8380}
8381
8382static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
8383{
8384 struct net_device *dev = tp->dev;
8385
8386 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
8387 return 0;
8388}
8389#endif
8390
8391static int __devinit tg3_get_device_address(struct tg3 *tp)
8392{
8393 struct net_device *dev = tp->dev;
8394 u32 hi, lo, mac_offset;
8395
8396#ifdef CONFIG_SPARC64
8397 if (!tg3_get_macaddr_sparc(tp))
8398 return 0;
8399#endif
8400
8401 mac_offset = 0x7c;
8402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8403 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
8404 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
8405 mac_offset = 0xcc;
8406 if (tg3_nvram_lock(tp))
8407 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
8408 else
8409 tg3_nvram_unlock(tp);
8410 }
8411
8412 /* First try to get it from MAC address mailbox. */
8413 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
8414 if ((hi >> 16) == 0x484b) {
8415 dev->dev_addr[0] = (hi >> 8) & 0xff;
8416 dev->dev_addr[1] = (hi >> 0) & 0xff;
8417
8418 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
8419 dev->dev_addr[2] = (lo >> 24) & 0xff;
8420 dev->dev_addr[3] = (lo >> 16) & 0xff;
8421 dev->dev_addr[4] = (lo >> 8) & 0xff;
8422 dev->dev_addr[5] = (lo >> 0) & 0xff;
8423 }
8424 /* Next, try NVRAM. */
8425 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
8426 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
8427 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
8428 dev->dev_addr[0] = ((hi >> 16) & 0xff);
8429 dev->dev_addr[1] = ((hi >> 24) & 0xff);
8430 dev->dev_addr[2] = ((lo >> 0) & 0xff);
8431 dev->dev_addr[3] = ((lo >> 8) & 0xff);
8432 dev->dev_addr[4] = ((lo >> 16) & 0xff);
8433 dev->dev_addr[5] = ((lo >> 24) & 0xff);
8434 }
8435 /* Finally just fetch it out of the MAC control regs. */
8436 else {
8437 hi = tr32(MAC_ADDR_0_HIGH);
8438 lo = tr32(MAC_ADDR_0_LOW);
8439
8440 dev->dev_addr[5] = lo & 0xff;
8441 dev->dev_addr[4] = (lo >> 8) & 0xff;
8442 dev->dev_addr[3] = (lo >> 16) & 0xff;
8443 dev->dev_addr[2] = (lo >> 24) & 0xff;
8444 dev->dev_addr[1] = hi & 0xff;
8445 dev->dev_addr[0] = (hi >> 8) & 0xff;
8446 }
8447
8448 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8449#ifdef CONFIG_SPARC64
8450 if (!tg3_get_default_macaddr_sparc(tp))
8451 return 0;
8452#endif
8453 return -EINVAL;
8454 }
8455 return 0;
8456}
8457
8458static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
8459{
8460 struct tg3_internal_buffer_desc test_desc;
8461 u32 sram_dma_descs;
8462 int i, ret;
8463
8464 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
8465
8466 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
8467 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
8468 tw32(RDMAC_STATUS, 0);
8469 tw32(WDMAC_STATUS, 0);
8470
8471 tw32(BUFMGR_MODE, 0);
8472 tw32(FTQ_RESET, 0);
8473
8474 test_desc.addr_hi = ((u64) buf_dma) >> 32;
8475 test_desc.addr_lo = buf_dma & 0xffffffff;
8476 test_desc.nic_mbuf = 0x00002100;
8477 test_desc.len = size;
8478
8479 /*
8480 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
8481 * the *second* time the tg3 driver was getting loaded after an
8482 * initial scan.
8483 *
8484 * Broadcom tells me:
8485 * ...the DMA engine is connected to the GRC block and a DMA
8486 * reset may affect the GRC block in some unpredictable way...
8487 * The behavior of resets to individual blocks has not been tested.
8488 *
8489 * Broadcom noted the GRC reset will also reset all sub-components.
8490 */
8491 if (to_device) {
8492 test_desc.cqid_sqid = (13 << 8) | 2;
8493
8494 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
8495 udelay(40);
8496 } else {
8497 test_desc.cqid_sqid = (16 << 8) | 7;
8498
8499 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
8500 udelay(40);
8501 }
8502 test_desc.flags = 0x00000005;
8503
8504 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
8505 u32 val;
8506
8507 val = *(((u32 *)&test_desc) + i);
8508 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
8509 sram_dma_descs + (i * sizeof(u32)));
8510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
8511 }
8512 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
8513
8514 if (to_device) {
8515 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
8516 } else {
8517 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
8518 }
8519
8520 ret = -ENODEV;
8521 for (i = 0; i < 40; i++) {
8522 u32 val;
8523
8524 if (to_device)
8525 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
8526 else
8527 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
8528 if ((val & 0xffff) == sram_dma_descs) {
8529 ret = 0;
8530 break;
8531 }
8532
8533 udelay(100);
8534 }
8535
8536 return ret;
8537}
8538
8539#define TEST_BUFFER_SIZE 0x400
8540
8541static int __devinit tg3_test_dma(struct tg3 *tp)
8542{
8543 dma_addr_t buf_dma;
8544 u32 *buf;
8545 int ret;
8546
8547 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
8548 if (!buf) {
8549 ret = -ENOMEM;
8550 goto out_nofree;
8551 }
8552
8553 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
8554 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
8555
8556#ifndef CONFIG_X86
8557 {
8558 u8 byte;
8559 int cacheline_size;
8560 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
8561
8562 if (byte == 0)
8563 cacheline_size = 1024;
8564 else
8565 cacheline_size = (int) byte * 4;
8566
8567 switch (cacheline_size) {
8568 case 16:
8569 case 32:
8570 case 64:
8571 case 128:
8572 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8573 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8574 tp->dma_rwctrl |=
8575 DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
8576 break;
8577 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8578 tp->dma_rwctrl &=
8579 ~(DMA_RWCTRL_PCI_WRITE_CMD);
8580 tp->dma_rwctrl |=
8581 DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
8582 break;
8583 }
8584 /* fallthrough */
8585 case 256:
8586 if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8587 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8588 tp->dma_rwctrl |=
8589 DMA_RWCTRL_WRITE_BNDRY_256;
8590 else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8591 tp->dma_rwctrl |=
8592 DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
8593 };
8594 }
8595#endif
8596
8597 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8598 /* DMA read watermark not used on PCIE */
8599 tp->dma_rwctrl |= 0x00180000;
8600 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 8601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
8602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 8603 tp->dma_rwctrl |= 0x003f0000;
8604 else
8605 tp->dma_rwctrl |= 0x003f000f;
8606 } else {
8607 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
8608 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8609 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
8610
8611 if (ccval == 0x6 || ccval == 0x7)
8612 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
8613
8614 /* Set bit 23 to renable PCIX hw bug fix */
8615 tp->dma_rwctrl |= 0x009f0000;
8616 } else {
8617 tp->dma_rwctrl |= 0x001b000f;
8618 }
8619 }
8620
8621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
8622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8623 tp->dma_rwctrl &= 0xfffffff0;
8624
8625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8626 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
8627 /* Remove this if it causes problems for some boards. */
8628 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
8629
8630 /* On 5700/5701 chips, we need to set this bit.
8631 * Otherwise the chip will issue cacheline transactions
8632 * to streamable DMA memory with not all the byte
8633 * enables turned on. This is an error on several
8634 * RISC PCI controllers, in particular sparc64.
8635 *
8636 * On 5703/5704 chips, this bit has been reassigned
8637 * a different meaning. In particular, it is used
8638 * on those chips to enable a PCI-X workaround.
8639 */
8640 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
8641 }
8642
8643 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8644
8645#if 0
8646 /* Unneeded, already done by tg3_get_invariants. */
8647 tg3_switch_clocks(tp);
8648#endif
8649
8650 ret = 0;
8651 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8652 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
8653 goto out;
8654
8655 while (1) {
8656 u32 *p = buf, i;
8657
8658 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
8659 p[i] = i;
8660
8661 /* Send the buffer to the chip. */
8662 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
8663 if (ret) {
8664 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
8665 break;
8666 }
8667
8668#if 0
8669 /* validate data reached card RAM correctly. */
8670 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8671 u32 val;
8672 tg3_read_mem(tp, 0x2100 + (i*4), &val);
8673 if (le32_to_cpu(val) != p[i]) {
8674 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
8675 /* ret = -ENODEV here? */
8676 }
8677 p[i] = 0;
8678 }
8679#endif
8680 /* Now read it back. */
8681 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
8682 if (ret) {
8683 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
8684
8685 break;
8686 }
8687
8688 /* Verify it. */
8689 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8690 if (p[i] == i)
8691 continue;
8692
8693 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
8694 DMA_RWCTRL_WRITE_BNDRY_DISAB) {
8695 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
8696 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8697 break;
8698 } else {
8699 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
8700 ret = -ENODEV;
8701 goto out;
8702 }
8703 }
8704
8705 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
8706 /* Success. */
8707 ret = 0;
8708 break;
8709 }
8710 }
8711
8712out:
8713 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
8714out_nofree:
8715 return ret;
8716}
8717
8718static void __devinit tg3_init_link_config(struct tg3 *tp)
8719{
8720 tp->link_config.advertising =
8721 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
8722 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
8723 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
8724 ADVERTISED_Autoneg | ADVERTISED_MII);
8725 tp->link_config.speed = SPEED_INVALID;
8726 tp->link_config.duplex = DUPLEX_INVALID;
8727 tp->link_config.autoneg = AUTONEG_ENABLE;
8728 netif_carrier_off(tp->dev);
8729 tp->link_config.active_speed = SPEED_INVALID;
8730 tp->link_config.active_duplex = DUPLEX_INVALID;
8731 tp->link_config.phy_is_low_power = 0;
8732 tp->link_config.orig_speed = SPEED_INVALID;
8733 tp->link_config.orig_duplex = DUPLEX_INVALID;
8734 tp->link_config.orig_autoneg = AUTONEG_INVALID;
8735}
8736
8737static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
8738{
8739 tp->bufmgr_config.mbuf_read_dma_low_water =
8740 DEFAULT_MB_RDMA_LOW_WATER;
8741 tp->bufmgr_config.mbuf_mac_rx_low_water =
8742 DEFAULT_MB_MACRX_LOW_WATER;
8743 tp->bufmgr_config.mbuf_high_water =
8744 DEFAULT_MB_HIGH_WATER;
8745
8746 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
8747 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
8748 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
8749 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
8750 tp->bufmgr_config.mbuf_high_water_jumbo =
8751 DEFAULT_MB_HIGH_WATER_JUMBO;
8752
8753 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
8754 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
8755}
8756
8757static char * __devinit tg3_phy_string(struct tg3 *tp)
8758{
8759 switch (tp->phy_id & PHY_ID_MASK) {
8760 case PHY_ID_BCM5400: return "5400";
8761 case PHY_ID_BCM5401: return "5401";
8762 case PHY_ID_BCM5411: return "5411";
8763 case PHY_ID_BCM5701: return "5701";
8764 case PHY_ID_BCM5703: return "5703";
8765 case PHY_ID_BCM5704: return "5704";
8766 case PHY_ID_BCM5705: return "5705";
8767 case PHY_ID_BCM5750: return "5750";
85e94ced 8768 case PHY_ID_BCM5752: return "5752";
1da177e4
LT		 8769 case PHY_ID_BCM8002: return "8002/serdes";
8770 case 0: return "serdes";
8771 default: return "unknown";
8772 };
8773}
8774
8775static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
8776{
8777 struct pci_dev *peer;
8778 unsigned int func, devnr = tp->pdev->devfn & ~7;
8779
8780 for (func = 0; func < 8; func++) {
8781 peer = pci_get_slot(tp->pdev->bus, devnr | func);
8782 if (peer && peer != tp->pdev)
8783 break;
8784 pci_dev_put(peer);
8785 }
8786 if (!peer || peer == tp->pdev)
8787 BUG();
8788
8789 /*
8790 * We don't need to keep the refcount elevated; there's no way
8791 * to remove one half of this device without removing the other
8792 */
8793 pci_dev_put(peer);
8794
8795 return peer;
8796}
8797
8798static int __devinit tg3_init_one(struct pci_dev *pdev,
8799 const struct pci_device_id *ent)
8800{
8801 static int tg3_version_printed = 0;
8802 unsigned long tg3reg_base, tg3reg_len;
8803 struct net_device *dev;
8804 struct tg3 *tp;
8805 int i, err, pci_using_dac, pm_cap;
8806
8807 if (tg3_version_printed++ == 0)
8808 printk(KERN_INFO "%s", version);
8809
8810 err = pci_enable_device(pdev);
8811 if (err) {
8812 printk(KERN_ERR PFX "Cannot enable PCI device, "
8813 "aborting.\n");
8814 return err;
8815 }
8816
8817 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8818 printk(KERN_ERR PFX "Cannot find proper PCI device "
8819 "base address, aborting.\n");
8820 err = -ENODEV;
8821 goto err_out_disable_pdev;
8822 }
8823
8824 err = pci_request_regions(pdev, DRV_MODULE_NAME);
8825 if (err) {
8826 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
8827 "aborting.\n");
8828 goto err_out_disable_pdev;
8829 }
8830
8831 pci_set_master(pdev);
8832
8833 /* Find power-management capability. */
8834 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
8835 if (pm_cap == 0) {
8836 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
8837 "aborting.\n");
8838 err = -EIO;
8839 goto err_out_free_res;
8840 }
8841
8842 /* Configure DMA attributes. */
8843 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
8844 if (!err) {
8845 pci_using_dac = 1;
8846 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
8847 if (err < 0) {
8848 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
8849 "for consistent allocations\n");
8850 goto err_out_free_res;
8851 }
8852 } else {
8853 err = pci_set_dma_mask(pdev, 0xffffffffULL);
8854 if (err) {
8855 printk(KERN_ERR PFX "No usable DMA configuration, "
8856 "aborting.\n");
8857 goto err_out_free_res;
8858 }
8859 pci_using_dac = 0;
8860 }
8861
8862 tg3reg_base = pci_resource_start(pdev, 0);
8863 tg3reg_len = pci_resource_len(pdev, 0);
8864
8865 dev = alloc_etherdev(sizeof(*tp));
8866 if (!dev) {
8867 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
8868 err = -ENOMEM;
8869 goto err_out_free_res;
8870 }
8871
8872 SET_MODULE_OWNER(dev);
8873 SET_NETDEV_DEV(dev, &pdev->dev);
8874
8875 if (pci_using_dac)
8876 dev->features |= NETIF_F_HIGHDMA;
8877 dev->features |= NETIF_F_LLTX;
8878#if TG3_VLAN_TAG_USED
8879 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8880 dev->vlan_rx_register = tg3_vlan_rx_register;
8881 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
8882#endif
8883
8884 tp = netdev_priv(dev);
8885 tp->pdev = pdev;
8886 tp->dev = dev;
8887 tp->pm_cap = pm_cap;
8888 tp->mac_mode = TG3_DEF_MAC_MODE;
8889 tp->rx_mode = TG3_DEF_RX_MODE;
8890 tp->tx_mode = TG3_DEF_TX_MODE;
8891 tp->mi_mode = MAC_MI_MODE_BASE;
8892 if (tg3_debug > 0)
8893 tp->msg_enable = tg3_debug;
8894 else
8895 tp->msg_enable = TG3_DEF_MSG_ENABLE;
8896
8897 /* The word/byte swap controls here control register access byte
8898 * swapping. DMA data byte swapping is controlled in the GRC_MODE
8899 * setting below.
8900 */
8901 tp->misc_host_ctrl =
8902 MISC_HOST_CTRL_MASK_PCI_INT |
8903 MISC_HOST_CTRL_WORD_SWAP |
8904 MISC_HOST_CTRL_INDIR_ACCESS |
8905 MISC_HOST_CTRL_PCISTATE_RW;
8906
8907 /* The NONFRM (non-frame) byte/word swap controls take effect
8908 * on descriptor entries, anything which isn't packet data.
8909 *
8910 * The StrongARM chips on the board (one for tx, one for rx)
8911 * are running in big-endian mode.
8912 */
8913 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
8914 GRC_MODE_WSWAP_NONFRM_DATA);
8915#ifdef __BIG_ENDIAN
8916 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
8917#endif
8918 spin_lock_init(&tp->lock);
8919 spin_lock_init(&tp->tx_lock);
8920 spin_lock_init(&tp->indirect_lock);
8921 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
8922
8923 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
8924 if (tp->regs == 0UL) {
8925 printk(KERN_ERR PFX "Cannot map device registers, "
8926 "aborting.\n");
8927 err = -ENOMEM;
8928 goto err_out_free_dev;
8929 }
8930
8931 tg3_init_link_config(tp);
8932
8933 tg3_init_bufmgr_config(tp);
8934
8935 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
8936 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
8937 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
8938
8939 dev->open = tg3_open;
8940 dev->stop = tg3_close;
8941 dev->get_stats = tg3_get_stats;
8942 dev->set_multicast_list = tg3_set_rx_mode;
8943 dev->set_mac_address = tg3_set_mac_addr;
8944 dev->do_ioctl = tg3_ioctl;
8945 dev->tx_timeout = tg3_tx_timeout;
8946 dev->poll = tg3_poll;
8947 dev->ethtool_ops = &tg3_ethtool_ops;
8948 dev->weight = 64;
8949 dev->watchdog_timeo = TG3_TX_TIMEOUT;
8950 dev->change_mtu = tg3_change_mtu;
8951 dev->irq = pdev->irq;
8952#ifdef CONFIG_NET_POLL_CONTROLLER
8953 dev->poll_controller = tg3_poll_controller;
8954#endif
8955
8956 err = tg3_get_invariants(tp);
8957 if (err) {
8958 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
8959 "aborting.\n");
8960 goto err_out_iounmap;
8961 }
8962
8963 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8964 tp->bufmgr_config.mbuf_read_dma_low_water =
8965 DEFAULT_MB_RDMA_LOW_WATER_5705;
8966 tp->bufmgr_config.mbuf_mac_rx_low_water =
8967 DEFAULT_MB_MACRX_LOW_WATER_5705;
8968 tp->bufmgr_config.mbuf_high_water =
8969 DEFAULT_MB_HIGH_WATER_5705;
8970 }
8971
8972#if TG3_TSO_SUPPORT != 0
8973 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
8974 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8975 }
8976 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8978 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
8979 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
8980 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8981 } else {
8982 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8983 }
8984
8985 /* TSO is off by default, user can enable using ethtool. */
8986#if 0
8987 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
8988 dev->features |= NETIF_F_TSO;
8989#endif
8990
8991#endif
8992
8993 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
8994 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8995 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
8996 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
8997 tp->rx_pending = 63;
8998 }
8999
9000 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9001 tp->pdev_peer = tg3_find_5704_peer(tp);
9002
9003 err = tg3_get_device_address(tp);
9004 if (err) {
9005 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
9006 "aborting.\n");
9007 goto err_out_iounmap;
9008 }
9009
9010 /*
9011 * Reset chip in case UNDI or EFI driver did not shutdown
9012 * DMA self test will enable WDMAC and we'll see (spurious)
9013 * pending DMA on the PCI bus at that point.
9014 */
9015 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
9016 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9017 pci_save_state(tp->pdev);
9018 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
9019 tg3_halt(tp);
9020 }
9021
9022 err = tg3_test_dma(tp);
9023 if (err) {
9024 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
9025 goto err_out_iounmap;
9026 }
9027
9028 /* Tigon3 can do ipv4 only... and some chips have buggy
9029 * checksumming.
9030 */
9031 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
9032 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
9033 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9034 } else
9035 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9036
9037 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
9038 dev->features &= ~NETIF_F_HIGHDMA;
9039
9040 /* flow control autonegotiation is default behavior */
9041 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9042
9043 err = register_netdev(dev);
9044 if (err) {
9045 printk(KERN_ERR PFX "Cannot register net device, "
9046 "aborting.\n");
9047 goto err_out_iounmap;
9048 }
9049
9050 pci_set_drvdata(pdev, dev);
9051
9052 /* Now that we have fully setup the chip, save away a snapshot
9053 * of the PCI config space. We need to restore this after
9054 * GRC_MISC_CFG core clock resets and some resume events.
9055 */
9056 pci_save_state(tp->pdev);
9057
9058 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
9059 dev->name,
9060 tp->board_part_number,
9061 tp->pci_chip_rev_id,
9062 tg3_phy_string(tp),
9063 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
9064 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
9065 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
9066 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
9067 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
9068 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
9069
9070 for (i = 0; i < 6; i++)
9071 printk("%2.2x%c", dev->dev_addr[i],
9072 i == 5 ? '\n' : ':');
9073
9074 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
9075 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
9076 "TSOcap[%d] \n",
9077 dev->name,
9078 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
9079 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
9080 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
9081 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
9082 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
9083 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
9084 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
9085
9086 return 0;
9087
9088err_out_iounmap:
9089 iounmap(tp->regs);
9090
9091err_out_free_dev:
9092 free_netdev(dev);
9093
9094err_out_free_res:
9095 pci_release_regions(pdev);
9096
9097err_out_disable_pdev:
9098 pci_disable_device(pdev);
9099 pci_set_drvdata(pdev, NULL);
9100 return err;
9101}
9102
9103static void __devexit tg3_remove_one(struct pci_dev *pdev)
9104{
9105 struct net_device *dev = pci_get_drvdata(pdev);
9106
9107 if (dev) {
9108 struct tg3 *tp = netdev_priv(dev);
9109
9110 unregister_netdev(dev);
9111 iounmap(tp->regs);
9112 free_netdev(dev);
9113 pci_release_regions(pdev);
9114 pci_disable_device(pdev);
9115 pci_set_drvdata(pdev, NULL);
9116 }
9117}
9118
9119static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9120{
9121 struct net_device *dev = pci_get_drvdata(pdev);
9122 struct tg3 *tp = netdev_priv(dev);
9123 int err;
9124
9125 if (!netif_running(dev))
9126 return 0;
9127
9128 tg3_netif_stop(tp);
9129
9130 del_timer_sync(&tp->timer);
9131
9132 spin_lock_irq(&tp->lock);
9133 spin_lock(&tp->tx_lock);
9134 tg3_disable_ints(tp);
9135 spin_unlock(&tp->tx_lock);
9136 spin_unlock_irq(&tp->lock);
9137
9138 netif_device_detach(dev);
9139
9140 spin_lock_irq(&tp->lock);
9141 spin_lock(&tp->tx_lock);
9142 tg3_halt(tp);
9143 spin_unlock(&tp->tx_lock);
9144 spin_unlock_irq(&tp->lock);
9145
9146 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
9147 if (err) {
9148 spin_lock_irq(&tp->lock);
9149 spin_lock(&tp->tx_lock);
9150
9151 tg3_init_hw(tp);
9152
9153 tp->timer.expires = jiffies + tp->timer_offset;
9154 add_timer(&tp->timer);
9155
9156 netif_device_attach(dev);
9157 tg3_netif_start(tp);
9158
9159 spin_unlock(&tp->tx_lock);
9160 spin_unlock_irq(&tp->lock);
9161 }
9162
9163 return err;
9164}
9165
9166static int tg3_resume(struct pci_dev *pdev)
9167{
9168 struct net_device *dev = pci_get_drvdata(pdev);
9169 struct tg3 *tp = netdev_priv(dev);
9170 int err;
9171
9172 if (!netif_running(dev))
9173 return 0;
9174
9175 pci_restore_state(tp->pdev);
9176
9177 err = tg3_set_power_state(tp, 0);
9178 if (err)
9179 return err;
9180
9181 netif_device_attach(dev);
9182
9183 spin_lock_irq(&tp->lock);
9184 spin_lock(&tp->tx_lock);
9185
9186 tg3_init_hw(tp);
9187
9188 tp->timer.expires = jiffies + tp->timer_offset;
9189 add_timer(&tp->timer);
9190
9191 tg3_enable_ints(tp);
9192
9193 tg3_netif_start(tp);
9194
9195 spin_unlock(&tp->tx_lock);
9196 spin_unlock_irq(&tp->lock);
9197
9198 return 0;
9199}
9200
9201static struct pci_driver tg3_driver = {
9202 .name = DRV_MODULE_NAME,
9203 .id_table = tg3_pci_tbl,
9204 .probe = tg3_init_one,
9205 .remove = __devexit_p(tg3_remove_one),
9206 .suspend = tg3_suspend,
9207 .resume = tg3_resume
9208};
9209
9210static int __init tg3_init(void)
9211{
9212 return pci_module_init(&tg3_driver);
9213}
9214
9215static void __exit tg3_cleanup(void)
9216{
9217 pci_unregister_driver(&tg3_driver);
9218}
9219
9220module_init(tg3_init);
9221module_exit(tg3_cleanup);
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