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[TG3]: Power down 5704 serdes transceiver when shutting down.
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/byteorder.h>
47#include <asm/uaccess.h>
48
49#ifdef CONFIG_SPARC64
50#include <asm/idprom.h>
51#include <asm/oplib.h>
52#include <asm/pbm.h>
53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
c1d2a196
MC		 67#define DRV_MODULE_VERSION "3.72"
68#define DRV_MODULE_RELDATE "January 8, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
13185217
HK		 201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
1da177e4
LT		 209};
210
211MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
50da859d 213static const struct {
1da177e4
LT		 214 const char string[ETH_GSTRING_LEN];
215} ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292};
293
50da859d 294static const struct {
4cafd3f5
MC		 295 const char string[ETH_GSTRING_LEN];
296} ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303};
304
b401e9e2
MC		 305static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306{
307 writel(val, tp->regs + off);
308}
309
310static u32 tg3_read32(struct tg3 *tp, u32 off)
311{
6aa20a22 312 return (readl(tp->regs + off));
b401e9e2
MC		 313}
314
1da177e4
LT		 315static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316{
6892914f
MC		 317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 323}
324
325static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326{
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
1da177e4
LT		 329}
330
6892914f 331static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 332{
6892914f
MC		 333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341}
342
343static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344{
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
1da177e4 356 }
6892914f
MC		 357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371}
372
373static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374{
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383}
384
b401e9e2
MC		 385/* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 391{
b401e9e2
MC		 392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
1da177e4
LT		 408}
409
09ee929c
MC		 410static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411{
412 tp->write32_mbox(tp, off, val);
6892914f
MC		 413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
09ee929c
MC		 416}
417
20094930 418static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 419{
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426}
427
b5d3772c
MC		 428static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429{
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431}
432
433static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434{
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436}
437
20094930 438#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 439#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 440#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 442#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 443
444#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 445#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 447#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 448
449static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450{
6892914f
MC		 451 unsigned long flags;
452
b5d3772c
MC		 453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
6892914f 457 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 461
bbadf503
MC		 462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 467
bbadf503
MC		 468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 472}
473
1da177e4
LT		 474static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475{
6892914f
MC		 476 unsigned long flags;
477
b5d3772c
MC		 478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
6892914f 484 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 488
bbadf503
MC		 489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 499}
500
501static void tg3_disable_ints(struct tg3 *tp)
502{
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 506}
507
508static inline void tg3_cond_int(struct tg3 *tp)
509{
38f3843e
MC		 510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 516}
517
518static void tg3_enable_ints(struct tg3 *tp)
519{
bbe832c0
MC		 520 tp->irq_sync = 0;
521 wmb();
522
1da177e4
LT		 523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
fcfa0a32
MC		 527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
1da177e4
LT		 530 tg3_cond_int(tp);
531}
532
04237ddd
MC		 533static inline unsigned int tg3_has_work(struct tg3 *tp)
534{
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551}
552
1da177e4 553/* tg3_restart_ints
04237ddd
MC		 554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
6aa20a22 556 * which reenables interrupts
1da177e4
LT		 557 */
558static void tg3_restart_ints(struct tg3 *tp)
559{
fac9b83e
DM		 560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
1da177e4
LT		 562 mmiowb();
563
fac9b83e
DM		 564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
04237ddd
MC		 570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 572}
573
574static inline void tg3_netif_stop(struct tg3 *tp)
575{
bbe832c0 576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579}
580
581static inline void tg3_netif_start(struct tg3 *tp)
582{
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
f47c11ee
DM		 589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
1da177e4
LT		 591}
592
593static void tg3_switch_clocks(struct tg3 *tp)
594{
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
a4e2b347 598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 599 return;
600
1da177e4
LT		 601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
1da177e4 620 }
b401e9e2 621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 622}
623
624#define PHY_BUSY_LOOPS 5000
625
626static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627{
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 645
1da177e4
LT		 646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673}
674
675static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676{
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
b5d3772c
MC		 681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
1da177e4
LT		 685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 697
1da177e4
LT		 698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722}
723
724static void tg3_phy_set_wirespeed(struct tg3 *tp)
725{
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735}
736
737static int tg3_bmcr_reset(struct tg3 *tp)
738{
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766}
767
768static int tg3_wait_macro_done(struct tg3 *tp)
769{
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784}
785
786static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787{
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850}
851
852static int tg3_phy_reset_chanpat(struct tg3 *tp)
853{
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870}
871
872static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873{
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946}
947
c8e1e82b
MC		 948static void tg3_link_report(struct tg3 *);
949
1da177e4
LT		 950/* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953static int tg3_phy_reset(struct tg3 *tp)
954{
955 u32 phy_status;
956 int err;
957
60189ddf
MC		 958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
1da177e4
LT		 965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
c8e1e82b
MC		 970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
1da177e4
LT		 975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
c424cb24
MC		 1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1da177e4
LT		 1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
0f893dc6 1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
715116a1
MC		 1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1da177e4
LT		 1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067}
1068
1069static void tg3_frob_aux_power(struct tg3 *tp)
1070{
1071 struct tg3 *tp_peer = tp;
1072
9d26e213 1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1074 return;
1075
8c2dc7e1
MC		 1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1081 /* remove_one() may have been run on the peer. */
8c2dc7e1 1082 if (!dev_peer)
bc1c7567
MC		 1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1086 }
1087
1da177e4 1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1da177e4
LT		 1101 } else {
1102 u32 no_gpio2;
dc56b7d4 1103 u32 grc_local_ctrl = 0;
1da177e4
LT		 1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
dc56b7d4
MC		 1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
dc56b7d4
MC		 1115 }
1116
1da177e4
LT		 1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
dc56b7d4 1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
b401e9e2
MC		 1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1da177e4
LT		 1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
b401e9e2
MC		 1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1da177e4
LT		 1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1da177e4
LT		 1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
b401e9e2
MC		 1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1154
b401e9e2
MC		 1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1157
b401e9e2
MC		 1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1161 }
1162 }
1163}
1164
1165static int tg3_setup_phy(struct tg3 *, int);
1166
1167#define RESET_KIND_SHUTDOWN 0
1168#define RESET_KIND_INIT 1
1169#define RESET_KIND_SUSPEND 2
1170
1171static void tg3_write_sig_post_reset(struct tg3 *, int);
1172static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1173static int tg3_nvram_lock(struct tg3 *);
1174static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1175
15c3b696
MC		 1176static void tg3_power_down_phy(struct tg3 *tp)
1177{
5129724a
MC		 1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183 sg_dig_ctrl |=
1184 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187 }
3f7045c1 1188 return;
5129724a 1189 }
3f7045c1 1190
60189ddf
MC		 1191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192 u32 val;
1193
1194 tg3_bmcr_reset(tp);
1195 val = tr32(GRC_MISC_CFG);
1196 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197 udelay(40);
1198 return;
1199 } else {
715116a1
MC		 1200 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203 }
3f7045c1 1204
15c3b696
MC		 1205 /* The PHY should not be powered down on some chips because
1206 * of bugs.
1207 */
1208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212 return;
1213 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214}
1215
bc1c7567 1216static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1217{
1218 u32 misc_host_ctrl;
1219 u16 power_control, power_caps;
1220 int pm = tp->pm_cap;
1221
1222 /* Make sure register accesses (indirect or otherwise)
1223 * will function correctly.
1224 */
1225 pci_write_config_dword(tp->pdev,
1226 TG3PCI_MISC_HOST_CTRL,
1227 tp->misc_host_ctrl);
1228
1229 pci_read_config_word(tp->pdev,
1230 pm + PCI_PM_CTRL,
1231 &power_control);
1232 power_control |= PCI_PM_CTRL_PME_STATUS;
1233 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234 switch (state) {
bc1c7567 1235 case PCI_D0:
1da177e4
LT		 1236 power_control |= 0;
1237 pci_write_config_word(tp->pdev,
1238 pm + PCI_PM_CTRL,
1239 power_control);
8c6bda1a
MC		 1240 udelay(100); /* Delay after power state change */
1241
9d26e213
MC		 1242 /* Switch out of Vaux if it is a NIC */
1243 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1244 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1245
1246 return 0;
1247
bc1c7567 1248 case PCI_D1:
1da177e4
LT		 1249 power_control |= 1;
1250 break;
1251
bc1c7567 1252 case PCI_D2:
1da177e4
LT		 1253 power_control |= 2;
1254 break;
1255
bc1c7567 1256 case PCI_D3hot:
1da177e4
LT		 1257 power_control |= 3;
1258 break;
1259
1260 default:
1261 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262 "requested.\n",
1263 tp->dev->name, state);
1264 return -EINVAL;
1265 };
1266
1267 power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270 tw32(TG3PCI_MISC_HOST_CTRL,
1271 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273 if (tp->link_config.phy_is_low_power == 0) {
1274 tp->link_config.phy_is_low_power = 1;
1275 tp->link_config.orig_speed = tp->link_config.speed;
1276 tp->link_config.orig_duplex = tp->link_config.duplex;
1277 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278 }
1279
747e8f8b 1280 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1281 tp->link_config.speed = SPEED_10;
1282 tp->link_config.duplex = DUPLEX_HALF;
1283 tp->link_config.autoneg = AUTONEG_ENABLE;
1284 tg3_setup_phy(tp, 0);
1285 }
1286
b5d3772c
MC		 1287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288 u32 val;
1289
1290 val = tr32(GRC_VCPU_EXT_CTRL);
1291 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1293 int i;
1294 u32 val;
1295
1296 for (i = 0; i < 200; i++) {
1297 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299 break;
1300 msleep(1);
1301 }
1302 }
1303 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1304 WOL_DRV_STATE_SHUTDOWN |
1305 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1306
1da177e4
LT		 1307 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1308
1309 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1310 u32 mac_mode;
1311
1312 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1313 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1314 udelay(40);
1315
3f7045c1
MC		 1316 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1317 mac_mode = MAC_MODE_PORT_MODE_GMII;
1318 else
1319 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4
LT		 1320
1321 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1322 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1323 mac_mode |= MAC_MODE_LINK_POLARITY;
1324 } else {
1325 mac_mode = MAC_MODE_PORT_MODE_TBI;
1326 }
1327
cbf46853 1328 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1329 tw32(MAC_LED_CTRL, tp->led_ctrl);
1330
1331 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1332 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1333 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1334
1335 tw32_f(MAC_MODE, mac_mode);
1336 udelay(100);
1337
1338 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1339 udelay(10);
1340 }
1341
1342 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1343 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1345 u32 base_val;
1346
1347 base_val = tp->pci_clock_ctrl;
1348 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1349 CLOCK_CTRL_TXCLK_DISABLE);
1350
b401e9e2
MC		 1351 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1352 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857
MC		 1353 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1354 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1355 /* do nothing */
85e94ced 1356 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1357 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1358 u32 newbits1, newbits2;
1359
1360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1361 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1362 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1363 CLOCK_CTRL_TXCLK_DISABLE |
1364 CLOCK_CTRL_ALTCLK);
1365 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1366 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1367 newbits1 = CLOCK_CTRL_625_CORE;
1368 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1369 } else {
1370 newbits1 = CLOCK_CTRL_ALTCLK;
1371 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1372 }
1373
b401e9e2
MC		 1374 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1375 40);
1da177e4 1376
b401e9e2
MC		 1377 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1378 40);
1da177e4
LT		 1379
1380 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1381 u32 newbits3;
1382
1383 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1385 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1386 CLOCK_CTRL_TXCLK_DISABLE |
1387 CLOCK_CTRL_44MHZ_CORE);
1388 } else {
1389 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1390 }
1391
b401e9e2
MC		 1392 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1393 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1394 }
1395 }
1396
6921d201 1397 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
3f7045c1
MC		 1398 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1399 tg3_power_down_phy(tp);
6921d201 1400
1da177e4
LT		 1401 tg3_frob_aux_power(tp);
1402
1403 /* Workaround for unstable PLL clock */
1404 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1405 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1406 u32 val = tr32(0x7d00);
1407
1408 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1409 tw32(0x7d00, val);
6921d201 1410 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1411 int err;
1412
1413 err = tg3_nvram_lock(tp);
1da177e4 1414 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1415 if (!err)
1416 tg3_nvram_unlock(tp);
6921d201 1417 }
1da177e4
LT		 1418 }
1419
bbadf503
MC		 1420 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1421
1da177e4
LT		 1422 /* Finally, set the new power state. */
1423 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1424 udelay(100); /* Delay after power state change */
1da177e4 1425
1da177e4
LT		 1426 return 0;
1427}
1428
1429static void tg3_link_report(struct tg3 *tp)
1430{
1431 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1432 if (netif_msg_link(tp))
1433 printk(KERN_INFO PFX "%s: Link is down.\n",
1434 tp->dev->name);
1435 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1436 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1437 tp->dev->name,
1438 (tp->link_config.active_speed == SPEED_1000 ?
1439 1000 :
1440 (tp->link_config.active_speed == SPEED_100 ?
1441 100 : 10)),
1442 (tp->link_config.active_duplex == DUPLEX_FULL ?
1443 "full" : "half"));
1444
1445 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1446 "%s for RX.\n",
1447 tp->dev->name,
1448 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1449 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1450 }
1451}
1452
1453static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1454{
1455 u32 new_tg3_flags = 0;
1456 u32 old_rx_mode = tp->rx_mode;
1457 u32 old_tx_mode = tp->tx_mode;
1458
1459 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1460
1461 /* Convert 1000BaseX flow control bits to 1000BaseT
1462 * bits before resolving flow control.
1463 */
1464 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1465 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1466 ADVERTISE_PAUSE_ASYM);
1467 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1468
1469 if (local_adv & ADVERTISE_1000XPAUSE)
1470 local_adv |= ADVERTISE_PAUSE_CAP;
1471 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1472 local_adv |= ADVERTISE_PAUSE_ASYM;
1473 if (remote_adv & LPA_1000XPAUSE)
1474 remote_adv |= LPA_PAUSE_CAP;
1475 if (remote_adv & LPA_1000XPAUSE_ASYM)
1476 remote_adv |= LPA_PAUSE_ASYM;
1477 }
1478
1da177e4
LT		 1479 if (local_adv & ADVERTISE_PAUSE_CAP) {
1480 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1481 if (remote_adv & LPA_PAUSE_CAP)
1482 new_tg3_flags |=
1483 (TG3_FLAG_RX_PAUSE |
1484 TG3_FLAG_TX_PAUSE);
1485 else if (remote_adv & LPA_PAUSE_ASYM)
1486 new_tg3_flags |=
1487 (TG3_FLAG_RX_PAUSE);
1488 } else {
1489 if (remote_adv & LPA_PAUSE_CAP)
1490 new_tg3_flags |=
1491 (TG3_FLAG_RX_PAUSE |
1492 TG3_FLAG_TX_PAUSE);
1493 }
1494 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1495 if ((remote_adv & LPA_PAUSE_CAP) &&
1496 (remote_adv & LPA_PAUSE_ASYM))
1497 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1498 }
1499
1500 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1501 tp->tg3_flags |= new_tg3_flags;
1502 } else {
1503 new_tg3_flags = tp->tg3_flags;
1504 }
1505
1506 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1507 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1508 else
1509 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1510
1511 if (old_rx_mode != tp->rx_mode) {
1512 tw32_f(MAC_RX_MODE, tp->rx_mode);
1513 }
6aa20a22 1514
1da177e4
LT		 1515 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1516 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1517 else
1518 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1519
1520 if (old_tx_mode != tp->tx_mode) {
1521 tw32_f(MAC_TX_MODE, tp->tx_mode);
1522 }
1523}
1524
1525static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1526{
1527 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1528 case MII_TG3_AUX_STAT_10HALF:
1529 *speed = SPEED_10;
1530 *duplex = DUPLEX_HALF;
1531 break;
1532
1533 case MII_TG3_AUX_STAT_10FULL:
1534 *speed = SPEED_10;
1535 *duplex = DUPLEX_FULL;
1536 break;
1537
1538 case MII_TG3_AUX_STAT_100HALF:
1539 *speed = SPEED_100;
1540 *duplex = DUPLEX_HALF;
1541 break;
1542
1543 case MII_TG3_AUX_STAT_100FULL:
1544 *speed = SPEED_100;
1545 *duplex = DUPLEX_FULL;
1546 break;
1547
1548 case MII_TG3_AUX_STAT_1000HALF:
1549 *speed = SPEED_1000;
1550 *duplex = DUPLEX_HALF;
1551 break;
1552
1553 case MII_TG3_AUX_STAT_1000FULL:
1554 *speed = SPEED_1000;
1555 *duplex = DUPLEX_FULL;
1556 break;
1557
1558 default:
715116a1
MC		 1559 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1560 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1561 SPEED_10;
1562 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1563 DUPLEX_HALF;
1564 break;
1565 }
1da177e4
LT		 1566 *speed = SPEED_INVALID;
1567 *duplex = DUPLEX_INVALID;
1568 break;
1569 };
1570}
1571
1572static void tg3_phy_copper_begin(struct tg3 *tp)
1573{
1574 u32 new_adv;
1575 int i;
1576
1577 if (tp->link_config.phy_is_low_power) {
1578 /* Entering low power mode. Disable gigabit and
1579 * 100baseT advertisements.
1580 */
1581 tg3_writephy(tp, MII_TG3_CTRL, 0);
1582
1583 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1584 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1585 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1586 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1587
1588 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1589 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1590 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1591 tp->link_config.advertising &=
1592 ~(ADVERTISED_1000baseT_Half |
1593 ADVERTISED_1000baseT_Full);
1594
1595 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1596 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1597 new_adv |= ADVERTISE_10HALF;
1598 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1599 new_adv |= ADVERTISE_10FULL;
1600 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1601 new_adv |= ADVERTISE_100HALF;
1602 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1603 new_adv |= ADVERTISE_100FULL;
1604 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1605
1606 if (tp->link_config.advertising &
1607 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1608 new_adv = 0;
1609 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1610 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1611 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1612 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1613 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1614 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1615 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1616 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1617 MII_TG3_CTRL_ENABLE_AS_MASTER);
1618 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1619 } else {
1620 tg3_writephy(tp, MII_TG3_CTRL, 0);
1621 }
1622 } else {
1623 /* Asking for a specific link mode. */
1624 if (tp->link_config.speed == SPEED_1000) {
1625 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1626 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1627
1628 if (tp->link_config.duplex == DUPLEX_FULL)
1629 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1630 else
1631 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1632 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1633 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1634 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1635 MII_TG3_CTRL_ENABLE_AS_MASTER);
1636 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1637 } else {
1638 tg3_writephy(tp, MII_TG3_CTRL, 0);
1639
1640 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1641 if (tp->link_config.speed == SPEED_100) {
1642 if (tp->link_config.duplex == DUPLEX_FULL)
1643 new_adv |= ADVERTISE_100FULL;
1644 else
1645 new_adv |= ADVERTISE_100HALF;
1646 } else {
1647 if (tp->link_config.duplex == DUPLEX_FULL)
1648 new_adv |= ADVERTISE_10FULL;
1649 else
1650 new_adv |= ADVERTISE_10HALF;
1651 }
1652 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1653 }
1654 }
1655
1656 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1657 tp->link_config.speed != SPEED_INVALID) {
1658 u32 bmcr, orig_bmcr;
1659
1660 tp->link_config.active_speed = tp->link_config.speed;
1661 tp->link_config.active_duplex = tp->link_config.duplex;
1662
1663 bmcr = 0;
1664 switch (tp->link_config.speed) {
1665 default:
1666 case SPEED_10:
1667 break;
1668
1669 case SPEED_100:
1670 bmcr |= BMCR_SPEED100;
1671 break;
1672
1673 case SPEED_1000:
1674 bmcr |= TG3_BMCR_SPEED1000;
1675 break;
1676 };
1677
1678 if (tp->link_config.duplex == DUPLEX_FULL)
1679 bmcr |= BMCR_FULLDPLX;
1680
1681 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1682 (bmcr != orig_bmcr)) {
1683 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1684 for (i = 0; i < 1500; i++) {
1685 u32 tmp;
1686
1687 udelay(10);
1688 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1689 tg3_readphy(tp, MII_BMSR, &tmp))
1690 continue;
1691 if (!(tmp & BMSR_LSTATUS)) {
1692 udelay(40);
1693 break;
1694 }
1695 }
1696 tg3_writephy(tp, MII_BMCR, bmcr);
1697 udelay(40);
1698 }
1699 } else {
1700 tg3_writephy(tp, MII_BMCR,
1701 BMCR_ANENABLE | BMCR_ANRESTART);
1702 }
1703}
1704
1705static int tg3_init_5401phy_dsp(struct tg3 *tp)
1706{
1707 int err;
1708
1709 /* Turn off tap power management. */
1710 /* Set Extended packet length bit */
1711 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1712
1713 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1714 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1715
1716 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1717 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1718
1719 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1720 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1721
1722 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1723 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1724
1725 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1726 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1727
1728 udelay(40);
1729
1730 return err;
1731}
1732
3600d918 1733static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1734{
3600d918
MC		 1735 u32 adv_reg, all_mask = 0;
1736
1737 if (mask & ADVERTISED_10baseT_Half)
1738 all_mask |= ADVERTISE_10HALF;
1739 if (mask & ADVERTISED_10baseT_Full)
1740 all_mask |= ADVERTISE_10FULL;
1741 if (mask & ADVERTISED_100baseT_Half)
1742 all_mask |= ADVERTISE_100HALF;
1743 if (mask & ADVERTISED_100baseT_Full)
1744 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1745
1746 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1747 return 0;
1748
1da177e4
LT		 1749 if ((adv_reg & all_mask) != all_mask)
1750 return 0;
1751 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1752 u32 tg3_ctrl;
1753
3600d918
MC		 1754 all_mask = 0;
1755 if (mask & ADVERTISED_1000baseT_Half)
1756 all_mask |= ADVERTISE_1000HALF;
1757 if (mask & ADVERTISED_1000baseT_Full)
1758 all_mask |= ADVERTISE_1000FULL;
1759
1da177e4
LT		 1760 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1761 return 0;
1762
1da177e4
LT		 1763 if ((tg3_ctrl & all_mask) != all_mask)
1764 return 0;
1765 }
1766 return 1;
1767}
1768
1769static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1770{
1771 int current_link_up;
1772 u32 bmsr, dummy;
1773 u16 current_speed;
1774 u8 current_duplex;
1775 int i, err;
1776
1777 tw32(MAC_EVENT, 0);
1778
1779 tw32_f(MAC_STATUS,
1780 (MAC_STATUS_SYNC_CHANGED |
1781 MAC_STATUS_CFG_CHANGED |
1782 MAC_STATUS_MI_COMPLETION |
1783 MAC_STATUS_LNKSTATE_CHANGED));
1784 udelay(40);
1785
1786 tp->mi_mode = MAC_MI_MODE_BASE;
1787 tw32_f(MAC_MI_MODE, tp->mi_mode);
1788 udelay(80);
1789
1790 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1791
1792 /* Some third-party PHYs need to be reset on link going
1793 * down.
1794 */
1795 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1797 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1798 netif_carrier_ok(tp->dev)) {
1799 tg3_readphy(tp, MII_BMSR, &bmsr);
1800 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1801 !(bmsr & BMSR_LSTATUS))
1802 force_reset = 1;
1803 }
1804 if (force_reset)
1805 tg3_phy_reset(tp);
1806
1807 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1808 tg3_readphy(tp, MII_BMSR, &bmsr);
1809 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1810 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1811 bmsr = 0;
1812
1813 if (!(bmsr & BMSR_LSTATUS)) {
1814 err = tg3_init_5401phy_dsp(tp);
1815 if (err)
1816 return err;
1817
1818 tg3_readphy(tp, MII_BMSR, &bmsr);
1819 for (i = 0; i < 1000; i++) {
1820 udelay(10);
1821 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1822 (bmsr & BMSR_LSTATUS)) {
1823 udelay(40);
1824 break;
1825 }
1826 }
1827
1828 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1829 !(bmsr & BMSR_LSTATUS) &&
1830 tp->link_config.active_speed == SPEED_1000) {
1831 err = tg3_phy_reset(tp);
1832 if (!err)
1833 err = tg3_init_5401phy_dsp(tp);
1834 if (err)
1835 return err;
1836 }
1837 }
1838 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1839 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1840 /* 5701 {A0,B0} CRC bug workaround */
1841 tg3_writephy(tp, 0x15, 0x0a75);
1842 tg3_writephy(tp, 0x1c, 0x8c68);
1843 tg3_writephy(tp, 0x1c, 0x8d68);
1844 tg3_writephy(tp, 0x1c, 0x8c68);
1845 }
1846
1847 /* Clear pending interrupts... */
1848 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1849 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850
1851 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1852 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 1853 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 1854 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1855
1856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1858 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1859 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1860 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1861 else
1862 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1863 }
1864
1865 current_link_up = 0;
1866 current_speed = SPEED_INVALID;
1867 current_duplex = DUPLEX_INVALID;
1868
1869 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1870 u32 val;
1871
1872 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1873 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1874 if (!(val & (1 << 10))) {
1875 val |= (1 << 10);
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1877 goto relink;
1878 }
1879 }
1880
1881 bmsr = 0;
1882 for (i = 0; i < 100; i++) {
1883 tg3_readphy(tp, MII_BMSR, &bmsr);
1884 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1885 (bmsr & BMSR_LSTATUS))
1886 break;
1887 udelay(40);
1888 }
1889
1890 if (bmsr & BMSR_LSTATUS) {
1891 u32 aux_stat, bmcr;
1892
1893 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1894 for (i = 0; i < 2000; i++) {
1895 udelay(10);
1896 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1897 aux_stat)
1898 break;
1899 }
1900
1901 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1902 &current_speed,
1903 &current_duplex);
1904
1905 bmcr = 0;
1906 for (i = 0; i < 200; i++) {
1907 tg3_readphy(tp, MII_BMCR, &bmcr);
1908 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1909 continue;
1910 if (bmcr && bmcr != 0x7fff)
1911 break;
1912 udelay(10);
1913 }
1914
1915 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1916 if (bmcr & BMCR_ANENABLE) {
1917 current_link_up = 1;
1918
1919 /* Force autoneg restart if we are exiting
1920 * low power mode.
1921 */
3600d918
MC		 1922 if (!tg3_copper_is_advertising_all(tp,
1923 tp->link_config.advertising))
1da177e4
LT		 1924 current_link_up = 0;
1925 } else {
1926 current_link_up = 0;
1927 }
1928 } else {
1929 if (!(bmcr & BMCR_ANENABLE) &&
1930 tp->link_config.speed == current_speed &&
1931 tp->link_config.duplex == current_duplex) {
1932 current_link_up = 1;
1933 } else {
1934 current_link_up = 0;
1935 }
1936 }
1937
1938 tp->link_config.active_speed = current_speed;
1939 tp->link_config.active_duplex = current_duplex;
1940 }
1941
1942 if (current_link_up == 1 &&
1943 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1944 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1945 u32 local_adv, remote_adv;
1946
1947 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1948 local_adv = 0;
1949 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1950
1951 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1952 remote_adv = 0;
1953
1954 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1955
1956 /* If we are not advertising full pause capability,
1957 * something is wrong. Bring the link down and reconfigure.
1958 */
1959 if (local_adv != ADVERTISE_PAUSE_CAP) {
1960 current_link_up = 0;
1961 } else {
1962 tg3_setup_flow_control(tp, local_adv, remote_adv);
1963 }
1964 }
1965relink:
6921d201 1966 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1967 u32 tmp;
1968
1969 tg3_phy_copper_begin(tp);
1970
1971 tg3_readphy(tp, MII_BMSR, &tmp);
1972 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1973 (tmp & BMSR_LSTATUS))
1974 current_link_up = 1;
1975 }
1976
1977 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1978 if (current_link_up == 1) {
1979 if (tp->link_config.active_speed == SPEED_100 ||
1980 tp->link_config.active_speed == SPEED_10)
1981 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1982 else
1983 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1984 } else
1985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986
1987 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1988 if (tp->link_config.active_duplex == DUPLEX_HALF)
1989 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1990
1991 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1993 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1994 (current_link_up == 1 &&
1995 tp->link_config.active_speed == SPEED_10))
1996 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1997 } else {
1998 if (current_link_up == 1)
1999 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2000 }
2001
2002 /* ??? Without this setting Netgear GA302T PHY does not
2003 * ??? send/receive packets...
2004 */
2005 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2006 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2007 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2008 tw32_f(MAC_MI_MODE, tp->mi_mode);
2009 udelay(80);
2010 }
2011
2012 tw32_f(MAC_MODE, tp->mac_mode);
2013 udelay(40);
2014
2015 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2016 /* Polled via timer. */
2017 tw32_f(MAC_EVENT, 0);
2018 } else {
2019 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2020 }
2021 udelay(40);
2022
2023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2024 current_link_up == 1 &&
2025 tp->link_config.active_speed == SPEED_1000 &&
2026 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2027 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2028 udelay(120);
2029 tw32_f(MAC_STATUS,
2030 (MAC_STATUS_SYNC_CHANGED |
2031 MAC_STATUS_CFG_CHANGED));
2032 udelay(40);
2033 tg3_write_mem(tp,
2034 NIC_SRAM_FIRMWARE_MBOX,
2035 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2036 }
2037
2038 if (current_link_up != netif_carrier_ok(tp->dev)) {
2039 if (current_link_up)
2040 netif_carrier_on(tp->dev);
2041 else
2042 netif_carrier_off(tp->dev);
2043 tg3_link_report(tp);
2044 }
2045
2046 return 0;
2047}
2048
2049struct tg3_fiber_aneginfo {
2050 int state;
2051#define ANEG_STATE_UNKNOWN 0
2052#define ANEG_STATE_AN_ENABLE 1
2053#define ANEG_STATE_RESTART_INIT 2
2054#define ANEG_STATE_RESTART 3
2055#define ANEG_STATE_DISABLE_LINK_OK 4
2056#define ANEG_STATE_ABILITY_DETECT_INIT 5
2057#define ANEG_STATE_ABILITY_DETECT 6
2058#define ANEG_STATE_ACK_DETECT_INIT 7
2059#define ANEG_STATE_ACK_DETECT 8
2060#define ANEG_STATE_COMPLETE_ACK_INIT 9
2061#define ANEG_STATE_COMPLETE_ACK 10
2062#define ANEG_STATE_IDLE_DETECT_INIT 11
2063#define ANEG_STATE_IDLE_DETECT 12
2064#define ANEG_STATE_LINK_OK 13
2065#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2066#define ANEG_STATE_NEXT_PAGE_WAIT 15
2067
2068 u32 flags;
2069#define MR_AN_ENABLE 0x00000001
2070#define MR_RESTART_AN 0x00000002
2071#define MR_AN_COMPLETE 0x00000004
2072#define MR_PAGE_RX 0x00000008
2073#define MR_NP_LOADED 0x00000010
2074#define MR_TOGGLE_TX 0x00000020
2075#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2076#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2077#define MR_LP_ADV_SYM_PAUSE 0x00000100
2078#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2079#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2080#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2081#define MR_LP_ADV_NEXT_PAGE 0x00001000
2082#define MR_TOGGLE_RX 0x00002000
2083#define MR_NP_RX 0x00004000
2084
2085#define MR_LINK_OK 0x80000000
2086
2087 unsigned long link_time, cur_time;
2088
2089 u32 ability_match_cfg;
2090 int ability_match_count;
2091
2092 char ability_match, idle_match, ack_match;
2093
2094 u32 txconfig, rxconfig;
2095#define ANEG_CFG_NP 0x00000080
2096#define ANEG_CFG_ACK 0x00000040
2097#define ANEG_CFG_RF2 0x00000020
2098#define ANEG_CFG_RF1 0x00000010
2099#define ANEG_CFG_PS2 0x00000001
2100#define ANEG_CFG_PS1 0x00008000
2101#define ANEG_CFG_HD 0x00004000
2102#define ANEG_CFG_FD 0x00002000
2103#define ANEG_CFG_INVAL 0x00001f06
2104
2105};
2106#define ANEG_OK 0
2107#define ANEG_DONE 1
2108#define ANEG_TIMER_ENAB 2
2109#define ANEG_FAILED -1
2110
2111#define ANEG_STATE_SETTLE_TIME 10000
2112
2113static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2114 struct tg3_fiber_aneginfo *ap)
2115{
2116 unsigned long delta;
2117 u32 rx_cfg_reg;
2118 int ret;
2119
2120 if (ap->state == ANEG_STATE_UNKNOWN) {
2121 ap->rxconfig = 0;
2122 ap->link_time = 0;
2123 ap->cur_time = 0;
2124 ap->ability_match_cfg = 0;
2125 ap->ability_match_count = 0;
2126 ap->ability_match = 0;
2127 ap->idle_match = 0;
2128 ap->ack_match = 0;
2129 }
2130 ap->cur_time++;
2131
2132 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2133 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2134
2135 if (rx_cfg_reg != ap->ability_match_cfg) {
2136 ap->ability_match_cfg = rx_cfg_reg;
2137 ap->ability_match = 0;
2138 ap->ability_match_count = 0;
2139 } else {
2140 if (++ap->ability_match_count > 1) {
2141 ap->ability_match = 1;
2142 ap->ability_match_cfg = rx_cfg_reg;
2143 }
2144 }
2145 if (rx_cfg_reg & ANEG_CFG_ACK)
2146 ap->ack_match = 1;
2147 else
2148 ap->ack_match = 0;
2149
2150 ap->idle_match = 0;
2151 } else {
2152 ap->idle_match = 1;
2153 ap->ability_match_cfg = 0;
2154 ap->ability_match_count = 0;
2155 ap->ability_match = 0;
2156 ap->ack_match = 0;
2157
2158 rx_cfg_reg = 0;
2159 }
2160
2161 ap->rxconfig = rx_cfg_reg;
2162 ret = ANEG_OK;
2163
2164 switch(ap->state) {
2165 case ANEG_STATE_UNKNOWN:
2166 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2167 ap->state = ANEG_STATE_AN_ENABLE;
2168
2169 /* fallthru */
2170 case ANEG_STATE_AN_ENABLE:
2171 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2172 if (ap->flags & MR_AN_ENABLE) {
2173 ap->link_time = 0;
2174 ap->cur_time = 0;
2175 ap->ability_match_cfg = 0;
2176 ap->ability_match_count = 0;
2177 ap->ability_match = 0;
2178 ap->idle_match = 0;
2179 ap->ack_match = 0;
2180
2181 ap->state = ANEG_STATE_RESTART_INIT;
2182 } else {
2183 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2184 }
2185 break;
2186
2187 case ANEG_STATE_RESTART_INIT:
2188 ap->link_time = ap->cur_time;
2189 ap->flags &= ~(MR_NP_LOADED);
2190 ap->txconfig = 0;
2191 tw32(MAC_TX_AUTO_NEG, 0);
2192 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2193 tw32_f(MAC_MODE, tp->mac_mode);
2194 udelay(40);
2195
2196 ret = ANEG_TIMER_ENAB;
2197 ap->state = ANEG_STATE_RESTART;
2198
2199 /* fallthru */
2200 case ANEG_STATE_RESTART:
2201 delta = ap->cur_time - ap->link_time;
2202 if (delta > ANEG_STATE_SETTLE_TIME) {
2203 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2204 } else {
2205 ret = ANEG_TIMER_ENAB;
2206 }
2207 break;
2208
2209 case ANEG_STATE_DISABLE_LINK_OK:
2210 ret = ANEG_DONE;
2211 break;
2212
2213 case ANEG_STATE_ABILITY_DETECT_INIT:
2214 ap->flags &= ~(MR_TOGGLE_TX);
2215 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2216 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2217 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2218 tw32_f(MAC_MODE, tp->mac_mode);
2219 udelay(40);
2220
2221 ap->state = ANEG_STATE_ABILITY_DETECT;
2222 break;
2223
2224 case ANEG_STATE_ABILITY_DETECT:
2225 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2226 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2227 }
2228 break;
2229
2230 case ANEG_STATE_ACK_DETECT_INIT:
2231 ap->txconfig |= ANEG_CFG_ACK;
2232 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2233 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2234 tw32_f(MAC_MODE, tp->mac_mode);
2235 udelay(40);
2236
2237 ap->state = ANEG_STATE_ACK_DETECT;
2238
2239 /* fallthru */
2240 case ANEG_STATE_ACK_DETECT:
2241 if (ap->ack_match != 0) {
2242 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2243 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2244 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2245 } else {
2246 ap->state = ANEG_STATE_AN_ENABLE;
2247 }
2248 } else if (ap->ability_match != 0 &&
2249 ap->rxconfig == 0) {
2250 ap->state = ANEG_STATE_AN_ENABLE;
2251 }
2252 break;
2253
2254 case ANEG_STATE_COMPLETE_ACK_INIT:
2255 if (ap->rxconfig & ANEG_CFG_INVAL) {
2256 ret = ANEG_FAILED;
2257 break;
2258 }
2259 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2260 MR_LP_ADV_HALF_DUPLEX |
2261 MR_LP_ADV_SYM_PAUSE |
2262 MR_LP_ADV_ASYM_PAUSE |
2263 MR_LP_ADV_REMOTE_FAULT1 |
2264 MR_LP_ADV_REMOTE_FAULT2 |
2265 MR_LP_ADV_NEXT_PAGE |
2266 MR_TOGGLE_RX |
2267 MR_NP_RX);
2268 if (ap->rxconfig & ANEG_CFG_FD)
2269 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2270 if (ap->rxconfig & ANEG_CFG_HD)
2271 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2272 if (ap->rxconfig & ANEG_CFG_PS1)
2273 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2274 if (ap->rxconfig & ANEG_CFG_PS2)
2275 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2276 if (ap->rxconfig & ANEG_CFG_RF1)
2277 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2278 if (ap->rxconfig & ANEG_CFG_RF2)
2279 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2280 if (ap->rxconfig & ANEG_CFG_NP)
2281 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2282
2283 ap->link_time = ap->cur_time;
2284
2285 ap->flags ^= (MR_TOGGLE_TX);
2286 if (ap->rxconfig & 0x0008)
2287 ap->flags |= MR_TOGGLE_RX;
2288 if (ap->rxconfig & ANEG_CFG_NP)
2289 ap->flags |= MR_NP_RX;
2290 ap->flags |= MR_PAGE_RX;
2291
2292 ap->state = ANEG_STATE_COMPLETE_ACK;
2293 ret = ANEG_TIMER_ENAB;
2294 break;
2295
2296 case ANEG_STATE_COMPLETE_ACK:
2297 if (ap->ability_match != 0 &&
2298 ap->rxconfig == 0) {
2299 ap->state = ANEG_STATE_AN_ENABLE;
2300 break;
2301 }
2302 delta = ap->cur_time - ap->link_time;
2303 if (delta > ANEG_STATE_SETTLE_TIME) {
2304 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2305 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2306 } else {
2307 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2308 !(ap->flags & MR_NP_RX)) {
2309 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2310 } else {
2311 ret = ANEG_FAILED;
2312 }
2313 }
2314 }
2315 break;
2316
2317 case ANEG_STATE_IDLE_DETECT_INIT:
2318 ap->link_time = ap->cur_time;
2319 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2320 tw32_f(MAC_MODE, tp->mac_mode);
2321 udelay(40);
2322
2323 ap->state = ANEG_STATE_IDLE_DETECT;
2324 ret = ANEG_TIMER_ENAB;
2325 break;
2326
2327 case ANEG_STATE_IDLE_DETECT:
2328 if (ap->ability_match != 0 &&
2329 ap->rxconfig == 0) {
2330 ap->state = ANEG_STATE_AN_ENABLE;
2331 break;
2332 }
2333 delta = ap->cur_time - ap->link_time;
2334 if (delta > ANEG_STATE_SETTLE_TIME) {
2335 /* XXX another gem from the Broadcom driver :( */
2336 ap->state = ANEG_STATE_LINK_OK;
2337 }
2338 break;
2339
2340 case ANEG_STATE_LINK_OK:
2341 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2342 ret = ANEG_DONE;
2343 break;
2344
2345 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2346 /* ??? unimplemented */
2347 break;
2348
2349 case ANEG_STATE_NEXT_PAGE_WAIT:
2350 /* ??? unimplemented */
2351 break;
2352
2353 default:
2354 ret = ANEG_FAILED;
2355 break;
2356 };
2357
2358 return ret;
2359}
2360
2361static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2362{
2363 int res = 0;
2364 struct tg3_fiber_aneginfo aninfo;
2365 int status = ANEG_FAILED;
2366 unsigned int tick;
2367 u32 tmp;
2368
2369 tw32_f(MAC_TX_AUTO_NEG, 0);
2370
2371 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2372 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2373 udelay(40);
2374
2375 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2376 udelay(40);
2377
2378 memset(&aninfo, 0, sizeof(aninfo));
2379 aninfo.flags |= MR_AN_ENABLE;
2380 aninfo.state = ANEG_STATE_UNKNOWN;
2381 aninfo.cur_time = 0;
2382 tick = 0;
2383 while (++tick < 195000) {
2384 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2385 if (status == ANEG_DONE || status == ANEG_FAILED)
2386 break;
2387
2388 udelay(1);
2389 }
2390
2391 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2392 tw32_f(MAC_MODE, tp->mac_mode);
2393 udelay(40);
2394
2395 *flags = aninfo.flags;
2396
2397 if (status == ANEG_DONE &&
2398 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2399 MR_LP_ADV_FULL_DUPLEX)))
2400 res = 1;
2401
2402 return res;
2403}
2404
2405static void tg3_init_bcm8002(struct tg3 *tp)
2406{
2407 u32 mac_status = tr32(MAC_STATUS);
2408 int i;
2409
2410 /* Reset when initting first time or we have a link. */
2411 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2412 !(mac_status & MAC_STATUS_PCS_SYNCED))
2413 return;
2414
2415 /* Set PLL lock range. */
2416 tg3_writephy(tp, 0x16, 0x8007);
2417
2418 /* SW reset */
2419 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2420
2421 /* Wait for reset to complete. */
2422 /* XXX schedule_timeout() ... */
2423 for (i = 0; i < 500; i++)
2424 udelay(10);
2425
2426 /* Config mode; select PMA/Ch 1 regs. */
2427 tg3_writephy(tp, 0x10, 0x8411);
2428
2429 /* Enable auto-lock and comdet, select txclk for tx. */
2430 tg3_writephy(tp, 0x11, 0x0a10);
2431
2432 tg3_writephy(tp, 0x18, 0x00a0);
2433 tg3_writephy(tp, 0x16, 0x41ff);
2434
2435 /* Assert and deassert POR. */
2436 tg3_writephy(tp, 0x13, 0x0400);
2437 udelay(40);
2438 tg3_writephy(tp, 0x13, 0x0000);
2439
2440 tg3_writephy(tp, 0x11, 0x0a50);
2441 udelay(40);
2442 tg3_writephy(tp, 0x11, 0x0a10);
2443
2444 /* Wait for signal to stabilize */
2445 /* XXX schedule_timeout() ... */
2446 for (i = 0; i < 15000; i++)
2447 udelay(10);
2448
2449 /* Deselect the channel register so we can read the PHYID
2450 * later.
2451 */
2452 tg3_writephy(tp, 0x10, 0x8011);
2453}
2454
2455static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2456{
2457 u32 sg_dig_ctrl, sg_dig_status;
2458 u32 serdes_cfg, expected_sg_dig_ctrl;
2459 int workaround, port_a;
2460 int current_link_up;
2461
2462 serdes_cfg = 0;
2463 expected_sg_dig_ctrl = 0;
2464 workaround = 0;
2465 port_a = 1;
2466 current_link_up = 0;
2467
2468 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2469 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2470 workaround = 1;
2471 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2472 port_a = 0;
2473
2474 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2475 /* preserve bits 20-23 for voltage regulator */
2476 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2477 }
2478
2479 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2480
2481 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2482 if (sg_dig_ctrl & (1 << 31)) {
2483 if (workaround) {
2484 u32 val = serdes_cfg;
2485
2486 if (port_a)
2487 val |= 0xc010000;
2488 else
2489 val |= 0x4010000;
2490 tw32_f(MAC_SERDES_CFG, val);
2491 }
2492 tw32_f(SG_DIG_CTRL, 0x01388400);
2493 }
2494 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2495 tg3_setup_flow_control(tp, 0, 0);
2496 current_link_up = 1;
2497 }
2498 goto out;
2499 }
2500
2501 /* Want auto-negotiation. */
2502 expected_sg_dig_ctrl = 0x81388400;
2503
2504 /* Pause capability */
2505 expected_sg_dig_ctrl |= (1 << 11);
2506
2507 /* Asymettric pause */
2508 expected_sg_dig_ctrl |= (1 << 12);
2509
2510 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2511 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2512 tp->serdes_counter &&
2513 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2514 MAC_STATUS_RCVD_CFG)) ==
2515 MAC_STATUS_PCS_SYNCED)) {
2516 tp->serdes_counter--;
2517 current_link_up = 1;
2518 goto out;
2519 }
2520restart_autoneg:
1da177e4
LT		 2521 if (workaround)
2522 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2523 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2524 udelay(5);
2525 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2526
3d3ebe74
MC		 2527 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2528 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2529 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2530 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2531 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2532 mac_status = tr32(MAC_STATUS);
2533
2534 if ((sg_dig_status & (1 << 1)) &&
2535 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2536 u32 local_adv, remote_adv;
2537
2538 local_adv = ADVERTISE_PAUSE_CAP;
2539 remote_adv = 0;
2540 if (sg_dig_status & (1 << 19))
2541 remote_adv |= LPA_PAUSE_CAP;
2542 if (sg_dig_status & (1 << 20))
2543 remote_adv |= LPA_PAUSE_ASYM;
2544
2545 tg3_setup_flow_control(tp, local_adv, remote_adv);
2546 current_link_up = 1;
3d3ebe74
MC		 2547 tp->serdes_counter = 0;
2548 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2549 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2550 if (tp->serdes_counter)
2551 tp->serdes_counter--;
1da177e4
LT		 2552 else {
2553 if (workaround) {
2554 u32 val = serdes_cfg;
2555
2556 if (port_a)
2557 val |= 0xc010000;
2558 else
2559 val |= 0x4010000;
2560
2561 tw32_f(MAC_SERDES_CFG, val);
2562 }
2563
2564 tw32_f(SG_DIG_CTRL, 0x01388400);
2565 udelay(40);
2566
2567 /* Link parallel detection - link is up */
2568 /* only if we have PCS_SYNC and not */
2569 /* receiving config code words */
2570 mac_status = tr32(MAC_STATUS);
2571 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2572 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2573 tg3_setup_flow_control(tp, 0, 0);
2574 current_link_up = 1;
3d3ebe74
MC		 2575 tp->tg3_flags2 |=
2576 TG3_FLG2_PARALLEL_DETECT;
2577 tp->serdes_counter =
2578 SERDES_PARALLEL_DET_TIMEOUT;
2579 } else
2580 goto restart_autoneg;
1da177e4
LT		 2581 }
2582 }
3d3ebe74
MC		 2583 } else {
2584 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2585 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2586 }
2587
2588out:
2589 return current_link_up;
2590}
2591
2592static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2593{
2594 int current_link_up = 0;
2595
2596 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2597 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2598 goto out;
2599 }
2600
2601 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602 u32 flags;
2603 int i;
6aa20a22 2604
1da177e4
LT		 2605 if (fiber_autoneg(tp, &flags)) {
2606 u32 local_adv, remote_adv;
2607
2608 local_adv = ADVERTISE_PAUSE_CAP;
2609 remote_adv = 0;
2610 if (flags & MR_LP_ADV_SYM_PAUSE)
2611 remote_adv |= LPA_PAUSE_CAP;
2612 if (flags & MR_LP_ADV_ASYM_PAUSE)
2613 remote_adv |= LPA_PAUSE_ASYM;
2614
2615 tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2618 current_link_up = 1;
2619 }
2620 for (i = 0; i < 30; i++) {
2621 udelay(20);
2622 tw32_f(MAC_STATUS,
2623 (MAC_STATUS_SYNC_CHANGED |
2624 MAC_STATUS_CFG_CHANGED));
2625 udelay(40);
2626 if ((tr32(MAC_STATUS) &
2627 (MAC_STATUS_SYNC_CHANGED |
2628 MAC_STATUS_CFG_CHANGED)) == 0)
2629 break;
2630 }
2631
2632 mac_status = tr32(MAC_STATUS);
2633 if (current_link_up == 0 &&
2634 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2635 !(mac_status & MAC_STATUS_RCVD_CFG))
2636 current_link_up = 1;
2637 } else {
2638 /* Forcing 1000FD link up. */
2639 current_link_up = 1;
2640 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2641
2642 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2643 udelay(40);
2644 }
2645
2646out:
2647 return current_link_up;
2648}
2649
2650static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2651{
2652 u32 orig_pause_cfg;
2653 u16 orig_active_speed;
2654 u8 orig_active_duplex;
2655 u32 mac_status;
2656 int current_link_up;
2657 int i;
2658
2659 orig_pause_cfg =
2660 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2661 TG3_FLAG_TX_PAUSE));
2662 orig_active_speed = tp->link_config.active_speed;
2663 orig_active_duplex = tp->link_config.active_duplex;
2664
2665 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2666 netif_carrier_ok(tp->dev) &&
2667 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2668 mac_status = tr32(MAC_STATUS);
2669 mac_status &= (MAC_STATUS_PCS_SYNCED |
2670 MAC_STATUS_SIGNAL_DET |
2671 MAC_STATUS_CFG_CHANGED |
2672 MAC_STATUS_RCVD_CFG);
2673 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2674 MAC_STATUS_SIGNAL_DET)) {
2675 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2676 MAC_STATUS_CFG_CHANGED));
2677 return 0;
2678 }
2679 }
2680
2681 tw32_f(MAC_TX_AUTO_NEG, 0);
2682
2683 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2684 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2685 tw32_f(MAC_MODE, tp->mac_mode);
2686 udelay(40);
2687
2688 if (tp->phy_id == PHY_ID_BCM8002)
2689 tg3_init_bcm8002(tp);
2690
2691 /* Enable link change event even when serdes polling. */
2692 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2693 udelay(40);
2694
2695 current_link_up = 0;
2696 mac_status = tr32(MAC_STATUS);
2697
2698 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2699 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2700 else
2701 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2702
2703 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704 tw32_f(MAC_MODE, tp->mac_mode);
2705 udelay(40);
2706
2707 tp->hw_status->status =
2708 (SD_STATUS_UPDATED |
2709 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2710
2711 for (i = 0; i < 100; i++) {
2712 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2713 MAC_STATUS_CFG_CHANGED));
2714 udelay(5);
2715 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2716 MAC_STATUS_CFG_CHANGED |
2717 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2718 break;
2719 }
2720
2721 mac_status = tr32(MAC_STATUS);
2722 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2723 current_link_up = 0;
3d3ebe74
MC		 2724 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2725 tp->serdes_counter == 0) {
1da177e4
LT		 2726 tw32_f(MAC_MODE, (tp->mac_mode |
2727 MAC_MODE_SEND_CONFIGS));
2728 udelay(1);
2729 tw32_f(MAC_MODE, tp->mac_mode);
2730 }
2731 }
2732
2733 if (current_link_up == 1) {
2734 tp->link_config.active_speed = SPEED_1000;
2735 tp->link_config.active_duplex = DUPLEX_FULL;
2736 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2737 LED_CTRL_LNKLED_OVERRIDE |
2738 LED_CTRL_1000MBPS_ON));
2739 } else {
2740 tp->link_config.active_speed = SPEED_INVALID;
2741 tp->link_config.active_duplex = DUPLEX_INVALID;
2742 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2743 LED_CTRL_LNKLED_OVERRIDE |
2744 LED_CTRL_TRAFFIC_OVERRIDE));
2745 }
2746
2747 if (current_link_up != netif_carrier_ok(tp->dev)) {
2748 if (current_link_up)
2749 netif_carrier_on(tp->dev);
2750 else
2751 netif_carrier_off(tp->dev);
2752 tg3_link_report(tp);
2753 } else {
2754 u32 now_pause_cfg =
2755 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2756 TG3_FLAG_TX_PAUSE);
2757 if (orig_pause_cfg != now_pause_cfg ||
2758 orig_active_speed != tp->link_config.active_speed ||
2759 orig_active_duplex != tp->link_config.active_duplex)
2760 tg3_link_report(tp);
2761 }
2762
2763 return 0;
2764}
2765
747e8f8b
MC		 2766static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2767{
2768 int current_link_up, err = 0;
2769 u32 bmsr, bmcr;
2770 u16 current_speed;
2771 u8 current_duplex;
2772
2773 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2774 tw32_f(MAC_MODE, tp->mac_mode);
2775 udelay(40);
2776
2777 tw32(MAC_EVENT, 0);
2778
2779 tw32_f(MAC_STATUS,
2780 (MAC_STATUS_SYNC_CHANGED |
2781 MAC_STATUS_CFG_CHANGED |
2782 MAC_STATUS_MI_COMPLETION |
2783 MAC_STATUS_LNKSTATE_CHANGED));
2784 udelay(40);
2785
2786 if (force_reset)
2787 tg3_phy_reset(tp);
2788
2789 current_link_up = 0;
2790 current_speed = SPEED_INVALID;
2791 current_duplex = DUPLEX_INVALID;
2792
2793 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2794 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2796 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2797 bmsr |= BMSR_LSTATUS;
2798 else
2799 bmsr &= ~BMSR_LSTATUS;
2800 }
747e8f8b
MC		 2801
2802 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2803
2804 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2805 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2806 /* do nothing, just check for link up at the end */
2807 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2808 u32 adv, new_adv;
2809
2810 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2811 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2812 ADVERTISE_1000XPAUSE |
2813 ADVERTISE_1000XPSE_ASYM |
2814 ADVERTISE_SLCT);
2815
2816 /* Always advertise symmetric PAUSE just like copper */
2817 new_adv |= ADVERTISE_1000XPAUSE;
2818
2819 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2820 new_adv |= ADVERTISE_1000XHALF;
2821 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2822 new_adv |= ADVERTISE_1000XFULL;
2823
2824 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2825 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2826 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2827 tg3_writephy(tp, MII_BMCR, bmcr);
2828
2829 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2830 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2831 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2832
2833 return err;
2834 }
2835 } else {
2836 u32 new_bmcr;
2837
2838 bmcr &= ~BMCR_SPEED1000;
2839 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2840
2841 if (tp->link_config.duplex == DUPLEX_FULL)
2842 new_bmcr |= BMCR_FULLDPLX;
2843
2844 if (new_bmcr != bmcr) {
2845 /* BMCR_SPEED1000 is a reserved bit that needs
2846 * to be set on write.
2847 */
2848 new_bmcr |= BMCR_SPEED1000;
2849
2850 /* Force a linkdown */
2851 if (netif_carrier_ok(tp->dev)) {
2852 u32 adv;
2853
2854 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2855 adv &= ~(ADVERTISE_1000XFULL |
2856 ADVERTISE_1000XHALF |
2857 ADVERTISE_SLCT);
2858 tg3_writephy(tp, MII_ADVERTISE, adv);
2859 tg3_writephy(tp, MII_BMCR, bmcr |
2860 BMCR_ANRESTART |
2861 BMCR_ANENABLE);
2862 udelay(10);
2863 netif_carrier_off(tp->dev);
2864 }
2865 tg3_writephy(tp, MII_BMCR, new_bmcr);
2866 bmcr = new_bmcr;
2867 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2868 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2869 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2870 ASIC_REV_5714) {
2871 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2872 bmsr |= BMSR_LSTATUS;
2873 else
2874 bmsr &= ~BMSR_LSTATUS;
2875 }
747e8f8b
MC		 2876 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2877 }
2878 }
2879
2880 if (bmsr & BMSR_LSTATUS) {
2881 current_speed = SPEED_1000;
2882 current_link_up = 1;
2883 if (bmcr & BMCR_FULLDPLX)
2884 current_duplex = DUPLEX_FULL;
2885 else
2886 current_duplex = DUPLEX_HALF;
2887
2888 if (bmcr & BMCR_ANENABLE) {
2889 u32 local_adv, remote_adv, common;
2890
2891 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2892 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2893 common = local_adv & remote_adv;
2894 if (common & (ADVERTISE_1000XHALF |
2895 ADVERTISE_1000XFULL)) {
2896 if (common & ADVERTISE_1000XFULL)
2897 current_duplex = DUPLEX_FULL;
2898 else
2899 current_duplex = DUPLEX_HALF;
2900
2901 tg3_setup_flow_control(tp, local_adv,
2902 remote_adv);
2903 }
2904 else
2905 current_link_up = 0;
2906 }
2907 }
2908
2909 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2910 if (tp->link_config.active_duplex == DUPLEX_HALF)
2911 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2912
2913 tw32_f(MAC_MODE, tp->mac_mode);
2914 udelay(40);
2915
2916 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2917
2918 tp->link_config.active_speed = current_speed;
2919 tp->link_config.active_duplex = current_duplex;
2920
2921 if (current_link_up != netif_carrier_ok(tp->dev)) {
2922 if (current_link_up)
2923 netif_carrier_on(tp->dev);
2924 else {
2925 netif_carrier_off(tp->dev);
2926 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927 }
2928 tg3_link_report(tp);
2929 }
2930 return err;
2931}
2932
2933static void tg3_serdes_parallel_detect(struct tg3 *tp)
2934{
3d3ebe74 2935 if (tp->serdes_counter) {
747e8f8b 2936 /* Give autoneg time to complete. */
3d3ebe74 2937 tp->serdes_counter--;
747e8f8b
MC		 2938 return;
2939 }
2940 if (!netif_carrier_ok(tp->dev) &&
2941 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2942 u32 bmcr;
2943
2944 tg3_readphy(tp, MII_BMCR, &bmcr);
2945 if (bmcr & BMCR_ANENABLE) {
2946 u32 phy1, phy2;
2947
2948 /* Select shadow register 0x1f */
2949 tg3_writephy(tp, 0x1c, 0x7c00);
2950 tg3_readphy(tp, 0x1c, &phy1);
2951
2952 /* Select expansion interrupt status register */
2953 tg3_writephy(tp, 0x17, 0x0f01);
2954 tg3_readphy(tp, 0x15, &phy2);
2955 tg3_readphy(tp, 0x15, &phy2);
2956
2957 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2958 /* We have signal detect and not receiving
2959 * config code words, link is up by parallel
2960 * detection.
2961 */
2962
2963 bmcr &= ~BMCR_ANENABLE;
2964 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2965 tg3_writephy(tp, MII_BMCR, bmcr);
2966 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2967 }
2968 }
2969 }
2970 else if (netif_carrier_ok(tp->dev) &&
2971 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2972 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2973 u32 phy2;
2974
2975 /* Select expansion interrupt status register */
2976 tg3_writephy(tp, 0x17, 0x0f01);
2977 tg3_readphy(tp, 0x15, &phy2);
2978 if (phy2 & 0x20) {
2979 u32 bmcr;
2980
2981 /* Config code words received, turn on autoneg. */
2982 tg3_readphy(tp, MII_BMCR, &bmcr);
2983 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2984
2985 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2986
2987 }
2988 }
2989}
2990
1da177e4
LT		 2991static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2992{
2993 int err;
2994
2995 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2996 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2997 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2998 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2999 } else {
3000 err = tg3_setup_copper_phy(tp, force_reset);
3001 }
3002
3003 if (tp->link_config.active_speed == SPEED_1000 &&
3004 tp->link_config.active_duplex == DUPLEX_HALF)
3005 tw32(MAC_TX_LENGTHS,
3006 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3007 (6 << TX_LENGTHS_IPG_SHIFT) |
3008 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3009 else
3010 tw32(MAC_TX_LENGTHS,
3011 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3012 (6 << TX_LENGTHS_IPG_SHIFT) |
3013 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3014
3015 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3016 if (netif_carrier_ok(tp->dev)) {
3017 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3018 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3019 } else {
3020 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3021 }
3022 }
3023
3024 return err;
3025}
3026
df3e6548
MC		 3027/* This is called whenever we suspect that the system chipset is re-
3028 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3029 * is bogus tx completions. We try to recover by setting the
3030 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3031 * in the workqueue.
3032 */
3033static void tg3_tx_recover(struct tg3 *tp)
3034{
3035 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3036 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3037
3038 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3039 "mapped I/O cycles to the network device, attempting to "
3040 "recover. Please report the problem to the driver maintainer "
3041 "and include system chipset information.\n", tp->dev->name);
3042
3043 spin_lock(&tp->lock);
df3e6548 3044 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3045 spin_unlock(&tp->lock);
3046}
3047
1b2a7205
MC		 3048static inline u32 tg3_tx_avail(struct tg3 *tp)
3049{
3050 smp_mb();
3051 return (tp->tx_pending -
3052 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3053}
3054
1da177e4
LT		 3055/* Tigon3 never reports partial packet sends. So we do not
3056 * need special logic to handle SKBs that have not had all
3057 * of their frags sent yet, like SunGEM does.
3058 */
3059static void tg3_tx(struct tg3 *tp)
3060{
3061 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3062 u32 sw_idx = tp->tx_cons;
3063
3064 while (sw_idx != hw_idx) {
3065 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3066 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3067 int i, tx_bug = 0;
3068
3069 if (unlikely(skb == NULL)) {
3070 tg3_tx_recover(tp);
3071 return;
3072 }
1da177e4 3073
1da177e4
LT		 3074 pci_unmap_single(tp->pdev,
3075 pci_unmap_addr(ri, mapping),
3076 skb_headlen(skb),
3077 PCI_DMA_TODEVICE);
3078
3079 ri->skb = NULL;
3080
3081 sw_idx = NEXT_TX(sw_idx);
3082
3083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3084 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3085 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3086 tx_bug = 1;
1da177e4
LT		 3087
3088 pci_unmap_page(tp->pdev,
3089 pci_unmap_addr(ri, mapping),
3090 skb_shinfo(skb)->frags[i].size,
3091 PCI_DMA_TODEVICE);
3092
3093 sw_idx = NEXT_TX(sw_idx);
3094 }
3095
f47c11ee 3096 dev_kfree_skb(skb);
df3e6548
MC		 3097
3098 if (unlikely(tx_bug)) {
3099 tg3_tx_recover(tp);
3100 return;
3101 }
1da177e4
LT		 3102 }
3103
3104 tp->tx_cons = sw_idx;
3105
1b2a7205
MC		 3106 /* Need to make the tx_cons update visible to tg3_start_xmit()
3107 * before checking for netif_queue_stopped(). Without the
3108 * memory barrier, there is a small possibility that tg3_start_xmit()
3109 * will miss it and cause the queue to be stopped forever.
3110 */
3111 smp_mb();
3112
3113 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3114 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3115 netif_tx_lock(tp->dev);
51b91468 3116 if (netif_queue_stopped(tp->dev) &&
42952231 3117 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3118 netif_wake_queue(tp->dev);
1b2a7205 3119 netif_tx_unlock(tp->dev);
51b91468 3120 }
1da177e4
LT		 3121}
3122
3123/* Returns size of skb allocated or < 0 on error.
3124 *
3125 * We only need to fill in the address because the other members
3126 * of the RX descriptor are invariant, see tg3_init_rings.
3127 *
3128 * Note the purposeful assymetry of cpu vs. chip accesses. For
3129 * posting buffers we only dirty the first cache line of the RX
3130 * descriptor (containing the address). Whereas for the RX status
3131 * buffers the cpu only reads the last cacheline of the RX descriptor
3132 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3133 */
3134static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3135 int src_idx, u32 dest_idx_unmasked)
3136{
3137 struct tg3_rx_buffer_desc *desc;
3138 struct ring_info *map, *src_map;
3139 struct sk_buff *skb;
3140 dma_addr_t mapping;
3141 int skb_size, dest_idx;
3142
3143 src_map = NULL;
3144 switch (opaque_key) {
3145 case RXD_OPAQUE_RING_STD:
3146 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3147 desc = &tp->rx_std[dest_idx];
3148 map = &tp->rx_std_buffers[dest_idx];
3149 if (src_idx >= 0)
3150 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3151 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3152 break;
3153
3154 case RXD_OPAQUE_RING_JUMBO:
3155 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3156 desc = &tp->rx_jumbo[dest_idx];
3157 map = &tp->rx_jumbo_buffers[dest_idx];
3158 if (src_idx >= 0)
3159 src_map = &tp->rx_jumbo_buffers[src_idx];
3160 skb_size = RX_JUMBO_PKT_BUF_SZ;
3161 break;
3162
3163 default:
3164 return -EINVAL;
3165 };
3166
3167 /* Do not overwrite any of the map or rp information
3168 * until we are sure we can commit to a new buffer.
3169 *
3170 * Callers depend upon this behavior and assume that
3171 * we leave everything unchanged if we fail.
3172 */
a20e9c62 3173 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3174 if (skb == NULL)
3175 return -ENOMEM;
3176
1da177e4
LT		 3177 skb_reserve(skb, tp->rx_offset);
3178
3179 mapping = pci_map_single(tp->pdev, skb->data,
3180 skb_size - tp->rx_offset,
3181 PCI_DMA_FROMDEVICE);
3182
3183 map->skb = skb;
3184 pci_unmap_addr_set(map, mapping, mapping);
3185
3186 if (src_map != NULL)
3187 src_map->skb = NULL;
3188
3189 desc->addr_hi = ((u64)mapping >> 32);
3190 desc->addr_lo = ((u64)mapping & 0xffffffff);
3191
3192 return skb_size;
3193}
3194
3195/* We only need to move over in the address because the other
3196 * members of the RX descriptor are invariant. See notes above
3197 * tg3_alloc_rx_skb for full details.
3198 */
3199static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3200 int src_idx, u32 dest_idx_unmasked)
3201{
3202 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3203 struct ring_info *src_map, *dest_map;
3204 int dest_idx;
3205
3206 switch (opaque_key) {
3207 case RXD_OPAQUE_RING_STD:
3208 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3209 dest_desc = &tp->rx_std[dest_idx];
3210 dest_map = &tp->rx_std_buffers[dest_idx];
3211 src_desc = &tp->rx_std[src_idx];
3212 src_map = &tp->rx_std_buffers[src_idx];
3213 break;
3214
3215 case RXD_OPAQUE_RING_JUMBO:
3216 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3217 dest_desc = &tp->rx_jumbo[dest_idx];
3218 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3219 src_desc = &tp->rx_jumbo[src_idx];
3220 src_map = &tp->rx_jumbo_buffers[src_idx];
3221 break;
3222
3223 default:
3224 return;
3225 };
3226
3227 dest_map->skb = src_map->skb;
3228 pci_unmap_addr_set(dest_map, mapping,
3229 pci_unmap_addr(src_map, mapping));
3230 dest_desc->addr_hi = src_desc->addr_hi;
3231 dest_desc->addr_lo = src_desc->addr_lo;
3232
3233 src_map->skb = NULL;
3234}
3235
3236#if TG3_VLAN_TAG_USED
3237static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3238{
3239 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3240}
3241#endif
3242
3243/* The RX ring scheme is composed of multiple rings which post fresh
3244 * buffers to the chip, and one special ring the chip uses to report
3245 * status back to the host.
3246 *
3247 * The special ring reports the status of received packets to the
3248 * host. The chip does not write into the original descriptor the
3249 * RX buffer was obtained from. The chip simply takes the original
3250 * descriptor as provided by the host, updates the status and length
3251 * field, then writes this into the next status ring entry.
3252 *
3253 * Each ring the host uses to post buffers to the chip is described
3254 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3255 * it is first placed into the on-chip ram. When the packet's length
3256 * is known, it walks down the TG3_BDINFO entries to select the ring.
3257 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3258 * which is within the range of the new packet's length is chosen.
3259 *
3260 * The "separate ring for rx status" scheme may sound queer, but it makes
3261 * sense from a cache coherency perspective. If only the host writes
3262 * to the buffer post rings, and only the chip writes to the rx status
3263 * rings, then cache lines never move beyond shared-modified state.
3264 * If both the host and chip were to write into the same ring, cache line
3265 * eviction could occur since both entities want it in an exclusive state.
3266 */
3267static int tg3_rx(struct tg3 *tp, int budget)
3268{
f92905de 3269 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3270 u32 sw_idx = tp->rx_rcb_ptr;
3271 u16 hw_idx;
1da177e4
LT		 3272 int received;
3273
3274 hw_idx = tp->hw_status->idx[0].rx_producer;
3275 /*
3276 * We need to order the read of hw_idx and the read of
3277 * the opaque cookie.
3278 */
3279 rmb();
1da177e4
LT		 3280 work_mask = 0;
3281 received = 0;
3282 while (sw_idx != hw_idx && budget > 0) {
3283 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3284 unsigned int len;
3285 struct sk_buff *skb;
3286 dma_addr_t dma_addr;
3287 u32 opaque_key, desc_idx, *post_ptr;
3288
3289 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3290 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3291 if (opaque_key == RXD_OPAQUE_RING_STD) {
3292 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3293 mapping);
3294 skb = tp->rx_std_buffers[desc_idx].skb;
3295 post_ptr = &tp->rx_std_ptr;
f92905de 3296 rx_std_posted++;
1da177e4
LT		 3297 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3298 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3299 mapping);
3300 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3301 post_ptr = &tp->rx_jumbo_ptr;
3302 }
3303 else {
3304 goto next_pkt_nopost;
3305 }
3306
3307 work_mask |= opaque_key;
3308
3309 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3310 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3311 drop_it:
3312 tg3_recycle_rx(tp, opaque_key,
3313 desc_idx, *post_ptr);
3314 drop_it_no_recycle:
3315 /* Other statistics kept track of by card. */
3316 tp->net_stats.rx_dropped++;
3317 goto next_pkt;
3318 }
3319
3320 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3321
6aa20a22 3322 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3323 && tp->rx_offset == 2
3324 /* rx_offset != 2 iff this is a 5701 card running
3325 * in PCI-X mode [see tg3_get_invariants()] */
3326 ) {
3327 int skb_size;
3328
3329 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3330 desc_idx, *post_ptr);
3331 if (skb_size < 0)
3332 goto drop_it;
3333
3334 pci_unmap_single(tp->pdev, dma_addr,
3335 skb_size - tp->rx_offset,
3336 PCI_DMA_FROMDEVICE);
3337
3338 skb_put(skb, len);
3339 } else {
3340 struct sk_buff *copy_skb;
3341
3342 tg3_recycle_rx(tp, opaque_key,
3343 desc_idx, *post_ptr);
3344
a20e9c62 3345 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3346 if (copy_skb == NULL)
3347 goto drop_it_no_recycle;
3348
1da177e4
LT		 3349 skb_reserve(copy_skb, 2);
3350 skb_put(copy_skb, len);
3351 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3352 memcpy(copy_skb->data, skb->data, len);
3353 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3354
3355 /* We'll reuse the original ring buffer. */
3356 skb = copy_skb;
3357 }
3358
3359 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3360 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3361 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3362 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3363 skb->ip_summed = CHECKSUM_UNNECESSARY;
3364 else
3365 skb->ip_summed = CHECKSUM_NONE;
3366
3367 skb->protocol = eth_type_trans(skb, tp->dev);
3368#if TG3_VLAN_TAG_USED
3369 if (tp->vlgrp != NULL &&
3370 desc->type_flags & RXD_FLAG_VLAN) {
3371 tg3_vlan_rx(tp, skb,
3372 desc->err_vlan & RXD_VLAN_MASK);
3373 } else
3374#endif
3375 netif_receive_skb(skb);
3376
3377 tp->dev->last_rx = jiffies;
3378 received++;
3379 budget--;
3380
3381next_pkt:
3382 (*post_ptr)++;
f92905de
MC		 3383
3384 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3385 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3386
3387 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3388 TG3_64BIT_REG_LOW, idx);
3389 work_mask &= ~RXD_OPAQUE_RING_STD;
3390 rx_std_posted = 0;
3391 }
1da177e4 3392next_pkt_nopost:
483ba50b 3393 sw_idx++;
6b31a515 3394 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3395
3396 /* Refresh hw_idx to see if there is new work */
3397 if (sw_idx == hw_idx) {
3398 hw_idx = tp->hw_status->idx[0].rx_producer;
3399 rmb();
3400 }
1da177e4
LT		 3401 }
3402
3403 /* ACK the status ring. */
483ba50b
MC		 3404 tp->rx_rcb_ptr = sw_idx;
3405 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3406
3407 /* Refill RX ring(s). */
3408 if (work_mask & RXD_OPAQUE_RING_STD) {
3409 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3410 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3411 sw_idx);
3412 }
3413 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3414 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3415 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3416 sw_idx);
3417 }
3418 mmiowb();
3419
3420 return received;
3421}
3422
3423static int tg3_poll(struct net_device *netdev, int *budget)
3424{
3425 struct tg3 *tp = netdev_priv(netdev);
3426 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3427 int done;
3428
1da177e4
LT		 3429 /* handle link change and other phy events */
3430 if (!(tp->tg3_flags &
3431 (TG3_FLAG_USE_LINKCHG_REG |
3432 TG3_FLAG_POLL_SERDES))) {
3433 if (sblk->status & SD_STATUS_LINK_CHG) {
3434 sblk->status = SD_STATUS_UPDATED |
3435 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3436 spin_lock(&tp->lock);
1da177e4 3437 tg3_setup_phy(tp, 0);
f47c11ee 3438 spin_unlock(&tp->lock);
1da177e4
LT		 3439 }
3440 }
3441
3442 /* run TX completion thread */
3443 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3444 tg3_tx(tp);
df3e6548
MC		 3445 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3446 netif_rx_complete(netdev);
3447 schedule_work(&tp->reset_task);
3448 return 0;
3449 }
1da177e4
LT		 3450 }
3451
1da177e4
LT		 3452 /* run RX thread, within the bounds set by NAPI.
3453 * All RX "locking" is done by ensuring outside
3454 * code synchronizes with dev->poll()
3455 */
1da177e4
LT		 3456 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3457 int orig_budget = *budget;
3458 int work_done;
3459
3460 if (orig_budget > netdev->quota)
3461 orig_budget = netdev->quota;
3462
3463 work_done = tg3_rx(tp, orig_budget);
3464
3465 *budget -= work_done;
3466 netdev->quota -= work_done;
1da177e4
LT		 3467 }
3468
38f3843e 3469 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3470 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3471 rmb();
3472 } else
3473 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3474
1da177e4 3475 /* if no more work, tell net stack and NIC we're done */
f7383c22 3476 done = !tg3_has_work(tp);
1da177e4 3477 if (done) {
f47c11ee 3478 netif_rx_complete(netdev);
1da177e4 3479 tg3_restart_ints(tp);
1da177e4
LT		 3480 }
3481
3482 return (done ? 0 : 1);
3483}
3484
f47c11ee
DM		 3485static void tg3_irq_quiesce(struct tg3 *tp)
3486{
3487 BUG_ON(tp->irq_sync);
3488
3489 tp->irq_sync = 1;
3490 smp_mb();
3491
3492 synchronize_irq(tp->pdev->irq);
3493}
3494
3495static inline int tg3_irq_sync(struct tg3 *tp)
3496{
3497 return tp->irq_sync;
3498}
3499
3500/* Fully shutdown all tg3 driver activity elsewhere in the system.
3501 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3502 * with as well. Most of the time, this is not necessary except when
3503 * shutting down the device.
3504 */
3505static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3506{
3507 if (irq_sync)
3508 tg3_irq_quiesce(tp);
3509 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3510}
3511
3512static inline void tg3_full_unlock(struct tg3 *tp)
3513{
f47c11ee
DM		 3514 spin_unlock_bh(&tp->lock);
3515}
3516
fcfa0a32
MC		 3517/* One-shot MSI handler - Chip automatically disables interrupt
3518 * after sending MSI so driver doesn't have to do it.
3519 */
7d12e780 3520static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3521{
3522 struct net_device *dev = dev_id;
3523 struct tg3 *tp = netdev_priv(dev);
3524
3525 prefetch(tp->hw_status);
3526 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3527
3528 if (likely(!tg3_irq_sync(tp)))
3529 netif_rx_schedule(dev); /* schedule NAPI poll */
3530
3531 return IRQ_HANDLED;
3532}
3533
88b06bc2
MC		 3534/* MSI ISR - No need to check for interrupt sharing and no need to
3535 * flush status block and interrupt mailbox. PCI ordering rules
3536 * guarantee that MSI will arrive after the status block.
3537 */
7d12e780 3538static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3539{
3540 struct net_device *dev = dev_id;
3541 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3542
61487480
MC		 3543 prefetch(tp->hw_status);
3544 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3545 /*
fac9b83e 3546 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3547 * chip-internal interrupt pending events.
fac9b83e 3548 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3549 * NIC to stop sending us irqs, engaging "in-intr-handler"
3550 * event coalescing.
3551 */
3552 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3553 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3554 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3555
88b06bc2
MC		 3556 return IRQ_RETVAL(1);
3557}
3558
7d12e780 3559static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3560{
3561 struct net_device *dev = dev_id;
3562 struct tg3 *tp = netdev_priv(dev);
3563 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3564 unsigned int handled = 1;
3565
1da177e4
LT		 3566 /* In INTx mode, it is possible for the interrupt to arrive at
3567 * the CPU before the status block posted prior to the interrupt.
3568 * Reading the PCI State register will confirm whether the
3569 * interrupt is ours and will flush the status block.
3570 */
3571 if ((sblk->status & SD_STATUS_UPDATED) ||
3572 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3573 /*
fac9b83e 3574 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3575 * chip-internal interrupt pending events.
fac9b83e 3576 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3577 * NIC to stop sending us irqs, engaging "in-intr-handler"
3578 * event coalescing.
3579 */
3580 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3581 0x00000001);
f47c11ee
DM		 3582 if (tg3_irq_sync(tp))
3583 goto out;
fac9b83e 3584 sblk->status &= ~SD_STATUS_UPDATED;
61487480
MC		 3585 if (likely(tg3_has_work(tp))) {
3586 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
fac9b83e 3587 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3588 } else {
fac9b83e
DM		 3589 /* No work, shared interrupt perhaps? re-enable
3590 * interrupts, and flush that PCI write
3591 */
09ee929c 3592 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3593 0x00000000);
fac9b83e
DM		 3594 }
3595 } else { /* shared interrupt */
3596 handled = 0;
3597 }
f47c11ee 3598out:
fac9b83e
DM		 3599 return IRQ_RETVAL(handled);
3600}
3601
7d12e780 3602static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3603{
3604 struct net_device *dev = dev_id;
3605 struct tg3 *tp = netdev_priv(dev);
3606 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3607 unsigned int handled = 1;
3608
fac9b83e
DM		 3609 /* In INTx mode, it is possible for the interrupt to arrive at
3610 * the CPU before the status block posted prior to the interrupt.
3611 * Reading the PCI State register will confirm whether the
3612 * interrupt is ours and will flush the status block.
3613 */
38f3843e 3614 if ((sblk->status_tag != tp->last_tag) ||
fac9b83e 3615 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3616 /*
fac9b83e
DM		 3617 * writing any value to intr-mbox-0 clears PCI INTA# and
3618 * chip-internal interrupt pending events.
3619 * writing non-zero to intr-mbox-0 additional tells the
3620 * NIC to stop sending us irqs, engaging "in-intr-handler"
3621 * event coalescing.
1da177e4 3622 */
fac9b83e
DM		 3623 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3624 0x00000001);
f47c11ee
DM		 3625 if (tg3_irq_sync(tp))
3626 goto out;
38f3843e 3627 if (netif_rx_schedule_prep(dev)) {
61487480 3628 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
38f3843e
MC		 3629 /* Update last_tag to mark that this status has been
3630 * seen. Because interrupt may be shared, we may be
3631 * racing with tg3_poll(), so only update last_tag
3632 * if tg3_poll() is not scheduled.
1da177e4 3633 */
38f3843e
MC		 3634 tp->last_tag = sblk->status_tag;
3635 __netif_rx_schedule(dev);
1da177e4
LT		 3636 }
3637 } else { /* shared interrupt */
3638 handled = 0;
3639 }
f47c11ee 3640out:
1da177e4
LT		 3641 return IRQ_RETVAL(handled);
3642}
3643
7938109f 3644/* ISR for interrupt test */
7d12e780 3645static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3646{
3647 struct net_device *dev = dev_id;
3648 struct tg3 *tp = netdev_priv(dev);
3649 struct tg3_hw_status *sblk = tp->hw_status;
3650
f9804ddb
MC		 3651 if ((sblk->status & SD_STATUS_UPDATED) ||
3652 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3653 tg3_disable_ints(tp);
7938109f
MC		 3654 return IRQ_RETVAL(1);
3655 }
3656 return IRQ_RETVAL(0);
3657}
3658
8e7a22e3 3659static int tg3_init_hw(struct tg3 *, int);
944d980e 3660static int tg3_halt(struct tg3 *, int, int);
1da177e4 3661
b9ec6c1b
MC		 3662/* Restart hardware after configuration changes, self-test, etc.
3663 * Invoked with tp->lock held.
3664 */
3665static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3666{
3667 int err;
3668
3669 err = tg3_init_hw(tp, reset_phy);
3670 if (err) {
3671 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3672 "aborting.\n", tp->dev->name);
3673 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3674 tg3_full_unlock(tp);
3675 del_timer_sync(&tp->timer);
3676 tp->irq_sync = 0;
3677 netif_poll_enable(tp->dev);
3678 dev_close(tp->dev);
3679 tg3_full_lock(tp, 0);
3680 }
3681 return err;
3682}
3683
1da177e4
LT		 3684#ifdef CONFIG_NET_POLL_CONTROLLER
3685static void tg3_poll_controller(struct net_device *dev)
3686{
88b06bc2
MC		 3687 struct tg3 *tp = netdev_priv(dev);
3688
7d12e780 3689 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3690}
3691#endif
3692
c4028958 3693static void tg3_reset_task(struct work_struct *work)
1da177e4 3694{
c4028958 3695 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3696 unsigned int restart_timer;
3697
7faa006f
MC		 3698 tg3_full_lock(tp, 0);
3699 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3700
3701 if (!netif_running(tp->dev)) {
3702 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3703 tg3_full_unlock(tp);
3704 return;
3705 }
3706
3707 tg3_full_unlock(tp);
3708
1da177e4
LT		 3709 tg3_netif_stop(tp);
3710
f47c11ee 3711 tg3_full_lock(tp, 1);
1da177e4
LT		 3712
3713 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3714 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3715
df3e6548
MC		 3716 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3717 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3718 tp->write32_rx_mbox = tg3_write_flush_reg32;
3719 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3720 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3721 }
3722
944d980e 3723 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3724 if (tg3_init_hw(tp, 1))
3725 goto out;
1da177e4
LT		 3726
3727 tg3_netif_start(tp);
3728
1da177e4
LT		 3729 if (restart_timer)
3730 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3731
b9ec6c1b 3732out:
7faa006f
MC		 3733 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3734
3735 tg3_full_unlock(tp);
1da177e4
LT		 3736}
3737
3738static void tg3_tx_timeout(struct net_device *dev)
3739{
3740 struct tg3 *tp = netdev_priv(dev);
3741
9f88f29f
MC		 3742 if (netif_msg_tx_err(tp))
3743 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3744 dev->name);
1da177e4
LT		 3745
3746 schedule_work(&tp->reset_task);
3747}
3748
c58ec932
MC		 3749/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3750static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3751{
3752 u32 base = (u32) mapping & 0xffffffff;
3753
3754 return ((base > 0xffffdcc0) &&
3755 (base + len + 8 < base));
3756}
3757
72f2afb8
MC		 3758/* Test for DMA addresses > 40-bit */
3759static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3760 int len)
3761{
3762#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3763 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3764 return (((u64) mapping + len) > DMA_40BIT_MASK);
3765 return 0;
3766#else
3767 return 0;
3768#endif
3769}
3770
1da177e4
LT		 3771static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3772
72f2afb8
MC		 3773/* Workaround 4GB and 40-bit hardware DMA bugs. */
3774static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3775 u32 last_plus_one, u32 *start,
3776 u32 base_flags, u32 mss)
1da177e4
LT		 3777{
3778 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3779 dma_addr_t new_addr = 0;
1da177e4 3780 u32 entry = *start;
c58ec932 3781 int i, ret = 0;
1da177e4
LT		 3782
3783 if (!new_skb) {
c58ec932
MC		 3784 ret = -1;
3785 } else {
3786 /* New SKB is guaranteed to be linear. */
3787 entry = *start;
3788 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3789 PCI_DMA_TODEVICE);
3790 /* Make sure new skb does not cross any 4G boundaries.
3791 * Drop the packet if it does.
3792 */
3793 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3794 ret = -1;
3795 dev_kfree_skb(new_skb);
3796 new_skb = NULL;
3797 } else {
3798 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3799 base_flags, 1 | (mss << 1));
3800 *start = NEXT_TX(entry);
3801 }
1da177e4
LT		 3802 }
3803
1da177e4
LT		 3804 /* Now clean up the sw ring entries. */
3805 i = 0;
3806 while (entry != last_plus_one) {
3807 int len;
3808
3809 if (i == 0)
3810 len = skb_headlen(skb);
3811 else
3812 len = skb_shinfo(skb)->frags[i-1].size;
3813 pci_unmap_single(tp->pdev,
3814 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3815 len, PCI_DMA_TODEVICE);
3816 if (i == 0) {
3817 tp->tx_buffers[entry].skb = new_skb;
3818 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3819 } else {
3820 tp->tx_buffers[entry].skb = NULL;
3821 }
3822 entry = NEXT_TX(entry);
3823 i++;
3824 }
3825
3826 dev_kfree_skb(skb);
3827
c58ec932 3828 return ret;
1da177e4
LT		 3829}
3830
3831static void tg3_set_txd(struct tg3 *tp, int entry,
3832 dma_addr_t mapping, int len, u32 flags,
3833 u32 mss_and_is_end)
3834{
3835 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3836 int is_end = (mss_and_is_end & 0x1);
3837 u32 mss = (mss_and_is_end >> 1);
3838 u32 vlan_tag = 0;
3839
3840 if (is_end)
3841 flags |= TXD_FLAG_END;
3842 if (flags & TXD_FLAG_VLAN) {
3843 vlan_tag = flags >> 16;
3844 flags &= 0xffff;
3845 }
3846 vlan_tag |= (mss << TXD_MSS_SHIFT);
3847
3848 txd->addr_hi = ((u64) mapping >> 32);
3849 txd->addr_lo = ((u64) mapping & 0xffffffff);
3850 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3851 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3852}
3853
5a6f3074
MC		 3854/* hard_start_xmit for devices that don't have any bugs and
3855 * support TG3_FLG2_HW_TSO_2 only.
3856 */
1da177e4 3857static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 3858{
3859 struct tg3 *tp = netdev_priv(dev);
3860 dma_addr_t mapping;
3861 u32 len, entry, base_flags, mss;
3862
3863 len = skb_headlen(skb);
3864
00b70504
MC		 3865 /* We are running in BH disabled context with netif_tx_lock
3866 * and TX reclaim runs via tp->poll inside of a software
5a6f3074
MC		 3867 * interrupt. Furthermore, IRQ processing runs lockless so we have
3868 * no IRQ context deadlocks to worry about either. Rejoice!
3869 */
1b2a7205 3870 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 3871 if (!netif_queue_stopped(dev)) {
3872 netif_stop_queue(dev);
3873
3874 /* This is a hard error, log it. */
3875 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3876 "queue awake!\n", dev->name);
3877 }
5a6f3074
MC		 3878 return NETDEV_TX_BUSY;
3879 }
3880
3881 entry = tp->tx_prod;
3882 base_flags = 0;
5a6f3074
MC		 3883 mss = 0;
3884 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
7967168c 3885 (mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 3886 int tcp_opt_len, ip_tcp_len;
3887
3888 if (skb_header_cloned(skb) &&
3889 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3890 dev_kfree_skb(skb);
3891 goto out_unlock;
3892 }
3893
b0026624
MC		 3894 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3895 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3896 else {
3897 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3898 ip_tcp_len = (skb->nh.iph->ihl * 4) +
3899 sizeof(struct tcphdr);
3900
3901 skb->nh.iph->check = 0;
3902 skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3903 tcp_opt_len);
3904 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3905 }
5a6f3074
MC		 3906
3907 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3908 TXD_FLAG_CPU_POST_DMA);
3909
5a6f3074
MC		 3910 skb->h.th->check = 0;
3911
5a6f3074 3912 }
84fa7933 3913 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 3914 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 3915#if TG3_VLAN_TAG_USED
3916 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3917 base_flags |= (TXD_FLAG_VLAN |
3918 (vlan_tx_tag_get(skb) << 16));
3919#endif
3920
3921 /* Queue skb data, a.k.a. the main skb fragment. */
3922 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3923
3924 tp->tx_buffers[entry].skb = skb;
3925 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3926
3927 tg3_set_txd(tp, entry, mapping, len, base_flags,
3928 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3929
3930 entry = NEXT_TX(entry);
3931
3932 /* Now loop through additional data fragments, and queue them. */
3933 if (skb_shinfo(skb)->nr_frags > 0) {
3934 unsigned int i, last;
3935
3936 last = skb_shinfo(skb)->nr_frags - 1;
3937 for (i = 0; i <= last; i++) {
3938 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3939
3940 len = frag->size;
3941 mapping = pci_map_page(tp->pdev,
3942 frag->page,
3943 frag->page_offset,
3944 len, PCI_DMA_TODEVICE);
3945
3946 tp->tx_buffers[entry].skb = NULL;
3947 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3948
3949 tg3_set_txd(tp, entry, mapping, len,
3950 base_flags, (i == last) | (mss << 1));
3951
3952 entry = NEXT_TX(entry);
3953 }
3954 }
3955
3956 /* Packets are ready, update Tx producer idx local and on card. */
3957 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3958
3959 tp->tx_prod = entry;
1b2a7205 3960 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 3961 netif_stop_queue(dev);
42952231 3962 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 3963 netif_wake_queue(tp->dev);
3964 }
3965
3966out_unlock:
3967 mmiowb();
5a6f3074
MC		 3968
3969 dev->trans_start = jiffies;
3970
3971 return NETDEV_TX_OK;
3972}
3973
52c0fd83
MC		 3974static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3975
3976/* Use GSO to workaround a rare TSO bug that may be triggered when the
3977 * TSO header is greater than 80 bytes.
3978 */
3979static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3980{
3981 struct sk_buff *segs, *nskb;
3982
3983 /* Estimate the number of fragments in the worst case */
1b2a7205 3984 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83
MC		 3985 netif_stop_queue(tp->dev);
3986 return NETDEV_TX_BUSY;
3987 }
3988
3989 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3990 if (unlikely(IS_ERR(segs)))
3991 goto tg3_tso_bug_end;
3992
3993 do {
3994 nskb = segs;
3995 segs = segs->next;
3996 nskb->next = NULL;
3997 tg3_start_xmit_dma_bug(nskb, tp->dev);
3998 } while (segs);
3999
4000tg3_tso_bug_end:
4001 dev_kfree_skb(skb);
4002
4003 return NETDEV_TX_OK;
4004}
52c0fd83 4005
5a6f3074
MC		 4006/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4007 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4008 */
4009static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4010{
4011 struct tg3 *tp = netdev_priv(dev);
4012 dma_addr_t mapping;
1da177e4
LT		 4013 u32 len, entry, base_flags, mss;
4014 int would_hit_hwbug;
1da177e4
LT		 4015
4016 len = skb_headlen(skb);
4017
00b70504
MC		 4018 /* We are running in BH disabled context with netif_tx_lock
4019 * and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 4020 * interrupt. Furthermore, IRQ processing runs lockless so we have
4021 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4022 */
1b2a7205 4023 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4024 if (!netif_queue_stopped(dev)) {
4025 netif_stop_queue(dev);
4026
4027 /* This is a hard error, log it. */
4028 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4029 "queue awake!\n", dev->name);
4030 }
1da177e4
LT		 4031 return NETDEV_TX_BUSY;
4032 }
4033
4034 entry = tp->tx_prod;
4035 base_flags = 0;
84fa7933 4036 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4037 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4
LT		 4038 mss = 0;
4039 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
7967168c 4040 (mss = skb_shinfo(skb)->gso_size) != 0) {
52c0fd83 4041 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4042
4043 if (skb_header_cloned(skb) &&
4044 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4045 dev_kfree_skb(skb);
4046 goto out_unlock;
4047 }
4048
4049 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4050 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4051
52c0fd83
MC		 4052 hdr_len = ip_tcp_len + tcp_opt_len;
4053 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4054 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4055 return (tg3_tso_bug(tp, skb));
4056
1da177e4
LT		 4057 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4058 TXD_FLAG_CPU_POST_DMA);
4059
4060 skb->nh.iph->check = 0;
52c0fd83 4061 skb->nh.iph->tot_len = htons(mss + hdr_len);
1da177e4
LT		 4062 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4063 skb->h.th->check = 0;
4064 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4065 }
4066 else {
4067 skb->h.th->check =
4068 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4069 skb->nh.iph->daddr,
4070 0, IPPROTO_TCP, 0);
4071 }
4072
4073 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4074 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4075 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4076 int tsflags;
4077
4078 tsflags = ((skb->nh.iph->ihl - 5) +
4079 (tcp_opt_len >> 2));
4080 mss |= (tsflags << 11);
4081 }
4082 } else {
4083 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4084 int tsflags;
4085
4086 tsflags = ((skb->nh.iph->ihl - 5) +
4087 (tcp_opt_len >> 2));
4088 base_flags |= tsflags << 12;
4089 }
4090 }
4091 }
1da177e4
LT		 4092#if TG3_VLAN_TAG_USED
4093 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4094 base_flags |= (TXD_FLAG_VLAN |
4095 (vlan_tx_tag_get(skb) << 16));
4096#endif
4097
4098 /* Queue skb data, a.k.a. the main skb fragment. */
4099 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4100
4101 tp->tx_buffers[entry].skb = skb;
4102 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4103
4104 would_hit_hwbug = 0;
4105
4106 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4107 would_hit_hwbug = 1;
1da177e4
LT		 4108
4109 tg3_set_txd(tp, entry, mapping, len, base_flags,
4110 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4111
4112 entry = NEXT_TX(entry);
4113
4114 /* Now loop through additional data fragments, and queue them. */
4115 if (skb_shinfo(skb)->nr_frags > 0) {
4116 unsigned int i, last;
4117
4118 last = skb_shinfo(skb)->nr_frags - 1;
4119 for (i = 0; i <= last; i++) {
4120 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4121
4122 len = frag->size;
4123 mapping = pci_map_page(tp->pdev,
4124 frag->page,
4125 frag->page_offset,
4126 len, PCI_DMA_TODEVICE);
4127
4128 tp->tx_buffers[entry].skb = NULL;
4129 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4130
c58ec932
MC		 4131 if (tg3_4g_overflow_test(mapping, len))
4132 would_hit_hwbug = 1;
1da177e4 4133
72f2afb8
MC		 4134 if (tg3_40bit_overflow_test(tp, mapping, len))
4135 would_hit_hwbug = 1;
4136
1da177e4
LT		 4137 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4138 tg3_set_txd(tp, entry, mapping, len,
4139 base_flags, (i == last)|(mss << 1));
4140 else
4141 tg3_set_txd(tp, entry, mapping, len,
4142 base_flags, (i == last));
4143
4144 entry = NEXT_TX(entry);
4145 }
4146 }
4147
4148 if (would_hit_hwbug) {
4149 u32 last_plus_one = entry;
4150 u32 start;
1da177e4 4151
c58ec932
MC		 4152 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4153 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4154
4155 /* If the workaround fails due to memory/mapping
4156 * failure, silently drop this packet.
4157 */
72f2afb8 4158 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4159 &start, base_flags, mss))
1da177e4
LT		 4160 goto out_unlock;
4161
4162 entry = start;
4163 }
4164
4165 /* Packets are ready, update Tx producer idx local and on card. */
4166 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4167
4168 tp->tx_prod = entry;
1b2a7205 4169 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4170 netif_stop_queue(dev);
42952231 4171 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4172 netif_wake_queue(tp->dev);
4173 }
1da177e4
LT		 4174
4175out_unlock:
4176 mmiowb();
1da177e4
LT		 4177
4178 dev->trans_start = jiffies;
4179
4180 return NETDEV_TX_OK;
4181}
4182
4183static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4184 int new_mtu)
4185{
4186 dev->mtu = new_mtu;
4187
ef7f5ec0 4188 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4189 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4190 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4191 ethtool_op_set_tso(dev, 0);
4192 }
4193 else
4194 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4195 } else {
a4e2b347 4196 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4197 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4198 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4199 }
1da177e4
LT		 4200}
4201
4202static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4203{
4204 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4205 int err;
1da177e4
LT		 4206
4207 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4208 return -EINVAL;
4209
4210 if (!netif_running(dev)) {
4211 /* We'll just catch it later when the
4212 * device is up'd.
4213 */
4214 tg3_set_mtu(dev, tp, new_mtu);
4215 return 0;
4216 }
4217
4218 tg3_netif_stop(tp);
f47c11ee
DM		 4219
4220 tg3_full_lock(tp, 1);
1da177e4 4221
944d980e 4222 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4223
4224 tg3_set_mtu(dev, tp, new_mtu);
4225
b9ec6c1b 4226 err = tg3_restart_hw(tp, 0);
1da177e4 4227
b9ec6c1b
MC		 4228 if (!err)
4229 tg3_netif_start(tp);
1da177e4 4230
f47c11ee 4231 tg3_full_unlock(tp);
1da177e4 4232
b9ec6c1b 4233 return err;
1da177e4
LT		 4234}
4235
4236/* Free up pending packets in all rx/tx rings.
4237 *
4238 * The chip has been shut down and the driver detached from
4239 * the networking, so no interrupts or new tx packets will
4240 * end up in the driver. tp->{tx,}lock is not held and we are not
4241 * in an interrupt context and thus may sleep.
4242 */
4243static void tg3_free_rings(struct tg3 *tp)
4244{
4245 struct ring_info *rxp;
4246 int i;
4247
4248 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4249 rxp = &tp->rx_std_buffers[i];
4250
4251 if (rxp->skb == NULL)
4252 continue;
4253 pci_unmap_single(tp->pdev,
4254 pci_unmap_addr(rxp, mapping),
7e72aad4 4255 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4256 PCI_DMA_FROMDEVICE);
4257 dev_kfree_skb_any(rxp->skb);
4258 rxp->skb = NULL;
4259 }
4260
4261 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4262 rxp = &tp->rx_jumbo_buffers[i];
4263
4264 if (rxp->skb == NULL)
4265 continue;
4266 pci_unmap_single(tp->pdev,
4267 pci_unmap_addr(rxp, mapping),
4268 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4269 PCI_DMA_FROMDEVICE);
4270 dev_kfree_skb_any(rxp->skb);
4271 rxp->skb = NULL;
4272 }
4273
4274 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4275 struct tx_ring_info *txp;
4276 struct sk_buff *skb;
4277 int j;
4278
4279 txp = &tp->tx_buffers[i];
4280 skb = txp->skb;
4281
4282 if (skb == NULL) {
4283 i++;
4284 continue;
4285 }
4286
4287 pci_unmap_single(tp->pdev,
4288 pci_unmap_addr(txp, mapping),
4289 skb_headlen(skb),
4290 PCI_DMA_TODEVICE);
4291 txp->skb = NULL;
4292
4293 i++;
4294
4295 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4296 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4297 pci_unmap_page(tp->pdev,
4298 pci_unmap_addr(txp, mapping),
4299 skb_shinfo(skb)->frags[j].size,
4300 PCI_DMA_TODEVICE);
4301 i++;
4302 }
4303
4304 dev_kfree_skb_any(skb);
4305 }
4306}
4307
4308/* Initialize tx/rx rings for packet processing.
4309 *
4310 * The chip has been shut down and the driver detached from
4311 * the networking, so no interrupts or new tx packets will
4312 * end up in the driver. tp->{tx,}lock are held and thus
4313 * we may not sleep.
4314 */
32d8c572 4315static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4316{
4317 u32 i;
4318
4319 /* Free up all the SKBs. */
4320 tg3_free_rings(tp);
4321
4322 /* Zero out all descriptors. */
4323 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4324 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4325 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4326 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4327
7e72aad4 4328 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4329 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4330 (tp->dev->mtu > ETH_DATA_LEN))
4331 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4332
1da177e4
LT		 4333 /* Initialize invariants of the rings, we only set this
4334 * stuff once. This works because the card does not
4335 * write into the rx buffer posting rings.
4336 */
4337 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4338 struct tg3_rx_buffer_desc *rxd;
4339
4340 rxd = &tp->rx_std[i];
7e72aad4 4341 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4342 << RXD_LEN_SHIFT;
4343 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4344 rxd->opaque = (RXD_OPAQUE_RING_STD |
4345 (i << RXD_OPAQUE_INDEX_SHIFT));
4346 }
4347
0f893dc6 4348 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4349 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4350 struct tg3_rx_buffer_desc *rxd;
4351
4352 rxd = &tp->rx_jumbo[i];
4353 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4354 << RXD_LEN_SHIFT;
4355 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4356 RXD_FLAG_JUMBO;
4357 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4358 (i << RXD_OPAQUE_INDEX_SHIFT));
4359 }
4360 }
4361
4362 /* Now allocate fresh SKBs for each rx ring. */
4363 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4364 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4365 printk(KERN_WARNING PFX
4366 "%s: Using a smaller RX standard ring, "
4367 "only %d out of %d buffers were allocated "
4368 "successfully.\n",
4369 tp->dev->name, i, tp->rx_pending);
4370 if (i == 0)
4371 return -ENOMEM;
4372 tp->rx_pending = i;
1da177e4 4373 break;
32d8c572 4374 }
1da177e4
LT		 4375 }
4376
0f893dc6 4377 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4378 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4379 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4380 -1, i) < 0) {
4381 printk(KERN_WARNING PFX
4382 "%s: Using a smaller RX jumbo ring, "
4383 "only %d out of %d buffers were "
4384 "allocated successfully.\n",
4385 tp->dev->name, i, tp->rx_jumbo_pending);
4386 if (i == 0) {
4387 tg3_free_rings(tp);
4388 return -ENOMEM;
4389 }
4390 tp->rx_jumbo_pending = i;
1da177e4 4391 break;
32d8c572 4392 }
1da177e4
LT		 4393 }
4394 }
32d8c572 4395 return 0;
1da177e4
LT		 4396}
4397
4398/*
4399 * Must not be invoked with interrupt sources disabled and
4400 * the hardware shutdown down.
4401 */
4402static void tg3_free_consistent(struct tg3 *tp)
4403{
b4558ea9
JJ		 4404 kfree(tp->rx_std_buffers);
4405 tp->rx_std_buffers = NULL;
1da177e4
LT		 4406 if (tp->rx_std) {
4407 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4408 tp->rx_std, tp->rx_std_mapping);
4409 tp->rx_std = NULL;
4410 }
4411 if (tp->rx_jumbo) {
4412 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4413 tp->rx_jumbo, tp->rx_jumbo_mapping);
4414 tp->rx_jumbo = NULL;
4415 }
4416 if (tp->rx_rcb) {
4417 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4418 tp->rx_rcb, tp->rx_rcb_mapping);
4419 tp->rx_rcb = NULL;
4420 }
4421 if (tp->tx_ring) {
4422 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4423 tp->tx_ring, tp->tx_desc_mapping);
4424 tp->tx_ring = NULL;
4425 }
4426 if (tp->hw_status) {
4427 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4428 tp->hw_status, tp->status_mapping);
4429 tp->hw_status = NULL;
4430 }
4431 if (tp->hw_stats) {
4432 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4433 tp->hw_stats, tp->stats_mapping);
4434 tp->hw_stats = NULL;
4435 }
4436}
4437
4438/*
4439 * Must not be invoked with interrupt sources disabled and
4440 * the hardware shutdown down. Can sleep.
4441 */
4442static int tg3_alloc_consistent(struct tg3 *tp)
4443{
bd2b3343 4444 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4445 (TG3_RX_RING_SIZE +
4446 TG3_RX_JUMBO_RING_SIZE)) +
4447 (sizeof(struct tx_ring_info) *
4448 TG3_TX_RING_SIZE),
4449 GFP_KERNEL);
4450 if (!tp->rx_std_buffers)
4451 return -ENOMEM;
4452
1da177e4
LT		 4453 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4454 tp->tx_buffers = (struct tx_ring_info *)
4455 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4456
4457 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4458 &tp->rx_std_mapping);
4459 if (!tp->rx_std)
4460 goto err_out;
4461
4462 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4463 &tp->rx_jumbo_mapping);
4464
4465 if (!tp->rx_jumbo)
4466 goto err_out;
4467
4468 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4469 &tp->rx_rcb_mapping);
4470 if (!tp->rx_rcb)
4471 goto err_out;
4472
4473 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4474 &tp->tx_desc_mapping);
4475 if (!tp->tx_ring)
4476 goto err_out;
4477
4478 tp->hw_status = pci_alloc_consistent(tp->pdev,
4479 TG3_HW_STATUS_SIZE,
4480 &tp->status_mapping);
4481 if (!tp->hw_status)
4482 goto err_out;
4483
4484 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4485 sizeof(struct tg3_hw_stats),
4486 &tp->stats_mapping);
4487 if (!tp->hw_stats)
4488 goto err_out;
4489
4490 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4491 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4492
4493 return 0;
4494
4495err_out:
4496 tg3_free_consistent(tp);
4497 return -ENOMEM;
4498}
4499
4500#define MAX_WAIT_CNT 1000
4501
4502/* To stop a block, clear the enable bit and poll till it
4503 * clears. tp->lock is held.
4504 */
b3b7d6be 4505static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4506{
4507 unsigned int i;
4508 u32 val;
4509
4510 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4511 switch (ofs) {
4512 case RCVLSC_MODE:
4513 case DMAC_MODE:
4514 case MBFREE_MODE:
4515 case BUFMGR_MODE:
4516 case MEMARB_MODE:
4517 /* We can't enable/disable these bits of the
4518 * 5705/5750, just say success.
4519 */
4520 return 0;
4521
4522 default:
4523 break;
4524 };
4525 }
4526
4527 val = tr32(ofs);
4528 val &= ~enable_bit;
4529 tw32_f(ofs, val);
4530
4531 for (i = 0; i < MAX_WAIT_CNT; i++) {
4532 udelay(100);
4533 val = tr32(ofs);
4534 if ((val & enable_bit) == 0)
4535 break;
4536 }
4537
b3b7d6be 4538 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4539 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4540 "ofs=%lx enable_bit=%x\n",
4541 ofs, enable_bit);
4542 return -ENODEV;
4543 }
4544
4545 return 0;
4546}
4547
4548/* tp->lock is held. */
b3b7d6be 4549static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4550{
4551 int i, err;
4552
4553 tg3_disable_ints(tp);
4554
4555 tp->rx_mode &= ~RX_MODE_ENABLE;
4556 tw32_f(MAC_RX_MODE, tp->rx_mode);
4557 udelay(10);
4558
b3b7d6be
DM		 4559 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4560 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4561 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4562 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4563 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4564 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4565
4566 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4567 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4568 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4569 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4570 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4571 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4572 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4573
4574 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4575 tw32_f(MAC_MODE, tp->mac_mode);
4576 udelay(40);
4577
4578 tp->tx_mode &= ~TX_MODE_ENABLE;
4579 tw32_f(MAC_TX_MODE, tp->tx_mode);
4580
4581 for (i = 0; i < MAX_WAIT_CNT; i++) {
4582 udelay(100);
4583 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4584 break;
4585 }
4586 if (i >= MAX_WAIT_CNT) {
4587 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4588 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4589 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4590 err |= -ENODEV;
1da177e4
LT		 4591 }
4592
e6de8ad1 4593 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4594 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4595 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4596
4597 tw32(FTQ_RESET, 0xffffffff);
4598 tw32(FTQ_RESET, 0x00000000);
4599
b3b7d6be
DM		 4600 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4601 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4602
4603 if (tp->hw_status)
4604 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4605 if (tp->hw_stats)
4606 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4607
1da177e4
LT		 4608 return err;
4609}
4610
4611/* tp->lock is held. */
4612static int tg3_nvram_lock(struct tg3 *tp)
4613{
4614 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4615 int i;
4616
ec41c7df
MC		 4617 if (tp->nvram_lock_cnt == 0) {
4618 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4619 for (i = 0; i < 8000; i++) {
4620 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4621 break;
4622 udelay(20);
4623 }
4624 if (i == 8000) {
4625 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4626 return -ENODEV;
4627 }
1da177e4 4628 }
ec41c7df 4629 tp->nvram_lock_cnt++;
1da177e4
LT		 4630 }
4631 return 0;
4632}
4633
4634/* tp->lock is held. */
4635static void tg3_nvram_unlock(struct tg3 *tp)
4636{
ec41c7df
MC		 4637 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4638 if (tp->nvram_lock_cnt > 0)
4639 tp->nvram_lock_cnt--;
4640 if (tp->nvram_lock_cnt == 0)
4641 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4642 }
1da177e4
LT		 4643}
4644
e6af301b
MC		 4645/* tp->lock is held. */
4646static void tg3_enable_nvram_access(struct tg3 *tp)
4647{
4648 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4649 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4650 u32 nvaccess = tr32(NVRAM_ACCESS);
4651
4652 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4653 }
4654}
4655
4656/* tp->lock is held. */
4657static void tg3_disable_nvram_access(struct tg3 *tp)
4658{
4659 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4660 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4661 u32 nvaccess = tr32(NVRAM_ACCESS);
4662
4663 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4664 }
4665}
4666
1da177e4
LT		 4667/* tp->lock is held. */
4668static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4669{
f49639e6
DM		 4670 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4671 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4672
4673 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4674 switch (kind) {
4675 case RESET_KIND_INIT:
4676 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4677 DRV_STATE_START);
4678 break;
4679
4680 case RESET_KIND_SHUTDOWN:
4681 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4682 DRV_STATE_UNLOAD);
4683 break;
4684
4685 case RESET_KIND_SUSPEND:
4686 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4687 DRV_STATE_SUSPEND);
4688 break;
4689
4690 default:
4691 break;
4692 };
4693 }
4694}
4695
4696/* tp->lock is held. */
4697static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4698{
4699 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4700 switch (kind) {
4701 case RESET_KIND_INIT:
4702 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4703 DRV_STATE_START_DONE);
4704 break;
4705
4706 case RESET_KIND_SHUTDOWN:
4707 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4708 DRV_STATE_UNLOAD_DONE);
4709 break;
4710
4711 default:
4712 break;
4713 };
4714 }
4715}
4716
4717/* tp->lock is held. */
4718static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4719{
4720 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4721 switch (kind) {
4722 case RESET_KIND_INIT:
4723 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4724 DRV_STATE_START);
4725 break;
4726
4727 case RESET_KIND_SHUTDOWN:
4728 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4729 DRV_STATE_UNLOAD);
4730 break;
4731
4732 case RESET_KIND_SUSPEND:
4733 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4734 DRV_STATE_SUSPEND);
4735 break;
4736
4737 default:
4738 break;
4739 };
4740 }
4741}
4742
7a6f4369
MC		 4743static int tg3_poll_fw(struct tg3 *tp)
4744{
4745 int i;
4746 u32 val;
4747
b5d3772c 4748 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 4749 /* Wait up to 20ms for init done. */
4750 for (i = 0; i < 200; i++) {
b5d3772c
MC		 4751 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4752 return 0;
0ccead18 4753 udelay(100);
b5d3772c
MC		 4754 }
4755 return -ENODEV;
4756 }
4757
7a6f4369
MC		 4758 /* Wait for firmware initialization to complete. */
4759 for (i = 0; i < 100000; i++) {
4760 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4761 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4762 break;
4763 udelay(10);
4764 }
4765
4766 /* Chip might not be fitted with firmware. Some Sun onboard
4767 * parts are configured like that. So don't signal the timeout
4768 * of the above loop as an error, but do report the lack of
4769 * running firmware once.
4770 */
4771 if (i >= 100000 &&
4772 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4773 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4774
4775 printk(KERN_INFO PFX "%s: No firmware running.\n",
4776 tp->dev->name);
4777 }
4778
4779 return 0;
4780}
4781
1da177e4
LT		 4782static void tg3_stop_fw(struct tg3 *);
4783
4784/* tp->lock is held. */
4785static int tg3_chip_reset(struct tg3 *tp)
4786{
4787 u32 val;
1ee582d8 4788 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 4789 int err;
1da177e4 4790
f49639e6
DM		 4791 tg3_nvram_lock(tp);
4792
4793 /* No matching tg3_nvram_unlock() after this because
4794 * chip reset below will undo the nvram lock.
4795 */
4796 tp->nvram_lock_cnt = 0;
1da177e4 4797
d9ab5ad1 4798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 4799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1
MC		 4800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4801 tw32(GRC_FASTBOOT_PC, 0);
4802
1da177e4
LT		 4803 /*
4804 * We must avoid the readl() that normally takes place.
4805 * It locks machines, causes machine checks, and other
4806 * fun things. So, temporarily disable the 5701
4807 * hardware workaround, while we do the reset.
4808 */
1ee582d8
MC		 4809 write_op = tp->write32;
4810 if (write_op == tg3_write_flush_reg32)
4811 tp->write32 = tg3_write32;
1da177e4
LT		 4812
4813 /* do the reset */
4814 val = GRC_MISC_CFG_CORECLK_RESET;
4815
4816 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4817 if (tr32(0x7e2c) == 0x60) {
4818 tw32(0x7e2c, 0x20);
4819 }
4820 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4821 tw32(GRC_MISC_CFG, (1 << 29));
4822 val |= (1 << 29);
4823 }
4824 }
4825
b5d3772c
MC		 4826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4827 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4828 tw32(GRC_VCPU_EXT_CTRL,
4829 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4830 }
4831
1da177e4
LT		 4832 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4833 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4834 tw32(GRC_MISC_CFG, val);
4835
1ee582d8
MC		 4836 /* restore 5701 hardware bug workaround write method */
4837 tp->write32 = write_op;
1da177e4
LT		 4838
4839 /* Unfortunately, we have to delay before the PCI read back.
4840 * Some 575X chips even will not respond to a PCI cfg access
4841 * when the reset command is given to the chip.
4842 *
4843 * How do these hardware designers expect things to work
4844 * properly if the PCI write is posted for a long period
4845 * of time? It is always necessary to have some method by
4846 * which a register read back can occur to push the write
4847 * out which does the reset.
4848 *
4849 * For most tg3 variants the trick below was working.
4850 * Ho hum...
4851 */
4852 udelay(120);
4853
4854 /* Flush PCI posted writes. The normal MMIO registers
4855 * are inaccessible at this time so this is the only
4856 * way to make this reliably (actually, this is no longer
4857 * the case, see above). I tried to use indirect
4858 * register read/write but this upset some 5701 variants.
4859 */
4860 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4861
4862 udelay(120);
4863
4864 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4865 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4866 int i;
4867 u32 cfg_val;
4868
4869 /* Wait for link training to complete. */
4870 for (i = 0; i < 5000; i++)
4871 udelay(100);
4872
4873 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4874 pci_write_config_dword(tp->pdev, 0xc4,
4875 cfg_val | (1 << 15));
4876 }
4877 /* Set PCIE max payload size and clear error status. */
4878 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4879 }
4880
4881 /* Re-enable indirect register accesses. */
4882 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4883 tp->misc_host_ctrl);
4884
4885 /* Set MAX PCI retry to zero. */
4886 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4887 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4888 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4889 val |= PCISTATE_RETRY_SAME_DMA;
4890 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4891
4892 pci_restore_state(tp->pdev);
4893
4894 /* Make sure PCI-X relaxed ordering bit is clear. */
4895 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4896 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4897 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4898
a4e2b347 4899 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4900 u32 val;
4901
4902 /* Chip reset on 5780 will reset MSI enable bit,
4903 * so need to restore it.
4904 */
4905 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4906 u16 ctrl;
4907
4908 pci_read_config_word(tp->pdev,
4909 tp->msi_cap + PCI_MSI_FLAGS,
4910 &ctrl);
4911 pci_write_config_word(tp->pdev,
4912 tp->msi_cap + PCI_MSI_FLAGS,
4913 ctrl | PCI_MSI_FLAGS_ENABLE);
4914 val = tr32(MSGINT_MODE);
4915 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4916 }
4917
4918 val = tr32(MEMARB_MODE);
4919 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4920
4921 } else
4922 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4923
4924 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4925 tg3_stop_fw(tp);
4926 tw32(0x5000, 0x400);
4927 }
4928
4929 tw32(GRC_MODE, tp->grc_mode);
4930
4931 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4932 u32 val = tr32(0xc4);
4933
4934 tw32(0xc4, val | (1 << 15));
4935 }
4936
4937 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4939 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4940 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4941 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4942 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4943 }
4944
4945 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4946 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4947 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4948 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4949 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4950 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4951 } else
4952 tw32_f(MAC_MODE, 0);
4953 udelay(40);
4954
7a6f4369
MC		 4955 err = tg3_poll_fw(tp);
4956 if (err)
4957 return err;
1da177e4
LT		 4958
4959 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4960 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4961 u32 val = tr32(0x7c00);
4962
4963 tw32(0x7c00, val | (1 << 25));
4964 }
4965
4966 /* Reprobe ASF enable state. */
4967 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4968 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4969 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4970 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4971 u32 nic_cfg;
4972
4973 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4974 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4975 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4976 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4977 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4978 }
4979 }
4980
4981 return 0;
4982}
4983
4984/* tp->lock is held. */
4985static void tg3_stop_fw(struct tg3 *tp)
4986{
4987 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4988 u32 val;
4989 int i;
4990
4991 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4992 val = tr32(GRC_RX_CPU_EVENT);
4993 val |= (1 << 14);
4994 tw32(GRC_RX_CPU_EVENT, val);
4995
4996 /* Wait for RX cpu to ACK the event. */
4997 for (i = 0; i < 100; i++) {
4998 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4999 break;
5000 udelay(1);
5001 }
5002 }
5003}
5004
5005/* tp->lock is held. */
944d980e 5006static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 5007{
5008 int err;
5009
5010 tg3_stop_fw(tp);
5011
944d980e 5012 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5013
b3b7d6be 5014 tg3_abort_hw(tp, silent);
1da177e4
LT		 5015 err = tg3_chip_reset(tp);
5016
944d980e
MC		 5017 tg3_write_sig_legacy(tp, kind);
5018 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5019
5020 if (err)
5021 return err;
5022
5023 return 0;
5024}
5025
5026#define TG3_FW_RELEASE_MAJOR 0x0
5027#define TG3_FW_RELASE_MINOR 0x0
5028#define TG3_FW_RELEASE_FIX 0x0
5029#define TG3_FW_START_ADDR 0x08000000
5030#define TG3_FW_TEXT_ADDR 0x08000000
5031#define TG3_FW_TEXT_LEN 0x9c0
5032#define TG3_FW_RODATA_ADDR 0x080009c0
5033#define TG3_FW_RODATA_LEN 0x60
5034#define TG3_FW_DATA_ADDR 0x08000a40
5035#define TG3_FW_DATA_LEN 0x20
5036#define TG3_FW_SBSS_ADDR 0x08000a60
5037#define TG3_FW_SBSS_LEN 0xc
5038#define TG3_FW_BSS_ADDR 0x08000a70
5039#define TG3_FW_BSS_LEN 0x10
5040
50da859d 5041static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5042 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5043 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5044 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5045 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5046 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5047 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5048 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5049 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5050 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5051 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5052 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5053 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5054 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5055 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5056 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5057 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5058 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5059 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5060 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5061 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5062 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5063 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5064 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5065 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5066 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5067 0, 0, 0, 0, 0, 0,
5068 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5069 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5070 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5071 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5072 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5073 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5074 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5075 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5076 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5077 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5078 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5079 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5080 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5081 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5082 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5083 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5084 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5085 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5086 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5087 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5088 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5089 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5090 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5091 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5092 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5093 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5094 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5095 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5096 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5097 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5098 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5099 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5100 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5101 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5102 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5103 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5104 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5105 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5106 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5107 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5108 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5109 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5110 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5111 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5112 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5113 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5114 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5115 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5116 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5117 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5118 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5119 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5120 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5121 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5122 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5123 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5124 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5125 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5126 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5127 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5128 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5129 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5130 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5131 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5132 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5133};
5134
50da859d 5135static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5136 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5137 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5138 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5139 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5140 0x00000000
5141};
5142
5143#if 0 /* All zeros, don't eat up space with it. */
5144u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5145 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5146 0x00000000, 0x00000000, 0x00000000, 0x00000000
5147};
5148#endif
5149
5150#define RX_CPU_SCRATCH_BASE 0x30000
5151#define RX_CPU_SCRATCH_SIZE 0x04000
5152#define TX_CPU_SCRATCH_BASE 0x34000
5153#define TX_CPU_SCRATCH_SIZE 0x04000
5154
5155/* tp->lock is held. */
5156static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5157{
5158 int i;
5159
5d9428de
ES		 5160 BUG_ON(offset == TX_CPU_BASE &&
5161 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5162
b5d3772c
MC		 5163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5164 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5165
5166 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5167 return 0;
5168 }
1da177e4
LT		 5169 if (offset == RX_CPU_BASE) {
5170 for (i = 0; i < 10000; i++) {
5171 tw32(offset + CPU_STATE, 0xffffffff);
5172 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5173 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5174 break;
5175 }
5176
5177 tw32(offset + CPU_STATE, 0xffffffff);
5178 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5179 udelay(10);
5180 } else {
5181 for (i = 0; i < 10000; i++) {
5182 tw32(offset + CPU_STATE, 0xffffffff);
5183 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5184 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5185 break;
5186 }
5187 }
5188
5189 if (i >= 10000) {
5190 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5191 "and %s CPU\n",
5192 tp->dev->name,
5193 (offset == RX_CPU_BASE ? "RX" : "TX"));
5194 return -ENODEV;
5195 }
ec41c7df
MC		 5196
5197 /* Clear firmware's nvram arbitration. */
5198 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5199 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5200 return 0;
5201}
5202
5203struct fw_info {
5204 unsigned int text_base;
5205 unsigned int text_len;
50da859d 5206 const u32 *text_data;
1da177e4
LT		 5207 unsigned int rodata_base;
5208 unsigned int rodata_len;
50da859d 5209 const u32 *rodata_data;
1da177e4
LT		 5210 unsigned int data_base;
5211 unsigned int data_len;
50da859d 5212 const u32 *data_data;
1da177e4
LT		 5213};
5214
5215/* tp->lock is held. */
5216static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5217 int cpu_scratch_size, struct fw_info *info)
5218{
ec41c7df 5219 int err, lock_err, i;
1da177e4
LT		 5220 void (*write_op)(struct tg3 *, u32, u32);
5221
5222 if (cpu_base == TX_CPU_BASE &&
5223 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5224 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5225 "TX cpu firmware on %s which is 5705.\n",
5226 tp->dev->name);
5227 return -EINVAL;
5228 }
5229
5230 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5231 write_op = tg3_write_mem;
5232 else
5233 write_op = tg3_write_indirect_reg32;
5234
1b628151
MC		 5235 /* It is possible that bootcode is still loading at this point.
5236 * Get the nvram lock first before halting the cpu.
5237 */
ec41c7df 5238 lock_err = tg3_nvram_lock(tp);
1da177e4 5239 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5240 if (!lock_err)
5241 tg3_nvram_unlock(tp);
1da177e4
LT		 5242 if (err)
5243 goto out;
5244
5245 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5246 write_op(tp, cpu_scratch_base + i, 0);
5247 tw32(cpu_base + CPU_STATE, 0xffffffff);
5248 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5249 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5250 write_op(tp, (cpu_scratch_base +
5251 (info->text_base & 0xffff) +
5252 (i * sizeof(u32))),
5253 (info->text_data ?
5254 info->text_data[i] : 0));
5255 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5256 write_op(tp, (cpu_scratch_base +
5257 (info->rodata_base & 0xffff) +
5258 (i * sizeof(u32))),
5259 (info->rodata_data ?
5260 info->rodata_data[i] : 0));
5261 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5262 write_op(tp, (cpu_scratch_base +
5263 (info->data_base & 0xffff) +
5264 (i * sizeof(u32))),
5265 (info->data_data ?
5266 info->data_data[i] : 0));
5267
5268 err = 0;
5269
5270out:
1da177e4
LT		 5271 return err;
5272}
5273
5274/* tp->lock is held. */
5275static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5276{
5277 struct fw_info info;
5278 int err, i;
5279
5280 info.text_base = TG3_FW_TEXT_ADDR;
5281 info.text_len = TG3_FW_TEXT_LEN;
5282 info.text_data = &tg3FwText[0];
5283 info.rodata_base = TG3_FW_RODATA_ADDR;
5284 info.rodata_len = TG3_FW_RODATA_LEN;
5285 info.rodata_data = &tg3FwRodata[0];
5286 info.data_base = TG3_FW_DATA_ADDR;
5287 info.data_len = TG3_FW_DATA_LEN;
5288 info.data_data = NULL;
5289
5290 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5291 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5292 &info);
5293 if (err)
5294 return err;
5295
5296 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5297 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5298 &info);
5299 if (err)
5300 return err;
5301
5302 /* Now startup only the RX cpu. */
5303 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5304 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5305
5306 for (i = 0; i < 5; i++) {
5307 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5308 break;
5309 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5310 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5311 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5312 udelay(1000);
5313 }
5314 if (i >= 5) {
5315 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5316 "to set RX CPU PC, is %08x should be %08x\n",
5317 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5318 TG3_FW_TEXT_ADDR);
5319 return -ENODEV;
5320 }
5321 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5322 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5323
5324 return 0;
5325}
5326
1da177e4
LT		 5327
5328#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5329#define TG3_TSO_FW_RELASE_MINOR 0x6
5330#define TG3_TSO_FW_RELEASE_FIX 0x0
5331#define TG3_TSO_FW_START_ADDR 0x08000000
5332#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5333#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5334#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5335#define TG3_TSO_FW_RODATA_LEN 0x60
5336#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5337#define TG3_TSO_FW_DATA_LEN 0x30
5338#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5339#define TG3_TSO_FW_SBSS_LEN 0x2c
5340#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5341#define TG3_TSO_FW_BSS_LEN 0x894
5342
50da859d 5343static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5344 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5345 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5346 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5347 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5348 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5349 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5350 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5351 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5352 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5353 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5354 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5355 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5356 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5357 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5358 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5359 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5360 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5361 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5362 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5363 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5364 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5365 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5366 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5367 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5368 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5369 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5370 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5371 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5372 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5373 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5374 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5375 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5376 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5377 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5378 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5379 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5380 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5381 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5382 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5383 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5384 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5385 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5386 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5387 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5388 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5389 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5390 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5391 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5392 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5393 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5394 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5395 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5396 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5397 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5398 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5399 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5400 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5401 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5402 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5403 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5404 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5405 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5406 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5407 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5408 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5409 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5410 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5411 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5412 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5413 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5414 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5415 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5416 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5417 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5418 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5419 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5420 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5421 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5422 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5423 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5424 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5425 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5426 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5427 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5428 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5429 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5430 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5431 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5432 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5433 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5434 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5435 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5436 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5437 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5438 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5439 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5440 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5441 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5442 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5443 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5444 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5445 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5446 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5447 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5448 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5449 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5450 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5451 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5452 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5453 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5454 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5455 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5456 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5457 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5458 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5459 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5460 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5461 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5462 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5463 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5464 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5465 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5466 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5467 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5468 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5469 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5470 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5471 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5472 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5473 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5474 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5475 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5476 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5477 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5478 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5479 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5480 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5481 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5482 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5483 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5484 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5485 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5486 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5487 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5488 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5489 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5490 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5491 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5492 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5493 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5494 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5495 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5496 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5497 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5498 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5499 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5500 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5501 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5502 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5503 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5504 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5505 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5506 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5507 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5508 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5509 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5510 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5511 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5512 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5513 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5514 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5515 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5516 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5517 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5518 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5519 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5520 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5521 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5522 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5523 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5524 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5525 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5526 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5527 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5528 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5529 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5530 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5531 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5532 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5533 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5534 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5535 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5536 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5537 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5538 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5539 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5540 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5541 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5542 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5543 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5544 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5545 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5546 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5547 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5548 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5549 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5550 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5551 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5552 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5553 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5554 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5555 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5556 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5557 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5558 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5559 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5560 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5561 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5562 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5563 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5564 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5565 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5566 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5567 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5568 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5569 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5570 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5571 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5572 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5573 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5574 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5575 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5576 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5577 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5578 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5579 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5580 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5581 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5582 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5583 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5584 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5585 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5586 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5587 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5588 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5589 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5590 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5591 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5592 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5593 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5594 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5595 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5596 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5597 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5598 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5599 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5600 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5601 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5602 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5603 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5604 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5605 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5606 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5607 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5608 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5609 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5610 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5611 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5612 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5613 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5614 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5615 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5616 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5617 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5618 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5619 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5620 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5621 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5622 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5623 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5624 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5625 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5626 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5627 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5628};
5629
50da859d 5630static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5631 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5632 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5633 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5634 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5635 0x00000000,
5636};
5637
50da859d 5638static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5639 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5640 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5641 0x00000000,
5642};
5643
5644/* 5705 needs a special version of the TSO firmware. */
5645#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5646#define TG3_TSO5_FW_RELASE_MINOR 0x2
5647#define TG3_TSO5_FW_RELEASE_FIX 0x0
5648#define TG3_TSO5_FW_START_ADDR 0x00010000
5649#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5650#define TG3_TSO5_FW_TEXT_LEN 0xe90
5651#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5652#define TG3_TSO5_FW_RODATA_LEN 0x50
5653#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5654#define TG3_TSO5_FW_DATA_LEN 0x20
5655#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5656#define TG3_TSO5_FW_SBSS_LEN 0x28
5657#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5658#define TG3_TSO5_FW_BSS_LEN 0x88
5659
50da859d 5660static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5661 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5662 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5663 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5664 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5665 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5666 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5667 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5668 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5669 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5670 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5671 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5672 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5673 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5674 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5675 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5676 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5677 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5678 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5679 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5680 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5681 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5682 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5683 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5684 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5685 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5686 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5687 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5688 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5689 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5690 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5691 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5692 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5693 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5694 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5695 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5696 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5697 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5698 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5699 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5700 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5701 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5702 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5703 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5704 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5705 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5706 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5707 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5708 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5709 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5710 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5711 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5712 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5713 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5714 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5715 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5716 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5717 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5718 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5719 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5720 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5721 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5722 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5723 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5724 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5725 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5726 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5727 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5728 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5729 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5730 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5731 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5732 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5733 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5734 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5735 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5736 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5737 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5738 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5739 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5740 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5741 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5742 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5743 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5744 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5745 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5746 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5747 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5748 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5749 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5750 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5751 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5752 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5753 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5754 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5755 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5756 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5757 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5758 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5759 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5760 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5761 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5762 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5763 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5764 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5765 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5766 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5767 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5768 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5769 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5770 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5771 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5772 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5773 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5774 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5775 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5776 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5777 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5778 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5779 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5780 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5781 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5782 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5783 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5784 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5785 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5786 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5787 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5788 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5789 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5790 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5791 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5792 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5793 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5794 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5795 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5796 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5797 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5798 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5799 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5800 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5801 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5802 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5803 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5804 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5805 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5806 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5807 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5808 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5809 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5810 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5811 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5812 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5813 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5814 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5815 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5816 0x00000000, 0x00000000, 0x00000000,
5817};
5818
50da859d 5819static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 5820 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5821 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5822 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5823 0x00000000, 0x00000000, 0x00000000,
5824};
5825
50da859d 5826static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 5827 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5828 0x00000000, 0x00000000, 0x00000000,
5829};
5830
5831/* tp->lock is held. */
5832static int tg3_load_tso_firmware(struct tg3 *tp)
5833{
5834 struct fw_info info;
5835 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5836 int err, i;
5837
5838 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5839 return 0;
5840
5841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5842 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5843 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5844 info.text_data = &tg3Tso5FwText[0];
5845 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5846 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5847 info.rodata_data = &tg3Tso5FwRodata[0];
5848 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5849 info.data_len = TG3_TSO5_FW_DATA_LEN;
5850 info.data_data = &tg3Tso5FwData[0];
5851 cpu_base = RX_CPU_BASE;
5852 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5853 cpu_scratch_size = (info.text_len +
5854 info.rodata_len +
5855 info.data_len +
5856 TG3_TSO5_FW_SBSS_LEN +
5857 TG3_TSO5_FW_BSS_LEN);
5858 } else {
5859 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5860 info.text_len = TG3_TSO_FW_TEXT_LEN;
5861 info.text_data = &tg3TsoFwText[0];
5862 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5863 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5864 info.rodata_data = &tg3TsoFwRodata[0];
5865 info.data_base = TG3_TSO_FW_DATA_ADDR;
5866 info.data_len = TG3_TSO_FW_DATA_LEN;
5867 info.data_data = &tg3TsoFwData[0];
5868 cpu_base = TX_CPU_BASE;
5869 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5870 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5871 }
5872
5873 err = tg3_load_firmware_cpu(tp, cpu_base,
5874 cpu_scratch_base, cpu_scratch_size,
5875 &info);
5876 if (err)
5877 return err;
5878
5879 /* Now startup the cpu. */
5880 tw32(cpu_base + CPU_STATE, 0xffffffff);
5881 tw32_f(cpu_base + CPU_PC, info.text_base);
5882
5883 for (i = 0; i < 5; i++) {
5884 if (tr32(cpu_base + CPU_PC) == info.text_base)
5885 break;
5886 tw32(cpu_base + CPU_STATE, 0xffffffff);
5887 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5888 tw32_f(cpu_base + CPU_PC, info.text_base);
5889 udelay(1000);
5890 }
5891 if (i >= 5) {
5892 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5893 "to set CPU PC, is %08x should be %08x\n",
5894 tp->dev->name, tr32(cpu_base + CPU_PC),
5895 info.text_base);
5896 return -ENODEV;
5897 }
5898 tw32(cpu_base + CPU_STATE, 0xffffffff);
5899 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5900 return 0;
5901}
5902
1da177e4
LT		 5903
5904/* tp->lock is held. */
5905static void __tg3_set_mac_addr(struct tg3 *tp)
5906{
5907 u32 addr_high, addr_low;
5908 int i;
5909
5910 addr_high = ((tp->dev->dev_addr[0] << 8) |
5911 tp->dev->dev_addr[1]);
5912 addr_low = ((tp->dev->dev_addr[2] << 24) |
5913 (tp->dev->dev_addr[3] << 16) |
5914 (tp->dev->dev_addr[4] << 8) |
5915 (tp->dev->dev_addr[5] << 0));
5916 for (i = 0; i < 4; i++) {
5917 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5918 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5919 }
5920
5921 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5923 for (i = 0; i < 12; i++) {
5924 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5925 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5926 }
5927 }
5928
5929 addr_high = (tp->dev->dev_addr[0] +
5930 tp->dev->dev_addr[1] +
5931 tp->dev->dev_addr[2] +
5932 tp->dev->dev_addr[3] +
5933 tp->dev->dev_addr[4] +
5934 tp->dev->dev_addr[5]) &
5935 TX_BACKOFF_SEED_MASK;
5936 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5937}
5938
5939static int tg3_set_mac_addr(struct net_device *dev, void *p)
5940{
5941 struct tg3 *tp = netdev_priv(dev);
5942 struct sockaddr *addr = p;
b9ec6c1b 5943 int err = 0;
1da177e4 5944
f9804ddb
MC		 5945 if (!is_valid_ether_addr(addr->sa_data))
5946 return -EINVAL;
5947
1da177e4
LT		 5948 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5949
e75f7c90
MC		 5950 if (!netif_running(dev))
5951 return 0;
5952
58712ef9
MC		 5953 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5954 /* Reset chip so that ASF can re-init any MAC addresses it
5955 * needs.
5956 */
5957 tg3_netif_stop(tp);
5958 tg3_full_lock(tp, 1);
5959
5960 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 5961 err = tg3_restart_hw(tp, 0);
5962 if (!err)
5963 tg3_netif_start(tp);
58712ef9
MC		 5964 tg3_full_unlock(tp);
5965 } else {
5966 spin_lock_bh(&tp->lock);
5967 __tg3_set_mac_addr(tp);
5968 spin_unlock_bh(&tp->lock);
5969 }
1da177e4 5970
b9ec6c1b 5971 return err;
1da177e4
LT		 5972}
5973
5974/* tp->lock is held. */
5975static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5976 dma_addr_t mapping, u32 maxlen_flags,
5977 u32 nic_addr)
5978{
5979 tg3_write_mem(tp,
5980 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5981 ((u64) mapping >> 32));
5982 tg3_write_mem(tp,
5983 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5984 ((u64) mapping & 0xffffffff));
5985 tg3_write_mem(tp,
5986 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5987 maxlen_flags);
5988
5989 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5990 tg3_write_mem(tp,
5991 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5992 nic_addr);
5993}
5994
5995static void __tg3_set_rx_mode(struct net_device *);
d244c892 5996static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5997{
5998 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5999 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6000 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6001 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6002 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6003 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6004 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6005 }
6006 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6007 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6008 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6009 u32 val = ec->stats_block_coalesce_usecs;
6010
6011 if (!netif_carrier_ok(tp->dev))
6012 val = 0;
6013
6014 tw32(HOSTCC_STAT_COAL_TICKS, val);
6015 }
6016}
1da177e4
LT		 6017
6018/* tp->lock is held. */
8e7a22e3 6019static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6020{
6021 u32 val, rdmac_mode;
6022 int i, err, limit;
6023
6024 tg3_disable_ints(tp);
6025
6026 tg3_stop_fw(tp);
6027
6028 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6029
6030 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6031 tg3_abort_hw(tp, 1);
1da177e4
LT		 6032 }
6033
36da4d86 6034 if (reset_phy)
d4d2c558
MC		 6035 tg3_phy_reset(tp);
6036
1da177e4
LT		 6037 err = tg3_chip_reset(tp);
6038 if (err)
6039 return err;
6040
6041 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6042
6043 /* This works around an issue with Athlon chipsets on
6044 * B3 tigon3 silicon. This bit has no effect on any
6045 * other revision. But do not set this on PCI Express
6046 * chips.
6047 */
6048 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6049 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6050 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6051
6052 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6053 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6054 val = tr32(TG3PCI_PCISTATE);
6055 val |= PCISTATE_RETRY_SAME_DMA;
6056 tw32(TG3PCI_PCISTATE, val);
6057 }
6058
6059 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6060 /* Enable some hw fixes. */
6061 val = tr32(TG3PCI_MSI_DATA);
6062 val |= (1 << 26) | (1 << 28) | (1 << 29);
6063 tw32(TG3PCI_MSI_DATA, val);
6064 }
6065
6066 /* Descriptor ring init may make accesses to the
6067 * NIC SRAM area to setup the TX descriptors, so we
6068 * can only do this after the hardware has been
6069 * successfully reset.
6070 */
32d8c572
MC		 6071 err = tg3_init_rings(tp);
6072 if (err)
6073 return err;
1da177e4
LT		 6074
6075 /* This value is determined during the probe time DMA
6076 * engine test, tg3_test_dma.
6077 */
6078 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6079
6080 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6081 GRC_MODE_4X_NIC_SEND_RINGS |
6082 GRC_MODE_NO_TX_PHDR_CSUM |
6083 GRC_MODE_NO_RX_PHDR_CSUM);
6084 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6085
6086 /* Pseudo-header checksum is done by hardware logic and not
6087 * the offload processers, so make the chip do the pseudo-
6088 * header checksums on receive. For transmit it is more
6089 * convenient to do the pseudo-header checksum in software
6090 * as Linux does that on transmit for us in all cases.
6091 */
6092 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6093
6094 tw32(GRC_MODE,
6095 tp->grc_mode |
6096 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6097
6098 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6099 val = tr32(GRC_MISC_CFG);
6100 val &= ~0xff;
6101 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6102 tw32(GRC_MISC_CFG, val);
6103
6104 /* Initialize MBUF/DESC pool. */
cbf46853 6105 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6106 /* Do nothing. */
6107 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6108 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6110 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6111 else
6112 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6113 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6114 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6115 }
1da177e4
LT		 6116 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6117 int fw_len;
6118
6119 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6120 TG3_TSO5_FW_RODATA_LEN +
6121 TG3_TSO5_FW_DATA_LEN +
6122 TG3_TSO5_FW_SBSS_LEN +
6123 TG3_TSO5_FW_BSS_LEN);
6124 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6125 tw32(BUFMGR_MB_POOL_ADDR,
6126 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6127 tw32(BUFMGR_MB_POOL_SIZE,
6128 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6129 }
1da177e4 6130
0f893dc6 6131 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6132 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6133 tp->bufmgr_config.mbuf_read_dma_low_water);
6134 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6135 tp->bufmgr_config.mbuf_mac_rx_low_water);
6136 tw32(BUFMGR_MB_HIGH_WATER,
6137 tp->bufmgr_config.mbuf_high_water);
6138 } else {
6139 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6140 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6141 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6142 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6143 tw32(BUFMGR_MB_HIGH_WATER,
6144 tp->bufmgr_config.mbuf_high_water_jumbo);
6145 }
6146 tw32(BUFMGR_DMA_LOW_WATER,
6147 tp->bufmgr_config.dma_low_water);
6148 tw32(BUFMGR_DMA_HIGH_WATER,
6149 tp->bufmgr_config.dma_high_water);
6150
6151 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6152 for (i = 0; i < 2000; i++) {
6153 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6154 break;
6155 udelay(10);
6156 }
6157 if (i >= 2000) {
6158 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6159 tp->dev->name);
6160 return -ENODEV;
6161 }
6162
6163 /* Setup replenish threshold. */
f92905de
MC		 6164 val = tp->rx_pending / 8;
6165 if (val == 0)
6166 val = 1;
6167 else if (val > tp->rx_std_max_post)
6168 val = tp->rx_std_max_post;
b5d3772c
MC		 6169 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6170 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6171 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6172
6173 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6174 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6175 }
f92905de
MC		 6176
6177 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6178
6179 /* Initialize TG3_BDINFO's at:
6180 * RCVDBDI_STD_BD: standard eth size rx ring
6181 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6182 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6183 *
6184 * like so:
6185 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6186 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6187 * ring attribute flags
6188 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6189 *
6190 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6191 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6192 *
6193 * The size of each ring is fixed in the firmware, but the location is
6194 * configurable.
6195 */
6196 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6197 ((u64) tp->rx_std_mapping >> 32));
6198 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6199 ((u64) tp->rx_std_mapping & 0xffffffff));
6200 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6201 NIC_SRAM_RX_BUFFER_DESC);
6202
6203 /* Don't even try to program the JUMBO/MINI buffer descriptor
6204 * configs on 5705.
6205 */
6206 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6207 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6208 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6209 } else {
6210 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6211 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6212
6213 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6214 BDINFO_FLAGS_DISABLED);
6215
6216 /* Setup replenish threshold. */
6217 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6218
0f893dc6 6219 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6220 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6221 ((u64) tp->rx_jumbo_mapping >> 32));
6222 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6223 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6224 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6225 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6226 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6227 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6228 } else {
6229 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6230 BDINFO_FLAGS_DISABLED);
6231 }
6232
6233 }
6234
6235 /* There is only one send ring on 5705/5750, no need to explicitly
6236 * disable the others.
6237 */
6238 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6239 /* Clear out send RCB ring in SRAM. */
6240 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6241 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6242 BDINFO_FLAGS_DISABLED);
6243 }
6244
6245 tp->tx_prod = 0;
6246 tp->tx_cons = 0;
6247 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6248 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6249
6250 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6251 tp->tx_desc_mapping,
6252 (TG3_TX_RING_SIZE <<
6253 BDINFO_FLAGS_MAXLEN_SHIFT),
6254 NIC_SRAM_TX_BUFFER_DESC);
6255
6256 /* There is only one receive return ring on 5705/5750, no need
6257 * to explicitly disable the others.
6258 */
6259 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6260 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6261 i += TG3_BDINFO_SIZE) {
6262 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6263 BDINFO_FLAGS_DISABLED);
6264 }
6265 }
6266
6267 tp->rx_rcb_ptr = 0;
6268 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6269
6270 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6271 tp->rx_rcb_mapping,
6272 (TG3_RX_RCB_RING_SIZE(tp) <<
6273 BDINFO_FLAGS_MAXLEN_SHIFT),
6274 0);
6275
6276 tp->rx_std_ptr = tp->rx_pending;
6277 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6278 tp->rx_std_ptr);
6279
0f893dc6 6280 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6281 tp->rx_jumbo_pending : 0;
6282 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6283 tp->rx_jumbo_ptr);
6284
6285 /* Initialize MAC address and backoff seed. */
6286 __tg3_set_mac_addr(tp);
6287
6288 /* MTU + ethernet header + FCS + optional VLAN tag */
6289 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6290
6291 /* The slot time is changed by tg3_setup_phy if we
6292 * run at gigabit with half duplex.
6293 */
6294 tw32(MAC_TX_LENGTHS,
6295 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6296 (6 << TX_LENGTHS_IPG_SHIFT) |
6297 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6298
6299 /* Receive rules. */
6300 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6301 tw32(RCVLPC_CONFIG, 0x0181);
6302
6303 /* Calculate RDMAC_MODE setting early, we need it to determine
6304 * the RCVLPC_STATE_ENABLE mask.
6305 */
6306 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6307 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6308 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6309 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6310 RDMAC_MODE_LNGREAD_ENAB);
6311 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6312 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 6313
6314 /* If statement applies to 5705 and 5750 PCI devices only */
6315 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6316 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6317 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 6318 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6319 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6320 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6321 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6322 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6323 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6324 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6325 }
6326 }
6327
85e94ced
MC		 6328 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6329 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6330
1da177e4
LT		 6331 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6332 rdmac_mode |= (1 << 27);
1da177e4
LT		 6333
6334 /* Receive/send statistics. */
1661394e
MC		 6335 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6336 val = tr32(RCVLPC_STATS_ENABLE);
6337 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6338 tw32(RCVLPC_STATS_ENABLE, val);
6339 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6340 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6341 val = tr32(RCVLPC_STATS_ENABLE);
6342 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6343 tw32(RCVLPC_STATS_ENABLE, val);
6344 } else {
6345 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6346 }
6347 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6348 tw32(SNDDATAI_STATSENAB, 0xffffff);
6349 tw32(SNDDATAI_STATSCTRL,
6350 (SNDDATAI_SCTRL_ENABLE |
6351 SNDDATAI_SCTRL_FASTUPD));
6352
6353 /* Setup host coalescing engine. */
6354 tw32(HOSTCC_MODE, 0);
6355 for (i = 0; i < 2000; i++) {
6356 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6357 break;
6358 udelay(10);
6359 }
6360
d244c892 6361 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6362
6363 /* set status block DMA address */
6364 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6365 ((u64) tp->status_mapping >> 32));
6366 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6367 ((u64) tp->status_mapping & 0xffffffff));
6368
6369 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6370 /* Status/statistics block address. See tg3_timer,
6371 * the tg3_periodic_fetch_stats call there, and
6372 * tg3_get_stats to see how this works for 5705/5750 chips.
6373 */
1da177e4
LT		 6374 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6375 ((u64) tp->stats_mapping >> 32));
6376 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6377 ((u64) tp->stats_mapping & 0xffffffff));
6378 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6379 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6380 }
6381
6382 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6383
6384 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6385 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6386 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6387 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6388
6389 /* Clear statistics/status block in chip, and status block in ram. */
6390 for (i = NIC_SRAM_STATS_BLK;
6391 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6392 i += sizeof(u32)) {
6393 tg3_write_mem(tp, i, 0);
6394 udelay(40);
6395 }
6396 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6397
c94e3941
MC		 6398 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6399 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6400 /* reset to prevent losing 1st rx packet intermittently */
6401 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6402 udelay(10);
6403 }
6404
1da177e4
LT		 6405 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6406 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6407 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6408 udelay(40);
6409
314fba34 6410 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6411 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6412 * register to preserve the GPIO settings for LOMs. The GPIOs,
6413 * whether used as inputs or outputs, are set by boot code after
6414 * reset.
6415 */
9d26e213 6416 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6417 u32 gpio_mask;
6418
9d26e213
MC		 6419 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6420 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6421 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6422
6423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6424 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6425 GRC_LCLCTRL_GPIO_OUTPUT3;
6426
af36e6b6
MC		 6427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6428 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6429
314fba34
MC		 6430 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6431
6432 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6433 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6434 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6435 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6436 }
1da177e4
LT		 6437 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6438 udelay(100);
6439
09ee929c 6440 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6441 tp->last_tag = 0;
1da177e4
LT		 6442
6443 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6444 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6445 udelay(40);
6446 }
6447
6448 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6449 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6450 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6451 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6452 WDMAC_MODE_LNGREAD_ENAB);
6453
85e94ced
MC		 6454 /* If statement applies to 5705 and 5750 PCI devices only */
6455 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6456 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6458 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6459 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6460 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6461 /* nothing */
6462 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6463 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6464 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6465 val |= WDMAC_MODE_RX_ACCEL;
6466 }
6467 }
6468
d9ab5ad1 6469 /* Enable host coalescing bug fix */
af36e6b6
MC		 6470 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6471 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
d9ab5ad1
MC		 6472 val |= (1 << 29);
6473
1da177e4
LT		 6474 tw32_f(WDMAC_MODE, val);
6475 udelay(40);
6476
6477 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6478 val = tr32(TG3PCI_X_CAPS);
6479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6480 val &= ~PCIX_CAPS_BURST_MASK;
6481 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6482 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6483 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6484 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6485 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6486 val |= (tp->split_mode_max_reqs <<
6487 PCIX_CAPS_SPLIT_SHIFT);
6488 }
6489 tw32(TG3PCI_X_CAPS, val);
6490 }
6491
6492 tw32_f(RDMAC_MODE, rdmac_mode);
6493 udelay(40);
6494
6495 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6496 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6497 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6498 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6499 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6500 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6501 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6502 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6503 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6504 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6505 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6506 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6507
6508 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6509 err = tg3_load_5701_a0_firmware_fix(tp);
6510 if (err)
6511 return err;
6512 }
6513
1da177e4
LT		 6514 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6515 err = tg3_load_tso_firmware(tp);
6516 if (err)
6517 return err;
6518 }
1da177e4
LT		 6519
6520 tp->tx_mode = TX_MODE_ENABLE;
6521 tw32_f(MAC_TX_MODE, tp->tx_mode);
6522 udelay(100);
6523
6524 tp->rx_mode = RX_MODE_ENABLE;
af36e6b6
MC		 6525 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6526 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6527
1da177e4
LT		 6528 tw32_f(MAC_RX_MODE, tp->rx_mode);
6529 udelay(10);
6530
6531 if (tp->link_config.phy_is_low_power) {
6532 tp->link_config.phy_is_low_power = 0;
6533 tp->link_config.speed = tp->link_config.orig_speed;
6534 tp->link_config.duplex = tp->link_config.orig_duplex;
6535 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6536 }
6537
6538 tp->mi_mode = MAC_MI_MODE_BASE;
6539 tw32_f(MAC_MI_MODE, tp->mi_mode);
6540 udelay(80);
6541
6542 tw32(MAC_LED_CTRL, tp->led_ctrl);
6543
6544 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6545 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6546 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6547 udelay(10);
6548 }
6549 tw32_f(MAC_RX_MODE, tp->rx_mode);
6550 udelay(10);
6551
6552 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6553 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6554 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6555 /* Set drive transmission level to 1.2V */
6556 /* only if the signal pre-emphasis bit is not set */
6557 val = tr32(MAC_SERDES_CFG);
6558 val &= 0xfffff000;
6559 val |= 0x880;
6560 tw32(MAC_SERDES_CFG, val);
6561 }
6562 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6563 tw32(MAC_SERDES_CFG, 0x616000);
6564 }
6565
6566 /* Prevent chip from dropping frames when flow control
6567 * is enabled.
6568 */
6569 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6570
6571 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6572 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6573 /* Use hardware link auto-negotiation */
6574 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6575 }
6576
d4d2c558
MC		 6577 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6578 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6579 u32 tmp;
6580
6581 tmp = tr32(SERDES_RX_CTRL);
6582 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6583 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6584 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6585 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6586 }
6587
36da4d86 6588 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6589 if (err)
6590 return err;
6591
715116a1
MC		 6592 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6593 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6594 u32 tmp;
6595
6596 /* Clear CRC stats. */
6597 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6598 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6599 tg3_readphy(tp, 0x14, &tmp);
6600 }
6601 }
6602
6603 __tg3_set_rx_mode(tp->dev);
6604
6605 /* Initialize receive rules. */
6606 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6607 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6608 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6609 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6610
4cf78e4f 6611 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6612 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6613 limit = 8;
6614 else
6615 limit = 16;
6616 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6617 limit -= 4;
6618 switch (limit) {
6619 case 16:
6620 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6621 case 15:
6622 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6623 case 14:
6624 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6625 case 13:
6626 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6627 case 12:
6628 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6629 case 11:
6630 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6631 case 10:
6632 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6633 case 9:
6634 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6635 case 8:
6636 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6637 case 7:
6638 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6639 case 6:
6640 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6641 case 5:
6642 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6643 case 4:
6644 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6645 case 3:
6646 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6647 case 2:
6648 case 1:
6649
6650 default:
6651 break;
6652 };
6653
6654 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6655
1da177e4
LT		 6656 return 0;
6657}
6658
6659/* Called at device open time to get the chip ready for
6660 * packet processing. Invoked with tp->lock held.
6661 */
8e7a22e3 6662static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6663{
6664 int err;
6665
6666 /* Force the chip into D0. */
bc1c7567 6667 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 6668 if (err)
6669 goto out;
6670
6671 tg3_switch_clocks(tp);
6672
6673 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6674
8e7a22e3 6675 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 6676
6677out:
6678 return err;
6679}
6680
6681#define TG3_STAT_ADD32(PSTAT, REG) \
6682do { u32 __val = tr32(REG); \
6683 (PSTAT)->low += __val; \
6684 if ((PSTAT)->low < __val) \
6685 (PSTAT)->high += 1; \
6686} while (0)
6687
6688static void tg3_periodic_fetch_stats(struct tg3 *tp)
6689{
6690 struct tg3_hw_stats *sp = tp->hw_stats;
6691
6692 if (!netif_carrier_ok(tp->dev))
6693 return;
6694
6695 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6696 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6697 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6698 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6699 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6700 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6701 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6702 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6703 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6704 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6705 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6706 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6707 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6708
6709 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6710 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6711 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6712 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6713 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6714 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6715 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6716 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6717 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6718 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6719 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6720 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6721 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6722 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 6723
6724 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6725 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6726 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 6727}
6728
6729static void tg3_timer(unsigned long __opaque)
6730{
6731 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6732
f475f163
MC		 6733 if (tp->irq_sync)
6734 goto restart_timer;
6735
f47c11ee 6736 spin_lock(&tp->lock);
1da177e4 6737
fac9b83e
DM		 6738 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6739 /* All of this garbage is because when using non-tagged
6740 * IRQ status the mailbox/status_block protocol the chip
6741 * uses with the cpu is race prone.
6742 */
6743 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6744 tw32(GRC_LOCAL_CTRL,
6745 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6746 } else {
6747 tw32(HOSTCC_MODE, tp->coalesce_mode |
6748 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6749 }
1da177e4 6750
fac9b83e
DM		 6751 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6752 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6753 spin_unlock(&tp->lock);
fac9b83e
DM		 6754 schedule_work(&tp->reset_task);
6755 return;
6756 }
1da177e4
LT		 6757 }
6758
1da177e4
LT		 6759 /* This part only runs once per second. */
6760 if (!--tp->timer_counter) {
fac9b83e
DM		 6761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6762 tg3_periodic_fetch_stats(tp);
6763
1da177e4
LT		 6764 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6765 u32 mac_stat;
6766 int phy_event;
6767
6768 mac_stat = tr32(MAC_STATUS);
6769
6770 phy_event = 0;
6771 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6772 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6773 phy_event = 1;
6774 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6775 phy_event = 1;
6776
6777 if (phy_event)
6778 tg3_setup_phy(tp, 0);
6779 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6780 u32 mac_stat = tr32(MAC_STATUS);
6781 int need_setup = 0;
6782
6783 if (netif_carrier_ok(tp->dev) &&
6784 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6785 need_setup = 1;
6786 }
6787 if (! netif_carrier_ok(tp->dev) &&
6788 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6789 MAC_STATUS_SIGNAL_DET))) {
6790 need_setup = 1;
6791 }
6792 if (need_setup) {
3d3ebe74
MC		 6793 if (!tp->serdes_counter) {
6794 tw32_f(MAC_MODE,
6795 (tp->mac_mode &
6796 ~MAC_MODE_PORT_MODE_MASK));
6797 udelay(40);
6798 tw32_f(MAC_MODE, tp->mac_mode);
6799 udelay(40);
6800 }
1da177e4
LT		 6801 tg3_setup_phy(tp, 0);
6802 }
747e8f8b
MC		 6803 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6804 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6805
6806 tp->timer_counter = tp->timer_multiplier;
6807 }
6808
130b8e4d
MC		 6809 /* Heartbeat is only sent once every 2 seconds.
6810 *
6811 * The heartbeat is to tell the ASF firmware that the host
6812 * driver is still alive. In the event that the OS crashes,
6813 * ASF needs to reset the hardware to free up the FIFO space
6814 * that may be filled with rx packets destined for the host.
6815 * If the FIFO is full, ASF will no longer function properly.
6816 *
6817 * Unintended resets have been reported on real time kernels
6818 * where the timer doesn't run on time. Netpoll will also have
6819 * same problem.
6820 *
6821 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6822 * to check the ring condition when the heartbeat is expiring
6823 * before doing the reset. This will prevent most unintended
6824 * resets.
6825 */
1da177e4
LT		 6826 if (!--tp->asf_counter) {
6827 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6828 u32 val;
6829
bbadf503 6830 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 6831 FWCMD_NICDRV_ALIVE3);
bbadf503 6832 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 6833 /* 5 seconds timeout */
bbadf503 6834 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6835 val = tr32(GRC_RX_CPU_EVENT);
6836 val |= (1 << 14);
6837 tw32(GRC_RX_CPU_EVENT, val);
6838 }
6839 tp->asf_counter = tp->asf_multiplier;
6840 }
6841
f47c11ee 6842 spin_unlock(&tp->lock);
1da177e4 6843
f475f163 6844restart_timer:
1da177e4
LT		 6845 tp->timer.expires = jiffies + tp->timer_offset;
6846 add_timer(&tp->timer);
6847}
6848
81789ef5 6849static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 6850{
7d12e780 6851 irq_handler_t fn;
fcfa0a32
MC		 6852 unsigned long flags;
6853 struct net_device *dev = tp->dev;
6854
6855 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6856 fn = tg3_msi;
6857 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6858 fn = tg3_msi_1shot;
1fb9df5d 6859 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6860 } else {
6861 fn = tg3_interrupt;
6862 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6863 fn = tg3_interrupt_tagged;
1fb9df5d 6864 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6865 }
6866 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6867}
6868
7938109f
MC		 6869static int tg3_test_interrupt(struct tg3 *tp)
6870{
6871 struct net_device *dev = tp->dev;
b16250e3 6872 int err, i, intr_ok = 0;
7938109f 6873
d4bc3927
MC		 6874 if (!netif_running(dev))
6875 return -ENODEV;
6876
7938109f
MC		 6877 tg3_disable_ints(tp);
6878
6879 free_irq(tp->pdev->irq, dev);
6880
6881 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 6882 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6883 if (err)
6884 return err;
6885
38f3843e 6886 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6887 tg3_enable_ints(tp);
6888
6889 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6890 HOSTCC_MODE_NOW);
6891
6892 for (i = 0; i < 5; i++) {
b16250e3
MC		 6893 u32 int_mbox, misc_host_ctrl;
6894
09ee929c
MC		 6895 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6896 TG3_64BIT_REG_LOW);
b16250e3
MC		 6897 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6898
6899 if ((int_mbox != 0) ||
6900 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6901 intr_ok = 1;
7938109f 6902 break;
b16250e3
MC		 6903 }
6904
7938109f
MC		 6905 msleep(10);
6906 }
6907
6908 tg3_disable_ints(tp);
6909
6910 free_irq(tp->pdev->irq, dev);
6aa20a22 6911
fcfa0a32 6912 err = tg3_request_irq(tp);
7938109f
MC		 6913
6914 if (err)
6915 return err;
6916
b16250e3 6917 if (intr_ok)
7938109f
MC		 6918 return 0;
6919
6920 return -EIO;
6921}
6922
6923/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6924 * successfully restored
6925 */
6926static int tg3_test_msi(struct tg3 *tp)
6927{
6928 struct net_device *dev = tp->dev;
6929 int err;
6930 u16 pci_cmd;
6931
6932 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6933 return 0;
6934
6935 /* Turn off SERR reporting in case MSI terminates with Master
6936 * Abort.
6937 */
6938 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6939 pci_write_config_word(tp->pdev, PCI_COMMAND,
6940 pci_cmd & ~PCI_COMMAND_SERR);
6941
6942 err = tg3_test_interrupt(tp);
6943
6944 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6945
6946 if (!err)
6947 return 0;
6948
6949 /* other failures */
6950 if (err != -EIO)
6951 return err;
6952
6953 /* MSI test failed, go back to INTx mode */
6954 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6955 "switching to INTx mode. Please report this failure to "
6956 "the PCI maintainer and include system chipset information.\n",
6957 tp->dev->name);
6958
6959 free_irq(tp->pdev->irq, dev);
6960 pci_disable_msi(tp->pdev);
6961
6962 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6963
fcfa0a32 6964 err = tg3_request_irq(tp);
7938109f
MC		 6965 if (err)
6966 return err;
6967
6968 /* Need to reset the chip because the MSI cycle may have terminated
6969 * with Master Abort.
6970 */
f47c11ee 6971 tg3_full_lock(tp, 1);
7938109f 6972
944d980e 6973 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 6974 err = tg3_init_hw(tp, 1);
7938109f 6975
f47c11ee 6976 tg3_full_unlock(tp);
7938109f
MC		 6977
6978 if (err)
6979 free_irq(tp->pdev->irq, dev);
6980
6981 return err;
6982}
6983
1da177e4
LT		 6984static int tg3_open(struct net_device *dev)
6985{
6986 struct tg3 *tp = netdev_priv(dev);
6987 int err;
6988
c49a1561
MC		 6989 netif_carrier_off(tp->dev);
6990
f47c11ee 6991 tg3_full_lock(tp, 0);
1da177e4 6992
bc1c7567 6993 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 6994 if (err) {
6995 tg3_full_unlock(tp);
bc1c7567 6996 return err;
12862086 6997 }
bc1c7567 6998
1da177e4
LT		 6999 tg3_disable_ints(tp);
7000 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7001
f47c11ee 7002 tg3_full_unlock(tp);
1da177e4
LT		 7003
7004 /* The placement of this call is tied
7005 * to the setup and use of Host TX descriptors.
7006 */
7007 err = tg3_alloc_consistent(tp);
7008 if (err)
7009 return err;
7010
88b06bc2
MC		 7011 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7012 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
d4d2c558
MC		 7013 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7014 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7015 (tp->pdev_peer == tp->pdev))) {
fac9b83e
DM		 7016 /* All MSI supporting chips should support tagged
7017 * status. Assert that this is the case.
7018 */
7019 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7020 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7021 "Not using MSI.\n", tp->dev->name);
7022 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7023 u32 msi_mode;
7024
7025 msi_mode = tr32(MSGINT_MODE);
7026 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7027 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7028 }
7029 }
fcfa0a32 7030 err = tg3_request_irq(tp);
1da177e4
LT		 7031
7032 if (err) {
88b06bc2
MC		 7033 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7034 pci_disable_msi(tp->pdev);
7035 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7036 }
1da177e4
LT		 7037 tg3_free_consistent(tp);
7038 return err;
7039 }
7040
f47c11ee 7041 tg3_full_lock(tp, 0);
1da177e4 7042
8e7a22e3 7043 err = tg3_init_hw(tp, 1);
1da177e4 7044 if (err) {
944d980e 7045 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7046 tg3_free_rings(tp);
7047 } else {
fac9b83e
DM		 7048 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7049 tp->timer_offset = HZ;
7050 else
7051 tp->timer_offset = HZ / 10;
7052
7053 BUG_ON(tp->timer_offset > HZ);
7054 tp->timer_counter = tp->timer_multiplier =
7055 (HZ / tp->timer_offset);
7056 tp->asf_counter = tp->asf_multiplier =
28fbef78 7057 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7058
7059 init_timer(&tp->timer);
7060 tp->timer.expires = jiffies + tp->timer_offset;
7061 tp->timer.data = (unsigned long) tp;
7062 tp->timer.function = tg3_timer;
1da177e4
LT		 7063 }
7064
f47c11ee 7065 tg3_full_unlock(tp);
1da177e4
LT		 7066
7067 if (err) {
88b06bc2
MC		 7068 free_irq(tp->pdev->irq, dev);
7069 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7070 pci_disable_msi(tp->pdev);
7071 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7072 }
1da177e4
LT		 7073 tg3_free_consistent(tp);
7074 return err;
7075 }
7076
7938109f
MC		 7077 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7078 err = tg3_test_msi(tp);
fac9b83e 7079
7938109f 7080 if (err) {
f47c11ee 7081 tg3_full_lock(tp, 0);
7938109f
MC		 7082
7083 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7084 pci_disable_msi(tp->pdev);
7085 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7086 }
944d980e 7087 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7088 tg3_free_rings(tp);
7089 tg3_free_consistent(tp);
7090
f47c11ee 7091 tg3_full_unlock(tp);
7938109f
MC		 7092
7093 return err;
7094 }
fcfa0a32
MC		 7095
7096 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7097 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7098 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7099
b5d3772c
MC		 7100 tw32(PCIE_TRANSACTION_CFG,
7101 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7102 }
7103 }
7938109f
MC		 7104 }
7105
f47c11ee 7106 tg3_full_lock(tp, 0);
1da177e4 7107
7938109f
MC		 7108 add_timer(&tp->timer);
7109 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7110 tg3_enable_ints(tp);
7111
f47c11ee 7112 tg3_full_unlock(tp);
1da177e4
LT		 7113
7114 netif_start_queue(dev);
7115
7116 return 0;
7117}
7118
7119#if 0
7120/*static*/ void tg3_dump_state(struct tg3 *tp)
7121{
7122 u32 val32, val32_2, val32_3, val32_4, val32_5;
7123 u16 val16;
7124 int i;
7125
7126 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7127 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7128 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7129 val16, val32);
7130
7131 /* MAC block */
7132 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7133 tr32(MAC_MODE), tr32(MAC_STATUS));
7134 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7135 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7136 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7137 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7138 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7139 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7140
7141 /* Send data initiator control block */
7142 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7143 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7144 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7145 tr32(SNDDATAI_STATSCTRL));
7146
7147 /* Send data completion control block */
7148 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7149
7150 /* Send BD ring selector block */
7151 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7152 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7153
7154 /* Send BD initiator control block */
7155 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7156 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7157
7158 /* Send BD completion control block */
7159 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7160
7161 /* Receive list placement control block */
7162 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7163 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7164 printk(" RCVLPC_STATSCTRL[%08x]\n",
7165 tr32(RCVLPC_STATSCTRL));
7166
7167 /* Receive data and receive BD initiator control block */
7168 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7169 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7170
7171 /* Receive data completion control block */
7172 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7173 tr32(RCVDCC_MODE));
7174
7175 /* Receive BD initiator control block */
7176 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7177 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7178
7179 /* Receive BD completion control block */
7180 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7181 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7182
7183 /* Receive list selector control block */
7184 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7185 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7186
7187 /* Mbuf cluster free block */
7188 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7189 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7190
7191 /* Host coalescing control block */
7192 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7193 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7194 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7195 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7196 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7197 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7198 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7199 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7200 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7201 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7202 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7203 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7204
7205 /* Memory arbiter control block */
7206 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7207 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7208
7209 /* Buffer manager control block */
7210 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7211 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7212 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7213 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7214 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7215 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7216 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7217 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7218
7219 /* Read DMA control block */
7220 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7221 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7222
7223 /* Write DMA control block */
7224 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7225 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7226
7227 /* DMA completion block */
7228 printk("DEBUG: DMAC_MODE[%08x]\n",
7229 tr32(DMAC_MODE));
7230
7231 /* GRC block */
7232 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7233 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7234 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7235 tr32(GRC_LOCAL_CTRL));
7236
7237 /* TG3_BDINFOs */
7238 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7239 tr32(RCVDBDI_JUMBO_BD + 0x0),
7240 tr32(RCVDBDI_JUMBO_BD + 0x4),
7241 tr32(RCVDBDI_JUMBO_BD + 0x8),
7242 tr32(RCVDBDI_JUMBO_BD + 0xc));
7243 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7244 tr32(RCVDBDI_STD_BD + 0x0),
7245 tr32(RCVDBDI_STD_BD + 0x4),
7246 tr32(RCVDBDI_STD_BD + 0x8),
7247 tr32(RCVDBDI_STD_BD + 0xc));
7248 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7249 tr32(RCVDBDI_MINI_BD + 0x0),
7250 tr32(RCVDBDI_MINI_BD + 0x4),
7251 tr32(RCVDBDI_MINI_BD + 0x8),
7252 tr32(RCVDBDI_MINI_BD + 0xc));
7253
7254 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7255 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7256 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7257 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7258 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7259 val32, val32_2, val32_3, val32_4);
7260
7261 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7262 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7263 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7264 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7265 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7266 val32, val32_2, val32_3, val32_4);
7267
7268 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7269 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7270 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7271 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7272 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7273 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7274 val32, val32_2, val32_3, val32_4, val32_5);
7275
7276 /* SW status block */
7277 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7278 tp->hw_status->status,
7279 tp->hw_status->status_tag,
7280 tp->hw_status->rx_jumbo_consumer,
7281 tp->hw_status->rx_consumer,
7282 tp->hw_status->rx_mini_consumer,
7283 tp->hw_status->idx[0].rx_producer,
7284 tp->hw_status->idx[0].tx_consumer);
7285
7286 /* SW statistics block */
7287 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7288 ((u32 *)tp->hw_stats)[0],
7289 ((u32 *)tp->hw_stats)[1],
7290 ((u32 *)tp->hw_stats)[2],
7291 ((u32 *)tp->hw_stats)[3]);
7292
7293 /* Mailboxes */
7294 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7295 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7296 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7297 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7298 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7299
7300 /* NIC side send descriptors. */
7301 for (i = 0; i < 6; i++) {
7302 unsigned long txd;
7303
7304 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7305 + (i * sizeof(struct tg3_tx_buffer_desc));
7306 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7307 i,
7308 readl(txd + 0x0), readl(txd + 0x4),
7309 readl(txd + 0x8), readl(txd + 0xc));
7310 }
7311
7312 /* NIC side RX descriptors. */
7313 for (i = 0; i < 6; i++) {
7314 unsigned long rxd;
7315
7316 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7317 + (i * sizeof(struct tg3_rx_buffer_desc));
7318 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7319 i,
7320 readl(rxd + 0x0), readl(rxd + 0x4),
7321 readl(rxd + 0x8), readl(rxd + 0xc));
7322 rxd += (4 * sizeof(u32));
7323 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7324 i,
7325 readl(rxd + 0x0), readl(rxd + 0x4),
7326 readl(rxd + 0x8), readl(rxd + 0xc));
7327 }
7328
7329 for (i = 0; i < 6; i++) {
7330 unsigned long rxd;
7331
7332 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7333 + (i * sizeof(struct tg3_rx_buffer_desc));
7334 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7335 i,
7336 readl(rxd + 0x0), readl(rxd + 0x4),
7337 readl(rxd + 0x8), readl(rxd + 0xc));
7338 rxd += (4 * sizeof(u32));
7339 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7340 i,
7341 readl(rxd + 0x0), readl(rxd + 0x4),
7342 readl(rxd + 0x8), readl(rxd + 0xc));
7343 }
7344}
7345#endif
7346
7347static struct net_device_stats *tg3_get_stats(struct net_device *);
7348static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7349
7350static int tg3_close(struct net_device *dev)
7351{
7352 struct tg3 *tp = netdev_priv(dev);
7353
7faa006f
MC		 7354 /* Calling flush_scheduled_work() may deadlock because
7355 * linkwatch_event() may be on the workqueue and it will try to get
7356 * the rtnl_lock which we are holding.
7357 */
7358 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7359 msleep(1);
7360
1da177e4
LT		 7361 netif_stop_queue(dev);
7362
7363 del_timer_sync(&tp->timer);
7364
f47c11ee 7365 tg3_full_lock(tp, 1);
1da177e4
LT		 7366#if 0
7367 tg3_dump_state(tp);
7368#endif
7369
7370 tg3_disable_ints(tp);
7371
944d980e 7372 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7373 tg3_free_rings(tp);
7374 tp->tg3_flags &=
7375 ~(TG3_FLAG_INIT_COMPLETE |
7376 TG3_FLAG_GOT_SERDES_FLOWCTL);
1da177e4 7377
f47c11ee 7378 tg3_full_unlock(tp);
1da177e4 7379
88b06bc2
MC		 7380 free_irq(tp->pdev->irq, dev);
7381 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7382 pci_disable_msi(tp->pdev);
7383 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7384 }
1da177e4
LT		 7385
7386 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7387 sizeof(tp->net_stats_prev));
7388 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7389 sizeof(tp->estats_prev));
7390
7391 tg3_free_consistent(tp);
7392
bc1c7567
MC		 7393 tg3_set_power_state(tp, PCI_D3hot);
7394
7395 netif_carrier_off(tp->dev);
7396
1da177e4
LT		 7397 return 0;
7398}
7399
7400static inline unsigned long get_stat64(tg3_stat64_t *val)
7401{
7402 unsigned long ret;
7403
7404#if (BITS_PER_LONG == 32)
7405 ret = val->low;
7406#else
7407 ret = ((u64)val->high << 32) | ((u64)val->low);
7408#endif
7409 return ret;
7410}
7411
7412static unsigned long calc_crc_errors(struct tg3 *tp)
7413{
7414 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7415
7416 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7417 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7419 u32 val;
7420
f47c11ee 7421 spin_lock_bh(&tp->lock);
1da177e4
LT		 7422 if (!tg3_readphy(tp, 0x1e, &val)) {
7423 tg3_writephy(tp, 0x1e, val | 0x8000);
7424 tg3_readphy(tp, 0x14, &val);
7425 } else
7426 val = 0;
f47c11ee 7427 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7428
7429 tp->phy_crc_errors += val;
7430
7431 return tp->phy_crc_errors;
7432 }
7433
7434 return get_stat64(&hw_stats->rx_fcs_errors);
7435}
7436
7437#define ESTAT_ADD(member) \
7438 estats->member = old_estats->member + \
7439 get_stat64(&hw_stats->member)
7440
7441static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7442{
7443 struct tg3_ethtool_stats *estats = &tp->estats;
7444 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7445 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7446
7447 if (!hw_stats)
7448 return old_estats;
7449
7450 ESTAT_ADD(rx_octets);
7451 ESTAT_ADD(rx_fragments);
7452 ESTAT_ADD(rx_ucast_packets);
7453 ESTAT_ADD(rx_mcast_packets);
7454 ESTAT_ADD(rx_bcast_packets);
7455 ESTAT_ADD(rx_fcs_errors);
7456 ESTAT_ADD(rx_align_errors);
7457 ESTAT_ADD(rx_xon_pause_rcvd);
7458 ESTAT_ADD(rx_xoff_pause_rcvd);
7459 ESTAT_ADD(rx_mac_ctrl_rcvd);
7460 ESTAT_ADD(rx_xoff_entered);
7461 ESTAT_ADD(rx_frame_too_long_errors);
7462 ESTAT_ADD(rx_jabbers);
7463 ESTAT_ADD(rx_undersize_packets);
7464 ESTAT_ADD(rx_in_length_errors);
7465 ESTAT_ADD(rx_out_length_errors);
7466 ESTAT_ADD(rx_64_or_less_octet_packets);
7467 ESTAT_ADD(rx_65_to_127_octet_packets);
7468 ESTAT_ADD(rx_128_to_255_octet_packets);
7469 ESTAT_ADD(rx_256_to_511_octet_packets);
7470 ESTAT_ADD(rx_512_to_1023_octet_packets);
7471 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7472 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7473 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7474 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7475 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7476
7477 ESTAT_ADD(tx_octets);
7478 ESTAT_ADD(tx_collisions);
7479 ESTAT_ADD(tx_xon_sent);
7480 ESTAT_ADD(tx_xoff_sent);
7481 ESTAT_ADD(tx_flow_control);
7482 ESTAT_ADD(tx_mac_errors);
7483 ESTAT_ADD(tx_single_collisions);
7484 ESTAT_ADD(tx_mult_collisions);
7485 ESTAT_ADD(tx_deferred);
7486 ESTAT_ADD(tx_excessive_collisions);
7487 ESTAT_ADD(tx_late_collisions);
7488 ESTAT_ADD(tx_collide_2times);
7489 ESTAT_ADD(tx_collide_3times);
7490 ESTAT_ADD(tx_collide_4times);
7491 ESTAT_ADD(tx_collide_5times);
7492 ESTAT_ADD(tx_collide_6times);
7493 ESTAT_ADD(tx_collide_7times);
7494 ESTAT_ADD(tx_collide_8times);
7495 ESTAT_ADD(tx_collide_9times);
7496 ESTAT_ADD(tx_collide_10times);
7497 ESTAT_ADD(tx_collide_11times);
7498 ESTAT_ADD(tx_collide_12times);
7499 ESTAT_ADD(tx_collide_13times);
7500 ESTAT_ADD(tx_collide_14times);
7501 ESTAT_ADD(tx_collide_15times);
7502 ESTAT_ADD(tx_ucast_packets);
7503 ESTAT_ADD(tx_mcast_packets);
7504 ESTAT_ADD(tx_bcast_packets);
7505 ESTAT_ADD(tx_carrier_sense_errors);
7506 ESTAT_ADD(tx_discards);
7507 ESTAT_ADD(tx_errors);
7508
7509 ESTAT_ADD(dma_writeq_full);
7510 ESTAT_ADD(dma_write_prioq_full);
7511 ESTAT_ADD(rxbds_empty);
7512 ESTAT_ADD(rx_discards);
7513 ESTAT_ADD(rx_errors);
7514 ESTAT_ADD(rx_threshold_hit);
7515
7516 ESTAT_ADD(dma_readq_full);
7517 ESTAT_ADD(dma_read_prioq_full);
7518 ESTAT_ADD(tx_comp_queue_full);
7519
7520 ESTAT_ADD(ring_set_send_prod_index);
7521 ESTAT_ADD(ring_status_update);
7522 ESTAT_ADD(nic_irqs);
7523 ESTAT_ADD(nic_avoided_irqs);
7524 ESTAT_ADD(nic_tx_threshold_hit);
7525
7526 return estats;
7527}
7528
7529static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7530{
7531 struct tg3 *tp = netdev_priv(dev);
7532 struct net_device_stats *stats = &tp->net_stats;
7533 struct net_device_stats *old_stats = &tp->net_stats_prev;
7534 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7535
7536 if (!hw_stats)
7537 return old_stats;
7538
7539 stats->rx_packets = old_stats->rx_packets +
7540 get_stat64(&hw_stats->rx_ucast_packets) +
7541 get_stat64(&hw_stats->rx_mcast_packets) +
7542 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7543
1da177e4
LT		 7544 stats->tx_packets = old_stats->tx_packets +
7545 get_stat64(&hw_stats->tx_ucast_packets) +
7546 get_stat64(&hw_stats->tx_mcast_packets) +
7547 get_stat64(&hw_stats->tx_bcast_packets);
7548
7549 stats->rx_bytes = old_stats->rx_bytes +
7550 get_stat64(&hw_stats->rx_octets);
7551 stats->tx_bytes = old_stats->tx_bytes +
7552 get_stat64(&hw_stats->tx_octets);
7553
7554 stats->rx_errors = old_stats->rx_errors +
4f63b877 7555 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7556 stats->tx_errors = old_stats->tx_errors +
7557 get_stat64(&hw_stats->tx_errors) +
7558 get_stat64(&hw_stats->tx_mac_errors) +
7559 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7560 get_stat64(&hw_stats->tx_discards);
7561
7562 stats->multicast = old_stats->multicast +
7563 get_stat64(&hw_stats->rx_mcast_packets);
7564 stats->collisions = old_stats->collisions +
7565 get_stat64(&hw_stats->tx_collisions);
7566
7567 stats->rx_length_errors = old_stats->rx_length_errors +
7568 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7569 get_stat64(&hw_stats->rx_undersize_packets);
7570
7571 stats->rx_over_errors = old_stats->rx_over_errors +
7572 get_stat64(&hw_stats->rxbds_empty);
7573 stats->rx_frame_errors = old_stats->rx_frame_errors +
7574 get_stat64(&hw_stats->rx_align_errors);
7575 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7576 get_stat64(&hw_stats->tx_discards);
7577 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7578 get_stat64(&hw_stats->tx_carrier_sense_errors);
7579
7580 stats->rx_crc_errors = old_stats->rx_crc_errors +
7581 calc_crc_errors(tp);
7582
4f63b877
JL		 7583 stats->rx_missed_errors = old_stats->rx_missed_errors +
7584 get_stat64(&hw_stats->rx_discards);
7585
1da177e4
LT		 7586 return stats;
7587}
7588
7589static inline u32 calc_crc(unsigned char *buf, int len)
7590{
7591 u32 reg;
7592 u32 tmp;
7593 int j, k;
7594
7595 reg = 0xffffffff;
7596
7597 for (j = 0; j < len; j++) {
7598 reg ^= buf[j];
7599
7600 for (k = 0; k < 8; k++) {
7601 tmp = reg & 0x01;
7602
7603 reg >>= 1;
7604
7605 if (tmp) {
7606 reg ^= 0xedb88320;
7607 }
7608 }
7609 }
7610
7611 return ~reg;
7612}
7613
7614static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7615{
7616 /* accept or reject all multicast frames */
7617 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7618 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7619 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7620 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7621}
7622
7623static void __tg3_set_rx_mode(struct net_device *dev)
7624{
7625 struct tg3 *tp = netdev_priv(dev);
7626 u32 rx_mode;
7627
7628 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7629 RX_MODE_KEEP_VLAN_TAG);
7630
7631 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7632 * flag clear.
7633 */
7634#if TG3_VLAN_TAG_USED
7635 if (!tp->vlgrp &&
7636 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7637 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7638#else
7639 /* By definition, VLAN is disabled always in this
7640 * case.
7641 */
7642 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7643 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7644#endif
7645
7646 if (dev->flags & IFF_PROMISC) {
7647 /* Promiscuous mode. */
7648 rx_mode |= RX_MODE_PROMISC;
7649 } else if (dev->flags & IFF_ALLMULTI) {
7650 /* Accept all multicast. */
7651 tg3_set_multi (tp, 1);
7652 } else if (dev->mc_count < 1) {
7653 /* Reject all multicast. */
7654 tg3_set_multi (tp, 0);
7655 } else {
7656 /* Accept one or more multicast(s). */
7657 struct dev_mc_list *mclist;
7658 unsigned int i;
7659 u32 mc_filter[4] = { 0, };
7660 u32 regidx;
7661 u32 bit;
7662 u32 crc;
7663
7664 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7665 i++, mclist = mclist->next) {
7666
7667 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7668 bit = ~crc & 0x7f;
7669 regidx = (bit & 0x60) >> 5;
7670 bit &= 0x1f;
7671 mc_filter[regidx] |= (1 << bit);
7672 }
7673
7674 tw32(MAC_HASH_REG_0, mc_filter[0]);
7675 tw32(MAC_HASH_REG_1, mc_filter[1]);
7676 tw32(MAC_HASH_REG_2, mc_filter[2]);
7677 tw32(MAC_HASH_REG_3, mc_filter[3]);
7678 }
7679
7680 if (rx_mode != tp->rx_mode) {
7681 tp->rx_mode = rx_mode;
7682 tw32_f(MAC_RX_MODE, rx_mode);
7683 udelay(10);
7684 }
7685}
7686
7687static void tg3_set_rx_mode(struct net_device *dev)
7688{
7689 struct tg3 *tp = netdev_priv(dev);
7690
e75f7c90
MC		 7691 if (!netif_running(dev))
7692 return;
7693
f47c11ee 7694 tg3_full_lock(tp, 0);
1da177e4 7695 __tg3_set_rx_mode(dev);
f47c11ee 7696 tg3_full_unlock(tp);
1da177e4
LT		 7697}
7698
7699#define TG3_REGDUMP_LEN (32 * 1024)
7700
7701static int tg3_get_regs_len(struct net_device *dev)
7702{
7703 return TG3_REGDUMP_LEN;
7704}
7705
7706static void tg3_get_regs(struct net_device *dev,
7707 struct ethtool_regs *regs, void *_p)
7708{
7709 u32 *p = _p;
7710 struct tg3 *tp = netdev_priv(dev);
7711 u8 *orig_p = _p;
7712 int i;
7713
7714 regs->version = 0;
7715
7716 memset(p, 0, TG3_REGDUMP_LEN);
7717
bc1c7567
MC		 7718 if (tp->link_config.phy_is_low_power)
7719 return;
7720
f47c11ee 7721 tg3_full_lock(tp, 0);
1da177e4
LT		 7722
7723#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7724#define GET_REG32_LOOP(base,len) \
7725do { p = (u32 *)(orig_p + (base)); \
7726 for (i = 0; i < len; i += 4) \
7727 __GET_REG32((base) + i); \
7728} while (0)
7729#define GET_REG32_1(reg) \
7730do { p = (u32 *)(orig_p + (reg)); \
7731 __GET_REG32((reg)); \
7732} while (0)
7733
7734 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7735 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7736 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7737 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7738 GET_REG32_1(SNDDATAC_MODE);
7739 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7740 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7741 GET_REG32_1(SNDBDC_MODE);
7742 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7743 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7744 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7745 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7746 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7747 GET_REG32_1(RCVDCC_MODE);
7748 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7749 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7750 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7751 GET_REG32_1(MBFREE_MODE);
7752 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7753 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7754 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7755 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7756 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 7757 GET_REG32_1(RX_CPU_MODE);
7758 GET_REG32_1(RX_CPU_STATE);
7759 GET_REG32_1(RX_CPU_PGMCTR);
7760 GET_REG32_1(RX_CPU_HWBKPT);
7761 GET_REG32_1(TX_CPU_MODE);
7762 GET_REG32_1(TX_CPU_STATE);
7763 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 7764 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7765 GET_REG32_LOOP(FTQ_RESET, 0x120);
7766 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7767 GET_REG32_1(DMAC_MODE);
7768 GET_REG32_LOOP(GRC_MODE, 0x4c);
7769 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7770 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7771
7772#undef __GET_REG32
7773#undef GET_REG32_LOOP
7774#undef GET_REG32_1
7775
f47c11ee 7776 tg3_full_unlock(tp);
1da177e4
LT		 7777}
7778
7779static int tg3_get_eeprom_len(struct net_device *dev)
7780{
7781 struct tg3 *tp = netdev_priv(dev);
7782
7783 return tp->nvram_size;
7784}
7785
7786static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 7787static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 7788
7789static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7790{
7791 struct tg3 *tp = netdev_priv(dev);
7792 int ret;
7793 u8 *pd;
7794 u32 i, offset, len, val, b_offset, b_count;
7795
bc1c7567
MC		 7796 if (tp->link_config.phy_is_low_power)
7797 return -EAGAIN;
7798
1da177e4
LT		 7799 offset = eeprom->offset;
7800 len = eeprom->len;
7801 eeprom->len = 0;
7802
7803 eeprom->magic = TG3_EEPROM_MAGIC;
7804
7805 if (offset & 3) {
7806 /* adjustments to start on required 4 byte boundary */
7807 b_offset = offset & 3;
7808 b_count = 4 - b_offset;
7809 if (b_count > len) {
7810 /* i.e. offset=1 len=2 */
7811 b_count = len;
7812 }
7813 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7814 if (ret)
7815 return ret;
7816 val = cpu_to_le32(val);
7817 memcpy(data, ((char*)&val) + b_offset, b_count);
7818 len -= b_count;
7819 offset += b_count;
7820 eeprom->len += b_count;
7821 }
7822
7823 /* read bytes upto the last 4 byte boundary */
7824 pd = &data[eeprom->len];
7825 for (i = 0; i < (len - (len & 3)); i += 4) {
7826 ret = tg3_nvram_read(tp, offset + i, &val);
7827 if (ret) {
7828 eeprom->len += i;
7829 return ret;
7830 }
7831 val = cpu_to_le32(val);
7832 memcpy(pd + i, &val, 4);
7833 }
7834 eeprom->len += i;
7835
7836 if (len & 3) {
7837 /* read last bytes not ending on 4 byte boundary */
7838 pd = &data[eeprom->len];
7839 b_count = len & 3;
7840 b_offset = offset + len - b_count;
7841 ret = tg3_nvram_read(tp, b_offset, &val);
7842 if (ret)
7843 return ret;
7844 val = cpu_to_le32(val);
7845 memcpy(pd, ((char*)&val), b_count);
7846 eeprom->len += b_count;
7847 }
7848 return 0;
7849}
7850
6aa20a22 7851static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 7852
7853static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7854{
7855 struct tg3 *tp = netdev_priv(dev);
7856 int ret;
7857 u32 offset, len, b_offset, odd_len, start, end;
7858 u8 *buf;
7859
bc1c7567
MC		 7860 if (tp->link_config.phy_is_low_power)
7861 return -EAGAIN;
7862
1da177e4
LT		 7863 if (eeprom->magic != TG3_EEPROM_MAGIC)
7864 return -EINVAL;
7865
7866 offset = eeprom->offset;
7867 len = eeprom->len;
7868
7869 if ((b_offset = (offset & 3))) {
7870 /* adjustments to start on required 4 byte boundary */
7871 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7872 if (ret)
7873 return ret;
7874 start = cpu_to_le32(start);
7875 len += b_offset;
7876 offset &= ~3;
1c8594b4
MC		 7877 if (len < 4)
7878 len = 4;
1da177e4
LT		 7879 }
7880
7881 odd_len = 0;
1c8594b4 7882 if (len & 3) {
1da177e4
LT		 7883 /* adjustments to end on required 4 byte boundary */
7884 odd_len = 1;
7885 len = (len + 3) & ~3;
7886 ret = tg3_nvram_read(tp, offset+len-4, &end);
7887 if (ret)
7888 return ret;
7889 end = cpu_to_le32(end);
7890 }
7891
7892 buf = data;
7893 if (b_offset || odd_len) {
7894 buf = kmalloc(len, GFP_KERNEL);
7895 if (buf == 0)
7896 return -ENOMEM;
7897 if (b_offset)
7898 memcpy(buf, &start, 4);
7899 if (odd_len)
7900 memcpy(buf+len-4, &end, 4);
7901 memcpy(buf + b_offset, data, eeprom->len);
7902 }
7903
7904 ret = tg3_nvram_write_block(tp, offset, len, buf);
7905
7906 if (buf != data)
7907 kfree(buf);
7908
7909 return ret;
7910}
7911
7912static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7913{
7914 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7915
1da177e4
LT		 7916 cmd->supported = (SUPPORTED_Autoneg);
7917
7918 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7919 cmd->supported |= (SUPPORTED_1000baseT_Half |
7920 SUPPORTED_1000baseT_Full);
7921
ef348144 7922 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 7923 cmd->supported |= (SUPPORTED_100baseT_Half |
7924 SUPPORTED_100baseT_Full |
7925 SUPPORTED_10baseT_Half |
7926 SUPPORTED_10baseT_Full |
7927 SUPPORTED_MII);
ef348144
KK		 7928 cmd->port = PORT_TP;
7929 } else {
1da177e4 7930 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 7931 cmd->port = PORT_FIBRE;
7932 }
6aa20a22 7933
1da177e4
LT		 7934 cmd->advertising = tp->link_config.advertising;
7935 if (netif_running(dev)) {
7936 cmd->speed = tp->link_config.active_speed;
7937 cmd->duplex = tp->link_config.active_duplex;
7938 }
1da177e4
LT		 7939 cmd->phy_address = PHY_ADDR;
7940 cmd->transceiver = 0;
7941 cmd->autoneg = tp->link_config.autoneg;
7942 cmd->maxtxpkt = 0;
7943 cmd->maxrxpkt = 0;
7944 return 0;
7945}
6aa20a22 7946
1da177e4
LT		 7947static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7948{
7949 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 7950
7951 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7952 /* These are the only valid advertisement bits allowed. */
7953 if (cmd->autoneg == AUTONEG_ENABLE &&
7954 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7955 ADVERTISED_1000baseT_Full |
7956 ADVERTISED_Autoneg |
7957 ADVERTISED_FIBRE)))
7958 return -EINVAL;
37ff238d
MC		 7959 /* Fiber can only do SPEED_1000. */
7960 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7961 (cmd->speed != SPEED_1000))
7962 return -EINVAL;
7963 /* Copper cannot force SPEED_1000. */
7964 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7965 (cmd->speed == SPEED_1000))
7966 return -EINVAL;
7967 else if ((cmd->speed == SPEED_1000) &&
7968 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7969 return -EINVAL;
1da177e4 7970
f47c11ee 7971 tg3_full_lock(tp, 0);
1da177e4
LT		 7972
7973 tp->link_config.autoneg = cmd->autoneg;
7974 if (cmd->autoneg == AUTONEG_ENABLE) {
7975 tp->link_config.advertising = cmd->advertising;
7976 tp->link_config.speed = SPEED_INVALID;
7977 tp->link_config.duplex = DUPLEX_INVALID;
7978 } else {
7979 tp->link_config.advertising = 0;
7980 tp->link_config.speed = cmd->speed;
7981 tp->link_config.duplex = cmd->duplex;
7982 }
6aa20a22 7983
24fcad6b
MC		 7984 tp->link_config.orig_speed = tp->link_config.speed;
7985 tp->link_config.orig_duplex = tp->link_config.duplex;
7986 tp->link_config.orig_autoneg = tp->link_config.autoneg;
7987
1da177e4
LT		 7988 if (netif_running(dev))
7989 tg3_setup_phy(tp, 1);
7990
f47c11ee 7991 tg3_full_unlock(tp);
6aa20a22 7992
1da177e4
LT		 7993 return 0;
7994}
6aa20a22 7995
1da177e4
LT		 7996static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7997{
7998 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7999
1da177e4
LT		 8000 strcpy(info->driver, DRV_MODULE_NAME);
8001 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8002 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8003 strcpy(info->bus_info, pci_name(tp->pdev));
8004}
6aa20a22 8005
1da177e4
LT		 8006static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8007{
8008 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8009
1da177e4
LT		 8010 wol->supported = WAKE_MAGIC;
8011 wol->wolopts = 0;
8012 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8013 wol->wolopts = WAKE_MAGIC;
8014 memset(&wol->sopass, 0, sizeof(wol->sopass));
8015}
6aa20a22 8016
1da177e4
LT		 8017static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8018{
8019 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8020
1da177e4
LT		 8021 if (wol->wolopts & ~WAKE_MAGIC)
8022 return -EINVAL;
8023 if ((wol->wolopts & WAKE_MAGIC) &&
3f7045c1 8024 tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
1da177e4
LT		 8025 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8026 return -EINVAL;
6aa20a22 8027
f47c11ee 8028 spin_lock_bh(&tp->lock);
1da177e4
LT		 8029 if (wol->wolopts & WAKE_MAGIC)
8030 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8031 else
8032 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8033 spin_unlock_bh(&tp->lock);
6aa20a22 8034
1da177e4
LT		 8035 return 0;
8036}
6aa20a22 8037
1da177e4
LT		 8038static u32 tg3_get_msglevel(struct net_device *dev)
8039{
8040 struct tg3 *tp = netdev_priv(dev);
8041 return tp->msg_enable;
8042}
6aa20a22 8043
1da177e4
LT		 8044static void tg3_set_msglevel(struct net_device *dev, u32 value)
8045{
8046 struct tg3 *tp = netdev_priv(dev);
8047 tp->msg_enable = value;
8048}
6aa20a22 8049
1da177e4
LT		 8050static int tg3_set_tso(struct net_device *dev, u32 value)
8051{
8052 struct tg3 *tp = netdev_priv(dev);
8053
8054 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8055 if (value)
8056 return -EINVAL;
8057 return 0;
8058 }
b5d3772c
MC		 8059 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8060 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
b0026624
MC		 8061 if (value)
8062 dev->features |= NETIF_F_TSO6;
8063 else
8064 dev->features &= ~NETIF_F_TSO6;
8065 }
1da177e4
LT		 8066 return ethtool_op_set_tso(dev, value);
8067}
6aa20a22 8068
1da177e4
LT		 8069static int tg3_nway_reset(struct net_device *dev)
8070{
8071 struct tg3 *tp = netdev_priv(dev);
8072 u32 bmcr;
8073 int r;
6aa20a22 8074
1da177e4
LT		 8075 if (!netif_running(dev))
8076 return -EAGAIN;
8077
c94e3941
MC		 8078 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8079 return -EINVAL;
8080
f47c11ee 8081 spin_lock_bh(&tp->lock);
1da177e4
LT		 8082 r = -EINVAL;
8083 tg3_readphy(tp, MII_BMCR, &bmcr);
8084 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8085 ((bmcr & BMCR_ANENABLE) ||
8086 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8087 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8088 BMCR_ANENABLE);
1da177e4
LT		 8089 r = 0;
8090 }
f47c11ee 8091 spin_unlock_bh(&tp->lock);
6aa20a22 8092
1da177e4
LT		 8093 return r;
8094}
6aa20a22 8095
1da177e4
LT		 8096static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8097{
8098 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8099
1da177e4
LT		 8100 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8101 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8102 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8103 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8104 else
8105 ering->rx_jumbo_max_pending = 0;
8106
8107 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8108
8109 ering->rx_pending = tp->rx_pending;
8110 ering->rx_mini_pending = 0;
4f81c32b
MC		 8111 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8112 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8113 else
8114 ering->rx_jumbo_pending = 0;
8115
1da177e4
LT		 8116 ering->tx_pending = tp->tx_pending;
8117}
6aa20a22 8118
1da177e4
LT		 8119static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8120{
8121 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8122 int irq_sync = 0, err = 0;
6aa20a22 8123
1da177e4
LT		 8124 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8125 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8126 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8127 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8128 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8129 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8130 return -EINVAL;
6aa20a22 8131
bbe832c0 8132 if (netif_running(dev)) {
1da177e4 8133 tg3_netif_stop(tp);
bbe832c0
MC		 8134 irq_sync = 1;
8135 }
1da177e4 8136
bbe832c0 8137 tg3_full_lock(tp, irq_sync);
6aa20a22 8138
1da177e4
LT		 8139 tp->rx_pending = ering->rx_pending;
8140
8141 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8142 tp->rx_pending > 63)
8143 tp->rx_pending = 63;
8144 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8145 tp->tx_pending = ering->tx_pending;
8146
8147 if (netif_running(dev)) {
944d980e 8148 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8149 err = tg3_restart_hw(tp, 1);
8150 if (!err)
8151 tg3_netif_start(tp);
1da177e4
LT		 8152 }
8153
f47c11ee 8154 tg3_full_unlock(tp);
6aa20a22 8155
b9ec6c1b 8156 return err;
1da177e4 8157}
6aa20a22 8158
1da177e4
LT		 8159static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8160{
8161 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8162
1da177e4
LT		 8163 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8164 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8165 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8166}
6aa20a22 8167
1da177e4
LT		 8168static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8169{
8170 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8171 int irq_sync = 0, err = 0;
6aa20a22 8172
bbe832c0 8173 if (netif_running(dev)) {
1da177e4 8174 tg3_netif_stop(tp);
bbe832c0
MC		 8175 irq_sync = 1;
8176 }
1da177e4 8177
bbe832c0 8178 tg3_full_lock(tp, irq_sync);
f47c11ee 8179
1da177e4
LT		 8180 if (epause->autoneg)
8181 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8182 else
8183 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8184 if (epause->rx_pause)
8185 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8186 else
8187 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8188 if (epause->tx_pause)
8189 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8190 else
8191 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8192
8193 if (netif_running(dev)) {
944d980e 8194 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8195 err = tg3_restart_hw(tp, 1);
8196 if (!err)
8197 tg3_netif_start(tp);
1da177e4 8198 }
f47c11ee
DM		 8199
8200 tg3_full_unlock(tp);
6aa20a22 8201
b9ec6c1b 8202 return err;
1da177e4 8203}
6aa20a22 8204
1da177e4
LT		 8205static u32 tg3_get_rx_csum(struct net_device *dev)
8206{
8207 struct tg3 *tp = netdev_priv(dev);
8208 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8209}
6aa20a22 8210
1da177e4
LT		 8211static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8212{
8213 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8214
1da177e4
LT		 8215 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8216 if (data != 0)
8217 return -EINVAL;
8218 return 0;
8219 }
6aa20a22 8220
f47c11ee 8221 spin_lock_bh(&tp->lock);
1da177e4
LT		 8222 if (data)
8223 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8224 else
8225 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8226 spin_unlock_bh(&tp->lock);
6aa20a22 8227
1da177e4
LT		 8228 return 0;
8229}
6aa20a22 8230
1da177e4
LT		 8231static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8232{
8233 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8234
1da177e4
LT		 8235 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8236 if (data != 0)
8237 return -EINVAL;
8238 return 0;
8239 }
6aa20a22 8240
af36e6b6
MC		 8241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8242 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf 8243 ethtool_op_set_tx_hw_csum(dev, data);
1da177e4 8244 else
9c27dbdf 8245 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8246
8247 return 0;
8248}
8249
8250static int tg3_get_stats_count (struct net_device *dev)
8251{
8252 return TG3_NUM_STATS;
8253}
8254
4cafd3f5
MC		 8255static int tg3_get_test_count (struct net_device *dev)
8256{
8257 return TG3_NUM_TEST;
8258}
8259
1da177e4
LT		 8260static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8261{
8262 switch (stringset) {
8263 case ETH_SS_STATS:
8264 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8265 break;
4cafd3f5
MC		 8266 case ETH_SS_TEST:
8267 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8268 break;
1da177e4
LT		 8269 default:
8270 WARN_ON(1); /* we need a WARN() */
8271 break;
8272 }
8273}
8274
4009a93d
MC		 8275static int tg3_phys_id(struct net_device *dev, u32 data)
8276{
8277 struct tg3 *tp = netdev_priv(dev);
8278 int i;
8279
8280 if (!netif_running(tp->dev))
8281 return -EAGAIN;
8282
8283 if (data == 0)
8284 data = 2;
8285
8286 for (i = 0; i < (data * 2); i++) {
8287 if ((i % 2) == 0)
8288 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8289 LED_CTRL_1000MBPS_ON |
8290 LED_CTRL_100MBPS_ON |
8291 LED_CTRL_10MBPS_ON |
8292 LED_CTRL_TRAFFIC_OVERRIDE |
8293 LED_CTRL_TRAFFIC_BLINK |
8294 LED_CTRL_TRAFFIC_LED);
6aa20a22 8295
4009a93d
MC		 8296 else
8297 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8298 LED_CTRL_TRAFFIC_OVERRIDE);
8299
8300 if (msleep_interruptible(500))
8301 break;
8302 }
8303 tw32(MAC_LED_CTRL, tp->led_ctrl);
8304 return 0;
8305}
8306
1da177e4
LT		 8307static void tg3_get_ethtool_stats (struct net_device *dev,
8308 struct ethtool_stats *estats, u64 *tmp_stats)
8309{
8310 struct tg3 *tp = netdev_priv(dev);
8311 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8312}
8313
566f86ad 8314#define NVRAM_TEST_SIZE 0x100
1b27777a 8315#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
b16250e3
MC		 8316#define NVRAM_SELFBOOT_HW_SIZE 0x20
8317#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8318
8319static int tg3_test_nvram(struct tg3 *tp)
8320{
1b27777a
MC		 8321 u32 *buf, csum, magic;
8322 int i, j, err = 0, size;
566f86ad 8323
1820180b 8324 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8325 return -EIO;
8326
1b27777a
MC		 8327 if (magic == TG3_EEPROM_MAGIC)
8328 size = NVRAM_TEST_SIZE;
b16250e3 8329 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8330 if ((magic & 0xe00000) == 0x200000)
8331 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8332 else
8333 return 0;
b16250e3
MC		 8334 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8335 size = NVRAM_SELFBOOT_HW_SIZE;
8336 else
1b27777a
MC		 8337 return -EIO;
8338
8339 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8340 if (buf == NULL)
8341 return -ENOMEM;
8342
1b27777a
MC		 8343 err = -EIO;
8344 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8345 u32 val;
8346
8347 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8348 break;
8349 buf[j] = cpu_to_le32(val);
8350 }
1b27777a 8351 if (i < size)
566f86ad
MC		 8352 goto out;
8353
1b27777a 8354 /* Selfboot format */
b16250e3
MC		 8355 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8356 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8357 u8 *buf8 = (u8 *) buf, csum8 = 0;
8358
8359 for (i = 0; i < size; i++)
8360 csum8 += buf8[i];
8361
ad96b485
AB		 8362 if (csum8 == 0) {
8363 err = 0;
8364 goto out;
8365 }
8366
8367 err = -EIO;
8368 goto out;
1b27777a 8369 }
566f86ad 8370
b16250e3
MC		 8371 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8372 TG3_EEPROM_MAGIC_HW) {
8373 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8374 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8375 u8 *buf8 = (u8 *) buf;
8376 int j, k;
8377
8378 /* Separate the parity bits and the data bytes. */
8379 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8380 if ((i == 0) || (i == 8)) {
8381 int l;
8382 u8 msk;
8383
8384 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8385 parity[k++] = buf8[i] & msk;
8386 i++;
8387 }
8388 else if (i == 16) {
8389 int l;
8390 u8 msk;
8391
8392 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8393 parity[k++] = buf8[i] & msk;
8394 i++;
8395
8396 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8397 parity[k++] = buf8[i] & msk;
8398 i++;
8399 }
8400 data[j++] = buf8[i];
8401 }
8402
8403 err = -EIO;
8404 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8405 u8 hw8 = hweight8(data[i]);
8406
8407 if ((hw8 & 0x1) && parity[i])
8408 goto out;
8409 else if (!(hw8 & 0x1) && !parity[i])
8410 goto out;
8411 }
8412 err = 0;
8413 goto out;
8414 }
8415
566f86ad
MC		 8416 /* Bootstrap checksum at offset 0x10 */
8417 csum = calc_crc((unsigned char *) buf, 0x10);
8418 if(csum != cpu_to_le32(buf[0x10/4]))
8419 goto out;
8420
8421 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8422 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8423 if (csum != cpu_to_le32(buf[0xfc/4]))
8424 goto out;
8425
8426 err = 0;
8427
8428out:
8429 kfree(buf);
8430 return err;
8431}
8432
ca43007a
MC		 8433#define TG3_SERDES_TIMEOUT_SEC 2
8434#define TG3_COPPER_TIMEOUT_SEC 6
8435
8436static int tg3_test_link(struct tg3 *tp)
8437{
8438 int i, max;
8439
8440 if (!netif_running(tp->dev))
8441 return -ENODEV;
8442
4c987487 8443 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8444 max = TG3_SERDES_TIMEOUT_SEC;
8445 else
8446 max = TG3_COPPER_TIMEOUT_SEC;
8447
8448 for (i = 0; i < max; i++) {
8449 if (netif_carrier_ok(tp->dev))
8450 return 0;
8451
8452 if (msleep_interruptible(1000))
8453 break;
8454 }
8455
8456 return -EIO;
8457}
8458
a71116d1 8459/* Only test the commonly used registers */
30ca3e37 8460static int tg3_test_registers(struct tg3 *tp)
a71116d1 8461{
b16250e3 8462 int i, is_5705, is_5750;
a71116d1
MC		 8463 u32 offset, read_mask, write_mask, val, save_val, read_val;
8464 static struct {
8465 u16 offset;
8466 u16 flags;
8467#define TG3_FL_5705 0x1
8468#define TG3_FL_NOT_5705 0x2
8469#define TG3_FL_NOT_5788 0x4
b16250e3 8470#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8471 u32 read_mask;
8472 u32 write_mask;
8473 } reg_tbl[] = {
8474 /* MAC Control Registers */
8475 { MAC_MODE, TG3_FL_NOT_5705,
8476 0x00000000, 0x00ef6f8c },
8477 { MAC_MODE, TG3_FL_5705,
8478 0x00000000, 0x01ef6b8c },
8479 { MAC_STATUS, TG3_FL_NOT_5705,
8480 0x03800107, 0x00000000 },
8481 { MAC_STATUS, TG3_FL_5705,
8482 0x03800100, 0x00000000 },
8483 { MAC_ADDR_0_HIGH, 0x0000,
8484 0x00000000, 0x0000ffff },
8485 { MAC_ADDR_0_LOW, 0x0000,
8486 0x00000000, 0xffffffff },
8487 { MAC_RX_MTU_SIZE, 0x0000,
8488 0x00000000, 0x0000ffff },
8489 { MAC_TX_MODE, 0x0000,
8490 0x00000000, 0x00000070 },
8491 { MAC_TX_LENGTHS, 0x0000,
8492 0x00000000, 0x00003fff },
8493 { MAC_RX_MODE, TG3_FL_NOT_5705,
8494 0x00000000, 0x000007fc },
8495 { MAC_RX_MODE, TG3_FL_5705,
8496 0x00000000, 0x000007dc },
8497 { MAC_HASH_REG_0, 0x0000,
8498 0x00000000, 0xffffffff },
8499 { MAC_HASH_REG_1, 0x0000,
8500 0x00000000, 0xffffffff },
8501 { MAC_HASH_REG_2, 0x0000,
8502 0x00000000, 0xffffffff },
8503 { MAC_HASH_REG_3, 0x0000,
8504 0x00000000, 0xffffffff },
8505
8506 /* Receive Data and Receive BD Initiator Control Registers. */
8507 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8508 0x00000000, 0xffffffff },
8509 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8510 0x00000000, 0xffffffff },
8511 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8512 0x00000000, 0x00000003 },
8513 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8514 0x00000000, 0xffffffff },
8515 { RCVDBDI_STD_BD+0, 0x0000,
8516 0x00000000, 0xffffffff },
8517 { RCVDBDI_STD_BD+4, 0x0000,
8518 0x00000000, 0xffffffff },
8519 { RCVDBDI_STD_BD+8, 0x0000,
8520 0x00000000, 0xffff0002 },
8521 { RCVDBDI_STD_BD+0xc, 0x0000,
8522 0x00000000, 0xffffffff },
6aa20a22 8523
a71116d1
MC		 8524 /* Receive BD Initiator Control Registers. */
8525 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8526 0x00000000, 0xffffffff },
8527 { RCVBDI_STD_THRESH, TG3_FL_5705,
8528 0x00000000, 0x000003ff },
8529 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8530 0x00000000, 0xffffffff },
6aa20a22 8531
a71116d1
MC		 8532 /* Host Coalescing Control Registers. */
8533 { HOSTCC_MODE, TG3_FL_NOT_5705,
8534 0x00000000, 0x00000004 },
8535 { HOSTCC_MODE, TG3_FL_5705,
8536 0x00000000, 0x000000f6 },
8537 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8538 0x00000000, 0xffffffff },
8539 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8540 0x00000000, 0x000003ff },
8541 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8542 0x00000000, 0xffffffff },
8543 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8544 0x00000000, 0x000003ff },
8545 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8546 0x00000000, 0xffffffff },
8547 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8548 0x00000000, 0x000000ff },
8549 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8550 0x00000000, 0xffffffff },
8551 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8552 0x00000000, 0x000000ff },
8553 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8554 0x00000000, 0xffffffff },
8555 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8556 0x00000000, 0xffffffff },
8557 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8558 0x00000000, 0xffffffff },
8559 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8560 0x00000000, 0x000000ff },
8561 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8562 0x00000000, 0xffffffff },
8563 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8564 0x00000000, 0x000000ff },
8565 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8566 0x00000000, 0xffffffff },
8567 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8568 0x00000000, 0xffffffff },
8569 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8570 0x00000000, 0xffffffff },
8571 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8572 0x00000000, 0xffffffff },
8573 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8574 0x00000000, 0xffffffff },
8575 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8576 0xffffffff, 0x00000000 },
8577 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8578 0xffffffff, 0x00000000 },
8579
8580 /* Buffer Manager Control Registers. */
b16250e3 8581 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 8582 0x00000000, 0x007fff80 },
b16250e3 8583 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 8584 0x00000000, 0x007fffff },
8585 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8586 0x00000000, 0x0000003f },
8587 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8588 0x00000000, 0x000001ff },
8589 { BUFMGR_MB_HIGH_WATER, 0x0000,
8590 0x00000000, 0x000001ff },
8591 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8592 0xffffffff, 0x00000000 },
8593 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8594 0xffffffff, 0x00000000 },
6aa20a22 8595
a71116d1
MC		 8596 /* Mailbox Registers */
8597 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8598 0x00000000, 0x000001ff },
8599 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8600 0x00000000, 0x000001ff },
8601 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8602 0x00000000, 0x000007ff },
8603 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8604 0x00000000, 0x000001ff },
8605
8606 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8607 };
8608
b16250e3
MC		 8609 is_5705 = is_5750 = 0;
8610 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 8611 is_5705 = 1;
b16250e3
MC		 8612 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8613 is_5750 = 1;
8614 }
a71116d1
MC		 8615
8616 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8617 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8618 continue;
8619
8620 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8621 continue;
8622
8623 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8624 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8625 continue;
8626
b16250e3
MC		 8627 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8628 continue;
8629
a71116d1
MC		 8630 offset = (u32) reg_tbl[i].offset;
8631 read_mask = reg_tbl[i].read_mask;
8632 write_mask = reg_tbl[i].write_mask;
8633
8634 /* Save the original register content */
8635 save_val = tr32(offset);
8636
8637 /* Determine the read-only value. */
8638 read_val = save_val & read_mask;
8639
8640 /* Write zero to the register, then make sure the read-only bits
8641 * are not changed and the read/write bits are all zeros.
8642 */
8643 tw32(offset, 0);
8644
8645 val = tr32(offset);
8646
8647 /* Test the read-only and read/write bits. */
8648 if (((val & read_mask) != read_val) || (val & write_mask))
8649 goto out;
8650
8651 /* Write ones to all the bits defined by RdMask and WrMask, then
8652 * make sure the read-only bits are not changed and the
8653 * read/write bits are all ones.
8654 */
8655 tw32(offset, read_mask | write_mask);
8656
8657 val = tr32(offset);
8658
8659 /* Test the read-only bits. */
8660 if ((val & read_mask) != read_val)
8661 goto out;
8662
8663 /* Test the read/write bits. */
8664 if ((val & write_mask) != write_mask)
8665 goto out;
8666
8667 tw32(offset, save_val);
8668 }
8669
8670 return 0;
8671
8672out:
9f88f29f
MC		 8673 if (netif_msg_hw(tp))
8674 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8675 offset);
a71116d1
MC		 8676 tw32(offset, save_val);
8677 return -EIO;
8678}
8679
7942e1db
MC		 8680static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8681{
f71e1309 8682 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 8683 int i;
8684 u32 j;
8685
8686 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8687 for (j = 0; j < len; j += 4) {
8688 u32 val;
8689
8690 tg3_write_mem(tp, offset + j, test_pattern[i]);
8691 tg3_read_mem(tp, offset + j, &val);
8692 if (val != test_pattern[i])
8693 return -EIO;
8694 }
8695 }
8696 return 0;
8697}
8698
8699static int tg3_test_memory(struct tg3 *tp)
8700{
8701 static struct mem_entry {
8702 u32 offset;
8703 u32 len;
8704 } mem_tbl_570x[] = {
38690194 8705 { 0x00000000, 0x00b50},
7942e1db
MC		 8706 { 0x00002000, 0x1c000},
8707 { 0xffffffff, 0x00000}
8708 }, mem_tbl_5705[] = {
8709 { 0x00000100, 0x0000c},
8710 { 0x00000200, 0x00008},
7942e1db
MC		 8711 { 0x00004000, 0x00800},
8712 { 0x00006000, 0x01000},
8713 { 0x00008000, 0x02000},
8714 { 0x00010000, 0x0e000},
8715 { 0xffffffff, 0x00000}
79f4d13a
MC		 8716 }, mem_tbl_5755[] = {
8717 { 0x00000200, 0x00008},
8718 { 0x00004000, 0x00800},
8719 { 0x00006000, 0x00800},
8720 { 0x00008000, 0x02000},
8721 { 0x00010000, 0x0c000},
8722 { 0xffffffff, 0x00000}
b16250e3
MC		 8723 }, mem_tbl_5906[] = {
8724 { 0x00000200, 0x00008},
8725 { 0x00004000, 0x00400},
8726 { 0x00006000, 0x00400},
8727 { 0x00008000, 0x01000},
8728 { 0x00010000, 0x01000},
8729 { 0xffffffff, 0x00000}
7942e1db
MC		 8730 };
8731 struct mem_entry *mem_tbl;
8732 int err = 0;
8733 int i;
8734
79f4d13a 8735 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6
MC		 8736 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
79f4d13a 8738 mem_tbl = mem_tbl_5755;
b16250e3
MC		 8739 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8740 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 8741 else
8742 mem_tbl = mem_tbl_5705;
8743 } else
7942e1db
MC		 8744 mem_tbl = mem_tbl_570x;
8745
8746 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8747 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8748 mem_tbl[i].len)) != 0)
8749 break;
8750 }
6aa20a22 8751
7942e1db
MC		 8752 return err;
8753}
8754
9f40dead
MC		 8755#define TG3_MAC_LOOPBACK 0
8756#define TG3_PHY_LOOPBACK 1
8757
8758static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8759{
9f40dead 8760 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8761 u32 desc_idx;
8762 struct sk_buff *skb, *rx_skb;
8763 u8 *tx_data;
8764 dma_addr_t map;
8765 int num_pkts, tx_len, rx_len, i, err;
8766 struct tg3_rx_buffer_desc *desc;
8767
9f40dead 8768 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8769 /* HW errata - mac loopback fails in some cases on 5780.
8770 * Normal traffic and PHY loopback are not affected by
8771 * errata.
8772 */
8773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8774 return 0;
8775
9f40dead 8776 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
3f7045c1
MC		 8777 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8778 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8779 mac_mode |= MAC_MODE_PORT_MODE_MII;
8780 else
8781 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 8782 tw32(MAC_MODE, mac_mode);
8783 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 8784 u32 val;
8785
b16250e3
MC		 8786 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8787 u32 phytest;
8788
8789 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8790 u32 phy;
8791
8792 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8793 phytest | MII_TG3_EPHY_SHADOW_EN);
8794 if (!tg3_readphy(tp, 0x1b, &phy))
8795 tg3_writephy(tp, 0x1b, phy & ~0x20);
8796 if (!tg3_readphy(tp, 0x10, &phy))
8797 tg3_writephy(tp, 0x10, phy & ~0x4000);
8798 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8799 }
5d64ad34
MC		 8800 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8801 } else
8802 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1
MC		 8803
8804 tg3_writephy(tp, MII_BMCR, val);
c94e3941 8805 udelay(40);
5d64ad34
MC		 8806
8807 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8808 MAC_MODE_LINK_POLARITY;
8809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 8810 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 8811 mac_mode |= MAC_MODE_PORT_MODE_MII;
8812 } else
8813 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 8814
c94e3941
MC		 8815 /* reset to prevent losing 1st rx packet intermittently */
8816 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8817 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8818 udelay(10);
8819 tw32_f(MAC_RX_MODE, tp->rx_mode);
8820 }
ff18ff02 8821 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9f40dead 8822 mac_mode &= ~MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 8823 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8824 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8825 }
9f40dead 8826 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8827 }
8828 else
8829 return -EINVAL;
c76949a6
MC		 8830
8831 err = -EIO;
8832
c76949a6 8833 tx_len = 1514;
a20e9c62 8834 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 8835 if (!skb)
8836 return -ENOMEM;
8837
c76949a6
MC		 8838 tx_data = skb_put(skb, tx_len);
8839 memcpy(tx_data, tp->dev->dev_addr, 6);
8840 memset(tx_data + 6, 0x0, 8);
8841
8842 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8843
8844 for (i = 14; i < tx_len; i++)
8845 tx_data[i] = (u8) (i & 0xff);
8846
8847 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8848
8849 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8850 HOSTCC_MODE_NOW);
8851
8852 udelay(10);
8853
8854 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8855
c76949a6
MC		 8856 num_pkts = 0;
8857
9f40dead 8858 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8859
9f40dead 8860 tp->tx_prod++;
c76949a6
MC		 8861 num_pkts++;
8862
9f40dead
MC		 8863 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8864 tp->tx_prod);
09ee929c 8865 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8866
8867 udelay(10);
8868
3f7045c1
MC		 8869 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8870 for (i = 0; i < 25; i++) {
c76949a6
MC		 8871 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8872 HOSTCC_MODE_NOW);
8873
8874 udelay(10);
8875
8876 tx_idx = tp->hw_status->idx[0].tx_consumer;
8877 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8878 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8879 (rx_idx == (rx_start_idx + num_pkts)))
8880 break;
8881 }
8882
8883 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8884 dev_kfree_skb(skb);
8885
9f40dead 8886 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8887 goto out;
8888
8889 if (rx_idx != rx_start_idx + num_pkts)
8890 goto out;
8891
8892 desc = &tp->rx_rcb[rx_start_idx];
8893 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8894 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8895 if (opaque_key != RXD_OPAQUE_RING_STD)
8896 goto out;
8897
8898 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8899 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8900 goto out;
8901
8902 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8903 if (rx_len != tx_len)
8904 goto out;
8905
8906 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8907
8908 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8909 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8910
8911 for (i = 14; i < tx_len; i++) {
8912 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8913 goto out;
8914 }
8915 err = 0;
6aa20a22 8916
c76949a6
MC		 8917 /* tg3_free_rings will unmap and free the rx_skb */
8918out:
8919 return err;
8920}
8921
9f40dead
MC		 8922#define TG3_MAC_LOOPBACK_FAILED 1
8923#define TG3_PHY_LOOPBACK_FAILED 2
8924#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8925 TG3_PHY_LOOPBACK_FAILED)
8926
8927static int tg3_test_loopback(struct tg3 *tp)
8928{
8929 int err = 0;
8930
8931 if (!netif_running(tp->dev))
8932 return TG3_LOOPBACK_FAILED;
8933
b9ec6c1b
MC		 8934 err = tg3_reset_hw(tp, 1);
8935 if (err)
8936 return TG3_LOOPBACK_FAILED;
9f40dead
MC		 8937
8938 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8939 err |= TG3_MAC_LOOPBACK_FAILED;
8940 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8941 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8942 err |= TG3_PHY_LOOPBACK_FAILED;
8943 }
8944
8945 return err;
8946}
8947
4cafd3f5
MC		 8948static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8949 u64 *data)
8950{
566f86ad
MC		 8951 struct tg3 *tp = netdev_priv(dev);
8952
bc1c7567
MC		 8953 if (tp->link_config.phy_is_low_power)
8954 tg3_set_power_state(tp, PCI_D0);
8955
566f86ad
MC		 8956 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8957
8958 if (tg3_test_nvram(tp) != 0) {
8959 etest->flags |= ETH_TEST_FL_FAILED;
8960 data[0] = 1;
8961 }
ca43007a
MC		 8962 if (tg3_test_link(tp) != 0) {
8963 etest->flags |= ETH_TEST_FL_FAILED;
8964 data[1] = 1;
8965 }
a71116d1 8966 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 8967 int err, irq_sync = 0;
bbe832c0
MC		 8968
8969 if (netif_running(dev)) {
a71116d1 8970 tg3_netif_stop(tp);
bbe832c0
MC		 8971 irq_sync = 1;
8972 }
a71116d1 8973
bbe832c0 8974 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8975
8976 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 8977 err = tg3_nvram_lock(tp);
a71116d1
MC		 8978 tg3_halt_cpu(tp, RX_CPU_BASE);
8979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8980 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 8981 if (!err)
8982 tg3_nvram_unlock(tp);
a71116d1 8983
d9ab5ad1
MC		 8984 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8985 tg3_phy_reset(tp);
8986
a71116d1
MC		 8987 if (tg3_test_registers(tp) != 0) {
8988 etest->flags |= ETH_TEST_FL_FAILED;
8989 data[2] = 1;
8990 }
7942e1db
MC		 8991 if (tg3_test_memory(tp) != 0) {
8992 etest->flags |= ETH_TEST_FL_FAILED;
8993 data[3] = 1;
8994 }
9f40dead 8995 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 8996 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 8997
f47c11ee
DM		 8998 tg3_full_unlock(tp);
8999
d4bc3927
MC		 9000 if (tg3_test_interrupt(tp) != 0) {
9001 etest->flags |= ETH_TEST_FL_FAILED;
9002 data[5] = 1;
9003 }
f47c11ee
DM		 9004
9005 tg3_full_lock(tp, 0);
d4bc3927 9006
a71116d1
MC		 9007 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9008 if (netif_running(dev)) {
9009 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9010 if (!tg3_restart_hw(tp, 1))
9011 tg3_netif_start(tp);
a71116d1 9012 }
f47c11ee
DM		 9013
9014 tg3_full_unlock(tp);
a71116d1 9015 }
bc1c7567
MC		 9016 if (tp->link_config.phy_is_low_power)
9017 tg3_set_power_state(tp, PCI_D3hot);
9018
4cafd3f5
MC		 9019}
9020
1da177e4
LT		 9021static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9022{
9023 struct mii_ioctl_data *data = if_mii(ifr);
9024 struct tg3 *tp = netdev_priv(dev);
9025 int err;
9026
9027 switch(cmd) {
9028 case SIOCGMIIPHY:
9029 data->phy_id = PHY_ADDR;
9030
9031 /* fallthru */
9032 case SIOCGMIIREG: {
9033 u32 mii_regval;
9034
9035 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9036 break; /* We have no PHY */
9037
bc1c7567
MC		 9038 if (tp->link_config.phy_is_low_power)
9039 return -EAGAIN;
9040
f47c11ee 9041 spin_lock_bh(&tp->lock);
1da177e4 9042 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9043 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9044
9045 data->val_out = mii_regval;
9046
9047 return err;
9048 }
9049
9050 case SIOCSMIIREG:
9051 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9052 break; /* We have no PHY */
9053
9054 if (!capable(CAP_NET_ADMIN))
9055 return -EPERM;
9056
bc1c7567
MC		 9057 if (tp->link_config.phy_is_low_power)
9058 return -EAGAIN;
9059
f47c11ee 9060 spin_lock_bh(&tp->lock);
1da177e4 9061 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9062 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9063
9064 return err;
9065
9066 default:
9067 /* do nothing */
9068 break;
9069 }
9070 return -EOPNOTSUPP;
9071}
9072
9073#if TG3_VLAN_TAG_USED
9074static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9075{
9076 struct tg3 *tp = netdev_priv(dev);
9077
29315e87
MC		 9078 if (netif_running(dev))
9079 tg3_netif_stop(tp);
9080
f47c11ee 9081 tg3_full_lock(tp, 0);
1da177e4
LT		 9082
9083 tp->vlgrp = grp;
9084
9085 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9086 __tg3_set_rx_mode(dev);
9087
f47c11ee 9088 tg3_full_unlock(tp);
29315e87
MC		 9089
9090 if (netif_running(dev))
9091 tg3_netif_start(tp);
1da177e4
LT		 9092}
9093
9094static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9095{
9096 struct tg3 *tp = netdev_priv(dev);
9097
29315e87
MC		 9098 if (netif_running(dev))
9099 tg3_netif_stop(tp);
9100
f47c11ee 9101 tg3_full_lock(tp, 0);
1da177e4
LT		 9102 if (tp->vlgrp)
9103 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 9104 tg3_full_unlock(tp);
29315e87
MC		 9105
9106 if (netif_running(dev))
9107 tg3_netif_start(tp);
1da177e4
LT		 9108}
9109#endif
9110
15f9850d
DM		 9111static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9112{
9113 struct tg3 *tp = netdev_priv(dev);
9114
9115 memcpy(ec, &tp->coal, sizeof(*ec));
9116 return 0;
9117}
9118
d244c892
MC		 9119static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9120{
9121 struct tg3 *tp = netdev_priv(dev);
9122 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9123 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9124
9125 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9126 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9127 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9128 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9129 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9130 }
9131
9132 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9133 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9134 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9135 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9136 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9137 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9138 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9139 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9140 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9141 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9142 return -EINVAL;
9143
9144 /* No rx interrupts will be generated if both are zero */
9145 if ((ec->rx_coalesce_usecs == 0) &&
9146 (ec->rx_max_coalesced_frames == 0))
9147 return -EINVAL;
9148
9149 /* No tx interrupts will be generated if both are zero */
9150 if ((ec->tx_coalesce_usecs == 0) &&
9151 (ec->tx_max_coalesced_frames == 0))
9152 return -EINVAL;
9153
9154 /* Only copy relevant parameters, ignore all others. */
9155 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9156 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9157 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9158 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9159 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9160 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9161 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9162 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9163 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9164
9165 if (netif_running(dev)) {
9166 tg3_full_lock(tp, 0);
9167 __tg3_set_coalesce(tp, &tp->coal);
9168 tg3_full_unlock(tp);
9169 }
9170 return 0;
9171}
9172
7282d491 9173static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9174 .get_settings = tg3_get_settings,
9175 .set_settings = tg3_set_settings,
9176 .get_drvinfo = tg3_get_drvinfo,
9177 .get_regs_len = tg3_get_regs_len,
9178 .get_regs = tg3_get_regs,
9179 .get_wol = tg3_get_wol,
9180 .set_wol = tg3_set_wol,
9181 .get_msglevel = tg3_get_msglevel,
9182 .set_msglevel = tg3_set_msglevel,
9183 .nway_reset = tg3_nway_reset,
9184 .get_link = ethtool_op_get_link,
9185 .get_eeprom_len = tg3_get_eeprom_len,
9186 .get_eeprom = tg3_get_eeprom,
9187 .set_eeprom = tg3_set_eeprom,
9188 .get_ringparam = tg3_get_ringparam,
9189 .set_ringparam = tg3_set_ringparam,
9190 .get_pauseparam = tg3_get_pauseparam,
9191 .set_pauseparam = tg3_set_pauseparam,
9192 .get_rx_csum = tg3_get_rx_csum,
9193 .set_rx_csum = tg3_set_rx_csum,
9194 .get_tx_csum = ethtool_op_get_tx_csum,
9195 .set_tx_csum = tg3_set_tx_csum,
9196 .get_sg = ethtool_op_get_sg,
9197 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 9198 .get_tso = ethtool_op_get_tso,
9199 .set_tso = tg3_set_tso,
4cafd3f5
MC		 9200 .self_test_count = tg3_get_test_count,
9201 .self_test = tg3_self_test,
1da177e4 9202 .get_strings = tg3_get_strings,
4009a93d 9203 .phys_id = tg3_phys_id,
1da177e4
LT		 9204 .get_stats_count = tg3_get_stats_count,
9205 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9206 .get_coalesce = tg3_get_coalesce,
d244c892 9207 .set_coalesce = tg3_set_coalesce,
2ff43697 9208 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 9209};
9210
9211static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9212{
1b27777a 9213 u32 cursize, val, magic;
1da177e4
LT		 9214
9215 tp->nvram_size = EEPROM_CHIP_SIZE;
9216
1820180b 9217 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9218 return;
9219
b16250e3
MC		 9220 if ((magic != TG3_EEPROM_MAGIC) &&
9221 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9222 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9223 return;
9224
9225 /*
9226 * Size the chip by reading offsets at increasing powers of two.
9227 * When we encounter our validation signature, we know the addressing
9228 * has wrapped around, and thus have our chip size.
9229 */
1b27777a 9230 cursize = 0x10;
1da177e4
LT		 9231
9232 while (cursize < tp->nvram_size) {
1820180b 9233 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9234 return;
9235
1820180b 9236 if (val == magic)
1da177e4
LT		 9237 break;
9238
9239 cursize <<= 1;
9240 }
9241
9242 tp->nvram_size = cursize;
9243}
6aa20a22 9244
1da177e4
LT		 9245static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9246{
9247 u32 val;
9248
1820180b 9249 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9250 return;
9251
9252 /* Selfboot format */
1820180b 9253 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9254 tg3_get_eeprom_size(tp);
9255 return;
9256 }
9257
1da177e4
LT		 9258 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9259 if (val != 0) {
9260 tp->nvram_size = (val >> 16) * 1024;
9261 return;
9262 }
9263 }
9264 tp->nvram_size = 0x20000;
9265}
9266
9267static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9268{
9269 u32 nvcfg1;
9270
9271 nvcfg1 = tr32(NVRAM_CFG1);
9272 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9273 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9274 }
9275 else {
9276 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9277 tw32(NVRAM_CFG1, nvcfg1);
9278 }
9279
4c987487 9280 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9281 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9282 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9283 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9284 tp->nvram_jedecnum = JEDEC_ATMEL;
9285 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9286 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9287 break;
9288 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9289 tp->nvram_jedecnum = JEDEC_ATMEL;
9290 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9291 break;
9292 case FLASH_VENDOR_ATMEL_EEPROM:
9293 tp->nvram_jedecnum = JEDEC_ATMEL;
9294 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9295 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9296 break;
9297 case FLASH_VENDOR_ST:
9298 tp->nvram_jedecnum = JEDEC_ST;
9299 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9300 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9301 break;
9302 case FLASH_VENDOR_SAIFUN:
9303 tp->nvram_jedecnum = JEDEC_SAIFUN;
9304 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9305 break;
9306 case FLASH_VENDOR_SST_SMALL:
9307 case FLASH_VENDOR_SST_LARGE:
9308 tp->nvram_jedecnum = JEDEC_SST;
9309 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9310 break;
9311 }
9312 }
9313 else {
9314 tp->nvram_jedecnum = JEDEC_ATMEL;
9315 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9316 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9317 }
9318}
9319
361b4ac2
MC		 9320static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9321{
9322 u32 nvcfg1;
9323
9324 nvcfg1 = tr32(NVRAM_CFG1);
9325
e6af301b
MC		 9326 /* NVRAM protection for TPM */
9327 if (nvcfg1 & (1 << 27))
9328 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9329
361b4ac2
MC		 9330 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9331 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9332 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9333 tp->nvram_jedecnum = JEDEC_ATMEL;
9334 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9335 break;
9336 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9337 tp->nvram_jedecnum = JEDEC_ATMEL;
9338 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9339 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9340 break;
9341 case FLASH_5752VENDOR_ST_M45PE10:
9342 case FLASH_5752VENDOR_ST_M45PE20:
9343 case FLASH_5752VENDOR_ST_M45PE40:
9344 tp->nvram_jedecnum = JEDEC_ST;
9345 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9346 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9347 break;
9348 }
9349
9350 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9351 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9352 case FLASH_5752PAGE_SIZE_256:
9353 tp->nvram_pagesize = 256;
9354 break;
9355 case FLASH_5752PAGE_SIZE_512:
9356 tp->nvram_pagesize = 512;
9357 break;
9358 case FLASH_5752PAGE_SIZE_1K:
9359 tp->nvram_pagesize = 1024;
9360 break;
9361 case FLASH_5752PAGE_SIZE_2K:
9362 tp->nvram_pagesize = 2048;
9363 break;
9364 case FLASH_5752PAGE_SIZE_4K:
9365 tp->nvram_pagesize = 4096;
9366 break;
9367 case FLASH_5752PAGE_SIZE_264:
9368 tp->nvram_pagesize = 264;
9369 break;
9370 }
9371 }
9372 else {
9373 /* For eeprom, set pagesize to maximum eeprom size */
9374 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9375
9376 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9377 tw32(NVRAM_CFG1, nvcfg1);
9378 }
9379}
9380
d3c7b886
MC		 9381static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9382{
9383 u32 nvcfg1;
9384
9385 nvcfg1 = tr32(NVRAM_CFG1);
9386
9387 /* NVRAM protection for TPM */
9388 if (nvcfg1 & (1 << 27))
9389 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9390
9391 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9392 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9393 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9394 tp->nvram_jedecnum = JEDEC_ATMEL;
9395 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9396 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9397
9398 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9399 tw32(NVRAM_CFG1, nvcfg1);
9400 break;
9401 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9402 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9403 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9404 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9405 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9406 tp->nvram_jedecnum = JEDEC_ATMEL;
9407 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9408 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9409 tp->nvram_pagesize = 264;
9410 break;
9411 case FLASH_5752VENDOR_ST_M45PE10:
9412 case FLASH_5752VENDOR_ST_M45PE20:
9413 case FLASH_5752VENDOR_ST_M45PE40:
9414 tp->nvram_jedecnum = JEDEC_ST;
9415 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9416 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9417 tp->nvram_pagesize = 256;
9418 break;
9419 }
9420}
9421
1b27777a
MC		 9422static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9423{
9424 u32 nvcfg1;
9425
9426 nvcfg1 = tr32(NVRAM_CFG1);
9427
9428 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9429 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9430 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9431 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9432 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9433 tp->nvram_jedecnum = JEDEC_ATMEL;
9434 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9435 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9436
9437 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9438 tw32(NVRAM_CFG1, nvcfg1);
9439 break;
9440 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9441 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9442 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9443 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9444 tp->nvram_jedecnum = JEDEC_ATMEL;
9445 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9446 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9447 tp->nvram_pagesize = 264;
9448 break;
9449 case FLASH_5752VENDOR_ST_M45PE10:
9450 case FLASH_5752VENDOR_ST_M45PE20:
9451 case FLASH_5752VENDOR_ST_M45PE40:
9452 tp->nvram_jedecnum = JEDEC_ST;
9453 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9454 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9455 tp->nvram_pagesize = 256;
9456 break;
9457 }
9458}
9459
b5d3772c
MC		 9460static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9461{
9462 tp->nvram_jedecnum = JEDEC_ATMEL;
9463 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9464 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9465}
9466
1da177e4
LT		 9467/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9468static void __devinit tg3_nvram_init(struct tg3 *tp)
9469{
1da177e4
LT		 9470 tw32_f(GRC_EEPROM_ADDR,
9471 (EEPROM_ADDR_FSM_RESET |
9472 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9473 EEPROM_ADDR_CLKPERD_SHIFT)));
9474
9d57f01c 9475 msleep(1);
1da177e4
LT		 9476
9477 /* Enable seeprom accesses. */
9478 tw32_f(GRC_LOCAL_CTRL,
9479 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9480 udelay(100);
9481
9482 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9483 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9484 tp->tg3_flags |= TG3_FLAG_NVRAM;
9485
ec41c7df
MC		 9486 if (tg3_nvram_lock(tp)) {
9487 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9488 "tg3_nvram_init failed.\n", tp->dev->name);
9489 return;
9490 }
e6af301b 9491 tg3_enable_nvram_access(tp);
1da177e4 9492
361b4ac2
MC		 9493 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9494 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 9495 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9496 tg3_get_5755_nvram_info(tp);
1b27777a
MC		 9497 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9498 tg3_get_5787_nvram_info(tp);
b5d3772c
MC		 9499 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9500 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 9501 else
9502 tg3_get_nvram_info(tp);
9503
1da177e4
LT		 9504 tg3_get_nvram_size(tp);
9505
e6af301b 9506 tg3_disable_nvram_access(tp);
381291b7 9507 tg3_nvram_unlock(tp);
1da177e4
LT		 9508
9509 } else {
9510 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9511
9512 tg3_get_eeprom_size(tp);
9513 }
9514}
9515
9516static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9517 u32 offset, u32 *val)
9518{
9519 u32 tmp;
9520 int i;
9521
9522 if (offset > EEPROM_ADDR_ADDR_MASK ||
9523 (offset % 4) != 0)
9524 return -EINVAL;
9525
9526 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9527 EEPROM_ADDR_DEVID_MASK |
9528 EEPROM_ADDR_READ);
9529 tw32(GRC_EEPROM_ADDR,
9530 tmp |
9531 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9532 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9533 EEPROM_ADDR_ADDR_MASK) |
9534 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9535
9d57f01c 9536 for (i = 0; i < 1000; i++) {
1da177e4
LT		 9537 tmp = tr32(GRC_EEPROM_ADDR);
9538
9539 if (tmp & EEPROM_ADDR_COMPLETE)
9540 break;
9d57f01c 9541 msleep(1);
1da177e4
LT		 9542 }
9543 if (!(tmp & EEPROM_ADDR_COMPLETE))
9544 return -EBUSY;
9545
9546 *val = tr32(GRC_EEPROM_DATA);
9547 return 0;
9548}
9549
9550#define NVRAM_CMD_TIMEOUT 10000
9551
9552static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9553{
9554 int i;
9555
9556 tw32(NVRAM_CMD, nvram_cmd);
9557 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9558 udelay(10);
9559 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9560 udelay(10);
9561 break;
9562 }
9563 }
9564 if (i == NVRAM_CMD_TIMEOUT) {
9565 return -EBUSY;
9566 }
9567 return 0;
9568}
9569
1820180b
MC		 9570static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9571{
9572 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9573 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9574 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9575 (tp->nvram_jedecnum == JEDEC_ATMEL))
9576
9577 addr = ((addr / tp->nvram_pagesize) <<
9578 ATMEL_AT45DB0X1B_PAGE_POS) +
9579 (addr % tp->nvram_pagesize);
9580
9581 return addr;
9582}
9583
c4e6575c
MC		 9584static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9585{
9586 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9587 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9588 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9589 (tp->nvram_jedecnum == JEDEC_ATMEL))
9590
9591 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9592 tp->nvram_pagesize) +
9593 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9594
9595 return addr;
9596}
9597
1da177e4
LT		 9598static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9599{
9600 int ret;
9601
1da177e4
LT		 9602 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9603 return tg3_nvram_read_using_eeprom(tp, offset, val);
9604
1820180b 9605 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9606
9607 if (offset > NVRAM_ADDR_MSK)
9608 return -EINVAL;
9609
ec41c7df
MC		 9610 ret = tg3_nvram_lock(tp);
9611 if (ret)
9612 return ret;
1da177e4 9613
e6af301b 9614 tg3_enable_nvram_access(tp);
1da177e4
LT		 9615
9616 tw32(NVRAM_ADDR, offset);
9617 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9618 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9619
9620 if (ret == 0)
9621 *val = swab32(tr32(NVRAM_RDDATA));
9622
e6af301b 9623 tg3_disable_nvram_access(tp);
1da177e4 9624
381291b7
MC		 9625 tg3_nvram_unlock(tp);
9626
1da177e4
LT		 9627 return ret;
9628}
9629
1820180b
MC		 9630static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9631{
9632 int err;
9633 u32 tmp;
9634
9635 err = tg3_nvram_read(tp, offset, &tmp);
9636 *val = swab32(tmp);
9637 return err;
9638}
9639
1da177e4
LT		 9640static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9641 u32 offset, u32 len, u8 *buf)
9642{
9643 int i, j, rc = 0;
9644 u32 val;
9645
9646 for (i = 0; i < len; i += 4) {
9647 u32 addr, data;
9648
9649 addr = offset + i;
9650
9651 memcpy(&data, buf + i, 4);
9652
9653 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9654
9655 val = tr32(GRC_EEPROM_ADDR);
9656 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9657
9658 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9659 EEPROM_ADDR_READ);
9660 tw32(GRC_EEPROM_ADDR, val |
9661 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9662 (addr & EEPROM_ADDR_ADDR_MASK) |
9663 EEPROM_ADDR_START |
9664 EEPROM_ADDR_WRITE);
6aa20a22 9665
9d57f01c 9666 for (j = 0; j < 1000; j++) {
1da177e4
LT		 9667 val = tr32(GRC_EEPROM_ADDR);
9668
9669 if (val & EEPROM_ADDR_COMPLETE)
9670 break;
9d57f01c 9671 msleep(1);
1da177e4
LT		 9672 }
9673 if (!(val & EEPROM_ADDR_COMPLETE)) {
9674 rc = -EBUSY;
9675 break;
9676 }
9677 }
9678
9679 return rc;
9680}
9681
9682/* offset and length are dword aligned */
9683static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9684 u8 *buf)
9685{
9686 int ret = 0;
9687 u32 pagesize = tp->nvram_pagesize;
9688 u32 pagemask = pagesize - 1;
9689 u32 nvram_cmd;
9690 u8 *tmp;
9691
9692 tmp = kmalloc(pagesize, GFP_KERNEL);
9693 if (tmp == NULL)
9694 return -ENOMEM;
9695
9696 while (len) {
9697 int j;
e6af301b 9698 u32 phy_addr, page_off, size;
1da177e4
LT		 9699
9700 phy_addr = offset & ~pagemask;
6aa20a22 9701
1da177e4
LT		 9702 for (j = 0; j < pagesize; j += 4) {
9703 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9704 (u32 *) (tmp + j))))
9705 break;
9706 }
9707 if (ret)
9708 break;
9709
9710 page_off = offset & pagemask;
9711 size = pagesize;
9712 if (len < size)
9713 size = len;
9714
9715 len -= size;
9716
9717 memcpy(tmp + page_off, buf, size);
9718
9719 offset = offset + (pagesize - page_off);
9720
e6af301b 9721 tg3_enable_nvram_access(tp);
1da177e4
LT		 9722
9723 /*
9724 * Before we can erase the flash page, we need
9725 * to issue a special "write enable" command.
9726 */
9727 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9728
9729 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9730 break;
9731
9732 /* Erase the target page */
9733 tw32(NVRAM_ADDR, phy_addr);
9734
9735 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9736 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9737
9738 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9739 break;
9740
9741 /* Issue another write enable to start the write. */
9742 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9743
9744 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9745 break;
9746
9747 for (j = 0; j < pagesize; j += 4) {
9748 u32 data;
9749
9750 data = *((u32 *) (tmp + j));
9751 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9752
9753 tw32(NVRAM_ADDR, phy_addr + j);
9754
9755 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9756 NVRAM_CMD_WR;
9757
9758 if (j == 0)
9759 nvram_cmd |= NVRAM_CMD_FIRST;
9760 else if (j == (pagesize - 4))
9761 nvram_cmd |= NVRAM_CMD_LAST;
9762
9763 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9764 break;
9765 }
9766 if (ret)
9767 break;
9768 }
9769
9770 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9771 tg3_nvram_exec_cmd(tp, nvram_cmd);
9772
9773 kfree(tmp);
9774
9775 return ret;
9776}
9777
9778/* offset and length are dword aligned */
9779static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9780 u8 *buf)
9781{
9782 int i, ret = 0;
9783
9784 for (i = 0; i < len; i += 4, offset += 4) {
9785 u32 data, page_off, phy_addr, nvram_cmd;
9786
9787 memcpy(&data, buf + i, 4);
9788 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9789
9790 page_off = offset % tp->nvram_pagesize;
9791
1820180b 9792 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9793
9794 tw32(NVRAM_ADDR, phy_addr);
9795
9796 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9797
9798 if ((page_off == 0) || (i == 0))
9799 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 9800 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 9801 nvram_cmd |= NVRAM_CMD_LAST;
9802
9803 if (i == (len - 4))
9804 nvram_cmd |= NVRAM_CMD_LAST;
9805
4c987487 9806 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 9807 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 9808 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
4c987487
MC		 9809 (tp->nvram_jedecnum == JEDEC_ST) &&
9810 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 9811
9812 if ((ret = tg3_nvram_exec_cmd(tp,
9813 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9814 NVRAM_CMD_DONE)))
9815
9816 break;
9817 }
9818 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9819 /* We always do complete word writes to eeprom. */
9820 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9821 }
9822
9823 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9824 break;
9825 }
9826 return ret;
9827}
9828
9829/* offset and length are dword aligned */
9830static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9831{
9832 int ret;
9833
1da177e4 9834 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 9835 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9836 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 9837 udelay(40);
9838 }
9839
9840 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9841 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9842 }
9843 else {
9844 u32 grc_mode;
9845
ec41c7df
MC		 9846 ret = tg3_nvram_lock(tp);
9847 if (ret)
9848 return ret;
1da177e4 9849
e6af301b
MC		 9850 tg3_enable_nvram_access(tp);
9851 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9852 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 9853 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 9854
9855 grc_mode = tr32(GRC_MODE);
9856 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9857
9858 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9859 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9860
9861 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9862 buf);
9863 }
9864 else {
9865 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9866 buf);
9867 }
9868
9869 grc_mode = tr32(GRC_MODE);
9870 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9871
e6af301b 9872 tg3_disable_nvram_access(tp);
1da177e4
LT		 9873 tg3_nvram_unlock(tp);
9874 }
9875
9876 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 9877 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 9878 udelay(40);
9879 }
9880
9881 return ret;
9882}
9883
9884struct subsys_tbl_ent {
9885 u16 subsys_vendor, subsys_devid;
9886 u32 phy_id;
9887};
9888
9889static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9890 /* Broadcom boards. */
9891 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9892 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9893 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9894 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9895 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9896 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9897 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9898 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9899 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9900 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9901 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9902
9903 /* 3com boards. */
9904 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9905 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9906 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9907 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9908 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9909
9910 /* DELL boards. */
9911 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9912 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9913 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9914 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9915
9916 /* Compaq boards. */
9917 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9918 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9919 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9920 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9921 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9922
9923 /* IBM boards. */
9924 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9925};
9926
9927static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9928{
9929 int i;
9930
9931 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9932 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9933 tp->pdev->subsystem_vendor) &&
9934 (subsys_id_to_phy_id[i].subsys_devid ==
9935 tp->pdev->subsystem_device))
9936 return &subsys_id_to_phy_id[i];
9937 }
9938 return NULL;
9939}
9940
7d0c41ef 9941static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9942{
1da177e4 9943 u32 val;
caf636c7
MC		 9944 u16 pmcsr;
9945
9946 /* On some early chips the SRAM cannot be accessed in D3hot state,
9947 * so need make sure we're in D0.
9948 */
9949 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9950 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9951 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9952 msleep(1);
7d0c41ef
MC		 9953
9954 /* Make sure register accesses (indirect or otherwise)
9955 * will function correctly.
9956 */
9957 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9958 tp->misc_host_ctrl);
1da177e4 9959
f49639e6
DM		 9960 /* The memory arbiter has to be enabled in order for SRAM accesses
9961 * to succeed. Normally on powerup the tg3 chip firmware will make
9962 * sure it is enabled, but other entities such as system netboot
9963 * code might disable it.
9964 */
9965 val = tr32(MEMARB_MODE);
9966 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9967
1da177e4 9968 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 9969 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9970
f49639e6
DM		 9971 /* Assume an onboard device by default. */
9972 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
72b845e0 9973
b5d3772c 9974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 9975 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 9976 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 9977 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9978 }
b5d3772c
MC		 9979 return;
9980 }
9981
1da177e4
LT		 9982 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9983 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9984 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 9985 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9986 int eeprom_phy_serdes = 0;
1da177e4
LT		 9987
9988 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9989 tp->nic_sram_data_cfg = nic_cfg;
9990
9991 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9992 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9993 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9994 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9995 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9996 (ver > 0) && (ver < 0x100))
9997 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9998
1da177e4
LT		 9999 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10000 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10001 eeprom_phy_serdes = 1;
10002
10003 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10004 if (nic_phy_id != 0) {
10005 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10006 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10007
10008 eeprom_phy_id = (id1 >> 16) << 10;
10009 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10010 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10011 } else
10012 eeprom_phy_id = 0;
10013
7d0c41ef 10014 tp->phy_id = eeprom_phy_id;
747e8f8b 10015 if (eeprom_phy_serdes) {
a4e2b347 10016 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10017 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10018 else
10019 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10020 }
7d0c41ef 10021
cbf46853 10022 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10023 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10024 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10025 else
1da177e4
LT		 10026 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10027
10028 switch (led_cfg) {
10029 default:
10030 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10031 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10032 break;
10033
10034 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10035 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10036 break;
10037
10038 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10039 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10040
10041 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10042 * read on some older 5700/5701 bootcode.
10043 */
10044 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10045 ASIC_REV_5700 ||
10046 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10047 ASIC_REV_5701)
10048 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10049
1da177e4
LT		 10050 break;
10051
10052 case SHASTA_EXT_LED_SHARED:
10053 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10054 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10055 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10056 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10057 LED_CTRL_MODE_PHY_2);
10058 break;
10059
10060 case SHASTA_EXT_LED_MAC:
10061 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10062 break;
10063
10064 case SHASTA_EXT_LED_COMBO:
10065 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10066 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10067 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10068 LED_CTRL_MODE_PHY_2);
10069 break;
10070
10071 };
10072
10073 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10075 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10076 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10077
9d26e213 10078 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10079 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10080 if ((tp->pdev->subsystem_vendor ==
10081 PCI_VENDOR_ID_ARIMA) &&
10082 (tp->pdev->subsystem_device == 0x205a ||
10083 tp->pdev->subsystem_device == 0x2063))
10084 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10085 } else {
f49639e6 10086 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10087 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10088 }
1da177e4
LT		 10089
10090 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10091 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10092 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10093 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10094 }
10095 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10096 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10097
10098 if (cfg2 & (1 << 17))
10099 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10100
10101 /* serdes signal pre-emphasis in register 0x590 set by */
10102 /* bootcode if bit 18 is set */
10103 if (cfg2 & (1 << 18))
10104 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10105 }
7d0c41ef
MC		 10106}
10107
10108static int __devinit tg3_phy_probe(struct tg3 *tp)
10109{
10110 u32 hw_phy_id_1, hw_phy_id_2;
10111 u32 hw_phy_id, hw_phy_id_masked;
10112 int err;
1da177e4
LT		 10113
10114 /* Reading the PHY ID register can conflict with ASF
10115 * firwmare access to the PHY hardware.
10116 */
10117 err = 0;
10118 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10119 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10120 } else {
10121 /* Now read the physical PHY_ID from the chip and verify
10122 * that it is sane. If it doesn't look good, we fall back
10123 * to either the hard-coded table based PHY_ID and failing
10124 * that the value found in the eeprom area.
10125 */
10126 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10127 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10128
10129 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10130 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10131 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10132
10133 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10134 }
10135
10136 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10137 tp->phy_id = hw_phy_id;
10138 if (hw_phy_id_masked == PHY_ID_BCM8002)
10139 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10140 else
10141 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10142 } else {
7d0c41ef
MC		 10143 if (tp->phy_id != PHY_ID_INVALID) {
10144 /* Do nothing, phy ID already set up in
10145 * tg3_get_eeprom_hw_cfg().
10146 */
1da177e4
LT		 10147 } else {
10148 struct subsys_tbl_ent *p;
10149
10150 /* No eeprom signature? Try the hardcoded
10151 * subsys device table.
10152 */
10153 p = lookup_by_subsys(tp);
10154 if (!p)
10155 return -ENODEV;
10156
10157 tp->phy_id = p->phy_id;
10158 if (!tp->phy_id ||
10159 tp->phy_id == PHY_ID_BCM8002)
10160 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10161 }
10162 }
10163
747e8f8b 10164 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4 10165 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10166 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10167
10168 tg3_readphy(tp, MII_BMSR, &bmsr);
10169 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10170 (bmsr & BMSR_LSTATUS))
10171 goto skip_phy_reset;
6aa20a22 10172
1da177e4
LT		 10173 err = tg3_phy_reset(tp);
10174 if (err)
10175 return err;
10176
10177 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10178 ADVERTISE_100HALF | ADVERTISE_100FULL |
10179 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10180 tg3_ctrl = 0;
10181 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10182 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10183 MII_TG3_CTRL_ADV_1000_FULL);
10184 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10185 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10186 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10187 MII_TG3_CTRL_ENABLE_AS_MASTER);
10188 }
10189
3600d918
MC		 10190 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10191 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10192 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10193 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10194 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10195
10196 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10197 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10198
10199 tg3_writephy(tp, MII_BMCR,
10200 BMCR_ANENABLE | BMCR_ANRESTART);
10201 }
10202 tg3_phy_set_wirespeed(tp);
10203
10204 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10205 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10206 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10207 }
10208
10209skip_phy_reset:
10210 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10211 err = tg3_init_5401phy_dsp(tp);
10212 if (err)
10213 return err;
10214 }
10215
10216 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10217 err = tg3_init_5401phy_dsp(tp);
10218 }
10219
747e8f8b 10220 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10221 tp->link_config.advertising =
10222 (ADVERTISED_1000baseT_Half |
10223 ADVERTISED_1000baseT_Full |
10224 ADVERTISED_Autoneg |
10225 ADVERTISED_FIBRE);
10226 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10227 tp->link_config.advertising &=
10228 ~(ADVERTISED_1000baseT_Half |
10229 ADVERTISED_1000baseT_Full);
10230
10231 return err;
10232}
10233
10234static void __devinit tg3_read_partno(struct tg3 *tp)
10235{
10236 unsigned char vpd_data[256];
af2c6a4a 10237 unsigned int i;
1b27777a 10238 u32 magic;
1da177e4 10239
1820180b 10240 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10241 goto out_not_found;
1da177e4 10242
1820180b 10243 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10244 for (i = 0; i < 256; i += 4) {
10245 u32 tmp;
1da177e4 10246
1b27777a
MC		 10247 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10248 goto out_not_found;
10249
10250 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10251 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10252 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10253 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10254 }
10255 } else {
10256 int vpd_cap;
10257
10258 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10259 for (i = 0; i < 256; i += 4) {
10260 u32 tmp, j = 0;
10261 u16 tmp16;
10262
10263 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10264 i);
10265 while (j++ < 100) {
10266 pci_read_config_word(tp->pdev, vpd_cap +
10267 PCI_VPD_ADDR, &tmp16);
10268 if (tmp16 & 0x8000)
10269 break;
10270 msleep(1);
10271 }
f49639e6
DM		 10272 if (!(tmp16 & 0x8000))
10273 goto out_not_found;
10274
1b27777a
MC		 10275 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10276 &tmp);
10277 tmp = cpu_to_le32(tmp);
10278 memcpy(&vpd_data[i], &tmp, 4);
10279 }
1da177e4
LT		 10280 }
10281
10282 /* Now parse and find the part number. */
af2c6a4a 10283 for (i = 0; i < 254; ) {
1da177e4 10284 unsigned char val = vpd_data[i];
af2c6a4a 10285 unsigned int block_end;
1da177e4
LT		 10286
10287 if (val == 0x82 || val == 0x91) {
10288 i = (i + 3 +
10289 (vpd_data[i + 1] +
10290 (vpd_data[i + 2] << 8)));
10291 continue;
10292 }
10293
10294 if (val != 0x90)
10295 goto out_not_found;
10296
10297 block_end = (i + 3 +
10298 (vpd_data[i + 1] +
10299 (vpd_data[i + 2] << 8)));
10300 i += 3;
af2c6a4a
MC		 10301
10302 if (block_end > 256)
10303 goto out_not_found;
10304
10305 while (i < (block_end - 2)) {
1da177e4
LT		 10306 if (vpd_data[i + 0] == 'P' &&
10307 vpd_data[i + 1] == 'N') {
10308 int partno_len = vpd_data[i + 2];
10309
af2c6a4a
MC		 10310 i += 3;
10311 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10312 goto out_not_found;
10313
10314 memcpy(tp->board_part_number,
af2c6a4a 10315 &vpd_data[i], partno_len);
1da177e4
LT		 10316
10317 /* Success. */
10318 return;
10319 }
af2c6a4a 10320 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10321 }
10322
10323 /* Part number not found. */
10324 goto out_not_found;
10325 }
10326
10327out_not_found:
b5d3772c
MC		 10328 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10329 strcpy(tp->board_part_number, "BCM95906");
10330 else
10331 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10332}
10333
c4e6575c
MC		 10334static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10335{
10336 u32 val, offset, start;
10337
10338 if (tg3_nvram_read_swab(tp, 0, &val))
10339 return;
10340
10341 if (val != TG3_EEPROM_MAGIC)
10342 return;
10343
10344 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10345 tg3_nvram_read_swab(tp, 0x4, &start))
10346 return;
10347
10348 offset = tg3_nvram_logical_addr(tp, offset);
10349 if (tg3_nvram_read_swab(tp, offset, &val))
10350 return;
10351
10352 if ((val & 0xfc000000) == 0x0c000000) {
10353 u32 ver_offset, addr;
10354 int i;
10355
10356 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10357 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10358 return;
10359
10360 if (val != 0)
10361 return;
10362
10363 addr = offset + ver_offset - start;
10364 for (i = 0; i < 16; i += 4) {
10365 if (tg3_nvram_read(tp, addr + i, &val))
10366 return;
10367
10368 val = cpu_to_le32(val);
10369 memcpy(tp->fw_ver + i, &val, 4);
10370 }
10371 }
10372}
10373
1da177e4
LT		 10374static int __devinit tg3_get_invariants(struct tg3 *tp)
10375{
10376 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 10377 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10378 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 10379 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10380 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 10381 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10382 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 10383 { },
10384 };
10385 u32 misc_ctrl_reg;
10386 u32 cacheline_sz_reg;
10387 u32 pci_state_reg, grc_misc_cfg;
10388 u32 val;
10389 u16 pci_cmd;
c7835a77 10390 int err, pcie_cap;
1da177e4 10391
1da177e4
LT		 10392 /* Force memory write invalidate off. If we leave it on,
10393 * then on 5700_BX chips we have to enable a workaround.
10394 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10395 * to match the cacheline size. The Broadcom driver have this
10396 * workaround but turns MWI off all the times so never uses
10397 * it. This seems to suggest that the workaround is insufficient.
10398 */
10399 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10400 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10401 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10402
10403 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10404 * has the register indirect write enable bit set before
10405 * we try to access any of the MMIO registers. It is also
10406 * critical that the PCI-X hw workaround situation is decided
10407 * before that as well.
10408 */
10409 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10410 &misc_ctrl_reg);
10411
10412 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10413 MISC_HOST_CTRL_CHIPREV_SHIFT);
10414
ff645bec
MC		 10415 /* Wrong chip ID in 5752 A0. This code can be removed later
10416 * as A0 is not in production.
10417 */
10418 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10419 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10420
6892914f
MC		 10421 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10422 * we need to disable memory and use config. cycles
10423 * only to access all registers. The 5702/03 chips
10424 * can mistakenly decode the special cycles from the
10425 * ICH chipsets as memory write cycles, causing corruption
10426 * of register and memory space. Only certain ICH bridges
10427 * will drive special cycles with non-zero data during the
10428 * address phase which can fall within the 5703's address
10429 * range. This is not an ICH bug as the PCI spec allows
10430 * non-zero address during special cycles. However, only
10431 * these ICH bridges are known to drive non-zero addresses
10432 * during special cycles.
10433 *
10434 * Since special cycles do not cross PCI bridges, we only
10435 * enable this workaround if the 5703 is on the secondary
10436 * bus of these ICH bridges.
10437 */
10438 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10439 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10440 static struct tg3_dev_id {
10441 u32 vendor;
10442 u32 device;
10443 u32 rev;
10444 } ich_chipsets[] = {
10445 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10446 PCI_ANY_ID },
10447 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10448 PCI_ANY_ID },
10449 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10450 0xa },
10451 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10452 PCI_ANY_ID },
10453 { },
10454 };
10455 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10456 struct pci_dev *bridge = NULL;
10457
10458 while (pci_id->vendor != 0) {
10459 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10460 bridge);
10461 if (!bridge) {
10462 pci_id++;
10463 continue;
10464 }
10465 if (pci_id->rev != PCI_ANY_ID) {
10466 u8 rev;
10467
10468 pci_read_config_byte(bridge, PCI_REVISION_ID,
10469 &rev);
10470 if (rev > pci_id->rev)
10471 continue;
10472 }
10473 if (bridge->subordinate &&
10474 (bridge->subordinate->number ==
10475 tp->pdev->bus->number)) {
10476
10477 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10478 pci_dev_put(bridge);
10479 break;
10480 }
10481 }
10482 }
10483
4a29cc2e
MC		 10484 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10485 * DMA addresses > 40-bit. This bridge may have other additional
10486 * 57xx devices behind it in some 4-port NIC designs for example.
10487 * Any tg3 device found behind the bridge will also need the 40-bit
10488 * DMA workaround.
10489 */
a4e2b347
MC		 10490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10491 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10492 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 10493 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 10494 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 10495 }
4a29cc2e
MC		 10496 else {
10497 struct pci_dev *bridge = NULL;
10498
10499 do {
10500 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10501 PCI_DEVICE_ID_SERVERWORKS_EPB,
10502 bridge);
10503 if (bridge && bridge->subordinate &&
10504 (bridge->subordinate->number <=
10505 tp->pdev->bus->number) &&
10506 (bridge->subordinate->subordinate >=
10507 tp->pdev->bus->number)) {
10508 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10509 pci_dev_put(bridge);
10510 break;
10511 }
10512 } while (bridge);
10513 }
4cf78e4f 10514
1da177e4
LT		 10515 /* Initialize misc host control in PCI block. */
10516 tp->misc_host_ctrl |= (misc_ctrl_reg &
10517 MISC_HOST_CTRL_CHIPREV);
10518 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10519 tp->misc_host_ctrl);
10520
10521 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10522 &cacheline_sz_reg);
10523
10524 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10525 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10526 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10527 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10528
6708e5cc 10529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 10530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 10531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 10532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
b5d3772c 10533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 10534 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 10535 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10536
1b440c56
JL		 10537 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10538 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10539 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10540
5a6f3074 10541 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
af36e6b6 10542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10543 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10544 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 10545 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 10546 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83
MC		 10547 } else {
10548 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10549 TG3_FLG2_HW_TSO_1_BUG;
10550 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10551 ASIC_REV_5750 &&
10552 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10553 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10554 }
5a6f3074 10555 }
1da177e4 10556
0f893dc6
MC		 10557 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10558 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 10559 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 10560 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c
MC		 10561 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10562 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 10563 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10564
c7835a77
MC		 10565 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10566 if (pcie_cap != 0) {
1da177e4 10567 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 10568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10569 u16 lnkctl;
10570
10571 pci_read_config_word(tp->pdev,
10572 pcie_cap + PCI_EXP_LNKCTL,
10573 &lnkctl);
10574 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10575 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10576 }
10577 }
1da177e4 10578
399de50b
MC		 10579 /* If we have an AMD 762 or VIA K8T800 chipset, write
10580 * reordering to the mailbox registers done by the host
10581 * controller can cause major troubles. We read back from
10582 * every mailbox register write to force the writes to be
10583 * posted to the chip in order.
10584 */
10585 if (pci_dev_present(write_reorder_chipsets) &&
10586 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10587 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10588
1da177e4
LT		 10589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10590 tp->pci_lat_timer < 64) {
10591 tp->pci_lat_timer = 64;
10592
10593 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10594 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10595 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10596 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10597
10598 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10599 cacheline_sz_reg);
10600 }
10601
10602 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10603 &pci_state_reg);
10604
10605 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10606 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10607
10608 /* If this is a 5700 BX chipset, and we are in PCI-X
10609 * mode, enable register write workaround.
10610 *
10611 * The workaround is to use indirect register accesses
10612 * for all chip writes not to mailbox registers.
10613 */
10614 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10615 u32 pm_reg;
10616 u16 pci_cmd;
10617
10618 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10619
10620 /* The chip can have it's power management PCI config
10621 * space registers clobbered due to this bug.
10622 * So explicitly force the chip into D0 here.
10623 */
10624 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10625 &pm_reg);
10626 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10627 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10628 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10629 pm_reg);
10630
10631 /* Also, force SERR#/PERR# in PCI command. */
10632 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10633 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10634 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10635 }
10636 }
10637
087fe256
MC		 10638 /* 5700 BX chips need to have their TX producer index mailboxes
10639 * written twice to workaround a bug.
10640 */
10641 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10642 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10643
1da177e4
LT		 10644 /* Back to back register writes can cause problems on this chip,
10645 * the workaround is to read back all reg writes except those to
10646 * mailbox regs. See tg3_write_indirect_reg32().
10647 *
10648 * PCI Express 5750_A0 rev chips need this workaround too.
10649 */
10650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10651 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10652 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10653 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10654
10655 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10656 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10657 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10658 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10659
10660 /* Chip-specific fixup from Broadcom driver */
10661 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10662 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10663 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10664 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10665 }
10666
1ee582d8 10667 /* Default fast path register access methods */
20094930 10668 tp->read32 = tg3_read32;
1ee582d8 10669 tp->write32 = tg3_write32;
09ee929c 10670 tp->read32_mbox = tg3_read32;
20094930 10671 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 10672 tp->write32_tx_mbox = tg3_write32;
10673 tp->write32_rx_mbox = tg3_write32;
10674
10675 /* Various workaround register access methods */
10676 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10677 tp->write32 = tg3_write_indirect_reg32;
10678 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10679 tp->write32 = tg3_write_flush_reg32;
10680
10681 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10682 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10683 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10684 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10685 tp->write32_rx_mbox = tg3_write_flush_reg32;
10686 }
20094930 10687
6892914f
MC		 10688 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10689 tp->read32 = tg3_read_indirect_reg32;
10690 tp->write32 = tg3_write_indirect_reg32;
10691 tp->read32_mbox = tg3_read_indirect_mbox;
10692 tp->write32_mbox = tg3_write_indirect_mbox;
10693 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10694 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10695
10696 iounmap(tp->regs);
22abe310 10697 tp->regs = NULL;
6892914f
MC		 10698
10699 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10700 pci_cmd &= ~PCI_COMMAND_MEMORY;
10701 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10702 }
b5d3772c
MC		 10703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10704 tp->read32_mbox = tg3_read32_mbox_5906;
10705 tp->write32_mbox = tg3_write32_mbox_5906;
10706 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10707 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10708 }
6892914f 10709
bbadf503
MC		 10710 if (tp->write32 == tg3_write_indirect_reg32 ||
10711 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10712 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 10713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 10714 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10715
7d0c41ef 10716 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 10717 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 10718 * determined before calling tg3_set_power_state() so that
10719 * we know whether or not to switch out of Vaux power.
10720 * When the flag is set, it means that GPIO1 is used for eeprom
10721 * write protect and also implies that it is a LOM where GPIOs
10722 * are not used to switch power.
6aa20a22 10723 */
7d0c41ef
MC		 10724 tg3_get_eeprom_hw_cfg(tp);
10725
314fba34
MC		 10726 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10727 * GPIO1 driven high will bring 5700's external PHY out of reset.
10728 * It is also used as eeprom write protect on LOMs.
10729 */
10730 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10731 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10732 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10733 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10734 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 10735 /* Unused GPIO3 must be driven as output on 5752 because there
10736 * are no pull-up resistors on unused GPIO pins.
10737 */
10738 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10739 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 10740
af36e6b6
MC		 10741 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10742 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10743
1da177e4 10744 /* Force the chip into D0. */
bc1c7567 10745 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 10746 if (err) {
10747 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10748 pci_name(tp->pdev));
10749 return err;
10750 }
10751
10752 /* 5700 B0 chips do not support checksumming correctly due
10753 * to hardware bugs.
10754 */
10755 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10756 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10757
1da177e4
LT		 10758 /* Derive initial jumbo mode from MTU assigned in
10759 * ether_setup() via the alloc_etherdev() call
10760 */
0f893dc6 10761 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 10762 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 10763 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 10764
10765 /* Determine WakeOnLan speed to use. */
10766 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10767 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10768 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10769 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10770 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10771 } else {
10772 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10773 }
10774
10775 /* A few boards don't want Ethernet@WireSpeed phy feature */
10776 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10777 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10778 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 10779 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 10780 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 10781 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 10782 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10783
10784 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10785 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10786 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10787 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10788 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10789
c424cb24
MC		 10790 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
c1d2a196 10792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
d4011ada
MC		 10793 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10794 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10795 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 10796 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10797 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10798 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 10799 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10800 }
1da177e4 10801
1da177e4 10802 tp->coalesce_mode = 0;
1da177e4
LT		 10803 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10804 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10805 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10806
10807 /* Initialize MAC MI mode, polling disabled. */
10808 tw32_f(MAC_MI_MODE, tp->mi_mode);
10809 udelay(80);
10810
10811 /* Initialize data/descriptor byte/word swapping. */
10812 val = tr32(GRC_MODE);
10813 val &= GRC_MODE_HOST_STACKUP;
10814 tw32(GRC_MODE, val | tp->grc_mode);
10815
10816 tg3_switch_clocks(tp);
10817
10818 /* Clear this out for sanity. */
10819 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10820
10821 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10822 &pci_state_reg);
10823 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10824 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10825 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10826
10827 if (chiprevid == CHIPREV_ID_5701_A0 ||
10828 chiprevid == CHIPREV_ID_5701_B0 ||
10829 chiprevid == CHIPREV_ID_5701_B2 ||
10830 chiprevid == CHIPREV_ID_5701_B5) {
10831 void __iomem *sram_base;
10832
10833 /* Write some dummy words into the SRAM status block
10834 * area, see if it reads back correctly. If the return
10835 * value is bad, force enable the PCIX workaround.
10836 */
10837 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10838
10839 writel(0x00000000, sram_base);
10840 writel(0x00000000, sram_base + 4);
10841 writel(0xffffffff, sram_base + 4);
10842 if (readl(sram_base) != 0x00000000)
10843 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10844 }
10845 }
10846
10847 udelay(50);
10848 tg3_nvram_init(tp);
10849
10850 grc_misc_cfg = tr32(GRC_MISC_CFG);
10851 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10852
10853 /* Broadcom's driver says that CIOBE multisplit has a bug */
10854#if 0
10855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10856 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10857 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10858 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10859 }
10860#endif
10861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10862 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10863 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10864 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10865
fac9b83e
DM		 10866 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10867 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10868 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10869 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10870 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10871 HOSTCC_MODE_CLRTICK_TXBD);
10872
10873 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10874 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10875 tp->misc_host_ctrl);
10876 }
10877
1da177e4
LT		 10878 /* these are limited to 10/100 only */
10879 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10880 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10881 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10882 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10883 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10884 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10885 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10886 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10887 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 10888 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10889 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 10890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 10891 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10892
10893 err = tg3_phy_probe(tp);
10894 if (err) {
10895 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10896 pci_name(tp->pdev), err);
10897 /* ... but do not return immediately ... */
10898 }
10899
10900 tg3_read_partno(tp);
c4e6575c 10901 tg3_read_fw_ver(tp);
1da177e4
LT		 10902
10903 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10904 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10905 } else {
10906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10907 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10908 else
10909 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10910 }
10911
10912 /* 5700 {AX,BX} chips have a broken status block link
10913 * change bit implementation, so we must use the
10914 * status register in those cases.
10915 */
10916 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10917 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10918 else
10919 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10920
10921 /* The led_ctrl is set during tg3_phy_probe, here we might
10922 * have to force the link status polling mechanism based
10923 * upon subsystem IDs.
10924 */
10925 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10926 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10927 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10928 TG3_FLAG_USE_LINKCHG_REG);
10929 }
10930
10931 /* For all SERDES we poll the MAC status register. */
10932 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10933 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10934 else
10935 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10936
5a6f3074 10937 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 10938 * straddle the 4GB address boundary in some cases.
10939 */
af36e6b6 10940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 10943 tp->dev->hard_start_xmit = tg3_start_xmit;
10944 else
10945 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 10946
10947 tp->rx_offset = 2;
10948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10949 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10950 tp->rx_offset = 0;
10951
f92905de
MC		 10952 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10953
10954 /* Increment the rx prod index on the rx std ring by at most
10955 * 8 for these chips to workaround hw errata.
10956 */
10957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10960 tp->rx_std_max_post = 8;
10961
1da177e4
LT		 10962 /* By default, disable wake-on-lan. User can change this
10963 * using ETHTOOL_SWOL.
10964 */
10965 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10966
10967 return err;
10968}
10969
10970#ifdef CONFIG_SPARC64
10971static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10972{
10973 struct net_device *dev = tp->dev;
10974 struct pci_dev *pdev = tp->pdev;
10975 struct pcidev_cookie *pcp = pdev->sysdata;
10976
10977 if (pcp != NULL) {
de8d28b1
DM		 10978 unsigned char *addr;
10979 int len;
1da177e4 10980
de8d28b1
DM		 10981 addr = of_get_property(pcp->prom_node, "local-mac-address",
10982 &len);
10983 if (addr && len == 6) {
10984 memcpy(dev->dev_addr, addr, 6);
2ff43697 10985 memcpy(dev->perm_addr, dev->dev_addr, 6);
1da177e4
LT		 10986 return 0;
10987 }
10988 }
10989 return -ENODEV;
10990}
10991
10992static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10993{
10994 struct net_device *dev = tp->dev;
10995
10996 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 10997 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 10998 return 0;
10999}
11000#endif
11001
11002static int __devinit tg3_get_device_address(struct tg3 *tp)
11003{
11004 struct net_device *dev = tp->dev;
11005 u32 hi, lo, mac_offset;
008652b3 11006 int addr_ok = 0;
1da177e4
LT		 11007
11008#ifdef CONFIG_SPARC64
11009 if (!tg3_get_macaddr_sparc(tp))
11010 return 0;
11011#endif
11012
11013 mac_offset = 0x7c;
f49639e6 11014 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11015 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11016 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11017 mac_offset = 0xcc;
11018 if (tg3_nvram_lock(tp))
11019 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11020 else
11021 tg3_nvram_unlock(tp);
11022 }
b5d3772c
MC		 11023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11024 mac_offset = 0x10;
1da177e4
LT		 11025
11026 /* First try to get it from MAC address mailbox. */
11027 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11028 if ((hi >> 16) == 0x484b) {
11029 dev->dev_addr[0] = (hi >> 8) & 0xff;
11030 dev->dev_addr[1] = (hi >> 0) & 0xff;
11031
11032 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11033 dev->dev_addr[2] = (lo >> 24) & 0xff;
11034 dev->dev_addr[3] = (lo >> 16) & 0xff;
11035 dev->dev_addr[4] = (lo >> 8) & 0xff;
11036 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11037
008652b3
MC		 11038 /* Some old bootcode may report a 0 MAC address in SRAM */
11039 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11040 }
11041 if (!addr_ok) {
11042 /* Next, try NVRAM. */
f49639e6 11043 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11044 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11045 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11046 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11047 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11048 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11049 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11050 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11051 }
11052 /* Finally just fetch it out of the MAC control regs. */
11053 else {
11054 hi = tr32(MAC_ADDR_0_HIGH);
11055 lo = tr32(MAC_ADDR_0_LOW);
11056
11057 dev->dev_addr[5] = lo & 0xff;
11058 dev->dev_addr[4] = (lo >> 8) & 0xff;
11059 dev->dev_addr[3] = (lo >> 16) & 0xff;
11060 dev->dev_addr[2] = (lo >> 24) & 0xff;
11061 dev->dev_addr[1] = hi & 0xff;
11062 dev->dev_addr[0] = (hi >> 8) & 0xff;
11063 }
1da177e4
LT		 11064 }
11065
11066 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11067#ifdef CONFIG_SPARC64
11068 if (!tg3_get_default_macaddr_sparc(tp))
11069 return 0;
11070#endif
11071 return -EINVAL;
11072 }
2ff43697 11073 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11074 return 0;
11075}
11076
59e6b434
DM		 11077#define BOUNDARY_SINGLE_CACHELINE 1
11078#define BOUNDARY_MULTI_CACHELINE 2
11079
11080static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11081{
11082 int cacheline_size;
11083 u8 byte;
11084 int goal;
11085
11086 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11087 if (byte == 0)
11088 cacheline_size = 1024;
11089 else
11090 cacheline_size = (int) byte * 4;
11091
11092 /* On 5703 and later chips, the boundary bits have no
11093 * effect.
11094 */
11095 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11096 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11097 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11098 goto out;
11099
11100#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11101 goal = BOUNDARY_MULTI_CACHELINE;
11102#else
11103#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11104 goal = BOUNDARY_SINGLE_CACHELINE;
11105#else
11106 goal = 0;
11107#endif
11108#endif
11109
11110 if (!goal)
11111 goto out;
11112
11113 /* PCI controllers on most RISC systems tend to disconnect
11114 * when a device tries to burst across a cache-line boundary.
11115 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11116 *
11117 * Unfortunately, for PCI-E there are only limited
11118 * write-side controls for this, and thus for reads
11119 * we will still get the disconnects. We'll also waste
11120 * these PCI cycles for both read and write for chips
11121 * other than 5700 and 5701 which do not implement the
11122 * boundary bits.
11123 */
11124 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11125 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11126 switch (cacheline_size) {
11127 case 16:
11128 case 32:
11129 case 64:
11130 case 128:
11131 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11132 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11133 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11134 } else {
11135 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11136 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11137 }
11138 break;
11139
11140 case 256:
11141 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11142 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11143 break;
11144
11145 default:
11146 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11147 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11148 break;
11149 };
11150 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11151 switch (cacheline_size) {
11152 case 16:
11153 case 32:
11154 case 64:
11155 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11156 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11157 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11158 break;
11159 }
11160 /* fallthrough */
11161 case 128:
11162 default:
11163 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11164 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11165 break;
11166 };
11167 } else {
11168 switch (cacheline_size) {
11169 case 16:
11170 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11171 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11172 DMA_RWCTRL_WRITE_BNDRY_16);
11173 break;
11174 }
11175 /* fallthrough */
11176 case 32:
11177 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11178 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11179 DMA_RWCTRL_WRITE_BNDRY_32);
11180 break;
11181 }
11182 /* fallthrough */
11183 case 64:
11184 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11185 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11186 DMA_RWCTRL_WRITE_BNDRY_64);
11187 break;
11188 }
11189 /* fallthrough */
11190 case 128:
11191 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11192 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11193 DMA_RWCTRL_WRITE_BNDRY_128);
11194 break;
11195 }
11196 /* fallthrough */
11197 case 256:
11198 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11199 DMA_RWCTRL_WRITE_BNDRY_256);
11200 break;
11201 case 512:
11202 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11203 DMA_RWCTRL_WRITE_BNDRY_512);
11204 break;
11205 case 1024:
11206 default:
11207 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11208 DMA_RWCTRL_WRITE_BNDRY_1024);
11209 break;
11210 };
11211 }
11212
11213out:
11214 return val;
11215}
11216
1da177e4
LT		 11217static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11218{
11219 struct tg3_internal_buffer_desc test_desc;
11220 u32 sram_dma_descs;
11221 int i, ret;
11222
11223 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11224
11225 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11226 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11227 tw32(RDMAC_STATUS, 0);
11228 tw32(WDMAC_STATUS, 0);
11229
11230 tw32(BUFMGR_MODE, 0);
11231 tw32(FTQ_RESET, 0);
11232
11233 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11234 test_desc.addr_lo = buf_dma & 0xffffffff;
11235 test_desc.nic_mbuf = 0x00002100;
11236 test_desc.len = size;
11237
11238 /*
11239 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11240 * the *second* time the tg3 driver was getting loaded after an
11241 * initial scan.
11242 *
11243 * Broadcom tells me:
11244 * ...the DMA engine is connected to the GRC block and a DMA
11245 * reset may affect the GRC block in some unpredictable way...
11246 * The behavior of resets to individual blocks has not been tested.
11247 *
11248 * Broadcom noted the GRC reset will also reset all sub-components.
11249 */
11250 if (to_device) {
11251 test_desc.cqid_sqid = (13 << 8) | 2;
11252
11253 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11254 udelay(40);
11255 } else {
11256 test_desc.cqid_sqid = (16 << 8) | 7;
11257
11258 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11259 udelay(40);
11260 }
11261 test_desc.flags = 0x00000005;
11262
11263 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11264 u32 val;
11265
11266 val = *(((u32 *)&test_desc) + i);
11267 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11268 sram_dma_descs + (i * sizeof(u32)));
11269 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11270 }
11271 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11272
11273 if (to_device) {
11274 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11275 } else {
11276 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11277 }
11278
11279 ret = -ENODEV;
11280 for (i = 0; i < 40; i++) {
11281 u32 val;
11282
11283 if (to_device)
11284 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11285 else
11286 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11287 if ((val & 0xffff) == sram_dma_descs) {
11288 ret = 0;
11289 break;
11290 }
11291
11292 udelay(100);
11293 }
11294
11295 return ret;
11296}
11297
ded7340d 11298#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11299
11300static int __devinit tg3_test_dma(struct tg3 *tp)
11301{
11302 dma_addr_t buf_dma;
59e6b434 11303 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11304 int ret;
11305
11306 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11307 if (!buf) {
11308 ret = -ENOMEM;
11309 goto out_nofree;
11310 }
11311
11312 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11313 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11314
59e6b434 11315 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11316
11317 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11318 /* DMA read watermark not used on PCIE */
11319 tp->dma_rwctrl |= 0x00180000;
11320 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11322 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11323 tp->dma_rwctrl |= 0x003f0000;
11324 else
11325 tp->dma_rwctrl |= 0x003f000f;
11326 } else {
11327 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11328 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11329 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11330 u32 read_water = 0x7;
1da177e4 11331
4a29cc2e
MC		 11332 /* If the 5704 is behind the EPB bridge, we can
11333 * do the less restrictive ONE_DMA workaround for
11334 * better performance.
11335 */
11336 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11337 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11338 tp->dma_rwctrl |= 0x8000;
11339 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 11340 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11341
49afdeb6
MC		 11342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11343 read_water = 4;
59e6b434 11344 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 11345 tp->dma_rwctrl |=
11346 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11347 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11348 (1 << 23);
4cf78e4f
MC		 11349 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11350 /* 5780 always in PCIX mode */
11351 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 11352 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11353 /* 5714 always in PCIX mode */
11354 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 11355 } else {
11356 tp->dma_rwctrl |= 0x001b000f;
11357 }
11358 }
11359
11360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11361 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11362 tp->dma_rwctrl &= 0xfffffff0;
11363
11364 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11365 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11366 /* Remove this if it causes problems for some boards. */
11367 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11368
11369 /* On 5700/5701 chips, we need to set this bit.
11370 * Otherwise the chip will issue cacheline transactions
11371 * to streamable DMA memory with not all the byte
11372 * enables turned on. This is an error on several
11373 * RISC PCI controllers, in particular sparc64.
11374 *
11375 * On 5703/5704 chips, this bit has been reassigned
11376 * a different meaning. In particular, it is used
11377 * on those chips to enable a PCI-X workaround.
11378 */
11379 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11380 }
11381
11382 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11383
11384#if 0
11385 /* Unneeded, already done by tg3_get_invariants. */
11386 tg3_switch_clocks(tp);
11387#endif
11388
11389 ret = 0;
11390 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11391 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11392 goto out;
11393
59e6b434
DM		 11394 /* It is best to perform DMA test with maximum write burst size
11395 * to expose the 5700/5701 write DMA bug.
11396 */
11397 saved_dma_rwctrl = tp->dma_rwctrl;
11398 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11399 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11400
1da177e4
LT		 11401 while (1) {
11402 u32 *p = buf, i;
11403
11404 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11405 p[i] = i;
11406
11407 /* Send the buffer to the chip. */
11408 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11409 if (ret) {
11410 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11411 break;
11412 }
11413
11414#if 0
11415 /* validate data reached card RAM correctly. */
11416 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11417 u32 val;
11418 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11419 if (le32_to_cpu(val) != p[i]) {
11420 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11421 /* ret = -ENODEV here? */
11422 }
11423 p[i] = 0;
11424 }
11425#endif
11426 /* Now read it back. */
11427 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11428 if (ret) {
11429 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11430
11431 break;
11432 }
11433
11434 /* Verify it. */
11435 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11436 if (p[i] == i)
11437 continue;
11438
59e6b434
DM		 11439 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11440 DMA_RWCTRL_WRITE_BNDRY_16) {
11441 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 11442 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11443 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11444 break;
11445 } else {
11446 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11447 ret = -ENODEV;
11448 goto out;
11449 }
11450 }
11451
11452 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11453 /* Success. */
11454 ret = 0;
11455 break;
11456 }
11457 }
59e6b434
DM		 11458 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11459 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 11460 static struct pci_device_id dma_wait_state_chipsets[] = {
11461 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11462 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11463 { },
11464 };
11465
59e6b434 11466 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 11467 * now look for chipsets that are known to expose the
11468 * DMA bug without failing the test.
59e6b434 11469 */
6d1cfbab
MC		 11470 if (pci_dev_present(dma_wait_state_chipsets)) {
11471 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11472 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11473 }
11474 else
11475 /* Safe to use the calculated DMA boundary. */
11476 tp->dma_rwctrl = saved_dma_rwctrl;
11477
59e6b434
DM		 11478 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11479 }
1da177e4
LT		 11480
11481out:
11482 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11483out_nofree:
11484 return ret;
11485}
11486
11487static void __devinit tg3_init_link_config(struct tg3 *tp)
11488{
11489 tp->link_config.advertising =
11490 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11491 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11492 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11493 ADVERTISED_Autoneg | ADVERTISED_MII);
11494 tp->link_config.speed = SPEED_INVALID;
11495 tp->link_config.duplex = DUPLEX_INVALID;
11496 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 11497 tp->link_config.active_speed = SPEED_INVALID;
11498 tp->link_config.active_duplex = DUPLEX_INVALID;
11499 tp->link_config.phy_is_low_power = 0;
11500 tp->link_config.orig_speed = SPEED_INVALID;
11501 tp->link_config.orig_duplex = DUPLEX_INVALID;
11502 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11503}
11504
11505static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11506{
fdfec172
MC		 11507 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11508 tp->bufmgr_config.mbuf_read_dma_low_water =
11509 DEFAULT_MB_RDMA_LOW_WATER_5705;
11510 tp->bufmgr_config.mbuf_mac_rx_low_water =
11511 DEFAULT_MB_MACRX_LOW_WATER_5705;
11512 tp->bufmgr_config.mbuf_high_water =
11513 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 11514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11515 tp->bufmgr_config.mbuf_mac_rx_low_water =
11516 DEFAULT_MB_MACRX_LOW_WATER_5906;
11517 tp->bufmgr_config.mbuf_high_water =
11518 DEFAULT_MB_HIGH_WATER_5906;
11519 }
fdfec172
MC		 11520
11521 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11522 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11523 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11524 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11525 tp->bufmgr_config.mbuf_high_water_jumbo =
11526 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11527 } else {
11528 tp->bufmgr_config.mbuf_read_dma_low_water =
11529 DEFAULT_MB_RDMA_LOW_WATER;
11530 tp->bufmgr_config.mbuf_mac_rx_low_water =
11531 DEFAULT_MB_MACRX_LOW_WATER;
11532 tp->bufmgr_config.mbuf_high_water =
11533 DEFAULT_MB_HIGH_WATER;
11534
11535 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11536 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11537 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11538 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11539 tp->bufmgr_config.mbuf_high_water_jumbo =
11540 DEFAULT_MB_HIGH_WATER_JUMBO;
11541 }
1da177e4
LT		 11542
11543 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11544 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11545}
11546
11547static char * __devinit tg3_phy_string(struct tg3 *tp)
11548{
11549 switch (tp->phy_id & PHY_ID_MASK) {
11550 case PHY_ID_BCM5400: return "5400";
11551 case PHY_ID_BCM5401: return "5401";
11552 case PHY_ID_BCM5411: return "5411";
11553 case PHY_ID_BCM5701: return "5701";
11554 case PHY_ID_BCM5703: return "5703";
11555 case PHY_ID_BCM5704: return "5704";
11556 case PHY_ID_BCM5705: return "5705";
11557 case PHY_ID_BCM5750: return "5750";
85e94ced 11558 case PHY_ID_BCM5752: return "5752";
a4e2b347 11559 case PHY_ID_BCM5714: return "5714";
4cf78e4f 11560 case PHY_ID_BCM5780: return "5780";
af36e6b6 11561 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 11562 case PHY_ID_BCM5787: return "5787";
126a3368 11563 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 11564 case PHY_ID_BCM5906: return "5906";
1da177e4
LT		 11565 case PHY_ID_BCM8002: return "8002/serdes";
11566 case 0: return "serdes";
11567 default: return "unknown";
11568 };
11569}
11570
f9804ddb
MC		 11571static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11572{
11573 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11574 strcpy(str, "PCI Express");
11575 return str;
11576 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11577 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11578
11579 strcpy(str, "PCIX:");
11580
11581 if ((clock_ctrl == 7) ||
11582 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11583 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11584 strcat(str, "133MHz");
11585 else if (clock_ctrl == 0)
11586 strcat(str, "33MHz");
11587 else if (clock_ctrl == 2)
11588 strcat(str, "50MHz");
11589 else if (clock_ctrl == 4)
11590 strcat(str, "66MHz");
11591 else if (clock_ctrl == 6)
11592 strcat(str, "100MHz");
f9804ddb
MC		 11593 } else {
11594 strcpy(str, "PCI:");
11595 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11596 strcat(str, "66MHz");
11597 else
11598 strcat(str, "33MHz");
11599 }
11600 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11601 strcat(str, ":32-bit");
11602 else
11603 strcat(str, ":64-bit");
11604 return str;
11605}
11606
8c2dc7e1 11607static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 11608{
11609 struct pci_dev *peer;
11610 unsigned int func, devnr = tp->pdev->devfn & ~7;
11611
11612 for (func = 0; func < 8; func++) {
11613 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11614 if (peer && peer != tp->pdev)
11615 break;
11616 pci_dev_put(peer);
11617 }
16fe9d74
MC		 11618 /* 5704 can be configured in single-port mode, set peer to
11619 * tp->pdev in that case.
11620 */
11621 if (!peer) {
11622 peer = tp->pdev;
11623 return peer;
11624 }
1da177e4
LT		 11625
11626 /*
11627 * We don't need to keep the refcount elevated; there's no way
11628 * to remove one half of this device without removing the other
11629 */
11630 pci_dev_put(peer);
11631
11632 return peer;
11633}
11634
15f9850d
DM		 11635static void __devinit tg3_init_coal(struct tg3 *tp)
11636{
11637 struct ethtool_coalesce *ec = &tp->coal;
11638
11639 memset(ec, 0, sizeof(*ec));
11640 ec->cmd = ETHTOOL_GCOALESCE;
11641 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11642 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11643 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11644 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11645 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11646 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11647 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11648 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11649 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11650
11651 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11652 HOSTCC_MODE_CLRTICK_TXBD)) {
11653 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11654 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11655 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11656 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11657 }
d244c892
MC		 11658
11659 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11660 ec->rx_coalesce_usecs_irq = 0;
11661 ec->tx_coalesce_usecs_irq = 0;
11662 ec->stats_block_coalesce_usecs = 0;
11663 }
15f9850d
DM		 11664}
11665
1da177e4
LT		 11666static int __devinit tg3_init_one(struct pci_dev *pdev,
11667 const struct pci_device_id *ent)
11668{
11669 static int tg3_version_printed = 0;
11670 unsigned long tg3reg_base, tg3reg_len;
11671 struct net_device *dev;
11672 struct tg3 *tp;
72f2afb8 11673 int i, err, pm_cap;
f9804ddb 11674 char str[40];
72f2afb8 11675 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 11676
11677 if (tg3_version_printed++ == 0)
11678 printk(KERN_INFO "%s", version);
11679
11680 err = pci_enable_device(pdev);
11681 if (err) {
11682 printk(KERN_ERR PFX "Cannot enable PCI device, "
11683 "aborting.\n");
11684 return err;
11685 }
11686
11687 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11688 printk(KERN_ERR PFX "Cannot find proper PCI device "
11689 "base address, aborting.\n");
11690 err = -ENODEV;
11691 goto err_out_disable_pdev;
11692 }
11693
11694 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11695 if (err) {
11696 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11697 "aborting.\n");
11698 goto err_out_disable_pdev;
11699 }
11700
11701 pci_set_master(pdev);
11702
11703 /* Find power-management capability. */
11704 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11705 if (pm_cap == 0) {
11706 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11707 "aborting.\n");
11708 err = -EIO;
11709 goto err_out_free_res;
11710 }
11711
1da177e4
LT		 11712 tg3reg_base = pci_resource_start(pdev, 0);
11713 tg3reg_len = pci_resource_len(pdev, 0);
11714
11715 dev = alloc_etherdev(sizeof(*tp));
11716 if (!dev) {
11717 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11718 err = -ENOMEM;
11719 goto err_out_free_res;
11720 }
11721
11722 SET_MODULE_OWNER(dev);
11723 SET_NETDEV_DEV(dev, &pdev->dev);
11724
1da177e4
LT		 11725#if TG3_VLAN_TAG_USED
11726 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11727 dev->vlan_rx_register = tg3_vlan_rx_register;
11728 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11729#endif
11730
11731 tp = netdev_priv(dev);
11732 tp->pdev = pdev;
11733 tp->dev = dev;
11734 tp->pm_cap = pm_cap;
11735 tp->mac_mode = TG3_DEF_MAC_MODE;
11736 tp->rx_mode = TG3_DEF_RX_MODE;
11737 tp->tx_mode = TG3_DEF_TX_MODE;
11738 tp->mi_mode = MAC_MI_MODE_BASE;
11739 if (tg3_debug > 0)
11740 tp->msg_enable = tg3_debug;
11741 else
11742 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11743
11744 /* The word/byte swap controls here control register access byte
11745 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11746 * setting below.
11747 */
11748 tp->misc_host_ctrl =
11749 MISC_HOST_CTRL_MASK_PCI_INT |
11750 MISC_HOST_CTRL_WORD_SWAP |
11751 MISC_HOST_CTRL_INDIR_ACCESS |
11752 MISC_HOST_CTRL_PCISTATE_RW;
11753
11754 /* The NONFRM (non-frame) byte/word swap controls take effect
11755 * on descriptor entries, anything which isn't packet data.
11756 *
11757 * The StrongARM chips on the board (one for tx, one for rx)
11758 * are running in big-endian mode.
11759 */
11760 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11761 GRC_MODE_WSWAP_NONFRM_DATA);
11762#ifdef __BIG_ENDIAN
11763 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11764#endif
11765 spin_lock_init(&tp->lock);
1da177e4 11766 spin_lock_init(&tp->indirect_lock);
c4028958 11767 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 11768
11769 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11770 if (tp->regs == 0UL) {
11771 printk(KERN_ERR PFX "Cannot map device registers, "
11772 "aborting.\n");
11773 err = -ENOMEM;
11774 goto err_out_free_dev;
11775 }
11776
11777 tg3_init_link_config(tp);
11778
1da177e4
LT		 11779 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11780 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11781 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11782
11783 dev->open = tg3_open;
11784 dev->stop = tg3_close;
11785 dev->get_stats = tg3_get_stats;
11786 dev->set_multicast_list = tg3_set_rx_mode;
11787 dev->set_mac_address = tg3_set_mac_addr;
11788 dev->do_ioctl = tg3_ioctl;
11789 dev->tx_timeout = tg3_tx_timeout;
11790 dev->poll = tg3_poll;
11791 dev->ethtool_ops = &tg3_ethtool_ops;
11792 dev->weight = 64;
11793 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11794 dev->change_mtu = tg3_change_mtu;
11795 dev->irq = pdev->irq;
11796#ifdef CONFIG_NET_POLL_CONTROLLER
11797 dev->poll_controller = tg3_poll_controller;
11798#endif
11799
11800 err = tg3_get_invariants(tp);
11801 if (err) {
11802 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11803 "aborting.\n");
11804 goto err_out_iounmap;
11805 }
11806
4a29cc2e
MC		 11807 /* The EPB bridge inside 5714, 5715, and 5780 and any
11808 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 11809 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11810 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11811 * do DMA address check in tg3_start_xmit().
11812 */
4a29cc2e
MC		 11813 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11814 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11815 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 11816 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11817#ifdef CONFIG_HIGHMEM
11818 dma_mask = DMA_64BIT_MASK;
11819#endif
4a29cc2e 11820 } else
72f2afb8
MC		 11821 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11822
11823 /* Configure DMA attributes. */
11824 if (dma_mask > DMA_32BIT_MASK) {
11825 err = pci_set_dma_mask(pdev, dma_mask);
11826 if (!err) {
11827 dev->features |= NETIF_F_HIGHDMA;
11828 err = pci_set_consistent_dma_mask(pdev,
11829 persist_dma_mask);
11830 if (err < 0) {
11831 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11832 "DMA for consistent allocations\n");
11833 goto err_out_iounmap;
11834 }
11835 }
11836 }
11837 if (err || dma_mask == DMA_32BIT_MASK) {
11838 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11839 if (err) {
11840 printk(KERN_ERR PFX "No usable DMA configuration, "
11841 "aborting.\n");
11842 goto err_out_iounmap;
11843 }
11844 }
11845
fdfec172 11846 tg3_init_bufmgr_config(tp);
1da177e4 11847
1da177e4
LT		 11848 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11849 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11850 }
11851 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11852 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11853 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 11854 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 11855 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11856 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11857 } else {
11858 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11859 }
11860
4e3a7aaa
MC		 11861 /* TSO is on by default on chips that support hardware TSO.
11862 * Firmware TSO on older chips gives lower performance, so it
11863 * is off by default, but can be enabled using ethtool.
11864 */
b0026624 11865 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 11866 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 11867 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11868 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624
MC		 11869 dev->features |= NETIF_F_TSO6;
11870 }
1da177e4 11871
1da177e4
LT		 11872
11873 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11874 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11875 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11876 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11877 tp->rx_pending = 63;
11878 }
11879
8c2dc7e1
MC		 11880 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11881 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11882 tp->pdev_peer = tg3_find_peer(tp);
1da177e4
LT		 11883
11884 err = tg3_get_device_address(tp);
11885 if (err) {
11886 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11887 "aborting.\n");
11888 goto err_out_iounmap;
11889 }
11890
11891 /*
11892 * Reset chip in case UNDI or EFI driver did not shutdown
11893 * DMA self test will enable WDMAC and we'll see (spurious)
11894 * pending DMA on the PCI bus at that point.
11895 */
11896 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11897 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11898 pci_save_state(tp->pdev);
11899 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 11900 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 11901 }
11902
11903 err = tg3_test_dma(tp);
11904 if (err) {
11905 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11906 goto err_out_iounmap;
11907 }
11908
11909 /* Tigon3 can do ipv4 only... and some chips have buggy
11910 * checksumming.
11911 */
11912 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
af36e6b6
MC		 11913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf
MC		 11915 dev->features |= NETIF_F_HW_CSUM;
11916 else
11917 dev->features |= NETIF_F_IP_CSUM;
11918 dev->features |= NETIF_F_SG;
1da177e4
LT		 11919 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11920 } else
11921 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11922
1da177e4
LT		 11923 /* flow control autonegotiation is default behavior */
11924 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11925
15f9850d
DM		 11926 tg3_init_coal(tp);
11927
7d3f4c97
DM		 11928 /* Now that we have fully setup the chip, save away a snapshot
11929 * of the PCI config space. We need to restore this after
11930 * GRC_MISC_CFG core clock resets and some resume events.
11931 */
11932 pci_save_state(tp->pdev);
11933
c49a1561
MC		 11934 pci_set_drvdata(pdev, dev);
11935
1da177e4
LT		 11936 err = register_netdev(dev);
11937 if (err) {
11938 printk(KERN_ERR PFX "Cannot register net device, "
11939 "aborting.\n");
11940 goto err_out_iounmap;
11941 }
11942
cbb45d21 11943 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 11944 dev->name,
11945 tp->board_part_number,
11946 tp->pci_chip_rev_id,
11947 tg3_phy_string(tp),
f9804ddb 11948 tg3_bus_string(tp, str),
cbb45d21
MC		 11949 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11950 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11951 "10/100/1000Base-T")));
1da177e4
LT		 11952
11953 for (i = 0; i < 6; i++)
11954 printk("%2.2x%c", dev->dev_addr[i],
11955 i == 5 ? '\n' : ':');
11956
11957 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11958 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11959 "TSOcap[%d] \n",
11960 dev->name,
11961 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11962 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11963 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11964 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11965 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11966 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11967 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 11968 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11969 dev->name, tp->dma_rwctrl,
11970 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11971 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 11972
11973 return 0;
11974
11975err_out_iounmap:
6892914f
MC		 11976 if (tp->regs) {
11977 iounmap(tp->regs);
22abe310 11978 tp->regs = NULL;
6892914f 11979 }
1da177e4
LT		 11980
11981err_out_free_dev:
11982 free_netdev(dev);
11983
11984err_out_free_res:
11985 pci_release_regions(pdev);
11986
11987err_out_disable_pdev:
11988 pci_disable_device(pdev);
11989 pci_set_drvdata(pdev, NULL);
11990 return err;
11991}
11992
11993static void __devexit tg3_remove_one(struct pci_dev *pdev)
11994{
11995 struct net_device *dev = pci_get_drvdata(pdev);
11996
11997 if (dev) {
11998 struct tg3 *tp = netdev_priv(dev);
11999
7faa006f 12000 flush_scheduled_work();
1da177e4 12001 unregister_netdev(dev);
6892914f
MC		 12002 if (tp->regs) {
12003 iounmap(tp->regs);
22abe310 12004 tp->regs = NULL;
6892914f 12005 }
1da177e4
LT		 12006 free_netdev(dev);
12007 pci_release_regions(pdev);
12008 pci_disable_device(pdev);
12009 pci_set_drvdata(pdev, NULL);
12010 }
12011}
12012
12013static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12014{
12015 struct net_device *dev = pci_get_drvdata(pdev);
12016 struct tg3 *tp = netdev_priv(dev);
12017 int err;
12018
12019 if (!netif_running(dev))
12020 return 0;
12021
7faa006f 12022 flush_scheduled_work();
1da177e4
LT		 12023 tg3_netif_stop(tp);
12024
12025 del_timer_sync(&tp->timer);
12026
f47c11ee 12027 tg3_full_lock(tp, 1);
1da177e4 12028 tg3_disable_ints(tp);
f47c11ee 12029 tg3_full_unlock(tp);
1da177e4
LT		 12030
12031 netif_device_detach(dev);
12032
f47c11ee 12033 tg3_full_lock(tp, 0);
944d980e 12034 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12035 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12036 tg3_full_unlock(tp);
1da177e4 12037
436f1379
MC		 12038 /* Save MSI address and data for resume. */
12039 pci_save_state(pdev);
12040
1da177e4
LT		 12041 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12042 if (err) {
f47c11ee 12043 tg3_full_lock(tp, 0);
1da177e4 12044
6a9eba15 12045 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12046 if (tg3_restart_hw(tp, 1))
12047 goto out;
1da177e4
LT		 12048
12049 tp->timer.expires = jiffies + tp->timer_offset;
12050 add_timer(&tp->timer);
12051
12052 netif_device_attach(dev);
12053 tg3_netif_start(tp);
12054
b9ec6c1b 12055out:
f47c11ee 12056 tg3_full_unlock(tp);
1da177e4
LT		 12057 }
12058
12059 return err;
12060}
12061
12062static int tg3_resume(struct pci_dev *pdev)
12063{
12064 struct net_device *dev = pci_get_drvdata(pdev);
12065 struct tg3 *tp = netdev_priv(dev);
12066 int err;
12067
12068 if (!netif_running(dev))
12069 return 0;
12070
12071 pci_restore_state(tp->pdev);
12072
bc1c7567 12073 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12074 if (err)
12075 return err;
12076
12077 netif_device_attach(dev);
12078
f47c11ee 12079 tg3_full_lock(tp, 0);
1da177e4 12080
6a9eba15 12081 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12082 err = tg3_restart_hw(tp, 1);
12083 if (err)
12084 goto out;
1da177e4
LT		 12085
12086 tp->timer.expires = jiffies + tp->timer_offset;
12087 add_timer(&tp->timer);
12088
1da177e4
LT		 12089 tg3_netif_start(tp);
12090
b9ec6c1b 12091out:
f47c11ee 12092 tg3_full_unlock(tp);
1da177e4 12093
b9ec6c1b 12094 return err;
1da177e4
LT		 12095}
12096
12097static struct pci_driver tg3_driver = {
12098 .name = DRV_MODULE_NAME,
12099 .id_table = tg3_pci_tbl,
12100 .probe = tg3_init_one,
12101 .remove = __devexit_p(tg3_remove_one),
12102 .suspend = tg3_suspend,
12103 .resume = tg3_resume
12104};
12105
12106static int __init tg3_init(void)
12107{
29917620 12108 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12109}
12110
12111static void __exit tg3_cleanup(void)
12112{
12113 pci_unregister_driver(&tg3_driver);
12114}
12115
12116module_init(tg3_init);
12117module_exit(tg3_cleanup);
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