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[TG3]: 5906 doesn't need to switch to slower clock.
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/byteorder.h>
47#include <asm/uaccess.h>
48
49#ifdef CONFIG_SPARC64
50#include <asm/idprom.h>
51#include <asm/oplib.h>
52#include <asm/pbm.h>
53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
c1d2a196
MC		 67#define DRV_MODULE_VERSION "3.72"
68#define DRV_MODULE_RELDATE "January 8, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
13185217
HK		 201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
1da177e4
LT		 209};
210
211MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
50da859d 213static const struct {
1da177e4
LT		 214 const char string[ETH_GSTRING_LEN];
215} ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292};
293
50da859d 294static const struct {
4cafd3f5
MC		 295 const char string[ETH_GSTRING_LEN];
296} ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303};
304
b401e9e2
MC		 305static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306{
307 writel(val, tp->regs + off);
308}
309
310static u32 tg3_read32(struct tg3 *tp, u32 off)
311{
6aa20a22 312 return (readl(tp->regs + off));
b401e9e2
MC		 313}
314
1da177e4
LT		 315static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316{
6892914f
MC		 317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 323}
324
325static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326{
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
1da177e4
LT		 329}
330
6892914f 331static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 332{
6892914f
MC		 333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341}
342
343static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344{
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
1da177e4 356 }
6892914f
MC		 357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371}
372
373static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374{
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383}
384
b401e9e2
MC		 385/* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 391{
b401e9e2
MC		 392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
1da177e4
LT		 408}
409
09ee929c
MC		 410static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411{
412 tp->write32_mbox(tp, off, val);
6892914f
MC		 413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
09ee929c
MC		 416}
417
20094930 418static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 419{
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426}
427
b5d3772c
MC		 428static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429{
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431}
432
433static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434{
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436}
437
20094930 438#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 439#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 440#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 442#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 443
444#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 445#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 447#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 448
449static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450{
6892914f
MC		 451 unsigned long flags;
452
b5d3772c
MC		 453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
6892914f 457 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 461
bbadf503
MC		 462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 467
bbadf503
MC		 468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 472}
473
1da177e4
LT		 474static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475{
6892914f
MC		 476 unsigned long flags;
477
b5d3772c
MC		 478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
6892914f 484 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 488
bbadf503
MC		 489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 499}
500
501static void tg3_disable_ints(struct tg3 *tp)
502{
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 506}
507
508static inline void tg3_cond_int(struct tg3 *tp)
509{
38f3843e
MC		 510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 516}
517
518static void tg3_enable_ints(struct tg3 *tp)
519{
bbe832c0
MC		 520 tp->irq_sync = 0;
521 wmb();
522
1da177e4
LT		 523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
fcfa0a32
MC		 527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
1da177e4
LT		 530 tg3_cond_int(tp);
531}
532
04237ddd
MC		 533static inline unsigned int tg3_has_work(struct tg3 *tp)
534{
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551}
552
1da177e4 553/* tg3_restart_ints
04237ddd
MC		 554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
6aa20a22 556 * which reenables interrupts
1da177e4
LT		 557 */
558static void tg3_restart_ints(struct tg3 *tp)
559{
fac9b83e
DM		 560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
1da177e4
LT		 562 mmiowb();
563
fac9b83e
DM		 564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
04237ddd
MC		 570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 572}
573
574static inline void tg3_netif_stop(struct tg3 *tp)
575{
bbe832c0 576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579}
580
581static inline void tg3_netif_start(struct tg3 *tp)
582{
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
f47c11ee
DM		 589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
1da177e4
LT		 591}
592
593static void tg3_switch_clocks(struct tg3 *tp)
594{
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
a4e2b347 598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 599 return;
600
1da177e4
LT		 601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
1da177e4 620 }
b401e9e2 621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 622}
623
624#define PHY_BUSY_LOOPS 5000
625
626static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627{
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 645
1da177e4
LT		 646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673}
674
675static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676{
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
b5d3772c
MC		 681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
1da177e4
LT		 685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 697
1da177e4
LT		 698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722}
723
724static void tg3_phy_set_wirespeed(struct tg3 *tp)
725{
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735}
736
737static int tg3_bmcr_reset(struct tg3 *tp)
738{
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766}
767
768static int tg3_wait_macro_done(struct tg3 *tp)
769{
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784}
785
786static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787{
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850}
851
852static int tg3_phy_reset_chanpat(struct tg3 *tp)
853{
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870}
871
872static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873{
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946}
947
c8e1e82b
MC		 948static void tg3_link_report(struct tg3 *);
949
1da177e4
LT		 950/* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953static int tg3_phy_reset(struct tg3 *tp)
954{
955 u32 phy_status;
956 int err;
957
60189ddf
MC		 958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
1da177e4
LT		 965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
c8e1e82b
MC		 970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
1da177e4
LT		 975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
c424cb24
MC		 1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1da177e4
LT		 1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
0f893dc6 1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
715116a1
MC		 1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1da177e4
LT		 1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067}
1068
1069static void tg3_frob_aux_power(struct tg3 *tp)
1070{
1071 struct tg3 *tp_peer = tp;
1072
9d26e213 1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1074 return;
1075
8c2dc7e1
MC		 1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1081 /* remove_one() may have been run on the peer. */
8c2dc7e1 1082 if (!dev_peer)
bc1c7567
MC		 1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1086 }
1087
1da177e4 1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1da177e4
LT		 1101 } else {
1102 u32 no_gpio2;
dc56b7d4 1103 u32 grc_local_ctrl = 0;
1da177e4
LT		 1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
dc56b7d4
MC		 1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
dc56b7d4
MC		 1115 }
1116
1da177e4
LT		 1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
dc56b7d4 1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
b401e9e2
MC		 1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1da177e4
LT		 1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
b401e9e2
MC		 1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1da177e4
LT		 1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1da177e4
LT		 1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
b401e9e2
MC		 1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1154
b401e9e2
MC		 1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1157
b401e9e2
MC		 1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1161 }
1162 }
1163}
1164
1165static int tg3_setup_phy(struct tg3 *, int);
1166
1167#define RESET_KIND_SHUTDOWN 0
1168#define RESET_KIND_INIT 1
1169#define RESET_KIND_SUSPEND 2
1170
1171static void tg3_write_sig_post_reset(struct tg3 *, int);
1172static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1173static int tg3_nvram_lock(struct tg3 *);
1174static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1175
15c3b696
MC		 1176static void tg3_power_down_phy(struct tg3 *tp)
1177{
3f7045c1
MC		 1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1179 return;
1180
60189ddf
MC		 1181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1182 u32 val;
1183
1184 tg3_bmcr_reset(tp);
1185 val = tr32(GRC_MISC_CFG);
1186 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1187 udelay(40);
1188 return;
1189 } else {
715116a1
MC		 1190 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1191 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1192 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1193 }
3f7045c1 1194
15c3b696
MC		 1195 /* The PHY should not be powered down on some chips because
1196 * of bugs.
1197 */
1198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1199 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1200 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1201 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1202 return;
1203 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1204}
1205
bc1c7567 1206static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1207{
1208 u32 misc_host_ctrl;
1209 u16 power_control, power_caps;
1210 int pm = tp->pm_cap;
1211
1212 /* Make sure register accesses (indirect or otherwise)
1213 * will function correctly.
1214 */
1215 pci_write_config_dword(tp->pdev,
1216 TG3PCI_MISC_HOST_CTRL,
1217 tp->misc_host_ctrl);
1218
1219 pci_read_config_word(tp->pdev,
1220 pm + PCI_PM_CTRL,
1221 &power_control);
1222 power_control |= PCI_PM_CTRL_PME_STATUS;
1223 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1224 switch (state) {
bc1c7567 1225 case PCI_D0:
1da177e4
LT		 1226 power_control |= 0;
1227 pci_write_config_word(tp->pdev,
1228 pm + PCI_PM_CTRL,
1229 power_control);
8c6bda1a
MC		 1230 udelay(100); /* Delay after power state change */
1231
9d26e213
MC		 1232 /* Switch out of Vaux if it is a NIC */
1233 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1234 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1235
1236 return 0;
1237
bc1c7567 1238 case PCI_D1:
1da177e4
LT		 1239 power_control |= 1;
1240 break;
1241
bc1c7567 1242 case PCI_D2:
1da177e4
LT		 1243 power_control |= 2;
1244 break;
1245
bc1c7567 1246 case PCI_D3hot:
1da177e4
LT		 1247 power_control |= 3;
1248 break;
1249
1250 default:
1251 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1252 "requested.\n",
1253 tp->dev->name, state);
1254 return -EINVAL;
1255 };
1256
1257 power_control |= PCI_PM_CTRL_PME_ENABLE;
1258
1259 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1260 tw32(TG3PCI_MISC_HOST_CTRL,
1261 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1262
1263 if (tp->link_config.phy_is_low_power == 0) {
1264 tp->link_config.phy_is_low_power = 1;
1265 tp->link_config.orig_speed = tp->link_config.speed;
1266 tp->link_config.orig_duplex = tp->link_config.duplex;
1267 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1268 }
1269
747e8f8b 1270 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1271 tp->link_config.speed = SPEED_10;
1272 tp->link_config.duplex = DUPLEX_HALF;
1273 tp->link_config.autoneg = AUTONEG_ENABLE;
1274 tg3_setup_phy(tp, 0);
1275 }
1276
b5d3772c
MC		 1277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1278 u32 val;
1279
1280 val = tr32(GRC_VCPU_EXT_CTRL);
1281 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1282 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1283 int i;
1284 u32 val;
1285
1286 for (i = 0; i < 200; i++) {
1287 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1288 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1289 break;
1290 msleep(1);
1291 }
1292 }
1293 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1294 WOL_DRV_STATE_SHUTDOWN |
1295 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1296
1da177e4
LT		 1297 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1298
1299 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1300 u32 mac_mode;
1301
1302 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1303 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1304 udelay(40);
1305
3f7045c1
MC		 1306 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1307 mac_mode = MAC_MODE_PORT_MODE_GMII;
1308 else
1309 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4
LT		 1310
1311 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1312 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1313 mac_mode |= MAC_MODE_LINK_POLARITY;
1314 } else {
1315 mac_mode = MAC_MODE_PORT_MODE_TBI;
1316 }
1317
cbf46853 1318 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1319 tw32(MAC_LED_CTRL, tp->led_ctrl);
1320
1321 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1322 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1323 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1324
1325 tw32_f(MAC_MODE, mac_mode);
1326 udelay(100);
1327
1328 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1329 udelay(10);
1330 }
1331
1332 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1333 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1335 u32 base_val;
1336
1337 base_val = tp->pci_clock_ctrl;
1338 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1339 CLOCK_CTRL_TXCLK_DISABLE);
1340
b401e9e2
MC		 1341 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1342 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857
MC		 1343 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1344 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1345 /* do nothing */
85e94ced 1346 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1347 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1348 u32 newbits1, newbits2;
1349
1350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1352 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1353 CLOCK_CTRL_TXCLK_DISABLE |
1354 CLOCK_CTRL_ALTCLK);
1355 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1356 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1357 newbits1 = CLOCK_CTRL_625_CORE;
1358 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1359 } else {
1360 newbits1 = CLOCK_CTRL_ALTCLK;
1361 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1362 }
1363
b401e9e2
MC		 1364 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1365 40);
1da177e4 1366
b401e9e2
MC		 1367 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1368 40);
1da177e4
LT		 1369
1370 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1371 u32 newbits3;
1372
1373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1375 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1376 CLOCK_CTRL_TXCLK_DISABLE |
1377 CLOCK_CTRL_44MHZ_CORE);
1378 } else {
1379 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1380 }
1381
b401e9e2
MC		 1382 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1383 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1384 }
1385 }
1386
6921d201 1387 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
3f7045c1
MC		 1388 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1389 tg3_power_down_phy(tp);
6921d201 1390
1da177e4
LT		 1391 tg3_frob_aux_power(tp);
1392
1393 /* Workaround for unstable PLL clock */
1394 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1395 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1396 u32 val = tr32(0x7d00);
1397
1398 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1399 tw32(0x7d00, val);
6921d201 1400 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1401 int err;
1402
1403 err = tg3_nvram_lock(tp);
1da177e4 1404 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1405 if (!err)
1406 tg3_nvram_unlock(tp);
6921d201 1407 }
1da177e4
LT		 1408 }
1409
bbadf503
MC		 1410 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1411
1da177e4
LT		 1412 /* Finally, set the new power state. */
1413 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1414 udelay(100); /* Delay after power state change */
1da177e4 1415
1da177e4
LT		 1416 return 0;
1417}
1418
1419static void tg3_link_report(struct tg3 *tp)
1420{
1421 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1422 if (netif_msg_link(tp))
1423 printk(KERN_INFO PFX "%s: Link is down.\n",
1424 tp->dev->name);
1425 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1426 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1427 tp->dev->name,
1428 (tp->link_config.active_speed == SPEED_1000 ?
1429 1000 :
1430 (tp->link_config.active_speed == SPEED_100 ?
1431 100 : 10)),
1432 (tp->link_config.active_duplex == DUPLEX_FULL ?
1433 "full" : "half"));
1434
1435 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1436 "%s for RX.\n",
1437 tp->dev->name,
1438 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1439 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1440 }
1441}
1442
1443static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1444{
1445 u32 new_tg3_flags = 0;
1446 u32 old_rx_mode = tp->rx_mode;
1447 u32 old_tx_mode = tp->tx_mode;
1448
1449 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1450
1451 /* Convert 1000BaseX flow control bits to 1000BaseT
1452 * bits before resolving flow control.
1453 */
1454 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1455 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1456 ADVERTISE_PAUSE_ASYM);
1457 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1458
1459 if (local_adv & ADVERTISE_1000XPAUSE)
1460 local_adv |= ADVERTISE_PAUSE_CAP;
1461 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1462 local_adv |= ADVERTISE_PAUSE_ASYM;
1463 if (remote_adv & LPA_1000XPAUSE)
1464 remote_adv |= LPA_PAUSE_CAP;
1465 if (remote_adv & LPA_1000XPAUSE_ASYM)
1466 remote_adv |= LPA_PAUSE_ASYM;
1467 }
1468
1da177e4
LT		 1469 if (local_adv & ADVERTISE_PAUSE_CAP) {
1470 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1471 if (remote_adv & LPA_PAUSE_CAP)
1472 new_tg3_flags |=
1473 (TG3_FLAG_RX_PAUSE |
1474 TG3_FLAG_TX_PAUSE);
1475 else if (remote_adv & LPA_PAUSE_ASYM)
1476 new_tg3_flags |=
1477 (TG3_FLAG_RX_PAUSE);
1478 } else {
1479 if (remote_adv & LPA_PAUSE_CAP)
1480 new_tg3_flags |=
1481 (TG3_FLAG_RX_PAUSE |
1482 TG3_FLAG_TX_PAUSE);
1483 }
1484 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1485 if ((remote_adv & LPA_PAUSE_CAP) &&
1486 (remote_adv & LPA_PAUSE_ASYM))
1487 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1488 }
1489
1490 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1491 tp->tg3_flags |= new_tg3_flags;
1492 } else {
1493 new_tg3_flags = tp->tg3_flags;
1494 }
1495
1496 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1497 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1498 else
1499 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1500
1501 if (old_rx_mode != tp->rx_mode) {
1502 tw32_f(MAC_RX_MODE, tp->rx_mode);
1503 }
6aa20a22 1504
1da177e4
LT		 1505 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1506 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1507 else
1508 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1509
1510 if (old_tx_mode != tp->tx_mode) {
1511 tw32_f(MAC_TX_MODE, tp->tx_mode);
1512 }
1513}
1514
1515static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1516{
1517 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1518 case MII_TG3_AUX_STAT_10HALF:
1519 *speed = SPEED_10;
1520 *duplex = DUPLEX_HALF;
1521 break;
1522
1523 case MII_TG3_AUX_STAT_10FULL:
1524 *speed = SPEED_10;
1525 *duplex = DUPLEX_FULL;
1526 break;
1527
1528 case MII_TG3_AUX_STAT_100HALF:
1529 *speed = SPEED_100;
1530 *duplex = DUPLEX_HALF;
1531 break;
1532
1533 case MII_TG3_AUX_STAT_100FULL:
1534 *speed = SPEED_100;
1535 *duplex = DUPLEX_FULL;
1536 break;
1537
1538 case MII_TG3_AUX_STAT_1000HALF:
1539 *speed = SPEED_1000;
1540 *duplex = DUPLEX_HALF;
1541 break;
1542
1543 case MII_TG3_AUX_STAT_1000FULL:
1544 *speed = SPEED_1000;
1545 *duplex = DUPLEX_FULL;
1546 break;
1547
1548 default:
715116a1
MC		 1549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1550 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1551 SPEED_10;
1552 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1553 DUPLEX_HALF;
1554 break;
1555 }
1da177e4
LT		 1556 *speed = SPEED_INVALID;
1557 *duplex = DUPLEX_INVALID;
1558 break;
1559 };
1560}
1561
1562static void tg3_phy_copper_begin(struct tg3 *tp)
1563{
1564 u32 new_adv;
1565 int i;
1566
1567 if (tp->link_config.phy_is_low_power) {
1568 /* Entering low power mode. Disable gigabit and
1569 * 100baseT advertisements.
1570 */
1571 tg3_writephy(tp, MII_TG3_CTRL, 0);
1572
1573 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1574 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1575 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1576 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1577
1578 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1579 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1580 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1581 tp->link_config.advertising &=
1582 ~(ADVERTISED_1000baseT_Half |
1583 ADVERTISED_1000baseT_Full);
1584
1585 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1586 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1587 new_adv |= ADVERTISE_10HALF;
1588 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1589 new_adv |= ADVERTISE_10FULL;
1590 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1591 new_adv |= ADVERTISE_100HALF;
1592 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1593 new_adv |= ADVERTISE_100FULL;
1594 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1595
1596 if (tp->link_config.advertising &
1597 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1598 new_adv = 0;
1599 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1600 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1601 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1602 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1603 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1604 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1605 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1606 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1607 MII_TG3_CTRL_ENABLE_AS_MASTER);
1608 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1609 } else {
1610 tg3_writephy(tp, MII_TG3_CTRL, 0);
1611 }
1612 } else {
1613 /* Asking for a specific link mode. */
1614 if (tp->link_config.speed == SPEED_1000) {
1615 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1616 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1617
1618 if (tp->link_config.duplex == DUPLEX_FULL)
1619 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1620 else
1621 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1622 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1623 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1624 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1625 MII_TG3_CTRL_ENABLE_AS_MASTER);
1626 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1627 } else {
1628 tg3_writephy(tp, MII_TG3_CTRL, 0);
1629
1630 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1631 if (tp->link_config.speed == SPEED_100) {
1632 if (tp->link_config.duplex == DUPLEX_FULL)
1633 new_adv |= ADVERTISE_100FULL;
1634 else
1635 new_adv |= ADVERTISE_100HALF;
1636 } else {
1637 if (tp->link_config.duplex == DUPLEX_FULL)
1638 new_adv |= ADVERTISE_10FULL;
1639 else
1640 new_adv |= ADVERTISE_10HALF;
1641 }
1642 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1643 }
1644 }
1645
1646 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1647 tp->link_config.speed != SPEED_INVALID) {
1648 u32 bmcr, orig_bmcr;
1649
1650 tp->link_config.active_speed = tp->link_config.speed;
1651 tp->link_config.active_duplex = tp->link_config.duplex;
1652
1653 bmcr = 0;
1654 switch (tp->link_config.speed) {
1655 default:
1656 case SPEED_10:
1657 break;
1658
1659 case SPEED_100:
1660 bmcr |= BMCR_SPEED100;
1661 break;
1662
1663 case SPEED_1000:
1664 bmcr |= TG3_BMCR_SPEED1000;
1665 break;
1666 };
1667
1668 if (tp->link_config.duplex == DUPLEX_FULL)
1669 bmcr |= BMCR_FULLDPLX;
1670
1671 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1672 (bmcr != orig_bmcr)) {
1673 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1674 for (i = 0; i < 1500; i++) {
1675 u32 tmp;
1676
1677 udelay(10);
1678 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1679 tg3_readphy(tp, MII_BMSR, &tmp))
1680 continue;
1681 if (!(tmp & BMSR_LSTATUS)) {
1682 udelay(40);
1683 break;
1684 }
1685 }
1686 tg3_writephy(tp, MII_BMCR, bmcr);
1687 udelay(40);
1688 }
1689 } else {
1690 tg3_writephy(tp, MII_BMCR,
1691 BMCR_ANENABLE | BMCR_ANRESTART);
1692 }
1693}
1694
1695static int tg3_init_5401phy_dsp(struct tg3 *tp)
1696{
1697 int err;
1698
1699 /* Turn off tap power management. */
1700 /* Set Extended packet length bit */
1701 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1702
1703 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1704 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1705
1706 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1707 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1708
1709 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1710 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1711
1712 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1713 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1714
1715 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1716 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1717
1718 udelay(40);
1719
1720 return err;
1721}
1722
3600d918 1723static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1724{
3600d918
MC		 1725 u32 adv_reg, all_mask = 0;
1726
1727 if (mask & ADVERTISED_10baseT_Half)
1728 all_mask |= ADVERTISE_10HALF;
1729 if (mask & ADVERTISED_10baseT_Full)
1730 all_mask |= ADVERTISE_10FULL;
1731 if (mask & ADVERTISED_100baseT_Half)
1732 all_mask |= ADVERTISE_100HALF;
1733 if (mask & ADVERTISED_100baseT_Full)
1734 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1735
1736 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1737 return 0;
1738
1da177e4
LT		 1739 if ((adv_reg & all_mask) != all_mask)
1740 return 0;
1741 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1742 u32 tg3_ctrl;
1743
3600d918
MC		 1744 all_mask = 0;
1745 if (mask & ADVERTISED_1000baseT_Half)
1746 all_mask |= ADVERTISE_1000HALF;
1747 if (mask & ADVERTISED_1000baseT_Full)
1748 all_mask |= ADVERTISE_1000FULL;
1749
1da177e4
LT		 1750 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1751 return 0;
1752
1da177e4
LT		 1753 if ((tg3_ctrl & all_mask) != all_mask)
1754 return 0;
1755 }
1756 return 1;
1757}
1758
1759static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1760{
1761 int current_link_up;
1762 u32 bmsr, dummy;
1763 u16 current_speed;
1764 u8 current_duplex;
1765 int i, err;
1766
1767 tw32(MAC_EVENT, 0);
1768
1769 tw32_f(MAC_STATUS,
1770 (MAC_STATUS_SYNC_CHANGED |
1771 MAC_STATUS_CFG_CHANGED |
1772 MAC_STATUS_MI_COMPLETION |
1773 MAC_STATUS_LNKSTATE_CHANGED));
1774 udelay(40);
1775
1776 tp->mi_mode = MAC_MI_MODE_BASE;
1777 tw32_f(MAC_MI_MODE, tp->mi_mode);
1778 udelay(80);
1779
1780 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1781
1782 /* Some third-party PHYs need to be reset on link going
1783 * down.
1784 */
1785 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1786 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1787 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1788 netif_carrier_ok(tp->dev)) {
1789 tg3_readphy(tp, MII_BMSR, &bmsr);
1790 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1791 !(bmsr & BMSR_LSTATUS))
1792 force_reset = 1;
1793 }
1794 if (force_reset)
1795 tg3_phy_reset(tp);
1796
1797 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1798 tg3_readphy(tp, MII_BMSR, &bmsr);
1799 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1800 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1801 bmsr = 0;
1802
1803 if (!(bmsr & BMSR_LSTATUS)) {
1804 err = tg3_init_5401phy_dsp(tp);
1805 if (err)
1806 return err;
1807
1808 tg3_readphy(tp, MII_BMSR, &bmsr);
1809 for (i = 0; i < 1000; i++) {
1810 udelay(10);
1811 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1812 (bmsr & BMSR_LSTATUS)) {
1813 udelay(40);
1814 break;
1815 }
1816 }
1817
1818 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1819 !(bmsr & BMSR_LSTATUS) &&
1820 tp->link_config.active_speed == SPEED_1000) {
1821 err = tg3_phy_reset(tp);
1822 if (!err)
1823 err = tg3_init_5401phy_dsp(tp);
1824 if (err)
1825 return err;
1826 }
1827 }
1828 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1829 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1830 /* 5701 {A0,B0} CRC bug workaround */
1831 tg3_writephy(tp, 0x15, 0x0a75);
1832 tg3_writephy(tp, 0x1c, 0x8c68);
1833 tg3_writephy(tp, 0x1c, 0x8d68);
1834 tg3_writephy(tp, 0x1c, 0x8c68);
1835 }
1836
1837 /* Clear pending interrupts... */
1838 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1839 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1840
1841 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1842 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 1843 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 1844 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1845
1846 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1848 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1849 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1850 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1851 else
1852 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1853 }
1854
1855 current_link_up = 0;
1856 current_speed = SPEED_INVALID;
1857 current_duplex = DUPLEX_INVALID;
1858
1859 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1860 u32 val;
1861
1862 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1863 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1864 if (!(val & (1 << 10))) {
1865 val |= (1 << 10);
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1867 goto relink;
1868 }
1869 }
1870
1871 bmsr = 0;
1872 for (i = 0; i < 100; i++) {
1873 tg3_readphy(tp, MII_BMSR, &bmsr);
1874 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1875 (bmsr & BMSR_LSTATUS))
1876 break;
1877 udelay(40);
1878 }
1879
1880 if (bmsr & BMSR_LSTATUS) {
1881 u32 aux_stat, bmcr;
1882
1883 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1884 for (i = 0; i < 2000; i++) {
1885 udelay(10);
1886 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1887 aux_stat)
1888 break;
1889 }
1890
1891 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1892 &current_speed,
1893 &current_duplex);
1894
1895 bmcr = 0;
1896 for (i = 0; i < 200; i++) {
1897 tg3_readphy(tp, MII_BMCR, &bmcr);
1898 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1899 continue;
1900 if (bmcr && bmcr != 0x7fff)
1901 break;
1902 udelay(10);
1903 }
1904
1905 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1906 if (bmcr & BMCR_ANENABLE) {
1907 current_link_up = 1;
1908
1909 /* Force autoneg restart if we are exiting
1910 * low power mode.
1911 */
3600d918
MC		 1912 if (!tg3_copper_is_advertising_all(tp,
1913 tp->link_config.advertising))
1da177e4
LT		 1914 current_link_up = 0;
1915 } else {
1916 current_link_up = 0;
1917 }
1918 } else {
1919 if (!(bmcr & BMCR_ANENABLE) &&
1920 tp->link_config.speed == current_speed &&
1921 tp->link_config.duplex == current_duplex) {
1922 current_link_up = 1;
1923 } else {
1924 current_link_up = 0;
1925 }
1926 }
1927
1928 tp->link_config.active_speed = current_speed;
1929 tp->link_config.active_duplex = current_duplex;
1930 }
1931
1932 if (current_link_up == 1 &&
1933 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1934 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1935 u32 local_adv, remote_adv;
1936
1937 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1938 local_adv = 0;
1939 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1940
1941 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1942 remote_adv = 0;
1943
1944 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1945
1946 /* If we are not advertising full pause capability,
1947 * something is wrong. Bring the link down and reconfigure.
1948 */
1949 if (local_adv != ADVERTISE_PAUSE_CAP) {
1950 current_link_up = 0;
1951 } else {
1952 tg3_setup_flow_control(tp, local_adv, remote_adv);
1953 }
1954 }
1955relink:
6921d201 1956 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1957 u32 tmp;
1958
1959 tg3_phy_copper_begin(tp);
1960
1961 tg3_readphy(tp, MII_BMSR, &tmp);
1962 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1963 (tmp & BMSR_LSTATUS))
1964 current_link_up = 1;
1965 }
1966
1967 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1968 if (current_link_up == 1) {
1969 if (tp->link_config.active_speed == SPEED_100 ||
1970 tp->link_config.active_speed == SPEED_10)
1971 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1972 else
1973 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1974 } else
1975 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1976
1977 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1978 if (tp->link_config.active_duplex == DUPLEX_HALF)
1979 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1980
1981 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1983 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1984 (current_link_up == 1 &&
1985 tp->link_config.active_speed == SPEED_10))
1986 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1987 } else {
1988 if (current_link_up == 1)
1989 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1990 }
1991
1992 /* ??? Without this setting Netgear GA302T PHY does not
1993 * ??? send/receive packets...
1994 */
1995 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1996 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1997 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1998 tw32_f(MAC_MI_MODE, tp->mi_mode);
1999 udelay(80);
2000 }
2001
2002 tw32_f(MAC_MODE, tp->mac_mode);
2003 udelay(40);
2004
2005 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2006 /* Polled via timer. */
2007 tw32_f(MAC_EVENT, 0);
2008 } else {
2009 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2010 }
2011 udelay(40);
2012
2013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2014 current_link_up == 1 &&
2015 tp->link_config.active_speed == SPEED_1000 &&
2016 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2017 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2018 udelay(120);
2019 tw32_f(MAC_STATUS,
2020 (MAC_STATUS_SYNC_CHANGED |
2021 MAC_STATUS_CFG_CHANGED));
2022 udelay(40);
2023 tg3_write_mem(tp,
2024 NIC_SRAM_FIRMWARE_MBOX,
2025 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2026 }
2027
2028 if (current_link_up != netif_carrier_ok(tp->dev)) {
2029 if (current_link_up)
2030 netif_carrier_on(tp->dev);
2031 else
2032 netif_carrier_off(tp->dev);
2033 tg3_link_report(tp);
2034 }
2035
2036 return 0;
2037}
2038
2039struct tg3_fiber_aneginfo {
2040 int state;
2041#define ANEG_STATE_UNKNOWN 0
2042#define ANEG_STATE_AN_ENABLE 1
2043#define ANEG_STATE_RESTART_INIT 2
2044#define ANEG_STATE_RESTART 3
2045#define ANEG_STATE_DISABLE_LINK_OK 4
2046#define ANEG_STATE_ABILITY_DETECT_INIT 5
2047#define ANEG_STATE_ABILITY_DETECT 6
2048#define ANEG_STATE_ACK_DETECT_INIT 7
2049#define ANEG_STATE_ACK_DETECT 8
2050#define ANEG_STATE_COMPLETE_ACK_INIT 9
2051#define ANEG_STATE_COMPLETE_ACK 10
2052#define ANEG_STATE_IDLE_DETECT_INIT 11
2053#define ANEG_STATE_IDLE_DETECT 12
2054#define ANEG_STATE_LINK_OK 13
2055#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2056#define ANEG_STATE_NEXT_PAGE_WAIT 15
2057
2058 u32 flags;
2059#define MR_AN_ENABLE 0x00000001
2060#define MR_RESTART_AN 0x00000002
2061#define MR_AN_COMPLETE 0x00000004
2062#define MR_PAGE_RX 0x00000008
2063#define MR_NP_LOADED 0x00000010
2064#define MR_TOGGLE_TX 0x00000020
2065#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2066#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2067#define MR_LP_ADV_SYM_PAUSE 0x00000100
2068#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2069#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2070#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2071#define MR_LP_ADV_NEXT_PAGE 0x00001000
2072#define MR_TOGGLE_RX 0x00002000
2073#define MR_NP_RX 0x00004000
2074
2075#define MR_LINK_OK 0x80000000
2076
2077 unsigned long link_time, cur_time;
2078
2079 u32 ability_match_cfg;
2080 int ability_match_count;
2081
2082 char ability_match, idle_match, ack_match;
2083
2084 u32 txconfig, rxconfig;
2085#define ANEG_CFG_NP 0x00000080
2086#define ANEG_CFG_ACK 0x00000040
2087#define ANEG_CFG_RF2 0x00000020
2088#define ANEG_CFG_RF1 0x00000010
2089#define ANEG_CFG_PS2 0x00000001
2090#define ANEG_CFG_PS1 0x00008000
2091#define ANEG_CFG_HD 0x00004000
2092#define ANEG_CFG_FD 0x00002000
2093#define ANEG_CFG_INVAL 0x00001f06
2094
2095};
2096#define ANEG_OK 0
2097#define ANEG_DONE 1
2098#define ANEG_TIMER_ENAB 2
2099#define ANEG_FAILED -1
2100
2101#define ANEG_STATE_SETTLE_TIME 10000
2102
2103static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2104 struct tg3_fiber_aneginfo *ap)
2105{
2106 unsigned long delta;
2107 u32 rx_cfg_reg;
2108 int ret;
2109
2110 if (ap->state == ANEG_STATE_UNKNOWN) {
2111 ap->rxconfig = 0;
2112 ap->link_time = 0;
2113 ap->cur_time = 0;
2114 ap->ability_match_cfg = 0;
2115 ap->ability_match_count = 0;
2116 ap->ability_match = 0;
2117 ap->idle_match = 0;
2118 ap->ack_match = 0;
2119 }
2120 ap->cur_time++;
2121
2122 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2123 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2124
2125 if (rx_cfg_reg != ap->ability_match_cfg) {
2126 ap->ability_match_cfg = rx_cfg_reg;
2127 ap->ability_match = 0;
2128 ap->ability_match_count = 0;
2129 } else {
2130 if (++ap->ability_match_count > 1) {
2131 ap->ability_match = 1;
2132 ap->ability_match_cfg = rx_cfg_reg;
2133 }
2134 }
2135 if (rx_cfg_reg & ANEG_CFG_ACK)
2136 ap->ack_match = 1;
2137 else
2138 ap->ack_match = 0;
2139
2140 ap->idle_match = 0;
2141 } else {
2142 ap->idle_match = 1;
2143 ap->ability_match_cfg = 0;
2144 ap->ability_match_count = 0;
2145 ap->ability_match = 0;
2146 ap->ack_match = 0;
2147
2148 rx_cfg_reg = 0;
2149 }
2150
2151 ap->rxconfig = rx_cfg_reg;
2152 ret = ANEG_OK;
2153
2154 switch(ap->state) {
2155 case ANEG_STATE_UNKNOWN:
2156 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2157 ap->state = ANEG_STATE_AN_ENABLE;
2158
2159 /* fallthru */
2160 case ANEG_STATE_AN_ENABLE:
2161 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2162 if (ap->flags & MR_AN_ENABLE) {
2163 ap->link_time = 0;
2164 ap->cur_time = 0;
2165 ap->ability_match_cfg = 0;
2166 ap->ability_match_count = 0;
2167 ap->ability_match = 0;
2168 ap->idle_match = 0;
2169 ap->ack_match = 0;
2170
2171 ap->state = ANEG_STATE_RESTART_INIT;
2172 } else {
2173 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2174 }
2175 break;
2176
2177 case ANEG_STATE_RESTART_INIT:
2178 ap->link_time = ap->cur_time;
2179 ap->flags &= ~(MR_NP_LOADED);
2180 ap->txconfig = 0;
2181 tw32(MAC_TX_AUTO_NEG, 0);
2182 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2183 tw32_f(MAC_MODE, tp->mac_mode);
2184 udelay(40);
2185
2186 ret = ANEG_TIMER_ENAB;
2187 ap->state = ANEG_STATE_RESTART;
2188
2189 /* fallthru */
2190 case ANEG_STATE_RESTART:
2191 delta = ap->cur_time - ap->link_time;
2192 if (delta > ANEG_STATE_SETTLE_TIME) {
2193 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2194 } else {
2195 ret = ANEG_TIMER_ENAB;
2196 }
2197 break;
2198
2199 case ANEG_STATE_DISABLE_LINK_OK:
2200 ret = ANEG_DONE;
2201 break;
2202
2203 case ANEG_STATE_ABILITY_DETECT_INIT:
2204 ap->flags &= ~(MR_TOGGLE_TX);
2205 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2206 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2207 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2208 tw32_f(MAC_MODE, tp->mac_mode);
2209 udelay(40);
2210
2211 ap->state = ANEG_STATE_ABILITY_DETECT;
2212 break;
2213
2214 case ANEG_STATE_ABILITY_DETECT:
2215 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2216 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2217 }
2218 break;
2219
2220 case ANEG_STATE_ACK_DETECT_INIT:
2221 ap->txconfig |= ANEG_CFG_ACK;
2222 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2223 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2224 tw32_f(MAC_MODE, tp->mac_mode);
2225 udelay(40);
2226
2227 ap->state = ANEG_STATE_ACK_DETECT;
2228
2229 /* fallthru */
2230 case ANEG_STATE_ACK_DETECT:
2231 if (ap->ack_match != 0) {
2232 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2233 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2234 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2235 } else {
2236 ap->state = ANEG_STATE_AN_ENABLE;
2237 }
2238 } else if (ap->ability_match != 0 &&
2239 ap->rxconfig == 0) {
2240 ap->state = ANEG_STATE_AN_ENABLE;
2241 }
2242 break;
2243
2244 case ANEG_STATE_COMPLETE_ACK_INIT:
2245 if (ap->rxconfig & ANEG_CFG_INVAL) {
2246 ret = ANEG_FAILED;
2247 break;
2248 }
2249 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2250 MR_LP_ADV_HALF_DUPLEX |
2251 MR_LP_ADV_SYM_PAUSE |
2252 MR_LP_ADV_ASYM_PAUSE |
2253 MR_LP_ADV_REMOTE_FAULT1 |
2254 MR_LP_ADV_REMOTE_FAULT2 |
2255 MR_LP_ADV_NEXT_PAGE |
2256 MR_TOGGLE_RX |
2257 MR_NP_RX);
2258 if (ap->rxconfig & ANEG_CFG_FD)
2259 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2260 if (ap->rxconfig & ANEG_CFG_HD)
2261 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2262 if (ap->rxconfig & ANEG_CFG_PS1)
2263 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2264 if (ap->rxconfig & ANEG_CFG_PS2)
2265 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2266 if (ap->rxconfig & ANEG_CFG_RF1)
2267 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2268 if (ap->rxconfig & ANEG_CFG_RF2)
2269 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2270 if (ap->rxconfig & ANEG_CFG_NP)
2271 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2272
2273 ap->link_time = ap->cur_time;
2274
2275 ap->flags ^= (MR_TOGGLE_TX);
2276 if (ap->rxconfig & 0x0008)
2277 ap->flags |= MR_TOGGLE_RX;
2278 if (ap->rxconfig & ANEG_CFG_NP)
2279 ap->flags |= MR_NP_RX;
2280 ap->flags |= MR_PAGE_RX;
2281
2282 ap->state = ANEG_STATE_COMPLETE_ACK;
2283 ret = ANEG_TIMER_ENAB;
2284 break;
2285
2286 case ANEG_STATE_COMPLETE_ACK:
2287 if (ap->ability_match != 0 &&
2288 ap->rxconfig == 0) {
2289 ap->state = ANEG_STATE_AN_ENABLE;
2290 break;
2291 }
2292 delta = ap->cur_time - ap->link_time;
2293 if (delta > ANEG_STATE_SETTLE_TIME) {
2294 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2295 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2296 } else {
2297 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2298 !(ap->flags & MR_NP_RX)) {
2299 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2300 } else {
2301 ret = ANEG_FAILED;
2302 }
2303 }
2304 }
2305 break;
2306
2307 case ANEG_STATE_IDLE_DETECT_INIT:
2308 ap->link_time = ap->cur_time;
2309 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2310 tw32_f(MAC_MODE, tp->mac_mode);
2311 udelay(40);
2312
2313 ap->state = ANEG_STATE_IDLE_DETECT;
2314 ret = ANEG_TIMER_ENAB;
2315 break;
2316
2317 case ANEG_STATE_IDLE_DETECT:
2318 if (ap->ability_match != 0 &&
2319 ap->rxconfig == 0) {
2320 ap->state = ANEG_STATE_AN_ENABLE;
2321 break;
2322 }
2323 delta = ap->cur_time - ap->link_time;
2324 if (delta > ANEG_STATE_SETTLE_TIME) {
2325 /* XXX another gem from the Broadcom driver :( */
2326 ap->state = ANEG_STATE_LINK_OK;
2327 }
2328 break;
2329
2330 case ANEG_STATE_LINK_OK:
2331 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2332 ret = ANEG_DONE;
2333 break;
2334
2335 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2336 /* ??? unimplemented */
2337 break;
2338
2339 case ANEG_STATE_NEXT_PAGE_WAIT:
2340 /* ??? unimplemented */
2341 break;
2342
2343 default:
2344 ret = ANEG_FAILED;
2345 break;
2346 };
2347
2348 return ret;
2349}
2350
2351static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2352{
2353 int res = 0;
2354 struct tg3_fiber_aneginfo aninfo;
2355 int status = ANEG_FAILED;
2356 unsigned int tick;
2357 u32 tmp;
2358
2359 tw32_f(MAC_TX_AUTO_NEG, 0);
2360
2361 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2362 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2363 udelay(40);
2364
2365 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2366 udelay(40);
2367
2368 memset(&aninfo, 0, sizeof(aninfo));
2369 aninfo.flags |= MR_AN_ENABLE;
2370 aninfo.state = ANEG_STATE_UNKNOWN;
2371 aninfo.cur_time = 0;
2372 tick = 0;
2373 while (++tick < 195000) {
2374 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2375 if (status == ANEG_DONE || status == ANEG_FAILED)
2376 break;
2377
2378 udelay(1);
2379 }
2380
2381 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2382 tw32_f(MAC_MODE, tp->mac_mode);
2383 udelay(40);
2384
2385 *flags = aninfo.flags;
2386
2387 if (status == ANEG_DONE &&
2388 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2389 MR_LP_ADV_FULL_DUPLEX)))
2390 res = 1;
2391
2392 return res;
2393}
2394
2395static void tg3_init_bcm8002(struct tg3 *tp)
2396{
2397 u32 mac_status = tr32(MAC_STATUS);
2398 int i;
2399
2400 /* Reset when initting first time or we have a link. */
2401 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2402 !(mac_status & MAC_STATUS_PCS_SYNCED))
2403 return;
2404
2405 /* Set PLL lock range. */
2406 tg3_writephy(tp, 0x16, 0x8007);
2407
2408 /* SW reset */
2409 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2410
2411 /* Wait for reset to complete. */
2412 /* XXX schedule_timeout() ... */
2413 for (i = 0; i < 500; i++)
2414 udelay(10);
2415
2416 /* Config mode; select PMA/Ch 1 regs. */
2417 tg3_writephy(tp, 0x10, 0x8411);
2418
2419 /* Enable auto-lock and comdet, select txclk for tx. */
2420 tg3_writephy(tp, 0x11, 0x0a10);
2421
2422 tg3_writephy(tp, 0x18, 0x00a0);
2423 tg3_writephy(tp, 0x16, 0x41ff);
2424
2425 /* Assert and deassert POR. */
2426 tg3_writephy(tp, 0x13, 0x0400);
2427 udelay(40);
2428 tg3_writephy(tp, 0x13, 0x0000);
2429
2430 tg3_writephy(tp, 0x11, 0x0a50);
2431 udelay(40);
2432 tg3_writephy(tp, 0x11, 0x0a10);
2433
2434 /* Wait for signal to stabilize */
2435 /* XXX schedule_timeout() ... */
2436 for (i = 0; i < 15000; i++)
2437 udelay(10);
2438
2439 /* Deselect the channel register so we can read the PHYID
2440 * later.
2441 */
2442 tg3_writephy(tp, 0x10, 0x8011);
2443}
2444
2445static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2446{
2447 u32 sg_dig_ctrl, sg_dig_status;
2448 u32 serdes_cfg, expected_sg_dig_ctrl;
2449 int workaround, port_a;
2450 int current_link_up;
2451
2452 serdes_cfg = 0;
2453 expected_sg_dig_ctrl = 0;
2454 workaround = 0;
2455 port_a = 1;
2456 current_link_up = 0;
2457
2458 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2459 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2460 workaround = 1;
2461 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2462 port_a = 0;
2463
2464 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2465 /* preserve bits 20-23 for voltage regulator */
2466 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2467 }
2468
2469 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2470
2471 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2472 if (sg_dig_ctrl & (1 << 31)) {
2473 if (workaround) {
2474 u32 val = serdes_cfg;
2475
2476 if (port_a)
2477 val |= 0xc010000;
2478 else
2479 val |= 0x4010000;
2480 tw32_f(MAC_SERDES_CFG, val);
2481 }
2482 tw32_f(SG_DIG_CTRL, 0x01388400);
2483 }
2484 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2485 tg3_setup_flow_control(tp, 0, 0);
2486 current_link_up = 1;
2487 }
2488 goto out;
2489 }
2490
2491 /* Want auto-negotiation. */
2492 expected_sg_dig_ctrl = 0x81388400;
2493
2494 /* Pause capability */
2495 expected_sg_dig_ctrl |= (1 << 11);
2496
2497 /* Asymettric pause */
2498 expected_sg_dig_ctrl |= (1 << 12);
2499
2500 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2501 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2502 tp->serdes_counter &&
2503 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2504 MAC_STATUS_RCVD_CFG)) ==
2505 MAC_STATUS_PCS_SYNCED)) {
2506 tp->serdes_counter--;
2507 current_link_up = 1;
2508 goto out;
2509 }
2510restart_autoneg:
1da177e4
LT		 2511 if (workaround)
2512 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2513 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2514 udelay(5);
2515 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2516
3d3ebe74
MC		 2517 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2518 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2519 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2520 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2521 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2522 mac_status = tr32(MAC_STATUS);
2523
2524 if ((sg_dig_status & (1 << 1)) &&
2525 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2526 u32 local_adv, remote_adv;
2527
2528 local_adv = ADVERTISE_PAUSE_CAP;
2529 remote_adv = 0;
2530 if (sg_dig_status & (1 << 19))
2531 remote_adv |= LPA_PAUSE_CAP;
2532 if (sg_dig_status & (1 << 20))
2533 remote_adv |= LPA_PAUSE_ASYM;
2534
2535 tg3_setup_flow_control(tp, local_adv, remote_adv);
2536 current_link_up = 1;
3d3ebe74
MC		 2537 tp->serdes_counter = 0;
2538 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2539 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2540 if (tp->serdes_counter)
2541 tp->serdes_counter--;
1da177e4
LT		 2542 else {
2543 if (workaround) {
2544 u32 val = serdes_cfg;
2545
2546 if (port_a)
2547 val |= 0xc010000;
2548 else
2549 val |= 0x4010000;
2550
2551 tw32_f(MAC_SERDES_CFG, val);
2552 }
2553
2554 tw32_f(SG_DIG_CTRL, 0x01388400);
2555 udelay(40);
2556
2557 /* Link parallel detection - link is up */
2558 /* only if we have PCS_SYNC and not */
2559 /* receiving config code words */
2560 mac_status = tr32(MAC_STATUS);
2561 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2562 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2563 tg3_setup_flow_control(tp, 0, 0);
2564 current_link_up = 1;
3d3ebe74
MC		 2565 tp->tg3_flags2 |=
2566 TG3_FLG2_PARALLEL_DETECT;
2567 tp->serdes_counter =
2568 SERDES_PARALLEL_DET_TIMEOUT;
2569 } else
2570 goto restart_autoneg;
1da177e4
LT		 2571 }
2572 }
3d3ebe74
MC		 2573 } else {
2574 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2575 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2576 }
2577
2578out:
2579 return current_link_up;
2580}
2581
2582static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2583{
2584 int current_link_up = 0;
2585
2586 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2587 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2588 goto out;
2589 }
2590
2591 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2592 u32 flags;
2593 int i;
6aa20a22 2594
1da177e4
LT		 2595 if (fiber_autoneg(tp, &flags)) {
2596 u32 local_adv, remote_adv;
2597
2598 local_adv = ADVERTISE_PAUSE_CAP;
2599 remote_adv = 0;
2600 if (flags & MR_LP_ADV_SYM_PAUSE)
2601 remote_adv |= LPA_PAUSE_CAP;
2602 if (flags & MR_LP_ADV_ASYM_PAUSE)
2603 remote_adv |= LPA_PAUSE_ASYM;
2604
2605 tg3_setup_flow_control(tp, local_adv, remote_adv);
2606
2607 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2608 current_link_up = 1;
2609 }
2610 for (i = 0; i < 30; i++) {
2611 udelay(20);
2612 tw32_f(MAC_STATUS,
2613 (MAC_STATUS_SYNC_CHANGED |
2614 MAC_STATUS_CFG_CHANGED));
2615 udelay(40);
2616 if ((tr32(MAC_STATUS) &
2617 (MAC_STATUS_SYNC_CHANGED |
2618 MAC_STATUS_CFG_CHANGED)) == 0)
2619 break;
2620 }
2621
2622 mac_status = tr32(MAC_STATUS);
2623 if (current_link_up == 0 &&
2624 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2625 !(mac_status & MAC_STATUS_RCVD_CFG))
2626 current_link_up = 1;
2627 } else {
2628 /* Forcing 1000FD link up. */
2629 current_link_up = 1;
2630 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2631
2632 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2633 udelay(40);
2634 }
2635
2636out:
2637 return current_link_up;
2638}
2639
2640static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2641{
2642 u32 orig_pause_cfg;
2643 u16 orig_active_speed;
2644 u8 orig_active_duplex;
2645 u32 mac_status;
2646 int current_link_up;
2647 int i;
2648
2649 orig_pause_cfg =
2650 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2651 TG3_FLAG_TX_PAUSE));
2652 orig_active_speed = tp->link_config.active_speed;
2653 orig_active_duplex = tp->link_config.active_duplex;
2654
2655 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2656 netif_carrier_ok(tp->dev) &&
2657 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2658 mac_status = tr32(MAC_STATUS);
2659 mac_status &= (MAC_STATUS_PCS_SYNCED |
2660 MAC_STATUS_SIGNAL_DET |
2661 MAC_STATUS_CFG_CHANGED |
2662 MAC_STATUS_RCVD_CFG);
2663 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2664 MAC_STATUS_SIGNAL_DET)) {
2665 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2666 MAC_STATUS_CFG_CHANGED));
2667 return 0;
2668 }
2669 }
2670
2671 tw32_f(MAC_TX_AUTO_NEG, 0);
2672
2673 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2674 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2675 tw32_f(MAC_MODE, tp->mac_mode);
2676 udelay(40);
2677
2678 if (tp->phy_id == PHY_ID_BCM8002)
2679 tg3_init_bcm8002(tp);
2680
2681 /* Enable link change event even when serdes polling. */
2682 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2683 udelay(40);
2684
2685 current_link_up = 0;
2686 mac_status = tr32(MAC_STATUS);
2687
2688 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2689 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2690 else
2691 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2692
2693 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2694 tw32_f(MAC_MODE, tp->mac_mode);
2695 udelay(40);
2696
2697 tp->hw_status->status =
2698 (SD_STATUS_UPDATED |
2699 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2700
2701 for (i = 0; i < 100; i++) {
2702 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2703 MAC_STATUS_CFG_CHANGED));
2704 udelay(5);
2705 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2706 MAC_STATUS_CFG_CHANGED |
2707 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2708 break;
2709 }
2710
2711 mac_status = tr32(MAC_STATUS);
2712 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2713 current_link_up = 0;
3d3ebe74
MC		 2714 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2715 tp->serdes_counter == 0) {
1da177e4
LT		 2716 tw32_f(MAC_MODE, (tp->mac_mode |
2717 MAC_MODE_SEND_CONFIGS));
2718 udelay(1);
2719 tw32_f(MAC_MODE, tp->mac_mode);
2720 }
2721 }
2722
2723 if (current_link_up == 1) {
2724 tp->link_config.active_speed = SPEED_1000;
2725 tp->link_config.active_duplex = DUPLEX_FULL;
2726 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2727 LED_CTRL_LNKLED_OVERRIDE |
2728 LED_CTRL_1000MBPS_ON));
2729 } else {
2730 tp->link_config.active_speed = SPEED_INVALID;
2731 tp->link_config.active_duplex = DUPLEX_INVALID;
2732 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2733 LED_CTRL_LNKLED_OVERRIDE |
2734 LED_CTRL_TRAFFIC_OVERRIDE));
2735 }
2736
2737 if (current_link_up != netif_carrier_ok(tp->dev)) {
2738 if (current_link_up)
2739 netif_carrier_on(tp->dev);
2740 else
2741 netif_carrier_off(tp->dev);
2742 tg3_link_report(tp);
2743 } else {
2744 u32 now_pause_cfg =
2745 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2746 TG3_FLAG_TX_PAUSE);
2747 if (orig_pause_cfg != now_pause_cfg ||
2748 orig_active_speed != tp->link_config.active_speed ||
2749 orig_active_duplex != tp->link_config.active_duplex)
2750 tg3_link_report(tp);
2751 }
2752
2753 return 0;
2754}
2755
747e8f8b
MC		 2756static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2757{
2758 int current_link_up, err = 0;
2759 u32 bmsr, bmcr;
2760 u16 current_speed;
2761 u8 current_duplex;
2762
2763 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2764 tw32_f(MAC_MODE, tp->mac_mode);
2765 udelay(40);
2766
2767 tw32(MAC_EVENT, 0);
2768
2769 tw32_f(MAC_STATUS,
2770 (MAC_STATUS_SYNC_CHANGED |
2771 MAC_STATUS_CFG_CHANGED |
2772 MAC_STATUS_MI_COMPLETION |
2773 MAC_STATUS_LNKSTATE_CHANGED));
2774 udelay(40);
2775
2776 if (force_reset)
2777 tg3_phy_reset(tp);
2778
2779 current_link_up = 0;
2780 current_speed = SPEED_INVALID;
2781 current_duplex = DUPLEX_INVALID;
2782
2783 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2784 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2785 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2786 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2787 bmsr |= BMSR_LSTATUS;
2788 else
2789 bmsr &= ~BMSR_LSTATUS;
2790 }
747e8f8b
MC		 2791
2792 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2793
2794 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2795 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2796 /* do nothing, just check for link up at the end */
2797 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2798 u32 adv, new_adv;
2799
2800 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2801 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2802 ADVERTISE_1000XPAUSE |
2803 ADVERTISE_1000XPSE_ASYM |
2804 ADVERTISE_SLCT);
2805
2806 /* Always advertise symmetric PAUSE just like copper */
2807 new_adv |= ADVERTISE_1000XPAUSE;
2808
2809 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2810 new_adv |= ADVERTISE_1000XHALF;
2811 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2812 new_adv |= ADVERTISE_1000XFULL;
2813
2814 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2815 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2816 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2817 tg3_writephy(tp, MII_BMCR, bmcr);
2818
2819 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2820 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2821 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2822
2823 return err;
2824 }
2825 } else {
2826 u32 new_bmcr;
2827
2828 bmcr &= ~BMCR_SPEED1000;
2829 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2830
2831 if (tp->link_config.duplex == DUPLEX_FULL)
2832 new_bmcr |= BMCR_FULLDPLX;
2833
2834 if (new_bmcr != bmcr) {
2835 /* BMCR_SPEED1000 is a reserved bit that needs
2836 * to be set on write.
2837 */
2838 new_bmcr |= BMCR_SPEED1000;
2839
2840 /* Force a linkdown */
2841 if (netif_carrier_ok(tp->dev)) {
2842 u32 adv;
2843
2844 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2845 adv &= ~(ADVERTISE_1000XFULL |
2846 ADVERTISE_1000XHALF |
2847 ADVERTISE_SLCT);
2848 tg3_writephy(tp, MII_ADVERTISE, adv);
2849 tg3_writephy(tp, MII_BMCR, bmcr |
2850 BMCR_ANRESTART |
2851 BMCR_ANENABLE);
2852 udelay(10);
2853 netif_carrier_off(tp->dev);
2854 }
2855 tg3_writephy(tp, MII_BMCR, new_bmcr);
2856 bmcr = new_bmcr;
2857 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2858 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2859 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2860 ASIC_REV_5714) {
2861 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2862 bmsr |= BMSR_LSTATUS;
2863 else
2864 bmsr &= ~BMSR_LSTATUS;
2865 }
747e8f8b
MC		 2866 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2867 }
2868 }
2869
2870 if (bmsr & BMSR_LSTATUS) {
2871 current_speed = SPEED_1000;
2872 current_link_up = 1;
2873 if (bmcr & BMCR_FULLDPLX)
2874 current_duplex = DUPLEX_FULL;
2875 else
2876 current_duplex = DUPLEX_HALF;
2877
2878 if (bmcr & BMCR_ANENABLE) {
2879 u32 local_adv, remote_adv, common;
2880
2881 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2882 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2883 common = local_adv & remote_adv;
2884 if (common & (ADVERTISE_1000XHALF |
2885 ADVERTISE_1000XFULL)) {
2886 if (common & ADVERTISE_1000XFULL)
2887 current_duplex = DUPLEX_FULL;
2888 else
2889 current_duplex = DUPLEX_HALF;
2890
2891 tg3_setup_flow_control(tp, local_adv,
2892 remote_adv);
2893 }
2894 else
2895 current_link_up = 0;
2896 }
2897 }
2898
2899 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2900 if (tp->link_config.active_duplex == DUPLEX_HALF)
2901 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2902
2903 tw32_f(MAC_MODE, tp->mac_mode);
2904 udelay(40);
2905
2906 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2907
2908 tp->link_config.active_speed = current_speed;
2909 tp->link_config.active_duplex = current_duplex;
2910
2911 if (current_link_up != netif_carrier_ok(tp->dev)) {
2912 if (current_link_up)
2913 netif_carrier_on(tp->dev);
2914 else {
2915 netif_carrier_off(tp->dev);
2916 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2917 }
2918 tg3_link_report(tp);
2919 }
2920 return err;
2921}
2922
2923static void tg3_serdes_parallel_detect(struct tg3 *tp)
2924{
3d3ebe74 2925 if (tp->serdes_counter) {
747e8f8b 2926 /* Give autoneg time to complete. */
3d3ebe74 2927 tp->serdes_counter--;
747e8f8b
MC		 2928 return;
2929 }
2930 if (!netif_carrier_ok(tp->dev) &&
2931 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2932 u32 bmcr;
2933
2934 tg3_readphy(tp, MII_BMCR, &bmcr);
2935 if (bmcr & BMCR_ANENABLE) {
2936 u32 phy1, phy2;
2937
2938 /* Select shadow register 0x1f */
2939 tg3_writephy(tp, 0x1c, 0x7c00);
2940 tg3_readphy(tp, 0x1c, &phy1);
2941
2942 /* Select expansion interrupt status register */
2943 tg3_writephy(tp, 0x17, 0x0f01);
2944 tg3_readphy(tp, 0x15, &phy2);
2945 tg3_readphy(tp, 0x15, &phy2);
2946
2947 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2948 /* We have signal detect and not receiving
2949 * config code words, link is up by parallel
2950 * detection.
2951 */
2952
2953 bmcr &= ~BMCR_ANENABLE;
2954 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2955 tg3_writephy(tp, MII_BMCR, bmcr);
2956 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2957 }
2958 }
2959 }
2960 else if (netif_carrier_ok(tp->dev) &&
2961 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2962 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2963 u32 phy2;
2964
2965 /* Select expansion interrupt status register */
2966 tg3_writephy(tp, 0x17, 0x0f01);
2967 tg3_readphy(tp, 0x15, &phy2);
2968 if (phy2 & 0x20) {
2969 u32 bmcr;
2970
2971 /* Config code words received, turn on autoneg. */
2972 tg3_readphy(tp, MII_BMCR, &bmcr);
2973 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2974
2975 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2976
2977 }
2978 }
2979}
2980
1da177e4
LT		 2981static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2982{
2983 int err;
2984
2985 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2986 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2987 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2988 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2989 } else {
2990 err = tg3_setup_copper_phy(tp, force_reset);
2991 }
2992
2993 if (tp->link_config.active_speed == SPEED_1000 &&
2994 tp->link_config.active_duplex == DUPLEX_HALF)
2995 tw32(MAC_TX_LENGTHS,
2996 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2997 (6 << TX_LENGTHS_IPG_SHIFT) |
2998 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2999 else
3000 tw32(MAC_TX_LENGTHS,
3001 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3002 (6 << TX_LENGTHS_IPG_SHIFT) |
3003 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3004
3005 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3006 if (netif_carrier_ok(tp->dev)) {
3007 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3008 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3009 } else {
3010 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3011 }
3012 }
3013
3014 return err;
3015}
3016
df3e6548
MC		 3017/* This is called whenever we suspect that the system chipset is re-
3018 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3019 * is bogus tx completions. We try to recover by setting the
3020 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3021 * in the workqueue.
3022 */
3023static void tg3_tx_recover(struct tg3 *tp)
3024{
3025 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3026 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3027
3028 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3029 "mapped I/O cycles to the network device, attempting to "
3030 "recover. Please report the problem to the driver maintainer "
3031 "and include system chipset information.\n", tp->dev->name);
3032
3033 spin_lock(&tp->lock);
df3e6548 3034 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3035 spin_unlock(&tp->lock);
3036}
3037
1b2a7205
MC		 3038static inline u32 tg3_tx_avail(struct tg3 *tp)
3039{
3040 smp_mb();
3041 return (tp->tx_pending -
3042 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3043}
3044
1da177e4
LT		 3045/* Tigon3 never reports partial packet sends. So we do not
3046 * need special logic to handle SKBs that have not had all
3047 * of their frags sent yet, like SunGEM does.
3048 */
3049static void tg3_tx(struct tg3 *tp)
3050{
3051 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3052 u32 sw_idx = tp->tx_cons;
3053
3054 while (sw_idx != hw_idx) {
3055 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3056 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3057 int i, tx_bug = 0;
3058
3059 if (unlikely(skb == NULL)) {
3060 tg3_tx_recover(tp);
3061 return;
3062 }
1da177e4 3063
1da177e4
LT		 3064 pci_unmap_single(tp->pdev,
3065 pci_unmap_addr(ri, mapping),
3066 skb_headlen(skb),
3067 PCI_DMA_TODEVICE);
3068
3069 ri->skb = NULL;
3070
3071 sw_idx = NEXT_TX(sw_idx);
3072
3073 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3074 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3075 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3076 tx_bug = 1;
1da177e4
LT		 3077
3078 pci_unmap_page(tp->pdev,
3079 pci_unmap_addr(ri, mapping),
3080 skb_shinfo(skb)->frags[i].size,
3081 PCI_DMA_TODEVICE);
3082
3083 sw_idx = NEXT_TX(sw_idx);
3084 }
3085
f47c11ee 3086 dev_kfree_skb(skb);
df3e6548
MC		 3087
3088 if (unlikely(tx_bug)) {
3089 tg3_tx_recover(tp);
3090 return;
3091 }
1da177e4
LT		 3092 }
3093
3094 tp->tx_cons = sw_idx;
3095
1b2a7205
MC		 3096 /* Need to make the tx_cons update visible to tg3_start_xmit()
3097 * before checking for netif_queue_stopped(). Without the
3098 * memory barrier, there is a small possibility that tg3_start_xmit()
3099 * will miss it and cause the queue to be stopped forever.
3100 */
3101 smp_mb();
3102
3103 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3104 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3105 netif_tx_lock(tp->dev);
51b91468 3106 if (netif_queue_stopped(tp->dev) &&
42952231 3107 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3108 netif_wake_queue(tp->dev);
1b2a7205 3109 netif_tx_unlock(tp->dev);
51b91468 3110 }
1da177e4
LT		 3111}
3112
3113/* Returns size of skb allocated or < 0 on error.
3114 *
3115 * We only need to fill in the address because the other members
3116 * of the RX descriptor are invariant, see tg3_init_rings.
3117 *
3118 * Note the purposeful assymetry of cpu vs. chip accesses. For
3119 * posting buffers we only dirty the first cache line of the RX
3120 * descriptor (containing the address). Whereas for the RX status
3121 * buffers the cpu only reads the last cacheline of the RX descriptor
3122 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3123 */
3124static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3125 int src_idx, u32 dest_idx_unmasked)
3126{
3127 struct tg3_rx_buffer_desc *desc;
3128 struct ring_info *map, *src_map;
3129 struct sk_buff *skb;
3130 dma_addr_t mapping;
3131 int skb_size, dest_idx;
3132
3133 src_map = NULL;
3134 switch (opaque_key) {
3135 case RXD_OPAQUE_RING_STD:
3136 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3137 desc = &tp->rx_std[dest_idx];
3138 map = &tp->rx_std_buffers[dest_idx];
3139 if (src_idx >= 0)
3140 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3141 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3142 break;
3143
3144 case RXD_OPAQUE_RING_JUMBO:
3145 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3146 desc = &tp->rx_jumbo[dest_idx];
3147 map = &tp->rx_jumbo_buffers[dest_idx];
3148 if (src_idx >= 0)
3149 src_map = &tp->rx_jumbo_buffers[src_idx];
3150 skb_size = RX_JUMBO_PKT_BUF_SZ;
3151 break;
3152
3153 default:
3154 return -EINVAL;
3155 };
3156
3157 /* Do not overwrite any of the map or rp information
3158 * until we are sure we can commit to a new buffer.
3159 *
3160 * Callers depend upon this behavior and assume that
3161 * we leave everything unchanged if we fail.
3162 */
a20e9c62 3163 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3164 if (skb == NULL)
3165 return -ENOMEM;
3166
1da177e4
LT		 3167 skb_reserve(skb, tp->rx_offset);
3168
3169 mapping = pci_map_single(tp->pdev, skb->data,
3170 skb_size - tp->rx_offset,
3171 PCI_DMA_FROMDEVICE);
3172
3173 map->skb = skb;
3174 pci_unmap_addr_set(map, mapping, mapping);
3175
3176 if (src_map != NULL)
3177 src_map->skb = NULL;
3178
3179 desc->addr_hi = ((u64)mapping >> 32);
3180 desc->addr_lo = ((u64)mapping & 0xffffffff);
3181
3182 return skb_size;
3183}
3184
3185/* We only need to move over in the address because the other
3186 * members of the RX descriptor are invariant. See notes above
3187 * tg3_alloc_rx_skb for full details.
3188 */
3189static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3190 int src_idx, u32 dest_idx_unmasked)
3191{
3192 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3193 struct ring_info *src_map, *dest_map;
3194 int dest_idx;
3195
3196 switch (opaque_key) {
3197 case RXD_OPAQUE_RING_STD:
3198 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3199 dest_desc = &tp->rx_std[dest_idx];
3200 dest_map = &tp->rx_std_buffers[dest_idx];
3201 src_desc = &tp->rx_std[src_idx];
3202 src_map = &tp->rx_std_buffers[src_idx];
3203 break;
3204
3205 case RXD_OPAQUE_RING_JUMBO:
3206 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207 dest_desc = &tp->rx_jumbo[dest_idx];
3208 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3209 src_desc = &tp->rx_jumbo[src_idx];
3210 src_map = &tp->rx_jumbo_buffers[src_idx];
3211 break;
3212
3213 default:
3214 return;
3215 };
3216
3217 dest_map->skb = src_map->skb;
3218 pci_unmap_addr_set(dest_map, mapping,
3219 pci_unmap_addr(src_map, mapping));
3220 dest_desc->addr_hi = src_desc->addr_hi;
3221 dest_desc->addr_lo = src_desc->addr_lo;
3222
3223 src_map->skb = NULL;
3224}
3225
3226#if TG3_VLAN_TAG_USED
3227static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3228{
3229 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3230}
3231#endif
3232
3233/* The RX ring scheme is composed of multiple rings which post fresh
3234 * buffers to the chip, and one special ring the chip uses to report
3235 * status back to the host.
3236 *
3237 * The special ring reports the status of received packets to the
3238 * host. The chip does not write into the original descriptor the
3239 * RX buffer was obtained from. The chip simply takes the original
3240 * descriptor as provided by the host, updates the status and length
3241 * field, then writes this into the next status ring entry.
3242 *
3243 * Each ring the host uses to post buffers to the chip is described
3244 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3245 * it is first placed into the on-chip ram. When the packet's length
3246 * is known, it walks down the TG3_BDINFO entries to select the ring.
3247 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3248 * which is within the range of the new packet's length is chosen.
3249 *
3250 * The "separate ring for rx status" scheme may sound queer, but it makes
3251 * sense from a cache coherency perspective. If only the host writes
3252 * to the buffer post rings, and only the chip writes to the rx status
3253 * rings, then cache lines never move beyond shared-modified state.
3254 * If both the host and chip were to write into the same ring, cache line
3255 * eviction could occur since both entities want it in an exclusive state.
3256 */
3257static int tg3_rx(struct tg3 *tp, int budget)
3258{
f92905de 3259 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3260 u32 sw_idx = tp->rx_rcb_ptr;
3261 u16 hw_idx;
1da177e4
LT		 3262 int received;
3263
3264 hw_idx = tp->hw_status->idx[0].rx_producer;
3265 /*
3266 * We need to order the read of hw_idx and the read of
3267 * the opaque cookie.
3268 */
3269 rmb();
1da177e4
LT		 3270 work_mask = 0;
3271 received = 0;
3272 while (sw_idx != hw_idx && budget > 0) {
3273 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3274 unsigned int len;
3275 struct sk_buff *skb;
3276 dma_addr_t dma_addr;
3277 u32 opaque_key, desc_idx, *post_ptr;
3278
3279 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3280 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3281 if (opaque_key == RXD_OPAQUE_RING_STD) {
3282 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3283 mapping);
3284 skb = tp->rx_std_buffers[desc_idx].skb;
3285 post_ptr = &tp->rx_std_ptr;
f92905de 3286 rx_std_posted++;
1da177e4
LT		 3287 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3288 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3289 mapping);
3290 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3291 post_ptr = &tp->rx_jumbo_ptr;
3292 }
3293 else {
3294 goto next_pkt_nopost;
3295 }
3296
3297 work_mask |= opaque_key;
3298
3299 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3300 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3301 drop_it:
3302 tg3_recycle_rx(tp, opaque_key,
3303 desc_idx, *post_ptr);
3304 drop_it_no_recycle:
3305 /* Other statistics kept track of by card. */
3306 tp->net_stats.rx_dropped++;
3307 goto next_pkt;
3308 }
3309
3310 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3311
6aa20a22 3312 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3313 && tp->rx_offset == 2
3314 /* rx_offset != 2 iff this is a 5701 card running
3315 * in PCI-X mode [see tg3_get_invariants()] */
3316 ) {
3317 int skb_size;
3318
3319 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3320 desc_idx, *post_ptr);
3321 if (skb_size < 0)
3322 goto drop_it;
3323
3324 pci_unmap_single(tp->pdev, dma_addr,
3325 skb_size - tp->rx_offset,
3326 PCI_DMA_FROMDEVICE);
3327
3328 skb_put(skb, len);
3329 } else {
3330 struct sk_buff *copy_skb;
3331
3332 tg3_recycle_rx(tp, opaque_key,
3333 desc_idx, *post_ptr);
3334
a20e9c62 3335 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3336 if (copy_skb == NULL)
3337 goto drop_it_no_recycle;
3338
1da177e4
LT		 3339 skb_reserve(copy_skb, 2);
3340 skb_put(copy_skb, len);
3341 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3342 memcpy(copy_skb->data, skb->data, len);
3343 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3344
3345 /* We'll reuse the original ring buffer. */
3346 skb = copy_skb;
3347 }
3348
3349 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3350 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3351 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3352 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3353 skb->ip_summed = CHECKSUM_UNNECESSARY;
3354 else
3355 skb->ip_summed = CHECKSUM_NONE;
3356
3357 skb->protocol = eth_type_trans(skb, tp->dev);
3358#if TG3_VLAN_TAG_USED
3359 if (tp->vlgrp != NULL &&
3360 desc->type_flags & RXD_FLAG_VLAN) {
3361 tg3_vlan_rx(tp, skb,
3362 desc->err_vlan & RXD_VLAN_MASK);
3363 } else
3364#endif
3365 netif_receive_skb(skb);
3366
3367 tp->dev->last_rx = jiffies;
3368 received++;
3369 budget--;
3370
3371next_pkt:
3372 (*post_ptr)++;
f92905de
MC		 3373
3374 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3375 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3376
3377 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3378 TG3_64BIT_REG_LOW, idx);
3379 work_mask &= ~RXD_OPAQUE_RING_STD;
3380 rx_std_posted = 0;
3381 }
1da177e4 3382next_pkt_nopost:
483ba50b 3383 sw_idx++;
6b31a515 3384 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3385
3386 /* Refresh hw_idx to see if there is new work */
3387 if (sw_idx == hw_idx) {
3388 hw_idx = tp->hw_status->idx[0].rx_producer;
3389 rmb();
3390 }
1da177e4
LT		 3391 }
3392
3393 /* ACK the status ring. */
483ba50b
MC		 3394 tp->rx_rcb_ptr = sw_idx;
3395 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3396
3397 /* Refill RX ring(s). */
3398 if (work_mask & RXD_OPAQUE_RING_STD) {
3399 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3400 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3401 sw_idx);
3402 }
3403 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3404 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3405 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3406 sw_idx);
3407 }
3408 mmiowb();
3409
3410 return received;
3411}
3412
3413static int tg3_poll(struct net_device *netdev, int *budget)
3414{
3415 struct tg3 *tp = netdev_priv(netdev);
3416 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3417 int done;
3418
1da177e4
LT		 3419 /* handle link change and other phy events */
3420 if (!(tp->tg3_flags &
3421 (TG3_FLAG_USE_LINKCHG_REG |
3422 TG3_FLAG_POLL_SERDES))) {
3423 if (sblk->status & SD_STATUS_LINK_CHG) {
3424 sblk->status = SD_STATUS_UPDATED |
3425 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3426 spin_lock(&tp->lock);
1da177e4 3427 tg3_setup_phy(tp, 0);
f47c11ee 3428 spin_unlock(&tp->lock);
1da177e4
LT		 3429 }
3430 }
3431
3432 /* run TX completion thread */
3433 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3434 tg3_tx(tp);
df3e6548
MC		 3435 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3436 netif_rx_complete(netdev);
3437 schedule_work(&tp->reset_task);
3438 return 0;
3439 }
1da177e4
LT		 3440 }
3441
1da177e4
LT		 3442 /* run RX thread, within the bounds set by NAPI.
3443 * All RX "locking" is done by ensuring outside
3444 * code synchronizes with dev->poll()
3445 */
1da177e4
LT		 3446 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3447 int orig_budget = *budget;
3448 int work_done;
3449
3450 if (orig_budget > netdev->quota)
3451 orig_budget = netdev->quota;
3452
3453 work_done = tg3_rx(tp, orig_budget);
3454
3455 *budget -= work_done;
3456 netdev->quota -= work_done;
1da177e4
LT		 3457 }
3458
38f3843e 3459 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3460 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3461 rmb();
3462 } else
3463 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3464
1da177e4 3465 /* if no more work, tell net stack and NIC we're done */
f7383c22 3466 done = !tg3_has_work(tp);
1da177e4 3467 if (done) {
f47c11ee 3468 netif_rx_complete(netdev);
1da177e4 3469 tg3_restart_ints(tp);
1da177e4
LT		 3470 }
3471
3472 return (done ? 0 : 1);
3473}
3474
f47c11ee
DM		 3475static void tg3_irq_quiesce(struct tg3 *tp)
3476{
3477 BUG_ON(tp->irq_sync);
3478
3479 tp->irq_sync = 1;
3480 smp_mb();
3481
3482 synchronize_irq(tp->pdev->irq);
3483}
3484
3485static inline int tg3_irq_sync(struct tg3 *tp)
3486{
3487 return tp->irq_sync;
3488}
3489
3490/* Fully shutdown all tg3 driver activity elsewhere in the system.
3491 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3492 * with as well. Most of the time, this is not necessary except when
3493 * shutting down the device.
3494 */
3495static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3496{
3497 if (irq_sync)
3498 tg3_irq_quiesce(tp);
3499 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3500}
3501
3502static inline void tg3_full_unlock(struct tg3 *tp)
3503{
f47c11ee
DM		 3504 spin_unlock_bh(&tp->lock);
3505}
3506
fcfa0a32
MC		 3507/* One-shot MSI handler - Chip automatically disables interrupt
3508 * after sending MSI so driver doesn't have to do it.
3509 */
7d12e780 3510static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3511{
3512 struct net_device *dev = dev_id;
3513 struct tg3 *tp = netdev_priv(dev);
3514
3515 prefetch(tp->hw_status);
3516 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3517
3518 if (likely(!tg3_irq_sync(tp)))
3519 netif_rx_schedule(dev); /* schedule NAPI poll */
3520
3521 return IRQ_HANDLED;
3522}
3523
88b06bc2
MC		 3524/* MSI ISR - No need to check for interrupt sharing and no need to
3525 * flush status block and interrupt mailbox. PCI ordering rules
3526 * guarantee that MSI will arrive after the status block.
3527 */
7d12e780 3528static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3529{
3530 struct net_device *dev = dev_id;
3531 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3532
61487480
MC		 3533 prefetch(tp->hw_status);
3534 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3535 /*
fac9b83e 3536 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3537 * chip-internal interrupt pending events.
fac9b83e 3538 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3539 * NIC to stop sending us irqs, engaging "in-intr-handler"
3540 * event coalescing.
3541 */
3542 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3543 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3544 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3545
88b06bc2
MC		 3546 return IRQ_RETVAL(1);
3547}
3548
7d12e780 3549static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3550{
3551 struct net_device *dev = dev_id;
3552 struct tg3 *tp = netdev_priv(dev);
3553 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3554 unsigned int handled = 1;
3555
1da177e4
LT		 3556 /* In INTx mode, it is possible for the interrupt to arrive at
3557 * the CPU before the status block posted prior to the interrupt.
3558 * Reading the PCI State register will confirm whether the
3559 * interrupt is ours and will flush the status block.
3560 */
3561 if ((sblk->status & SD_STATUS_UPDATED) ||
3562 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3563 /*
fac9b83e 3564 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3565 * chip-internal interrupt pending events.
fac9b83e 3566 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3567 * NIC to stop sending us irqs, engaging "in-intr-handler"
3568 * event coalescing.
3569 */
3570 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3571 0x00000001);
f47c11ee
DM		 3572 if (tg3_irq_sync(tp))
3573 goto out;
fac9b83e 3574 sblk->status &= ~SD_STATUS_UPDATED;
61487480
MC		 3575 if (likely(tg3_has_work(tp))) {
3576 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
fac9b83e 3577 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3578 } else {
fac9b83e
DM		 3579 /* No work, shared interrupt perhaps? re-enable
3580 * interrupts, and flush that PCI write
3581 */
09ee929c 3582 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3583 0x00000000);
fac9b83e
DM		 3584 }
3585 } else { /* shared interrupt */
3586 handled = 0;
3587 }
f47c11ee 3588out:
fac9b83e
DM		 3589 return IRQ_RETVAL(handled);
3590}
3591
7d12e780 3592static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3593{
3594 struct net_device *dev = dev_id;
3595 struct tg3 *tp = netdev_priv(dev);
3596 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3597 unsigned int handled = 1;
3598
fac9b83e
DM		 3599 /* In INTx mode, it is possible for the interrupt to arrive at
3600 * the CPU before the status block posted prior to the interrupt.
3601 * Reading the PCI State register will confirm whether the
3602 * interrupt is ours and will flush the status block.
3603 */
38f3843e 3604 if ((sblk->status_tag != tp->last_tag) ||
fac9b83e 3605 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3606 /*
fac9b83e
DM		 3607 * writing any value to intr-mbox-0 clears PCI INTA# and
3608 * chip-internal interrupt pending events.
3609 * writing non-zero to intr-mbox-0 additional tells the
3610 * NIC to stop sending us irqs, engaging "in-intr-handler"
3611 * event coalescing.
1da177e4 3612 */
fac9b83e
DM		 3613 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3614 0x00000001);
f47c11ee
DM		 3615 if (tg3_irq_sync(tp))
3616 goto out;
38f3843e 3617 if (netif_rx_schedule_prep(dev)) {
61487480 3618 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
38f3843e
MC		 3619 /* Update last_tag to mark that this status has been
3620 * seen. Because interrupt may be shared, we may be
3621 * racing with tg3_poll(), so only update last_tag
3622 * if tg3_poll() is not scheduled.
1da177e4 3623 */
38f3843e
MC		 3624 tp->last_tag = sblk->status_tag;
3625 __netif_rx_schedule(dev);
1da177e4
LT		 3626 }
3627 } else { /* shared interrupt */
3628 handled = 0;
3629 }
f47c11ee 3630out:
1da177e4
LT		 3631 return IRQ_RETVAL(handled);
3632}
3633
7938109f 3634/* ISR for interrupt test */
7d12e780 3635static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3636{
3637 struct net_device *dev = dev_id;
3638 struct tg3 *tp = netdev_priv(dev);
3639 struct tg3_hw_status *sblk = tp->hw_status;
3640
f9804ddb
MC		 3641 if ((sblk->status & SD_STATUS_UPDATED) ||
3642 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3643 tg3_disable_ints(tp);
7938109f
MC		 3644 return IRQ_RETVAL(1);
3645 }
3646 return IRQ_RETVAL(0);
3647}
3648
8e7a22e3 3649static int tg3_init_hw(struct tg3 *, int);
944d980e 3650static int tg3_halt(struct tg3 *, int, int);
1da177e4 3651
b9ec6c1b
MC		 3652/* Restart hardware after configuration changes, self-test, etc.
3653 * Invoked with tp->lock held.
3654 */
3655static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3656{
3657 int err;
3658
3659 err = tg3_init_hw(tp, reset_phy);
3660 if (err) {
3661 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3662 "aborting.\n", tp->dev->name);
3663 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3664 tg3_full_unlock(tp);
3665 del_timer_sync(&tp->timer);
3666 tp->irq_sync = 0;
3667 netif_poll_enable(tp->dev);
3668 dev_close(tp->dev);
3669 tg3_full_lock(tp, 0);
3670 }
3671 return err;
3672}
3673
1da177e4
LT		 3674#ifdef CONFIG_NET_POLL_CONTROLLER
3675static void tg3_poll_controller(struct net_device *dev)
3676{
88b06bc2
MC		 3677 struct tg3 *tp = netdev_priv(dev);
3678
7d12e780 3679 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3680}
3681#endif
3682
c4028958 3683static void tg3_reset_task(struct work_struct *work)
1da177e4 3684{
c4028958 3685 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3686 unsigned int restart_timer;
3687
7faa006f
MC		 3688 tg3_full_lock(tp, 0);
3689 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3690
3691 if (!netif_running(tp->dev)) {
3692 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3693 tg3_full_unlock(tp);
3694 return;
3695 }
3696
3697 tg3_full_unlock(tp);
3698
1da177e4
LT		 3699 tg3_netif_stop(tp);
3700
f47c11ee 3701 tg3_full_lock(tp, 1);
1da177e4
LT		 3702
3703 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3704 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3705
df3e6548
MC		 3706 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3707 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3708 tp->write32_rx_mbox = tg3_write_flush_reg32;
3709 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3710 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3711 }
3712
944d980e 3713 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3714 if (tg3_init_hw(tp, 1))
3715 goto out;
1da177e4
LT		 3716
3717 tg3_netif_start(tp);
3718
1da177e4
LT		 3719 if (restart_timer)
3720 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3721
b9ec6c1b 3722out:
7faa006f
MC		 3723 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3724
3725 tg3_full_unlock(tp);
1da177e4
LT		 3726}
3727
3728static void tg3_tx_timeout(struct net_device *dev)
3729{
3730 struct tg3 *tp = netdev_priv(dev);
3731
9f88f29f
MC		 3732 if (netif_msg_tx_err(tp))
3733 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3734 dev->name);
1da177e4
LT		 3735
3736 schedule_work(&tp->reset_task);
3737}
3738
c58ec932
MC		 3739/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3740static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3741{
3742 u32 base = (u32) mapping & 0xffffffff;
3743
3744 return ((base > 0xffffdcc0) &&
3745 (base + len + 8 < base));
3746}
3747
72f2afb8
MC		 3748/* Test for DMA addresses > 40-bit */
3749static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3750 int len)
3751{
3752#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3753 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3754 return (((u64) mapping + len) > DMA_40BIT_MASK);
3755 return 0;
3756#else
3757 return 0;
3758#endif
3759}
3760
1da177e4
LT		 3761static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3762
72f2afb8
MC		 3763/* Workaround 4GB and 40-bit hardware DMA bugs. */
3764static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3765 u32 last_plus_one, u32 *start,
3766 u32 base_flags, u32 mss)
1da177e4
LT		 3767{
3768 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3769 dma_addr_t new_addr = 0;
1da177e4 3770 u32 entry = *start;
c58ec932 3771 int i, ret = 0;
1da177e4
LT		 3772
3773 if (!new_skb) {
c58ec932
MC		 3774 ret = -1;
3775 } else {
3776 /* New SKB is guaranteed to be linear. */
3777 entry = *start;
3778 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3779 PCI_DMA_TODEVICE);
3780 /* Make sure new skb does not cross any 4G boundaries.
3781 * Drop the packet if it does.
3782 */
3783 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3784 ret = -1;
3785 dev_kfree_skb(new_skb);
3786 new_skb = NULL;
3787 } else {
3788 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3789 base_flags, 1 | (mss << 1));
3790 *start = NEXT_TX(entry);
3791 }
1da177e4
LT		 3792 }
3793
1da177e4
LT		 3794 /* Now clean up the sw ring entries. */
3795 i = 0;
3796 while (entry != last_plus_one) {
3797 int len;
3798
3799 if (i == 0)
3800 len = skb_headlen(skb);
3801 else
3802 len = skb_shinfo(skb)->frags[i-1].size;
3803 pci_unmap_single(tp->pdev,
3804 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3805 len, PCI_DMA_TODEVICE);
3806 if (i == 0) {
3807 tp->tx_buffers[entry].skb = new_skb;
3808 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3809 } else {
3810 tp->tx_buffers[entry].skb = NULL;
3811 }
3812 entry = NEXT_TX(entry);
3813 i++;
3814 }
3815
3816 dev_kfree_skb(skb);
3817
c58ec932 3818 return ret;
1da177e4
LT		 3819}
3820
3821static void tg3_set_txd(struct tg3 *tp, int entry,
3822 dma_addr_t mapping, int len, u32 flags,
3823 u32 mss_and_is_end)
3824{
3825 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3826 int is_end = (mss_and_is_end & 0x1);
3827 u32 mss = (mss_and_is_end >> 1);
3828 u32 vlan_tag = 0;
3829
3830 if (is_end)
3831 flags |= TXD_FLAG_END;
3832 if (flags & TXD_FLAG_VLAN) {
3833 vlan_tag = flags >> 16;
3834 flags &= 0xffff;
3835 }
3836 vlan_tag |= (mss << TXD_MSS_SHIFT);
3837
3838 txd->addr_hi = ((u64) mapping >> 32);
3839 txd->addr_lo = ((u64) mapping & 0xffffffff);
3840 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3841 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3842}
3843
5a6f3074
MC		 3844/* hard_start_xmit for devices that don't have any bugs and
3845 * support TG3_FLG2_HW_TSO_2 only.
3846 */
1da177e4 3847static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 3848{
3849 struct tg3 *tp = netdev_priv(dev);
3850 dma_addr_t mapping;
3851 u32 len, entry, base_flags, mss;
3852
3853 len = skb_headlen(skb);
3854
00b70504
MC		 3855 /* We are running in BH disabled context with netif_tx_lock
3856 * and TX reclaim runs via tp->poll inside of a software
5a6f3074
MC		 3857 * interrupt. Furthermore, IRQ processing runs lockless so we have
3858 * no IRQ context deadlocks to worry about either. Rejoice!
3859 */
1b2a7205 3860 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 3861 if (!netif_queue_stopped(dev)) {
3862 netif_stop_queue(dev);
3863
3864 /* This is a hard error, log it. */
3865 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3866 "queue awake!\n", dev->name);
3867 }
5a6f3074
MC		 3868 return NETDEV_TX_BUSY;
3869 }
3870
3871 entry = tp->tx_prod;
3872 base_flags = 0;
5a6f3074
MC		 3873 mss = 0;
3874 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
7967168c 3875 (mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 3876 int tcp_opt_len, ip_tcp_len;
3877
3878 if (skb_header_cloned(skb) &&
3879 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3880 dev_kfree_skb(skb);
3881 goto out_unlock;
3882 }
3883
b0026624
MC		 3884 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3885 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3886 else {
3887 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3888 ip_tcp_len = (skb->nh.iph->ihl * 4) +
3889 sizeof(struct tcphdr);
3890
3891 skb->nh.iph->check = 0;
3892 skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3893 tcp_opt_len);
3894 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3895 }
5a6f3074
MC		 3896
3897 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3898 TXD_FLAG_CPU_POST_DMA);
3899
5a6f3074
MC		 3900 skb->h.th->check = 0;
3901
5a6f3074 3902 }
84fa7933 3903 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 3904 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 3905#if TG3_VLAN_TAG_USED
3906 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3907 base_flags |= (TXD_FLAG_VLAN |
3908 (vlan_tx_tag_get(skb) << 16));
3909#endif
3910
3911 /* Queue skb data, a.k.a. the main skb fragment. */
3912 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3913
3914 tp->tx_buffers[entry].skb = skb;
3915 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3916
3917 tg3_set_txd(tp, entry, mapping, len, base_flags,
3918 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3919
3920 entry = NEXT_TX(entry);
3921
3922 /* Now loop through additional data fragments, and queue them. */
3923 if (skb_shinfo(skb)->nr_frags > 0) {
3924 unsigned int i, last;
3925
3926 last = skb_shinfo(skb)->nr_frags - 1;
3927 for (i = 0; i <= last; i++) {
3928 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3929
3930 len = frag->size;
3931 mapping = pci_map_page(tp->pdev,
3932 frag->page,
3933 frag->page_offset,
3934 len, PCI_DMA_TODEVICE);
3935
3936 tp->tx_buffers[entry].skb = NULL;
3937 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3938
3939 tg3_set_txd(tp, entry, mapping, len,
3940 base_flags, (i == last) | (mss << 1));
3941
3942 entry = NEXT_TX(entry);
3943 }
3944 }
3945
3946 /* Packets are ready, update Tx producer idx local and on card. */
3947 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3948
3949 tp->tx_prod = entry;
1b2a7205 3950 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 3951 netif_stop_queue(dev);
42952231 3952 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 3953 netif_wake_queue(tp->dev);
3954 }
3955
3956out_unlock:
3957 mmiowb();
5a6f3074
MC		 3958
3959 dev->trans_start = jiffies;
3960
3961 return NETDEV_TX_OK;
3962}
3963
52c0fd83
MC		 3964static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3965
3966/* Use GSO to workaround a rare TSO bug that may be triggered when the
3967 * TSO header is greater than 80 bytes.
3968 */
3969static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3970{
3971 struct sk_buff *segs, *nskb;
3972
3973 /* Estimate the number of fragments in the worst case */
1b2a7205 3974 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83
MC		 3975 netif_stop_queue(tp->dev);
3976 return NETDEV_TX_BUSY;
3977 }
3978
3979 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3980 if (unlikely(IS_ERR(segs)))
3981 goto tg3_tso_bug_end;
3982
3983 do {
3984 nskb = segs;
3985 segs = segs->next;
3986 nskb->next = NULL;
3987 tg3_start_xmit_dma_bug(nskb, tp->dev);
3988 } while (segs);
3989
3990tg3_tso_bug_end:
3991 dev_kfree_skb(skb);
3992
3993 return NETDEV_TX_OK;
3994}
52c0fd83 3995
5a6f3074
MC		 3996/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3997 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3998 */
3999static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4000{
4001 struct tg3 *tp = netdev_priv(dev);
4002 dma_addr_t mapping;
1da177e4
LT		 4003 u32 len, entry, base_flags, mss;
4004 int would_hit_hwbug;
1da177e4
LT		 4005
4006 len = skb_headlen(skb);
4007
00b70504
MC		 4008 /* We are running in BH disabled context with netif_tx_lock
4009 * and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 4010 * interrupt. Furthermore, IRQ processing runs lockless so we have
4011 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4012 */
1b2a7205 4013 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4014 if (!netif_queue_stopped(dev)) {
4015 netif_stop_queue(dev);
4016
4017 /* This is a hard error, log it. */
4018 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4019 "queue awake!\n", dev->name);
4020 }
1da177e4
LT		 4021 return NETDEV_TX_BUSY;
4022 }
4023
4024 entry = tp->tx_prod;
4025 base_flags = 0;
84fa7933 4026 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4027 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4
LT		 4028 mss = 0;
4029 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
7967168c 4030 (mss = skb_shinfo(skb)->gso_size) != 0) {
52c0fd83 4031 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4032
4033 if (skb_header_cloned(skb) &&
4034 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4035 dev_kfree_skb(skb);
4036 goto out_unlock;
4037 }
4038
4039 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4040 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4041
52c0fd83
MC		 4042 hdr_len = ip_tcp_len + tcp_opt_len;
4043 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4044 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4045 return (tg3_tso_bug(tp, skb));
4046
1da177e4
LT		 4047 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4048 TXD_FLAG_CPU_POST_DMA);
4049
4050 skb->nh.iph->check = 0;
52c0fd83 4051 skb->nh.iph->tot_len = htons(mss + hdr_len);
1da177e4
LT		 4052 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4053 skb->h.th->check = 0;
4054 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4055 }
4056 else {
4057 skb->h.th->check =
4058 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4059 skb->nh.iph->daddr,
4060 0, IPPROTO_TCP, 0);
4061 }
4062
4063 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4064 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4065 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4066 int tsflags;
4067
4068 tsflags = ((skb->nh.iph->ihl - 5) +
4069 (tcp_opt_len >> 2));
4070 mss |= (tsflags << 11);
4071 }
4072 } else {
4073 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4074 int tsflags;
4075
4076 tsflags = ((skb->nh.iph->ihl - 5) +
4077 (tcp_opt_len >> 2));
4078 base_flags |= tsflags << 12;
4079 }
4080 }
4081 }
1da177e4
LT		 4082#if TG3_VLAN_TAG_USED
4083 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4084 base_flags |= (TXD_FLAG_VLAN |
4085 (vlan_tx_tag_get(skb) << 16));
4086#endif
4087
4088 /* Queue skb data, a.k.a. the main skb fragment. */
4089 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4090
4091 tp->tx_buffers[entry].skb = skb;
4092 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4093
4094 would_hit_hwbug = 0;
4095
4096 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4097 would_hit_hwbug = 1;
1da177e4
LT		 4098
4099 tg3_set_txd(tp, entry, mapping, len, base_flags,
4100 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4101
4102 entry = NEXT_TX(entry);
4103
4104 /* Now loop through additional data fragments, and queue them. */
4105 if (skb_shinfo(skb)->nr_frags > 0) {
4106 unsigned int i, last;
4107
4108 last = skb_shinfo(skb)->nr_frags - 1;
4109 for (i = 0; i <= last; i++) {
4110 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4111
4112 len = frag->size;
4113 mapping = pci_map_page(tp->pdev,
4114 frag->page,
4115 frag->page_offset,
4116 len, PCI_DMA_TODEVICE);
4117
4118 tp->tx_buffers[entry].skb = NULL;
4119 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4120
c58ec932
MC		 4121 if (tg3_4g_overflow_test(mapping, len))
4122 would_hit_hwbug = 1;
1da177e4 4123
72f2afb8
MC		 4124 if (tg3_40bit_overflow_test(tp, mapping, len))
4125 would_hit_hwbug = 1;
4126
1da177e4
LT		 4127 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4128 tg3_set_txd(tp, entry, mapping, len,
4129 base_flags, (i == last)|(mss << 1));
4130 else
4131 tg3_set_txd(tp, entry, mapping, len,
4132 base_flags, (i == last));
4133
4134 entry = NEXT_TX(entry);
4135 }
4136 }
4137
4138 if (would_hit_hwbug) {
4139 u32 last_plus_one = entry;
4140 u32 start;
1da177e4 4141
c58ec932
MC		 4142 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4143 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4144
4145 /* If the workaround fails due to memory/mapping
4146 * failure, silently drop this packet.
4147 */
72f2afb8 4148 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4149 &start, base_flags, mss))
1da177e4
LT		 4150 goto out_unlock;
4151
4152 entry = start;
4153 }
4154
4155 /* Packets are ready, update Tx producer idx local and on card. */
4156 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4157
4158 tp->tx_prod = entry;
1b2a7205 4159 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4160 netif_stop_queue(dev);
42952231 4161 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4162 netif_wake_queue(tp->dev);
4163 }
1da177e4
LT		 4164
4165out_unlock:
4166 mmiowb();
1da177e4
LT		 4167
4168 dev->trans_start = jiffies;
4169
4170 return NETDEV_TX_OK;
4171}
4172
4173static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4174 int new_mtu)
4175{
4176 dev->mtu = new_mtu;
4177
ef7f5ec0 4178 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4179 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4180 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4181 ethtool_op_set_tso(dev, 0);
4182 }
4183 else
4184 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4185 } else {
a4e2b347 4186 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4187 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4188 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4189 }
1da177e4
LT		 4190}
4191
4192static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4193{
4194 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4195 int err;
1da177e4
LT		 4196
4197 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4198 return -EINVAL;
4199
4200 if (!netif_running(dev)) {
4201 /* We'll just catch it later when the
4202 * device is up'd.
4203 */
4204 tg3_set_mtu(dev, tp, new_mtu);
4205 return 0;
4206 }
4207
4208 tg3_netif_stop(tp);
f47c11ee
DM		 4209
4210 tg3_full_lock(tp, 1);
1da177e4 4211
944d980e 4212 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4213
4214 tg3_set_mtu(dev, tp, new_mtu);
4215
b9ec6c1b 4216 err = tg3_restart_hw(tp, 0);
1da177e4 4217
b9ec6c1b
MC		 4218 if (!err)
4219 tg3_netif_start(tp);
1da177e4 4220
f47c11ee 4221 tg3_full_unlock(tp);
1da177e4 4222
b9ec6c1b 4223 return err;
1da177e4
LT		 4224}
4225
4226/* Free up pending packets in all rx/tx rings.
4227 *
4228 * The chip has been shut down and the driver detached from
4229 * the networking, so no interrupts or new tx packets will
4230 * end up in the driver. tp->{tx,}lock is not held and we are not
4231 * in an interrupt context and thus may sleep.
4232 */
4233static void tg3_free_rings(struct tg3 *tp)
4234{
4235 struct ring_info *rxp;
4236 int i;
4237
4238 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4239 rxp = &tp->rx_std_buffers[i];
4240
4241 if (rxp->skb == NULL)
4242 continue;
4243 pci_unmap_single(tp->pdev,
4244 pci_unmap_addr(rxp, mapping),
7e72aad4 4245 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4246 PCI_DMA_FROMDEVICE);
4247 dev_kfree_skb_any(rxp->skb);
4248 rxp->skb = NULL;
4249 }
4250
4251 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4252 rxp = &tp->rx_jumbo_buffers[i];
4253
4254 if (rxp->skb == NULL)
4255 continue;
4256 pci_unmap_single(tp->pdev,
4257 pci_unmap_addr(rxp, mapping),
4258 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4259 PCI_DMA_FROMDEVICE);
4260 dev_kfree_skb_any(rxp->skb);
4261 rxp->skb = NULL;
4262 }
4263
4264 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4265 struct tx_ring_info *txp;
4266 struct sk_buff *skb;
4267 int j;
4268
4269 txp = &tp->tx_buffers[i];
4270 skb = txp->skb;
4271
4272 if (skb == NULL) {
4273 i++;
4274 continue;
4275 }
4276
4277 pci_unmap_single(tp->pdev,
4278 pci_unmap_addr(txp, mapping),
4279 skb_headlen(skb),
4280 PCI_DMA_TODEVICE);
4281 txp->skb = NULL;
4282
4283 i++;
4284
4285 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4286 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4287 pci_unmap_page(tp->pdev,
4288 pci_unmap_addr(txp, mapping),
4289 skb_shinfo(skb)->frags[j].size,
4290 PCI_DMA_TODEVICE);
4291 i++;
4292 }
4293
4294 dev_kfree_skb_any(skb);
4295 }
4296}
4297
4298/* Initialize tx/rx rings for packet processing.
4299 *
4300 * The chip has been shut down and the driver detached from
4301 * the networking, so no interrupts or new tx packets will
4302 * end up in the driver. tp->{tx,}lock are held and thus
4303 * we may not sleep.
4304 */
32d8c572 4305static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4306{
4307 u32 i;
4308
4309 /* Free up all the SKBs. */
4310 tg3_free_rings(tp);
4311
4312 /* Zero out all descriptors. */
4313 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4314 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4315 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4316 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4317
7e72aad4 4318 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4319 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4320 (tp->dev->mtu > ETH_DATA_LEN))
4321 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4322
1da177e4
LT		 4323 /* Initialize invariants of the rings, we only set this
4324 * stuff once. This works because the card does not
4325 * write into the rx buffer posting rings.
4326 */
4327 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4328 struct tg3_rx_buffer_desc *rxd;
4329
4330 rxd = &tp->rx_std[i];
7e72aad4 4331 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4332 << RXD_LEN_SHIFT;
4333 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4334 rxd->opaque = (RXD_OPAQUE_RING_STD |
4335 (i << RXD_OPAQUE_INDEX_SHIFT));
4336 }
4337
0f893dc6 4338 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4339 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4340 struct tg3_rx_buffer_desc *rxd;
4341
4342 rxd = &tp->rx_jumbo[i];
4343 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4344 << RXD_LEN_SHIFT;
4345 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4346 RXD_FLAG_JUMBO;
4347 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4348 (i << RXD_OPAQUE_INDEX_SHIFT));
4349 }
4350 }
4351
4352 /* Now allocate fresh SKBs for each rx ring. */
4353 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4354 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4355 printk(KERN_WARNING PFX
4356 "%s: Using a smaller RX standard ring, "
4357 "only %d out of %d buffers were allocated "
4358 "successfully.\n",
4359 tp->dev->name, i, tp->rx_pending);
4360 if (i == 0)
4361 return -ENOMEM;
4362 tp->rx_pending = i;
1da177e4 4363 break;
32d8c572 4364 }
1da177e4
LT		 4365 }
4366
0f893dc6 4367 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4368 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4369 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4370 -1, i) < 0) {
4371 printk(KERN_WARNING PFX
4372 "%s: Using a smaller RX jumbo ring, "
4373 "only %d out of %d buffers were "
4374 "allocated successfully.\n",
4375 tp->dev->name, i, tp->rx_jumbo_pending);
4376 if (i == 0) {
4377 tg3_free_rings(tp);
4378 return -ENOMEM;
4379 }
4380 tp->rx_jumbo_pending = i;
1da177e4 4381 break;
32d8c572 4382 }
1da177e4
LT		 4383 }
4384 }
32d8c572 4385 return 0;
1da177e4
LT		 4386}
4387
4388/*
4389 * Must not be invoked with interrupt sources disabled and
4390 * the hardware shutdown down.
4391 */
4392static void tg3_free_consistent(struct tg3 *tp)
4393{
b4558ea9
JJ		 4394 kfree(tp->rx_std_buffers);
4395 tp->rx_std_buffers = NULL;
1da177e4
LT		 4396 if (tp->rx_std) {
4397 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4398 tp->rx_std, tp->rx_std_mapping);
4399 tp->rx_std = NULL;
4400 }
4401 if (tp->rx_jumbo) {
4402 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4403 tp->rx_jumbo, tp->rx_jumbo_mapping);
4404 tp->rx_jumbo = NULL;
4405 }
4406 if (tp->rx_rcb) {
4407 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4408 tp->rx_rcb, tp->rx_rcb_mapping);
4409 tp->rx_rcb = NULL;
4410 }
4411 if (tp->tx_ring) {
4412 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4413 tp->tx_ring, tp->tx_desc_mapping);
4414 tp->tx_ring = NULL;
4415 }
4416 if (tp->hw_status) {
4417 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4418 tp->hw_status, tp->status_mapping);
4419 tp->hw_status = NULL;
4420 }
4421 if (tp->hw_stats) {
4422 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4423 tp->hw_stats, tp->stats_mapping);
4424 tp->hw_stats = NULL;
4425 }
4426}
4427
4428/*
4429 * Must not be invoked with interrupt sources disabled and
4430 * the hardware shutdown down. Can sleep.
4431 */
4432static int tg3_alloc_consistent(struct tg3 *tp)
4433{
bd2b3343 4434 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4435 (TG3_RX_RING_SIZE +
4436 TG3_RX_JUMBO_RING_SIZE)) +
4437 (sizeof(struct tx_ring_info) *
4438 TG3_TX_RING_SIZE),
4439 GFP_KERNEL);
4440 if (!tp->rx_std_buffers)
4441 return -ENOMEM;
4442
1da177e4
LT		 4443 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4444 tp->tx_buffers = (struct tx_ring_info *)
4445 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4446
4447 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4448 &tp->rx_std_mapping);
4449 if (!tp->rx_std)
4450 goto err_out;
4451
4452 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4453 &tp->rx_jumbo_mapping);
4454
4455 if (!tp->rx_jumbo)
4456 goto err_out;
4457
4458 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4459 &tp->rx_rcb_mapping);
4460 if (!tp->rx_rcb)
4461 goto err_out;
4462
4463 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4464 &tp->tx_desc_mapping);
4465 if (!tp->tx_ring)
4466 goto err_out;
4467
4468 tp->hw_status = pci_alloc_consistent(tp->pdev,
4469 TG3_HW_STATUS_SIZE,
4470 &tp->status_mapping);
4471 if (!tp->hw_status)
4472 goto err_out;
4473
4474 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4475 sizeof(struct tg3_hw_stats),
4476 &tp->stats_mapping);
4477 if (!tp->hw_stats)
4478 goto err_out;
4479
4480 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4481 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4482
4483 return 0;
4484
4485err_out:
4486 tg3_free_consistent(tp);
4487 return -ENOMEM;
4488}
4489
4490#define MAX_WAIT_CNT 1000
4491
4492/* To stop a block, clear the enable bit and poll till it
4493 * clears. tp->lock is held.
4494 */
b3b7d6be 4495static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4496{
4497 unsigned int i;
4498 u32 val;
4499
4500 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4501 switch (ofs) {
4502 case RCVLSC_MODE:
4503 case DMAC_MODE:
4504 case MBFREE_MODE:
4505 case BUFMGR_MODE:
4506 case MEMARB_MODE:
4507 /* We can't enable/disable these bits of the
4508 * 5705/5750, just say success.
4509 */
4510 return 0;
4511
4512 default:
4513 break;
4514 };
4515 }
4516
4517 val = tr32(ofs);
4518 val &= ~enable_bit;
4519 tw32_f(ofs, val);
4520
4521 for (i = 0; i < MAX_WAIT_CNT; i++) {
4522 udelay(100);
4523 val = tr32(ofs);
4524 if ((val & enable_bit) == 0)
4525 break;
4526 }
4527
b3b7d6be 4528 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4529 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4530 "ofs=%lx enable_bit=%x\n",
4531 ofs, enable_bit);
4532 return -ENODEV;
4533 }
4534
4535 return 0;
4536}
4537
4538/* tp->lock is held. */
b3b7d6be 4539static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4540{
4541 int i, err;
4542
4543 tg3_disable_ints(tp);
4544
4545 tp->rx_mode &= ~RX_MODE_ENABLE;
4546 tw32_f(MAC_RX_MODE, tp->rx_mode);
4547 udelay(10);
4548
b3b7d6be
DM		 4549 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4550 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4551 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4552 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4553 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4554 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4555
4556 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4557 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4558 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4559 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4560 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4561 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4562 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4563
4564 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4565 tw32_f(MAC_MODE, tp->mac_mode);
4566 udelay(40);
4567
4568 tp->tx_mode &= ~TX_MODE_ENABLE;
4569 tw32_f(MAC_TX_MODE, tp->tx_mode);
4570
4571 for (i = 0; i < MAX_WAIT_CNT; i++) {
4572 udelay(100);
4573 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4574 break;
4575 }
4576 if (i >= MAX_WAIT_CNT) {
4577 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4578 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4579 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4580 err |= -ENODEV;
1da177e4
LT		 4581 }
4582
e6de8ad1 4583 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4584 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4585 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4586
4587 tw32(FTQ_RESET, 0xffffffff);
4588 tw32(FTQ_RESET, 0x00000000);
4589
b3b7d6be
DM		 4590 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4591 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4592
4593 if (tp->hw_status)
4594 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4595 if (tp->hw_stats)
4596 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4597
1da177e4
LT		 4598 return err;
4599}
4600
4601/* tp->lock is held. */
4602static int tg3_nvram_lock(struct tg3 *tp)
4603{
4604 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4605 int i;
4606
ec41c7df
MC		 4607 if (tp->nvram_lock_cnt == 0) {
4608 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4609 for (i = 0; i < 8000; i++) {
4610 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4611 break;
4612 udelay(20);
4613 }
4614 if (i == 8000) {
4615 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4616 return -ENODEV;
4617 }
1da177e4 4618 }
ec41c7df 4619 tp->nvram_lock_cnt++;
1da177e4
LT		 4620 }
4621 return 0;
4622}
4623
4624/* tp->lock is held. */
4625static void tg3_nvram_unlock(struct tg3 *tp)
4626{
ec41c7df
MC		 4627 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4628 if (tp->nvram_lock_cnt > 0)
4629 tp->nvram_lock_cnt--;
4630 if (tp->nvram_lock_cnt == 0)
4631 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4632 }
1da177e4
LT		 4633}
4634
e6af301b
MC		 4635/* tp->lock is held. */
4636static void tg3_enable_nvram_access(struct tg3 *tp)
4637{
4638 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4639 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4640 u32 nvaccess = tr32(NVRAM_ACCESS);
4641
4642 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4643 }
4644}
4645
4646/* tp->lock is held. */
4647static void tg3_disable_nvram_access(struct tg3 *tp)
4648{
4649 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4650 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4651 u32 nvaccess = tr32(NVRAM_ACCESS);
4652
4653 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4654 }
4655}
4656
1da177e4
LT		 4657/* tp->lock is held. */
4658static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4659{
f49639e6
DM		 4660 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4661 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4662
4663 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4664 switch (kind) {
4665 case RESET_KIND_INIT:
4666 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4667 DRV_STATE_START);
4668 break;
4669
4670 case RESET_KIND_SHUTDOWN:
4671 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4672 DRV_STATE_UNLOAD);
4673 break;
4674
4675 case RESET_KIND_SUSPEND:
4676 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4677 DRV_STATE_SUSPEND);
4678 break;
4679
4680 default:
4681 break;
4682 };
4683 }
4684}
4685
4686/* tp->lock is held. */
4687static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4688{
4689 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4690 switch (kind) {
4691 case RESET_KIND_INIT:
4692 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4693 DRV_STATE_START_DONE);
4694 break;
4695
4696 case RESET_KIND_SHUTDOWN:
4697 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4698 DRV_STATE_UNLOAD_DONE);
4699 break;
4700
4701 default:
4702 break;
4703 };
4704 }
4705}
4706
4707/* tp->lock is held. */
4708static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4709{
4710 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4711 switch (kind) {
4712 case RESET_KIND_INIT:
4713 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4714 DRV_STATE_START);
4715 break;
4716
4717 case RESET_KIND_SHUTDOWN:
4718 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4719 DRV_STATE_UNLOAD);
4720 break;
4721
4722 case RESET_KIND_SUSPEND:
4723 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4724 DRV_STATE_SUSPEND);
4725 break;
4726
4727 default:
4728 break;
4729 };
4730 }
4731}
4732
7a6f4369
MC		 4733static int tg3_poll_fw(struct tg3 *tp)
4734{
4735 int i;
4736 u32 val;
4737
b5d3772c 4738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 4739 /* Wait up to 20ms for init done. */
4740 for (i = 0; i < 200; i++) {
b5d3772c
MC		 4741 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4742 return 0;
0ccead18 4743 udelay(100);
b5d3772c
MC		 4744 }
4745 return -ENODEV;
4746 }
4747
7a6f4369
MC		 4748 /* Wait for firmware initialization to complete. */
4749 for (i = 0; i < 100000; i++) {
4750 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4751 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4752 break;
4753 udelay(10);
4754 }
4755
4756 /* Chip might not be fitted with firmware. Some Sun onboard
4757 * parts are configured like that. So don't signal the timeout
4758 * of the above loop as an error, but do report the lack of
4759 * running firmware once.
4760 */
4761 if (i >= 100000 &&
4762 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4763 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4764
4765 printk(KERN_INFO PFX "%s: No firmware running.\n",
4766 tp->dev->name);
4767 }
4768
4769 return 0;
4770}
4771
1da177e4
LT		 4772static void tg3_stop_fw(struct tg3 *);
4773
4774/* tp->lock is held. */
4775static int tg3_chip_reset(struct tg3 *tp)
4776{
4777 u32 val;
1ee582d8 4778 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 4779 int err;
1da177e4 4780
f49639e6
DM		 4781 tg3_nvram_lock(tp);
4782
4783 /* No matching tg3_nvram_unlock() after this because
4784 * chip reset below will undo the nvram lock.
4785 */
4786 tp->nvram_lock_cnt = 0;
1da177e4 4787
d9ab5ad1 4788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 4789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1
MC		 4790 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4791 tw32(GRC_FASTBOOT_PC, 0);
4792
1da177e4
LT		 4793 /*
4794 * We must avoid the readl() that normally takes place.
4795 * It locks machines, causes machine checks, and other
4796 * fun things. So, temporarily disable the 5701
4797 * hardware workaround, while we do the reset.
4798 */
1ee582d8
MC		 4799 write_op = tp->write32;
4800 if (write_op == tg3_write_flush_reg32)
4801 tp->write32 = tg3_write32;
1da177e4
LT		 4802
4803 /* do the reset */
4804 val = GRC_MISC_CFG_CORECLK_RESET;
4805
4806 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4807 if (tr32(0x7e2c) == 0x60) {
4808 tw32(0x7e2c, 0x20);
4809 }
4810 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4811 tw32(GRC_MISC_CFG, (1 << 29));
4812 val |= (1 << 29);
4813 }
4814 }
4815
b5d3772c
MC		 4816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4817 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4818 tw32(GRC_VCPU_EXT_CTRL,
4819 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4820 }
4821
1da177e4
LT		 4822 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4823 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4824 tw32(GRC_MISC_CFG, val);
4825
1ee582d8
MC		 4826 /* restore 5701 hardware bug workaround write method */
4827 tp->write32 = write_op;
1da177e4
LT		 4828
4829 /* Unfortunately, we have to delay before the PCI read back.
4830 * Some 575X chips even will not respond to a PCI cfg access
4831 * when the reset command is given to the chip.
4832 *
4833 * How do these hardware designers expect things to work
4834 * properly if the PCI write is posted for a long period
4835 * of time? It is always necessary to have some method by
4836 * which a register read back can occur to push the write
4837 * out which does the reset.
4838 *
4839 * For most tg3 variants the trick below was working.
4840 * Ho hum...
4841 */
4842 udelay(120);
4843
4844 /* Flush PCI posted writes. The normal MMIO registers
4845 * are inaccessible at this time so this is the only
4846 * way to make this reliably (actually, this is no longer
4847 * the case, see above). I tried to use indirect
4848 * register read/write but this upset some 5701 variants.
4849 */
4850 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4851
4852 udelay(120);
4853
4854 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4855 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4856 int i;
4857 u32 cfg_val;
4858
4859 /* Wait for link training to complete. */
4860 for (i = 0; i < 5000; i++)
4861 udelay(100);
4862
4863 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4864 pci_write_config_dword(tp->pdev, 0xc4,
4865 cfg_val | (1 << 15));
4866 }
4867 /* Set PCIE max payload size and clear error status. */
4868 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4869 }
4870
4871 /* Re-enable indirect register accesses. */
4872 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4873 tp->misc_host_ctrl);
4874
4875 /* Set MAX PCI retry to zero. */
4876 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4877 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4878 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4879 val |= PCISTATE_RETRY_SAME_DMA;
4880 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4881
4882 pci_restore_state(tp->pdev);
4883
4884 /* Make sure PCI-X relaxed ordering bit is clear. */
4885 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4886 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4887 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4888
a4e2b347 4889 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4890 u32 val;
4891
4892 /* Chip reset on 5780 will reset MSI enable bit,
4893 * so need to restore it.
4894 */
4895 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4896 u16 ctrl;
4897
4898 pci_read_config_word(tp->pdev,
4899 tp->msi_cap + PCI_MSI_FLAGS,
4900 &ctrl);
4901 pci_write_config_word(tp->pdev,
4902 tp->msi_cap + PCI_MSI_FLAGS,
4903 ctrl | PCI_MSI_FLAGS_ENABLE);
4904 val = tr32(MSGINT_MODE);
4905 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4906 }
4907
4908 val = tr32(MEMARB_MODE);
4909 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4910
4911 } else
4912 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4913
4914 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4915 tg3_stop_fw(tp);
4916 tw32(0x5000, 0x400);
4917 }
4918
4919 tw32(GRC_MODE, tp->grc_mode);
4920
4921 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4922 u32 val = tr32(0xc4);
4923
4924 tw32(0xc4, val | (1 << 15));
4925 }
4926
4927 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4929 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4930 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4931 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4932 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4933 }
4934
4935 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4936 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4937 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4938 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4939 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4940 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4941 } else
4942 tw32_f(MAC_MODE, 0);
4943 udelay(40);
4944
7a6f4369
MC		 4945 err = tg3_poll_fw(tp);
4946 if (err)
4947 return err;
1da177e4
LT		 4948
4949 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4950 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4951 u32 val = tr32(0x7c00);
4952
4953 tw32(0x7c00, val | (1 << 25));
4954 }
4955
4956 /* Reprobe ASF enable state. */
4957 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4958 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4959 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4960 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4961 u32 nic_cfg;
4962
4963 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4964 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4965 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4966 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4967 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4968 }
4969 }
4970
4971 return 0;
4972}
4973
4974/* tp->lock is held. */
4975static void tg3_stop_fw(struct tg3 *tp)
4976{
4977 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4978 u32 val;
4979 int i;
4980
4981 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4982 val = tr32(GRC_RX_CPU_EVENT);
4983 val |= (1 << 14);
4984 tw32(GRC_RX_CPU_EVENT, val);
4985
4986 /* Wait for RX cpu to ACK the event. */
4987 for (i = 0; i < 100; i++) {
4988 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4989 break;
4990 udelay(1);
4991 }
4992 }
4993}
4994
4995/* tp->lock is held. */
944d980e 4996static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4997{
4998 int err;
4999
5000 tg3_stop_fw(tp);
5001
944d980e 5002 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5003
b3b7d6be 5004 tg3_abort_hw(tp, silent);
1da177e4
LT		 5005 err = tg3_chip_reset(tp);
5006
944d980e
MC		 5007 tg3_write_sig_legacy(tp, kind);
5008 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5009
5010 if (err)
5011 return err;
5012
5013 return 0;
5014}
5015
5016#define TG3_FW_RELEASE_MAJOR 0x0
5017#define TG3_FW_RELASE_MINOR 0x0
5018#define TG3_FW_RELEASE_FIX 0x0
5019#define TG3_FW_START_ADDR 0x08000000
5020#define TG3_FW_TEXT_ADDR 0x08000000
5021#define TG3_FW_TEXT_LEN 0x9c0
5022#define TG3_FW_RODATA_ADDR 0x080009c0
5023#define TG3_FW_RODATA_LEN 0x60
5024#define TG3_FW_DATA_ADDR 0x08000a40
5025#define TG3_FW_DATA_LEN 0x20
5026#define TG3_FW_SBSS_ADDR 0x08000a60
5027#define TG3_FW_SBSS_LEN 0xc
5028#define TG3_FW_BSS_ADDR 0x08000a70
5029#define TG3_FW_BSS_LEN 0x10
5030
50da859d 5031static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5032 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5033 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5034 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5035 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5036 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5037 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5038 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5039 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5040 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5041 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5042 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5043 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5044 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5045 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5046 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5047 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5048 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5049 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5050 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5051 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5052 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5053 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5054 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5055 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5056 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5057 0, 0, 0, 0, 0, 0,
5058 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5059 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5060 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5061 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5062 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5063 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5064 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5065 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5066 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5067 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5068 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5069 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5070 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5071 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5072 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5073 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5074 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5075 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5076 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5077 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5078 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5079 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5080 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5081 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5082 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5083 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5084 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5085 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5086 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5087 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5088 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5089 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5090 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5091 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5092 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5093 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5094 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5095 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5096 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5097 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5098 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5099 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5100 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5101 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5102 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5103 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5104 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5105 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5106 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5107 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5108 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5109 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5110 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5111 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5112 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5113 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5114 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5115 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5116 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5117 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5118 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5119 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5120 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5121 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5122 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5123};
5124
50da859d 5125static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5126 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5127 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5128 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5129 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5130 0x00000000
5131};
5132
5133#if 0 /* All zeros, don't eat up space with it. */
5134u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5135 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5136 0x00000000, 0x00000000, 0x00000000, 0x00000000
5137};
5138#endif
5139
5140#define RX_CPU_SCRATCH_BASE 0x30000
5141#define RX_CPU_SCRATCH_SIZE 0x04000
5142#define TX_CPU_SCRATCH_BASE 0x34000
5143#define TX_CPU_SCRATCH_SIZE 0x04000
5144
5145/* tp->lock is held. */
5146static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5147{
5148 int i;
5149
5d9428de
ES		 5150 BUG_ON(offset == TX_CPU_BASE &&
5151 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5152
b5d3772c
MC		 5153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5154 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5155
5156 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5157 return 0;
5158 }
1da177e4
LT		 5159 if (offset == RX_CPU_BASE) {
5160 for (i = 0; i < 10000; i++) {
5161 tw32(offset + CPU_STATE, 0xffffffff);
5162 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5163 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5164 break;
5165 }
5166
5167 tw32(offset + CPU_STATE, 0xffffffff);
5168 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5169 udelay(10);
5170 } else {
5171 for (i = 0; i < 10000; i++) {
5172 tw32(offset + CPU_STATE, 0xffffffff);
5173 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5174 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5175 break;
5176 }
5177 }
5178
5179 if (i >= 10000) {
5180 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5181 "and %s CPU\n",
5182 tp->dev->name,
5183 (offset == RX_CPU_BASE ? "RX" : "TX"));
5184 return -ENODEV;
5185 }
ec41c7df
MC		 5186
5187 /* Clear firmware's nvram arbitration. */
5188 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5189 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5190 return 0;
5191}
5192
5193struct fw_info {
5194 unsigned int text_base;
5195 unsigned int text_len;
50da859d 5196 const u32 *text_data;
1da177e4
LT		 5197 unsigned int rodata_base;
5198 unsigned int rodata_len;
50da859d 5199 const u32 *rodata_data;
1da177e4
LT		 5200 unsigned int data_base;
5201 unsigned int data_len;
50da859d 5202 const u32 *data_data;
1da177e4
LT		 5203};
5204
5205/* tp->lock is held. */
5206static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5207 int cpu_scratch_size, struct fw_info *info)
5208{
ec41c7df 5209 int err, lock_err, i;
1da177e4
LT		 5210 void (*write_op)(struct tg3 *, u32, u32);
5211
5212 if (cpu_base == TX_CPU_BASE &&
5213 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5214 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5215 "TX cpu firmware on %s which is 5705.\n",
5216 tp->dev->name);
5217 return -EINVAL;
5218 }
5219
5220 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5221 write_op = tg3_write_mem;
5222 else
5223 write_op = tg3_write_indirect_reg32;
5224
1b628151
MC		 5225 /* It is possible that bootcode is still loading at this point.
5226 * Get the nvram lock first before halting the cpu.
5227 */
ec41c7df 5228 lock_err = tg3_nvram_lock(tp);
1da177e4 5229 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5230 if (!lock_err)
5231 tg3_nvram_unlock(tp);
1da177e4
LT		 5232 if (err)
5233 goto out;
5234
5235 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5236 write_op(tp, cpu_scratch_base + i, 0);
5237 tw32(cpu_base + CPU_STATE, 0xffffffff);
5238 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5239 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5240 write_op(tp, (cpu_scratch_base +
5241 (info->text_base & 0xffff) +
5242 (i * sizeof(u32))),
5243 (info->text_data ?
5244 info->text_data[i] : 0));
5245 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5246 write_op(tp, (cpu_scratch_base +
5247 (info->rodata_base & 0xffff) +
5248 (i * sizeof(u32))),
5249 (info->rodata_data ?
5250 info->rodata_data[i] : 0));
5251 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5252 write_op(tp, (cpu_scratch_base +
5253 (info->data_base & 0xffff) +
5254 (i * sizeof(u32))),
5255 (info->data_data ?
5256 info->data_data[i] : 0));
5257
5258 err = 0;
5259
5260out:
1da177e4
LT		 5261 return err;
5262}
5263
5264/* tp->lock is held. */
5265static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5266{
5267 struct fw_info info;
5268 int err, i;
5269
5270 info.text_base = TG3_FW_TEXT_ADDR;
5271 info.text_len = TG3_FW_TEXT_LEN;
5272 info.text_data = &tg3FwText[0];
5273 info.rodata_base = TG3_FW_RODATA_ADDR;
5274 info.rodata_len = TG3_FW_RODATA_LEN;
5275 info.rodata_data = &tg3FwRodata[0];
5276 info.data_base = TG3_FW_DATA_ADDR;
5277 info.data_len = TG3_FW_DATA_LEN;
5278 info.data_data = NULL;
5279
5280 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5281 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5282 &info);
5283 if (err)
5284 return err;
5285
5286 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5287 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5288 &info);
5289 if (err)
5290 return err;
5291
5292 /* Now startup only the RX cpu. */
5293 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5294 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5295
5296 for (i = 0; i < 5; i++) {
5297 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5298 break;
5299 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5300 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5301 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5302 udelay(1000);
5303 }
5304 if (i >= 5) {
5305 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5306 "to set RX CPU PC, is %08x should be %08x\n",
5307 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5308 TG3_FW_TEXT_ADDR);
5309 return -ENODEV;
5310 }
5311 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5312 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5313
5314 return 0;
5315}
5316
1da177e4
LT		 5317
5318#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5319#define TG3_TSO_FW_RELASE_MINOR 0x6
5320#define TG3_TSO_FW_RELEASE_FIX 0x0
5321#define TG3_TSO_FW_START_ADDR 0x08000000
5322#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5323#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5324#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5325#define TG3_TSO_FW_RODATA_LEN 0x60
5326#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5327#define TG3_TSO_FW_DATA_LEN 0x30
5328#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5329#define TG3_TSO_FW_SBSS_LEN 0x2c
5330#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5331#define TG3_TSO_FW_BSS_LEN 0x894
5332
50da859d 5333static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5334 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5335 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5336 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5337 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5338 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5339 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5340 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5341 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5342 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5343 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5344 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5345 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5346 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5347 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5348 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5349 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5350 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5351 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5352 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5353 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5354 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5355 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5356 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5357 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5358 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5359 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5360 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5361 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5362 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5363 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5364 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5365 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5366 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5367 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5368 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5369 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5370 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5371 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5372 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5373 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5374 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5375 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5376 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5377 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5378 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5379 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5380 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5381 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5382 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5383 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5384 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5385 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5386 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5387 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5388 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5389 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5390 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5391 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5392 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5393 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5394 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5395 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5396 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5397 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5398 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5399 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5400 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5401 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5402 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5403 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5404 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5405 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5406 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5407 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5408 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5409 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5410 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5411 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5412 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5413 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5414 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5415 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5416 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5417 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5418 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5419 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5420 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5421 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5422 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5423 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5424 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5425 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5426 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5427 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5428 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5429 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5430 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5431 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5432 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5433 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5434 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5435 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5436 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5437 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5438 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5439 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5440 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5441 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5442 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5443 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5444 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5445 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5446 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5447 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5448 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5449 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5450 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5451 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5452 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5453 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5454 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5455 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5456 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5457 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5458 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5459 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5460 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5461 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5462 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5463 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5464 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5465 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5466 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5467 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5468 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5469 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5470 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5471 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5472 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5473 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5474 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5475 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5476 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5477 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5478 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5479 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5480 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5481 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5482 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5483 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5484 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5485 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5486 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5487 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5488 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5489 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5490 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5491 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5492 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5493 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5494 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5495 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5496 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5497 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5498 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5499 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5500 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5501 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5502 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5503 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5504 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5505 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5506 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5507 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5508 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5509 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5510 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5511 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5512 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5513 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5514 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5515 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5516 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5517 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5518 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5519 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5520 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5521 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5522 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5523 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5524 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5525 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5526 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5527 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5528 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5529 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5530 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5531 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5532 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5533 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5534 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5535 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5536 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5537 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5538 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5539 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5540 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5541 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5542 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5543 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5544 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5545 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5546 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5547 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5548 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5549 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5550 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5551 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5552 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5553 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5554 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5555 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5556 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5557 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5558 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5559 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5560 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5561 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5562 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5563 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5564 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5565 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5566 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5567 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5568 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5569 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5570 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5571 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5572 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5573 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5574 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5575 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5576 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5577 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5578 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5579 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5580 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5581 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5582 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5583 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5584 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5585 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5586 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5587 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5588 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5589 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5590 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5591 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5592 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5593 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5594 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5595 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5596 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5597 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5598 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5599 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5600 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5601 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5602 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5603 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5604 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5605 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5606 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5607 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5608 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5609 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5610 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5611 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5612 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5613 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5614 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5615 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5616 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5617 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5618};
5619
50da859d 5620static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5621 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5622 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5623 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5624 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5625 0x00000000,
5626};
5627
50da859d 5628static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5629 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5630 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5631 0x00000000,
5632};
5633
5634/* 5705 needs a special version of the TSO firmware. */
5635#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5636#define TG3_TSO5_FW_RELASE_MINOR 0x2
5637#define TG3_TSO5_FW_RELEASE_FIX 0x0
5638#define TG3_TSO5_FW_START_ADDR 0x00010000
5639#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5640#define TG3_TSO5_FW_TEXT_LEN 0xe90
5641#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5642#define TG3_TSO5_FW_RODATA_LEN 0x50
5643#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5644#define TG3_TSO5_FW_DATA_LEN 0x20
5645#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5646#define TG3_TSO5_FW_SBSS_LEN 0x28
5647#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5648#define TG3_TSO5_FW_BSS_LEN 0x88
5649
50da859d 5650static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5651 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5652 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5653 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5654 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5655 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5656 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5657 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5658 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5659 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5660 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5661 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5662 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5663 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5664 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5665 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5666 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5667 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5668 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5669 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5670 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5671 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5672 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5673 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5674 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5675 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5676 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5677 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5678 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5679 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5680 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5681 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5682 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5683 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5684 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5685 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5686 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5687 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5688 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5689 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5690 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5691 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5692 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5693 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5694 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5695 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5696 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5697 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5698 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5699 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5700 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5701 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5702 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5703 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5704 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5705 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5706 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5707 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5708 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5709 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5710 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5711 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5712 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5713 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5714 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5715 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5716 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5717 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5718 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5719 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5720 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5721 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5722 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5723 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5724 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5725 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5726 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5727 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5728 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5729 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5730 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5731 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5732 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5733 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5734 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5735 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5736 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5737 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5738 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5739 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5740 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5741 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5742 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5743 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5744 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5745 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5746 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5747 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5748 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5749 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5750 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5751 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5752 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5753 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5754 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5755 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5756 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5757 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5758 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5759 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5760 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5761 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5762 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5763 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5764 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5765 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5766 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5767 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5768 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5769 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5770 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5771 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5772 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5773 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5774 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5775 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5776 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5777 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5778 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5779 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5780 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5781 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5782 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5783 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5784 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5785 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5786 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5787 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5788 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5789 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5790 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5791 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5792 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5793 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5794 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5795 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5796 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5797 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5798 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5799 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5800 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5801 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5802 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5803 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5804 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5805 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5806 0x00000000, 0x00000000, 0x00000000,
5807};
5808
50da859d 5809static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 5810 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5811 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5812 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5813 0x00000000, 0x00000000, 0x00000000,
5814};
5815
50da859d 5816static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 5817 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5818 0x00000000, 0x00000000, 0x00000000,
5819};
5820
5821/* tp->lock is held. */
5822static int tg3_load_tso_firmware(struct tg3 *tp)
5823{
5824 struct fw_info info;
5825 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5826 int err, i;
5827
5828 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5829 return 0;
5830
5831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5832 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5833 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5834 info.text_data = &tg3Tso5FwText[0];
5835 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5836 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5837 info.rodata_data = &tg3Tso5FwRodata[0];
5838 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5839 info.data_len = TG3_TSO5_FW_DATA_LEN;
5840 info.data_data = &tg3Tso5FwData[0];
5841 cpu_base = RX_CPU_BASE;
5842 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5843 cpu_scratch_size = (info.text_len +
5844 info.rodata_len +
5845 info.data_len +
5846 TG3_TSO5_FW_SBSS_LEN +
5847 TG3_TSO5_FW_BSS_LEN);
5848 } else {
5849 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5850 info.text_len = TG3_TSO_FW_TEXT_LEN;
5851 info.text_data = &tg3TsoFwText[0];
5852 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5853 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5854 info.rodata_data = &tg3TsoFwRodata[0];
5855 info.data_base = TG3_TSO_FW_DATA_ADDR;
5856 info.data_len = TG3_TSO_FW_DATA_LEN;
5857 info.data_data = &tg3TsoFwData[0];
5858 cpu_base = TX_CPU_BASE;
5859 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5860 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5861 }
5862
5863 err = tg3_load_firmware_cpu(tp, cpu_base,
5864 cpu_scratch_base, cpu_scratch_size,
5865 &info);
5866 if (err)
5867 return err;
5868
5869 /* Now startup the cpu. */
5870 tw32(cpu_base + CPU_STATE, 0xffffffff);
5871 tw32_f(cpu_base + CPU_PC, info.text_base);
5872
5873 for (i = 0; i < 5; i++) {
5874 if (tr32(cpu_base + CPU_PC) == info.text_base)
5875 break;
5876 tw32(cpu_base + CPU_STATE, 0xffffffff);
5877 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5878 tw32_f(cpu_base + CPU_PC, info.text_base);
5879 udelay(1000);
5880 }
5881 if (i >= 5) {
5882 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5883 "to set CPU PC, is %08x should be %08x\n",
5884 tp->dev->name, tr32(cpu_base + CPU_PC),
5885 info.text_base);
5886 return -ENODEV;
5887 }
5888 tw32(cpu_base + CPU_STATE, 0xffffffff);
5889 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5890 return 0;
5891}
5892
1da177e4
LT		 5893
5894/* tp->lock is held. */
5895static void __tg3_set_mac_addr(struct tg3 *tp)
5896{
5897 u32 addr_high, addr_low;
5898 int i;
5899
5900 addr_high = ((tp->dev->dev_addr[0] << 8) |
5901 tp->dev->dev_addr[1]);
5902 addr_low = ((tp->dev->dev_addr[2] << 24) |
5903 (tp->dev->dev_addr[3] << 16) |
5904 (tp->dev->dev_addr[4] << 8) |
5905 (tp->dev->dev_addr[5] << 0));
5906 for (i = 0; i < 4; i++) {
5907 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5908 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5909 }
5910
5911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5912 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5913 for (i = 0; i < 12; i++) {
5914 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5915 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5916 }
5917 }
5918
5919 addr_high = (tp->dev->dev_addr[0] +
5920 tp->dev->dev_addr[1] +
5921 tp->dev->dev_addr[2] +
5922 tp->dev->dev_addr[3] +
5923 tp->dev->dev_addr[4] +
5924 tp->dev->dev_addr[5]) &
5925 TX_BACKOFF_SEED_MASK;
5926 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5927}
5928
5929static int tg3_set_mac_addr(struct net_device *dev, void *p)
5930{
5931 struct tg3 *tp = netdev_priv(dev);
5932 struct sockaddr *addr = p;
b9ec6c1b 5933 int err = 0;
1da177e4 5934
f9804ddb
MC		 5935 if (!is_valid_ether_addr(addr->sa_data))
5936 return -EINVAL;
5937
1da177e4
LT		 5938 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5939
e75f7c90
MC		 5940 if (!netif_running(dev))
5941 return 0;
5942
58712ef9
MC		 5943 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5944 /* Reset chip so that ASF can re-init any MAC addresses it
5945 * needs.
5946 */
5947 tg3_netif_stop(tp);
5948 tg3_full_lock(tp, 1);
5949
5950 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 5951 err = tg3_restart_hw(tp, 0);
5952 if (!err)
5953 tg3_netif_start(tp);
58712ef9
MC		 5954 tg3_full_unlock(tp);
5955 } else {
5956 spin_lock_bh(&tp->lock);
5957 __tg3_set_mac_addr(tp);
5958 spin_unlock_bh(&tp->lock);
5959 }
1da177e4 5960
b9ec6c1b 5961 return err;
1da177e4
LT		 5962}
5963
5964/* tp->lock is held. */
5965static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5966 dma_addr_t mapping, u32 maxlen_flags,
5967 u32 nic_addr)
5968{
5969 tg3_write_mem(tp,
5970 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5971 ((u64) mapping >> 32));
5972 tg3_write_mem(tp,
5973 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5974 ((u64) mapping & 0xffffffff));
5975 tg3_write_mem(tp,
5976 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5977 maxlen_flags);
5978
5979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5980 tg3_write_mem(tp,
5981 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5982 nic_addr);
5983}
5984
5985static void __tg3_set_rx_mode(struct net_device *);
d244c892 5986static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5987{
5988 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5989 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5990 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5991 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5992 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5993 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5994 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5995 }
5996 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5997 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5998 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5999 u32 val = ec->stats_block_coalesce_usecs;
6000
6001 if (!netif_carrier_ok(tp->dev))
6002 val = 0;
6003
6004 tw32(HOSTCC_STAT_COAL_TICKS, val);
6005 }
6006}
1da177e4
LT		 6007
6008/* tp->lock is held. */
8e7a22e3 6009static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6010{
6011 u32 val, rdmac_mode;
6012 int i, err, limit;
6013
6014 tg3_disable_ints(tp);
6015
6016 tg3_stop_fw(tp);
6017
6018 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6019
6020 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6021 tg3_abort_hw(tp, 1);
1da177e4
LT		 6022 }
6023
36da4d86 6024 if (reset_phy)
d4d2c558
MC		 6025 tg3_phy_reset(tp);
6026
1da177e4
LT		 6027 err = tg3_chip_reset(tp);
6028 if (err)
6029 return err;
6030
6031 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6032
6033 /* This works around an issue with Athlon chipsets on
6034 * B3 tigon3 silicon. This bit has no effect on any
6035 * other revision. But do not set this on PCI Express
6036 * chips.
6037 */
6038 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6039 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6040 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6041
6042 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6043 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6044 val = tr32(TG3PCI_PCISTATE);
6045 val |= PCISTATE_RETRY_SAME_DMA;
6046 tw32(TG3PCI_PCISTATE, val);
6047 }
6048
6049 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6050 /* Enable some hw fixes. */
6051 val = tr32(TG3PCI_MSI_DATA);
6052 val |= (1 << 26) | (1 << 28) | (1 << 29);
6053 tw32(TG3PCI_MSI_DATA, val);
6054 }
6055
6056 /* Descriptor ring init may make accesses to the
6057 * NIC SRAM area to setup the TX descriptors, so we
6058 * can only do this after the hardware has been
6059 * successfully reset.
6060 */
32d8c572
MC		 6061 err = tg3_init_rings(tp);
6062 if (err)
6063 return err;
1da177e4
LT		 6064
6065 /* This value is determined during the probe time DMA
6066 * engine test, tg3_test_dma.
6067 */
6068 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6069
6070 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6071 GRC_MODE_4X_NIC_SEND_RINGS |
6072 GRC_MODE_NO_TX_PHDR_CSUM |
6073 GRC_MODE_NO_RX_PHDR_CSUM);
6074 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6075
6076 /* Pseudo-header checksum is done by hardware logic and not
6077 * the offload processers, so make the chip do the pseudo-
6078 * header checksums on receive. For transmit it is more
6079 * convenient to do the pseudo-header checksum in software
6080 * as Linux does that on transmit for us in all cases.
6081 */
6082 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6083
6084 tw32(GRC_MODE,
6085 tp->grc_mode |
6086 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6087
6088 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6089 val = tr32(GRC_MISC_CFG);
6090 val &= ~0xff;
6091 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6092 tw32(GRC_MISC_CFG, val);
6093
6094 /* Initialize MBUF/DESC pool. */
cbf46853 6095 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6096 /* Do nothing. */
6097 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6098 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6100 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6101 else
6102 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6103 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6104 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6105 }
1da177e4
LT		 6106 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6107 int fw_len;
6108
6109 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6110 TG3_TSO5_FW_RODATA_LEN +
6111 TG3_TSO5_FW_DATA_LEN +
6112 TG3_TSO5_FW_SBSS_LEN +
6113 TG3_TSO5_FW_BSS_LEN);
6114 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6115 tw32(BUFMGR_MB_POOL_ADDR,
6116 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6117 tw32(BUFMGR_MB_POOL_SIZE,
6118 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6119 }
1da177e4 6120
0f893dc6 6121 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6122 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6123 tp->bufmgr_config.mbuf_read_dma_low_water);
6124 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6125 tp->bufmgr_config.mbuf_mac_rx_low_water);
6126 tw32(BUFMGR_MB_HIGH_WATER,
6127 tp->bufmgr_config.mbuf_high_water);
6128 } else {
6129 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6130 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6131 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6132 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6133 tw32(BUFMGR_MB_HIGH_WATER,
6134 tp->bufmgr_config.mbuf_high_water_jumbo);
6135 }
6136 tw32(BUFMGR_DMA_LOW_WATER,
6137 tp->bufmgr_config.dma_low_water);
6138 tw32(BUFMGR_DMA_HIGH_WATER,
6139 tp->bufmgr_config.dma_high_water);
6140
6141 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6142 for (i = 0; i < 2000; i++) {
6143 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6144 break;
6145 udelay(10);
6146 }
6147 if (i >= 2000) {
6148 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6149 tp->dev->name);
6150 return -ENODEV;
6151 }
6152
6153 /* Setup replenish threshold. */
f92905de
MC		 6154 val = tp->rx_pending / 8;
6155 if (val == 0)
6156 val = 1;
6157 else if (val > tp->rx_std_max_post)
6158 val = tp->rx_std_max_post;
b5d3772c
MC		 6159 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6160 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6161 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6162
6163 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6164 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6165 }
f92905de
MC		 6166
6167 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6168
6169 /* Initialize TG3_BDINFO's at:
6170 * RCVDBDI_STD_BD: standard eth size rx ring
6171 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6172 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6173 *
6174 * like so:
6175 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6176 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6177 * ring attribute flags
6178 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6179 *
6180 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6181 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6182 *
6183 * The size of each ring is fixed in the firmware, but the location is
6184 * configurable.
6185 */
6186 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6187 ((u64) tp->rx_std_mapping >> 32));
6188 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6189 ((u64) tp->rx_std_mapping & 0xffffffff));
6190 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6191 NIC_SRAM_RX_BUFFER_DESC);
6192
6193 /* Don't even try to program the JUMBO/MINI buffer descriptor
6194 * configs on 5705.
6195 */
6196 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6197 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6198 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6199 } else {
6200 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6201 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6202
6203 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6204 BDINFO_FLAGS_DISABLED);
6205
6206 /* Setup replenish threshold. */
6207 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6208
0f893dc6 6209 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6210 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6211 ((u64) tp->rx_jumbo_mapping >> 32));
6212 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6213 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6214 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6215 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6216 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6217 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6218 } else {
6219 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6220 BDINFO_FLAGS_DISABLED);
6221 }
6222
6223 }
6224
6225 /* There is only one send ring on 5705/5750, no need to explicitly
6226 * disable the others.
6227 */
6228 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6229 /* Clear out send RCB ring in SRAM. */
6230 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6231 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6232 BDINFO_FLAGS_DISABLED);
6233 }
6234
6235 tp->tx_prod = 0;
6236 tp->tx_cons = 0;
6237 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6238 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6239
6240 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6241 tp->tx_desc_mapping,
6242 (TG3_TX_RING_SIZE <<
6243 BDINFO_FLAGS_MAXLEN_SHIFT),
6244 NIC_SRAM_TX_BUFFER_DESC);
6245
6246 /* There is only one receive return ring on 5705/5750, no need
6247 * to explicitly disable the others.
6248 */
6249 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6250 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6251 i += TG3_BDINFO_SIZE) {
6252 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6253 BDINFO_FLAGS_DISABLED);
6254 }
6255 }
6256
6257 tp->rx_rcb_ptr = 0;
6258 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6259
6260 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6261 tp->rx_rcb_mapping,
6262 (TG3_RX_RCB_RING_SIZE(tp) <<
6263 BDINFO_FLAGS_MAXLEN_SHIFT),
6264 0);
6265
6266 tp->rx_std_ptr = tp->rx_pending;
6267 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6268 tp->rx_std_ptr);
6269
0f893dc6 6270 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6271 tp->rx_jumbo_pending : 0;
6272 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6273 tp->rx_jumbo_ptr);
6274
6275 /* Initialize MAC address and backoff seed. */
6276 __tg3_set_mac_addr(tp);
6277
6278 /* MTU + ethernet header + FCS + optional VLAN tag */
6279 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6280
6281 /* The slot time is changed by tg3_setup_phy if we
6282 * run at gigabit with half duplex.
6283 */
6284 tw32(MAC_TX_LENGTHS,
6285 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6286 (6 << TX_LENGTHS_IPG_SHIFT) |
6287 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6288
6289 /* Receive rules. */
6290 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6291 tw32(RCVLPC_CONFIG, 0x0181);
6292
6293 /* Calculate RDMAC_MODE setting early, we need it to determine
6294 * the RCVLPC_STATE_ENABLE mask.
6295 */
6296 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6297 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6298 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6299 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6300 RDMAC_MODE_LNGREAD_ENAB);
6301 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6302 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 6303
6304 /* If statement applies to 5705 and 5750 PCI devices only */
6305 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6306 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6307 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 6308 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6309 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6310 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6311 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6312 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6313 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6314 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6315 }
6316 }
6317
85e94ced
MC		 6318 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6319 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6320
1da177e4
LT		 6321 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6322 rdmac_mode |= (1 << 27);
1da177e4
LT		 6323
6324 /* Receive/send statistics. */
1661394e
MC		 6325 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6326 val = tr32(RCVLPC_STATS_ENABLE);
6327 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6328 tw32(RCVLPC_STATS_ENABLE, val);
6329 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6330 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6331 val = tr32(RCVLPC_STATS_ENABLE);
6332 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6333 tw32(RCVLPC_STATS_ENABLE, val);
6334 } else {
6335 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6336 }
6337 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6338 tw32(SNDDATAI_STATSENAB, 0xffffff);
6339 tw32(SNDDATAI_STATSCTRL,
6340 (SNDDATAI_SCTRL_ENABLE |
6341 SNDDATAI_SCTRL_FASTUPD));
6342
6343 /* Setup host coalescing engine. */
6344 tw32(HOSTCC_MODE, 0);
6345 for (i = 0; i < 2000; i++) {
6346 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6347 break;
6348 udelay(10);
6349 }
6350
d244c892 6351 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6352
6353 /* set status block DMA address */
6354 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6355 ((u64) tp->status_mapping >> 32));
6356 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6357 ((u64) tp->status_mapping & 0xffffffff));
6358
6359 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6360 /* Status/statistics block address. See tg3_timer,
6361 * the tg3_periodic_fetch_stats call there, and
6362 * tg3_get_stats to see how this works for 5705/5750 chips.
6363 */
1da177e4
LT		 6364 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6365 ((u64) tp->stats_mapping >> 32));
6366 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6367 ((u64) tp->stats_mapping & 0xffffffff));
6368 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6369 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6370 }
6371
6372 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6373
6374 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6375 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6376 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6377 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6378
6379 /* Clear statistics/status block in chip, and status block in ram. */
6380 for (i = NIC_SRAM_STATS_BLK;
6381 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6382 i += sizeof(u32)) {
6383 tg3_write_mem(tp, i, 0);
6384 udelay(40);
6385 }
6386 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6387
c94e3941
MC		 6388 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6389 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6390 /* reset to prevent losing 1st rx packet intermittently */
6391 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6392 udelay(10);
6393 }
6394
1da177e4
LT		 6395 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6396 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6397 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6398 udelay(40);
6399
314fba34 6400 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6401 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6402 * register to preserve the GPIO settings for LOMs. The GPIOs,
6403 * whether used as inputs or outputs, are set by boot code after
6404 * reset.
6405 */
9d26e213 6406 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6407 u32 gpio_mask;
6408
9d26e213
MC		 6409 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6410 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6411 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6412
6413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6414 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6415 GRC_LCLCTRL_GPIO_OUTPUT3;
6416
af36e6b6
MC		 6417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6418 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6419
314fba34
MC		 6420 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6421
6422 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6423 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6424 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6425 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6426 }
1da177e4
LT		 6427 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6428 udelay(100);
6429
09ee929c 6430 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6431 tp->last_tag = 0;
1da177e4
LT		 6432
6433 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6434 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6435 udelay(40);
6436 }
6437
6438 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6439 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6440 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6441 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6442 WDMAC_MODE_LNGREAD_ENAB);
6443
85e94ced
MC		 6444 /* If statement applies to 5705 and 5750 PCI devices only */
6445 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6446 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6448 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6449 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6450 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6451 /* nothing */
6452 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6453 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6454 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6455 val |= WDMAC_MODE_RX_ACCEL;
6456 }
6457 }
6458
d9ab5ad1 6459 /* Enable host coalescing bug fix */
af36e6b6
MC		 6460 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6461 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
d9ab5ad1
MC		 6462 val |= (1 << 29);
6463
1da177e4
LT		 6464 tw32_f(WDMAC_MODE, val);
6465 udelay(40);
6466
6467 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6468 val = tr32(TG3PCI_X_CAPS);
6469 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6470 val &= ~PCIX_CAPS_BURST_MASK;
6471 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6472 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6473 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6474 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6475 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6476 val |= (tp->split_mode_max_reqs <<
6477 PCIX_CAPS_SPLIT_SHIFT);
6478 }
6479 tw32(TG3PCI_X_CAPS, val);
6480 }
6481
6482 tw32_f(RDMAC_MODE, rdmac_mode);
6483 udelay(40);
6484
6485 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6486 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6487 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6488 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6489 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6490 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6491 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6492 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6493 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6494 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6495 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6496 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6497
6498 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6499 err = tg3_load_5701_a0_firmware_fix(tp);
6500 if (err)
6501 return err;
6502 }
6503
1da177e4
LT		 6504 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6505 err = tg3_load_tso_firmware(tp);
6506 if (err)
6507 return err;
6508 }
1da177e4
LT		 6509
6510 tp->tx_mode = TX_MODE_ENABLE;
6511 tw32_f(MAC_TX_MODE, tp->tx_mode);
6512 udelay(100);
6513
6514 tp->rx_mode = RX_MODE_ENABLE;
af36e6b6
MC		 6515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6516 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6517
1da177e4
LT		 6518 tw32_f(MAC_RX_MODE, tp->rx_mode);
6519 udelay(10);
6520
6521 if (tp->link_config.phy_is_low_power) {
6522 tp->link_config.phy_is_low_power = 0;
6523 tp->link_config.speed = tp->link_config.orig_speed;
6524 tp->link_config.duplex = tp->link_config.orig_duplex;
6525 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6526 }
6527
6528 tp->mi_mode = MAC_MI_MODE_BASE;
6529 tw32_f(MAC_MI_MODE, tp->mi_mode);
6530 udelay(80);
6531
6532 tw32(MAC_LED_CTRL, tp->led_ctrl);
6533
6534 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6535 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6536 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6537 udelay(10);
6538 }
6539 tw32_f(MAC_RX_MODE, tp->rx_mode);
6540 udelay(10);
6541
6542 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6543 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6544 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6545 /* Set drive transmission level to 1.2V */
6546 /* only if the signal pre-emphasis bit is not set */
6547 val = tr32(MAC_SERDES_CFG);
6548 val &= 0xfffff000;
6549 val |= 0x880;
6550 tw32(MAC_SERDES_CFG, val);
6551 }
6552 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6553 tw32(MAC_SERDES_CFG, 0x616000);
6554 }
6555
6556 /* Prevent chip from dropping frames when flow control
6557 * is enabled.
6558 */
6559 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6560
6561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6562 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6563 /* Use hardware link auto-negotiation */
6564 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6565 }
6566
d4d2c558
MC		 6567 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6568 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6569 u32 tmp;
6570
6571 tmp = tr32(SERDES_RX_CTRL);
6572 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6573 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6574 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6575 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6576 }
6577
36da4d86 6578 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6579 if (err)
6580 return err;
6581
715116a1
MC		 6582 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6583 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6584 u32 tmp;
6585
6586 /* Clear CRC stats. */
6587 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6588 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6589 tg3_readphy(tp, 0x14, &tmp);
6590 }
6591 }
6592
6593 __tg3_set_rx_mode(tp->dev);
6594
6595 /* Initialize receive rules. */
6596 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6597 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6598 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6599 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6600
4cf78e4f 6601 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6602 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6603 limit = 8;
6604 else
6605 limit = 16;
6606 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6607 limit -= 4;
6608 switch (limit) {
6609 case 16:
6610 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6611 case 15:
6612 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6613 case 14:
6614 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6615 case 13:
6616 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6617 case 12:
6618 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6619 case 11:
6620 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6621 case 10:
6622 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6623 case 9:
6624 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6625 case 8:
6626 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6627 case 7:
6628 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6629 case 6:
6630 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6631 case 5:
6632 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6633 case 4:
6634 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6635 case 3:
6636 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6637 case 2:
6638 case 1:
6639
6640 default:
6641 break;
6642 };
6643
6644 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6645
1da177e4
LT		 6646 return 0;
6647}
6648
6649/* Called at device open time to get the chip ready for
6650 * packet processing. Invoked with tp->lock held.
6651 */
8e7a22e3 6652static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6653{
6654 int err;
6655
6656 /* Force the chip into D0. */
bc1c7567 6657 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 6658 if (err)
6659 goto out;
6660
6661 tg3_switch_clocks(tp);
6662
6663 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6664
8e7a22e3 6665 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 6666
6667out:
6668 return err;
6669}
6670
6671#define TG3_STAT_ADD32(PSTAT, REG) \
6672do { u32 __val = tr32(REG); \
6673 (PSTAT)->low += __val; \
6674 if ((PSTAT)->low < __val) \
6675 (PSTAT)->high += 1; \
6676} while (0)
6677
6678static void tg3_periodic_fetch_stats(struct tg3 *tp)
6679{
6680 struct tg3_hw_stats *sp = tp->hw_stats;
6681
6682 if (!netif_carrier_ok(tp->dev))
6683 return;
6684
6685 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6686 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6687 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6688 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6689 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6690 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6691 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6692 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6693 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6694 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6695 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6696 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6697 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6698
6699 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6700 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6701 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6702 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6703 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6704 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6705 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6706 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6707 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6708 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6709 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6710 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6711 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6712 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 6713
6714 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6715 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6716 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 6717}
6718
6719static void tg3_timer(unsigned long __opaque)
6720{
6721 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6722
f475f163
MC		 6723 if (tp->irq_sync)
6724 goto restart_timer;
6725
f47c11ee 6726 spin_lock(&tp->lock);
1da177e4 6727
fac9b83e
DM		 6728 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6729 /* All of this garbage is because when using non-tagged
6730 * IRQ status the mailbox/status_block protocol the chip
6731 * uses with the cpu is race prone.
6732 */
6733 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6734 tw32(GRC_LOCAL_CTRL,
6735 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6736 } else {
6737 tw32(HOSTCC_MODE, tp->coalesce_mode |
6738 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6739 }
1da177e4 6740
fac9b83e
DM		 6741 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6742 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6743 spin_unlock(&tp->lock);
fac9b83e
DM		 6744 schedule_work(&tp->reset_task);
6745 return;
6746 }
1da177e4
LT		 6747 }
6748
1da177e4
LT		 6749 /* This part only runs once per second. */
6750 if (!--tp->timer_counter) {
fac9b83e
DM		 6751 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6752 tg3_periodic_fetch_stats(tp);
6753
1da177e4
LT		 6754 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6755 u32 mac_stat;
6756 int phy_event;
6757
6758 mac_stat = tr32(MAC_STATUS);
6759
6760 phy_event = 0;
6761 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6762 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6763 phy_event = 1;
6764 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6765 phy_event = 1;
6766
6767 if (phy_event)
6768 tg3_setup_phy(tp, 0);
6769 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6770 u32 mac_stat = tr32(MAC_STATUS);
6771 int need_setup = 0;
6772
6773 if (netif_carrier_ok(tp->dev) &&
6774 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6775 need_setup = 1;
6776 }
6777 if (! netif_carrier_ok(tp->dev) &&
6778 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6779 MAC_STATUS_SIGNAL_DET))) {
6780 need_setup = 1;
6781 }
6782 if (need_setup) {
3d3ebe74
MC		 6783 if (!tp->serdes_counter) {
6784 tw32_f(MAC_MODE,
6785 (tp->mac_mode &
6786 ~MAC_MODE_PORT_MODE_MASK));
6787 udelay(40);
6788 tw32_f(MAC_MODE, tp->mac_mode);
6789 udelay(40);
6790 }
1da177e4
LT		 6791 tg3_setup_phy(tp, 0);
6792 }
747e8f8b
MC		 6793 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6794 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6795
6796 tp->timer_counter = tp->timer_multiplier;
6797 }
6798
130b8e4d
MC		 6799 /* Heartbeat is only sent once every 2 seconds.
6800 *
6801 * The heartbeat is to tell the ASF firmware that the host
6802 * driver is still alive. In the event that the OS crashes,
6803 * ASF needs to reset the hardware to free up the FIFO space
6804 * that may be filled with rx packets destined for the host.
6805 * If the FIFO is full, ASF will no longer function properly.
6806 *
6807 * Unintended resets have been reported on real time kernels
6808 * where the timer doesn't run on time. Netpoll will also have
6809 * same problem.
6810 *
6811 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6812 * to check the ring condition when the heartbeat is expiring
6813 * before doing the reset. This will prevent most unintended
6814 * resets.
6815 */
1da177e4
LT		 6816 if (!--tp->asf_counter) {
6817 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6818 u32 val;
6819
bbadf503 6820 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 6821 FWCMD_NICDRV_ALIVE3);
bbadf503 6822 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 6823 /* 5 seconds timeout */
bbadf503 6824 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6825 val = tr32(GRC_RX_CPU_EVENT);
6826 val |= (1 << 14);
6827 tw32(GRC_RX_CPU_EVENT, val);
6828 }
6829 tp->asf_counter = tp->asf_multiplier;
6830 }
6831
f47c11ee 6832 spin_unlock(&tp->lock);
1da177e4 6833
f475f163 6834restart_timer:
1da177e4
LT		 6835 tp->timer.expires = jiffies + tp->timer_offset;
6836 add_timer(&tp->timer);
6837}
6838
81789ef5 6839static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 6840{
7d12e780 6841 irq_handler_t fn;
fcfa0a32
MC		 6842 unsigned long flags;
6843 struct net_device *dev = tp->dev;
6844
6845 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6846 fn = tg3_msi;
6847 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6848 fn = tg3_msi_1shot;
1fb9df5d 6849 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6850 } else {
6851 fn = tg3_interrupt;
6852 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6853 fn = tg3_interrupt_tagged;
1fb9df5d 6854 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6855 }
6856 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6857}
6858
7938109f
MC		 6859static int tg3_test_interrupt(struct tg3 *tp)
6860{
6861 struct net_device *dev = tp->dev;
b16250e3 6862 int err, i, intr_ok = 0;
7938109f 6863
d4bc3927
MC		 6864 if (!netif_running(dev))
6865 return -ENODEV;
6866
7938109f
MC		 6867 tg3_disable_ints(tp);
6868
6869 free_irq(tp->pdev->irq, dev);
6870
6871 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 6872 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6873 if (err)
6874 return err;
6875
38f3843e 6876 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6877 tg3_enable_ints(tp);
6878
6879 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6880 HOSTCC_MODE_NOW);
6881
6882 for (i = 0; i < 5; i++) {
b16250e3
MC		 6883 u32 int_mbox, misc_host_ctrl;
6884
09ee929c
MC		 6885 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6886 TG3_64BIT_REG_LOW);
b16250e3
MC		 6887 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6888
6889 if ((int_mbox != 0) ||
6890 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6891 intr_ok = 1;
7938109f 6892 break;
b16250e3
MC		 6893 }
6894
7938109f
MC		 6895 msleep(10);
6896 }
6897
6898 tg3_disable_ints(tp);
6899
6900 free_irq(tp->pdev->irq, dev);
6aa20a22 6901
fcfa0a32 6902 err = tg3_request_irq(tp);
7938109f
MC		 6903
6904 if (err)
6905 return err;
6906
b16250e3 6907 if (intr_ok)
7938109f
MC		 6908 return 0;
6909
6910 return -EIO;
6911}
6912
6913/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6914 * successfully restored
6915 */
6916static int tg3_test_msi(struct tg3 *tp)
6917{
6918 struct net_device *dev = tp->dev;
6919 int err;
6920 u16 pci_cmd;
6921
6922 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6923 return 0;
6924
6925 /* Turn off SERR reporting in case MSI terminates with Master
6926 * Abort.
6927 */
6928 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6929 pci_write_config_word(tp->pdev, PCI_COMMAND,
6930 pci_cmd & ~PCI_COMMAND_SERR);
6931
6932 err = tg3_test_interrupt(tp);
6933
6934 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6935
6936 if (!err)
6937 return 0;
6938
6939 /* other failures */
6940 if (err != -EIO)
6941 return err;
6942
6943 /* MSI test failed, go back to INTx mode */
6944 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6945 "switching to INTx mode. Please report this failure to "
6946 "the PCI maintainer and include system chipset information.\n",
6947 tp->dev->name);
6948
6949 free_irq(tp->pdev->irq, dev);
6950 pci_disable_msi(tp->pdev);
6951
6952 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6953
fcfa0a32 6954 err = tg3_request_irq(tp);
7938109f
MC		 6955 if (err)
6956 return err;
6957
6958 /* Need to reset the chip because the MSI cycle may have terminated
6959 * with Master Abort.
6960 */
f47c11ee 6961 tg3_full_lock(tp, 1);
7938109f 6962
944d980e 6963 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 6964 err = tg3_init_hw(tp, 1);
7938109f 6965
f47c11ee 6966 tg3_full_unlock(tp);
7938109f
MC		 6967
6968 if (err)
6969 free_irq(tp->pdev->irq, dev);
6970
6971 return err;
6972}
6973
1da177e4
LT		 6974static int tg3_open(struct net_device *dev)
6975{
6976 struct tg3 *tp = netdev_priv(dev);
6977 int err;
6978
c49a1561
MC		 6979 netif_carrier_off(tp->dev);
6980
f47c11ee 6981 tg3_full_lock(tp, 0);
1da177e4 6982
bc1c7567 6983 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 6984 if (err) {
6985 tg3_full_unlock(tp);
bc1c7567 6986 return err;
12862086 6987 }
bc1c7567 6988
1da177e4
LT		 6989 tg3_disable_ints(tp);
6990 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6991
f47c11ee 6992 tg3_full_unlock(tp);
1da177e4
LT		 6993
6994 /* The placement of this call is tied
6995 * to the setup and use of Host TX descriptors.
6996 */
6997 err = tg3_alloc_consistent(tp);
6998 if (err)
6999 return err;
7000
88b06bc2
MC		 7001 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7002 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
d4d2c558
MC		 7003 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7004 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7005 (tp->pdev_peer == tp->pdev))) {
fac9b83e
DM		 7006 /* All MSI supporting chips should support tagged
7007 * status. Assert that this is the case.
7008 */
7009 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7010 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7011 "Not using MSI.\n", tp->dev->name);
7012 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7013 u32 msi_mode;
7014
7015 msi_mode = tr32(MSGINT_MODE);
7016 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7017 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7018 }
7019 }
fcfa0a32 7020 err = tg3_request_irq(tp);
1da177e4
LT		 7021
7022 if (err) {
88b06bc2
MC		 7023 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7024 pci_disable_msi(tp->pdev);
7025 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7026 }
1da177e4
LT		 7027 tg3_free_consistent(tp);
7028 return err;
7029 }
7030
f47c11ee 7031 tg3_full_lock(tp, 0);
1da177e4 7032
8e7a22e3 7033 err = tg3_init_hw(tp, 1);
1da177e4 7034 if (err) {
944d980e 7035 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7036 tg3_free_rings(tp);
7037 } else {
fac9b83e
DM		 7038 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7039 tp->timer_offset = HZ;
7040 else
7041 tp->timer_offset = HZ / 10;
7042
7043 BUG_ON(tp->timer_offset > HZ);
7044 tp->timer_counter = tp->timer_multiplier =
7045 (HZ / tp->timer_offset);
7046 tp->asf_counter = tp->asf_multiplier =
28fbef78 7047 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7048
7049 init_timer(&tp->timer);
7050 tp->timer.expires = jiffies + tp->timer_offset;
7051 tp->timer.data = (unsigned long) tp;
7052 tp->timer.function = tg3_timer;
1da177e4
LT		 7053 }
7054
f47c11ee 7055 tg3_full_unlock(tp);
1da177e4
LT		 7056
7057 if (err) {
88b06bc2
MC		 7058 free_irq(tp->pdev->irq, dev);
7059 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7060 pci_disable_msi(tp->pdev);
7061 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7062 }
1da177e4
LT		 7063 tg3_free_consistent(tp);
7064 return err;
7065 }
7066
7938109f
MC		 7067 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7068 err = tg3_test_msi(tp);
fac9b83e 7069
7938109f 7070 if (err) {
f47c11ee 7071 tg3_full_lock(tp, 0);
7938109f
MC		 7072
7073 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7074 pci_disable_msi(tp->pdev);
7075 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7076 }
944d980e 7077 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7078 tg3_free_rings(tp);
7079 tg3_free_consistent(tp);
7080
f47c11ee 7081 tg3_full_unlock(tp);
7938109f
MC		 7082
7083 return err;
7084 }
fcfa0a32
MC		 7085
7086 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7087 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7088 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7089
b5d3772c
MC		 7090 tw32(PCIE_TRANSACTION_CFG,
7091 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7092 }
7093 }
7938109f
MC		 7094 }
7095
f47c11ee 7096 tg3_full_lock(tp, 0);
1da177e4 7097
7938109f
MC		 7098 add_timer(&tp->timer);
7099 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7100 tg3_enable_ints(tp);
7101
f47c11ee 7102 tg3_full_unlock(tp);
1da177e4
LT		 7103
7104 netif_start_queue(dev);
7105
7106 return 0;
7107}
7108
7109#if 0
7110/*static*/ void tg3_dump_state(struct tg3 *tp)
7111{
7112 u32 val32, val32_2, val32_3, val32_4, val32_5;
7113 u16 val16;
7114 int i;
7115
7116 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7117 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7118 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7119 val16, val32);
7120
7121 /* MAC block */
7122 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7123 tr32(MAC_MODE), tr32(MAC_STATUS));
7124 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7125 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7126 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7127 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7128 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7129 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7130
7131 /* Send data initiator control block */
7132 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7133 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7134 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7135 tr32(SNDDATAI_STATSCTRL));
7136
7137 /* Send data completion control block */
7138 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7139
7140 /* Send BD ring selector block */
7141 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7142 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7143
7144 /* Send BD initiator control block */
7145 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7146 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7147
7148 /* Send BD completion control block */
7149 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7150
7151 /* Receive list placement control block */
7152 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7153 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7154 printk(" RCVLPC_STATSCTRL[%08x]\n",
7155 tr32(RCVLPC_STATSCTRL));
7156
7157 /* Receive data and receive BD initiator control block */
7158 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7159 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7160
7161 /* Receive data completion control block */
7162 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7163 tr32(RCVDCC_MODE));
7164
7165 /* Receive BD initiator control block */
7166 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7167 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7168
7169 /* Receive BD completion control block */
7170 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7171 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7172
7173 /* Receive list selector control block */
7174 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7175 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7176
7177 /* Mbuf cluster free block */
7178 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7179 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7180
7181 /* Host coalescing control block */
7182 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7183 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7184 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7185 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7186 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7187 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7188 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7189 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7190 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7191 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7192 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7193 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7194
7195 /* Memory arbiter control block */
7196 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7197 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7198
7199 /* Buffer manager control block */
7200 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7201 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7202 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7203 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7204 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7205 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7206 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7207 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7208
7209 /* Read DMA control block */
7210 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7211 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7212
7213 /* Write DMA control block */
7214 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7215 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7216
7217 /* DMA completion block */
7218 printk("DEBUG: DMAC_MODE[%08x]\n",
7219 tr32(DMAC_MODE));
7220
7221 /* GRC block */
7222 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7223 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7224 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7225 tr32(GRC_LOCAL_CTRL));
7226
7227 /* TG3_BDINFOs */
7228 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7229 tr32(RCVDBDI_JUMBO_BD + 0x0),
7230 tr32(RCVDBDI_JUMBO_BD + 0x4),
7231 tr32(RCVDBDI_JUMBO_BD + 0x8),
7232 tr32(RCVDBDI_JUMBO_BD + 0xc));
7233 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7234 tr32(RCVDBDI_STD_BD + 0x0),
7235 tr32(RCVDBDI_STD_BD + 0x4),
7236 tr32(RCVDBDI_STD_BD + 0x8),
7237 tr32(RCVDBDI_STD_BD + 0xc));
7238 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7239 tr32(RCVDBDI_MINI_BD + 0x0),
7240 tr32(RCVDBDI_MINI_BD + 0x4),
7241 tr32(RCVDBDI_MINI_BD + 0x8),
7242 tr32(RCVDBDI_MINI_BD + 0xc));
7243
7244 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7245 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7246 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7247 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7248 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7249 val32, val32_2, val32_3, val32_4);
7250
7251 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7252 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7253 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7254 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7255 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7256 val32, val32_2, val32_3, val32_4);
7257
7258 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7259 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7260 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7261 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7262 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7263 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7264 val32, val32_2, val32_3, val32_4, val32_5);
7265
7266 /* SW status block */
7267 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7268 tp->hw_status->status,
7269 tp->hw_status->status_tag,
7270 tp->hw_status->rx_jumbo_consumer,
7271 tp->hw_status->rx_consumer,
7272 tp->hw_status->rx_mini_consumer,
7273 tp->hw_status->idx[0].rx_producer,
7274 tp->hw_status->idx[0].tx_consumer);
7275
7276 /* SW statistics block */
7277 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7278 ((u32 *)tp->hw_stats)[0],
7279 ((u32 *)tp->hw_stats)[1],
7280 ((u32 *)tp->hw_stats)[2],
7281 ((u32 *)tp->hw_stats)[3]);
7282
7283 /* Mailboxes */
7284 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7285 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7286 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7287 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7288 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7289
7290 /* NIC side send descriptors. */
7291 for (i = 0; i < 6; i++) {
7292 unsigned long txd;
7293
7294 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7295 + (i * sizeof(struct tg3_tx_buffer_desc));
7296 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7297 i,
7298 readl(txd + 0x0), readl(txd + 0x4),
7299 readl(txd + 0x8), readl(txd + 0xc));
7300 }
7301
7302 /* NIC side RX descriptors. */
7303 for (i = 0; i < 6; i++) {
7304 unsigned long rxd;
7305
7306 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7307 + (i * sizeof(struct tg3_rx_buffer_desc));
7308 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7309 i,
7310 readl(rxd + 0x0), readl(rxd + 0x4),
7311 readl(rxd + 0x8), readl(rxd + 0xc));
7312 rxd += (4 * sizeof(u32));
7313 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7314 i,
7315 readl(rxd + 0x0), readl(rxd + 0x4),
7316 readl(rxd + 0x8), readl(rxd + 0xc));
7317 }
7318
7319 for (i = 0; i < 6; i++) {
7320 unsigned long rxd;
7321
7322 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7323 + (i * sizeof(struct tg3_rx_buffer_desc));
7324 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7325 i,
7326 readl(rxd + 0x0), readl(rxd + 0x4),
7327 readl(rxd + 0x8), readl(rxd + 0xc));
7328 rxd += (4 * sizeof(u32));
7329 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7330 i,
7331 readl(rxd + 0x0), readl(rxd + 0x4),
7332 readl(rxd + 0x8), readl(rxd + 0xc));
7333 }
7334}
7335#endif
7336
7337static struct net_device_stats *tg3_get_stats(struct net_device *);
7338static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7339
7340static int tg3_close(struct net_device *dev)
7341{
7342 struct tg3 *tp = netdev_priv(dev);
7343
7faa006f
MC		 7344 /* Calling flush_scheduled_work() may deadlock because
7345 * linkwatch_event() may be on the workqueue and it will try to get
7346 * the rtnl_lock which we are holding.
7347 */
7348 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7349 msleep(1);
7350
1da177e4
LT		 7351 netif_stop_queue(dev);
7352
7353 del_timer_sync(&tp->timer);
7354
f47c11ee 7355 tg3_full_lock(tp, 1);
1da177e4
LT		 7356#if 0
7357 tg3_dump_state(tp);
7358#endif
7359
7360 tg3_disable_ints(tp);
7361
944d980e 7362 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7363 tg3_free_rings(tp);
7364 tp->tg3_flags &=
7365 ~(TG3_FLAG_INIT_COMPLETE |
7366 TG3_FLAG_GOT_SERDES_FLOWCTL);
1da177e4 7367
f47c11ee 7368 tg3_full_unlock(tp);
1da177e4 7369
88b06bc2
MC		 7370 free_irq(tp->pdev->irq, dev);
7371 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7372 pci_disable_msi(tp->pdev);
7373 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7374 }
1da177e4
LT		 7375
7376 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7377 sizeof(tp->net_stats_prev));
7378 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7379 sizeof(tp->estats_prev));
7380
7381 tg3_free_consistent(tp);
7382
bc1c7567
MC		 7383 tg3_set_power_state(tp, PCI_D3hot);
7384
7385 netif_carrier_off(tp->dev);
7386
1da177e4
LT		 7387 return 0;
7388}
7389
7390static inline unsigned long get_stat64(tg3_stat64_t *val)
7391{
7392 unsigned long ret;
7393
7394#if (BITS_PER_LONG == 32)
7395 ret = val->low;
7396#else
7397 ret = ((u64)val->high << 32) | ((u64)val->low);
7398#endif
7399 return ret;
7400}
7401
7402static unsigned long calc_crc_errors(struct tg3 *tp)
7403{
7404 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7405
7406 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7407 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7409 u32 val;
7410
f47c11ee 7411 spin_lock_bh(&tp->lock);
1da177e4
LT		 7412 if (!tg3_readphy(tp, 0x1e, &val)) {
7413 tg3_writephy(tp, 0x1e, val | 0x8000);
7414 tg3_readphy(tp, 0x14, &val);
7415 } else
7416 val = 0;
f47c11ee 7417 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7418
7419 tp->phy_crc_errors += val;
7420
7421 return tp->phy_crc_errors;
7422 }
7423
7424 return get_stat64(&hw_stats->rx_fcs_errors);
7425}
7426
7427#define ESTAT_ADD(member) \
7428 estats->member = old_estats->member + \
7429 get_stat64(&hw_stats->member)
7430
7431static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7432{
7433 struct tg3_ethtool_stats *estats = &tp->estats;
7434 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7435 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7436
7437 if (!hw_stats)
7438 return old_estats;
7439
7440 ESTAT_ADD(rx_octets);
7441 ESTAT_ADD(rx_fragments);
7442 ESTAT_ADD(rx_ucast_packets);
7443 ESTAT_ADD(rx_mcast_packets);
7444 ESTAT_ADD(rx_bcast_packets);
7445 ESTAT_ADD(rx_fcs_errors);
7446 ESTAT_ADD(rx_align_errors);
7447 ESTAT_ADD(rx_xon_pause_rcvd);
7448 ESTAT_ADD(rx_xoff_pause_rcvd);
7449 ESTAT_ADD(rx_mac_ctrl_rcvd);
7450 ESTAT_ADD(rx_xoff_entered);
7451 ESTAT_ADD(rx_frame_too_long_errors);
7452 ESTAT_ADD(rx_jabbers);
7453 ESTAT_ADD(rx_undersize_packets);
7454 ESTAT_ADD(rx_in_length_errors);
7455 ESTAT_ADD(rx_out_length_errors);
7456 ESTAT_ADD(rx_64_or_less_octet_packets);
7457 ESTAT_ADD(rx_65_to_127_octet_packets);
7458 ESTAT_ADD(rx_128_to_255_octet_packets);
7459 ESTAT_ADD(rx_256_to_511_octet_packets);
7460 ESTAT_ADD(rx_512_to_1023_octet_packets);
7461 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7462 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7463 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7464 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7465 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7466
7467 ESTAT_ADD(tx_octets);
7468 ESTAT_ADD(tx_collisions);
7469 ESTAT_ADD(tx_xon_sent);
7470 ESTAT_ADD(tx_xoff_sent);
7471 ESTAT_ADD(tx_flow_control);
7472 ESTAT_ADD(tx_mac_errors);
7473 ESTAT_ADD(tx_single_collisions);
7474 ESTAT_ADD(tx_mult_collisions);
7475 ESTAT_ADD(tx_deferred);
7476 ESTAT_ADD(tx_excessive_collisions);
7477 ESTAT_ADD(tx_late_collisions);
7478 ESTAT_ADD(tx_collide_2times);
7479 ESTAT_ADD(tx_collide_3times);
7480 ESTAT_ADD(tx_collide_4times);
7481 ESTAT_ADD(tx_collide_5times);
7482 ESTAT_ADD(tx_collide_6times);
7483 ESTAT_ADD(tx_collide_7times);
7484 ESTAT_ADD(tx_collide_8times);
7485 ESTAT_ADD(tx_collide_9times);
7486 ESTAT_ADD(tx_collide_10times);
7487 ESTAT_ADD(tx_collide_11times);
7488 ESTAT_ADD(tx_collide_12times);
7489 ESTAT_ADD(tx_collide_13times);
7490 ESTAT_ADD(tx_collide_14times);
7491 ESTAT_ADD(tx_collide_15times);
7492 ESTAT_ADD(tx_ucast_packets);
7493 ESTAT_ADD(tx_mcast_packets);
7494 ESTAT_ADD(tx_bcast_packets);
7495 ESTAT_ADD(tx_carrier_sense_errors);
7496 ESTAT_ADD(tx_discards);
7497 ESTAT_ADD(tx_errors);
7498
7499 ESTAT_ADD(dma_writeq_full);
7500 ESTAT_ADD(dma_write_prioq_full);
7501 ESTAT_ADD(rxbds_empty);
7502 ESTAT_ADD(rx_discards);
7503 ESTAT_ADD(rx_errors);
7504 ESTAT_ADD(rx_threshold_hit);
7505
7506 ESTAT_ADD(dma_readq_full);
7507 ESTAT_ADD(dma_read_prioq_full);
7508 ESTAT_ADD(tx_comp_queue_full);
7509
7510 ESTAT_ADD(ring_set_send_prod_index);
7511 ESTAT_ADD(ring_status_update);
7512 ESTAT_ADD(nic_irqs);
7513 ESTAT_ADD(nic_avoided_irqs);
7514 ESTAT_ADD(nic_tx_threshold_hit);
7515
7516 return estats;
7517}
7518
7519static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7520{
7521 struct tg3 *tp = netdev_priv(dev);
7522 struct net_device_stats *stats = &tp->net_stats;
7523 struct net_device_stats *old_stats = &tp->net_stats_prev;
7524 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7525
7526 if (!hw_stats)
7527 return old_stats;
7528
7529 stats->rx_packets = old_stats->rx_packets +
7530 get_stat64(&hw_stats->rx_ucast_packets) +
7531 get_stat64(&hw_stats->rx_mcast_packets) +
7532 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7533
1da177e4
LT		 7534 stats->tx_packets = old_stats->tx_packets +
7535 get_stat64(&hw_stats->tx_ucast_packets) +
7536 get_stat64(&hw_stats->tx_mcast_packets) +
7537 get_stat64(&hw_stats->tx_bcast_packets);
7538
7539 stats->rx_bytes = old_stats->rx_bytes +
7540 get_stat64(&hw_stats->rx_octets);
7541 stats->tx_bytes = old_stats->tx_bytes +
7542 get_stat64(&hw_stats->tx_octets);
7543
7544 stats->rx_errors = old_stats->rx_errors +
4f63b877 7545 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7546 stats->tx_errors = old_stats->tx_errors +
7547 get_stat64(&hw_stats->tx_errors) +
7548 get_stat64(&hw_stats->tx_mac_errors) +
7549 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7550 get_stat64(&hw_stats->tx_discards);
7551
7552 stats->multicast = old_stats->multicast +
7553 get_stat64(&hw_stats->rx_mcast_packets);
7554 stats->collisions = old_stats->collisions +
7555 get_stat64(&hw_stats->tx_collisions);
7556
7557 stats->rx_length_errors = old_stats->rx_length_errors +
7558 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7559 get_stat64(&hw_stats->rx_undersize_packets);
7560
7561 stats->rx_over_errors = old_stats->rx_over_errors +
7562 get_stat64(&hw_stats->rxbds_empty);
7563 stats->rx_frame_errors = old_stats->rx_frame_errors +
7564 get_stat64(&hw_stats->rx_align_errors);
7565 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7566 get_stat64(&hw_stats->tx_discards);
7567 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7568 get_stat64(&hw_stats->tx_carrier_sense_errors);
7569
7570 stats->rx_crc_errors = old_stats->rx_crc_errors +
7571 calc_crc_errors(tp);
7572
4f63b877
JL		 7573 stats->rx_missed_errors = old_stats->rx_missed_errors +
7574 get_stat64(&hw_stats->rx_discards);
7575
1da177e4
LT		 7576 return stats;
7577}
7578
7579static inline u32 calc_crc(unsigned char *buf, int len)
7580{
7581 u32 reg;
7582 u32 tmp;
7583 int j, k;
7584
7585 reg = 0xffffffff;
7586
7587 for (j = 0; j < len; j++) {
7588 reg ^= buf[j];
7589
7590 for (k = 0; k < 8; k++) {
7591 tmp = reg & 0x01;
7592
7593 reg >>= 1;
7594
7595 if (tmp) {
7596 reg ^= 0xedb88320;
7597 }
7598 }
7599 }
7600
7601 return ~reg;
7602}
7603
7604static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7605{
7606 /* accept or reject all multicast frames */
7607 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7608 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7609 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7610 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7611}
7612
7613static void __tg3_set_rx_mode(struct net_device *dev)
7614{
7615 struct tg3 *tp = netdev_priv(dev);
7616 u32 rx_mode;
7617
7618 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7619 RX_MODE_KEEP_VLAN_TAG);
7620
7621 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7622 * flag clear.
7623 */
7624#if TG3_VLAN_TAG_USED
7625 if (!tp->vlgrp &&
7626 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7627 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7628#else
7629 /* By definition, VLAN is disabled always in this
7630 * case.
7631 */
7632 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7633 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7634#endif
7635
7636 if (dev->flags & IFF_PROMISC) {
7637 /* Promiscuous mode. */
7638 rx_mode |= RX_MODE_PROMISC;
7639 } else if (dev->flags & IFF_ALLMULTI) {
7640 /* Accept all multicast. */
7641 tg3_set_multi (tp, 1);
7642 } else if (dev->mc_count < 1) {
7643 /* Reject all multicast. */
7644 tg3_set_multi (tp, 0);
7645 } else {
7646 /* Accept one or more multicast(s). */
7647 struct dev_mc_list *mclist;
7648 unsigned int i;
7649 u32 mc_filter[4] = { 0, };
7650 u32 regidx;
7651 u32 bit;
7652 u32 crc;
7653
7654 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7655 i++, mclist = mclist->next) {
7656
7657 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7658 bit = ~crc & 0x7f;
7659 regidx = (bit & 0x60) >> 5;
7660 bit &= 0x1f;
7661 mc_filter[regidx] |= (1 << bit);
7662 }
7663
7664 tw32(MAC_HASH_REG_0, mc_filter[0]);
7665 tw32(MAC_HASH_REG_1, mc_filter[1]);
7666 tw32(MAC_HASH_REG_2, mc_filter[2]);
7667 tw32(MAC_HASH_REG_3, mc_filter[3]);
7668 }
7669
7670 if (rx_mode != tp->rx_mode) {
7671 tp->rx_mode = rx_mode;
7672 tw32_f(MAC_RX_MODE, rx_mode);
7673 udelay(10);
7674 }
7675}
7676
7677static void tg3_set_rx_mode(struct net_device *dev)
7678{
7679 struct tg3 *tp = netdev_priv(dev);
7680
e75f7c90
MC		 7681 if (!netif_running(dev))
7682 return;
7683
f47c11ee 7684 tg3_full_lock(tp, 0);
1da177e4 7685 __tg3_set_rx_mode(dev);
f47c11ee 7686 tg3_full_unlock(tp);
1da177e4
LT		 7687}
7688
7689#define TG3_REGDUMP_LEN (32 * 1024)
7690
7691static int tg3_get_regs_len(struct net_device *dev)
7692{
7693 return TG3_REGDUMP_LEN;
7694}
7695
7696static void tg3_get_regs(struct net_device *dev,
7697 struct ethtool_regs *regs, void *_p)
7698{
7699 u32 *p = _p;
7700 struct tg3 *tp = netdev_priv(dev);
7701 u8 *orig_p = _p;
7702 int i;
7703
7704 regs->version = 0;
7705
7706 memset(p, 0, TG3_REGDUMP_LEN);
7707
bc1c7567
MC		 7708 if (tp->link_config.phy_is_low_power)
7709 return;
7710
f47c11ee 7711 tg3_full_lock(tp, 0);
1da177e4
LT		 7712
7713#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7714#define GET_REG32_LOOP(base,len) \
7715do { p = (u32 *)(orig_p + (base)); \
7716 for (i = 0; i < len; i += 4) \
7717 __GET_REG32((base) + i); \
7718} while (0)
7719#define GET_REG32_1(reg) \
7720do { p = (u32 *)(orig_p + (reg)); \
7721 __GET_REG32((reg)); \
7722} while (0)
7723
7724 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7725 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7726 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7727 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7728 GET_REG32_1(SNDDATAC_MODE);
7729 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7730 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7731 GET_REG32_1(SNDBDC_MODE);
7732 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7733 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7734 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7735 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7736 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7737 GET_REG32_1(RCVDCC_MODE);
7738 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7739 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7740 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7741 GET_REG32_1(MBFREE_MODE);
7742 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7743 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7744 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7745 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7746 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 7747 GET_REG32_1(RX_CPU_MODE);
7748 GET_REG32_1(RX_CPU_STATE);
7749 GET_REG32_1(RX_CPU_PGMCTR);
7750 GET_REG32_1(RX_CPU_HWBKPT);
7751 GET_REG32_1(TX_CPU_MODE);
7752 GET_REG32_1(TX_CPU_STATE);
7753 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 7754 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7755 GET_REG32_LOOP(FTQ_RESET, 0x120);
7756 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7757 GET_REG32_1(DMAC_MODE);
7758 GET_REG32_LOOP(GRC_MODE, 0x4c);
7759 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7760 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7761
7762#undef __GET_REG32
7763#undef GET_REG32_LOOP
7764#undef GET_REG32_1
7765
f47c11ee 7766 tg3_full_unlock(tp);
1da177e4
LT		 7767}
7768
7769static int tg3_get_eeprom_len(struct net_device *dev)
7770{
7771 struct tg3 *tp = netdev_priv(dev);
7772
7773 return tp->nvram_size;
7774}
7775
7776static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 7777static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 7778
7779static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7780{
7781 struct tg3 *tp = netdev_priv(dev);
7782 int ret;
7783 u8 *pd;
7784 u32 i, offset, len, val, b_offset, b_count;
7785
bc1c7567
MC		 7786 if (tp->link_config.phy_is_low_power)
7787 return -EAGAIN;
7788
1da177e4
LT		 7789 offset = eeprom->offset;
7790 len = eeprom->len;
7791 eeprom->len = 0;
7792
7793 eeprom->magic = TG3_EEPROM_MAGIC;
7794
7795 if (offset & 3) {
7796 /* adjustments to start on required 4 byte boundary */
7797 b_offset = offset & 3;
7798 b_count = 4 - b_offset;
7799 if (b_count > len) {
7800 /* i.e. offset=1 len=2 */
7801 b_count = len;
7802 }
7803 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7804 if (ret)
7805 return ret;
7806 val = cpu_to_le32(val);
7807 memcpy(data, ((char*)&val) + b_offset, b_count);
7808 len -= b_count;
7809 offset += b_count;
7810 eeprom->len += b_count;
7811 }
7812
7813 /* read bytes upto the last 4 byte boundary */
7814 pd = &data[eeprom->len];
7815 for (i = 0; i < (len - (len & 3)); i += 4) {
7816 ret = tg3_nvram_read(tp, offset + i, &val);
7817 if (ret) {
7818 eeprom->len += i;
7819 return ret;
7820 }
7821 val = cpu_to_le32(val);
7822 memcpy(pd + i, &val, 4);
7823 }
7824 eeprom->len += i;
7825
7826 if (len & 3) {
7827 /* read last bytes not ending on 4 byte boundary */
7828 pd = &data[eeprom->len];
7829 b_count = len & 3;
7830 b_offset = offset + len - b_count;
7831 ret = tg3_nvram_read(tp, b_offset, &val);
7832 if (ret)
7833 return ret;
7834 val = cpu_to_le32(val);
7835 memcpy(pd, ((char*)&val), b_count);
7836 eeprom->len += b_count;
7837 }
7838 return 0;
7839}
7840
6aa20a22 7841static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 7842
7843static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7844{
7845 struct tg3 *tp = netdev_priv(dev);
7846 int ret;
7847 u32 offset, len, b_offset, odd_len, start, end;
7848 u8 *buf;
7849
bc1c7567
MC		 7850 if (tp->link_config.phy_is_low_power)
7851 return -EAGAIN;
7852
1da177e4
LT		 7853 if (eeprom->magic != TG3_EEPROM_MAGIC)
7854 return -EINVAL;
7855
7856 offset = eeprom->offset;
7857 len = eeprom->len;
7858
7859 if ((b_offset = (offset & 3))) {
7860 /* adjustments to start on required 4 byte boundary */
7861 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7862 if (ret)
7863 return ret;
7864 start = cpu_to_le32(start);
7865 len += b_offset;
7866 offset &= ~3;
1c8594b4
MC		 7867 if (len < 4)
7868 len = 4;
1da177e4
LT		 7869 }
7870
7871 odd_len = 0;
1c8594b4 7872 if (len & 3) {
1da177e4
LT		 7873 /* adjustments to end on required 4 byte boundary */
7874 odd_len = 1;
7875 len = (len + 3) & ~3;
7876 ret = tg3_nvram_read(tp, offset+len-4, &end);
7877 if (ret)
7878 return ret;
7879 end = cpu_to_le32(end);
7880 }
7881
7882 buf = data;
7883 if (b_offset || odd_len) {
7884 buf = kmalloc(len, GFP_KERNEL);
7885 if (buf == 0)
7886 return -ENOMEM;
7887 if (b_offset)
7888 memcpy(buf, &start, 4);
7889 if (odd_len)
7890 memcpy(buf+len-4, &end, 4);
7891 memcpy(buf + b_offset, data, eeprom->len);
7892 }
7893
7894 ret = tg3_nvram_write_block(tp, offset, len, buf);
7895
7896 if (buf != data)
7897 kfree(buf);
7898
7899 return ret;
7900}
7901
7902static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7903{
7904 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7905
1da177e4
LT		 7906 cmd->supported = (SUPPORTED_Autoneg);
7907
7908 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7909 cmd->supported |= (SUPPORTED_1000baseT_Half |
7910 SUPPORTED_1000baseT_Full);
7911
ef348144 7912 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 7913 cmd->supported |= (SUPPORTED_100baseT_Half |
7914 SUPPORTED_100baseT_Full |
7915 SUPPORTED_10baseT_Half |
7916 SUPPORTED_10baseT_Full |
7917 SUPPORTED_MII);
ef348144
KK		 7918 cmd->port = PORT_TP;
7919 } else {
1da177e4 7920 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 7921 cmd->port = PORT_FIBRE;
7922 }
6aa20a22 7923
1da177e4
LT		 7924 cmd->advertising = tp->link_config.advertising;
7925 if (netif_running(dev)) {
7926 cmd->speed = tp->link_config.active_speed;
7927 cmd->duplex = tp->link_config.active_duplex;
7928 }
1da177e4
LT		 7929 cmd->phy_address = PHY_ADDR;
7930 cmd->transceiver = 0;
7931 cmd->autoneg = tp->link_config.autoneg;
7932 cmd->maxtxpkt = 0;
7933 cmd->maxrxpkt = 0;
7934 return 0;
7935}
6aa20a22 7936
1da177e4
LT		 7937static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7938{
7939 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 7940
7941 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7942 /* These are the only valid advertisement bits allowed. */
7943 if (cmd->autoneg == AUTONEG_ENABLE &&
7944 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7945 ADVERTISED_1000baseT_Full |
7946 ADVERTISED_Autoneg |
7947 ADVERTISED_FIBRE)))
7948 return -EINVAL;
37ff238d
MC		 7949 /* Fiber can only do SPEED_1000. */
7950 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7951 (cmd->speed != SPEED_1000))
7952 return -EINVAL;
7953 /* Copper cannot force SPEED_1000. */
7954 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7955 (cmd->speed == SPEED_1000))
7956 return -EINVAL;
7957 else if ((cmd->speed == SPEED_1000) &&
7958 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7959 return -EINVAL;
1da177e4 7960
f47c11ee 7961 tg3_full_lock(tp, 0);
1da177e4
LT		 7962
7963 tp->link_config.autoneg = cmd->autoneg;
7964 if (cmd->autoneg == AUTONEG_ENABLE) {
7965 tp->link_config.advertising = cmd->advertising;
7966 tp->link_config.speed = SPEED_INVALID;
7967 tp->link_config.duplex = DUPLEX_INVALID;
7968 } else {
7969 tp->link_config.advertising = 0;
7970 tp->link_config.speed = cmd->speed;
7971 tp->link_config.duplex = cmd->duplex;
7972 }
6aa20a22 7973
24fcad6b
MC		 7974 tp->link_config.orig_speed = tp->link_config.speed;
7975 tp->link_config.orig_duplex = tp->link_config.duplex;
7976 tp->link_config.orig_autoneg = tp->link_config.autoneg;
7977
1da177e4
LT		 7978 if (netif_running(dev))
7979 tg3_setup_phy(tp, 1);
7980
f47c11ee 7981 tg3_full_unlock(tp);
6aa20a22 7982
1da177e4
LT		 7983 return 0;
7984}
6aa20a22 7985
1da177e4
LT		 7986static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7987{
7988 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7989
1da177e4
LT		 7990 strcpy(info->driver, DRV_MODULE_NAME);
7991 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 7992 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 7993 strcpy(info->bus_info, pci_name(tp->pdev));
7994}
6aa20a22 7995
1da177e4
LT		 7996static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7997{
7998 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7999
1da177e4
LT		 8000 wol->supported = WAKE_MAGIC;
8001 wol->wolopts = 0;
8002 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8003 wol->wolopts = WAKE_MAGIC;
8004 memset(&wol->sopass, 0, sizeof(wol->sopass));
8005}
6aa20a22 8006
1da177e4
LT		 8007static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8008{
8009 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8010
1da177e4
LT		 8011 if (wol->wolopts & ~WAKE_MAGIC)
8012 return -EINVAL;
8013 if ((wol->wolopts & WAKE_MAGIC) &&
3f7045c1 8014 tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
1da177e4
LT		 8015 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8016 return -EINVAL;
6aa20a22 8017
f47c11ee 8018 spin_lock_bh(&tp->lock);
1da177e4
LT		 8019 if (wol->wolopts & WAKE_MAGIC)
8020 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8021 else
8022 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8023 spin_unlock_bh(&tp->lock);
6aa20a22 8024
1da177e4
LT		 8025 return 0;
8026}
6aa20a22 8027
1da177e4
LT		 8028static u32 tg3_get_msglevel(struct net_device *dev)
8029{
8030 struct tg3 *tp = netdev_priv(dev);
8031 return tp->msg_enable;
8032}
6aa20a22 8033
1da177e4
LT		 8034static void tg3_set_msglevel(struct net_device *dev, u32 value)
8035{
8036 struct tg3 *tp = netdev_priv(dev);
8037 tp->msg_enable = value;
8038}
6aa20a22 8039
1da177e4
LT		 8040static int tg3_set_tso(struct net_device *dev, u32 value)
8041{
8042 struct tg3 *tp = netdev_priv(dev);
8043
8044 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8045 if (value)
8046 return -EINVAL;
8047 return 0;
8048 }
b5d3772c
MC		 8049 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8050 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
b0026624
MC		 8051 if (value)
8052 dev->features |= NETIF_F_TSO6;
8053 else
8054 dev->features &= ~NETIF_F_TSO6;
8055 }
1da177e4
LT		 8056 return ethtool_op_set_tso(dev, value);
8057}
6aa20a22 8058
1da177e4
LT		 8059static int tg3_nway_reset(struct net_device *dev)
8060{
8061 struct tg3 *tp = netdev_priv(dev);
8062 u32 bmcr;
8063 int r;
6aa20a22 8064
1da177e4
LT		 8065 if (!netif_running(dev))
8066 return -EAGAIN;
8067
c94e3941
MC		 8068 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8069 return -EINVAL;
8070
f47c11ee 8071 spin_lock_bh(&tp->lock);
1da177e4
LT		 8072 r = -EINVAL;
8073 tg3_readphy(tp, MII_BMCR, &bmcr);
8074 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8075 ((bmcr & BMCR_ANENABLE) ||
8076 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8077 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8078 BMCR_ANENABLE);
1da177e4
LT		 8079 r = 0;
8080 }
f47c11ee 8081 spin_unlock_bh(&tp->lock);
6aa20a22 8082
1da177e4
LT		 8083 return r;
8084}
6aa20a22 8085
1da177e4
LT		 8086static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8087{
8088 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8089
1da177e4
LT		 8090 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8091 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8092 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8093 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8094 else
8095 ering->rx_jumbo_max_pending = 0;
8096
8097 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8098
8099 ering->rx_pending = tp->rx_pending;
8100 ering->rx_mini_pending = 0;
4f81c32b
MC		 8101 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8102 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8103 else
8104 ering->rx_jumbo_pending = 0;
8105
1da177e4
LT		 8106 ering->tx_pending = tp->tx_pending;
8107}
6aa20a22 8108
1da177e4
LT		 8109static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8110{
8111 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8112 int irq_sync = 0, err = 0;
6aa20a22 8113
1da177e4
LT		 8114 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8115 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8116 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8117 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8118 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8119 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8120 return -EINVAL;
6aa20a22 8121
bbe832c0 8122 if (netif_running(dev)) {
1da177e4 8123 tg3_netif_stop(tp);
bbe832c0
MC		 8124 irq_sync = 1;
8125 }
1da177e4 8126
bbe832c0 8127 tg3_full_lock(tp, irq_sync);
6aa20a22 8128
1da177e4
LT		 8129 tp->rx_pending = ering->rx_pending;
8130
8131 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8132 tp->rx_pending > 63)
8133 tp->rx_pending = 63;
8134 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8135 tp->tx_pending = ering->tx_pending;
8136
8137 if (netif_running(dev)) {
944d980e 8138 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8139 err = tg3_restart_hw(tp, 1);
8140 if (!err)
8141 tg3_netif_start(tp);
1da177e4
LT		 8142 }
8143
f47c11ee 8144 tg3_full_unlock(tp);
6aa20a22 8145
b9ec6c1b 8146 return err;
1da177e4 8147}
6aa20a22 8148
1da177e4
LT		 8149static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8150{
8151 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8152
1da177e4
LT		 8153 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8154 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8155 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8156}
6aa20a22 8157
1da177e4
LT		 8158static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8159{
8160 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8161 int irq_sync = 0, err = 0;
6aa20a22 8162
bbe832c0 8163 if (netif_running(dev)) {
1da177e4 8164 tg3_netif_stop(tp);
bbe832c0
MC		 8165 irq_sync = 1;
8166 }
1da177e4 8167
bbe832c0 8168 tg3_full_lock(tp, irq_sync);
f47c11ee 8169
1da177e4
LT		 8170 if (epause->autoneg)
8171 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8172 else
8173 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8174 if (epause->rx_pause)
8175 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8176 else
8177 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8178 if (epause->tx_pause)
8179 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8180 else
8181 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8182
8183 if (netif_running(dev)) {
944d980e 8184 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8185 err = tg3_restart_hw(tp, 1);
8186 if (!err)
8187 tg3_netif_start(tp);
1da177e4 8188 }
f47c11ee
DM		 8189
8190 tg3_full_unlock(tp);
6aa20a22 8191
b9ec6c1b 8192 return err;
1da177e4 8193}
6aa20a22 8194
1da177e4
LT		 8195static u32 tg3_get_rx_csum(struct net_device *dev)
8196{
8197 struct tg3 *tp = netdev_priv(dev);
8198 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8199}
6aa20a22 8200
1da177e4
LT		 8201static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8202{
8203 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8204
1da177e4
LT		 8205 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8206 if (data != 0)
8207 return -EINVAL;
8208 return 0;
8209 }
6aa20a22 8210
f47c11ee 8211 spin_lock_bh(&tp->lock);
1da177e4
LT		 8212 if (data)
8213 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8214 else
8215 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8216 spin_unlock_bh(&tp->lock);
6aa20a22 8217
1da177e4
LT		 8218 return 0;
8219}
6aa20a22 8220
1da177e4
LT		 8221static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8222{
8223 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8224
1da177e4
LT		 8225 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8226 if (data != 0)
8227 return -EINVAL;
8228 return 0;
8229 }
6aa20a22 8230
af36e6b6
MC		 8231 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8232 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf 8233 ethtool_op_set_tx_hw_csum(dev, data);
1da177e4 8234 else
9c27dbdf 8235 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8236
8237 return 0;
8238}
8239
8240static int tg3_get_stats_count (struct net_device *dev)
8241{
8242 return TG3_NUM_STATS;
8243}
8244
4cafd3f5
MC		 8245static int tg3_get_test_count (struct net_device *dev)
8246{
8247 return TG3_NUM_TEST;
8248}
8249
1da177e4
LT		 8250static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8251{
8252 switch (stringset) {
8253 case ETH_SS_STATS:
8254 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8255 break;
4cafd3f5
MC		 8256 case ETH_SS_TEST:
8257 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8258 break;
1da177e4
LT		 8259 default:
8260 WARN_ON(1); /* we need a WARN() */
8261 break;
8262 }
8263}
8264
4009a93d
MC		 8265static int tg3_phys_id(struct net_device *dev, u32 data)
8266{
8267 struct tg3 *tp = netdev_priv(dev);
8268 int i;
8269
8270 if (!netif_running(tp->dev))
8271 return -EAGAIN;
8272
8273 if (data == 0)
8274 data = 2;
8275
8276 for (i = 0; i < (data * 2); i++) {
8277 if ((i % 2) == 0)
8278 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8279 LED_CTRL_1000MBPS_ON |
8280 LED_CTRL_100MBPS_ON |
8281 LED_CTRL_10MBPS_ON |
8282 LED_CTRL_TRAFFIC_OVERRIDE |
8283 LED_CTRL_TRAFFIC_BLINK |
8284 LED_CTRL_TRAFFIC_LED);
6aa20a22 8285
4009a93d
MC		 8286 else
8287 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8288 LED_CTRL_TRAFFIC_OVERRIDE);
8289
8290 if (msleep_interruptible(500))
8291 break;
8292 }
8293 tw32(MAC_LED_CTRL, tp->led_ctrl);
8294 return 0;
8295}
8296
1da177e4
LT		 8297static void tg3_get_ethtool_stats (struct net_device *dev,
8298 struct ethtool_stats *estats, u64 *tmp_stats)
8299{
8300 struct tg3 *tp = netdev_priv(dev);
8301 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8302}
8303
566f86ad 8304#define NVRAM_TEST_SIZE 0x100
1b27777a 8305#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
b16250e3
MC		 8306#define NVRAM_SELFBOOT_HW_SIZE 0x20
8307#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8308
8309static int tg3_test_nvram(struct tg3 *tp)
8310{
1b27777a
MC		 8311 u32 *buf, csum, magic;
8312 int i, j, err = 0, size;
566f86ad 8313
1820180b 8314 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8315 return -EIO;
8316
1b27777a
MC		 8317 if (magic == TG3_EEPROM_MAGIC)
8318 size = NVRAM_TEST_SIZE;
b16250e3 8319 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8320 if ((magic & 0xe00000) == 0x200000)
8321 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8322 else
8323 return 0;
b16250e3
MC		 8324 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8325 size = NVRAM_SELFBOOT_HW_SIZE;
8326 else
1b27777a
MC		 8327 return -EIO;
8328
8329 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8330 if (buf == NULL)
8331 return -ENOMEM;
8332
1b27777a
MC		 8333 err = -EIO;
8334 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8335 u32 val;
8336
8337 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8338 break;
8339 buf[j] = cpu_to_le32(val);
8340 }
1b27777a 8341 if (i < size)
566f86ad
MC		 8342 goto out;
8343
1b27777a 8344 /* Selfboot format */
b16250e3
MC		 8345 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8346 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8347 u8 *buf8 = (u8 *) buf, csum8 = 0;
8348
8349 for (i = 0; i < size; i++)
8350 csum8 += buf8[i];
8351
ad96b485
AB		 8352 if (csum8 == 0) {
8353 err = 0;
8354 goto out;
8355 }
8356
8357 err = -EIO;
8358 goto out;
1b27777a 8359 }
566f86ad 8360
b16250e3
MC		 8361 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8362 TG3_EEPROM_MAGIC_HW) {
8363 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8364 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8365 u8 *buf8 = (u8 *) buf;
8366 int j, k;
8367
8368 /* Separate the parity bits and the data bytes. */
8369 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8370 if ((i == 0) || (i == 8)) {
8371 int l;
8372 u8 msk;
8373
8374 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8375 parity[k++] = buf8[i] & msk;
8376 i++;
8377 }
8378 else if (i == 16) {
8379 int l;
8380 u8 msk;
8381
8382 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8383 parity[k++] = buf8[i] & msk;
8384 i++;
8385
8386 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8387 parity[k++] = buf8[i] & msk;
8388 i++;
8389 }
8390 data[j++] = buf8[i];
8391 }
8392
8393 err = -EIO;
8394 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8395 u8 hw8 = hweight8(data[i]);
8396
8397 if ((hw8 & 0x1) && parity[i])
8398 goto out;
8399 else if (!(hw8 & 0x1) && !parity[i])
8400 goto out;
8401 }
8402 err = 0;
8403 goto out;
8404 }
8405
566f86ad
MC		 8406 /* Bootstrap checksum at offset 0x10 */
8407 csum = calc_crc((unsigned char *) buf, 0x10);
8408 if(csum != cpu_to_le32(buf[0x10/4]))
8409 goto out;
8410
8411 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8412 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8413 if (csum != cpu_to_le32(buf[0xfc/4]))
8414 goto out;
8415
8416 err = 0;
8417
8418out:
8419 kfree(buf);
8420 return err;
8421}
8422
ca43007a
MC		 8423#define TG3_SERDES_TIMEOUT_SEC 2
8424#define TG3_COPPER_TIMEOUT_SEC 6
8425
8426static int tg3_test_link(struct tg3 *tp)
8427{
8428 int i, max;
8429
8430 if (!netif_running(tp->dev))
8431 return -ENODEV;
8432
4c987487 8433 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8434 max = TG3_SERDES_TIMEOUT_SEC;
8435 else
8436 max = TG3_COPPER_TIMEOUT_SEC;
8437
8438 for (i = 0; i < max; i++) {
8439 if (netif_carrier_ok(tp->dev))
8440 return 0;
8441
8442 if (msleep_interruptible(1000))
8443 break;
8444 }
8445
8446 return -EIO;
8447}
8448
a71116d1 8449/* Only test the commonly used registers */
30ca3e37 8450static int tg3_test_registers(struct tg3 *tp)
a71116d1 8451{
b16250e3 8452 int i, is_5705, is_5750;
a71116d1
MC		 8453 u32 offset, read_mask, write_mask, val, save_val, read_val;
8454 static struct {
8455 u16 offset;
8456 u16 flags;
8457#define TG3_FL_5705 0x1
8458#define TG3_FL_NOT_5705 0x2
8459#define TG3_FL_NOT_5788 0x4
b16250e3 8460#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8461 u32 read_mask;
8462 u32 write_mask;
8463 } reg_tbl[] = {
8464 /* MAC Control Registers */
8465 { MAC_MODE, TG3_FL_NOT_5705,
8466 0x00000000, 0x00ef6f8c },
8467 { MAC_MODE, TG3_FL_5705,
8468 0x00000000, 0x01ef6b8c },
8469 { MAC_STATUS, TG3_FL_NOT_5705,
8470 0x03800107, 0x00000000 },
8471 { MAC_STATUS, TG3_FL_5705,
8472 0x03800100, 0x00000000 },
8473 { MAC_ADDR_0_HIGH, 0x0000,
8474 0x00000000, 0x0000ffff },
8475 { MAC_ADDR_0_LOW, 0x0000,
8476 0x00000000, 0xffffffff },
8477 { MAC_RX_MTU_SIZE, 0x0000,
8478 0x00000000, 0x0000ffff },
8479 { MAC_TX_MODE, 0x0000,
8480 0x00000000, 0x00000070 },
8481 { MAC_TX_LENGTHS, 0x0000,
8482 0x00000000, 0x00003fff },
8483 { MAC_RX_MODE, TG3_FL_NOT_5705,
8484 0x00000000, 0x000007fc },
8485 { MAC_RX_MODE, TG3_FL_5705,
8486 0x00000000, 0x000007dc },
8487 { MAC_HASH_REG_0, 0x0000,
8488 0x00000000, 0xffffffff },
8489 { MAC_HASH_REG_1, 0x0000,
8490 0x00000000, 0xffffffff },
8491 { MAC_HASH_REG_2, 0x0000,
8492 0x00000000, 0xffffffff },
8493 { MAC_HASH_REG_3, 0x0000,
8494 0x00000000, 0xffffffff },
8495
8496 /* Receive Data and Receive BD Initiator Control Registers. */
8497 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8498 0x00000000, 0xffffffff },
8499 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8500 0x00000000, 0xffffffff },
8501 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8502 0x00000000, 0x00000003 },
8503 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8504 0x00000000, 0xffffffff },
8505 { RCVDBDI_STD_BD+0, 0x0000,
8506 0x00000000, 0xffffffff },
8507 { RCVDBDI_STD_BD+4, 0x0000,
8508 0x00000000, 0xffffffff },
8509 { RCVDBDI_STD_BD+8, 0x0000,
8510 0x00000000, 0xffff0002 },
8511 { RCVDBDI_STD_BD+0xc, 0x0000,
8512 0x00000000, 0xffffffff },
6aa20a22 8513
a71116d1
MC		 8514 /* Receive BD Initiator Control Registers. */
8515 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8516 0x00000000, 0xffffffff },
8517 { RCVBDI_STD_THRESH, TG3_FL_5705,
8518 0x00000000, 0x000003ff },
8519 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8520 0x00000000, 0xffffffff },
6aa20a22 8521
a71116d1
MC		 8522 /* Host Coalescing Control Registers. */
8523 { HOSTCC_MODE, TG3_FL_NOT_5705,
8524 0x00000000, 0x00000004 },
8525 { HOSTCC_MODE, TG3_FL_5705,
8526 0x00000000, 0x000000f6 },
8527 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8528 0x00000000, 0xffffffff },
8529 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8530 0x00000000, 0x000003ff },
8531 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8532 0x00000000, 0xffffffff },
8533 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8534 0x00000000, 0x000003ff },
8535 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8536 0x00000000, 0xffffffff },
8537 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8538 0x00000000, 0x000000ff },
8539 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8540 0x00000000, 0xffffffff },
8541 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8542 0x00000000, 0x000000ff },
8543 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8544 0x00000000, 0xffffffff },
8545 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8546 0x00000000, 0xffffffff },
8547 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8548 0x00000000, 0xffffffff },
8549 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8550 0x00000000, 0x000000ff },
8551 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8552 0x00000000, 0xffffffff },
8553 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8554 0x00000000, 0x000000ff },
8555 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8556 0x00000000, 0xffffffff },
8557 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8558 0x00000000, 0xffffffff },
8559 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8560 0x00000000, 0xffffffff },
8561 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8562 0x00000000, 0xffffffff },
8563 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8564 0x00000000, 0xffffffff },
8565 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8566 0xffffffff, 0x00000000 },
8567 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8568 0xffffffff, 0x00000000 },
8569
8570 /* Buffer Manager Control Registers. */
b16250e3 8571 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 8572 0x00000000, 0x007fff80 },
b16250e3 8573 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 8574 0x00000000, 0x007fffff },
8575 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8576 0x00000000, 0x0000003f },
8577 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8578 0x00000000, 0x000001ff },
8579 { BUFMGR_MB_HIGH_WATER, 0x0000,
8580 0x00000000, 0x000001ff },
8581 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8582 0xffffffff, 0x00000000 },
8583 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8584 0xffffffff, 0x00000000 },
6aa20a22 8585
a71116d1
MC		 8586 /* Mailbox Registers */
8587 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8588 0x00000000, 0x000001ff },
8589 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8590 0x00000000, 0x000001ff },
8591 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8592 0x00000000, 0x000007ff },
8593 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8594 0x00000000, 0x000001ff },
8595
8596 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8597 };
8598
b16250e3
MC		 8599 is_5705 = is_5750 = 0;
8600 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 8601 is_5705 = 1;
b16250e3
MC		 8602 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8603 is_5750 = 1;
8604 }
a71116d1
MC		 8605
8606 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8607 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8608 continue;
8609
8610 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8611 continue;
8612
8613 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8614 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8615 continue;
8616
b16250e3
MC		 8617 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8618 continue;
8619
a71116d1
MC		 8620 offset = (u32) reg_tbl[i].offset;
8621 read_mask = reg_tbl[i].read_mask;
8622 write_mask = reg_tbl[i].write_mask;
8623
8624 /* Save the original register content */
8625 save_val = tr32(offset);
8626
8627 /* Determine the read-only value. */
8628 read_val = save_val & read_mask;
8629
8630 /* Write zero to the register, then make sure the read-only bits
8631 * are not changed and the read/write bits are all zeros.
8632 */
8633 tw32(offset, 0);
8634
8635 val = tr32(offset);
8636
8637 /* Test the read-only and read/write bits. */
8638 if (((val & read_mask) != read_val) || (val & write_mask))
8639 goto out;
8640
8641 /* Write ones to all the bits defined by RdMask and WrMask, then
8642 * make sure the read-only bits are not changed and the
8643 * read/write bits are all ones.
8644 */
8645 tw32(offset, read_mask | write_mask);
8646
8647 val = tr32(offset);
8648
8649 /* Test the read-only bits. */
8650 if ((val & read_mask) != read_val)
8651 goto out;
8652
8653 /* Test the read/write bits. */
8654 if ((val & write_mask) != write_mask)
8655 goto out;
8656
8657 tw32(offset, save_val);
8658 }
8659
8660 return 0;
8661
8662out:
9f88f29f
MC		 8663 if (netif_msg_hw(tp))
8664 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8665 offset);
a71116d1
MC		 8666 tw32(offset, save_val);
8667 return -EIO;
8668}
8669
7942e1db
MC		 8670static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8671{
f71e1309 8672 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 8673 int i;
8674 u32 j;
8675
8676 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8677 for (j = 0; j < len; j += 4) {
8678 u32 val;
8679
8680 tg3_write_mem(tp, offset + j, test_pattern[i]);
8681 tg3_read_mem(tp, offset + j, &val);
8682 if (val != test_pattern[i])
8683 return -EIO;
8684 }
8685 }
8686 return 0;
8687}
8688
8689static int tg3_test_memory(struct tg3 *tp)
8690{
8691 static struct mem_entry {
8692 u32 offset;
8693 u32 len;
8694 } mem_tbl_570x[] = {
38690194 8695 { 0x00000000, 0x00b50},
7942e1db
MC		 8696 { 0x00002000, 0x1c000},
8697 { 0xffffffff, 0x00000}
8698 }, mem_tbl_5705[] = {
8699 { 0x00000100, 0x0000c},
8700 { 0x00000200, 0x00008},
7942e1db
MC		 8701 { 0x00004000, 0x00800},
8702 { 0x00006000, 0x01000},
8703 { 0x00008000, 0x02000},
8704 { 0x00010000, 0x0e000},
8705 { 0xffffffff, 0x00000}
79f4d13a
MC		 8706 }, mem_tbl_5755[] = {
8707 { 0x00000200, 0x00008},
8708 { 0x00004000, 0x00800},
8709 { 0x00006000, 0x00800},
8710 { 0x00008000, 0x02000},
8711 { 0x00010000, 0x0c000},
8712 { 0xffffffff, 0x00000}
b16250e3
MC		 8713 }, mem_tbl_5906[] = {
8714 { 0x00000200, 0x00008},
8715 { 0x00004000, 0x00400},
8716 { 0x00006000, 0x00400},
8717 { 0x00008000, 0x01000},
8718 { 0x00010000, 0x01000},
8719 { 0xffffffff, 0x00000}
7942e1db
MC		 8720 };
8721 struct mem_entry *mem_tbl;
8722 int err = 0;
8723 int i;
8724
79f4d13a 8725 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6
MC		 8726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8727 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
79f4d13a 8728 mem_tbl = mem_tbl_5755;
b16250e3
MC		 8729 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8730 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 8731 else
8732 mem_tbl = mem_tbl_5705;
8733 } else
7942e1db
MC		 8734 mem_tbl = mem_tbl_570x;
8735
8736 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8737 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8738 mem_tbl[i].len)) != 0)
8739 break;
8740 }
6aa20a22 8741
7942e1db
MC		 8742 return err;
8743}
8744
9f40dead
MC		 8745#define TG3_MAC_LOOPBACK 0
8746#define TG3_PHY_LOOPBACK 1
8747
8748static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8749{
9f40dead 8750 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8751 u32 desc_idx;
8752 struct sk_buff *skb, *rx_skb;
8753 u8 *tx_data;
8754 dma_addr_t map;
8755 int num_pkts, tx_len, rx_len, i, err;
8756 struct tg3_rx_buffer_desc *desc;
8757
9f40dead 8758 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8759 /* HW errata - mac loopback fails in some cases on 5780.
8760 * Normal traffic and PHY loopback are not affected by
8761 * errata.
8762 */
8763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8764 return 0;
8765
9f40dead 8766 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
3f7045c1
MC		 8767 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8768 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8769 mac_mode |= MAC_MODE_PORT_MODE_MII;
8770 else
8771 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 8772 tw32(MAC_MODE, mac_mode);
8773 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 8774 u32 val;
8775
b16250e3
MC		 8776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8777 u32 phytest;
8778
8779 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8780 u32 phy;
8781
8782 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8783 phytest | MII_TG3_EPHY_SHADOW_EN);
8784 if (!tg3_readphy(tp, 0x1b, &phy))
8785 tg3_writephy(tp, 0x1b, phy & ~0x20);
8786 if (!tg3_readphy(tp, 0x10, &phy))
8787 tg3_writephy(tp, 0x10, phy & ~0x4000);
8788 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8789 }
5d64ad34
MC		 8790 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8791 } else
8792 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1
MC		 8793
8794 tg3_writephy(tp, MII_BMCR, val);
c94e3941 8795 udelay(40);
5d64ad34
MC		 8796
8797 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8798 MAC_MODE_LINK_POLARITY;
8799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 8800 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 8801 mac_mode |= MAC_MODE_PORT_MODE_MII;
8802 } else
8803 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 8804
c94e3941
MC		 8805 /* reset to prevent losing 1st rx packet intermittently */
8806 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8807 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8808 udelay(10);
8809 tw32_f(MAC_RX_MODE, tp->rx_mode);
8810 }
ff18ff02 8811 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9f40dead 8812 mac_mode &= ~MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 8813 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8814 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8815 }
9f40dead 8816 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8817 }
8818 else
8819 return -EINVAL;
c76949a6
MC		 8820
8821 err = -EIO;
8822
c76949a6 8823 tx_len = 1514;
a20e9c62 8824 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 8825 if (!skb)
8826 return -ENOMEM;
8827
c76949a6
MC		 8828 tx_data = skb_put(skb, tx_len);
8829 memcpy(tx_data, tp->dev->dev_addr, 6);
8830 memset(tx_data + 6, 0x0, 8);
8831
8832 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8833
8834 for (i = 14; i < tx_len; i++)
8835 tx_data[i] = (u8) (i & 0xff);
8836
8837 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8838
8839 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8840 HOSTCC_MODE_NOW);
8841
8842 udelay(10);
8843
8844 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8845
c76949a6
MC		 8846 num_pkts = 0;
8847
9f40dead 8848 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8849
9f40dead 8850 tp->tx_prod++;
c76949a6
MC		 8851 num_pkts++;
8852
9f40dead
MC		 8853 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8854 tp->tx_prod);
09ee929c 8855 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8856
8857 udelay(10);
8858
3f7045c1
MC		 8859 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8860 for (i = 0; i < 25; i++) {
c76949a6
MC		 8861 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8862 HOSTCC_MODE_NOW);
8863
8864 udelay(10);
8865
8866 tx_idx = tp->hw_status->idx[0].tx_consumer;
8867 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8868 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8869 (rx_idx == (rx_start_idx + num_pkts)))
8870 break;
8871 }
8872
8873 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8874 dev_kfree_skb(skb);
8875
9f40dead 8876 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8877 goto out;
8878
8879 if (rx_idx != rx_start_idx + num_pkts)
8880 goto out;
8881
8882 desc = &tp->rx_rcb[rx_start_idx];
8883 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8884 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8885 if (opaque_key != RXD_OPAQUE_RING_STD)
8886 goto out;
8887
8888 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8889 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8890 goto out;
8891
8892 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8893 if (rx_len != tx_len)
8894 goto out;
8895
8896 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8897
8898 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8899 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8900
8901 for (i = 14; i < tx_len; i++) {
8902 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8903 goto out;
8904 }
8905 err = 0;
6aa20a22 8906
c76949a6
MC		 8907 /* tg3_free_rings will unmap and free the rx_skb */
8908out:
8909 return err;
8910}
8911
9f40dead
MC		 8912#define TG3_MAC_LOOPBACK_FAILED 1
8913#define TG3_PHY_LOOPBACK_FAILED 2
8914#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8915 TG3_PHY_LOOPBACK_FAILED)
8916
8917static int tg3_test_loopback(struct tg3 *tp)
8918{
8919 int err = 0;
8920
8921 if (!netif_running(tp->dev))
8922 return TG3_LOOPBACK_FAILED;
8923
b9ec6c1b
MC		 8924 err = tg3_reset_hw(tp, 1);
8925 if (err)
8926 return TG3_LOOPBACK_FAILED;
9f40dead
MC		 8927
8928 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8929 err |= TG3_MAC_LOOPBACK_FAILED;
8930 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8931 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8932 err |= TG3_PHY_LOOPBACK_FAILED;
8933 }
8934
8935 return err;
8936}
8937
4cafd3f5
MC		 8938static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8939 u64 *data)
8940{
566f86ad
MC		 8941 struct tg3 *tp = netdev_priv(dev);
8942
bc1c7567
MC		 8943 if (tp->link_config.phy_is_low_power)
8944 tg3_set_power_state(tp, PCI_D0);
8945
566f86ad
MC		 8946 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8947
8948 if (tg3_test_nvram(tp) != 0) {
8949 etest->flags |= ETH_TEST_FL_FAILED;
8950 data[0] = 1;
8951 }
ca43007a
MC		 8952 if (tg3_test_link(tp) != 0) {
8953 etest->flags |= ETH_TEST_FL_FAILED;
8954 data[1] = 1;
8955 }
a71116d1 8956 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 8957 int err, irq_sync = 0;
bbe832c0
MC		 8958
8959 if (netif_running(dev)) {
a71116d1 8960 tg3_netif_stop(tp);
bbe832c0
MC		 8961 irq_sync = 1;
8962 }
a71116d1 8963
bbe832c0 8964 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8965
8966 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 8967 err = tg3_nvram_lock(tp);
a71116d1
MC		 8968 tg3_halt_cpu(tp, RX_CPU_BASE);
8969 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8970 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 8971 if (!err)
8972 tg3_nvram_unlock(tp);
a71116d1 8973
d9ab5ad1
MC		 8974 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8975 tg3_phy_reset(tp);
8976
a71116d1
MC		 8977 if (tg3_test_registers(tp) != 0) {
8978 etest->flags |= ETH_TEST_FL_FAILED;
8979 data[2] = 1;
8980 }
7942e1db
MC		 8981 if (tg3_test_memory(tp) != 0) {
8982 etest->flags |= ETH_TEST_FL_FAILED;
8983 data[3] = 1;
8984 }
9f40dead 8985 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 8986 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 8987
f47c11ee
DM		 8988 tg3_full_unlock(tp);
8989
d4bc3927
MC		 8990 if (tg3_test_interrupt(tp) != 0) {
8991 etest->flags |= ETH_TEST_FL_FAILED;
8992 data[5] = 1;
8993 }
f47c11ee
DM		 8994
8995 tg3_full_lock(tp, 0);
d4bc3927 8996
a71116d1
MC		 8997 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8998 if (netif_running(dev)) {
8999 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9000 if (!tg3_restart_hw(tp, 1))
9001 tg3_netif_start(tp);
a71116d1 9002 }
f47c11ee
DM		 9003
9004 tg3_full_unlock(tp);
a71116d1 9005 }
bc1c7567
MC		 9006 if (tp->link_config.phy_is_low_power)
9007 tg3_set_power_state(tp, PCI_D3hot);
9008
4cafd3f5
MC		 9009}
9010
1da177e4
LT		 9011static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9012{
9013 struct mii_ioctl_data *data = if_mii(ifr);
9014 struct tg3 *tp = netdev_priv(dev);
9015 int err;
9016
9017 switch(cmd) {
9018 case SIOCGMIIPHY:
9019 data->phy_id = PHY_ADDR;
9020
9021 /* fallthru */
9022 case SIOCGMIIREG: {
9023 u32 mii_regval;
9024
9025 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9026 break; /* We have no PHY */
9027
bc1c7567
MC		 9028 if (tp->link_config.phy_is_low_power)
9029 return -EAGAIN;
9030
f47c11ee 9031 spin_lock_bh(&tp->lock);
1da177e4 9032 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9033 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9034
9035 data->val_out = mii_regval;
9036
9037 return err;
9038 }
9039
9040 case SIOCSMIIREG:
9041 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9042 break; /* We have no PHY */
9043
9044 if (!capable(CAP_NET_ADMIN))
9045 return -EPERM;
9046
bc1c7567
MC		 9047 if (tp->link_config.phy_is_low_power)
9048 return -EAGAIN;
9049
f47c11ee 9050 spin_lock_bh(&tp->lock);
1da177e4 9051 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9052 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9053
9054 return err;
9055
9056 default:
9057 /* do nothing */
9058 break;
9059 }
9060 return -EOPNOTSUPP;
9061}
9062
9063#if TG3_VLAN_TAG_USED
9064static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9065{
9066 struct tg3 *tp = netdev_priv(dev);
9067
29315e87
MC		 9068 if (netif_running(dev))
9069 tg3_netif_stop(tp);
9070
f47c11ee 9071 tg3_full_lock(tp, 0);
1da177e4
LT		 9072
9073 tp->vlgrp = grp;
9074
9075 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9076 __tg3_set_rx_mode(dev);
9077
f47c11ee 9078 tg3_full_unlock(tp);
29315e87
MC		 9079
9080 if (netif_running(dev))
9081 tg3_netif_start(tp);
1da177e4
LT		 9082}
9083
9084static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9085{
9086 struct tg3 *tp = netdev_priv(dev);
9087
29315e87
MC		 9088 if (netif_running(dev))
9089 tg3_netif_stop(tp);
9090
f47c11ee 9091 tg3_full_lock(tp, 0);
1da177e4
LT		 9092 if (tp->vlgrp)
9093 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 9094 tg3_full_unlock(tp);
29315e87
MC		 9095
9096 if (netif_running(dev))
9097 tg3_netif_start(tp);
1da177e4
LT		 9098}
9099#endif
9100
15f9850d
DM		 9101static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9102{
9103 struct tg3 *tp = netdev_priv(dev);
9104
9105 memcpy(ec, &tp->coal, sizeof(*ec));
9106 return 0;
9107}
9108
d244c892
MC		 9109static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9110{
9111 struct tg3 *tp = netdev_priv(dev);
9112 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9113 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9114
9115 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9116 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9117 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9118 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9119 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9120 }
9121
9122 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9123 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9124 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9125 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9126 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9127 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9128 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9129 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9130 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9131 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9132 return -EINVAL;
9133
9134 /* No rx interrupts will be generated if both are zero */
9135 if ((ec->rx_coalesce_usecs == 0) &&
9136 (ec->rx_max_coalesced_frames == 0))
9137 return -EINVAL;
9138
9139 /* No tx interrupts will be generated if both are zero */
9140 if ((ec->tx_coalesce_usecs == 0) &&
9141 (ec->tx_max_coalesced_frames == 0))
9142 return -EINVAL;
9143
9144 /* Only copy relevant parameters, ignore all others. */
9145 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9146 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9147 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9148 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9149 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9150 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9151 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9152 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9153 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9154
9155 if (netif_running(dev)) {
9156 tg3_full_lock(tp, 0);
9157 __tg3_set_coalesce(tp, &tp->coal);
9158 tg3_full_unlock(tp);
9159 }
9160 return 0;
9161}
9162
7282d491 9163static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9164 .get_settings = tg3_get_settings,
9165 .set_settings = tg3_set_settings,
9166 .get_drvinfo = tg3_get_drvinfo,
9167 .get_regs_len = tg3_get_regs_len,
9168 .get_regs = tg3_get_regs,
9169 .get_wol = tg3_get_wol,
9170 .set_wol = tg3_set_wol,
9171 .get_msglevel = tg3_get_msglevel,
9172 .set_msglevel = tg3_set_msglevel,
9173 .nway_reset = tg3_nway_reset,
9174 .get_link = ethtool_op_get_link,
9175 .get_eeprom_len = tg3_get_eeprom_len,
9176 .get_eeprom = tg3_get_eeprom,
9177 .set_eeprom = tg3_set_eeprom,
9178 .get_ringparam = tg3_get_ringparam,
9179 .set_ringparam = tg3_set_ringparam,
9180 .get_pauseparam = tg3_get_pauseparam,
9181 .set_pauseparam = tg3_set_pauseparam,
9182 .get_rx_csum = tg3_get_rx_csum,
9183 .set_rx_csum = tg3_set_rx_csum,
9184 .get_tx_csum = ethtool_op_get_tx_csum,
9185 .set_tx_csum = tg3_set_tx_csum,
9186 .get_sg = ethtool_op_get_sg,
9187 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 9188 .get_tso = ethtool_op_get_tso,
9189 .set_tso = tg3_set_tso,
4cafd3f5
MC		 9190 .self_test_count = tg3_get_test_count,
9191 .self_test = tg3_self_test,
1da177e4 9192 .get_strings = tg3_get_strings,
4009a93d 9193 .phys_id = tg3_phys_id,
1da177e4
LT		 9194 .get_stats_count = tg3_get_stats_count,
9195 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9196 .get_coalesce = tg3_get_coalesce,
d244c892 9197 .set_coalesce = tg3_set_coalesce,
2ff43697 9198 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 9199};
9200
9201static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9202{
1b27777a 9203 u32 cursize, val, magic;
1da177e4
LT		 9204
9205 tp->nvram_size = EEPROM_CHIP_SIZE;
9206
1820180b 9207 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9208 return;
9209
b16250e3
MC		 9210 if ((magic != TG3_EEPROM_MAGIC) &&
9211 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9212 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9213 return;
9214
9215 /*
9216 * Size the chip by reading offsets at increasing powers of two.
9217 * When we encounter our validation signature, we know the addressing
9218 * has wrapped around, and thus have our chip size.
9219 */
1b27777a 9220 cursize = 0x10;
1da177e4
LT		 9221
9222 while (cursize < tp->nvram_size) {
1820180b 9223 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9224 return;
9225
1820180b 9226 if (val == magic)
1da177e4
LT		 9227 break;
9228
9229 cursize <<= 1;
9230 }
9231
9232 tp->nvram_size = cursize;
9233}
6aa20a22 9234
1da177e4
LT		 9235static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9236{
9237 u32 val;
9238
1820180b 9239 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9240 return;
9241
9242 /* Selfboot format */
1820180b 9243 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9244 tg3_get_eeprom_size(tp);
9245 return;
9246 }
9247
1da177e4
LT		 9248 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9249 if (val != 0) {
9250 tp->nvram_size = (val >> 16) * 1024;
9251 return;
9252 }
9253 }
9254 tp->nvram_size = 0x20000;
9255}
9256
9257static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9258{
9259 u32 nvcfg1;
9260
9261 nvcfg1 = tr32(NVRAM_CFG1);
9262 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9263 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9264 }
9265 else {
9266 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9267 tw32(NVRAM_CFG1, nvcfg1);
9268 }
9269
4c987487 9270 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9271 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9272 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9273 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9274 tp->nvram_jedecnum = JEDEC_ATMEL;
9275 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9276 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9277 break;
9278 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9279 tp->nvram_jedecnum = JEDEC_ATMEL;
9280 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9281 break;
9282 case FLASH_VENDOR_ATMEL_EEPROM:
9283 tp->nvram_jedecnum = JEDEC_ATMEL;
9284 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9285 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9286 break;
9287 case FLASH_VENDOR_ST:
9288 tp->nvram_jedecnum = JEDEC_ST;
9289 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9290 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9291 break;
9292 case FLASH_VENDOR_SAIFUN:
9293 tp->nvram_jedecnum = JEDEC_SAIFUN;
9294 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9295 break;
9296 case FLASH_VENDOR_SST_SMALL:
9297 case FLASH_VENDOR_SST_LARGE:
9298 tp->nvram_jedecnum = JEDEC_SST;
9299 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9300 break;
9301 }
9302 }
9303 else {
9304 tp->nvram_jedecnum = JEDEC_ATMEL;
9305 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9306 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9307 }
9308}
9309
361b4ac2
MC		 9310static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9311{
9312 u32 nvcfg1;
9313
9314 nvcfg1 = tr32(NVRAM_CFG1);
9315
e6af301b
MC		 9316 /* NVRAM protection for TPM */
9317 if (nvcfg1 & (1 << 27))
9318 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9319
361b4ac2
MC		 9320 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9321 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9322 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9323 tp->nvram_jedecnum = JEDEC_ATMEL;
9324 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9325 break;
9326 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9327 tp->nvram_jedecnum = JEDEC_ATMEL;
9328 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9329 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9330 break;
9331 case FLASH_5752VENDOR_ST_M45PE10:
9332 case FLASH_5752VENDOR_ST_M45PE20:
9333 case FLASH_5752VENDOR_ST_M45PE40:
9334 tp->nvram_jedecnum = JEDEC_ST;
9335 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9336 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9337 break;
9338 }
9339
9340 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9341 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9342 case FLASH_5752PAGE_SIZE_256:
9343 tp->nvram_pagesize = 256;
9344 break;
9345 case FLASH_5752PAGE_SIZE_512:
9346 tp->nvram_pagesize = 512;
9347 break;
9348 case FLASH_5752PAGE_SIZE_1K:
9349 tp->nvram_pagesize = 1024;
9350 break;
9351 case FLASH_5752PAGE_SIZE_2K:
9352 tp->nvram_pagesize = 2048;
9353 break;
9354 case FLASH_5752PAGE_SIZE_4K:
9355 tp->nvram_pagesize = 4096;
9356 break;
9357 case FLASH_5752PAGE_SIZE_264:
9358 tp->nvram_pagesize = 264;
9359 break;
9360 }
9361 }
9362 else {
9363 /* For eeprom, set pagesize to maximum eeprom size */
9364 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9365
9366 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9367 tw32(NVRAM_CFG1, nvcfg1);
9368 }
9369}
9370
d3c7b886
MC		 9371static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9372{
9373 u32 nvcfg1;
9374
9375 nvcfg1 = tr32(NVRAM_CFG1);
9376
9377 /* NVRAM protection for TPM */
9378 if (nvcfg1 & (1 << 27))
9379 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9380
9381 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9382 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9383 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9384 tp->nvram_jedecnum = JEDEC_ATMEL;
9385 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9386 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9387
9388 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9389 tw32(NVRAM_CFG1, nvcfg1);
9390 break;
9391 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9392 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9393 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9394 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9395 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9396 tp->nvram_jedecnum = JEDEC_ATMEL;
9397 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9398 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9399 tp->nvram_pagesize = 264;
9400 break;
9401 case FLASH_5752VENDOR_ST_M45PE10:
9402 case FLASH_5752VENDOR_ST_M45PE20:
9403 case FLASH_5752VENDOR_ST_M45PE40:
9404 tp->nvram_jedecnum = JEDEC_ST;
9405 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9406 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9407 tp->nvram_pagesize = 256;
9408 break;
9409 }
9410}
9411
1b27777a
MC		 9412static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9413{
9414 u32 nvcfg1;
9415
9416 nvcfg1 = tr32(NVRAM_CFG1);
9417
9418 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9419 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9420 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9421 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9422 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9423 tp->nvram_jedecnum = JEDEC_ATMEL;
9424 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9425 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9426
9427 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9428 tw32(NVRAM_CFG1, nvcfg1);
9429 break;
9430 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9431 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9432 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9433 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9434 tp->nvram_jedecnum = JEDEC_ATMEL;
9435 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9436 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9437 tp->nvram_pagesize = 264;
9438 break;
9439 case FLASH_5752VENDOR_ST_M45PE10:
9440 case FLASH_5752VENDOR_ST_M45PE20:
9441 case FLASH_5752VENDOR_ST_M45PE40:
9442 tp->nvram_jedecnum = JEDEC_ST;
9443 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9444 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9445 tp->nvram_pagesize = 256;
9446 break;
9447 }
9448}
9449
b5d3772c
MC		 9450static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9451{
9452 tp->nvram_jedecnum = JEDEC_ATMEL;
9453 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9454 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9455}
9456
1da177e4
LT		 9457/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9458static void __devinit tg3_nvram_init(struct tg3 *tp)
9459{
1da177e4
LT		 9460 tw32_f(GRC_EEPROM_ADDR,
9461 (EEPROM_ADDR_FSM_RESET |
9462 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9463 EEPROM_ADDR_CLKPERD_SHIFT)));
9464
9d57f01c 9465 msleep(1);
1da177e4
LT		 9466
9467 /* Enable seeprom accesses. */
9468 tw32_f(GRC_LOCAL_CTRL,
9469 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9470 udelay(100);
9471
9472 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9473 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9474 tp->tg3_flags |= TG3_FLAG_NVRAM;
9475
ec41c7df
MC		 9476 if (tg3_nvram_lock(tp)) {
9477 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9478 "tg3_nvram_init failed.\n", tp->dev->name);
9479 return;
9480 }
e6af301b 9481 tg3_enable_nvram_access(tp);
1da177e4 9482
361b4ac2
MC		 9483 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9484 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 9485 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9486 tg3_get_5755_nvram_info(tp);
1b27777a
MC		 9487 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9488 tg3_get_5787_nvram_info(tp);
b5d3772c
MC		 9489 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9490 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 9491 else
9492 tg3_get_nvram_info(tp);
9493
1da177e4
LT		 9494 tg3_get_nvram_size(tp);
9495
e6af301b 9496 tg3_disable_nvram_access(tp);
381291b7 9497 tg3_nvram_unlock(tp);
1da177e4
LT		 9498
9499 } else {
9500 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9501
9502 tg3_get_eeprom_size(tp);
9503 }
9504}
9505
9506static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9507 u32 offset, u32 *val)
9508{
9509 u32 tmp;
9510 int i;
9511
9512 if (offset > EEPROM_ADDR_ADDR_MASK ||
9513 (offset % 4) != 0)
9514 return -EINVAL;
9515
9516 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9517 EEPROM_ADDR_DEVID_MASK |
9518 EEPROM_ADDR_READ);
9519 tw32(GRC_EEPROM_ADDR,
9520 tmp |
9521 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9522 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9523 EEPROM_ADDR_ADDR_MASK) |
9524 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9525
9d57f01c 9526 for (i = 0; i < 1000; i++) {
1da177e4
LT		 9527 tmp = tr32(GRC_EEPROM_ADDR);
9528
9529 if (tmp & EEPROM_ADDR_COMPLETE)
9530 break;
9d57f01c 9531 msleep(1);
1da177e4
LT		 9532 }
9533 if (!(tmp & EEPROM_ADDR_COMPLETE))
9534 return -EBUSY;
9535
9536 *val = tr32(GRC_EEPROM_DATA);
9537 return 0;
9538}
9539
9540#define NVRAM_CMD_TIMEOUT 10000
9541
9542static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9543{
9544 int i;
9545
9546 tw32(NVRAM_CMD, nvram_cmd);
9547 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9548 udelay(10);
9549 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9550 udelay(10);
9551 break;
9552 }
9553 }
9554 if (i == NVRAM_CMD_TIMEOUT) {
9555 return -EBUSY;
9556 }
9557 return 0;
9558}
9559
1820180b
MC		 9560static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9561{
9562 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9563 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9564 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9565 (tp->nvram_jedecnum == JEDEC_ATMEL))
9566
9567 addr = ((addr / tp->nvram_pagesize) <<
9568 ATMEL_AT45DB0X1B_PAGE_POS) +
9569 (addr % tp->nvram_pagesize);
9570
9571 return addr;
9572}
9573
c4e6575c
MC		 9574static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9575{
9576 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9577 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9578 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9579 (tp->nvram_jedecnum == JEDEC_ATMEL))
9580
9581 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9582 tp->nvram_pagesize) +
9583 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9584
9585 return addr;
9586}
9587
1da177e4
LT		 9588static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9589{
9590 int ret;
9591
1da177e4
LT		 9592 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9593 return tg3_nvram_read_using_eeprom(tp, offset, val);
9594
1820180b 9595 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9596
9597 if (offset > NVRAM_ADDR_MSK)
9598 return -EINVAL;
9599
ec41c7df
MC		 9600 ret = tg3_nvram_lock(tp);
9601 if (ret)
9602 return ret;
1da177e4 9603
e6af301b 9604 tg3_enable_nvram_access(tp);
1da177e4
LT		 9605
9606 tw32(NVRAM_ADDR, offset);
9607 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9608 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9609
9610 if (ret == 0)
9611 *val = swab32(tr32(NVRAM_RDDATA));
9612
e6af301b 9613 tg3_disable_nvram_access(tp);
1da177e4 9614
381291b7
MC		 9615 tg3_nvram_unlock(tp);
9616
1da177e4
LT		 9617 return ret;
9618}
9619
1820180b
MC		 9620static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9621{
9622 int err;
9623 u32 tmp;
9624
9625 err = tg3_nvram_read(tp, offset, &tmp);
9626 *val = swab32(tmp);
9627 return err;
9628}
9629
1da177e4
LT		 9630static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9631 u32 offset, u32 len, u8 *buf)
9632{
9633 int i, j, rc = 0;
9634 u32 val;
9635
9636 for (i = 0; i < len; i += 4) {
9637 u32 addr, data;
9638
9639 addr = offset + i;
9640
9641 memcpy(&data, buf + i, 4);
9642
9643 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9644
9645 val = tr32(GRC_EEPROM_ADDR);
9646 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9647
9648 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9649 EEPROM_ADDR_READ);
9650 tw32(GRC_EEPROM_ADDR, val |
9651 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9652 (addr & EEPROM_ADDR_ADDR_MASK) |
9653 EEPROM_ADDR_START |
9654 EEPROM_ADDR_WRITE);
6aa20a22 9655
9d57f01c 9656 for (j = 0; j < 1000; j++) {
1da177e4
LT		 9657 val = tr32(GRC_EEPROM_ADDR);
9658
9659 if (val & EEPROM_ADDR_COMPLETE)
9660 break;
9d57f01c 9661 msleep(1);
1da177e4
LT		 9662 }
9663 if (!(val & EEPROM_ADDR_COMPLETE)) {
9664 rc = -EBUSY;
9665 break;
9666 }
9667 }
9668
9669 return rc;
9670}
9671
9672/* offset and length are dword aligned */
9673static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9674 u8 *buf)
9675{
9676 int ret = 0;
9677 u32 pagesize = tp->nvram_pagesize;
9678 u32 pagemask = pagesize - 1;
9679 u32 nvram_cmd;
9680 u8 *tmp;
9681
9682 tmp = kmalloc(pagesize, GFP_KERNEL);
9683 if (tmp == NULL)
9684 return -ENOMEM;
9685
9686 while (len) {
9687 int j;
e6af301b 9688 u32 phy_addr, page_off, size;
1da177e4
LT		 9689
9690 phy_addr = offset & ~pagemask;
6aa20a22 9691
1da177e4
LT		 9692 for (j = 0; j < pagesize; j += 4) {
9693 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9694 (u32 *) (tmp + j))))
9695 break;
9696 }
9697 if (ret)
9698 break;
9699
9700 page_off = offset & pagemask;
9701 size = pagesize;
9702 if (len < size)
9703 size = len;
9704
9705 len -= size;
9706
9707 memcpy(tmp + page_off, buf, size);
9708
9709 offset = offset + (pagesize - page_off);
9710
e6af301b 9711 tg3_enable_nvram_access(tp);
1da177e4
LT		 9712
9713 /*
9714 * Before we can erase the flash page, we need
9715 * to issue a special "write enable" command.
9716 */
9717 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9718
9719 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9720 break;
9721
9722 /* Erase the target page */
9723 tw32(NVRAM_ADDR, phy_addr);
9724
9725 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9726 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9727
9728 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9729 break;
9730
9731 /* Issue another write enable to start the write. */
9732 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9733
9734 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9735 break;
9736
9737 for (j = 0; j < pagesize; j += 4) {
9738 u32 data;
9739
9740 data = *((u32 *) (tmp + j));
9741 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9742
9743 tw32(NVRAM_ADDR, phy_addr + j);
9744
9745 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9746 NVRAM_CMD_WR;
9747
9748 if (j == 0)
9749 nvram_cmd |= NVRAM_CMD_FIRST;
9750 else if (j == (pagesize - 4))
9751 nvram_cmd |= NVRAM_CMD_LAST;
9752
9753 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9754 break;
9755 }
9756 if (ret)
9757 break;
9758 }
9759
9760 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9761 tg3_nvram_exec_cmd(tp, nvram_cmd);
9762
9763 kfree(tmp);
9764
9765 return ret;
9766}
9767
9768/* offset and length are dword aligned */
9769static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9770 u8 *buf)
9771{
9772 int i, ret = 0;
9773
9774 for (i = 0; i < len; i += 4, offset += 4) {
9775 u32 data, page_off, phy_addr, nvram_cmd;
9776
9777 memcpy(&data, buf + i, 4);
9778 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9779
9780 page_off = offset % tp->nvram_pagesize;
9781
1820180b 9782 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9783
9784 tw32(NVRAM_ADDR, phy_addr);
9785
9786 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9787
9788 if ((page_off == 0) || (i == 0))
9789 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 9790 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 9791 nvram_cmd |= NVRAM_CMD_LAST;
9792
9793 if (i == (len - 4))
9794 nvram_cmd |= NVRAM_CMD_LAST;
9795
4c987487 9796 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 9797 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 9798 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
4c987487
MC		 9799 (tp->nvram_jedecnum == JEDEC_ST) &&
9800 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 9801
9802 if ((ret = tg3_nvram_exec_cmd(tp,
9803 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9804 NVRAM_CMD_DONE)))
9805
9806 break;
9807 }
9808 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9809 /* We always do complete word writes to eeprom. */
9810 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9811 }
9812
9813 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9814 break;
9815 }
9816 return ret;
9817}
9818
9819/* offset and length are dword aligned */
9820static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9821{
9822 int ret;
9823
1da177e4 9824 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 9825 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9826 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 9827 udelay(40);
9828 }
9829
9830 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9831 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9832 }
9833 else {
9834 u32 grc_mode;
9835
ec41c7df
MC		 9836 ret = tg3_nvram_lock(tp);
9837 if (ret)
9838 return ret;
1da177e4 9839
e6af301b
MC		 9840 tg3_enable_nvram_access(tp);
9841 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9842 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 9843 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 9844
9845 grc_mode = tr32(GRC_MODE);
9846 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9847
9848 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9849 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9850
9851 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9852 buf);
9853 }
9854 else {
9855 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9856 buf);
9857 }
9858
9859 grc_mode = tr32(GRC_MODE);
9860 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9861
e6af301b 9862 tg3_disable_nvram_access(tp);
1da177e4
LT		 9863 tg3_nvram_unlock(tp);
9864 }
9865
9866 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 9867 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 9868 udelay(40);
9869 }
9870
9871 return ret;
9872}
9873
9874struct subsys_tbl_ent {
9875 u16 subsys_vendor, subsys_devid;
9876 u32 phy_id;
9877};
9878
9879static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9880 /* Broadcom boards. */
9881 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9882 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9883 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9884 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9885 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9886 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9887 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9888 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9889 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9890 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9891 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9892
9893 /* 3com boards. */
9894 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9895 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9896 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9897 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9898 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9899
9900 /* DELL boards. */
9901 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9902 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9903 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9904 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9905
9906 /* Compaq boards. */
9907 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9908 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9909 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9910 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9911 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9912
9913 /* IBM boards. */
9914 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9915};
9916
9917static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9918{
9919 int i;
9920
9921 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9922 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9923 tp->pdev->subsystem_vendor) &&
9924 (subsys_id_to_phy_id[i].subsys_devid ==
9925 tp->pdev->subsystem_device))
9926 return &subsys_id_to_phy_id[i];
9927 }
9928 return NULL;
9929}
9930
7d0c41ef 9931static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9932{
1da177e4 9933 u32 val;
caf636c7
MC		 9934 u16 pmcsr;
9935
9936 /* On some early chips the SRAM cannot be accessed in D3hot state,
9937 * so need make sure we're in D0.
9938 */
9939 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9940 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9941 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9942 msleep(1);
7d0c41ef
MC		 9943
9944 /* Make sure register accesses (indirect or otherwise)
9945 * will function correctly.
9946 */
9947 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9948 tp->misc_host_ctrl);
1da177e4 9949
f49639e6
DM		 9950 /* The memory arbiter has to be enabled in order for SRAM accesses
9951 * to succeed. Normally on powerup the tg3 chip firmware will make
9952 * sure it is enabled, but other entities such as system netboot
9953 * code might disable it.
9954 */
9955 val = tr32(MEMARB_MODE);
9956 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9957
1da177e4 9958 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 9959 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9960
f49639e6
DM		 9961 /* Assume an onboard device by default. */
9962 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
72b845e0 9963
b5d3772c 9964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 9965 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 9966 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 9967 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9968 }
b5d3772c
MC		 9969 return;
9970 }
9971
1da177e4
LT		 9972 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9973 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9974 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 9975 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9976 int eeprom_phy_serdes = 0;
1da177e4
LT		 9977
9978 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9979 tp->nic_sram_data_cfg = nic_cfg;
9980
9981 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9982 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9983 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9984 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9985 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9986 (ver > 0) && (ver < 0x100))
9987 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9988
1da177e4
LT		 9989 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9990 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9991 eeprom_phy_serdes = 1;
9992
9993 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9994 if (nic_phy_id != 0) {
9995 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9996 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9997
9998 eeprom_phy_id = (id1 >> 16) << 10;
9999 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10000 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10001 } else
10002 eeprom_phy_id = 0;
10003
7d0c41ef 10004 tp->phy_id = eeprom_phy_id;
747e8f8b 10005 if (eeprom_phy_serdes) {
a4e2b347 10006 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10007 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10008 else
10009 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10010 }
7d0c41ef 10011
cbf46853 10012 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10013 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10014 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10015 else
1da177e4
LT		 10016 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10017
10018 switch (led_cfg) {
10019 default:
10020 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10021 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10022 break;
10023
10024 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10025 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10026 break;
10027
10028 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10029 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10030
10031 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10032 * read on some older 5700/5701 bootcode.
10033 */
10034 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10035 ASIC_REV_5700 ||
10036 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10037 ASIC_REV_5701)
10038 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10039
1da177e4
LT		 10040 break;
10041
10042 case SHASTA_EXT_LED_SHARED:
10043 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10044 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10045 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10046 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10047 LED_CTRL_MODE_PHY_2);
10048 break;
10049
10050 case SHASTA_EXT_LED_MAC:
10051 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10052 break;
10053
10054 case SHASTA_EXT_LED_COMBO:
10055 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10056 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10057 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10058 LED_CTRL_MODE_PHY_2);
10059 break;
10060
10061 };
10062
10063 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10065 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10066 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10067
9d26e213 10068 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10069 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10070 if ((tp->pdev->subsystem_vendor ==
10071 PCI_VENDOR_ID_ARIMA) &&
10072 (tp->pdev->subsystem_device == 0x205a ||
10073 tp->pdev->subsystem_device == 0x2063))
10074 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10075 } else {
f49639e6 10076 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10077 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10078 }
1da177e4
LT		 10079
10080 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10081 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10082 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10083 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10084 }
10085 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10086 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10087
10088 if (cfg2 & (1 << 17))
10089 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10090
10091 /* serdes signal pre-emphasis in register 0x590 set by */
10092 /* bootcode if bit 18 is set */
10093 if (cfg2 & (1 << 18))
10094 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10095 }
7d0c41ef
MC		 10096}
10097
10098static int __devinit tg3_phy_probe(struct tg3 *tp)
10099{
10100 u32 hw_phy_id_1, hw_phy_id_2;
10101 u32 hw_phy_id, hw_phy_id_masked;
10102 int err;
1da177e4
LT		 10103
10104 /* Reading the PHY ID register can conflict with ASF
10105 * firwmare access to the PHY hardware.
10106 */
10107 err = 0;
10108 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10109 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10110 } else {
10111 /* Now read the physical PHY_ID from the chip and verify
10112 * that it is sane. If it doesn't look good, we fall back
10113 * to either the hard-coded table based PHY_ID and failing
10114 * that the value found in the eeprom area.
10115 */
10116 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10117 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10118
10119 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10120 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10121 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10122
10123 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10124 }
10125
10126 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10127 tp->phy_id = hw_phy_id;
10128 if (hw_phy_id_masked == PHY_ID_BCM8002)
10129 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10130 else
10131 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10132 } else {
7d0c41ef
MC		 10133 if (tp->phy_id != PHY_ID_INVALID) {
10134 /* Do nothing, phy ID already set up in
10135 * tg3_get_eeprom_hw_cfg().
10136 */
1da177e4
LT		 10137 } else {
10138 struct subsys_tbl_ent *p;
10139
10140 /* No eeprom signature? Try the hardcoded
10141 * subsys device table.
10142 */
10143 p = lookup_by_subsys(tp);
10144 if (!p)
10145 return -ENODEV;
10146
10147 tp->phy_id = p->phy_id;
10148 if (!tp->phy_id ||
10149 tp->phy_id == PHY_ID_BCM8002)
10150 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10151 }
10152 }
10153
747e8f8b 10154 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4 10155 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10156 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10157
10158 tg3_readphy(tp, MII_BMSR, &bmsr);
10159 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10160 (bmsr & BMSR_LSTATUS))
10161 goto skip_phy_reset;
6aa20a22 10162
1da177e4
LT		 10163 err = tg3_phy_reset(tp);
10164 if (err)
10165 return err;
10166
10167 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10168 ADVERTISE_100HALF | ADVERTISE_100FULL |
10169 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10170 tg3_ctrl = 0;
10171 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10172 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10173 MII_TG3_CTRL_ADV_1000_FULL);
10174 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10175 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10176 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10177 MII_TG3_CTRL_ENABLE_AS_MASTER);
10178 }
10179
3600d918
MC		 10180 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10181 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10182 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10183 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10184 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10185
10186 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10187 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10188
10189 tg3_writephy(tp, MII_BMCR,
10190 BMCR_ANENABLE | BMCR_ANRESTART);
10191 }
10192 tg3_phy_set_wirespeed(tp);
10193
10194 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10195 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10196 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10197 }
10198
10199skip_phy_reset:
10200 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10201 err = tg3_init_5401phy_dsp(tp);
10202 if (err)
10203 return err;
10204 }
10205
10206 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10207 err = tg3_init_5401phy_dsp(tp);
10208 }
10209
747e8f8b 10210 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10211 tp->link_config.advertising =
10212 (ADVERTISED_1000baseT_Half |
10213 ADVERTISED_1000baseT_Full |
10214 ADVERTISED_Autoneg |
10215 ADVERTISED_FIBRE);
10216 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10217 tp->link_config.advertising &=
10218 ~(ADVERTISED_1000baseT_Half |
10219 ADVERTISED_1000baseT_Full);
10220
10221 return err;
10222}
10223
10224static void __devinit tg3_read_partno(struct tg3 *tp)
10225{
10226 unsigned char vpd_data[256];
af2c6a4a 10227 unsigned int i;
1b27777a 10228 u32 magic;
1da177e4 10229
1820180b 10230 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10231 goto out_not_found;
1da177e4 10232
1820180b 10233 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10234 for (i = 0; i < 256; i += 4) {
10235 u32 tmp;
1da177e4 10236
1b27777a
MC		 10237 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10238 goto out_not_found;
10239
10240 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10241 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10242 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10243 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10244 }
10245 } else {
10246 int vpd_cap;
10247
10248 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10249 for (i = 0; i < 256; i += 4) {
10250 u32 tmp, j = 0;
10251 u16 tmp16;
10252
10253 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10254 i);
10255 while (j++ < 100) {
10256 pci_read_config_word(tp->pdev, vpd_cap +
10257 PCI_VPD_ADDR, &tmp16);
10258 if (tmp16 & 0x8000)
10259 break;
10260 msleep(1);
10261 }
f49639e6
DM		 10262 if (!(tmp16 & 0x8000))
10263 goto out_not_found;
10264
1b27777a
MC		 10265 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10266 &tmp);
10267 tmp = cpu_to_le32(tmp);
10268 memcpy(&vpd_data[i], &tmp, 4);
10269 }
1da177e4
LT		 10270 }
10271
10272 /* Now parse and find the part number. */
af2c6a4a 10273 for (i = 0; i < 254; ) {
1da177e4 10274 unsigned char val = vpd_data[i];
af2c6a4a 10275 unsigned int block_end;
1da177e4
LT		 10276
10277 if (val == 0x82 || val == 0x91) {
10278 i = (i + 3 +
10279 (vpd_data[i + 1] +
10280 (vpd_data[i + 2] << 8)));
10281 continue;
10282 }
10283
10284 if (val != 0x90)
10285 goto out_not_found;
10286
10287 block_end = (i + 3 +
10288 (vpd_data[i + 1] +
10289 (vpd_data[i + 2] << 8)));
10290 i += 3;
af2c6a4a
MC		 10291
10292 if (block_end > 256)
10293 goto out_not_found;
10294
10295 while (i < (block_end - 2)) {
1da177e4
LT		 10296 if (vpd_data[i + 0] == 'P' &&
10297 vpd_data[i + 1] == 'N') {
10298 int partno_len = vpd_data[i + 2];
10299
af2c6a4a
MC		 10300 i += 3;
10301 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10302 goto out_not_found;
10303
10304 memcpy(tp->board_part_number,
af2c6a4a 10305 &vpd_data[i], partno_len);
1da177e4
LT		 10306
10307 /* Success. */
10308 return;
10309 }
af2c6a4a 10310 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10311 }
10312
10313 /* Part number not found. */
10314 goto out_not_found;
10315 }
10316
10317out_not_found:
b5d3772c
MC		 10318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10319 strcpy(tp->board_part_number, "BCM95906");
10320 else
10321 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10322}
10323
c4e6575c
MC		 10324static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10325{
10326 u32 val, offset, start;
10327
10328 if (tg3_nvram_read_swab(tp, 0, &val))
10329 return;
10330
10331 if (val != TG3_EEPROM_MAGIC)
10332 return;
10333
10334 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10335 tg3_nvram_read_swab(tp, 0x4, &start))
10336 return;
10337
10338 offset = tg3_nvram_logical_addr(tp, offset);
10339 if (tg3_nvram_read_swab(tp, offset, &val))
10340 return;
10341
10342 if ((val & 0xfc000000) == 0x0c000000) {
10343 u32 ver_offset, addr;
10344 int i;
10345
10346 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10347 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10348 return;
10349
10350 if (val != 0)
10351 return;
10352
10353 addr = offset + ver_offset - start;
10354 for (i = 0; i < 16; i += 4) {
10355 if (tg3_nvram_read(tp, addr + i, &val))
10356 return;
10357
10358 val = cpu_to_le32(val);
10359 memcpy(tp->fw_ver + i, &val, 4);
10360 }
10361 }
10362}
10363
1da177e4
LT		 10364static int __devinit tg3_get_invariants(struct tg3 *tp)
10365{
10366 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 10367 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10368 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 10369 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10370 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 10371 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10372 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 10373 { },
10374 };
10375 u32 misc_ctrl_reg;
10376 u32 cacheline_sz_reg;
10377 u32 pci_state_reg, grc_misc_cfg;
10378 u32 val;
10379 u16 pci_cmd;
c7835a77 10380 int err, pcie_cap;
1da177e4 10381
1da177e4
LT		 10382 /* Force memory write invalidate off. If we leave it on,
10383 * then on 5700_BX chips we have to enable a workaround.
10384 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10385 * to match the cacheline size. The Broadcom driver have this
10386 * workaround but turns MWI off all the times so never uses
10387 * it. This seems to suggest that the workaround is insufficient.
10388 */
10389 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10390 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10391 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10392
10393 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10394 * has the register indirect write enable bit set before
10395 * we try to access any of the MMIO registers. It is also
10396 * critical that the PCI-X hw workaround situation is decided
10397 * before that as well.
10398 */
10399 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10400 &misc_ctrl_reg);
10401
10402 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10403 MISC_HOST_CTRL_CHIPREV_SHIFT);
10404
ff645bec
MC		 10405 /* Wrong chip ID in 5752 A0. This code can be removed later
10406 * as A0 is not in production.
10407 */
10408 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10409 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10410
6892914f
MC		 10411 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10412 * we need to disable memory and use config. cycles
10413 * only to access all registers. The 5702/03 chips
10414 * can mistakenly decode the special cycles from the
10415 * ICH chipsets as memory write cycles, causing corruption
10416 * of register and memory space. Only certain ICH bridges
10417 * will drive special cycles with non-zero data during the
10418 * address phase which can fall within the 5703's address
10419 * range. This is not an ICH bug as the PCI spec allows
10420 * non-zero address during special cycles. However, only
10421 * these ICH bridges are known to drive non-zero addresses
10422 * during special cycles.
10423 *
10424 * Since special cycles do not cross PCI bridges, we only
10425 * enable this workaround if the 5703 is on the secondary
10426 * bus of these ICH bridges.
10427 */
10428 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10429 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10430 static struct tg3_dev_id {
10431 u32 vendor;
10432 u32 device;
10433 u32 rev;
10434 } ich_chipsets[] = {
10435 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10436 PCI_ANY_ID },
10437 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10438 PCI_ANY_ID },
10439 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10440 0xa },
10441 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10442 PCI_ANY_ID },
10443 { },
10444 };
10445 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10446 struct pci_dev *bridge = NULL;
10447
10448 while (pci_id->vendor != 0) {
10449 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10450 bridge);
10451 if (!bridge) {
10452 pci_id++;
10453 continue;
10454 }
10455 if (pci_id->rev != PCI_ANY_ID) {
10456 u8 rev;
10457
10458 pci_read_config_byte(bridge, PCI_REVISION_ID,
10459 &rev);
10460 if (rev > pci_id->rev)
10461 continue;
10462 }
10463 if (bridge->subordinate &&
10464 (bridge->subordinate->number ==
10465 tp->pdev->bus->number)) {
10466
10467 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10468 pci_dev_put(bridge);
10469 break;
10470 }
10471 }
10472 }
10473
4a29cc2e
MC		 10474 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10475 * DMA addresses > 40-bit. This bridge may have other additional
10476 * 57xx devices behind it in some 4-port NIC designs for example.
10477 * Any tg3 device found behind the bridge will also need the 40-bit
10478 * DMA workaround.
10479 */
a4e2b347
MC		 10480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10482 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 10483 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 10484 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 10485 }
4a29cc2e
MC		 10486 else {
10487 struct pci_dev *bridge = NULL;
10488
10489 do {
10490 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10491 PCI_DEVICE_ID_SERVERWORKS_EPB,
10492 bridge);
10493 if (bridge && bridge->subordinate &&
10494 (bridge->subordinate->number <=
10495 tp->pdev->bus->number) &&
10496 (bridge->subordinate->subordinate >=
10497 tp->pdev->bus->number)) {
10498 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10499 pci_dev_put(bridge);
10500 break;
10501 }
10502 } while (bridge);
10503 }
4cf78e4f 10504
1da177e4
LT		 10505 /* Initialize misc host control in PCI block. */
10506 tp->misc_host_ctrl |= (misc_ctrl_reg &
10507 MISC_HOST_CTRL_CHIPREV);
10508 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10509 tp->misc_host_ctrl);
10510
10511 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10512 &cacheline_sz_reg);
10513
10514 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10515 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10516 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10517 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10518
6708e5cc 10519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 10520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 10521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 10522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
b5d3772c 10523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 10524 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 10525 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10526
1b440c56
JL		 10527 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10528 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10529 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10530
5a6f3074 10531 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
af36e6b6 10532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 10535 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 10536 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83
MC		 10537 } else {
10538 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10539 TG3_FLG2_HW_TSO_1_BUG;
10540 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10541 ASIC_REV_5750 &&
10542 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10543 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10544 }
5a6f3074 10545 }
1da177e4 10546
0f893dc6
MC		 10547 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10548 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 10549 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 10550 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c
MC		 10551 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10552 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 10553 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10554
c7835a77
MC		 10555 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10556 if (pcie_cap != 0) {
1da177e4 10557 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 10558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10559 u16 lnkctl;
10560
10561 pci_read_config_word(tp->pdev,
10562 pcie_cap + PCI_EXP_LNKCTL,
10563 &lnkctl);
10564 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10565 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10566 }
10567 }
1da177e4 10568
399de50b
MC		 10569 /* If we have an AMD 762 or VIA K8T800 chipset, write
10570 * reordering to the mailbox registers done by the host
10571 * controller can cause major troubles. We read back from
10572 * every mailbox register write to force the writes to be
10573 * posted to the chip in order.
10574 */
10575 if (pci_dev_present(write_reorder_chipsets) &&
10576 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10577 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10578
1da177e4
LT		 10579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10580 tp->pci_lat_timer < 64) {
10581 tp->pci_lat_timer = 64;
10582
10583 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10584 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10585 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10586 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10587
10588 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10589 cacheline_sz_reg);
10590 }
10591
10592 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10593 &pci_state_reg);
10594
10595 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10596 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10597
10598 /* If this is a 5700 BX chipset, and we are in PCI-X
10599 * mode, enable register write workaround.
10600 *
10601 * The workaround is to use indirect register accesses
10602 * for all chip writes not to mailbox registers.
10603 */
10604 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10605 u32 pm_reg;
10606 u16 pci_cmd;
10607
10608 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10609
10610 /* The chip can have it's power management PCI config
10611 * space registers clobbered due to this bug.
10612 * So explicitly force the chip into D0 here.
10613 */
10614 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10615 &pm_reg);
10616 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10617 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10618 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10619 pm_reg);
10620
10621 /* Also, force SERR#/PERR# in PCI command. */
10622 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10623 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10624 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10625 }
10626 }
10627
087fe256
MC		 10628 /* 5700 BX chips need to have their TX producer index mailboxes
10629 * written twice to workaround a bug.
10630 */
10631 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10632 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10633
1da177e4
LT		 10634 /* Back to back register writes can cause problems on this chip,
10635 * the workaround is to read back all reg writes except those to
10636 * mailbox regs. See tg3_write_indirect_reg32().
10637 *
10638 * PCI Express 5750_A0 rev chips need this workaround too.
10639 */
10640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10641 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10642 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10643 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10644
10645 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10646 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10647 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10648 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10649
10650 /* Chip-specific fixup from Broadcom driver */
10651 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10652 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10653 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10654 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10655 }
10656
1ee582d8 10657 /* Default fast path register access methods */
20094930 10658 tp->read32 = tg3_read32;
1ee582d8 10659 tp->write32 = tg3_write32;
09ee929c 10660 tp->read32_mbox = tg3_read32;
20094930 10661 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 10662 tp->write32_tx_mbox = tg3_write32;
10663 tp->write32_rx_mbox = tg3_write32;
10664
10665 /* Various workaround register access methods */
10666 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10667 tp->write32 = tg3_write_indirect_reg32;
10668 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10669 tp->write32 = tg3_write_flush_reg32;
10670
10671 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10672 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10673 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10674 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10675 tp->write32_rx_mbox = tg3_write_flush_reg32;
10676 }
20094930 10677
6892914f
MC		 10678 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10679 tp->read32 = tg3_read_indirect_reg32;
10680 tp->write32 = tg3_write_indirect_reg32;
10681 tp->read32_mbox = tg3_read_indirect_mbox;
10682 tp->write32_mbox = tg3_write_indirect_mbox;
10683 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10684 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10685
10686 iounmap(tp->regs);
22abe310 10687 tp->regs = NULL;
6892914f
MC		 10688
10689 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10690 pci_cmd &= ~PCI_COMMAND_MEMORY;
10691 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10692 }
b5d3772c
MC		 10693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10694 tp->read32_mbox = tg3_read32_mbox_5906;
10695 tp->write32_mbox = tg3_write32_mbox_5906;
10696 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10697 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10698 }
6892914f 10699
bbadf503
MC		 10700 if (tp->write32 == tg3_write_indirect_reg32 ||
10701 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10702 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 10703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 10704 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10705
7d0c41ef 10706 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 10707 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 10708 * determined before calling tg3_set_power_state() so that
10709 * we know whether or not to switch out of Vaux power.
10710 * When the flag is set, it means that GPIO1 is used for eeprom
10711 * write protect and also implies that it is a LOM where GPIOs
10712 * are not used to switch power.
6aa20a22 10713 */
7d0c41ef
MC		 10714 tg3_get_eeprom_hw_cfg(tp);
10715
314fba34
MC		 10716 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10717 * GPIO1 driven high will bring 5700's external PHY out of reset.
10718 * It is also used as eeprom write protect on LOMs.
10719 */
10720 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10721 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10722 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10723 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10724 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 10725 /* Unused GPIO3 must be driven as output on 5752 because there
10726 * are no pull-up resistors on unused GPIO pins.
10727 */
10728 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10729 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 10730
af36e6b6
MC		 10731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10732 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10733
1da177e4 10734 /* Force the chip into D0. */
bc1c7567 10735 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 10736 if (err) {
10737 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10738 pci_name(tp->pdev));
10739 return err;
10740 }
10741
10742 /* 5700 B0 chips do not support checksumming correctly due
10743 * to hardware bugs.
10744 */
10745 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10746 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10747
1da177e4
LT		 10748 /* Derive initial jumbo mode from MTU assigned in
10749 * ether_setup() via the alloc_etherdev() call
10750 */
0f893dc6 10751 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 10752 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 10753 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 10754
10755 /* Determine WakeOnLan speed to use. */
10756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10757 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10758 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10760 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10761 } else {
10762 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10763 }
10764
10765 /* A few boards don't want Ethernet@WireSpeed phy feature */
10766 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10767 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10768 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 10769 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 10770 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 10771 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 10772 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10773
10774 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10775 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10776 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10777 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10778 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10779
c424cb24
MC		 10780 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10781 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
c1d2a196 10782 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
d4011ada
MC		 10783 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10784 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10785 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 10786 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10787 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10788 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 10789 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10790 }
1da177e4 10791
1da177e4 10792 tp->coalesce_mode = 0;
1da177e4
LT		 10793 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10794 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10795 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10796
10797 /* Initialize MAC MI mode, polling disabled. */
10798 tw32_f(MAC_MI_MODE, tp->mi_mode);
10799 udelay(80);
10800
10801 /* Initialize data/descriptor byte/word swapping. */
10802 val = tr32(GRC_MODE);
10803 val &= GRC_MODE_HOST_STACKUP;
10804 tw32(GRC_MODE, val | tp->grc_mode);
10805
10806 tg3_switch_clocks(tp);
10807
10808 /* Clear this out for sanity. */
10809 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10810
10811 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10812 &pci_state_reg);
10813 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10814 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10815 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10816
10817 if (chiprevid == CHIPREV_ID_5701_A0 ||
10818 chiprevid == CHIPREV_ID_5701_B0 ||
10819 chiprevid == CHIPREV_ID_5701_B2 ||
10820 chiprevid == CHIPREV_ID_5701_B5) {
10821 void __iomem *sram_base;
10822
10823 /* Write some dummy words into the SRAM status block
10824 * area, see if it reads back correctly. If the return
10825 * value is bad, force enable the PCIX workaround.
10826 */
10827 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10828
10829 writel(0x00000000, sram_base);
10830 writel(0x00000000, sram_base + 4);
10831 writel(0xffffffff, sram_base + 4);
10832 if (readl(sram_base) != 0x00000000)
10833 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10834 }
10835 }
10836
10837 udelay(50);
10838 tg3_nvram_init(tp);
10839
10840 grc_misc_cfg = tr32(GRC_MISC_CFG);
10841 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10842
10843 /* Broadcom's driver says that CIOBE multisplit has a bug */
10844#if 0
10845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10846 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10847 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10848 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10849 }
10850#endif
10851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10852 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10853 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10854 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10855
fac9b83e
DM		 10856 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10857 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10858 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10859 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10860 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10861 HOSTCC_MODE_CLRTICK_TXBD);
10862
10863 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10864 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10865 tp->misc_host_ctrl);
10866 }
10867
1da177e4
LT		 10868 /* these are limited to 10/100 only */
10869 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10870 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10871 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10872 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10873 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10874 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10875 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10876 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10877 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 10878 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10879 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 10880 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 10881 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10882
10883 err = tg3_phy_probe(tp);
10884 if (err) {
10885 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10886 pci_name(tp->pdev), err);
10887 /* ... but do not return immediately ... */
10888 }
10889
10890 tg3_read_partno(tp);
c4e6575c 10891 tg3_read_fw_ver(tp);
1da177e4
LT		 10892
10893 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10894 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10895 } else {
10896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10897 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10898 else
10899 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10900 }
10901
10902 /* 5700 {AX,BX} chips have a broken status block link
10903 * change bit implementation, so we must use the
10904 * status register in those cases.
10905 */
10906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10907 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10908 else
10909 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10910
10911 /* The led_ctrl is set during tg3_phy_probe, here we might
10912 * have to force the link status polling mechanism based
10913 * upon subsystem IDs.
10914 */
10915 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10916 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10917 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10918 TG3_FLAG_USE_LINKCHG_REG);
10919 }
10920
10921 /* For all SERDES we poll the MAC status register. */
10922 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10923 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10924 else
10925 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10926
5a6f3074 10927 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 10928 * straddle the 4GB address boundary in some cases.
10929 */
af36e6b6 10930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 10933 tp->dev->hard_start_xmit = tg3_start_xmit;
10934 else
10935 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 10936
10937 tp->rx_offset = 2;
10938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10939 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10940 tp->rx_offset = 0;
10941
f92905de
MC		 10942 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10943
10944 /* Increment the rx prod index on the rx std ring by at most
10945 * 8 for these chips to workaround hw errata.
10946 */
10947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10950 tp->rx_std_max_post = 8;
10951
1da177e4
LT		 10952 /* By default, disable wake-on-lan. User can change this
10953 * using ETHTOOL_SWOL.
10954 */
10955 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10956
10957 return err;
10958}
10959
10960#ifdef CONFIG_SPARC64
10961static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10962{
10963 struct net_device *dev = tp->dev;
10964 struct pci_dev *pdev = tp->pdev;
10965 struct pcidev_cookie *pcp = pdev->sysdata;
10966
10967 if (pcp != NULL) {
de8d28b1
DM		 10968 unsigned char *addr;
10969 int len;
1da177e4 10970
de8d28b1
DM		 10971 addr = of_get_property(pcp->prom_node, "local-mac-address",
10972 &len);
10973 if (addr && len == 6) {
10974 memcpy(dev->dev_addr, addr, 6);
2ff43697 10975 memcpy(dev->perm_addr, dev->dev_addr, 6);
1da177e4
LT		 10976 return 0;
10977 }
10978 }
10979 return -ENODEV;
10980}
10981
10982static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10983{
10984 struct net_device *dev = tp->dev;
10985
10986 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 10987 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 10988 return 0;
10989}
10990#endif
10991
10992static int __devinit tg3_get_device_address(struct tg3 *tp)
10993{
10994 struct net_device *dev = tp->dev;
10995 u32 hi, lo, mac_offset;
008652b3 10996 int addr_ok = 0;
1da177e4
LT		 10997
10998#ifdef CONFIG_SPARC64
10999 if (!tg3_get_macaddr_sparc(tp))
11000 return 0;
11001#endif
11002
11003 mac_offset = 0x7c;
f49639e6 11004 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11005 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11006 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11007 mac_offset = 0xcc;
11008 if (tg3_nvram_lock(tp))
11009 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11010 else
11011 tg3_nvram_unlock(tp);
11012 }
b5d3772c
MC		 11013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11014 mac_offset = 0x10;
1da177e4
LT		 11015
11016 /* First try to get it from MAC address mailbox. */
11017 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11018 if ((hi >> 16) == 0x484b) {
11019 dev->dev_addr[0] = (hi >> 8) & 0xff;
11020 dev->dev_addr[1] = (hi >> 0) & 0xff;
11021
11022 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11023 dev->dev_addr[2] = (lo >> 24) & 0xff;
11024 dev->dev_addr[3] = (lo >> 16) & 0xff;
11025 dev->dev_addr[4] = (lo >> 8) & 0xff;
11026 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11027
008652b3
MC		 11028 /* Some old bootcode may report a 0 MAC address in SRAM */
11029 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11030 }
11031 if (!addr_ok) {
11032 /* Next, try NVRAM. */
f49639e6 11033 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11034 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11035 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11036 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11037 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11038 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11039 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11040 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11041 }
11042 /* Finally just fetch it out of the MAC control regs. */
11043 else {
11044 hi = tr32(MAC_ADDR_0_HIGH);
11045 lo = tr32(MAC_ADDR_0_LOW);
11046
11047 dev->dev_addr[5] = lo & 0xff;
11048 dev->dev_addr[4] = (lo >> 8) & 0xff;
11049 dev->dev_addr[3] = (lo >> 16) & 0xff;
11050 dev->dev_addr[2] = (lo >> 24) & 0xff;
11051 dev->dev_addr[1] = hi & 0xff;
11052 dev->dev_addr[0] = (hi >> 8) & 0xff;
11053 }
1da177e4
LT		 11054 }
11055
11056 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11057#ifdef CONFIG_SPARC64
11058 if (!tg3_get_default_macaddr_sparc(tp))
11059 return 0;
11060#endif
11061 return -EINVAL;
11062 }
2ff43697 11063 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11064 return 0;
11065}
11066
59e6b434
DM		 11067#define BOUNDARY_SINGLE_CACHELINE 1
11068#define BOUNDARY_MULTI_CACHELINE 2
11069
11070static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11071{
11072 int cacheline_size;
11073 u8 byte;
11074 int goal;
11075
11076 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11077 if (byte == 0)
11078 cacheline_size = 1024;
11079 else
11080 cacheline_size = (int) byte * 4;
11081
11082 /* On 5703 and later chips, the boundary bits have no
11083 * effect.
11084 */
11085 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11086 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11087 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11088 goto out;
11089
11090#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11091 goal = BOUNDARY_MULTI_CACHELINE;
11092#else
11093#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11094 goal = BOUNDARY_SINGLE_CACHELINE;
11095#else
11096 goal = 0;
11097#endif
11098#endif
11099
11100 if (!goal)
11101 goto out;
11102
11103 /* PCI controllers on most RISC systems tend to disconnect
11104 * when a device tries to burst across a cache-line boundary.
11105 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11106 *
11107 * Unfortunately, for PCI-E there are only limited
11108 * write-side controls for this, and thus for reads
11109 * we will still get the disconnects. We'll also waste
11110 * these PCI cycles for both read and write for chips
11111 * other than 5700 and 5701 which do not implement the
11112 * boundary bits.
11113 */
11114 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11115 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11116 switch (cacheline_size) {
11117 case 16:
11118 case 32:
11119 case 64:
11120 case 128:
11121 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11122 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11123 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11124 } else {
11125 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11126 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11127 }
11128 break;
11129
11130 case 256:
11131 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11132 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11133 break;
11134
11135 default:
11136 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11137 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11138 break;
11139 };
11140 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11141 switch (cacheline_size) {
11142 case 16:
11143 case 32:
11144 case 64:
11145 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11146 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11147 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11148 break;
11149 }
11150 /* fallthrough */
11151 case 128:
11152 default:
11153 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11154 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11155 break;
11156 };
11157 } else {
11158 switch (cacheline_size) {
11159 case 16:
11160 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11161 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11162 DMA_RWCTRL_WRITE_BNDRY_16);
11163 break;
11164 }
11165 /* fallthrough */
11166 case 32:
11167 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11168 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11169 DMA_RWCTRL_WRITE_BNDRY_32);
11170 break;
11171 }
11172 /* fallthrough */
11173 case 64:
11174 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11175 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11176 DMA_RWCTRL_WRITE_BNDRY_64);
11177 break;
11178 }
11179 /* fallthrough */
11180 case 128:
11181 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11182 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11183 DMA_RWCTRL_WRITE_BNDRY_128);
11184 break;
11185 }
11186 /* fallthrough */
11187 case 256:
11188 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11189 DMA_RWCTRL_WRITE_BNDRY_256);
11190 break;
11191 case 512:
11192 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11193 DMA_RWCTRL_WRITE_BNDRY_512);
11194 break;
11195 case 1024:
11196 default:
11197 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11198 DMA_RWCTRL_WRITE_BNDRY_1024);
11199 break;
11200 };
11201 }
11202
11203out:
11204 return val;
11205}
11206
1da177e4
LT		 11207static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11208{
11209 struct tg3_internal_buffer_desc test_desc;
11210 u32 sram_dma_descs;
11211 int i, ret;
11212
11213 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11214
11215 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11216 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11217 tw32(RDMAC_STATUS, 0);
11218 tw32(WDMAC_STATUS, 0);
11219
11220 tw32(BUFMGR_MODE, 0);
11221 tw32(FTQ_RESET, 0);
11222
11223 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11224 test_desc.addr_lo = buf_dma & 0xffffffff;
11225 test_desc.nic_mbuf = 0x00002100;
11226 test_desc.len = size;
11227
11228 /*
11229 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11230 * the *second* time the tg3 driver was getting loaded after an
11231 * initial scan.
11232 *
11233 * Broadcom tells me:
11234 * ...the DMA engine is connected to the GRC block and a DMA
11235 * reset may affect the GRC block in some unpredictable way...
11236 * The behavior of resets to individual blocks has not been tested.
11237 *
11238 * Broadcom noted the GRC reset will also reset all sub-components.
11239 */
11240 if (to_device) {
11241 test_desc.cqid_sqid = (13 << 8) | 2;
11242
11243 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11244 udelay(40);
11245 } else {
11246 test_desc.cqid_sqid = (16 << 8) | 7;
11247
11248 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11249 udelay(40);
11250 }
11251 test_desc.flags = 0x00000005;
11252
11253 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11254 u32 val;
11255
11256 val = *(((u32 *)&test_desc) + i);
11257 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11258 sram_dma_descs + (i * sizeof(u32)));
11259 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11260 }
11261 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11262
11263 if (to_device) {
11264 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11265 } else {
11266 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11267 }
11268
11269 ret = -ENODEV;
11270 for (i = 0; i < 40; i++) {
11271 u32 val;
11272
11273 if (to_device)
11274 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11275 else
11276 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11277 if ((val & 0xffff) == sram_dma_descs) {
11278 ret = 0;
11279 break;
11280 }
11281
11282 udelay(100);
11283 }
11284
11285 return ret;
11286}
11287
ded7340d 11288#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11289
11290static int __devinit tg3_test_dma(struct tg3 *tp)
11291{
11292 dma_addr_t buf_dma;
59e6b434 11293 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11294 int ret;
11295
11296 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11297 if (!buf) {
11298 ret = -ENOMEM;
11299 goto out_nofree;
11300 }
11301
11302 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11303 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11304
59e6b434 11305 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11306
11307 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11308 /* DMA read watermark not used on PCIE */
11309 tp->dma_rwctrl |= 0x00180000;
11310 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11311 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11313 tp->dma_rwctrl |= 0x003f0000;
11314 else
11315 tp->dma_rwctrl |= 0x003f000f;
11316 } else {
11317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11319 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11320 u32 read_water = 0x7;
1da177e4 11321
4a29cc2e
MC		 11322 /* If the 5704 is behind the EPB bridge, we can
11323 * do the less restrictive ONE_DMA workaround for
11324 * better performance.
11325 */
11326 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11327 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11328 tp->dma_rwctrl |= 0x8000;
11329 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 11330 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11331
49afdeb6
MC		 11332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11333 read_water = 4;
59e6b434 11334 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 11335 tp->dma_rwctrl |=
11336 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11337 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11338 (1 << 23);
4cf78e4f
MC		 11339 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11340 /* 5780 always in PCIX mode */
11341 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 11342 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11343 /* 5714 always in PCIX mode */
11344 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 11345 } else {
11346 tp->dma_rwctrl |= 0x001b000f;
11347 }
11348 }
11349
11350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11352 tp->dma_rwctrl &= 0xfffffff0;
11353
11354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11355 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11356 /* Remove this if it causes problems for some boards. */
11357 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11358
11359 /* On 5700/5701 chips, we need to set this bit.
11360 * Otherwise the chip will issue cacheline transactions
11361 * to streamable DMA memory with not all the byte
11362 * enables turned on. This is an error on several
11363 * RISC PCI controllers, in particular sparc64.
11364 *
11365 * On 5703/5704 chips, this bit has been reassigned
11366 * a different meaning. In particular, it is used
11367 * on those chips to enable a PCI-X workaround.
11368 */
11369 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11370 }
11371
11372 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11373
11374#if 0
11375 /* Unneeded, already done by tg3_get_invariants. */
11376 tg3_switch_clocks(tp);
11377#endif
11378
11379 ret = 0;
11380 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11381 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11382 goto out;
11383
59e6b434
DM		 11384 /* It is best to perform DMA test with maximum write burst size
11385 * to expose the 5700/5701 write DMA bug.
11386 */
11387 saved_dma_rwctrl = tp->dma_rwctrl;
11388 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11389 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11390
1da177e4
LT		 11391 while (1) {
11392 u32 *p = buf, i;
11393
11394 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11395 p[i] = i;
11396
11397 /* Send the buffer to the chip. */
11398 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11399 if (ret) {
11400 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11401 break;
11402 }
11403
11404#if 0
11405 /* validate data reached card RAM correctly. */
11406 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11407 u32 val;
11408 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11409 if (le32_to_cpu(val) != p[i]) {
11410 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11411 /* ret = -ENODEV here? */
11412 }
11413 p[i] = 0;
11414 }
11415#endif
11416 /* Now read it back. */
11417 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11418 if (ret) {
11419 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11420
11421 break;
11422 }
11423
11424 /* Verify it. */
11425 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11426 if (p[i] == i)
11427 continue;
11428
59e6b434
DM		 11429 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11430 DMA_RWCTRL_WRITE_BNDRY_16) {
11431 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 11432 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11433 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11434 break;
11435 } else {
11436 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11437 ret = -ENODEV;
11438 goto out;
11439 }
11440 }
11441
11442 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11443 /* Success. */
11444 ret = 0;
11445 break;
11446 }
11447 }
59e6b434
DM		 11448 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11449 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 11450 static struct pci_device_id dma_wait_state_chipsets[] = {
11451 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11452 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11453 { },
11454 };
11455
59e6b434 11456 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 11457 * now look for chipsets that are known to expose the
11458 * DMA bug without failing the test.
59e6b434 11459 */
6d1cfbab
MC		 11460 if (pci_dev_present(dma_wait_state_chipsets)) {
11461 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11462 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11463 }
11464 else
11465 /* Safe to use the calculated DMA boundary. */
11466 tp->dma_rwctrl = saved_dma_rwctrl;
11467
59e6b434
DM		 11468 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11469 }
1da177e4
LT		 11470
11471out:
11472 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11473out_nofree:
11474 return ret;
11475}
11476
11477static void __devinit tg3_init_link_config(struct tg3 *tp)
11478{
11479 tp->link_config.advertising =
11480 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11481 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11482 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11483 ADVERTISED_Autoneg | ADVERTISED_MII);
11484 tp->link_config.speed = SPEED_INVALID;
11485 tp->link_config.duplex = DUPLEX_INVALID;
11486 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 11487 tp->link_config.active_speed = SPEED_INVALID;
11488 tp->link_config.active_duplex = DUPLEX_INVALID;
11489 tp->link_config.phy_is_low_power = 0;
11490 tp->link_config.orig_speed = SPEED_INVALID;
11491 tp->link_config.orig_duplex = DUPLEX_INVALID;
11492 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11493}
11494
11495static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11496{
fdfec172
MC		 11497 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11498 tp->bufmgr_config.mbuf_read_dma_low_water =
11499 DEFAULT_MB_RDMA_LOW_WATER_5705;
11500 tp->bufmgr_config.mbuf_mac_rx_low_water =
11501 DEFAULT_MB_MACRX_LOW_WATER_5705;
11502 tp->bufmgr_config.mbuf_high_water =
11503 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 11504 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11505 tp->bufmgr_config.mbuf_mac_rx_low_water =
11506 DEFAULT_MB_MACRX_LOW_WATER_5906;
11507 tp->bufmgr_config.mbuf_high_water =
11508 DEFAULT_MB_HIGH_WATER_5906;
11509 }
fdfec172
MC		 11510
11511 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11512 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11513 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11514 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11515 tp->bufmgr_config.mbuf_high_water_jumbo =
11516 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11517 } else {
11518 tp->bufmgr_config.mbuf_read_dma_low_water =
11519 DEFAULT_MB_RDMA_LOW_WATER;
11520 tp->bufmgr_config.mbuf_mac_rx_low_water =
11521 DEFAULT_MB_MACRX_LOW_WATER;
11522 tp->bufmgr_config.mbuf_high_water =
11523 DEFAULT_MB_HIGH_WATER;
11524
11525 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11526 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11527 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11528 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11529 tp->bufmgr_config.mbuf_high_water_jumbo =
11530 DEFAULT_MB_HIGH_WATER_JUMBO;
11531 }
1da177e4
LT		 11532
11533 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11534 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11535}
11536
11537static char * __devinit tg3_phy_string(struct tg3 *tp)
11538{
11539 switch (tp->phy_id & PHY_ID_MASK) {
11540 case PHY_ID_BCM5400: return "5400";
11541 case PHY_ID_BCM5401: return "5401";
11542 case PHY_ID_BCM5411: return "5411";
11543 case PHY_ID_BCM5701: return "5701";
11544 case PHY_ID_BCM5703: return "5703";
11545 case PHY_ID_BCM5704: return "5704";
11546 case PHY_ID_BCM5705: return "5705";
11547 case PHY_ID_BCM5750: return "5750";
85e94ced 11548 case PHY_ID_BCM5752: return "5752";
a4e2b347 11549 case PHY_ID_BCM5714: return "5714";
4cf78e4f 11550 case PHY_ID_BCM5780: return "5780";
af36e6b6 11551 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 11552 case PHY_ID_BCM5787: return "5787";
126a3368 11553 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 11554 case PHY_ID_BCM5906: return "5906";
1da177e4
LT		 11555 case PHY_ID_BCM8002: return "8002/serdes";
11556 case 0: return "serdes";
11557 default: return "unknown";
11558 };
11559}
11560
f9804ddb
MC		 11561static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11562{
11563 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11564 strcpy(str, "PCI Express");
11565 return str;
11566 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11567 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11568
11569 strcpy(str, "PCIX:");
11570
11571 if ((clock_ctrl == 7) ||
11572 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11573 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11574 strcat(str, "133MHz");
11575 else if (clock_ctrl == 0)
11576 strcat(str, "33MHz");
11577 else if (clock_ctrl == 2)
11578 strcat(str, "50MHz");
11579 else if (clock_ctrl == 4)
11580 strcat(str, "66MHz");
11581 else if (clock_ctrl == 6)
11582 strcat(str, "100MHz");
f9804ddb
MC		 11583 } else {
11584 strcpy(str, "PCI:");
11585 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11586 strcat(str, "66MHz");
11587 else
11588 strcat(str, "33MHz");
11589 }
11590 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11591 strcat(str, ":32-bit");
11592 else
11593 strcat(str, ":64-bit");
11594 return str;
11595}
11596
8c2dc7e1 11597static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 11598{
11599 struct pci_dev *peer;
11600 unsigned int func, devnr = tp->pdev->devfn & ~7;
11601
11602 for (func = 0; func < 8; func++) {
11603 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11604 if (peer && peer != tp->pdev)
11605 break;
11606 pci_dev_put(peer);
11607 }
16fe9d74
MC		 11608 /* 5704 can be configured in single-port mode, set peer to
11609 * tp->pdev in that case.
11610 */
11611 if (!peer) {
11612 peer = tp->pdev;
11613 return peer;
11614 }
1da177e4
LT		 11615
11616 /*
11617 * We don't need to keep the refcount elevated; there's no way
11618 * to remove one half of this device without removing the other
11619 */
11620 pci_dev_put(peer);
11621
11622 return peer;
11623}
11624
15f9850d
DM		 11625static void __devinit tg3_init_coal(struct tg3 *tp)
11626{
11627 struct ethtool_coalesce *ec = &tp->coal;
11628
11629 memset(ec, 0, sizeof(*ec));
11630 ec->cmd = ETHTOOL_GCOALESCE;
11631 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11632 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11633 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11634 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11635 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11636 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11637 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11638 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11639 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11640
11641 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11642 HOSTCC_MODE_CLRTICK_TXBD)) {
11643 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11644 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11645 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11646 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11647 }
d244c892
MC		 11648
11649 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11650 ec->rx_coalesce_usecs_irq = 0;
11651 ec->tx_coalesce_usecs_irq = 0;
11652 ec->stats_block_coalesce_usecs = 0;
11653 }
15f9850d
DM		 11654}
11655
1da177e4
LT		 11656static int __devinit tg3_init_one(struct pci_dev *pdev,
11657 const struct pci_device_id *ent)
11658{
11659 static int tg3_version_printed = 0;
11660 unsigned long tg3reg_base, tg3reg_len;
11661 struct net_device *dev;
11662 struct tg3 *tp;
72f2afb8 11663 int i, err, pm_cap;
f9804ddb 11664 char str[40];
72f2afb8 11665 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 11666
11667 if (tg3_version_printed++ == 0)
11668 printk(KERN_INFO "%s", version);
11669
11670 err = pci_enable_device(pdev);
11671 if (err) {
11672 printk(KERN_ERR PFX "Cannot enable PCI device, "
11673 "aborting.\n");
11674 return err;
11675 }
11676
11677 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11678 printk(KERN_ERR PFX "Cannot find proper PCI device "
11679 "base address, aborting.\n");
11680 err = -ENODEV;
11681 goto err_out_disable_pdev;
11682 }
11683
11684 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11685 if (err) {
11686 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11687 "aborting.\n");
11688 goto err_out_disable_pdev;
11689 }
11690
11691 pci_set_master(pdev);
11692
11693 /* Find power-management capability. */
11694 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11695 if (pm_cap == 0) {
11696 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11697 "aborting.\n");
11698 err = -EIO;
11699 goto err_out_free_res;
11700 }
11701
1da177e4
LT		 11702 tg3reg_base = pci_resource_start(pdev, 0);
11703 tg3reg_len = pci_resource_len(pdev, 0);
11704
11705 dev = alloc_etherdev(sizeof(*tp));
11706 if (!dev) {
11707 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11708 err = -ENOMEM;
11709 goto err_out_free_res;
11710 }
11711
11712 SET_MODULE_OWNER(dev);
11713 SET_NETDEV_DEV(dev, &pdev->dev);
11714
1da177e4
LT		 11715#if TG3_VLAN_TAG_USED
11716 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11717 dev->vlan_rx_register = tg3_vlan_rx_register;
11718 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11719#endif
11720
11721 tp = netdev_priv(dev);
11722 tp->pdev = pdev;
11723 tp->dev = dev;
11724 tp->pm_cap = pm_cap;
11725 tp->mac_mode = TG3_DEF_MAC_MODE;
11726 tp->rx_mode = TG3_DEF_RX_MODE;
11727 tp->tx_mode = TG3_DEF_TX_MODE;
11728 tp->mi_mode = MAC_MI_MODE_BASE;
11729 if (tg3_debug > 0)
11730 tp->msg_enable = tg3_debug;
11731 else
11732 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11733
11734 /* The word/byte swap controls here control register access byte
11735 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11736 * setting below.
11737 */
11738 tp->misc_host_ctrl =
11739 MISC_HOST_CTRL_MASK_PCI_INT |
11740 MISC_HOST_CTRL_WORD_SWAP |
11741 MISC_HOST_CTRL_INDIR_ACCESS |
11742 MISC_HOST_CTRL_PCISTATE_RW;
11743
11744 /* The NONFRM (non-frame) byte/word swap controls take effect
11745 * on descriptor entries, anything which isn't packet data.
11746 *
11747 * The StrongARM chips on the board (one for tx, one for rx)
11748 * are running in big-endian mode.
11749 */
11750 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11751 GRC_MODE_WSWAP_NONFRM_DATA);
11752#ifdef __BIG_ENDIAN
11753 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11754#endif
11755 spin_lock_init(&tp->lock);
1da177e4 11756 spin_lock_init(&tp->indirect_lock);
c4028958 11757 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 11758
11759 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11760 if (tp->regs == 0UL) {
11761 printk(KERN_ERR PFX "Cannot map device registers, "
11762 "aborting.\n");
11763 err = -ENOMEM;
11764 goto err_out_free_dev;
11765 }
11766
11767 tg3_init_link_config(tp);
11768
1da177e4
LT		 11769 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11770 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11771 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11772
11773 dev->open = tg3_open;
11774 dev->stop = tg3_close;
11775 dev->get_stats = tg3_get_stats;
11776 dev->set_multicast_list = tg3_set_rx_mode;
11777 dev->set_mac_address = tg3_set_mac_addr;
11778 dev->do_ioctl = tg3_ioctl;
11779 dev->tx_timeout = tg3_tx_timeout;
11780 dev->poll = tg3_poll;
11781 dev->ethtool_ops = &tg3_ethtool_ops;
11782 dev->weight = 64;
11783 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11784 dev->change_mtu = tg3_change_mtu;
11785 dev->irq = pdev->irq;
11786#ifdef CONFIG_NET_POLL_CONTROLLER
11787 dev->poll_controller = tg3_poll_controller;
11788#endif
11789
11790 err = tg3_get_invariants(tp);
11791 if (err) {
11792 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11793 "aborting.\n");
11794 goto err_out_iounmap;
11795 }
11796
4a29cc2e
MC		 11797 /* The EPB bridge inside 5714, 5715, and 5780 and any
11798 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 11799 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11800 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11801 * do DMA address check in tg3_start_xmit().
11802 */
4a29cc2e
MC		 11803 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11804 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11805 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 11806 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11807#ifdef CONFIG_HIGHMEM
11808 dma_mask = DMA_64BIT_MASK;
11809#endif
4a29cc2e 11810 } else
72f2afb8
MC		 11811 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11812
11813 /* Configure DMA attributes. */
11814 if (dma_mask > DMA_32BIT_MASK) {
11815 err = pci_set_dma_mask(pdev, dma_mask);
11816 if (!err) {
11817 dev->features |= NETIF_F_HIGHDMA;
11818 err = pci_set_consistent_dma_mask(pdev,
11819 persist_dma_mask);
11820 if (err < 0) {
11821 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11822 "DMA for consistent allocations\n");
11823 goto err_out_iounmap;
11824 }
11825 }
11826 }
11827 if (err || dma_mask == DMA_32BIT_MASK) {
11828 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11829 if (err) {
11830 printk(KERN_ERR PFX "No usable DMA configuration, "
11831 "aborting.\n");
11832 goto err_out_iounmap;
11833 }
11834 }
11835
fdfec172 11836 tg3_init_bufmgr_config(tp);
1da177e4 11837
1da177e4
LT		 11838 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11839 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11840 }
11841 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11843 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 11844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 11845 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11846 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11847 } else {
11848 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11849 }
11850
4e3a7aaa
MC		 11851 /* TSO is on by default on chips that support hardware TSO.
11852 * Firmware TSO on older chips gives lower performance, so it
11853 * is off by default, but can be enabled using ethtool.
11854 */
b0026624 11855 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 11856 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 11857 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11858 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624
MC		 11859 dev->features |= NETIF_F_TSO6;
11860 }
1da177e4 11861
1da177e4
LT		 11862
11863 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11864 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11865 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11866 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11867 tp->rx_pending = 63;
11868 }
11869
8c2dc7e1
MC		 11870 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11871 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11872 tp->pdev_peer = tg3_find_peer(tp);
1da177e4
LT		 11873
11874 err = tg3_get_device_address(tp);
11875 if (err) {
11876 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11877 "aborting.\n");
11878 goto err_out_iounmap;
11879 }
11880
11881 /*
11882 * Reset chip in case UNDI or EFI driver did not shutdown
11883 * DMA self test will enable WDMAC and we'll see (spurious)
11884 * pending DMA on the PCI bus at that point.
11885 */
11886 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11887 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11888 pci_save_state(tp->pdev);
11889 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 11890 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 11891 }
11892
11893 err = tg3_test_dma(tp);
11894 if (err) {
11895 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11896 goto err_out_iounmap;
11897 }
11898
11899 /* Tigon3 can do ipv4 only... and some chips have buggy
11900 * checksumming.
11901 */
11902 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
af36e6b6
MC		 11903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf
MC		 11905 dev->features |= NETIF_F_HW_CSUM;
11906 else
11907 dev->features |= NETIF_F_IP_CSUM;
11908 dev->features |= NETIF_F_SG;
1da177e4
LT		 11909 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11910 } else
11911 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11912
1da177e4
LT		 11913 /* flow control autonegotiation is default behavior */
11914 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11915
15f9850d
DM		 11916 tg3_init_coal(tp);
11917
7d3f4c97
DM		 11918 /* Now that we have fully setup the chip, save away a snapshot
11919 * of the PCI config space. We need to restore this after
11920 * GRC_MISC_CFG core clock resets and some resume events.
11921 */
11922 pci_save_state(tp->pdev);
11923
c49a1561
MC		 11924 pci_set_drvdata(pdev, dev);
11925
1da177e4
LT		 11926 err = register_netdev(dev);
11927 if (err) {
11928 printk(KERN_ERR PFX "Cannot register net device, "
11929 "aborting.\n");
11930 goto err_out_iounmap;
11931 }
11932
cbb45d21 11933 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 11934 dev->name,
11935 tp->board_part_number,
11936 tp->pci_chip_rev_id,
11937 tg3_phy_string(tp),
f9804ddb 11938 tg3_bus_string(tp, str),
cbb45d21
MC		 11939 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11940 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11941 "10/100/1000Base-T")));
1da177e4
LT		 11942
11943 for (i = 0; i < 6; i++)
11944 printk("%2.2x%c", dev->dev_addr[i],
11945 i == 5 ? '\n' : ':');
11946
11947 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11948 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11949 "TSOcap[%d] \n",
11950 dev->name,
11951 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11952 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11953 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11954 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11955 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11956 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11957 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 11958 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11959 dev->name, tp->dma_rwctrl,
11960 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11961 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 11962
11963 return 0;
11964
11965err_out_iounmap:
6892914f
MC		 11966 if (tp->regs) {
11967 iounmap(tp->regs);
22abe310 11968 tp->regs = NULL;
6892914f 11969 }
1da177e4
LT		 11970
11971err_out_free_dev:
11972 free_netdev(dev);
11973
11974err_out_free_res:
11975 pci_release_regions(pdev);
11976
11977err_out_disable_pdev:
11978 pci_disable_device(pdev);
11979 pci_set_drvdata(pdev, NULL);
11980 return err;
11981}
11982
11983static void __devexit tg3_remove_one(struct pci_dev *pdev)
11984{
11985 struct net_device *dev = pci_get_drvdata(pdev);
11986
11987 if (dev) {
11988 struct tg3 *tp = netdev_priv(dev);
11989
7faa006f 11990 flush_scheduled_work();
1da177e4 11991 unregister_netdev(dev);
6892914f
MC		 11992 if (tp->regs) {
11993 iounmap(tp->regs);
22abe310 11994 tp->regs = NULL;
6892914f 11995 }
1da177e4
LT		 11996 free_netdev(dev);
11997 pci_release_regions(pdev);
11998 pci_disable_device(pdev);
11999 pci_set_drvdata(pdev, NULL);
12000 }
12001}
12002
12003static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12004{
12005 struct net_device *dev = pci_get_drvdata(pdev);
12006 struct tg3 *tp = netdev_priv(dev);
12007 int err;
12008
12009 if (!netif_running(dev))
12010 return 0;
12011
7faa006f 12012 flush_scheduled_work();
1da177e4
LT		 12013 tg3_netif_stop(tp);
12014
12015 del_timer_sync(&tp->timer);
12016
f47c11ee 12017 tg3_full_lock(tp, 1);
1da177e4 12018 tg3_disable_ints(tp);
f47c11ee 12019 tg3_full_unlock(tp);
1da177e4
LT		 12020
12021 netif_device_detach(dev);
12022
f47c11ee 12023 tg3_full_lock(tp, 0);
944d980e 12024 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12025 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12026 tg3_full_unlock(tp);
1da177e4 12027
436f1379
MC		 12028 /* Save MSI address and data for resume. */
12029 pci_save_state(pdev);
12030
1da177e4
LT		 12031 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12032 if (err) {
f47c11ee 12033 tg3_full_lock(tp, 0);
1da177e4 12034
6a9eba15 12035 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12036 if (tg3_restart_hw(tp, 1))
12037 goto out;
1da177e4
LT		 12038
12039 tp->timer.expires = jiffies + tp->timer_offset;
12040 add_timer(&tp->timer);
12041
12042 netif_device_attach(dev);
12043 tg3_netif_start(tp);
12044
b9ec6c1b 12045out:
f47c11ee 12046 tg3_full_unlock(tp);
1da177e4
LT		 12047 }
12048
12049 return err;
12050}
12051
12052static int tg3_resume(struct pci_dev *pdev)
12053{
12054 struct net_device *dev = pci_get_drvdata(pdev);
12055 struct tg3 *tp = netdev_priv(dev);
12056 int err;
12057
12058 if (!netif_running(dev))
12059 return 0;
12060
12061 pci_restore_state(tp->pdev);
12062
bc1c7567 12063 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12064 if (err)
12065 return err;
12066
12067 netif_device_attach(dev);
12068
f47c11ee 12069 tg3_full_lock(tp, 0);
1da177e4 12070
6a9eba15 12071 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12072 err = tg3_restart_hw(tp, 1);
12073 if (err)
12074 goto out;
1da177e4
LT		 12075
12076 tp->timer.expires = jiffies + tp->timer_offset;
12077 add_timer(&tp->timer);
12078
1da177e4
LT		 12079 tg3_netif_start(tp);
12080
b9ec6c1b 12081out:
f47c11ee 12082 tg3_full_unlock(tp);
1da177e4 12083
b9ec6c1b 12084 return err;
1da177e4
LT		 12085}
12086
12087static struct pci_driver tg3_driver = {
12088 .name = DRV_MODULE_NAME,
12089 .id_table = tg3_pci_tbl,
12090 .probe = tg3_init_one,
12091 .remove = __devexit_p(tg3_remove_one),
12092 .suspend = tg3_suspend,
12093 .resume = tg3_resume
12094};
12095
12096static int __init tg3_init(void)
12097{
29917620 12098 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12099}
12100
12101static void __exit tg3_cleanup(void)
12102{
12103 pci_unregister_driver(&tg3_driver);
12104}
12105
12106module_init(tg3_init);
12107module_exit(tg3_cleanup);
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