]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[TEXTSEARCH]: Fix broken good shift array calculation in Boyer-Moore
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
18#include <linux/config.h>
19
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4
LT		 28#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/workqueue.h>
61487480 40#include <linux/prefetch.h>
f9a5f7d3 41#include <linux/dma-mapping.h>
1da177e4
LT		 42
43#include <net/checksum.h>
44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
50#ifdef CONFIG_SPARC64
51#include <asm/idprom.h>
52#include <asm/oplib.h>
53#include <asm/pbm.h>
54#endif
55
56#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57#define TG3_VLAN_TAG_USED 1
58#else
59#define TG3_VLAN_TAG_USED 0
60#endif
61
62#ifdef NETIF_F_TSO
63#define TG3_TSO_SUPPORT 1
64#else
65#define TG3_TSO_SUPPORT 0
66#endif
67
68#include "tg3.h"
69
70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": "
ec41c7df
MC		 72#define DRV_MODULE_VERSION "3.48"
73#define DRV_MODULE_RELDATE "Jan 16, 2006"
1da177e4
LT		 74
75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0
77#define TG3_DEF_TX_MODE 0
78#define TG3_DEF_MSG_ENABLE \
79 (NETIF_MSG_DRV | \
80 NETIF_MSG_PROBE | \
81 NETIF_MSG_LINK | \
82 NETIF_MSG_TIMER | \
83 NETIF_MSG_IFDOWN | \
84 NETIF_MSG_IFUP | \
85 NETIF_MSG_RX_ERR | \
86 NETIF_MSG_TX_ERR)
87
88/* length of time before we decide the hardware is borked,
89 * and dev->tx_timeout() should be called to fix the problem
90 */
91#define TG3_TX_TIMEOUT (5 * HZ)
92
93/* hardware minimum and maximum for a single frame's data payload */
94#define TG3_MIN_MTU 60
95#define TG3_MAX_MTU(tp) \
0f893dc6 96 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 97
98/* These numbers seem to be hard coded in the NIC firmware somehow.
99 * You can't change the ring sizes, but you can change where you place
100 * them in the NIC onboard memory.
101 */
102#define TG3_RX_RING_SIZE 512
103#define TG3_DEF_RX_RING_PENDING 200
104#define TG3_RX_JUMBO_RING_SIZE 256
105#define TG3_DEF_RX_JUMBO_RING_PENDING 100
106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
114 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
1da177e4 127#define TX_BUFFS_AVAIL(TP) \
51b91468
MC		 128 ((TP)->tx_pending - \
129 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
1da177e4
LT		 130#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
131
132#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
133#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
134
135/* minimum number of free TX descriptors required to wake up TX process */
136#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
137
138/* number of ETHTOOL_GSTATS u64's */
139#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
140
4cafd3f5
MC		 141#define TG3_NUM_TEST 6
142
1da177e4
LT		 143static char version[] __devinitdata =
144 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
145
146MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
147MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
148MODULE_LICENSE("GPL");
149MODULE_VERSION(DRV_MODULE_VERSION);
150
151static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
152module_param(tg3_debug, int, 0);
153MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
154
155static struct pci_device_id tg3_pci_tbl[] = {
156 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
d8659255
XVP		 216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
a4e2b347
MC		 224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
4cf78e4f
MC		 228 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 232 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
246 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
248 { 0, }
249};
250
251MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
252
253static struct {
254 const char string[ETH_GSTRING_LEN];
255} ethtool_stats_keys[TG3_NUM_STATS] = {
256 { "rx_octets" },
257 { "rx_fragments" },
258 { "rx_ucast_packets" },
259 { "rx_mcast_packets" },
260 { "rx_bcast_packets" },
261 { "rx_fcs_errors" },
262 { "rx_align_errors" },
263 { "rx_xon_pause_rcvd" },
264 { "rx_xoff_pause_rcvd" },
265 { "rx_mac_ctrl_rcvd" },
266 { "rx_xoff_entered" },
267 { "rx_frame_too_long_errors" },
268 { "rx_jabbers" },
269 { "rx_undersize_packets" },
270 { "rx_in_length_errors" },
271 { "rx_out_length_errors" },
272 { "rx_64_or_less_octet_packets" },
273 { "rx_65_to_127_octet_packets" },
274 { "rx_128_to_255_octet_packets" },
275 { "rx_256_to_511_octet_packets" },
276 { "rx_512_to_1023_octet_packets" },
277 { "rx_1024_to_1522_octet_packets" },
278 { "rx_1523_to_2047_octet_packets" },
279 { "rx_2048_to_4095_octet_packets" },
280 { "rx_4096_to_8191_octet_packets" },
281 { "rx_8192_to_9022_octet_packets" },
282
283 { "tx_octets" },
284 { "tx_collisions" },
285
286 { "tx_xon_sent" },
287 { "tx_xoff_sent" },
288 { "tx_flow_control" },
289 { "tx_mac_errors" },
290 { "tx_single_collisions" },
291 { "tx_mult_collisions" },
292 { "tx_deferred" },
293 { "tx_excessive_collisions" },
294 { "tx_late_collisions" },
295 { "tx_collide_2times" },
296 { "tx_collide_3times" },
297 { "tx_collide_4times" },
298 { "tx_collide_5times" },
299 { "tx_collide_6times" },
300 { "tx_collide_7times" },
301 { "tx_collide_8times" },
302 { "tx_collide_9times" },
303 { "tx_collide_10times" },
304 { "tx_collide_11times" },
305 { "tx_collide_12times" },
306 { "tx_collide_13times" },
307 { "tx_collide_14times" },
308 { "tx_collide_15times" },
309 { "tx_ucast_packets" },
310 { "tx_mcast_packets" },
311 { "tx_bcast_packets" },
312 { "tx_carrier_sense_errors" },
313 { "tx_discards" },
314 { "tx_errors" },
315
316 { "dma_writeq_full" },
317 { "dma_write_prioq_full" },
318 { "rxbds_empty" },
319 { "rx_discards" },
320 { "rx_errors" },
321 { "rx_threshold_hit" },
322
323 { "dma_readq_full" },
324 { "dma_read_prioq_full" },
325 { "tx_comp_queue_full" },
326
327 { "ring_set_send_prod_index" },
328 { "ring_status_update" },
329 { "nic_irqs" },
330 { "nic_avoided_irqs" },
331 { "nic_tx_threshold_hit" }
332};
333
4cafd3f5
MC		 334static struct {
335 const char string[ETH_GSTRING_LEN];
336} ethtool_test_keys[TG3_NUM_TEST] = {
337 { "nvram test (online) " },
338 { "link test (online) " },
339 { "register test (offline)" },
340 { "memory test (offline)" },
341 { "loopback test (offline)" },
342 { "interrupt test (offline)" },
343};
344
b401e9e2
MC		 345static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
346{
347 writel(val, tp->regs + off);
348}
349
350static u32 tg3_read32(struct tg3 *tp, u32 off)
351{
352 return (readl(tp->regs + off));
353}
354
1da177e4
LT		 355static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
356{
6892914f
MC		 357 unsigned long flags;
358
359 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 360 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
361 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 362 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 363}
364
365static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
366{
367 writel(val, tp->regs + off);
368 readl(tp->regs + off);
1da177e4
LT		 369}
370
6892914f 371static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 372{
6892914f
MC		 373 unsigned long flags;
374 u32 val;
375
376 spin_lock_irqsave(&tp->indirect_lock, flags);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
378 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
379 spin_unlock_irqrestore(&tp->indirect_lock, flags);
380 return val;
381}
382
383static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
384{
385 unsigned long flags;
386
387 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
388 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
389 TG3_64BIT_REG_LOW, val);
390 return;
391 }
392 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
393 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
394 TG3_64BIT_REG_LOW, val);
395 return;
1da177e4 396 }
6892914f
MC		 397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
400 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402
403 /* In indirect mode when disabling interrupts, we also need
404 * to clear the interrupt bit in the GRC local ctrl register.
405 */
406 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
407 (val == 0x1)) {
408 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
409 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
410 }
411}
412
413static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
414{
415 unsigned long flags;
416 u32 val;
417
418 spin_lock_irqsave(&tp->indirect_lock, flags);
419 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
420 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
421 spin_unlock_irqrestore(&tp->indirect_lock, flags);
422 return val;
423}
424
b401e9e2
MC		 425/* usec_wait specifies the wait time in usec when writing to certain registers
426 * where it is unsafe to read back the register without some delay.
427 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
428 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
429 */
430static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 431{
b401e9e2
MC		 432 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
433 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
434 /* Non-posted methods */
435 tp->write32(tp, off, val);
436 else {
437 /* Posted method */
438 tg3_write32(tp, off, val);
439 if (usec_wait)
440 udelay(usec_wait);
441 tp->read32(tp, off);
442 }
443 /* Wait again after the read for the posted method to guarantee that
444 * the wait time is met.
445 */
446 if (usec_wait)
447 udelay(usec_wait);
1da177e4
LT		 448}
449
09ee929c
MC		 450static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
451{
452 tp->write32_mbox(tp, off, val);
6892914f
MC		 453 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
454 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
455 tp->read32_mbox(tp, off);
09ee929c
MC		 456}
457
20094930 458static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 459{
460 void __iomem *mbox = tp->regs + off;
461 writel(val, mbox);
462 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
463 writel(val, mbox);
464 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
465 readl(mbox);
466}
467
20094930 468#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 469#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 470#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
471#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 472#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 473
474#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 475#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
476#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 477#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 478
479static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
480{
6892914f
MC		 481 unsigned long flags;
482
483 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 484 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
485 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
486
487 /* Always leave this as zero. */
488 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 489 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 490}
491
28fbef78
MC		 492static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
493{
494 /* If no workaround is needed, write to mem space directly */
495 if (tp->write32 != tg3_write_indirect_reg32)
496 tw32(NIC_SRAM_WIN_BASE + off, val);
497 else
498 tg3_write_mem(tp, off, val);
499}
500
1da177e4
LT		 501static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
502{
6892914f
MC		 503 unsigned long flags;
504
505 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508
509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 511 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 512}
513
514static void tg3_disable_ints(struct tg3 *tp)
515{
516 tw32(TG3PCI_MISC_HOST_CTRL,
517 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 518 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 519}
520
521static inline void tg3_cond_int(struct tg3 *tp)
522{
38f3843e
MC		 523 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
524 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4
LT		 525 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
526}
527
528static void tg3_enable_ints(struct tg3 *tp)
529{
bbe832c0
MC		 530 tp->irq_sync = 0;
531 wmb();
532
1da177e4
LT		 533 tw32(TG3PCI_MISC_HOST_CTRL,
534 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 535 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
536 (tp->last_tag << 24));
1da177e4
LT		 537 tg3_cond_int(tp);
538}
539
04237ddd
MC		 540static inline unsigned int tg3_has_work(struct tg3 *tp)
541{
542 struct tg3_hw_status *sblk = tp->hw_status;
543 unsigned int work_exists = 0;
544
545 /* check for phy events */
546 if (!(tp->tg3_flags &
547 (TG3_FLAG_USE_LINKCHG_REG |
548 TG3_FLAG_POLL_SERDES))) {
549 if (sblk->status & SD_STATUS_LINK_CHG)
550 work_exists = 1;
551 }
552 /* check for RX/TX work to do */
553 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
554 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
555 work_exists = 1;
556
557 return work_exists;
558}
559
1da177e4 560/* tg3_restart_ints
04237ddd
MC		 561 * similar to tg3_enable_ints, but it accurately determines whether there
562 * is new work pending and can return without flushing the PIO write
563 * which reenables interrupts
1da177e4
LT		 564 */
565static void tg3_restart_ints(struct tg3 *tp)
566{
fac9b83e
DM		 567 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
568 tp->last_tag << 24);
1da177e4
LT		 569 mmiowb();
570
fac9b83e
DM		 571 /* When doing tagged status, this work check is unnecessary.
572 * The last_tag we write above tells the chip which piece of
573 * work we've completed.
574 */
575 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
576 tg3_has_work(tp))
04237ddd
MC		 577 tw32(HOSTCC_MODE, tp->coalesce_mode |
578 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 579}
580
581static inline void tg3_netif_stop(struct tg3 *tp)
582{
bbe832c0 583 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 584 netif_poll_disable(tp->dev);
585 netif_tx_disable(tp->dev);
586}
587
588static inline void tg3_netif_start(struct tg3 *tp)
589{
590 netif_wake_queue(tp->dev);
591 /* NOTE: unconditional netif_wake_queue is only appropriate
592 * so long as all callers are assured to have free tx slots
593 * (such as after tg3_init_hw)
594 */
595 netif_poll_enable(tp->dev);
f47c11ee
DM		 596 tp->hw_status->status |= SD_STATUS_UPDATED;
597 tg3_enable_ints(tp);
1da177e4
LT		 598}
599
600static void tg3_switch_clocks(struct tg3 *tp)
601{
602 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
603 u32 orig_clock_ctrl;
604
a4e2b347 605 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 606 return;
607
1da177e4
LT		 608 orig_clock_ctrl = clock_ctrl;
609 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
610 CLOCK_CTRL_CLKRUN_OENABLE |
611 0x1f);
612 tp->pci_clock_ctrl = clock_ctrl;
613
614 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
615 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 616 tw32_wait_f(TG3PCI_CLOCK_CTRL,
617 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 618 }
619 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 620 tw32_wait_f(TG3PCI_CLOCK_CTRL,
621 clock_ctrl |
622 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
623 40);
624 tw32_wait_f(TG3PCI_CLOCK_CTRL,
625 clock_ctrl | (CLOCK_CTRL_ALTCLK),
626 40);
1da177e4 627 }
b401e9e2 628 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 629}
630
631#define PHY_BUSY_LOOPS 5000
632
633static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
634{
635 u32 frame_val;
636 unsigned int loops;
637 int ret;
638
639 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
640 tw32_f(MAC_MI_MODE,
641 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
642 udelay(80);
643 }
644
645 *val = 0x0;
646
647 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
648 MI_COM_PHY_ADDR_MASK);
649 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
650 MI_COM_REG_ADDR_MASK);
651 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
652
653 tw32_f(MAC_MI_COM, frame_val);
654
655 loops = PHY_BUSY_LOOPS;
656 while (loops != 0) {
657 udelay(10);
658 frame_val = tr32(MAC_MI_COM);
659
660 if ((frame_val & MI_COM_BUSY) == 0) {
661 udelay(5);
662 frame_val = tr32(MAC_MI_COM);
663 break;
664 }
665 loops -= 1;
666 }
667
668 ret = -EBUSY;
669 if (loops != 0) {
670 *val = frame_val & MI_COM_DATA_MASK;
671 ret = 0;
672 }
673
674 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
675 tw32_f(MAC_MI_MODE, tp->mi_mode);
676 udelay(80);
677 }
678
679 return ret;
680}
681
682static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
683{
684 u32 frame_val;
685 unsigned int loops;
686 int ret;
687
688 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
689 tw32_f(MAC_MI_MODE,
690 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
691 udelay(80);
692 }
693
694 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
695 MI_COM_PHY_ADDR_MASK);
696 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
697 MI_COM_REG_ADDR_MASK);
698 frame_val |= (val & MI_COM_DATA_MASK);
699 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
700
701 tw32_f(MAC_MI_COM, frame_val);
702
703 loops = PHY_BUSY_LOOPS;
704 while (loops != 0) {
705 udelay(10);
706 frame_val = tr32(MAC_MI_COM);
707 if ((frame_val & MI_COM_BUSY) == 0) {
708 udelay(5);
709 frame_val = tr32(MAC_MI_COM);
710 break;
711 }
712 loops -= 1;
713 }
714
715 ret = -EBUSY;
716 if (loops != 0)
717 ret = 0;
718
719 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
720 tw32_f(MAC_MI_MODE, tp->mi_mode);
721 udelay(80);
722 }
723
724 return ret;
725}
726
727static void tg3_phy_set_wirespeed(struct tg3 *tp)
728{
729 u32 val;
730
731 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
732 return;
733
734 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
735 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
736 tg3_writephy(tp, MII_TG3_AUX_CTRL,
737 (val | (1 << 15) | (1 << 4)));
738}
739
740static int tg3_bmcr_reset(struct tg3 *tp)
741{
742 u32 phy_control;
743 int limit, err;
744
745 /* OK, reset it, and poll the BMCR_RESET bit until it
746 * clears or we time out.
747 */
748 phy_control = BMCR_RESET;
749 err = tg3_writephy(tp, MII_BMCR, phy_control);
750 if (err != 0)
751 return -EBUSY;
752
753 limit = 5000;
754 while (limit--) {
755 err = tg3_readphy(tp, MII_BMCR, &phy_control);
756 if (err != 0)
757 return -EBUSY;
758
759 if ((phy_control & BMCR_RESET) == 0) {
760 udelay(40);
761 break;
762 }
763 udelay(10);
764 }
765 if (limit <= 0)
766 return -EBUSY;
767
768 return 0;
769}
770
771static int tg3_wait_macro_done(struct tg3 *tp)
772{
773 int limit = 100;
774
775 while (limit--) {
776 u32 tmp32;
777
778 if (!tg3_readphy(tp, 0x16, &tmp32)) {
779 if ((tmp32 & 0x1000) == 0)
780 break;
781 }
782 }
783 if (limit <= 0)
784 return -EBUSY;
785
786 return 0;
787}
788
789static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
790{
791 static const u32 test_pat[4][6] = {
792 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
793 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
794 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
795 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
796 };
797 int chan;
798
799 for (chan = 0; chan < 4; chan++) {
800 int i;
801
802 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
803 (chan * 0x2000) | 0x0200);
804 tg3_writephy(tp, 0x16, 0x0002);
805
806 for (i = 0; i < 6; i++)
807 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
808 test_pat[chan][i]);
809
810 tg3_writephy(tp, 0x16, 0x0202);
811 if (tg3_wait_macro_done(tp)) {
812 *resetp = 1;
813 return -EBUSY;
814 }
815
816 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
817 (chan * 0x2000) | 0x0200);
818 tg3_writephy(tp, 0x16, 0x0082);
819 if (tg3_wait_macro_done(tp)) {
820 *resetp = 1;
821 return -EBUSY;
822 }
823
824 tg3_writephy(tp, 0x16, 0x0802);
825 if (tg3_wait_macro_done(tp)) {
826 *resetp = 1;
827 return -EBUSY;
828 }
829
830 for (i = 0; i < 6; i += 2) {
831 u32 low, high;
832
833 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
834 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
835 tg3_wait_macro_done(tp)) {
836 *resetp = 1;
837 return -EBUSY;
838 }
839 low &= 0x7fff;
840 high &= 0x000f;
841 if (low != test_pat[chan][i] ||
842 high != test_pat[chan][i+1]) {
843 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
845 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
846
847 return -EBUSY;
848 }
849 }
850 }
851
852 return 0;
853}
854
855static int tg3_phy_reset_chanpat(struct tg3 *tp)
856{
857 int chan;
858
859 for (chan = 0; chan < 4; chan++) {
860 int i;
861
862 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
863 (chan * 0x2000) | 0x0200);
864 tg3_writephy(tp, 0x16, 0x0002);
865 for (i = 0; i < 6; i++)
866 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
867 tg3_writephy(tp, 0x16, 0x0202);
868 if (tg3_wait_macro_done(tp))
869 return -EBUSY;
870 }
871
872 return 0;
873}
874
875static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
876{
877 u32 reg32, phy9_orig;
878 int retries, do_phy_reset, err;
879
880 retries = 10;
881 do_phy_reset = 1;
882 do {
883 if (do_phy_reset) {
884 err = tg3_bmcr_reset(tp);
885 if (err)
886 return err;
887 do_phy_reset = 0;
888 }
889
890 /* Disable transmitter and interrupt. */
891 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
892 continue;
893
894 reg32 |= 0x3000;
895 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
896
897 /* Set full-duplex, 1000 mbps. */
898 tg3_writephy(tp, MII_BMCR,
899 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
900
901 /* Set to master mode. */
902 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
903 continue;
904
905 tg3_writephy(tp, MII_TG3_CTRL,
906 (MII_TG3_CTRL_AS_MASTER |
907 MII_TG3_CTRL_ENABLE_AS_MASTER));
908
909 /* Enable SM_DSP_CLOCK and 6dB. */
910 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
911
912 /* Block the PHY control access. */
913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
915
916 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
917 if (!err)
918 break;
919 } while (--retries);
920
921 err = tg3_phy_reset_chanpat(tp);
922 if (err)
923 return err;
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
926 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
927
928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
929 tg3_writephy(tp, 0x16, 0x0000);
930
931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
933 /* Set Extended packet length bit for jumbo frames */
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
935 }
936 else {
937 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
938 }
939
940 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
941
942 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
943 reg32 &= ~0x3000;
944 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
945 } else if (!err)
946 err = -EBUSY;
947
948 return err;
949}
950
951/* This will reset the tigon3 PHY if there is no valid
952 * link unless the FORCE argument is non-zero.
953 */
954static int tg3_phy_reset(struct tg3 *tp)
955{
956 u32 phy_status;
957 int err;
958
959 err = tg3_readphy(tp, MII_BMSR, &phy_status);
960 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
961 if (err != 0)
962 return -EBUSY;
963
964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
967 err = tg3_phy_reset_5703_4_5(tp);
968 if (err)
969 return err;
970 goto out;
971 }
972
973 err = tg3_bmcr_reset(tp);
974 if (err)
975 return err;
976
977out:
978 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
981 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
982 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
983 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
984 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
985 }
986 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
987 tg3_writephy(tp, 0x1c, 0x8d68);
988 tg3_writephy(tp, 0x1c, 0x8d68);
989 }
990 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
991 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
992 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
994 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
995 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
996 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
997 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
998 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
999 }
1000 /* Set Extended packet length bit (bit 14) on all chips that */
1001 /* support jumbo frames */
1002 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1003 /* Cannot do read-modify-write on 5401 */
1004 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1005 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1006 u32 phy_reg;
1007
1008 /* Set bit 14 with read-modify-write to preserve other bits */
1009 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1010 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1011 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1012 }
1013
1014 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1015 * jumbo frames transmission.
1016 */
0f893dc6 1017 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1018 u32 phy_reg;
1019
1020 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1021 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1022 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1023 }
1024
1025 tg3_phy_set_wirespeed(tp);
1026 return 0;
1027}
1028
1029static void tg3_frob_aux_power(struct tg3 *tp)
1030{
1031 struct tg3 *tp_peer = tp;
1032
1033 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1034 return;
1035
8c2dc7e1
MC		 1036 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1037 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1038 struct net_device *dev_peer;
1039
1040 dev_peer = pci_get_drvdata(tp->pdev_peer);
1041 if (!dev_peer)
1da177e4 1042 BUG();
8c2dc7e1 1043 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1044 }
1045
1da177e4 1046 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1047 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1048 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1049 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1052 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1053 (GRC_LCLCTRL_GPIO_OE0 |
1054 GRC_LCLCTRL_GPIO_OE1 |
1055 GRC_LCLCTRL_GPIO_OE2 |
1056 GRC_LCLCTRL_GPIO_OUTPUT0 |
1057 GRC_LCLCTRL_GPIO_OUTPUT1),
1058 100);
1da177e4
LT		 1059 } else {
1060 u32 no_gpio2;
dc56b7d4 1061 u32 grc_local_ctrl = 0;
1da177e4
LT		 1062
1063 if (tp_peer != tp &&
1064 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1065 return;
1066
dc56b7d4
MC		 1067 /* Workaround to prevent overdrawing Amps. */
1068 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1069 ASIC_REV_5714) {
1070 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1071 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1072 grc_local_ctrl, 100);
dc56b7d4
MC		 1073 }
1074
1da177e4
LT		 1075 /* On 5753 and variants, GPIO2 cannot be used. */
1076 no_gpio2 = tp->nic_sram_data_cfg &
1077 NIC_SRAM_DATA_CFG_NO_GPIO2;
1078
dc56b7d4 1079 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1080 GRC_LCLCTRL_GPIO_OE1 |
1081 GRC_LCLCTRL_GPIO_OE2 |
1082 GRC_LCLCTRL_GPIO_OUTPUT1 |
1083 GRC_LCLCTRL_GPIO_OUTPUT2;
1084 if (no_gpio2) {
1085 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1086 GRC_LCLCTRL_GPIO_OUTPUT2);
1087 }
b401e9e2
MC		 1088 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1089 grc_local_ctrl, 100);
1da177e4
LT		 1090
1091 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1092
b401e9e2
MC		 1093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094 grc_local_ctrl, 100);
1da177e4
LT		 1095
1096 if (!no_gpio2) {
1097 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1098 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1099 grc_local_ctrl, 100);
1da177e4
LT		 1100 }
1101 }
1102 } else {
1103 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1104 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
b401e9e2
MC		 1109 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1110 (GRC_LCLCTRL_GPIO_OE1 |
1111 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1112
b401e9e2
MC		 1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1115
b401e9e2
MC		 1116 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1117 (GRC_LCLCTRL_GPIO_OE1 |
1118 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1119 }
1120 }
1121}
1122
1123static int tg3_setup_phy(struct tg3 *, int);
1124
1125#define RESET_KIND_SHUTDOWN 0
1126#define RESET_KIND_INIT 1
1127#define RESET_KIND_SUSPEND 2
1128
1129static void tg3_write_sig_post_reset(struct tg3 *, int);
1130static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1131static int tg3_nvram_lock(struct tg3 *);
1132static void tg3_nvram_unlock(struct tg3 *);
1da177e4
LT		 1133
1134static int tg3_set_power_state(struct tg3 *tp, int state)
1135{
1136 u32 misc_host_ctrl;
1137 u16 power_control, power_caps;
1138 int pm = tp->pm_cap;
1139
1140 /* Make sure register accesses (indirect or otherwise)
1141 * will function correctly.
1142 */
1143 pci_write_config_dword(tp->pdev,
1144 TG3PCI_MISC_HOST_CTRL,
1145 tp->misc_host_ctrl);
1146
1147 pci_read_config_word(tp->pdev,
1148 pm + PCI_PM_CTRL,
1149 &power_control);
1150 power_control |= PCI_PM_CTRL_PME_STATUS;
1151 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1152 switch (state) {
1153 case 0:
1154 power_control |= 0;
1155 pci_write_config_word(tp->pdev,
1156 pm + PCI_PM_CTRL,
1157 power_control);
8c6bda1a
MC		 1158 udelay(100); /* Delay after power state change */
1159
1160 /* Switch out of Vaux if it is not a LOM */
b401e9e2
MC		 1161 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1162 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1163
1164 return 0;
1165
1166 case 1:
1167 power_control |= 1;
1168 break;
1169
1170 case 2:
1171 power_control |= 2;
1172 break;
1173
1174 case 3:
1175 power_control |= 3;
1176 break;
1177
1178 default:
1179 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1180 "requested.\n",
1181 tp->dev->name, state);
1182 return -EINVAL;
1183 };
1184
1185 power_control |= PCI_PM_CTRL_PME_ENABLE;
1186
1187 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1188 tw32(TG3PCI_MISC_HOST_CTRL,
1189 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1190
1191 if (tp->link_config.phy_is_low_power == 0) {
1192 tp->link_config.phy_is_low_power = 1;
1193 tp->link_config.orig_speed = tp->link_config.speed;
1194 tp->link_config.orig_duplex = tp->link_config.duplex;
1195 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1196 }
1197
747e8f8b 1198 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1199 tp->link_config.speed = SPEED_10;
1200 tp->link_config.duplex = DUPLEX_HALF;
1201 tp->link_config.autoneg = AUTONEG_ENABLE;
1202 tg3_setup_phy(tp, 0);
1203 }
1204
6921d201
MC		 1205 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1206 int i;
1207 u32 val;
1208
1209 for (i = 0; i < 200; i++) {
1210 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1211 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1212 break;
1213 msleep(1);
1214 }
1215 }
1216 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1217 WOL_DRV_STATE_SHUTDOWN |
1218 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1219
1da177e4
LT		 1220 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1221
1222 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1223 u32 mac_mode;
1224
1225 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1226 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1227 udelay(40);
1228
1229 mac_mode = MAC_MODE_PORT_MODE_MII;
1230
1231 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1232 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1233 mac_mode |= MAC_MODE_LINK_POLARITY;
1234 } else {
1235 mac_mode = MAC_MODE_PORT_MODE_TBI;
1236 }
1237
cbf46853 1238 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1239 tw32(MAC_LED_CTRL, tp->led_ctrl);
1240
1241 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1242 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1243 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1244
1245 tw32_f(MAC_MODE, mac_mode);
1246 udelay(100);
1247
1248 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1249 udelay(10);
1250 }
1251
1252 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1253 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1255 u32 base_val;
1256
1257 base_val = tp->pci_clock_ctrl;
1258 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1259 CLOCK_CTRL_TXCLK_DISABLE);
1260
b401e9e2
MC		 1261 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1262 CLOCK_CTRL_PWRDOWN_PLL133, 40);
a4e2b347 1263 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f 1264 /* do nothing */
85e94ced 1265 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1266 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1267 u32 newbits1, newbits2;
1268
1269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1271 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1272 CLOCK_CTRL_TXCLK_DISABLE |
1273 CLOCK_CTRL_ALTCLK);
1274 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1275 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1276 newbits1 = CLOCK_CTRL_625_CORE;
1277 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1278 } else {
1279 newbits1 = CLOCK_CTRL_ALTCLK;
1280 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1281 }
1282
b401e9e2
MC		 1283 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1284 40);
1da177e4 1285
b401e9e2
MC		 1286 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1287 40);
1da177e4
LT		 1288
1289 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1290 u32 newbits3;
1291
1292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1294 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1295 CLOCK_CTRL_TXCLK_DISABLE |
1296 CLOCK_CTRL_44MHZ_CORE);
1297 } else {
1298 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1299 }
1300
b401e9e2
MC		 1301 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1302 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1303 }
1304 }
1305
6921d201
MC		 1306 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1307 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1308 /* Turn off the PHY */
1309 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1310 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1311 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1312 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
dc56b7d4
MC		 1313 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
1314 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
6921d201
MC		 1315 }
1316 }
1317
1da177e4
LT		 1318 tg3_frob_aux_power(tp);
1319
1320 /* Workaround for unstable PLL clock */
1321 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1322 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1323 u32 val = tr32(0x7d00);
1324
1325 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1326 tw32(0x7d00, val);
6921d201 1327 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1328 int err;
1329
1330 err = tg3_nvram_lock(tp);
1da177e4 1331 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1332 if (!err)
1333 tg3_nvram_unlock(tp);
6921d201 1334 }
1da177e4
LT		 1335 }
1336
1337 /* Finally, set the new power state. */
1338 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1339 udelay(100); /* Delay after power state change */
1da177e4
LT		 1340
1341 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1342
1343 return 0;
1344}
1345
1346static void tg3_link_report(struct tg3 *tp)
1347{
1348 if (!netif_carrier_ok(tp->dev)) {
1349 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1350 } else {
1351 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1352 tp->dev->name,
1353 (tp->link_config.active_speed == SPEED_1000 ?
1354 1000 :
1355 (tp->link_config.active_speed == SPEED_100 ?
1356 100 : 10)),
1357 (tp->link_config.active_duplex == DUPLEX_FULL ?
1358 "full" : "half"));
1359
1360 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1361 "%s for RX.\n",
1362 tp->dev->name,
1363 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1364 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1365 }
1366}
1367
1368static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1369{
1370 u32 new_tg3_flags = 0;
1371 u32 old_rx_mode = tp->rx_mode;
1372 u32 old_tx_mode = tp->tx_mode;
1373
1374 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1375
1376 /* Convert 1000BaseX flow control bits to 1000BaseT
1377 * bits before resolving flow control.
1378 */
1379 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1380 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1381 ADVERTISE_PAUSE_ASYM);
1382 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1383
1384 if (local_adv & ADVERTISE_1000XPAUSE)
1385 local_adv |= ADVERTISE_PAUSE_CAP;
1386 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1387 local_adv |= ADVERTISE_PAUSE_ASYM;
1388 if (remote_adv & LPA_1000XPAUSE)
1389 remote_adv |= LPA_PAUSE_CAP;
1390 if (remote_adv & LPA_1000XPAUSE_ASYM)
1391 remote_adv |= LPA_PAUSE_ASYM;
1392 }
1393
1da177e4
LT		 1394 if (local_adv & ADVERTISE_PAUSE_CAP) {
1395 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1396 if (remote_adv & LPA_PAUSE_CAP)
1397 new_tg3_flags |=
1398 (TG3_FLAG_RX_PAUSE |
1399 TG3_FLAG_TX_PAUSE);
1400 else if (remote_adv & LPA_PAUSE_ASYM)
1401 new_tg3_flags |=
1402 (TG3_FLAG_RX_PAUSE);
1403 } else {
1404 if (remote_adv & LPA_PAUSE_CAP)
1405 new_tg3_flags |=
1406 (TG3_FLAG_RX_PAUSE |
1407 TG3_FLAG_TX_PAUSE);
1408 }
1409 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1410 if ((remote_adv & LPA_PAUSE_CAP) &&
1411 (remote_adv & LPA_PAUSE_ASYM))
1412 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1413 }
1414
1415 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1416 tp->tg3_flags |= new_tg3_flags;
1417 } else {
1418 new_tg3_flags = tp->tg3_flags;
1419 }
1420
1421 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1422 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1423 else
1424 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1425
1426 if (old_rx_mode != tp->rx_mode) {
1427 tw32_f(MAC_RX_MODE, tp->rx_mode);
1428 }
1429
1430 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1431 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1432 else
1433 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1434
1435 if (old_tx_mode != tp->tx_mode) {
1436 tw32_f(MAC_TX_MODE, tp->tx_mode);
1437 }
1438}
1439
1440static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1441{
1442 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1443 case MII_TG3_AUX_STAT_10HALF:
1444 *speed = SPEED_10;
1445 *duplex = DUPLEX_HALF;
1446 break;
1447
1448 case MII_TG3_AUX_STAT_10FULL:
1449 *speed = SPEED_10;
1450 *duplex = DUPLEX_FULL;
1451 break;
1452
1453 case MII_TG3_AUX_STAT_100HALF:
1454 *speed = SPEED_100;
1455 *duplex = DUPLEX_HALF;
1456 break;
1457
1458 case MII_TG3_AUX_STAT_100FULL:
1459 *speed = SPEED_100;
1460 *duplex = DUPLEX_FULL;
1461 break;
1462
1463 case MII_TG3_AUX_STAT_1000HALF:
1464 *speed = SPEED_1000;
1465 *duplex = DUPLEX_HALF;
1466 break;
1467
1468 case MII_TG3_AUX_STAT_1000FULL:
1469 *speed = SPEED_1000;
1470 *duplex = DUPLEX_FULL;
1471 break;
1472
1473 default:
1474 *speed = SPEED_INVALID;
1475 *duplex = DUPLEX_INVALID;
1476 break;
1477 };
1478}
1479
1480static void tg3_phy_copper_begin(struct tg3 *tp)
1481{
1482 u32 new_adv;
1483 int i;
1484
1485 if (tp->link_config.phy_is_low_power) {
1486 /* Entering low power mode. Disable gigabit and
1487 * 100baseT advertisements.
1488 */
1489 tg3_writephy(tp, MII_TG3_CTRL, 0);
1490
1491 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1492 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1493 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1494 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1495
1496 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1497 } else if (tp->link_config.speed == SPEED_INVALID) {
1498 tp->link_config.advertising =
1499 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1500 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1501 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1502 ADVERTISED_Autoneg | ADVERTISED_MII);
1503
1504 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1505 tp->link_config.advertising &=
1506 ~(ADVERTISED_1000baseT_Half |
1507 ADVERTISED_1000baseT_Full);
1508
1509 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1510 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1511 new_adv |= ADVERTISE_10HALF;
1512 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1513 new_adv |= ADVERTISE_10FULL;
1514 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1515 new_adv |= ADVERTISE_100HALF;
1516 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1517 new_adv |= ADVERTISE_100FULL;
1518 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1519
1520 if (tp->link_config.advertising &
1521 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1522 new_adv = 0;
1523 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1524 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1525 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1526 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1527 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1528 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1529 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1530 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1531 MII_TG3_CTRL_ENABLE_AS_MASTER);
1532 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1533 } else {
1534 tg3_writephy(tp, MII_TG3_CTRL, 0);
1535 }
1536 } else {
1537 /* Asking for a specific link mode. */
1538 if (tp->link_config.speed == SPEED_1000) {
1539 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1540 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1541
1542 if (tp->link_config.duplex == DUPLEX_FULL)
1543 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1544 else
1545 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1546 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1547 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1548 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1549 MII_TG3_CTRL_ENABLE_AS_MASTER);
1550 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1551 } else {
1552 tg3_writephy(tp, MII_TG3_CTRL, 0);
1553
1554 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1555 if (tp->link_config.speed == SPEED_100) {
1556 if (tp->link_config.duplex == DUPLEX_FULL)
1557 new_adv |= ADVERTISE_100FULL;
1558 else
1559 new_adv |= ADVERTISE_100HALF;
1560 } else {
1561 if (tp->link_config.duplex == DUPLEX_FULL)
1562 new_adv |= ADVERTISE_10FULL;
1563 else
1564 new_adv |= ADVERTISE_10HALF;
1565 }
1566 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1567 }
1568 }
1569
1570 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1571 tp->link_config.speed != SPEED_INVALID) {
1572 u32 bmcr, orig_bmcr;
1573
1574 tp->link_config.active_speed = tp->link_config.speed;
1575 tp->link_config.active_duplex = tp->link_config.duplex;
1576
1577 bmcr = 0;
1578 switch (tp->link_config.speed) {
1579 default:
1580 case SPEED_10:
1581 break;
1582
1583 case SPEED_100:
1584 bmcr |= BMCR_SPEED100;
1585 break;
1586
1587 case SPEED_1000:
1588 bmcr |= TG3_BMCR_SPEED1000;
1589 break;
1590 };
1591
1592 if (tp->link_config.duplex == DUPLEX_FULL)
1593 bmcr |= BMCR_FULLDPLX;
1594
1595 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1596 (bmcr != orig_bmcr)) {
1597 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1598 for (i = 0; i < 1500; i++) {
1599 u32 tmp;
1600
1601 udelay(10);
1602 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1603 tg3_readphy(tp, MII_BMSR, &tmp))
1604 continue;
1605 if (!(tmp & BMSR_LSTATUS)) {
1606 udelay(40);
1607 break;
1608 }
1609 }
1610 tg3_writephy(tp, MII_BMCR, bmcr);
1611 udelay(40);
1612 }
1613 } else {
1614 tg3_writephy(tp, MII_BMCR,
1615 BMCR_ANENABLE | BMCR_ANRESTART);
1616 }
1617}
1618
1619static int tg3_init_5401phy_dsp(struct tg3 *tp)
1620{
1621 int err;
1622
1623 /* Turn off tap power management. */
1624 /* Set Extended packet length bit */
1625 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1626
1627 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1628 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1629
1630 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1631 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1632
1633 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1634 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1635
1636 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1637 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1638
1639 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1640 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1641
1642 udelay(40);
1643
1644 return err;
1645}
1646
1647static int tg3_copper_is_advertising_all(struct tg3 *tp)
1648{
1649 u32 adv_reg, all_mask;
1650
1651 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1652 return 0;
1653
1654 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1655 ADVERTISE_100HALF | ADVERTISE_100FULL);
1656 if ((adv_reg & all_mask) != all_mask)
1657 return 0;
1658 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1659 u32 tg3_ctrl;
1660
1661 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1662 return 0;
1663
1664 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1665 MII_TG3_CTRL_ADV_1000_FULL);
1666 if ((tg3_ctrl & all_mask) != all_mask)
1667 return 0;
1668 }
1669 return 1;
1670}
1671
1672static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1673{
1674 int current_link_up;
1675 u32 bmsr, dummy;
1676 u16 current_speed;
1677 u8 current_duplex;
1678 int i, err;
1679
1680 tw32(MAC_EVENT, 0);
1681
1682 tw32_f(MAC_STATUS,
1683 (MAC_STATUS_SYNC_CHANGED |
1684 MAC_STATUS_CFG_CHANGED |
1685 MAC_STATUS_MI_COMPLETION |
1686 MAC_STATUS_LNKSTATE_CHANGED));
1687 udelay(40);
1688
1689 tp->mi_mode = MAC_MI_MODE_BASE;
1690 tw32_f(MAC_MI_MODE, tp->mi_mode);
1691 udelay(80);
1692
1693 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1694
1695 /* Some third-party PHYs need to be reset on link going
1696 * down.
1697 */
1698 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1701 netif_carrier_ok(tp->dev)) {
1702 tg3_readphy(tp, MII_BMSR, &bmsr);
1703 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1704 !(bmsr & BMSR_LSTATUS))
1705 force_reset = 1;
1706 }
1707 if (force_reset)
1708 tg3_phy_reset(tp);
1709
1710 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1711 tg3_readphy(tp, MII_BMSR, &bmsr);
1712 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1713 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1714 bmsr = 0;
1715
1716 if (!(bmsr & BMSR_LSTATUS)) {
1717 err = tg3_init_5401phy_dsp(tp);
1718 if (err)
1719 return err;
1720
1721 tg3_readphy(tp, MII_BMSR, &bmsr);
1722 for (i = 0; i < 1000; i++) {
1723 udelay(10);
1724 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1725 (bmsr & BMSR_LSTATUS)) {
1726 udelay(40);
1727 break;
1728 }
1729 }
1730
1731 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1732 !(bmsr & BMSR_LSTATUS) &&
1733 tp->link_config.active_speed == SPEED_1000) {
1734 err = tg3_phy_reset(tp);
1735 if (!err)
1736 err = tg3_init_5401phy_dsp(tp);
1737 if (err)
1738 return err;
1739 }
1740 }
1741 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1742 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1743 /* 5701 {A0,B0} CRC bug workaround */
1744 tg3_writephy(tp, 0x15, 0x0a75);
1745 tg3_writephy(tp, 0x1c, 0x8c68);
1746 tg3_writephy(tp, 0x1c, 0x8d68);
1747 tg3_writephy(tp, 0x1c, 0x8c68);
1748 }
1749
1750 /* Clear pending interrupts... */
1751 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1752 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1753
1754 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1755 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1756 else
1757 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1758
1759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1760 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1761 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1762 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1763 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1764 else
1765 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1766 }
1767
1768 current_link_up = 0;
1769 current_speed = SPEED_INVALID;
1770 current_duplex = DUPLEX_INVALID;
1771
1772 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1773 u32 val;
1774
1775 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1776 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1777 if (!(val & (1 << 10))) {
1778 val |= (1 << 10);
1779 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1780 goto relink;
1781 }
1782 }
1783
1784 bmsr = 0;
1785 for (i = 0; i < 100; i++) {
1786 tg3_readphy(tp, MII_BMSR, &bmsr);
1787 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1788 (bmsr & BMSR_LSTATUS))
1789 break;
1790 udelay(40);
1791 }
1792
1793 if (bmsr & BMSR_LSTATUS) {
1794 u32 aux_stat, bmcr;
1795
1796 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1797 for (i = 0; i < 2000; i++) {
1798 udelay(10);
1799 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1800 aux_stat)
1801 break;
1802 }
1803
1804 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1805 &current_speed,
1806 &current_duplex);
1807
1808 bmcr = 0;
1809 for (i = 0; i < 200; i++) {
1810 tg3_readphy(tp, MII_BMCR, &bmcr);
1811 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1812 continue;
1813 if (bmcr && bmcr != 0x7fff)
1814 break;
1815 udelay(10);
1816 }
1817
1818 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1819 if (bmcr & BMCR_ANENABLE) {
1820 current_link_up = 1;
1821
1822 /* Force autoneg restart if we are exiting
1823 * low power mode.
1824 */
1825 if (!tg3_copper_is_advertising_all(tp))
1826 current_link_up = 0;
1827 } else {
1828 current_link_up = 0;
1829 }
1830 } else {
1831 if (!(bmcr & BMCR_ANENABLE) &&
1832 tp->link_config.speed == current_speed &&
1833 tp->link_config.duplex == current_duplex) {
1834 current_link_up = 1;
1835 } else {
1836 current_link_up = 0;
1837 }
1838 }
1839
1840 tp->link_config.active_speed = current_speed;
1841 tp->link_config.active_duplex = current_duplex;
1842 }
1843
1844 if (current_link_up == 1 &&
1845 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1846 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1847 u32 local_adv, remote_adv;
1848
1849 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1850 local_adv = 0;
1851 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1852
1853 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1854 remote_adv = 0;
1855
1856 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1857
1858 /* If we are not advertising full pause capability,
1859 * something is wrong. Bring the link down and reconfigure.
1860 */
1861 if (local_adv != ADVERTISE_PAUSE_CAP) {
1862 current_link_up = 0;
1863 } else {
1864 tg3_setup_flow_control(tp, local_adv, remote_adv);
1865 }
1866 }
1867relink:
6921d201 1868 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1869 u32 tmp;
1870
1871 tg3_phy_copper_begin(tp);
1872
1873 tg3_readphy(tp, MII_BMSR, &tmp);
1874 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1875 (tmp & BMSR_LSTATUS))
1876 current_link_up = 1;
1877 }
1878
1879 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1880 if (current_link_up == 1) {
1881 if (tp->link_config.active_speed == SPEED_100 ||
1882 tp->link_config.active_speed == SPEED_10)
1883 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1884 else
1885 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1886 } else
1887 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1888
1889 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1890 if (tp->link_config.active_duplex == DUPLEX_HALF)
1891 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1892
1893 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1895 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1896 (current_link_up == 1 &&
1897 tp->link_config.active_speed == SPEED_10))
1898 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1899 } else {
1900 if (current_link_up == 1)
1901 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1902 }
1903
1904 /* ??? Without this setting Netgear GA302T PHY does not
1905 * ??? send/receive packets...
1906 */
1907 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1908 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1909 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1910 tw32_f(MAC_MI_MODE, tp->mi_mode);
1911 udelay(80);
1912 }
1913
1914 tw32_f(MAC_MODE, tp->mac_mode);
1915 udelay(40);
1916
1917 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1918 /* Polled via timer. */
1919 tw32_f(MAC_EVENT, 0);
1920 } else {
1921 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1922 }
1923 udelay(40);
1924
1925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1926 current_link_up == 1 &&
1927 tp->link_config.active_speed == SPEED_1000 &&
1928 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1929 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1930 udelay(120);
1931 tw32_f(MAC_STATUS,
1932 (MAC_STATUS_SYNC_CHANGED |
1933 MAC_STATUS_CFG_CHANGED));
1934 udelay(40);
1935 tg3_write_mem(tp,
1936 NIC_SRAM_FIRMWARE_MBOX,
1937 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1938 }
1939
1940 if (current_link_up != netif_carrier_ok(tp->dev)) {
1941 if (current_link_up)
1942 netif_carrier_on(tp->dev);
1943 else
1944 netif_carrier_off(tp->dev);
1945 tg3_link_report(tp);
1946 }
1947
1948 return 0;
1949}
1950
1951struct tg3_fiber_aneginfo {
1952 int state;
1953#define ANEG_STATE_UNKNOWN 0
1954#define ANEG_STATE_AN_ENABLE 1
1955#define ANEG_STATE_RESTART_INIT 2
1956#define ANEG_STATE_RESTART 3
1957#define ANEG_STATE_DISABLE_LINK_OK 4
1958#define ANEG_STATE_ABILITY_DETECT_INIT 5
1959#define ANEG_STATE_ABILITY_DETECT 6
1960#define ANEG_STATE_ACK_DETECT_INIT 7
1961#define ANEG_STATE_ACK_DETECT 8
1962#define ANEG_STATE_COMPLETE_ACK_INIT 9
1963#define ANEG_STATE_COMPLETE_ACK 10
1964#define ANEG_STATE_IDLE_DETECT_INIT 11
1965#define ANEG_STATE_IDLE_DETECT 12
1966#define ANEG_STATE_LINK_OK 13
1967#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1968#define ANEG_STATE_NEXT_PAGE_WAIT 15
1969
1970 u32 flags;
1971#define MR_AN_ENABLE 0x00000001
1972#define MR_RESTART_AN 0x00000002
1973#define MR_AN_COMPLETE 0x00000004
1974#define MR_PAGE_RX 0x00000008
1975#define MR_NP_LOADED 0x00000010
1976#define MR_TOGGLE_TX 0x00000020
1977#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1978#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1979#define MR_LP_ADV_SYM_PAUSE 0x00000100
1980#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1981#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1982#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1983#define MR_LP_ADV_NEXT_PAGE 0x00001000
1984#define MR_TOGGLE_RX 0x00002000
1985#define MR_NP_RX 0x00004000
1986
1987#define MR_LINK_OK 0x80000000
1988
1989 unsigned long link_time, cur_time;
1990
1991 u32 ability_match_cfg;
1992 int ability_match_count;
1993
1994 char ability_match, idle_match, ack_match;
1995
1996 u32 txconfig, rxconfig;
1997#define ANEG_CFG_NP 0x00000080
1998#define ANEG_CFG_ACK 0x00000040
1999#define ANEG_CFG_RF2 0x00000020
2000#define ANEG_CFG_RF1 0x00000010
2001#define ANEG_CFG_PS2 0x00000001
2002#define ANEG_CFG_PS1 0x00008000
2003#define ANEG_CFG_HD 0x00004000
2004#define ANEG_CFG_FD 0x00002000
2005#define ANEG_CFG_INVAL 0x00001f06
2006
2007};
2008#define ANEG_OK 0
2009#define ANEG_DONE 1
2010#define ANEG_TIMER_ENAB 2
2011#define ANEG_FAILED -1
2012
2013#define ANEG_STATE_SETTLE_TIME 10000
2014
2015static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2016 struct tg3_fiber_aneginfo *ap)
2017{
2018 unsigned long delta;
2019 u32 rx_cfg_reg;
2020 int ret;
2021
2022 if (ap->state == ANEG_STATE_UNKNOWN) {
2023 ap->rxconfig = 0;
2024 ap->link_time = 0;
2025 ap->cur_time = 0;
2026 ap->ability_match_cfg = 0;
2027 ap->ability_match_count = 0;
2028 ap->ability_match = 0;
2029 ap->idle_match = 0;
2030 ap->ack_match = 0;
2031 }
2032 ap->cur_time++;
2033
2034 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2035 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2036
2037 if (rx_cfg_reg != ap->ability_match_cfg) {
2038 ap->ability_match_cfg = rx_cfg_reg;
2039 ap->ability_match = 0;
2040 ap->ability_match_count = 0;
2041 } else {
2042 if (++ap->ability_match_count > 1) {
2043 ap->ability_match = 1;
2044 ap->ability_match_cfg = rx_cfg_reg;
2045 }
2046 }
2047 if (rx_cfg_reg & ANEG_CFG_ACK)
2048 ap->ack_match = 1;
2049 else
2050 ap->ack_match = 0;
2051
2052 ap->idle_match = 0;
2053 } else {
2054 ap->idle_match = 1;
2055 ap->ability_match_cfg = 0;
2056 ap->ability_match_count = 0;
2057 ap->ability_match = 0;
2058 ap->ack_match = 0;
2059
2060 rx_cfg_reg = 0;
2061 }
2062
2063 ap->rxconfig = rx_cfg_reg;
2064 ret = ANEG_OK;
2065
2066 switch(ap->state) {
2067 case ANEG_STATE_UNKNOWN:
2068 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2069 ap->state = ANEG_STATE_AN_ENABLE;
2070
2071 /* fallthru */
2072 case ANEG_STATE_AN_ENABLE:
2073 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2074 if (ap->flags & MR_AN_ENABLE) {
2075 ap->link_time = 0;
2076 ap->cur_time = 0;
2077 ap->ability_match_cfg = 0;
2078 ap->ability_match_count = 0;
2079 ap->ability_match = 0;
2080 ap->idle_match = 0;
2081 ap->ack_match = 0;
2082
2083 ap->state = ANEG_STATE_RESTART_INIT;
2084 } else {
2085 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2086 }
2087 break;
2088
2089 case ANEG_STATE_RESTART_INIT:
2090 ap->link_time = ap->cur_time;
2091 ap->flags &= ~(MR_NP_LOADED);
2092 ap->txconfig = 0;
2093 tw32(MAC_TX_AUTO_NEG, 0);
2094 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2095 tw32_f(MAC_MODE, tp->mac_mode);
2096 udelay(40);
2097
2098 ret = ANEG_TIMER_ENAB;
2099 ap->state = ANEG_STATE_RESTART;
2100
2101 /* fallthru */
2102 case ANEG_STATE_RESTART:
2103 delta = ap->cur_time - ap->link_time;
2104 if (delta > ANEG_STATE_SETTLE_TIME) {
2105 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2106 } else {
2107 ret = ANEG_TIMER_ENAB;
2108 }
2109 break;
2110
2111 case ANEG_STATE_DISABLE_LINK_OK:
2112 ret = ANEG_DONE;
2113 break;
2114
2115 case ANEG_STATE_ABILITY_DETECT_INIT:
2116 ap->flags &= ~(MR_TOGGLE_TX);
2117 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2118 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2119 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2120 tw32_f(MAC_MODE, tp->mac_mode);
2121 udelay(40);
2122
2123 ap->state = ANEG_STATE_ABILITY_DETECT;
2124 break;
2125
2126 case ANEG_STATE_ABILITY_DETECT:
2127 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2128 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2129 }
2130 break;
2131
2132 case ANEG_STATE_ACK_DETECT_INIT:
2133 ap->txconfig |= ANEG_CFG_ACK;
2134 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2135 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2136 tw32_f(MAC_MODE, tp->mac_mode);
2137 udelay(40);
2138
2139 ap->state = ANEG_STATE_ACK_DETECT;
2140
2141 /* fallthru */
2142 case ANEG_STATE_ACK_DETECT:
2143 if (ap->ack_match != 0) {
2144 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2145 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2146 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2147 } else {
2148 ap->state = ANEG_STATE_AN_ENABLE;
2149 }
2150 } else if (ap->ability_match != 0 &&
2151 ap->rxconfig == 0) {
2152 ap->state = ANEG_STATE_AN_ENABLE;
2153 }
2154 break;
2155
2156 case ANEG_STATE_COMPLETE_ACK_INIT:
2157 if (ap->rxconfig & ANEG_CFG_INVAL) {
2158 ret = ANEG_FAILED;
2159 break;
2160 }
2161 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2162 MR_LP_ADV_HALF_DUPLEX |
2163 MR_LP_ADV_SYM_PAUSE |
2164 MR_LP_ADV_ASYM_PAUSE |
2165 MR_LP_ADV_REMOTE_FAULT1 |
2166 MR_LP_ADV_REMOTE_FAULT2 |
2167 MR_LP_ADV_NEXT_PAGE |
2168 MR_TOGGLE_RX |
2169 MR_NP_RX);
2170 if (ap->rxconfig & ANEG_CFG_FD)
2171 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2172 if (ap->rxconfig & ANEG_CFG_HD)
2173 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2174 if (ap->rxconfig & ANEG_CFG_PS1)
2175 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2176 if (ap->rxconfig & ANEG_CFG_PS2)
2177 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2178 if (ap->rxconfig & ANEG_CFG_RF1)
2179 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2180 if (ap->rxconfig & ANEG_CFG_RF2)
2181 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2182 if (ap->rxconfig & ANEG_CFG_NP)
2183 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2184
2185 ap->link_time = ap->cur_time;
2186
2187 ap->flags ^= (MR_TOGGLE_TX);
2188 if (ap->rxconfig & 0x0008)
2189 ap->flags |= MR_TOGGLE_RX;
2190 if (ap->rxconfig & ANEG_CFG_NP)
2191 ap->flags |= MR_NP_RX;
2192 ap->flags |= MR_PAGE_RX;
2193
2194 ap->state = ANEG_STATE_COMPLETE_ACK;
2195 ret = ANEG_TIMER_ENAB;
2196 break;
2197
2198 case ANEG_STATE_COMPLETE_ACK:
2199 if (ap->ability_match != 0 &&
2200 ap->rxconfig == 0) {
2201 ap->state = ANEG_STATE_AN_ENABLE;
2202 break;
2203 }
2204 delta = ap->cur_time - ap->link_time;
2205 if (delta > ANEG_STATE_SETTLE_TIME) {
2206 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2207 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2208 } else {
2209 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2210 !(ap->flags & MR_NP_RX)) {
2211 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2212 } else {
2213 ret = ANEG_FAILED;
2214 }
2215 }
2216 }
2217 break;
2218
2219 case ANEG_STATE_IDLE_DETECT_INIT:
2220 ap->link_time = ap->cur_time;
2221 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2222 tw32_f(MAC_MODE, tp->mac_mode);
2223 udelay(40);
2224
2225 ap->state = ANEG_STATE_IDLE_DETECT;
2226 ret = ANEG_TIMER_ENAB;
2227 break;
2228
2229 case ANEG_STATE_IDLE_DETECT:
2230 if (ap->ability_match != 0 &&
2231 ap->rxconfig == 0) {
2232 ap->state = ANEG_STATE_AN_ENABLE;
2233 break;
2234 }
2235 delta = ap->cur_time - ap->link_time;
2236 if (delta > ANEG_STATE_SETTLE_TIME) {
2237 /* XXX another gem from the Broadcom driver :( */
2238 ap->state = ANEG_STATE_LINK_OK;
2239 }
2240 break;
2241
2242 case ANEG_STATE_LINK_OK:
2243 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2244 ret = ANEG_DONE;
2245 break;
2246
2247 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2248 /* ??? unimplemented */
2249 break;
2250
2251 case ANEG_STATE_NEXT_PAGE_WAIT:
2252 /* ??? unimplemented */
2253 break;
2254
2255 default:
2256 ret = ANEG_FAILED;
2257 break;
2258 };
2259
2260 return ret;
2261}
2262
2263static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2264{
2265 int res = 0;
2266 struct tg3_fiber_aneginfo aninfo;
2267 int status = ANEG_FAILED;
2268 unsigned int tick;
2269 u32 tmp;
2270
2271 tw32_f(MAC_TX_AUTO_NEG, 0);
2272
2273 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2274 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2275 udelay(40);
2276
2277 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2278 udelay(40);
2279
2280 memset(&aninfo, 0, sizeof(aninfo));
2281 aninfo.flags |= MR_AN_ENABLE;
2282 aninfo.state = ANEG_STATE_UNKNOWN;
2283 aninfo.cur_time = 0;
2284 tick = 0;
2285 while (++tick < 195000) {
2286 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2287 if (status == ANEG_DONE || status == ANEG_FAILED)
2288 break;
2289
2290 udelay(1);
2291 }
2292
2293 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2294 tw32_f(MAC_MODE, tp->mac_mode);
2295 udelay(40);
2296
2297 *flags = aninfo.flags;
2298
2299 if (status == ANEG_DONE &&
2300 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2301 MR_LP_ADV_FULL_DUPLEX)))
2302 res = 1;
2303
2304 return res;
2305}
2306
2307static void tg3_init_bcm8002(struct tg3 *tp)
2308{
2309 u32 mac_status = tr32(MAC_STATUS);
2310 int i;
2311
2312 /* Reset when initting first time or we have a link. */
2313 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2314 !(mac_status & MAC_STATUS_PCS_SYNCED))
2315 return;
2316
2317 /* Set PLL lock range. */
2318 tg3_writephy(tp, 0x16, 0x8007);
2319
2320 /* SW reset */
2321 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2322
2323 /* Wait for reset to complete. */
2324 /* XXX schedule_timeout() ... */
2325 for (i = 0; i < 500; i++)
2326 udelay(10);
2327
2328 /* Config mode; select PMA/Ch 1 regs. */
2329 tg3_writephy(tp, 0x10, 0x8411);
2330
2331 /* Enable auto-lock and comdet, select txclk for tx. */
2332 tg3_writephy(tp, 0x11, 0x0a10);
2333
2334 tg3_writephy(tp, 0x18, 0x00a0);
2335 tg3_writephy(tp, 0x16, 0x41ff);
2336
2337 /* Assert and deassert POR. */
2338 tg3_writephy(tp, 0x13, 0x0400);
2339 udelay(40);
2340 tg3_writephy(tp, 0x13, 0x0000);
2341
2342 tg3_writephy(tp, 0x11, 0x0a50);
2343 udelay(40);
2344 tg3_writephy(tp, 0x11, 0x0a10);
2345
2346 /* Wait for signal to stabilize */
2347 /* XXX schedule_timeout() ... */
2348 for (i = 0; i < 15000; i++)
2349 udelay(10);
2350
2351 /* Deselect the channel register so we can read the PHYID
2352 * later.
2353 */
2354 tg3_writephy(tp, 0x10, 0x8011);
2355}
2356
2357static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2358{
2359 u32 sg_dig_ctrl, sg_dig_status;
2360 u32 serdes_cfg, expected_sg_dig_ctrl;
2361 int workaround, port_a;
2362 int current_link_up;
2363
2364 serdes_cfg = 0;
2365 expected_sg_dig_ctrl = 0;
2366 workaround = 0;
2367 port_a = 1;
2368 current_link_up = 0;
2369
2370 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2371 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2372 workaround = 1;
2373 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2374 port_a = 0;
2375
2376 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2377 /* preserve bits 20-23 for voltage regulator */
2378 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2379 }
2380
2381 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2382
2383 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2384 if (sg_dig_ctrl & (1 << 31)) {
2385 if (workaround) {
2386 u32 val = serdes_cfg;
2387
2388 if (port_a)
2389 val |= 0xc010000;
2390 else
2391 val |= 0x4010000;
2392 tw32_f(MAC_SERDES_CFG, val);
2393 }
2394 tw32_f(SG_DIG_CTRL, 0x01388400);
2395 }
2396 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2397 tg3_setup_flow_control(tp, 0, 0);
2398 current_link_up = 1;
2399 }
2400 goto out;
2401 }
2402
2403 /* Want auto-negotiation. */
2404 expected_sg_dig_ctrl = 0x81388400;
2405
2406 /* Pause capability */
2407 expected_sg_dig_ctrl |= (1 << 11);
2408
2409 /* Asymettric pause */
2410 expected_sg_dig_ctrl |= (1 << 12);
2411
2412 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2413 if (workaround)
2414 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2415 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2416 udelay(5);
2417 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2418
2419 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2420 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2421 MAC_STATUS_SIGNAL_DET)) {
2422 int i;
2423
2424 /* Giver time to negotiate (~200ms) */
2425 for (i = 0; i < 40000; i++) {
2426 sg_dig_status = tr32(SG_DIG_STATUS);
2427 if (sg_dig_status & (0x3))
2428 break;
2429 udelay(5);
2430 }
2431 mac_status = tr32(MAC_STATUS);
2432
2433 if ((sg_dig_status & (1 << 1)) &&
2434 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2435 u32 local_adv, remote_adv;
2436
2437 local_adv = ADVERTISE_PAUSE_CAP;
2438 remote_adv = 0;
2439 if (sg_dig_status & (1 << 19))
2440 remote_adv |= LPA_PAUSE_CAP;
2441 if (sg_dig_status & (1 << 20))
2442 remote_adv |= LPA_PAUSE_ASYM;
2443
2444 tg3_setup_flow_control(tp, local_adv, remote_adv);
2445 current_link_up = 1;
2446 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2447 } else if (!(sg_dig_status & (1 << 1))) {
2448 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2449 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2450 else {
2451 if (workaround) {
2452 u32 val = serdes_cfg;
2453
2454 if (port_a)
2455 val |= 0xc010000;
2456 else
2457 val |= 0x4010000;
2458
2459 tw32_f(MAC_SERDES_CFG, val);
2460 }
2461
2462 tw32_f(SG_DIG_CTRL, 0x01388400);
2463 udelay(40);
2464
2465 /* Link parallel detection - link is up */
2466 /* only if we have PCS_SYNC and not */
2467 /* receiving config code words */
2468 mac_status = tr32(MAC_STATUS);
2469 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2470 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2471 tg3_setup_flow_control(tp, 0, 0);
2472 current_link_up = 1;
2473 }
2474 }
2475 }
2476 }
2477
2478out:
2479 return current_link_up;
2480}
2481
2482static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2483{
2484 int current_link_up = 0;
2485
2486 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2487 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2488 goto out;
2489 }
2490
2491 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2492 u32 flags;
2493 int i;
2494
2495 if (fiber_autoneg(tp, &flags)) {
2496 u32 local_adv, remote_adv;
2497
2498 local_adv = ADVERTISE_PAUSE_CAP;
2499 remote_adv = 0;
2500 if (flags & MR_LP_ADV_SYM_PAUSE)
2501 remote_adv |= LPA_PAUSE_CAP;
2502 if (flags & MR_LP_ADV_ASYM_PAUSE)
2503 remote_adv |= LPA_PAUSE_ASYM;
2504
2505 tg3_setup_flow_control(tp, local_adv, remote_adv);
2506
2507 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2508 current_link_up = 1;
2509 }
2510 for (i = 0; i < 30; i++) {
2511 udelay(20);
2512 tw32_f(MAC_STATUS,
2513 (MAC_STATUS_SYNC_CHANGED |
2514 MAC_STATUS_CFG_CHANGED));
2515 udelay(40);
2516 if ((tr32(MAC_STATUS) &
2517 (MAC_STATUS_SYNC_CHANGED |
2518 MAC_STATUS_CFG_CHANGED)) == 0)
2519 break;
2520 }
2521
2522 mac_status = tr32(MAC_STATUS);
2523 if (current_link_up == 0 &&
2524 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2525 !(mac_status & MAC_STATUS_RCVD_CFG))
2526 current_link_up = 1;
2527 } else {
2528 /* Forcing 1000FD link up. */
2529 current_link_up = 1;
2530 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2531
2532 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2533 udelay(40);
2534 }
2535
2536out:
2537 return current_link_up;
2538}
2539
2540static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2541{
2542 u32 orig_pause_cfg;
2543 u16 orig_active_speed;
2544 u8 orig_active_duplex;
2545 u32 mac_status;
2546 int current_link_up;
2547 int i;
2548
2549 orig_pause_cfg =
2550 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2551 TG3_FLAG_TX_PAUSE));
2552 orig_active_speed = tp->link_config.active_speed;
2553 orig_active_duplex = tp->link_config.active_duplex;
2554
2555 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2556 netif_carrier_ok(tp->dev) &&
2557 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2558 mac_status = tr32(MAC_STATUS);
2559 mac_status &= (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_SIGNAL_DET |
2561 MAC_STATUS_CFG_CHANGED |
2562 MAC_STATUS_RCVD_CFG);
2563 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2564 MAC_STATUS_SIGNAL_DET)) {
2565 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2566 MAC_STATUS_CFG_CHANGED));
2567 return 0;
2568 }
2569 }
2570
2571 tw32_f(MAC_TX_AUTO_NEG, 0);
2572
2573 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2574 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2575 tw32_f(MAC_MODE, tp->mac_mode);
2576 udelay(40);
2577
2578 if (tp->phy_id == PHY_ID_BCM8002)
2579 tg3_init_bcm8002(tp);
2580
2581 /* Enable link change event even when serdes polling. */
2582 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2583 udelay(40);
2584
2585 current_link_up = 0;
2586 mac_status = tr32(MAC_STATUS);
2587
2588 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2589 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2590 else
2591 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2592
2593 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2594 tw32_f(MAC_MODE, tp->mac_mode);
2595 udelay(40);
2596
2597 tp->hw_status->status =
2598 (SD_STATUS_UPDATED |
2599 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2600
2601 for (i = 0; i < 100; i++) {
2602 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2603 MAC_STATUS_CFG_CHANGED));
2604 udelay(5);
2605 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2606 MAC_STATUS_CFG_CHANGED)) == 0)
2607 break;
2608 }
2609
2610 mac_status = tr32(MAC_STATUS);
2611 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2612 current_link_up = 0;
2613 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2614 tw32_f(MAC_MODE, (tp->mac_mode |
2615 MAC_MODE_SEND_CONFIGS));
2616 udelay(1);
2617 tw32_f(MAC_MODE, tp->mac_mode);
2618 }
2619 }
2620
2621 if (current_link_up == 1) {
2622 tp->link_config.active_speed = SPEED_1000;
2623 tp->link_config.active_duplex = DUPLEX_FULL;
2624 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2625 LED_CTRL_LNKLED_OVERRIDE |
2626 LED_CTRL_1000MBPS_ON));
2627 } else {
2628 tp->link_config.active_speed = SPEED_INVALID;
2629 tp->link_config.active_duplex = DUPLEX_INVALID;
2630 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2631 LED_CTRL_LNKLED_OVERRIDE |
2632 LED_CTRL_TRAFFIC_OVERRIDE));
2633 }
2634
2635 if (current_link_up != netif_carrier_ok(tp->dev)) {
2636 if (current_link_up)
2637 netif_carrier_on(tp->dev);
2638 else
2639 netif_carrier_off(tp->dev);
2640 tg3_link_report(tp);
2641 } else {
2642 u32 now_pause_cfg =
2643 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2644 TG3_FLAG_TX_PAUSE);
2645 if (orig_pause_cfg != now_pause_cfg ||
2646 orig_active_speed != tp->link_config.active_speed ||
2647 orig_active_duplex != tp->link_config.active_duplex)
2648 tg3_link_report(tp);
2649 }
2650
2651 return 0;
2652}
2653
747e8f8b
MC		 2654static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2655{
2656 int current_link_up, err = 0;
2657 u32 bmsr, bmcr;
2658 u16 current_speed;
2659 u8 current_duplex;
2660
2661 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2662 tw32_f(MAC_MODE, tp->mac_mode);
2663 udelay(40);
2664
2665 tw32(MAC_EVENT, 0);
2666
2667 tw32_f(MAC_STATUS,
2668 (MAC_STATUS_SYNC_CHANGED |
2669 MAC_STATUS_CFG_CHANGED |
2670 MAC_STATUS_MI_COMPLETION |
2671 MAC_STATUS_LNKSTATE_CHANGED));
2672 udelay(40);
2673
2674 if (force_reset)
2675 tg3_phy_reset(tp);
2676
2677 current_link_up = 0;
2678 current_speed = SPEED_INVALID;
2679 current_duplex = DUPLEX_INVALID;
2680
2681 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2682 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2683
2684 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2685
2686 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2687 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2688 /* do nothing, just check for link up at the end */
2689 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2690 u32 adv, new_adv;
2691
2692 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2693 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2694 ADVERTISE_1000XPAUSE |
2695 ADVERTISE_1000XPSE_ASYM |
2696 ADVERTISE_SLCT);
2697
2698 /* Always advertise symmetric PAUSE just like copper */
2699 new_adv |= ADVERTISE_1000XPAUSE;
2700
2701 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2702 new_adv |= ADVERTISE_1000XHALF;
2703 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2704 new_adv |= ADVERTISE_1000XFULL;
2705
2706 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2707 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2708 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2709 tg3_writephy(tp, MII_BMCR, bmcr);
2710
2711 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2712 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2713 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2714
2715 return err;
2716 }
2717 } else {
2718 u32 new_bmcr;
2719
2720 bmcr &= ~BMCR_SPEED1000;
2721 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2722
2723 if (tp->link_config.duplex == DUPLEX_FULL)
2724 new_bmcr |= BMCR_FULLDPLX;
2725
2726 if (new_bmcr != bmcr) {
2727 /* BMCR_SPEED1000 is a reserved bit that needs
2728 * to be set on write.
2729 */
2730 new_bmcr |= BMCR_SPEED1000;
2731
2732 /* Force a linkdown */
2733 if (netif_carrier_ok(tp->dev)) {
2734 u32 adv;
2735
2736 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2737 adv &= ~(ADVERTISE_1000XFULL |
2738 ADVERTISE_1000XHALF |
2739 ADVERTISE_SLCT);
2740 tg3_writephy(tp, MII_ADVERTISE, adv);
2741 tg3_writephy(tp, MII_BMCR, bmcr |
2742 BMCR_ANRESTART |
2743 BMCR_ANENABLE);
2744 udelay(10);
2745 netif_carrier_off(tp->dev);
2746 }
2747 tg3_writephy(tp, MII_BMCR, new_bmcr);
2748 bmcr = new_bmcr;
2749 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2750 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2751 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2752 }
2753 }
2754
2755 if (bmsr & BMSR_LSTATUS) {
2756 current_speed = SPEED_1000;
2757 current_link_up = 1;
2758 if (bmcr & BMCR_FULLDPLX)
2759 current_duplex = DUPLEX_FULL;
2760 else
2761 current_duplex = DUPLEX_HALF;
2762
2763 if (bmcr & BMCR_ANENABLE) {
2764 u32 local_adv, remote_adv, common;
2765
2766 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2767 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2768 common = local_adv & remote_adv;
2769 if (common & (ADVERTISE_1000XHALF |
2770 ADVERTISE_1000XFULL)) {
2771 if (common & ADVERTISE_1000XFULL)
2772 current_duplex = DUPLEX_FULL;
2773 else
2774 current_duplex = DUPLEX_HALF;
2775
2776 tg3_setup_flow_control(tp, local_adv,
2777 remote_adv);
2778 }
2779 else
2780 current_link_up = 0;
2781 }
2782 }
2783
2784 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2785 if (tp->link_config.active_duplex == DUPLEX_HALF)
2786 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2787
2788 tw32_f(MAC_MODE, tp->mac_mode);
2789 udelay(40);
2790
2791 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2792
2793 tp->link_config.active_speed = current_speed;
2794 tp->link_config.active_duplex = current_duplex;
2795
2796 if (current_link_up != netif_carrier_ok(tp->dev)) {
2797 if (current_link_up)
2798 netif_carrier_on(tp->dev);
2799 else {
2800 netif_carrier_off(tp->dev);
2801 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2802 }
2803 tg3_link_report(tp);
2804 }
2805 return err;
2806}
2807
2808static void tg3_serdes_parallel_detect(struct tg3 *tp)
2809{
2810 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2811 /* Give autoneg time to complete. */
2812 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2813 return;
2814 }
2815 if (!netif_carrier_ok(tp->dev) &&
2816 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2817 u32 bmcr;
2818
2819 tg3_readphy(tp, MII_BMCR, &bmcr);
2820 if (bmcr & BMCR_ANENABLE) {
2821 u32 phy1, phy2;
2822
2823 /* Select shadow register 0x1f */
2824 tg3_writephy(tp, 0x1c, 0x7c00);
2825 tg3_readphy(tp, 0x1c, &phy1);
2826
2827 /* Select expansion interrupt status register */
2828 tg3_writephy(tp, 0x17, 0x0f01);
2829 tg3_readphy(tp, 0x15, &phy2);
2830 tg3_readphy(tp, 0x15, &phy2);
2831
2832 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2833 /* We have signal detect and not receiving
2834 * config code words, link is up by parallel
2835 * detection.
2836 */
2837
2838 bmcr &= ~BMCR_ANENABLE;
2839 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2840 tg3_writephy(tp, MII_BMCR, bmcr);
2841 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2842 }
2843 }
2844 }
2845 else if (netif_carrier_ok(tp->dev) &&
2846 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2847 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2848 u32 phy2;
2849
2850 /* Select expansion interrupt status register */
2851 tg3_writephy(tp, 0x17, 0x0f01);
2852 tg3_readphy(tp, 0x15, &phy2);
2853 if (phy2 & 0x20) {
2854 u32 bmcr;
2855
2856 /* Config code words received, turn on autoneg. */
2857 tg3_readphy(tp, MII_BMCR, &bmcr);
2858 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2859
2860 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2861
2862 }
2863 }
2864}
2865
1da177e4
LT		 2866static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2867{
2868 int err;
2869
2870 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2871 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2872 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2873 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2874 } else {
2875 err = tg3_setup_copper_phy(tp, force_reset);
2876 }
2877
2878 if (tp->link_config.active_speed == SPEED_1000 &&
2879 tp->link_config.active_duplex == DUPLEX_HALF)
2880 tw32(MAC_TX_LENGTHS,
2881 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2882 (6 << TX_LENGTHS_IPG_SHIFT) |
2883 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2884 else
2885 tw32(MAC_TX_LENGTHS,
2886 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2887 (6 << TX_LENGTHS_IPG_SHIFT) |
2888 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2889
2890 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2891 if (netif_carrier_ok(tp->dev)) {
2892 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 2893 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 2894 } else {
2895 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2896 }
2897 }
2898
2899 return err;
2900}
2901
2902/* Tigon3 never reports partial packet sends. So we do not
2903 * need special logic to handle SKBs that have not had all
2904 * of their frags sent yet, like SunGEM does.
2905 */
2906static void tg3_tx(struct tg3 *tp)
2907{
2908 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2909 u32 sw_idx = tp->tx_cons;
2910
2911 while (sw_idx != hw_idx) {
2912 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2913 struct sk_buff *skb = ri->skb;
2914 int i;
2915
2916 if (unlikely(skb == NULL))
2917 BUG();
2918
2919 pci_unmap_single(tp->pdev,
2920 pci_unmap_addr(ri, mapping),
2921 skb_headlen(skb),
2922 PCI_DMA_TODEVICE);
2923
2924 ri->skb = NULL;
2925
2926 sw_idx = NEXT_TX(sw_idx);
2927
2928 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2929 if (unlikely(sw_idx == hw_idx))
2930 BUG();
2931
2932 ri = &tp->tx_buffers[sw_idx];
2933 if (unlikely(ri->skb != NULL))
2934 BUG();
2935
2936 pci_unmap_page(tp->pdev,
2937 pci_unmap_addr(ri, mapping),
2938 skb_shinfo(skb)->frags[i].size,
2939 PCI_DMA_TODEVICE);
2940
2941 sw_idx = NEXT_TX(sw_idx);
2942 }
2943
f47c11ee 2944 dev_kfree_skb(skb);
1da177e4
LT		 2945 }
2946
2947 tp->tx_cons = sw_idx;
2948
51b91468
MC		 2949 if (unlikely(netif_queue_stopped(tp->dev))) {
2950 spin_lock(&tp->tx_lock);
2951 if (netif_queue_stopped(tp->dev) &&
2952 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2953 netif_wake_queue(tp->dev);
2954 spin_unlock(&tp->tx_lock);
2955 }
1da177e4
LT		 2956}
2957
2958/* Returns size of skb allocated or < 0 on error.
2959 *
2960 * We only need to fill in the address because the other members
2961 * of the RX descriptor are invariant, see tg3_init_rings.
2962 *
2963 * Note the purposeful assymetry of cpu vs. chip accesses. For
2964 * posting buffers we only dirty the first cache line of the RX
2965 * descriptor (containing the address). Whereas for the RX status
2966 * buffers the cpu only reads the last cacheline of the RX descriptor
2967 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2968 */
2969static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2970 int src_idx, u32 dest_idx_unmasked)
2971{
2972 struct tg3_rx_buffer_desc *desc;
2973 struct ring_info *map, *src_map;
2974 struct sk_buff *skb;
2975 dma_addr_t mapping;
2976 int skb_size, dest_idx;
2977
2978 src_map = NULL;
2979 switch (opaque_key) {
2980 case RXD_OPAQUE_RING_STD:
2981 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2982 desc = &tp->rx_std[dest_idx];
2983 map = &tp->rx_std_buffers[dest_idx];
2984 if (src_idx >= 0)
2985 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 2986 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 2987 break;
2988
2989 case RXD_OPAQUE_RING_JUMBO:
2990 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2991 desc = &tp->rx_jumbo[dest_idx];
2992 map = &tp->rx_jumbo_buffers[dest_idx];
2993 if (src_idx >= 0)
2994 src_map = &tp->rx_jumbo_buffers[src_idx];
2995 skb_size = RX_JUMBO_PKT_BUF_SZ;
2996 break;
2997
2998 default:
2999 return -EINVAL;
3000 };
3001
3002 /* Do not overwrite any of the map or rp information
3003 * until we are sure we can commit to a new buffer.
3004 *
3005 * Callers depend upon this behavior and assume that
3006 * we leave everything unchanged if we fail.
3007 */
3008 skb = dev_alloc_skb(skb_size);
3009 if (skb == NULL)
3010 return -ENOMEM;
3011
3012 skb->dev = tp->dev;
3013 skb_reserve(skb, tp->rx_offset);
3014
3015 mapping = pci_map_single(tp->pdev, skb->data,
3016 skb_size - tp->rx_offset,
3017 PCI_DMA_FROMDEVICE);
3018
3019 map->skb = skb;
3020 pci_unmap_addr_set(map, mapping, mapping);
3021
3022 if (src_map != NULL)
3023 src_map->skb = NULL;
3024
3025 desc->addr_hi = ((u64)mapping >> 32);
3026 desc->addr_lo = ((u64)mapping & 0xffffffff);
3027
3028 return skb_size;
3029}
3030
3031/* We only need to move over in the address because the other
3032 * members of the RX descriptor are invariant. See notes above
3033 * tg3_alloc_rx_skb for full details.
3034 */
3035static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3036 int src_idx, u32 dest_idx_unmasked)
3037{
3038 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3039 struct ring_info *src_map, *dest_map;
3040 int dest_idx;
3041
3042 switch (opaque_key) {
3043 case RXD_OPAQUE_RING_STD:
3044 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3045 dest_desc = &tp->rx_std[dest_idx];
3046 dest_map = &tp->rx_std_buffers[dest_idx];
3047 src_desc = &tp->rx_std[src_idx];
3048 src_map = &tp->rx_std_buffers[src_idx];
3049 break;
3050
3051 case RXD_OPAQUE_RING_JUMBO:
3052 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3053 dest_desc = &tp->rx_jumbo[dest_idx];
3054 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3055 src_desc = &tp->rx_jumbo[src_idx];
3056 src_map = &tp->rx_jumbo_buffers[src_idx];
3057 break;
3058
3059 default:
3060 return;
3061 };
3062
3063 dest_map->skb = src_map->skb;
3064 pci_unmap_addr_set(dest_map, mapping,
3065 pci_unmap_addr(src_map, mapping));
3066 dest_desc->addr_hi = src_desc->addr_hi;
3067 dest_desc->addr_lo = src_desc->addr_lo;
3068
3069 src_map->skb = NULL;
3070}
3071
3072#if TG3_VLAN_TAG_USED
3073static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3074{
3075 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3076}
3077#endif
3078
3079/* The RX ring scheme is composed of multiple rings which post fresh
3080 * buffers to the chip, and one special ring the chip uses to report
3081 * status back to the host.
3082 *
3083 * The special ring reports the status of received packets to the
3084 * host. The chip does not write into the original descriptor the
3085 * RX buffer was obtained from. The chip simply takes the original
3086 * descriptor as provided by the host, updates the status and length
3087 * field, then writes this into the next status ring entry.
3088 *
3089 * Each ring the host uses to post buffers to the chip is described
3090 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3091 * it is first placed into the on-chip ram. When the packet's length
3092 * is known, it walks down the TG3_BDINFO entries to select the ring.
3093 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3094 * which is within the range of the new packet's length is chosen.
3095 *
3096 * The "separate ring for rx status" scheme may sound queer, but it makes
3097 * sense from a cache coherency perspective. If only the host writes
3098 * to the buffer post rings, and only the chip writes to the rx status
3099 * rings, then cache lines never move beyond shared-modified state.
3100 * If both the host and chip were to write into the same ring, cache line
3101 * eviction could occur since both entities want it in an exclusive state.
3102 */
3103static int tg3_rx(struct tg3 *tp, int budget)
3104{
3105 u32 work_mask;
483ba50b
MC		 3106 u32 sw_idx = tp->rx_rcb_ptr;
3107 u16 hw_idx;
1da177e4
LT		 3108 int received;
3109
3110 hw_idx = tp->hw_status->idx[0].rx_producer;
3111 /*
3112 * We need to order the read of hw_idx and the read of
3113 * the opaque cookie.
3114 */
3115 rmb();
1da177e4
LT		 3116 work_mask = 0;
3117 received = 0;
3118 while (sw_idx != hw_idx && budget > 0) {
3119 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3120 unsigned int len;
3121 struct sk_buff *skb;
3122 dma_addr_t dma_addr;
3123 u32 opaque_key, desc_idx, *post_ptr;
3124
3125 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3126 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3127 if (opaque_key == RXD_OPAQUE_RING_STD) {
3128 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3129 mapping);
3130 skb = tp->rx_std_buffers[desc_idx].skb;
3131 post_ptr = &tp->rx_std_ptr;
3132 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3133 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3134 mapping);
3135 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3136 post_ptr = &tp->rx_jumbo_ptr;
3137 }
3138 else {
3139 goto next_pkt_nopost;
3140 }
3141
3142 work_mask |= opaque_key;
3143
3144 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3145 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3146 drop_it:
3147 tg3_recycle_rx(tp, opaque_key,
3148 desc_idx, *post_ptr);
3149 drop_it_no_recycle:
3150 /* Other statistics kept track of by card. */
3151 tp->net_stats.rx_dropped++;
3152 goto next_pkt;
3153 }
3154
3155 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3156
3157 if (len > RX_COPY_THRESHOLD
3158 && tp->rx_offset == 2
3159 /* rx_offset != 2 iff this is a 5701 card running
3160 * in PCI-X mode [see tg3_get_invariants()] */
3161 ) {
3162 int skb_size;
3163
3164 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3165 desc_idx, *post_ptr);
3166 if (skb_size < 0)
3167 goto drop_it;
3168
3169 pci_unmap_single(tp->pdev, dma_addr,
3170 skb_size - tp->rx_offset,
3171 PCI_DMA_FROMDEVICE);
3172
3173 skb_put(skb, len);
3174 } else {
3175 struct sk_buff *copy_skb;
3176
3177 tg3_recycle_rx(tp, opaque_key,
3178 desc_idx, *post_ptr);
3179
3180 copy_skb = dev_alloc_skb(len + 2);
3181 if (copy_skb == NULL)
3182 goto drop_it_no_recycle;
3183
3184 copy_skb->dev = tp->dev;
3185 skb_reserve(copy_skb, 2);
3186 skb_put(copy_skb, len);
3187 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3188 memcpy(copy_skb->data, skb->data, len);
3189 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3190
3191 /* We'll reuse the original ring buffer. */
3192 skb = copy_skb;
3193 }
3194
3195 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3196 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3197 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3198 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3199 skb->ip_summed = CHECKSUM_UNNECESSARY;
3200 else
3201 skb->ip_summed = CHECKSUM_NONE;
3202
3203 skb->protocol = eth_type_trans(skb, tp->dev);
3204#if TG3_VLAN_TAG_USED
3205 if (tp->vlgrp != NULL &&
3206 desc->type_flags & RXD_FLAG_VLAN) {
3207 tg3_vlan_rx(tp, skb,
3208 desc->err_vlan & RXD_VLAN_MASK);
3209 } else
3210#endif
3211 netif_receive_skb(skb);
3212
3213 tp->dev->last_rx = jiffies;
3214 received++;
3215 budget--;
3216
3217next_pkt:
3218 (*post_ptr)++;
3219next_pkt_nopost:
483ba50b
MC		 3220 sw_idx++;
3221 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
52f6d697
MC		 3222
3223 /* Refresh hw_idx to see if there is new work */
3224 if (sw_idx == hw_idx) {
3225 hw_idx = tp->hw_status->idx[0].rx_producer;
3226 rmb();
3227 }
1da177e4
LT		 3228 }
3229
3230 /* ACK the status ring. */
483ba50b
MC		 3231 tp->rx_rcb_ptr = sw_idx;
3232 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3233
3234 /* Refill RX ring(s). */
3235 if (work_mask & RXD_OPAQUE_RING_STD) {
3236 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3237 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3238 sw_idx);
3239 }
3240 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3241 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3242 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3243 sw_idx);
3244 }
3245 mmiowb();
3246
3247 return received;
3248}
3249
3250static int tg3_poll(struct net_device *netdev, int *budget)
3251{
3252 struct tg3 *tp = netdev_priv(netdev);
3253 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3254 int done;
3255
1da177e4
LT		 3256 /* handle link change and other phy events */
3257 if (!(tp->tg3_flags &
3258 (TG3_FLAG_USE_LINKCHG_REG |
3259 TG3_FLAG_POLL_SERDES))) {
3260 if (sblk->status & SD_STATUS_LINK_CHG) {
3261 sblk->status = SD_STATUS_UPDATED |
3262 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3263 spin_lock(&tp->lock);
1da177e4 3264 tg3_setup_phy(tp, 0);
f47c11ee 3265 spin_unlock(&tp->lock);
1da177e4
LT		 3266 }
3267 }
3268
3269 /* run TX completion thread */
3270 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3271 tg3_tx(tp);
1da177e4
LT		 3272 }
3273
1da177e4
LT		 3274 /* run RX thread, within the bounds set by NAPI.
3275 * All RX "locking" is done by ensuring outside
3276 * code synchronizes with dev->poll()
3277 */
1da177e4
LT		 3278 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3279 int orig_budget = *budget;
3280 int work_done;
3281
3282 if (orig_budget > netdev->quota)
3283 orig_budget = netdev->quota;
3284
3285 work_done = tg3_rx(tp, orig_budget);
3286
3287 *budget -= work_done;
3288 netdev->quota -= work_done;
1da177e4
LT		 3289 }
3290
38f3843e 3291 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3292 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3293 rmb();
3294 } else
3295 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3296
1da177e4 3297 /* if no more work, tell net stack and NIC we're done */
f7383c22 3298 done = !tg3_has_work(tp);
1da177e4 3299 if (done) {
f47c11ee 3300 netif_rx_complete(netdev);
1da177e4 3301 tg3_restart_ints(tp);
1da177e4
LT		 3302 }
3303
3304 return (done ? 0 : 1);
3305}
3306
f47c11ee
DM		 3307static void tg3_irq_quiesce(struct tg3 *tp)
3308{
3309 BUG_ON(tp->irq_sync);
3310
3311 tp->irq_sync = 1;
3312 smp_mb();
3313
3314 synchronize_irq(tp->pdev->irq);
3315}
3316
3317static inline int tg3_irq_sync(struct tg3 *tp)
3318{
3319 return tp->irq_sync;
3320}
3321
3322/* Fully shutdown all tg3 driver activity elsewhere in the system.
3323 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3324 * with as well. Most of the time, this is not necessary except when
3325 * shutting down the device.
3326 */
3327static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3328{
3329 if (irq_sync)
3330 tg3_irq_quiesce(tp);
3331 spin_lock_bh(&tp->lock);
3332 spin_lock(&tp->tx_lock);
3333}
3334
3335static inline void tg3_full_unlock(struct tg3 *tp)
3336{
3337 spin_unlock(&tp->tx_lock);
3338 spin_unlock_bh(&tp->lock);
3339}
3340
88b06bc2
MC		 3341/* MSI ISR - No need to check for interrupt sharing and no need to
3342 * flush status block and interrupt mailbox. PCI ordering rules
3343 * guarantee that MSI will arrive after the status block.
3344 */
3345static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3346{
3347 struct net_device *dev = dev_id;
3348 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3349
61487480
MC		 3350 prefetch(tp->hw_status);
3351 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3352 /*
fac9b83e 3353 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3354 * chip-internal interrupt pending events.
fac9b83e 3355 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3356 * NIC to stop sending us irqs, engaging "in-intr-handler"
3357 * event coalescing.
3358 */
3359 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3360 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3361 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3362
88b06bc2
MC		 3363 return IRQ_RETVAL(1);
3364}
3365
1da177e4
LT		 3366static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3367{
3368 struct net_device *dev = dev_id;
3369 struct tg3 *tp = netdev_priv(dev);
3370 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3371 unsigned int handled = 1;
3372
1da177e4
LT		 3373 /* In INTx mode, it is possible for the interrupt to arrive at
3374 * the CPU before the status block posted prior to the interrupt.
3375 * Reading the PCI State register will confirm whether the
3376 * interrupt is ours and will flush the status block.
3377 */
3378 if ((sblk->status & SD_STATUS_UPDATED) ||
3379 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3380 /*
fac9b83e 3381 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3382 * chip-internal interrupt pending events.
fac9b83e 3383 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3384 * NIC to stop sending us irqs, engaging "in-intr-handler"
3385 * event coalescing.
3386 */
3387 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3388 0x00000001);
f47c11ee
DM		 3389 if (tg3_irq_sync(tp))
3390 goto out;
fac9b83e 3391 sblk->status &= ~SD_STATUS_UPDATED;
61487480
MC		 3392 if (likely(tg3_has_work(tp))) {
3393 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
fac9b83e 3394 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3395 } else {
fac9b83e
DM		 3396 /* No work, shared interrupt perhaps? re-enable
3397 * interrupts, and flush that PCI write
3398 */
09ee929c 3399 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3400 0x00000000);
fac9b83e
DM		 3401 }
3402 } else { /* shared interrupt */
3403 handled = 0;
3404 }
f47c11ee 3405out:
fac9b83e
DM		 3406 return IRQ_RETVAL(handled);
3407}
3408
3409static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3410{
3411 struct net_device *dev = dev_id;
3412 struct tg3 *tp = netdev_priv(dev);
3413 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3414 unsigned int handled = 1;
3415
fac9b83e
DM		 3416 /* In INTx mode, it is possible for the interrupt to arrive at
3417 * the CPU before the status block posted prior to the interrupt.
3418 * Reading the PCI State register will confirm whether the
3419 * interrupt is ours and will flush the status block.
3420 */
38f3843e 3421 if ((sblk->status_tag != tp->last_tag) ||
fac9b83e 3422 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3423 /*
fac9b83e
DM		 3424 * writing any value to intr-mbox-0 clears PCI INTA# and
3425 * chip-internal interrupt pending events.
3426 * writing non-zero to intr-mbox-0 additional tells the
3427 * NIC to stop sending us irqs, engaging "in-intr-handler"
3428 * event coalescing.
1da177e4 3429 */
fac9b83e
DM		 3430 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3431 0x00000001);
f47c11ee
DM		 3432 if (tg3_irq_sync(tp))
3433 goto out;
38f3843e 3434 if (netif_rx_schedule_prep(dev)) {
61487480 3435 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
38f3843e
MC		 3436 /* Update last_tag to mark that this status has been
3437 * seen. Because interrupt may be shared, we may be
3438 * racing with tg3_poll(), so only update last_tag
3439 * if tg3_poll() is not scheduled.
1da177e4 3440 */
38f3843e
MC		 3441 tp->last_tag = sblk->status_tag;
3442 __netif_rx_schedule(dev);
1da177e4
LT		 3443 }
3444 } else { /* shared interrupt */
3445 handled = 0;
3446 }
f47c11ee 3447out:
1da177e4
LT		 3448 return IRQ_RETVAL(handled);
3449}
3450
7938109f
MC		 3451/* ISR for interrupt test */
3452static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3453 struct pt_regs *regs)
3454{
3455 struct net_device *dev = dev_id;
3456 struct tg3 *tp = netdev_priv(dev);
3457 struct tg3_hw_status *sblk = tp->hw_status;
3458
f9804ddb
MC		 3459 if ((sblk->status & SD_STATUS_UPDATED) ||
3460 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7938109f
MC		 3461 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3462 0x00000001);
3463 return IRQ_RETVAL(1);
3464 }
3465 return IRQ_RETVAL(0);
3466}
3467
1da177e4 3468static int tg3_init_hw(struct tg3 *);
944d980e 3469static int tg3_halt(struct tg3 *, int, int);
1da177e4
LT		 3470
3471#ifdef CONFIG_NET_POLL_CONTROLLER
3472static void tg3_poll_controller(struct net_device *dev)
3473{
88b06bc2
MC		 3474 struct tg3 *tp = netdev_priv(dev);
3475
3476 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3477}
3478#endif
3479
3480static void tg3_reset_task(void *_data)
3481{
3482 struct tg3 *tp = _data;
3483 unsigned int restart_timer;
3484
3485 tg3_netif_stop(tp);
3486
f47c11ee 3487 tg3_full_lock(tp, 1);
1da177e4
LT		 3488
3489 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3490 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3491
944d980e 3492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
1da177e4
LT		 3493 tg3_init_hw(tp);
3494
3495 tg3_netif_start(tp);
3496
f47c11ee 3497 tg3_full_unlock(tp);
1da177e4
LT		 3498
3499 if (restart_timer)
3500 mod_timer(&tp->timer, jiffies + 1);
3501}
3502
3503static void tg3_tx_timeout(struct net_device *dev)
3504{
3505 struct tg3 *tp = netdev_priv(dev);
3506
3507 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3508 dev->name);
3509
3510 schedule_work(&tp->reset_task);
3511}
3512
c58ec932
MC		 3513/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3514static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3515{
3516 u32 base = (u32) mapping & 0xffffffff;
3517
3518 return ((base > 0xffffdcc0) &&
3519 (base + len + 8 < base));
3520}
3521
1da177e4
LT		 3522static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3523
3524static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3525 u32 last_plus_one, u32 *start,
3526 u32 base_flags, u32 mss)
1da177e4
LT		 3527{
3528 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3529 dma_addr_t new_addr = 0;
1da177e4 3530 u32 entry = *start;
c58ec932 3531 int i, ret = 0;
1da177e4
LT		 3532
3533 if (!new_skb) {
c58ec932
MC		 3534 ret = -1;
3535 } else {
3536 /* New SKB is guaranteed to be linear. */
3537 entry = *start;
3538 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3539 PCI_DMA_TODEVICE);
3540 /* Make sure new skb does not cross any 4G boundaries.
3541 * Drop the packet if it does.
3542 */
3543 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3544 ret = -1;
3545 dev_kfree_skb(new_skb);
3546 new_skb = NULL;
3547 } else {
3548 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3549 base_flags, 1 | (mss << 1));
3550 *start = NEXT_TX(entry);
3551 }
1da177e4
LT		 3552 }
3553
1da177e4
LT		 3554 /* Now clean up the sw ring entries. */
3555 i = 0;
3556 while (entry != last_plus_one) {
3557 int len;
3558
3559 if (i == 0)
3560 len = skb_headlen(skb);
3561 else
3562 len = skb_shinfo(skb)->frags[i-1].size;
3563 pci_unmap_single(tp->pdev,
3564 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3565 len, PCI_DMA_TODEVICE);
3566 if (i == 0) {
3567 tp->tx_buffers[entry].skb = new_skb;
3568 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3569 } else {
3570 tp->tx_buffers[entry].skb = NULL;
3571 }
3572 entry = NEXT_TX(entry);
3573 i++;
3574 }
3575
3576 dev_kfree_skb(skb);
3577
c58ec932 3578 return ret;
1da177e4
LT		 3579}
3580
3581static void tg3_set_txd(struct tg3 *tp, int entry,
3582 dma_addr_t mapping, int len, u32 flags,
3583 u32 mss_and_is_end)
3584{
3585 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3586 int is_end = (mss_and_is_end & 0x1);
3587 u32 mss = (mss_and_is_end >> 1);
3588 u32 vlan_tag = 0;
3589
3590 if (is_end)
3591 flags |= TXD_FLAG_END;
3592 if (flags & TXD_FLAG_VLAN) {
3593 vlan_tag = flags >> 16;
3594 flags &= 0xffff;
3595 }
3596 vlan_tag |= (mss << TXD_MSS_SHIFT);
3597
3598 txd->addr_hi = ((u64) mapping >> 32);
3599 txd->addr_lo = ((u64) mapping & 0xffffffff);
3600 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3601 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3602}
3603
1da177e4
LT		 3604static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3605{
3606 struct tg3 *tp = netdev_priv(dev);
3607 dma_addr_t mapping;
1da177e4
LT		 3608 u32 len, entry, base_flags, mss;
3609 int would_hit_hwbug;
1da177e4
LT		 3610
3611 len = skb_headlen(skb);
3612
3613 /* No BH disabling for tx_lock here. We are running in BH disabled
3614 * context and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 3615 * interrupt. Furthermore, IRQ processing runs lockless so we have
3616 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 3617 */
f47c11ee 3618 if (!spin_trylock(&tp->tx_lock))
1da177e4 3619 return NETDEV_TX_LOCKED;
1da177e4 3620
1da177e4 3621 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 3622 if (!netif_queue_stopped(dev)) {
3623 netif_stop_queue(dev);
3624
3625 /* This is a hard error, log it. */
3626 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3627 "queue awake!\n", dev->name);
3628 }
f47c11ee 3629 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3630 return NETDEV_TX_BUSY;
3631 }
3632
3633 entry = tp->tx_prod;
3634 base_flags = 0;
3635 if (skb->ip_summed == CHECKSUM_HW)
3636 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3637#if TG3_TSO_SUPPORT != 0
3638 mss = 0;
3639 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3640 (mss = skb_shinfo(skb)->tso_size) != 0) {
3641 int tcp_opt_len, ip_tcp_len;
3642
3643 if (skb_header_cloned(skb) &&
3644 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3645 dev_kfree_skb(skb);
3646 goto out_unlock;
3647 }
3648
3649 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3650 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3651
3652 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3653 TXD_FLAG_CPU_POST_DMA);
3654
3655 skb->nh.iph->check = 0;
fd30333d 3656 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
1da177e4
LT		 3657 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3658 skb->h.th->check = 0;
3659 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3660 }
3661 else {
3662 skb->h.th->check =
3663 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3664 skb->nh.iph->daddr,
3665 0, IPPROTO_TCP, 0);
3666 }
3667
3668 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3669 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3670 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3671 int tsflags;
3672
3673 tsflags = ((skb->nh.iph->ihl - 5) +
3674 (tcp_opt_len >> 2));
3675 mss |= (tsflags << 11);
3676 }
3677 } else {
3678 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3679 int tsflags;
3680
3681 tsflags = ((skb->nh.iph->ihl - 5) +
3682 (tcp_opt_len >> 2));
3683 base_flags |= tsflags << 12;
3684 }
3685 }
3686 }
3687#else
3688 mss = 0;
3689#endif
3690#if TG3_VLAN_TAG_USED
3691 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3692 base_flags |= (TXD_FLAG_VLAN |
3693 (vlan_tx_tag_get(skb) << 16));
3694#endif
3695
3696 /* Queue skb data, a.k.a. the main skb fragment. */
3697 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3698
3699 tp->tx_buffers[entry].skb = skb;
3700 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3701
3702 would_hit_hwbug = 0;
3703
3704 if (tg3_4g_overflow_test(mapping, len))
c58ec932 3705 would_hit_hwbug = 1;
1da177e4
LT		 3706
3707 tg3_set_txd(tp, entry, mapping, len, base_flags,
3708 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3709
3710 entry = NEXT_TX(entry);
3711
3712 /* Now loop through additional data fragments, and queue them. */
3713 if (skb_shinfo(skb)->nr_frags > 0) {
3714 unsigned int i, last;
3715
3716 last = skb_shinfo(skb)->nr_frags - 1;
3717 for (i = 0; i <= last; i++) {
3718 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3719
3720 len = frag->size;
3721 mapping = pci_map_page(tp->pdev,
3722 frag->page,
3723 frag->page_offset,
3724 len, PCI_DMA_TODEVICE);
3725
3726 tp->tx_buffers[entry].skb = NULL;
3727 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3728
c58ec932
MC		 3729 if (tg3_4g_overflow_test(mapping, len))
3730 would_hit_hwbug = 1;
1da177e4
LT		 3731
3732 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3733 tg3_set_txd(tp, entry, mapping, len,
3734 base_flags, (i == last)|(mss << 1));
3735 else
3736 tg3_set_txd(tp, entry, mapping, len,
3737 base_flags, (i == last));
3738
3739 entry = NEXT_TX(entry);
3740 }
3741 }
3742
3743 if (would_hit_hwbug) {
3744 u32 last_plus_one = entry;
3745 u32 start;
1da177e4 3746
c58ec932
MC		 3747 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3748 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 3749
3750 /* If the workaround fails due to memory/mapping
3751 * failure, silently drop this packet.
3752 */
c58ec932
MC		 3753 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one,
3754 &start, base_flags, mss))
1da177e4
LT		 3755 goto out_unlock;
3756
3757 entry = start;
3758 }
3759
3760 /* Packets are ready, update Tx producer idx local and on card. */
3761 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3762
3763 tp->tx_prod = entry;
51b91468 3764 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
1da177e4 3765 netif_stop_queue(dev);
51b91468
MC		 3766 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3767 netif_wake_queue(tp->dev);
3768 }
1da177e4
LT		 3769
3770out_unlock:
3771 mmiowb();
f47c11ee 3772 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3773
3774 dev->trans_start = jiffies;
3775
3776 return NETDEV_TX_OK;
3777}
3778
3779static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3780 int new_mtu)
3781{
3782 dev->mtu = new_mtu;
3783
ef7f5ec0 3784 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 3785 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 3786 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3787 ethtool_op_set_tso(dev, 0);
3788 }
3789 else
3790 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3791 } else {
a4e2b347 3792 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 3793 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 3794 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 3795 }
1da177e4
LT		 3796}
3797
3798static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3799{
3800 struct tg3 *tp = netdev_priv(dev);
3801
3802 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3803 return -EINVAL;
3804
3805 if (!netif_running(dev)) {
3806 /* We'll just catch it later when the
3807 * device is up'd.
3808 */
3809 tg3_set_mtu(dev, tp, new_mtu);
3810 return 0;
3811 }
3812
3813 tg3_netif_stop(tp);
f47c11ee
DM		 3814
3815 tg3_full_lock(tp, 1);
1da177e4 3816
944d980e 3817 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 3818
3819 tg3_set_mtu(dev, tp, new_mtu);
3820
3821 tg3_init_hw(tp);
3822
3823 tg3_netif_start(tp);
3824
f47c11ee 3825 tg3_full_unlock(tp);
1da177e4
LT		 3826
3827 return 0;
3828}
3829
3830/* Free up pending packets in all rx/tx rings.
3831 *
3832 * The chip has been shut down and the driver detached from
3833 * the networking, so no interrupts or new tx packets will
3834 * end up in the driver. tp->{tx,}lock is not held and we are not
3835 * in an interrupt context and thus may sleep.
3836 */
3837static void tg3_free_rings(struct tg3 *tp)
3838{
3839 struct ring_info *rxp;
3840 int i;
3841
3842 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3843 rxp = &tp->rx_std_buffers[i];
3844
3845 if (rxp->skb == NULL)
3846 continue;
3847 pci_unmap_single(tp->pdev,
3848 pci_unmap_addr(rxp, mapping),
7e72aad4 3849 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 3850 PCI_DMA_FROMDEVICE);
3851 dev_kfree_skb_any(rxp->skb);
3852 rxp->skb = NULL;
3853 }
3854
3855 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3856 rxp = &tp->rx_jumbo_buffers[i];
3857
3858 if (rxp->skb == NULL)
3859 continue;
3860 pci_unmap_single(tp->pdev,
3861 pci_unmap_addr(rxp, mapping),
3862 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3863 PCI_DMA_FROMDEVICE);
3864 dev_kfree_skb_any(rxp->skb);
3865 rxp->skb = NULL;
3866 }
3867
3868 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3869 struct tx_ring_info *txp;
3870 struct sk_buff *skb;
3871 int j;
3872
3873 txp = &tp->tx_buffers[i];
3874 skb = txp->skb;
3875
3876 if (skb == NULL) {
3877 i++;
3878 continue;
3879 }
3880
3881 pci_unmap_single(tp->pdev,
3882 pci_unmap_addr(txp, mapping),
3883 skb_headlen(skb),
3884 PCI_DMA_TODEVICE);
3885 txp->skb = NULL;
3886
3887 i++;
3888
3889 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3890 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3891 pci_unmap_page(tp->pdev,
3892 pci_unmap_addr(txp, mapping),
3893 skb_shinfo(skb)->frags[j].size,
3894 PCI_DMA_TODEVICE);
3895 i++;
3896 }
3897
3898 dev_kfree_skb_any(skb);
3899 }
3900}
3901
3902/* Initialize tx/rx rings for packet processing.
3903 *
3904 * The chip has been shut down and the driver detached from
3905 * the networking, so no interrupts or new tx packets will
3906 * end up in the driver. tp->{tx,}lock are held and thus
3907 * we may not sleep.
3908 */
3909static void tg3_init_rings(struct tg3 *tp)
3910{
3911 u32 i;
3912
3913 /* Free up all the SKBs. */
3914 tg3_free_rings(tp);
3915
3916 /* Zero out all descriptors. */
3917 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3918 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3919 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3920 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3921
7e72aad4 3922 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 3923 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 3924 (tp->dev->mtu > ETH_DATA_LEN))
3925 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3926
1da177e4
LT		 3927 /* Initialize invariants of the rings, we only set this
3928 * stuff once. This works because the card does not
3929 * write into the rx buffer posting rings.
3930 */
3931 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3932 struct tg3_rx_buffer_desc *rxd;
3933
3934 rxd = &tp->rx_std[i];
7e72aad4 3935 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 3936 << RXD_LEN_SHIFT;
3937 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3938 rxd->opaque = (RXD_OPAQUE_RING_STD |
3939 (i << RXD_OPAQUE_INDEX_SHIFT));
3940 }
3941
0f893dc6 3942 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3943 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3944 struct tg3_rx_buffer_desc *rxd;
3945
3946 rxd = &tp->rx_jumbo[i];
3947 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3948 << RXD_LEN_SHIFT;
3949 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3950 RXD_FLAG_JUMBO;
3951 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3952 (i << RXD_OPAQUE_INDEX_SHIFT));
3953 }
3954 }
3955
3956 /* Now allocate fresh SKBs for each rx ring. */
3957 for (i = 0; i < tp->rx_pending; i++) {
3958 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3959 -1, i) < 0)
3960 break;
3961 }
3962
0f893dc6 3963 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3964 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3965 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3966 -1, i) < 0)
3967 break;
3968 }
3969 }
3970}
3971
3972/*
3973 * Must not be invoked with interrupt sources disabled and
3974 * the hardware shutdown down.
3975 */
3976static void tg3_free_consistent(struct tg3 *tp)
3977{
b4558ea9
JJ		 3978 kfree(tp->rx_std_buffers);
3979 tp->rx_std_buffers = NULL;
1da177e4
LT		 3980 if (tp->rx_std) {
3981 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3982 tp->rx_std, tp->rx_std_mapping);
3983 tp->rx_std = NULL;
3984 }
3985 if (tp->rx_jumbo) {
3986 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3987 tp->rx_jumbo, tp->rx_jumbo_mapping);
3988 tp->rx_jumbo = NULL;
3989 }
3990 if (tp->rx_rcb) {
3991 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3992 tp->rx_rcb, tp->rx_rcb_mapping);
3993 tp->rx_rcb = NULL;
3994 }
3995 if (tp->tx_ring) {
3996 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3997 tp->tx_ring, tp->tx_desc_mapping);
3998 tp->tx_ring = NULL;
3999 }
4000 if (tp->hw_status) {
4001 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4002 tp->hw_status, tp->status_mapping);
4003 tp->hw_status = NULL;
4004 }
4005 if (tp->hw_stats) {
4006 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4007 tp->hw_stats, tp->stats_mapping);
4008 tp->hw_stats = NULL;
4009 }
4010}
4011
4012/*
4013 * Must not be invoked with interrupt sources disabled and
4014 * the hardware shutdown down. Can sleep.
4015 */
4016static int tg3_alloc_consistent(struct tg3 *tp)
4017{
4018 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4019 (TG3_RX_RING_SIZE +
4020 TG3_RX_JUMBO_RING_SIZE)) +
4021 (sizeof(struct tx_ring_info) *
4022 TG3_TX_RING_SIZE),
4023 GFP_KERNEL);
4024 if (!tp->rx_std_buffers)
4025 return -ENOMEM;
4026
4027 memset(tp->rx_std_buffers, 0,
4028 (sizeof(struct ring_info) *
4029 (TG3_RX_RING_SIZE +
4030 TG3_RX_JUMBO_RING_SIZE)) +
4031 (sizeof(struct tx_ring_info) *
4032 TG3_TX_RING_SIZE));
4033
4034 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4035 tp->tx_buffers = (struct tx_ring_info *)
4036 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4037
4038 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4039 &tp->rx_std_mapping);
4040 if (!tp->rx_std)
4041 goto err_out;
4042
4043 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4044 &tp->rx_jumbo_mapping);
4045
4046 if (!tp->rx_jumbo)
4047 goto err_out;
4048
4049 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4050 &tp->rx_rcb_mapping);
4051 if (!tp->rx_rcb)
4052 goto err_out;
4053
4054 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4055 &tp->tx_desc_mapping);
4056 if (!tp->tx_ring)
4057 goto err_out;
4058
4059 tp->hw_status = pci_alloc_consistent(tp->pdev,
4060 TG3_HW_STATUS_SIZE,
4061 &tp->status_mapping);
4062 if (!tp->hw_status)
4063 goto err_out;
4064
4065 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4066 sizeof(struct tg3_hw_stats),
4067 &tp->stats_mapping);
4068 if (!tp->hw_stats)
4069 goto err_out;
4070
4071 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4072 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4073
4074 return 0;
4075
4076err_out:
4077 tg3_free_consistent(tp);
4078 return -ENOMEM;
4079}
4080
4081#define MAX_WAIT_CNT 1000
4082
4083/* To stop a block, clear the enable bit and poll till it
4084 * clears. tp->lock is held.
4085 */
b3b7d6be 4086static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4087{
4088 unsigned int i;
4089 u32 val;
4090
4091 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4092 switch (ofs) {
4093 case RCVLSC_MODE:
4094 case DMAC_MODE:
4095 case MBFREE_MODE:
4096 case BUFMGR_MODE:
4097 case MEMARB_MODE:
4098 /* We can't enable/disable these bits of the
4099 * 5705/5750, just say success.
4100 */
4101 return 0;
4102
4103 default:
4104 break;
4105 };
4106 }
4107
4108 val = tr32(ofs);
4109 val &= ~enable_bit;
4110 tw32_f(ofs, val);
4111
4112 for (i = 0; i < MAX_WAIT_CNT; i++) {
4113 udelay(100);
4114 val = tr32(ofs);
4115 if ((val & enable_bit) == 0)
4116 break;
4117 }
4118
b3b7d6be 4119 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4120 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4121 "ofs=%lx enable_bit=%x\n",
4122 ofs, enable_bit);
4123 return -ENODEV;
4124 }
4125
4126 return 0;
4127}
4128
4129/* tp->lock is held. */
b3b7d6be 4130static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4131{
4132 int i, err;
4133
4134 tg3_disable_ints(tp);
4135
4136 tp->rx_mode &= ~RX_MODE_ENABLE;
4137 tw32_f(MAC_RX_MODE, tp->rx_mode);
4138 udelay(10);
4139
b3b7d6be
DM		 4140 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4141 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4142 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4143 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4144 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4145 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4146
4147 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4148 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4149 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4150 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4151 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4152 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4153 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4154
4155 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4156 tw32_f(MAC_MODE, tp->mac_mode);
4157 udelay(40);
4158
4159 tp->tx_mode &= ~TX_MODE_ENABLE;
4160 tw32_f(MAC_TX_MODE, tp->tx_mode);
4161
4162 for (i = 0; i < MAX_WAIT_CNT; i++) {
4163 udelay(100);
4164 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4165 break;
4166 }
4167 if (i >= MAX_WAIT_CNT) {
4168 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4169 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4170 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4171 err |= -ENODEV;
1da177e4
LT		 4172 }
4173
e6de8ad1 4174 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4175 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4176 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4177
4178 tw32(FTQ_RESET, 0xffffffff);
4179 tw32(FTQ_RESET, 0x00000000);
4180
b3b7d6be
DM		 4181 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4182 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4183
4184 if (tp->hw_status)
4185 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4186 if (tp->hw_stats)
4187 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4188
1da177e4
LT		 4189 return err;
4190}
4191
4192/* tp->lock is held. */
4193static int tg3_nvram_lock(struct tg3 *tp)
4194{
4195 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4196 int i;
4197
ec41c7df
MC		 4198 if (tp->nvram_lock_cnt == 0) {
4199 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4200 for (i = 0; i < 8000; i++) {
4201 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4202 break;
4203 udelay(20);
4204 }
4205 if (i == 8000) {
4206 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4207 return -ENODEV;
4208 }
1da177e4 4209 }
ec41c7df 4210 tp->nvram_lock_cnt++;
1da177e4
LT		 4211 }
4212 return 0;
4213}
4214
4215/* tp->lock is held. */
4216static void tg3_nvram_unlock(struct tg3 *tp)
4217{
ec41c7df
MC		 4218 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4219 if (tp->nvram_lock_cnt > 0)
4220 tp->nvram_lock_cnt--;
4221 if (tp->nvram_lock_cnt == 0)
4222 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4223 }
1da177e4
LT		 4224}
4225
e6af301b
MC		 4226/* tp->lock is held. */
4227static void tg3_enable_nvram_access(struct tg3 *tp)
4228{
4229 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4230 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4231 u32 nvaccess = tr32(NVRAM_ACCESS);
4232
4233 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4234 }
4235}
4236
4237/* tp->lock is held. */
4238static void tg3_disable_nvram_access(struct tg3 *tp)
4239{
4240 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4241 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4242 u32 nvaccess = tr32(NVRAM_ACCESS);
4243
4244 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4245 }
4246}
4247
1da177e4
LT		 4248/* tp->lock is held. */
4249static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4250{
4251 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4252 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4253 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4254
4255 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4256 switch (kind) {
4257 case RESET_KIND_INIT:
4258 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4259 DRV_STATE_START);
4260 break;
4261
4262 case RESET_KIND_SHUTDOWN:
4263 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4264 DRV_STATE_UNLOAD);
4265 break;
4266
4267 case RESET_KIND_SUSPEND:
4268 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4269 DRV_STATE_SUSPEND);
4270 break;
4271
4272 default:
4273 break;
4274 };
4275 }
4276}
4277
4278/* tp->lock is held. */
4279static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4280{
4281 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4282 switch (kind) {
4283 case RESET_KIND_INIT:
4284 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4285 DRV_STATE_START_DONE);
4286 break;
4287
4288 case RESET_KIND_SHUTDOWN:
4289 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4290 DRV_STATE_UNLOAD_DONE);
4291 break;
4292
4293 default:
4294 break;
4295 };
4296 }
4297}
4298
4299/* tp->lock is held. */
4300static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4301{
4302 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4303 switch (kind) {
4304 case RESET_KIND_INIT:
4305 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4306 DRV_STATE_START);
4307 break;
4308
4309 case RESET_KIND_SHUTDOWN:
4310 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4311 DRV_STATE_UNLOAD);
4312 break;
4313
4314 case RESET_KIND_SUSPEND:
4315 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4316 DRV_STATE_SUSPEND);
4317 break;
4318
4319 default:
4320 break;
4321 };
4322 }
4323}
4324
4325static void tg3_stop_fw(struct tg3 *);
4326
4327/* tp->lock is held. */
4328static int tg3_chip_reset(struct tg3 *tp)
4329{
4330 u32 val;
1ee582d8 4331 void (*write_op)(struct tg3 *, u32, u32);
1da177e4
LT		 4332 int i;
4333
ec41c7df 4334 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
1da177e4 4335 tg3_nvram_lock(tp);
ec41c7df
MC		 4336 /* No matching tg3_nvram_unlock() after this because
4337 * chip reset below will undo the nvram lock.
4338 */
4339 tp->nvram_lock_cnt = 0;
4340 }
1da177e4
LT		 4341
4342 /*
4343 * We must avoid the readl() that normally takes place.
4344 * It locks machines, causes machine checks, and other
4345 * fun things. So, temporarily disable the 5701
4346 * hardware workaround, while we do the reset.
4347 */
1ee582d8
MC		 4348 write_op = tp->write32;
4349 if (write_op == tg3_write_flush_reg32)
4350 tp->write32 = tg3_write32;
1da177e4
LT		 4351
4352 /* do the reset */
4353 val = GRC_MISC_CFG_CORECLK_RESET;
4354
4355 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4356 if (tr32(0x7e2c) == 0x60) {
4357 tw32(0x7e2c, 0x20);
4358 }
4359 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4360 tw32(GRC_MISC_CFG, (1 << 29));
4361 val |= (1 << 29);
4362 }
4363 }
4364
4365 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4366 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4367 tw32(GRC_MISC_CFG, val);
4368
1ee582d8
MC		 4369 /* restore 5701 hardware bug workaround write method */
4370 tp->write32 = write_op;
1da177e4
LT		 4371
4372 /* Unfortunately, we have to delay before the PCI read back.
4373 * Some 575X chips even will not respond to a PCI cfg access
4374 * when the reset command is given to the chip.
4375 *
4376 * How do these hardware designers expect things to work
4377 * properly if the PCI write is posted for a long period
4378 * of time? It is always necessary to have some method by
4379 * which a register read back can occur to push the write
4380 * out which does the reset.
4381 *
4382 * For most tg3 variants the trick below was working.
4383 * Ho hum...
4384 */
4385 udelay(120);
4386
4387 /* Flush PCI posted writes. The normal MMIO registers
4388 * are inaccessible at this time so this is the only
4389 * way to make this reliably (actually, this is no longer
4390 * the case, see above). I tried to use indirect
4391 * register read/write but this upset some 5701 variants.
4392 */
4393 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4394
4395 udelay(120);
4396
4397 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4398 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4399 int i;
4400 u32 cfg_val;
4401
4402 /* Wait for link training to complete. */
4403 for (i = 0; i < 5000; i++)
4404 udelay(100);
4405
4406 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4407 pci_write_config_dword(tp->pdev, 0xc4,
4408 cfg_val | (1 << 15));
4409 }
4410 /* Set PCIE max payload size and clear error status. */
4411 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4412 }
4413
4414 /* Re-enable indirect register accesses. */
4415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4416 tp->misc_host_ctrl);
4417
4418 /* Set MAX PCI retry to zero. */
4419 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4420 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4421 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4422 val |= PCISTATE_RETRY_SAME_DMA;
4423 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4424
4425 pci_restore_state(tp->pdev);
4426
4427 /* Make sure PCI-X relaxed ordering bit is clear. */
4428 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4429 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4430 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4431
a4e2b347 4432 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4433 u32 val;
4434
4435 /* Chip reset on 5780 will reset MSI enable bit,
4436 * so need to restore it.
4437 */
4438 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4439 u16 ctrl;
4440
4441 pci_read_config_word(tp->pdev,
4442 tp->msi_cap + PCI_MSI_FLAGS,
4443 &ctrl);
4444 pci_write_config_word(tp->pdev,
4445 tp->msi_cap + PCI_MSI_FLAGS,
4446 ctrl | PCI_MSI_FLAGS_ENABLE);
4447 val = tr32(MSGINT_MODE);
4448 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4449 }
4450
4451 val = tr32(MEMARB_MODE);
4452 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4453
4454 } else
4455 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4456
4457 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4458 tg3_stop_fw(tp);
4459 tw32(0x5000, 0x400);
4460 }
4461
4462 tw32(GRC_MODE, tp->grc_mode);
4463
4464 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4465 u32 val = tr32(0xc4);
4466
4467 tw32(0xc4, val | (1 << 15));
4468 }
4469
4470 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4472 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4473 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4474 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4475 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4476 }
4477
4478 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4479 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4480 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4481 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4482 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4483 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4484 } else
4485 tw32_f(MAC_MODE, 0);
4486 udelay(40);
4487
4488 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4489 /* Wait for firmware initialization to complete. */
4490 for (i = 0; i < 100000; i++) {
4491 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4492 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4493 break;
4494 udelay(10);
4495 }
4496 if (i >= 100000) {
4497 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4498 "firmware will not restart magic=%08x\n",
4499 tp->dev->name, val);
4500 return -ENODEV;
4501 }
4502 }
4503
4504 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4505 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4506 u32 val = tr32(0x7c00);
4507
4508 tw32(0x7c00, val | (1 << 25));
4509 }
4510
4511 /* Reprobe ASF enable state. */
4512 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4513 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4514 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4515 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4516 u32 nic_cfg;
4517
4518 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4519 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4520 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4521 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4522 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4523 }
4524 }
4525
4526 return 0;
4527}
4528
4529/* tp->lock is held. */
4530static void tg3_stop_fw(struct tg3 *tp)
4531{
4532 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4533 u32 val;
4534 int i;
4535
4536 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4537 val = tr32(GRC_RX_CPU_EVENT);
4538 val |= (1 << 14);
4539 tw32(GRC_RX_CPU_EVENT, val);
4540
4541 /* Wait for RX cpu to ACK the event. */
4542 for (i = 0; i < 100; i++) {
4543 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4544 break;
4545 udelay(1);
4546 }
4547 }
4548}
4549
4550/* tp->lock is held. */
944d980e 4551static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4552{
4553 int err;
4554
4555 tg3_stop_fw(tp);
4556
944d980e 4557 tg3_write_sig_pre_reset(tp, kind);
1da177e4 4558
b3b7d6be 4559 tg3_abort_hw(tp, silent);
1da177e4
LT		 4560 err = tg3_chip_reset(tp);
4561
944d980e
MC		 4562 tg3_write_sig_legacy(tp, kind);
4563 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 4564
4565 if (err)
4566 return err;
4567
4568 return 0;
4569}
4570
4571#define TG3_FW_RELEASE_MAJOR 0x0
4572#define TG3_FW_RELASE_MINOR 0x0
4573#define TG3_FW_RELEASE_FIX 0x0
4574#define TG3_FW_START_ADDR 0x08000000
4575#define TG3_FW_TEXT_ADDR 0x08000000
4576#define TG3_FW_TEXT_LEN 0x9c0
4577#define TG3_FW_RODATA_ADDR 0x080009c0
4578#define TG3_FW_RODATA_LEN 0x60
4579#define TG3_FW_DATA_ADDR 0x08000a40
4580#define TG3_FW_DATA_LEN 0x20
4581#define TG3_FW_SBSS_ADDR 0x08000a60
4582#define TG3_FW_SBSS_LEN 0xc
4583#define TG3_FW_BSS_ADDR 0x08000a70
4584#define TG3_FW_BSS_LEN 0x10
4585
4586static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4587 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4588 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4589 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4590 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4591 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4592 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4593 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4594 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4595 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4596 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4597 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4598 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4599 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4600 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4601 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4602 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4603 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4604 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4605 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4606 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4607 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4608 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4609 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4612 0, 0, 0, 0, 0, 0,
4613 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4614 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4615 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4616 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4617 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4618 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4619 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4620 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4621 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4622 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4623 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4625 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4627 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4628 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4629 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4630 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4631 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4632 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4633 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4634 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4635 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4636 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4637 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4638 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4639 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4640 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4641 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4642 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4643 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4644 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4645 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4646 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4647 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4648 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4649 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4650 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4651 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4652 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4653 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4654 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4655 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4656 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4657 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4658 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4659 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4660 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4661 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4662 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4663 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4664 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4665 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4666 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4667 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4668 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4669 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4670 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4671 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4672 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4673 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4674 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4675 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4676 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4677 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4678};
4679
4680static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4681 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4682 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4683 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4684 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4685 0x00000000
4686};
4687
4688#if 0 /* All zeros, don't eat up space with it. */
4689u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4690 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4691 0x00000000, 0x00000000, 0x00000000, 0x00000000
4692};
4693#endif
4694
4695#define RX_CPU_SCRATCH_BASE 0x30000
4696#define RX_CPU_SCRATCH_SIZE 0x04000
4697#define TX_CPU_SCRATCH_BASE 0x34000
4698#define TX_CPU_SCRATCH_SIZE 0x04000
4699
4700/* tp->lock is held. */
4701static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4702{
4703 int i;
4704
4705 if (offset == TX_CPU_BASE &&
4706 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4707 BUG();
4708
4709 if (offset == RX_CPU_BASE) {
4710 for (i = 0; i < 10000; i++) {
4711 tw32(offset + CPU_STATE, 0xffffffff);
4712 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4713 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4714 break;
4715 }
4716
4717 tw32(offset + CPU_STATE, 0xffffffff);
4718 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4719 udelay(10);
4720 } else {
4721 for (i = 0; i < 10000; i++) {
4722 tw32(offset + CPU_STATE, 0xffffffff);
4723 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4724 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4725 break;
4726 }
4727 }
4728
4729 if (i >= 10000) {
4730 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4731 "and %s CPU\n",
4732 tp->dev->name,
4733 (offset == RX_CPU_BASE ? "RX" : "TX"));
4734 return -ENODEV;
4735 }
ec41c7df
MC		 4736
4737 /* Clear firmware's nvram arbitration. */
4738 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4739 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 4740 return 0;
4741}
4742
4743struct fw_info {
4744 unsigned int text_base;
4745 unsigned int text_len;
4746 u32 *text_data;
4747 unsigned int rodata_base;
4748 unsigned int rodata_len;
4749 u32 *rodata_data;
4750 unsigned int data_base;
4751 unsigned int data_len;
4752 u32 *data_data;
4753};
4754
4755/* tp->lock is held. */
4756static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4757 int cpu_scratch_size, struct fw_info *info)
4758{
ec41c7df 4759 int err, lock_err, i;
1da177e4
LT		 4760 void (*write_op)(struct tg3 *, u32, u32);
4761
4762 if (cpu_base == TX_CPU_BASE &&
4763 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4764 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4765 "TX cpu firmware on %s which is 5705.\n",
4766 tp->dev->name);
4767 return -EINVAL;
4768 }
4769
4770 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4771 write_op = tg3_write_mem;
4772 else
4773 write_op = tg3_write_indirect_reg32;
4774
1b628151
MC		 4775 /* It is possible that bootcode is still loading at this point.
4776 * Get the nvram lock first before halting the cpu.
4777 */
ec41c7df 4778 lock_err = tg3_nvram_lock(tp);
1da177e4 4779 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 4780 if (!lock_err)
4781 tg3_nvram_unlock(tp);
1da177e4
LT		 4782 if (err)
4783 goto out;
4784
4785 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4786 write_op(tp, cpu_scratch_base + i, 0);
4787 tw32(cpu_base + CPU_STATE, 0xffffffff);
4788 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4789 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4790 write_op(tp, (cpu_scratch_base +
4791 (info->text_base & 0xffff) +
4792 (i * sizeof(u32))),
4793 (info->text_data ?
4794 info->text_data[i] : 0));
4795 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4796 write_op(tp, (cpu_scratch_base +
4797 (info->rodata_base & 0xffff) +
4798 (i * sizeof(u32))),
4799 (info->rodata_data ?
4800 info->rodata_data[i] : 0));
4801 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4802 write_op(tp, (cpu_scratch_base +
4803 (info->data_base & 0xffff) +
4804 (i * sizeof(u32))),
4805 (info->data_data ?
4806 info->data_data[i] : 0));
4807
4808 err = 0;
4809
4810out:
1da177e4
LT		 4811 return err;
4812}
4813
4814/* tp->lock is held. */
4815static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4816{
4817 struct fw_info info;
4818 int err, i;
4819
4820 info.text_base = TG3_FW_TEXT_ADDR;
4821 info.text_len = TG3_FW_TEXT_LEN;
4822 info.text_data = &tg3FwText[0];
4823 info.rodata_base = TG3_FW_RODATA_ADDR;
4824 info.rodata_len = TG3_FW_RODATA_LEN;
4825 info.rodata_data = &tg3FwRodata[0];
4826 info.data_base = TG3_FW_DATA_ADDR;
4827 info.data_len = TG3_FW_DATA_LEN;
4828 info.data_data = NULL;
4829
4830 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4831 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4832 &info);
4833 if (err)
4834 return err;
4835
4836 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4837 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4838 &info);
4839 if (err)
4840 return err;
4841
4842 /* Now startup only the RX cpu. */
4843 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4844 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4845
4846 for (i = 0; i < 5; i++) {
4847 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4848 break;
4849 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4850 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4851 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4852 udelay(1000);
4853 }
4854 if (i >= 5) {
4855 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4856 "to set RX CPU PC, is %08x should be %08x\n",
4857 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4858 TG3_FW_TEXT_ADDR);
4859 return -ENODEV;
4860 }
4861 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4862 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4863
4864 return 0;
4865}
4866
4867#if TG3_TSO_SUPPORT != 0
4868
4869#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4870#define TG3_TSO_FW_RELASE_MINOR 0x6
4871#define TG3_TSO_FW_RELEASE_FIX 0x0
4872#define TG3_TSO_FW_START_ADDR 0x08000000
4873#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4874#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4875#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4876#define TG3_TSO_FW_RODATA_LEN 0x60
4877#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4878#define TG3_TSO_FW_DATA_LEN 0x30
4879#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4880#define TG3_TSO_FW_SBSS_LEN 0x2c
4881#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4882#define TG3_TSO_FW_BSS_LEN 0x894
4883
4884static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4885 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4886 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4887 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4888 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4889 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4890 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4891 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4892 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4893 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4894 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4895 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4896 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4897 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4898 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4899 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4900 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4901 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4902 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4903 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4904 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4905 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4906 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4907 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4908 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4909 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4910 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4911 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4912 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4913 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4914 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4915 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4916 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4917 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4918 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4919 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4920 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4921 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4922 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4923 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4924 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4925 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4926 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4927 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4928 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4929 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4930 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4931 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4932 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4933 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4934 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4935 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4936 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4937 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4938 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4939 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4940 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4941 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4942 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4943 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4944 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4945 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4946 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4947 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4948 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4949 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4950 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4951 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4952 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4953 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4954 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4955 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4956 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4957 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4958 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4959 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4960 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4961 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4962 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4963 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4964 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4965 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4966 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4967 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4968 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4969 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4970 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4971 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4972 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4973 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4974 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4975 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4976 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4977 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4978 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4979 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4980 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4981 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4982 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4983 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4984 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4985 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4986 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4987 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4988 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4989 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4990 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4991 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4992 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4993 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4994 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4995 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4996 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4997 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4998 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4999 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5000 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5001 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5002 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5003 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5004 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5005 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5006 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5007 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5008 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5009 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5010 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5011 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5012 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5013 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5014 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5015 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5016 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5017 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5018 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5019 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5020 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5021 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5022 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5023 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5024 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5025 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5026 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5027 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5028 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5029 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5030 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5031 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5032 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5033 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5034 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5035 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5036 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5037 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5038 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5039 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5040 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5041 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5042 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5043 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5044 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5045 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5046 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5047 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5048 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5049 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5050 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5051 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5052 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5053 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5054 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5055 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5056 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5057 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5058 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5059 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5060 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5061 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5062 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5063 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5064 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5065 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5066 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5067 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5068 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5069 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5070 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5071 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5072 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5073 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5074 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5075 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5076 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5077 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5078 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5079 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5080 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5081 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5082 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5083 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5084 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5085 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5086 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5087 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5088 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5089 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5090 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5091 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5092 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5093 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5094 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5095 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5096 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5097 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5098 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5099 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5100 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5101 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5102 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5103 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5104 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5105 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5106 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5107 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5108 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5109 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5110 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5111 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5112 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5113 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5114 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5115 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5116 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5117 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5118 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5119 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5120 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5121 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5122 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5123 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5124 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5125 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5126 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5127 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5128 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5129 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5130 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5131 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5132 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5133 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5134 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5135 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5136 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5137 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5138 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5139 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5140 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5141 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5142 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5143 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5144 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5145 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5146 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5147 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5148 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5149 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5150 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5151 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5152 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5153 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5154 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5155 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5156 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5157 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5158 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5159 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5160 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5161 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5162 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5163 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5164 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5165 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5166 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5167 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5168 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5169};
5170
5171static u32 tg3TsoFwRodata[] = {
5172 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5173 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5174 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5175 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5176 0x00000000,
5177};
5178
5179static u32 tg3TsoFwData[] = {
5180 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5181 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5182 0x00000000,
5183};
5184
5185/* 5705 needs a special version of the TSO firmware. */
5186#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5187#define TG3_TSO5_FW_RELASE_MINOR 0x2
5188#define TG3_TSO5_FW_RELEASE_FIX 0x0
5189#define TG3_TSO5_FW_START_ADDR 0x00010000
5190#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5191#define TG3_TSO5_FW_TEXT_LEN 0xe90
5192#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5193#define TG3_TSO5_FW_RODATA_LEN 0x50
5194#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5195#define TG3_TSO5_FW_DATA_LEN 0x20
5196#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5197#define TG3_TSO5_FW_SBSS_LEN 0x28
5198#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5199#define TG3_TSO5_FW_BSS_LEN 0x88
5200
5201static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5202 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5203 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5204 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5205 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5206 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5207 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5208 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5209 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5210 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5211 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5212 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5213 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5214 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5215 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5216 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5217 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5218 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5219 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5220 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5221 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5222 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5223 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5224 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5225 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5226 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5227 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5228 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5229 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5230 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5231 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5232 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5233 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5234 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5235 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5236 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5237 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5238 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5239 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5240 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5241 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5242 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5243 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5244 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5245 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5246 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5247 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5248 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5249 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5250 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5251 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5252 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5253 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5254 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5255 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5256 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5257 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5258 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5259 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5260 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5261 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5262 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5263 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5264 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5265 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5266 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5267 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5268 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5269 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5270 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5271 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5272 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5273 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5274 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5275 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5276 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5277 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5278 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5279 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5280 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5281 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5282 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5283 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5284 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5285 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5286 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5287 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5288 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5289 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5290 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5291 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5292 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5293 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5294 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5295 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5296 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5297 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5298 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5299 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5300 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5301 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5302 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5303 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5304 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5305 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5306 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5307 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5308 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5309 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5310 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5311 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5312 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5313 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5314 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5315 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5316 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5317 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5318 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5319 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5320 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5321 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5322 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5323 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5324 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5325 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5326 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5327 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5328 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5329 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5330 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5331 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5332 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5333 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5334 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5335 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5336 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5337 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5338 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5339 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5340 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5341 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5342 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5343 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5344 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5345 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5346 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5347 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5348 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5349 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5350 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5351 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5352 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5353 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5354 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5355 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5356 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5357 0x00000000, 0x00000000, 0x00000000,
5358};
5359
5360static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5361 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5362 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5363 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5364 0x00000000, 0x00000000, 0x00000000,
5365};
5366
5367static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5368 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5369 0x00000000, 0x00000000, 0x00000000,
5370};
5371
5372/* tp->lock is held. */
5373static int tg3_load_tso_firmware(struct tg3 *tp)
5374{
5375 struct fw_info info;
5376 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5377 int err, i;
5378
5379 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5380 return 0;
5381
5382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5383 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5384 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5385 info.text_data = &tg3Tso5FwText[0];
5386 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5387 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5388 info.rodata_data = &tg3Tso5FwRodata[0];
5389 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5390 info.data_len = TG3_TSO5_FW_DATA_LEN;
5391 info.data_data = &tg3Tso5FwData[0];
5392 cpu_base = RX_CPU_BASE;
5393 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5394 cpu_scratch_size = (info.text_len +
5395 info.rodata_len +
5396 info.data_len +
5397 TG3_TSO5_FW_SBSS_LEN +
5398 TG3_TSO5_FW_BSS_LEN);
5399 } else {
5400 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5401 info.text_len = TG3_TSO_FW_TEXT_LEN;
5402 info.text_data = &tg3TsoFwText[0];
5403 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5404 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5405 info.rodata_data = &tg3TsoFwRodata[0];
5406 info.data_base = TG3_TSO_FW_DATA_ADDR;
5407 info.data_len = TG3_TSO_FW_DATA_LEN;
5408 info.data_data = &tg3TsoFwData[0];
5409 cpu_base = TX_CPU_BASE;
5410 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5411 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5412 }
5413
5414 err = tg3_load_firmware_cpu(tp, cpu_base,
5415 cpu_scratch_base, cpu_scratch_size,
5416 &info);
5417 if (err)
5418 return err;
5419
5420 /* Now startup the cpu. */
5421 tw32(cpu_base + CPU_STATE, 0xffffffff);
5422 tw32_f(cpu_base + CPU_PC, info.text_base);
5423
5424 for (i = 0; i < 5; i++) {
5425 if (tr32(cpu_base + CPU_PC) == info.text_base)
5426 break;
5427 tw32(cpu_base + CPU_STATE, 0xffffffff);
5428 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5429 tw32_f(cpu_base + CPU_PC, info.text_base);
5430 udelay(1000);
5431 }
5432 if (i >= 5) {
5433 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5434 "to set CPU PC, is %08x should be %08x\n",
5435 tp->dev->name, tr32(cpu_base + CPU_PC),
5436 info.text_base);
5437 return -ENODEV;
5438 }
5439 tw32(cpu_base + CPU_STATE, 0xffffffff);
5440 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5441 return 0;
5442}
5443
5444#endif /* TG3_TSO_SUPPORT != 0 */
5445
5446/* tp->lock is held. */
5447static void __tg3_set_mac_addr(struct tg3 *tp)
5448{
5449 u32 addr_high, addr_low;
5450 int i;
5451
5452 addr_high = ((tp->dev->dev_addr[0] << 8) |
5453 tp->dev->dev_addr[1]);
5454 addr_low = ((tp->dev->dev_addr[2] << 24) |
5455 (tp->dev->dev_addr[3] << 16) |
5456 (tp->dev->dev_addr[4] << 8) |
5457 (tp->dev->dev_addr[5] << 0));
5458 for (i = 0; i < 4; i++) {
5459 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5460 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5461 }
5462
5463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5465 for (i = 0; i < 12; i++) {
5466 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5467 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5468 }
5469 }
5470
5471 addr_high = (tp->dev->dev_addr[0] +
5472 tp->dev->dev_addr[1] +
5473 tp->dev->dev_addr[2] +
5474 tp->dev->dev_addr[3] +
5475 tp->dev->dev_addr[4] +
5476 tp->dev->dev_addr[5]) &
5477 TX_BACKOFF_SEED_MASK;
5478 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5479}
5480
5481static int tg3_set_mac_addr(struct net_device *dev, void *p)
5482{
5483 struct tg3 *tp = netdev_priv(dev);
5484 struct sockaddr *addr = p;
5485
f9804ddb
MC		 5486 if (!is_valid_ether_addr(addr->sa_data))
5487 return -EINVAL;
5488
1da177e4
LT		 5489 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5490
f47c11ee 5491 spin_lock_bh(&tp->lock);
1da177e4 5492 __tg3_set_mac_addr(tp);
f47c11ee 5493 spin_unlock_bh(&tp->lock);
1da177e4
LT		 5494
5495 return 0;
5496}
5497
5498/* tp->lock is held. */
5499static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5500 dma_addr_t mapping, u32 maxlen_flags,
5501 u32 nic_addr)
5502{
5503 tg3_write_mem(tp,
5504 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5505 ((u64) mapping >> 32));
5506 tg3_write_mem(tp,
5507 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5508 ((u64) mapping & 0xffffffff));
5509 tg3_write_mem(tp,
5510 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5511 maxlen_flags);
5512
5513 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5514 tg3_write_mem(tp,
5515 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5516 nic_addr);
5517}
5518
5519static void __tg3_set_rx_mode(struct net_device *);
d244c892 5520static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5521{
5522 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5523 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5524 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5525 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5526 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5527 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5528 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5529 }
5530 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5531 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5532 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5533 u32 val = ec->stats_block_coalesce_usecs;
5534
5535 if (!netif_carrier_ok(tp->dev))
5536 val = 0;
5537
5538 tw32(HOSTCC_STAT_COAL_TICKS, val);
5539 }
5540}
1da177e4
LT		 5541
5542/* tp->lock is held. */
5543static int tg3_reset_hw(struct tg3 *tp)
5544{
5545 u32 val, rdmac_mode;
5546 int i, err, limit;
5547
5548 tg3_disable_ints(tp);
5549
5550 tg3_stop_fw(tp);
5551
5552 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5553
5554 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 5555 tg3_abort_hw(tp, 1);
1da177e4
LT		 5556 }
5557
5558 err = tg3_chip_reset(tp);
5559 if (err)
5560 return err;
5561
5562 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5563
5564 /* This works around an issue with Athlon chipsets on
5565 * B3 tigon3 silicon. This bit has no effect on any
5566 * other revision. But do not set this on PCI Express
5567 * chips.
5568 */
5569 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5570 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5571 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5572
5573 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5574 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5575 val = tr32(TG3PCI_PCISTATE);
5576 val |= PCISTATE_RETRY_SAME_DMA;
5577 tw32(TG3PCI_PCISTATE, val);
5578 }
5579
5580 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5581 /* Enable some hw fixes. */
5582 val = tr32(TG3PCI_MSI_DATA);
5583 val |= (1 << 26) | (1 << 28) | (1 << 29);
5584 tw32(TG3PCI_MSI_DATA, val);
5585 }
5586
5587 /* Descriptor ring init may make accesses to the
5588 * NIC SRAM area to setup the TX descriptors, so we
5589 * can only do this after the hardware has been
5590 * successfully reset.
5591 */
5592 tg3_init_rings(tp);
5593
5594 /* This value is determined during the probe time DMA
5595 * engine test, tg3_test_dma.
5596 */
5597 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5598
5599 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5600 GRC_MODE_4X_NIC_SEND_RINGS |
5601 GRC_MODE_NO_TX_PHDR_CSUM |
5602 GRC_MODE_NO_RX_PHDR_CSUM);
5603 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5604 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5605 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5606 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5607 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5608
5609 tw32(GRC_MODE,
5610 tp->grc_mode |
5611 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5612
5613 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5614 val = tr32(GRC_MISC_CFG);
5615 val &= ~0xff;
5616 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5617 tw32(GRC_MISC_CFG, val);
5618
5619 /* Initialize MBUF/DESC pool. */
cbf46853 5620 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5621 /* Do nothing. */
5622 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5623 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5625 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5626 else
5627 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5628 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5629 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5630 }
5631#if TG3_TSO_SUPPORT != 0
5632 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5633 int fw_len;
5634
5635 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5636 TG3_TSO5_FW_RODATA_LEN +
5637 TG3_TSO5_FW_DATA_LEN +
5638 TG3_TSO5_FW_SBSS_LEN +
5639 TG3_TSO5_FW_BSS_LEN);
5640 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5641 tw32(BUFMGR_MB_POOL_ADDR,
5642 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5643 tw32(BUFMGR_MB_POOL_SIZE,
5644 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5645 }
5646#endif
5647
0f893dc6 5648 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 5649 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5650 tp->bufmgr_config.mbuf_read_dma_low_water);
5651 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5652 tp->bufmgr_config.mbuf_mac_rx_low_water);
5653 tw32(BUFMGR_MB_HIGH_WATER,
5654 tp->bufmgr_config.mbuf_high_water);
5655 } else {
5656 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5657 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5658 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5659 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5660 tw32(BUFMGR_MB_HIGH_WATER,
5661 tp->bufmgr_config.mbuf_high_water_jumbo);
5662 }
5663 tw32(BUFMGR_DMA_LOW_WATER,
5664 tp->bufmgr_config.dma_low_water);
5665 tw32(BUFMGR_DMA_HIGH_WATER,
5666 tp->bufmgr_config.dma_high_water);
5667
5668 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5669 for (i = 0; i < 2000; i++) {
5670 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5671 break;
5672 udelay(10);
5673 }
5674 if (i >= 2000) {
5675 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5676 tp->dev->name);
5677 return -ENODEV;
5678 }
5679
5680 /* Setup replenish threshold. */
5681 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5682
5683 /* Initialize TG3_BDINFO's at:
5684 * RCVDBDI_STD_BD: standard eth size rx ring
5685 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5686 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5687 *
5688 * like so:
5689 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5690 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5691 * ring attribute flags
5692 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5693 *
5694 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5695 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5696 *
5697 * The size of each ring is fixed in the firmware, but the location is
5698 * configurable.
5699 */
5700 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5701 ((u64) tp->rx_std_mapping >> 32));
5702 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5703 ((u64) tp->rx_std_mapping & 0xffffffff));
5704 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5705 NIC_SRAM_RX_BUFFER_DESC);
5706
5707 /* Don't even try to program the JUMBO/MINI buffer descriptor
5708 * configs on 5705.
5709 */
5710 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5711 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5712 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5713 } else {
5714 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5715 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5716
5717 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5718 BDINFO_FLAGS_DISABLED);
5719
5720 /* Setup replenish threshold. */
5721 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5722
0f893dc6 5723 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5724 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5725 ((u64) tp->rx_jumbo_mapping >> 32));
5726 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5727 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5728 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5729 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5730 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5731 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5732 } else {
5733 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5734 BDINFO_FLAGS_DISABLED);
5735 }
5736
5737 }
5738
5739 /* There is only one send ring on 5705/5750, no need to explicitly
5740 * disable the others.
5741 */
5742 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5743 /* Clear out send RCB ring in SRAM. */
5744 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5745 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5746 BDINFO_FLAGS_DISABLED);
5747 }
5748
5749 tp->tx_prod = 0;
5750 tp->tx_cons = 0;
5751 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5752 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5753
5754 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5755 tp->tx_desc_mapping,
5756 (TG3_TX_RING_SIZE <<
5757 BDINFO_FLAGS_MAXLEN_SHIFT),
5758 NIC_SRAM_TX_BUFFER_DESC);
5759
5760 /* There is only one receive return ring on 5705/5750, no need
5761 * to explicitly disable the others.
5762 */
5763 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5764 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5765 i += TG3_BDINFO_SIZE) {
5766 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5767 BDINFO_FLAGS_DISABLED);
5768 }
5769 }
5770
5771 tp->rx_rcb_ptr = 0;
5772 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5773
5774 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5775 tp->rx_rcb_mapping,
5776 (TG3_RX_RCB_RING_SIZE(tp) <<
5777 BDINFO_FLAGS_MAXLEN_SHIFT),
5778 0);
5779
5780 tp->rx_std_ptr = tp->rx_pending;
5781 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5782 tp->rx_std_ptr);
5783
0f893dc6 5784 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 5785 tp->rx_jumbo_pending : 0;
5786 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5787 tp->rx_jumbo_ptr);
5788
5789 /* Initialize MAC address and backoff seed. */
5790 __tg3_set_mac_addr(tp);
5791
5792 /* MTU + ethernet header + FCS + optional VLAN tag */
5793 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5794
5795 /* The slot time is changed by tg3_setup_phy if we
5796 * run at gigabit with half duplex.
5797 */
5798 tw32(MAC_TX_LENGTHS,
5799 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5800 (6 << TX_LENGTHS_IPG_SHIFT) |
5801 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5802
5803 /* Receive rules. */
5804 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5805 tw32(RCVLPC_CONFIG, 0x0181);
5806
5807 /* Calculate RDMAC_MODE setting early, we need it to determine
5808 * the RCVLPC_STATE_ENABLE mask.
5809 */
5810 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5811 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5812 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5813 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5814 RDMAC_MODE_LNGREAD_ENAB);
5815 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5816 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5817
5818 /* If statement applies to 5705 and 5750 PCI devices only */
5819 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5820 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5821 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5822 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5823 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5824 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5825 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5826 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5827 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5828 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5829 }
5830 }
5831
85e94ced
MC		 5832 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5833 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5834
1da177e4
LT		 5835#if TG3_TSO_SUPPORT != 0
5836 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5837 rdmac_mode |= (1 << 27);
5838#endif
5839
5840 /* Receive/send statistics. */
5841 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5842 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5843 val = tr32(RCVLPC_STATS_ENABLE);
5844 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5845 tw32(RCVLPC_STATS_ENABLE, val);
5846 } else {
5847 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5848 }
5849 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5850 tw32(SNDDATAI_STATSENAB, 0xffffff);
5851 tw32(SNDDATAI_STATSCTRL,
5852 (SNDDATAI_SCTRL_ENABLE |
5853 SNDDATAI_SCTRL_FASTUPD));
5854
5855 /* Setup host coalescing engine. */
5856 tw32(HOSTCC_MODE, 0);
5857 for (i = 0; i < 2000; i++) {
5858 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5859 break;
5860 udelay(10);
5861 }
5862
d244c892 5863 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 5864
5865 /* set status block DMA address */
5866 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5867 ((u64) tp->status_mapping >> 32));
5868 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5869 ((u64) tp->status_mapping & 0xffffffff));
5870
5871 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5872 /* Status/statistics block address. See tg3_timer,
5873 * the tg3_periodic_fetch_stats call there, and
5874 * tg3_get_stats to see how this works for 5705/5750 chips.
5875 */
1da177e4
LT		 5876 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5877 ((u64) tp->stats_mapping >> 32));
5878 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5879 ((u64) tp->stats_mapping & 0xffffffff));
5880 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5881 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5882 }
5883
5884 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5885
5886 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5887 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5888 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5889 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5890
5891 /* Clear statistics/status block in chip, and status block in ram. */
5892 for (i = NIC_SRAM_STATS_BLK;
5893 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5894 i += sizeof(u32)) {
5895 tg3_write_mem(tp, i, 0);
5896 udelay(40);
5897 }
5898 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5899
c94e3941
MC		 5900 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5901 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5902 /* reset to prevent losing 1st rx packet intermittently */
5903 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5904 udelay(10);
5905 }
5906
1da177e4
LT		 5907 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5908 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5909 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5910 udelay(40);
5911
314fba34
MC		 5912 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5913 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5914 * register to preserve the GPIO settings for LOMs. The GPIOs,
5915 * whether used as inputs or outputs, are set by boot code after
5916 * reset.
5917 */
5918 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5919 u32 gpio_mask;
5920
5921 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5922 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5923
5924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5925 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5926 GRC_LCLCTRL_GPIO_OUTPUT3;
5927
314fba34
MC		 5928 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5929
5930 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5931 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5932 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5933 }
1da177e4
LT		 5934 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5935 udelay(100);
5936
09ee929c 5937 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 5938 tp->last_tag = 0;
1da177e4
LT		 5939
5940 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5941 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5942 udelay(40);
5943 }
5944
5945 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5946 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5947 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5948 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5949 WDMAC_MODE_LNGREAD_ENAB);
5950
85e94ced
MC		 5951 /* If statement applies to 5705 and 5750 PCI devices only */
5952 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5953 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5955 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5956 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5957 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5958 /* nothing */
5959 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5960 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5961 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5962 val |= WDMAC_MODE_RX_ACCEL;
5963 }
5964 }
5965
5966 tw32_f(WDMAC_MODE, val);
5967 udelay(40);
5968
5969 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5970 val = tr32(TG3PCI_X_CAPS);
5971 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5972 val &= ~PCIX_CAPS_BURST_MASK;
5973 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5974 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5975 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5976 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5977 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5978 val |= (tp->split_mode_max_reqs <<
5979 PCIX_CAPS_SPLIT_SHIFT);
5980 }
5981 tw32(TG3PCI_X_CAPS, val);
5982 }
5983
5984 tw32_f(RDMAC_MODE, rdmac_mode);
5985 udelay(40);
5986
5987 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5988 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5989 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5990 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5991 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5992 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5993 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5994 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5995#if TG3_TSO_SUPPORT != 0
5996 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5997 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5998#endif
5999 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6000 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6001
6002 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6003 err = tg3_load_5701_a0_firmware_fix(tp);
6004 if (err)
6005 return err;
6006 }
6007
6008#if TG3_TSO_SUPPORT != 0
6009 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6010 err = tg3_load_tso_firmware(tp);
6011 if (err)
6012 return err;
6013 }
6014#endif
6015
6016 tp->tx_mode = TX_MODE_ENABLE;
6017 tw32_f(MAC_TX_MODE, tp->tx_mode);
6018 udelay(100);
6019
6020 tp->rx_mode = RX_MODE_ENABLE;
6021 tw32_f(MAC_RX_MODE, tp->rx_mode);
6022 udelay(10);
6023
6024 if (tp->link_config.phy_is_low_power) {
6025 tp->link_config.phy_is_low_power = 0;
6026 tp->link_config.speed = tp->link_config.orig_speed;
6027 tp->link_config.duplex = tp->link_config.orig_duplex;
6028 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6029 }
6030
6031 tp->mi_mode = MAC_MI_MODE_BASE;
6032 tw32_f(MAC_MI_MODE, tp->mi_mode);
6033 udelay(80);
6034
6035 tw32(MAC_LED_CTRL, tp->led_ctrl);
6036
6037 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6038 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6039 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6040 udelay(10);
6041 }
6042 tw32_f(MAC_RX_MODE, tp->rx_mode);
6043 udelay(10);
6044
6045 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6046 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6047 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6048 /* Set drive transmission level to 1.2V */
6049 /* only if the signal pre-emphasis bit is not set */
6050 val = tr32(MAC_SERDES_CFG);
6051 val &= 0xfffff000;
6052 val |= 0x880;
6053 tw32(MAC_SERDES_CFG, val);
6054 }
6055 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6056 tw32(MAC_SERDES_CFG, 0x616000);
6057 }
6058
6059 /* Prevent chip from dropping frames when flow control
6060 * is enabled.
6061 */
6062 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6063
6064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6065 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6066 /* Use hardware link auto-negotiation */
6067 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6068 }
6069
6070 err = tg3_setup_phy(tp, 1);
6071 if (err)
6072 return err;
6073
6074 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6075 u32 tmp;
6076
6077 /* Clear CRC stats. */
6078 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6079 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6080 tg3_readphy(tp, 0x14, &tmp);
6081 }
6082 }
6083
6084 __tg3_set_rx_mode(tp->dev);
6085
6086 /* Initialize receive rules. */
6087 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6088 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6089 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6090 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6091
4cf78e4f 6092 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6093 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6094 limit = 8;
6095 else
6096 limit = 16;
6097 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6098 limit -= 4;
6099 switch (limit) {
6100 case 16:
6101 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6102 case 15:
6103 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6104 case 14:
6105 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6106 case 13:
6107 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6108 case 12:
6109 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6110 case 11:
6111 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6112 case 10:
6113 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6114 case 9:
6115 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6116 case 8:
6117 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6118 case 7:
6119 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6120 case 6:
6121 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6122 case 5:
6123 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6124 case 4:
6125 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6126 case 3:
6127 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6128 case 2:
6129 case 1:
6130
6131 default:
6132 break;
6133 };
6134
6135 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6136
1da177e4
LT		 6137 return 0;
6138}
6139
6140/* Called at device open time to get the chip ready for
6141 * packet processing. Invoked with tp->lock held.
6142 */
6143static int tg3_init_hw(struct tg3 *tp)
6144{
6145 int err;
6146
6147 /* Force the chip into D0. */
6148 err = tg3_set_power_state(tp, 0);
6149 if (err)
6150 goto out;
6151
6152 tg3_switch_clocks(tp);
6153
6154 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6155
6156 err = tg3_reset_hw(tp);
6157
6158out:
6159 return err;
6160}
6161
6162#define TG3_STAT_ADD32(PSTAT, REG) \
6163do { u32 __val = tr32(REG); \
6164 (PSTAT)->low += __val; \
6165 if ((PSTAT)->low < __val) \
6166 (PSTAT)->high += 1; \
6167} while (0)
6168
6169static void tg3_periodic_fetch_stats(struct tg3 *tp)
6170{
6171 struct tg3_hw_stats *sp = tp->hw_stats;
6172
6173 if (!netif_carrier_ok(tp->dev))
6174 return;
6175
6176 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6177 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6178 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6179 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6180 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6181 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6182 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6183 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6184 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6185 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6186 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6187 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6188 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6189
6190 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6191 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6192 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6193 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6194 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6195 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6196 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6197 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6198 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6199 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6200 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6201 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6202 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6203 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6204}
6205
6206static void tg3_timer(unsigned long __opaque)
6207{
6208 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6209
f47c11ee 6210 spin_lock(&tp->lock);
1da177e4 6211
fac9b83e
DM		 6212 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6213 /* All of this garbage is because when using non-tagged
6214 * IRQ status the mailbox/status_block protocol the chip
6215 * uses with the cpu is race prone.
6216 */
6217 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6218 tw32(GRC_LOCAL_CTRL,
6219 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6220 } else {
6221 tw32(HOSTCC_MODE, tp->coalesce_mode |
6222 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6223 }
1da177e4 6224
fac9b83e
DM		 6225 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6226 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6227 spin_unlock(&tp->lock);
fac9b83e
DM		 6228 schedule_work(&tp->reset_task);
6229 return;
6230 }
1da177e4
LT		 6231 }
6232
1da177e4
LT		 6233 /* This part only runs once per second. */
6234 if (!--tp->timer_counter) {
fac9b83e
DM		 6235 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6236 tg3_periodic_fetch_stats(tp);
6237
1da177e4
LT		 6238 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6239 u32 mac_stat;
6240 int phy_event;
6241
6242 mac_stat = tr32(MAC_STATUS);
6243
6244 phy_event = 0;
6245 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6246 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6247 phy_event = 1;
6248 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6249 phy_event = 1;
6250
6251 if (phy_event)
6252 tg3_setup_phy(tp, 0);
6253 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6254 u32 mac_stat = tr32(MAC_STATUS);
6255 int need_setup = 0;
6256
6257 if (netif_carrier_ok(tp->dev) &&
6258 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6259 need_setup = 1;
6260 }
6261 if (! netif_carrier_ok(tp->dev) &&
6262 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6263 MAC_STATUS_SIGNAL_DET))) {
6264 need_setup = 1;
6265 }
6266 if (need_setup) {
6267 tw32_f(MAC_MODE,
6268 (tp->mac_mode &
6269 ~MAC_MODE_PORT_MODE_MASK));
6270 udelay(40);
6271 tw32_f(MAC_MODE, tp->mac_mode);
6272 udelay(40);
6273 tg3_setup_phy(tp, 0);
6274 }
747e8f8b
MC		 6275 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6276 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6277
6278 tp->timer_counter = tp->timer_multiplier;
6279 }
6280
28fbef78 6281 /* Heartbeat is only sent once every 2 seconds. */
1da177e4
LT		 6282 if (!--tp->asf_counter) {
6283 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6284 u32 val;
6285
28fbef78
MC		 6286 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
6287 FWCMD_NICDRV_ALIVE2);
6288 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6289 /* 5 seconds timeout */
6290 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6291 val = tr32(GRC_RX_CPU_EVENT);
6292 val |= (1 << 14);
6293 tw32(GRC_RX_CPU_EVENT, val);
6294 }
6295 tp->asf_counter = tp->asf_multiplier;
6296 }
6297
f47c11ee 6298 spin_unlock(&tp->lock);
1da177e4
LT		 6299
6300 tp->timer.expires = jiffies + tp->timer_offset;
6301 add_timer(&tp->timer);
6302}
6303
7938109f
MC		 6304static int tg3_test_interrupt(struct tg3 *tp)
6305{
6306 struct net_device *dev = tp->dev;
6307 int err, i;
6308 u32 int_mbox = 0;
6309
d4bc3927
MC		 6310 if (!netif_running(dev))
6311 return -ENODEV;
6312
7938109f
MC		 6313 tg3_disable_ints(tp);
6314
6315 free_irq(tp->pdev->irq, dev);
6316
6317 err = request_irq(tp->pdev->irq, tg3_test_isr,
f4d0ee98 6318 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6319 if (err)
6320 return err;
6321
38f3843e 6322 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6323 tg3_enable_ints(tp);
6324
6325 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6326 HOSTCC_MODE_NOW);
6327
6328 for (i = 0; i < 5; i++) {
09ee929c
MC		 6329 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6330 TG3_64BIT_REG_LOW);
7938109f
MC		 6331 if (int_mbox != 0)
6332 break;
6333 msleep(10);
6334 }
6335
6336 tg3_disable_ints(tp);
6337
6338 free_irq(tp->pdev->irq, dev);
6339
6340 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6341 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6342 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6343 else {
6344 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6345 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6346 fn = tg3_interrupt_tagged;
6347 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6348 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6349 }
7938109f
MC		 6350
6351 if (err)
6352 return err;
6353
6354 if (int_mbox != 0)
6355 return 0;
6356
6357 return -EIO;
6358}
6359
6360/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6361 * successfully restored
6362 */
6363static int tg3_test_msi(struct tg3 *tp)
6364{
6365 struct net_device *dev = tp->dev;
6366 int err;
6367 u16 pci_cmd;
6368
6369 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6370 return 0;
6371
6372 /* Turn off SERR reporting in case MSI terminates with Master
6373 * Abort.
6374 */
6375 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6376 pci_write_config_word(tp->pdev, PCI_COMMAND,
6377 pci_cmd & ~PCI_COMMAND_SERR);
6378
6379 err = tg3_test_interrupt(tp);
6380
6381 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6382
6383 if (!err)
6384 return 0;
6385
6386 /* other failures */
6387 if (err != -EIO)
6388 return err;
6389
6390 /* MSI test failed, go back to INTx mode */
6391 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6392 "switching to INTx mode. Please report this failure to "
6393 "the PCI maintainer and include system chipset information.\n",
6394 tp->dev->name);
6395
6396 free_irq(tp->pdev->irq, dev);
6397 pci_disable_msi(tp->pdev);
6398
6399 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6400
fac9b83e
DM		 6401 {
6402 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6403 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6404 fn = tg3_interrupt_tagged;
7938109f 6405
fac9b83e
DM		 6406 err = request_irq(tp->pdev->irq, fn,
6407 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6408 }
7938109f
MC		 6409 if (err)
6410 return err;
6411
6412 /* Need to reset the chip because the MSI cycle may have terminated
6413 * with Master Abort.
6414 */
f47c11ee 6415 tg3_full_lock(tp, 1);
7938109f 6416
944d980e 6417 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6418 err = tg3_init_hw(tp);
6419
f47c11ee 6420 tg3_full_unlock(tp);
7938109f
MC		 6421
6422 if (err)
6423 free_irq(tp->pdev->irq, dev);
6424
6425 return err;
6426}
6427
1da177e4
LT		 6428static int tg3_open(struct net_device *dev)
6429{
6430 struct tg3 *tp = netdev_priv(dev);
6431 int err;
6432
f47c11ee 6433 tg3_full_lock(tp, 0);
1da177e4
LT		 6434
6435 tg3_disable_ints(tp);
6436 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6437
f47c11ee 6438 tg3_full_unlock(tp);
1da177e4
LT		 6439
6440 /* The placement of this call is tied
6441 * to the setup and use of Host TX descriptors.
6442 */
6443 err = tg3_alloc_consistent(tp);
6444 if (err)
6445 return err;
6446
88b06bc2
MC		 6447 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6448 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6449 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
fac9b83e
DM		 6450 /* All MSI supporting chips should support tagged
6451 * status. Assert that this is the case.
6452 */
6453 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6454 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6455 "Not using MSI.\n", tp->dev->name);
6456 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 6457 u32 msi_mode;
6458
6459 msi_mode = tr32(MSGINT_MODE);
6460 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6461 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6462 }
6463 }
6464 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6465 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6466 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6467 else {
6468 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6469 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6470 fn = tg3_interrupt_tagged;
6471
6472 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6473 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6474 }
1da177e4
LT		 6475
6476 if (err) {
88b06bc2
MC		 6477 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6478 pci_disable_msi(tp->pdev);
6479 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6480 }
1da177e4
LT		 6481 tg3_free_consistent(tp);
6482 return err;
6483 }
6484
f47c11ee 6485 tg3_full_lock(tp, 0);
1da177e4
LT		 6486
6487 err = tg3_init_hw(tp);
6488 if (err) {
944d980e 6489 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6490 tg3_free_rings(tp);
6491 } else {
fac9b83e
DM		 6492 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6493 tp->timer_offset = HZ;
6494 else
6495 tp->timer_offset = HZ / 10;
6496
6497 BUG_ON(tp->timer_offset > HZ);
6498 tp->timer_counter = tp->timer_multiplier =
6499 (HZ / tp->timer_offset);
6500 tp->asf_counter = tp->asf_multiplier =
28fbef78 6501 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 6502
6503 init_timer(&tp->timer);
6504 tp->timer.expires = jiffies + tp->timer_offset;
6505 tp->timer.data = (unsigned long) tp;
6506 tp->timer.function = tg3_timer;
1da177e4
LT		 6507 }
6508
f47c11ee 6509 tg3_full_unlock(tp);
1da177e4
LT		 6510
6511 if (err) {
88b06bc2
MC		 6512 free_irq(tp->pdev->irq, dev);
6513 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6514 pci_disable_msi(tp->pdev);
6515 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6516 }
1da177e4
LT		 6517 tg3_free_consistent(tp);
6518 return err;
6519 }
6520
7938109f
MC		 6521 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6522 err = tg3_test_msi(tp);
fac9b83e 6523
7938109f 6524 if (err) {
f47c11ee 6525 tg3_full_lock(tp, 0);
7938109f
MC		 6526
6527 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6528 pci_disable_msi(tp->pdev);
6529 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6530 }
944d980e 6531 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6532 tg3_free_rings(tp);
6533 tg3_free_consistent(tp);
6534
f47c11ee 6535 tg3_full_unlock(tp);
7938109f
MC		 6536
6537 return err;
6538 }
6539 }
6540
f47c11ee 6541 tg3_full_lock(tp, 0);
1da177e4 6542
7938109f
MC		 6543 add_timer(&tp->timer);
6544 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6545 tg3_enable_ints(tp);
6546
f47c11ee 6547 tg3_full_unlock(tp);
1da177e4
LT		 6548
6549 netif_start_queue(dev);
6550
6551 return 0;
6552}
6553
6554#if 0
6555/*static*/ void tg3_dump_state(struct tg3 *tp)
6556{
6557 u32 val32, val32_2, val32_3, val32_4, val32_5;
6558 u16 val16;
6559 int i;
6560
6561 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6562 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6563 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6564 val16, val32);
6565
6566 /* MAC block */
6567 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6568 tr32(MAC_MODE), tr32(MAC_STATUS));
6569 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6570 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6571 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6572 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6573 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6574 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6575
6576 /* Send data initiator control block */
6577 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6578 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6579 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6580 tr32(SNDDATAI_STATSCTRL));
6581
6582 /* Send data completion control block */
6583 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6584
6585 /* Send BD ring selector block */
6586 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6587 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6588
6589 /* Send BD initiator control block */
6590 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6591 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6592
6593 /* Send BD completion control block */
6594 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6595
6596 /* Receive list placement control block */
6597 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6598 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6599 printk(" RCVLPC_STATSCTRL[%08x]\n",
6600 tr32(RCVLPC_STATSCTRL));
6601
6602 /* Receive data and receive BD initiator control block */
6603 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6604 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6605
6606 /* Receive data completion control block */
6607 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6608 tr32(RCVDCC_MODE));
6609
6610 /* Receive BD initiator control block */
6611 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6612 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6613
6614 /* Receive BD completion control block */
6615 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6616 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6617
6618 /* Receive list selector control block */
6619 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6620 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6621
6622 /* Mbuf cluster free block */
6623 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6624 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6625
6626 /* Host coalescing control block */
6627 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6628 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6629 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6630 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6631 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6632 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6633 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6634 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6635 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6636 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6637 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6638 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6639
6640 /* Memory arbiter control block */
6641 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6642 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6643
6644 /* Buffer manager control block */
6645 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6646 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6647 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6648 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6649 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6650 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6651 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6652 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6653
6654 /* Read DMA control block */
6655 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6656 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6657
6658 /* Write DMA control block */
6659 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6660 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6661
6662 /* DMA completion block */
6663 printk("DEBUG: DMAC_MODE[%08x]\n",
6664 tr32(DMAC_MODE));
6665
6666 /* GRC block */
6667 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6668 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6669 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6670 tr32(GRC_LOCAL_CTRL));
6671
6672 /* TG3_BDINFOs */
6673 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6674 tr32(RCVDBDI_JUMBO_BD + 0x0),
6675 tr32(RCVDBDI_JUMBO_BD + 0x4),
6676 tr32(RCVDBDI_JUMBO_BD + 0x8),
6677 tr32(RCVDBDI_JUMBO_BD + 0xc));
6678 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6679 tr32(RCVDBDI_STD_BD + 0x0),
6680 tr32(RCVDBDI_STD_BD + 0x4),
6681 tr32(RCVDBDI_STD_BD + 0x8),
6682 tr32(RCVDBDI_STD_BD + 0xc));
6683 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6684 tr32(RCVDBDI_MINI_BD + 0x0),
6685 tr32(RCVDBDI_MINI_BD + 0x4),
6686 tr32(RCVDBDI_MINI_BD + 0x8),
6687 tr32(RCVDBDI_MINI_BD + 0xc));
6688
6689 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6690 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6691 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6692 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6693 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6694 val32, val32_2, val32_3, val32_4);
6695
6696 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6697 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6698 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6699 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6700 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6701 val32, val32_2, val32_3, val32_4);
6702
6703 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6704 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6705 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6706 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6707 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6708 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6709 val32, val32_2, val32_3, val32_4, val32_5);
6710
6711 /* SW status block */
6712 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6713 tp->hw_status->status,
6714 tp->hw_status->status_tag,
6715 tp->hw_status->rx_jumbo_consumer,
6716 tp->hw_status->rx_consumer,
6717 tp->hw_status->rx_mini_consumer,
6718 tp->hw_status->idx[0].rx_producer,
6719 tp->hw_status->idx[0].tx_consumer);
6720
6721 /* SW statistics block */
6722 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6723 ((u32 *)tp->hw_stats)[0],
6724 ((u32 *)tp->hw_stats)[1],
6725 ((u32 *)tp->hw_stats)[2],
6726 ((u32 *)tp->hw_stats)[3]);
6727
6728 /* Mailboxes */
6729 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 6730 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6731 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6732 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6733 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 6734
6735 /* NIC side send descriptors. */
6736 for (i = 0; i < 6; i++) {
6737 unsigned long txd;
6738
6739 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6740 + (i * sizeof(struct tg3_tx_buffer_desc));
6741 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6742 i,
6743 readl(txd + 0x0), readl(txd + 0x4),
6744 readl(txd + 0x8), readl(txd + 0xc));
6745 }
6746
6747 /* NIC side RX descriptors. */
6748 for (i = 0; i < 6; i++) {
6749 unsigned long rxd;
6750
6751 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6752 + (i * sizeof(struct tg3_rx_buffer_desc));
6753 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6754 i,
6755 readl(rxd + 0x0), readl(rxd + 0x4),
6756 readl(rxd + 0x8), readl(rxd + 0xc));
6757 rxd += (4 * sizeof(u32));
6758 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6759 i,
6760 readl(rxd + 0x0), readl(rxd + 0x4),
6761 readl(rxd + 0x8), readl(rxd + 0xc));
6762 }
6763
6764 for (i = 0; i < 6; i++) {
6765 unsigned long rxd;
6766
6767 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6768 + (i * sizeof(struct tg3_rx_buffer_desc));
6769 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6770 i,
6771 readl(rxd + 0x0), readl(rxd + 0x4),
6772 readl(rxd + 0x8), readl(rxd + 0xc));
6773 rxd += (4 * sizeof(u32));
6774 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6775 i,
6776 readl(rxd + 0x0), readl(rxd + 0x4),
6777 readl(rxd + 0x8), readl(rxd + 0xc));
6778 }
6779}
6780#endif
6781
6782static struct net_device_stats *tg3_get_stats(struct net_device *);
6783static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6784
6785static int tg3_close(struct net_device *dev)
6786{
6787 struct tg3 *tp = netdev_priv(dev);
6788
6789 netif_stop_queue(dev);
6790
6791 del_timer_sync(&tp->timer);
6792
f47c11ee 6793 tg3_full_lock(tp, 1);
1da177e4
LT		 6794#if 0
6795 tg3_dump_state(tp);
6796#endif
6797
6798 tg3_disable_ints(tp);
6799
944d980e 6800 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6801 tg3_free_rings(tp);
6802 tp->tg3_flags &=
6803 ~(TG3_FLAG_INIT_COMPLETE |
6804 TG3_FLAG_GOT_SERDES_FLOWCTL);
6805 netif_carrier_off(tp->dev);
6806
f47c11ee 6807 tg3_full_unlock(tp);
1da177e4 6808
88b06bc2
MC		 6809 free_irq(tp->pdev->irq, dev);
6810 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6811 pci_disable_msi(tp->pdev);
6812 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6813 }
1da177e4
LT		 6814
6815 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6816 sizeof(tp->net_stats_prev));
6817 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6818 sizeof(tp->estats_prev));
6819
6820 tg3_free_consistent(tp);
6821
6822 return 0;
6823}
6824
6825static inline unsigned long get_stat64(tg3_stat64_t *val)
6826{
6827 unsigned long ret;
6828
6829#if (BITS_PER_LONG == 32)
6830 ret = val->low;
6831#else
6832 ret = ((u64)val->high << 32) | ((u64)val->low);
6833#endif
6834 return ret;
6835}
6836
6837static unsigned long calc_crc_errors(struct tg3 *tp)
6838{
6839 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6840
6841 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6842 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6843 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 6844 u32 val;
6845
f47c11ee 6846 spin_lock_bh(&tp->lock);
1da177e4
LT		 6847 if (!tg3_readphy(tp, 0x1e, &val)) {
6848 tg3_writephy(tp, 0x1e, val | 0x8000);
6849 tg3_readphy(tp, 0x14, &val);
6850 } else
6851 val = 0;
f47c11ee 6852 spin_unlock_bh(&tp->lock);
1da177e4
LT		 6853
6854 tp->phy_crc_errors += val;
6855
6856 return tp->phy_crc_errors;
6857 }
6858
6859 return get_stat64(&hw_stats->rx_fcs_errors);
6860}
6861
6862#define ESTAT_ADD(member) \
6863 estats->member = old_estats->member + \
6864 get_stat64(&hw_stats->member)
6865
6866static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6867{
6868 struct tg3_ethtool_stats *estats = &tp->estats;
6869 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6870 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6871
6872 if (!hw_stats)
6873 return old_estats;
6874
6875 ESTAT_ADD(rx_octets);
6876 ESTAT_ADD(rx_fragments);
6877 ESTAT_ADD(rx_ucast_packets);
6878 ESTAT_ADD(rx_mcast_packets);
6879 ESTAT_ADD(rx_bcast_packets);
6880 ESTAT_ADD(rx_fcs_errors);
6881 ESTAT_ADD(rx_align_errors);
6882 ESTAT_ADD(rx_xon_pause_rcvd);
6883 ESTAT_ADD(rx_xoff_pause_rcvd);
6884 ESTAT_ADD(rx_mac_ctrl_rcvd);
6885 ESTAT_ADD(rx_xoff_entered);
6886 ESTAT_ADD(rx_frame_too_long_errors);
6887 ESTAT_ADD(rx_jabbers);
6888 ESTAT_ADD(rx_undersize_packets);
6889 ESTAT_ADD(rx_in_length_errors);
6890 ESTAT_ADD(rx_out_length_errors);
6891 ESTAT_ADD(rx_64_or_less_octet_packets);
6892 ESTAT_ADD(rx_65_to_127_octet_packets);
6893 ESTAT_ADD(rx_128_to_255_octet_packets);
6894 ESTAT_ADD(rx_256_to_511_octet_packets);
6895 ESTAT_ADD(rx_512_to_1023_octet_packets);
6896 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6897 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6898 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6899 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6900 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6901
6902 ESTAT_ADD(tx_octets);
6903 ESTAT_ADD(tx_collisions);
6904 ESTAT_ADD(tx_xon_sent);
6905 ESTAT_ADD(tx_xoff_sent);
6906 ESTAT_ADD(tx_flow_control);
6907 ESTAT_ADD(tx_mac_errors);
6908 ESTAT_ADD(tx_single_collisions);
6909 ESTAT_ADD(tx_mult_collisions);
6910 ESTAT_ADD(tx_deferred);
6911 ESTAT_ADD(tx_excessive_collisions);
6912 ESTAT_ADD(tx_late_collisions);
6913 ESTAT_ADD(tx_collide_2times);
6914 ESTAT_ADD(tx_collide_3times);
6915 ESTAT_ADD(tx_collide_4times);
6916 ESTAT_ADD(tx_collide_5times);
6917 ESTAT_ADD(tx_collide_6times);
6918 ESTAT_ADD(tx_collide_7times);
6919 ESTAT_ADD(tx_collide_8times);
6920 ESTAT_ADD(tx_collide_9times);
6921 ESTAT_ADD(tx_collide_10times);
6922 ESTAT_ADD(tx_collide_11times);
6923 ESTAT_ADD(tx_collide_12times);
6924 ESTAT_ADD(tx_collide_13times);
6925 ESTAT_ADD(tx_collide_14times);
6926 ESTAT_ADD(tx_collide_15times);
6927 ESTAT_ADD(tx_ucast_packets);
6928 ESTAT_ADD(tx_mcast_packets);
6929 ESTAT_ADD(tx_bcast_packets);
6930 ESTAT_ADD(tx_carrier_sense_errors);
6931 ESTAT_ADD(tx_discards);
6932 ESTAT_ADD(tx_errors);
6933
6934 ESTAT_ADD(dma_writeq_full);
6935 ESTAT_ADD(dma_write_prioq_full);
6936 ESTAT_ADD(rxbds_empty);
6937 ESTAT_ADD(rx_discards);
6938 ESTAT_ADD(rx_errors);
6939 ESTAT_ADD(rx_threshold_hit);
6940
6941 ESTAT_ADD(dma_readq_full);
6942 ESTAT_ADD(dma_read_prioq_full);
6943 ESTAT_ADD(tx_comp_queue_full);
6944
6945 ESTAT_ADD(ring_set_send_prod_index);
6946 ESTAT_ADD(ring_status_update);
6947 ESTAT_ADD(nic_irqs);
6948 ESTAT_ADD(nic_avoided_irqs);
6949 ESTAT_ADD(nic_tx_threshold_hit);
6950
6951 return estats;
6952}
6953
6954static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6955{
6956 struct tg3 *tp = netdev_priv(dev);
6957 struct net_device_stats *stats = &tp->net_stats;
6958 struct net_device_stats *old_stats = &tp->net_stats_prev;
6959 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6960
6961 if (!hw_stats)
6962 return old_stats;
6963
6964 stats->rx_packets = old_stats->rx_packets +
6965 get_stat64(&hw_stats->rx_ucast_packets) +
6966 get_stat64(&hw_stats->rx_mcast_packets) +
6967 get_stat64(&hw_stats->rx_bcast_packets);
6968
6969 stats->tx_packets = old_stats->tx_packets +
6970 get_stat64(&hw_stats->tx_ucast_packets) +
6971 get_stat64(&hw_stats->tx_mcast_packets) +
6972 get_stat64(&hw_stats->tx_bcast_packets);
6973
6974 stats->rx_bytes = old_stats->rx_bytes +
6975 get_stat64(&hw_stats->rx_octets);
6976 stats->tx_bytes = old_stats->tx_bytes +
6977 get_stat64(&hw_stats->tx_octets);
6978
6979 stats->rx_errors = old_stats->rx_errors +
4f63b877 6980 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 6981 stats->tx_errors = old_stats->tx_errors +
6982 get_stat64(&hw_stats->tx_errors) +
6983 get_stat64(&hw_stats->tx_mac_errors) +
6984 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6985 get_stat64(&hw_stats->tx_discards);
6986
6987 stats->multicast = old_stats->multicast +
6988 get_stat64(&hw_stats->rx_mcast_packets);
6989 stats->collisions = old_stats->collisions +
6990 get_stat64(&hw_stats->tx_collisions);
6991
6992 stats->rx_length_errors = old_stats->rx_length_errors +
6993 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6994 get_stat64(&hw_stats->rx_undersize_packets);
6995
6996 stats->rx_over_errors = old_stats->rx_over_errors +
6997 get_stat64(&hw_stats->rxbds_empty);
6998 stats->rx_frame_errors = old_stats->rx_frame_errors +
6999 get_stat64(&hw_stats->rx_align_errors);
7000 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7001 get_stat64(&hw_stats->tx_discards);
7002 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7003 get_stat64(&hw_stats->tx_carrier_sense_errors);
7004
7005 stats->rx_crc_errors = old_stats->rx_crc_errors +
7006 calc_crc_errors(tp);
7007
4f63b877
JL		 7008 stats->rx_missed_errors = old_stats->rx_missed_errors +
7009 get_stat64(&hw_stats->rx_discards);
7010
1da177e4
LT		 7011 return stats;
7012}
7013
7014static inline u32 calc_crc(unsigned char *buf, int len)
7015{
7016 u32 reg;
7017 u32 tmp;
7018 int j, k;
7019
7020 reg = 0xffffffff;
7021
7022 for (j = 0; j < len; j++) {
7023 reg ^= buf[j];
7024
7025 for (k = 0; k < 8; k++) {
7026 tmp = reg & 0x01;
7027
7028 reg >>= 1;
7029
7030 if (tmp) {
7031 reg ^= 0xedb88320;
7032 }
7033 }
7034 }
7035
7036 return ~reg;
7037}
7038
7039static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7040{
7041 /* accept or reject all multicast frames */
7042 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7043 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7044 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7045 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7046}
7047
7048static void __tg3_set_rx_mode(struct net_device *dev)
7049{
7050 struct tg3 *tp = netdev_priv(dev);
7051 u32 rx_mode;
7052
7053 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7054 RX_MODE_KEEP_VLAN_TAG);
7055
7056 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7057 * flag clear.
7058 */
7059#if TG3_VLAN_TAG_USED
7060 if (!tp->vlgrp &&
7061 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7062 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7063#else
7064 /* By definition, VLAN is disabled always in this
7065 * case.
7066 */
7067 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7068 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7069#endif
7070
7071 if (dev->flags & IFF_PROMISC) {
7072 /* Promiscuous mode. */
7073 rx_mode |= RX_MODE_PROMISC;
7074 } else if (dev->flags & IFF_ALLMULTI) {
7075 /* Accept all multicast. */
7076 tg3_set_multi (tp, 1);
7077 } else if (dev->mc_count < 1) {
7078 /* Reject all multicast. */
7079 tg3_set_multi (tp, 0);
7080 } else {
7081 /* Accept one or more multicast(s). */
7082 struct dev_mc_list *mclist;
7083 unsigned int i;
7084 u32 mc_filter[4] = { 0, };
7085 u32 regidx;
7086 u32 bit;
7087 u32 crc;
7088
7089 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7090 i++, mclist = mclist->next) {
7091
7092 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7093 bit = ~crc & 0x7f;
7094 regidx = (bit & 0x60) >> 5;
7095 bit &= 0x1f;
7096 mc_filter[regidx] |= (1 << bit);
7097 }
7098
7099 tw32(MAC_HASH_REG_0, mc_filter[0]);
7100 tw32(MAC_HASH_REG_1, mc_filter[1]);
7101 tw32(MAC_HASH_REG_2, mc_filter[2]);
7102 tw32(MAC_HASH_REG_3, mc_filter[3]);
7103 }
7104
7105 if (rx_mode != tp->rx_mode) {
7106 tp->rx_mode = rx_mode;
7107 tw32_f(MAC_RX_MODE, rx_mode);
7108 udelay(10);
7109 }
7110}
7111
7112static void tg3_set_rx_mode(struct net_device *dev)
7113{
7114 struct tg3 *tp = netdev_priv(dev);
7115
f47c11ee 7116 tg3_full_lock(tp, 0);
1da177e4 7117 __tg3_set_rx_mode(dev);
f47c11ee 7118 tg3_full_unlock(tp);
1da177e4
LT		 7119}
7120
7121#define TG3_REGDUMP_LEN (32 * 1024)
7122
7123static int tg3_get_regs_len(struct net_device *dev)
7124{
7125 return TG3_REGDUMP_LEN;
7126}
7127
7128static void tg3_get_regs(struct net_device *dev,
7129 struct ethtool_regs *regs, void *_p)
7130{
7131 u32 *p = _p;
7132 struct tg3 *tp = netdev_priv(dev);
7133 u8 *orig_p = _p;
7134 int i;
7135
7136 regs->version = 0;
7137
7138 memset(p, 0, TG3_REGDUMP_LEN);
7139
f47c11ee 7140 tg3_full_lock(tp, 0);
1da177e4
LT		 7141
7142#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7143#define GET_REG32_LOOP(base,len) \
7144do { p = (u32 *)(orig_p + (base)); \
7145 for (i = 0; i < len; i += 4) \
7146 __GET_REG32((base) + i); \
7147} while (0)
7148#define GET_REG32_1(reg) \
7149do { p = (u32 *)(orig_p + (reg)); \
7150 __GET_REG32((reg)); \
7151} while (0)
7152
7153 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7154 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7155 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7156 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7157 GET_REG32_1(SNDDATAC_MODE);
7158 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7159 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7160 GET_REG32_1(SNDBDC_MODE);
7161 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7162 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7163 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7164 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7165 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7166 GET_REG32_1(RCVDCC_MODE);
7167 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7168 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7169 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7170 GET_REG32_1(MBFREE_MODE);
7171 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7172 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7173 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7174 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7175 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 7176 GET_REG32_1(RX_CPU_MODE);
7177 GET_REG32_1(RX_CPU_STATE);
7178 GET_REG32_1(RX_CPU_PGMCTR);
7179 GET_REG32_1(RX_CPU_HWBKPT);
7180 GET_REG32_1(TX_CPU_MODE);
7181 GET_REG32_1(TX_CPU_STATE);
7182 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 7183 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7184 GET_REG32_LOOP(FTQ_RESET, 0x120);
7185 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7186 GET_REG32_1(DMAC_MODE);
7187 GET_REG32_LOOP(GRC_MODE, 0x4c);
7188 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7189 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7190
7191#undef __GET_REG32
7192#undef GET_REG32_LOOP
7193#undef GET_REG32_1
7194
f47c11ee 7195 tg3_full_unlock(tp);
1da177e4
LT		 7196}
7197
7198static int tg3_get_eeprom_len(struct net_device *dev)
7199{
7200 struct tg3 *tp = netdev_priv(dev);
7201
7202 return tp->nvram_size;
7203}
7204
7205static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7206
7207static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7208{
7209 struct tg3 *tp = netdev_priv(dev);
7210 int ret;
7211 u8 *pd;
7212 u32 i, offset, len, val, b_offset, b_count;
7213
7214 offset = eeprom->offset;
7215 len = eeprom->len;
7216 eeprom->len = 0;
7217
7218 eeprom->magic = TG3_EEPROM_MAGIC;
7219
7220 if (offset & 3) {
7221 /* adjustments to start on required 4 byte boundary */
7222 b_offset = offset & 3;
7223 b_count = 4 - b_offset;
7224 if (b_count > len) {
7225 /* i.e. offset=1 len=2 */
7226 b_count = len;
7227 }
7228 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7229 if (ret)
7230 return ret;
7231 val = cpu_to_le32(val);
7232 memcpy(data, ((char*)&val) + b_offset, b_count);
7233 len -= b_count;
7234 offset += b_count;
7235 eeprom->len += b_count;
7236 }
7237
7238 /* read bytes upto the last 4 byte boundary */
7239 pd = &data[eeprom->len];
7240 for (i = 0; i < (len - (len & 3)); i += 4) {
7241 ret = tg3_nvram_read(tp, offset + i, &val);
7242 if (ret) {
7243 eeprom->len += i;
7244 return ret;
7245 }
7246 val = cpu_to_le32(val);
7247 memcpy(pd + i, &val, 4);
7248 }
7249 eeprom->len += i;
7250
7251 if (len & 3) {
7252 /* read last bytes not ending on 4 byte boundary */
7253 pd = &data[eeprom->len];
7254 b_count = len & 3;
7255 b_offset = offset + len - b_count;
7256 ret = tg3_nvram_read(tp, b_offset, &val);
7257 if (ret)
7258 return ret;
7259 val = cpu_to_le32(val);
7260 memcpy(pd, ((char*)&val), b_count);
7261 eeprom->len += b_count;
7262 }
7263 return 0;
7264}
7265
7266static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7267
7268static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7269{
7270 struct tg3 *tp = netdev_priv(dev);
7271 int ret;
7272 u32 offset, len, b_offset, odd_len, start, end;
7273 u8 *buf;
7274
7275 if (eeprom->magic != TG3_EEPROM_MAGIC)
7276 return -EINVAL;
7277
7278 offset = eeprom->offset;
7279 len = eeprom->len;
7280
7281 if ((b_offset = (offset & 3))) {
7282 /* adjustments to start on required 4 byte boundary */
7283 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7284 if (ret)
7285 return ret;
7286 start = cpu_to_le32(start);
7287 len += b_offset;
7288 offset &= ~3;
1c8594b4
MC		 7289 if (len < 4)
7290 len = 4;
1da177e4
LT		 7291 }
7292
7293 odd_len = 0;
1c8594b4 7294 if (len & 3) {
1da177e4
LT		 7295 /* adjustments to end on required 4 byte boundary */
7296 odd_len = 1;
7297 len = (len + 3) & ~3;
7298 ret = tg3_nvram_read(tp, offset+len-4, &end);
7299 if (ret)
7300 return ret;
7301 end = cpu_to_le32(end);
7302 }
7303
7304 buf = data;
7305 if (b_offset || odd_len) {
7306 buf = kmalloc(len, GFP_KERNEL);
7307 if (buf == 0)
7308 return -ENOMEM;
7309 if (b_offset)
7310 memcpy(buf, &start, 4);
7311 if (odd_len)
7312 memcpy(buf+len-4, &end, 4);
7313 memcpy(buf + b_offset, data, eeprom->len);
7314 }
7315
7316 ret = tg3_nvram_write_block(tp, offset, len, buf);
7317
7318 if (buf != data)
7319 kfree(buf);
7320
7321 return ret;
7322}
7323
7324static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7325{
7326 struct tg3 *tp = netdev_priv(dev);
7327
7328 cmd->supported = (SUPPORTED_Autoneg);
7329
7330 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7331 cmd->supported |= (SUPPORTED_1000baseT_Half |
7332 SUPPORTED_1000baseT_Full);
7333
a4e2b347 7334 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 7335 cmd->supported |= (SUPPORTED_100baseT_Half |
7336 SUPPORTED_100baseT_Full |
7337 SUPPORTED_10baseT_Half |
7338 SUPPORTED_10baseT_Full |
7339 SUPPORTED_MII);
7340 else
7341 cmd->supported |= SUPPORTED_FIBRE;
7342
7343 cmd->advertising = tp->link_config.advertising;
7344 if (netif_running(dev)) {
7345 cmd->speed = tp->link_config.active_speed;
7346 cmd->duplex = tp->link_config.active_duplex;
7347 }
7348 cmd->port = 0;
7349 cmd->phy_address = PHY_ADDR;
7350 cmd->transceiver = 0;
7351 cmd->autoneg = tp->link_config.autoneg;
7352 cmd->maxtxpkt = 0;
7353 cmd->maxrxpkt = 0;
7354 return 0;
7355}
7356
7357static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7358{
7359 struct tg3 *tp = netdev_priv(dev);
7360
37ff238d 7361 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7362 /* These are the only valid advertisement bits allowed. */
7363 if (cmd->autoneg == AUTONEG_ENABLE &&
7364 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7365 ADVERTISED_1000baseT_Full |
7366 ADVERTISED_Autoneg |
7367 ADVERTISED_FIBRE)))
7368 return -EINVAL;
37ff238d
MC		 7369 /* Fiber can only do SPEED_1000. */
7370 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7371 (cmd->speed != SPEED_1000))
7372 return -EINVAL;
7373 /* Copper cannot force SPEED_1000. */
7374 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7375 (cmd->speed == SPEED_1000))
7376 return -EINVAL;
7377 else if ((cmd->speed == SPEED_1000) &&
7378 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7379 return -EINVAL;
1da177e4 7380
f47c11ee 7381 tg3_full_lock(tp, 0);
1da177e4
LT		 7382
7383 tp->link_config.autoneg = cmd->autoneg;
7384 if (cmd->autoneg == AUTONEG_ENABLE) {
7385 tp->link_config.advertising = cmd->advertising;
7386 tp->link_config.speed = SPEED_INVALID;
7387 tp->link_config.duplex = DUPLEX_INVALID;
7388 } else {
7389 tp->link_config.advertising = 0;
7390 tp->link_config.speed = cmd->speed;
7391 tp->link_config.duplex = cmd->duplex;
7392 }
7393
7394 if (netif_running(dev))
7395 tg3_setup_phy(tp, 1);
7396
f47c11ee 7397 tg3_full_unlock(tp);
1da177e4
LT		 7398
7399 return 0;
7400}
7401
7402static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7403{
7404 struct tg3 *tp = netdev_priv(dev);
7405
7406 strcpy(info->driver, DRV_MODULE_NAME);
7407 strcpy(info->version, DRV_MODULE_VERSION);
7408 strcpy(info->bus_info, pci_name(tp->pdev));
7409}
7410
7411static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7412{
7413 struct tg3 *tp = netdev_priv(dev);
7414
7415 wol->supported = WAKE_MAGIC;
7416 wol->wolopts = 0;
7417 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7418 wol->wolopts = WAKE_MAGIC;
7419 memset(&wol->sopass, 0, sizeof(wol->sopass));
7420}
7421
7422static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7423{
7424 struct tg3 *tp = netdev_priv(dev);
7425
7426 if (wol->wolopts & ~WAKE_MAGIC)
7427 return -EINVAL;
7428 if ((wol->wolopts & WAKE_MAGIC) &&
7429 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7430 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7431 return -EINVAL;
7432
f47c11ee 7433 spin_lock_bh(&tp->lock);
1da177e4
LT		 7434 if (wol->wolopts & WAKE_MAGIC)
7435 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7436 else
7437 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 7438 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7439
7440 return 0;
7441}
7442
7443static u32 tg3_get_msglevel(struct net_device *dev)
7444{
7445 struct tg3 *tp = netdev_priv(dev);
7446 return tp->msg_enable;
7447}
7448
7449static void tg3_set_msglevel(struct net_device *dev, u32 value)
7450{
7451 struct tg3 *tp = netdev_priv(dev);
7452 tp->msg_enable = value;
7453}
7454
7455#if TG3_TSO_SUPPORT != 0
7456static int tg3_set_tso(struct net_device *dev, u32 value)
7457{
7458 struct tg3 *tp = netdev_priv(dev);
7459
7460 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7461 if (value)
7462 return -EINVAL;
7463 return 0;
7464 }
7465 return ethtool_op_set_tso(dev, value);
7466}
7467#endif
7468
7469static int tg3_nway_reset(struct net_device *dev)
7470{
7471 struct tg3 *tp = netdev_priv(dev);
7472 u32 bmcr;
7473 int r;
7474
7475 if (!netif_running(dev))
7476 return -EAGAIN;
7477
c94e3941
MC		 7478 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7479 return -EINVAL;
7480
f47c11ee 7481 spin_lock_bh(&tp->lock);
1da177e4
LT		 7482 r = -EINVAL;
7483 tg3_readphy(tp, MII_BMCR, &bmcr);
7484 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 7485 ((bmcr & BMCR_ANENABLE) ||
7486 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7487 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7488 BMCR_ANENABLE);
1da177e4
LT		 7489 r = 0;
7490 }
f47c11ee 7491 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7492
7493 return r;
7494}
7495
7496static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7497{
7498 struct tg3 *tp = netdev_priv(dev);
7499
7500 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7501 ering->rx_mini_max_pending = 0;
7502 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7503
7504 ering->rx_pending = tp->rx_pending;
7505 ering->rx_mini_pending = 0;
7506 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7507 ering->tx_pending = tp->tx_pending;
7508}
7509
7510static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7511{
7512 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7513 int irq_sync = 0;
1da177e4
LT		 7514
7515 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7516 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7517 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7518 return -EINVAL;
7519
bbe832c0 7520 if (netif_running(dev)) {
1da177e4 7521 tg3_netif_stop(tp);
bbe832c0
MC		 7522 irq_sync = 1;
7523 }
1da177e4 7524
bbe832c0 7525 tg3_full_lock(tp, irq_sync);
1da177e4
LT		 7526
7527 tp->rx_pending = ering->rx_pending;
7528
7529 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7530 tp->rx_pending > 63)
7531 tp->rx_pending = 63;
7532 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7533 tp->tx_pending = ering->tx_pending;
7534
7535 if (netif_running(dev)) {
944d980e 7536 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7537 tg3_init_hw(tp);
7538 tg3_netif_start(tp);
7539 }
7540
f47c11ee 7541 tg3_full_unlock(tp);
1da177e4
LT		 7542
7543 return 0;
7544}
7545
7546static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7547{
7548 struct tg3 *tp = netdev_priv(dev);
7549
7550 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7551 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7552 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7553}
7554
7555static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7556{
7557 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7558 int irq_sync = 0;
1da177e4 7559
bbe832c0 7560 if (netif_running(dev)) {
1da177e4 7561 tg3_netif_stop(tp);
bbe832c0
MC		 7562 irq_sync = 1;
7563 }
1da177e4 7564
bbe832c0 7565 tg3_full_lock(tp, irq_sync);
f47c11ee 7566
1da177e4
LT		 7567 if (epause->autoneg)
7568 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7569 else
7570 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7571 if (epause->rx_pause)
7572 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7573 else
7574 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7575 if (epause->tx_pause)
7576 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7577 else
7578 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7579
7580 if (netif_running(dev)) {
944d980e 7581 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7582 tg3_init_hw(tp);
7583 tg3_netif_start(tp);
7584 }
f47c11ee
DM		 7585
7586 tg3_full_unlock(tp);
1da177e4
LT		 7587
7588 return 0;
7589}
7590
7591static u32 tg3_get_rx_csum(struct net_device *dev)
7592{
7593 struct tg3 *tp = netdev_priv(dev);
7594 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7595}
7596
7597static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7598{
7599 struct tg3 *tp = netdev_priv(dev);
7600
7601 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7602 if (data != 0)
7603 return -EINVAL;
7604 return 0;
7605 }
7606
f47c11ee 7607 spin_lock_bh(&tp->lock);
1da177e4
LT		 7608 if (data)
7609 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7610 else
7611 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 7612 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7613
7614 return 0;
7615}
7616
7617static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7618{
7619 struct tg3 *tp = netdev_priv(dev);
7620
7621 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7622 if (data != 0)
7623 return -EINVAL;
7624 return 0;
7625 }
7626
7627 if (data)
7628 dev->features |= NETIF_F_IP_CSUM;
7629 else
7630 dev->features &= ~NETIF_F_IP_CSUM;
7631
7632 return 0;
7633}
7634
7635static int tg3_get_stats_count (struct net_device *dev)
7636{
7637 return TG3_NUM_STATS;
7638}
7639
4cafd3f5
MC		 7640static int tg3_get_test_count (struct net_device *dev)
7641{
7642 return TG3_NUM_TEST;
7643}
7644
1da177e4
LT		 7645static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7646{
7647 switch (stringset) {
7648 case ETH_SS_STATS:
7649 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7650 break;
4cafd3f5
MC		 7651 case ETH_SS_TEST:
7652 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7653 break;
1da177e4
LT		 7654 default:
7655 WARN_ON(1); /* we need a WARN() */
7656 break;
7657 }
7658}
7659
4009a93d
MC		 7660static int tg3_phys_id(struct net_device *dev, u32 data)
7661{
7662 struct tg3 *tp = netdev_priv(dev);
7663 int i;
7664
7665 if (!netif_running(tp->dev))
7666 return -EAGAIN;
7667
7668 if (data == 0)
7669 data = 2;
7670
7671 for (i = 0; i < (data * 2); i++) {
7672 if ((i % 2) == 0)
7673 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7674 LED_CTRL_1000MBPS_ON |
7675 LED_CTRL_100MBPS_ON |
7676 LED_CTRL_10MBPS_ON |
7677 LED_CTRL_TRAFFIC_OVERRIDE |
7678 LED_CTRL_TRAFFIC_BLINK |
7679 LED_CTRL_TRAFFIC_LED);
7680
7681 else
7682 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7683 LED_CTRL_TRAFFIC_OVERRIDE);
7684
7685 if (msleep_interruptible(500))
7686 break;
7687 }
7688 tw32(MAC_LED_CTRL, tp->led_ctrl);
7689 return 0;
7690}
7691
1da177e4
LT		 7692static void tg3_get_ethtool_stats (struct net_device *dev,
7693 struct ethtool_stats *estats, u64 *tmp_stats)
7694{
7695 struct tg3 *tp = netdev_priv(dev);
7696 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7697}
7698
566f86ad
MC		 7699#define NVRAM_TEST_SIZE 0x100
7700
7701static int tg3_test_nvram(struct tg3 *tp)
7702{
7703 u32 *buf, csum;
7704 int i, j, err = 0;
7705
7706 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7707 if (buf == NULL)
7708 return -ENOMEM;
7709
7710 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7711 u32 val;
7712
7713 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7714 break;
7715 buf[j] = cpu_to_le32(val);
7716 }
7717 if (i < NVRAM_TEST_SIZE)
7718 goto out;
7719
7720 err = -EIO;
7721 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7722 goto out;
7723
7724 /* Bootstrap checksum at offset 0x10 */
7725 csum = calc_crc((unsigned char *) buf, 0x10);
7726 if(csum != cpu_to_le32(buf[0x10/4]))
7727 goto out;
7728
7729 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7730 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7731 if (csum != cpu_to_le32(buf[0xfc/4]))
7732 goto out;
7733
7734 err = 0;
7735
7736out:
7737 kfree(buf);
7738 return err;
7739}
7740
ca43007a
MC		 7741#define TG3_SERDES_TIMEOUT_SEC 2
7742#define TG3_COPPER_TIMEOUT_SEC 6
7743
7744static int tg3_test_link(struct tg3 *tp)
7745{
7746 int i, max;
7747
7748 if (!netif_running(tp->dev))
7749 return -ENODEV;
7750
4c987487 7751 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 7752 max = TG3_SERDES_TIMEOUT_SEC;
7753 else
7754 max = TG3_COPPER_TIMEOUT_SEC;
7755
7756 for (i = 0; i < max; i++) {
7757 if (netif_carrier_ok(tp->dev))
7758 return 0;
7759
7760 if (msleep_interruptible(1000))
7761 break;
7762 }
7763
7764 return -EIO;
7765}
7766
a71116d1
MC		 7767/* Only test the commonly used registers */
7768static int tg3_test_registers(struct tg3 *tp)
7769{
7770 int i, is_5705;
7771 u32 offset, read_mask, write_mask, val, save_val, read_val;
7772 static struct {
7773 u16 offset;
7774 u16 flags;
7775#define TG3_FL_5705 0x1
7776#define TG3_FL_NOT_5705 0x2
7777#define TG3_FL_NOT_5788 0x4
7778 u32 read_mask;
7779 u32 write_mask;
7780 } reg_tbl[] = {
7781 /* MAC Control Registers */
7782 { MAC_MODE, TG3_FL_NOT_5705,
7783 0x00000000, 0x00ef6f8c },
7784 { MAC_MODE, TG3_FL_5705,
7785 0x00000000, 0x01ef6b8c },
7786 { MAC_STATUS, TG3_FL_NOT_5705,
7787 0x03800107, 0x00000000 },
7788 { MAC_STATUS, TG3_FL_5705,
7789 0x03800100, 0x00000000 },
7790 { MAC_ADDR_0_HIGH, 0x0000,
7791 0x00000000, 0x0000ffff },
7792 { MAC_ADDR_0_LOW, 0x0000,
7793 0x00000000, 0xffffffff },
7794 { MAC_RX_MTU_SIZE, 0x0000,
7795 0x00000000, 0x0000ffff },
7796 { MAC_TX_MODE, 0x0000,
7797 0x00000000, 0x00000070 },
7798 { MAC_TX_LENGTHS, 0x0000,
7799 0x00000000, 0x00003fff },
7800 { MAC_RX_MODE, TG3_FL_NOT_5705,
7801 0x00000000, 0x000007fc },
7802 { MAC_RX_MODE, TG3_FL_5705,
7803 0x00000000, 0x000007dc },
7804 { MAC_HASH_REG_0, 0x0000,
7805 0x00000000, 0xffffffff },
7806 { MAC_HASH_REG_1, 0x0000,
7807 0x00000000, 0xffffffff },
7808 { MAC_HASH_REG_2, 0x0000,
7809 0x00000000, 0xffffffff },
7810 { MAC_HASH_REG_3, 0x0000,
7811 0x00000000, 0xffffffff },
7812
7813 /* Receive Data and Receive BD Initiator Control Registers. */
7814 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7815 0x00000000, 0xffffffff },
7816 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7817 0x00000000, 0xffffffff },
7818 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7819 0x00000000, 0x00000003 },
7820 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7821 0x00000000, 0xffffffff },
7822 { RCVDBDI_STD_BD+0, 0x0000,
7823 0x00000000, 0xffffffff },
7824 { RCVDBDI_STD_BD+4, 0x0000,
7825 0x00000000, 0xffffffff },
7826 { RCVDBDI_STD_BD+8, 0x0000,
7827 0x00000000, 0xffff0002 },
7828 { RCVDBDI_STD_BD+0xc, 0x0000,
7829 0x00000000, 0xffffffff },
7830
7831 /* Receive BD Initiator Control Registers. */
7832 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7833 0x00000000, 0xffffffff },
7834 { RCVBDI_STD_THRESH, TG3_FL_5705,
7835 0x00000000, 0x000003ff },
7836 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7837 0x00000000, 0xffffffff },
7838
7839 /* Host Coalescing Control Registers. */
7840 { HOSTCC_MODE, TG3_FL_NOT_5705,
7841 0x00000000, 0x00000004 },
7842 { HOSTCC_MODE, TG3_FL_5705,
7843 0x00000000, 0x000000f6 },
7844 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7845 0x00000000, 0xffffffff },
7846 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7847 0x00000000, 0x000003ff },
7848 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7849 0x00000000, 0xffffffff },
7850 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7851 0x00000000, 0x000003ff },
7852 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7853 0x00000000, 0xffffffff },
7854 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7855 0x00000000, 0x000000ff },
7856 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7857 0x00000000, 0xffffffff },
7858 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7859 0x00000000, 0x000000ff },
7860 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7861 0x00000000, 0xffffffff },
7862 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7863 0x00000000, 0xffffffff },
7864 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7865 0x00000000, 0xffffffff },
7866 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7867 0x00000000, 0x000000ff },
7868 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7869 0x00000000, 0xffffffff },
7870 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7871 0x00000000, 0x000000ff },
7872 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7873 0x00000000, 0xffffffff },
7874 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7875 0x00000000, 0xffffffff },
7876 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7877 0x00000000, 0xffffffff },
7878 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7879 0x00000000, 0xffffffff },
7880 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7881 0x00000000, 0xffffffff },
7882 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7883 0xffffffff, 0x00000000 },
7884 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7885 0xffffffff, 0x00000000 },
7886
7887 /* Buffer Manager Control Registers. */
7888 { BUFMGR_MB_POOL_ADDR, 0x0000,
7889 0x00000000, 0x007fff80 },
7890 { BUFMGR_MB_POOL_SIZE, 0x0000,
7891 0x00000000, 0x007fffff },
7892 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7893 0x00000000, 0x0000003f },
7894 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7895 0x00000000, 0x000001ff },
7896 { BUFMGR_MB_HIGH_WATER, 0x0000,
7897 0x00000000, 0x000001ff },
7898 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7899 0xffffffff, 0x00000000 },
7900 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7901 0xffffffff, 0x00000000 },
7902
7903 /* Mailbox Registers */
7904 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7905 0x00000000, 0x000001ff },
7906 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7907 0x00000000, 0x000001ff },
7908 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7909 0x00000000, 0x000007ff },
7910 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7911 0x00000000, 0x000001ff },
7912
7913 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7914 };
7915
7916 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7917 is_5705 = 1;
7918 else
7919 is_5705 = 0;
7920
7921 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7922 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7923 continue;
7924
7925 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7926 continue;
7927
7928 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7929 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7930 continue;
7931
7932 offset = (u32) reg_tbl[i].offset;
7933 read_mask = reg_tbl[i].read_mask;
7934 write_mask = reg_tbl[i].write_mask;
7935
7936 /* Save the original register content */
7937 save_val = tr32(offset);
7938
7939 /* Determine the read-only value. */
7940 read_val = save_val & read_mask;
7941
7942 /* Write zero to the register, then make sure the read-only bits
7943 * are not changed and the read/write bits are all zeros.
7944 */
7945 tw32(offset, 0);
7946
7947 val = tr32(offset);
7948
7949 /* Test the read-only and read/write bits. */
7950 if (((val & read_mask) != read_val) || (val & write_mask))
7951 goto out;
7952
7953 /* Write ones to all the bits defined by RdMask and WrMask, then
7954 * make sure the read-only bits are not changed and the
7955 * read/write bits are all ones.
7956 */
7957 tw32(offset, read_mask | write_mask);
7958
7959 val = tr32(offset);
7960
7961 /* Test the read-only bits. */
7962 if ((val & read_mask) != read_val)
7963 goto out;
7964
7965 /* Test the read/write bits. */
7966 if ((val & write_mask) != write_mask)
7967 goto out;
7968
7969 tw32(offset, save_val);
7970 }
7971
7972 return 0;
7973
7974out:
7975 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7976 tw32(offset, save_val);
7977 return -EIO;
7978}
7979
7942e1db
MC		 7980static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7981{
7982 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7983 int i;
7984 u32 j;
7985
7986 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7987 for (j = 0; j < len; j += 4) {
7988 u32 val;
7989
7990 tg3_write_mem(tp, offset + j, test_pattern[i]);
7991 tg3_read_mem(tp, offset + j, &val);
7992 if (val != test_pattern[i])
7993 return -EIO;
7994 }
7995 }
7996 return 0;
7997}
7998
7999static int tg3_test_memory(struct tg3 *tp)
8000{
8001 static struct mem_entry {
8002 u32 offset;
8003 u32 len;
8004 } mem_tbl_570x[] = {
38690194 8005 { 0x00000000, 0x00b50},
7942e1db
MC		 8006 { 0x00002000, 0x1c000},
8007 { 0xffffffff, 0x00000}
8008 }, mem_tbl_5705[] = {
8009 { 0x00000100, 0x0000c},
8010 { 0x00000200, 0x00008},
7942e1db
MC		 8011 { 0x00004000, 0x00800},
8012 { 0x00006000, 0x01000},
8013 { 0x00008000, 0x02000},
8014 { 0x00010000, 0x0e000},
8015 { 0xffffffff, 0x00000}
8016 };
8017 struct mem_entry *mem_tbl;
8018 int err = 0;
8019 int i;
8020
8021 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8022 mem_tbl = mem_tbl_5705;
8023 else
8024 mem_tbl = mem_tbl_570x;
8025
8026 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8027 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8028 mem_tbl[i].len)) != 0)
8029 break;
8030 }
8031
8032 return err;
8033}
8034
9f40dead
MC		 8035#define TG3_MAC_LOOPBACK 0
8036#define TG3_PHY_LOOPBACK 1
8037
8038static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8039{
9f40dead 8040 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8041 u32 desc_idx;
8042 struct sk_buff *skb, *rx_skb;
8043 u8 *tx_data;
8044 dma_addr_t map;
8045 int num_pkts, tx_len, rx_len, i, err;
8046 struct tg3_rx_buffer_desc *desc;
8047
9f40dead 8048 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8049 /* HW errata - mac loopback fails in some cases on 5780.
8050 * Normal traffic and PHY loopback are not affected by
8051 * errata.
8052 */
8053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8054 return 0;
8055
9f40dead
MC		 8056 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8057 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8058 MAC_MODE_PORT_MODE_GMII;
8059 tw32(MAC_MODE, mac_mode);
8060 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
c94e3941
MC		 8061 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8062 BMCR_SPEED1000);
8063 udelay(40);
8064 /* reset to prevent losing 1st rx packet intermittently */
8065 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8066 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8067 udelay(10);
8068 tw32_f(MAC_RX_MODE, tp->rx_mode);
8069 }
9f40dead
MC		 8070 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8071 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8072 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8073 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8074 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8075 }
8076 else
8077 return -EINVAL;
c76949a6
MC		 8078
8079 err = -EIO;
8080
c76949a6
MC		 8081 tx_len = 1514;
8082 skb = dev_alloc_skb(tx_len);
8083 tx_data = skb_put(skb, tx_len);
8084 memcpy(tx_data, tp->dev->dev_addr, 6);
8085 memset(tx_data + 6, 0x0, 8);
8086
8087 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8088
8089 for (i = 14; i < tx_len; i++)
8090 tx_data[i] = (u8) (i & 0xff);
8091
8092 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8093
8094 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8095 HOSTCC_MODE_NOW);
8096
8097 udelay(10);
8098
8099 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8100
c76949a6
MC		 8101 num_pkts = 0;
8102
9f40dead 8103 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8104
9f40dead 8105 tp->tx_prod++;
c76949a6
MC		 8106 num_pkts++;
8107
9f40dead
MC		 8108 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8109 tp->tx_prod);
09ee929c 8110 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8111
8112 udelay(10);
8113
8114 for (i = 0; i < 10; i++) {
8115 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8116 HOSTCC_MODE_NOW);
8117
8118 udelay(10);
8119
8120 tx_idx = tp->hw_status->idx[0].tx_consumer;
8121 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8122 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8123 (rx_idx == (rx_start_idx + num_pkts)))
8124 break;
8125 }
8126
8127 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8128 dev_kfree_skb(skb);
8129
9f40dead 8130 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8131 goto out;
8132
8133 if (rx_idx != rx_start_idx + num_pkts)
8134 goto out;
8135
8136 desc = &tp->rx_rcb[rx_start_idx];
8137 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8138 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8139 if (opaque_key != RXD_OPAQUE_RING_STD)
8140 goto out;
8141
8142 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8143 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8144 goto out;
8145
8146 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8147 if (rx_len != tx_len)
8148 goto out;
8149
8150 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8151
8152 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8153 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8154
8155 for (i = 14; i < tx_len; i++) {
8156 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8157 goto out;
8158 }
8159 err = 0;
8160
8161 /* tg3_free_rings will unmap and free the rx_skb */
8162out:
8163 return err;
8164}
8165
9f40dead
MC		 8166#define TG3_MAC_LOOPBACK_FAILED 1
8167#define TG3_PHY_LOOPBACK_FAILED 2
8168#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8169 TG3_PHY_LOOPBACK_FAILED)
8170
8171static int tg3_test_loopback(struct tg3 *tp)
8172{
8173 int err = 0;
8174
8175 if (!netif_running(tp->dev))
8176 return TG3_LOOPBACK_FAILED;
8177
8178 tg3_reset_hw(tp);
8179
8180 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8181 err |= TG3_MAC_LOOPBACK_FAILED;
8182 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8183 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8184 err |= TG3_PHY_LOOPBACK_FAILED;
8185 }
8186
8187 return err;
8188}
8189
4cafd3f5
MC		 8190static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8191 u64 *data)
8192{
566f86ad
MC		 8193 struct tg3 *tp = netdev_priv(dev);
8194
8195 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8196
8197 if (tg3_test_nvram(tp) != 0) {
8198 etest->flags |= ETH_TEST_FL_FAILED;
8199 data[0] = 1;
8200 }
ca43007a
MC		 8201 if (tg3_test_link(tp) != 0) {
8202 etest->flags |= ETH_TEST_FL_FAILED;
8203 data[1] = 1;
8204 }
a71116d1 8205 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 8206 int err, irq_sync = 0;
bbe832c0
MC		 8207
8208 if (netif_running(dev)) {
a71116d1 8209 tg3_netif_stop(tp);
bbe832c0
MC		 8210 irq_sync = 1;
8211 }
a71116d1 8212
bbe832c0 8213 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8214
8215 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 8216 err = tg3_nvram_lock(tp);
a71116d1
MC		 8217 tg3_halt_cpu(tp, RX_CPU_BASE);
8218 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8219 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 8220 if (!err)
8221 tg3_nvram_unlock(tp);
a71116d1
MC		 8222
8223 if (tg3_test_registers(tp) != 0) {
8224 etest->flags |= ETH_TEST_FL_FAILED;
8225 data[2] = 1;
8226 }
7942e1db
MC		 8227 if (tg3_test_memory(tp) != 0) {
8228 etest->flags |= ETH_TEST_FL_FAILED;
8229 data[3] = 1;
8230 }
9f40dead 8231 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 8232 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 8233
f47c11ee
DM		 8234 tg3_full_unlock(tp);
8235
d4bc3927
MC		 8236 if (tg3_test_interrupt(tp) != 0) {
8237 etest->flags |= ETH_TEST_FL_FAILED;
8238 data[5] = 1;
8239 }
f47c11ee
DM		 8240
8241 tg3_full_lock(tp, 0);
d4bc3927 8242
a71116d1
MC		 8243 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8244 if (netif_running(dev)) {
8245 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8246 tg3_init_hw(tp);
8247 tg3_netif_start(tp);
8248 }
f47c11ee
DM		 8249
8250 tg3_full_unlock(tp);
a71116d1 8251 }
4cafd3f5
MC		 8252}
8253
1da177e4
LT		 8254static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8255{
8256 struct mii_ioctl_data *data = if_mii(ifr);
8257 struct tg3 *tp = netdev_priv(dev);
8258 int err;
8259
8260 switch(cmd) {
8261 case SIOCGMIIPHY:
8262 data->phy_id = PHY_ADDR;
8263
8264 /* fallthru */
8265 case SIOCGMIIREG: {
8266 u32 mii_regval;
8267
8268 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8269 break; /* We have no PHY */
8270
f47c11ee 8271 spin_lock_bh(&tp->lock);
1da177e4 8272 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 8273 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8274
8275 data->val_out = mii_regval;
8276
8277 return err;
8278 }
8279
8280 case SIOCSMIIREG:
8281 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8282 break; /* We have no PHY */
8283
8284 if (!capable(CAP_NET_ADMIN))
8285 return -EPERM;
8286
f47c11ee 8287 spin_lock_bh(&tp->lock);
1da177e4 8288 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 8289 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8290
8291 return err;
8292
8293 default:
8294 /* do nothing */
8295 break;
8296 }
8297 return -EOPNOTSUPP;
8298}
8299
8300#if TG3_VLAN_TAG_USED
8301static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8302{
8303 struct tg3 *tp = netdev_priv(dev);
8304
f47c11ee 8305 tg3_full_lock(tp, 0);
1da177e4
LT		 8306
8307 tp->vlgrp = grp;
8308
8309 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8310 __tg3_set_rx_mode(dev);
8311
f47c11ee 8312 tg3_full_unlock(tp);
1da177e4
LT		 8313}
8314
8315static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8316{
8317 struct tg3 *tp = netdev_priv(dev);
8318
f47c11ee 8319 tg3_full_lock(tp, 0);
1da177e4
LT		 8320 if (tp->vlgrp)
8321 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 8322 tg3_full_unlock(tp);
1da177e4
LT		 8323}
8324#endif
8325
15f9850d
DM		 8326static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8327{
8328 struct tg3 *tp = netdev_priv(dev);
8329
8330 memcpy(ec, &tp->coal, sizeof(*ec));
8331 return 0;
8332}
8333
d244c892
MC		 8334static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8335{
8336 struct tg3 *tp = netdev_priv(dev);
8337 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8338 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8339
8340 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8341 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8342 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8343 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8344 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8345 }
8346
8347 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8348 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8349 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8350 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8351 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8352 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8353 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8354 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8355 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8356 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8357 return -EINVAL;
8358
8359 /* No rx interrupts will be generated if both are zero */
8360 if ((ec->rx_coalesce_usecs == 0) &&
8361 (ec->rx_max_coalesced_frames == 0))
8362 return -EINVAL;
8363
8364 /* No tx interrupts will be generated if both are zero */
8365 if ((ec->tx_coalesce_usecs == 0) &&
8366 (ec->tx_max_coalesced_frames == 0))
8367 return -EINVAL;
8368
8369 /* Only copy relevant parameters, ignore all others. */
8370 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8371 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8372 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8373 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8374 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8375 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8376 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8377 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8378 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8379
8380 if (netif_running(dev)) {
8381 tg3_full_lock(tp, 0);
8382 __tg3_set_coalesce(tp, &tp->coal);
8383 tg3_full_unlock(tp);
8384 }
8385 return 0;
8386}
8387
1da177e4
LT		 8388static struct ethtool_ops tg3_ethtool_ops = {
8389 .get_settings = tg3_get_settings,
8390 .set_settings = tg3_set_settings,
8391 .get_drvinfo = tg3_get_drvinfo,
8392 .get_regs_len = tg3_get_regs_len,
8393 .get_regs = tg3_get_regs,
8394 .get_wol = tg3_get_wol,
8395 .set_wol = tg3_set_wol,
8396 .get_msglevel = tg3_get_msglevel,
8397 .set_msglevel = tg3_set_msglevel,
8398 .nway_reset = tg3_nway_reset,
8399 .get_link = ethtool_op_get_link,
8400 .get_eeprom_len = tg3_get_eeprom_len,
8401 .get_eeprom = tg3_get_eeprom,
8402 .set_eeprom = tg3_set_eeprom,
8403 .get_ringparam = tg3_get_ringparam,
8404 .set_ringparam = tg3_set_ringparam,
8405 .get_pauseparam = tg3_get_pauseparam,
8406 .set_pauseparam = tg3_set_pauseparam,
8407 .get_rx_csum = tg3_get_rx_csum,
8408 .set_rx_csum = tg3_set_rx_csum,
8409 .get_tx_csum = ethtool_op_get_tx_csum,
8410 .set_tx_csum = tg3_set_tx_csum,
8411 .get_sg = ethtool_op_get_sg,
8412 .set_sg = ethtool_op_set_sg,
8413#if TG3_TSO_SUPPORT != 0
8414 .get_tso = ethtool_op_get_tso,
8415 .set_tso = tg3_set_tso,
8416#endif
4cafd3f5
MC		 8417 .self_test_count = tg3_get_test_count,
8418 .self_test = tg3_self_test,
1da177e4 8419 .get_strings = tg3_get_strings,
4009a93d 8420 .phys_id = tg3_phys_id,
1da177e4
LT		 8421 .get_stats_count = tg3_get_stats_count,
8422 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 8423 .get_coalesce = tg3_get_coalesce,
d244c892 8424 .set_coalesce = tg3_set_coalesce,
2ff43697 8425 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 8426};
8427
8428static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8429{
8430 u32 cursize, val;
8431
8432 tp->nvram_size = EEPROM_CHIP_SIZE;
8433
8434 if (tg3_nvram_read(tp, 0, &val) != 0)
8435 return;
8436
8437 if (swab32(val) != TG3_EEPROM_MAGIC)
8438 return;
8439
8440 /*
8441 * Size the chip by reading offsets at increasing powers of two.
8442 * When we encounter our validation signature, we know the addressing
8443 * has wrapped around, and thus have our chip size.
8444 */
8445 cursize = 0x800;
8446
8447 while (cursize < tp->nvram_size) {
8448 if (tg3_nvram_read(tp, cursize, &val) != 0)
8449 return;
8450
8451 if (swab32(val) == TG3_EEPROM_MAGIC)
8452 break;
8453
8454 cursize <<= 1;
8455 }
8456
8457 tp->nvram_size = cursize;
8458}
8459
8460static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8461{
8462 u32 val;
8463
8464 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8465 if (val != 0) {
8466 tp->nvram_size = (val >> 16) * 1024;
8467 return;
8468 }
8469 }
8470 tp->nvram_size = 0x20000;
8471}
8472
8473static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8474{
8475 u32 nvcfg1;
8476
8477 nvcfg1 = tr32(NVRAM_CFG1);
8478 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8479 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8480 }
8481 else {
8482 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8483 tw32(NVRAM_CFG1, nvcfg1);
8484 }
8485
4c987487 8486 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 8487 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 8488 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8489 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8490 tp->nvram_jedecnum = JEDEC_ATMEL;
8491 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8492 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8493 break;
8494 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8495 tp->nvram_jedecnum = JEDEC_ATMEL;
8496 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8497 break;
8498 case FLASH_VENDOR_ATMEL_EEPROM:
8499 tp->nvram_jedecnum = JEDEC_ATMEL;
8500 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8501 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8502 break;
8503 case FLASH_VENDOR_ST:
8504 tp->nvram_jedecnum = JEDEC_ST;
8505 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8507 break;
8508 case FLASH_VENDOR_SAIFUN:
8509 tp->nvram_jedecnum = JEDEC_SAIFUN;
8510 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8511 break;
8512 case FLASH_VENDOR_SST_SMALL:
8513 case FLASH_VENDOR_SST_LARGE:
8514 tp->nvram_jedecnum = JEDEC_SST;
8515 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8516 break;
8517 }
8518 }
8519 else {
8520 tp->nvram_jedecnum = JEDEC_ATMEL;
8521 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8522 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8523 }
8524}
8525
361b4ac2
MC		 8526static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8527{
8528 u32 nvcfg1;
8529
8530 nvcfg1 = tr32(NVRAM_CFG1);
8531
e6af301b
MC		 8532 /* NVRAM protection for TPM */
8533 if (nvcfg1 & (1 << 27))
8534 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8535
361b4ac2
MC		 8536 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8537 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8538 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8539 tp->nvram_jedecnum = JEDEC_ATMEL;
8540 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8541 break;
8542 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8543 tp->nvram_jedecnum = JEDEC_ATMEL;
8544 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8545 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8546 break;
8547 case FLASH_5752VENDOR_ST_M45PE10:
8548 case FLASH_5752VENDOR_ST_M45PE20:
8549 case FLASH_5752VENDOR_ST_M45PE40:
8550 tp->nvram_jedecnum = JEDEC_ST;
8551 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8552 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8553 break;
8554 }
8555
8556 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8557 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8558 case FLASH_5752PAGE_SIZE_256:
8559 tp->nvram_pagesize = 256;
8560 break;
8561 case FLASH_5752PAGE_SIZE_512:
8562 tp->nvram_pagesize = 512;
8563 break;
8564 case FLASH_5752PAGE_SIZE_1K:
8565 tp->nvram_pagesize = 1024;
8566 break;
8567 case FLASH_5752PAGE_SIZE_2K:
8568 tp->nvram_pagesize = 2048;
8569 break;
8570 case FLASH_5752PAGE_SIZE_4K:
8571 tp->nvram_pagesize = 4096;
8572 break;
8573 case FLASH_5752PAGE_SIZE_264:
8574 tp->nvram_pagesize = 264;
8575 break;
8576 }
8577 }
8578 else {
8579 /* For eeprom, set pagesize to maximum eeprom size */
8580 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8581
8582 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8583 tw32(NVRAM_CFG1, nvcfg1);
8584 }
8585}
8586
1da177e4
LT		 8587/* Chips other than 5700/5701 use the NVRAM for fetching info. */
8588static void __devinit tg3_nvram_init(struct tg3 *tp)
8589{
8590 int j;
8591
8592 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8593 return;
8594
8595 tw32_f(GRC_EEPROM_ADDR,
8596 (EEPROM_ADDR_FSM_RESET |
8597 (EEPROM_DEFAULT_CLOCK_PERIOD <<
8598 EEPROM_ADDR_CLKPERD_SHIFT)));
8599
8600 /* XXX schedule_timeout() ... */
8601 for (j = 0; j < 100; j++)
8602 udelay(10);
8603
8604 /* Enable seeprom accesses. */
8605 tw32_f(GRC_LOCAL_CTRL,
8606 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8607 udelay(100);
8608
8609 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8610 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8611 tp->tg3_flags |= TG3_FLAG_NVRAM;
8612
ec41c7df
MC		 8613 if (tg3_nvram_lock(tp)) {
8614 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
8615 "tg3_nvram_init failed.\n", tp->dev->name);
8616 return;
8617 }
e6af301b 8618 tg3_enable_nvram_access(tp);
1da177e4 8619
361b4ac2
MC		 8620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8621 tg3_get_5752_nvram_info(tp);
8622 else
8623 tg3_get_nvram_info(tp);
8624
1da177e4
LT		 8625 tg3_get_nvram_size(tp);
8626
e6af301b 8627 tg3_disable_nvram_access(tp);
381291b7 8628 tg3_nvram_unlock(tp);
1da177e4
LT		 8629
8630 } else {
8631 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8632
8633 tg3_get_eeprom_size(tp);
8634 }
8635}
8636
8637static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8638 u32 offset, u32 *val)
8639{
8640 u32 tmp;
8641 int i;
8642
8643 if (offset > EEPROM_ADDR_ADDR_MASK ||
8644 (offset % 4) != 0)
8645 return -EINVAL;
8646
8647 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8648 EEPROM_ADDR_DEVID_MASK |
8649 EEPROM_ADDR_READ);
8650 tw32(GRC_EEPROM_ADDR,
8651 tmp |
8652 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8653 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8654 EEPROM_ADDR_ADDR_MASK) |
8655 EEPROM_ADDR_READ | EEPROM_ADDR_START);
8656
8657 for (i = 0; i < 10000; i++) {
8658 tmp = tr32(GRC_EEPROM_ADDR);
8659
8660 if (tmp & EEPROM_ADDR_COMPLETE)
8661 break;
8662 udelay(100);
8663 }
8664 if (!(tmp & EEPROM_ADDR_COMPLETE))
8665 return -EBUSY;
8666
8667 *val = tr32(GRC_EEPROM_DATA);
8668 return 0;
8669}
8670
8671#define NVRAM_CMD_TIMEOUT 10000
8672
8673static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8674{
8675 int i;
8676
8677 tw32(NVRAM_CMD, nvram_cmd);
8678 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8679 udelay(10);
8680 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8681 udelay(10);
8682 break;
8683 }
8684 }
8685 if (i == NVRAM_CMD_TIMEOUT) {
8686 return -EBUSY;
8687 }
8688 return 0;
8689}
8690
8691static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8692{
8693 int ret;
8694
8695 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8696 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8697 return -EINVAL;
8698 }
8699
8700 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8701 return tg3_nvram_read_using_eeprom(tp, offset, val);
8702
8703 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8704 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8705 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8706
8707 offset = ((offset / tp->nvram_pagesize) <<
8708 ATMEL_AT45DB0X1B_PAGE_POS) +
8709 (offset % tp->nvram_pagesize);
8710 }
8711
8712 if (offset > NVRAM_ADDR_MSK)
8713 return -EINVAL;
8714
ec41c7df
MC		 8715 ret = tg3_nvram_lock(tp);
8716 if (ret)
8717 return ret;
1da177e4 8718
e6af301b 8719 tg3_enable_nvram_access(tp);
1da177e4
LT		 8720
8721 tw32(NVRAM_ADDR, offset);
8722 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8723 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8724
8725 if (ret == 0)
8726 *val = swab32(tr32(NVRAM_RDDATA));
8727
e6af301b 8728 tg3_disable_nvram_access(tp);
1da177e4 8729
381291b7
MC		 8730 tg3_nvram_unlock(tp);
8731
1da177e4
LT		 8732 return ret;
8733}
8734
8735static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8736 u32 offset, u32 len, u8 *buf)
8737{
8738 int i, j, rc = 0;
8739 u32 val;
8740
8741 for (i = 0; i < len; i += 4) {
8742 u32 addr, data;
8743
8744 addr = offset + i;
8745
8746 memcpy(&data, buf + i, 4);
8747
8748 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8749
8750 val = tr32(GRC_EEPROM_ADDR);
8751 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8752
8753 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8754 EEPROM_ADDR_READ);
8755 tw32(GRC_EEPROM_ADDR, val |
8756 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8757 (addr & EEPROM_ADDR_ADDR_MASK) |
8758 EEPROM_ADDR_START |
8759 EEPROM_ADDR_WRITE);
8760
8761 for (j = 0; j < 10000; j++) {
8762 val = tr32(GRC_EEPROM_ADDR);
8763
8764 if (val & EEPROM_ADDR_COMPLETE)
8765 break;
8766 udelay(100);
8767 }
8768 if (!(val & EEPROM_ADDR_COMPLETE)) {
8769 rc = -EBUSY;
8770 break;
8771 }
8772 }
8773
8774 return rc;
8775}
8776
8777/* offset and length are dword aligned */
8778static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8779 u8 *buf)
8780{
8781 int ret = 0;
8782 u32 pagesize = tp->nvram_pagesize;
8783 u32 pagemask = pagesize - 1;
8784 u32 nvram_cmd;
8785 u8 *tmp;
8786
8787 tmp = kmalloc(pagesize, GFP_KERNEL);
8788 if (tmp == NULL)
8789 return -ENOMEM;
8790
8791 while (len) {
8792 int j;
e6af301b 8793 u32 phy_addr, page_off, size;
1da177e4
LT		 8794
8795 phy_addr = offset & ~pagemask;
8796
8797 for (j = 0; j < pagesize; j += 4) {
8798 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8799 (u32 *) (tmp + j))))
8800 break;
8801 }
8802 if (ret)
8803 break;
8804
8805 page_off = offset & pagemask;
8806 size = pagesize;
8807 if (len < size)
8808 size = len;
8809
8810 len -= size;
8811
8812 memcpy(tmp + page_off, buf, size);
8813
8814 offset = offset + (pagesize - page_off);
8815
e6af301b 8816 tg3_enable_nvram_access(tp);
1da177e4
LT		 8817
8818 /*
8819 * Before we can erase the flash page, we need
8820 * to issue a special "write enable" command.
8821 */
8822 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8823
8824 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8825 break;
8826
8827 /* Erase the target page */
8828 tw32(NVRAM_ADDR, phy_addr);
8829
8830 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8831 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8832
8833 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8834 break;
8835
8836 /* Issue another write enable to start the write. */
8837 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8838
8839 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8840 break;
8841
8842 for (j = 0; j < pagesize; j += 4) {
8843 u32 data;
8844
8845 data = *((u32 *) (tmp + j));
8846 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8847
8848 tw32(NVRAM_ADDR, phy_addr + j);
8849
8850 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8851 NVRAM_CMD_WR;
8852
8853 if (j == 0)
8854 nvram_cmd |= NVRAM_CMD_FIRST;
8855 else if (j == (pagesize - 4))
8856 nvram_cmd |= NVRAM_CMD_LAST;
8857
8858 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8859 break;
8860 }
8861 if (ret)
8862 break;
8863 }
8864
8865 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8866 tg3_nvram_exec_cmd(tp, nvram_cmd);
8867
8868 kfree(tmp);
8869
8870 return ret;
8871}
8872
8873/* offset and length are dword aligned */
8874static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8875 u8 *buf)
8876{
8877 int i, ret = 0;
8878
8879 for (i = 0; i < len; i += 4, offset += 4) {
8880 u32 data, page_off, phy_addr, nvram_cmd;
8881
8882 memcpy(&data, buf + i, 4);
8883 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8884
8885 page_off = offset % tp->nvram_pagesize;
8886
8887 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8888 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8889
8890 phy_addr = ((offset / tp->nvram_pagesize) <<
8891 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8892 }
8893 else {
8894 phy_addr = offset;
8895 }
8896
8897 tw32(NVRAM_ADDR, phy_addr);
8898
8899 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8900
8901 if ((page_off == 0) || (i == 0))
8902 nvram_cmd |= NVRAM_CMD_FIRST;
8903 else if (page_off == (tp->nvram_pagesize - 4))
8904 nvram_cmd |= NVRAM_CMD_LAST;
8905
8906 if (i == (len - 4))
8907 nvram_cmd |= NVRAM_CMD_LAST;
8908
4c987487
MC		 8909 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8910 (tp->nvram_jedecnum == JEDEC_ST) &&
8911 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 8912
8913 if ((ret = tg3_nvram_exec_cmd(tp,
8914 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8915 NVRAM_CMD_DONE)))
8916
8917 break;
8918 }
8919 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8920 /* We always do complete word writes to eeprom. */
8921 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8922 }
8923
8924 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8925 break;
8926 }
8927 return ret;
8928}
8929
8930/* offset and length are dword aligned */
8931static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8932{
8933 int ret;
8934
8935 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8936 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8937 return -EINVAL;
8938 }
8939
8940 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 8941 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8942 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 8943 udelay(40);
8944 }
8945
8946 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8947 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8948 }
8949 else {
8950 u32 grc_mode;
8951
ec41c7df
MC		 8952 ret = tg3_nvram_lock(tp);
8953 if (ret)
8954 return ret;
1da177e4 8955
e6af301b
MC		 8956 tg3_enable_nvram_access(tp);
8957 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8958 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 8959 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 8960
8961 grc_mode = tr32(GRC_MODE);
8962 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8963
8964 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8965 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8966
8967 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8968 buf);
8969 }
8970 else {
8971 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8972 buf);
8973 }
8974
8975 grc_mode = tr32(GRC_MODE);
8976 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8977
e6af301b 8978 tg3_disable_nvram_access(tp);
1da177e4
LT		 8979 tg3_nvram_unlock(tp);
8980 }
8981
8982 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 8983 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 8984 udelay(40);
8985 }
8986
8987 return ret;
8988}
8989
8990struct subsys_tbl_ent {
8991 u16 subsys_vendor, subsys_devid;
8992 u32 phy_id;
8993};
8994
8995static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8996 /* Broadcom boards. */
8997 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8998 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8999 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9000 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9001 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9002 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9003 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9004 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9005 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9006 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9007 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9008
9009 /* 3com boards. */
9010 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9011 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9012 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9013 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9014 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9015
9016 /* DELL boards. */
9017 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9018 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9019 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9020 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9021
9022 /* Compaq boards. */
9023 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9024 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9025 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9026 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9027 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9028
9029 /* IBM boards. */
9030 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9031};
9032
9033static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9034{
9035 int i;
9036
9037 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9038 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9039 tp->pdev->subsystem_vendor) &&
9040 (subsys_id_to_phy_id[i].subsys_devid ==
9041 tp->pdev->subsystem_device))
9042 return &subsys_id_to_phy_id[i];
9043 }
9044 return NULL;
9045}
9046
7d0c41ef
MC		 9047/* Since this function may be called in D3-hot power state during
9048 * tg3_init_one(), only config cycles are allowed.
9049 */
9050static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9051{
1da177e4 9052 u32 val;
7d0c41ef
MC		 9053
9054 /* Make sure register accesses (indirect or otherwise)
9055 * will function correctly.
9056 */
9057 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9058 tp->misc_host_ctrl);
1da177e4
LT		 9059
9060 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 9061 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9062
1da177e4
LT		 9063 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9064 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9065 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 9066 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9067 int eeprom_phy_serdes = 0;
1da177e4
LT		 9068
9069 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9070 tp->nic_sram_data_cfg = nic_cfg;
9071
9072 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9073 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9074 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9075 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9076 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9077 (ver > 0) && (ver < 0x100))
9078 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9079
1da177e4
LT		 9080 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9081 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9082 eeprom_phy_serdes = 1;
9083
9084 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9085 if (nic_phy_id != 0) {
9086 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9087 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9088
9089 eeprom_phy_id = (id1 >> 16) << 10;
9090 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9091 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9092 } else
9093 eeprom_phy_id = 0;
9094
7d0c41ef 9095 tp->phy_id = eeprom_phy_id;
747e8f8b 9096 if (eeprom_phy_serdes) {
a4e2b347 9097 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 9098 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9099 else
9100 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9101 }
7d0c41ef 9102
cbf46853 9103 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9104 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9105 SHASTA_EXT_LED_MODE_MASK);
cbf46853 9106 else
1da177e4
LT		 9107 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9108
9109 switch (led_cfg) {
9110 default:
9111 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9112 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9113 break;
9114
9115 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9116 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9117 break;
9118
9119 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9120 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 9121
9122 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9123 * read on some older 5700/5701 bootcode.
9124 */
9125 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9126 ASIC_REV_5700 ||
9127 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9128 ASIC_REV_5701)
9129 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9130
1da177e4
LT		 9131 break;
9132
9133 case SHASTA_EXT_LED_SHARED:
9134 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9135 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9136 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9137 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9138 LED_CTRL_MODE_PHY_2);
9139 break;
9140
9141 case SHASTA_EXT_LED_MAC:
9142 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9143 break;
9144
9145 case SHASTA_EXT_LED_COMBO:
9146 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9147 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9148 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9149 LED_CTRL_MODE_PHY_2);
9150 break;
9151
9152 };
9153
9154 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9155 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9156 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9157 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9158
9159 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9160 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9161 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9162 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9163
9164 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9165 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 9166 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9167 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9168 }
9169 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9170 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9171
9172 if (cfg2 & (1 << 17))
9173 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9174
9175 /* serdes signal pre-emphasis in register 0x590 set by */
9176 /* bootcode if bit 18 is set */
9177 if (cfg2 & (1 << 18))
9178 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9179 }
7d0c41ef
MC		 9180}
9181
9182static int __devinit tg3_phy_probe(struct tg3 *tp)
9183{
9184 u32 hw_phy_id_1, hw_phy_id_2;
9185 u32 hw_phy_id, hw_phy_id_masked;
9186 int err;
1da177e4
LT		 9187
9188 /* Reading the PHY ID register can conflict with ASF
9189 * firwmare access to the PHY hardware.
9190 */
9191 err = 0;
9192 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9193 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9194 } else {
9195 /* Now read the physical PHY_ID from the chip and verify
9196 * that it is sane. If it doesn't look good, we fall back
9197 * to either the hard-coded table based PHY_ID and failing
9198 * that the value found in the eeprom area.
9199 */
9200 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9201 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9202
9203 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9204 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9205 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9206
9207 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9208 }
9209
9210 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9211 tp->phy_id = hw_phy_id;
9212 if (hw_phy_id_masked == PHY_ID_BCM8002)
9213 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 9214 else
9215 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 9216 } else {
7d0c41ef
MC		 9217 if (tp->phy_id != PHY_ID_INVALID) {
9218 /* Do nothing, phy ID already set up in
9219 * tg3_get_eeprom_hw_cfg().
9220 */
1da177e4
LT		 9221 } else {
9222 struct subsys_tbl_ent *p;
9223
9224 /* No eeprom signature? Try the hardcoded
9225 * subsys device table.
9226 */
9227 p = lookup_by_subsys(tp);
9228 if (!p)
9229 return -ENODEV;
9230
9231 tp->phy_id = p->phy_id;
9232 if (!tp->phy_id ||
9233 tp->phy_id == PHY_ID_BCM8002)
9234 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9235 }
9236 }
9237
747e8f8b 9238 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4
LT		 9239 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9240 u32 bmsr, adv_reg, tg3_ctrl;
9241
9242 tg3_readphy(tp, MII_BMSR, &bmsr);
9243 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9244 (bmsr & BMSR_LSTATUS))
9245 goto skip_phy_reset;
9246
9247 err = tg3_phy_reset(tp);
9248 if (err)
9249 return err;
9250
9251 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9252 ADVERTISE_100HALF | ADVERTISE_100FULL |
9253 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9254 tg3_ctrl = 0;
9255 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9256 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9257 MII_TG3_CTRL_ADV_1000_FULL);
9258 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9259 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9260 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9261 MII_TG3_CTRL_ENABLE_AS_MASTER);
9262 }
9263
9264 if (!tg3_copper_is_advertising_all(tp)) {
9265 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9266
9267 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9268 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9269
9270 tg3_writephy(tp, MII_BMCR,
9271 BMCR_ANENABLE | BMCR_ANRESTART);
9272 }
9273 tg3_phy_set_wirespeed(tp);
9274
9275 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9276 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9277 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9278 }
9279
9280skip_phy_reset:
9281 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9282 err = tg3_init_5401phy_dsp(tp);
9283 if (err)
9284 return err;
9285 }
9286
9287 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9288 err = tg3_init_5401phy_dsp(tp);
9289 }
9290
747e8f8b 9291 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 9292 tp->link_config.advertising =
9293 (ADVERTISED_1000baseT_Half |
9294 ADVERTISED_1000baseT_Full |
9295 ADVERTISED_Autoneg |
9296 ADVERTISED_FIBRE);
9297 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9298 tp->link_config.advertising &=
9299 ~(ADVERTISED_1000baseT_Half |
9300 ADVERTISED_1000baseT_Full);
9301
9302 return err;
9303}
9304
9305static void __devinit tg3_read_partno(struct tg3 *tp)
9306{
9307 unsigned char vpd_data[256];
9308 int i;
9309
9310 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9311 /* Sun decided not to put the necessary bits in the
9312 * NVRAM of their onboard tg3 parts :(
9313 */
9314 strcpy(tp->board_part_number, "Sun 570X");
9315 return;
9316 }
9317
9318 for (i = 0; i < 256; i += 4) {
9319 u32 tmp;
9320
9321 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9322 goto out_not_found;
9323
9324 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9325 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9326 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9327 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9328 }
9329
9330 /* Now parse and find the part number. */
9331 for (i = 0; i < 256; ) {
9332 unsigned char val = vpd_data[i];
9333 int block_end;
9334
9335 if (val == 0x82 || val == 0x91) {
9336 i = (i + 3 +
9337 (vpd_data[i + 1] +
9338 (vpd_data[i + 2] << 8)));
9339 continue;
9340 }
9341
9342 if (val != 0x90)
9343 goto out_not_found;
9344
9345 block_end = (i + 3 +
9346 (vpd_data[i + 1] +
9347 (vpd_data[i + 2] << 8)));
9348 i += 3;
9349 while (i < block_end) {
9350 if (vpd_data[i + 0] == 'P' &&
9351 vpd_data[i + 1] == 'N') {
9352 int partno_len = vpd_data[i + 2];
9353
9354 if (partno_len > 24)
9355 goto out_not_found;
9356
9357 memcpy(tp->board_part_number,
9358 &vpd_data[i + 3],
9359 partno_len);
9360
9361 /* Success. */
9362 return;
9363 }
9364 }
9365
9366 /* Part number not found. */
9367 goto out_not_found;
9368 }
9369
9370out_not_found:
9371 strcpy(tp->board_part_number, "none");
9372}
9373
9374#ifdef CONFIG_SPARC64
9375static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9376{
9377 struct pci_dev *pdev = tp->pdev;
9378 struct pcidev_cookie *pcp = pdev->sysdata;
9379
9380 if (pcp != NULL) {
9381 int node = pcp->prom_node;
9382 u32 venid;
9383 int err;
9384
9385 err = prom_getproperty(node, "subsystem-vendor-id",
9386 (char *) &venid, sizeof(venid));
9387 if (err == 0 || err == -1)
9388 return 0;
9389 if (venid == PCI_VENDOR_ID_SUN)
9390 return 1;
9391 }
9392 return 0;
9393}
9394#endif
9395
9396static int __devinit tg3_get_invariants(struct tg3 *tp)
9397{
9398 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 9399 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9400 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
399de50b
MC		 9401 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9402 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 9403 { },
9404 };
9405 u32 misc_ctrl_reg;
9406 u32 cacheline_sz_reg;
9407 u32 pci_state_reg, grc_misc_cfg;
9408 u32 val;
9409 u16 pci_cmd;
9410 int err;
9411
9412#ifdef CONFIG_SPARC64
9413 if (tg3_is_sun_570X(tp))
9414 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9415#endif
9416
1da177e4
LT		 9417 /* Force memory write invalidate off. If we leave it on,
9418 * then on 5700_BX chips we have to enable a workaround.
9419 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9420 * to match the cacheline size. The Broadcom driver have this
9421 * workaround but turns MWI off all the times so never uses
9422 * it. This seems to suggest that the workaround is insufficient.
9423 */
9424 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9425 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9426 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9427
9428 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9429 * has the register indirect write enable bit set before
9430 * we try to access any of the MMIO registers. It is also
9431 * critical that the PCI-X hw workaround situation is decided
9432 * before that as well.
9433 */
9434 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9435 &misc_ctrl_reg);
9436
9437 tp->pci_chip_rev_id = (misc_ctrl_reg >>
9438 MISC_HOST_CTRL_CHIPREV_SHIFT);
9439
ff645bec
MC		 9440 /* Wrong chip ID in 5752 A0. This code can be removed later
9441 * as A0 is not in production.
9442 */
9443 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9444 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9445
6892914f
MC		 9446 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9447 * we need to disable memory and use config. cycles
9448 * only to access all registers. The 5702/03 chips
9449 * can mistakenly decode the special cycles from the
9450 * ICH chipsets as memory write cycles, causing corruption
9451 * of register and memory space. Only certain ICH bridges
9452 * will drive special cycles with non-zero data during the
9453 * address phase which can fall within the 5703's address
9454 * range. This is not an ICH bug as the PCI spec allows
9455 * non-zero address during special cycles. However, only
9456 * these ICH bridges are known to drive non-zero addresses
9457 * during special cycles.
9458 *
9459 * Since special cycles do not cross PCI bridges, we only
9460 * enable this workaround if the 5703 is on the secondary
9461 * bus of these ICH bridges.
9462 */
9463 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9464 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9465 static struct tg3_dev_id {
9466 u32 vendor;
9467 u32 device;
9468 u32 rev;
9469 } ich_chipsets[] = {
9470 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9471 PCI_ANY_ID },
9472 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9473 PCI_ANY_ID },
9474 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9475 0xa },
9476 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9477 PCI_ANY_ID },
9478 { },
9479 };
9480 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9481 struct pci_dev *bridge = NULL;
9482
9483 while (pci_id->vendor != 0) {
9484 bridge = pci_get_device(pci_id->vendor, pci_id->device,
9485 bridge);
9486 if (!bridge) {
9487 pci_id++;
9488 continue;
9489 }
9490 if (pci_id->rev != PCI_ANY_ID) {
9491 u8 rev;
9492
9493 pci_read_config_byte(bridge, PCI_REVISION_ID,
9494 &rev);
9495 if (rev > pci_id->rev)
9496 continue;
9497 }
9498 if (bridge->subordinate &&
9499 (bridge->subordinate->number ==
9500 tp->pdev->bus->number)) {
9501
9502 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9503 pci_dev_put(bridge);
9504 break;
9505 }
9506 }
9507 }
9508
4cf78e4f 9509 /* Find msi capability. */
a4e2b347
MC		 9510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
9511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9512 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4cf78e4f 9513 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 9514 }
4cf78e4f 9515
1da177e4
LT		 9516 /* Initialize misc host control in PCI block. */
9517 tp->misc_host_ctrl |= (misc_ctrl_reg &
9518 MISC_HOST_CTRL_CHIPREV);
9519 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9520 tp->misc_host_ctrl);
9521
9522 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9523 &cacheline_sz_reg);
9524
9525 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
9526 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
9527 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
9528 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
9529
6708e5cc 9530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 9531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
a4e2b347 9532 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 9533 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9534
1b440c56
JL		 9535 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9536 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9537 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9538
bb7064dc 9539 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9540 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9541
0f893dc6
MC		 9542 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9543 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9544 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9545 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9546
1da177e4
LT		 9547 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9548 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9549
399de50b
MC		 9550 /* If we have an AMD 762 or VIA K8T800 chipset, write
9551 * reordering to the mailbox registers done by the host
9552 * controller can cause major troubles. We read back from
9553 * every mailbox register write to force the writes to be
9554 * posted to the chip in order.
9555 */
9556 if (pci_dev_present(write_reorder_chipsets) &&
9557 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9558 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9559
1da177e4
LT		 9560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9561 tp->pci_lat_timer < 64) {
9562 tp->pci_lat_timer = 64;
9563
9564 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
9565 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
9566 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
9567 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
9568
9569 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9570 cacheline_sz_reg);
9571 }
9572
9573 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9574 &pci_state_reg);
9575
9576 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9577 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9578
9579 /* If this is a 5700 BX chipset, and we are in PCI-X
9580 * mode, enable register write workaround.
9581 *
9582 * The workaround is to use indirect register accesses
9583 * for all chip writes not to mailbox registers.
9584 */
9585 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9586 u32 pm_reg;
9587 u16 pci_cmd;
9588
9589 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9590
9591 /* The chip can have it's power management PCI config
9592 * space registers clobbered due to this bug.
9593 * So explicitly force the chip into D0 here.
9594 */
9595 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9596 &pm_reg);
9597 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9598 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9599 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9600 pm_reg);
9601
9602 /* Also, force SERR#/PERR# in PCI command. */
9603 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9604 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9605 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9606 }
9607 }
9608
087fe256
MC		 9609 /* 5700 BX chips need to have their TX producer index mailboxes
9610 * written twice to workaround a bug.
9611 */
9612 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9613 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9614
1da177e4
LT		 9615 /* Back to back register writes can cause problems on this chip,
9616 * the workaround is to read back all reg writes except those to
9617 * mailbox regs. See tg3_write_indirect_reg32().
9618 *
9619 * PCI Express 5750_A0 rev chips need this workaround too.
9620 */
9621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9622 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9623 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9624 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9625
9626 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9627 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9628 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9629 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9630
9631 /* Chip-specific fixup from Broadcom driver */
9632 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9633 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9634 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9635 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9636 }
9637
1ee582d8 9638 /* Default fast path register access methods */
20094930 9639 tp->read32 = tg3_read32;
1ee582d8 9640 tp->write32 = tg3_write32;
09ee929c 9641 tp->read32_mbox = tg3_read32;
20094930 9642 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 9643 tp->write32_tx_mbox = tg3_write32;
9644 tp->write32_rx_mbox = tg3_write32;
9645
9646 /* Various workaround register access methods */
9647 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9648 tp->write32 = tg3_write_indirect_reg32;
9649 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9650 tp->write32 = tg3_write_flush_reg32;
9651
9652 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9653 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9654 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9655 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9656 tp->write32_rx_mbox = tg3_write_flush_reg32;
9657 }
20094930 9658
6892914f
MC		 9659 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9660 tp->read32 = tg3_read_indirect_reg32;
9661 tp->write32 = tg3_write_indirect_reg32;
9662 tp->read32_mbox = tg3_read_indirect_mbox;
9663 tp->write32_mbox = tg3_write_indirect_mbox;
9664 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9665 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9666
9667 iounmap(tp->regs);
22abe310 9668 tp->regs = NULL;
6892914f
MC		 9669
9670 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9671 pci_cmd &= ~PCI_COMMAND_MEMORY;
9672 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9673 }
9674
7d0c41ef
MC		 9675 /* Get eeprom hw config before calling tg3_set_power_state().
9676 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9677 * determined before calling tg3_set_power_state() so that
9678 * we know whether or not to switch out of Vaux power.
9679 * When the flag is set, it means that GPIO1 is used for eeprom
9680 * write protect and also implies that it is a LOM where GPIOs
9681 * are not used to switch power.
9682 */
9683 tg3_get_eeprom_hw_cfg(tp);
9684
314fba34
MC		 9685 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9686 * GPIO1 driven high will bring 5700's external PHY out of reset.
9687 * It is also used as eeprom write protect on LOMs.
9688 */
9689 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9690 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9691 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9692 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9693 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 9694 /* Unused GPIO3 must be driven as output on 5752 because there
9695 * are no pull-up resistors on unused GPIO pins.
9696 */
9697 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9698 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 9699
1da177e4
LT		 9700 /* Force the chip into D0. */
9701 err = tg3_set_power_state(tp, 0);
9702 if (err) {
9703 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9704 pci_name(tp->pdev));
9705 return err;
9706 }
9707
9708 /* 5700 B0 chips do not support checksumming correctly due
9709 * to hardware bugs.
9710 */
9711 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9712 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9713
9714 /* Pseudo-header checksum is done by hardware logic and not
9715 * the offload processers, so make the chip do the pseudo-
9716 * header checksums on receive. For transmit it is more
9717 * convenient to do the pseudo-header checksum in software
9718 * as Linux does that on transmit for us in all cases.
9719 */
9720 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9721 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9722
9723 /* Derive initial jumbo mode from MTU assigned in
9724 * ether_setup() via the alloc_etherdev() call
9725 */
0f893dc6 9726 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 9727 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 9728 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 9729
9730 /* Determine WakeOnLan speed to use. */
9731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9732 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9733 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9734 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9735 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9736 } else {
9737 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9738 }
9739
9740 /* A few boards don't want Ethernet@WireSpeed phy feature */
9741 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9742 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9743 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b
MC		 9744 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9745 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 9746 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9747
9748 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9749 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9750 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9751 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9752 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9753
bb7064dc 9754 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 9755 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9756
1da177e4 9757 tp->coalesce_mode = 0;
1da177e4
LT		 9758 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9759 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9760 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9761
9762 /* Initialize MAC MI mode, polling disabled. */
9763 tw32_f(MAC_MI_MODE, tp->mi_mode);
9764 udelay(80);
9765
9766 /* Initialize data/descriptor byte/word swapping. */
9767 val = tr32(GRC_MODE);
9768 val &= GRC_MODE_HOST_STACKUP;
9769 tw32(GRC_MODE, val | tp->grc_mode);
9770
9771 tg3_switch_clocks(tp);
9772
9773 /* Clear this out for sanity. */
9774 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9775
9776 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9777 &pci_state_reg);
9778 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9779 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9780 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9781
9782 if (chiprevid == CHIPREV_ID_5701_A0 ||
9783 chiprevid == CHIPREV_ID_5701_B0 ||
9784 chiprevid == CHIPREV_ID_5701_B2 ||
9785 chiprevid == CHIPREV_ID_5701_B5) {
9786 void __iomem *sram_base;
9787
9788 /* Write some dummy words into the SRAM status block
9789 * area, see if it reads back correctly. If the return
9790 * value is bad, force enable the PCIX workaround.
9791 */
9792 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9793
9794 writel(0x00000000, sram_base);
9795 writel(0x00000000, sram_base + 4);
9796 writel(0xffffffff, sram_base + 4);
9797 if (readl(sram_base) != 0x00000000)
9798 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9799 }
9800 }
9801
9802 udelay(50);
9803 tg3_nvram_init(tp);
9804
9805 grc_misc_cfg = tr32(GRC_MISC_CFG);
9806 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9807
9808 /* Broadcom's driver says that CIOBE multisplit has a bug */
9809#if 0
9810 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9811 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9812 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9813 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9814 }
9815#endif
9816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9817 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9818 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9819 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9820
fac9b83e
DM		 9821 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9822 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9823 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9824 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9825 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9826 HOSTCC_MODE_CLRTICK_TXBD);
9827
9828 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9829 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9830 tp->misc_host_ctrl);
9831 }
9832
1da177e4
LT		 9833 /* these are limited to 10/100 only */
9834 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9835 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9836 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9837 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9838 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9839 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9840 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9841 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9842 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9843 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9844 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9845
9846 err = tg3_phy_probe(tp);
9847 if (err) {
9848 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9849 pci_name(tp->pdev), err);
9850 /* ... but do not return immediately ... */
9851 }
9852
9853 tg3_read_partno(tp);
9854
9855 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9856 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9857 } else {
9858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9859 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9860 else
9861 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9862 }
9863
9864 /* 5700 {AX,BX} chips have a broken status block link
9865 * change bit implementation, so we must use the
9866 * status register in those cases.
9867 */
9868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9869 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9870 else
9871 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9872
9873 /* The led_ctrl is set during tg3_phy_probe, here we might
9874 * have to force the link status polling mechanism based
9875 * upon subsystem IDs.
9876 */
9877 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9878 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9879 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9880 TG3_FLAG_USE_LINKCHG_REG);
9881 }
9882
9883 /* For all SERDES we poll the MAC status register. */
9884 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9885 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9886 else
9887 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9888
1da177e4
LT		 9889 /* It seems all chips can get confused if TX buffers
9890 * straddle the 4GB address boundary in some cases.
9891 */
9892 tp->dev->hard_start_xmit = tg3_start_xmit;
9893
9894 tp->rx_offset = 2;
9895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9896 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9897 tp->rx_offset = 0;
9898
9899 /* By default, disable wake-on-lan. User can change this
9900 * using ETHTOOL_SWOL.
9901 */
9902 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9903
9904 return err;
9905}
9906
9907#ifdef CONFIG_SPARC64
9908static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9909{
9910 struct net_device *dev = tp->dev;
9911 struct pci_dev *pdev = tp->pdev;
9912 struct pcidev_cookie *pcp = pdev->sysdata;
9913
9914 if (pcp != NULL) {
9915 int node = pcp->prom_node;
9916
9917 if (prom_getproplen(node, "local-mac-address") == 6) {
9918 prom_getproperty(node, "local-mac-address",
9919 dev->dev_addr, 6);
2ff43697 9920 memcpy(dev->perm_addr, dev->dev_addr, 6);
1da177e4
LT		 9921 return 0;
9922 }
9923 }
9924 return -ENODEV;
9925}
9926
9927static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9928{
9929 struct net_device *dev = tp->dev;
9930
9931 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 9932 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 9933 return 0;
9934}
9935#endif
9936
9937static int __devinit tg3_get_device_address(struct tg3 *tp)
9938{
9939 struct net_device *dev = tp->dev;
9940 u32 hi, lo, mac_offset;
9941
9942#ifdef CONFIG_SPARC64
9943 if (!tg3_get_macaddr_sparc(tp))
9944 return 0;
9945#endif
9946
9947 mac_offset = 0x7c;
4cf78e4f
MC		 9948 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9949 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
a4e2b347 9950 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9951 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9952 mac_offset = 0xcc;
9953 if (tg3_nvram_lock(tp))
9954 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9955 else
9956 tg3_nvram_unlock(tp);
9957 }
9958
9959 /* First try to get it from MAC address mailbox. */
9960 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9961 if ((hi >> 16) == 0x484b) {
9962 dev->dev_addr[0] = (hi >> 8) & 0xff;
9963 dev->dev_addr[1] = (hi >> 0) & 0xff;
9964
9965 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9966 dev->dev_addr[2] = (lo >> 24) & 0xff;
9967 dev->dev_addr[3] = (lo >> 16) & 0xff;
9968 dev->dev_addr[4] = (lo >> 8) & 0xff;
9969 dev->dev_addr[5] = (lo >> 0) & 0xff;
9970 }
9971 /* Next, try NVRAM. */
9972 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9973 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9974 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9975 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9976 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9977 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9978 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9979 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9980 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9981 }
9982 /* Finally just fetch it out of the MAC control regs. */
9983 else {
9984 hi = tr32(MAC_ADDR_0_HIGH);
9985 lo = tr32(MAC_ADDR_0_LOW);
9986
9987 dev->dev_addr[5] = lo & 0xff;
9988 dev->dev_addr[4] = (lo >> 8) & 0xff;
9989 dev->dev_addr[3] = (lo >> 16) & 0xff;
9990 dev->dev_addr[2] = (lo >> 24) & 0xff;
9991 dev->dev_addr[1] = hi & 0xff;
9992 dev->dev_addr[0] = (hi >> 8) & 0xff;
9993 }
9994
9995 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9996#ifdef CONFIG_SPARC64
9997 if (!tg3_get_default_macaddr_sparc(tp))
9998 return 0;
9999#endif
10000 return -EINVAL;
10001 }
2ff43697 10002 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 10003 return 0;
10004}
10005
59e6b434
DM		 10006#define BOUNDARY_SINGLE_CACHELINE 1
10007#define BOUNDARY_MULTI_CACHELINE 2
10008
10009static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10010{
10011 int cacheline_size;
10012 u8 byte;
10013 int goal;
10014
10015 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10016 if (byte == 0)
10017 cacheline_size = 1024;
10018 else
10019 cacheline_size = (int) byte * 4;
10020
10021 /* On 5703 and later chips, the boundary bits have no
10022 * effect.
10023 */
10024 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10025 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10026 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10027 goto out;
10028
10029#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10030 goal = BOUNDARY_MULTI_CACHELINE;
10031#else
10032#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10033 goal = BOUNDARY_SINGLE_CACHELINE;
10034#else
10035 goal = 0;
10036#endif
10037#endif
10038
10039 if (!goal)
10040 goto out;
10041
10042 /* PCI controllers on most RISC systems tend to disconnect
10043 * when a device tries to burst across a cache-line boundary.
10044 * Therefore, letting tg3 do so just wastes PCI bandwidth.
10045 *
10046 * Unfortunately, for PCI-E there are only limited
10047 * write-side controls for this, and thus for reads
10048 * we will still get the disconnects. We'll also waste
10049 * these PCI cycles for both read and write for chips
10050 * other than 5700 and 5701 which do not implement the
10051 * boundary bits.
10052 */
10053 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10054 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10055 switch (cacheline_size) {
10056 case 16:
10057 case 32:
10058 case 64:
10059 case 128:
10060 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10061 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10062 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10063 } else {
10064 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10065 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10066 }
10067 break;
10068
10069 case 256:
10070 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10071 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10072 break;
10073
10074 default:
10075 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10076 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10077 break;
10078 };
10079 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10080 switch (cacheline_size) {
10081 case 16:
10082 case 32:
10083 case 64:
10084 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10085 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10086 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10087 break;
10088 }
10089 /* fallthrough */
10090 case 128:
10091 default:
10092 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10093 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10094 break;
10095 };
10096 } else {
10097 switch (cacheline_size) {
10098 case 16:
10099 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10100 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10101 DMA_RWCTRL_WRITE_BNDRY_16);
10102 break;
10103 }
10104 /* fallthrough */
10105 case 32:
10106 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10107 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10108 DMA_RWCTRL_WRITE_BNDRY_32);
10109 break;
10110 }
10111 /* fallthrough */
10112 case 64:
10113 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10114 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10115 DMA_RWCTRL_WRITE_BNDRY_64);
10116 break;
10117 }
10118 /* fallthrough */
10119 case 128:
10120 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10121 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10122 DMA_RWCTRL_WRITE_BNDRY_128);
10123 break;
10124 }
10125 /* fallthrough */
10126 case 256:
10127 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10128 DMA_RWCTRL_WRITE_BNDRY_256);
10129 break;
10130 case 512:
10131 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10132 DMA_RWCTRL_WRITE_BNDRY_512);
10133 break;
10134 case 1024:
10135 default:
10136 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10137 DMA_RWCTRL_WRITE_BNDRY_1024);
10138 break;
10139 };
10140 }
10141
10142out:
10143 return val;
10144}
10145
1da177e4
LT		 10146static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10147{
10148 struct tg3_internal_buffer_desc test_desc;
10149 u32 sram_dma_descs;
10150 int i, ret;
10151
10152 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10153
10154 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10155 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10156 tw32(RDMAC_STATUS, 0);
10157 tw32(WDMAC_STATUS, 0);
10158
10159 tw32(BUFMGR_MODE, 0);
10160 tw32(FTQ_RESET, 0);
10161
10162 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10163 test_desc.addr_lo = buf_dma & 0xffffffff;
10164 test_desc.nic_mbuf = 0x00002100;
10165 test_desc.len = size;
10166
10167 /*
10168 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10169 * the *second* time the tg3 driver was getting loaded after an
10170 * initial scan.
10171 *
10172 * Broadcom tells me:
10173 * ...the DMA engine is connected to the GRC block and a DMA
10174 * reset may affect the GRC block in some unpredictable way...
10175 * The behavior of resets to individual blocks has not been tested.
10176 *
10177 * Broadcom noted the GRC reset will also reset all sub-components.
10178 */
10179 if (to_device) {
10180 test_desc.cqid_sqid = (13 << 8) | 2;
10181
10182 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10183 udelay(40);
10184 } else {
10185 test_desc.cqid_sqid = (16 << 8) | 7;
10186
10187 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10188 udelay(40);
10189 }
10190 test_desc.flags = 0x00000005;
10191
10192 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10193 u32 val;
10194
10195 val = *(((u32 *)&test_desc) + i);
10196 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10197 sram_dma_descs + (i * sizeof(u32)));
10198 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10199 }
10200 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10201
10202 if (to_device) {
10203 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10204 } else {
10205 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10206 }
10207
10208 ret = -ENODEV;
10209 for (i = 0; i < 40; i++) {
10210 u32 val;
10211
10212 if (to_device)
10213 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10214 else
10215 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10216 if ((val & 0xffff) == sram_dma_descs) {
10217 ret = 0;
10218 break;
10219 }
10220
10221 udelay(100);
10222 }
10223
10224 return ret;
10225}
10226
ded7340d 10227#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 10228
10229static int __devinit tg3_test_dma(struct tg3 *tp)
10230{
10231 dma_addr_t buf_dma;
59e6b434 10232 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 10233 int ret;
10234
10235 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10236 if (!buf) {
10237 ret = -ENOMEM;
10238 goto out_nofree;
10239 }
10240
10241 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10242 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10243
59e6b434 10244 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 10245
10246 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10247 /* DMA read watermark not used on PCIE */
10248 tp->dma_rwctrl |= 0x00180000;
10249 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 10250 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 10252 tp->dma_rwctrl |= 0x003f0000;
10253 else
10254 tp->dma_rwctrl |= 0x003f000f;
10255 } else {
10256 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10257 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10258 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10259
10260 if (ccval == 0x6 || ccval == 0x7)
10261 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10262
59e6b434 10263 /* Set bit 23 to enable PCIX hw bug fix */
1da177e4 10264 tp->dma_rwctrl |= 0x009f0000;
4cf78e4f
MC		 10265 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10266 /* 5780 always in PCIX mode */
10267 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 10268 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10269 /* 5714 always in PCIX mode */
10270 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 10271 } else {
10272 tp->dma_rwctrl |= 0x001b000f;
10273 }
10274 }
10275
10276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10277 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10278 tp->dma_rwctrl &= 0xfffffff0;
10279
10280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10281 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10282 /* Remove this if it causes problems for some boards. */
10283 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10284
10285 /* On 5700/5701 chips, we need to set this bit.
10286 * Otherwise the chip will issue cacheline transactions
10287 * to streamable DMA memory with not all the byte
10288 * enables turned on. This is an error on several
10289 * RISC PCI controllers, in particular sparc64.
10290 *
10291 * On 5703/5704 chips, this bit has been reassigned
10292 * a different meaning. In particular, it is used
10293 * on those chips to enable a PCI-X workaround.
10294 */
10295 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10296 }
10297
10298 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10299
10300#if 0
10301 /* Unneeded, already done by tg3_get_invariants. */
10302 tg3_switch_clocks(tp);
10303#endif
10304
10305 ret = 0;
10306 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10307 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10308 goto out;
10309
59e6b434
DM		 10310 /* It is best to perform DMA test with maximum write burst size
10311 * to expose the 5700/5701 write DMA bug.
10312 */
10313 saved_dma_rwctrl = tp->dma_rwctrl;
10314 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10315 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10316
1da177e4
LT		 10317 while (1) {
10318 u32 *p = buf, i;
10319
10320 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10321 p[i] = i;
10322
10323 /* Send the buffer to the chip. */
10324 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10325 if (ret) {
10326 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10327 break;
10328 }
10329
10330#if 0
10331 /* validate data reached card RAM correctly. */
10332 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10333 u32 val;
10334 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10335 if (le32_to_cpu(val) != p[i]) {
10336 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10337 /* ret = -ENODEV here? */
10338 }
10339 p[i] = 0;
10340 }
10341#endif
10342 /* Now read it back. */
10343 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10344 if (ret) {
10345 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10346
10347 break;
10348 }
10349
10350 /* Verify it. */
10351 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10352 if (p[i] == i)
10353 continue;
10354
59e6b434
DM		 10355 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10356 DMA_RWCTRL_WRITE_BNDRY_16) {
10357 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 10358 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10359 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10360 break;
10361 } else {
10362 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10363 ret = -ENODEV;
10364 goto out;
10365 }
10366 }
10367
10368 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10369 /* Success. */
10370 ret = 0;
10371 break;
10372 }
10373 }
59e6b434
DM		 10374 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10375 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 10376 static struct pci_device_id dma_wait_state_chipsets[] = {
10377 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10378 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10379 { },
10380 };
10381
59e6b434 10382 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 10383 * now look for chipsets that are known to expose the
10384 * DMA bug without failing the test.
59e6b434 10385 */
6d1cfbab
MC		 10386 if (pci_dev_present(dma_wait_state_chipsets)) {
10387 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10388 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10389 }
10390 else
10391 /* Safe to use the calculated DMA boundary. */
10392 tp->dma_rwctrl = saved_dma_rwctrl;
10393
59e6b434
DM		 10394 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10395 }
1da177e4
LT		 10396
10397out:
10398 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10399out_nofree:
10400 return ret;
10401}
10402
10403static void __devinit tg3_init_link_config(struct tg3 *tp)
10404{
10405 tp->link_config.advertising =
10406 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10407 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10408 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10409 ADVERTISED_Autoneg | ADVERTISED_MII);
10410 tp->link_config.speed = SPEED_INVALID;
10411 tp->link_config.duplex = DUPLEX_INVALID;
10412 tp->link_config.autoneg = AUTONEG_ENABLE;
10413 netif_carrier_off(tp->dev);
10414 tp->link_config.active_speed = SPEED_INVALID;
10415 tp->link_config.active_duplex = DUPLEX_INVALID;
10416 tp->link_config.phy_is_low_power = 0;
10417 tp->link_config.orig_speed = SPEED_INVALID;
10418 tp->link_config.orig_duplex = DUPLEX_INVALID;
10419 tp->link_config.orig_autoneg = AUTONEG_INVALID;
10420}
10421
10422static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10423{
fdfec172
MC		 10424 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10425 tp->bufmgr_config.mbuf_read_dma_low_water =
10426 DEFAULT_MB_RDMA_LOW_WATER_5705;
10427 tp->bufmgr_config.mbuf_mac_rx_low_water =
10428 DEFAULT_MB_MACRX_LOW_WATER_5705;
10429 tp->bufmgr_config.mbuf_high_water =
10430 DEFAULT_MB_HIGH_WATER_5705;
10431
10432 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10433 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10434 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10435 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10436 tp->bufmgr_config.mbuf_high_water_jumbo =
10437 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10438 } else {
10439 tp->bufmgr_config.mbuf_read_dma_low_water =
10440 DEFAULT_MB_RDMA_LOW_WATER;
10441 tp->bufmgr_config.mbuf_mac_rx_low_water =
10442 DEFAULT_MB_MACRX_LOW_WATER;
10443 tp->bufmgr_config.mbuf_high_water =
10444 DEFAULT_MB_HIGH_WATER;
10445
10446 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10447 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10448 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10449 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10450 tp->bufmgr_config.mbuf_high_water_jumbo =
10451 DEFAULT_MB_HIGH_WATER_JUMBO;
10452 }
1da177e4
LT		 10453
10454 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10455 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10456}
10457
10458static char * __devinit tg3_phy_string(struct tg3 *tp)
10459{
10460 switch (tp->phy_id & PHY_ID_MASK) {
10461 case PHY_ID_BCM5400: return "5400";
10462 case PHY_ID_BCM5401: return "5401";
10463 case PHY_ID_BCM5411: return "5411";
10464 case PHY_ID_BCM5701: return "5701";
10465 case PHY_ID_BCM5703: return "5703";
10466 case PHY_ID_BCM5704: return "5704";
10467 case PHY_ID_BCM5705: return "5705";
10468 case PHY_ID_BCM5750: return "5750";
85e94ced 10469 case PHY_ID_BCM5752: return "5752";
a4e2b347 10470 case PHY_ID_BCM5714: return "5714";
4cf78e4f 10471 case PHY_ID_BCM5780: return "5780";
1da177e4
LT		 10472 case PHY_ID_BCM8002: return "8002/serdes";
10473 case 0: return "serdes";
10474 default: return "unknown";
10475 };
10476}
10477
f9804ddb
MC		 10478static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10479{
10480 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10481 strcpy(str, "PCI Express");
10482 return str;
10483 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10484 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10485
10486 strcpy(str, "PCIX:");
10487
10488 if ((clock_ctrl == 7) ||
10489 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10490 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10491 strcat(str, "133MHz");
10492 else if (clock_ctrl == 0)
10493 strcat(str, "33MHz");
10494 else if (clock_ctrl == 2)
10495 strcat(str, "50MHz");
10496 else if (clock_ctrl == 4)
10497 strcat(str, "66MHz");
10498 else if (clock_ctrl == 6)
10499 strcat(str, "100MHz");
10500 else if (clock_ctrl == 7)
10501 strcat(str, "133MHz");
10502 } else {
10503 strcpy(str, "PCI:");
10504 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10505 strcat(str, "66MHz");
10506 else
10507 strcat(str, "33MHz");
10508 }
10509 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10510 strcat(str, ":32-bit");
10511 else
10512 strcat(str, ":64-bit");
10513 return str;
10514}
10515
8c2dc7e1 10516static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 10517{
10518 struct pci_dev *peer;
10519 unsigned int func, devnr = tp->pdev->devfn & ~7;
10520
10521 for (func = 0; func < 8; func++) {
10522 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10523 if (peer && peer != tp->pdev)
10524 break;
10525 pci_dev_put(peer);
10526 }
16fe9d74
MC		 10527 /* 5704 can be configured in single-port mode, set peer to
10528 * tp->pdev in that case.
10529 */
10530 if (!peer) {
10531 peer = tp->pdev;
10532 return peer;
10533 }
1da177e4
LT		 10534
10535 /*
10536 * We don't need to keep the refcount elevated; there's no way
10537 * to remove one half of this device without removing the other
10538 */
10539 pci_dev_put(peer);
10540
10541 return peer;
10542}
10543
15f9850d
DM		 10544static void __devinit tg3_init_coal(struct tg3 *tp)
10545{
10546 struct ethtool_coalesce *ec = &tp->coal;
10547
10548 memset(ec, 0, sizeof(*ec));
10549 ec->cmd = ETHTOOL_GCOALESCE;
10550 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10551 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10552 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10553 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10554 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10555 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10556 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10557 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10558 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10559
10560 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10561 HOSTCC_MODE_CLRTICK_TXBD)) {
10562 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10563 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10564 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10565 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10566 }
d244c892
MC		 10567
10568 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10569 ec->rx_coalesce_usecs_irq = 0;
10570 ec->tx_coalesce_usecs_irq = 0;
10571 ec->stats_block_coalesce_usecs = 0;
10572 }
15f9850d
DM		 10573}
10574
1da177e4
LT		 10575static int __devinit tg3_init_one(struct pci_dev *pdev,
10576 const struct pci_device_id *ent)
10577{
10578 static int tg3_version_printed = 0;
10579 unsigned long tg3reg_base, tg3reg_len;
10580 struct net_device *dev;
10581 struct tg3 *tp;
10582 int i, err, pci_using_dac, pm_cap;
f9804ddb 10583 char str[40];
1da177e4
LT		 10584
10585 if (tg3_version_printed++ == 0)
10586 printk(KERN_INFO "%s", version);
10587
10588 err = pci_enable_device(pdev);
10589 if (err) {
10590 printk(KERN_ERR PFX "Cannot enable PCI device, "
10591 "aborting.\n");
10592 return err;
10593 }
10594
10595 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10596 printk(KERN_ERR PFX "Cannot find proper PCI device "
10597 "base address, aborting.\n");
10598 err = -ENODEV;
10599 goto err_out_disable_pdev;
10600 }
10601
10602 err = pci_request_regions(pdev, DRV_MODULE_NAME);
10603 if (err) {
10604 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10605 "aborting.\n");
10606 goto err_out_disable_pdev;
10607 }
10608
10609 pci_set_master(pdev);
10610
10611 /* Find power-management capability. */
10612 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10613 if (pm_cap == 0) {
10614 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10615 "aborting.\n");
10616 err = -EIO;
10617 goto err_out_free_res;
10618 }
10619
10620 /* Configure DMA attributes. */
f9a5f7d3 10621 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1da177e4
LT		 10622 if (!err) {
10623 pci_using_dac = 1;
f9a5f7d3 10624 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1da177e4
LT		 10625 if (err < 0) {
10626 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10627 "for consistent allocations\n");
10628 goto err_out_free_res;
10629 }
10630 } else {
f9a5f7d3 10631 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 10632 if (err) {
10633 printk(KERN_ERR PFX "No usable DMA configuration, "
10634 "aborting.\n");
10635 goto err_out_free_res;
10636 }
10637 pci_using_dac = 0;
10638 }
10639
10640 tg3reg_base = pci_resource_start(pdev, 0);
10641 tg3reg_len = pci_resource_len(pdev, 0);
10642
10643 dev = alloc_etherdev(sizeof(*tp));
10644 if (!dev) {
10645 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10646 err = -ENOMEM;
10647 goto err_out_free_res;
10648 }
10649
10650 SET_MODULE_OWNER(dev);
10651 SET_NETDEV_DEV(dev, &pdev->dev);
10652
10653 if (pci_using_dac)
10654 dev->features |= NETIF_F_HIGHDMA;
10655 dev->features |= NETIF_F_LLTX;
10656#if TG3_VLAN_TAG_USED
10657 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10658 dev->vlan_rx_register = tg3_vlan_rx_register;
10659 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10660#endif
10661
10662 tp = netdev_priv(dev);
10663 tp->pdev = pdev;
10664 tp->dev = dev;
10665 tp->pm_cap = pm_cap;
10666 tp->mac_mode = TG3_DEF_MAC_MODE;
10667 tp->rx_mode = TG3_DEF_RX_MODE;
10668 tp->tx_mode = TG3_DEF_TX_MODE;
10669 tp->mi_mode = MAC_MI_MODE_BASE;
10670 if (tg3_debug > 0)
10671 tp->msg_enable = tg3_debug;
10672 else
10673 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10674
10675 /* The word/byte swap controls here control register access byte
10676 * swapping. DMA data byte swapping is controlled in the GRC_MODE
10677 * setting below.
10678 */
10679 tp->misc_host_ctrl =
10680 MISC_HOST_CTRL_MASK_PCI_INT |
10681 MISC_HOST_CTRL_WORD_SWAP |
10682 MISC_HOST_CTRL_INDIR_ACCESS |
10683 MISC_HOST_CTRL_PCISTATE_RW;
10684
10685 /* The NONFRM (non-frame) byte/word swap controls take effect
10686 * on descriptor entries, anything which isn't packet data.
10687 *
10688 * The StrongARM chips on the board (one for tx, one for rx)
10689 * are running in big-endian mode.
10690 */
10691 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10692 GRC_MODE_WSWAP_NONFRM_DATA);
10693#ifdef __BIG_ENDIAN
10694 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10695#endif
10696 spin_lock_init(&tp->lock);
10697 spin_lock_init(&tp->tx_lock);
10698 spin_lock_init(&tp->indirect_lock);
10699 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10700
10701 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10702 if (tp->regs == 0UL) {
10703 printk(KERN_ERR PFX "Cannot map device registers, "
10704 "aborting.\n");
10705 err = -ENOMEM;
10706 goto err_out_free_dev;
10707 }
10708
10709 tg3_init_link_config(tp);
10710
1da177e4
LT		 10711 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10712 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10713 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10714
10715 dev->open = tg3_open;
10716 dev->stop = tg3_close;
10717 dev->get_stats = tg3_get_stats;
10718 dev->set_multicast_list = tg3_set_rx_mode;
10719 dev->set_mac_address = tg3_set_mac_addr;
10720 dev->do_ioctl = tg3_ioctl;
10721 dev->tx_timeout = tg3_tx_timeout;
10722 dev->poll = tg3_poll;
10723 dev->ethtool_ops = &tg3_ethtool_ops;
10724 dev->weight = 64;
10725 dev->watchdog_timeo = TG3_TX_TIMEOUT;
10726 dev->change_mtu = tg3_change_mtu;
10727 dev->irq = pdev->irq;
10728#ifdef CONFIG_NET_POLL_CONTROLLER
10729 dev->poll_controller = tg3_poll_controller;
10730#endif
10731
10732 err = tg3_get_invariants(tp);
10733 if (err) {
10734 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10735 "aborting.\n");
10736 goto err_out_iounmap;
10737 }
10738
fdfec172 10739 tg3_init_bufmgr_config(tp);
1da177e4
LT		 10740
10741#if TG3_TSO_SUPPORT != 0
10742 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10743 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10744 }
10745 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10746 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10747 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10748 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10749 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10750 } else {
10751 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10752 }
10753
10754 /* TSO is off by default, user can enable using ethtool. */
10755#if 0
10756 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10757 dev->features |= NETIF_F_TSO;
10758#endif
10759
10760#endif
10761
10762 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10763 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10764 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10765 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10766 tp->rx_pending = 63;
10767 }
10768
8c2dc7e1
MC		 10769 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10770 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10771 tp->pdev_peer = tg3_find_peer(tp);
1da177e4
LT		 10772
10773 err = tg3_get_device_address(tp);
10774 if (err) {
10775 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10776 "aborting.\n");
10777 goto err_out_iounmap;
10778 }
10779
10780 /*
10781 * Reset chip in case UNDI or EFI driver did not shutdown
10782 * DMA self test will enable WDMAC and we'll see (spurious)
10783 * pending DMA on the PCI bus at that point.
10784 */
10785 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10786 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10787 pci_save_state(tp->pdev);
10788 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 10789 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 10790 }
10791
10792 err = tg3_test_dma(tp);
10793 if (err) {
10794 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10795 goto err_out_iounmap;
10796 }
10797
10798 /* Tigon3 can do ipv4 only... and some chips have buggy
10799 * checksumming.
10800 */
10801 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10802 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10803 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10804 } else
10805 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10806
10807 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10808 dev->features &= ~NETIF_F_HIGHDMA;
10809
10810 /* flow control autonegotiation is default behavior */
10811 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10812
15f9850d
DM		 10813 tg3_init_coal(tp);
10814
7d3f4c97
DM		 10815 /* Now that we have fully setup the chip, save away a snapshot
10816 * of the PCI config space. We need to restore this after
10817 * GRC_MISC_CFG core clock resets and some resume events.
10818 */
10819 pci_save_state(tp->pdev);
10820
1da177e4
LT		 10821 err = register_netdev(dev);
10822 if (err) {
10823 printk(KERN_ERR PFX "Cannot register net device, "
10824 "aborting.\n");
10825 goto err_out_iounmap;
10826 }
10827
10828 pci_set_drvdata(pdev, dev);
10829
f9804ddb 10830 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
1da177e4
LT		 10831 dev->name,
10832 tp->board_part_number,
10833 tp->pci_chip_rev_id,
10834 tg3_phy_string(tp),
f9804ddb 10835 tg3_bus_string(tp, str),
1da177e4
LT		 10836 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10837
10838 for (i = 0; i < 6; i++)
10839 printk("%2.2x%c", dev->dev_addr[i],
10840 i == 5 ? '\n' : ':');
10841
10842 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10843 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10844 "TSOcap[%d] \n",
10845 dev->name,
10846 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10847 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10848 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10849 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10850 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10851 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10852 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
59e6b434
DM		 10853 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10854 dev->name, tp->dma_rwctrl);
1da177e4
LT		 10855
10856 return 0;
10857
10858err_out_iounmap:
6892914f
MC		 10859 if (tp->regs) {
10860 iounmap(tp->regs);
22abe310 10861 tp->regs = NULL;
6892914f 10862 }
1da177e4
LT		 10863
10864err_out_free_dev:
10865 free_netdev(dev);
10866
10867err_out_free_res:
10868 pci_release_regions(pdev);
10869
10870err_out_disable_pdev:
10871 pci_disable_device(pdev);
10872 pci_set_drvdata(pdev, NULL);
10873 return err;
10874}
10875
10876static void __devexit tg3_remove_one(struct pci_dev *pdev)
10877{
10878 struct net_device *dev = pci_get_drvdata(pdev);
10879
10880 if (dev) {
10881 struct tg3 *tp = netdev_priv(dev);
10882
10883 unregister_netdev(dev);
6892914f
MC		 10884 if (tp->regs) {
10885 iounmap(tp->regs);
22abe310 10886 tp->regs = NULL;
6892914f 10887 }
1da177e4
LT		 10888 free_netdev(dev);
10889 pci_release_regions(pdev);
10890 pci_disable_device(pdev);
10891 pci_set_drvdata(pdev, NULL);
10892 }
10893}
10894
10895static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10896{
10897 struct net_device *dev = pci_get_drvdata(pdev);
10898 struct tg3 *tp = netdev_priv(dev);
10899 int err;
10900
10901 if (!netif_running(dev))
10902 return 0;
10903
10904 tg3_netif_stop(tp);
10905
10906 del_timer_sync(&tp->timer);
10907
f47c11ee 10908 tg3_full_lock(tp, 1);
1da177e4 10909 tg3_disable_ints(tp);
f47c11ee 10910 tg3_full_unlock(tp);
1da177e4
LT		 10911
10912 netif_device_detach(dev);
10913
f47c11ee 10914 tg3_full_lock(tp, 0);
944d980e 10915 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 10916 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 10917 tg3_full_unlock(tp);
1da177e4
LT		 10918
10919 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10920 if (err) {
f47c11ee 10921 tg3_full_lock(tp, 0);
1da177e4 10922
6a9eba15 10923 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 10924 tg3_init_hw(tp);
10925
10926 tp->timer.expires = jiffies + tp->timer_offset;
10927 add_timer(&tp->timer);
10928
10929 netif_device_attach(dev);
10930 tg3_netif_start(tp);
10931
f47c11ee 10932 tg3_full_unlock(tp);
1da177e4
LT		 10933 }
10934
10935 return err;
10936}
10937
10938static int tg3_resume(struct pci_dev *pdev)
10939{
10940 struct net_device *dev = pci_get_drvdata(pdev);
10941 struct tg3 *tp = netdev_priv(dev);
10942 int err;
10943
10944 if (!netif_running(dev))
10945 return 0;
10946
10947 pci_restore_state(tp->pdev);
10948
10949 err = tg3_set_power_state(tp, 0);
10950 if (err)
10951 return err;
10952
10953 netif_device_attach(dev);
10954
f47c11ee 10955 tg3_full_lock(tp, 0);
1da177e4 10956
6a9eba15 10957 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 10958 tg3_init_hw(tp);
10959
10960 tp->timer.expires = jiffies + tp->timer_offset;
10961 add_timer(&tp->timer);
10962
1da177e4
LT		 10963 tg3_netif_start(tp);
10964
f47c11ee 10965 tg3_full_unlock(tp);
1da177e4
LT		 10966
10967 return 0;
10968}
10969
10970static struct pci_driver tg3_driver = {
10971 .name = DRV_MODULE_NAME,
10972 .id_table = tg3_pci_tbl,
10973 .probe = tg3_init_one,
10974 .remove = __devexit_p(tg3_remove_one),
10975 .suspend = tg3_suspend,
10976 .resume = tg3_resume
10977};
10978
10979static int __init tg3_init(void)
10980{
10981 return pci_module_init(&tg3_driver);
10982}
10983
10984static void __exit tg3_cleanup(void)
10985{
10986 pci_unregister_driver(&tg3_driver);
10987}
10988
10989module_init(tg3_init);
10990module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree