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[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
c9bdd4b5 43#include <net/ip.h>
1da177e4
LT		 44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
49b6e95f 50#ifdef CONFIG_SPARC
1da177e4 51#include <asm/idprom.h>
49b6e95f 52#include <asm/prom.h>
1da177e4
LT		 53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
20bd7dd4
MC		 67#define DRV_MODULE_VERSION "3.75"
68#define DRV_MODULE_RELDATE "March 23, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
13185217
HK		 201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
1da177e4
LT		 209};
210
211MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
50da859d 213static const struct {
1da177e4
LT		 214 const char string[ETH_GSTRING_LEN];
215} ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292};
293
50da859d 294static const struct {
4cafd3f5
MC		 295 const char string[ETH_GSTRING_LEN];
296} ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303};
304
b401e9e2
MC		 305static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306{
307 writel(val, tp->regs + off);
308}
309
310static u32 tg3_read32(struct tg3 *tp, u32 off)
311{
6aa20a22 312 return (readl(tp->regs + off));
b401e9e2
MC		 313}
314
1da177e4
LT		 315static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316{
6892914f
MC		 317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 323}
324
325static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326{
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
1da177e4
LT		 329}
330
6892914f 331static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 332{
6892914f
MC		 333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341}
342
343static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344{
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
1da177e4 356 }
6892914f
MC		 357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371}
372
373static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374{
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383}
384
b401e9e2
MC		 385/* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 391{
b401e9e2
MC		 392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
1da177e4
LT		 408}
409
09ee929c
MC		 410static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411{
412 tp->write32_mbox(tp, off, val);
6892914f
MC		 413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
09ee929c
MC		 416}
417
20094930 418static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 419{
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426}
427
b5d3772c
MC		 428static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429{
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431}
432
433static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434{
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436}
437
20094930 438#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 439#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 440#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 442#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 443
444#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 445#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 447#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 448
449static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450{
6892914f
MC		 451 unsigned long flags;
452
b5d3772c
MC		 453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
6892914f 457 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 461
bbadf503
MC		 462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 467
bbadf503
MC		 468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 472}
473
1da177e4
LT		 474static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475{
6892914f
MC		 476 unsigned long flags;
477
b5d3772c
MC		 478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
6892914f 484 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 488
bbadf503
MC		 489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 499}
500
501static void tg3_disable_ints(struct tg3 *tp)
502{
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 506}
507
508static inline void tg3_cond_int(struct tg3 *tp)
509{
38f3843e
MC		 510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 516}
517
518static void tg3_enable_ints(struct tg3 *tp)
519{
bbe832c0
MC		 520 tp->irq_sync = 0;
521 wmb();
522
1da177e4
LT		 523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
fcfa0a32
MC		 527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
1da177e4
LT		 530 tg3_cond_int(tp);
531}
532
04237ddd
MC		 533static inline unsigned int tg3_has_work(struct tg3 *tp)
534{
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551}
552
1da177e4 553/* tg3_restart_ints
04237ddd
MC		 554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
6aa20a22 556 * which reenables interrupts
1da177e4
LT		 557 */
558static void tg3_restart_ints(struct tg3 *tp)
559{
fac9b83e
DM		 560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
1da177e4
LT		 562 mmiowb();
563
fac9b83e
DM		 564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
04237ddd
MC		 570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 572}
573
574static inline void tg3_netif_stop(struct tg3 *tp)
575{
bbe832c0 576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579}
580
581static inline void tg3_netif_start(struct tg3 *tp)
582{
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
f47c11ee
DM		 589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
1da177e4
LT		 591}
592
593static void tg3_switch_clocks(struct tg3 *tp)
594{
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
a4e2b347 598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 599 return;
600
1da177e4
LT		 601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
1da177e4 620 }
b401e9e2 621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 622}
623
624#define PHY_BUSY_LOOPS 5000
625
626static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627{
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 645
1da177e4
LT		 646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673}
674
675static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676{
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
b5d3772c
MC		 681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
1da177e4
LT		 685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 697
1da177e4
LT		 698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722}
723
724static void tg3_phy_set_wirespeed(struct tg3 *tp)
725{
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735}
736
737static int tg3_bmcr_reset(struct tg3 *tp)
738{
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766}
767
768static int tg3_wait_macro_done(struct tg3 *tp)
769{
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784}
785
786static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787{
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850}
851
852static int tg3_phy_reset_chanpat(struct tg3 *tp)
853{
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870}
871
872static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873{
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946}
947
c8e1e82b
MC		 948static void tg3_link_report(struct tg3 *);
949
1da177e4
LT		 950/* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953static int tg3_phy_reset(struct tg3 *tp)
954{
955 u32 phy_status;
956 int err;
957
60189ddf
MC		 958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
1da177e4
LT		 965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
c8e1e82b
MC		 970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
1da177e4
LT		 975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
c424cb24
MC		 1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1da177e4
LT		 1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
0f893dc6 1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
715116a1
MC		 1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1da177e4
LT		 1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067}
1068
1069static void tg3_frob_aux_power(struct tg3 *tp)
1070{
1071 struct tg3 *tp_peer = tp;
1072
9d26e213 1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1074 return;
1075
8c2dc7e1
MC		 1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1081 /* remove_one() may have been run on the peer. */
8c2dc7e1 1082 if (!dev_peer)
bc1c7567
MC		 1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1086 }
1087
1da177e4 1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1da177e4
LT		 1101 } else {
1102 u32 no_gpio2;
dc56b7d4 1103 u32 grc_local_ctrl = 0;
1da177e4
LT		 1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
dc56b7d4
MC		 1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
dc56b7d4
MC		 1115 }
1116
1da177e4
LT		 1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
dc56b7d4 1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
b401e9e2
MC		 1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1da177e4
LT		 1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
b401e9e2
MC		 1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1da177e4
LT		 1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1da177e4
LT		 1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
b401e9e2
MC		 1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1154
b401e9e2
MC		 1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1157
b401e9e2
MC		 1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1161 }
1162 }
1163}
1164
1165static int tg3_setup_phy(struct tg3 *, int);
1166
1167#define RESET_KIND_SHUTDOWN 0
1168#define RESET_KIND_INIT 1
1169#define RESET_KIND_SUSPEND 2
1170
1171static void tg3_write_sig_post_reset(struct tg3 *, int);
1172static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1173static int tg3_nvram_lock(struct tg3 *);
1174static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1175
15c3b696
MC		 1176static void tg3_power_down_phy(struct tg3 *tp)
1177{
5129724a
MC		 1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183 sg_dig_ctrl |=
1184 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187 }
3f7045c1 1188 return;
5129724a 1189 }
3f7045c1 1190
60189ddf
MC		 1191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192 u32 val;
1193
1194 tg3_bmcr_reset(tp);
1195 val = tr32(GRC_MISC_CFG);
1196 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197 udelay(40);
1198 return;
1199 } else {
715116a1
MC		 1200 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203 }
3f7045c1 1204
15c3b696
MC		 1205 /* The PHY should not be powered down on some chips because
1206 * of bugs.
1207 */
1208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212 return;
1213 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214}
1215
bc1c7567 1216static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1217{
1218 u32 misc_host_ctrl;
1219 u16 power_control, power_caps;
1220 int pm = tp->pm_cap;
1221
1222 /* Make sure register accesses (indirect or otherwise)
1223 * will function correctly.
1224 */
1225 pci_write_config_dword(tp->pdev,
1226 TG3PCI_MISC_HOST_CTRL,
1227 tp->misc_host_ctrl);
1228
1229 pci_read_config_word(tp->pdev,
1230 pm + PCI_PM_CTRL,
1231 &power_control);
1232 power_control |= PCI_PM_CTRL_PME_STATUS;
1233 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234 switch (state) {
bc1c7567 1235 case PCI_D0:
1da177e4
LT		 1236 power_control |= 0;
1237 pci_write_config_word(tp->pdev,
1238 pm + PCI_PM_CTRL,
1239 power_control);
8c6bda1a
MC		 1240 udelay(100); /* Delay after power state change */
1241
9d26e213
MC		 1242 /* Switch out of Vaux if it is a NIC */
1243 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1244 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1245
1246 return 0;
1247
bc1c7567 1248 case PCI_D1:
1da177e4
LT		 1249 power_control |= 1;
1250 break;
1251
bc1c7567 1252 case PCI_D2:
1da177e4
LT		 1253 power_control |= 2;
1254 break;
1255
bc1c7567 1256 case PCI_D3hot:
1da177e4
LT		 1257 power_control |= 3;
1258 break;
1259
1260 default:
1261 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262 "requested.\n",
1263 tp->dev->name, state);
1264 return -EINVAL;
1265 };
1266
1267 power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270 tw32(TG3PCI_MISC_HOST_CTRL,
1271 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273 if (tp->link_config.phy_is_low_power == 0) {
1274 tp->link_config.phy_is_low_power = 1;
1275 tp->link_config.orig_speed = tp->link_config.speed;
1276 tp->link_config.orig_duplex = tp->link_config.duplex;
1277 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278 }
1279
747e8f8b 1280 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1281 tp->link_config.speed = SPEED_10;
1282 tp->link_config.duplex = DUPLEX_HALF;
1283 tp->link_config.autoneg = AUTONEG_ENABLE;
1284 tg3_setup_phy(tp, 0);
1285 }
1286
b5d3772c
MC		 1287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288 u32 val;
1289
1290 val = tr32(GRC_VCPU_EXT_CTRL);
1291 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1293 int i;
1294 u32 val;
1295
1296 for (i = 0; i < 200; i++) {
1297 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299 break;
1300 msleep(1);
1301 }
1302 }
a85feb8c
GZ		 1303 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305 WOL_DRV_STATE_SHUTDOWN |
1306 WOL_DRV_WOL |
1307 WOL_SET_MAGIC_PKT);
6921d201 1308
1da177e4
LT		 1309 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1310
1311 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1312 u32 mac_mode;
1313
1314 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1315 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1316 udelay(40);
1317
3f7045c1
MC		 1318 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1319 mac_mode = MAC_MODE_PORT_MODE_GMII;
1320 else
1321 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4
LT		 1322
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1324 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1325 mac_mode |= MAC_MODE_LINK_POLARITY;
1326 } else {
1327 mac_mode = MAC_MODE_PORT_MODE_TBI;
1328 }
1329
cbf46853 1330 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1331 tw32(MAC_LED_CTRL, tp->led_ctrl);
1332
1333 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1334 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1335 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1336
1337 tw32_f(MAC_MODE, mac_mode);
1338 udelay(100);
1339
1340 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1341 udelay(10);
1342 }
1343
1344 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1345 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1347 u32 base_val;
1348
1349 base_val = tp->pci_clock_ctrl;
1350 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1351 CLOCK_CTRL_TXCLK_DISABLE);
1352
b401e9e2
MC		 1353 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1354 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857
MC		 1355 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1357 /* do nothing */
85e94ced 1358 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1359 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1360 u32 newbits1, newbits2;
1361
1362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1364 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1365 CLOCK_CTRL_TXCLK_DISABLE |
1366 CLOCK_CTRL_ALTCLK);
1367 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1368 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1369 newbits1 = CLOCK_CTRL_625_CORE;
1370 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1371 } else {
1372 newbits1 = CLOCK_CTRL_ALTCLK;
1373 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1374 }
1375
b401e9e2
MC		 1376 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1377 40);
1da177e4 1378
b401e9e2
MC		 1379 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1380 40);
1da177e4
LT		 1381
1382 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1383 u32 newbits3;
1384
1385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1386 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1387 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1388 CLOCK_CTRL_TXCLK_DISABLE |
1389 CLOCK_CTRL_44MHZ_CORE);
1390 } else {
1391 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1392 }
1393
b401e9e2
MC		 1394 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1395 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1396 }
1397 }
1398
6921d201 1399 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
3f7045c1
MC		 1400 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1401 tg3_power_down_phy(tp);
6921d201 1402
1da177e4
LT		 1403 tg3_frob_aux_power(tp);
1404
1405 /* Workaround for unstable PLL clock */
1406 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1407 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1408 u32 val = tr32(0x7d00);
1409
1410 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1411 tw32(0x7d00, val);
6921d201 1412 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1413 int err;
1414
1415 err = tg3_nvram_lock(tp);
1da177e4 1416 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1417 if (!err)
1418 tg3_nvram_unlock(tp);
6921d201 1419 }
1da177e4
LT		 1420 }
1421
bbadf503
MC		 1422 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1423
1da177e4
LT		 1424 /* Finally, set the new power state. */
1425 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1426 udelay(100); /* Delay after power state change */
1da177e4 1427
1da177e4
LT		 1428 return 0;
1429}
1430
1431static void tg3_link_report(struct tg3 *tp)
1432{
1433 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1434 if (netif_msg_link(tp))
1435 printk(KERN_INFO PFX "%s: Link is down.\n",
1436 tp->dev->name);
1437 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1438 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1439 tp->dev->name,
1440 (tp->link_config.active_speed == SPEED_1000 ?
1441 1000 :
1442 (tp->link_config.active_speed == SPEED_100 ?
1443 100 : 10)),
1444 (tp->link_config.active_duplex == DUPLEX_FULL ?
1445 "full" : "half"));
1446
1447 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1448 "%s for RX.\n",
1449 tp->dev->name,
1450 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1451 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1452 }
1453}
1454
1455static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1456{
1457 u32 new_tg3_flags = 0;
1458 u32 old_rx_mode = tp->rx_mode;
1459 u32 old_tx_mode = tp->tx_mode;
1460
1461 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1462
1463 /* Convert 1000BaseX flow control bits to 1000BaseT
1464 * bits before resolving flow control.
1465 */
1466 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1467 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1468 ADVERTISE_PAUSE_ASYM);
1469 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1470
1471 if (local_adv & ADVERTISE_1000XPAUSE)
1472 local_adv |= ADVERTISE_PAUSE_CAP;
1473 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1474 local_adv |= ADVERTISE_PAUSE_ASYM;
1475 if (remote_adv & LPA_1000XPAUSE)
1476 remote_adv |= LPA_PAUSE_CAP;
1477 if (remote_adv & LPA_1000XPAUSE_ASYM)
1478 remote_adv |= LPA_PAUSE_ASYM;
1479 }
1480
1da177e4
LT		 1481 if (local_adv & ADVERTISE_PAUSE_CAP) {
1482 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1483 if (remote_adv & LPA_PAUSE_CAP)
1484 new_tg3_flags |=
1485 (TG3_FLAG_RX_PAUSE |
1486 TG3_FLAG_TX_PAUSE);
1487 else if (remote_adv & LPA_PAUSE_ASYM)
1488 new_tg3_flags |=
1489 (TG3_FLAG_RX_PAUSE);
1490 } else {
1491 if (remote_adv & LPA_PAUSE_CAP)
1492 new_tg3_flags |=
1493 (TG3_FLAG_RX_PAUSE |
1494 TG3_FLAG_TX_PAUSE);
1495 }
1496 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1497 if ((remote_adv & LPA_PAUSE_CAP) &&
1498 (remote_adv & LPA_PAUSE_ASYM))
1499 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1500 }
1501
1502 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1503 tp->tg3_flags |= new_tg3_flags;
1504 } else {
1505 new_tg3_flags = tp->tg3_flags;
1506 }
1507
1508 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1509 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1510 else
1511 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1512
1513 if (old_rx_mode != tp->rx_mode) {
1514 tw32_f(MAC_RX_MODE, tp->rx_mode);
1515 }
6aa20a22 1516
1da177e4
LT		 1517 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1518 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1519 else
1520 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1521
1522 if (old_tx_mode != tp->tx_mode) {
1523 tw32_f(MAC_TX_MODE, tp->tx_mode);
1524 }
1525}
1526
1527static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1528{
1529 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1530 case MII_TG3_AUX_STAT_10HALF:
1531 *speed = SPEED_10;
1532 *duplex = DUPLEX_HALF;
1533 break;
1534
1535 case MII_TG3_AUX_STAT_10FULL:
1536 *speed = SPEED_10;
1537 *duplex = DUPLEX_FULL;
1538 break;
1539
1540 case MII_TG3_AUX_STAT_100HALF:
1541 *speed = SPEED_100;
1542 *duplex = DUPLEX_HALF;
1543 break;
1544
1545 case MII_TG3_AUX_STAT_100FULL:
1546 *speed = SPEED_100;
1547 *duplex = DUPLEX_FULL;
1548 break;
1549
1550 case MII_TG3_AUX_STAT_1000HALF:
1551 *speed = SPEED_1000;
1552 *duplex = DUPLEX_HALF;
1553 break;
1554
1555 case MII_TG3_AUX_STAT_1000FULL:
1556 *speed = SPEED_1000;
1557 *duplex = DUPLEX_FULL;
1558 break;
1559
1560 default:
715116a1
MC		 1561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1562 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1563 SPEED_10;
1564 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1565 DUPLEX_HALF;
1566 break;
1567 }
1da177e4
LT		 1568 *speed = SPEED_INVALID;
1569 *duplex = DUPLEX_INVALID;
1570 break;
1571 };
1572}
1573
1574static void tg3_phy_copper_begin(struct tg3 *tp)
1575{
1576 u32 new_adv;
1577 int i;
1578
1579 if (tp->link_config.phy_is_low_power) {
1580 /* Entering low power mode. Disable gigabit and
1581 * 100baseT advertisements.
1582 */
1583 tg3_writephy(tp, MII_TG3_CTRL, 0);
1584
1585 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1586 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1587 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1588 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1589
1590 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1591 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1592 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1593 tp->link_config.advertising &=
1594 ~(ADVERTISED_1000baseT_Half |
1595 ADVERTISED_1000baseT_Full);
1596
1597 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1598 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1599 new_adv |= ADVERTISE_10HALF;
1600 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1601 new_adv |= ADVERTISE_10FULL;
1602 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1603 new_adv |= ADVERTISE_100HALF;
1604 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1605 new_adv |= ADVERTISE_100FULL;
1606 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1607
1608 if (tp->link_config.advertising &
1609 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1610 new_adv = 0;
1611 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1612 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1613 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1614 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1615 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1616 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1617 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1618 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1619 MII_TG3_CTRL_ENABLE_AS_MASTER);
1620 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1621 } else {
1622 tg3_writephy(tp, MII_TG3_CTRL, 0);
1623 }
1624 } else {
1625 /* Asking for a specific link mode. */
1626 if (tp->link_config.speed == SPEED_1000) {
1627 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1628 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629
1630 if (tp->link_config.duplex == DUPLEX_FULL)
1631 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1632 else
1633 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1634 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1635 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1636 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1637 MII_TG3_CTRL_ENABLE_AS_MASTER);
1638 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1639 } else {
1640 tg3_writephy(tp, MII_TG3_CTRL, 0);
1641
1642 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1643 if (tp->link_config.speed == SPEED_100) {
1644 if (tp->link_config.duplex == DUPLEX_FULL)
1645 new_adv |= ADVERTISE_100FULL;
1646 else
1647 new_adv |= ADVERTISE_100HALF;
1648 } else {
1649 if (tp->link_config.duplex == DUPLEX_FULL)
1650 new_adv |= ADVERTISE_10FULL;
1651 else
1652 new_adv |= ADVERTISE_10HALF;
1653 }
1654 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655 }
1656 }
1657
1658 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1659 tp->link_config.speed != SPEED_INVALID) {
1660 u32 bmcr, orig_bmcr;
1661
1662 tp->link_config.active_speed = tp->link_config.speed;
1663 tp->link_config.active_duplex = tp->link_config.duplex;
1664
1665 bmcr = 0;
1666 switch (tp->link_config.speed) {
1667 default:
1668 case SPEED_10:
1669 break;
1670
1671 case SPEED_100:
1672 bmcr |= BMCR_SPEED100;
1673 break;
1674
1675 case SPEED_1000:
1676 bmcr |= TG3_BMCR_SPEED1000;
1677 break;
1678 };
1679
1680 if (tp->link_config.duplex == DUPLEX_FULL)
1681 bmcr |= BMCR_FULLDPLX;
1682
1683 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1684 (bmcr != orig_bmcr)) {
1685 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1686 for (i = 0; i < 1500; i++) {
1687 u32 tmp;
1688
1689 udelay(10);
1690 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1691 tg3_readphy(tp, MII_BMSR, &tmp))
1692 continue;
1693 if (!(tmp & BMSR_LSTATUS)) {
1694 udelay(40);
1695 break;
1696 }
1697 }
1698 tg3_writephy(tp, MII_BMCR, bmcr);
1699 udelay(40);
1700 }
1701 } else {
1702 tg3_writephy(tp, MII_BMCR,
1703 BMCR_ANENABLE | BMCR_ANRESTART);
1704 }
1705}
1706
1707static int tg3_init_5401phy_dsp(struct tg3 *tp)
1708{
1709 int err;
1710
1711 /* Turn off tap power management. */
1712 /* Set Extended packet length bit */
1713 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1714
1715 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1716 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1717
1718 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1719 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1720
1721 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1722 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1723
1724 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1725 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1726
1727 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1728 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1729
1730 udelay(40);
1731
1732 return err;
1733}
1734
3600d918 1735static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1736{
3600d918
MC		 1737 u32 adv_reg, all_mask = 0;
1738
1739 if (mask & ADVERTISED_10baseT_Half)
1740 all_mask |= ADVERTISE_10HALF;
1741 if (mask & ADVERTISED_10baseT_Full)
1742 all_mask |= ADVERTISE_10FULL;
1743 if (mask & ADVERTISED_100baseT_Half)
1744 all_mask |= ADVERTISE_100HALF;
1745 if (mask & ADVERTISED_100baseT_Full)
1746 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1747
1748 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1749 return 0;
1750
1da177e4
LT		 1751 if ((adv_reg & all_mask) != all_mask)
1752 return 0;
1753 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1754 u32 tg3_ctrl;
1755
3600d918
MC		 1756 all_mask = 0;
1757 if (mask & ADVERTISED_1000baseT_Half)
1758 all_mask |= ADVERTISE_1000HALF;
1759 if (mask & ADVERTISED_1000baseT_Full)
1760 all_mask |= ADVERTISE_1000FULL;
1761
1da177e4
LT		 1762 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1763 return 0;
1764
1da177e4
LT		 1765 if ((tg3_ctrl & all_mask) != all_mask)
1766 return 0;
1767 }
1768 return 1;
1769}
1770
1771static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1772{
1773 int current_link_up;
1774 u32 bmsr, dummy;
1775 u16 current_speed;
1776 u8 current_duplex;
1777 int i, err;
1778
1779 tw32(MAC_EVENT, 0);
1780
1781 tw32_f(MAC_STATUS,
1782 (MAC_STATUS_SYNC_CHANGED |
1783 MAC_STATUS_CFG_CHANGED |
1784 MAC_STATUS_MI_COMPLETION |
1785 MAC_STATUS_LNKSTATE_CHANGED));
1786 udelay(40);
1787
1788 tp->mi_mode = MAC_MI_MODE_BASE;
1789 tw32_f(MAC_MI_MODE, tp->mi_mode);
1790 udelay(80);
1791
1792 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1793
1794 /* Some third-party PHYs need to be reset on link going
1795 * down.
1796 */
1797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1800 netif_carrier_ok(tp->dev)) {
1801 tg3_readphy(tp, MII_BMSR, &bmsr);
1802 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1803 !(bmsr & BMSR_LSTATUS))
1804 force_reset = 1;
1805 }
1806 if (force_reset)
1807 tg3_phy_reset(tp);
1808
1809 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1810 tg3_readphy(tp, MII_BMSR, &bmsr);
1811 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1812 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1813 bmsr = 0;
1814
1815 if (!(bmsr & BMSR_LSTATUS)) {
1816 err = tg3_init_5401phy_dsp(tp);
1817 if (err)
1818 return err;
1819
1820 tg3_readphy(tp, MII_BMSR, &bmsr);
1821 for (i = 0; i < 1000; i++) {
1822 udelay(10);
1823 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1824 (bmsr & BMSR_LSTATUS)) {
1825 udelay(40);
1826 break;
1827 }
1828 }
1829
1830 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1831 !(bmsr & BMSR_LSTATUS) &&
1832 tp->link_config.active_speed == SPEED_1000) {
1833 err = tg3_phy_reset(tp);
1834 if (!err)
1835 err = tg3_init_5401phy_dsp(tp);
1836 if (err)
1837 return err;
1838 }
1839 }
1840 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1841 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1842 /* 5701 {A0,B0} CRC bug workaround */
1843 tg3_writephy(tp, 0x15, 0x0a75);
1844 tg3_writephy(tp, 0x1c, 0x8c68);
1845 tg3_writephy(tp, 0x1c, 0x8d68);
1846 tg3_writephy(tp, 0x1c, 0x8c68);
1847 }
1848
1849 /* Clear pending interrupts... */
1850 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1852
1853 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 1855 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 1856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1857
1858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1863 else
1864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1865 }
1866
1867 current_link_up = 0;
1868 current_speed = SPEED_INVALID;
1869 current_duplex = DUPLEX_INVALID;
1870
1871 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1872 u32 val;
1873
1874 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1875 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1876 if (!(val & (1 << 10))) {
1877 val |= (1 << 10);
1878 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1879 goto relink;
1880 }
1881 }
1882
1883 bmsr = 0;
1884 for (i = 0; i < 100; i++) {
1885 tg3_readphy(tp, MII_BMSR, &bmsr);
1886 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1887 (bmsr & BMSR_LSTATUS))
1888 break;
1889 udelay(40);
1890 }
1891
1892 if (bmsr & BMSR_LSTATUS) {
1893 u32 aux_stat, bmcr;
1894
1895 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1896 for (i = 0; i < 2000; i++) {
1897 udelay(10);
1898 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1899 aux_stat)
1900 break;
1901 }
1902
1903 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1904 &current_speed,
1905 &current_duplex);
1906
1907 bmcr = 0;
1908 for (i = 0; i < 200; i++) {
1909 tg3_readphy(tp, MII_BMCR, &bmcr);
1910 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1911 continue;
1912 if (bmcr && bmcr != 0x7fff)
1913 break;
1914 udelay(10);
1915 }
1916
1917 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1918 if (bmcr & BMCR_ANENABLE) {
1919 current_link_up = 1;
1920
1921 /* Force autoneg restart if we are exiting
1922 * low power mode.
1923 */
3600d918
MC		 1924 if (!tg3_copper_is_advertising_all(tp,
1925 tp->link_config.advertising))
1da177e4
LT		 1926 current_link_up = 0;
1927 } else {
1928 current_link_up = 0;
1929 }
1930 } else {
1931 if (!(bmcr & BMCR_ANENABLE) &&
1932 tp->link_config.speed == current_speed &&
1933 tp->link_config.duplex == current_duplex) {
1934 current_link_up = 1;
1935 } else {
1936 current_link_up = 0;
1937 }
1938 }
1939
1940 tp->link_config.active_speed = current_speed;
1941 tp->link_config.active_duplex = current_duplex;
1942 }
1943
1944 if (current_link_up == 1 &&
1945 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1946 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1947 u32 local_adv, remote_adv;
1948
1949 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1950 local_adv = 0;
1951 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1952
1953 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1954 remote_adv = 0;
1955
1956 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1957
1958 /* If we are not advertising full pause capability,
1959 * something is wrong. Bring the link down and reconfigure.
1960 */
1961 if (local_adv != ADVERTISE_PAUSE_CAP) {
1962 current_link_up = 0;
1963 } else {
1964 tg3_setup_flow_control(tp, local_adv, remote_adv);
1965 }
1966 }
1967relink:
6921d201 1968 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1969 u32 tmp;
1970
1971 tg3_phy_copper_begin(tp);
1972
1973 tg3_readphy(tp, MII_BMSR, &tmp);
1974 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1975 (tmp & BMSR_LSTATUS))
1976 current_link_up = 1;
1977 }
1978
1979 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1980 if (current_link_up == 1) {
1981 if (tp->link_config.active_speed == SPEED_100 ||
1982 tp->link_config.active_speed == SPEED_10)
1983 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1984 else
1985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986 } else
1987 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1988
1989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1990 if (tp->link_config.active_duplex == DUPLEX_HALF)
1991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992
1993 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1996 (current_link_up == 1 &&
1997 tp->link_config.active_speed == SPEED_10))
1998 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999 } else {
2000 if (current_link_up == 1)
2001 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2002 }
2003
2004 /* ??? Without this setting Netgear GA302T PHY does not
2005 * ??? send/receive packets...
2006 */
2007 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2008 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2009 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2010 tw32_f(MAC_MI_MODE, tp->mi_mode);
2011 udelay(80);
2012 }
2013
2014 tw32_f(MAC_MODE, tp->mac_mode);
2015 udelay(40);
2016
2017 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2018 /* Polled via timer. */
2019 tw32_f(MAC_EVENT, 0);
2020 } else {
2021 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2022 }
2023 udelay(40);
2024
2025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2026 current_link_up == 1 &&
2027 tp->link_config.active_speed == SPEED_1000 &&
2028 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2029 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2030 udelay(120);
2031 tw32_f(MAC_STATUS,
2032 (MAC_STATUS_SYNC_CHANGED |
2033 MAC_STATUS_CFG_CHANGED));
2034 udelay(40);
2035 tg3_write_mem(tp,
2036 NIC_SRAM_FIRMWARE_MBOX,
2037 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2038 }
2039
2040 if (current_link_up != netif_carrier_ok(tp->dev)) {
2041 if (current_link_up)
2042 netif_carrier_on(tp->dev);
2043 else
2044 netif_carrier_off(tp->dev);
2045 tg3_link_report(tp);
2046 }
2047
2048 return 0;
2049}
2050
2051struct tg3_fiber_aneginfo {
2052 int state;
2053#define ANEG_STATE_UNKNOWN 0
2054#define ANEG_STATE_AN_ENABLE 1
2055#define ANEG_STATE_RESTART_INIT 2
2056#define ANEG_STATE_RESTART 3
2057#define ANEG_STATE_DISABLE_LINK_OK 4
2058#define ANEG_STATE_ABILITY_DETECT_INIT 5
2059#define ANEG_STATE_ABILITY_DETECT 6
2060#define ANEG_STATE_ACK_DETECT_INIT 7
2061#define ANEG_STATE_ACK_DETECT 8
2062#define ANEG_STATE_COMPLETE_ACK_INIT 9
2063#define ANEG_STATE_COMPLETE_ACK 10
2064#define ANEG_STATE_IDLE_DETECT_INIT 11
2065#define ANEG_STATE_IDLE_DETECT 12
2066#define ANEG_STATE_LINK_OK 13
2067#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2068#define ANEG_STATE_NEXT_PAGE_WAIT 15
2069
2070 u32 flags;
2071#define MR_AN_ENABLE 0x00000001
2072#define MR_RESTART_AN 0x00000002
2073#define MR_AN_COMPLETE 0x00000004
2074#define MR_PAGE_RX 0x00000008
2075#define MR_NP_LOADED 0x00000010
2076#define MR_TOGGLE_TX 0x00000020
2077#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2078#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2079#define MR_LP_ADV_SYM_PAUSE 0x00000100
2080#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2081#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2082#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2083#define MR_LP_ADV_NEXT_PAGE 0x00001000
2084#define MR_TOGGLE_RX 0x00002000
2085#define MR_NP_RX 0x00004000
2086
2087#define MR_LINK_OK 0x80000000
2088
2089 unsigned long link_time, cur_time;
2090
2091 u32 ability_match_cfg;
2092 int ability_match_count;
2093
2094 char ability_match, idle_match, ack_match;
2095
2096 u32 txconfig, rxconfig;
2097#define ANEG_CFG_NP 0x00000080
2098#define ANEG_CFG_ACK 0x00000040
2099#define ANEG_CFG_RF2 0x00000020
2100#define ANEG_CFG_RF1 0x00000010
2101#define ANEG_CFG_PS2 0x00000001
2102#define ANEG_CFG_PS1 0x00008000
2103#define ANEG_CFG_HD 0x00004000
2104#define ANEG_CFG_FD 0x00002000
2105#define ANEG_CFG_INVAL 0x00001f06
2106
2107};
2108#define ANEG_OK 0
2109#define ANEG_DONE 1
2110#define ANEG_TIMER_ENAB 2
2111#define ANEG_FAILED -1
2112
2113#define ANEG_STATE_SETTLE_TIME 10000
2114
2115static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2116 struct tg3_fiber_aneginfo *ap)
2117{
2118 unsigned long delta;
2119 u32 rx_cfg_reg;
2120 int ret;
2121
2122 if (ap->state == ANEG_STATE_UNKNOWN) {
2123 ap->rxconfig = 0;
2124 ap->link_time = 0;
2125 ap->cur_time = 0;
2126 ap->ability_match_cfg = 0;
2127 ap->ability_match_count = 0;
2128 ap->ability_match = 0;
2129 ap->idle_match = 0;
2130 ap->ack_match = 0;
2131 }
2132 ap->cur_time++;
2133
2134 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2135 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2136
2137 if (rx_cfg_reg != ap->ability_match_cfg) {
2138 ap->ability_match_cfg = rx_cfg_reg;
2139 ap->ability_match = 0;
2140 ap->ability_match_count = 0;
2141 } else {
2142 if (++ap->ability_match_count > 1) {
2143 ap->ability_match = 1;
2144 ap->ability_match_cfg = rx_cfg_reg;
2145 }
2146 }
2147 if (rx_cfg_reg & ANEG_CFG_ACK)
2148 ap->ack_match = 1;
2149 else
2150 ap->ack_match = 0;
2151
2152 ap->idle_match = 0;
2153 } else {
2154 ap->idle_match = 1;
2155 ap->ability_match_cfg = 0;
2156 ap->ability_match_count = 0;
2157 ap->ability_match = 0;
2158 ap->ack_match = 0;
2159
2160 rx_cfg_reg = 0;
2161 }
2162
2163 ap->rxconfig = rx_cfg_reg;
2164 ret = ANEG_OK;
2165
2166 switch(ap->state) {
2167 case ANEG_STATE_UNKNOWN:
2168 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2169 ap->state = ANEG_STATE_AN_ENABLE;
2170
2171 /* fallthru */
2172 case ANEG_STATE_AN_ENABLE:
2173 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2174 if (ap->flags & MR_AN_ENABLE) {
2175 ap->link_time = 0;
2176 ap->cur_time = 0;
2177 ap->ability_match_cfg = 0;
2178 ap->ability_match_count = 0;
2179 ap->ability_match = 0;
2180 ap->idle_match = 0;
2181 ap->ack_match = 0;
2182
2183 ap->state = ANEG_STATE_RESTART_INIT;
2184 } else {
2185 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2186 }
2187 break;
2188
2189 case ANEG_STATE_RESTART_INIT:
2190 ap->link_time = ap->cur_time;
2191 ap->flags &= ~(MR_NP_LOADED);
2192 ap->txconfig = 0;
2193 tw32(MAC_TX_AUTO_NEG, 0);
2194 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2195 tw32_f(MAC_MODE, tp->mac_mode);
2196 udelay(40);
2197
2198 ret = ANEG_TIMER_ENAB;
2199 ap->state = ANEG_STATE_RESTART;
2200
2201 /* fallthru */
2202 case ANEG_STATE_RESTART:
2203 delta = ap->cur_time - ap->link_time;
2204 if (delta > ANEG_STATE_SETTLE_TIME) {
2205 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2206 } else {
2207 ret = ANEG_TIMER_ENAB;
2208 }
2209 break;
2210
2211 case ANEG_STATE_DISABLE_LINK_OK:
2212 ret = ANEG_DONE;
2213 break;
2214
2215 case ANEG_STATE_ABILITY_DETECT_INIT:
2216 ap->flags &= ~(MR_TOGGLE_TX);
2217 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2218 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2219 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2220 tw32_f(MAC_MODE, tp->mac_mode);
2221 udelay(40);
2222
2223 ap->state = ANEG_STATE_ABILITY_DETECT;
2224 break;
2225
2226 case ANEG_STATE_ABILITY_DETECT:
2227 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2228 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2229 }
2230 break;
2231
2232 case ANEG_STATE_ACK_DETECT_INIT:
2233 ap->txconfig |= ANEG_CFG_ACK;
2234 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2235 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2236 tw32_f(MAC_MODE, tp->mac_mode);
2237 udelay(40);
2238
2239 ap->state = ANEG_STATE_ACK_DETECT;
2240
2241 /* fallthru */
2242 case ANEG_STATE_ACK_DETECT:
2243 if (ap->ack_match != 0) {
2244 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2245 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2246 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2247 } else {
2248 ap->state = ANEG_STATE_AN_ENABLE;
2249 }
2250 } else if (ap->ability_match != 0 &&
2251 ap->rxconfig == 0) {
2252 ap->state = ANEG_STATE_AN_ENABLE;
2253 }
2254 break;
2255
2256 case ANEG_STATE_COMPLETE_ACK_INIT:
2257 if (ap->rxconfig & ANEG_CFG_INVAL) {
2258 ret = ANEG_FAILED;
2259 break;
2260 }
2261 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2262 MR_LP_ADV_HALF_DUPLEX |
2263 MR_LP_ADV_SYM_PAUSE |
2264 MR_LP_ADV_ASYM_PAUSE |
2265 MR_LP_ADV_REMOTE_FAULT1 |
2266 MR_LP_ADV_REMOTE_FAULT2 |
2267 MR_LP_ADV_NEXT_PAGE |
2268 MR_TOGGLE_RX |
2269 MR_NP_RX);
2270 if (ap->rxconfig & ANEG_CFG_FD)
2271 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2272 if (ap->rxconfig & ANEG_CFG_HD)
2273 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2274 if (ap->rxconfig & ANEG_CFG_PS1)
2275 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2276 if (ap->rxconfig & ANEG_CFG_PS2)
2277 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2278 if (ap->rxconfig & ANEG_CFG_RF1)
2279 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2280 if (ap->rxconfig & ANEG_CFG_RF2)
2281 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2282 if (ap->rxconfig & ANEG_CFG_NP)
2283 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2284
2285 ap->link_time = ap->cur_time;
2286
2287 ap->flags ^= (MR_TOGGLE_TX);
2288 if (ap->rxconfig & 0x0008)
2289 ap->flags |= MR_TOGGLE_RX;
2290 if (ap->rxconfig & ANEG_CFG_NP)
2291 ap->flags |= MR_NP_RX;
2292 ap->flags |= MR_PAGE_RX;
2293
2294 ap->state = ANEG_STATE_COMPLETE_ACK;
2295 ret = ANEG_TIMER_ENAB;
2296 break;
2297
2298 case ANEG_STATE_COMPLETE_ACK:
2299 if (ap->ability_match != 0 &&
2300 ap->rxconfig == 0) {
2301 ap->state = ANEG_STATE_AN_ENABLE;
2302 break;
2303 }
2304 delta = ap->cur_time - ap->link_time;
2305 if (delta > ANEG_STATE_SETTLE_TIME) {
2306 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2307 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2308 } else {
2309 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2310 !(ap->flags & MR_NP_RX)) {
2311 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2312 } else {
2313 ret = ANEG_FAILED;
2314 }
2315 }
2316 }
2317 break;
2318
2319 case ANEG_STATE_IDLE_DETECT_INIT:
2320 ap->link_time = ap->cur_time;
2321 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2322 tw32_f(MAC_MODE, tp->mac_mode);
2323 udelay(40);
2324
2325 ap->state = ANEG_STATE_IDLE_DETECT;
2326 ret = ANEG_TIMER_ENAB;
2327 break;
2328
2329 case ANEG_STATE_IDLE_DETECT:
2330 if (ap->ability_match != 0 &&
2331 ap->rxconfig == 0) {
2332 ap->state = ANEG_STATE_AN_ENABLE;
2333 break;
2334 }
2335 delta = ap->cur_time - ap->link_time;
2336 if (delta > ANEG_STATE_SETTLE_TIME) {
2337 /* XXX another gem from the Broadcom driver :( */
2338 ap->state = ANEG_STATE_LINK_OK;
2339 }
2340 break;
2341
2342 case ANEG_STATE_LINK_OK:
2343 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2344 ret = ANEG_DONE;
2345 break;
2346
2347 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2348 /* ??? unimplemented */
2349 break;
2350
2351 case ANEG_STATE_NEXT_PAGE_WAIT:
2352 /* ??? unimplemented */
2353 break;
2354
2355 default:
2356 ret = ANEG_FAILED;
2357 break;
2358 };
2359
2360 return ret;
2361}
2362
2363static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2364{
2365 int res = 0;
2366 struct tg3_fiber_aneginfo aninfo;
2367 int status = ANEG_FAILED;
2368 unsigned int tick;
2369 u32 tmp;
2370
2371 tw32_f(MAC_TX_AUTO_NEG, 0);
2372
2373 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2374 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2375 udelay(40);
2376
2377 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2378 udelay(40);
2379
2380 memset(&aninfo, 0, sizeof(aninfo));
2381 aninfo.flags |= MR_AN_ENABLE;
2382 aninfo.state = ANEG_STATE_UNKNOWN;
2383 aninfo.cur_time = 0;
2384 tick = 0;
2385 while (++tick < 195000) {
2386 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2387 if (status == ANEG_DONE || status == ANEG_FAILED)
2388 break;
2389
2390 udelay(1);
2391 }
2392
2393 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2394 tw32_f(MAC_MODE, tp->mac_mode);
2395 udelay(40);
2396
2397 *flags = aninfo.flags;
2398
2399 if (status == ANEG_DONE &&
2400 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2401 MR_LP_ADV_FULL_DUPLEX)))
2402 res = 1;
2403
2404 return res;
2405}
2406
2407static void tg3_init_bcm8002(struct tg3 *tp)
2408{
2409 u32 mac_status = tr32(MAC_STATUS);
2410 int i;
2411
2412 /* Reset when initting first time or we have a link. */
2413 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2414 !(mac_status & MAC_STATUS_PCS_SYNCED))
2415 return;
2416
2417 /* Set PLL lock range. */
2418 tg3_writephy(tp, 0x16, 0x8007);
2419
2420 /* SW reset */
2421 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2422
2423 /* Wait for reset to complete. */
2424 /* XXX schedule_timeout() ... */
2425 for (i = 0; i < 500; i++)
2426 udelay(10);
2427
2428 /* Config mode; select PMA/Ch 1 regs. */
2429 tg3_writephy(tp, 0x10, 0x8411);
2430
2431 /* Enable auto-lock and comdet, select txclk for tx. */
2432 tg3_writephy(tp, 0x11, 0x0a10);
2433
2434 tg3_writephy(tp, 0x18, 0x00a0);
2435 tg3_writephy(tp, 0x16, 0x41ff);
2436
2437 /* Assert and deassert POR. */
2438 tg3_writephy(tp, 0x13, 0x0400);
2439 udelay(40);
2440 tg3_writephy(tp, 0x13, 0x0000);
2441
2442 tg3_writephy(tp, 0x11, 0x0a50);
2443 udelay(40);
2444 tg3_writephy(tp, 0x11, 0x0a10);
2445
2446 /* Wait for signal to stabilize */
2447 /* XXX schedule_timeout() ... */
2448 for (i = 0; i < 15000; i++)
2449 udelay(10);
2450
2451 /* Deselect the channel register so we can read the PHYID
2452 * later.
2453 */
2454 tg3_writephy(tp, 0x10, 0x8011);
2455}
2456
2457static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2458{
2459 u32 sg_dig_ctrl, sg_dig_status;
2460 u32 serdes_cfg, expected_sg_dig_ctrl;
2461 int workaround, port_a;
2462 int current_link_up;
2463
2464 serdes_cfg = 0;
2465 expected_sg_dig_ctrl = 0;
2466 workaround = 0;
2467 port_a = 1;
2468 current_link_up = 0;
2469
2470 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2471 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2472 workaround = 1;
2473 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2474 port_a = 0;
2475
2476 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2477 /* preserve bits 20-23 for voltage regulator */
2478 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2479 }
2480
2481 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2482
2483 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2484 if (sg_dig_ctrl & (1 << 31)) {
2485 if (workaround) {
2486 u32 val = serdes_cfg;
2487
2488 if (port_a)
2489 val |= 0xc010000;
2490 else
2491 val |= 0x4010000;
2492 tw32_f(MAC_SERDES_CFG, val);
2493 }
2494 tw32_f(SG_DIG_CTRL, 0x01388400);
2495 }
2496 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2497 tg3_setup_flow_control(tp, 0, 0);
2498 current_link_up = 1;
2499 }
2500 goto out;
2501 }
2502
2503 /* Want auto-negotiation. */
2504 expected_sg_dig_ctrl = 0x81388400;
2505
2506 /* Pause capability */
2507 expected_sg_dig_ctrl |= (1 << 11);
2508
2509 /* Asymettric pause */
2510 expected_sg_dig_ctrl |= (1 << 12);
2511
2512 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2513 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2514 tp->serdes_counter &&
2515 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2516 MAC_STATUS_RCVD_CFG)) ==
2517 MAC_STATUS_PCS_SYNCED)) {
2518 tp->serdes_counter--;
2519 current_link_up = 1;
2520 goto out;
2521 }
2522restart_autoneg:
1da177e4
LT		 2523 if (workaround)
2524 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2525 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2526 udelay(5);
2527 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2528
3d3ebe74
MC		 2529 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2530 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2531 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2532 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2533 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2534 mac_status = tr32(MAC_STATUS);
2535
2536 if ((sg_dig_status & (1 << 1)) &&
2537 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2538 u32 local_adv, remote_adv;
2539
2540 local_adv = ADVERTISE_PAUSE_CAP;
2541 remote_adv = 0;
2542 if (sg_dig_status & (1 << 19))
2543 remote_adv |= LPA_PAUSE_CAP;
2544 if (sg_dig_status & (1 << 20))
2545 remote_adv |= LPA_PAUSE_ASYM;
2546
2547 tg3_setup_flow_control(tp, local_adv, remote_adv);
2548 current_link_up = 1;
3d3ebe74
MC		 2549 tp->serdes_counter = 0;
2550 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2551 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2552 if (tp->serdes_counter)
2553 tp->serdes_counter--;
1da177e4
LT		 2554 else {
2555 if (workaround) {
2556 u32 val = serdes_cfg;
2557
2558 if (port_a)
2559 val |= 0xc010000;
2560 else
2561 val |= 0x4010000;
2562
2563 tw32_f(MAC_SERDES_CFG, val);
2564 }
2565
2566 tw32_f(SG_DIG_CTRL, 0x01388400);
2567 udelay(40);
2568
2569 /* Link parallel detection - link is up */
2570 /* only if we have PCS_SYNC and not */
2571 /* receiving config code words */
2572 mac_status = tr32(MAC_STATUS);
2573 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2574 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2575 tg3_setup_flow_control(tp, 0, 0);
2576 current_link_up = 1;
3d3ebe74
MC		 2577 tp->tg3_flags2 |=
2578 TG3_FLG2_PARALLEL_DETECT;
2579 tp->serdes_counter =
2580 SERDES_PARALLEL_DET_TIMEOUT;
2581 } else
2582 goto restart_autoneg;
1da177e4
LT		 2583 }
2584 }
3d3ebe74
MC		 2585 } else {
2586 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2587 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2588 }
2589
2590out:
2591 return current_link_up;
2592}
2593
2594static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2595{
2596 int current_link_up = 0;
2597
5cf64b8a 2598 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 2599 goto out;
1da177e4
LT		 2600
2601 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602 u32 flags;
2603 int i;
6aa20a22 2604
1da177e4
LT		 2605 if (fiber_autoneg(tp, &flags)) {
2606 u32 local_adv, remote_adv;
2607
2608 local_adv = ADVERTISE_PAUSE_CAP;
2609 remote_adv = 0;
2610 if (flags & MR_LP_ADV_SYM_PAUSE)
2611 remote_adv |= LPA_PAUSE_CAP;
2612 if (flags & MR_LP_ADV_ASYM_PAUSE)
2613 remote_adv |= LPA_PAUSE_ASYM;
2614
2615 tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
1da177e4
LT		 2617 current_link_up = 1;
2618 }
2619 for (i = 0; i < 30; i++) {
2620 udelay(20);
2621 tw32_f(MAC_STATUS,
2622 (MAC_STATUS_SYNC_CHANGED |
2623 MAC_STATUS_CFG_CHANGED));
2624 udelay(40);
2625 if ((tr32(MAC_STATUS) &
2626 (MAC_STATUS_SYNC_CHANGED |
2627 MAC_STATUS_CFG_CHANGED)) == 0)
2628 break;
2629 }
2630
2631 mac_status = tr32(MAC_STATUS);
2632 if (current_link_up == 0 &&
2633 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2634 !(mac_status & MAC_STATUS_RCVD_CFG))
2635 current_link_up = 1;
2636 } else {
2637 /* Forcing 1000FD link up. */
2638 current_link_up = 1;
1da177e4
LT		 2639
2640 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2641 udelay(40);
2642 }
2643
2644out:
2645 return current_link_up;
2646}
2647
2648static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2649{
2650 u32 orig_pause_cfg;
2651 u16 orig_active_speed;
2652 u8 orig_active_duplex;
2653 u32 mac_status;
2654 int current_link_up;
2655 int i;
2656
2657 orig_pause_cfg =
2658 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2659 TG3_FLAG_TX_PAUSE));
2660 orig_active_speed = tp->link_config.active_speed;
2661 orig_active_duplex = tp->link_config.active_duplex;
2662
2663 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2664 netif_carrier_ok(tp->dev) &&
2665 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2666 mac_status = tr32(MAC_STATUS);
2667 mac_status &= (MAC_STATUS_PCS_SYNCED |
2668 MAC_STATUS_SIGNAL_DET |
2669 MAC_STATUS_CFG_CHANGED |
2670 MAC_STATUS_RCVD_CFG);
2671 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2672 MAC_STATUS_SIGNAL_DET)) {
2673 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2674 MAC_STATUS_CFG_CHANGED));
2675 return 0;
2676 }
2677 }
2678
2679 tw32_f(MAC_TX_AUTO_NEG, 0);
2680
2681 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2682 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2683 tw32_f(MAC_MODE, tp->mac_mode);
2684 udelay(40);
2685
2686 if (tp->phy_id == PHY_ID_BCM8002)
2687 tg3_init_bcm8002(tp);
2688
2689 /* Enable link change event even when serdes polling. */
2690 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2691 udelay(40);
2692
2693 current_link_up = 0;
2694 mac_status = tr32(MAC_STATUS);
2695
2696 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2697 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2698 else
2699 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2700
2701 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2702 tw32_f(MAC_MODE, tp->mac_mode);
2703 udelay(40);
2704
2705 tp->hw_status->status =
2706 (SD_STATUS_UPDATED |
2707 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2708
2709 for (i = 0; i < 100; i++) {
2710 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2711 MAC_STATUS_CFG_CHANGED));
2712 udelay(5);
2713 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2714 MAC_STATUS_CFG_CHANGED |
2715 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2716 break;
2717 }
2718
2719 mac_status = tr32(MAC_STATUS);
2720 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2721 current_link_up = 0;
3d3ebe74
MC		 2722 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2723 tp->serdes_counter == 0) {
1da177e4
LT		 2724 tw32_f(MAC_MODE, (tp->mac_mode |
2725 MAC_MODE_SEND_CONFIGS));
2726 udelay(1);
2727 tw32_f(MAC_MODE, tp->mac_mode);
2728 }
2729 }
2730
2731 if (current_link_up == 1) {
2732 tp->link_config.active_speed = SPEED_1000;
2733 tp->link_config.active_duplex = DUPLEX_FULL;
2734 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2735 LED_CTRL_LNKLED_OVERRIDE |
2736 LED_CTRL_1000MBPS_ON));
2737 } else {
2738 tp->link_config.active_speed = SPEED_INVALID;
2739 tp->link_config.active_duplex = DUPLEX_INVALID;
2740 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2741 LED_CTRL_LNKLED_OVERRIDE |
2742 LED_CTRL_TRAFFIC_OVERRIDE));
2743 }
2744
2745 if (current_link_up != netif_carrier_ok(tp->dev)) {
2746 if (current_link_up)
2747 netif_carrier_on(tp->dev);
2748 else
2749 netif_carrier_off(tp->dev);
2750 tg3_link_report(tp);
2751 } else {
2752 u32 now_pause_cfg =
2753 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2754 TG3_FLAG_TX_PAUSE);
2755 if (orig_pause_cfg != now_pause_cfg ||
2756 orig_active_speed != tp->link_config.active_speed ||
2757 orig_active_duplex != tp->link_config.active_duplex)
2758 tg3_link_report(tp);
2759 }
2760
2761 return 0;
2762}
2763
747e8f8b
MC		 2764static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2765{
2766 int current_link_up, err = 0;
2767 u32 bmsr, bmcr;
2768 u16 current_speed;
2769 u8 current_duplex;
2770
2771 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2772 tw32_f(MAC_MODE, tp->mac_mode);
2773 udelay(40);
2774
2775 tw32(MAC_EVENT, 0);
2776
2777 tw32_f(MAC_STATUS,
2778 (MAC_STATUS_SYNC_CHANGED |
2779 MAC_STATUS_CFG_CHANGED |
2780 MAC_STATUS_MI_COMPLETION |
2781 MAC_STATUS_LNKSTATE_CHANGED));
2782 udelay(40);
2783
2784 if (force_reset)
2785 tg3_phy_reset(tp);
2786
2787 current_link_up = 0;
2788 current_speed = SPEED_INVALID;
2789 current_duplex = DUPLEX_INVALID;
2790
2791 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2792 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2794 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2795 bmsr |= BMSR_LSTATUS;
2796 else
2797 bmsr &= ~BMSR_LSTATUS;
2798 }
747e8f8b
MC		 2799
2800 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2801
2802 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2803 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2804 /* do nothing, just check for link up at the end */
2805 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2806 u32 adv, new_adv;
2807
2808 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2809 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2810 ADVERTISE_1000XPAUSE |
2811 ADVERTISE_1000XPSE_ASYM |
2812 ADVERTISE_SLCT);
2813
2814 /* Always advertise symmetric PAUSE just like copper */
2815 new_adv |= ADVERTISE_1000XPAUSE;
2816
2817 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2818 new_adv |= ADVERTISE_1000XHALF;
2819 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2820 new_adv |= ADVERTISE_1000XFULL;
2821
2822 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2823 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2824 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2825 tg3_writephy(tp, MII_BMCR, bmcr);
2826
2827 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2828 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2829 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2830
2831 return err;
2832 }
2833 } else {
2834 u32 new_bmcr;
2835
2836 bmcr &= ~BMCR_SPEED1000;
2837 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2838
2839 if (tp->link_config.duplex == DUPLEX_FULL)
2840 new_bmcr |= BMCR_FULLDPLX;
2841
2842 if (new_bmcr != bmcr) {
2843 /* BMCR_SPEED1000 is a reserved bit that needs
2844 * to be set on write.
2845 */
2846 new_bmcr |= BMCR_SPEED1000;
2847
2848 /* Force a linkdown */
2849 if (netif_carrier_ok(tp->dev)) {
2850 u32 adv;
2851
2852 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2853 adv &= ~(ADVERTISE_1000XFULL |
2854 ADVERTISE_1000XHALF |
2855 ADVERTISE_SLCT);
2856 tg3_writephy(tp, MII_ADVERTISE, adv);
2857 tg3_writephy(tp, MII_BMCR, bmcr |
2858 BMCR_ANRESTART |
2859 BMCR_ANENABLE);
2860 udelay(10);
2861 netif_carrier_off(tp->dev);
2862 }
2863 tg3_writephy(tp, MII_BMCR, new_bmcr);
2864 bmcr = new_bmcr;
2865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2866 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2867 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2868 ASIC_REV_5714) {
2869 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2870 bmsr |= BMSR_LSTATUS;
2871 else
2872 bmsr &= ~BMSR_LSTATUS;
2873 }
747e8f8b
MC		 2874 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2875 }
2876 }
2877
2878 if (bmsr & BMSR_LSTATUS) {
2879 current_speed = SPEED_1000;
2880 current_link_up = 1;
2881 if (bmcr & BMCR_FULLDPLX)
2882 current_duplex = DUPLEX_FULL;
2883 else
2884 current_duplex = DUPLEX_HALF;
2885
2886 if (bmcr & BMCR_ANENABLE) {
2887 u32 local_adv, remote_adv, common;
2888
2889 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2890 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2891 common = local_adv & remote_adv;
2892 if (common & (ADVERTISE_1000XHALF |
2893 ADVERTISE_1000XFULL)) {
2894 if (common & ADVERTISE_1000XFULL)
2895 current_duplex = DUPLEX_FULL;
2896 else
2897 current_duplex = DUPLEX_HALF;
2898
2899 tg3_setup_flow_control(tp, local_adv,
2900 remote_adv);
2901 }
2902 else
2903 current_link_up = 0;
2904 }
2905 }
2906
2907 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2908 if (tp->link_config.active_duplex == DUPLEX_HALF)
2909 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2910
2911 tw32_f(MAC_MODE, tp->mac_mode);
2912 udelay(40);
2913
2914 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2915
2916 tp->link_config.active_speed = current_speed;
2917 tp->link_config.active_duplex = current_duplex;
2918
2919 if (current_link_up != netif_carrier_ok(tp->dev)) {
2920 if (current_link_up)
2921 netif_carrier_on(tp->dev);
2922 else {
2923 netif_carrier_off(tp->dev);
2924 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2925 }
2926 tg3_link_report(tp);
2927 }
2928 return err;
2929}
2930
2931static void tg3_serdes_parallel_detect(struct tg3 *tp)
2932{
3d3ebe74 2933 if (tp->serdes_counter) {
747e8f8b 2934 /* Give autoneg time to complete. */
3d3ebe74 2935 tp->serdes_counter--;
747e8f8b
MC		 2936 return;
2937 }
2938 if (!netif_carrier_ok(tp->dev) &&
2939 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2940 u32 bmcr;
2941
2942 tg3_readphy(tp, MII_BMCR, &bmcr);
2943 if (bmcr & BMCR_ANENABLE) {
2944 u32 phy1, phy2;
2945
2946 /* Select shadow register 0x1f */
2947 tg3_writephy(tp, 0x1c, 0x7c00);
2948 tg3_readphy(tp, 0x1c, &phy1);
2949
2950 /* Select expansion interrupt status register */
2951 tg3_writephy(tp, 0x17, 0x0f01);
2952 tg3_readphy(tp, 0x15, &phy2);
2953 tg3_readphy(tp, 0x15, &phy2);
2954
2955 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2956 /* We have signal detect and not receiving
2957 * config code words, link is up by parallel
2958 * detection.
2959 */
2960
2961 bmcr &= ~BMCR_ANENABLE;
2962 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2963 tg3_writephy(tp, MII_BMCR, bmcr);
2964 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2965 }
2966 }
2967 }
2968 else if (netif_carrier_ok(tp->dev) &&
2969 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2970 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2971 u32 phy2;
2972
2973 /* Select expansion interrupt status register */
2974 tg3_writephy(tp, 0x17, 0x0f01);
2975 tg3_readphy(tp, 0x15, &phy2);
2976 if (phy2 & 0x20) {
2977 u32 bmcr;
2978
2979 /* Config code words received, turn on autoneg. */
2980 tg3_readphy(tp, MII_BMCR, &bmcr);
2981 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2982
2983 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2984
2985 }
2986 }
2987}
2988
1da177e4
LT		 2989static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2990{
2991 int err;
2992
2993 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2994 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2995 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2996 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2997 } else {
2998 err = tg3_setup_copper_phy(tp, force_reset);
2999 }
3000
3001 if (tp->link_config.active_speed == SPEED_1000 &&
3002 tp->link_config.active_duplex == DUPLEX_HALF)
3003 tw32(MAC_TX_LENGTHS,
3004 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3005 (6 << TX_LENGTHS_IPG_SHIFT) |
3006 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3007 else
3008 tw32(MAC_TX_LENGTHS,
3009 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3010 (6 << TX_LENGTHS_IPG_SHIFT) |
3011 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3012
3013 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3014 if (netif_carrier_ok(tp->dev)) {
3015 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3016 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3017 } else {
3018 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3019 }
3020 }
3021
3022 return err;
3023}
3024
df3e6548
MC		 3025/* This is called whenever we suspect that the system chipset is re-
3026 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3027 * is bogus tx completions. We try to recover by setting the
3028 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3029 * in the workqueue.
3030 */
3031static void tg3_tx_recover(struct tg3 *tp)
3032{
3033 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3034 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3035
3036 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3037 "mapped I/O cycles to the network device, attempting to "
3038 "recover. Please report the problem to the driver maintainer "
3039 "and include system chipset information.\n", tp->dev->name);
3040
3041 spin_lock(&tp->lock);
df3e6548 3042 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3043 spin_unlock(&tp->lock);
3044}
3045
1b2a7205
MC		 3046static inline u32 tg3_tx_avail(struct tg3 *tp)
3047{
3048 smp_mb();
3049 return (tp->tx_pending -
3050 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3051}
3052
1da177e4
LT		 3053/* Tigon3 never reports partial packet sends. So we do not
3054 * need special logic to handle SKBs that have not had all
3055 * of their frags sent yet, like SunGEM does.
3056 */
3057static void tg3_tx(struct tg3 *tp)
3058{
3059 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3060 u32 sw_idx = tp->tx_cons;
3061
3062 while (sw_idx != hw_idx) {
3063 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3064 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3065 int i, tx_bug = 0;
3066
3067 if (unlikely(skb == NULL)) {
3068 tg3_tx_recover(tp);
3069 return;
3070 }
1da177e4 3071
1da177e4
LT		 3072 pci_unmap_single(tp->pdev,
3073 pci_unmap_addr(ri, mapping),
3074 skb_headlen(skb),
3075 PCI_DMA_TODEVICE);
3076
3077 ri->skb = NULL;
3078
3079 sw_idx = NEXT_TX(sw_idx);
3080
3081 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3082 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3083 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3084 tx_bug = 1;
1da177e4
LT		 3085
3086 pci_unmap_page(tp->pdev,
3087 pci_unmap_addr(ri, mapping),
3088 skb_shinfo(skb)->frags[i].size,
3089 PCI_DMA_TODEVICE);
3090
3091 sw_idx = NEXT_TX(sw_idx);
3092 }
3093
f47c11ee 3094 dev_kfree_skb(skb);
df3e6548
MC		 3095
3096 if (unlikely(tx_bug)) {
3097 tg3_tx_recover(tp);
3098 return;
3099 }
1da177e4
LT		 3100 }
3101
3102 tp->tx_cons = sw_idx;
3103
1b2a7205
MC		 3104 /* Need to make the tx_cons update visible to tg3_start_xmit()
3105 * before checking for netif_queue_stopped(). Without the
3106 * memory barrier, there is a small possibility that tg3_start_xmit()
3107 * will miss it and cause the queue to be stopped forever.
3108 */
3109 smp_mb();
3110
3111 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3112 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3113 netif_tx_lock(tp->dev);
51b91468 3114 if (netif_queue_stopped(tp->dev) &&
42952231 3115 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3116 netif_wake_queue(tp->dev);
1b2a7205 3117 netif_tx_unlock(tp->dev);
51b91468 3118 }
1da177e4
LT		 3119}
3120
3121/* Returns size of skb allocated or < 0 on error.
3122 *
3123 * We only need to fill in the address because the other members
3124 * of the RX descriptor are invariant, see tg3_init_rings.
3125 *
3126 * Note the purposeful assymetry of cpu vs. chip accesses. For
3127 * posting buffers we only dirty the first cache line of the RX
3128 * descriptor (containing the address). Whereas for the RX status
3129 * buffers the cpu only reads the last cacheline of the RX descriptor
3130 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3131 */
3132static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3133 int src_idx, u32 dest_idx_unmasked)
3134{
3135 struct tg3_rx_buffer_desc *desc;
3136 struct ring_info *map, *src_map;
3137 struct sk_buff *skb;
3138 dma_addr_t mapping;
3139 int skb_size, dest_idx;
3140
3141 src_map = NULL;
3142 switch (opaque_key) {
3143 case RXD_OPAQUE_RING_STD:
3144 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3145 desc = &tp->rx_std[dest_idx];
3146 map = &tp->rx_std_buffers[dest_idx];
3147 if (src_idx >= 0)
3148 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3149 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3150 break;
3151
3152 case RXD_OPAQUE_RING_JUMBO:
3153 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3154 desc = &tp->rx_jumbo[dest_idx];
3155 map = &tp->rx_jumbo_buffers[dest_idx];
3156 if (src_idx >= 0)
3157 src_map = &tp->rx_jumbo_buffers[src_idx];
3158 skb_size = RX_JUMBO_PKT_BUF_SZ;
3159 break;
3160
3161 default:
3162 return -EINVAL;
3163 };
3164
3165 /* Do not overwrite any of the map or rp information
3166 * until we are sure we can commit to a new buffer.
3167 *
3168 * Callers depend upon this behavior and assume that
3169 * we leave everything unchanged if we fail.
3170 */
a20e9c62 3171 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3172 if (skb == NULL)
3173 return -ENOMEM;
3174
1da177e4
LT		 3175 skb_reserve(skb, tp->rx_offset);
3176
3177 mapping = pci_map_single(tp->pdev, skb->data,
3178 skb_size - tp->rx_offset,
3179 PCI_DMA_FROMDEVICE);
3180
3181 map->skb = skb;
3182 pci_unmap_addr_set(map, mapping, mapping);
3183
3184 if (src_map != NULL)
3185 src_map->skb = NULL;
3186
3187 desc->addr_hi = ((u64)mapping >> 32);
3188 desc->addr_lo = ((u64)mapping & 0xffffffff);
3189
3190 return skb_size;
3191}
3192
3193/* We only need to move over in the address because the other
3194 * members of the RX descriptor are invariant. See notes above
3195 * tg3_alloc_rx_skb for full details.
3196 */
3197static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3198 int src_idx, u32 dest_idx_unmasked)
3199{
3200 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3201 struct ring_info *src_map, *dest_map;
3202 int dest_idx;
3203
3204 switch (opaque_key) {
3205 case RXD_OPAQUE_RING_STD:
3206 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3207 dest_desc = &tp->rx_std[dest_idx];
3208 dest_map = &tp->rx_std_buffers[dest_idx];
3209 src_desc = &tp->rx_std[src_idx];
3210 src_map = &tp->rx_std_buffers[src_idx];
3211 break;
3212
3213 case RXD_OPAQUE_RING_JUMBO:
3214 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3215 dest_desc = &tp->rx_jumbo[dest_idx];
3216 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3217 src_desc = &tp->rx_jumbo[src_idx];
3218 src_map = &tp->rx_jumbo_buffers[src_idx];
3219 break;
3220
3221 default:
3222 return;
3223 };
3224
3225 dest_map->skb = src_map->skb;
3226 pci_unmap_addr_set(dest_map, mapping,
3227 pci_unmap_addr(src_map, mapping));
3228 dest_desc->addr_hi = src_desc->addr_hi;
3229 dest_desc->addr_lo = src_desc->addr_lo;
3230
3231 src_map->skb = NULL;
3232}
3233
3234#if TG3_VLAN_TAG_USED
3235static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3236{
3237 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3238}
3239#endif
3240
3241/* The RX ring scheme is composed of multiple rings which post fresh
3242 * buffers to the chip, and one special ring the chip uses to report
3243 * status back to the host.
3244 *
3245 * The special ring reports the status of received packets to the
3246 * host. The chip does not write into the original descriptor the
3247 * RX buffer was obtained from. The chip simply takes the original
3248 * descriptor as provided by the host, updates the status and length
3249 * field, then writes this into the next status ring entry.
3250 *
3251 * Each ring the host uses to post buffers to the chip is described
3252 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3253 * it is first placed into the on-chip ram. When the packet's length
3254 * is known, it walks down the TG3_BDINFO entries to select the ring.
3255 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3256 * which is within the range of the new packet's length is chosen.
3257 *
3258 * The "separate ring for rx status" scheme may sound queer, but it makes
3259 * sense from a cache coherency perspective. If only the host writes
3260 * to the buffer post rings, and only the chip writes to the rx status
3261 * rings, then cache lines never move beyond shared-modified state.
3262 * If both the host and chip were to write into the same ring, cache line
3263 * eviction could occur since both entities want it in an exclusive state.
3264 */
3265static int tg3_rx(struct tg3 *tp, int budget)
3266{
f92905de 3267 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3268 u32 sw_idx = tp->rx_rcb_ptr;
3269 u16 hw_idx;
1da177e4
LT		 3270 int received;
3271
3272 hw_idx = tp->hw_status->idx[0].rx_producer;
3273 /*
3274 * We need to order the read of hw_idx and the read of
3275 * the opaque cookie.
3276 */
3277 rmb();
1da177e4
LT		 3278 work_mask = 0;
3279 received = 0;
3280 while (sw_idx != hw_idx && budget > 0) {
3281 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3282 unsigned int len;
3283 struct sk_buff *skb;
3284 dma_addr_t dma_addr;
3285 u32 opaque_key, desc_idx, *post_ptr;
3286
3287 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3288 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3289 if (opaque_key == RXD_OPAQUE_RING_STD) {
3290 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3291 mapping);
3292 skb = tp->rx_std_buffers[desc_idx].skb;
3293 post_ptr = &tp->rx_std_ptr;
f92905de 3294 rx_std_posted++;
1da177e4
LT		 3295 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3296 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3297 mapping);
3298 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3299 post_ptr = &tp->rx_jumbo_ptr;
3300 }
3301 else {
3302 goto next_pkt_nopost;
3303 }
3304
3305 work_mask |= opaque_key;
3306
3307 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3308 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3309 drop_it:
3310 tg3_recycle_rx(tp, opaque_key,
3311 desc_idx, *post_ptr);
3312 drop_it_no_recycle:
3313 /* Other statistics kept track of by card. */
3314 tp->net_stats.rx_dropped++;
3315 goto next_pkt;
3316 }
3317
3318 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3319
6aa20a22 3320 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3321 && tp->rx_offset == 2
3322 /* rx_offset != 2 iff this is a 5701 card running
3323 * in PCI-X mode [see tg3_get_invariants()] */
3324 ) {
3325 int skb_size;
3326
3327 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3328 desc_idx, *post_ptr);
3329 if (skb_size < 0)
3330 goto drop_it;
3331
3332 pci_unmap_single(tp->pdev, dma_addr,
3333 skb_size - tp->rx_offset,
3334 PCI_DMA_FROMDEVICE);
3335
3336 skb_put(skb, len);
3337 } else {
3338 struct sk_buff *copy_skb;
3339
3340 tg3_recycle_rx(tp, opaque_key,
3341 desc_idx, *post_ptr);
3342
a20e9c62 3343 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3344 if (copy_skb == NULL)
3345 goto drop_it_no_recycle;
3346
1da177e4
LT		 3347 skb_reserve(copy_skb, 2);
3348 skb_put(copy_skb, len);
3349 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 3350 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 3351 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3352
3353 /* We'll reuse the original ring buffer. */
3354 skb = copy_skb;
3355 }
3356
3357 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3358 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3359 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3360 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3361 skb->ip_summed = CHECKSUM_UNNECESSARY;
3362 else
3363 skb->ip_summed = CHECKSUM_NONE;
3364
3365 skb->protocol = eth_type_trans(skb, tp->dev);
3366#if TG3_VLAN_TAG_USED
3367 if (tp->vlgrp != NULL &&
3368 desc->type_flags & RXD_FLAG_VLAN) {
3369 tg3_vlan_rx(tp, skb,
3370 desc->err_vlan & RXD_VLAN_MASK);
3371 } else
3372#endif
3373 netif_receive_skb(skb);
3374
3375 tp->dev->last_rx = jiffies;
3376 received++;
3377 budget--;
3378
3379next_pkt:
3380 (*post_ptr)++;
f92905de
MC		 3381
3382 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3383 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3384
3385 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3386 TG3_64BIT_REG_LOW, idx);
3387 work_mask &= ~RXD_OPAQUE_RING_STD;
3388 rx_std_posted = 0;
3389 }
1da177e4 3390next_pkt_nopost:
483ba50b 3391 sw_idx++;
6b31a515 3392 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3393
3394 /* Refresh hw_idx to see if there is new work */
3395 if (sw_idx == hw_idx) {
3396 hw_idx = tp->hw_status->idx[0].rx_producer;
3397 rmb();
3398 }
1da177e4
LT		 3399 }
3400
3401 /* ACK the status ring. */
483ba50b
MC		 3402 tp->rx_rcb_ptr = sw_idx;
3403 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3404
3405 /* Refill RX ring(s). */
3406 if (work_mask & RXD_OPAQUE_RING_STD) {
3407 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3408 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3409 sw_idx);
3410 }
3411 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3412 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3413 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3414 sw_idx);
3415 }
3416 mmiowb();
3417
3418 return received;
3419}
3420
3421static int tg3_poll(struct net_device *netdev, int *budget)
3422{
3423 struct tg3 *tp = netdev_priv(netdev);
3424 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3425 int done;
3426
1da177e4
LT		 3427 /* handle link change and other phy events */
3428 if (!(tp->tg3_flags &
3429 (TG3_FLAG_USE_LINKCHG_REG |
3430 TG3_FLAG_POLL_SERDES))) {
3431 if (sblk->status & SD_STATUS_LINK_CHG) {
3432 sblk->status = SD_STATUS_UPDATED |
3433 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3434 spin_lock(&tp->lock);
1da177e4 3435 tg3_setup_phy(tp, 0);
f47c11ee 3436 spin_unlock(&tp->lock);
1da177e4
LT		 3437 }
3438 }
3439
3440 /* run TX completion thread */
3441 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3442 tg3_tx(tp);
df3e6548
MC		 3443 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3444 netif_rx_complete(netdev);
3445 schedule_work(&tp->reset_task);
3446 return 0;
3447 }
1da177e4
LT		 3448 }
3449
1da177e4
LT		 3450 /* run RX thread, within the bounds set by NAPI.
3451 * All RX "locking" is done by ensuring outside
3452 * code synchronizes with dev->poll()
3453 */
1da177e4
LT		 3454 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3455 int orig_budget = *budget;
3456 int work_done;
3457
3458 if (orig_budget > netdev->quota)
3459 orig_budget = netdev->quota;
3460
3461 work_done = tg3_rx(tp, orig_budget);
3462
3463 *budget -= work_done;
3464 netdev->quota -= work_done;
1da177e4
LT		 3465 }
3466
38f3843e 3467 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3468 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3469 rmb();
3470 } else
3471 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3472
1da177e4 3473 /* if no more work, tell net stack and NIC we're done */
f7383c22 3474 done = !tg3_has_work(tp);
1da177e4 3475 if (done) {
f47c11ee 3476 netif_rx_complete(netdev);
1da177e4 3477 tg3_restart_ints(tp);
1da177e4
LT		 3478 }
3479
3480 return (done ? 0 : 1);
3481}
3482
f47c11ee
DM		 3483static void tg3_irq_quiesce(struct tg3 *tp)
3484{
3485 BUG_ON(tp->irq_sync);
3486
3487 tp->irq_sync = 1;
3488 smp_mb();
3489
3490 synchronize_irq(tp->pdev->irq);
3491}
3492
3493static inline int tg3_irq_sync(struct tg3 *tp)
3494{
3495 return tp->irq_sync;
3496}
3497
3498/* Fully shutdown all tg3 driver activity elsewhere in the system.
3499 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3500 * with as well. Most of the time, this is not necessary except when
3501 * shutting down the device.
3502 */
3503static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3504{
3505 if (irq_sync)
3506 tg3_irq_quiesce(tp);
3507 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3508}
3509
3510static inline void tg3_full_unlock(struct tg3 *tp)
3511{
f47c11ee
DM		 3512 spin_unlock_bh(&tp->lock);
3513}
3514
fcfa0a32
MC		 3515/* One-shot MSI handler - Chip automatically disables interrupt
3516 * after sending MSI so driver doesn't have to do it.
3517 */
7d12e780 3518static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3519{
3520 struct net_device *dev = dev_id;
3521 struct tg3 *tp = netdev_priv(dev);
3522
3523 prefetch(tp->hw_status);
3524 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3525
3526 if (likely(!tg3_irq_sync(tp)))
3527 netif_rx_schedule(dev); /* schedule NAPI poll */
3528
3529 return IRQ_HANDLED;
3530}
3531
88b06bc2
MC		 3532/* MSI ISR - No need to check for interrupt sharing and no need to
3533 * flush status block and interrupt mailbox. PCI ordering rules
3534 * guarantee that MSI will arrive after the status block.
3535 */
7d12e780 3536static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3537{
3538 struct net_device *dev = dev_id;
3539 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3540
61487480
MC		 3541 prefetch(tp->hw_status);
3542 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3543 /*
fac9b83e 3544 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3545 * chip-internal interrupt pending events.
fac9b83e 3546 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3547 * NIC to stop sending us irqs, engaging "in-intr-handler"
3548 * event coalescing.
3549 */
3550 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3551 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3552 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3553
88b06bc2
MC		 3554 return IRQ_RETVAL(1);
3555}
3556
7d12e780 3557static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3558{
3559 struct net_device *dev = dev_id;
3560 struct tg3 *tp = netdev_priv(dev);
3561 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3562 unsigned int handled = 1;
3563
1da177e4
LT		 3564 /* In INTx mode, it is possible for the interrupt to arrive at
3565 * the CPU before the status block posted prior to the interrupt.
3566 * Reading the PCI State register will confirm whether the
3567 * interrupt is ours and will flush the status block.
3568 */
d18edcb2
MC		 3569 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3570 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3571 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3572 handled = 0;
f47c11ee 3573 goto out;
fac9b83e 3574 }
d18edcb2
MC		 3575 }
3576
3577 /*
3578 * Writing any value to intr-mbox-0 clears PCI INTA# and
3579 * chip-internal interrupt pending events.
3580 * Writing non-zero to intr-mbox-0 additional tells the
3581 * NIC to stop sending us irqs, engaging "in-intr-handler"
3582 * event coalescing.
3583 */
3584 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3585 if (tg3_irq_sync(tp))
3586 goto out;
3587 sblk->status &= ~SD_STATUS_UPDATED;
3588 if (likely(tg3_has_work(tp))) {
3589 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3590 netif_rx_schedule(dev); /* schedule NAPI poll */
3591 } else {
3592 /* No work, shared interrupt perhaps? re-enable
3593 * interrupts, and flush that PCI write
3594 */
3595 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3596 0x00000000);
fac9b83e 3597 }
f47c11ee 3598out:
fac9b83e
DM		 3599 return IRQ_RETVAL(handled);
3600}
3601
7d12e780 3602static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3603{
3604 struct net_device *dev = dev_id;
3605 struct tg3 *tp = netdev_priv(dev);
3606 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3607 unsigned int handled = 1;
3608
fac9b83e
DM		 3609 /* In INTx mode, it is possible for the interrupt to arrive at
3610 * the CPU before the status block posted prior to the interrupt.
3611 * Reading the PCI State register will confirm whether the
3612 * interrupt is ours and will flush the status block.
3613 */
d18edcb2
MC		 3614 if (unlikely(sblk->status_tag == tp->last_tag)) {
3615 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3616 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3617 handled = 0;
f47c11ee 3618 goto out;
1da177e4 3619 }
d18edcb2
MC		 3620 }
3621
3622 /*
3623 * writing any value to intr-mbox-0 clears PCI INTA# and
3624 * chip-internal interrupt pending events.
3625 * writing non-zero to intr-mbox-0 additional tells the
3626 * NIC to stop sending us irqs, engaging "in-intr-handler"
3627 * event coalescing.
3628 */
3629 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3630 if (tg3_irq_sync(tp))
3631 goto out;
3632 if (netif_rx_schedule_prep(dev)) {
3633 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3634 /* Update last_tag to mark that this status has been
3635 * seen. Because interrupt may be shared, we may be
3636 * racing with tg3_poll(), so only update last_tag
3637 * if tg3_poll() is not scheduled.
3638 */
3639 tp->last_tag = sblk->status_tag;
3640 __netif_rx_schedule(dev);
1da177e4 3641 }
f47c11ee 3642out:
1da177e4
LT		 3643 return IRQ_RETVAL(handled);
3644}
3645
7938109f 3646/* ISR for interrupt test */
7d12e780 3647static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3648{
3649 struct net_device *dev = dev_id;
3650 struct tg3 *tp = netdev_priv(dev);
3651 struct tg3_hw_status *sblk = tp->hw_status;
3652
f9804ddb
MC		 3653 if ((sblk->status & SD_STATUS_UPDATED) ||
3654 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3655 tg3_disable_ints(tp);
7938109f
MC		 3656 return IRQ_RETVAL(1);
3657 }
3658 return IRQ_RETVAL(0);
3659}
3660
8e7a22e3 3661static int tg3_init_hw(struct tg3 *, int);
944d980e 3662static int tg3_halt(struct tg3 *, int, int);
1da177e4 3663
b9ec6c1b
MC		 3664/* Restart hardware after configuration changes, self-test, etc.
3665 * Invoked with tp->lock held.
3666 */
3667static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3668{
3669 int err;
3670
3671 err = tg3_init_hw(tp, reset_phy);
3672 if (err) {
3673 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3674 "aborting.\n", tp->dev->name);
3675 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3676 tg3_full_unlock(tp);
3677 del_timer_sync(&tp->timer);
3678 tp->irq_sync = 0;
3679 netif_poll_enable(tp->dev);
3680 dev_close(tp->dev);
3681 tg3_full_lock(tp, 0);
3682 }
3683 return err;
3684}
3685
1da177e4
LT		 3686#ifdef CONFIG_NET_POLL_CONTROLLER
3687static void tg3_poll_controller(struct net_device *dev)
3688{
88b06bc2
MC		 3689 struct tg3 *tp = netdev_priv(dev);
3690
7d12e780 3691 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3692}
3693#endif
3694
c4028958 3695static void tg3_reset_task(struct work_struct *work)
1da177e4 3696{
c4028958 3697 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3698 unsigned int restart_timer;
3699
7faa006f
MC		 3700 tg3_full_lock(tp, 0);
3701 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3702
3703 if (!netif_running(tp->dev)) {
3704 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3705 tg3_full_unlock(tp);
3706 return;
3707 }
3708
3709 tg3_full_unlock(tp);
3710
1da177e4
LT		 3711 tg3_netif_stop(tp);
3712
f47c11ee 3713 tg3_full_lock(tp, 1);
1da177e4
LT		 3714
3715 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3716 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3717
df3e6548
MC		 3718 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3719 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3720 tp->write32_rx_mbox = tg3_write_flush_reg32;
3721 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3722 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3723 }
3724
944d980e 3725 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3726 if (tg3_init_hw(tp, 1))
3727 goto out;
1da177e4
LT		 3728
3729 tg3_netif_start(tp);
3730
1da177e4
LT		 3731 if (restart_timer)
3732 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3733
b9ec6c1b 3734out:
7faa006f
MC		 3735 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3736
3737 tg3_full_unlock(tp);
1da177e4
LT		 3738}
3739
b0408751
MC		 3740static void tg3_dump_short_state(struct tg3 *tp)
3741{
3742 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3743 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3744 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3745 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3746}
3747
1da177e4
LT		 3748static void tg3_tx_timeout(struct net_device *dev)
3749{
3750 struct tg3 *tp = netdev_priv(dev);
3751
b0408751 3752 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 3753 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3754 dev->name);
b0408751
MC		 3755 tg3_dump_short_state(tp);
3756 }
1da177e4
LT		 3757
3758 schedule_work(&tp->reset_task);
3759}
3760
c58ec932
MC		 3761/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3762static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3763{
3764 u32 base = (u32) mapping & 0xffffffff;
3765
3766 return ((base > 0xffffdcc0) &&
3767 (base + len + 8 < base));
3768}
3769
72f2afb8
MC		 3770/* Test for DMA addresses > 40-bit */
3771static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3772 int len)
3773{
3774#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3775 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3776 return (((u64) mapping + len) > DMA_40BIT_MASK);
3777 return 0;
3778#else
3779 return 0;
3780#endif
3781}
3782
1da177e4
LT		 3783static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3784
72f2afb8
MC		 3785/* Workaround 4GB and 40-bit hardware DMA bugs. */
3786static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3787 u32 last_plus_one, u32 *start,
3788 u32 base_flags, u32 mss)
1da177e4
LT		 3789{
3790 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3791 dma_addr_t new_addr = 0;
1da177e4 3792 u32 entry = *start;
c58ec932 3793 int i, ret = 0;
1da177e4
LT		 3794
3795 if (!new_skb) {
c58ec932
MC		 3796 ret = -1;
3797 } else {
3798 /* New SKB is guaranteed to be linear. */
3799 entry = *start;
3800 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3801 PCI_DMA_TODEVICE);
3802 /* Make sure new skb does not cross any 4G boundaries.
3803 * Drop the packet if it does.
3804 */
3805 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3806 ret = -1;
3807 dev_kfree_skb(new_skb);
3808 new_skb = NULL;
3809 } else {
3810 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3811 base_flags, 1 | (mss << 1));
3812 *start = NEXT_TX(entry);
3813 }
1da177e4
LT		 3814 }
3815
1da177e4
LT		 3816 /* Now clean up the sw ring entries. */
3817 i = 0;
3818 while (entry != last_plus_one) {
3819 int len;
3820
3821 if (i == 0)
3822 len = skb_headlen(skb);
3823 else
3824 len = skb_shinfo(skb)->frags[i-1].size;
3825 pci_unmap_single(tp->pdev,
3826 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3827 len, PCI_DMA_TODEVICE);
3828 if (i == 0) {
3829 tp->tx_buffers[entry].skb = new_skb;
3830 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3831 } else {
3832 tp->tx_buffers[entry].skb = NULL;
3833 }
3834 entry = NEXT_TX(entry);
3835 i++;
3836 }
3837
3838 dev_kfree_skb(skb);
3839
c58ec932 3840 return ret;
1da177e4
LT		 3841}
3842
3843static void tg3_set_txd(struct tg3 *tp, int entry,
3844 dma_addr_t mapping, int len, u32 flags,
3845 u32 mss_and_is_end)
3846{
3847 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3848 int is_end = (mss_and_is_end & 0x1);
3849 u32 mss = (mss_and_is_end >> 1);
3850 u32 vlan_tag = 0;
3851
3852 if (is_end)
3853 flags |= TXD_FLAG_END;
3854 if (flags & TXD_FLAG_VLAN) {
3855 vlan_tag = flags >> 16;
3856 flags &= 0xffff;
3857 }
3858 vlan_tag |= (mss << TXD_MSS_SHIFT);
3859
3860 txd->addr_hi = ((u64) mapping >> 32);
3861 txd->addr_lo = ((u64) mapping & 0xffffffff);
3862 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3863 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3864}
3865
5a6f3074
MC		 3866/* hard_start_xmit for devices that don't have any bugs and
3867 * support TG3_FLG2_HW_TSO_2 only.
3868 */
1da177e4 3869static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 3870{
3871 struct tg3 *tp = netdev_priv(dev);
3872 dma_addr_t mapping;
3873 u32 len, entry, base_flags, mss;
3874
3875 len = skb_headlen(skb);
3876
00b70504
MC		 3877 /* We are running in BH disabled context with netif_tx_lock
3878 * and TX reclaim runs via tp->poll inside of a software
5a6f3074
MC		 3879 * interrupt. Furthermore, IRQ processing runs lockless so we have
3880 * no IRQ context deadlocks to worry about either. Rejoice!
3881 */
1b2a7205 3882 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 3883 if (!netif_queue_stopped(dev)) {
3884 netif_stop_queue(dev);
3885
3886 /* This is a hard error, log it. */
3887 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3888 "queue awake!\n", dev->name);
3889 }
5a6f3074
MC		 3890 return NETDEV_TX_BUSY;
3891 }
3892
3893 entry = tp->tx_prod;
3894 base_flags = 0;
5a6f3074 3895 mss = 0;
c13e3713 3896 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 3897 int tcp_opt_len, ip_tcp_len;
3898
3899 if (skb_header_cloned(skb) &&
3900 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3901 dev_kfree_skb(skb);
3902 goto out_unlock;
3903 }
3904
b0026624
MC		 3905 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3906 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3907 else {
eddc9ec5
ACM		 3908 struct iphdr *iph = ip_hdr(skb);
3909
ab6a5bb6 3910 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 3911 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 3912
eddc9ec5
ACM		 3913 iph->check = 0;
3914 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 3915 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3916 }
5a6f3074
MC		 3917
3918 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3919 TXD_FLAG_CPU_POST_DMA);
3920
aa8223c7 3921 tcp_hdr(skb)->check = 0;
5a6f3074 3922
5a6f3074 3923 }
84fa7933 3924 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 3925 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 3926#if TG3_VLAN_TAG_USED
3927 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3928 base_flags |= (TXD_FLAG_VLAN |
3929 (vlan_tx_tag_get(skb) << 16));
3930#endif
3931
3932 /* Queue skb data, a.k.a. the main skb fragment. */
3933 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3934
3935 tp->tx_buffers[entry].skb = skb;
3936 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3937
3938 tg3_set_txd(tp, entry, mapping, len, base_flags,
3939 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3940
3941 entry = NEXT_TX(entry);
3942
3943 /* Now loop through additional data fragments, and queue them. */
3944 if (skb_shinfo(skb)->nr_frags > 0) {
3945 unsigned int i, last;
3946
3947 last = skb_shinfo(skb)->nr_frags - 1;
3948 for (i = 0; i <= last; i++) {
3949 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3950
3951 len = frag->size;
3952 mapping = pci_map_page(tp->pdev,
3953 frag->page,
3954 frag->page_offset,
3955 len, PCI_DMA_TODEVICE);
3956
3957 tp->tx_buffers[entry].skb = NULL;
3958 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3959
3960 tg3_set_txd(tp, entry, mapping, len,
3961 base_flags, (i == last) | (mss << 1));
3962
3963 entry = NEXT_TX(entry);
3964 }
3965 }
3966
3967 /* Packets are ready, update Tx producer idx local and on card. */
3968 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3969
3970 tp->tx_prod = entry;
1b2a7205 3971 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 3972 netif_stop_queue(dev);
42952231 3973 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 3974 netif_wake_queue(tp->dev);
3975 }
3976
3977out_unlock:
3978 mmiowb();
5a6f3074
MC		 3979
3980 dev->trans_start = jiffies;
3981
3982 return NETDEV_TX_OK;
3983}
3984
52c0fd83
MC		 3985static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3986
3987/* Use GSO to workaround a rare TSO bug that may be triggered when the
3988 * TSO header is greater than 80 bytes.
3989 */
3990static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3991{
3992 struct sk_buff *segs, *nskb;
3993
3994 /* Estimate the number of fragments in the worst case */
1b2a7205 3995 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 3996 netif_stop_queue(tp->dev);
7f62ad5d
MC		 3997 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
3998 return NETDEV_TX_BUSY;
3999
4000 netif_wake_queue(tp->dev);
52c0fd83
MC		 4001 }
4002
4003 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4004 if (unlikely(IS_ERR(segs)))
4005 goto tg3_tso_bug_end;
4006
4007 do {
4008 nskb = segs;
4009 segs = segs->next;
4010 nskb->next = NULL;
4011 tg3_start_xmit_dma_bug(nskb, tp->dev);
4012 } while (segs);
4013
4014tg3_tso_bug_end:
4015 dev_kfree_skb(skb);
4016
4017 return NETDEV_TX_OK;
4018}
52c0fd83 4019
5a6f3074
MC		 4020/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4021 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4022 */
4023static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4024{
4025 struct tg3 *tp = netdev_priv(dev);
4026 dma_addr_t mapping;
1da177e4
LT		 4027 u32 len, entry, base_flags, mss;
4028 int would_hit_hwbug;
1da177e4
LT		 4029
4030 len = skb_headlen(skb);
4031
00b70504
MC		 4032 /* We are running in BH disabled context with netif_tx_lock
4033 * and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 4034 * interrupt. Furthermore, IRQ processing runs lockless so we have
4035 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4036 */
1b2a7205 4037 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4038 if (!netif_queue_stopped(dev)) {
4039 netif_stop_queue(dev);
4040
4041 /* This is a hard error, log it. */
4042 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4043 "queue awake!\n", dev->name);
4044 }
1da177e4
LT		 4045 return NETDEV_TX_BUSY;
4046 }
4047
4048 entry = tp->tx_prod;
4049 base_flags = 0;
84fa7933 4050 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4051 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 4052 mss = 0;
c13e3713 4053 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 4054 struct iphdr *iph;
52c0fd83 4055 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4056
4057 if (skb_header_cloned(skb) &&
4058 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4059 dev_kfree_skb(skb);
4060 goto out_unlock;
4061 }
4062
ab6a5bb6 4063 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4064 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 4065
52c0fd83
MC		 4066 hdr_len = ip_tcp_len + tcp_opt_len;
4067 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 4068 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 4069 return (tg3_tso_bug(tp, skb));
4070
1da177e4
LT		 4071 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4072 TXD_FLAG_CPU_POST_DMA);
4073
eddc9ec5
ACM		 4074 iph = ip_hdr(skb);
4075 iph->check = 0;
4076 iph->tot_len = htons(mss + hdr_len);
1da177e4 4077 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 4078 tcp_hdr(skb)->check = 0;
1da177e4 4079 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 4080 } else
4081 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4082 iph->daddr, 0,
4083 IPPROTO_TCP,
4084 0);
1da177e4
LT		 4085
4086 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4087 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 4088 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4089 int tsflags;
4090
eddc9ec5 4091 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4092 mss |= (tsflags << 11);
4093 }
4094 } else {
eddc9ec5 4095 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4096 int tsflags;
4097
eddc9ec5 4098 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4099 base_flags |= tsflags << 12;
4100 }
4101 }
4102 }
1da177e4
LT		 4103#if TG3_VLAN_TAG_USED
4104 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4105 base_flags |= (TXD_FLAG_VLAN |
4106 (vlan_tx_tag_get(skb) << 16));
4107#endif
4108
4109 /* Queue skb data, a.k.a. the main skb fragment. */
4110 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4111
4112 tp->tx_buffers[entry].skb = skb;
4113 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4114
4115 would_hit_hwbug = 0;
4116
4117 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4118 would_hit_hwbug = 1;
1da177e4
LT		 4119
4120 tg3_set_txd(tp, entry, mapping, len, base_flags,
4121 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4122
4123 entry = NEXT_TX(entry);
4124
4125 /* Now loop through additional data fragments, and queue them. */
4126 if (skb_shinfo(skb)->nr_frags > 0) {
4127 unsigned int i, last;
4128
4129 last = skb_shinfo(skb)->nr_frags - 1;
4130 for (i = 0; i <= last; i++) {
4131 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4132
4133 len = frag->size;
4134 mapping = pci_map_page(tp->pdev,
4135 frag->page,
4136 frag->page_offset,
4137 len, PCI_DMA_TODEVICE);
4138
4139 tp->tx_buffers[entry].skb = NULL;
4140 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4141
c58ec932
MC		 4142 if (tg3_4g_overflow_test(mapping, len))
4143 would_hit_hwbug = 1;
1da177e4 4144
72f2afb8
MC		 4145 if (tg3_40bit_overflow_test(tp, mapping, len))
4146 would_hit_hwbug = 1;
4147
1da177e4
LT		 4148 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4149 tg3_set_txd(tp, entry, mapping, len,
4150 base_flags, (i == last)|(mss << 1));
4151 else
4152 tg3_set_txd(tp, entry, mapping, len,
4153 base_flags, (i == last));
4154
4155 entry = NEXT_TX(entry);
4156 }
4157 }
4158
4159 if (would_hit_hwbug) {
4160 u32 last_plus_one = entry;
4161 u32 start;
1da177e4 4162
c58ec932
MC		 4163 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4164 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4165
4166 /* If the workaround fails due to memory/mapping
4167 * failure, silently drop this packet.
4168 */
72f2afb8 4169 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4170 &start, base_flags, mss))
1da177e4
LT		 4171 goto out_unlock;
4172
4173 entry = start;
4174 }
4175
4176 /* Packets are ready, update Tx producer idx local and on card. */
4177 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4178
4179 tp->tx_prod = entry;
1b2a7205 4180 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4181 netif_stop_queue(dev);
42952231 4182 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4183 netif_wake_queue(tp->dev);
4184 }
1da177e4
LT		 4185
4186out_unlock:
4187 mmiowb();
1da177e4
LT		 4188
4189 dev->trans_start = jiffies;
4190
4191 return NETDEV_TX_OK;
4192}
4193
4194static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4195 int new_mtu)
4196{
4197 dev->mtu = new_mtu;
4198
ef7f5ec0 4199 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4200 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4201 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4202 ethtool_op_set_tso(dev, 0);
4203 }
4204 else
4205 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4206 } else {
a4e2b347 4207 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4208 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4209 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4210 }
1da177e4
LT		 4211}
4212
4213static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4214{
4215 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4216 int err;
1da177e4
LT		 4217
4218 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4219 return -EINVAL;
4220
4221 if (!netif_running(dev)) {
4222 /* We'll just catch it later when the
4223 * device is up'd.
4224 */
4225 tg3_set_mtu(dev, tp, new_mtu);
4226 return 0;
4227 }
4228
4229 tg3_netif_stop(tp);
f47c11ee
DM		 4230
4231 tg3_full_lock(tp, 1);
1da177e4 4232
944d980e 4233 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4234
4235 tg3_set_mtu(dev, tp, new_mtu);
4236
b9ec6c1b 4237 err = tg3_restart_hw(tp, 0);
1da177e4 4238
b9ec6c1b
MC		 4239 if (!err)
4240 tg3_netif_start(tp);
1da177e4 4241
f47c11ee 4242 tg3_full_unlock(tp);
1da177e4 4243
b9ec6c1b 4244 return err;
1da177e4
LT		 4245}
4246
4247/* Free up pending packets in all rx/tx rings.
4248 *
4249 * The chip has been shut down and the driver detached from
4250 * the networking, so no interrupts or new tx packets will
4251 * end up in the driver. tp->{tx,}lock is not held and we are not
4252 * in an interrupt context and thus may sleep.
4253 */
4254static void tg3_free_rings(struct tg3 *tp)
4255{
4256 struct ring_info *rxp;
4257 int i;
4258
4259 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4260 rxp = &tp->rx_std_buffers[i];
4261
4262 if (rxp->skb == NULL)
4263 continue;
4264 pci_unmap_single(tp->pdev,
4265 pci_unmap_addr(rxp, mapping),
7e72aad4 4266 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4267 PCI_DMA_FROMDEVICE);
4268 dev_kfree_skb_any(rxp->skb);
4269 rxp->skb = NULL;
4270 }
4271
4272 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4273 rxp = &tp->rx_jumbo_buffers[i];
4274
4275 if (rxp->skb == NULL)
4276 continue;
4277 pci_unmap_single(tp->pdev,
4278 pci_unmap_addr(rxp, mapping),
4279 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4280 PCI_DMA_FROMDEVICE);
4281 dev_kfree_skb_any(rxp->skb);
4282 rxp->skb = NULL;
4283 }
4284
4285 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4286 struct tx_ring_info *txp;
4287 struct sk_buff *skb;
4288 int j;
4289
4290 txp = &tp->tx_buffers[i];
4291 skb = txp->skb;
4292
4293 if (skb == NULL) {
4294 i++;
4295 continue;
4296 }
4297
4298 pci_unmap_single(tp->pdev,
4299 pci_unmap_addr(txp, mapping),
4300 skb_headlen(skb),
4301 PCI_DMA_TODEVICE);
4302 txp->skb = NULL;
4303
4304 i++;
4305
4306 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4307 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4308 pci_unmap_page(tp->pdev,
4309 pci_unmap_addr(txp, mapping),
4310 skb_shinfo(skb)->frags[j].size,
4311 PCI_DMA_TODEVICE);
4312 i++;
4313 }
4314
4315 dev_kfree_skb_any(skb);
4316 }
4317}
4318
4319/* Initialize tx/rx rings for packet processing.
4320 *
4321 * The chip has been shut down and the driver detached from
4322 * the networking, so no interrupts or new tx packets will
4323 * end up in the driver. tp->{tx,}lock are held and thus
4324 * we may not sleep.
4325 */
32d8c572 4326static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4327{
4328 u32 i;
4329
4330 /* Free up all the SKBs. */
4331 tg3_free_rings(tp);
4332
4333 /* Zero out all descriptors. */
4334 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4335 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4336 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4337 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4338
7e72aad4 4339 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4340 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4341 (tp->dev->mtu > ETH_DATA_LEN))
4342 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4343
1da177e4
LT		 4344 /* Initialize invariants of the rings, we only set this
4345 * stuff once. This works because the card does not
4346 * write into the rx buffer posting rings.
4347 */
4348 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4349 struct tg3_rx_buffer_desc *rxd;
4350
4351 rxd = &tp->rx_std[i];
7e72aad4 4352 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4353 << RXD_LEN_SHIFT;
4354 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4355 rxd->opaque = (RXD_OPAQUE_RING_STD |
4356 (i << RXD_OPAQUE_INDEX_SHIFT));
4357 }
4358
0f893dc6 4359 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4360 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4361 struct tg3_rx_buffer_desc *rxd;
4362
4363 rxd = &tp->rx_jumbo[i];
4364 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4365 << RXD_LEN_SHIFT;
4366 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4367 RXD_FLAG_JUMBO;
4368 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4369 (i << RXD_OPAQUE_INDEX_SHIFT));
4370 }
4371 }
4372
4373 /* Now allocate fresh SKBs for each rx ring. */
4374 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4375 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4376 printk(KERN_WARNING PFX
4377 "%s: Using a smaller RX standard ring, "
4378 "only %d out of %d buffers were allocated "
4379 "successfully.\n",
4380 tp->dev->name, i, tp->rx_pending);
4381 if (i == 0)
4382 return -ENOMEM;
4383 tp->rx_pending = i;
1da177e4 4384 break;
32d8c572 4385 }
1da177e4
LT		 4386 }
4387
0f893dc6 4388 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4389 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4390 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4391 -1, i) < 0) {
4392 printk(KERN_WARNING PFX
4393 "%s: Using a smaller RX jumbo ring, "
4394 "only %d out of %d buffers were "
4395 "allocated successfully.\n",
4396 tp->dev->name, i, tp->rx_jumbo_pending);
4397 if (i == 0) {
4398 tg3_free_rings(tp);
4399 return -ENOMEM;
4400 }
4401 tp->rx_jumbo_pending = i;
1da177e4 4402 break;
32d8c572 4403 }
1da177e4
LT		 4404 }
4405 }
32d8c572 4406 return 0;
1da177e4
LT		 4407}
4408
4409/*
4410 * Must not be invoked with interrupt sources disabled and
4411 * the hardware shutdown down.
4412 */
4413static void tg3_free_consistent(struct tg3 *tp)
4414{
b4558ea9
JJ		 4415 kfree(tp->rx_std_buffers);
4416 tp->rx_std_buffers = NULL;
1da177e4
LT		 4417 if (tp->rx_std) {
4418 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4419 tp->rx_std, tp->rx_std_mapping);
4420 tp->rx_std = NULL;
4421 }
4422 if (tp->rx_jumbo) {
4423 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4424 tp->rx_jumbo, tp->rx_jumbo_mapping);
4425 tp->rx_jumbo = NULL;
4426 }
4427 if (tp->rx_rcb) {
4428 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4429 tp->rx_rcb, tp->rx_rcb_mapping);
4430 tp->rx_rcb = NULL;
4431 }
4432 if (tp->tx_ring) {
4433 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4434 tp->tx_ring, tp->tx_desc_mapping);
4435 tp->tx_ring = NULL;
4436 }
4437 if (tp->hw_status) {
4438 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4439 tp->hw_status, tp->status_mapping);
4440 tp->hw_status = NULL;
4441 }
4442 if (tp->hw_stats) {
4443 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4444 tp->hw_stats, tp->stats_mapping);
4445 tp->hw_stats = NULL;
4446 }
4447}
4448
4449/*
4450 * Must not be invoked with interrupt sources disabled and
4451 * the hardware shutdown down. Can sleep.
4452 */
4453static int tg3_alloc_consistent(struct tg3 *tp)
4454{
bd2b3343 4455 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4456 (TG3_RX_RING_SIZE +
4457 TG3_RX_JUMBO_RING_SIZE)) +
4458 (sizeof(struct tx_ring_info) *
4459 TG3_TX_RING_SIZE),
4460 GFP_KERNEL);
4461 if (!tp->rx_std_buffers)
4462 return -ENOMEM;
4463
1da177e4
LT		 4464 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4465 tp->tx_buffers = (struct tx_ring_info *)
4466 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4467
4468 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4469 &tp->rx_std_mapping);
4470 if (!tp->rx_std)
4471 goto err_out;
4472
4473 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4474 &tp->rx_jumbo_mapping);
4475
4476 if (!tp->rx_jumbo)
4477 goto err_out;
4478
4479 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4480 &tp->rx_rcb_mapping);
4481 if (!tp->rx_rcb)
4482 goto err_out;
4483
4484 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4485 &tp->tx_desc_mapping);
4486 if (!tp->tx_ring)
4487 goto err_out;
4488
4489 tp->hw_status = pci_alloc_consistent(tp->pdev,
4490 TG3_HW_STATUS_SIZE,
4491 &tp->status_mapping);
4492 if (!tp->hw_status)
4493 goto err_out;
4494
4495 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4496 sizeof(struct tg3_hw_stats),
4497 &tp->stats_mapping);
4498 if (!tp->hw_stats)
4499 goto err_out;
4500
4501 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4502 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4503
4504 return 0;
4505
4506err_out:
4507 tg3_free_consistent(tp);
4508 return -ENOMEM;
4509}
4510
4511#define MAX_WAIT_CNT 1000
4512
4513/* To stop a block, clear the enable bit and poll till it
4514 * clears. tp->lock is held.
4515 */
b3b7d6be 4516static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4517{
4518 unsigned int i;
4519 u32 val;
4520
4521 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4522 switch (ofs) {
4523 case RCVLSC_MODE:
4524 case DMAC_MODE:
4525 case MBFREE_MODE:
4526 case BUFMGR_MODE:
4527 case MEMARB_MODE:
4528 /* We can't enable/disable these bits of the
4529 * 5705/5750, just say success.
4530 */
4531 return 0;
4532
4533 default:
4534 break;
4535 };
4536 }
4537
4538 val = tr32(ofs);
4539 val &= ~enable_bit;
4540 tw32_f(ofs, val);
4541
4542 for (i = 0; i < MAX_WAIT_CNT; i++) {
4543 udelay(100);
4544 val = tr32(ofs);
4545 if ((val & enable_bit) == 0)
4546 break;
4547 }
4548
b3b7d6be 4549 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4550 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4551 "ofs=%lx enable_bit=%x\n",
4552 ofs, enable_bit);
4553 return -ENODEV;
4554 }
4555
4556 return 0;
4557}
4558
4559/* tp->lock is held. */
b3b7d6be 4560static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4561{
4562 int i, err;
4563
4564 tg3_disable_ints(tp);
4565
4566 tp->rx_mode &= ~RX_MODE_ENABLE;
4567 tw32_f(MAC_RX_MODE, tp->rx_mode);
4568 udelay(10);
4569
b3b7d6be
DM		 4570 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4571 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4572 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4573 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4574 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4575 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4576
4577 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4578 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4579 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4580 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4581 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4582 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4583 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4584
4585 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4586 tw32_f(MAC_MODE, tp->mac_mode);
4587 udelay(40);
4588
4589 tp->tx_mode &= ~TX_MODE_ENABLE;
4590 tw32_f(MAC_TX_MODE, tp->tx_mode);
4591
4592 for (i = 0; i < MAX_WAIT_CNT; i++) {
4593 udelay(100);
4594 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4595 break;
4596 }
4597 if (i >= MAX_WAIT_CNT) {
4598 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4599 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4600 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4601 err |= -ENODEV;
1da177e4
LT		 4602 }
4603
e6de8ad1 4604 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4605 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4606 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4607
4608 tw32(FTQ_RESET, 0xffffffff);
4609 tw32(FTQ_RESET, 0x00000000);
4610
b3b7d6be
DM		 4611 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4612 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4613
4614 if (tp->hw_status)
4615 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4616 if (tp->hw_stats)
4617 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4618
1da177e4
LT		 4619 return err;
4620}
4621
4622/* tp->lock is held. */
4623static int tg3_nvram_lock(struct tg3 *tp)
4624{
4625 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4626 int i;
4627
ec41c7df
MC		 4628 if (tp->nvram_lock_cnt == 0) {
4629 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4630 for (i = 0; i < 8000; i++) {
4631 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4632 break;
4633 udelay(20);
4634 }
4635 if (i == 8000) {
4636 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4637 return -ENODEV;
4638 }
1da177e4 4639 }
ec41c7df 4640 tp->nvram_lock_cnt++;
1da177e4
LT		 4641 }
4642 return 0;
4643}
4644
4645/* tp->lock is held. */
4646static void tg3_nvram_unlock(struct tg3 *tp)
4647{
ec41c7df
MC		 4648 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4649 if (tp->nvram_lock_cnt > 0)
4650 tp->nvram_lock_cnt--;
4651 if (tp->nvram_lock_cnt == 0)
4652 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4653 }
1da177e4
LT		 4654}
4655
e6af301b
MC		 4656/* tp->lock is held. */
4657static void tg3_enable_nvram_access(struct tg3 *tp)
4658{
4659 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4660 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4661 u32 nvaccess = tr32(NVRAM_ACCESS);
4662
4663 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4664 }
4665}
4666
4667/* tp->lock is held. */
4668static void tg3_disable_nvram_access(struct tg3 *tp)
4669{
4670 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4671 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4672 u32 nvaccess = tr32(NVRAM_ACCESS);
4673
4674 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4675 }
4676}
4677
1da177e4
LT		 4678/* tp->lock is held. */
4679static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4680{
f49639e6
DM		 4681 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4682 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4683
4684 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4685 switch (kind) {
4686 case RESET_KIND_INIT:
4687 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4688 DRV_STATE_START);
4689 break;
4690
4691 case RESET_KIND_SHUTDOWN:
4692 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4693 DRV_STATE_UNLOAD);
4694 break;
4695
4696 case RESET_KIND_SUSPEND:
4697 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4698 DRV_STATE_SUSPEND);
4699 break;
4700
4701 default:
4702 break;
4703 };
4704 }
4705}
4706
4707/* tp->lock is held. */
4708static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4709{
4710 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4711 switch (kind) {
4712 case RESET_KIND_INIT:
4713 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4714 DRV_STATE_START_DONE);
4715 break;
4716
4717 case RESET_KIND_SHUTDOWN:
4718 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4719 DRV_STATE_UNLOAD_DONE);
4720 break;
4721
4722 default:
4723 break;
4724 };
4725 }
4726}
4727
4728/* tp->lock is held. */
4729static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4730{
4731 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4732 switch (kind) {
4733 case RESET_KIND_INIT:
4734 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4735 DRV_STATE_START);
4736 break;
4737
4738 case RESET_KIND_SHUTDOWN:
4739 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4740 DRV_STATE_UNLOAD);
4741 break;
4742
4743 case RESET_KIND_SUSPEND:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745 DRV_STATE_SUSPEND);
4746 break;
4747
4748 default:
4749 break;
4750 };
4751 }
4752}
4753
7a6f4369
MC		 4754static int tg3_poll_fw(struct tg3 *tp)
4755{
4756 int i;
4757 u32 val;
4758
b5d3772c 4759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 4760 /* Wait up to 20ms for init done. */
4761 for (i = 0; i < 200; i++) {
b5d3772c
MC		 4762 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4763 return 0;
0ccead18 4764 udelay(100);
b5d3772c
MC		 4765 }
4766 return -ENODEV;
4767 }
4768
7a6f4369
MC		 4769 /* Wait for firmware initialization to complete. */
4770 for (i = 0; i < 100000; i++) {
4771 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4772 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4773 break;
4774 udelay(10);
4775 }
4776
4777 /* Chip might not be fitted with firmware. Some Sun onboard
4778 * parts are configured like that. So don't signal the timeout
4779 * of the above loop as an error, but do report the lack of
4780 * running firmware once.
4781 */
4782 if (i >= 100000 &&
4783 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4784 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4785
4786 printk(KERN_INFO PFX "%s: No firmware running.\n",
4787 tp->dev->name);
4788 }
4789
4790 return 0;
4791}
4792
1da177e4
LT		 4793static void tg3_stop_fw(struct tg3 *);
4794
4795/* tp->lock is held. */
4796static int tg3_chip_reset(struct tg3 *tp)
4797{
4798 u32 val;
1ee582d8 4799 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 4800 int err;
1da177e4 4801
f49639e6
DM		 4802 tg3_nvram_lock(tp);
4803
4804 /* No matching tg3_nvram_unlock() after this because
4805 * chip reset below will undo the nvram lock.
4806 */
4807 tp->nvram_lock_cnt = 0;
1da177e4 4808
d9ab5ad1 4809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 4810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1
MC		 4811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4812 tw32(GRC_FASTBOOT_PC, 0);
4813
1da177e4
LT		 4814 /*
4815 * We must avoid the readl() that normally takes place.
4816 * It locks machines, causes machine checks, and other
4817 * fun things. So, temporarily disable the 5701
4818 * hardware workaround, while we do the reset.
4819 */
1ee582d8
MC		 4820 write_op = tp->write32;
4821 if (write_op == tg3_write_flush_reg32)
4822 tp->write32 = tg3_write32;
1da177e4 4823
d18edcb2
MC		 4824 /* Prevent the irq handler from reading or writing PCI registers
4825 * during chip reset when the memory enable bit in the PCI command
4826 * register may be cleared. The chip does not generate interrupt
4827 * at this time, but the irq handler may still be called due to irq
4828 * sharing or irqpoll.
4829 */
4830 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 4831 if (tp->hw_status) {
4832 tp->hw_status->status = 0;
4833 tp->hw_status->status_tag = 0;
4834 }
d18edcb2
MC		 4835 tp->last_tag = 0;
4836 smp_mb();
4837 synchronize_irq(tp->pdev->irq);
4838
1da177e4
LT		 4839 /* do the reset */
4840 val = GRC_MISC_CFG_CORECLK_RESET;
4841
4842 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4843 if (tr32(0x7e2c) == 0x60) {
4844 tw32(0x7e2c, 0x20);
4845 }
4846 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4847 tw32(GRC_MISC_CFG, (1 << 29));
4848 val |= (1 << 29);
4849 }
4850 }
4851
b5d3772c
MC		 4852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4853 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4854 tw32(GRC_VCPU_EXT_CTRL,
4855 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4856 }
4857
1da177e4
LT		 4858 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4859 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4860 tw32(GRC_MISC_CFG, val);
4861
1ee582d8
MC		 4862 /* restore 5701 hardware bug workaround write method */
4863 tp->write32 = write_op;
1da177e4
LT		 4864
4865 /* Unfortunately, we have to delay before the PCI read back.
4866 * Some 575X chips even will not respond to a PCI cfg access
4867 * when the reset command is given to the chip.
4868 *
4869 * How do these hardware designers expect things to work
4870 * properly if the PCI write is posted for a long period
4871 * of time? It is always necessary to have some method by
4872 * which a register read back can occur to push the write
4873 * out which does the reset.
4874 *
4875 * For most tg3 variants the trick below was working.
4876 * Ho hum...
4877 */
4878 udelay(120);
4879
4880 /* Flush PCI posted writes. The normal MMIO registers
4881 * are inaccessible at this time so this is the only
4882 * way to make this reliably (actually, this is no longer
4883 * the case, see above). I tried to use indirect
4884 * register read/write but this upset some 5701 variants.
4885 */
4886 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4887
4888 udelay(120);
4889
4890 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4891 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4892 int i;
4893 u32 cfg_val;
4894
4895 /* Wait for link training to complete. */
4896 for (i = 0; i < 5000; i++)
4897 udelay(100);
4898
4899 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4900 pci_write_config_dword(tp->pdev, 0xc4,
4901 cfg_val | (1 << 15));
4902 }
4903 /* Set PCIE max payload size and clear error status. */
4904 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4905 }
4906
4907 /* Re-enable indirect register accesses. */
4908 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4909 tp->misc_host_ctrl);
4910
4911 /* Set MAX PCI retry to zero. */
4912 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4913 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4914 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4915 val |= PCISTATE_RETRY_SAME_DMA;
4916 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4917
4918 pci_restore_state(tp->pdev);
4919
d18edcb2
MC		 4920 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4921
1da177e4
LT		 4922 /* Make sure PCI-X relaxed ordering bit is clear. */
4923 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4924 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4925 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4926
a4e2b347 4927 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4928 u32 val;
4929
4930 /* Chip reset on 5780 will reset MSI enable bit,
4931 * so need to restore it.
4932 */
4933 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4934 u16 ctrl;
4935
4936 pci_read_config_word(tp->pdev,
4937 tp->msi_cap + PCI_MSI_FLAGS,
4938 &ctrl);
4939 pci_write_config_word(tp->pdev,
4940 tp->msi_cap + PCI_MSI_FLAGS,
4941 ctrl | PCI_MSI_FLAGS_ENABLE);
4942 val = tr32(MSGINT_MODE);
4943 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4944 }
4945
4946 val = tr32(MEMARB_MODE);
4947 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4948
4949 } else
4950 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4951
4952 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4953 tg3_stop_fw(tp);
4954 tw32(0x5000, 0x400);
4955 }
4956
4957 tw32(GRC_MODE, tp->grc_mode);
4958
4959 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4960 u32 val = tr32(0xc4);
4961
4962 tw32(0xc4, val | (1 << 15));
4963 }
4964
4965 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4967 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4968 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4969 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4970 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4971 }
4972
4973 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4974 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4975 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4976 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4977 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4978 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4979 } else
4980 tw32_f(MAC_MODE, 0);
4981 udelay(40);
4982
7a6f4369
MC		 4983 err = tg3_poll_fw(tp);
4984 if (err)
4985 return err;
1da177e4
LT		 4986
4987 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4988 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4989 u32 val = tr32(0x7c00);
4990
4991 tw32(0x7c00, val | (1 << 25));
4992 }
4993
4994 /* Reprobe ASF enable state. */
4995 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4996 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4997 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4998 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4999 u32 nic_cfg;
5000
5001 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5002 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5003 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 5004 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 5005 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5006 }
5007 }
5008
5009 return 0;
5010}
5011
5012/* tp->lock is held. */
5013static void tg3_stop_fw(struct tg3 *tp)
5014{
5015 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5016 u32 val;
5017 int i;
5018
5019 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5020 val = tr32(GRC_RX_CPU_EVENT);
5021 val |= (1 << 14);
5022 tw32(GRC_RX_CPU_EVENT, val);
5023
5024 /* Wait for RX cpu to ACK the event. */
5025 for (i = 0; i < 100; i++) {
5026 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5027 break;
5028 udelay(1);
5029 }
5030 }
5031}
5032
5033/* tp->lock is held. */
944d980e 5034static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 5035{
5036 int err;
5037
5038 tg3_stop_fw(tp);
5039
944d980e 5040 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5041
b3b7d6be 5042 tg3_abort_hw(tp, silent);
1da177e4
LT		 5043 err = tg3_chip_reset(tp);
5044
944d980e
MC		 5045 tg3_write_sig_legacy(tp, kind);
5046 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5047
5048 if (err)
5049 return err;
5050
5051 return 0;
5052}
5053
5054#define TG3_FW_RELEASE_MAJOR 0x0
5055#define TG3_FW_RELASE_MINOR 0x0
5056#define TG3_FW_RELEASE_FIX 0x0
5057#define TG3_FW_START_ADDR 0x08000000
5058#define TG3_FW_TEXT_ADDR 0x08000000
5059#define TG3_FW_TEXT_LEN 0x9c0
5060#define TG3_FW_RODATA_ADDR 0x080009c0
5061#define TG3_FW_RODATA_LEN 0x60
5062#define TG3_FW_DATA_ADDR 0x08000a40
5063#define TG3_FW_DATA_LEN 0x20
5064#define TG3_FW_SBSS_ADDR 0x08000a60
5065#define TG3_FW_SBSS_LEN 0xc
5066#define TG3_FW_BSS_ADDR 0x08000a70
5067#define TG3_FW_BSS_LEN 0x10
5068
50da859d 5069static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5070 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5071 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5072 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5073 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5074 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5075 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5076 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5077 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5078 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5079 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5080 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5081 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5082 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5083 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5084 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5085 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5086 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5087 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5088 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5089 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5090 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5091 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5092 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5093 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5094 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5095 0, 0, 0, 0, 0, 0,
5096 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5097 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5098 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5099 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5100 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5101 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5102 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5103 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5104 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5105 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5106 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5107 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5108 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5109 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5110 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5111 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5112 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5113 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5114 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5115 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5116 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5117 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5118 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5119 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5120 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5121 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5122 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5123 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5124 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5125 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5126 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5127 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5128 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5129 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5130 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5131 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5132 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5133 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5134 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5135 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5136 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5137 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5138 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5139 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5140 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5141 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5142 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5143 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5144 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5145 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5146 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5147 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5148 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5149 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5150 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5151 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5152 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5153 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5154 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5155 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5156 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5157 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5158 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5159 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5160 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5161};
5162
50da859d 5163static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5164 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5165 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5166 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5167 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5168 0x00000000
5169};
5170
5171#if 0 /* All zeros, don't eat up space with it. */
5172u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5173 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5174 0x00000000, 0x00000000, 0x00000000, 0x00000000
5175};
5176#endif
5177
5178#define RX_CPU_SCRATCH_BASE 0x30000
5179#define RX_CPU_SCRATCH_SIZE 0x04000
5180#define TX_CPU_SCRATCH_BASE 0x34000
5181#define TX_CPU_SCRATCH_SIZE 0x04000
5182
5183/* tp->lock is held. */
5184static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5185{
5186 int i;
5187
5d9428de
ES		 5188 BUG_ON(offset == TX_CPU_BASE &&
5189 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5190
b5d3772c
MC		 5191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5192 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5193
5194 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5195 return 0;
5196 }
1da177e4
LT		 5197 if (offset == RX_CPU_BASE) {
5198 for (i = 0; i < 10000; i++) {
5199 tw32(offset + CPU_STATE, 0xffffffff);
5200 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5201 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5202 break;
5203 }
5204
5205 tw32(offset + CPU_STATE, 0xffffffff);
5206 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5207 udelay(10);
5208 } else {
5209 for (i = 0; i < 10000; i++) {
5210 tw32(offset + CPU_STATE, 0xffffffff);
5211 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5212 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5213 break;
5214 }
5215 }
5216
5217 if (i >= 10000) {
5218 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5219 "and %s CPU\n",
5220 tp->dev->name,
5221 (offset == RX_CPU_BASE ? "RX" : "TX"));
5222 return -ENODEV;
5223 }
ec41c7df
MC		 5224
5225 /* Clear firmware's nvram arbitration. */
5226 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5227 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5228 return 0;
5229}
5230
5231struct fw_info {
5232 unsigned int text_base;
5233 unsigned int text_len;
50da859d 5234 const u32 *text_data;
1da177e4
LT		 5235 unsigned int rodata_base;
5236 unsigned int rodata_len;
50da859d 5237 const u32 *rodata_data;
1da177e4
LT		 5238 unsigned int data_base;
5239 unsigned int data_len;
50da859d 5240 const u32 *data_data;
1da177e4
LT		 5241};
5242
5243/* tp->lock is held. */
5244static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5245 int cpu_scratch_size, struct fw_info *info)
5246{
ec41c7df 5247 int err, lock_err, i;
1da177e4
LT		 5248 void (*write_op)(struct tg3 *, u32, u32);
5249
5250 if (cpu_base == TX_CPU_BASE &&
5251 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5252 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5253 "TX cpu firmware on %s which is 5705.\n",
5254 tp->dev->name);
5255 return -EINVAL;
5256 }
5257
5258 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5259 write_op = tg3_write_mem;
5260 else
5261 write_op = tg3_write_indirect_reg32;
5262
1b628151
MC		 5263 /* It is possible that bootcode is still loading at this point.
5264 * Get the nvram lock first before halting the cpu.
5265 */
ec41c7df 5266 lock_err = tg3_nvram_lock(tp);
1da177e4 5267 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5268 if (!lock_err)
5269 tg3_nvram_unlock(tp);
1da177e4
LT		 5270 if (err)
5271 goto out;
5272
5273 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5274 write_op(tp, cpu_scratch_base + i, 0);
5275 tw32(cpu_base + CPU_STATE, 0xffffffff);
5276 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5277 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5278 write_op(tp, (cpu_scratch_base +
5279 (info->text_base & 0xffff) +
5280 (i * sizeof(u32))),
5281 (info->text_data ?
5282 info->text_data[i] : 0));
5283 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5284 write_op(tp, (cpu_scratch_base +
5285 (info->rodata_base & 0xffff) +
5286 (i * sizeof(u32))),
5287 (info->rodata_data ?
5288 info->rodata_data[i] : 0));
5289 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5290 write_op(tp, (cpu_scratch_base +
5291 (info->data_base & 0xffff) +
5292 (i * sizeof(u32))),
5293 (info->data_data ?
5294 info->data_data[i] : 0));
5295
5296 err = 0;
5297
5298out:
1da177e4
LT		 5299 return err;
5300}
5301
5302/* tp->lock is held. */
5303static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5304{
5305 struct fw_info info;
5306 int err, i;
5307
5308 info.text_base = TG3_FW_TEXT_ADDR;
5309 info.text_len = TG3_FW_TEXT_LEN;
5310 info.text_data = &tg3FwText[0];
5311 info.rodata_base = TG3_FW_RODATA_ADDR;
5312 info.rodata_len = TG3_FW_RODATA_LEN;
5313 info.rodata_data = &tg3FwRodata[0];
5314 info.data_base = TG3_FW_DATA_ADDR;
5315 info.data_len = TG3_FW_DATA_LEN;
5316 info.data_data = NULL;
5317
5318 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5319 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5320 &info);
5321 if (err)
5322 return err;
5323
5324 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5325 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5326 &info);
5327 if (err)
5328 return err;
5329
5330 /* Now startup only the RX cpu. */
5331 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5332 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5333
5334 for (i = 0; i < 5; i++) {
5335 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5336 break;
5337 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5338 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5339 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5340 udelay(1000);
5341 }
5342 if (i >= 5) {
5343 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5344 "to set RX CPU PC, is %08x should be %08x\n",
5345 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5346 TG3_FW_TEXT_ADDR);
5347 return -ENODEV;
5348 }
5349 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5350 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5351
5352 return 0;
5353}
5354
1da177e4
LT		 5355
5356#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5357#define TG3_TSO_FW_RELASE_MINOR 0x6
5358#define TG3_TSO_FW_RELEASE_FIX 0x0
5359#define TG3_TSO_FW_START_ADDR 0x08000000
5360#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5361#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5362#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5363#define TG3_TSO_FW_RODATA_LEN 0x60
5364#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5365#define TG3_TSO_FW_DATA_LEN 0x30
5366#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5367#define TG3_TSO_FW_SBSS_LEN 0x2c
5368#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5369#define TG3_TSO_FW_BSS_LEN 0x894
5370
50da859d 5371static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5372 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5373 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5374 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5375 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5376 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5377 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5378 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5379 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5380 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5381 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5382 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5383 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5384 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5385 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5386 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5387 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5388 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5389 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5390 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5391 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5392 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5393 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5394 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5395 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5396 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5397 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5398 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5399 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5400 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5401 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5402 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5403 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5404 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5405 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5406 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5407 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5408 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5409 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5410 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5411 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5412 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5413 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5414 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5415 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5416 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5417 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5418 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5419 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5420 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5421 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5422 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5423 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5424 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5425 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5426 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5427 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5428 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5429 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5430 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5431 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5432 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5433 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5434 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5435 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5436 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5437 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5438 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5439 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5440 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5441 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5442 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5443 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5444 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5445 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5446 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5447 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5448 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5449 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5450 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5451 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5452 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5453 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5454 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5455 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5456 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5457 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5458 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5459 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5460 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5461 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5462 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5463 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5464 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5465 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5466 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5467 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5468 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5469 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5470 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5471 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5472 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5473 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5474 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5475 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5476 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5477 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5478 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5479 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5480 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5481 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5482 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5483 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5484 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5485 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5486 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5487 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5488 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5489 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5490 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5491 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5492 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5493 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5494 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5495 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5496 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5497 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5498 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5499 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5500 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5501 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5502 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5503 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5504 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5505 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5506 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5507 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5508 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5509 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5510 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5511 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5512 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5513 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5514 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5515 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5516 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5517 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5518 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5519 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5520 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5521 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5522 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5523 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5524 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5525 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5526 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5527 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5528 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5529 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5530 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5531 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5532 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5533 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5534 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5535 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5536 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5537 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5538 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5539 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5540 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5541 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5542 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5543 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5544 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5545 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5546 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5547 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5548 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5549 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5550 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5551 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5552 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5553 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5554 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5555 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5556 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5557 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5558 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5559 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5560 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5561 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5562 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5563 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5564 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5565 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5566 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5567 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5568 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5569 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5570 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5571 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5572 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5573 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5574 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5575 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5576 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5577 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5578 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5579 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5580 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5581 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5582 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5583 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5584 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5585 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5586 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5587 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5588 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5589 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5590 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5591 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5592 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5593 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5594 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5595 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5596 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5597 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5598 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5599 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5600 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5601 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5602 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5603 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5604 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5605 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5606 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5607 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5608 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5609 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5610 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5611 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5612 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5613 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5614 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5615 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5616 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5617 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5618 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5619 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5620 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5621 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5622 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5623 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5624 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5625 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5626 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5627 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5628 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5629 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5630 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5631 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5632 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5633 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5634 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5635 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5636 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5637 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5638 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5639 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5640 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5641 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5642 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5643 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5644 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5645 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5646 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5647 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5648 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5649 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5650 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5651 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5652 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5653 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5654 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5655 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5656};
5657
50da859d 5658static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5659 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5660 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5661 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5662 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5663 0x00000000,
5664};
5665
50da859d 5666static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5667 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5668 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5669 0x00000000,
5670};
5671
5672/* 5705 needs a special version of the TSO firmware. */
5673#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5674#define TG3_TSO5_FW_RELASE_MINOR 0x2
5675#define TG3_TSO5_FW_RELEASE_FIX 0x0
5676#define TG3_TSO5_FW_START_ADDR 0x00010000
5677#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5678#define TG3_TSO5_FW_TEXT_LEN 0xe90
5679#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5680#define TG3_TSO5_FW_RODATA_LEN 0x50
5681#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5682#define TG3_TSO5_FW_DATA_LEN 0x20
5683#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5684#define TG3_TSO5_FW_SBSS_LEN 0x28
5685#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5686#define TG3_TSO5_FW_BSS_LEN 0x88
5687
50da859d 5688static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5689 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5690 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5691 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5692 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5693 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5694 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5695 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5696 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5697 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5698 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5699 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5700 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5701 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5702 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5703 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5704 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5705 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5706 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5707 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5708 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5709 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5710 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5711 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5712 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5713 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5714 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5715 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5716 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5717 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5718 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5719 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5720 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5721 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5722 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5723 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5724 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5725 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5726 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5727 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5728 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5729 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5730 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5731 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5732 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5733 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5734 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5735 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5736 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5737 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5738 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5739 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5740 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5741 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5742 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5743 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5744 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5745 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5746 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5747 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5748 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5749 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5750 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5751 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5752 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5753 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5754 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5755 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5756 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5757 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5758 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5759 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5760 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5761 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5762 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5763 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5764 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5765 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5766 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5767 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5768 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5769 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5770 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5771 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5772 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5773 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5774 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5775 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5776 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5777 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5778 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5779 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5780 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5781 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5782 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5783 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5784 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5785 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5786 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5787 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5788 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5789 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5790 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5791 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5792 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5793 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5794 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5795 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5796 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5797 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5798 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5799 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5800 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5801 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5802 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5803 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5804 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5805 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5806 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5807 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5808 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5809 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5810 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5811 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5812 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5813 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5814 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5815 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5816 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5817 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5818 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5819 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5820 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5821 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5822 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5823 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5824 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5825 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5826 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5827 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5828 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5829 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5830 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5831 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5832 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5833 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5834 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5835 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5836 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5837 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5838 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5839 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5840 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5841 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5842 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5843 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5844 0x00000000, 0x00000000, 0x00000000,
5845};
5846
50da859d 5847static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 5848 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5849 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5850 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5851 0x00000000, 0x00000000, 0x00000000,
5852};
5853
50da859d 5854static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 5855 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5856 0x00000000, 0x00000000, 0x00000000,
5857};
5858
5859/* tp->lock is held. */
5860static int tg3_load_tso_firmware(struct tg3 *tp)
5861{
5862 struct fw_info info;
5863 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5864 int err, i;
5865
5866 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5867 return 0;
5868
5869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5870 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5871 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5872 info.text_data = &tg3Tso5FwText[0];
5873 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5874 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5875 info.rodata_data = &tg3Tso5FwRodata[0];
5876 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5877 info.data_len = TG3_TSO5_FW_DATA_LEN;
5878 info.data_data = &tg3Tso5FwData[0];
5879 cpu_base = RX_CPU_BASE;
5880 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5881 cpu_scratch_size = (info.text_len +
5882 info.rodata_len +
5883 info.data_len +
5884 TG3_TSO5_FW_SBSS_LEN +
5885 TG3_TSO5_FW_BSS_LEN);
5886 } else {
5887 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5888 info.text_len = TG3_TSO_FW_TEXT_LEN;
5889 info.text_data = &tg3TsoFwText[0];
5890 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5891 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5892 info.rodata_data = &tg3TsoFwRodata[0];
5893 info.data_base = TG3_TSO_FW_DATA_ADDR;
5894 info.data_len = TG3_TSO_FW_DATA_LEN;
5895 info.data_data = &tg3TsoFwData[0];
5896 cpu_base = TX_CPU_BASE;
5897 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5898 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5899 }
5900
5901 err = tg3_load_firmware_cpu(tp, cpu_base,
5902 cpu_scratch_base, cpu_scratch_size,
5903 &info);
5904 if (err)
5905 return err;
5906
5907 /* Now startup the cpu. */
5908 tw32(cpu_base + CPU_STATE, 0xffffffff);
5909 tw32_f(cpu_base + CPU_PC, info.text_base);
5910
5911 for (i = 0; i < 5; i++) {
5912 if (tr32(cpu_base + CPU_PC) == info.text_base)
5913 break;
5914 tw32(cpu_base + CPU_STATE, 0xffffffff);
5915 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5916 tw32_f(cpu_base + CPU_PC, info.text_base);
5917 udelay(1000);
5918 }
5919 if (i >= 5) {
5920 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5921 "to set CPU PC, is %08x should be %08x\n",
5922 tp->dev->name, tr32(cpu_base + CPU_PC),
5923 info.text_base);
5924 return -ENODEV;
5925 }
5926 tw32(cpu_base + CPU_STATE, 0xffffffff);
5927 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5928 return 0;
5929}
5930
1da177e4
LT		 5931
5932/* tp->lock is held. */
986e0aeb 5933static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
1da177e4
LT		 5934{
5935 u32 addr_high, addr_low;
5936 int i;
5937
5938 addr_high = ((tp->dev->dev_addr[0] << 8) |
5939 tp->dev->dev_addr[1]);
5940 addr_low = ((tp->dev->dev_addr[2] << 24) |
5941 (tp->dev->dev_addr[3] << 16) |
5942 (tp->dev->dev_addr[4] << 8) |
5943 (tp->dev->dev_addr[5] << 0));
5944 for (i = 0; i < 4; i++) {
986e0aeb
MC		 5945 if (i == 1 && skip_mac_1)
5946 continue;
1da177e4
LT		 5947 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5948 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5949 }
5950
5951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5953 for (i = 0; i < 12; i++) {
5954 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5955 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5956 }
5957 }
5958
5959 addr_high = (tp->dev->dev_addr[0] +
5960 tp->dev->dev_addr[1] +
5961 tp->dev->dev_addr[2] +
5962 tp->dev->dev_addr[3] +
5963 tp->dev->dev_addr[4] +
5964 tp->dev->dev_addr[5]) &
5965 TX_BACKOFF_SEED_MASK;
5966 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5967}
5968
5969static int tg3_set_mac_addr(struct net_device *dev, void *p)
5970{
5971 struct tg3 *tp = netdev_priv(dev);
5972 struct sockaddr *addr = p;
986e0aeb 5973 int err = 0, skip_mac_1 = 0;
1da177e4 5974
f9804ddb
MC		 5975 if (!is_valid_ether_addr(addr->sa_data))
5976 return -EINVAL;
5977
1da177e4
LT		 5978 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5979
e75f7c90
MC		 5980 if (!netif_running(dev))
5981 return 0;
5982
58712ef9 5983 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 5984 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 5985
986e0aeb
MC		 5986 addr0_high = tr32(MAC_ADDR_0_HIGH);
5987 addr0_low = tr32(MAC_ADDR_0_LOW);
5988 addr1_high = tr32(MAC_ADDR_1_HIGH);
5989 addr1_low = tr32(MAC_ADDR_1_LOW);
5990
5991 /* Skip MAC addr 1 if ASF is using it. */
5992 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
5993 !(addr1_high == 0 && addr1_low == 0))
5994 skip_mac_1 = 1;
58712ef9 5995 }
986e0aeb
MC		 5996 spin_lock_bh(&tp->lock);
5997 __tg3_set_mac_addr(tp, skip_mac_1);
5998 spin_unlock_bh(&tp->lock);
1da177e4 5999
b9ec6c1b 6000 return err;
1da177e4
LT		 6001}
6002
6003/* tp->lock is held. */
6004static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6005 dma_addr_t mapping, u32 maxlen_flags,
6006 u32 nic_addr)
6007{
6008 tg3_write_mem(tp,
6009 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6010 ((u64) mapping >> 32));
6011 tg3_write_mem(tp,
6012 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6013 ((u64) mapping & 0xffffffff));
6014 tg3_write_mem(tp,
6015 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6016 maxlen_flags);
6017
6018 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6019 tg3_write_mem(tp,
6020 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6021 nic_addr);
6022}
6023
6024static void __tg3_set_rx_mode(struct net_device *);
d244c892 6025static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6026{
6027 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6028 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6029 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6030 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6031 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6032 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6033 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6034 }
6035 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6036 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6037 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6038 u32 val = ec->stats_block_coalesce_usecs;
6039
6040 if (!netif_carrier_ok(tp->dev))
6041 val = 0;
6042
6043 tw32(HOSTCC_STAT_COAL_TICKS, val);
6044 }
6045}
1da177e4
LT		 6046
6047/* tp->lock is held. */
8e7a22e3 6048static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6049{
6050 u32 val, rdmac_mode;
6051 int i, err, limit;
6052
6053 tg3_disable_ints(tp);
6054
6055 tg3_stop_fw(tp);
6056
6057 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6058
6059 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6060 tg3_abort_hw(tp, 1);
1da177e4
LT		 6061 }
6062
36da4d86 6063 if (reset_phy)
d4d2c558
MC		 6064 tg3_phy_reset(tp);
6065
1da177e4
LT		 6066 err = tg3_chip_reset(tp);
6067 if (err)
6068 return err;
6069
6070 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6071
6072 /* This works around an issue with Athlon chipsets on
6073 * B3 tigon3 silicon. This bit has no effect on any
6074 * other revision. But do not set this on PCI Express
6075 * chips.
6076 */
6077 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6078 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6079 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6080
6081 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6082 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6083 val = tr32(TG3PCI_PCISTATE);
6084 val |= PCISTATE_RETRY_SAME_DMA;
6085 tw32(TG3PCI_PCISTATE, val);
6086 }
6087
6088 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6089 /* Enable some hw fixes. */
6090 val = tr32(TG3PCI_MSI_DATA);
6091 val |= (1 << 26) | (1 << 28) | (1 << 29);
6092 tw32(TG3PCI_MSI_DATA, val);
6093 }
6094
6095 /* Descriptor ring init may make accesses to the
6096 * NIC SRAM area to setup the TX descriptors, so we
6097 * can only do this after the hardware has been
6098 * successfully reset.
6099 */
32d8c572
MC		 6100 err = tg3_init_rings(tp);
6101 if (err)
6102 return err;
1da177e4
LT		 6103
6104 /* This value is determined during the probe time DMA
6105 * engine test, tg3_test_dma.
6106 */
6107 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6108
6109 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6110 GRC_MODE_4X_NIC_SEND_RINGS |
6111 GRC_MODE_NO_TX_PHDR_CSUM |
6112 GRC_MODE_NO_RX_PHDR_CSUM);
6113 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6114
6115 /* Pseudo-header checksum is done by hardware logic and not
6116 * the offload processers, so make the chip do the pseudo-
6117 * header checksums on receive. For transmit it is more
6118 * convenient to do the pseudo-header checksum in software
6119 * as Linux does that on transmit for us in all cases.
6120 */
6121 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6122
6123 tw32(GRC_MODE,
6124 tp->grc_mode |
6125 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6126
6127 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6128 val = tr32(GRC_MISC_CFG);
6129 val &= ~0xff;
6130 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6131 tw32(GRC_MISC_CFG, val);
6132
6133 /* Initialize MBUF/DESC pool. */
cbf46853 6134 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6135 /* Do nothing. */
6136 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6137 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6139 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6140 else
6141 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6142 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6143 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6144 }
1da177e4
LT		 6145 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6146 int fw_len;
6147
6148 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6149 TG3_TSO5_FW_RODATA_LEN +
6150 TG3_TSO5_FW_DATA_LEN +
6151 TG3_TSO5_FW_SBSS_LEN +
6152 TG3_TSO5_FW_BSS_LEN);
6153 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6154 tw32(BUFMGR_MB_POOL_ADDR,
6155 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6156 tw32(BUFMGR_MB_POOL_SIZE,
6157 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6158 }
1da177e4 6159
0f893dc6 6160 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6161 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6162 tp->bufmgr_config.mbuf_read_dma_low_water);
6163 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6164 tp->bufmgr_config.mbuf_mac_rx_low_water);
6165 tw32(BUFMGR_MB_HIGH_WATER,
6166 tp->bufmgr_config.mbuf_high_water);
6167 } else {
6168 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6169 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6170 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6171 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6172 tw32(BUFMGR_MB_HIGH_WATER,
6173 tp->bufmgr_config.mbuf_high_water_jumbo);
6174 }
6175 tw32(BUFMGR_DMA_LOW_WATER,
6176 tp->bufmgr_config.dma_low_water);
6177 tw32(BUFMGR_DMA_HIGH_WATER,
6178 tp->bufmgr_config.dma_high_water);
6179
6180 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6181 for (i = 0; i < 2000; i++) {
6182 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6183 break;
6184 udelay(10);
6185 }
6186 if (i >= 2000) {
6187 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6188 tp->dev->name);
6189 return -ENODEV;
6190 }
6191
6192 /* Setup replenish threshold. */
f92905de
MC		 6193 val = tp->rx_pending / 8;
6194 if (val == 0)
6195 val = 1;
6196 else if (val > tp->rx_std_max_post)
6197 val = tp->rx_std_max_post;
b5d3772c
MC		 6198 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6199 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6200 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6201
6202 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6203 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6204 }
f92905de
MC		 6205
6206 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6207
6208 /* Initialize TG3_BDINFO's at:
6209 * RCVDBDI_STD_BD: standard eth size rx ring
6210 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6211 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6212 *
6213 * like so:
6214 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6215 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6216 * ring attribute flags
6217 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6218 *
6219 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6220 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6221 *
6222 * The size of each ring is fixed in the firmware, but the location is
6223 * configurable.
6224 */
6225 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6226 ((u64) tp->rx_std_mapping >> 32));
6227 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6228 ((u64) tp->rx_std_mapping & 0xffffffff));
6229 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6230 NIC_SRAM_RX_BUFFER_DESC);
6231
6232 /* Don't even try to program the JUMBO/MINI buffer descriptor
6233 * configs on 5705.
6234 */
6235 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6236 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6237 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6238 } else {
6239 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6240 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6241
6242 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6243 BDINFO_FLAGS_DISABLED);
6244
6245 /* Setup replenish threshold. */
6246 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6247
0f893dc6 6248 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6249 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6250 ((u64) tp->rx_jumbo_mapping >> 32));
6251 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6252 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6253 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6254 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6255 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6256 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6257 } else {
6258 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6259 BDINFO_FLAGS_DISABLED);
6260 }
6261
6262 }
6263
6264 /* There is only one send ring on 5705/5750, no need to explicitly
6265 * disable the others.
6266 */
6267 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6268 /* Clear out send RCB ring in SRAM. */
6269 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6270 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6271 BDINFO_FLAGS_DISABLED);
6272 }
6273
6274 tp->tx_prod = 0;
6275 tp->tx_cons = 0;
6276 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6277 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6278
6279 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6280 tp->tx_desc_mapping,
6281 (TG3_TX_RING_SIZE <<
6282 BDINFO_FLAGS_MAXLEN_SHIFT),
6283 NIC_SRAM_TX_BUFFER_DESC);
6284
6285 /* There is only one receive return ring on 5705/5750, no need
6286 * to explicitly disable the others.
6287 */
6288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6289 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6290 i += TG3_BDINFO_SIZE) {
6291 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6292 BDINFO_FLAGS_DISABLED);
6293 }
6294 }
6295
6296 tp->rx_rcb_ptr = 0;
6297 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6298
6299 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6300 tp->rx_rcb_mapping,
6301 (TG3_RX_RCB_RING_SIZE(tp) <<
6302 BDINFO_FLAGS_MAXLEN_SHIFT),
6303 0);
6304
6305 tp->rx_std_ptr = tp->rx_pending;
6306 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6307 tp->rx_std_ptr);
6308
0f893dc6 6309 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6310 tp->rx_jumbo_pending : 0;
6311 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6312 tp->rx_jumbo_ptr);
6313
6314 /* Initialize MAC address and backoff seed. */
986e0aeb 6315 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6316
6317 /* MTU + ethernet header + FCS + optional VLAN tag */
6318 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6319
6320 /* The slot time is changed by tg3_setup_phy if we
6321 * run at gigabit with half duplex.
6322 */
6323 tw32(MAC_TX_LENGTHS,
6324 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6325 (6 << TX_LENGTHS_IPG_SHIFT) |
6326 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6327
6328 /* Receive rules. */
6329 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6330 tw32(RCVLPC_CONFIG, 0x0181);
6331
6332 /* Calculate RDMAC_MODE setting early, we need it to determine
6333 * the RCVLPC_STATE_ENABLE mask.
6334 */
6335 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6336 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6337 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6338 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6339 RDMAC_MODE_LNGREAD_ENAB);
85e94ced
MC		 6340
6341 /* If statement applies to 5705 and 5750 PCI devices only */
6342 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6343 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6344 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 6345 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 6346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6347 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6348 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6349 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6350 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6351 }
6352 }
6353
85e94ced
MC		 6354 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6355 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6356
1da177e4
LT		 6357 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6358 rdmac_mode |= (1 << 27);
1da177e4
LT		 6359
6360 /* Receive/send statistics. */
1661394e
MC		 6361 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6362 val = tr32(RCVLPC_STATS_ENABLE);
6363 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6364 tw32(RCVLPC_STATS_ENABLE, val);
6365 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6366 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6367 val = tr32(RCVLPC_STATS_ENABLE);
6368 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6369 tw32(RCVLPC_STATS_ENABLE, val);
6370 } else {
6371 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6372 }
6373 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6374 tw32(SNDDATAI_STATSENAB, 0xffffff);
6375 tw32(SNDDATAI_STATSCTRL,
6376 (SNDDATAI_SCTRL_ENABLE |
6377 SNDDATAI_SCTRL_FASTUPD));
6378
6379 /* Setup host coalescing engine. */
6380 tw32(HOSTCC_MODE, 0);
6381 for (i = 0; i < 2000; i++) {
6382 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6383 break;
6384 udelay(10);
6385 }
6386
d244c892 6387 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6388
6389 /* set status block DMA address */
6390 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6391 ((u64) tp->status_mapping >> 32));
6392 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6393 ((u64) tp->status_mapping & 0xffffffff));
6394
6395 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6396 /* Status/statistics block address. See tg3_timer,
6397 * the tg3_periodic_fetch_stats call there, and
6398 * tg3_get_stats to see how this works for 5705/5750 chips.
6399 */
1da177e4
LT		 6400 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6401 ((u64) tp->stats_mapping >> 32));
6402 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6403 ((u64) tp->stats_mapping & 0xffffffff));
6404 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6405 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6406 }
6407
6408 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6409
6410 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6411 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6412 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6413 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6414
6415 /* Clear statistics/status block in chip, and status block in ram. */
6416 for (i = NIC_SRAM_STATS_BLK;
6417 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6418 i += sizeof(u32)) {
6419 tg3_write_mem(tp, i, 0);
6420 udelay(40);
6421 }
6422 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6423
c94e3941
MC		 6424 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6425 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6426 /* reset to prevent losing 1st rx packet intermittently */
6427 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6428 udelay(10);
6429 }
6430
1da177e4
LT		 6431 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6432 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6433 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6434 udelay(40);
6435
314fba34 6436 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6437 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6438 * register to preserve the GPIO settings for LOMs. The GPIOs,
6439 * whether used as inputs or outputs, are set by boot code after
6440 * reset.
6441 */
9d26e213 6442 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6443 u32 gpio_mask;
6444
9d26e213
MC		 6445 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6446 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6447 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6448
6449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6450 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6451 GRC_LCLCTRL_GPIO_OUTPUT3;
6452
af36e6b6
MC		 6453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6454 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6455
aaf84465 6456 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 6457 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6458
6459 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6460 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6461 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6462 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6463 }
1da177e4
LT		 6464 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6465 udelay(100);
6466
09ee929c 6467 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6468 tp->last_tag = 0;
1da177e4
LT		 6469
6470 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6471 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6472 udelay(40);
6473 }
6474
6475 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6476 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6477 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6478 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6479 WDMAC_MODE_LNGREAD_ENAB);
6480
85e94ced
MC		 6481 /* If statement applies to 5705 and 5750 PCI devices only */
6482 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6483 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6484 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6485 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6486 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6487 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6488 /* nothing */
6489 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6490 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6491 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6492 val |= WDMAC_MODE_RX_ACCEL;
6493 }
6494 }
6495
d9ab5ad1 6496 /* Enable host coalescing bug fix */
af36e6b6
MC		 6497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6498 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
d9ab5ad1
MC		 6499 val |= (1 << 29);
6500
1da177e4
LT		 6501 tw32_f(WDMAC_MODE, val);
6502 udelay(40);
6503
6504 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6505 val = tr32(TG3PCI_X_CAPS);
6506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6507 val &= ~PCIX_CAPS_BURST_MASK;
6508 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6509 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6510 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6511 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
1da177e4
LT		 6512 }
6513 tw32(TG3PCI_X_CAPS, val);
6514 }
6515
6516 tw32_f(RDMAC_MODE, rdmac_mode);
6517 udelay(40);
6518
6519 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6520 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6521 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6522 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6523 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6524 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6525 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6526 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6527 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6528 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6529 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6530 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6531
6532 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6533 err = tg3_load_5701_a0_firmware_fix(tp);
6534 if (err)
6535 return err;
6536 }
6537
1da177e4
LT		 6538 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6539 err = tg3_load_tso_firmware(tp);
6540 if (err)
6541 return err;
6542 }
1da177e4
LT		 6543
6544 tp->tx_mode = TX_MODE_ENABLE;
6545 tw32_f(MAC_TX_MODE, tp->tx_mode);
6546 udelay(100);
6547
6548 tp->rx_mode = RX_MODE_ENABLE;
af36e6b6
MC		 6549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6550 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6551
1da177e4
LT		 6552 tw32_f(MAC_RX_MODE, tp->rx_mode);
6553 udelay(10);
6554
6555 if (tp->link_config.phy_is_low_power) {
6556 tp->link_config.phy_is_low_power = 0;
6557 tp->link_config.speed = tp->link_config.orig_speed;
6558 tp->link_config.duplex = tp->link_config.orig_duplex;
6559 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6560 }
6561
6562 tp->mi_mode = MAC_MI_MODE_BASE;
6563 tw32_f(MAC_MI_MODE, tp->mi_mode);
6564 udelay(80);
6565
6566 tw32(MAC_LED_CTRL, tp->led_ctrl);
6567
6568 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6569 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6570 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6571 udelay(10);
6572 }
6573 tw32_f(MAC_RX_MODE, tp->rx_mode);
6574 udelay(10);
6575
6576 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6577 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6578 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6579 /* Set drive transmission level to 1.2V */
6580 /* only if the signal pre-emphasis bit is not set */
6581 val = tr32(MAC_SERDES_CFG);
6582 val &= 0xfffff000;
6583 val |= 0x880;
6584 tw32(MAC_SERDES_CFG, val);
6585 }
6586 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6587 tw32(MAC_SERDES_CFG, 0x616000);
6588 }
6589
6590 /* Prevent chip from dropping frames when flow control
6591 * is enabled.
6592 */
6593 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6594
6595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6596 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6597 /* Use hardware link auto-negotiation */
6598 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6599 }
6600
d4d2c558
MC		 6601 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6602 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6603 u32 tmp;
6604
6605 tmp = tr32(SERDES_RX_CTRL);
6606 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6607 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6608 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6609 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6610 }
6611
36da4d86 6612 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6613 if (err)
6614 return err;
6615
715116a1
MC		 6616 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6617 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6618 u32 tmp;
6619
6620 /* Clear CRC stats. */
569a5df8
MC		 6621 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6622 tg3_writephy(tp, MII_TG3_TEST1,
6623 tmp | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 6624 tg3_readphy(tp, 0x14, &tmp);
6625 }
6626 }
6627
6628 __tg3_set_rx_mode(tp->dev);
6629
6630 /* Initialize receive rules. */
6631 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6632 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6633 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6634 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6635
4cf78e4f 6636 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6637 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6638 limit = 8;
6639 else
6640 limit = 16;
6641 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6642 limit -= 4;
6643 switch (limit) {
6644 case 16:
6645 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6646 case 15:
6647 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6648 case 14:
6649 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6650 case 13:
6651 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6652 case 12:
6653 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6654 case 11:
6655 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6656 case 10:
6657 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6658 case 9:
6659 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6660 case 8:
6661 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6662 case 7:
6663 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6664 case 6:
6665 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6666 case 5:
6667 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6668 case 4:
6669 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6670 case 3:
6671 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6672 case 2:
6673 case 1:
6674
6675 default:
6676 break;
6677 };
6678
6679 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6680
1da177e4
LT		 6681 return 0;
6682}
6683
6684/* Called at device open time to get the chip ready for
6685 * packet processing. Invoked with tp->lock held.
6686 */
8e7a22e3 6687static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6688{
6689 int err;
6690
6691 /* Force the chip into D0. */
bc1c7567 6692 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 6693 if (err)
6694 goto out;
6695
6696 tg3_switch_clocks(tp);
6697
6698 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6699
8e7a22e3 6700 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 6701
6702out:
6703 return err;
6704}
6705
6706#define TG3_STAT_ADD32(PSTAT, REG) \
6707do { u32 __val = tr32(REG); \
6708 (PSTAT)->low += __val; \
6709 if ((PSTAT)->low < __val) \
6710 (PSTAT)->high += 1; \
6711} while (0)
6712
6713static void tg3_periodic_fetch_stats(struct tg3 *tp)
6714{
6715 struct tg3_hw_stats *sp = tp->hw_stats;
6716
6717 if (!netif_carrier_ok(tp->dev))
6718 return;
6719
6720 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6721 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6722 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6723 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6724 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6725 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6726 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6727 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6728 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6729 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6730 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6731 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6732 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6733
6734 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6735 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6736 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6737 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6738 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6739 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6740 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6741 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6742 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6743 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6744 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6745 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6746 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6747 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 6748
6749 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6750 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6751 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 6752}
6753
6754static void tg3_timer(unsigned long __opaque)
6755{
6756 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6757
f475f163
MC		 6758 if (tp->irq_sync)
6759 goto restart_timer;
6760
f47c11ee 6761 spin_lock(&tp->lock);
1da177e4 6762
fac9b83e
DM		 6763 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6764 /* All of this garbage is because when using non-tagged
6765 * IRQ status the mailbox/status_block protocol the chip
6766 * uses with the cpu is race prone.
6767 */
6768 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6769 tw32(GRC_LOCAL_CTRL,
6770 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6771 } else {
6772 tw32(HOSTCC_MODE, tp->coalesce_mode |
6773 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6774 }
1da177e4 6775
fac9b83e
DM		 6776 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6777 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6778 spin_unlock(&tp->lock);
fac9b83e
DM		 6779 schedule_work(&tp->reset_task);
6780 return;
6781 }
1da177e4
LT		 6782 }
6783
1da177e4
LT		 6784 /* This part only runs once per second. */
6785 if (!--tp->timer_counter) {
fac9b83e
DM		 6786 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6787 tg3_periodic_fetch_stats(tp);
6788
1da177e4
LT		 6789 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6790 u32 mac_stat;
6791 int phy_event;
6792
6793 mac_stat = tr32(MAC_STATUS);
6794
6795 phy_event = 0;
6796 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6797 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6798 phy_event = 1;
6799 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6800 phy_event = 1;
6801
6802 if (phy_event)
6803 tg3_setup_phy(tp, 0);
6804 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6805 u32 mac_stat = tr32(MAC_STATUS);
6806 int need_setup = 0;
6807
6808 if (netif_carrier_ok(tp->dev) &&
6809 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6810 need_setup = 1;
6811 }
6812 if (! netif_carrier_ok(tp->dev) &&
6813 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6814 MAC_STATUS_SIGNAL_DET))) {
6815 need_setup = 1;
6816 }
6817 if (need_setup) {
3d3ebe74
MC		 6818 if (!tp->serdes_counter) {
6819 tw32_f(MAC_MODE,
6820 (tp->mac_mode &
6821 ~MAC_MODE_PORT_MODE_MASK));
6822 udelay(40);
6823 tw32_f(MAC_MODE, tp->mac_mode);
6824 udelay(40);
6825 }
1da177e4
LT		 6826 tg3_setup_phy(tp, 0);
6827 }
747e8f8b
MC		 6828 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6829 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6830
6831 tp->timer_counter = tp->timer_multiplier;
6832 }
6833
130b8e4d
MC		 6834 /* Heartbeat is only sent once every 2 seconds.
6835 *
6836 * The heartbeat is to tell the ASF firmware that the host
6837 * driver is still alive. In the event that the OS crashes,
6838 * ASF needs to reset the hardware to free up the FIFO space
6839 * that may be filled with rx packets destined for the host.
6840 * If the FIFO is full, ASF will no longer function properly.
6841 *
6842 * Unintended resets have been reported on real time kernels
6843 * where the timer doesn't run on time. Netpoll will also have
6844 * same problem.
6845 *
6846 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6847 * to check the ring condition when the heartbeat is expiring
6848 * before doing the reset. This will prevent most unintended
6849 * resets.
6850 */
1da177e4
LT		 6851 if (!--tp->asf_counter) {
6852 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6853 u32 val;
6854
bbadf503 6855 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 6856 FWCMD_NICDRV_ALIVE3);
bbadf503 6857 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 6858 /* 5 seconds timeout */
bbadf503 6859 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6860 val = tr32(GRC_RX_CPU_EVENT);
6861 val |= (1 << 14);
6862 tw32(GRC_RX_CPU_EVENT, val);
6863 }
6864 tp->asf_counter = tp->asf_multiplier;
6865 }
6866
f47c11ee 6867 spin_unlock(&tp->lock);
1da177e4 6868
f475f163 6869restart_timer:
1da177e4
LT		 6870 tp->timer.expires = jiffies + tp->timer_offset;
6871 add_timer(&tp->timer);
6872}
6873
81789ef5 6874static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 6875{
7d12e780 6876 irq_handler_t fn;
fcfa0a32
MC		 6877 unsigned long flags;
6878 struct net_device *dev = tp->dev;
6879
6880 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6881 fn = tg3_msi;
6882 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6883 fn = tg3_msi_1shot;
1fb9df5d 6884 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6885 } else {
6886 fn = tg3_interrupt;
6887 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6888 fn = tg3_interrupt_tagged;
1fb9df5d 6889 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6890 }
6891 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6892}
6893
7938109f
MC		 6894static int tg3_test_interrupt(struct tg3 *tp)
6895{
6896 struct net_device *dev = tp->dev;
b16250e3 6897 int err, i, intr_ok = 0;
7938109f 6898
d4bc3927
MC		 6899 if (!netif_running(dev))
6900 return -ENODEV;
6901
7938109f
MC		 6902 tg3_disable_ints(tp);
6903
6904 free_irq(tp->pdev->irq, dev);
6905
6906 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 6907 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6908 if (err)
6909 return err;
6910
38f3843e 6911 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6912 tg3_enable_ints(tp);
6913
6914 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6915 HOSTCC_MODE_NOW);
6916
6917 for (i = 0; i < 5; i++) {
b16250e3
MC		 6918 u32 int_mbox, misc_host_ctrl;
6919
09ee929c
MC		 6920 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6921 TG3_64BIT_REG_LOW);
b16250e3
MC		 6922 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6923
6924 if ((int_mbox != 0) ||
6925 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6926 intr_ok = 1;
7938109f 6927 break;
b16250e3
MC		 6928 }
6929
7938109f
MC		 6930 msleep(10);
6931 }
6932
6933 tg3_disable_ints(tp);
6934
6935 free_irq(tp->pdev->irq, dev);
6aa20a22 6936
fcfa0a32 6937 err = tg3_request_irq(tp);
7938109f
MC		 6938
6939 if (err)
6940 return err;
6941
b16250e3 6942 if (intr_ok)
7938109f
MC		 6943 return 0;
6944
6945 return -EIO;
6946}
6947
6948/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6949 * successfully restored
6950 */
6951static int tg3_test_msi(struct tg3 *tp)
6952{
6953 struct net_device *dev = tp->dev;
6954 int err;
6955 u16 pci_cmd;
6956
6957 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6958 return 0;
6959
6960 /* Turn off SERR reporting in case MSI terminates with Master
6961 * Abort.
6962 */
6963 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6964 pci_write_config_word(tp->pdev, PCI_COMMAND,
6965 pci_cmd & ~PCI_COMMAND_SERR);
6966
6967 err = tg3_test_interrupt(tp);
6968
6969 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6970
6971 if (!err)
6972 return 0;
6973
6974 /* other failures */
6975 if (err != -EIO)
6976 return err;
6977
6978 /* MSI test failed, go back to INTx mode */
6979 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6980 "switching to INTx mode. Please report this failure to "
6981 "the PCI maintainer and include system chipset information.\n",
6982 tp->dev->name);
6983
6984 free_irq(tp->pdev->irq, dev);
6985 pci_disable_msi(tp->pdev);
6986
6987 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6988
fcfa0a32 6989 err = tg3_request_irq(tp);
7938109f
MC		 6990 if (err)
6991 return err;
6992
6993 /* Need to reset the chip because the MSI cycle may have terminated
6994 * with Master Abort.
6995 */
f47c11ee 6996 tg3_full_lock(tp, 1);
7938109f 6997
944d980e 6998 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 6999 err = tg3_init_hw(tp, 1);
7938109f 7000
f47c11ee 7001 tg3_full_unlock(tp);
7938109f
MC		 7002
7003 if (err)
7004 free_irq(tp->pdev->irq, dev);
7005
7006 return err;
7007}
7008
1da177e4
LT		 7009static int tg3_open(struct net_device *dev)
7010{
7011 struct tg3 *tp = netdev_priv(dev);
7012 int err;
7013
c49a1561
MC		 7014 netif_carrier_off(tp->dev);
7015
f47c11ee 7016 tg3_full_lock(tp, 0);
1da177e4 7017
bc1c7567 7018 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 7019 if (err) {
7020 tg3_full_unlock(tp);
bc1c7567 7021 return err;
12862086 7022 }
bc1c7567 7023
1da177e4
LT		 7024 tg3_disable_ints(tp);
7025 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7026
f47c11ee 7027 tg3_full_unlock(tp);
1da177e4
LT		 7028
7029 /* The placement of this call is tied
7030 * to the setup and use of Host TX descriptors.
7031 */
7032 err = tg3_alloc_consistent(tp);
7033 if (err)
7034 return err;
7035
7544b097 7036 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7037 /* All MSI supporting chips should support tagged
7038 * status. Assert that this is the case.
7039 */
7040 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7041 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7042 "Not using MSI.\n", tp->dev->name);
7043 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7044 u32 msi_mode;
7045
7046 msi_mode = tr32(MSGINT_MODE);
7047 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7048 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7049 }
7050 }
fcfa0a32 7051 err = tg3_request_irq(tp);
1da177e4
LT		 7052
7053 if (err) {
88b06bc2
MC		 7054 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7055 pci_disable_msi(tp->pdev);
7056 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7057 }
1da177e4
LT		 7058 tg3_free_consistent(tp);
7059 return err;
7060 }
7061
f47c11ee 7062 tg3_full_lock(tp, 0);
1da177e4 7063
8e7a22e3 7064 err = tg3_init_hw(tp, 1);
1da177e4 7065 if (err) {
944d980e 7066 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7067 tg3_free_rings(tp);
7068 } else {
fac9b83e
DM		 7069 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7070 tp->timer_offset = HZ;
7071 else
7072 tp->timer_offset = HZ / 10;
7073
7074 BUG_ON(tp->timer_offset > HZ);
7075 tp->timer_counter = tp->timer_multiplier =
7076 (HZ / tp->timer_offset);
7077 tp->asf_counter = tp->asf_multiplier =
28fbef78 7078 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7079
7080 init_timer(&tp->timer);
7081 tp->timer.expires = jiffies + tp->timer_offset;
7082 tp->timer.data = (unsigned long) tp;
7083 tp->timer.function = tg3_timer;
1da177e4
LT		 7084 }
7085
f47c11ee 7086 tg3_full_unlock(tp);
1da177e4
LT		 7087
7088 if (err) {
88b06bc2
MC		 7089 free_irq(tp->pdev->irq, dev);
7090 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7091 pci_disable_msi(tp->pdev);
7092 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7093 }
1da177e4
LT		 7094 tg3_free_consistent(tp);
7095 return err;
7096 }
7097
7938109f
MC		 7098 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7099 err = tg3_test_msi(tp);
fac9b83e 7100
7938109f 7101 if (err) {
f47c11ee 7102 tg3_full_lock(tp, 0);
7938109f
MC		 7103
7104 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7105 pci_disable_msi(tp->pdev);
7106 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7107 }
944d980e 7108 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7109 tg3_free_rings(tp);
7110 tg3_free_consistent(tp);
7111
f47c11ee 7112 tg3_full_unlock(tp);
7938109f
MC		 7113
7114 return err;
7115 }
fcfa0a32
MC		 7116
7117 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7118 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7119 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7120
b5d3772c
MC		 7121 tw32(PCIE_TRANSACTION_CFG,
7122 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7123 }
7124 }
7938109f
MC		 7125 }
7126
f47c11ee 7127 tg3_full_lock(tp, 0);
1da177e4 7128
7938109f
MC		 7129 add_timer(&tp->timer);
7130 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7131 tg3_enable_ints(tp);
7132
f47c11ee 7133 tg3_full_unlock(tp);
1da177e4
LT		 7134
7135 netif_start_queue(dev);
7136
7137 return 0;
7138}
7139
7140#if 0
7141/*static*/ void tg3_dump_state(struct tg3 *tp)
7142{
7143 u32 val32, val32_2, val32_3, val32_4, val32_5;
7144 u16 val16;
7145 int i;
7146
7147 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7148 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7149 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7150 val16, val32);
7151
7152 /* MAC block */
7153 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7154 tr32(MAC_MODE), tr32(MAC_STATUS));
7155 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7156 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7157 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7158 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7159 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7160 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7161
7162 /* Send data initiator control block */
7163 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7164 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7165 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7166 tr32(SNDDATAI_STATSCTRL));
7167
7168 /* Send data completion control block */
7169 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7170
7171 /* Send BD ring selector block */
7172 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7173 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7174
7175 /* Send BD initiator control block */
7176 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7177 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7178
7179 /* Send BD completion control block */
7180 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7181
7182 /* Receive list placement control block */
7183 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7184 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7185 printk(" RCVLPC_STATSCTRL[%08x]\n",
7186 tr32(RCVLPC_STATSCTRL));
7187
7188 /* Receive data and receive BD initiator control block */
7189 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7190 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7191
7192 /* Receive data completion control block */
7193 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7194 tr32(RCVDCC_MODE));
7195
7196 /* Receive BD initiator control block */
7197 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7198 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7199
7200 /* Receive BD completion control block */
7201 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7202 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7203
7204 /* Receive list selector control block */
7205 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7206 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7207
7208 /* Mbuf cluster free block */
7209 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7210 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7211
7212 /* Host coalescing control block */
7213 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7214 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7215 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7216 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7217 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7218 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7219 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7220 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7221 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7222 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7223 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7224 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7225
7226 /* Memory arbiter control block */
7227 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7228 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7229
7230 /* Buffer manager control block */
7231 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7232 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7233 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7234 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7235 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7236 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7237 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7238 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7239
7240 /* Read DMA control block */
7241 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7242 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7243
7244 /* Write DMA control block */
7245 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7246 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7247
7248 /* DMA completion block */
7249 printk("DEBUG: DMAC_MODE[%08x]\n",
7250 tr32(DMAC_MODE));
7251
7252 /* GRC block */
7253 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7254 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7255 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7256 tr32(GRC_LOCAL_CTRL));
7257
7258 /* TG3_BDINFOs */
7259 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7260 tr32(RCVDBDI_JUMBO_BD + 0x0),
7261 tr32(RCVDBDI_JUMBO_BD + 0x4),
7262 tr32(RCVDBDI_JUMBO_BD + 0x8),
7263 tr32(RCVDBDI_JUMBO_BD + 0xc));
7264 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7265 tr32(RCVDBDI_STD_BD + 0x0),
7266 tr32(RCVDBDI_STD_BD + 0x4),
7267 tr32(RCVDBDI_STD_BD + 0x8),
7268 tr32(RCVDBDI_STD_BD + 0xc));
7269 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7270 tr32(RCVDBDI_MINI_BD + 0x0),
7271 tr32(RCVDBDI_MINI_BD + 0x4),
7272 tr32(RCVDBDI_MINI_BD + 0x8),
7273 tr32(RCVDBDI_MINI_BD + 0xc));
7274
7275 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7276 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7277 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7278 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7279 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7280 val32, val32_2, val32_3, val32_4);
7281
7282 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7283 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7284 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7285 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7286 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7287 val32, val32_2, val32_3, val32_4);
7288
7289 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7290 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7291 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7292 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7293 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7294 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7295 val32, val32_2, val32_3, val32_4, val32_5);
7296
7297 /* SW status block */
7298 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7299 tp->hw_status->status,
7300 tp->hw_status->status_tag,
7301 tp->hw_status->rx_jumbo_consumer,
7302 tp->hw_status->rx_consumer,
7303 tp->hw_status->rx_mini_consumer,
7304 tp->hw_status->idx[0].rx_producer,
7305 tp->hw_status->idx[0].tx_consumer);
7306
7307 /* SW statistics block */
7308 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7309 ((u32 *)tp->hw_stats)[0],
7310 ((u32 *)tp->hw_stats)[1],
7311 ((u32 *)tp->hw_stats)[2],
7312 ((u32 *)tp->hw_stats)[3]);
7313
7314 /* Mailboxes */
7315 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7316 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7317 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7318 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7319 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7320
7321 /* NIC side send descriptors. */
7322 for (i = 0; i < 6; i++) {
7323 unsigned long txd;
7324
7325 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7326 + (i * sizeof(struct tg3_tx_buffer_desc));
7327 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7328 i,
7329 readl(txd + 0x0), readl(txd + 0x4),
7330 readl(txd + 0x8), readl(txd + 0xc));
7331 }
7332
7333 /* NIC side RX descriptors. */
7334 for (i = 0; i < 6; i++) {
7335 unsigned long rxd;
7336
7337 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7338 + (i * sizeof(struct tg3_rx_buffer_desc));
7339 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7340 i,
7341 readl(rxd + 0x0), readl(rxd + 0x4),
7342 readl(rxd + 0x8), readl(rxd + 0xc));
7343 rxd += (4 * sizeof(u32));
7344 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7345 i,
7346 readl(rxd + 0x0), readl(rxd + 0x4),
7347 readl(rxd + 0x8), readl(rxd + 0xc));
7348 }
7349
7350 for (i = 0; i < 6; i++) {
7351 unsigned long rxd;
7352
7353 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7354 + (i * sizeof(struct tg3_rx_buffer_desc));
7355 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7356 i,
7357 readl(rxd + 0x0), readl(rxd + 0x4),
7358 readl(rxd + 0x8), readl(rxd + 0xc));
7359 rxd += (4 * sizeof(u32));
7360 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7361 i,
7362 readl(rxd + 0x0), readl(rxd + 0x4),
7363 readl(rxd + 0x8), readl(rxd + 0xc));
7364 }
7365}
7366#endif
7367
7368static struct net_device_stats *tg3_get_stats(struct net_device *);
7369static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7370
7371static int tg3_close(struct net_device *dev)
7372{
7373 struct tg3 *tp = netdev_priv(dev);
7374
7faa006f
MC		 7375 /* Calling flush_scheduled_work() may deadlock because
7376 * linkwatch_event() may be on the workqueue and it will try to get
7377 * the rtnl_lock which we are holding.
7378 */
7379 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7380 msleep(1);
7381
1da177e4
LT		 7382 netif_stop_queue(dev);
7383
7384 del_timer_sync(&tp->timer);
7385
f47c11ee 7386 tg3_full_lock(tp, 1);
1da177e4
LT		 7387#if 0
7388 tg3_dump_state(tp);
7389#endif
7390
7391 tg3_disable_ints(tp);
7392
944d980e 7393 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 7394 tg3_free_rings(tp);
5cf64b8a 7395 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 7396
f47c11ee 7397 tg3_full_unlock(tp);
1da177e4 7398
88b06bc2
MC		 7399 free_irq(tp->pdev->irq, dev);
7400 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7401 pci_disable_msi(tp->pdev);
7402 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7403 }
1da177e4
LT		 7404
7405 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7406 sizeof(tp->net_stats_prev));
7407 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7408 sizeof(tp->estats_prev));
7409
7410 tg3_free_consistent(tp);
7411
bc1c7567
MC		 7412 tg3_set_power_state(tp, PCI_D3hot);
7413
7414 netif_carrier_off(tp->dev);
7415
1da177e4
LT		 7416 return 0;
7417}
7418
7419static inline unsigned long get_stat64(tg3_stat64_t *val)
7420{
7421 unsigned long ret;
7422
7423#if (BITS_PER_LONG == 32)
7424 ret = val->low;
7425#else
7426 ret = ((u64)val->high << 32) | ((u64)val->low);
7427#endif
7428 return ret;
7429}
7430
7431static unsigned long calc_crc_errors(struct tg3 *tp)
7432{
7433 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7434
7435 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7436 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7437 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7438 u32 val;
7439
f47c11ee 7440 spin_lock_bh(&tp->lock);
569a5df8
MC		 7441 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7442 tg3_writephy(tp, MII_TG3_TEST1,
7443 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7444 tg3_readphy(tp, 0x14, &val);
7445 } else
7446 val = 0;
f47c11ee 7447 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7448
7449 tp->phy_crc_errors += val;
7450
7451 return tp->phy_crc_errors;
7452 }
7453
7454 return get_stat64(&hw_stats->rx_fcs_errors);
7455}
7456
7457#define ESTAT_ADD(member) \
7458 estats->member = old_estats->member + \
7459 get_stat64(&hw_stats->member)
7460
7461static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7462{
7463 struct tg3_ethtool_stats *estats = &tp->estats;
7464 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7465 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7466
7467 if (!hw_stats)
7468 return old_estats;
7469
7470 ESTAT_ADD(rx_octets);
7471 ESTAT_ADD(rx_fragments);
7472 ESTAT_ADD(rx_ucast_packets);
7473 ESTAT_ADD(rx_mcast_packets);
7474 ESTAT_ADD(rx_bcast_packets);
7475 ESTAT_ADD(rx_fcs_errors);
7476 ESTAT_ADD(rx_align_errors);
7477 ESTAT_ADD(rx_xon_pause_rcvd);
7478 ESTAT_ADD(rx_xoff_pause_rcvd);
7479 ESTAT_ADD(rx_mac_ctrl_rcvd);
7480 ESTAT_ADD(rx_xoff_entered);
7481 ESTAT_ADD(rx_frame_too_long_errors);
7482 ESTAT_ADD(rx_jabbers);
7483 ESTAT_ADD(rx_undersize_packets);
7484 ESTAT_ADD(rx_in_length_errors);
7485 ESTAT_ADD(rx_out_length_errors);
7486 ESTAT_ADD(rx_64_or_less_octet_packets);
7487 ESTAT_ADD(rx_65_to_127_octet_packets);
7488 ESTAT_ADD(rx_128_to_255_octet_packets);
7489 ESTAT_ADD(rx_256_to_511_octet_packets);
7490 ESTAT_ADD(rx_512_to_1023_octet_packets);
7491 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7492 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7493 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7494 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7495 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7496
7497 ESTAT_ADD(tx_octets);
7498 ESTAT_ADD(tx_collisions);
7499 ESTAT_ADD(tx_xon_sent);
7500 ESTAT_ADD(tx_xoff_sent);
7501 ESTAT_ADD(tx_flow_control);
7502 ESTAT_ADD(tx_mac_errors);
7503 ESTAT_ADD(tx_single_collisions);
7504 ESTAT_ADD(tx_mult_collisions);
7505 ESTAT_ADD(tx_deferred);
7506 ESTAT_ADD(tx_excessive_collisions);
7507 ESTAT_ADD(tx_late_collisions);
7508 ESTAT_ADD(tx_collide_2times);
7509 ESTAT_ADD(tx_collide_3times);
7510 ESTAT_ADD(tx_collide_4times);
7511 ESTAT_ADD(tx_collide_5times);
7512 ESTAT_ADD(tx_collide_6times);
7513 ESTAT_ADD(tx_collide_7times);
7514 ESTAT_ADD(tx_collide_8times);
7515 ESTAT_ADD(tx_collide_9times);
7516 ESTAT_ADD(tx_collide_10times);
7517 ESTAT_ADD(tx_collide_11times);
7518 ESTAT_ADD(tx_collide_12times);
7519 ESTAT_ADD(tx_collide_13times);
7520 ESTAT_ADD(tx_collide_14times);
7521 ESTAT_ADD(tx_collide_15times);
7522 ESTAT_ADD(tx_ucast_packets);
7523 ESTAT_ADD(tx_mcast_packets);
7524 ESTAT_ADD(tx_bcast_packets);
7525 ESTAT_ADD(tx_carrier_sense_errors);
7526 ESTAT_ADD(tx_discards);
7527 ESTAT_ADD(tx_errors);
7528
7529 ESTAT_ADD(dma_writeq_full);
7530 ESTAT_ADD(dma_write_prioq_full);
7531 ESTAT_ADD(rxbds_empty);
7532 ESTAT_ADD(rx_discards);
7533 ESTAT_ADD(rx_errors);
7534 ESTAT_ADD(rx_threshold_hit);
7535
7536 ESTAT_ADD(dma_readq_full);
7537 ESTAT_ADD(dma_read_prioq_full);
7538 ESTAT_ADD(tx_comp_queue_full);
7539
7540 ESTAT_ADD(ring_set_send_prod_index);
7541 ESTAT_ADD(ring_status_update);
7542 ESTAT_ADD(nic_irqs);
7543 ESTAT_ADD(nic_avoided_irqs);
7544 ESTAT_ADD(nic_tx_threshold_hit);
7545
7546 return estats;
7547}
7548
7549static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7550{
7551 struct tg3 *tp = netdev_priv(dev);
7552 struct net_device_stats *stats = &tp->net_stats;
7553 struct net_device_stats *old_stats = &tp->net_stats_prev;
7554 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7555
7556 if (!hw_stats)
7557 return old_stats;
7558
7559 stats->rx_packets = old_stats->rx_packets +
7560 get_stat64(&hw_stats->rx_ucast_packets) +
7561 get_stat64(&hw_stats->rx_mcast_packets) +
7562 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7563
1da177e4
LT		 7564 stats->tx_packets = old_stats->tx_packets +
7565 get_stat64(&hw_stats->tx_ucast_packets) +
7566 get_stat64(&hw_stats->tx_mcast_packets) +
7567 get_stat64(&hw_stats->tx_bcast_packets);
7568
7569 stats->rx_bytes = old_stats->rx_bytes +
7570 get_stat64(&hw_stats->rx_octets);
7571 stats->tx_bytes = old_stats->tx_bytes +
7572 get_stat64(&hw_stats->tx_octets);
7573
7574 stats->rx_errors = old_stats->rx_errors +
4f63b877 7575 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7576 stats->tx_errors = old_stats->tx_errors +
7577 get_stat64(&hw_stats->tx_errors) +
7578 get_stat64(&hw_stats->tx_mac_errors) +
7579 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7580 get_stat64(&hw_stats->tx_discards);
7581
7582 stats->multicast = old_stats->multicast +
7583 get_stat64(&hw_stats->rx_mcast_packets);
7584 stats->collisions = old_stats->collisions +
7585 get_stat64(&hw_stats->tx_collisions);
7586
7587 stats->rx_length_errors = old_stats->rx_length_errors +
7588 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7589 get_stat64(&hw_stats->rx_undersize_packets);
7590
7591 stats->rx_over_errors = old_stats->rx_over_errors +
7592 get_stat64(&hw_stats->rxbds_empty);
7593 stats->rx_frame_errors = old_stats->rx_frame_errors +
7594 get_stat64(&hw_stats->rx_align_errors);
7595 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7596 get_stat64(&hw_stats->tx_discards);
7597 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7598 get_stat64(&hw_stats->tx_carrier_sense_errors);
7599
7600 stats->rx_crc_errors = old_stats->rx_crc_errors +
7601 calc_crc_errors(tp);
7602
4f63b877
JL		 7603 stats->rx_missed_errors = old_stats->rx_missed_errors +
7604 get_stat64(&hw_stats->rx_discards);
7605
1da177e4
LT		 7606 return stats;
7607}
7608
7609static inline u32 calc_crc(unsigned char *buf, int len)
7610{
7611 u32 reg;
7612 u32 tmp;
7613 int j, k;
7614
7615 reg = 0xffffffff;
7616
7617 for (j = 0; j < len; j++) {
7618 reg ^= buf[j];
7619
7620 for (k = 0; k < 8; k++) {
7621 tmp = reg & 0x01;
7622
7623 reg >>= 1;
7624
7625 if (tmp) {
7626 reg ^= 0xedb88320;
7627 }
7628 }
7629 }
7630
7631 return ~reg;
7632}
7633
7634static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7635{
7636 /* accept or reject all multicast frames */
7637 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7638 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7639 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7640 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7641}
7642
7643static void __tg3_set_rx_mode(struct net_device *dev)
7644{
7645 struct tg3 *tp = netdev_priv(dev);
7646 u32 rx_mode;
7647
7648 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7649 RX_MODE_KEEP_VLAN_TAG);
7650
7651 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7652 * flag clear.
7653 */
7654#if TG3_VLAN_TAG_USED
7655 if (!tp->vlgrp &&
7656 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7657 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7658#else
7659 /* By definition, VLAN is disabled always in this
7660 * case.
7661 */
7662 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7663 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7664#endif
7665
7666 if (dev->flags & IFF_PROMISC) {
7667 /* Promiscuous mode. */
7668 rx_mode |= RX_MODE_PROMISC;
7669 } else if (dev->flags & IFF_ALLMULTI) {
7670 /* Accept all multicast. */
7671 tg3_set_multi (tp, 1);
7672 } else if (dev->mc_count < 1) {
7673 /* Reject all multicast. */
7674 tg3_set_multi (tp, 0);
7675 } else {
7676 /* Accept one or more multicast(s). */
7677 struct dev_mc_list *mclist;
7678 unsigned int i;
7679 u32 mc_filter[4] = { 0, };
7680 u32 regidx;
7681 u32 bit;
7682 u32 crc;
7683
7684 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7685 i++, mclist = mclist->next) {
7686
7687 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7688 bit = ~crc & 0x7f;
7689 regidx = (bit & 0x60) >> 5;
7690 bit &= 0x1f;
7691 mc_filter[regidx] |= (1 << bit);
7692 }
7693
7694 tw32(MAC_HASH_REG_0, mc_filter[0]);
7695 tw32(MAC_HASH_REG_1, mc_filter[1]);
7696 tw32(MAC_HASH_REG_2, mc_filter[2]);
7697 tw32(MAC_HASH_REG_3, mc_filter[3]);
7698 }
7699
7700 if (rx_mode != tp->rx_mode) {
7701 tp->rx_mode = rx_mode;
7702 tw32_f(MAC_RX_MODE, rx_mode);
7703 udelay(10);
7704 }
7705}
7706
7707static void tg3_set_rx_mode(struct net_device *dev)
7708{
7709 struct tg3 *tp = netdev_priv(dev);
7710
e75f7c90
MC		 7711 if (!netif_running(dev))
7712 return;
7713
f47c11ee 7714 tg3_full_lock(tp, 0);
1da177e4 7715 __tg3_set_rx_mode(dev);
f47c11ee 7716 tg3_full_unlock(tp);
1da177e4
LT		 7717}
7718
7719#define TG3_REGDUMP_LEN (32 * 1024)
7720
7721static int tg3_get_regs_len(struct net_device *dev)
7722{
7723 return TG3_REGDUMP_LEN;
7724}
7725
7726static void tg3_get_regs(struct net_device *dev,
7727 struct ethtool_regs *regs, void *_p)
7728{
7729 u32 *p = _p;
7730 struct tg3 *tp = netdev_priv(dev);
7731 u8 *orig_p = _p;
7732 int i;
7733
7734 regs->version = 0;
7735
7736 memset(p, 0, TG3_REGDUMP_LEN);
7737
bc1c7567
MC		 7738 if (tp->link_config.phy_is_low_power)
7739 return;
7740
f47c11ee 7741 tg3_full_lock(tp, 0);
1da177e4
LT		 7742
7743#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7744#define GET_REG32_LOOP(base,len) \
7745do { p = (u32 *)(orig_p + (base)); \
7746 for (i = 0; i < len; i += 4) \
7747 __GET_REG32((base) + i); \
7748} while (0)
7749#define GET_REG32_1(reg) \
7750do { p = (u32 *)(orig_p + (reg)); \
7751 __GET_REG32((reg)); \
7752} while (0)
7753
7754 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7755 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7756 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7757 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7758 GET_REG32_1(SNDDATAC_MODE);
7759 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7760 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7761 GET_REG32_1(SNDBDC_MODE);
7762 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7763 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7764 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7765 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7766 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7767 GET_REG32_1(RCVDCC_MODE);
7768 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7769 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7770 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7771 GET_REG32_1(MBFREE_MODE);
7772 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7773 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7774 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7775 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7776 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 7777 GET_REG32_1(RX_CPU_MODE);
7778 GET_REG32_1(RX_CPU_STATE);
7779 GET_REG32_1(RX_CPU_PGMCTR);
7780 GET_REG32_1(RX_CPU_HWBKPT);
7781 GET_REG32_1(TX_CPU_MODE);
7782 GET_REG32_1(TX_CPU_STATE);
7783 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 7784 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7785 GET_REG32_LOOP(FTQ_RESET, 0x120);
7786 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7787 GET_REG32_1(DMAC_MODE);
7788 GET_REG32_LOOP(GRC_MODE, 0x4c);
7789 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7790 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7791
7792#undef __GET_REG32
7793#undef GET_REG32_LOOP
7794#undef GET_REG32_1
7795
f47c11ee 7796 tg3_full_unlock(tp);
1da177e4
LT		 7797}
7798
7799static int tg3_get_eeprom_len(struct net_device *dev)
7800{
7801 struct tg3 *tp = netdev_priv(dev);
7802
7803 return tp->nvram_size;
7804}
7805
7806static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 7807static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 7808
7809static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7810{
7811 struct tg3 *tp = netdev_priv(dev);
7812 int ret;
7813 u8 *pd;
7814 u32 i, offset, len, val, b_offset, b_count;
7815
bc1c7567
MC		 7816 if (tp->link_config.phy_is_low_power)
7817 return -EAGAIN;
7818
1da177e4
LT		 7819 offset = eeprom->offset;
7820 len = eeprom->len;
7821 eeprom->len = 0;
7822
7823 eeprom->magic = TG3_EEPROM_MAGIC;
7824
7825 if (offset & 3) {
7826 /* adjustments to start on required 4 byte boundary */
7827 b_offset = offset & 3;
7828 b_count = 4 - b_offset;
7829 if (b_count > len) {
7830 /* i.e. offset=1 len=2 */
7831 b_count = len;
7832 }
7833 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7834 if (ret)
7835 return ret;
7836 val = cpu_to_le32(val);
7837 memcpy(data, ((char*)&val) + b_offset, b_count);
7838 len -= b_count;
7839 offset += b_count;
7840 eeprom->len += b_count;
7841 }
7842
7843 /* read bytes upto the last 4 byte boundary */
7844 pd = &data[eeprom->len];
7845 for (i = 0; i < (len - (len & 3)); i += 4) {
7846 ret = tg3_nvram_read(tp, offset + i, &val);
7847 if (ret) {
7848 eeprom->len += i;
7849 return ret;
7850 }
7851 val = cpu_to_le32(val);
7852 memcpy(pd + i, &val, 4);
7853 }
7854 eeprom->len += i;
7855
7856 if (len & 3) {
7857 /* read last bytes not ending on 4 byte boundary */
7858 pd = &data[eeprom->len];
7859 b_count = len & 3;
7860 b_offset = offset + len - b_count;
7861 ret = tg3_nvram_read(tp, b_offset, &val);
7862 if (ret)
7863 return ret;
7864 val = cpu_to_le32(val);
7865 memcpy(pd, ((char*)&val), b_count);
7866 eeprom->len += b_count;
7867 }
7868 return 0;
7869}
7870
6aa20a22 7871static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 7872
7873static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7874{
7875 struct tg3 *tp = netdev_priv(dev);
7876 int ret;
7877 u32 offset, len, b_offset, odd_len, start, end;
7878 u8 *buf;
7879
bc1c7567
MC		 7880 if (tp->link_config.phy_is_low_power)
7881 return -EAGAIN;
7882
1da177e4
LT		 7883 if (eeprom->magic != TG3_EEPROM_MAGIC)
7884 return -EINVAL;
7885
7886 offset = eeprom->offset;
7887 len = eeprom->len;
7888
7889 if ((b_offset = (offset & 3))) {
7890 /* adjustments to start on required 4 byte boundary */
7891 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7892 if (ret)
7893 return ret;
7894 start = cpu_to_le32(start);
7895 len += b_offset;
7896 offset &= ~3;
1c8594b4
MC		 7897 if (len < 4)
7898 len = 4;
1da177e4
LT		 7899 }
7900
7901 odd_len = 0;
1c8594b4 7902 if (len & 3) {
1da177e4
LT		 7903 /* adjustments to end on required 4 byte boundary */
7904 odd_len = 1;
7905 len = (len + 3) & ~3;
7906 ret = tg3_nvram_read(tp, offset+len-4, &end);
7907 if (ret)
7908 return ret;
7909 end = cpu_to_le32(end);
7910 }
7911
7912 buf = data;
7913 if (b_offset || odd_len) {
7914 buf = kmalloc(len, GFP_KERNEL);
7915 if (buf == 0)
7916 return -ENOMEM;
7917 if (b_offset)
7918 memcpy(buf, &start, 4);
7919 if (odd_len)
7920 memcpy(buf+len-4, &end, 4);
7921 memcpy(buf + b_offset, data, eeprom->len);
7922 }
7923
7924 ret = tg3_nvram_write_block(tp, offset, len, buf);
7925
7926 if (buf != data)
7927 kfree(buf);
7928
7929 return ret;
7930}
7931
7932static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7933{
7934 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7935
1da177e4
LT		 7936 cmd->supported = (SUPPORTED_Autoneg);
7937
7938 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7939 cmd->supported |= (SUPPORTED_1000baseT_Half |
7940 SUPPORTED_1000baseT_Full);
7941
ef348144 7942 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 7943 cmd->supported |= (SUPPORTED_100baseT_Half |
7944 SUPPORTED_100baseT_Full |
7945 SUPPORTED_10baseT_Half |
7946 SUPPORTED_10baseT_Full |
7947 SUPPORTED_MII);
ef348144
KK		 7948 cmd->port = PORT_TP;
7949 } else {
1da177e4 7950 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 7951 cmd->port = PORT_FIBRE;
7952 }
6aa20a22 7953
1da177e4
LT		 7954 cmd->advertising = tp->link_config.advertising;
7955 if (netif_running(dev)) {
7956 cmd->speed = tp->link_config.active_speed;
7957 cmd->duplex = tp->link_config.active_duplex;
7958 }
1da177e4
LT		 7959 cmd->phy_address = PHY_ADDR;
7960 cmd->transceiver = 0;
7961 cmd->autoneg = tp->link_config.autoneg;
7962 cmd->maxtxpkt = 0;
7963 cmd->maxrxpkt = 0;
7964 return 0;
7965}
6aa20a22 7966
1da177e4
LT		 7967static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7968{
7969 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 7970
7971 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7972 /* These are the only valid advertisement bits allowed. */
7973 if (cmd->autoneg == AUTONEG_ENABLE &&
7974 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7975 ADVERTISED_1000baseT_Full |
7976 ADVERTISED_Autoneg |
7977 ADVERTISED_FIBRE)))
7978 return -EINVAL;
37ff238d
MC		 7979 /* Fiber can only do SPEED_1000. */
7980 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7981 (cmd->speed != SPEED_1000))
7982 return -EINVAL;
7983 /* Copper cannot force SPEED_1000. */
7984 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7985 (cmd->speed == SPEED_1000))
7986 return -EINVAL;
7987 else if ((cmd->speed == SPEED_1000) &&
7988 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7989 return -EINVAL;
1da177e4 7990
f47c11ee 7991 tg3_full_lock(tp, 0);
1da177e4
LT		 7992
7993 tp->link_config.autoneg = cmd->autoneg;
7994 if (cmd->autoneg == AUTONEG_ENABLE) {
7995 tp->link_config.advertising = cmd->advertising;
7996 tp->link_config.speed = SPEED_INVALID;
7997 tp->link_config.duplex = DUPLEX_INVALID;
7998 } else {
7999 tp->link_config.advertising = 0;
8000 tp->link_config.speed = cmd->speed;
8001 tp->link_config.duplex = cmd->duplex;
8002 }
6aa20a22 8003
24fcad6b
MC		 8004 tp->link_config.orig_speed = tp->link_config.speed;
8005 tp->link_config.orig_duplex = tp->link_config.duplex;
8006 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8007
1da177e4
LT		 8008 if (netif_running(dev))
8009 tg3_setup_phy(tp, 1);
8010
f47c11ee 8011 tg3_full_unlock(tp);
6aa20a22 8012
1da177e4
LT		 8013 return 0;
8014}
6aa20a22 8015
1da177e4
LT		 8016static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8017{
8018 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8019
1da177e4
LT		 8020 strcpy(info->driver, DRV_MODULE_NAME);
8021 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8022 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8023 strcpy(info->bus_info, pci_name(tp->pdev));
8024}
6aa20a22 8025
1da177e4
LT		 8026static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8027{
8028 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8029
a85feb8c
GZ		 8030 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8031 wol->supported = WAKE_MAGIC;
8032 else
8033 wol->supported = 0;
1da177e4
LT		 8034 wol->wolopts = 0;
8035 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8036 wol->wolopts = WAKE_MAGIC;
8037 memset(&wol->sopass, 0, sizeof(wol->sopass));
8038}
6aa20a22 8039
1da177e4
LT		 8040static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8041{
8042 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8043
1da177e4
LT		 8044 if (wol->wolopts & ~WAKE_MAGIC)
8045 return -EINVAL;
8046 if ((wol->wolopts & WAKE_MAGIC) &&
a85feb8c 8047 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
1da177e4 8048 return -EINVAL;
6aa20a22 8049
f47c11ee 8050 spin_lock_bh(&tp->lock);
1da177e4
LT		 8051 if (wol->wolopts & WAKE_MAGIC)
8052 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8053 else
8054 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8055 spin_unlock_bh(&tp->lock);
6aa20a22 8056
1da177e4
LT		 8057 return 0;
8058}
6aa20a22 8059
1da177e4
LT		 8060static u32 tg3_get_msglevel(struct net_device *dev)
8061{
8062 struct tg3 *tp = netdev_priv(dev);
8063 return tp->msg_enable;
8064}
6aa20a22 8065
1da177e4
LT		 8066static void tg3_set_msglevel(struct net_device *dev, u32 value)
8067{
8068 struct tg3 *tp = netdev_priv(dev);
8069 tp->msg_enable = value;
8070}
6aa20a22 8071
1da177e4
LT		 8072static int tg3_set_tso(struct net_device *dev, u32 value)
8073{
8074 struct tg3 *tp = netdev_priv(dev);
8075
8076 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8077 if (value)
8078 return -EINVAL;
8079 return 0;
8080 }
b5d3772c
MC		 8081 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8082 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
b0026624
MC		 8083 if (value)
8084 dev->features |= NETIF_F_TSO6;
8085 else
8086 dev->features &= ~NETIF_F_TSO6;
8087 }
1da177e4
LT		 8088 return ethtool_op_set_tso(dev, value);
8089}
6aa20a22 8090
1da177e4
LT		 8091static int tg3_nway_reset(struct net_device *dev)
8092{
8093 struct tg3 *tp = netdev_priv(dev);
8094 u32 bmcr;
8095 int r;
6aa20a22 8096
1da177e4
LT		 8097 if (!netif_running(dev))
8098 return -EAGAIN;
8099
c94e3941
MC		 8100 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8101 return -EINVAL;
8102
f47c11ee 8103 spin_lock_bh(&tp->lock);
1da177e4
LT		 8104 r = -EINVAL;
8105 tg3_readphy(tp, MII_BMCR, &bmcr);
8106 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8107 ((bmcr & BMCR_ANENABLE) ||
8108 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8109 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8110 BMCR_ANENABLE);
1da177e4
LT		 8111 r = 0;
8112 }
f47c11ee 8113 spin_unlock_bh(&tp->lock);
6aa20a22 8114
1da177e4
LT		 8115 return r;
8116}
6aa20a22 8117
1da177e4
LT		 8118static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8119{
8120 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8121
1da177e4
LT		 8122 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8123 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8124 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8125 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8126 else
8127 ering->rx_jumbo_max_pending = 0;
8128
8129 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8130
8131 ering->rx_pending = tp->rx_pending;
8132 ering->rx_mini_pending = 0;
4f81c32b
MC		 8133 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8134 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8135 else
8136 ering->rx_jumbo_pending = 0;
8137
1da177e4
LT		 8138 ering->tx_pending = tp->tx_pending;
8139}
6aa20a22 8140
1da177e4
LT		 8141static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8142{
8143 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8144 int irq_sync = 0, err = 0;
6aa20a22 8145
1da177e4
LT		 8146 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8147 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8148 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8149 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8150 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8151 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8152 return -EINVAL;
6aa20a22 8153
bbe832c0 8154 if (netif_running(dev)) {
1da177e4 8155 tg3_netif_stop(tp);
bbe832c0
MC		 8156 irq_sync = 1;
8157 }
1da177e4 8158
bbe832c0 8159 tg3_full_lock(tp, irq_sync);
6aa20a22 8160
1da177e4
LT		 8161 tp->rx_pending = ering->rx_pending;
8162
8163 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8164 tp->rx_pending > 63)
8165 tp->rx_pending = 63;
8166 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8167 tp->tx_pending = ering->tx_pending;
8168
8169 if (netif_running(dev)) {
944d980e 8170 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8171 err = tg3_restart_hw(tp, 1);
8172 if (!err)
8173 tg3_netif_start(tp);
1da177e4
LT		 8174 }
8175
f47c11ee 8176 tg3_full_unlock(tp);
6aa20a22 8177
b9ec6c1b 8178 return err;
1da177e4 8179}
6aa20a22 8180
1da177e4
LT		 8181static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8182{
8183 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8184
1da177e4
LT		 8185 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8186 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8187 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8188}
6aa20a22 8189
1da177e4
LT		 8190static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8191{
8192 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8193 int irq_sync = 0, err = 0;
6aa20a22 8194
bbe832c0 8195 if (netif_running(dev)) {
1da177e4 8196 tg3_netif_stop(tp);
bbe832c0
MC		 8197 irq_sync = 1;
8198 }
1da177e4 8199
bbe832c0 8200 tg3_full_lock(tp, irq_sync);
f47c11ee 8201
1da177e4
LT		 8202 if (epause->autoneg)
8203 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8204 else
8205 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8206 if (epause->rx_pause)
8207 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8208 else
8209 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8210 if (epause->tx_pause)
8211 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8212 else
8213 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8214
8215 if (netif_running(dev)) {
944d980e 8216 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8217 err = tg3_restart_hw(tp, 1);
8218 if (!err)
8219 tg3_netif_start(tp);
1da177e4 8220 }
f47c11ee
DM		 8221
8222 tg3_full_unlock(tp);
6aa20a22 8223
b9ec6c1b 8224 return err;
1da177e4 8225}
6aa20a22 8226
1da177e4
LT		 8227static u32 tg3_get_rx_csum(struct net_device *dev)
8228{
8229 struct tg3 *tp = netdev_priv(dev);
8230 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8231}
6aa20a22 8232
1da177e4
LT		 8233static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8234{
8235 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8236
1da177e4
LT		 8237 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8238 if (data != 0)
8239 return -EINVAL;
8240 return 0;
8241 }
6aa20a22 8242
f47c11ee 8243 spin_lock_bh(&tp->lock);
1da177e4
LT		 8244 if (data)
8245 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8246 else
8247 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8248 spin_unlock_bh(&tp->lock);
6aa20a22 8249
1da177e4
LT		 8250 return 0;
8251}
6aa20a22 8252
1da177e4
LT		 8253static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8254{
8255 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8256
1da177e4
LT		 8257 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8258 if (data != 0)
8259 return -EINVAL;
8260 return 0;
8261 }
6aa20a22 8262
af36e6b6
MC		 8263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf 8265 ethtool_op_set_tx_hw_csum(dev, data);
1da177e4 8266 else
9c27dbdf 8267 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8268
8269 return 0;
8270}
8271
8272static int tg3_get_stats_count (struct net_device *dev)
8273{
8274 return TG3_NUM_STATS;
8275}
8276
4cafd3f5
MC		 8277static int tg3_get_test_count (struct net_device *dev)
8278{
8279 return TG3_NUM_TEST;
8280}
8281
1da177e4
LT		 8282static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8283{
8284 switch (stringset) {
8285 case ETH_SS_STATS:
8286 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8287 break;
4cafd3f5
MC		 8288 case ETH_SS_TEST:
8289 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8290 break;
1da177e4
LT		 8291 default:
8292 WARN_ON(1); /* we need a WARN() */
8293 break;
8294 }
8295}
8296
4009a93d
MC		 8297static int tg3_phys_id(struct net_device *dev, u32 data)
8298{
8299 struct tg3 *tp = netdev_priv(dev);
8300 int i;
8301
8302 if (!netif_running(tp->dev))
8303 return -EAGAIN;
8304
8305 if (data == 0)
8306 data = 2;
8307
8308 for (i = 0; i < (data * 2); i++) {
8309 if ((i % 2) == 0)
8310 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8311 LED_CTRL_1000MBPS_ON |
8312 LED_CTRL_100MBPS_ON |
8313 LED_CTRL_10MBPS_ON |
8314 LED_CTRL_TRAFFIC_OVERRIDE |
8315 LED_CTRL_TRAFFIC_BLINK |
8316 LED_CTRL_TRAFFIC_LED);
6aa20a22 8317
4009a93d
MC		 8318 else
8319 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8320 LED_CTRL_TRAFFIC_OVERRIDE);
8321
8322 if (msleep_interruptible(500))
8323 break;
8324 }
8325 tw32(MAC_LED_CTRL, tp->led_ctrl);
8326 return 0;
8327}
8328
1da177e4
LT		 8329static void tg3_get_ethtool_stats (struct net_device *dev,
8330 struct ethtool_stats *estats, u64 *tmp_stats)
8331{
8332 struct tg3 *tp = netdev_priv(dev);
8333 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8334}
8335
566f86ad 8336#define NVRAM_TEST_SIZE 0x100
1b27777a 8337#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
b16250e3
MC		 8338#define NVRAM_SELFBOOT_HW_SIZE 0x20
8339#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8340
8341static int tg3_test_nvram(struct tg3 *tp)
8342{
1b27777a
MC		 8343 u32 *buf, csum, magic;
8344 int i, j, err = 0, size;
566f86ad 8345
1820180b 8346 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8347 return -EIO;
8348
1b27777a
MC		 8349 if (magic == TG3_EEPROM_MAGIC)
8350 size = NVRAM_TEST_SIZE;
b16250e3 8351 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8352 if ((magic & 0xe00000) == 0x200000)
8353 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8354 else
8355 return 0;
b16250e3
MC		 8356 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8357 size = NVRAM_SELFBOOT_HW_SIZE;
8358 else
1b27777a
MC		 8359 return -EIO;
8360
8361 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8362 if (buf == NULL)
8363 return -ENOMEM;
8364
1b27777a
MC		 8365 err = -EIO;
8366 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8367 u32 val;
8368
8369 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8370 break;
8371 buf[j] = cpu_to_le32(val);
8372 }
1b27777a 8373 if (i < size)
566f86ad
MC		 8374 goto out;
8375
1b27777a 8376 /* Selfboot format */
b16250e3
MC		 8377 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8378 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8379 u8 *buf8 = (u8 *) buf, csum8 = 0;
8380
8381 for (i = 0; i < size; i++)
8382 csum8 += buf8[i];
8383
ad96b485
AB		 8384 if (csum8 == 0) {
8385 err = 0;
8386 goto out;
8387 }
8388
8389 err = -EIO;
8390 goto out;
1b27777a 8391 }
566f86ad 8392
b16250e3
MC		 8393 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8394 TG3_EEPROM_MAGIC_HW) {
8395 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8396 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8397 u8 *buf8 = (u8 *) buf;
8398 int j, k;
8399
8400 /* Separate the parity bits and the data bytes. */
8401 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8402 if ((i == 0) || (i == 8)) {
8403 int l;
8404 u8 msk;
8405
8406 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8407 parity[k++] = buf8[i] & msk;
8408 i++;
8409 }
8410 else if (i == 16) {
8411 int l;
8412 u8 msk;
8413
8414 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8415 parity[k++] = buf8[i] & msk;
8416 i++;
8417
8418 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8419 parity[k++] = buf8[i] & msk;
8420 i++;
8421 }
8422 data[j++] = buf8[i];
8423 }
8424
8425 err = -EIO;
8426 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8427 u8 hw8 = hweight8(data[i]);
8428
8429 if ((hw8 & 0x1) && parity[i])
8430 goto out;
8431 else if (!(hw8 & 0x1) && !parity[i])
8432 goto out;
8433 }
8434 err = 0;
8435 goto out;
8436 }
8437
566f86ad
MC		 8438 /* Bootstrap checksum at offset 0x10 */
8439 csum = calc_crc((unsigned char *) buf, 0x10);
8440 if(csum != cpu_to_le32(buf[0x10/4]))
8441 goto out;
8442
8443 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8444 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8445 if (csum != cpu_to_le32(buf[0xfc/4]))
8446 goto out;
8447
8448 err = 0;
8449
8450out:
8451 kfree(buf);
8452 return err;
8453}
8454
ca43007a
MC		 8455#define TG3_SERDES_TIMEOUT_SEC 2
8456#define TG3_COPPER_TIMEOUT_SEC 6
8457
8458static int tg3_test_link(struct tg3 *tp)
8459{
8460 int i, max;
8461
8462 if (!netif_running(tp->dev))
8463 return -ENODEV;
8464
4c987487 8465 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8466 max = TG3_SERDES_TIMEOUT_SEC;
8467 else
8468 max = TG3_COPPER_TIMEOUT_SEC;
8469
8470 for (i = 0; i < max; i++) {
8471 if (netif_carrier_ok(tp->dev))
8472 return 0;
8473
8474 if (msleep_interruptible(1000))
8475 break;
8476 }
8477
8478 return -EIO;
8479}
8480
a71116d1 8481/* Only test the commonly used registers */
30ca3e37 8482static int tg3_test_registers(struct tg3 *tp)
a71116d1 8483{
b16250e3 8484 int i, is_5705, is_5750;
a71116d1
MC		 8485 u32 offset, read_mask, write_mask, val, save_val, read_val;
8486 static struct {
8487 u16 offset;
8488 u16 flags;
8489#define TG3_FL_5705 0x1
8490#define TG3_FL_NOT_5705 0x2
8491#define TG3_FL_NOT_5788 0x4
b16250e3 8492#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8493 u32 read_mask;
8494 u32 write_mask;
8495 } reg_tbl[] = {
8496 /* MAC Control Registers */
8497 { MAC_MODE, TG3_FL_NOT_5705,
8498 0x00000000, 0x00ef6f8c },
8499 { MAC_MODE, TG3_FL_5705,
8500 0x00000000, 0x01ef6b8c },
8501 { MAC_STATUS, TG3_FL_NOT_5705,
8502 0x03800107, 0x00000000 },
8503 { MAC_STATUS, TG3_FL_5705,
8504 0x03800100, 0x00000000 },
8505 { MAC_ADDR_0_HIGH, 0x0000,
8506 0x00000000, 0x0000ffff },
8507 { MAC_ADDR_0_LOW, 0x0000,
8508 0x00000000, 0xffffffff },
8509 { MAC_RX_MTU_SIZE, 0x0000,
8510 0x00000000, 0x0000ffff },
8511 { MAC_TX_MODE, 0x0000,
8512 0x00000000, 0x00000070 },
8513 { MAC_TX_LENGTHS, 0x0000,
8514 0x00000000, 0x00003fff },
8515 { MAC_RX_MODE, TG3_FL_NOT_5705,
8516 0x00000000, 0x000007fc },
8517 { MAC_RX_MODE, TG3_FL_5705,
8518 0x00000000, 0x000007dc },
8519 { MAC_HASH_REG_0, 0x0000,
8520 0x00000000, 0xffffffff },
8521 { MAC_HASH_REG_1, 0x0000,
8522 0x00000000, 0xffffffff },
8523 { MAC_HASH_REG_2, 0x0000,
8524 0x00000000, 0xffffffff },
8525 { MAC_HASH_REG_3, 0x0000,
8526 0x00000000, 0xffffffff },
8527
8528 /* Receive Data and Receive BD Initiator Control Registers. */
8529 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8530 0x00000000, 0xffffffff },
8531 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8532 0x00000000, 0xffffffff },
8533 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8534 0x00000000, 0x00000003 },
8535 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8536 0x00000000, 0xffffffff },
8537 { RCVDBDI_STD_BD+0, 0x0000,
8538 0x00000000, 0xffffffff },
8539 { RCVDBDI_STD_BD+4, 0x0000,
8540 0x00000000, 0xffffffff },
8541 { RCVDBDI_STD_BD+8, 0x0000,
8542 0x00000000, 0xffff0002 },
8543 { RCVDBDI_STD_BD+0xc, 0x0000,
8544 0x00000000, 0xffffffff },
6aa20a22 8545
a71116d1
MC		 8546 /* Receive BD Initiator Control Registers. */
8547 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8548 0x00000000, 0xffffffff },
8549 { RCVBDI_STD_THRESH, TG3_FL_5705,
8550 0x00000000, 0x000003ff },
8551 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8552 0x00000000, 0xffffffff },
6aa20a22 8553
a71116d1
MC		 8554 /* Host Coalescing Control Registers. */
8555 { HOSTCC_MODE, TG3_FL_NOT_5705,
8556 0x00000000, 0x00000004 },
8557 { HOSTCC_MODE, TG3_FL_5705,
8558 0x00000000, 0x000000f6 },
8559 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8560 0x00000000, 0xffffffff },
8561 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8562 0x00000000, 0x000003ff },
8563 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8564 0x00000000, 0xffffffff },
8565 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8566 0x00000000, 0x000003ff },
8567 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8568 0x00000000, 0xffffffff },
8569 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8570 0x00000000, 0x000000ff },
8571 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8572 0x00000000, 0xffffffff },
8573 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8574 0x00000000, 0x000000ff },
8575 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8576 0x00000000, 0xffffffff },
8577 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8578 0x00000000, 0xffffffff },
8579 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8580 0x00000000, 0xffffffff },
8581 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8582 0x00000000, 0x000000ff },
8583 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8584 0x00000000, 0xffffffff },
8585 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8586 0x00000000, 0x000000ff },
8587 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8588 0x00000000, 0xffffffff },
8589 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8590 0x00000000, 0xffffffff },
8591 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8592 0x00000000, 0xffffffff },
8593 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8594 0x00000000, 0xffffffff },
8595 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8596 0x00000000, 0xffffffff },
8597 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8598 0xffffffff, 0x00000000 },
8599 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8600 0xffffffff, 0x00000000 },
8601
8602 /* Buffer Manager Control Registers. */
b16250e3 8603 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 8604 0x00000000, 0x007fff80 },
b16250e3 8605 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 8606 0x00000000, 0x007fffff },
8607 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8608 0x00000000, 0x0000003f },
8609 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8610 0x00000000, 0x000001ff },
8611 { BUFMGR_MB_HIGH_WATER, 0x0000,
8612 0x00000000, 0x000001ff },
8613 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8614 0xffffffff, 0x00000000 },
8615 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8616 0xffffffff, 0x00000000 },
6aa20a22 8617
a71116d1
MC		 8618 /* Mailbox Registers */
8619 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8620 0x00000000, 0x000001ff },
8621 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8622 0x00000000, 0x000001ff },
8623 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8624 0x00000000, 0x000007ff },
8625 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8626 0x00000000, 0x000001ff },
8627
8628 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8629 };
8630
b16250e3
MC		 8631 is_5705 = is_5750 = 0;
8632 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 8633 is_5705 = 1;
b16250e3
MC		 8634 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8635 is_5750 = 1;
8636 }
a71116d1
MC		 8637
8638 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8639 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8640 continue;
8641
8642 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8643 continue;
8644
8645 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8646 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8647 continue;
8648
b16250e3
MC		 8649 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8650 continue;
8651
a71116d1
MC		 8652 offset = (u32) reg_tbl[i].offset;
8653 read_mask = reg_tbl[i].read_mask;
8654 write_mask = reg_tbl[i].write_mask;
8655
8656 /* Save the original register content */
8657 save_val = tr32(offset);
8658
8659 /* Determine the read-only value. */
8660 read_val = save_val & read_mask;
8661
8662 /* Write zero to the register, then make sure the read-only bits
8663 * are not changed and the read/write bits are all zeros.
8664 */
8665 tw32(offset, 0);
8666
8667 val = tr32(offset);
8668
8669 /* Test the read-only and read/write bits. */
8670 if (((val & read_mask) != read_val) || (val & write_mask))
8671 goto out;
8672
8673 /* Write ones to all the bits defined by RdMask and WrMask, then
8674 * make sure the read-only bits are not changed and the
8675 * read/write bits are all ones.
8676 */
8677 tw32(offset, read_mask | write_mask);
8678
8679 val = tr32(offset);
8680
8681 /* Test the read-only bits. */
8682 if ((val & read_mask) != read_val)
8683 goto out;
8684
8685 /* Test the read/write bits. */
8686 if ((val & write_mask) != write_mask)
8687 goto out;
8688
8689 tw32(offset, save_val);
8690 }
8691
8692 return 0;
8693
8694out:
9f88f29f
MC		 8695 if (netif_msg_hw(tp))
8696 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8697 offset);
a71116d1
MC		 8698 tw32(offset, save_val);
8699 return -EIO;
8700}
8701
7942e1db
MC		 8702static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8703{
f71e1309 8704 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 8705 int i;
8706 u32 j;
8707
8708 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8709 for (j = 0; j < len; j += 4) {
8710 u32 val;
8711
8712 tg3_write_mem(tp, offset + j, test_pattern[i]);
8713 tg3_read_mem(tp, offset + j, &val);
8714 if (val != test_pattern[i])
8715 return -EIO;
8716 }
8717 }
8718 return 0;
8719}
8720
8721static int tg3_test_memory(struct tg3 *tp)
8722{
8723 static struct mem_entry {
8724 u32 offset;
8725 u32 len;
8726 } mem_tbl_570x[] = {
38690194 8727 { 0x00000000, 0x00b50},
7942e1db
MC		 8728 { 0x00002000, 0x1c000},
8729 { 0xffffffff, 0x00000}
8730 }, mem_tbl_5705[] = {
8731 { 0x00000100, 0x0000c},
8732 { 0x00000200, 0x00008},
7942e1db
MC		 8733 { 0x00004000, 0x00800},
8734 { 0x00006000, 0x01000},
8735 { 0x00008000, 0x02000},
8736 { 0x00010000, 0x0e000},
8737 { 0xffffffff, 0x00000}
79f4d13a
MC		 8738 }, mem_tbl_5755[] = {
8739 { 0x00000200, 0x00008},
8740 { 0x00004000, 0x00800},
8741 { 0x00006000, 0x00800},
8742 { 0x00008000, 0x02000},
8743 { 0x00010000, 0x0c000},
8744 { 0xffffffff, 0x00000}
b16250e3
MC		 8745 }, mem_tbl_5906[] = {
8746 { 0x00000200, 0x00008},
8747 { 0x00004000, 0x00400},
8748 { 0x00006000, 0x00400},
8749 { 0x00008000, 0x01000},
8750 { 0x00010000, 0x01000},
8751 { 0xffffffff, 0x00000}
7942e1db
MC		 8752 };
8753 struct mem_entry *mem_tbl;
8754 int err = 0;
8755 int i;
8756
79f4d13a 8757 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6
MC		 8758 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8759 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
79f4d13a 8760 mem_tbl = mem_tbl_5755;
b16250e3
MC		 8761 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8762 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 8763 else
8764 mem_tbl = mem_tbl_5705;
8765 } else
7942e1db
MC		 8766 mem_tbl = mem_tbl_570x;
8767
8768 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8769 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8770 mem_tbl[i].len)) != 0)
8771 break;
8772 }
6aa20a22 8773
7942e1db
MC		 8774 return err;
8775}
8776
9f40dead
MC		 8777#define TG3_MAC_LOOPBACK 0
8778#define TG3_PHY_LOOPBACK 1
8779
8780static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8781{
9f40dead 8782 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8783 u32 desc_idx;
8784 struct sk_buff *skb, *rx_skb;
8785 u8 *tx_data;
8786 dma_addr_t map;
8787 int num_pkts, tx_len, rx_len, i, err;
8788 struct tg3_rx_buffer_desc *desc;
8789
9f40dead 8790 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8791 /* HW errata - mac loopback fails in some cases on 5780.
8792 * Normal traffic and PHY loopback are not affected by
8793 * errata.
8794 */
8795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8796 return 0;
8797
9f40dead 8798 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
3f7045c1
MC		 8799 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8800 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8801 mac_mode |= MAC_MODE_PORT_MODE_MII;
8802 else
8803 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 8804 tw32(MAC_MODE, mac_mode);
8805 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 8806 u32 val;
8807
b16250e3
MC		 8808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8809 u32 phytest;
8810
8811 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8812 u32 phy;
8813
8814 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8815 phytest | MII_TG3_EPHY_SHADOW_EN);
8816 if (!tg3_readphy(tp, 0x1b, &phy))
8817 tg3_writephy(tp, 0x1b, phy & ~0x20);
8818 if (!tg3_readphy(tp, 0x10, &phy))
8819 tg3_writephy(tp, 0x10, phy & ~0x4000);
8820 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8821 }
5d64ad34
MC		 8822 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8823 } else
8824 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1
MC		 8825
8826 tg3_writephy(tp, MII_BMCR, val);
c94e3941 8827 udelay(40);
5d64ad34
MC		 8828
8829 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8830 MAC_MODE_LINK_POLARITY;
8831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 8832 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 8833 mac_mode |= MAC_MODE_PORT_MODE_MII;
8834 } else
8835 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 8836
c94e3941
MC		 8837 /* reset to prevent losing 1st rx packet intermittently */
8838 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8839 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8840 udelay(10);
8841 tw32_f(MAC_RX_MODE, tp->rx_mode);
8842 }
ff18ff02 8843 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9f40dead 8844 mac_mode &= ~MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 8845 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8846 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8847 }
9f40dead 8848 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8849 }
8850 else
8851 return -EINVAL;
c76949a6
MC		 8852
8853 err = -EIO;
8854
c76949a6 8855 tx_len = 1514;
a20e9c62 8856 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 8857 if (!skb)
8858 return -ENOMEM;
8859
c76949a6
MC		 8860 tx_data = skb_put(skb, tx_len);
8861 memcpy(tx_data, tp->dev->dev_addr, 6);
8862 memset(tx_data + 6, 0x0, 8);
8863
8864 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8865
8866 for (i = 14; i < tx_len; i++)
8867 tx_data[i] = (u8) (i & 0xff);
8868
8869 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8870
8871 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8872 HOSTCC_MODE_NOW);
8873
8874 udelay(10);
8875
8876 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8877
c76949a6
MC		 8878 num_pkts = 0;
8879
9f40dead 8880 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8881
9f40dead 8882 tp->tx_prod++;
c76949a6
MC		 8883 num_pkts++;
8884
9f40dead
MC		 8885 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8886 tp->tx_prod);
09ee929c 8887 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8888
8889 udelay(10);
8890
3f7045c1
MC		 8891 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8892 for (i = 0; i < 25; i++) {
c76949a6
MC		 8893 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8894 HOSTCC_MODE_NOW);
8895
8896 udelay(10);
8897
8898 tx_idx = tp->hw_status->idx[0].tx_consumer;
8899 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8900 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8901 (rx_idx == (rx_start_idx + num_pkts)))
8902 break;
8903 }
8904
8905 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8906 dev_kfree_skb(skb);
8907
9f40dead 8908 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8909 goto out;
8910
8911 if (rx_idx != rx_start_idx + num_pkts)
8912 goto out;
8913
8914 desc = &tp->rx_rcb[rx_start_idx];
8915 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8916 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8917 if (opaque_key != RXD_OPAQUE_RING_STD)
8918 goto out;
8919
8920 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8921 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8922 goto out;
8923
8924 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8925 if (rx_len != tx_len)
8926 goto out;
8927
8928 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8929
8930 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8931 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8932
8933 for (i = 14; i < tx_len; i++) {
8934 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8935 goto out;
8936 }
8937 err = 0;
6aa20a22 8938
c76949a6
MC		 8939 /* tg3_free_rings will unmap and free the rx_skb */
8940out:
8941 return err;
8942}
8943
9f40dead
MC		 8944#define TG3_MAC_LOOPBACK_FAILED 1
8945#define TG3_PHY_LOOPBACK_FAILED 2
8946#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8947 TG3_PHY_LOOPBACK_FAILED)
8948
8949static int tg3_test_loopback(struct tg3 *tp)
8950{
8951 int err = 0;
8952
8953 if (!netif_running(tp->dev))
8954 return TG3_LOOPBACK_FAILED;
8955
b9ec6c1b
MC		 8956 err = tg3_reset_hw(tp, 1);
8957 if (err)
8958 return TG3_LOOPBACK_FAILED;
9f40dead
MC		 8959
8960 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8961 err |= TG3_MAC_LOOPBACK_FAILED;
8962 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8963 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8964 err |= TG3_PHY_LOOPBACK_FAILED;
8965 }
8966
8967 return err;
8968}
8969
4cafd3f5
MC		 8970static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8971 u64 *data)
8972{
566f86ad
MC		 8973 struct tg3 *tp = netdev_priv(dev);
8974
bc1c7567
MC		 8975 if (tp->link_config.phy_is_low_power)
8976 tg3_set_power_state(tp, PCI_D0);
8977
566f86ad
MC		 8978 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8979
8980 if (tg3_test_nvram(tp) != 0) {
8981 etest->flags |= ETH_TEST_FL_FAILED;
8982 data[0] = 1;
8983 }
ca43007a
MC		 8984 if (tg3_test_link(tp) != 0) {
8985 etest->flags |= ETH_TEST_FL_FAILED;
8986 data[1] = 1;
8987 }
a71116d1 8988 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 8989 int err, irq_sync = 0;
bbe832c0
MC		 8990
8991 if (netif_running(dev)) {
a71116d1 8992 tg3_netif_stop(tp);
bbe832c0
MC		 8993 irq_sync = 1;
8994 }
a71116d1 8995
bbe832c0 8996 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8997
8998 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 8999 err = tg3_nvram_lock(tp);
a71116d1
MC		 9000 tg3_halt_cpu(tp, RX_CPU_BASE);
9001 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9002 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9003 if (!err)
9004 tg3_nvram_unlock(tp);
a71116d1 9005
d9ab5ad1
MC		 9006 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9007 tg3_phy_reset(tp);
9008
a71116d1
MC		 9009 if (tg3_test_registers(tp) != 0) {
9010 etest->flags |= ETH_TEST_FL_FAILED;
9011 data[2] = 1;
9012 }
7942e1db
MC		 9013 if (tg3_test_memory(tp) != 0) {
9014 etest->flags |= ETH_TEST_FL_FAILED;
9015 data[3] = 1;
9016 }
9f40dead 9017 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9018 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9019
f47c11ee
DM		 9020 tg3_full_unlock(tp);
9021
d4bc3927
MC		 9022 if (tg3_test_interrupt(tp) != 0) {
9023 etest->flags |= ETH_TEST_FL_FAILED;
9024 data[5] = 1;
9025 }
f47c11ee
DM		 9026
9027 tg3_full_lock(tp, 0);
d4bc3927 9028
a71116d1
MC		 9029 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9030 if (netif_running(dev)) {
9031 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9032 if (!tg3_restart_hw(tp, 1))
9033 tg3_netif_start(tp);
a71116d1 9034 }
f47c11ee
DM		 9035
9036 tg3_full_unlock(tp);
a71116d1 9037 }
bc1c7567
MC		 9038 if (tp->link_config.phy_is_low_power)
9039 tg3_set_power_state(tp, PCI_D3hot);
9040
4cafd3f5
MC		 9041}
9042
1da177e4
LT		 9043static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9044{
9045 struct mii_ioctl_data *data = if_mii(ifr);
9046 struct tg3 *tp = netdev_priv(dev);
9047 int err;
9048
9049 switch(cmd) {
9050 case SIOCGMIIPHY:
9051 data->phy_id = PHY_ADDR;
9052
9053 /* fallthru */
9054 case SIOCGMIIREG: {
9055 u32 mii_regval;
9056
9057 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9058 break; /* We have no PHY */
9059
bc1c7567
MC		 9060 if (tp->link_config.phy_is_low_power)
9061 return -EAGAIN;
9062
f47c11ee 9063 spin_lock_bh(&tp->lock);
1da177e4 9064 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9065 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9066
9067 data->val_out = mii_regval;
9068
9069 return err;
9070 }
9071
9072 case SIOCSMIIREG:
9073 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9074 break; /* We have no PHY */
9075
9076 if (!capable(CAP_NET_ADMIN))
9077 return -EPERM;
9078
bc1c7567
MC		 9079 if (tp->link_config.phy_is_low_power)
9080 return -EAGAIN;
9081
f47c11ee 9082 spin_lock_bh(&tp->lock);
1da177e4 9083 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9084 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9085
9086 return err;
9087
9088 default:
9089 /* do nothing */
9090 break;
9091 }
9092 return -EOPNOTSUPP;
9093}
9094
9095#if TG3_VLAN_TAG_USED
9096static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9097{
9098 struct tg3 *tp = netdev_priv(dev);
9099
29315e87
MC		 9100 if (netif_running(dev))
9101 tg3_netif_stop(tp);
9102
f47c11ee 9103 tg3_full_lock(tp, 0);
1da177e4
LT		 9104
9105 tp->vlgrp = grp;
9106
9107 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9108 __tg3_set_rx_mode(dev);
9109
f47c11ee 9110 tg3_full_unlock(tp);
29315e87
MC		 9111
9112 if (netif_running(dev))
9113 tg3_netif_start(tp);
1da177e4
LT		 9114}
9115
9116static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9117{
9118 struct tg3 *tp = netdev_priv(dev);
9119
29315e87
MC		 9120 if (netif_running(dev))
9121 tg3_netif_stop(tp);
9122
f47c11ee 9123 tg3_full_lock(tp, 0);
5c15bdec 9124 vlan_group_set_device(tp->vlgrp, vid, NULL);
f47c11ee 9125 tg3_full_unlock(tp);
29315e87
MC		 9126
9127 if (netif_running(dev))
9128 tg3_netif_start(tp);
1da177e4
LT		 9129}
9130#endif
9131
15f9850d
DM		 9132static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9133{
9134 struct tg3 *tp = netdev_priv(dev);
9135
9136 memcpy(ec, &tp->coal, sizeof(*ec));
9137 return 0;
9138}
9139
d244c892
MC		 9140static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9141{
9142 struct tg3 *tp = netdev_priv(dev);
9143 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9144 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9145
9146 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9147 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9148 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9149 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9150 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9151 }
9152
9153 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9154 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9155 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9156 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9157 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9158 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9159 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9160 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9161 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9162 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9163 return -EINVAL;
9164
9165 /* No rx interrupts will be generated if both are zero */
9166 if ((ec->rx_coalesce_usecs == 0) &&
9167 (ec->rx_max_coalesced_frames == 0))
9168 return -EINVAL;
9169
9170 /* No tx interrupts will be generated if both are zero */
9171 if ((ec->tx_coalesce_usecs == 0) &&
9172 (ec->tx_max_coalesced_frames == 0))
9173 return -EINVAL;
9174
9175 /* Only copy relevant parameters, ignore all others. */
9176 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9177 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9178 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9179 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9180 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9181 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9182 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9183 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9184 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9185
9186 if (netif_running(dev)) {
9187 tg3_full_lock(tp, 0);
9188 __tg3_set_coalesce(tp, &tp->coal);
9189 tg3_full_unlock(tp);
9190 }
9191 return 0;
9192}
9193
7282d491 9194static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9195 .get_settings = tg3_get_settings,
9196 .set_settings = tg3_set_settings,
9197 .get_drvinfo = tg3_get_drvinfo,
9198 .get_regs_len = tg3_get_regs_len,
9199 .get_regs = tg3_get_regs,
9200 .get_wol = tg3_get_wol,
9201 .set_wol = tg3_set_wol,
9202 .get_msglevel = tg3_get_msglevel,
9203 .set_msglevel = tg3_set_msglevel,
9204 .nway_reset = tg3_nway_reset,
9205 .get_link = ethtool_op_get_link,
9206 .get_eeprom_len = tg3_get_eeprom_len,
9207 .get_eeprom = tg3_get_eeprom,
9208 .set_eeprom = tg3_set_eeprom,
9209 .get_ringparam = tg3_get_ringparam,
9210 .set_ringparam = tg3_set_ringparam,
9211 .get_pauseparam = tg3_get_pauseparam,
9212 .set_pauseparam = tg3_set_pauseparam,
9213 .get_rx_csum = tg3_get_rx_csum,
9214 .set_rx_csum = tg3_set_rx_csum,
9215 .get_tx_csum = ethtool_op_get_tx_csum,
9216 .set_tx_csum = tg3_set_tx_csum,
9217 .get_sg = ethtool_op_get_sg,
9218 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 9219 .get_tso = ethtool_op_get_tso,
9220 .set_tso = tg3_set_tso,
4cafd3f5
MC		 9221 .self_test_count = tg3_get_test_count,
9222 .self_test = tg3_self_test,
1da177e4 9223 .get_strings = tg3_get_strings,
4009a93d 9224 .phys_id = tg3_phys_id,
1da177e4
LT		 9225 .get_stats_count = tg3_get_stats_count,
9226 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9227 .get_coalesce = tg3_get_coalesce,
d244c892 9228 .set_coalesce = tg3_set_coalesce,
2ff43697 9229 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 9230};
9231
9232static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9233{
1b27777a 9234 u32 cursize, val, magic;
1da177e4
LT		 9235
9236 tp->nvram_size = EEPROM_CHIP_SIZE;
9237
1820180b 9238 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9239 return;
9240
b16250e3
MC		 9241 if ((magic != TG3_EEPROM_MAGIC) &&
9242 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9243 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9244 return;
9245
9246 /*
9247 * Size the chip by reading offsets at increasing powers of two.
9248 * When we encounter our validation signature, we know the addressing
9249 * has wrapped around, and thus have our chip size.
9250 */
1b27777a 9251 cursize = 0x10;
1da177e4
LT		 9252
9253 while (cursize < tp->nvram_size) {
1820180b 9254 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9255 return;
9256
1820180b 9257 if (val == magic)
1da177e4
LT		 9258 break;
9259
9260 cursize <<= 1;
9261 }
9262
9263 tp->nvram_size = cursize;
9264}
6aa20a22 9265
1da177e4
LT		 9266static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9267{
9268 u32 val;
9269
1820180b 9270 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9271 return;
9272
9273 /* Selfboot format */
1820180b 9274 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9275 tg3_get_eeprom_size(tp);
9276 return;
9277 }
9278
1da177e4
LT		 9279 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9280 if (val != 0) {
9281 tp->nvram_size = (val >> 16) * 1024;
9282 return;
9283 }
9284 }
989a9d23 9285 tp->nvram_size = 0x80000;
1da177e4
LT		 9286}
9287
9288static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9289{
9290 u32 nvcfg1;
9291
9292 nvcfg1 = tr32(NVRAM_CFG1);
9293 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9294 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9295 }
9296 else {
9297 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9298 tw32(NVRAM_CFG1, nvcfg1);
9299 }
9300
4c987487 9301 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9302 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9303 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9304 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9305 tp->nvram_jedecnum = JEDEC_ATMEL;
9306 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9307 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9308 break;
9309 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9310 tp->nvram_jedecnum = JEDEC_ATMEL;
9311 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9312 break;
9313 case FLASH_VENDOR_ATMEL_EEPROM:
9314 tp->nvram_jedecnum = JEDEC_ATMEL;
9315 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9316 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9317 break;
9318 case FLASH_VENDOR_ST:
9319 tp->nvram_jedecnum = JEDEC_ST;
9320 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9321 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9322 break;
9323 case FLASH_VENDOR_SAIFUN:
9324 tp->nvram_jedecnum = JEDEC_SAIFUN;
9325 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9326 break;
9327 case FLASH_VENDOR_SST_SMALL:
9328 case FLASH_VENDOR_SST_LARGE:
9329 tp->nvram_jedecnum = JEDEC_SST;
9330 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9331 break;
9332 }
9333 }
9334 else {
9335 tp->nvram_jedecnum = JEDEC_ATMEL;
9336 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9337 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9338 }
9339}
9340
361b4ac2
MC		 9341static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9342{
9343 u32 nvcfg1;
9344
9345 nvcfg1 = tr32(NVRAM_CFG1);
9346
e6af301b
MC		 9347 /* NVRAM protection for TPM */
9348 if (nvcfg1 & (1 << 27))
9349 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9350
361b4ac2
MC		 9351 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9352 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9353 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9354 tp->nvram_jedecnum = JEDEC_ATMEL;
9355 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9356 break;
9357 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9358 tp->nvram_jedecnum = JEDEC_ATMEL;
9359 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9360 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9361 break;
9362 case FLASH_5752VENDOR_ST_M45PE10:
9363 case FLASH_5752VENDOR_ST_M45PE20:
9364 case FLASH_5752VENDOR_ST_M45PE40:
9365 tp->nvram_jedecnum = JEDEC_ST;
9366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9368 break;
9369 }
9370
9371 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9372 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9373 case FLASH_5752PAGE_SIZE_256:
9374 tp->nvram_pagesize = 256;
9375 break;
9376 case FLASH_5752PAGE_SIZE_512:
9377 tp->nvram_pagesize = 512;
9378 break;
9379 case FLASH_5752PAGE_SIZE_1K:
9380 tp->nvram_pagesize = 1024;
9381 break;
9382 case FLASH_5752PAGE_SIZE_2K:
9383 tp->nvram_pagesize = 2048;
9384 break;
9385 case FLASH_5752PAGE_SIZE_4K:
9386 tp->nvram_pagesize = 4096;
9387 break;
9388 case FLASH_5752PAGE_SIZE_264:
9389 tp->nvram_pagesize = 264;
9390 break;
9391 }
9392 }
9393 else {
9394 /* For eeprom, set pagesize to maximum eeprom size */
9395 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9396
9397 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9398 tw32(NVRAM_CFG1, nvcfg1);
9399 }
9400}
9401
d3c7b886
MC		 9402static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9403{
989a9d23 9404 u32 nvcfg1, protect = 0;
d3c7b886
MC		 9405
9406 nvcfg1 = tr32(NVRAM_CFG1);
9407
9408 /* NVRAM protection for TPM */
989a9d23 9409 if (nvcfg1 & (1 << 27)) {
d3c7b886 9410 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 9411 protect = 1;
9412 }
d3c7b886 9413
989a9d23
MC		 9414 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9415 switch (nvcfg1) {
d3c7b886
MC		 9416 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9417 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9418 case FLASH_5755VENDOR_ATMEL_FLASH_3:
d3c7b886
MC		 9419 tp->nvram_jedecnum = JEDEC_ATMEL;
9420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9421 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9422 tp->nvram_pagesize = 264;
989a9d23
MC		 9423 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9424 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9425 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9426 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9427 else
9428 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
d3c7b886
MC		 9429 break;
9430 case FLASH_5752VENDOR_ST_M45PE10:
9431 case FLASH_5752VENDOR_ST_M45PE20:
9432 case FLASH_5752VENDOR_ST_M45PE40:
9433 tp->nvram_jedecnum = JEDEC_ST;
9434 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9435 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9436 tp->nvram_pagesize = 256;
989a9d23
MC		 9437 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9438 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9439 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9440 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9441 else
9442 tp->nvram_size = (protect ? 0x20000 : 0x80000);
d3c7b886
MC		 9443 break;
9444 }
9445}
9446
1b27777a
MC		 9447static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9448{
9449 u32 nvcfg1;
9450
9451 nvcfg1 = tr32(NVRAM_CFG1);
9452
9453 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9454 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9455 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9456 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9457 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9458 tp->nvram_jedecnum = JEDEC_ATMEL;
9459 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9460 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9461
9462 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9463 tw32(NVRAM_CFG1, nvcfg1);
9464 break;
9465 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9466 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9467 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9468 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9469 tp->nvram_jedecnum = JEDEC_ATMEL;
9470 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9471 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9472 tp->nvram_pagesize = 264;
9473 break;
9474 case FLASH_5752VENDOR_ST_M45PE10:
9475 case FLASH_5752VENDOR_ST_M45PE20:
9476 case FLASH_5752VENDOR_ST_M45PE40:
9477 tp->nvram_jedecnum = JEDEC_ST;
9478 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9479 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9480 tp->nvram_pagesize = 256;
9481 break;
9482 }
9483}
9484
b5d3772c
MC		 9485static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9486{
9487 tp->nvram_jedecnum = JEDEC_ATMEL;
9488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9489 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9490}
9491
1da177e4
LT		 9492/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9493static void __devinit tg3_nvram_init(struct tg3 *tp)
9494{
1da177e4
LT		 9495 tw32_f(GRC_EEPROM_ADDR,
9496 (EEPROM_ADDR_FSM_RESET |
9497 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9498 EEPROM_ADDR_CLKPERD_SHIFT)));
9499
9d57f01c 9500 msleep(1);
1da177e4
LT		 9501
9502 /* Enable seeprom accesses. */
9503 tw32_f(GRC_LOCAL_CTRL,
9504 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9505 udelay(100);
9506
9507 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9508 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9509 tp->tg3_flags |= TG3_FLAG_NVRAM;
9510
ec41c7df
MC		 9511 if (tg3_nvram_lock(tp)) {
9512 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9513 "tg3_nvram_init failed.\n", tp->dev->name);
9514 return;
9515 }
e6af301b 9516 tg3_enable_nvram_access(tp);
1da177e4 9517
989a9d23
MC		 9518 tp->nvram_size = 0;
9519
361b4ac2
MC		 9520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9521 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 9522 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9523 tg3_get_5755_nvram_info(tp);
1b27777a
MC		 9524 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9525 tg3_get_5787_nvram_info(tp);
b5d3772c
MC		 9526 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9527 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 9528 else
9529 tg3_get_nvram_info(tp);
9530
989a9d23
MC		 9531 if (tp->nvram_size == 0)
9532 tg3_get_nvram_size(tp);
1da177e4 9533
e6af301b 9534 tg3_disable_nvram_access(tp);
381291b7 9535 tg3_nvram_unlock(tp);
1da177e4
LT		 9536
9537 } else {
9538 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9539
9540 tg3_get_eeprom_size(tp);
9541 }
9542}
9543
9544static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9545 u32 offset, u32 *val)
9546{
9547 u32 tmp;
9548 int i;
9549
9550 if (offset > EEPROM_ADDR_ADDR_MASK ||
9551 (offset % 4) != 0)
9552 return -EINVAL;
9553
9554 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9555 EEPROM_ADDR_DEVID_MASK |
9556 EEPROM_ADDR_READ);
9557 tw32(GRC_EEPROM_ADDR,
9558 tmp |
9559 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9560 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9561 EEPROM_ADDR_ADDR_MASK) |
9562 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9563
9d57f01c 9564 for (i = 0; i < 1000; i++) {
1da177e4
LT		 9565 tmp = tr32(GRC_EEPROM_ADDR);
9566
9567 if (tmp & EEPROM_ADDR_COMPLETE)
9568 break;
9d57f01c 9569 msleep(1);
1da177e4
LT		 9570 }
9571 if (!(tmp & EEPROM_ADDR_COMPLETE))
9572 return -EBUSY;
9573
9574 *val = tr32(GRC_EEPROM_DATA);
9575 return 0;
9576}
9577
9578#define NVRAM_CMD_TIMEOUT 10000
9579
9580static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9581{
9582 int i;
9583
9584 tw32(NVRAM_CMD, nvram_cmd);
9585 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9586 udelay(10);
9587 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9588 udelay(10);
9589 break;
9590 }
9591 }
9592 if (i == NVRAM_CMD_TIMEOUT) {
9593 return -EBUSY;
9594 }
9595 return 0;
9596}
9597
1820180b
MC		 9598static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9599{
9600 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9601 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9602 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9603 (tp->nvram_jedecnum == JEDEC_ATMEL))
9604
9605 addr = ((addr / tp->nvram_pagesize) <<
9606 ATMEL_AT45DB0X1B_PAGE_POS) +
9607 (addr % tp->nvram_pagesize);
9608
9609 return addr;
9610}
9611
c4e6575c
MC		 9612static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9613{
9614 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9615 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9616 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9617 (tp->nvram_jedecnum == JEDEC_ATMEL))
9618
9619 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9620 tp->nvram_pagesize) +
9621 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9622
9623 return addr;
9624}
9625
1da177e4
LT		 9626static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9627{
9628 int ret;
9629
1da177e4
LT		 9630 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9631 return tg3_nvram_read_using_eeprom(tp, offset, val);
9632
1820180b 9633 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9634
9635 if (offset > NVRAM_ADDR_MSK)
9636 return -EINVAL;
9637
ec41c7df
MC		 9638 ret = tg3_nvram_lock(tp);
9639 if (ret)
9640 return ret;
1da177e4 9641
e6af301b 9642 tg3_enable_nvram_access(tp);
1da177e4
LT		 9643
9644 tw32(NVRAM_ADDR, offset);
9645 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9646 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9647
9648 if (ret == 0)
9649 *val = swab32(tr32(NVRAM_RDDATA));
9650
e6af301b 9651 tg3_disable_nvram_access(tp);
1da177e4 9652
381291b7
MC		 9653 tg3_nvram_unlock(tp);
9654
1da177e4
LT		 9655 return ret;
9656}
9657
1820180b
MC		 9658static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9659{
9660 int err;
9661 u32 tmp;
9662
9663 err = tg3_nvram_read(tp, offset, &tmp);
9664 *val = swab32(tmp);
9665 return err;
9666}
9667
1da177e4
LT		 9668static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9669 u32 offset, u32 len, u8 *buf)
9670{
9671 int i, j, rc = 0;
9672 u32 val;
9673
9674 for (i = 0; i < len; i += 4) {
9675 u32 addr, data;
9676
9677 addr = offset + i;
9678
9679 memcpy(&data, buf + i, 4);
9680
9681 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9682
9683 val = tr32(GRC_EEPROM_ADDR);
9684 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9685
9686 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9687 EEPROM_ADDR_READ);
9688 tw32(GRC_EEPROM_ADDR, val |
9689 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9690 (addr & EEPROM_ADDR_ADDR_MASK) |
9691 EEPROM_ADDR_START |
9692 EEPROM_ADDR_WRITE);
6aa20a22 9693
9d57f01c 9694 for (j = 0; j < 1000; j++) {
1da177e4
LT		 9695 val = tr32(GRC_EEPROM_ADDR);
9696
9697 if (val & EEPROM_ADDR_COMPLETE)
9698 break;
9d57f01c 9699 msleep(1);
1da177e4
LT		 9700 }
9701 if (!(val & EEPROM_ADDR_COMPLETE)) {
9702 rc = -EBUSY;
9703 break;
9704 }
9705 }
9706
9707 return rc;
9708}
9709
9710/* offset and length are dword aligned */
9711static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9712 u8 *buf)
9713{
9714 int ret = 0;
9715 u32 pagesize = tp->nvram_pagesize;
9716 u32 pagemask = pagesize - 1;
9717 u32 nvram_cmd;
9718 u8 *tmp;
9719
9720 tmp = kmalloc(pagesize, GFP_KERNEL);
9721 if (tmp == NULL)
9722 return -ENOMEM;
9723
9724 while (len) {
9725 int j;
e6af301b 9726 u32 phy_addr, page_off, size;
1da177e4
LT		 9727
9728 phy_addr = offset & ~pagemask;
6aa20a22 9729
1da177e4
LT		 9730 for (j = 0; j < pagesize; j += 4) {
9731 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9732 (u32 *) (tmp + j))))
9733 break;
9734 }
9735 if (ret)
9736 break;
9737
9738 page_off = offset & pagemask;
9739 size = pagesize;
9740 if (len < size)
9741 size = len;
9742
9743 len -= size;
9744
9745 memcpy(tmp + page_off, buf, size);
9746
9747 offset = offset + (pagesize - page_off);
9748
e6af301b 9749 tg3_enable_nvram_access(tp);
1da177e4
LT		 9750
9751 /*
9752 * Before we can erase the flash page, we need
9753 * to issue a special "write enable" command.
9754 */
9755 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9756
9757 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9758 break;
9759
9760 /* Erase the target page */
9761 tw32(NVRAM_ADDR, phy_addr);
9762
9763 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9764 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9765
9766 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9767 break;
9768
9769 /* Issue another write enable to start the write. */
9770 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9771
9772 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9773 break;
9774
9775 for (j = 0; j < pagesize; j += 4) {
9776 u32 data;
9777
9778 data = *((u32 *) (tmp + j));
9779 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9780
9781 tw32(NVRAM_ADDR, phy_addr + j);
9782
9783 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9784 NVRAM_CMD_WR;
9785
9786 if (j == 0)
9787 nvram_cmd |= NVRAM_CMD_FIRST;
9788 else if (j == (pagesize - 4))
9789 nvram_cmd |= NVRAM_CMD_LAST;
9790
9791 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9792 break;
9793 }
9794 if (ret)
9795 break;
9796 }
9797
9798 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9799 tg3_nvram_exec_cmd(tp, nvram_cmd);
9800
9801 kfree(tmp);
9802
9803 return ret;
9804}
9805
9806/* offset and length are dword aligned */
9807static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9808 u8 *buf)
9809{
9810 int i, ret = 0;
9811
9812 for (i = 0; i < len; i += 4, offset += 4) {
9813 u32 data, page_off, phy_addr, nvram_cmd;
9814
9815 memcpy(&data, buf + i, 4);
9816 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9817
9818 page_off = offset % tp->nvram_pagesize;
9819
1820180b 9820 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9821
9822 tw32(NVRAM_ADDR, phy_addr);
9823
9824 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9825
9826 if ((page_off == 0) || (i == 0))
9827 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 9828 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 9829 nvram_cmd |= NVRAM_CMD_LAST;
9830
9831 if (i == (len - 4))
9832 nvram_cmd |= NVRAM_CMD_LAST;
9833
4c987487 9834 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 9835 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 9836 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
4c987487
MC		 9837 (tp->nvram_jedecnum == JEDEC_ST) &&
9838 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 9839
9840 if ((ret = tg3_nvram_exec_cmd(tp,
9841 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9842 NVRAM_CMD_DONE)))
9843
9844 break;
9845 }
9846 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9847 /* We always do complete word writes to eeprom. */
9848 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9849 }
9850
9851 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9852 break;
9853 }
9854 return ret;
9855}
9856
9857/* offset and length are dword aligned */
9858static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9859{
9860 int ret;
9861
1da177e4 9862 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 9863 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9864 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 9865 udelay(40);
9866 }
9867
9868 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9869 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9870 }
9871 else {
9872 u32 grc_mode;
9873
ec41c7df
MC		 9874 ret = tg3_nvram_lock(tp);
9875 if (ret)
9876 return ret;
1da177e4 9877
e6af301b
MC		 9878 tg3_enable_nvram_access(tp);
9879 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9880 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 9881 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 9882
9883 grc_mode = tr32(GRC_MODE);
9884 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9885
9886 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9887 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9888
9889 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9890 buf);
9891 }
9892 else {
9893 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9894 buf);
9895 }
9896
9897 grc_mode = tr32(GRC_MODE);
9898 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9899
e6af301b 9900 tg3_disable_nvram_access(tp);
1da177e4
LT		 9901 tg3_nvram_unlock(tp);
9902 }
9903
9904 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 9905 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 9906 udelay(40);
9907 }
9908
9909 return ret;
9910}
9911
9912struct subsys_tbl_ent {
9913 u16 subsys_vendor, subsys_devid;
9914 u32 phy_id;
9915};
9916
9917static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9918 /* Broadcom boards. */
9919 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9920 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9921 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9922 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9923 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9924 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9925 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9926 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9927 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9928 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9929 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9930
9931 /* 3com boards. */
9932 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9933 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9934 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9935 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9936 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9937
9938 /* DELL boards. */
9939 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9940 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9941 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9942 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9943
9944 /* Compaq boards. */
9945 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9946 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9947 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9948 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9949 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9950
9951 /* IBM boards. */
9952 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9953};
9954
9955static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9956{
9957 int i;
9958
9959 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9960 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9961 tp->pdev->subsystem_vendor) &&
9962 (subsys_id_to_phy_id[i].subsys_devid ==
9963 tp->pdev->subsystem_device))
9964 return &subsys_id_to_phy_id[i];
9965 }
9966 return NULL;
9967}
9968
7d0c41ef 9969static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9970{
1da177e4 9971 u32 val;
caf636c7
MC		 9972 u16 pmcsr;
9973
9974 /* On some early chips the SRAM cannot be accessed in D3hot state,
9975 * so need make sure we're in D0.
9976 */
9977 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9978 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9979 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9980 msleep(1);
7d0c41ef
MC		 9981
9982 /* Make sure register accesses (indirect or otherwise)
9983 * will function correctly.
9984 */
9985 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9986 tp->misc_host_ctrl);
1da177e4 9987
f49639e6
DM		 9988 /* The memory arbiter has to be enabled in order for SRAM accesses
9989 * to succeed. Normally on powerup the tg3 chip firmware will make
9990 * sure it is enabled, but other entities such as system netboot
9991 * code might disable it.
9992 */
9993 val = tr32(MEMARB_MODE);
9994 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9995
1da177e4 9996 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 9997 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9998
a85feb8c
GZ		 9999 /* Assume an onboard device and WOL capable by default. */
10000 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10001
b5d3772c 10002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10003 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10004 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10005 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10006 }
b5d3772c
MC		 10007 return;
10008 }
10009
1da177e4
LT		 10010 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10011 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10012 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 10013 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10014 int eeprom_phy_serdes = 0;
1da177e4
LT		 10015
10016 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10017 tp->nic_sram_data_cfg = nic_cfg;
10018
10019 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10020 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10021 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10022 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10023 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10024 (ver > 0) && (ver < 0x100))
10025 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10026
1da177e4
LT		 10027 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10028 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10029 eeprom_phy_serdes = 1;
10030
10031 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10032 if (nic_phy_id != 0) {
10033 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10034 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10035
10036 eeprom_phy_id = (id1 >> 16) << 10;
10037 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10038 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10039 } else
10040 eeprom_phy_id = 0;
10041
7d0c41ef 10042 tp->phy_id = eeprom_phy_id;
747e8f8b 10043 if (eeprom_phy_serdes) {
a4e2b347 10044 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10045 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10046 else
10047 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10048 }
7d0c41ef 10049
cbf46853 10050 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10051 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10052 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10053 else
1da177e4
LT		 10054 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10055
10056 switch (led_cfg) {
10057 default:
10058 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10059 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10060 break;
10061
10062 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10063 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10064 break;
10065
10066 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10067 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10068
10069 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10070 * read on some older 5700/5701 bootcode.
10071 */
10072 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10073 ASIC_REV_5700 ||
10074 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10075 ASIC_REV_5701)
10076 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10077
1da177e4
LT		 10078 break;
10079
10080 case SHASTA_EXT_LED_SHARED:
10081 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10082 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10083 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10084 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10085 LED_CTRL_MODE_PHY_2);
10086 break;
10087
10088 case SHASTA_EXT_LED_MAC:
10089 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10090 break;
10091
10092 case SHASTA_EXT_LED_COMBO:
10093 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10094 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10095 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10096 LED_CTRL_MODE_PHY_2);
10097 break;
10098
10099 };
10100
10101 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10103 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10104 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10105
9d26e213 10106 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10107 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10108 if ((tp->pdev->subsystem_vendor ==
10109 PCI_VENDOR_ID_ARIMA) &&
10110 (tp->pdev->subsystem_device == 0x205a ||
10111 tp->pdev->subsystem_device == 0x2063))
10112 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10113 } else {
f49639e6 10114 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10115 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10116 }
1da177e4
LT		 10117
10118 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10119 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10120 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10121 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10122 }
a85feb8c
GZ		 10123 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10124 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10125 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4
LT		 10126
10127 if (cfg2 & (1 << 17))
10128 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10129
10130 /* serdes signal pre-emphasis in register 0x590 set by */
10131 /* bootcode if bit 18 is set */
10132 if (cfg2 & (1 << 18))
10133 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10134 }
7d0c41ef
MC		 10135}
10136
10137static int __devinit tg3_phy_probe(struct tg3 *tp)
10138{
10139 u32 hw_phy_id_1, hw_phy_id_2;
10140 u32 hw_phy_id, hw_phy_id_masked;
10141 int err;
1da177e4
LT		 10142
10143 /* Reading the PHY ID register can conflict with ASF
10144 * firwmare access to the PHY hardware.
10145 */
10146 err = 0;
10147 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10148 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10149 } else {
10150 /* Now read the physical PHY_ID from the chip and verify
10151 * that it is sane. If it doesn't look good, we fall back
10152 * to either the hard-coded table based PHY_ID and failing
10153 * that the value found in the eeprom area.
10154 */
10155 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10156 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10157
10158 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10159 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10160 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10161
10162 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10163 }
10164
10165 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10166 tp->phy_id = hw_phy_id;
10167 if (hw_phy_id_masked == PHY_ID_BCM8002)
10168 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10169 else
10170 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10171 } else {
7d0c41ef
MC		 10172 if (tp->phy_id != PHY_ID_INVALID) {
10173 /* Do nothing, phy ID already set up in
10174 * tg3_get_eeprom_hw_cfg().
10175 */
1da177e4
LT		 10176 } else {
10177 struct subsys_tbl_ent *p;
10178
10179 /* No eeprom signature? Try the hardcoded
10180 * subsys device table.
10181 */
10182 p = lookup_by_subsys(tp);
10183 if (!p)
10184 return -ENODEV;
10185
10186 tp->phy_id = p->phy_id;
10187 if (!tp->phy_id ||
10188 tp->phy_id == PHY_ID_BCM8002)
10189 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10190 }
10191 }
10192
747e8f8b 10193 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4 10194 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10195 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10196
10197 tg3_readphy(tp, MII_BMSR, &bmsr);
10198 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10199 (bmsr & BMSR_LSTATUS))
10200 goto skip_phy_reset;
6aa20a22 10201
1da177e4
LT		 10202 err = tg3_phy_reset(tp);
10203 if (err)
10204 return err;
10205
10206 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10207 ADVERTISE_100HALF | ADVERTISE_100FULL |
10208 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10209 tg3_ctrl = 0;
10210 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10211 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10212 MII_TG3_CTRL_ADV_1000_FULL);
10213 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10214 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10215 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10216 MII_TG3_CTRL_ENABLE_AS_MASTER);
10217 }
10218
3600d918
MC		 10219 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10220 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10221 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10222 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10223 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10224
10225 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10226 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10227
10228 tg3_writephy(tp, MII_BMCR,
10229 BMCR_ANENABLE | BMCR_ANRESTART);
10230 }
10231 tg3_phy_set_wirespeed(tp);
10232
10233 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10234 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10235 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10236 }
10237
10238skip_phy_reset:
10239 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10240 err = tg3_init_5401phy_dsp(tp);
10241 if (err)
10242 return err;
10243 }
10244
10245 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10246 err = tg3_init_5401phy_dsp(tp);
10247 }
10248
747e8f8b 10249 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10250 tp->link_config.advertising =
10251 (ADVERTISED_1000baseT_Half |
10252 ADVERTISED_1000baseT_Full |
10253 ADVERTISED_Autoneg |
10254 ADVERTISED_FIBRE);
10255 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10256 tp->link_config.advertising &=
10257 ~(ADVERTISED_1000baseT_Half |
10258 ADVERTISED_1000baseT_Full);
10259
10260 return err;
10261}
10262
10263static void __devinit tg3_read_partno(struct tg3 *tp)
10264{
10265 unsigned char vpd_data[256];
af2c6a4a 10266 unsigned int i;
1b27777a 10267 u32 magic;
1da177e4 10268
1820180b 10269 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10270 goto out_not_found;
1da177e4 10271
1820180b 10272 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10273 for (i = 0; i < 256; i += 4) {
10274 u32 tmp;
1da177e4 10275
1b27777a
MC		 10276 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10277 goto out_not_found;
10278
10279 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10280 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10281 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10282 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10283 }
10284 } else {
10285 int vpd_cap;
10286
10287 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10288 for (i = 0; i < 256; i += 4) {
10289 u32 tmp, j = 0;
10290 u16 tmp16;
10291
10292 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10293 i);
10294 while (j++ < 100) {
10295 pci_read_config_word(tp->pdev, vpd_cap +
10296 PCI_VPD_ADDR, &tmp16);
10297 if (tmp16 & 0x8000)
10298 break;
10299 msleep(1);
10300 }
f49639e6
DM		 10301 if (!(tmp16 & 0x8000))
10302 goto out_not_found;
10303
1b27777a
MC		 10304 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10305 &tmp);
10306 tmp = cpu_to_le32(tmp);
10307 memcpy(&vpd_data[i], &tmp, 4);
10308 }
1da177e4
LT		 10309 }
10310
10311 /* Now parse and find the part number. */
af2c6a4a 10312 for (i = 0; i < 254; ) {
1da177e4 10313 unsigned char val = vpd_data[i];
af2c6a4a 10314 unsigned int block_end;
1da177e4
LT		 10315
10316 if (val == 0x82 || val == 0x91) {
10317 i = (i + 3 +
10318 (vpd_data[i + 1] +
10319 (vpd_data[i + 2] << 8)));
10320 continue;
10321 }
10322
10323 if (val != 0x90)
10324 goto out_not_found;
10325
10326 block_end = (i + 3 +
10327 (vpd_data[i + 1] +
10328 (vpd_data[i + 2] << 8)));
10329 i += 3;
af2c6a4a
MC		 10330
10331 if (block_end > 256)
10332 goto out_not_found;
10333
10334 while (i < (block_end - 2)) {
1da177e4
LT		 10335 if (vpd_data[i + 0] == 'P' &&
10336 vpd_data[i + 1] == 'N') {
10337 int partno_len = vpd_data[i + 2];
10338
af2c6a4a
MC		 10339 i += 3;
10340 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10341 goto out_not_found;
10342
10343 memcpy(tp->board_part_number,
af2c6a4a 10344 &vpd_data[i], partno_len);
1da177e4
LT		 10345
10346 /* Success. */
10347 return;
10348 }
af2c6a4a 10349 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10350 }
10351
10352 /* Part number not found. */
10353 goto out_not_found;
10354 }
10355
10356out_not_found:
b5d3772c
MC		 10357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10358 strcpy(tp->board_part_number, "BCM95906");
10359 else
10360 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10361}
10362
c4e6575c
MC		 10363static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10364{
10365 u32 val, offset, start;
10366
10367 if (tg3_nvram_read_swab(tp, 0, &val))
10368 return;
10369
10370 if (val != TG3_EEPROM_MAGIC)
10371 return;
10372
10373 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10374 tg3_nvram_read_swab(tp, 0x4, &start))
10375 return;
10376
10377 offset = tg3_nvram_logical_addr(tp, offset);
10378 if (tg3_nvram_read_swab(tp, offset, &val))
10379 return;
10380
10381 if ((val & 0xfc000000) == 0x0c000000) {
10382 u32 ver_offset, addr;
10383 int i;
10384
10385 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10386 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10387 return;
10388
10389 if (val != 0)
10390 return;
10391
10392 addr = offset + ver_offset - start;
10393 for (i = 0; i < 16; i += 4) {
10394 if (tg3_nvram_read(tp, addr + i, &val))
10395 return;
10396
10397 val = cpu_to_le32(val);
10398 memcpy(tp->fw_ver + i, &val, 4);
10399 }
10400 }
10401}
10402
7544b097
MC		 10403static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10404
1da177e4
LT		 10405static int __devinit tg3_get_invariants(struct tg3 *tp)
10406{
10407 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 10408 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10409 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 10410 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10411 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 10412 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10413 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 10414 { },
10415 };
10416 u32 misc_ctrl_reg;
10417 u32 cacheline_sz_reg;
10418 u32 pci_state_reg, grc_misc_cfg;
10419 u32 val;
10420 u16 pci_cmd;
c7835a77 10421 int err, pcie_cap;
1da177e4 10422
1da177e4
LT		 10423 /* Force memory write invalidate off. If we leave it on,
10424 * then on 5700_BX chips we have to enable a workaround.
10425 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10426 * to match the cacheline size. The Broadcom driver have this
10427 * workaround but turns MWI off all the times so never uses
10428 * it. This seems to suggest that the workaround is insufficient.
10429 */
10430 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10431 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10432 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10433
10434 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10435 * has the register indirect write enable bit set before
10436 * we try to access any of the MMIO registers. It is also
10437 * critical that the PCI-X hw workaround situation is decided
10438 * before that as well.
10439 */
10440 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10441 &misc_ctrl_reg);
10442
10443 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10444 MISC_HOST_CTRL_CHIPREV_SHIFT);
10445
ff645bec
MC		 10446 /* Wrong chip ID in 5752 A0. This code can be removed later
10447 * as A0 is not in production.
10448 */
10449 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10450 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10451
6892914f
MC		 10452 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10453 * we need to disable memory and use config. cycles
10454 * only to access all registers. The 5702/03 chips
10455 * can mistakenly decode the special cycles from the
10456 * ICH chipsets as memory write cycles, causing corruption
10457 * of register and memory space. Only certain ICH bridges
10458 * will drive special cycles with non-zero data during the
10459 * address phase which can fall within the 5703's address
10460 * range. This is not an ICH bug as the PCI spec allows
10461 * non-zero address during special cycles. However, only
10462 * these ICH bridges are known to drive non-zero addresses
10463 * during special cycles.
10464 *
10465 * Since special cycles do not cross PCI bridges, we only
10466 * enable this workaround if the 5703 is on the secondary
10467 * bus of these ICH bridges.
10468 */
10469 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10470 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10471 static struct tg3_dev_id {
10472 u32 vendor;
10473 u32 device;
10474 u32 rev;
10475 } ich_chipsets[] = {
10476 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10477 PCI_ANY_ID },
10478 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10479 PCI_ANY_ID },
10480 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10481 0xa },
10482 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10483 PCI_ANY_ID },
10484 { },
10485 };
10486 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10487 struct pci_dev *bridge = NULL;
10488
10489 while (pci_id->vendor != 0) {
10490 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10491 bridge);
10492 if (!bridge) {
10493 pci_id++;
10494 continue;
10495 }
10496 if (pci_id->rev != PCI_ANY_ID) {
10497 u8 rev;
10498
10499 pci_read_config_byte(bridge, PCI_REVISION_ID,
10500 &rev);
10501 if (rev > pci_id->rev)
10502 continue;
10503 }
10504 if (bridge->subordinate &&
10505 (bridge->subordinate->number ==
10506 tp->pdev->bus->number)) {
10507
10508 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10509 pci_dev_put(bridge);
10510 break;
10511 }
10512 }
10513 }
10514
4a29cc2e
MC		 10515 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10516 * DMA addresses > 40-bit. This bridge may have other additional
10517 * 57xx devices behind it in some 4-port NIC designs for example.
10518 * Any tg3 device found behind the bridge will also need the 40-bit
10519 * DMA workaround.
10520 */
a4e2b347
MC		 10521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10523 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 10524 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 10525 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 10526 }
4a29cc2e
MC		 10527 else {
10528 struct pci_dev *bridge = NULL;
10529
10530 do {
10531 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10532 PCI_DEVICE_ID_SERVERWORKS_EPB,
10533 bridge);
10534 if (bridge && bridge->subordinate &&
10535 (bridge->subordinate->number <=
10536 tp->pdev->bus->number) &&
10537 (bridge->subordinate->subordinate >=
10538 tp->pdev->bus->number)) {
10539 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10540 pci_dev_put(bridge);
10541 break;
10542 }
10543 } while (bridge);
10544 }
4cf78e4f 10545
1da177e4
LT		 10546 /* Initialize misc host control in PCI block. */
10547 tp->misc_host_ctrl |= (misc_ctrl_reg &
10548 MISC_HOST_CTRL_CHIPREV);
10549 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10550 tp->misc_host_ctrl);
10551
10552 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10553 &cacheline_sz_reg);
10554
10555 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10556 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10557 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10558 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10559
7544b097
MC		 10560 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10561 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10562 tp->pdev_peer = tg3_find_peer(tp);
10563
6708e5cc 10564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 10565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 10566 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 10567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
b5d3772c 10568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 10569 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 10570 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10571
1b440c56
JL		 10572 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10573 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10574 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10575
5a6f3074 10576 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 10577 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10578 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10579 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10580 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10581 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10582 tp->pdev_peer == tp->pdev))
10583 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10584
af36e6b6 10585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 10588 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 10589 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 10590 } else {
7f62ad5d 10591 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 10592 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10593 ASIC_REV_5750 &&
10594 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 10595 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 10596 }
5a6f3074 10597 }
1da177e4 10598
0f893dc6
MC		 10599 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10600 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 10601 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 10602 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c
MC		 10603 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10604 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 10605 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10606
c7835a77
MC		 10607 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10608 if (pcie_cap != 0) {
1da177e4 10609 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 10610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10611 u16 lnkctl;
10612
10613 pci_read_config_word(tp->pdev,
10614 pcie_cap + PCI_EXP_LNKCTL,
10615 &lnkctl);
10616 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10617 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10618 }
10619 }
1da177e4 10620
399de50b
MC		 10621 /* If we have an AMD 762 or VIA K8T800 chipset, write
10622 * reordering to the mailbox registers done by the host
10623 * controller can cause major troubles. We read back from
10624 * every mailbox register write to force the writes to be
10625 * posted to the chip in order.
10626 */
10627 if (pci_dev_present(write_reorder_chipsets) &&
10628 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10629 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10630
1da177e4
LT		 10631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10632 tp->pci_lat_timer < 64) {
10633 tp->pci_lat_timer = 64;
10634
10635 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10636 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10637 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10638 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10639
10640 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10641 cacheline_sz_reg);
10642 }
10643
10644 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10645 &pci_state_reg);
10646
10647 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10648 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10649
10650 /* If this is a 5700 BX chipset, and we are in PCI-X
10651 * mode, enable register write workaround.
10652 *
10653 * The workaround is to use indirect register accesses
10654 * for all chip writes not to mailbox registers.
10655 */
10656 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10657 u32 pm_reg;
10658 u16 pci_cmd;
10659
10660 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10661
10662 /* The chip can have it's power management PCI config
10663 * space registers clobbered due to this bug.
10664 * So explicitly force the chip into D0 here.
10665 */
10666 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10667 &pm_reg);
10668 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10669 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10670 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10671 pm_reg);
10672
10673 /* Also, force SERR#/PERR# in PCI command. */
10674 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10675 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10676 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10677 }
10678 }
10679
087fe256
MC		 10680 /* 5700 BX chips need to have their TX producer index mailboxes
10681 * written twice to workaround a bug.
10682 */
10683 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10684 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10685
1da177e4
LT		 10686 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10687 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10688 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10689 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10690
10691 /* Chip-specific fixup from Broadcom driver */
10692 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10693 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10694 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10695 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10696 }
10697
1ee582d8 10698 /* Default fast path register access methods */
20094930 10699 tp->read32 = tg3_read32;
1ee582d8 10700 tp->write32 = tg3_write32;
09ee929c 10701 tp->read32_mbox = tg3_read32;
20094930 10702 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 10703 tp->write32_tx_mbox = tg3_write32;
10704 tp->write32_rx_mbox = tg3_write32;
10705
10706 /* Various workaround register access methods */
10707 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10708 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 10709 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10710 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10711 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10712 /*
10713 * Back to back register writes can cause problems on these
10714 * chips, the workaround is to read back all reg writes
10715 * except those to mailbox regs.
10716 *
10717 * See tg3_write_indirect_reg32().
10718 */
1ee582d8 10719 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 10720 }
10721
1ee582d8
MC		 10722
10723 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10724 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10725 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10726 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10727 tp->write32_rx_mbox = tg3_write_flush_reg32;
10728 }
20094930 10729
6892914f
MC		 10730 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10731 tp->read32 = tg3_read_indirect_reg32;
10732 tp->write32 = tg3_write_indirect_reg32;
10733 tp->read32_mbox = tg3_read_indirect_mbox;
10734 tp->write32_mbox = tg3_write_indirect_mbox;
10735 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10736 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10737
10738 iounmap(tp->regs);
22abe310 10739 tp->regs = NULL;
6892914f
MC		 10740
10741 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10742 pci_cmd &= ~PCI_COMMAND_MEMORY;
10743 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10744 }
b5d3772c
MC		 10745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10746 tp->read32_mbox = tg3_read32_mbox_5906;
10747 tp->write32_mbox = tg3_write32_mbox_5906;
10748 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10749 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10750 }
6892914f 10751
bbadf503
MC		 10752 if (tp->write32 == tg3_write_indirect_reg32 ||
10753 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10754 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 10755 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 10756 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10757
7d0c41ef 10758 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 10759 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 10760 * determined before calling tg3_set_power_state() so that
10761 * we know whether or not to switch out of Vaux power.
10762 * When the flag is set, it means that GPIO1 is used for eeprom
10763 * write protect and also implies that it is a LOM where GPIOs
10764 * are not used to switch power.
6aa20a22 10765 */
7d0c41ef
MC		 10766 tg3_get_eeprom_hw_cfg(tp);
10767
314fba34
MC		 10768 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10769 * GPIO1 driven high will bring 5700's external PHY out of reset.
10770 * It is also used as eeprom write protect on LOMs.
10771 */
10772 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10773 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10774 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10775 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10776 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 10777 /* Unused GPIO3 must be driven as output on 5752 because there
10778 * are no pull-up resistors on unused GPIO pins.
10779 */
10780 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10781 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 10782
af36e6b6
MC		 10783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10784 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10785
1da177e4 10786 /* Force the chip into D0. */
bc1c7567 10787 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 10788 if (err) {
10789 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10790 pci_name(tp->pdev));
10791 return err;
10792 }
10793
10794 /* 5700 B0 chips do not support checksumming correctly due
10795 * to hardware bugs.
10796 */
10797 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10798 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10799
1da177e4
LT		 10800 /* Derive initial jumbo mode from MTU assigned in
10801 * ether_setup() via the alloc_etherdev() call
10802 */
0f893dc6 10803 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 10804 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 10805 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 10806
10807 /* Determine WakeOnLan speed to use. */
10808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10809 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10810 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10811 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10812 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10813 } else {
10814 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10815 }
10816
10817 /* A few boards don't want Ethernet@WireSpeed phy feature */
10818 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10819 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10820 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 10821 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 10822 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 10823 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 10824 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10825
10826 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10827 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10828 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10829 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10830 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10831
c424cb24
MC		 10832 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
c1d2a196 10834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
d4011ada
MC		 10835 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10836 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10837 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 10838 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10839 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10840 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 10841 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10842 }
1da177e4 10843
1da177e4 10844 tp->coalesce_mode = 0;
1da177e4
LT		 10845 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10846 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10847 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10848
10849 /* Initialize MAC MI mode, polling disabled. */
10850 tw32_f(MAC_MI_MODE, tp->mi_mode);
10851 udelay(80);
10852
10853 /* Initialize data/descriptor byte/word swapping. */
10854 val = tr32(GRC_MODE);
10855 val &= GRC_MODE_HOST_STACKUP;
10856 tw32(GRC_MODE, val | tp->grc_mode);
10857
10858 tg3_switch_clocks(tp);
10859
10860 /* Clear this out for sanity. */
10861 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10862
10863 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10864 &pci_state_reg);
10865 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10866 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10867 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10868
10869 if (chiprevid == CHIPREV_ID_5701_A0 ||
10870 chiprevid == CHIPREV_ID_5701_B0 ||
10871 chiprevid == CHIPREV_ID_5701_B2 ||
10872 chiprevid == CHIPREV_ID_5701_B5) {
10873 void __iomem *sram_base;
10874
10875 /* Write some dummy words into the SRAM status block
10876 * area, see if it reads back correctly. If the return
10877 * value is bad, force enable the PCIX workaround.
10878 */
10879 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10880
10881 writel(0x00000000, sram_base);
10882 writel(0x00000000, sram_base + 4);
10883 writel(0xffffffff, sram_base + 4);
10884 if (readl(sram_base) != 0x00000000)
10885 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10886 }
10887 }
10888
10889 udelay(50);
10890 tg3_nvram_init(tp);
10891
10892 grc_misc_cfg = tr32(GRC_MISC_CFG);
10893 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10894
1da177e4
LT		 10895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10896 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10897 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10898 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10899
fac9b83e
DM		 10900 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10901 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10902 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10903 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10904 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10905 HOSTCC_MODE_CLRTICK_TXBD);
10906
10907 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10908 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10909 tp->misc_host_ctrl);
10910 }
10911
1da177e4
LT		 10912 /* these are limited to 10/100 only */
10913 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10914 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10915 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10916 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10917 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10918 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10919 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10920 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10921 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 10922 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10923 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 10924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 10925 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10926
10927 err = tg3_phy_probe(tp);
10928 if (err) {
10929 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10930 pci_name(tp->pdev), err);
10931 /* ... but do not return immediately ... */
10932 }
10933
10934 tg3_read_partno(tp);
c4e6575c 10935 tg3_read_fw_ver(tp);
1da177e4
LT		 10936
10937 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10938 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10939 } else {
10940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10941 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10942 else
10943 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10944 }
10945
10946 /* 5700 {AX,BX} chips have a broken status block link
10947 * change bit implementation, so we must use the
10948 * status register in those cases.
10949 */
10950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10951 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10952 else
10953 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10954
10955 /* The led_ctrl is set during tg3_phy_probe, here we might
10956 * have to force the link status polling mechanism based
10957 * upon subsystem IDs.
10958 */
10959 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10960 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10961 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10962 TG3_FLAG_USE_LINKCHG_REG);
10963 }
10964
10965 /* For all SERDES we poll the MAC status register. */
10966 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10967 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10968 else
10969 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10970
5a6f3074 10971 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 10972 * straddle the 4GB address boundary in some cases.
10973 */
af36e6b6 10974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 10977 tp->dev->hard_start_xmit = tg3_start_xmit;
10978 else
10979 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 10980
10981 tp->rx_offset = 2;
10982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10983 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10984 tp->rx_offset = 0;
10985
f92905de
MC		 10986 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10987
10988 /* Increment the rx prod index on the rx std ring by at most
10989 * 8 for these chips to workaround hw errata.
10990 */
10991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10994 tp->rx_std_max_post = 8;
10995
1da177e4
LT		 10996 /* By default, disable wake-on-lan. User can change this
10997 * using ETHTOOL_SWOL.
10998 */
10999 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11000
11001 return err;
11002}
11003
49b6e95f 11004#ifdef CONFIG_SPARC
1da177e4
LT		 11005static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11006{
11007 struct net_device *dev = tp->dev;
11008 struct pci_dev *pdev = tp->pdev;
49b6e95f 11009 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 11010 const unsigned char *addr;
49b6e95f
DM		 11011 int len;
11012
11013 addr = of_get_property(dp, "local-mac-address", &len);
11014 if (addr && len == 6) {
11015 memcpy(dev->dev_addr, addr, 6);
11016 memcpy(dev->perm_addr, dev->dev_addr, 6);
11017 return 0;
1da177e4
LT		 11018 }
11019 return -ENODEV;
11020}
11021
11022static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11023{
11024 struct net_device *dev = tp->dev;
11025
11026 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 11027 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 11028 return 0;
11029}
11030#endif
11031
11032static int __devinit tg3_get_device_address(struct tg3 *tp)
11033{
11034 struct net_device *dev = tp->dev;
11035 u32 hi, lo, mac_offset;
008652b3 11036 int addr_ok = 0;
1da177e4 11037
49b6e95f 11038#ifdef CONFIG_SPARC
1da177e4
LT		 11039 if (!tg3_get_macaddr_sparc(tp))
11040 return 0;
11041#endif
11042
11043 mac_offset = 0x7c;
f49639e6 11044 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11045 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11046 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11047 mac_offset = 0xcc;
11048 if (tg3_nvram_lock(tp))
11049 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11050 else
11051 tg3_nvram_unlock(tp);
11052 }
b5d3772c
MC		 11053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11054 mac_offset = 0x10;
1da177e4
LT		 11055
11056 /* First try to get it from MAC address mailbox. */
11057 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11058 if ((hi >> 16) == 0x484b) {
11059 dev->dev_addr[0] = (hi >> 8) & 0xff;
11060 dev->dev_addr[1] = (hi >> 0) & 0xff;
11061
11062 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11063 dev->dev_addr[2] = (lo >> 24) & 0xff;
11064 dev->dev_addr[3] = (lo >> 16) & 0xff;
11065 dev->dev_addr[4] = (lo >> 8) & 0xff;
11066 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11067
008652b3
MC		 11068 /* Some old bootcode may report a 0 MAC address in SRAM */
11069 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11070 }
11071 if (!addr_ok) {
11072 /* Next, try NVRAM. */
f49639e6 11073 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11074 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11075 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11076 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11077 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11078 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11079 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11080 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11081 }
11082 /* Finally just fetch it out of the MAC control regs. */
11083 else {
11084 hi = tr32(MAC_ADDR_0_HIGH);
11085 lo = tr32(MAC_ADDR_0_LOW);
11086
11087 dev->dev_addr[5] = lo & 0xff;
11088 dev->dev_addr[4] = (lo >> 8) & 0xff;
11089 dev->dev_addr[3] = (lo >> 16) & 0xff;
11090 dev->dev_addr[2] = (lo >> 24) & 0xff;
11091 dev->dev_addr[1] = hi & 0xff;
11092 dev->dev_addr[0] = (hi >> 8) & 0xff;
11093 }
1da177e4
LT		 11094 }
11095
11096 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11097#ifdef CONFIG_SPARC64
11098 if (!tg3_get_default_macaddr_sparc(tp))
11099 return 0;
11100#endif
11101 return -EINVAL;
11102 }
2ff43697 11103 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11104 return 0;
11105}
11106
59e6b434
DM		 11107#define BOUNDARY_SINGLE_CACHELINE 1
11108#define BOUNDARY_MULTI_CACHELINE 2
11109
11110static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11111{
11112 int cacheline_size;
11113 u8 byte;
11114 int goal;
11115
11116 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11117 if (byte == 0)
11118 cacheline_size = 1024;
11119 else
11120 cacheline_size = (int) byte * 4;
11121
11122 /* On 5703 and later chips, the boundary bits have no
11123 * effect.
11124 */
11125 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11126 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11127 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11128 goto out;
11129
11130#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11131 goal = BOUNDARY_MULTI_CACHELINE;
11132#else
11133#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11134 goal = BOUNDARY_SINGLE_CACHELINE;
11135#else
11136 goal = 0;
11137#endif
11138#endif
11139
11140 if (!goal)
11141 goto out;
11142
11143 /* PCI controllers on most RISC systems tend to disconnect
11144 * when a device tries to burst across a cache-line boundary.
11145 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11146 *
11147 * Unfortunately, for PCI-E there are only limited
11148 * write-side controls for this, and thus for reads
11149 * we will still get the disconnects. We'll also waste
11150 * these PCI cycles for both read and write for chips
11151 * other than 5700 and 5701 which do not implement the
11152 * boundary bits.
11153 */
11154 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11155 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11156 switch (cacheline_size) {
11157 case 16:
11158 case 32:
11159 case 64:
11160 case 128:
11161 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11162 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11163 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11164 } else {
11165 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11166 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11167 }
11168 break;
11169
11170 case 256:
11171 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11172 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11173 break;
11174
11175 default:
11176 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11177 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11178 break;
11179 };
11180 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11181 switch (cacheline_size) {
11182 case 16:
11183 case 32:
11184 case 64:
11185 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11186 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11187 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11188 break;
11189 }
11190 /* fallthrough */
11191 case 128:
11192 default:
11193 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11194 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11195 break;
11196 };
11197 } else {
11198 switch (cacheline_size) {
11199 case 16:
11200 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11201 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11202 DMA_RWCTRL_WRITE_BNDRY_16);
11203 break;
11204 }
11205 /* fallthrough */
11206 case 32:
11207 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11208 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11209 DMA_RWCTRL_WRITE_BNDRY_32);
11210 break;
11211 }
11212 /* fallthrough */
11213 case 64:
11214 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11215 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11216 DMA_RWCTRL_WRITE_BNDRY_64);
11217 break;
11218 }
11219 /* fallthrough */
11220 case 128:
11221 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11222 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11223 DMA_RWCTRL_WRITE_BNDRY_128);
11224 break;
11225 }
11226 /* fallthrough */
11227 case 256:
11228 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11229 DMA_RWCTRL_WRITE_BNDRY_256);
11230 break;
11231 case 512:
11232 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11233 DMA_RWCTRL_WRITE_BNDRY_512);
11234 break;
11235 case 1024:
11236 default:
11237 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11238 DMA_RWCTRL_WRITE_BNDRY_1024);
11239 break;
11240 };
11241 }
11242
11243out:
11244 return val;
11245}
11246
1da177e4
LT		 11247static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11248{
11249 struct tg3_internal_buffer_desc test_desc;
11250 u32 sram_dma_descs;
11251 int i, ret;
11252
11253 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11254
11255 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11256 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11257 tw32(RDMAC_STATUS, 0);
11258 tw32(WDMAC_STATUS, 0);
11259
11260 tw32(BUFMGR_MODE, 0);
11261 tw32(FTQ_RESET, 0);
11262
11263 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11264 test_desc.addr_lo = buf_dma & 0xffffffff;
11265 test_desc.nic_mbuf = 0x00002100;
11266 test_desc.len = size;
11267
11268 /*
11269 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11270 * the *second* time the tg3 driver was getting loaded after an
11271 * initial scan.
11272 *
11273 * Broadcom tells me:
11274 * ...the DMA engine is connected to the GRC block and a DMA
11275 * reset may affect the GRC block in some unpredictable way...
11276 * The behavior of resets to individual blocks has not been tested.
11277 *
11278 * Broadcom noted the GRC reset will also reset all sub-components.
11279 */
11280 if (to_device) {
11281 test_desc.cqid_sqid = (13 << 8) | 2;
11282
11283 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11284 udelay(40);
11285 } else {
11286 test_desc.cqid_sqid = (16 << 8) | 7;
11287
11288 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11289 udelay(40);
11290 }
11291 test_desc.flags = 0x00000005;
11292
11293 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11294 u32 val;
11295
11296 val = *(((u32 *)&test_desc) + i);
11297 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11298 sram_dma_descs + (i * sizeof(u32)));
11299 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11300 }
11301 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11302
11303 if (to_device) {
11304 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11305 } else {
11306 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11307 }
11308
11309 ret = -ENODEV;
11310 for (i = 0; i < 40; i++) {
11311 u32 val;
11312
11313 if (to_device)
11314 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11315 else
11316 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11317 if ((val & 0xffff) == sram_dma_descs) {
11318 ret = 0;
11319 break;
11320 }
11321
11322 udelay(100);
11323 }
11324
11325 return ret;
11326}
11327
ded7340d 11328#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11329
11330static int __devinit tg3_test_dma(struct tg3 *tp)
11331{
11332 dma_addr_t buf_dma;
59e6b434 11333 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11334 int ret;
11335
11336 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11337 if (!buf) {
11338 ret = -ENOMEM;
11339 goto out_nofree;
11340 }
11341
11342 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11343 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11344
59e6b434 11345 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11346
11347 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11348 /* DMA read watermark not used on PCIE */
11349 tp->dma_rwctrl |= 0x00180000;
11350 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11353 tp->dma_rwctrl |= 0x003f0000;
11354 else
11355 tp->dma_rwctrl |= 0x003f000f;
11356 } else {
11357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11359 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11360 u32 read_water = 0x7;
1da177e4 11361
4a29cc2e
MC		 11362 /* If the 5704 is behind the EPB bridge, we can
11363 * do the less restrictive ONE_DMA workaround for
11364 * better performance.
11365 */
11366 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11368 tp->dma_rwctrl |= 0x8000;
11369 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 11370 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11371
49afdeb6
MC		 11372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11373 read_water = 4;
59e6b434 11374 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 11375 tp->dma_rwctrl |=
11376 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11377 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11378 (1 << 23);
4cf78e4f
MC		 11379 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11380 /* 5780 always in PCIX mode */
11381 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 11382 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11383 /* 5714 always in PCIX mode */
11384 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 11385 } else {
11386 tp->dma_rwctrl |= 0x001b000f;
11387 }
11388 }
11389
11390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11392 tp->dma_rwctrl &= 0xfffffff0;
11393
11394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11395 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11396 /* Remove this if it causes problems for some boards. */
11397 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11398
11399 /* On 5700/5701 chips, we need to set this bit.
11400 * Otherwise the chip will issue cacheline transactions
11401 * to streamable DMA memory with not all the byte
11402 * enables turned on. This is an error on several
11403 * RISC PCI controllers, in particular sparc64.
11404 *
11405 * On 5703/5704 chips, this bit has been reassigned
11406 * a different meaning. In particular, it is used
11407 * on those chips to enable a PCI-X workaround.
11408 */
11409 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11410 }
11411
11412 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11413
11414#if 0
11415 /* Unneeded, already done by tg3_get_invariants. */
11416 tg3_switch_clocks(tp);
11417#endif
11418
11419 ret = 0;
11420 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11421 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11422 goto out;
11423
59e6b434
DM		 11424 /* It is best to perform DMA test with maximum write burst size
11425 * to expose the 5700/5701 write DMA bug.
11426 */
11427 saved_dma_rwctrl = tp->dma_rwctrl;
11428 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11429 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11430
1da177e4
LT		 11431 while (1) {
11432 u32 *p = buf, i;
11433
11434 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11435 p[i] = i;
11436
11437 /* Send the buffer to the chip. */
11438 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11439 if (ret) {
11440 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11441 break;
11442 }
11443
11444#if 0
11445 /* validate data reached card RAM correctly. */
11446 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11447 u32 val;
11448 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11449 if (le32_to_cpu(val) != p[i]) {
11450 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11451 /* ret = -ENODEV here? */
11452 }
11453 p[i] = 0;
11454 }
11455#endif
11456 /* Now read it back. */
11457 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11458 if (ret) {
11459 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11460
11461 break;
11462 }
11463
11464 /* Verify it. */
11465 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11466 if (p[i] == i)
11467 continue;
11468
59e6b434
DM		 11469 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11470 DMA_RWCTRL_WRITE_BNDRY_16) {
11471 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 11472 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11473 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11474 break;
11475 } else {
11476 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11477 ret = -ENODEV;
11478 goto out;
11479 }
11480 }
11481
11482 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11483 /* Success. */
11484 ret = 0;
11485 break;
11486 }
11487 }
59e6b434
DM		 11488 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11489 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 11490 static struct pci_device_id dma_wait_state_chipsets[] = {
11491 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11492 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11493 { },
11494 };
11495
59e6b434 11496 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 11497 * now look for chipsets that are known to expose the
11498 * DMA bug without failing the test.
59e6b434 11499 */
6d1cfbab
MC		 11500 if (pci_dev_present(dma_wait_state_chipsets)) {
11501 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11502 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11503 }
11504 else
11505 /* Safe to use the calculated DMA boundary. */
11506 tp->dma_rwctrl = saved_dma_rwctrl;
11507
59e6b434
DM		 11508 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11509 }
1da177e4
LT		 11510
11511out:
11512 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11513out_nofree:
11514 return ret;
11515}
11516
11517static void __devinit tg3_init_link_config(struct tg3 *tp)
11518{
11519 tp->link_config.advertising =
11520 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11521 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11522 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11523 ADVERTISED_Autoneg | ADVERTISED_MII);
11524 tp->link_config.speed = SPEED_INVALID;
11525 tp->link_config.duplex = DUPLEX_INVALID;
11526 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 11527 tp->link_config.active_speed = SPEED_INVALID;
11528 tp->link_config.active_duplex = DUPLEX_INVALID;
11529 tp->link_config.phy_is_low_power = 0;
11530 tp->link_config.orig_speed = SPEED_INVALID;
11531 tp->link_config.orig_duplex = DUPLEX_INVALID;
11532 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11533}
11534
11535static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11536{
fdfec172
MC		 11537 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11538 tp->bufmgr_config.mbuf_read_dma_low_water =
11539 DEFAULT_MB_RDMA_LOW_WATER_5705;
11540 tp->bufmgr_config.mbuf_mac_rx_low_water =
11541 DEFAULT_MB_MACRX_LOW_WATER_5705;
11542 tp->bufmgr_config.mbuf_high_water =
11543 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 11544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11545 tp->bufmgr_config.mbuf_mac_rx_low_water =
11546 DEFAULT_MB_MACRX_LOW_WATER_5906;
11547 tp->bufmgr_config.mbuf_high_water =
11548 DEFAULT_MB_HIGH_WATER_5906;
11549 }
fdfec172
MC		 11550
11551 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11552 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11553 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11554 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11555 tp->bufmgr_config.mbuf_high_water_jumbo =
11556 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11557 } else {
11558 tp->bufmgr_config.mbuf_read_dma_low_water =
11559 DEFAULT_MB_RDMA_LOW_WATER;
11560 tp->bufmgr_config.mbuf_mac_rx_low_water =
11561 DEFAULT_MB_MACRX_LOW_WATER;
11562 tp->bufmgr_config.mbuf_high_water =
11563 DEFAULT_MB_HIGH_WATER;
11564
11565 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11566 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11567 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11568 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11569 tp->bufmgr_config.mbuf_high_water_jumbo =
11570 DEFAULT_MB_HIGH_WATER_JUMBO;
11571 }
1da177e4
LT		 11572
11573 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11574 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11575}
11576
11577static char * __devinit tg3_phy_string(struct tg3 *tp)
11578{
11579 switch (tp->phy_id & PHY_ID_MASK) {
11580 case PHY_ID_BCM5400: return "5400";
11581 case PHY_ID_BCM5401: return "5401";
11582 case PHY_ID_BCM5411: return "5411";
11583 case PHY_ID_BCM5701: return "5701";
11584 case PHY_ID_BCM5703: return "5703";
11585 case PHY_ID_BCM5704: return "5704";
11586 case PHY_ID_BCM5705: return "5705";
11587 case PHY_ID_BCM5750: return "5750";
85e94ced 11588 case PHY_ID_BCM5752: return "5752";
a4e2b347 11589 case PHY_ID_BCM5714: return "5714";
4cf78e4f 11590 case PHY_ID_BCM5780: return "5780";
af36e6b6 11591 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 11592 case PHY_ID_BCM5787: return "5787";
126a3368 11593 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 11594 case PHY_ID_BCM5906: return "5906";
1da177e4
LT		 11595 case PHY_ID_BCM8002: return "8002/serdes";
11596 case 0: return "serdes";
11597 default: return "unknown";
11598 };
11599}
11600
f9804ddb
MC		 11601static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11602{
11603 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11604 strcpy(str, "PCI Express");
11605 return str;
11606 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11607 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11608
11609 strcpy(str, "PCIX:");
11610
11611 if ((clock_ctrl == 7) ||
11612 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11613 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11614 strcat(str, "133MHz");
11615 else if (clock_ctrl == 0)
11616 strcat(str, "33MHz");
11617 else if (clock_ctrl == 2)
11618 strcat(str, "50MHz");
11619 else if (clock_ctrl == 4)
11620 strcat(str, "66MHz");
11621 else if (clock_ctrl == 6)
11622 strcat(str, "100MHz");
f9804ddb
MC		 11623 } else {
11624 strcpy(str, "PCI:");
11625 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11626 strcat(str, "66MHz");
11627 else
11628 strcat(str, "33MHz");
11629 }
11630 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11631 strcat(str, ":32-bit");
11632 else
11633 strcat(str, ":64-bit");
11634 return str;
11635}
11636
8c2dc7e1 11637static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 11638{
11639 struct pci_dev *peer;
11640 unsigned int func, devnr = tp->pdev->devfn & ~7;
11641
11642 for (func = 0; func < 8; func++) {
11643 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11644 if (peer && peer != tp->pdev)
11645 break;
11646 pci_dev_put(peer);
11647 }
16fe9d74
MC		 11648 /* 5704 can be configured in single-port mode, set peer to
11649 * tp->pdev in that case.
11650 */
11651 if (!peer) {
11652 peer = tp->pdev;
11653 return peer;
11654 }
1da177e4
LT		 11655
11656 /*
11657 * We don't need to keep the refcount elevated; there's no way
11658 * to remove one half of this device without removing the other
11659 */
11660 pci_dev_put(peer);
11661
11662 return peer;
11663}
11664
15f9850d
DM		 11665static void __devinit tg3_init_coal(struct tg3 *tp)
11666{
11667 struct ethtool_coalesce *ec = &tp->coal;
11668
11669 memset(ec, 0, sizeof(*ec));
11670 ec->cmd = ETHTOOL_GCOALESCE;
11671 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11672 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11673 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11674 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11675 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11676 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11677 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11678 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11679 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11680
11681 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11682 HOSTCC_MODE_CLRTICK_TXBD)) {
11683 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11684 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11685 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11686 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11687 }
d244c892
MC		 11688
11689 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11690 ec->rx_coalesce_usecs_irq = 0;
11691 ec->tx_coalesce_usecs_irq = 0;
11692 ec->stats_block_coalesce_usecs = 0;
11693 }
15f9850d
DM		 11694}
11695
1da177e4
LT		 11696static int __devinit tg3_init_one(struct pci_dev *pdev,
11697 const struct pci_device_id *ent)
11698{
11699 static int tg3_version_printed = 0;
11700 unsigned long tg3reg_base, tg3reg_len;
11701 struct net_device *dev;
11702 struct tg3 *tp;
72f2afb8 11703 int i, err, pm_cap;
f9804ddb 11704 char str[40];
72f2afb8 11705 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 11706
11707 if (tg3_version_printed++ == 0)
11708 printk(KERN_INFO "%s", version);
11709
11710 err = pci_enable_device(pdev);
11711 if (err) {
11712 printk(KERN_ERR PFX "Cannot enable PCI device, "
11713 "aborting.\n");
11714 return err;
11715 }
11716
11717 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11718 printk(KERN_ERR PFX "Cannot find proper PCI device "
11719 "base address, aborting.\n");
11720 err = -ENODEV;
11721 goto err_out_disable_pdev;
11722 }
11723
11724 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11725 if (err) {
11726 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11727 "aborting.\n");
11728 goto err_out_disable_pdev;
11729 }
11730
11731 pci_set_master(pdev);
11732
11733 /* Find power-management capability. */
11734 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11735 if (pm_cap == 0) {
11736 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11737 "aborting.\n");
11738 err = -EIO;
11739 goto err_out_free_res;
11740 }
11741
1da177e4
LT		 11742 tg3reg_base = pci_resource_start(pdev, 0);
11743 tg3reg_len = pci_resource_len(pdev, 0);
11744
11745 dev = alloc_etherdev(sizeof(*tp));
11746 if (!dev) {
11747 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11748 err = -ENOMEM;
11749 goto err_out_free_res;
11750 }
11751
11752 SET_MODULE_OWNER(dev);
11753 SET_NETDEV_DEV(dev, &pdev->dev);
11754
1da177e4
LT		 11755#if TG3_VLAN_TAG_USED
11756 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11757 dev->vlan_rx_register = tg3_vlan_rx_register;
11758 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11759#endif
11760
11761 tp = netdev_priv(dev);
11762 tp->pdev = pdev;
11763 tp->dev = dev;
11764 tp->pm_cap = pm_cap;
11765 tp->mac_mode = TG3_DEF_MAC_MODE;
11766 tp->rx_mode = TG3_DEF_RX_MODE;
11767 tp->tx_mode = TG3_DEF_TX_MODE;
11768 tp->mi_mode = MAC_MI_MODE_BASE;
11769 if (tg3_debug > 0)
11770 tp->msg_enable = tg3_debug;
11771 else
11772 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11773
11774 /* The word/byte swap controls here control register access byte
11775 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11776 * setting below.
11777 */
11778 tp->misc_host_ctrl =
11779 MISC_HOST_CTRL_MASK_PCI_INT |
11780 MISC_HOST_CTRL_WORD_SWAP |
11781 MISC_HOST_CTRL_INDIR_ACCESS |
11782 MISC_HOST_CTRL_PCISTATE_RW;
11783
11784 /* The NONFRM (non-frame) byte/word swap controls take effect
11785 * on descriptor entries, anything which isn't packet data.
11786 *
11787 * The StrongARM chips on the board (one for tx, one for rx)
11788 * are running in big-endian mode.
11789 */
11790 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11791 GRC_MODE_WSWAP_NONFRM_DATA);
11792#ifdef __BIG_ENDIAN
11793 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11794#endif
11795 spin_lock_init(&tp->lock);
1da177e4 11796 spin_lock_init(&tp->indirect_lock);
c4028958 11797 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 11798
11799 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11800 if (tp->regs == 0UL) {
11801 printk(KERN_ERR PFX "Cannot map device registers, "
11802 "aborting.\n");
11803 err = -ENOMEM;
11804 goto err_out_free_dev;
11805 }
11806
11807 tg3_init_link_config(tp);
11808
1da177e4
LT		 11809 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11810 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11811 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11812
11813 dev->open = tg3_open;
11814 dev->stop = tg3_close;
11815 dev->get_stats = tg3_get_stats;
11816 dev->set_multicast_list = tg3_set_rx_mode;
11817 dev->set_mac_address = tg3_set_mac_addr;
11818 dev->do_ioctl = tg3_ioctl;
11819 dev->tx_timeout = tg3_tx_timeout;
11820 dev->poll = tg3_poll;
11821 dev->ethtool_ops = &tg3_ethtool_ops;
11822 dev->weight = 64;
11823 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11824 dev->change_mtu = tg3_change_mtu;
11825 dev->irq = pdev->irq;
11826#ifdef CONFIG_NET_POLL_CONTROLLER
11827 dev->poll_controller = tg3_poll_controller;
11828#endif
11829
11830 err = tg3_get_invariants(tp);
11831 if (err) {
11832 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11833 "aborting.\n");
11834 goto err_out_iounmap;
11835 }
11836
4a29cc2e
MC		 11837 /* The EPB bridge inside 5714, 5715, and 5780 and any
11838 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 11839 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11840 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11841 * do DMA address check in tg3_start_xmit().
11842 */
4a29cc2e
MC		 11843 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11844 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11845 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 11846 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11847#ifdef CONFIG_HIGHMEM
11848 dma_mask = DMA_64BIT_MASK;
11849#endif
4a29cc2e 11850 } else
72f2afb8
MC		 11851 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11852
11853 /* Configure DMA attributes. */
11854 if (dma_mask > DMA_32BIT_MASK) {
11855 err = pci_set_dma_mask(pdev, dma_mask);
11856 if (!err) {
11857 dev->features |= NETIF_F_HIGHDMA;
11858 err = pci_set_consistent_dma_mask(pdev,
11859 persist_dma_mask);
11860 if (err < 0) {
11861 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11862 "DMA for consistent allocations\n");
11863 goto err_out_iounmap;
11864 }
11865 }
11866 }
11867 if (err || dma_mask == DMA_32BIT_MASK) {
11868 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11869 if (err) {
11870 printk(KERN_ERR PFX "No usable DMA configuration, "
11871 "aborting.\n");
11872 goto err_out_iounmap;
11873 }
11874 }
11875
fdfec172 11876 tg3_init_bufmgr_config(tp);
1da177e4 11877
1da177e4
LT		 11878 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11879 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11880 }
11881 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11883 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 11884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 11885 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11886 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11887 } else {
7f62ad5d 11888 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
1da177e4
LT		 11889 }
11890
4e3a7aaa
MC		 11891 /* TSO is on by default on chips that support hardware TSO.
11892 * Firmware TSO on older chips gives lower performance, so it
11893 * is off by default, but can be enabled using ethtool.
11894 */
b0026624 11895 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 11896 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 11897 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11898 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624
MC		 11899 dev->features |= NETIF_F_TSO6;
11900 }
1da177e4 11901
1da177e4
LT		 11902
11903 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11904 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11905 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11906 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11907 tp->rx_pending = 63;
11908 }
11909
1da177e4
LT		 11910 err = tg3_get_device_address(tp);
11911 if (err) {
11912 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11913 "aborting.\n");
11914 goto err_out_iounmap;
11915 }
11916
11917 /*
11918 * Reset chip in case UNDI or EFI driver did not shutdown
11919 * DMA self test will enable WDMAC and we'll see (spurious)
11920 * pending DMA on the PCI bus at that point.
11921 */
11922 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11923 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11924 pci_save_state(tp->pdev);
11925 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 11926 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 11927 }
11928
11929 err = tg3_test_dma(tp);
11930 if (err) {
11931 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11932 goto err_out_iounmap;
11933 }
11934
11935 /* Tigon3 can do ipv4 only... and some chips have buggy
11936 * checksumming.
11937 */
11938 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
af36e6b6
MC		 11939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf
MC		 11941 dev->features |= NETIF_F_HW_CSUM;
11942 else
11943 dev->features |= NETIF_F_IP_CSUM;
11944 dev->features |= NETIF_F_SG;
1da177e4
LT		 11945 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11946 } else
11947 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11948
1da177e4
LT		 11949 /* flow control autonegotiation is default behavior */
11950 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11951
15f9850d
DM		 11952 tg3_init_coal(tp);
11953
7d3f4c97
DM		 11954 /* Now that we have fully setup the chip, save away a snapshot
11955 * of the PCI config space. We need to restore this after
11956 * GRC_MISC_CFG core clock resets and some resume events.
11957 */
11958 pci_save_state(tp->pdev);
11959
c49a1561
MC		 11960 pci_set_drvdata(pdev, dev);
11961
1da177e4
LT		 11962 err = register_netdev(dev);
11963 if (err) {
11964 printk(KERN_ERR PFX "Cannot register net device, "
11965 "aborting.\n");
11966 goto err_out_iounmap;
11967 }
11968
cbb45d21 11969 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 11970 dev->name,
11971 tp->board_part_number,
11972 tp->pci_chip_rev_id,
11973 tg3_phy_string(tp),
f9804ddb 11974 tg3_bus_string(tp, str),
cbb45d21
MC		 11975 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11976 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11977 "10/100/1000Base-T")));
1da177e4
LT		 11978
11979 for (i = 0; i < 6; i++)
11980 printk("%2.2x%c", dev->dev_addr[i],
11981 i == 5 ? '\n' : ':');
11982
11983 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
1c46ae05 11984 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
1da177e4
LT		 11985 dev->name,
11986 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11987 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11988 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11989 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4
LT		 11990 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11991 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 11992 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11993 dev->name, tp->dma_rwctrl,
11994 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11995 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 11996
11997 return 0;
11998
11999err_out_iounmap:
6892914f
MC		 12000 if (tp->regs) {
12001 iounmap(tp->regs);
22abe310 12002 tp->regs = NULL;
6892914f 12003 }
1da177e4
LT		 12004
12005err_out_free_dev:
12006 free_netdev(dev);
12007
12008err_out_free_res:
12009 pci_release_regions(pdev);
12010
12011err_out_disable_pdev:
12012 pci_disable_device(pdev);
12013 pci_set_drvdata(pdev, NULL);
12014 return err;
12015}
12016
12017static void __devexit tg3_remove_one(struct pci_dev *pdev)
12018{
12019 struct net_device *dev = pci_get_drvdata(pdev);
12020
12021 if (dev) {
12022 struct tg3 *tp = netdev_priv(dev);
12023
7faa006f 12024 flush_scheduled_work();
1da177e4 12025 unregister_netdev(dev);
6892914f
MC		 12026 if (tp->regs) {
12027 iounmap(tp->regs);
22abe310 12028 tp->regs = NULL;
6892914f 12029 }
1da177e4
LT		 12030 free_netdev(dev);
12031 pci_release_regions(pdev);
12032 pci_disable_device(pdev);
12033 pci_set_drvdata(pdev, NULL);
12034 }
12035}
12036
12037static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12038{
12039 struct net_device *dev = pci_get_drvdata(pdev);
12040 struct tg3 *tp = netdev_priv(dev);
12041 int err;
12042
12043 if (!netif_running(dev))
12044 return 0;
12045
7faa006f 12046 flush_scheduled_work();
1da177e4
LT		 12047 tg3_netif_stop(tp);
12048
12049 del_timer_sync(&tp->timer);
12050
f47c11ee 12051 tg3_full_lock(tp, 1);
1da177e4 12052 tg3_disable_ints(tp);
f47c11ee 12053 tg3_full_unlock(tp);
1da177e4
LT		 12054
12055 netif_device_detach(dev);
12056
f47c11ee 12057 tg3_full_lock(tp, 0);
944d980e 12058 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12059 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12060 tg3_full_unlock(tp);
1da177e4 12061
436f1379
MC		 12062 /* Save MSI address and data for resume. */
12063 pci_save_state(pdev);
12064
1da177e4
LT		 12065 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12066 if (err) {
f47c11ee 12067 tg3_full_lock(tp, 0);
1da177e4 12068
6a9eba15 12069 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12070 if (tg3_restart_hw(tp, 1))
12071 goto out;
1da177e4
LT		 12072
12073 tp->timer.expires = jiffies + tp->timer_offset;
12074 add_timer(&tp->timer);
12075
12076 netif_device_attach(dev);
12077 tg3_netif_start(tp);
12078
b9ec6c1b 12079out:
f47c11ee 12080 tg3_full_unlock(tp);
1da177e4
LT		 12081 }
12082
12083 return err;
12084}
12085
12086static int tg3_resume(struct pci_dev *pdev)
12087{
12088 struct net_device *dev = pci_get_drvdata(pdev);
12089 struct tg3 *tp = netdev_priv(dev);
12090 int err;
12091
12092 if (!netif_running(dev))
12093 return 0;
12094
12095 pci_restore_state(tp->pdev);
12096
bc1c7567 12097 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12098 if (err)
12099 return err;
12100
12101 netif_device_attach(dev);
12102
f47c11ee 12103 tg3_full_lock(tp, 0);
1da177e4 12104
6a9eba15 12105 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12106 err = tg3_restart_hw(tp, 1);
12107 if (err)
12108 goto out;
1da177e4
LT		 12109
12110 tp->timer.expires = jiffies + tp->timer_offset;
12111 add_timer(&tp->timer);
12112
1da177e4
LT		 12113 tg3_netif_start(tp);
12114
b9ec6c1b 12115out:
f47c11ee 12116 tg3_full_unlock(tp);
1da177e4 12117
b9ec6c1b 12118 return err;
1da177e4
LT		 12119}
12120
12121static struct pci_driver tg3_driver = {
12122 .name = DRV_MODULE_NAME,
12123 .id_table = tg3_pci_tbl,
12124 .probe = tg3_init_one,
12125 .remove = __devexit_p(tg3_remove_one),
12126 .suspend = tg3_suspend,
12127 .resume = tg3_resume
12128};
12129
12130static int __init tg3_init(void)
12131{
29917620 12132 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12133}
12134
12135static void __exit tg3_cleanup(void)
12136{
12137 pci_unregister_driver(&tg3_driver);
12138}
12139
12140module_init(tg3_init);
12141module_exit(tg3_cleanup);
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