]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix up more bio fallout
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
c9bdd4b5 43#include <net/ip.h>
1da177e4
LT		 44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
49b6e95f 50#ifdef CONFIG_SPARC
1da177e4 51#include <asm/idprom.h>
49b6e95f 52#include <asm/prom.h>
1da177e4
LT		 53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
414c66e0
MC		 67#define DRV_MODULE_VERSION "3.83"
68#define DRV_MODULE_RELDATE "October 10, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
9936bcf6
MC		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
13185217
HK		 205 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
211 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
212 {}
1da177e4
LT		 213};
214
215MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
216
50da859d 217static const struct {
1da177e4
LT		 218 const char string[ETH_GSTRING_LEN];
219} ethtool_stats_keys[TG3_NUM_STATS] = {
220 { "rx_octets" },
221 { "rx_fragments" },
222 { "rx_ucast_packets" },
223 { "rx_mcast_packets" },
224 { "rx_bcast_packets" },
225 { "rx_fcs_errors" },
226 { "rx_align_errors" },
227 { "rx_xon_pause_rcvd" },
228 { "rx_xoff_pause_rcvd" },
229 { "rx_mac_ctrl_rcvd" },
230 { "rx_xoff_entered" },
231 { "rx_frame_too_long_errors" },
232 { "rx_jabbers" },
233 { "rx_undersize_packets" },
234 { "rx_in_length_errors" },
235 { "rx_out_length_errors" },
236 { "rx_64_or_less_octet_packets" },
237 { "rx_65_to_127_octet_packets" },
238 { "rx_128_to_255_octet_packets" },
239 { "rx_256_to_511_octet_packets" },
240 { "rx_512_to_1023_octet_packets" },
241 { "rx_1024_to_1522_octet_packets" },
242 { "rx_1523_to_2047_octet_packets" },
243 { "rx_2048_to_4095_octet_packets" },
244 { "rx_4096_to_8191_octet_packets" },
245 { "rx_8192_to_9022_octet_packets" },
246
247 { "tx_octets" },
248 { "tx_collisions" },
249
250 { "tx_xon_sent" },
251 { "tx_xoff_sent" },
252 { "tx_flow_control" },
253 { "tx_mac_errors" },
254 { "tx_single_collisions" },
255 { "tx_mult_collisions" },
256 { "tx_deferred" },
257 { "tx_excessive_collisions" },
258 { "tx_late_collisions" },
259 { "tx_collide_2times" },
260 { "tx_collide_3times" },
261 { "tx_collide_4times" },
262 { "tx_collide_5times" },
263 { "tx_collide_6times" },
264 { "tx_collide_7times" },
265 { "tx_collide_8times" },
266 { "tx_collide_9times" },
267 { "tx_collide_10times" },
268 { "tx_collide_11times" },
269 { "tx_collide_12times" },
270 { "tx_collide_13times" },
271 { "tx_collide_14times" },
272 { "tx_collide_15times" },
273 { "tx_ucast_packets" },
274 { "tx_mcast_packets" },
275 { "tx_bcast_packets" },
276 { "tx_carrier_sense_errors" },
277 { "tx_discards" },
278 { "tx_errors" },
279
280 { "dma_writeq_full" },
281 { "dma_write_prioq_full" },
282 { "rxbds_empty" },
283 { "rx_discards" },
284 { "rx_errors" },
285 { "rx_threshold_hit" },
286
287 { "dma_readq_full" },
288 { "dma_read_prioq_full" },
289 { "tx_comp_queue_full" },
290
291 { "ring_set_send_prod_index" },
292 { "ring_status_update" },
293 { "nic_irqs" },
294 { "nic_avoided_irqs" },
295 { "nic_tx_threshold_hit" }
296};
297
50da859d 298static const struct {
4cafd3f5
MC		 299 const char string[ETH_GSTRING_LEN];
300} ethtool_test_keys[TG3_NUM_TEST] = {
301 { "nvram test (online) " },
302 { "link test (online) " },
303 { "register test (offline)" },
304 { "memory test (offline)" },
305 { "loopback test (offline)" },
306 { "interrupt test (offline)" },
307};
308
b401e9e2
MC		 309static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
310{
311 writel(val, tp->regs + off);
312}
313
314static u32 tg3_read32(struct tg3 *tp, u32 off)
315{
6aa20a22 316 return (readl(tp->regs + off));
b401e9e2
MC		 317}
318
0d3031d9
MC		 319static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
320{
321 writel(val, tp->aperegs + off);
322}
323
324static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
325{
326 return (readl(tp->aperegs + off));
327}
328
1da177e4
LT		 329static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
330{
6892914f
MC		 331 unsigned long flags;
332
333 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 334 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
335 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 336 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 337}
338
339static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342 readl(tp->regs + off);
1da177e4
LT		 343}
344
6892914f 345static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 346{
6892914f
MC		 347 unsigned long flags;
348 u32 val;
349
350 spin_lock_irqsave(&tp->indirect_lock, flags);
351 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
352 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
353 spin_unlock_irqrestore(&tp->indirect_lock, flags);
354 return val;
355}
356
357static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
358{
359 unsigned long flags;
360
361 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
362 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
363 TG3_64BIT_REG_LOW, val);
364 return;
365 }
366 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
367 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
368 TG3_64BIT_REG_LOW, val);
369 return;
1da177e4 370 }
6892914f
MC		 371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376
377 /* In indirect mode when disabling interrupts, we also need
378 * to clear the interrupt bit in the GRC local ctrl register.
379 */
380 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
381 (val == 0x1)) {
382 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
383 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
384 }
385}
386
387static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
388{
389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
b401e9e2
MC		 399/* usec_wait specifies the wait time in usec when writing to certain registers
400 * where it is unsafe to read back the register without some delay.
401 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
402 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
403 */
404static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 405{
b401e9e2
MC		 406 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
407 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
408 /* Non-posted methods */
409 tp->write32(tp, off, val);
410 else {
411 /* Posted method */
412 tg3_write32(tp, off, val);
413 if (usec_wait)
414 udelay(usec_wait);
415 tp->read32(tp, off);
416 }
417 /* Wait again after the read for the posted method to guarantee that
418 * the wait time is met.
419 */
420 if (usec_wait)
421 udelay(usec_wait);
1da177e4
LT		 422}
423
09ee929c
MC		 424static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
425{
426 tp->write32_mbox(tp, off, val);
6892914f
MC		 427 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
428 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
429 tp->read32_mbox(tp, off);
09ee929c
MC		 430}
431
20094930 432static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 433{
434 void __iomem *mbox = tp->regs + off;
435 writel(val, mbox);
436 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
437 writel(val, mbox);
438 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
439 readl(mbox);
440}
441
b5d3772c
MC		 442static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
443{
444 return (readl(tp->regs + off + GRCMBOX_BASE));
445}
446
447static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
448{
449 writel(val, tp->regs + off + GRCMBOX_BASE);
450}
451
20094930 452#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 453#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 454#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
455#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 456#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 457
458#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 459#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
460#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 461#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 462
463static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
464{
6892914f
MC		 465 unsigned long flags;
466
b5d3772c
MC		 467 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
468 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
469 return;
470
6892914f 471 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 472 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
473 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 475
bbadf503
MC		 476 /* Always leave this as zero. */
477 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
478 } else {
479 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
480 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 481
bbadf503
MC		 482 /* Always leave this as zero. */
483 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
484 }
485 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 486}
487
1da177e4
LT		 488static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
489{
6892914f
MC		 490 unsigned long flags;
491
b5d3772c
MC		 492 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
493 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
494 *val = 0;
495 return;
496 }
497
6892914f 498 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 499 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
500 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
501 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 502
bbadf503
MC		 503 /* Always leave this as zero. */
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
505 } else {
506 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
507 *val = tr32(TG3PCI_MEM_WIN_DATA);
508
509 /* Always leave this as zero. */
510 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 }
6892914f 512 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 513}
514
0d3031d9
MC		 515static void tg3_ape_lock_init(struct tg3 *tp)
516{
517 int i;
518
519 /* Make sure the driver hasn't any stale locks. */
520 for (i = 0; i < 8; i++)
521 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
522 APE_LOCK_GRANT_DRIVER);
523}
524
525static int tg3_ape_lock(struct tg3 *tp, int locknum)
526{
527 int i, off;
528 int ret = 0;
529 u32 status;
530
531 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
532 return 0;
533
534 switch (locknum) {
535 case TG3_APE_LOCK_MEM:
536 break;
537 default:
538 return -EINVAL;
539 }
540
541 off = 4 * locknum;
542
543 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
544
545 /* Wait for up to 1 millisecond to acquire lock. */
546 for (i = 0; i < 100; i++) {
547 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
548 if (status == APE_LOCK_GRANT_DRIVER)
549 break;
550 udelay(10);
551 }
552
553 if (status != APE_LOCK_GRANT_DRIVER) {
554 /* Revoke the lock request. */
555 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
556 APE_LOCK_GRANT_DRIVER);
557
558 ret = -EBUSY;
559 }
560
561 return ret;
562}
563
564static void tg3_ape_unlock(struct tg3 *tp, int locknum)
565{
566 int off;
567
568 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
569 return;
570
571 switch (locknum) {
572 case TG3_APE_LOCK_MEM:
573 break;
574 default:
575 return;
576 }
577
578 off = 4 * locknum;
579 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
580}
581
1da177e4
LT		 582static void tg3_disable_ints(struct tg3 *tp)
583{
584 tw32(TG3PCI_MISC_HOST_CTRL,
585 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 586 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 587}
588
589static inline void tg3_cond_int(struct tg3 *tp)
590{
38f3843e
MC		 591 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
592 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 593 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 594 else
595 tw32(HOSTCC_MODE, tp->coalesce_mode |
596 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 597}
598
599static void tg3_enable_ints(struct tg3 *tp)
600{
bbe832c0
MC		 601 tp->irq_sync = 0;
602 wmb();
603
1da177e4
LT		 604 tw32(TG3PCI_MISC_HOST_CTRL,
605 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 606 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
607 (tp->last_tag << 24));
fcfa0a32
MC		 608 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
609 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
610 (tp->last_tag << 24));
1da177e4
LT		 611 tg3_cond_int(tp);
612}
613
04237ddd
MC		 614static inline unsigned int tg3_has_work(struct tg3 *tp)
615{
616 struct tg3_hw_status *sblk = tp->hw_status;
617 unsigned int work_exists = 0;
618
619 /* check for phy events */
620 if (!(tp->tg3_flags &
621 (TG3_FLAG_USE_LINKCHG_REG |
622 TG3_FLAG_POLL_SERDES))) {
623 if (sblk->status & SD_STATUS_LINK_CHG)
624 work_exists = 1;
625 }
626 /* check for RX/TX work to do */
627 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
628 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
629 work_exists = 1;
630
631 return work_exists;
632}
633
1da177e4 634/* tg3_restart_ints
04237ddd
MC		 635 * similar to tg3_enable_ints, but it accurately determines whether there
636 * is new work pending and can return without flushing the PIO write
6aa20a22 637 * which reenables interrupts
1da177e4
LT		 638 */
639static void tg3_restart_ints(struct tg3 *tp)
640{
fac9b83e
DM		 641 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
642 tp->last_tag << 24);
1da177e4
LT		 643 mmiowb();
644
fac9b83e
DM		 645 /* When doing tagged status, this work check is unnecessary.
646 * The last_tag we write above tells the chip which piece of
647 * work we've completed.
648 */
649 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
650 tg3_has_work(tp))
04237ddd
MC		 651 tw32(HOSTCC_MODE, tp->coalesce_mode |
652 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 653}
654
655static inline void tg3_netif_stop(struct tg3 *tp)
656{
bbe832c0 657 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 658 napi_disable(&tp->napi);
1da177e4
LT		 659 netif_tx_disable(tp->dev);
660}
661
662static inline void tg3_netif_start(struct tg3 *tp)
663{
664 netif_wake_queue(tp->dev);
665 /* NOTE: unconditional netif_wake_queue is only appropriate
666 * so long as all callers are assured to have free tx slots
667 * (such as after tg3_init_hw)
668 */
bea3348e 669 napi_enable(&tp->napi);
f47c11ee
DM		 670 tp->hw_status->status |= SD_STATUS_UPDATED;
671 tg3_enable_ints(tp);
1da177e4
LT		 672}
673
674static void tg3_switch_clocks(struct tg3 *tp)
675{
676 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
677 u32 orig_clock_ctrl;
678
795d01c5
MC		 679 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
680 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 681 return;
682
1da177e4
LT		 683 orig_clock_ctrl = clock_ctrl;
684 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
685 CLOCK_CTRL_CLKRUN_OENABLE |
686 0x1f);
687 tp->pci_clock_ctrl = clock_ctrl;
688
689 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
690 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 691 tw32_wait_f(TG3PCI_CLOCK_CTRL,
692 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 693 }
694 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 695 tw32_wait_f(TG3PCI_CLOCK_CTRL,
696 clock_ctrl |
697 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
698 40);
699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
700 clock_ctrl | (CLOCK_CTRL_ALTCLK),
701 40);
1da177e4 702 }
b401e9e2 703 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 704}
705
706#define PHY_BUSY_LOOPS 5000
707
708static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
709{
710 u32 frame_val;
711 unsigned int loops;
712 int ret;
713
714 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
715 tw32_f(MAC_MI_MODE,
716 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
717 udelay(80);
718 }
719
720 *val = 0x0;
721
722 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
723 MI_COM_PHY_ADDR_MASK);
724 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
725 MI_COM_REG_ADDR_MASK);
726 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 727
1da177e4
LT		 728 tw32_f(MAC_MI_COM, frame_val);
729
730 loops = PHY_BUSY_LOOPS;
731 while (loops != 0) {
732 udelay(10);
733 frame_val = tr32(MAC_MI_COM);
734
735 if ((frame_val & MI_COM_BUSY) == 0) {
736 udelay(5);
737 frame_val = tr32(MAC_MI_COM);
738 break;
739 }
740 loops -= 1;
741 }
742
743 ret = -EBUSY;
744 if (loops != 0) {
745 *val = frame_val & MI_COM_DATA_MASK;
746 ret = 0;
747 }
748
749 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
750 tw32_f(MAC_MI_MODE, tp->mi_mode);
751 udelay(80);
752 }
753
754 return ret;
755}
756
757static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
758{
759 u32 frame_val;
760 unsigned int loops;
761 int ret;
762
b5d3772c
MC		 763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
764 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
765 return 0;
766
1da177e4
LT		 767 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
768 tw32_f(MAC_MI_MODE,
769 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
770 udelay(80);
771 }
772
773 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
774 MI_COM_PHY_ADDR_MASK);
775 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
776 MI_COM_REG_ADDR_MASK);
777 frame_val |= (val & MI_COM_DATA_MASK);
778 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 779
1da177e4
LT		 780 tw32_f(MAC_MI_COM, frame_val);
781
782 loops = PHY_BUSY_LOOPS;
783 while (loops != 0) {
784 udelay(10);
785 frame_val = tr32(MAC_MI_COM);
786 if ((frame_val & MI_COM_BUSY) == 0) {
787 udelay(5);
788 frame_val = tr32(MAC_MI_COM);
789 break;
790 }
791 loops -= 1;
792 }
793
794 ret = -EBUSY;
795 if (loops != 0)
796 ret = 0;
797
798 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
799 tw32_f(MAC_MI_MODE, tp->mi_mode);
800 udelay(80);
801 }
802
803 return ret;
804}
805
9ef8ca99
MC		 806static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
807{
808 u32 phy;
809
810 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
811 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
812 return;
813
814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
815 u32 ephy;
816
817 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
818 tg3_writephy(tp, MII_TG3_EPHY_TEST,
819 ephy | MII_TG3_EPHY_SHADOW_EN);
820 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
821 if (enable)
822 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
823 else
824 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
825 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
826 }
827 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
828 }
829 } else {
830 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
831 MII_TG3_AUXCTL_SHDWSEL_MISC;
832 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
833 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
834 if (enable)
835 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
836 else
837 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
838 phy |= MII_TG3_AUXCTL_MISC_WREN;
839 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
840 }
841 }
842}
843
1da177e4
LT		 844static void tg3_phy_set_wirespeed(struct tg3 *tp)
845{
846 u32 val;
847
848 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
849 return;
850
851 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
852 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
853 tg3_writephy(tp, MII_TG3_AUX_CTRL,
854 (val | (1 << 15) | (1 << 4)));
855}
856
857static int tg3_bmcr_reset(struct tg3 *tp)
858{
859 u32 phy_control;
860 int limit, err;
861
862 /* OK, reset it, and poll the BMCR_RESET bit until it
863 * clears or we time out.
864 */
865 phy_control = BMCR_RESET;
866 err = tg3_writephy(tp, MII_BMCR, phy_control);
867 if (err != 0)
868 return -EBUSY;
869
870 limit = 5000;
871 while (limit--) {
872 err = tg3_readphy(tp, MII_BMCR, &phy_control);
873 if (err != 0)
874 return -EBUSY;
875
876 if ((phy_control & BMCR_RESET) == 0) {
877 udelay(40);
878 break;
879 }
880 udelay(10);
881 }
882 if (limit <= 0)
883 return -EBUSY;
884
885 return 0;
886}
887
888static int tg3_wait_macro_done(struct tg3 *tp)
889{
890 int limit = 100;
891
892 while (limit--) {
893 u32 tmp32;
894
895 if (!tg3_readphy(tp, 0x16, &tmp32)) {
896 if ((tmp32 & 0x1000) == 0)
897 break;
898 }
899 }
900 if (limit <= 0)
901 return -EBUSY;
902
903 return 0;
904}
905
906static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
907{
908 static const u32 test_pat[4][6] = {
909 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
910 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
911 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
912 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
913 };
914 int chan;
915
916 for (chan = 0; chan < 4; chan++) {
917 int i;
918
919 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
920 (chan * 0x2000) | 0x0200);
921 tg3_writephy(tp, 0x16, 0x0002);
922
923 for (i = 0; i < 6; i++)
924 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
925 test_pat[chan][i]);
926
927 tg3_writephy(tp, 0x16, 0x0202);
928 if (tg3_wait_macro_done(tp)) {
929 *resetp = 1;
930 return -EBUSY;
931 }
932
933 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
934 (chan * 0x2000) | 0x0200);
935 tg3_writephy(tp, 0x16, 0x0082);
936 if (tg3_wait_macro_done(tp)) {
937 *resetp = 1;
938 return -EBUSY;
939 }
940
941 tg3_writephy(tp, 0x16, 0x0802);
942 if (tg3_wait_macro_done(tp)) {
943 *resetp = 1;
944 return -EBUSY;
945 }
946
947 for (i = 0; i < 6; i += 2) {
948 u32 low, high;
949
950 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
951 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
952 tg3_wait_macro_done(tp)) {
953 *resetp = 1;
954 return -EBUSY;
955 }
956 low &= 0x7fff;
957 high &= 0x000f;
958 if (low != test_pat[chan][i] ||
959 high != test_pat[chan][i+1]) {
960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
962 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
963
964 return -EBUSY;
965 }
966 }
967 }
968
969 return 0;
970}
971
972static int tg3_phy_reset_chanpat(struct tg3 *tp)
973{
974 int chan;
975
976 for (chan = 0; chan < 4; chan++) {
977 int i;
978
979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
980 (chan * 0x2000) | 0x0200);
981 tg3_writephy(tp, 0x16, 0x0002);
982 for (i = 0; i < 6; i++)
983 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
984 tg3_writephy(tp, 0x16, 0x0202);
985 if (tg3_wait_macro_done(tp))
986 return -EBUSY;
987 }
988
989 return 0;
990}
991
992static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
993{
994 u32 reg32, phy9_orig;
995 int retries, do_phy_reset, err;
996
997 retries = 10;
998 do_phy_reset = 1;
999 do {
1000 if (do_phy_reset) {
1001 err = tg3_bmcr_reset(tp);
1002 if (err)
1003 return err;
1004 do_phy_reset = 0;
1005 }
1006
1007 /* Disable transmitter and interrupt. */
1008 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1009 continue;
1010
1011 reg32 |= 0x3000;
1012 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1013
1014 /* Set full-duplex, 1000 mbps. */
1015 tg3_writephy(tp, MII_BMCR,
1016 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1017
1018 /* Set to master mode. */
1019 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1020 continue;
1021
1022 tg3_writephy(tp, MII_TG3_CTRL,
1023 (MII_TG3_CTRL_AS_MASTER |
1024 MII_TG3_CTRL_ENABLE_AS_MASTER));
1025
1026 /* Enable SM_DSP_CLOCK and 6dB. */
1027 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1028
1029 /* Block the PHY control access. */
1030 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1031 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1032
1033 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1034 if (!err)
1035 break;
1036 } while (--retries);
1037
1038 err = tg3_phy_reset_chanpat(tp);
1039 if (err)
1040 return err;
1041
1042 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1043 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1044
1045 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1046 tg3_writephy(tp, 0x16, 0x0000);
1047
1048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1050 /* Set Extended packet length bit for jumbo frames */
1051 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1052 }
1053 else {
1054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1055 }
1056
1057 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1058
1059 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1060 reg32 &= ~0x3000;
1061 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1062 } else if (!err)
1063 err = -EBUSY;
1064
1065 return err;
1066}
1067
c8e1e82b
MC		 1068static void tg3_link_report(struct tg3 *);
1069
1da177e4
LT		 1070/* This will reset the tigon3 PHY if there is no valid
1071 * link unless the FORCE argument is non-zero.
1072 */
1073static int tg3_phy_reset(struct tg3 *tp)
1074{
1075 u32 phy_status;
1076 int err;
1077
60189ddf
MC		 1078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1079 u32 val;
1080
1081 val = tr32(GRC_MISC_CFG);
1082 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1083 udelay(40);
1084 }
1da177e4
LT		 1085 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1086 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1087 if (err != 0)
1088 return -EBUSY;
1089
c8e1e82b
MC		 1090 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1091 netif_carrier_off(tp->dev);
1092 tg3_link_report(tp);
1093 }
1094
1da177e4
LT		 1095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1098 err = tg3_phy_reset_5703_4_5(tp);
1099 if (err)
1100 return err;
1101 goto out;
1102 }
1103
1104 err = tg3_bmcr_reset(tp);
1105 if (err)
1106 return err;
1107
1108out:
1109 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1110 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1111 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1112 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1113 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1114 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1115 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1116 }
1117 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1118 tg3_writephy(tp, 0x1c, 0x8d68);
1119 tg3_writephy(tp, 0x1c, 0x8d68);
1120 }
1121 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1122 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1123 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1124 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1125 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1126 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1127 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1128 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1129 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1130 }
c424cb24
MC		 1131 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1132 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1133 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1134 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1135 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1136 tg3_writephy(tp, MII_TG3_TEST1,
1137 MII_TG3_TEST1_TRIM_EN | 0x4);
1138 } else
1139 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1140 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1141 }
1da177e4
LT		 1142 /* Set Extended packet length bit (bit 14) on all chips that */
1143 /* support jumbo frames */
1144 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1145 /* Cannot do read-modify-write on 5401 */
1146 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1147 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1148 u32 phy_reg;
1149
1150 /* Set bit 14 with read-modify-write to preserve other bits */
1151 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1152 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1153 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1154 }
1155
1156 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1157 * jumbo frames transmission.
1158 */
0f893dc6 1159 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1160 u32 phy_reg;
1161
1162 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1163 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1164 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1165 }
1166
715116a1 1167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1168 /* adjust output voltage */
1169 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1170 }
1171
9ef8ca99 1172 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1173 tg3_phy_set_wirespeed(tp);
1174 return 0;
1175}
1176
1177static void tg3_frob_aux_power(struct tg3 *tp)
1178{
1179 struct tg3 *tp_peer = tp;
1180
9d26e213 1181 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1182 return;
1183
8c2dc7e1
MC		 1184 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1185 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1186 struct net_device *dev_peer;
1187
1188 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1189 /* remove_one() may have been run on the peer. */
8c2dc7e1 1190 if (!dev_peer)
bc1c7567
MC		 1191 tp_peer = tp;
1192 else
1193 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1194 }
1195
1da177e4 1196 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1197 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1198 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1199 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1202 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1203 (GRC_LCLCTRL_GPIO_OE0 |
1204 GRC_LCLCTRL_GPIO_OE1 |
1205 GRC_LCLCTRL_GPIO_OE2 |
1206 GRC_LCLCTRL_GPIO_OUTPUT0 |
1207 GRC_LCLCTRL_GPIO_OUTPUT1),
1208 100);
1da177e4
LT		 1209 } else {
1210 u32 no_gpio2;
dc56b7d4 1211 u32 grc_local_ctrl = 0;
1da177e4
LT		 1212
1213 if (tp_peer != tp &&
1214 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1215 return;
1216
dc56b7d4
MC		 1217 /* Workaround to prevent overdrawing Amps. */
1218 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1219 ASIC_REV_5714) {
1220 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1221 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1222 grc_local_ctrl, 100);
dc56b7d4
MC		 1223 }
1224
1da177e4
LT		 1225 /* On 5753 and variants, GPIO2 cannot be used. */
1226 no_gpio2 = tp->nic_sram_data_cfg &
1227 NIC_SRAM_DATA_CFG_NO_GPIO2;
1228
dc56b7d4 1229 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1230 GRC_LCLCTRL_GPIO_OE1 |
1231 GRC_LCLCTRL_GPIO_OE2 |
1232 GRC_LCLCTRL_GPIO_OUTPUT1 |
1233 GRC_LCLCTRL_GPIO_OUTPUT2;
1234 if (no_gpio2) {
1235 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1236 GRC_LCLCTRL_GPIO_OUTPUT2);
1237 }
b401e9e2
MC		 1238 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1239 grc_local_ctrl, 100);
1da177e4
LT		 1240
1241 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1242
b401e9e2
MC		 1243 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1244 grc_local_ctrl, 100);
1da177e4
LT		 1245
1246 if (!no_gpio2) {
1247 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1248 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1249 grc_local_ctrl, 100);
1da177e4
LT		 1250 }
1251 }
1252 } else {
1253 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1254 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1255 if (tp_peer != tp &&
1256 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1257 return;
1258
b401e9e2
MC		 1259 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1260 (GRC_LCLCTRL_GPIO_OE1 |
1261 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1262
b401e9e2
MC		 1263 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1264 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1265
b401e9e2
MC		 1266 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1267 (GRC_LCLCTRL_GPIO_OE1 |
1268 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1269 }
1270 }
1271}
1272
e8f3f6ca
MC		 1273static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1274{
1275 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1276 return 1;
1277 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1278 if (speed != SPEED_10)
1279 return 1;
1280 } else if (speed == SPEED_10)
1281 return 1;
1282
1283 return 0;
1284}
1285
1da177e4
LT		 1286static int tg3_setup_phy(struct tg3 *, int);
1287
1288#define RESET_KIND_SHUTDOWN 0
1289#define RESET_KIND_INIT 1
1290#define RESET_KIND_SUSPEND 2
1291
1292static void tg3_write_sig_post_reset(struct tg3 *, int);
1293static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1294static int tg3_nvram_lock(struct tg3 *);
1295static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1296
15c3b696
MC		 1297static void tg3_power_down_phy(struct tg3 *tp)
1298{
5129724a
MC		 1299 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1301 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1302 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1303
1304 sg_dig_ctrl |=
1305 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1306 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1307 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1308 }
3f7045c1 1309 return;
5129724a 1310 }
3f7045c1 1311
60189ddf
MC		 1312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1313 u32 val;
1314
1315 tg3_bmcr_reset(tp);
1316 val = tr32(GRC_MISC_CFG);
1317 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1318 udelay(40);
1319 return;
1320 } else {
715116a1
MC		 1321 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1322 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1323 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1324 }
3f7045c1 1325
15c3b696
MC		 1326 /* The PHY should not be powered down on some chips because
1327 * of bugs.
1328 */
1329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1330 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1331 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1332 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1333 return;
1334 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1335}
1336
bc1c7567 1337static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1338{
1339 u32 misc_host_ctrl;
1340 u16 power_control, power_caps;
1341 int pm = tp->pm_cap;
1342
1343 /* Make sure register accesses (indirect or otherwise)
1344 * will function correctly.
1345 */
1346 pci_write_config_dword(tp->pdev,
1347 TG3PCI_MISC_HOST_CTRL,
1348 tp->misc_host_ctrl);
1349
1350 pci_read_config_word(tp->pdev,
1351 pm + PCI_PM_CTRL,
1352 &power_control);
1353 power_control |= PCI_PM_CTRL_PME_STATUS;
1354 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1355 switch (state) {
bc1c7567 1356 case PCI_D0:
1da177e4
LT		 1357 power_control |= 0;
1358 pci_write_config_word(tp->pdev,
1359 pm + PCI_PM_CTRL,
1360 power_control);
8c6bda1a
MC		 1361 udelay(100); /* Delay after power state change */
1362
9d26e213
MC		 1363 /* Switch out of Vaux if it is a NIC */
1364 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1365 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1366
1367 return 0;
1368
bc1c7567 1369 case PCI_D1:
1da177e4
LT		 1370 power_control |= 1;
1371 break;
1372
bc1c7567 1373 case PCI_D2:
1da177e4
LT		 1374 power_control |= 2;
1375 break;
1376
bc1c7567 1377 case PCI_D3hot:
1da177e4
LT		 1378 power_control |= 3;
1379 break;
1380
1381 default:
1382 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1383 "requested.\n",
1384 tp->dev->name, state);
1385 return -EINVAL;
1386 };
1387
1388 power_control |= PCI_PM_CTRL_PME_ENABLE;
1389
1390 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1391 tw32(TG3PCI_MISC_HOST_CTRL,
1392 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1393
1394 if (tp->link_config.phy_is_low_power == 0) {
1395 tp->link_config.phy_is_low_power = 1;
1396 tp->link_config.orig_speed = tp->link_config.speed;
1397 tp->link_config.orig_duplex = tp->link_config.duplex;
1398 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1399 }
1400
747e8f8b 1401 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1402 tp->link_config.speed = SPEED_10;
1403 tp->link_config.duplex = DUPLEX_HALF;
1404 tp->link_config.autoneg = AUTONEG_ENABLE;
1405 tg3_setup_phy(tp, 0);
1406 }
1407
b5d3772c
MC		 1408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1409 u32 val;
1410
1411 val = tr32(GRC_VCPU_EXT_CTRL);
1412 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1413 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1414 int i;
1415 u32 val;
1416
1417 for (i = 0; i < 200; i++) {
1418 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1419 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1420 break;
1421 msleep(1);
1422 }
1423 }
a85feb8c
GZ		 1424 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1425 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1426 WOL_DRV_STATE_SHUTDOWN |
1427 WOL_DRV_WOL |
1428 WOL_SET_MAGIC_PKT);
6921d201 1429
1da177e4
LT		 1430 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1431
1432 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1433 u32 mac_mode;
1434
1435 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1436 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1437 udelay(40);
1438
3f7045c1
MC		 1439 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1440 mac_mode = MAC_MODE_PORT_MODE_GMII;
1441 else
1442 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 1443
e8f3f6ca
MC		 1444 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1445 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1446 ASIC_REV_5700) {
1447 u32 speed = (tp->tg3_flags &
1448 TG3_FLAG_WOL_SPEED_100MB) ?
1449 SPEED_100 : SPEED_10;
1450 if (tg3_5700_link_polarity(tp, speed))
1451 mac_mode |= MAC_MODE_LINK_POLARITY;
1452 else
1453 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1454 }
1da177e4
LT		 1455 } else {
1456 mac_mode = MAC_MODE_PORT_MODE_TBI;
1457 }
1458
cbf46853 1459 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1460 tw32(MAC_LED_CTRL, tp->led_ctrl);
1461
1462 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1463 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1464 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1465
1466 tw32_f(MAC_MODE, mac_mode);
1467 udelay(100);
1468
1469 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1470 udelay(10);
1471 }
1472
1473 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1474 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1476 u32 base_val;
1477
1478 base_val = tp->pci_clock_ctrl;
1479 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1480 CLOCK_CTRL_TXCLK_DISABLE);
1481
b401e9e2
MC		 1482 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1483 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 1484 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 1485 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 1486 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1487 /* do nothing */
85e94ced 1488 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1489 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1490 u32 newbits1, newbits2;
1491
1492 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1494 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1495 CLOCK_CTRL_TXCLK_DISABLE |
1496 CLOCK_CTRL_ALTCLK);
1497 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1498 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1499 newbits1 = CLOCK_CTRL_625_CORE;
1500 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1501 } else {
1502 newbits1 = CLOCK_CTRL_ALTCLK;
1503 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1504 }
1505
b401e9e2
MC		 1506 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1507 40);
1da177e4 1508
b401e9e2
MC		 1509 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1510 40);
1da177e4
LT		 1511
1512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1513 u32 newbits3;
1514
1515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1517 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1518 CLOCK_CTRL_TXCLK_DISABLE |
1519 CLOCK_CTRL_44MHZ_CORE);
1520 } else {
1521 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1522 }
1523
b401e9e2
MC		 1524 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1525 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1526 }
1527 }
1528
6921d201 1529 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
0d3031d9
MC		 1530 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1531 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
3f7045c1 1532 tg3_power_down_phy(tp);
6921d201 1533
1da177e4
LT		 1534 tg3_frob_aux_power(tp);
1535
1536 /* Workaround for unstable PLL clock */
1537 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1538 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1539 u32 val = tr32(0x7d00);
1540
1541 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1542 tw32(0x7d00, val);
6921d201 1543 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1544 int err;
1545
1546 err = tg3_nvram_lock(tp);
1da177e4 1547 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1548 if (!err)
1549 tg3_nvram_unlock(tp);
6921d201 1550 }
1da177e4
LT		 1551 }
1552
bbadf503
MC		 1553 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1554
1da177e4
LT		 1555 /* Finally, set the new power state. */
1556 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1557 udelay(100); /* Delay after power state change */
1da177e4 1558
1da177e4
LT		 1559 return 0;
1560}
1561
1562static void tg3_link_report(struct tg3 *tp)
1563{
1564 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1565 if (netif_msg_link(tp))
1566 printk(KERN_INFO PFX "%s: Link is down.\n",
1567 tp->dev->name);
1568 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1569 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1570 tp->dev->name,
1571 (tp->link_config.active_speed == SPEED_1000 ?
1572 1000 :
1573 (tp->link_config.active_speed == SPEED_100 ?
1574 100 : 10)),
1575 (tp->link_config.active_duplex == DUPLEX_FULL ?
1576 "full" : "half"));
1577
1578 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1579 "%s for RX.\n",
1580 tp->dev->name,
1581 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1582 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1583 }
1584}
1585
1586static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1587{
1588 u32 new_tg3_flags = 0;
1589 u32 old_rx_mode = tp->rx_mode;
1590 u32 old_tx_mode = tp->tx_mode;
1591
1592 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1593
1594 /* Convert 1000BaseX flow control bits to 1000BaseT
1595 * bits before resolving flow control.
1596 */
1597 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1598 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1599 ADVERTISE_PAUSE_ASYM);
1600 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1601
1602 if (local_adv & ADVERTISE_1000XPAUSE)
1603 local_adv |= ADVERTISE_PAUSE_CAP;
1604 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1605 local_adv |= ADVERTISE_PAUSE_ASYM;
1606 if (remote_adv & LPA_1000XPAUSE)
1607 remote_adv |= LPA_PAUSE_CAP;
1608 if (remote_adv & LPA_1000XPAUSE_ASYM)
1609 remote_adv |= LPA_PAUSE_ASYM;
1610 }
1611
1da177e4
LT		 1612 if (local_adv & ADVERTISE_PAUSE_CAP) {
1613 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1614 if (remote_adv & LPA_PAUSE_CAP)
1615 new_tg3_flags |=
1616 (TG3_FLAG_RX_PAUSE |
1617 TG3_FLAG_TX_PAUSE);
1618 else if (remote_adv & LPA_PAUSE_ASYM)
1619 new_tg3_flags |=
1620 (TG3_FLAG_RX_PAUSE);
1621 } else {
1622 if (remote_adv & LPA_PAUSE_CAP)
1623 new_tg3_flags |=
1624 (TG3_FLAG_RX_PAUSE |
1625 TG3_FLAG_TX_PAUSE);
1626 }
1627 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1628 if ((remote_adv & LPA_PAUSE_CAP) &&
1629 (remote_adv & LPA_PAUSE_ASYM))
1630 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1631 }
1632
1633 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1634 tp->tg3_flags |= new_tg3_flags;
1635 } else {
1636 new_tg3_flags = tp->tg3_flags;
1637 }
1638
1639 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1640 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1641 else
1642 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1643
1644 if (old_rx_mode != tp->rx_mode) {
1645 tw32_f(MAC_RX_MODE, tp->rx_mode);
1646 }
6aa20a22 1647
1da177e4
LT		 1648 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1649 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1650 else
1651 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1652
1653 if (old_tx_mode != tp->tx_mode) {
1654 tw32_f(MAC_TX_MODE, tp->tx_mode);
1655 }
1656}
1657
1658static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1659{
1660 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1661 case MII_TG3_AUX_STAT_10HALF:
1662 *speed = SPEED_10;
1663 *duplex = DUPLEX_HALF;
1664 break;
1665
1666 case MII_TG3_AUX_STAT_10FULL:
1667 *speed = SPEED_10;
1668 *duplex = DUPLEX_FULL;
1669 break;
1670
1671 case MII_TG3_AUX_STAT_100HALF:
1672 *speed = SPEED_100;
1673 *duplex = DUPLEX_HALF;
1674 break;
1675
1676 case MII_TG3_AUX_STAT_100FULL:
1677 *speed = SPEED_100;
1678 *duplex = DUPLEX_FULL;
1679 break;
1680
1681 case MII_TG3_AUX_STAT_1000HALF:
1682 *speed = SPEED_1000;
1683 *duplex = DUPLEX_HALF;
1684 break;
1685
1686 case MII_TG3_AUX_STAT_1000FULL:
1687 *speed = SPEED_1000;
1688 *duplex = DUPLEX_FULL;
1689 break;
1690
1691 default:
715116a1
MC		 1692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1693 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1694 SPEED_10;
1695 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1696 DUPLEX_HALF;
1697 break;
1698 }
1da177e4
LT		 1699 *speed = SPEED_INVALID;
1700 *duplex = DUPLEX_INVALID;
1701 break;
1702 };
1703}
1704
1705static void tg3_phy_copper_begin(struct tg3 *tp)
1706{
1707 u32 new_adv;
1708 int i;
1709
1710 if (tp->link_config.phy_is_low_power) {
1711 /* Entering low power mode. Disable gigabit and
1712 * 100baseT advertisements.
1713 */
1714 tg3_writephy(tp, MII_TG3_CTRL, 0);
1715
1716 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1717 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1718 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1719 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1720
1721 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1722 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1723 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1724 tp->link_config.advertising &=
1725 ~(ADVERTISED_1000baseT_Half |
1726 ADVERTISED_1000baseT_Full);
1727
1728 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1729 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1730 new_adv |= ADVERTISE_10HALF;
1731 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1732 new_adv |= ADVERTISE_10FULL;
1733 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1734 new_adv |= ADVERTISE_100HALF;
1735 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1736 new_adv |= ADVERTISE_100FULL;
1737 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1738
1739 if (tp->link_config.advertising &
1740 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1741 new_adv = 0;
1742 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1743 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1744 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1745 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1746 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1747 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1748 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1749 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1750 MII_TG3_CTRL_ENABLE_AS_MASTER);
1751 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1752 } else {
1753 tg3_writephy(tp, MII_TG3_CTRL, 0);
1754 }
1755 } else {
1756 /* Asking for a specific link mode. */
1757 if (tp->link_config.speed == SPEED_1000) {
1758 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1759 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1760
1761 if (tp->link_config.duplex == DUPLEX_FULL)
1762 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1763 else
1764 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1765 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1766 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1767 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1768 MII_TG3_CTRL_ENABLE_AS_MASTER);
1769 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1770 } else {
1771 tg3_writephy(tp, MII_TG3_CTRL, 0);
1772
1773 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1774 if (tp->link_config.speed == SPEED_100) {
1775 if (tp->link_config.duplex == DUPLEX_FULL)
1776 new_adv |= ADVERTISE_100FULL;
1777 else
1778 new_adv |= ADVERTISE_100HALF;
1779 } else {
1780 if (tp->link_config.duplex == DUPLEX_FULL)
1781 new_adv |= ADVERTISE_10FULL;
1782 else
1783 new_adv |= ADVERTISE_10HALF;
1784 }
1785 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1786 }
1787 }
1788
1789 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1790 tp->link_config.speed != SPEED_INVALID) {
1791 u32 bmcr, orig_bmcr;
1792
1793 tp->link_config.active_speed = tp->link_config.speed;
1794 tp->link_config.active_duplex = tp->link_config.duplex;
1795
1796 bmcr = 0;
1797 switch (tp->link_config.speed) {
1798 default:
1799 case SPEED_10:
1800 break;
1801
1802 case SPEED_100:
1803 bmcr |= BMCR_SPEED100;
1804 break;
1805
1806 case SPEED_1000:
1807 bmcr |= TG3_BMCR_SPEED1000;
1808 break;
1809 };
1810
1811 if (tp->link_config.duplex == DUPLEX_FULL)
1812 bmcr |= BMCR_FULLDPLX;
1813
1814 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1815 (bmcr != orig_bmcr)) {
1816 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1817 for (i = 0; i < 1500; i++) {
1818 u32 tmp;
1819
1820 udelay(10);
1821 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1822 tg3_readphy(tp, MII_BMSR, &tmp))
1823 continue;
1824 if (!(tmp & BMSR_LSTATUS)) {
1825 udelay(40);
1826 break;
1827 }
1828 }
1829 tg3_writephy(tp, MII_BMCR, bmcr);
1830 udelay(40);
1831 }
1832 } else {
1833 tg3_writephy(tp, MII_BMCR,
1834 BMCR_ANENABLE | BMCR_ANRESTART);
1835 }
1836}
1837
1838static int tg3_init_5401phy_dsp(struct tg3 *tp)
1839{
1840 int err;
1841
1842 /* Turn off tap power management. */
1843 /* Set Extended packet length bit */
1844 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1845
1846 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1847 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1848
1849 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1850 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1851
1852 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1853 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1854
1855 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1856 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1857
1858 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1859 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1860
1861 udelay(40);
1862
1863 return err;
1864}
1865
3600d918 1866static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1867{
3600d918
MC		 1868 u32 adv_reg, all_mask = 0;
1869
1870 if (mask & ADVERTISED_10baseT_Half)
1871 all_mask |= ADVERTISE_10HALF;
1872 if (mask & ADVERTISED_10baseT_Full)
1873 all_mask |= ADVERTISE_10FULL;
1874 if (mask & ADVERTISED_100baseT_Half)
1875 all_mask |= ADVERTISE_100HALF;
1876 if (mask & ADVERTISED_100baseT_Full)
1877 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1878
1879 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1880 return 0;
1881
1da177e4
LT		 1882 if ((adv_reg & all_mask) != all_mask)
1883 return 0;
1884 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1885 u32 tg3_ctrl;
1886
3600d918
MC		 1887 all_mask = 0;
1888 if (mask & ADVERTISED_1000baseT_Half)
1889 all_mask |= ADVERTISE_1000HALF;
1890 if (mask & ADVERTISED_1000baseT_Full)
1891 all_mask |= ADVERTISE_1000FULL;
1892
1da177e4
LT		 1893 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1894 return 0;
1895
1da177e4
LT		 1896 if ((tg3_ctrl & all_mask) != all_mask)
1897 return 0;
1898 }
1899 return 1;
1900}
1901
1902static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1903{
1904 int current_link_up;
1905 u32 bmsr, dummy;
1906 u16 current_speed;
1907 u8 current_duplex;
1908 int i, err;
1909
1910 tw32(MAC_EVENT, 0);
1911
1912 tw32_f(MAC_STATUS,
1913 (MAC_STATUS_SYNC_CHANGED |
1914 MAC_STATUS_CFG_CHANGED |
1915 MAC_STATUS_MI_COMPLETION |
1916 MAC_STATUS_LNKSTATE_CHANGED));
1917 udelay(40);
1918
1919 tp->mi_mode = MAC_MI_MODE_BASE;
1920 tw32_f(MAC_MI_MODE, tp->mi_mode);
1921 udelay(80);
1922
1923 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1924
1925 /* Some third-party PHYs need to be reset on link going
1926 * down.
1927 */
1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1931 netif_carrier_ok(tp->dev)) {
1932 tg3_readphy(tp, MII_BMSR, &bmsr);
1933 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934 !(bmsr & BMSR_LSTATUS))
1935 force_reset = 1;
1936 }
1937 if (force_reset)
1938 tg3_phy_reset(tp);
1939
1940 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1941 tg3_readphy(tp, MII_BMSR, &bmsr);
1942 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1943 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1944 bmsr = 0;
1945
1946 if (!(bmsr & BMSR_LSTATUS)) {
1947 err = tg3_init_5401phy_dsp(tp);
1948 if (err)
1949 return err;
1950
1951 tg3_readphy(tp, MII_BMSR, &bmsr);
1952 for (i = 0; i < 1000; i++) {
1953 udelay(10);
1954 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1955 (bmsr & BMSR_LSTATUS)) {
1956 udelay(40);
1957 break;
1958 }
1959 }
1960
1961 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1962 !(bmsr & BMSR_LSTATUS) &&
1963 tp->link_config.active_speed == SPEED_1000) {
1964 err = tg3_phy_reset(tp);
1965 if (!err)
1966 err = tg3_init_5401phy_dsp(tp);
1967 if (err)
1968 return err;
1969 }
1970 }
1971 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1972 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1973 /* 5701 {A0,B0} CRC bug workaround */
1974 tg3_writephy(tp, 0x15, 0x0a75);
1975 tg3_writephy(tp, 0x1c, 0x8c68);
1976 tg3_writephy(tp, 0x1c, 0x8d68);
1977 tg3_writephy(tp, 0x1c, 0x8c68);
1978 }
1979
1980 /* Clear pending interrupts... */
1981 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1982 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1983
1984 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1985 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 1986 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 1987 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1988
1989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1991 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1992 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1993 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1994 else
1995 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1996 }
1997
1998 current_link_up = 0;
1999 current_speed = SPEED_INVALID;
2000 current_duplex = DUPLEX_INVALID;
2001
2002 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2003 u32 val;
2004
2005 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2006 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2007 if (!(val & (1 << 10))) {
2008 val |= (1 << 10);
2009 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2010 goto relink;
2011 }
2012 }
2013
2014 bmsr = 0;
2015 for (i = 0; i < 100; i++) {
2016 tg3_readphy(tp, MII_BMSR, &bmsr);
2017 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2018 (bmsr & BMSR_LSTATUS))
2019 break;
2020 udelay(40);
2021 }
2022
2023 if (bmsr & BMSR_LSTATUS) {
2024 u32 aux_stat, bmcr;
2025
2026 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2027 for (i = 0; i < 2000; i++) {
2028 udelay(10);
2029 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2030 aux_stat)
2031 break;
2032 }
2033
2034 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2035 &current_speed,
2036 &current_duplex);
2037
2038 bmcr = 0;
2039 for (i = 0; i < 200; i++) {
2040 tg3_readphy(tp, MII_BMCR, &bmcr);
2041 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2042 continue;
2043 if (bmcr && bmcr != 0x7fff)
2044 break;
2045 udelay(10);
2046 }
2047
2048 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2049 if (bmcr & BMCR_ANENABLE) {
2050 current_link_up = 1;
2051
2052 /* Force autoneg restart if we are exiting
2053 * low power mode.
2054 */
3600d918
MC		 2055 if (!tg3_copper_is_advertising_all(tp,
2056 tp->link_config.advertising))
1da177e4
LT		 2057 current_link_up = 0;
2058 } else {
2059 current_link_up = 0;
2060 }
2061 } else {
2062 if (!(bmcr & BMCR_ANENABLE) &&
2063 tp->link_config.speed == current_speed &&
2064 tp->link_config.duplex == current_duplex) {
2065 current_link_up = 1;
2066 } else {
2067 current_link_up = 0;
2068 }
2069 }
2070
2071 tp->link_config.active_speed = current_speed;
2072 tp->link_config.active_duplex = current_duplex;
2073 }
2074
2075 if (current_link_up == 1 &&
2076 (tp->link_config.active_duplex == DUPLEX_FULL) &&
2077 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2078 u32 local_adv, remote_adv;
2079
2080 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
2081 local_adv = 0;
2082 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2083
2084 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2085 remote_adv = 0;
2086
2087 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2088
2089 /* If we are not advertising full pause capability,
2090 * something is wrong. Bring the link down and reconfigure.
2091 */
2092 if (local_adv != ADVERTISE_PAUSE_CAP) {
2093 current_link_up = 0;
2094 } else {
2095 tg3_setup_flow_control(tp, local_adv, remote_adv);
2096 }
2097 }
2098relink:
6921d201 2099 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 2100 u32 tmp;
2101
2102 tg3_phy_copper_begin(tp);
2103
2104 tg3_readphy(tp, MII_BMSR, &tmp);
2105 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2106 (tmp & BMSR_LSTATUS))
2107 current_link_up = 1;
2108 }
2109
2110 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2111 if (current_link_up == 1) {
2112 if (tp->link_config.active_speed == SPEED_100 ||
2113 tp->link_config.active_speed == SPEED_10)
2114 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2115 else
2116 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2117 } else
2118 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2119
2120 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2121 if (tp->link_config.active_duplex == DUPLEX_HALF)
2122 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2123
1da177e4 2124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 2125 if (current_link_up == 1 &&
2126 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 2127 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 2128 else
2129 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 2130 }
2131
2132 /* ??? Without this setting Netgear GA302T PHY does not
2133 * ??? send/receive packets...
2134 */
2135 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2136 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2137 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2138 tw32_f(MAC_MI_MODE, tp->mi_mode);
2139 udelay(80);
2140 }
2141
2142 tw32_f(MAC_MODE, tp->mac_mode);
2143 udelay(40);
2144
2145 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2146 /* Polled via timer. */
2147 tw32_f(MAC_EVENT, 0);
2148 } else {
2149 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2150 }
2151 udelay(40);
2152
2153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2154 current_link_up == 1 &&
2155 tp->link_config.active_speed == SPEED_1000 &&
2156 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2157 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2158 udelay(120);
2159 tw32_f(MAC_STATUS,
2160 (MAC_STATUS_SYNC_CHANGED |
2161 MAC_STATUS_CFG_CHANGED));
2162 udelay(40);
2163 tg3_write_mem(tp,
2164 NIC_SRAM_FIRMWARE_MBOX,
2165 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2166 }
2167
2168 if (current_link_up != netif_carrier_ok(tp->dev)) {
2169 if (current_link_up)
2170 netif_carrier_on(tp->dev);
2171 else
2172 netif_carrier_off(tp->dev);
2173 tg3_link_report(tp);
2174 }
2175
2176 return 0;
2177}
2178
2179struct tg3_fiber_aneginfo {
2180 int state;
2181#define ANEG_STATE_UNKNOWN 0
2182#define ANEG_STATE_AN_ENABLE 1
2183#define ANEG_STATE_RESTART_INIT 2
2184#define ANEG_STATE_RESTART 3
2185#define ANEG_STATE_DISABLE_LINK_OK 4
2186#define ANEG_STATE_ABILITY_DETECT_INIT 5
2187#define ANEG_STATE_ABILITY_DETECT 6
2188#define ANEG_STATE_ACK_DETECT_INIT 7
2189#define ANEG_STATE_ACK_DETECT 8
2190#define ANEG_STATE_COMPLETE_ACK_INIT 9
2191#define ANEG_STATE_COMPLETE_ACK 10
2192#define ANEG_STATE_IDLE_DETECT_INIT 11
2193#define ANEG_STATE_IDLE_DETECT 12
2194#define ANEG_STATE_LINK_OK 13
2195#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2196#define ANEG_STATE_NEXT_PAGE_WAIT 15
2197
2198 u32 flags;
2199#define MR_AN_ENABLE 0x00000001
2200#define MR_RESTART_AN 0x00000002
2201#define MR_AN_COMPLETE 0x00000004
2202#define MR_PAGE_RX 0x00000008
2203#define MR_NP_LOADED 0x00000010
2204#define MR_TOGGLE_TX 0x00000020
2205#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2206#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2207#define MR_LP_ADV_SYM_PAUSE 0x00000100
2208#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2209#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2210#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2211#define MR_LP_ADV_NEXT_PAGE 0x00001000
2212#define MR_TOGGLE_RX 0x00002000
2213#define MR_NP_RX 0x00004000
2214
2215#define MR_LINK_OK 0x80000000
2216
2217 unsigned long link_time, cur_time;
2218
2219 u32 ability_match_cfg;
2220 int ability_match_count;
2221
2222 char ability_match, idle_match, ack_match;
2223
2224 u32 txconfig, rxconfig;
2225#define ANEG_CFG_NP 0x00000080
2226#define ANEG_CFG_ACK 0x00000040
2227#define ANEG_CFG_RF2 0x00000020
2228#define ANEG_CFG_RF1 0x00000010
2229#define ANEG_CFG_PS2 0x00000001
2230#define ANEG_CFG_PS1 0x00008000
2231#define ANEG_CFG_HD 0x00004000
2232#define ANEG_CFG_FD 0x00002000
2233#define ANEG_CFG_INVAL 0x00001f06
2234
2235};
2236#define ANEG_OK 0
2237#define ANEG_DONE 1
2238#define ANEG_TIMER_ENAB 2
2239#define ANEG_FAILED -1
2240
2241#define ANEG_STATE_SETTLE_TIME 10000
2242
2243static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2244 struct tg3_fiber_aneginfo *ap)
2245{
2246 unsigned long delta;
2247 u32 rx_cfg_reg;
2248 int ret;
2249
2250 if (ap->state == ANEG_STATE_UNKNOWN) {
2251 ap->rxconfig = 0;
2252 ap->link_time = 0;
2253 ap->cur_time = 0;
2254 ap->ability_match_cfg = 0;
2255 ap->ability_match_count = 0;
2256 ap->ability_match = 0;
2257 ap->idle_match = 0;
2258 ap->ack_match = 0;
2259 }
2260 ap->cur_time++;
2261
2262 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2263 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2264
2265 if (rx_cfg_reg != ap->ability_match_cfg) {
2266 ap->ability_match_cfg = rx_cfg_reg;
2267 ap->ability_match = 0;
2268 ap->ability_match_count = 0;
2269 } else {
2270 if (++ap->ability_match_count > 1) {
2271 ap->ability_match = 1;
2272 ap->ability_match_cfg = rx_cfg_reg;
2273 }
2274 }
2275 if (rx_cfg_reg & ANEG_CFG_ACK)
2276 ap->ack_match = 1;
2277 else
2278 ap->ack_match = 0;
2279
2280 ap->idle_match = 0;
2281 } else {
2282 ap->idle_match = 1;
2283 ap->ability_match_cfg = 0;
2284 ap->ability_match_count = 0;
2285 ap->ability_match = 0;
2286 ap->ack_match = 0;
2287
2288 rx_cfg_reg = 0;
2289 }
2290
2291 ap->rxconfig = rx_cfg_reg;
2292 ret = ANEG_OK;
2293
2294 switch(ap->state) {
2295 case ANEG_STATE_UNKNOWN:
2296 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2297 ap->state = ANEG_STATE_AN_ENABLE;
2298
2299 /* fallthru */
2300 case ANEG_STATE_AN_ENABLE:
2301 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2302 if (ap->flags & MR_AN_ENABLE) {
2303 ap->link_time = 0;
2304 ap->cur_time = 0;
2305 ap->ability_match_cfg = 0;
2306 ap->ability_match_count = 0;
2307 ap->ability_match = 0;
2308 ap->idle_match = 0;
2309 ap->ack_match = 0;
2310
2311 ap->state = ANEG_STATE_RESTART_INIT;
2312 } else {
2313 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2314 }
2315 break;
2316
2317 case ANEG_STATE_RESTART_INIT:
2318 ap->link_time = ap->cur_time;
2319 ap->flags &= ~(MR_NP_LOADED);
2320 ap->txconfig = 0;
2321 tw32(MAC_TX_AUTO_NEG, 0);
2322 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2323 tw32_f(MAC_MODE, tp->mac_mode);
2324 udelay(40);
2325
2326 ret = ANEG_TIMER_ENAB;
2327 ap->state = ANEG_STATE_RESTART;
2328
2329 /* fallthru */
2330 case ANEG_STATE_RESTART:
2331 delta = ap->cur_time - ap->link_time;
2332 if (delta > ANEG_STATE_SETTLE_TIME) {
2333 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2334 } else {
2335 ret = ANEG_TIMER_ENAB;
2336 }
2337 break;
2338
2339 case ANEG_STATE_DISABLE_LINK_OK:
2340 ret = ANEG_DONE;
2341 break;
2342
2343 case ANEG_STATE_ABILITY_DETECT_INIT:
2344 ap->flags &= ~(MR_TOGGLE_TX);
2345 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2346 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2347 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2348 tw32_f(MAC_MODE, tp->mac_mode);
2349 udelay(40);
2350
2351 ap->state = ANEG_STATE_ABILITY_DETECT;
2352 break;
2353
2354 case ANEG_STATE_ABILITY_DETECT:
2355 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2356 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2357 }
2358 break;
2359
2360 case ANEG_STATE_ACK_DETECT_INIT:
2361 ap->txconfig |= ANEG_CFG_ACK;
2362 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2363 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2364 tw32_f(MAC_MODE, tp->mac_mode);
2365 udelay(40);
2366
2367 ap->state = ANEG_STATE_ACK_DETECT;
2368
2369 /* fallthru */
2370 case ANEG_STATE_ACK_DETECT:
2371 if (ap->ack_match != 0) {
2372 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2373 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2374 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2375 } else {
2376 ap->state = ANEG_STATE_AN_ENABLE;
2377 }
2378 } else if (ap->ability_match != 0 &&
2379 ap->rxconfig == 0) {
2380 ap->state = ANEG_STATE_AN_ENABLE;
2381 }
2382 break;
2383
2384 case ANEG_STATE_COMPLETE_ACK_INIT:
2385 if (ap->rxconfig & ANEG_CFG_INVAL) {
2386 ret = ANEG_FAILED;
2387 break;
2388 }
2389 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2390 MR_LP_ADV_HALF_DUPLEX |
2391 MR_LP_ADV_SYM_PAUSE |
2392 MR_LP_ADV_ASYM_PAUSE |
2393 MR_LP_ADV_REMOTE_FAULT1 |
2394 MR_LP_ADV_REMOTE_FAULT2 |
2395 MR_LP_ADV_NEXT_PAGE |
2396 MR_TOGGLE_RX |
2397 MR_NP_RX);
2398 if (ap->rxconfig & ANEG_CFG_FD)
2399 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2400 if (ap->rxconfig & ANEG_CFG_HD)
2401 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2402 if (ap->rxconfig & ANEG_CFG_PS1)
2403 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2404 if (ap->rxconfig & ANEG_CFG_PS2)
2405 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2406 if (ap->rxconfig & ANEG_CFG_RF1)
2407 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2408 if (ap->rxconfig & ANEG_CFG_RF2)
2409 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2410 if (ap->rxconfig & ANEG_CFG_NP)
2411 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2412
2413 ap->link_time = ap->cur_time;
2414
2415 ap->flags ^= (MR_TOGGLE_TX);
2416 if (ap->rxconfig & 0x0008)
2417 ap->flags |= MR_TOGGLE_RX;
2418 if (ap->rxconfig & ANEG_CFG_NP)
2419 ap->flags |= MR_NP_RX;
2420 ap->flags |= MR_PAGE_RX;
2421
2422 ap->state = ANEG_STATE_COMPLETE_ACK;
2423 ret = ANEG_TIMER_ENAB;
2424 break;
2425
2426 case ANEG_STATE_COMPLETE_ACK:
2427 if (ap->ability_match != 0 &&
2428 ap->rxconfig == 0) {
2429 ap->state = ANEG_STATE_AN_ENABLE;
2430 break;
2431 }
2432 delta = ap->cur_time - ap->link_time;
2433 if (delta > ANEG_STATE_SETTLE_TIME) {
2434 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2435 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2436 } else {
2437 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2438 !(ap->flags & MR_NP_RX)) {
2439 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2440 } else {
2441 ret = ANEG_FAILED;
2442 }
2443 }
2444 }
2445 break;
2446
2447 case ANEG_STATE_IDLE_DETECT_INIT:
2448 ap->link_time = ap->cur_time;
2449 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2450 tw32_f(MAC_MODE, tp->mac_mode);
2451 udelay(40);
2452
2453 ap->state = ANEG_STATE_IDLE_DETECT;
2454 ret = ANEG_TIMER_ENAB;
2455 break;
2456
2457 case ANEG_STATE_IDLE_DETECT:
2458 if (ap->ability_match != 0 &&
2459 ap->rxconfig == 0) {
2460 ap->state = ANEG_STATE_AN_ENABLE;
2461 break;
2462 }
2463 delta = ap->cur_time - ap->link_time;
2464 if (delta > ANEG_STATE_SETTLE_TIME) {
2465 /* XXX another gem from the Broadcom driver :( */
2466 ap->state = ANEG_STATE_LINK_OK;
2467 }
2468 break;
2469
2470 case ANEG_STATE_LINK_OK:
2471 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2472 ret = ANEG_DONE;
2473 break;
2474
2475 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2476 /* ??? unimplemented */
2477 break;
2478
2479 case ANEG_STATE_NEXT_PAGE_WAIT:
2480 /* ??? unimplemented */
2481 break;
2482
2483 default:
2484 ret = ANEG_FAILED;
2485 break;
2486 };
2487
2488 return ret;
2489}
2490
2491static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2492{
2493 int res = 0;
2494 struct tg3_fiber_aneginfo aninfo;
2495 int status = ANEG_FAILED;
2496 unsigned int tick;
2497 u32 tmp;
2498
2499 tw32_f(MAC_TX_AUTO_NEG, 0);
2500
2501 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2502 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2503 udelay(40);
2504
2505 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2506 udelay(40);
2507
2508 memset(&aninfo, 0, sizeof(aninfo));
2509 aninfo.flags |= MR_AN_ENABLE;
2510 aninfo.state = ANEG_STATE_UNKNOWN;
2511 aninfo.cur_time = 0;
2512 tick = 0;
2513 while (++tick < 195000) {
2514 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2515 if (status == ANEG_DONE || status == ANEG_FAILED)
2516 break;
2517
2518 udelay(1);
2519 }
2520
2521 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2522 tw32_f(MAC_MODE, tp->mac_mode);
2523 udelay(40);
2524
2525 *flags = aninfo.flags;
2526
2527 if (status == ANEG_DONE &&
2528 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2529 MR_LP_ADV_FULL_DUPLEX)))
2530 res = 1;
2531
2532 return res;
2533}
2534
2535static void tg3_init_bcm8002(struct tg3 *tp)
2536{
2537 u32 mac_status = tr32(MAC_STATUS);
2538 int i;
2539
2540 /* Reset when initting first time or we have a link. */
2541 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2542 !(mac_status & MAC_STATUS_PCS_SYNCED))
2543 return;
2544
2545 /* Set PLL lock range. */
2546 tg3_writephy(tp, 0x16, 0x8007);
2547
2548 /* SW reset */
2549 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2550
2551 /* Wait for reset to complete. */
2552 /* XXX schedule_timeout() ... */
2553 for (i = 0; i < 500; i++)
2554 udelay(10);
2555
2556 /* Config mode; select PMA/Ch 1 regs. */
2557 tg3_writephy(tp, 0x10, 0x8411);
2558
2559 /* Enable auto-lock and comdet, select txclk for tx. */
2560 tg3_writephy(tp, 0x11, 0x0a10);
2561
2562 tg3_writephy(tp, 0x18, 0x00a0);
2563 tg3_writephy(tp, 0x16, 0x41ff);
2564
2565 /* Assert and deassert POR. */
2566 tg3_writephy(tp, 0x13, 0x0400);
2567 udelay(40);
2568 tg3_writephy(tp, 0x13, 0x0000);
2569
2570 tg3_writephy(tp, 0x11, 0x0a50);
2571 udelay(40);
2572 tg3_writephy(tp, 0x11, 0x0a10);
2573
2574 /* Wait for signal to stabilize */
2575 /* XXX schedule_timeout() ... */
2576 for (i = 0; i < 15000; i++)
2577 udelay(10);
2578
2579 /* Deselect the channel register so we can read the PHYID
2580 * later.
2581 */
2582 tg3_writephy(tp, 0x10, 0x8011);
2583}
2584
2585static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2586{
2587 u32 sg_dig_ctrl, sg_dig_status;
2588 u32 serdes_cfg, expected_sg_dig_ctrl;
2589 int workaround, port_a;
2590 int current_link_up;
2591
2592 serdes_cfg = 0;
2593 expected_sg_dig_ctrl = 0;
2594 workaround = 0;
2595 port_a = 1;
2596 current_link_up = 0;
2597
2598 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2599 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2600 workaround = 1;
2601 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2602 port_a = 0;
2603
2604 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2605 /* preserve bits 20-23 for voltage regulator */
2606 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2607 }
2608
2609 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2610
2611 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2612 if (sg_dig_ctrl & (1 << 31)) {
2613 if (workaround) {
2614 u32 val = serdes_cfg;
2615
2616 if (port_a)
2617 val |= 0xc010000;
2618 else
2619 val |= 0x4010000;
2620 tw32_f(MAC_SERDES_CFG, val);
2621 }
2622 tw32_f(SG_DIG_CTRL, 0x01388400);
2623 }
2624 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2625 tg3_setup_flow_control(tp, 0, 0);
2626 current_link_up = 1;
2627 }
2628 goto out;
2629 }
2630
2631 /* Want auto-negotiation. */
2632 expected_sg_dig_ctrl = 0x81388400;
2633
2634 /* Pause capability */
2635 expected_sg_dig_ctrl |= (1 << 11);
2636
2637 /* Asymettric pause */
2638 expected_sg_dig_ctrl |= (1 << 12);
2639
2640 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2641 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2642 tp->serdes_counter &&
2643 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2644 MAC_STATUS_RCVD_CFG)) ==
2645 MAC_STATUS_PCS_SYNCED)) {
2646 tp->serdes_counter--;
2647 current_link_up = 1;
2648 goto out;
2649 }
2650restart_autoneg:
1da177e4
LT		 2651 if (workaround)
2652 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2653 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2654 udelay(5);
2655 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2656
3d3ebe74
MC		 2657 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2658 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2659 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2660 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2661 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2662 mac_status = tr32(MAC_STATUS);
2663
2664 if ((sg_dig_status & (1 << 1)) &&
2665 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2666 u32 local_adv, remote_adv;
2667
2668 local_adv = ADVERTISE_PAUSE_CAP;
2669 remote_adv = 0;
2670 if (sg_dig_status & (1 << 19))
2671 remote_adv |= LPA_PAUSE_CAP;
2672 if (sg_dig_status & (1 << 20))
2673 remote_adv |= LPA_PAUSE_ASYM;
2674
2675 tg3_setup_flow_control(tp, local_adv, remote_adv);
2676 current_link_up = 1;
3d3ebe74
MC		 2677 tp->serdes_counter = 0;
2678 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2679 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2680 if (tp->serdes_counter)
2681 tp->serdes_counter--;
1da177e4
LT		 2682 else {
2683 if (workaround) {
2684 u32 val = serdes_cfg;
2685
2686 if (port_a)
2687 val |= 0xc010000;
2688 else
2689 val |= 0x4010000;
2690
2691 tw32_f(MAC_SERDES_CFG, val);
2692 }
2693
2694 tw32_f(SG_DIG_CTRL, 0x01388400);
2695 udelay(40);
2696
2697 /* Link parallel detection - link is up */
2698 /* only if we have PCS_SYNC and not */
2699 /* receiving config code words */
2700 mac_status = tr32(MAC_STATUS);
2701 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2702 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2703 tg3_setup_flow_control(tp, 0, 0);
2704 current_link_up = 1;
3d3ebe74
MC		 2705 tp->tg3_flags2 |=
2706 TG3_FLG2_PARALLEL_DETECT;
2707 tp->serdes_counter =
2708 SERDES_PARALLEL_DET_TIMEOUT;
2709 } else
2710 goto restart_autoneg;
1da177e4
LT		 2711 }
2712 }
3d3ebe74
MC		 2713 } else {
2714 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2715 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2716 }
2717
2718out:
2719 return current_link_up;
2720}
2721
2722static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2723{
2724 int current_link_up = 0;
2725
5cf64b8a 2726 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 2727 goto out;
1da177e4
LT		 2728
2729 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2730 u32 flags;
2731 int i;
6aa20a22 2732
1da177e4
LT		 2733 if (fiber_autoneg(tp, &flags)) {
2734 u32 local_adv, remote_adv;
2735
2736 local_adv = ADVERTISE_PAUSE_CAP;
2737 remote_adv = 0;
2738 if (flags & MR_LP_ADV_SYM_PAUSE)
2739 remote_adv |= LPA_PAUSE_CAP;
2740 if (flags & MR_LP_ADV_ASYM_PAUSE)
2741 remote_adv |= LPA_PAUSE_ASYM;
2742
2743 tg3_setup_flow_control(tp, local_adv, remote_adv);
2744
1da177e4
LT		 2745 current_link_up = 1;
2746 }
2747 for (i = 0; i < 30; i++) {
2748 udelay(20);
2749 tw32_f(MAC_STATUS,
2750 (MAC_STATUS_SYNC_CHANGED |
2751 MAC_STATUS_CFG_CHANGED));
2752 udelay(40);
2753 if ((tr32(MAC_STATUS) &
2754 (MAC_STATUS_SYNC_CHANGED |
2755 MAC_STATUS_CFG_CHANGED)) == 0)
2756 break;
2757 }
2758
2759 mac_status = tr32(MAC_STATUS);
2760 if (current_link_up == 0 &&
2761 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2762 !(mac_status & MAC_STATUS_RCVD_CFG))
2763 current_link_up = 1;
2764 } else {
2765 /* Forcing 1000FD link up. */
2766 current_link_up = 1;
1da177e4
LT		 2767
2768 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2769 udelay(40);
e8f3f6ca
MC		 2770
2771 tw32_f(MAC_MODE, tp->mac_mode);
2772 udelay(40);
1da177e4
LT		 2773 }
2774
2775out:
2776 return current_link_up;
2777}
2778
2779static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2780{
2781 u32 orig_pause_cfg;
2782 u16 orig_active_speed;
2783 u8 orig_active_duplex;
2784 u32 mac_status;
2785 int current_link_up;
2786 int i;
2787
2788 orig_pause_cfg =
2789 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2790 TG3_FLAG_TX_PAUSE));
2791 orig_active_speed = tp->link_config.active_speed;
2792 orig_active_duplex = tp->link_config.active_duplex;
2793
2794 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2795 netif_carrier_ok(tp->dev) &&
2796 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2797 mac_status = tr32(MAC_STATUS);
2798 mac_status &= (MAC_STATUS_PCS_SYNCED |
2799 MAC_STATUS_SIGNAL_DET |
2800 MAC_STATUS_CFG_CHANGED |
2801 MAC_STATUS_RCVD_CFG);
2802 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2803 MAC_STATUS_SIGNAL_DET)) {
2804 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2805 MAC_STATUS_CFG_CHANGED));
2806 return 0;
2807 }
2808 }
2809
2810 tw32_f(MAC_TX_AUTO_NEG, 0);
2811
2812 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2813 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2814 tw32_f(MAC_MODE, tp->mac_mode);
2815 udelay(40);
2816
2817 if (tp->phy_id == PHY_ID_BCM8002)
2818 tg3_init_bcm8002(tp);
2819
2820 /* Enable link change event even when serdes polling. */
2821 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2822 udelay(40);
2823
2824 current_link_up = 0;
2825 mac_status = tr32(MAC_STATUS);
2826
2827 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2828 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2829 else
2830 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2831
1da177e4
LT		 2832 tp->hw_status->status =
2833 (SD_STATUS_UPDATED |
2834 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2835
2836 for (i = 0; i < 100; i++) {
2837 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2838 MAC_STATUS_CFG_CHANGED));
2839 udelay(5);
2840 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2841 MAC_STATUS_CFG_CHANGED |
2842 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2843 break;
2844 }
2845
2846 mac_status = tr32(MAC_STATUS);
2847 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2848 current_link_up = 0;
3d3ebe74
MC		 2849 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2850 tp->serdes_counter == 0) {
1da177e4
LT		 2851 tw32_f(MAC_MODE, (tp->mac_mode |
2852 MAC_MODE_SEND_CONFIGS));
2853 udelay(1);
2854 tw32_f(MAC_MODE, tp->mac_mode);
2855 }
2856 }
2857
2858 if (current_link_up == 1) {
2859 tp->link_config.active_speed = SPEED_1000;
2860 tp->link_config.active_duplex = DUPLEX_FULL;
2861 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2862 LED_CTRL_LNKLED_OVERRIDE |
2863 LED_CTRL_1000MBPS_ON));
2864 } else {
2865 tp->link_config.active_speed = SPEED_INVALID;
2866 tp->link_config.active_duplex = DUPLEX_INVALID;
2867 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2868 LED_CTRL_LNKLED_OVERRIDE |
2869 LED_CTRL_TRAFFIC_OVERRIDE));
2870 }
2871
2872 if (current_link_up != netif_carrier_ok(tp->dev)) {
2873 if (current_link_up)
2874 netif_carrier_on(tp->dev);
2875 else
2876 netif_carrier_off(tp->dev);
2877 tg3_link_report(tp);
2878 } else {
2879 u32 now_pause_cfg =
2880 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2881 TG3_FLAG_TX_PAUSE);
2882 if (orig_pause_cfg != now_pause_cfg ||
2883 orig_active_speed != tp->link_config.active_speed ||
2884 orig_active_duplex != tp->link_config.active_duplex)
2885 tg3_link_report(tp);
2886 }
2887
2888 return 0;
2889}
2890
747e8f8b
MC		 2891static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2892{
2893 int current_link_up, err = 0;
2894 u32 bmsr, bmcr;
2895 u16 current_speed;
2896 u8 current_duplex;
2897
2898 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2899 tw32_f(MAC_MODE, tp->mac_mode);
2900 udelay(40);
2901
2902 tw32(MAC_EVENT, 0);
2903
2904 tw32_f(MAC_STATUS,
2905 (MAC_STATUS_SYNC_CHANGED |
2906 MAC_STATUS_CFG_CHANGED |
2907 MAC_STATUS_MI_COMPLETION |
2908 MAC_STATUS_LNKSTATE_CHANGED));
2909 udelay(40);
2910
2911 if (force_reset)
2912 tg3_phy_reset(tp);
2913
2914 current_link_up = 0;
2915 current_speed = SPEED_INVALID;
2916 current_duplex = DUPLEX_INVALID;
2917
2918 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2919 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2921 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2922 bmsr |= BMSR_LSTATUS;
2923 else
2924 bmsr &= ~BMSR_LSTATUS;
2925 }
747e8f8b
MC		 2926
2927 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2928
2929 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2930 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2931 /* do nothing, just check for link up at the end */
2932 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2933 u32 adv, new_adv;
2934
2935 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2936 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2937 ADVERTISE_1000XPAUSE |
2938 ADVERTISE_1000XPSE_ASYM |
2939 ADVERTISE_SLCT);
2940
2941 /* Always advertise symmetric PAUSE just like copper */
2942 new_adv |= ADVERTISE_1000XPAUSE;
2943
2944 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2945 new_adv |= ADVERTISE_1000XHALF;
2946 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2947 new_adv |= ADVERTISE_1000XFULL;
2948
2949 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2950 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2951 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2952 tg3_writephy(tp, MII_BMCR, bmcr);
2953
2954 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2955 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2956 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2957
2958 return err;
2959 }
2960 } else {
2961 u32 new_bmcr;
2962
2963 bmcr &= ~BMCR_SPEED1000;
2964 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2965
2966 if (tp->link_config.duplex == DUPLEX_FULL)
2967 new_bmcr |= BMCR_FULLDPLX;
2968
2969 if (new_bmcr != bmcr) {
2970 /* BMCR_SPEED1000 is a reserved bit that needs
2971 * to be set on write.
2972 */
2973 new_bmcr |= BMCR_SPEED1000;
2974
2975 /* Force a linkdown */
2976 if (netif_carrier_ok(tp->dev)) {
2977 u32 adv;
2978
2979 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2980 adv &= ~(ADVERTISE_1000XFULL |
2981 ADVERTISE_1000XHALF |
2982 ADVERTISE_SLCT);
2983 tg3_writephy(tp, MII_ADVERTISE, adv);
2984 tg3_writephy(tp, MII_BMCR, bmcr |
2985 BMCR_ANRESTART |
2986 BMCR_ANENABLE);
2987 udelay(10);
2988 netif_carrier_off(tp->dev);
2989 }
2990 tg3_writephy(tp, MII_BMCR, new_bmcr);
2991 bmcr = new_bmcr;
2992 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2993 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2994 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2995 ASIC_REV_5714) {
2996 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2997 bmsr |= BMSR_LSTATUS;
2998 else
2999 bmsr &= ~BMSR_LSTATUS;
3000 }
747e8f8b
MC		 3001 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3002 }
3003 }
3004
3005 if (bmsr & BMSR_LSTATUS) {
3006 current_speed = SPEED_1000;
3007 current_link_up = 1;
3008 if (bmcr & BMCR_FULLDPLX)
3009 current_duplex = DUPLEX_FULL;
3010 else
3011 current_duplex = DUPLEX_HALF;
3012
3013 if (bmcr & BMCR_ANENABLE) {
3014 u32 local_adv, remote_adv, common;
3015
3016 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3017 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3018 common = local_adv & remote_adv;
3019 if (common & (ADVERTISE_1000XHALF |
3020 ADVERTISE_1000XFULL)) {
3021 if (common & ADVERTISE_1000XFULL)
3022 current_duplex = DUPLEX_FULL;
3023 else
3024 current_duplex = DUPLEX_HALF;
3025
3026 tg3_setup_flow_control(tp, local_adv,
3027 remote_adv);
3028 }
3029 else
3030 current_link_up = 0;
3031 }
3032 }
3033
3034 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3035 if (tp->link_config.active_duplex == DUPLEX_HALF)
3036 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3037
3038 tw32_f(MAC_MODE, tp->mac_mode);
3039 udelay(40);
3040
3041 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3042
3043 tp->link_config.active_speed = current_speed;
3044 tp->link_config.active_duplex = current_duplex;
3045
3046 if (current_link_up != netif_carrier_ok(tp->dev)) {
3047 if (current_link_up)
3048 netif_carrier_on(tp->dev);
3049 else {
3050 netif_carrier_off(tp->dev);
3051 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3052 }
3053 tg3_link_report(tp);
3054 }
3055 return err;
3056}
3057
3058static void tg3_serdes_parallel_detect(struct tg3 *tp)
3059{
3d3ebe74 3060 if (tp->serdes_counter) {
747e8f8b 3061 /* Give autoneg time to complete. */
3d3ebe74 3062 tp->serdes_counter--;
747e8f8b
MC		 3063 return;
3064 }
3065 if (!netif_carrier_ok(tp->dev) &&
3066 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3067 u32 bmcr;
3068
3069 tg3_readphy(tp, MII_BMCR, &bmcr);
3070 if (bmcr & BMCR_ANENABLE) {
3071 u32 phy1, phy2;
3072
3073 /* Select shadow register 0x1f */
3074 tg3_writephy(tp, 0x1c, 0x7c00);
3075 tg3_readphy(tp, 0x1c, &phy1);
3076
3077 /* Select expansion interrupt status register */
3078 tg3_writephy(tp, 0x17, 0x0f01);
3079 tg3_readphy(tp, 0x15, &phy2);
3080 tg3_readphy(tp, 0x15, &phy2);
3081
3082 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3083 /* We have signal detect and not receiving
3084 * config code words, link is up by parallel
3085 * detection.
3086 */
3087
3088 bmcr &= ~BMCR_ANENABLE;
3089 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3090 tg3_writephy(tp, MII_BMCR, bmcr);
3091 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3092 }
3093 }
3094 }
3095 else if (netif_carrier_ok(tp->dev) &&
3096 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3097 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3098 u32 phy2;
3099
3100 /* Select expansion interrupt status register */
3101 tg3_writephy(tp, 0x17, 0x0f01);
3102 tg3_readphy(tp, 0x15, &phy2);
3103 if (phy2 & 0x20) {
3104 u32 bmcr;
3105
3106 /* Config code words received, turn on autoneg. */
3107 tg3_readphy(tp, MII_BMCR, &bmcr);
3108 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3109
3110 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3111
3112 }
3113 }
3114}
3115
1da177e4
LT		 3116static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3117{
3118 int err;
3119
3120 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3121 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 3122 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3123 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 3124 } else {
3125 err = tg3_setup_copper_phy(tp, force_reset);
3126 }
3127
3128 if (tp->link_config.active_speed == SPEED_1000 &&
3129 tp->link_config.active_duplex == DUPLEX_HALF)
3130 tw32(MAC_TX_LENGTHS,
3131 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3132 (6 << TX_LENGTHS_IPG_SHIFT) |
3133 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3134 else
3135 tw32(MAC_TX_LENGTHS,
3136 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3137 (6 << TX_LENGTHS_IPG_SHIFT) |
3138 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3139
3140 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3141 if (netif_carrier_ok(tp->dev)) {
3142 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3143 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3144 } else {
3145 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3146 }
3147 }
3148
8ed5d97e
MC		 3149 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3150 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3151 if (!netif_carrier_ok(tp->dev))
3152 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3153 tp->pwrmgmt_thresh;
3154 else
3155 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3156 tw32(PCIE_PWR_MGMT_THRESH, val);
3157 }
3158
1da177e4
LT		 3159 return err;
3160}
3161
df3e6548
MC		 3162/* This is called whenever we suspect that the system chipset is re-
3163 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3164 * is bogus tx completions. We try to recover by setting the
3165 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3166 * in the workqueue.
3167 */
3168static void tg3_tx_recover(struct tg3 *tp)
3169{
3170 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3171 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3172
3173 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3174 "mapped I/O cycles to the network device, attempting to "
3175 "recover. Please report the problem to the driver maintainer "
3176 "and include system chipset information.\n", tp->dev->name);
3177
3178 spin_lock(&tp->lock);
df3e6548 3179 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3180 spin_unlock(&tp->lock);
3181}
3182
1b2a7205
MC		 3183static inline u32 tg3_tx_avail(struct tg3 *tp)
3184{
3185 smp_mb();
3186 return (tp->tx_pending -
3187 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3188}
3189
1da177e4
LT		 3190/* Tigon3 never reports partial packet sends. So we do not
3191 * need special logic to handle SKBs that have not had all
3192 * of their frags sent yet, like SunGEM does.
3193 */
3194static void tg3_tx(struct tg3 *tp)
3195{
3196 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3197 u32 sw_idx = tp->tx_cons;
3198
3199 while (sw_idx != hw_idx) {
3200 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3201 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3202 int i, tx_bug = 0;
3203
3204 if (unlikely(skb == NULL)) {
3205 tg3_tx_recover(tp);
3206 return;
3207 }
1da177e4 3208
1da177e4
LT		 3209 pci_unmap_single(tp->pdev,
3210 pci_unmap_addr(ri, mapping),
3211 skb_headlen(skb),
3212 PCI_DMA_TODEVICE);
3213
3214 ri->skb = NULL;
3215
3216 sw_idx = NEXT_TX(sw_idx);
3217
3218 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3219 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3220 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3221 tx_bug = 1;
1da177e4
LT		 3222
3223 pci_unmap_page(tp->pdev,
3224 pci_unmap_addr(ri, mapping),
3225 skb_shinfo(skb)->frags[i].size,
3226 PCI_DMA_TODEVICE);
3227
3228 sw_idx = NEXT_TX(sw_idx);
3229 }
3230
f47c11ee 3231 dev_kfree_skb(skb);
df3e6548
MC		 3232
3233 if (unlikely(tx_bug)) {
3234 tg3_tx_recover(tp);
3235 return;
3236 }
1da177e4
LT		 3237 }
3238
3239 tp->tx_cons = sw_idx;
3240
1b2a7205
MC		 3241 /* Need to make the tx_cons update visible to tg3_start_xmit()
3242 * before checking for netif_queue_stopped(). Without the
3243 * memory barrier, there is a small possibility that tg3_start_xmit()
3244 * will miss it and cause the queue to be stopped forever.
3245 */
3246 smp_mb();
3247
3248 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3249 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3250 netif_tx_lock(tp->dev);
51b91468 3251 if (netif_queue_stopped(tp->dev) &&
42952231 3252 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3253 netif_wake_queue(tp->dev);
1b2a7205 3254 netif_tx_unlock(tp->dev);
51b91468 3255 }
1da177e4
LT		 3256}
3257
3258/* Returns size of skb allocated or < 0 on error.
3259 *
3260 * We only need to fill in the address because the other members
3261 * of the RX descriptor are invariant, see tg3_init_rings.
3262 *
3263 * Note the purposeful assymetry of cpu vs. chip accesses. For
3264 * posting buffers we only dirty the first cache line of the RX
3265 * descriptor (containing the address). Whereas for the RX status
3266 * buffers the cpu only reads the last cacheline of the RX descriptor
3267 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3268 */
3269static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3270 int src_idx, u32 dest_idx_unmasked)
3271{
3272 struct tg3_rx_buffer_desc *desc;
3273 struct ring_info *map, *src_map;
3274 struct sk_buff *skb;
3275 dma_addr_t mapping;
3276 int skb_size, dest_idx;
3277
3278 src_map = NULL;
3279 switch (opaque_key) {
3280 case RXD_OPAQUE_RING_STD:
3281 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3282 desc = &tp->rx_std[dest_idx];
3283 map = &tp->rx_std_buffers[dest_idx];
3284 if (src_idx >= 0)
3285 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3286 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3287 break;
3288
3289 case RXD_OPAQUE_RING_JUMBO:
3290 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3291 desc = &tp->rx_jumbo[dest_idx];
3292 map = &tp->rx_jumbo_buffers[dest_idx];
3293 if (src_idx >= 0)
3294 src_map = &tp->rx_jumbo_buffers[src_idx];
3295 skb_size = RX_JUMBO_PKT_BUF_SZ;
3296 break;
3297
3298 default:
3299 return -EINVAL;
3300 };
3301
3302 /* Do not overwrite any of the map or rp information
3303 * until we are sure we can commit to a new buffer.
3304 *
3305 * Callers depend upon this behavior and assume that
3306 * we leave everything unchanged if we fail.
3307 */
a20e9c62 3308 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3309 if (skb == NULL)
3310 return -ENOMEM;
3311
1da177e4
LT		 3312 skb_reserve(skb, tp->rx_offset);
3313
3314 mapping = pci_map_single(tp->pdev, skb->data,
3315 skb_size - tp->rx_offset,
3316 PCI_DMA_FROMDEVICE);
3317
3318 map->skb = skb;
3319 pci_unmap_addr_set(map, mapping, mapping);
3320
3321 if (src_map != NULL)
3322 src_map->skb = NULL;
3323
3324 desc->addr_hi = ((u64)mapping >> 32);
3325 desc->addr_lo = ((u64)mapping & 0xffffffff);
3326
3327 return skb_size;
3328}
3329
3330/* We only need to move over in the address because the other
3331 * members of the RX descriptor are invariant. See notes above
3332 * tg3_alloc_rx_skb for full details.
3333 */
3334static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3335 int src_idx, u32 dest_idx_unmasked)
3336{
3337 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3338 struct ring_info *src_map, *dest_map;
3339 int dest_idx;
3340
3341 switch (opaque_key) {
3342 case RXD_OPAQUE_RING_STD:
3343 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3344 dest_desc = &tp->rx_std[dest_idx];
3345 dest_map = &tp->rx_std_buffers[dest_idx];
3346 src_desc = &tp->rx_std[src_idx];
3347 src_map = &tp->rx_std_buffers[src_idx];
3348 break;
3349
3350 case RXD_OPAQUE_RING_JUMBO:
3351 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3352 dest_desc = &tp->rx_jumbo[dest_idx];
3353 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3354 src_desc = &tp->rx_jumbo[src_idx];
3355 src_map = &tp->rx_jumbo_buffers[src_idx];
3356 break;
3357
3358 default:
3359 return;
3360 };
3361
3362 dest_map->skb = src_map->skb;
3363 pci_unmap_addr_set(dest_map, mapping,
3364 pci_unmap_addr(src_map, mapping));
3365 dest_desc->addr_hi = src_desc->addr_hi;
3366 dest_desc->addr_lo = src_desc->addr_lo;
3367
3368 src_map->skb = NULL;
3369}
3370
3371#if TG3_VLAN_TAG_USED
3372static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3373{
3374 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3375}
3376#endif
3377
3378/* The RX ring scheme is composed of multiple rings which post fresh
3379 * buffers to the chip, and one special ring the chip uses to report
3380 * status back to the host.
3381 *
3382 * The special ring reports the status of received packets to the
3383 * host. The chip does not write into the original descriptor the
3384 * RX buffer was obtained from. The chip simply takes the original
3385 * descriptor as provided by the host, updates the status and length
3386 * field, then writes this into the next status ring entry.
3387 *
3388 * Each ring the host uses to post buffers to the chip is described
3389 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3390 * it is first placed into the on-chip ram. When the packet's length
3391 * is known, it walks down the TG3_BDINFO entries to select the ring.
3392 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3393 * which is within the range of the new packet's length is chosen.
3394 *
3395 * The "separate ring for rx status" scheme may sound queer, but it makes
3396 * sense from a cache coherency perspective. If only the host writes
3397 * to the buffer post rings, and only the chip writes to the rx status
3398 * rings, then cache lines never move beyond shared-modified state.
3399 * If both the host and chip were to write into the same ring, cache line
3400 * eviction could occur since both entities want it in an exclusive state.
3401 */
3402static int tg3_rx(struct tg3 *tp, int budget)
3403{
f92905de 3404 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3405 u32 sw_idx = tp->rx_rcb_ptr;
3406 u16 hw_idx;
1da177e4
LT		 3407 int received;
3408
3409 hw_idx = tp->hw_status->idx[0].rx_producer;
3410 /*
3411 * We need to order the read of hw_idx and the read of
3412 * the opaque cookie.
3413 */
3414 rmb();
1da177e4
LT		 3415 work_mask = 0;
3416 received = 0;
3417 while (sw_idx != hw_idx && budget > 0) {
3418 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3419 unsigned int len;
3420 struct sk_buff *skb;
3421 dma_addr_t dma_addr;
3422 u32 opaque_key, desc_idx, *post_ptr;
3423
3424 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3425 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3426 if (opaque_key == RXD_OPAQUE_RING_STD) {
3427 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3428 mapping);
3429 skb = tp->rx_std_buffers[desc_idx].skb;
3430 post_ptr = &tp->rx_std_ptr;
f92905de 3431 rx_std_posted++;
1da177e4
LT		 3432 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3433 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3434 mapping);
3435 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3436 post_ptr = &tp->rx_jumbo_ptr;
3437 }
3438 else {
3439 goto next_pkt_nopost;
3440 }
3441
3442 work_mask |= opaque_key;
3443
3444 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3445 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3446 drop_it:
3447 tg3_recycle_rx(tp, opaque_key,
3448 desc_idx, *post_ptr);
3449 drop_it_no_recycle:
3450 /* Other statistics kept track of by card. */
3451 tp->net_stats.rx_dropped++;
3452 goto next_pkt;
3453 }
3454
3455 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3456
6aa20a22 3457 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3458 && tp->rx_offset == 2
3459 /* rx_offset != 2 iff this is a 5701 card running
3460 * in PCI-X mode [see tg3_get_invariants()] */
3461 ) {
3462 int skb_size;
3463
3464 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3465 desc_idx, *post_ptr);
3466 if (skb_size < 0)
3467 goto drop_it;
3468
3469 pci_unmap_single(tp->pdev, dma_addr,
3470 skb_size - tp->rx_offset,
3471 PCI_DMA_FROMDEVICE);
3472
3473 skb_put(skb, len);
3474 } else {
3475 struct sk_buff *copy_skb;
3476
3477 tg3_recycle_rx(tp, opaque_key,
3478 desc_idx, *post_ptr);
3479
a20e9c62 3480 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3481 if (copy_skb == NULL)
3482 goto drop_it_no_recycle;
3483
1da177e4
LT		 3484 skb_reserve(copy_skb, 2);
3485 skb_put(copy_skb, len);
3486 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 3487 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 3488 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3489
3490 /* We'll reuse the original ring buffer. */
3491 skb = copy_skb;
3492 }
3493
3494 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3495 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3496 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3497 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3498 skb->ip_summed = CHECKSUM_UNNECESSARY;
3499 else
3500 skb->ip_summed = CHECKSUM_NONE;
3501
3502 skb->protocol = eth_type_trans(skb, tp->dev);
3503#if TG3_VLAN_TAG_USED
3504 if (tp->vlgrp != NULL &&
3505 desc->type_flags & RXD_FLAG_VLAN) {
3506 tg3_vlan_rx(tp, skb,
3507 desc->err_vlan & RXD_VLAN_MASK);
3508 } else
3509#endif
3510 netif_receive_skb(skb);
3511
3512 tp->dev->last_rx = jiffies;
3513 received++;
3514 budget--;
3515
3516next_pkt:
3517 (*post_ptr)++;
f92905de
MC		 3518
3519 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3520 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3521
3522 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3523 TG3_64BIT_REG_LOW, idx);
3524 work_mask &= ~RXD_OPAQUE_RING_STD;
3525 rx_std_posted = 0;
3526 }
1da177e4 3527next_pkt_nopost:
483ba50b 3528 sw_idx++;
6b31a515 3529 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3530
3531 /* Refresh hw_idx to see if there is new work */
3532 if (sw_idx == hw_idx) {
3533 hw_idx = tp->hw_status->idx[0].rx_producer;
3534 rmb();
3535 }
1da177e4
LT		 3536 }
3537
3538 /* ACK the status ring. */
483ba50b
MC		 3539 tp->rx_rcb_ptr = sw_idx;
3540 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3541
3542 /* Refill RX ring(s). */
3543 if (work_mask & RXD_OPAQUE_RING_STD) {
3544 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3545 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3546 sw_idx);
3547 }
3548 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3549 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3550 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3551 sw_idx);
3552 }
3553 mmiowb();
3554
3555 return received;
3556}
3557
6f535763 3558static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 3559{
1da177e4 3560 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 3561
1da177e4
LT		 3562 /* handle link change and other phy events */
3563 if (!(tp->tg3_flags &
3564 (TG3_FLAG_USE_LINKCHG_REG |
3565 TG3_FLAG_POLL_SERDES))) {
3566 if (sblk->status & SD_STATUS_LINK_CHG) {
3567 sblk->status = SD_STATUS_UPDATED |
3568 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3569 spin_lock(&tp->lock);
1da177e4 3570 tg3_setup_phy(tp, 0);
f47c11ee 3571 spin_unlock(&tp->lock);
1da177e4
LT		 3572 }
3573 }
3574
3575 /* run TX completion thread */
3576 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3577 tg3_tx(tp);
6f535763 3578 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
df3e6548 3579 return 0;
1da177e4
LT		 3580 }
3581
1da177e4
LT		 3582 /* run RX thread, within the bounds set by NAPI.
3583 * All RX "locking" is done by ensuring outside
bea3348e 3584 * code synchronizes with tg3->napi.poll()
1da177e4 3585 */
bea3348e 3586 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 3587 work_done += tg3_rx(tp, budget - work_done);
1da177e4 3588
6f535763
DM		 3589 return work_done;
3590}
3591
3592static int tg3_poll(struct napi_struct *napi, int budget)
3593{
3594 struct tg3 *tp = container_of(napi, struct tg3, napi);
3595 int work_done = 0;
3596
3597 while (1) {
3598 work_done = tg3_poll_work(tp, work_done, budget);
3599
3600 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3601 goto tx_recovery;
3602
3603 if (unlikely(work_done >= budget))
3604 break;
3605
3606 if (likely(!tg3_has_work(tp))) {
3607 struct tg3_hw_status *sblk = tp->hw_status;
f7383c22 3608
6f535763
DM		 3609 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3610 tp->last_tag = sblk->status_tag;
3611 rmb();
3612 } else
3613 sblk->status &= ~SD_STATUS_UPDATED;
3614
3615 netif_rx_complete(tp->dev, napi);
3616 tg3_restart_ints(tp);
3617 break;
3618 }
1da177e4
LT		 3619 }
3620
bea3348e 3621 return work_done;
6f535763
DM		 3622
3623tx_recovery:
3624 netif_rx_complete(tp->dev, napi);
3625 schedule_work(&tp->reset_task);
3626 return 0;
1da177e4
LT		 3627}
3628
f47c11ee
DM		 3629static void tg3_irq_quiesce(struct tg3 *tp)
3630{
3631 BUG_ON(tp->irq_sync);
3632
3633 tp->irq_sync = 1;
3634 smp_mb();
3635
3636 synchronize_irq(tp->pdev->irq);
3637}
3638
3639static inline int tg3_irq_sync(struct tg3 *tp)
3640{
3641 return tp->irq_sync;
3642}
3643
3644/* Fully shutdown all tg3 driver activity elsewhere in the system.
3645 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3646 * with as well. Most of the time, this is not necessary except when
3647 * shutting down the device.
3648 */
3649static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3650{
46966545 3651 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3652 if (irq_sync)
3653 tg3_irq_quiesce(tp);
f47c11ee
DM		 3654}
3655
3656static inline void tg3_full_unlock(struct tg3 *tp)
3657{
f47c11ee
DM		 3658 spin_unlock_bh(&tp->lock);
3659}
3660
fcfa0a32
MC		 3661/* One-shot MSI handler - Chip automatically disables interrupt
3662 * after sending MSI so driver doesn't have to do it.
3663 */
7d12e780 3664static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3665{
3666 struct net_device *dev = dev_id;
3667 struct tg3 *tp = netdev_priv(dev);
3668
3669 prefetch(tp->hw_status);
3670 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3671
3672 if (likely(!tg3_irq_sync(tp)))
bea3348e 3673 netif_rx_schedule(dev, &tp->napi);
fcfa0a32
MC		 3674
3675 return IRQ_HANDLED;
3676}
3677
88b06bc2
MC		 3678/* MSI ISR - No need to check for interrupt sharing and no need to
3679 * flush status block and interrupt mailbox. PCI ordering rules
3680 * guarantee that MSI will arrive after the status block.
3681 */
7d12e780 3682static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3683{
3684 struct net_device *dev = dev_id;
3685 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3686
61487480
MC		 3687 prefetch(tp->hw_status);
3688 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3689 /*
fac9b83e 3690 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3691 * chip-internal interrupt pending events.
fac9b83e 3692 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3693 * NIC to stop sending us irqs, engaging "in-intr-handler"
3694 * event coalescing.
3695 */
3696 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3697 if (likely(!tg3_irq_sync(tp)))
bea3348e 3698 netif_rx_schedule(dev, &tp->napi);
61487480 3699
88b06bc2
MC		 3700 return IRQ_RETVAL(1);
3701}
3702
7d12e780 3703static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3704{
3705 struct net_device *dev = dev_id;
3706 struct tg3 *tp = netdev_priv(dev);
3707 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3708 unsigned int handled = 1;
3709
1da177e4
LT		 3710 /* In INTx mode, it is possible for the interrupt to arrive at
3711 * the CPU before the status block posted prior to the interrupt.
3712 * Reading the PCI State register will confirm whether the
3713 * interrupt is ours and will flush the status block.
3714 */
d18edcb2
MC		 3715 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3716 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3717 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3718 handled = 0;
f47c11ee 3719 goto out;
fac9b83e 3720 }
d18edcb2
MC		 3721 }
3722
3723 /*
3724 * Writing any value to intr-mbox-0 clears PCI INTA# and
3725 * chip-internal interrupt pending events.
3726 * Writing non-zero to intr-mbox-0 additional tells the
3727 * NIC to stop sending us irqs, engaging "in-intr-handler"
3728 * event coalescing.
c04cb347
MC		 3729 *
3730 * Flush the mailbox to de-assert the IRQ immediately to prevent
3731 * spurious interrupts. The flush impacts performance but
3732 * excessive spurious interrupts can be worse in some cases.
d18edcb2 3733 */
c04cb347 3734 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 3735 if (tg3_irq_sync(tp))
3736 goto out;
3737 sblk->status &= ~SD_STATUS_UPDATED;
3738 if (likely(tg3_has_work(tp))) {
3739 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
bea3348e 3740 netif_rx_schedule(dev, &tp->napi);
d18edcb2
MC		 3741 } else {
3742 /* No work, shared interrupt perhaps? re-enable
3743 * interrupts, and flush that PCI write
3744 */
3745 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3746 0x00000000);
fac9b83e 3747 }
f47c11ee 3748out:
fac9b83e
DM		 3749 return IRQ_RETVAL(handled);
3750}
3751
7d12e780 3752static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3753{
3754 struct net_device *dev = dev_id;
3755 struct tg3 *tp = netdev_priv(dev);
3756 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3757 unsigned int handled = 1;
3758
fac9b83e
DM		 3759 /* In INTx mode, it is possible for the interrupt to arrive at
3760 * the CPU before the status block posted prior to the interrupt.
3761 * Reading the PCI State register will confirm whether the
3762 * interrupt is ours and will flush the status block.
3763 */
d18edcb2
MC		 3764 if (unlikely(sblk->status_tag == tp->last_tag)) {
3765 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3766 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3767 handled = 0;
f47c11ee 3768 goto out;
1da177e4 3769 }
d18edcb2
MC		 3770 }
3771
3772 /*
3773 * writing any value to intr-mbox-0 clears PCI INTA# and
3774 * chip-internal interrupt pending events.
3775 * writing non-zero to intr-mbox-0 additional tells the
3776 * NIC to stop sending us irqs, engaging "in-intr-handler"
3777 * event coalescing.
c04cb347
MC		 3778 *
3779 * Flush the mailbox to de-assert the IRQ immediately to prevent
3780 * spurious interrupts. The flush impacts performance but
3781 * excessive spurious interrupts can be worse in some cases.
d18edcb2 3782 */
c04cb347 3783 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 3784 if (tg3_irq_sync(tp))
3785 goto out;
bea3348e 3786 if (netif_rx_schedule_prep(dev, &tp->napi)) {
d18edcb2
MC		 3787 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3788 /* Update last_tag to mark that this status has been
3789 * seen. Because interrupt may be shared, we may be
3790 * racing with tg3_poll(), so only update last_tag
3791 * if tg3_poll() is not scheduled.
3792 */
3793 tp->last_tag = sblk->status_tag;
bea3348e 3794 __netif_rx_schedule(dev, &tp->napi);
1da177e4 3795 }
f47c11ee 3796out:
1da177e4
LT		 3797 return IRQ_RETVAL(handled);
3798}
3799
7938109f 3800/* ISR for interrupt test */
7d12e780 3801static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3802{
3803 struct net_device *dev = dev_id;
3804 struct tg3 *tp = netdev_priv(dev);
3805 struct tg3_hw_status *sblk = tp->hw_status;
3806
f9804ddb
MC		 3807 if ((sblk->status & SD_STATUS_UPDATED) ||
3808 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3809 tg3_disable_ints(tp);
7938109f
MC		 3810 return IRQ_RETVAL(1);
3811 }
3812 return IRQ_RETVAL(0);
3813}
3814
8e7a22e3 3815static int tg3_init_hw(struct tg3 *, int);
944d980e 3816static int tg3_halt(struct tg3 *, int, int);
1da177e4 3817
b9ec6c1b
MC		 3818/* Restart hardware after configuration changes, self-test, etc.
3819 * Invoked with tp->lock held.
3820 */
3821static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3822{
3823 int err;
3824
3825 err = tg3_init_hw(tp, reset_phy);
3826 if (err) {
3827 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3828 "aborting.\n", tp->dev->name);
3829 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3830 tg3_full_unlock(tp);
3831 del_timer_sync(&tp->timer);
3832 tp->irq_sync = 0;
bea3348e 3833 napi_enable(&tp->napi);
b9ec6c1b
MC		 3834 dev_close(tp->dev);
3835 tg3_full_lock(tp, 0);
3836 }
3837 return err;
3838}
3839
1da177e4
LT		 3840#ifdef CONFIG_NET_POLL_CONTROLLER
3841static void tg3_poll_controller(struct net_device *dev)
3842{
88b06bc2
MC		 3843 struct tg3 *tp = netdev_priv(dev);
3844
7d12e780 3845 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3846}
3847#endif
3848
c4028958 3849static void tg3_reset_task(struct work_struct *work)
1da177e4 3850{
c4028958 3851 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3852 unsigned int restart_timer;
3853
7faa006f 3854 tg3_full_lock(tp, 0);
7faa006f
MC		 3855
3856 if (!netif_running(tp->dev)) {
7faa006f
MC		 3857 tg3_full_unlock(tp);
3858 return;
3859 }
3860
3861 tg3_full_unlock(tp);
3862
1da177e4
LT		 3863 tg3_netif_stop(tp);
3864
f47c11ee 3865 tg3_full_lock(tp, 1);
1da177e4
LT		 3866
3867 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3868 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3869
df3e6548
MC		 3870 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3871 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3872 tp->write32_rx_mbox = tg3_write_flush_reg32;
3873 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3874 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3875 }
3876
944d980e 3877 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3878 if (tg3_init_hw(tp, 1))
3879 goto out;
1da177e4
LT		 3880
3881 tg3_netif_start(tp);
3882
1da177e4
LT		 3883 if (restart_timer)
3884 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3885
b9ec6c1b 3886out:
7faa006f 3887 tg3_full_unlock(tp);
1da177e4
LT		 3888}
3889
b0408751
MC		 3890static void tg3_dump_short_state(struct tg3 *tp)
3891{
3892 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3893 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3894 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3895 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3896}
3897
1da177e4
LT		 3898static void tg3_tx_timeout(struct net_device *dev)
3899{
3900 struct tg3 *tp = netdev_priv(dev);
3901
b0408751 3902 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 3903 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3904 dev->name);
b0408751
MC		 3905 tg3_dump_short_state(tp);
3906 }
1da177e4
LT		 3907
3908 schedule_work(&tp->reset_task);
3909}
3910
c58ec932
MC		 3911/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3912static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3913{
3914 u32 base = (u32) mapping & 0xffffffff;
3915
3916 return ((base > 0xffffdcc0) &&
3917 (base + len + 8 < base));
3918}
3919
72f2afb8
MC		 3920/* Test for DMA addresses > 40-bit */
3921static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3922 int len)
3923{
3924#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3925 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3926 return (((u64) mapping + len) > DMA_40BIT_MASK);
3927 return 0;
3928#else
3929 return 0;
3930#endif
3931}
3932
1da177e4
LT		 3933static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3934
72f2afb8
MC		 3935/* Workaround 4GB and 40-bit hardware DMA bugs. */
3936static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3937 u32 last_plus_one, u32 *start,
3938 u32 base_flags, u32 mss)
1da177e4
LT		 3939{
3940 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3941 dma_addr_t new_addr = 0;
1da177e4 3942 u32 entry = *start;
c58ec932 3943 int i, ret = 0;
1da177e4
LT		 3944
3945 if (!new_skb) {
c58ec932
MC		 3946 ret = -1;
3947 } else {
3948 /* New SKB is guaranteed to be linear. */
3949 entry = *start;
3950 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3951 PCI_DMA_TODEVICE);
3952 /* Make sure new skb does not cross any 4G boundaries.
3953 * Drop the packet if it does.
3954 */
3955 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3956 ret = -1;
3957 dev_kfree_skb(new_skb);
3958 new_skb = NULL;
3959 } else {
3960 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3961 base_flags, 1 | (mss << 1));
3962 *start = NEXT_TX(entry);
3963 }
1da177e4
LT		 3964 }
3965
1da177e4
LT		 3966 /* Now clean up the sw ring entries. */
3967 i = 0;
3968 while (entry != last_plus_one) {
3969 int len;
3970
3971 if (i == 0)
3972 len = skb_headlen(skb);
3973 else
3974 len = skb_shinfo(skb)->frags[i-1].size;
3975 pci_unmap_single(tp->pdev,
3976 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3977 len, PCI_DMA_TODEVICE);
3978 if (i == 0) {
3979 tp->tx_buffers[entry].skb = new_skb;
3980 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3981 } else {
3982 tp->tx_buffers[entry].skb = NULL;
3983 }
3984 entry = NEXT_TX(entry);
3985 i++;
3986 }
3987
3988 dev_kfree_skb(skb);
3989
c58ec932 3990 return ret;
1da177e4
LT		 3991}
3992
3993static void tg3_set_txd(struct tg3 *tp, int entry,
3994 dma_addr_t mapping, int len, u32 flags,
3995 u32 mss_and_is_end)
3996{
3997 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3998 int is_end = (mss_and_is_end & 0x1);
3999 u32 mss = (mss_and_is_end >> 1);
4000 u32 vlan_tag = 0;
4001
4002 if (is_end)
4003 flags |= TXD_FLAG_END;
4004 if (flags & TXD_FLAG_VLAN) {
4005 vlan_tag = flags >> 16;
4006 flags &= 0xffff;
4007 }
4008 vlan_tag |= (mss << TXD_MSS_SHIFT);
4009
4010 txd->addr_hi = ((u64) mapping >> 32);
4011 txd->addr_lo = ((u64) mapping & 0xffffffff);
4012 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4013 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4014}
4015
5a6f3074
MC		 4016/* hard_start_xmit for devices that don't have any bugs and
4017 * support TG3_FLG2_HW_TSO_2 only.
4018 */
1da177e4 4019static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 4020{
4021 struct tg3 *tp = netdev_priv(dev);
4022 dma_addr_t mapping;
4023 u32 len, entry, base_flags, mss;
4024
4025 len = skb_headlen(skb);
4026
00b70504 4027 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4028 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 4029 * interrupt. Furthermore, IRQ processing runs lockless so we have
4030 * no IRQ context deadlocks to worry about either. Rejoice!
4031 */
1b2a7205 4032 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 4033 if (!netif_queue_stopped(dev)) {
4034 netif_stop_queue(dev);
4035
4036 /* This is a hard error, log it. */
4037 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4038 "queue awake!\n", dev->name);
4039 }
5a6f3074
MC		 4040 return NETDEV_TX_BUSY;
4041 }
4042
4043 entry = tp->tx_prod;
4044 base_flags = 0;
5a6f3074 4045 mss = 0;
c13e3713 4046 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 4047 int tcp_opt_len, ip_tcp_len;
4048
4049 if (skb_header_cloned(skb) &&
4050 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4051 dev_kfree_skb(skb);
4052 goto out_unlock;
4053 }
4054
b0026624
MC		 4055 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4056 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4057 else {
eddc9ec5
ACM		 4058 struct iphdr *iph = ip_hdr(skb);
4059
ab6a5bb6 4060 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4061 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 4062
eddc9ec5
ACM		 4063 iph->check = 0;
4064 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 4065 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4066 }
5a6f3074
MC		 4067
4068 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4069 TXD_FLAG_CPU_POST_DMA);
4070
aa8223c7 4071 tcp_hdr(skb)->check = 0;
5a6f3074 4072
5a6f3074 4073 }
84fa7933 4074 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 4075 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 4076#if TG3_VLAN_TAG_USED
4077 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4078 base_flags |= (TXD_FLAG_VLAN |
4079 (vlan_tx_tag_get(skb) << 16));
4080#endif
4081
4082 /* Queue skb data, a.k.a. the main skb fragment. */
4083 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4084
4085 tp->tx_buffers[entry].skb = skb;
4086 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4087
4088 tg3_set_txd(tp, entry, mapping, len, base_flags,
4089 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4090
4091 entry = NEXT_TX(entry);
4092
4093 /* Now loop through additional data fragments, and queue them. */
4094 if (skb_shinfo(skb)->nr_frags > 0) {
4095 unsigned int i, last;
4096
4097 last = skb_shinfo(skb)->nr_frags - 1;
4098 for (i = 0; i <= last; i++) {
4099 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4100
4101 len = frag->size;
4102 mapping = pci_map_page(tp->pdev,
4103 frag->page,
4104 frag->page_offset,
4105 len, PCI_DMA_TODEVICE);
4106
4107 tp->tx_buffers[entry].skb = NULL;
4108 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4109
4110 tg3_set_txd(tp, entry, mapping, len,
4111 base_flags, (i == last) | (mss << 1));
4112
4113 entry = NEXT_TX(entry);
4114 }
4115 }
4116
4117 /* Packets are ready, update Tx producer idx local and on card. */
4118 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4119
4120 tp->tx_prod = entry;
1b2a7205 4121 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 4122 netif_stop_queue(dev);
42952231 4123 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 4124 netif_wake_queue(tp->dev);
4125 }
4126
4127out_unlock:
4128 mmiowb();
5a6f3074
MC		 4129
4130 dev->trans_start = jiffies;
4131
4132 return NETDEV_TX_OK;
4133}
4134
52c0fd83
MC		 4135static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4136
4137/* Use GSO to workaround a rare TSO bug that may be triggered when the
4138 * TSO header is greater than 80 bytes.
4139 */
4140static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4141{
4142 struct sk_buff *segs, *nskb;
4143
4144 /* Estimate the number of fragments in the worst case */
1b2a7205 4145 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 4146 netif_stop_queue(tp->dev);
7f62ad5d
MC		 4147 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4148 return NETDEV_TX_BUSY;
4149
4150 netif_wake_queue(tp->dev);
52c0fd83
MC		 4151 }
4152
4153 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4154 if (unlikely(IS_ERR(segs)))
4155 goto tg3_tso_bug_end;
4156
4157 do {
4158 nskb = segs;
4159 segs = segs->next;
4160 nskb->next = NULL;
4161 tg3_start_xmit_dma_bug(nskb, tp->dev);
4162 } while (segs);
4163
4164tg3_tso_bug_end:
4165 dev_kfree_skb(skb);
4166
4167 return NETDEV_TX_OK;
4168}
52c0fd83 4169
5a6f3074
MC		 4170/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4171 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4172 */
4173static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4174{
4175 struct tg3 *tp = netdev_priv(dev);
4176 dma_addr_t mapping;
1da177e4
LT		 4177 u32 len, entry, base_flags, mss;
4178 int would_hit_hwbug;
1da177e4
LT		 4179
4180 len = skb_headlen(skb);
4181
00b70504 4182 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4183 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 4184 * interrupt. Furthermore, IRQ processing runs lockless so we have
4185 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4186 */
1b2a7205 4187 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4188 if (!netif_queue_stopped(dev)) {
4189 netif_stop_queue(dev);
4190
4191 /* This is a hard error, log it. */
4192 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4193 "queue awake!\n", dev->name);
4194 }
1da177e4
LT		 4195 return NETDEV_TX_BUSY;
4196 }
4197
4198 entry = tp->tx_prod;
4199 base_flags = 0;
84fa7933 4200 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4201 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 4202 mss = 0;
c13e3713 4203 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 4204 struct iphdr *iph;
52c0fd83 4205 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4206
4207 if (skb_header_cloned(skb) &&
4208 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4209 dev_kfree_skb(skb);
4210 goto out_unlock;
4211 }
4212
ab6a5bb6 4213 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4214 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 4215
52c0fd83
MC		 4216 hdr_len = ip_tcp_len + tcp_opt_len;
4217 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 4218 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 4219 return (tg3_tso_bug(tp, skb));
4220
1da177e4
LT		 4221 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4222 TXD_FLAG_CPU_POST_DMA);
4223
eddc9ec5
ACM		 4224 iph = ip_hdr(skb);
4225 iph->check = 0;
4226 iph->tot_len = htons(mss + hdr_len);
1da177e4 4227 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 4228 tcp_hdr(skb)->check = 0;
1da177e4 4229 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 4230 } else
4231 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4232 iph->daddr, 0,
4233 IPPROTO_TCP,
4234 0);
1da177e4
LT		 4235
4236 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4237 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 4238 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4239 int tsflags;
4240
eddc9ec5 4241 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4242 mss |= (tsflags << 11);
4243 }
4244 } else {
eddc9ec5 4245 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4246 int tsflags;
4247
eddc9ec5 4248 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4249 base_flags |= tsflags << 12;
4250 }
4251 }
4252 }
1da177e4
LT		 4253#if TG3_VLAN_TAG_USED
4254 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4255 base_flags |= (TXD_FLAG_VLAN |
4256 (vlan_tx_tag_get(skb) << 16));
4257#endif
4258
4259 /* Queue skb data, a.k.a. the main skb fragment. */
4260 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4261
4262 tp->tx_buffers[entry].skb = skb;
4263 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4264
4265 would_hit_hwbug = 0;
4266
4267 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4268 would_hit_hwbug = 1;
1da177e4
LT		 4269
4270 tg3_set_txd(tp, entry, mapping, len, base_flags,
4271 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4272
4273 entry = NEXT_TX(entry);
4274
4275 /* Now loop through additional data fragments, and queue them. */
4276 if (skb_shinfo(skb)->nr_frags > 0) {
4277 unsigned int i, last;
4278
4279 last = skb_shinfo(skb)->nr_frags - 1;
4280 for (i = 0; i <= last; i++) {
4281 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4282
4283 len = frag->size;
4284 mapping = pci_map_page(tp->pdev,
4285 frag->page,
4286 frag->page_offset,
4287 len, PCI_DMA_TODEVICE);
4288
4289 tp->tx_buffers[entry].skb = NULL;
4290 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4291
c58ec932
MC		 4292 if (tg3_4g_overflow_test(mapping, len))
4293 would_hit_hwbug = 1;
1da177e4 4294
72f2afb8
MC		 4295 if (tg3_40bit_overflow_test(tp, mapping, len))
4296 would_hit_hwbug = 1;
4297
1da177e4
LT		 4298 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4299 tg3_set_txd(tp, entry, mapping, len,
4300 base_flags, (i == last)|(mss << 1));
4301 else
4302 tg3_set_txd(tp, entry, mapping, len,
4303 base_flags, (i == last));
4304
4305 entry = NEXT_TX(entry);
4306 }
4307 }
4308
4309 if (would_hit_hwbug) {
4310 u32 last_plus_one = entry;
4311 u32 start;
1da177e4 4312
c58ec932
MC		 4313 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4314 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4315
4316 /* If the workaround fails due to memory/mapping
4317 * failure, silently drop this packet.
4318 */
72f2afb8 4319 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4320 &start, base_flags, mss))
1da177e4
LT		 4321 goto out_unlock;
4322
4323 entry = start;
4324 }
4325
4326 /* Packets are ready, update Tx producer idx local and on card. */
4327 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4328
4329 tp->tx_prod = entry;
1b2a7205 4330 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4331 netif_stop_queue(dev);
42952231 4332 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4333 netif_wake_queue(tp->dev);
4334 }
1da177e4
LT		 4335
4336out_unlock:
4337 mmiowb();
1da177e4
LT		 4338
4339 dev->trans_start = jiffies;
4340
4341 return NETDEV_TX_OK;
4342}
4343
4344static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4345 int new_mtu)
4346{
4347 dev->mtu = new_mtu;
4348
ef7f5ec0 4349 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4350 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4351 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4352 ethtool_op_set_tso(dev, 0);
4353 }
4354 else
4355 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4356 } else {
a4e2b347 4357 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4358 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4359 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4360 }
1da177e4
LT		 4361}
4362
4363static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4364{
4365 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4366 int err;
1da177e4
LT		 4367
4368 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4369 return -EINVAL;
4370
4371 if (!netif_running(dev)) {
4372 /* We'll just catch it later when the
4373 * device is up'd.
4374 */
4375 tg3_set_mtu(dev, tp, new_mtu);
4376 return 0;
4377 }
4378
4379 tg3_netif_stop(tp);
f47c11ee
DM		 4380
4381 tg3_full_lock(tp, 1);
1da177e4 4382
944d980e 4383 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4384
4385 tg3_set_mtu(dev, tp, new_mtu);
4386
b9ec6c1b 4387 err = tg3_restart_hw(tp, 0);
1da177e4 4388
b9ec6c1b
MC		 4389 if (!err)
4390 tg3_netif_start(tp);
1da177e4 4391
f47c11ee 4392 tg3_full_unlock(tp);
1da177e4 4393
b9ec6c1b 4394 return err;
1da177e4
LT		 4395}
4396
4397/* Free up pending packets in all rx/tx rings.
4398 *
4399 * The chip has been shut down and the driver detached from
4400 * the networking, so no interrupts or new tx packets will
4401 * end up in the driver. tp->{tx,}lock is not held and we are not
4402 * in an interrupt context and thus may sleep.
4403 */
4404static void tg3_free_rings(struct tg3 *tp)
4405{
4406 struct ring_info *rxp;
4407 int i;
4408
4409 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4410 rxp = &tp->rx_std_buffers[i];
4411
4412 if (rxp->skb == NULL)
4413 continue;
4414 pci_unmap_single(tp->pdev,
4415 pci_unmap_addr(rxp, mapping),
7e72aad4 4416 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4417 PCI_DMA_FROMDEVICE);
4418 dev_kfree_skb_any(rxp->skb);
4419 rxp->skb = NULL;
4420 }
4421
4422 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4423 rxp = &tp->rx_jumbo_buffers[i];
4424
4425 if (rxp->skb == NULL)
4426 continue;
4427 pci_unmap_single(tp->pdev,
4428 pci_unmap_addr(rxp, mapping),
4429 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4430 PCI_DMA_FROMDEVICE);
4431 dev_kfree_skb_any(rxp->skb);
4432 rxp->skb = NULL;
4433 }
4434
4435 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4436 struct tx_ring_info *txp;
4437 struct sk_buff *skb;
4438 int j;
4439
4440 txp = &tp->tx_buffers[i];
4441 skb = txp->skb;
4442
4443 if (skb == NULL) {
4444 i++;
4445 continue;
4446 }
4447
4448 pci_unmap_single(tp->pdev,
4449 pci_unmap_addr(txp, mapping),
4450 skb_headlen(skb),
4451 PCI_DMA_TODEVICE);
4452 txp->skb = NULL;
4453
4454 i++;
4455
4456 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4457 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4458 pci_unmap_page(tp->pdev,
4459 pci_unmap_addr(txp, mapping),
4460 skb_shinfo(skb)->frags[j].size,
4461 PCI_DMA_TODEVICE);
4462 i++;
4463 }
4464
4465 dev_kfree_skb_any(skb);
4466 }
4467}
4468
4469/* Initialize tx/rx rings for packet processing.
4470 *
4471 * The chip has been shut down and the driver detached from
4472 * the networking, so no interrupts or new tx packets will
4473 * end up in the driver. tp->{tx,}lock are held and thus
4474 * we may not sleep.
4475 */
32d8c572 4476static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4477{
4478 u32 i;
4479
4480 /* Free up all the SKBs. */
4481 tg3_free_rings(tp);
4482
4483 /* Zero out all descriptors. */
4484 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4485 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4486 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4487 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4488
7e72aad4 4489 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4490 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4491 (tp->dev->mtu > ETH_DATA_LEN))
4492 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4493
1da177e4
LT		 4494 /* Initialize invariants of the rings, we only set this
4495 * stuff once. This works because the card does not
4496 * write into the rx buffer posting rings.
4497 */
4498 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4499 struct tg3_rx_buffer_desc *rxd;
4500
4501 rxd = &tp->rx_std[i];
7e72aad4 4502 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4503 << RXD_LEN_SHIFT;
4504 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4505 rxd->opaque = (RXD_OPAQUE_RING_STD |
4506 (i << RXD_OPAQUE_INDEX_SHIFT));
4507 }
4508
0f893dc6 4509 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4510 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4511 struct tg3_rx_buffer_desc *rxd;
4512
4513 rxd = &tp->rx_jumbo[i];
4514 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4515 << RXD_LEN_SHIFT;
4516 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4517 RXD_FLAG_JUMBO;
4518 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4519 (i << RXD_OPAQUE_INDEX_SHIFT));
4520 }
4521 }
4522
4523 /* Now allocate fresh SKBs for each rx ring. */
4524 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4525 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4526 printk(KERN_WARNING PFX
4527 "%s: Using a smaller RX standard ring, "
4528 "only %d out of %d buffers were allocated "
4529 "successfully.\n",
4530 tp->dev->name, i, tp->rx_pending);
4531 if (i == 0)
4532 return -ENOMEM;
4533 tp->rx_pending = i;
1da177e4 4534 break;
32d8c572 4535 }
1da177e4
LT		 4536 }
4537
0f893dc6 4538 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4539 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4540 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4541 -1, i) < 0) {
4542 printk(KERN_WARNING PFX
4543 "%s: Using a smaller RX jumbo ring, "
4544 "only %d out of %d buffers were "
4545 "allocated successfully.\n",
4546 tp->dev->name, i, tp->rx_jumbo_pending);
4547 if (i == 0) {
4548 tg3_free_rings(tp);
4549 return -ENOMEM;
4550 }
4551 tp->rx_jumbo_pending = i;
1da177e4 4552 break;
32d8c572 4553 }
1da177e4
LT		 4554 }
4555 }
32d8c572 4556 return 0;
1da177e4
LT		 4557}
4558
4559/*
4560 * Must not be invoked with interrupt sources disabled and
4561 * the hardware shutdown down.
4562 */
4563static void tg3_free_consistent(struct tg3 *tp)
4564{
b4558ea9
JJ		 4565 kfree(tp->rx_std_buffers);
4566 tp->rx_std_buffers = NULL;
1da177e4
LT		 4567 if (tp->rx_std) {
4568 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4569 tp->rx_std, tp->rx_std_mapping);
4570 tp->rx_std = NULL;
4571 }
4572 if (tp->rx_jumbo) {
4573 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4574 tp->rx_jumbo, tp->rx_jumbo_mapping);
4575 tp->rx_jumbo = NULL;
4576 }
4577 if (tp->rx_rcb) {
4578 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4579 tp->rx_rcb, tp->rx_rcb_mapping);
4580 tp->rx_rcb = NULL;
4581 }
4582 if (tp->tx_ring) {
4583 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4584 tp->tx_ring, tp->tx_desc_mapping);
4585 tp->tx_ring = NULL;
4586 }
4587 if (tp->hw_status) {
4588 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4589 tp->hw_status, tp->status_mapping);
4590 tp->hw_status = NULL;
4591 }
4592 if (tp->hw_stats) {
4593 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4594 tp->hw_stats, tp->stats_mapping);
4595 tp->hw_stats = NULL;
4596 }
4597}
4598
4599/*
4600 * Must not be invoked with interrupt sources disabled and
4601 * the hardware shutdown down. Can sleep.
4602 */
4603static int tg3_alloc_consistent(struct tg3 *tp)
4604{
bd2b3343 4605 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4606 (TG3_RX_RING_SIZE +
4607 TG3_RX_JUMBO_RING_SIZE)) +
4608 (sizeof(struct tx_ring_info) *
4609 TG3_TX_RING_SIZE),
4610 GFP_KERNEL);
4611 if (!tp->rx_std_buffers)
4612 return -ENOMEM;
4613
1da177e4
LT		 4614 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4615 tp->tx_buffers = (struct tx_ring_info *)
4616 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4617
4618 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4619 &tp->rx_std_mapping);
4620 if (!tp->rx_std)
4621 goto err_out;
4622
4623 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4624 &tp->rx_jumbo_mapping);
4625
4626 if (!tp->rx_jumbo)
4627 goto err_out;
4628
4629 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4630 &tp->rx_rcb_mapping);
4631 if (!tp->rx_rcb)
4632 goto err_out;
4633
4634 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4635 &tp->tx_desc_mapping);
4636 if (!tp->tx_ring)
4637 goto err_out;
4638
4639 tp->hw_status = pci_alloc_consistent(tp->pdev,
4640 TG3_HW_STATUS_SIZE,
4641 &tp->status_mapping);
4642 if (!tp->hw_status)
4643 goto err_out;
4644
4645 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4646 sizeof(struct tg3_hw_stats),
4647 &tp->stats_mapping);
4648 if (!tp->hw_stats)
4649 goto err_out;
4650
4651 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4652 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4653
4654 return 0;
4655
4656err_out:
4657 tg3_free_consistent(tp);
4658 return -ENOMEM;
4659}
4660
4661#define MAX_WAIT_CNT 1000
4662
4663/* To stop a block, clear the enable bit and poll till it
4664 * clears. tp->lock is held.
4665 */
b3b7d6be 4666static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4667{
4668 unsigned int i;
4669 u32 val;
4670
4671 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4672 switch (ofs) {
4673 case RCVLSC_MODE:
4674 case DMAC_MODE:
4675 case MBFREE_MODE:
4676 case BUFMGR_MODE:
4677 case MEMARB_MODE:
4678 /* We can't enable/disable these bits of the
4679 * 5705/5750, just say success.
4680 */
4681 return 0;
4682
4683 default:
4684 break;
4685 };
4686 }
4687
4688 val = tr32(ofs);
4689 val &= ~enable_bit;
4690 tw32_f(ofs, val);
4691
4692 for (i = 0; i < MAX_WAIT_CNT; i++) {
4693 udelay(100);
4694 val = tr32(ofs);
4695 if ((val & enable_bit) == 0)
4696 break;
4697 }
4698
b3b7d6be 4699 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4700 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4701 "ofs=%lx enable_bit=%x\n",
4702 ofs, enable_bit);
4703 return -ENODEV;
4704 }
4705
4706 return 0;
4707}
4708
4709/* tp->lock is held. */
b3b7d6be 4710static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4711{
4712 int i, err;
4713
4714 tg3_disable_ints(tp);
4715
4716 tp->rx_mode &= ~RX_MODE_ENABLE;
4717 tw32_f(MAC_RX_MODE, tp->rx_mode);
4718 udelay(10);
4719
b3b7d6be
DM		 4720 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4721 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4722 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4723 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4724 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4725 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4726
4727 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4728 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4729 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4730 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4731 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4732 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4733 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4734
4735 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4736 tw32_f(MAC_MODE, tp->mac_mode);
4737 udelay(40);
4738
4739 tp->tx_mode &= ~TX_MODE_ENABLE;
4740 tw32_f(MAC_TX_MODE, tp->tx_mode);
4741
4742 for (i = 0; i < MAX_WAIT_CNT; i++) {
4743 udelay(100);
4744 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4745 break;
4746 }
4747 if (i >= MAX_WAIT_CNT) {
4748 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4749 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4750 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4751 err |= -ENODEV;
1da177e4
LT		 4752 }
4753
e6de8ad1 4754 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4755 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4756 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4757
4758 tw32(FTQ_RESET, 0xffffffff);
4759 tw32(FTQ_RESET, 0x00000000);
4760
b3b7d6be
DM		 4761 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4762 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4763
4764 if (tp->hw_status)
4765 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4766 if (tp->hw_stats)
4767 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4768
1da177e4
LT		 4769 return err;
4770}
4771
4772/* tp->lock is held. */
4773static int tg3_nvram_lock(struct tg3 *tp)
4774{
4775 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4776 int i;
4777
ec41c7df
MC		 4778 if (tp->nvram_lock_cnt == 0) {
4779 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4780 for (i = 0; i < 8000; i++) {
4781 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4782 break;
4783 udelay(20);
4784 }
4785 if (i == 8000) {
4786 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4787 return -ENODEV;
4788 }
1da177e4 4789 }
ec41c7df 4790 tp->nvram_lock_cnt++;
1da177e4
LT		 4791 }
4792 return 0;
4793}
4794
4795/* tp->lock is held. */
4796static void tg3_nvram_unlock(struct tg3 *tp)
4797{
ec41c7df
MC		 4798 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4799 if (tp->nvram_lock_cnt > 0)
4800 tp->nvram_lock_cnt--;
4801 if (tp->nvram_lock_cnt == 0)
4802 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4803 }
1da177e4
LT		 4804}
4805
e6af301b
MC		 4806/* tp->lock is held. */
4807static void tg3_enable_nvram_access(struct tg3 *tp)
4808{
4809 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4810 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4811 u32 nvaccess = tr32(NVRAM_ACCESS);
4812
4813 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4814 }
4815}
4816
4817/* tp->lock is held. */
4818static void tg3_disable_nvram_access(struct tg3 *tp)
4819{
4820 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4821 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4822 u32 nvaccess = tr32(NVRAM_ACCESS);
4823
4824 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4825 }
4826}
4827
0d3031d9
MC		 4828static void tg3_ape_send_event(struct tg3 *tp, u32 event)
4829{
4830 int i;
4831 u32 apedata;
4832
4833 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
4834 if (apedata != APE_SEG_SIG_MAGIC)
4835 return;
4836
4837 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
4838 if (apedata != APE_FW_STATUS_READY)
4839 return;
4840
4841 /* Wait for up to 1 millisecond for APE to service previous event. */
4842 for (i = 0; i < 10; i++) {
4843 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
4844 return;
4845
4846 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
4847
4848 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4849 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
4850 event | APE_EVENT_STATUS_EVENT_PENDING);
4851
4852 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
4853
4854 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4855 break;
4856
4857 udelay(100);
4858 }
4859
4860 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4861 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
4862}
4863
4864static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
4865{
4866 u32 event;
4867 u32 apedata;
4868
4869 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
4870 return;
4871
4872 switch (kind) {
4873 case RESET_KIND_INIT:
4874 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
4875 APE_HOST_SEG_SIG_MAGIC);
4876 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
4877 APE_HOST_SEG_LEN_MAGIC);
4878 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
4879 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
4880 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
4881 APE_HOST_DRIVER_ID_MAGIC);
4882 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
4883 APE_HOST_BEHAV_NO_PHYLOCK);
4884
4885 event = APE_EVENT_STATUS_STATE_START;
4886 break;
4887 case RESET_KIND_SHUTDOWN:
4888 event = APE_EVENT_STATUS_STATE_UNLOAD;
4889 break;
4890 case RESET_KIND_SUSPEND:
4891 event = APE_EVENT_STATUS_STATE_SUSPEND;
4892 break;
4893 default:
4894 return;
4895 }
4896
4897 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
4898
4899 tg3_ape_send_event(tp, event);
4900}
4901
1da177e4
LT		 4902/* tp->lock is held. */
4903static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4904{
f49639e6
DM		 4905 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4906 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4907
4908 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4909 switch (kind) {
4910 case RESET_KIND_INIT:
4911 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4912 DRV_STATE_START);
4913 break;
4914
4915 case RESET_KIND_SHUTDOWN:
4916 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4917 DRV_STATE_UNLOAD);
4918 break;
4919
4920 case RESET_KIND_SUSPEND:
4921 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4922 DRV_STATE_SUSPEND);
4923 break;
4924
4925 default:
4926 break;
4927 };
4928 }
0d3031d9
MC		 4929
4930 if (kind == RESET_KIND_INIT ||
4931 kind == RESET_KIND_SUSPEND)
4932 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 4933}
4934
4935/* tp->lock is held. */
4936static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4937{
4938 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4939 switch (kind) {
4940 case RESET_KIND_INIT:
4941 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4942 DRV_STATE_START_DONE);
4943 break;
4944
4945 case RESET_KIND_SHUTDOWN:
4946 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4947 DRV_STATE_UNLOAD_DONE);
4948 break;
4949
4950 default:
4951 break;
4952 };
4953 }
0d3031d9
MC		 4954
4955 if (kind == RESET_KIND_SHUTDOWN)
4956 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 4957}
4958
4959/* tp->lock is held. */
4960static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4961{
4962 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4963 switch (kind) {
4964 case RESET_KIND_INIT:
4965 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4966 DRV_STATE_START);
4967 break;
4968
4969 case RESET_KIND_SHUTDOWN:
4970 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4971 DRV_STATE_UNLOAD);
4972 break;
4973
4974 case RESET_KIND_SUSPEND:
4975 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4976 DRV_STATE_SUSPEND);
4977 break;
4978
4979 default:
4980 break;
4981 };
4982 }
4983}
4984
7a6f4369
MC		 4985static int tg3_poll_fw(struct tg3 *tp)
4986{
4987 int i;
4988 u32 val;
4989
b5d3772c 4990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 4991 /* Wait up to 20ms for init done. */
4992 for (i = 0; i < 200; i++) {
b5d3772c
MC		 4993 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4994 return 0;
0ccead18 4995 udelay(100);
b5d3772c
MC		 4996 }
4997 return -ENODEV;
4998 }
4999
7a6f4369
MC		 5000 /* Wait for firmware initialization to complete. */
5001 for (i = 0; i < 100000; i++) {
5002 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5003 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5004 break;
5005 udelay(10);
5006 }
5007
5008 /* Chip might not be fitted with firmware. Some Sun onboard
5009 * parts are configured like that. So don't signal the timeout
5010 * of the above loop as an error, but do report the lack of
5011 * running firmware once.
5012 */
5013 if (i >= 100000 &&
5014 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5015 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5016
5017 printk(KERN_INFO PFX "%s: No firmware running.\n",
5018 tp->dev->name);
5019 }
5020
5021 return 0;
5022}
5023
ee6a99b5
MC		 5024/* Save PCI command register before chip reset */
5025static void tg3_save_pci_state(struct tg3 *tp)
5026{
5027 u32 val;
5028
5029 pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
5030 tp->pci_cmd = val;
5031}
5032
5033/* Restore PCI state after chip reset */
5034static void tg3_restore_pci_state(struct tg3 *tp)
5035{
5036 u32 val;
5037
5038 /* Re-enable indirect register accesses. */
5039 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5040 tp->misc_host_ctrl);
5041
5042 /* Set MAX PCI retry to zero. */
5043 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5044 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5045 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5046 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 5047 /* Allow reads and writes to the APE register and memory space. */
5048 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5049 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5050 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 5051 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5052
5053 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
5054
5055 /* Make sure PCI-X relaxed ordering bit is clear. */
9974a356
MC		 5056 if (tp->pcix_cap) {
5057 u16 pcix_cmd;
5058
5059 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5060 &pcix_cmd);
5061 pcix_cmd &= ~PCI_X_CMD_ERO;
5062 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5063 pcix_cmd);
5064 }
ee6a99b5
MC		 5065
5066 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 5067
5068 /* Chip reset on 5780 will reset MSI enable bit,
5069 * so need to restore it.
5070 */
5071 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5072 u16 ctrl;
5073
5074 pci_read_config_word(tp->pdev,
5075 tp->msi_cap + PCI_MSI_FLAGS,
5076 &ctrl);
5077 pci_write_config_word(tp->pdev,
5078 tp->msi_cap + PCI_MSI_FLAGS,
5079 ctrl | PCI_MSI_FLAGS_ENABLE);
5080 val = tr32(MSGINT_MODE);
5081 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5082 }
5083 }
5084}
5085
1da177e4
LT		 5086static void tg3_stop_fw(struct tg3 *);
5087
5088/* tp->lock is held. */
5089static int tg3_chip_reset(struct tg3 *tp)
5090{
5091 u32 val;
1ee582d8 5092 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 5093 int err;
1da177e4 5094
f49639e6
DM		 5095 tg3_nvram_lock(tp);
5096
5097 /* No matching tg3_nvram_unlock() after this because
5098 * chip reset below will undo the nvram lock.
5099 */
5100 tp->nvram_lock_cnt = 0;
1da177e4 5101
ee6a99b5
MC		 5102 /* GRC_MISC_CFG core clock reset will clear the memory
5103 * enable bit in PCI register 4 and the MSI enable bit
5104 * on some chips, so we save relevant registers here.
5105 */
5106 tg3_save_pci_state(tp);
5107
d9ab5ad1 5108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 5109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 5110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 5111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d9ab5ad1
MC		 5113 tw32(GRC_FASTBOOT_PC, 0);
5114
1da177e4
LT		 5115 /*
5116 * We must avoid the readl() that normally takes place.
5117 * It locks machines, causes machine checks, and other
5118 * fun things. So, temporarily disable the 5701
5119 * hardware workaround, while we do the reset.
5120 */
1ee582d8
MC		 5121 write_op = tp->write32;
5122 if (write_op == tg3_write_flush_reg32)
5123 tp->write32 = tg3_write32;
1da177e4 5124
d18edcb2
MC		 5125 /* Prevent the irq handler from reading or writing PCI registers
5126 * during chip reset when the memory enable bit in the PCI command
5127 * register may be cleared. The chip does not generate interrupt
5128 * at this time, but the irq handler may still be called due to irq
5129 * sharing or irqpoll.
5130 */
5131 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 5132 if (tp->hw_status) {
5133 tp->hw_status->status = 0;
5134 tp->hw_status->status_tag = 0;
5135 }
d18edcb2
MC		 5136 tp->last_tag = 0;
5137 smp_mb();
5138 synchronize_irq(tp->pdev->irq);
5139
1da177e4
LT		 5140 /* do the reset */
5141 val = GRC_MISC_CFG_CORECLK_RESET;
5142
5143 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5144 if (tr32(0x7e2c) == 0x60) {
5145 tw32(0x7e2c, 0x20);
5146 }
5147 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5148 tw32(GRC_MISC_CFG, (1 << 29));
5149 val |= (1 << 29);
5150 }
5151 }
5152
b5d3772c
MC		 5153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5154 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5155 tw32(GRC_VCPU_EXT_CTRL,
5156 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5157 }
5158
1da177e4
LT		 5159 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5160 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5161 tw32(GRC_MISC_CFG, val);
5162
1ee582d8
MC		 5163 /* restore 5701 hardware bug workaround write method */
5164 tp->write32 = write_op;
1da177e4
LT		 5165
5166 /* Unfortunately, we have to delay before the PCI read back.
5167 * Some 575X chips even will not respond to a PCI cfg access
5168 * when the reset command is given to the chip.
5169 *
5170 * How do these hardware designers expect things to work
5171 * properly if the PCI write is posted for a long period
5172 * of time? It is always necessary to have some method by
5173 * which a register read back can occur to push the write
5174 * out which does the reset.
5175 *
5176 * For most tg3 variants the trick below was working.
5177 * Ho hum...
5178 */
5179 udelay(120);
5180
5181 /* Flush PCI posted writes. The normal MMIO registers
5182 * are inaccessible at this time so this is the only
5183 * way to make this reliably (actually, this is no longer
5184 * the case, see above). I tried to use indirect
5185 * register read/write but this upset some 5701 variants.
5186 */
5187 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5188
5189 udelay(120);
5190
5191 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5192 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5193 int i;
5194 u32 cfg_val;
5195
5196 /* Wait for link training to complete. */
5197 for (i = 0; i < 5000; i++)
5198 udelay(100);
5199
5200 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5201 pci_write_config_dword(tp->pdev, 0xc4,
5202 cfg_val | (1 << 15));
5203 }
5204 /* Set PCIE max payload size and clear error status. */
5205 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5206 }
5207
ee6a99b5 5208 tg3_restore_pci_state(tp);
1da177e4 5209
d18edcb2
MC		 5210 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5211
ee6a99b5
MC		 5212 val = 0;
5213 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 5214 val = tr32(MEMARB_MODE);
ee6a99b5 5215 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 5216
5217 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5218 tg3_stop_fw(tp);
5219 tw32(0x5000, 0x400);
5220 }
5221
5222 tw32(GRC_MODE, tp->grc_mode);
5223
5224 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 5225 val = tr32(0xc4);
1da177e4
LT		 5226
5227 tw32(0xc4, val | (1 << 15));
5228 }
5229
5230 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5232 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5233 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5234 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5235 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5236 }
5237
5238 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5239 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5240 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 5241 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5242 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5243 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 5244 } else
5245 tw32_f(MAC_MODE, 0);
5246 udelay(40);
5247
7a6f4369
MC		 5248 err = tg3_poll_fw(tp);
5249 if (err)
5250 return err;
1da177e4
LT		 5251
5252 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5253 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 5254 val = tr32(0x7c00);
1da177e4
LT		 5255
5256 tw32(0x7c00, val | (1 << 25));
5257 }
5258
5259 /* Reprobe ASF enable state. */
5260 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5261 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5262 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5263 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5264 u32 nic_cfg;
5265
5266 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5267 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5268 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 5269 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 5270 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5271 }
5272 }
5273
5274 return 0;
5275}
5276
5277/* tp->lock is held. */
5278static void tg3_stop_fw(struct tg3 *tp)
5279{
0d3031d9
MC		 5280 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5281 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 5282 u32 val;
5283 int i;
5284
5285 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5286 val = tr32(GRC_RX_CPU_EVENT);
5287 val |= (1 << 14);
5288 tw32(GRC_RX_CPU_EVENT, val);
5289
5290 /* Wait for RX cpu to ACK the event. */
5291 for (i = 0; i < 100; i++) {
5292 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5293 break;
5294 udelay(1);
5295 }
5296 }
5297}
5298
5299/* tp->lock is held. */
944d980e 5300static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 5301{
5302 int err;
5303
5304 tg3_stop_fw(tp);
5305
944d980e 5306 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5307
b3b7d6be 5308 tg3_abort_hw(tp, silent);
1da177e4
LT		 5309 err = tg3_chip_reset(tp);
5310
944d980e
MC		 5311 tg3_write_sig_legacy(tp, kind);
5312 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5313
5314 if (err)
5315 return err;
5316
5317 return 0;
5318}
5319
5320#define TG3_FW_RELEASE_MAJOR 0x0
5321#define TG3_FW_RELASE_MINOR 0x0
5322#define TG3_FW_RELEASE_FIX 0x0
5323#define TG3_FW_START_ADDR 0x08000000
5324#define TG3_FW_TEXT_ADDR 0x08000000
5325#define TG3_FW_TEXT_LEN 0x9c0
5326#define TG3_FW_RODATA_ADDR 0x080009c0
5327#define TG3_FW_RODATA_LEN 0x60
5328#define TG3_FW_DATA_ADDR 0x08000a40
5329#define TG3_FW_DATA_LEN 0x20
5330#define TG3_FW_SBSS_ADDR 0x08000a60
5331#define TG3_FW_SBSS_LEN 0xc
5332#define TG3_FW_BSS_ADDR 0x08000a70
5333#define TG3_FW_BSS_LEN 0x10
5334
50da859d 5335static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5336 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5337 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5338 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5339 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5340 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5341 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5342 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5343 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5344 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5345 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5346 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5347 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5348 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5349 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5350 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5351 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5352 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5353 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5354 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5355 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5356 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5357 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5358 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5359 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5360 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5361 0, 0, 0, 0, 0, 0,
5362 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5363 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5364 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5365 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5366 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5367 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5368 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5369 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5370 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5371 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5372 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5373 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5376 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5377 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5378 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5379 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5380 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5381 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5382 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5383 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5384 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5385 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5386 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5387 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5388 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5389 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5390 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5391 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5392 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5393 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5394 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5395 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5396 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5397 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5398 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5399 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5400 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5401 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5402 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5403 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5404 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5405 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5406 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5407 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5408 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5409 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5410 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5411 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5412 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5413 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5414 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5415 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5416 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5417 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5418 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5419 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5420 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5421 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5422 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5423 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5424 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5425 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5426 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5427};
5428
50da859d 5429static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5430 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5431 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5432 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5433 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5434 0x00000000
5435};
5436
5437#if 0 /* All zeros, don't eat up space with it. */
5438u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5439 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5440 0x00000000, 0x00000000, 0x00000000, 0x00000000
5441};
5442#endif
5443
5444#define RX_CPU_SCRATCH_BASE 0x30000
5445#define RX_CPU_SCRATCH_SIZE 0x04000
5446#define TX_CPU_SCRATCH_BASE 0x34000
5447#define TX_CPU_SCRATCH_SIZE 0x04000
5448
5449/* tp->lock is held. */
5450static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5451{
5452 int i;
5453
5d9428de
ES		 5454 BUG_ON(offset == TX_CPU_BASE &&
5455 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5456
b5d3772c
MC		 5457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5458 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5459
5460 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5461 return 0;
5462 }
1da177e4
LT		 5463 if (offset == RX_CPU_BASE) {
5464 for (i = 0; i < 10000; i++) {
5465 tw32(offset + CPU_STATE, 0xffffffff);
5466 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5467 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5468 break;
5469 }
5470
5471 tw32(offset + CPU_STATE, 0xffffffff);
5472 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5473 udelay(10);
5474 } else {
5475 for (i = 0; i < 10000; i++) {
5476 tw32(offset + CPU_STATE, 0xffffffff);
5477 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5478 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5479 break;
5480 }
5481 }
5482
5483 if (i >= 10000) {
5484 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5485 "and %s CPU\n",
5486 tp->dev->name,
5487 (offset == RX_CPU_BASE ? "RX" : "TX"));
5488 return -ENODEV;
5489 }
ec41c7df
MC		 5490
5491 /* Clear firmware's nvram arbitration. */
5492 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5493 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5494 return 0;
5495}
5496
5497struct fw_info {
5498 unsigned int text_base;
5499 unsigned int text_len;
50da859d 5500 const u32 *text_data;
1da177e4
LT		 5501 unsigned int rodata_base;
5502 unsigned int rodata_len;
50da859d 5503 const u32 *rodata_data;
1da177e4
LT		 5504 unsigned int data_base;
5505 unsigned int data_len;
50da859d 5506 const u32 *data_data;
1da177e4
LT		 5507};
5508
5509/* tp->lock is held. */
5510static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5511 int cpu_scratch_size, struct fw_info *info)
5512{
ec41c7df 5513 int err, lock_err, i;
1da177e4
LT		 5514 void (*write_op)(struct tg3 *, u32, u32);
5515
5516 if (cpu_base == TX_CPU_BASE &&
5517 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5518 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5519 "TX cpu firmware on %s which is 5705.\n",
5520 tp->dev->name);
5521 return -EINVAL;
5522 }
5523
5524 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5525 write_op = tg3_write_mem;
5526 else
5527 write_op = tg3_write_indirect_reg32;
5528
1b628151
MC		 5529 /* It is possible that bootcode is still loading at this point.
5530 * Get the nvram lock first before halting the cpu.
5531 */
ec41c7df 5532 lock_err = tg3_nvram_lock(tp);
1da177e4 5533 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5534 if (!lock_err)
5535 tg3_nvram_unlock(tp);
1da177e4
LT		 5536 if (err)
5537 goto out;
5538
5539 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5540 write_op(tp, cpu_scratch_base + i, 0);
5541 tw32(cpu_base + CPU_STATE, 0xffffffff);
5542 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5543 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5544 write_op(tp, (cpu_scratch_base +
5545 (info->text_base & 0xffff) +
5546 (i * sizeof(u32))),
5547 (info->text_data ?
5548 info->text_data[i] : 0));
5549 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5550 write_op(tp, (cpu_scratch_base +
5551 (info->rodata_base & 0xffff) +
5552 (i * sizeof(u32))),
5553 (info->rodata_data ?
5554 info->rodata_data[i] : 0));
5555 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5556 write_op(tp, (cpu_scratch_base +
5557 (info->data_base & 0xffff) +
5558 (i * sizeof(u32))),
5559 (info->data_data ?
5560 info->data_data[i] : 0));
5561
5562 err = 0;
5563
5564out:
1da177e4
LT		 5565 return err;
5566}
5567
5568/* tp->lock is held. */
5569static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5570{
5571 struct fw_info info;
5572 int err, i;
5573
5574 info.text_base = TG3_FW_TEXT_ADDR;
5575 info.text_len = TG3_FW_TEXT_LEN;
5576 info.text_data = &tg3FwText[0];
5577 info.rodata_base = TG3_FW_RODATA_ADDR;
5578 info.rodata_len = TG3_FW_RODATA_LEN;
5579 info.rodata_data = &tg3FwRodata[0];
5580 info.data_base = TG3_FW_DATA_ADDR;
5581 info.data_len = TG3_FW_DATA_LEN;
5582 info.data_data = NULL;
5583
5584 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5585 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5586 &info);
5587 if (err)
5588 return err;
5589
5590 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5591 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5592 &info);
5593 if (err)
5594 return err;
5595
5596 /* Now startup only the RX cpu. */
5597 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5598 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5599
5600 for (i = 0; i < 5; i++) {
5601 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5602 break;
5603 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5604 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5605 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5606 udelay(1000);
5607 }
5608 if (i >= 5) {
5609 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5610 "to set RX CPU PC, is %08x should be %08x\n",
5611 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5612 TG3_FW_TEXT_ADDR);
5613 return -ENODEV;
5614 }
5615 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5616 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5617
5618 return 0;
5619}
5620
1da177e4
LT		 5621
5622#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5623#define TG3_TSO_FW_RELASE_MINOR 0x6
5624#define TG3_TSO_FW_RELEASE_FIX 0x0
5625#define TG3_TSO_FW_START_ADDR 0x08000000
5626#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5627#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5628#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5629#define TG3_TSO_FW_RODATA_LEN 0x60
5630#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5631#define TG3_TSO_FW_DATA_LEN 0x30
5632#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5633#define TG3_TSO_FW_SBSS_LEN 0x2c
5634#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5635#define TG3_TSO_FW_BSS_LEN 0x894
5636
50da859d 5637static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5638 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5639 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5640 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5641 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5642 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5643 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5644 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5645 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5646 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5647 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5648 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5649 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5650 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5651 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5652 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5653 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5654 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5655 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5656 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5657 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5658 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5659 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5660 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5661 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5662 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5663 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5664 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5665 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5666 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5667 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5668 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5669 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5670 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5671 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5672 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5673 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5674 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5675 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5676 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5677 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5678 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5679 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5680 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5681 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5682 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5683 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5684 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5685 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5686 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5687 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5688 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5689 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5690 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5691 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5692 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5693 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5694 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5695 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5696 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5697 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5698 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5699 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5700 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5701 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5702 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5703 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5704 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5705 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5706 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5707 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5708 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5709 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5710 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5711 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5712 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5713 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5714 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5715 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5716 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5717 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5718 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5719 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5720 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5721 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5722 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5723 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5724 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5725 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5726 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5727 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5728 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5729 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5730 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5731 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5732 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5733 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5734 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5735 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5736 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5737 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5738 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5739 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5740 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5741 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5742 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5743 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5744 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5745 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5746 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5747 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5748 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5749 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5750 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5751 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5752 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5753 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5754 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5755 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5756 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5757 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5758 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5759 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5760 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5761 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5762 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5763 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5764 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5765 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5766 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5767 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5768 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5769 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5770 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5771 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5772 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5773 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5774 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5775 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5776 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5777 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5778 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5779 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5780 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5781 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5782 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5783 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5784 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5785 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5786 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5787 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5788 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5789 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5790 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5791 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5792 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5793 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5794 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5795 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5796 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5797 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5798 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5799 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5800 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5801 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5802 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5803 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5804 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5805 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5806 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5807 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5808 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5809 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5810 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5811 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5812 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5813 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5814 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5815 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5816 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5817 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5818 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5819 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5820 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5821 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5822 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5823 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5824 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5825 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5826 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5827 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5828 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5829 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5830 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5831 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5832 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5833 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5834 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5835 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5836 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5837 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5838 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5839 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5840 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5841 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5842 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5843 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5844 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5845 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5846 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5847 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5848 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5849 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5850 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5851 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5852 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5853 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5854 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5855 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5856 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5857 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5858 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5859 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5860 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5861 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5862 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5863 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5864 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5865 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5866 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5867 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5868 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5869 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5870 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5871 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5872 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5873 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5874 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5875 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5876 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5877 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5878 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5879 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5880 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5881 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5882 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5883 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5884 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5885 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5886 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5887 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5888 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5889 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5890 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5891 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5892 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5893 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5894 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5895 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5896 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5897 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5898 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5899 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5900 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5901 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5902 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5903 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5904 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5905 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5906 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5907 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5908 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5909 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5910 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5911 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5912 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5913 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5914 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5915 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5916 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5917 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5918 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5919 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5920 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5921 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5922};
5923
50da859d 5924static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5925 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5926 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5927 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5928 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5929 0x00000000,
5930};
5931
50da859d 5932static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5933 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5934 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5935 0x00000000,
5936};
5937
5938/* 5705 needs a special version of the TSO firmware. */
5939#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5940#define TG3_TSO5_FW_RELASE_MINOR 0x2
5941#define TG3_TSO5_FW_RELEASE_FIX 0x0
5942#define TG3_TSO5_FW_START_ADDR 0x00010000
5943#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5944#define TG3_TSO5_FW_TEXT_LEN 0xe90
5945#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5946#define TG3_TSO5_FW_RODATA_LEN 0x50
5947#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5948#define TG3_TSO5_FW_DATA_LEN 0x20
5949#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5950#define TG3_TSO5_FW_SBSS_LEN 0x28
5951#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5952#define TG3_TSO5_FW_BSS_LEN 0x88
5953
50da859d 5954static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5955 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5956 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5957 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5958 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5959 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5960 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5961 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5962 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5963 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5964 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5965 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5966 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5967 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5968 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5969 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5970 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5971 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5972 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5973 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5974 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5975 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5976 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5977 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5978 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5979 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5980 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5981 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5982 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5983 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5984 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5985 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5986 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5987 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5988 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5989 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5990 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5991 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5992 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5993 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5994 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5995 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5996 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5997 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5998 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5999 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6000 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6001 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6002 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6003 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6004 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6005 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6006 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6007 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6008 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6009 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6010 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6011 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6012 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6013 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6014 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6015 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6016 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6017 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6018 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6019 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6020 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6021 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6022 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6023 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6024 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6025 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6026 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6027 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6028 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6029 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6030 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6031 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6032 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6033 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6034 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6035 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6036 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6037 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6038 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6039 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6040 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6041 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6042 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6043 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6044 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6045 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6046 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6047 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6048 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6049 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6050 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6051 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6052 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6053 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6054 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6055 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6056 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6057 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6058 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6059 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6060 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6061 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6062 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6063 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6064 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6065 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6066 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6067 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6068 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6069 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6070 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6071 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6072 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6073 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6074 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6075 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6076 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6077 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6078 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6079 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6080 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6081 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6082 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6083 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6084 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6085 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6086 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6087 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6088 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6089 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6090 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6091 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6092 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6093 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6094 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6095 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6096 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6097 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6098 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6099 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6100 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6101 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6102 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6103 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6104 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6105 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6106 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6107 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6108 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6109 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6110 0x00000000, 0x00000000, 0x00000000,
6111};
6112
50da859d 6113static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 6114 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6115 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6116 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6117 0x00000000, 0x00000000, 0x00000000,
6118};
6119
50da859d 6120static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 6121 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6122 0x00000000, 0x00000000, 0x00000000,
6123};
6124
6125/* tp->lock is held. */
6126static int tg3_load_tso_firmware(struct tg3 *tp)
6127{
6128 struct fw_info info;
6129 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6130 int err, i;
6131
6132 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6133 return 0;
6134
6135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6136 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6137 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6138 info.text_data = &tg3Tso5FwText[0];
6139 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6140 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6141 info.rodata_data = &tg3Tso5FwRodata[0];
6142 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6143 info.data_len = TG3_TSO5_FW_DATA_LEN;
6144 info.data_data = &tg3Tso5FwData[0];
6145 cpu_base = RX_CPU_BASE;
6146 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6147 cpu_scratch_size = (info.text_len +
6148 info.rodata_len +
6149 info.data_len +
6150 TG3_TSO5_FW_SBSS_LEN +
6151 TG3_TSO5_FW_BSS_LEN);
6152 } else {
6153 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6154 info.text_len = TG3_TSO_FW_TEXT_LEN;
6155 info.text_data = &tg3TsoFwText[0];
6156 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6157 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6158 info.rodata_data = &tg3TsoFwRodata[0];
6159 info.data_base = TG3_TSO_FW_DATA_ADDR;
6160 info.data_len = TG3_TSO_FW_DATA_LEN;
6161 info.data_data = &tg3TsoFwData[0];
6162 cpu_base = TX_CPU_BASE;
6163 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6164 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6165 }
6166
6167 err = tg3_load_firmware_cpu(tp, cpu_base,
6168 cpu_scratch_base, cpu_scratch_size,
6169 &info);
6170 if (err)
6171 return err;
6172
6173 /* Now startup the cpu. */
6174 tw32(cpu_base + CPU_STATE, 0xffffffff);
6175 tw32_f(cpu_base + CPU_PC, info.text_base);
6176
6177 for (i = 0; i < 5; i++) {
6178 if (tr32(cpu_base + CPU_PC) == info.text_base)
6179 break;
6180 tw32(cpu_base + CPU_STATE, 0xffffffff);
6181 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6182 tw32_f(cpu_base + CPU_PC, info.text_base);
6183 udelay(1000);
6184 }
6185 if (i >= 5) {
6186 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6187 "to set CPU PC, is %08x should be %08x\n",
6188 tp->dev->name, tr32(cpu_base + CPU_PC),
6189 info.text_base);
6190 return -ENODEV;
6191 }
6192 tw32(cpu_base + CPU_STATE, 0xffffffff);
6193 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6194 return 0;
6195}
6196
1da177e4
LT		 6197
6198/* tp->lock is held. */
986e0aeb 6199static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
1da177e4
LT		 6200{
6201 u32 addr_high, addr_low;
6202 int i;
6203
6204 addr_high = ((tp->dev->dev_addr[0] << 8) |
6205 tp->dev->dev_addr[1]);
6206 addr_low = ((tp->dev->dev_addr[2] << 24) |
6207 (tp->dev->dev_addr[3] << 16) |
6208 (tp->dev->dev_addr[4] << 8) |
6209 (tp->dev->dev_addr[5] << 0));
6210 for (i = 0; i < 4; i++) {
986e0aeb
MC		 6211 if (i == 1 && skip_mac_1)
6212 continue;
1da177e4
LT		 6213 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6214 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6215 }
6216
6217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6219 for (i = 0; i < 12; i++) {
6220 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6221 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6222 }
6223 }
6224
6225 addr_high = (tp->dev->dev_addr[0] +
6226 tp->dev->dev_addr[1] +
6227 tp->dev->dev_addr[2] +
6228 tp->dev->dev_addr[3] +
6229 tp->dev->dev_addr[4] +
6230 tp->dev->dev_addr[5]) &
6231 TX_BACKOFF_SEED_MASK;
6232 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6233}
6234
6235static int tg3_set_mac_addr(struct net_device *dev, void *p)
6236{
6237 struct tg3 *tp = netdev_priv(dev);
6238 struct sockaddr *addr = p;
986e0aeb 6239 int err = 0, skip_mac_1 = 0;
1da177e4 6240
f9804ddb
MC		 6241 if (!is_valid_ether_addr(addr->sa_data))
6242 return -EINVAL;
6243
1da177e4
LT		 6244 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6245
e75f7c90
MC		 6246 if (!netif_running(dev))
6247 return 0;
6248
58712ef9 6249 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6250 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6251
986e0aeb
MC		 6252 addr0_high = tr32(MAC_ADDR_0_HIGH);
6253 addr0_low = tr32(MAC_ADDR_0_LOW);
6254 addr1_high = tr32(MAC_ADDR_1_HIGH);
6255 addr1_low = tr32(MAC_ADDR_1_LOW);
6256
6257 /* Skip MAC addr 1 if ASF is using it. */
6258 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6259 !(addr1_high == 0 && addr1_low == 0))
6260 skip_mac_1 = 1;
58712ef9 6261 }
986e0aeb
MC		 6262 spin_lock_bh(&tp->lock);
6263 __tg3_set_mac_addr(tp, skip_mac_1);
6264 spin_unlock_bh(&tp->lock);
1da177e4 6265
b9ec6c1b 6266 return err;
1da177e4
LT		 6267}
6268
6269/* tp->lock is held. */
6270static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6271 dma_addr_t mapping, u32 maxlen_flags,
6272 u32 nic_addr)
6273{
6274 tg3_write_mem(tp,
6275 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6276 ((u64) mapping >> 32));
6277 tg3_write_mem(tp,
6278 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6279 ((u64) mapping & 0xffffffff));
6280 tg3_write_mem(tp,
6281 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6282 maxlen_flags);
6283
6284 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6285 tg3_write_mem(tp,
6286 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6287 nic_addr);
6288}
6289
6290static void __tg3_set_rx_mode(struct net_device *);
d244c892 6291static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6292{
6293 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6294 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6295 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6296 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6297 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6298 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6299 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6300 }
6301 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6302 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6303 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6304 u32 val = ec->stats_block_coalesce_usecs;
6305
6306 if (!netif_carrier_ok(tp->dev))
6307 val = 0;
6308
6309 tw32(HOSTCC_STAT_COAL_TICKS, val);
6310 }
6311}
1da177e4
LT		 6312
6313/* tp->lock is held. */
8e7a22e3 6314static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6315{
6316 u32 val, rdmac_mode;
6317 int i, err, limit;
6318
6319 tg3_disable_ints(tp);
6320
6321 tg3_stop_fw(tp);
6322
6323 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6324
6325 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6326 tg3_abort_hw(tp, 1);
1da177e4
LT		 6327 }
6328
36da4d86 6329 if (reset_phy)
d4d2c558
MC		 6330 tg3_phy_reset(tp);
6331
1da177e4
LT		 6332 err = tg3_chip_reset(tp);
6333 if (err)
6334 return err;
6335
6336 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6337
d30cdd28
MC		 6338 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
6339 val = tr32(TG3_CPMU_CTRL);
6340 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6341 tw32(TG3_CPMU_CTRL, val);
6342 }
6343
1da177e4
LT		 6344 /* This works around an issue with Athlon chipsets on
6345 * B3 tigon3 silicon. This bit has no effect on any
6346 * other revision. But do not set this on PCI Express
795d01c5 6347 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6348 */
795d01c5
MC		 6349 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6350 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6351 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6352 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6353 }
1da177e4
LT		 6354
6355 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6356 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6357 val = tr32(TG3PCI_PCISTATE);
6358 val |= PCISTATE_RETRY_SAME_DMA;
6359 tw32(TG3PCI_PCISTATE, val);
6360 }
6361
0d3031d9
MC		 6362 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6363 /* Allow reads and writes to the
6364 * APE register and memory space.
6365 */
6366 val = tr32(TG3PCI_PCISTATE);
6367 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6368 PCISTATE_ALLOW_APE_SHMEM_WR;
6369 tw32(TG3PCI_PCISTATE, val);
6370 }
6371
1da177e4
LT		 6372 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6373 /* Enable some hw fixes. */
6374 val = tr32(TG3PCI_MSI_DATA);
6375 val |= (1 << 26) | (1 << 28) | (1 << 29);
6376 tw32(TG3PCI_MSI_DATA, val);
6377 }
6378
6379 /* Descriptor ring init may make accesses to the
6380 * NIC SRAM area to setup the TX descriptors, so we
6381 * can only do this after the hardware has been
6382 * successfully reset.
6383 */
32d8c572
MC		 6384 err = tg3_init_rings(tp);
6385 if (err)
6386 return err;
1da177e4 6387
9936bcf6
MC		 6388 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6389 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6390 /* This value is determined during the probe time DMA
6391 * engine test, tg3_test_dma.
6392 */
6393 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6394 }
1da177e4
LT		 6395
6396 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6397 GRC_MODE_4X_NIC_SEND_RINGS |
6398 GRC_MODE_NO_TX_PHDR_CSUM |
6399 GRC_MODE_NO_RX_PHDR_CSUM);
6400 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6401
6402 /* Pseudo-header checksum is done by hardware logic and not
6403 * the offload processers, so make the chip do the pseudo-
6404 * header checksums on receive. For transmit it is more
6405 * convenient to do the pseudo-header checksum in software
6406 * as Linux does that on transmit for us in all cases.
6407 */
6408 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6409
6410 tw32(GRC_MODE,
6411 tp->grc_mode |
6412 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6413
6414 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6415 val = tr32(GRC_MISC_CFG);
6416 val &= ~0xff;
6417 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6418 tw32(GRC_MISC_CFG, val);
6419
6420 /* Initialize MBUF/DESC pool. */
cbf46853 6421 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6422 /* Do nothing. */
6423 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6424 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6425 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6426 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6427 else
6428 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6429 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6430 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6431 }
1da177e4
LT		 6432 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6433 int fw_len;
6434
6435 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6436 TG3_TSO5_FW_RODATA_LEN +
6437 TG3_TSO5_FW_DATA_LEN +
6438 TG3_TSO5_FW_SBSS_LEN +
6439 TG3_TSO5_FW_BSS_LEN);
6440 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6441 tw32(BUFMGR_MB_POOL_ADDR,
6442 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6443 tw32(BUFMGR_MB_POOL_SIZE,
6444 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6445 }
1da177e4 6446
0f893dc6 6447 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6448 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6449 tp->bufmgr_config.mbuf_read_dma_low_water);
6450 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6451 tp->bufmgr_config.mbuf_mac_rx_low_water);
6452 tw32(BUFMGR_MB_HIGH_WATER,
6453 tp->bufmgr_config.mbuf_high_water);
6454 } else {
6455 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6456 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6457 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6458 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6459 tw32(BUFMGR_MB_HIGH_WATER,
6460 tp->bufmgr_config.mbuf_high_water_jumbo);
6461 }
6462 tw32(BUFMGR_DMA_LOW_WATER,
6463 tp->bufmgr_config.dma_low_water);
6464 tw32(BUFMGR_DMA_HIGH_WATER,
6465 tp->bufmgr_config.dma_high_water);
6466
6467 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6468 for (i = 0; i < 2000; i++) {
6469 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6470 break;
6471 udelay(10);
6472 }
6473 if (i >= 2000) {
6474 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6475 tp->dev->name);
6476 return -ENODEV;
6477 }
6478
6479 /* Setup replenish threshold. */
f92905de
MC		 6480 val = tp->rx_pending / 8;
6481 if (val == 0)
6482 val = 1;
6483 else if (val > tp->rx_std_max_post)
6484 val = tp->rx_std_max_post;
b5d3772c
MC		 6485 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6486 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6487 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6488
6489 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6490 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6491 }
f92905de
MC		 6492
6493 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6494
6495 /* Initialize TG3_BDINFO's at:
6496 * RCVDBDI_STD_BD: standard eth size rx ring
6497 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6498 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6499 *
6500 * like so:
6501 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6502 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6503 * ring attribute flags
6504 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6505 *
6506 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6507 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6508 *
6509 * The size of each ring is fixed in the firmware, but the location is
6510 * configurable.
6511 */
6512 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6513 ((u64) tp->rx_std_mapping >> 32));
6514 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6515 ((u64) tp->rx_std_mapping & 0xffffffff));
6516 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6517 NIC_SRAM_RX_BUFFER_DESC);
6518
6519 /* Don't even try to program the JUMBO/MINI buffer descriptor
6520 * configs on 5705.
6521 */
6522 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6523 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6524 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6525 } else {
6526 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6527 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6528
6529 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6530 BDINFO_FLAGS_DISABLED);
6531
6532 /* Setup replenish threshold. */
6533 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6534
0f893dc6 6535 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6536 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6537 ((u64) tp->rx_jumbo_mapping >> 32));
6538 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6539 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6540 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6541 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6542 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6543 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6544 } else {
6545 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6546 BDINFO_FLAGS_DISABLED);
6547 }
6548
6549 }
6550
6551 /* There is only one send ring on 5705/5750, no need to explicitly
6552 * disable the others.
6553 */
6554 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6555 /* Clear out send RCB ring in SRAM. */
6556 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6557 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6558 BDINFO_FLAGS_DISABLED);
6559 }
6560
6561 tp->tx_prod = 0;
6562 tp->tx_cons = 0;
6563 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6564 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6565
6566 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6567 tp->tx_desc_mapping,
6568 (TG3_TX_RING_SIZE <<
6569 BDINFO_FLAGS_MAXLEN_SHIFT),
6570 NIC_SRAM_TX_BUFFER_DESC);
6571
6572 /* There is only one receive return ring on 5705/5750, no need
6573 * to explicitly disable the others.
6574 */
6575 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6576 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6577 i += TG3_BDINFO_SIZE) {
6578 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6579 BDINFO_FLAGS_DISABLED);
6580 }
6581 }
6582
6583 tp->rx_rcb_ptr = 0;
6584 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6585
6586 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6587 tp->rx_rcb_mapping,
6588 (TG3_RX_RCB_RING_SIZE(tp) <<
6589 BDINFO_FLAGS_MAXLEN_SHIFT),
6590 0);
6591
6592 tp->rx_std_ptr = tp->rx_pending;
6593 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6594 tp->rx_std_ptr);
6595
0f893dc6 6596 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6597 tp->rx_jumbo_pending : 0;
6598 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6599 tp->rx_jumbo_ptr);
6600
6601 /* Initialize MAC address and backoff seed. */
986e0aeb 6602 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6603
6604 /* MTU + ethernet header + FCS + optional VLAN tag */
6605 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6606
6607 /* The slot time is changed by tg3_setup_phy if we
6608 * run at gigabit with half duplex.
6609 */
6610 tw32(MAC_TX_LENGTHS,
6611 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6612 (6 << TX_LENGTHS_IPG_SHIFT) |
6613 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6614
6615 /* Receive rules. */
6616 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6617 tw32(RCVLPC_CONFIG, 0x0181);
6618
6619 /* Calculate RDMAC_MODE setting early, we need it to determine
6620 * the RCVLPC_STATE_ENABLE mask.
6621 */
6622 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6623 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6624 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6625 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6626 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6627
d30cdd28
MC		 6628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
6629 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6630 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6631 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6632
85e94ced
MC		 6633 /* If statement applies to 5705 and 5750 PCI devices only */
6634 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6635 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6636 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 6637 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 6638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6639 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6640 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6641 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6642 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6643 }
6644 }
6645
85e94ced
MC		 6646 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6647 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6648
1da177e4
LT		 6649 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6650 rdmac_mode |= (1 << 27);
1da177e4
LT		 6651
6652 /* Receive/send statistics. */
1661394e
MC		 6653 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6654 val = tr32(RCVLPC_STATS_ENABLE);
6655 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6656 tw32(RCVLPC_STATS_ENABLE, val);
6657 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6658 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6659 val = tr32(RCVLPC_STATS_ENABLE);
6660 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6661 tw32(RCVLPC_STATS_ENABLE, val);
6662 } else {
6663 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6664 }
6665 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6666 tw32(SNDDATAI_STATSENAB, 0xffffff);
6667 tw32(SNDDATAI_STATSCTRL,
6668 (SNDDATAI_SCTRL_ENABLE |
6669 SNDDATAI_SCTRL_FASTUPD));
6670
6671 /* Setup host coalescing engine. */
6672 tw32(HOSTCC_MODE, 0);
6673 for (i = 0; i < 2000; i++) {
6674 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6675 break;
6676 udelay(10);
6677 }
6678
d244c892 6679 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6680
6681 /* set status block DMA address */
6682 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6683 ((u64) tp->status_mapping >> 32));
6684 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6685 ((u64) tp->status_mapping & 0xffffffff));
6686
6687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6688 /* Status/statistics block address. See tg3_timer,
6689 * the tg3_periodic_fetch_stats call there, and
6690 * tg3_get_stats to see how this works for 5705/5750 chips.
6691 */
1da177e4
LT		 6692 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6693 ((u64) tp->stats_mapping >> 32));
6694 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6695 ((u64) tp->stats_mapping & 0xffffffff));
6696 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6697 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6698 }
6699
6700 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6701
6702 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6703 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6704 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6705 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6706
6707 /* Clear statistics/status block in chip, and status block in ram. */
6708 for (i = NIC_SRAM_STATS_BLK;
6709 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6710 i += sizeof(u32)) {
6711 tg3_write_mem(tp, i, 0);
6712 udelay(40);
6713 }
6714 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6715
c94e3941
MC		 6716 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6717 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6718 /* reset to prevent losing 1st rx packet intermittently */
6719 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6720 udelay(10);
6721 }
6722
1da177e4
LT		 6723 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6724 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 6725 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6726 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6727 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6728 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 6729 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6730 udelay(40);
6731
314fba34 6732 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6733 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6734 * register to preserve the GPIO settings for LOMs. The GPIOs,
6735 * whether used as inputs or outputs, are set by boot code after
6736 * reset.
6737 */
9d26e213 6738 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6739 u32 gpio_mask;
6740
9d26e213
MC		 6741 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6742 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6743 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6744
6745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6746 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6747 GRC_LCLCTRL_GPIO_OUTPUT3;
6748
af36e6b6
MC		 6749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6750 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6751
aaf84465 6752 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 6753 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6754
6755 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6756 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6757 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6758 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6759 }
1da177e4
LT		 6760 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6761 udelay(100);
6762
09ee929c 6763 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6764 tp->last_tag = 0;
1da177e4
LT		 6765
6766 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6767 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6768 udelay(40);
6769 }
6770
6771 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6772 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6773 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6774 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6775 WDMAC_MODE_LNGREAD_ENAB);
6776
85e94ced
MC		 6777 /* If statement applies to 5705 and 5750 PCI devices only */
6778 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6779 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6780 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6781 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6782 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6783 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6784 /* nothing */
6785 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6786 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6787 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6788 val |= WDMAC_MODE_RX_ACCEL;
6789 }
6790 }
6791
d9ab5ad1 6792 /* Enable host coalescing bug fix */
af36e6b6 6793 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
d30cdd28 6794 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
9936bcf6
MC		 6795 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
6796 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
d9ab5ad1
MC		 6797 val |= (1 << 29);
6798
1da177e4
LT		 6799 tw32_f(WDMAC_MODE, val);
6800 udelay(40);
6801
9974a356
MC		 6802 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6803 u16 pcix_cmd;
6804
6805 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6806 &pcix_cmd);
1da177e4 6807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 6808 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
6809 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 6810 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 6811 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
6812 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 6813 }
9974a356
MC		 6814 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6815 pcix_cmd);
1da177e4
LT		 6816 }
6817
6818 tw32_f(RDMAC_MODE, rdmac_mode);
6819 udelay(40);
6820
6821 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6822 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6823 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 6824
6825 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
6826 tw32(SNDDATAC_MODE,
6827 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
6828 else
6829 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6830
1da177e4
LT		 6831 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6832 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6833 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6834 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6835 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6836 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6837 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6838 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6839
6840 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6841 err = tg3_load_5701_a0_firmware_fix(tp);
6842 if (err)
6843 return err;
6844 }
6845
1da177e4
LT		 6846 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6847 err = tg3_load_tso_firmware(tp);
6848 if (err)
6849 return err;
6850 }
1da177e4
LT		 6851
6852 tp->tx_mode = TX_MODE_ENABLE;
6853 tw32_f(MAC_TX_MODE, tp->tx_mode);
6854 udelay(100);
6855
6856 tp->rx_mode = RX_MODE_ENABLE;
9936bcf6
MC		 6857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
6858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
af36e6b6
MC		 6859 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6860
1da177e4
LT		 6861 tw32_f(MAC_RX_MODE, tp->rx_mode);
6862 udelay(10);
6863
6864 if (tp->link_config.phy_is_low_power) {
6865 tp->link_config.phy_is_low_power = 0;
6866 tp->link_config.speed = tp->link_config.orig_speed;
6867 tp->link_config.duplex = tp->link_config.orig_duplex;
6868 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6869 }
6870
6871 tp->mi_mode = MAC_MI_MODE_BASE;
6872 tw32_f(MAC_MI_MODE, tp->mi_mode);
6873 udelay(80);
6874
6875 tw32(MAC_LED_CTRL, tp->led_ctrl);
6876
6877 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6878 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6879 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6880 udelay(10);
6881 }
6882 tw32_f(MAC_RX_MODE, tp->rx_mode);
6883 udelay(10);
6884
6885 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6886 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6887 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6888 /* Set drive transmission level to 1.2V */
6889 /* only if the signal pre-emphasis bit is not set */
6890 val = tr32(MAC_SERDES_CFG);
6891 val &= 0xfffff000;
6892 val |= 0x880;
6893 tw32(MAC_SERDES_CFG, val);
6894 }
6895 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6896 tw32(MAC_SERDES_CFG, 0x616000);
6897 }
6898
6899 /* Prevent chip from dropping frames when flow control
6900 * is enabled.
6901 */
6902 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6903
6904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6905 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6906 /* Use hardware link auto-negotiation */
6907 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6908 }
6909
d4d2c558
MC		 6910 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6911 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6912 u32 tmp;
6913
6914 tmp = tr32(SERDES_RX_CTRL);
6915 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6916 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6917 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6918 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6919 }
6920
36da4d86 6921 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6922 if (err)
6923 return err;
6924
715116a1
MC		 6925 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6926 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6927 u32 tmp;
6928
6929 /* Clear CRC stats. */
569a5df8
MC		 6930 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6931 tg3_writephy(tp, MII_TG3_TEST1,
6932 tmp | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 6933 tg3_readphy(tp, 0x14, &tmp);
6934 }
6935 }
6936
6937 __tg3_set_rx_mode(tp->dev);
6938
6939 /* Initialize receive rules. */
6940 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6941 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6942 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6943 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6944
4cf78e4f 6945 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6946 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6947 limit = 8;
6948 else
6949 limit = 16;
6950 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6951 limit -= 4;
6952 switch (limit) {
6953 case 16:
6954 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6955 case 15:
6956 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6957 case 14:
6958 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6959 case 13:
6960 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6961 case 12:
6962 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6963 case 11:
6964 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6965 case 10:
6966 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6967 case 9:
6968 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6969 case 8:
6970 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6971 case 7:
6972 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6973 case 6:
6974 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6975 case 5:
6976 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6977 case 4:
6978 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6979 case 3:
6980 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6981 case 2:
6982 case 1:
6983
6984 default:
6985 break;
6986 };
6987
9ce768ea
MC		 6988 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6989 /* Write our heartbeat update interval to APE. */
6990 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
6991 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 6992
1da177e4
LT		 6993 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6994
1da177e4
LT		 6995 return 0;
6996}
6997
6998/* Called at device open time to get the chip ready for
6999 * packet processing. Invoked with tp->lock held.
7000 */
8e7a22e3 7001static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7002{
7003 int err;
7004
7005 /* Force the chip into D0. */
bc1c7567 7006 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 7007 if (err)
7008 goto out;
7009
7010 tg3_switch_clocks(tp);
7011
7012 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7013
8e7a22e3 7014 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7015
7016out:
7017 return err;
7018}
7019
7020#define TG3_STAT_ADD32(PSTAT, REG) \
7021do { u32 __val = tr32(REG); \
7022 (PSTAT)->low += __val; \
7023 if ((PSTAT)->low < __val) \
7024 (PSTAT)->high += 1; \
7025} while (0)
7026
7027static void tg3_periodic_fetch_stats(struct tg3 *tp)
7028{
7029 struct tg3_hw_stats *sp = tp->hw_stats;
7030
7031 if (!netif_carrier_ok(tp->dev))
7032 return;
7033
7034 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7035 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7036 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7037 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7038 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7039 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7040 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7041 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7042 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7043 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7044 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7045 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7046 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7047
7048 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7049 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7050 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7051 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7052 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7053 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7054 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7055 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7056 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7057 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7058 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7059 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7060 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7061 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7062
7063 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7064 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7065 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7066}
7067
7068static void tg3_timer(unsigned long __opaque)
7069{
7070 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7071
f475f163
MC		 7072 if (tp->irq_sync)
7073 goto restart_timer;
7074
f47c11ee 7075 spin_lock(&tp->lock);
1da177e4 7076
fac9b83e
DM		 7077 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7078 /* All of this garbage is because when using non-tagged
7079 * IRQ status the mailbox/status_block protocol the chip
7080 * uses with the cpu is race prone.
7081 */
7082 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7083 tw32(GRC_LOCAL_CTRL,
7084 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7085 } else {
7086 tw32(HOSTCC_MODE, tp->coalesce_mode |
7087 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7088 }
1da177e4 7089
fac9b83e
DM		 7090 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7091 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7092 spin_unlock(&tp->lock);
fac9b83e
DM		 7093 schedule_work(&tp->reset_task);
7094 return;
7095 }
1da177e4
LT		 7096 }
7097
1da177e4
LT		 7098 /* This part only runs once per second. */
7099 if (!--tp->timer_counter) {
fac9b83e
DM		 7100 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7101 tg3_periodic_fetch_stats(tp);
7102
1da177e4
LT		 7103 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7104 u32 mac_stat;
7105 int phy_event;
7106
7107 mac_stat = tr32(MAC_STATUS);
7108
7109 phy_event = 0;
7110 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7111 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7112 phy_event = 1;
7113 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7114 phy_event = 1;
7115
7116 if (phy_event)
7117 tg3_setup_phy(tp, 0);
7118 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7119 u32 mac_stat = tr32(MAC_STATUS);
7120 int need_setup = 0;
7121
7122 if (netif_carrier_ok(tp->dev) &&
7123 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7124 need_setup = 1;
7125 }
7126 if (! netif_carrier_ok(tp->dev) &&
7127 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7128 MAC_STATUS_SIGNAL_DET))) {
7129 need_setup = 1;
7130 }
7131 if (need_setup) {
3d3ebe74
MC		 7132 if (!tp->serdes_counter) {
7133 tw32_f(MAC_MODE,
7134 (tp->mac_mode &
7135 ~MAC_MODE_PORT_MODE_MASK));
7136 udelay(40);
7137 tw32_f(MAC_MODE, tp->mac_mode);
7138 udelay(40);
7139 }
1da177e4
LT		 7140 tg3_setup_phy(tp, 0);
7141 }
747e8f8b
MC		 7142 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7143 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7144
7145 tp->timer_counter = tp->timer_multiplier;
7146 }
7147
130b8e4d
MC		 7148 /* Heartbeat is only sent once every 2 seconds.
7149 *
7150 * The heartbeat is to tell the ASF firmware that the host
7151 * driver is still alive. In the event that the OS crashes,
7152 * ASF needs to reset the hardware to free up the FIFO space
7153 * that may be filled with rx packets destined for the host.
7154 * If the FIFO is full, ASF will no longer function properly.
7155 *
7156 * Unintended resets have been reported on real time kernels
7157 * where the timer doesn't run on time. Netpoll will also have
7158 * same problem.
7159 *
7160 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7161 * to check the ring condition when the heartbeat is expiring
7162 * before doing the reset. This will prevent most unintended
7163 * resets.
7164 */
1da177e4
LT		 7165 if (!--tp->asf_counter) {
7166 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7167 u32 val;
7168
bbadf503 7169 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7170 FWCMD_NICDRV_ALIVE3);
bbadf503 7171 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7172 /* 5 seconds timeout */
bbadf503 7173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 7174 val = tr32(GRC_RX_CPU_EVENT);
7175 val |= (1 << 14);
7176 tw32(GRC_RX_CPU_EVENT, val);
7177 }
7178 tp->asf_counter = tp->asf_multiplier;
7179 }
7180
f47c11ee 7181 spin_unlock(&tp->lock);
1da177e4 7182
f475f163 7183restart_timer:
1da177e4
LT		 7184 tp->timer.expires = jiffies + tp->timer_offset;
7185 add_timer(&tp->timer);
7186}
7187
81789ef5 7188static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7189{
7d12e780 7190 irq_handler_t fn;
fcfa0a32
MC		 7191 unsigned long flags;
7192 struct net_device *dev = tp->dev;
7193
7194 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7195 fn = tg3_msi;
7196 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7197 fn = tg3_msi_1shot;
1fb9df5d 7198 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7199 } else {
7200 fn = tg3_interrupt;
7201 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7202 fn = tg3_interrupt_tagged;
1fb9df5d 7203 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7204 }
7205 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7206}
7207
7938109f
MC		 7208static int tg3_test_interrupt(struct tg3 *tp)
7209{
7210 struct net_device *dev = tp->dev;
b16250e3 7211 int err, i, intr_ok = 0;
7938109f 7212
d4bc3927
MC		 7213 if (!netif_running(dev))
7214 return -ENODEV;
7215
7938109f
MC		 7216 tg3_disable_ints(tp);
7217
7218 free_irq(tp->pdev->irq, dev);
7219
7220 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7221 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7222 if (err)
7223 return err;
7224
38f3843e 7225 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7226 tg3_enable_ints(tp);
7227
7228 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7229 HOSTCC_MODE_NOW);
7230
7231 for (i = 0; i < 5; i++) {
b16250e3
MC		 7232 u32 int_mbox, misc_host_ctrl;
7233
09ee929c
MC		 7234 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7235 TG3_64BIT_REG_LOW);
b16250e3
MC		 7236 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7237
7238 if ((int_mbox != 0) ||
7239 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7240 intr_ok = 1;
7938109f 7241 break;
b16250e3
MC		 7242 }
7243
7938109f
MC		 7244 msleep(10);
7245 }
7246
7247 tg3_disable_ints(tp);
7248
7249 free_irq(tp->pdev->irq, dev);
6aa20a22 7250
fcfa0a32 7251 err = tg3_request_irq(tp);
7938109f
MC		 7252
7253 if (err)
7254 return err;
7255
b16250e3 7256 if (intr_ok)
7938109f
MC		 7257 return 0;
7258
7259 return -EIO;
7260}
7261
7262/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7263 * successfully restored
7264 */
7265static int tg3_test_msi(struct tg3 *tp)
7266{
7267 struct net_device *dev = tp->dev;
7268 int err;
7269 u16 pci_cmd;
7270
7271 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7272 return 0;
7273
7274 /* Turn off SERR reporting in case MSI terminates with Master
7275 * Abort.
7276 */
7277 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7278 pci_write_config_word(tp->pdev, PCI_COMMAND,
7279 pci_cmd & ~PCI_COMMAND_SERR);
7280
7281 err = tg3_test_interrupt(tp);
7282
7283 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7284
7285 if (!err)
7286 return 0;
7287
7288 /* other failures */
7289 if (err != -EIO)
7290 return err;
7291
7292 /* MSI test failed, go back to INTx mode */
7293 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7294 "switching to INTx mode. Please report this failure to "
7295 "the PCI maintainer and include system chipset information.\n",
7296 tp->dev->name);
7297
7298 free_irq(tp->pdev->irq, dev);
7299 pci_disable_msi(tp->pdev);
7300
7301 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7302
fcfa0a32 7303 err = tg3_request_irq(tp);
7938109f
MC		 7304 if (err)
7305 return err;
7306
7307 /* Need to reset the chip because the MSI cycle may have terminated
7308 * with Master Abort.
7309 */
f47c11ee 7310 tg3_full_lock(tp, 1);
7938109f 7311
944d980e 7312 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7313 err = tg3_init_hw(tp, 1);
7938109f 7314
f47c11ee 7315 tg3_full_unlock(tp);
7938109f
MC		 7316
7317 if (err)
7318 free_irq(tp->pdev->irq, dev);
7319
7320 return err;
7321}
7322
1da177e4
LT		 7323static int tg3_open(struct net_device *dev)
7324{
7325 struct tg3 *tp = netdev_priv(dev);
7326 int err;
7327
c49a1561
MC		 7328 netif_carrier_off(tp->dev);
7329
f47c11ee 7330 tg3_full_lock(tp, 0);
1da177e4 7331
bc1c7567 7332 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 7333 if (err) {
7334 tg3_full_unlock(tp);
bc1c7567 7335 return err;
12862086 7336 }
bc1c7567 7337
1da177e4
LT		 7338 tg3_disable_ints(tp);
7339 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7340
f47c11ee 7341 tg3_full_unlock(tp);
1da177e4
LT		 7342
7343 /* The placement of this call is tied
7344 * to the setup and use of Host TX descriptors.
7345 */
7346 err = tg3_alloc_consistent(tp);
7347 if (err)
7348 return err;
7349
7544b097 7350 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7351 /* All MSI supporting chips should support tagged
7352 * status. Assert that this is the case.
7353 */
7354 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7355 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7356 "Not using MSI.\n", tp->dev->name);
7357 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7358 u32 msi_mode;
7359
2fbe43f6
MC		 7360 /* Hardware bug - MSI won't work if INTX disabled. */
7361 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7362 pci_intx(tp->pdev, 1);
7363
88b06bc2
MC		 7364 msi_mode = tr32(MSGINT_MODE);
7365 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7366 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7367 }
7368 }
fcfa0a32 7369 err = tg3_request_irq(tp);
1da177e4
LT		 7370
7371 if (err) {
88b06bc2
MC		 7372 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7373 pci_disable_msi(tp->pdev);
7374 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7375 }
1da177e4
LT		 7376 tg3_free_consistent(tp);
7377 return err;
7378 }
7379
bea3348e
SH		 7380 napi_enable(&tp->napi);
7381
f47c11ee 7382 tg3_full_lock(tp, 0);
1da177e4 7383
8e7a22e3 7384 err = tg3_init_hw(tp, 1);
1da177e4 7385 if (err) {
944d980e 7386 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7387 tg3_free_rings(tp);
7388 } else {
fac9b83e
DM		 7389 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7390 tp->timer_offset = HZ;
7391 else
7392 tp->timer_offset = HZ / 10;
7393
7394 BUG_ON(tp->timer_offset > HZ);
7395 tp->timer_counter = tp->timer_multiplier =
7396 (HZ / tp->timer_offset);
7397 tp->asf_counter = tp->asf_multiplier =
28fbef78 7398 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7399
7400 init_timer(&tp->timer);
7401 tp->timer.expires = jiffies + tp->timer_offset;
7402 tp->timer.data = (unsigned long) tp;
7403 tp->timer.function = tg3_timer;
1da177e4
LT		 7404 }
7405
f47c11ee 7406 tg3_full_unlock(tp);
1da177e4
LT		 7407
7408 if (err) {
bea3348e 7409 napi_disable(&tp->napi);
88b06bc2
MC		 7410 free_irq(tp->pdev->irq, dev);
7411 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7412 pci_disable_msi(tp->pdev);
7413 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7414 }
1da177e4
LT		 7415 tg3_free_consistent(tp);
7416 return err;
7417 }
7418
7938109f
MC		 7419 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7420 err = tg3_test_msi(tp);
fac9b83e 7421
7938109f 7422 if (err) {
f47c11ee 7423 tg3_full_lock(tp, 0);
7938109f
MC		 7424
7425 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7426 pci_disable_msi(tp->pdev);
7427 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7428 }
944d980e 7429 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7430 tg3_free_rings(tp);
7431 tg3_free_consistent(tp);
7432
f47c11ee 7433 tg3_full_unlock(tp);
7938109f 7434
bea3348e
SH		 7435 napi_disable(&tp->napi);
7436
7938109f
MC		 7437 return err;
7438 }
fcfa0a32
MC		 7439
7440 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7441 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7442 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7443
b5d3772c
MC		 7444 tw32(PCIE_TRANSACTION_CFG,
7445 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7446 }
7447 }
7938109f
MC		 7448 }
7449
f47c11ee 7450 tg3_full_lock(tp, 0);
1da177e4 7451
7938109f
MC		 7452 add_timer(&tp->timer);
7453 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7454 tg3_enable_ints(tp);
7455
f47c11ee 7456 tg3_full_unlock(tp);
1da177e4
LT		 7457
7458 netif_start_queue(dev);
7459
7460 return 0;
7461}
7462
7463#if 0
7464/*static*/ void tg3_dump_state(struct tg3 *tp)
7465{
7466 u32 val32, val32_2, val32_3, val32_4, val32_5;
7467 u16 val16;
7468 int i;
7469
7470 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7471 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7472 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7473 val16, val32);
7474
7475 /* MAC block */
7476 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7477 tr32(MAC_MODE), tr32(MAC_STATUS));
7478 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7479 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7480 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7481 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7482 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7483 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7484
7485 /* Send data initiator control block */
7486 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7487 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7488 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7489 tr32(SNDDATAI_STATSCTRL));
7490
7491 /* Send data completion control block */
7492 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7493
7494 /* Send BD ring selector block */
7495 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7496 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7497
7498 /* Send BD initiator control block */
7499 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7500 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7501
7502 /* Send BD completion control block */
7503 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7504
7505 /* Receive list placement control block */
7506 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7507 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7508 printk(" RCVLPC_STATSCTRL[%08x]\n",
7509 tr32(RCVLPC_STATSCTRL));
7510
7511 /* Receive data and receive BD initiator control block */
7512 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7513 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7514
7515 /* Receive data completion control block */
7516 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7517 tr32(RCVDCC_MODE));
7518
7519 /* Receive BD initiator control block */
7520 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7521 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7522
7523 /* Receive BD completion control block */
7524 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7525 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7526
7527 /* Receive list selector control block */
7528 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7529 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7530
7531 /* Mbuf cluster free block */
7532 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7533 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7534
7535 /* Host coalescing control block */
7536 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7537 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7538 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7539 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7540 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7541 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7542 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7543 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7544 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7545 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7546 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7547 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7548
7549 /* Memory arbiter control block */
7550 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7551 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7552
7553 /* Buffer manager control block */
7554 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7555 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7556 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7557 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7558 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7559 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7560 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7561 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7562
7563 /* Read DMA control block */
7564 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7565 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7566
7567 /* Write DMA control block */
7568 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7569 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7570
7571 /* DMA completion block */
7572 printk("DEBUG: DMAC_MODE[%08x]\n",
7573 tr32(DMAC_MODE));
7574
7575 /* GRC block */
7576 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7577 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7578 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7579 tr32(GRC_LOCAL_CTRL));
7580
7581 /* TG3_BDINFOs */
7582 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7583 tr32(RCVDBDI_JUMBO_BD + 0x0),
7584 tr32(RCVDBDI_JUMBO_BD + 0x4),
7585 tr32(RCVDBDI_JUMBO_BD + 0x8),
7586 tr32(RCVDBDI_JUMBO_BD + 0xc));
7587 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7588 tr32(RCVDBDI_STD_BD + 0x0),
7589 tr32(RCVDBDI_STD_BD + 0x4),
7590 tr32(RCVDBDI_STD_BD + 0x8),
7591 tr32(RCVDBDI_STD_BD + 0xc));
7592 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7593 tr32(RCVDBDI_MINI_BD + 0x0),
7594 tr32(RCVDBDI_MINI_BD + 0x4),
7595 tr32(RCVDBDI_MINI_BD + 0x8),
7596 tr32(RCVDBDI_MINI_BD + 0xc));
7597
7598 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7599 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7600 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7601 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7602 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7603 val32, val32_2, val32_3, val32_4);
7604
7605 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7606 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7607 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7608 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7609 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7610 val32, val32_2, val32_3, val32_4);
7611
7612 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7613 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7614 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7615 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7616 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7617 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7618 val32, val32_2, val32_3, val32_4, val32_5);
7619
7620 /* SW status block */
7621 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7622 tp->hw_status->status,
7623 tp->hw_status->status_tag,
7624 tp->hw_status->rx_jumbo_consumer,
7625 tp->hw_status->rx_consumer,
7626 tp->hw_status->rx_mini_consumer,
7627 tp->hw_status->idx[0].rx_producer,
7628 tp->hw_status->idx[0].tx_consumer);
7629
7630 /* SW statistics block */
7631 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7632 ((u32 *)tp->hw_stats)[0],
7633 ((u32 *)tp->hw_stats)[1],
7634 ((u32 *)tp->hw_stats)[2],
7635 ((u32 *)tp->hw_stats)[3]);
7636
7637 /* Mailboxes */
7638 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7639 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7640 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7641 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7642 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7643
7644 /* NIC side send descriptors. */
7645 for (i = 0; i < 6; i++) {
7646 unsigned long txd;
7647
7648 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7649 + (i * sizeof(struct tg3_tx_buffer_desc));
7650 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7651 i,
7652 readl(txd + 0x0), readl(txd + 0x4),
7653 readl(txd + 0x8), readl(txd + 0xc));
7654 }
7655
7656 /* NIC side RX descriptors. */
7657 for (i = 0; i < 6; i++) {
7658 unsigned long rxd;
7659
7660 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7661 + (i * sizeof(struct tg3_rx_buffer_desc));
7662 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7663 i,
7664 readl(rxd + 0x0), readl(rxd + 0x4),
7665 readl(rxd + 0x8), readl(rxd + 0xc));
7666 rxd += (4 * sizeof(u32));
7667 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7668 i,
7669 readl(rxd + 0x0), readl(rxd + 0x4),
7670 readl(rxd + 0x8), readl(rxd + 0xc));
7671 }
7672
7673 for (i = 0; i < 6; i++) {
7674 unsigned long rxd;
7675
7676 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7677 + (i * sizeof(struct tg3_rx_buffer_desc));
7678 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7679 i,
7680 readl(rxd + 0x0), readl(rxd + 0x4),
7681 readl(rxd + 0x8), readl(rxd + 0xc));
7682 rxd += (4 * sizeof(u32));
7683 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7684 i,
7685 readl(rxd + 0x0), readl(rxd + 0x4),
7686 readl(rxd + 0x8), readl(rxd + 0xc));
7687 }
7688}
7689#endif
7690
7691static struct net_device_stats *tg3_get_stats(struct net_device *);
7692static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7693
7694static int tg3_close(struct net_device *dev)
7695{
7696 struct tg3 *tp = netdev_priv(dev);
7697
bea3348e 7698 napi_disable(&tp->napi);
28e53bdd 7699 cancel_work_sync(&tp->reset_task);
7faa006f 7700
1da177e4
LT		 7701 netif_stop_queue(dev);
7702
7703 del_timer_sync(&tp->timer);
7704
f47c11ee 7705 tg3_full_lock(tp, 1);
1da177e4
LT		 7706#if 0
7707 tg3_dump_state(tp);
7708#endif
7709
7710 tg3_disable_ints(tp);
7711
944d980e 7712 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 7713 tg3_free_rings(tp);
5cf64b8a 7714 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 7715
f47c11ee 7716 tg3_full_unlock(tp);
1da177e4 7717
88b06bc2
MC		 7718 free_irq(tp->pdev->irq, dev);
7719 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7720 pci_disable_msi(tp->pdev);
7721 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7722 }
1da177e4
LT		 7723
7724 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7725 sizeof(tp->net_stats_prev));
7726 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7727 sizeof(tp->estats_prev));
7728
7729 tg3_free_consistent(tp);
7730
bc1c7567
MC		 7731 tg3_set_power_state(tp, PCI_D3hot);
7732
7733 netif_carrier_off(tp->dev);
7734
1da177e4
LT		 7735 return 0;
7736}
7737
7738static inline unsigned long get_stat64(tg3_stat64_t *val)
7739{
7740 unsigned long ret;
7741
7742#if (BITS_PER_LONG == 32)
7743 ret = val->low;
7744#else
7745 ret = ((u64)val->high << 32) | ((u64)val->low);
7746#endif
7747 return ret;
7748}
7749
7750static unsigned long calc_crc_errors(struct tg3 *tp)
7751{
7752 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7753
7754 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7755 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7757 u32 val;
7758
f47c11ee 7759 spin_lock_bh(&tp->lock);
569a5df8
MC		 7760 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7761 tg3_writephy(tp, MII_TG3_TEST1,
7762 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7763 tg3_readphy(tp, 0x14, &val);
7764 } else
7765 val = 0;
f47c11ee 7766 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7767
7768 tp->phy_crc_errors += val;
7769
7770 return tp->phy_crc_errors;
7771 }
7772
7773 return get_stat64(&hw_stats->rx_fcs_errors);
7774}
7775
7776#define ESTAT_ADD(member) \
7777 estats->member = old_estats->member + \
7778 get_stat64(&hw_stats->member)
7779
7780static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7781{
7782 struct tg3_ethtool_stats *estats = &tp->estats;
7783 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7784 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7785
7786 if (!hw_stats)
7787 return old_estats;
7788
7789 ESTAT_ADD(rx_octets);
7790 ESTAT_ADD(rx_fragments);
7791 ESTAT_ADD(rx_ucast_packets);
7792 ESTAT_ADD(rx_mcast_packets);
7793 ESTAT_ADD(rx_bcast_packets);
7794 ESTAT_ADD(rx_fcs_errors);
7795 ESTAT_ADD(rx_align_errors);
7796 ESTAT_ADD(rx_xon_pause_rcvd);
7797 ESTAT_ADD(rx_xoff_pause_rcvd);
7798 ESTAT_ADD(rx_mac_ctrl_rcvd);
7799 ESTAT_ADD(rx_xoff_entered);
7800 ESTAT_ADD(rx_frame_too_long_errors);
7801 ESTAT_ADD(rx_jabbers);
7802 ESTAT_ADD(rx_undersize_packets);
7803 ESTAT_ADD(rx_in_length_errors);
7804 ESTAT_ADD(rx_out_length_errors);
7805 ESTAT_ADD(rx_64_or_less_octet_packets);
7806 ESTAT_ADD(rx_65_to_127_octet_packets);
7807 ESTAT_ADD(rx_128_to_255_octet_packets);
7808 ESTAT_ADD(rx_256_to_511_octet_packets);
7809 ESTAT_ADD(rx_512_to_1023_octet_packets);
7810 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7811 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7812 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7813 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7814 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7815
7816 ESTAT_ADD(tx_octets);
7817 ESTAT_ADD(tx_collisions);
7818 ESTAT_ADD(tx_xon_sent);
7819 ESTAT_ADD(tx_xoff_sent);
7820 ESTAT_ADD(tx_flow_control);
7821 ESTAT_ADD(tx_mac_errors);
7822 ESTAT_ADD(tx_single_collisions);
7823 ESTAT_ADD(tx_mult_collisions);
7824 ESTAT_ADD(tx_deferred);
7825 ESTAT_ADD(tx_excessive_collisions);
7826 ESTAT_ADD(tx_late_collisions);
7827 ESTAT_ADD(tx_collide_2times);
7828 ESTAT_ADD(tx_collide_3times);
7829 ESTAT_ADD(tx_collide_4times);
7830 ESTAT_ADD(tx_collide_5times);
7831 ESTAT_ADD(tx_collide_6times);
7832 ESTAT_ADD(tx_collide_7times);
7833 ESTAT_ADD(tx_collide_8times);
7834 ESTAT_ADD(tx_collide_9times);
7835 ESTAT_ADD(tx_collide_10times);
7836 ESTAT_ADD(tx_collide_11times);
7837 ESTAT_ADD(tx_collide_12times);
7838 ESTAT_ADD(tx_collide_13times);
7839 ESTAT_ADD(tx_collide_14times);
7840 ESTAT_ADD(tx_collide_15times);
7841 ESTAT_ADD(tx_ucast_packets);
7842 ESTAT_ADD(tx_mcast_packets);
7843 ESTAT_ADD(tx_bcast_packets);
7844 ESTAT_ADD(tx_carrier_sense_errors);
7845 ESTAT_ADD(tx_discards);
7846 ESTAT_ADD(tx_errors);
7847
7848 ESTAT_ADD(dma_writeq_full);
7849 ESTAT_ADD(dma_write_prioq_full);
7850 ESTAT_ADD(rxbds_empty);
7851 ESTAT_ADD(rx_discards);
7852 ESTAT_ADD(rx_errors);
7853 ESTAT_ADD(rx_threshold_hit);
7854
7855 ESTAT_ADD(dma_readq_full);
7856 ESTAT_ADD(dma_read_prioq_full);
7857 ESTAT_ADD(tx_comp_queue_full);
7858
7859 ESTAT_ADD(ring_set_send_prod_index);
7860 ESTAT_ADD(ring_status_update);
7861 ESTAT_ADD(nic_irqs);
7862 ESTAT_ADD(nic_avoided_irqs);
7863 ESTAT_ADD(nic_tx_threshold_hit);
7864
7865 return estats;
7866}
7867
7868static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7869{
7870 struct tg3 *tp = netdev_priv(dev);
7871 struct net_device_stats *stats = &tp->net_stats;
7872 struct net_device_stats *old_stats = &tp->net_stats_prev;
7873 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7874
7875 if (!hw_stats)
7876 return old_stats;
7877
7878 stats->rx_packets = old_stats->rx_packets +
7879 get_stat64(&hw_stats->rx_ucast_packets) +
7880 get_stat64(&hw_stats->rx_mcast_packets) +
7881 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7882
1da177e4
LT		 7883 stats->tx_packets = old_stats->tx_packets +
7884 get_stat64(&hw_stats->tx_ucast_packets) +
7885 get_stat64(&hw_stats->tx_mcast_packets) +
7886 get_stat64(&hw_stats->tx_bcast_packets);
7887
7888 stats->rx_bytes = old_stats->rx_bytes +
7889 get_stat64(&hw_stats->rx_octets);
7890 stats->tx_bytes = old_stats->tx_bytes +
7891 get_stat64(&hw_stats->tx_octets);
7892
7893 stats->rx_errors = old_stats->rx_errors +
4f63b877 7894 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7895 stats->tx_errors = old_stats->tx_errors +
7896 get_stat64(&hw_stats->tx_errors) +
7897 get_stat64(&hw_stats->tx_mac_errors) +
7898 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7899 get_stat64(&hw_stats->tx_discards);
7900
7901 stats->multicast = old_stats->multicast +
7902 get_stat64(&hw_stats->rx_mcast_packets);
7903 stats->collisions = old_stats->collisions +
7904 get_stat64(&hw_stats->tx_collisions);
7905
7906 stats->rx_length_errors = old_stats->rx_length_errors +
7907 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7908 get_stat64(&hw_stats->rx_undersize_packets);
7909
7910 stats->rx_over_errors = old_stats->rx_over_errors +
7911 get_stat64(&hw_stats->rxbds_empty);
7912 stats->rx_frame_errors = old_stats->rx_frame_errors +
7913 get_stat64(&hw_stats->rx_align_errors);
7914 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7915 get_stat64(&hw_stats->tx_discards);
7916 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7917 get_stat64(&hw_stats->tx_carrier_sense_errors);
7918
7919 stats->rx_crc_errors = old_stats->rx_crc_errors +
7920 calc_crc_errors(tp);
7921
4f63b877
JL		 7922 stats->rx_missed_errors = old_stats->rx_missed_errors +
7923 get_stat64(&hw_stats->rx_discards);
7924
1da177e4
LT		 7925 return stats;
7926}
7927
7928static inline u32 calc_crc(unsigned char *buf, int len)
7929{
7930 u32 reg;
7931 u32 tmp;
7932 int j, k;
7933
7934 reg = 0xffffffff;
7935
7936 for (j = 0; j < len; j++) {
7937 reg ^= buf[j];
7938
7939 for (k = 0; k < 8; k++) {
7940 tmp = reg & 0x01;
7941
7942 reg >>= 1;
7943
7944 if (tmp) {
7945 reg ^= 0xedb88320;
7946 }
7947 }
7948 }
7949
7950 return ~reg;
7951}
7952
7953static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7954{
7955 /* accept or reject all multicast frames */
7956 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7957 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7958 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7959 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7960}
7961
7962static void __tg3_set_rx_mode(struct net_device *dev)
7963{
7964 struct tg3 *tp = netdev_priv(dev);
7965 u32 rx_mode;
7966
7967 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7968 RX_MODE_KEEP_VLAN_TAG);
7969
7970 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7971 * flag clear.
7972 */
7973#if TG3_VLAN_TAG_USED
7974 if (!tp->vlgrp &&
7975 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7976 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7977#else
7978 /* By definition, VLAN is disabled always in this
7979 * case.
7980 */
7981 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7982 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7983#endif
7984
7985 if (dev->flags & IFF_PROMISC) {
7986 /* Promiscuous mode. */
7987 rx_mode |= RX_MODE_PROMISC;
7988 } else if (dev->flags & IFF_ALLMULTI) {
7989 /* Accept all multicast. */
7990 tg3_set_multi (tp, 1);
7991 } else if (dev->mc_count < 1) {
7992 /* Reject all multicast. */
7993 tg3_set_multi (tp, 0);
7994 } else {
7995 /* Accept one or more multicast(s). */
7996 struct dev_mc_list *mclist;
7997 unsigned int i;
7998 u32 mc_filter[4] = { 0, };
7999 u32 regidx;
8000 u32 bit;
8001 u32 crc;
8002
8003 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8004 i++, mclist = mclist->next) {
8005
8006 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8007 bit = ~crc & 0x7f;
8008 regidx = (bit & 0x60) >> 5;
8009 bit &= 0x1f;
8010 mc_filter[regidx] |= (1 << bit);
8011 }
8012
8013 tw32(MAC_HASH_REG_0, mc_filter[0]);
8014 tw32(MAC_HASH_REG_1, mc_filter[1]);
8015 tw32(MAC_HASH_REG_2, mc_filter[2]);
8016 tw32(MAC_HASH_REG_3, mc_filter[3]);
8017 }
8018
8019 if (rx_mode != tp->rx_mode) {
8020 tp->rx_mode = rx_mode;
8021 tw32_f(MAC_RX_MODE, rx_mode);
8022 udelay(10);
8023 }
8024}
8025
8026static void tg3_set_rx_mode(struct net_device *dev)
8027{
8028 struct tg3 *tp = netdev_priv(dev);
8029
e75f7c90
MC		 8030 if (!netif_running(dev))
8031 return;
8032
f47c11ee 8033 tg3_full_lock(tp, 0);
1da177e4 8034 __tg3_set_rx_mode(dev);
f47c11ee 8035 tg3_full_unlock(tp);
1da177e4
LT		 8036}
8037
8038#define TG3_REGDUMP_LEN (32 * 1024)
8039
8040static int tg3_get_regs_len(struct net_device *dev)
8041{
8042 return TG3_REGDUMP_LEN;
8043}
8044
8045static void tg3_get_regs(struct net_device *dev,
8046 struct ethtool_regs *regs, void *_p)
8047{
8048 u32 *p = _p;
8049 struct tg3 *tp = netdev_priv(dev);
8050 u8 *orig_p = _p;
8051 int i;
8052
8053 regs->version = 0;
8054
8055 memset(p, 0, TG3_REGDUMP_LEN);
8056
bc1c7567
MC		 8057 if (tp->link_config.phy_is_low_power)
8058 return;
8059
f47c11ee 8060 tg3_full_lock(tp, 0);
1da177e4
LT		 8061
8062#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8063#define GET_REG32_LOOP(base,len) \
8064do { p = (u32 *)(orig_p + (base)); \
8065 for (i = 0; i < len; i += 4) \
8066 __GET_REG32((base) + i); \
8067} while (0)
8068#define GET_REG32_1(reg) \
8069do { p = (u32 *)(orig_p + (reg)); \
8070 __GET_REG32((reg)); \
8071} while (0)
8072
8073 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8074 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8075 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8076 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8077 GET_REG32_1(SNDDATAC_MODE);
8078 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8079 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8080 GET_REG32_1(SNDBDC_MODE);
8081 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8082 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8083 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8084 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8085 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8086 GET_REG32_1(RCVDCC_MODE);
8087 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8088 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8089 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8090 GET_REG32_1(MBFREE_MODE);
8091 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8092 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8093 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8094 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8095 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8096 GET_REG32_1(RX_CPU_MODE);
8097 GET_REG32_1(RX_CPU_STATE);
8098 GET_REG32_1(RX_CPU_PGMCTR);
8099 GET_REG32_1(RX_CPU_HWBKPT);
8100 GET_REG32_1(TX_CPU_MODE);
8101 GET_REG32_1(TX_CPU_STATE);
8102 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8103 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8104 GET_REG32_LOOP(FTQ_RESET, 0x120);
8105 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8106 GET_REG32_1(DMAC_MODE);
8107 GET_REG32_LOOP(GRC_MODE, 0x4c);
8108 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8109 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8110
8111#undef __GET_REG32
8112#undef GET_REG32_LOOP
8113#undef GET_REG32_1
8114
f47c11ee 8115 tg3_full_unlock(tp);
1da177e4
LT		 8116}
8117
8118static int tg3_get_eeprom_len(struct net_device *dev)
8119{
8120 struct tg3 *tp = netdev_priv(dev);
8121
8122 return tp->nvram_size;
8123}
8124
8125static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 8126static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 8127
8128static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8129{
8130 struct tg3 *tp = netdev_priv(dev);
8131 int ret;
8132 u8 *pd;
8133 u32 i, offset, len, val, b_offset, b_count;
8134
bc1c7567
MC		 8135 if (tp->link_config.phy_is_low_power)
8136 return -EAGAIN;
8137
1da177e4
LT		 8138 offset = eeprom->offset;
8139 len = eeprom->len;
8140 eeprom->len = 0;
8141
8142 eeprom->magic = TG3_EEPROM_MAGIC;
8143
8144 if (offset & 3) {
8145 /* adjustments to start on required 4 byte boundary */
8146 b_offset = offset & 3;
8147 b_count = 4 - b_offset;
8148 if (b_count > len) {
8149 /* i.e. offset=1 len=2 */
8150 b_count = len;
8151 }
8152 ret = tg3_nvram_read(tp, offset-b_offset, &val);
8153 if (ret)
8154 return ret;
8155 val = cpu_to_le32(val);
8156 memcpy(data, ((char*)&val) + b_offset, b_count);
8157 len -= b_count;
8158 offset += b_count;
8159 eeprom->len += b_count;
8160 }
8161
8162 /* read bytes upto the last 4 byte boundary */
8163 pd = &data[eeprom->len];
8164 for (i = 0; i < (len - (len & 3)); i += 4) {
8165 ret = tg3_nvram_read(tp, offset + i, &val);
8166 if (ret) {
8167 eeprom->len += i;
8168 return ret;
8169 }
8170 val = cpu_to_le32(val);
8171 memcpy(pd + i, &val, 4);
8172 }
8173 eeprom->len += i;
8174
8175 if (len & 3) {
8176 /* read last bytes not ending on 4 byte boundary */
8177 pd = &data[eeprom->len];
8178 b_count = len & 3;
8179 b_offset = offset + len - b_count;
8180 ret = tg3_nvram_read(tp, b_offset, &val);
8181 if (ret)
8182 return ret;
8183 val = cpu_to_le32(val);
8184 memcpy(pd, ((char*)&val), b_count);
8185 eeprom->len += b_count;
8186 }
8187 return 0;
8188}
8189
6aa20a22 8190static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8191
8192static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8193{
8194 struct tg3 *tp = netdev_priv(dev);
8195 int ret;
8196 u32 offset, len, b_offset, odd_len, start, end;
8197 u8 *buf;
8198
bc1c7567
MC		 8199 if (tp->link_config.phy_is_low_power)
8200 return -EAGAIN;
8201
1da177e4
LT		 8202 if (eeprom->magic != TG3_EEPROM_MAGIC)
8203 return -EINVAL;
8204
8205 offset = eeprom->offset;
8206 len = eeprom->len;
8207
8208 if ((b_offset = (offset & 3))) {
8209 /* adjustments to start on required 4 byte boundary */
8210 ret = tg3_nvram_read(tp, offset-b_offset, &start);
8211 if (ret)
8212 return ret;
8213 start = cpu_to_le32(start);
8214 len += b_offset;
8215 offset &= ~3;
1c8594b4
MC		 8216 if (len < 4)
8217 len = 4;
1da177e4
LT		 8218 }
8219
8220 odd_len = 0;
1c8594b4 8221 if (len & 3) {
1da177e4
LT		 8222 /* adjustments to end on required 4 byte boundary */
8223 odd_len = 1;
8224 len = (len + 3) & ~3;
8225 ret = tg3_nvram_read(tp, offset+len-4, &end);
8226 if (ret)
8227 return ret;
8228 end = cpu_to_le32(end);
8229 }
8230
8231 buf = data;
8232 if (b_offset || odd_len) {
8233 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8234 if (!buf)
1da177e4
LT		 8235 return -ENOMEM;
8236 if (b_offset)
8237 memcpy(buf, &start, 4);
8238 if (odd_len)
8239 memcpy(buf+len-4, &end, 4);
8240 memcpy(buf + b_offset, data, eeprom->len);
8241 }
8242
8243 ret = tg3_nvram_write_block(tp, offset, len, buf);
8244
8245 if (buf != data)
8246 kfree(buf);
8247
8248 return ret;
8249}
8250
8251static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8252{
8253 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8254
1da177e4
LT		 8255 cmd->supported = (SUPPORTED_Autoneg);
8256
8257 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8258 cmd->supported |= (SUPPORTED_1000baseT_Half |
8259 SUPPORTED_1000baseT_Full);
8260
ef348144 8261 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8262 cmd->supported |= (SUPPORTED_100baseT_Half |
8263 SUPPORTED_100baseT_Full |
8264 SUPPORTED_10baseT_Half |
8265 SUPPORTED_10baseT_Full |
8266 SUPPORTED_MII);
ef348144
KK		 8267 cmd->port = PORT_TP;
8268 } else {
1da177e4 8269 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8270 cmd->port = PORT_FIBRE;
8271 }
6aa20a22 8272
1da177e4
LT		 8273 cmd->advertising = tp->link_config.advertising;
8274 if (netif_running(dev)) {
8275 cmd->speed = tp->link_config.active_speed;
8276 cmd->duplex = tp->link_config.active_duplex;
8277 }
1da177e4
LT		 8278 cmd->phy_address = PHY_ADDR;
8279 cmd->transceiver = 0;
8280 cmd->autoneg = tp->link_config.autoneg;
8281 cmd->maxtxpkt = 0;
8282 cmd->maxrxpkt = 0;
8283 return 0;
8284}
6aa20a22 8285
1da177e4
LT		 8286static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8287{
8288 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 8289
8290 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 8291 /* These are the only valid advertisement bits allowed. */
8292 if (cmd->autoneg == AUTONEG_ENABLE &&
8293 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8294 ADVERTISED_1000baseT_Full |
8295 ADVERTISED_Autoneg |
8296 ADVERTISED_FIBRE)))
8297 return -EINVAL;
37ff238d
MC		 8298 /* Fiber can only do SPEED_1000. */
8299 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8300 (cmd->speed != SPEED_1000))
8301 return -EINVAL;
8302 /* Copper cannot force SPEED_1000. */
8303 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8304 (cmd->speed == SPEED_1000))
8305 return -EINVAL;
8306 else if ((cmd->speed == SPEED_1000) &&
8307 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8308 return -EINVAL;
1da177e4 8309
f47c11ee 8310 tg3_full_lock(tp, 0);
1da177e4
LT		 8311
8312 tp->link_config.autoneg = cmd->autoneg;
8313 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8314 tp->link_config.advertising = (cmd->advertising |
8315 ADVERTISED_Autoneg);
1da177e4
LT		 8316 tp->link_config.speed = SPEED_INVALID;
8317 tp->link_config.duplex = DUPLEX_INVALID;
8318 } else {
8319 tp->link_config.advertising = 0;
8320 tp->link_config.speed = cmd->speed;
8321 tp->link_config.duplex = cmd->duplex;
8322 }
6aa20a22 8323
24fcad6b
MC		 8324 tp->link_config.orig_speed = tp->link_config.speed;
8325 tp->link_config.orig_duplex = tp->link_config.duplex;
8326 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8327
1da177e4
LT		 8328 if (netif_running(dev))
8329 tg3_setup_phy(tp, 1);
8330
f47c11ee 8331 tg3_full_unlock(tp);
6aa20a22 8332
1da177e4
LT		 8333 return 0;
8334}
6aa20a22 8335
1da177e4
LT		 8336static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8337{
8338 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8339
1da177e4
LT		 8340 strcpy(info->driver, DRV_MODULE_NAME);
8341 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8342 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8343 strcpy(info->bus_info, pci_name(tp->pdev));
8344}
6aa20a22 8345
1da177e4
LT		 8346static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8347{
8348 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8349
a85feb8c
GZ		 8350 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8351 wol->supported = WAKE_MAGIC;
8352 else
8353 wol->supported = 0;
1da177e4
LT		 8354 wol->wolopts = 0;
8355 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8356 wol->wolopts = WAKE_MAGIC;
8357 memset(&wol->sopass, 0, sizeof(wol->sopass));
8358}
6aa20a22 8359
1da177e4
LT		 8360static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8361{
8362 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8363
1da177e4
LT		 8364 if (wol->wolopts & ~WAKE_MAGIC)
8365 return -EINVAL;
8366 if ((wol->wolopts & WAKE_MAGIC) &&
a85feb8c 8367 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
1da177e4 8368 return -EINVAL;
6aa20a22 8369
f47c11ee 8370 spin_lock_bh(&tp->lock);
1da177e4
LT		 8371 if (wol->wolopts & WAKE_MAGIC)
8372 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8373 else
8374 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8375 spin_unlock_bh(&tp->lock);
6aa20a22 8376
1da177e4
LT		 8377 return 0;
8378}
6aa20a22 8379
1da177e4
LT		 8380static u32 tg3_get_msglevel(struct net_device *dev)
8381{
8382 struct tg3 *tp = netdev_priv(dev);
8383 return tp->msg_enable;
8384}
6aa20a22 8385
1da177e4
LT		 8386static void tg3_set_msglevel(struct net_device *dev, u32 value)
8387{
8388 struct tg3 *tp = netdev_priv(dev);
8389 tp->msg_enable = value;
8390}
6aa20a22 8391
1da177e4
LT		 8392static int tg3_set_tso(struct net_device *dev, u32 value)
8393{
8394 struct tg3 *tp = netdev_priv(dev);
8395
8396 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8397 if (value)
8398 return -EINVAL;
8399 return 0;
8400 }
b5d3772c
MC		 8401 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8402 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9936bcf6 8403 if (value) {
b0026624 8404 dev->features |= NETIF_F_TSO6;
9936bcf6
MC		 8405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8406 dev->features |= NETIF_F_TSO_ECN;
8407 } else
8408 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8409 }
1da177e4
LT		 8410 return ethtool_op_set_tso(dev, value);
8411}
6aa20a22 8412
1da177e4
LT		 8413static int tg3_nway_reset(struct net_device *dev)
8414{
8415 struct tg3 *tp = netdev_priv(dev);
8416 u32 bmcr;
8417 int r;
6aa20a22 8418
1da177e4
LT		 8419 if (!netif_running(dev))
8420 return -EAGAIN;
8421
c94e3941
MC		 8422 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8423 return -EINVAL;
8424
f47c11ee 8425 spin_lock_bh(&tp->lock);
1da177e4
LT		 8426 r = -EINVAL;
8427 tg3_readphy(tp, MII_BMCR, &bmcr);
8428 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8429 ((bmcr & BMCR_ANENABLE) ||
8430 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8431 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8432 BMCR_ANENABLE);
1da177e4
LT		 8433 r = 0;
8434 }
f47c11ee 8435 spin_unlock_bh(&tp->lock);
6aa20a22 8436
1da177e4
LT		 8437 return r;
8438}
6aa20a22 8439
1da177e4
LT		 8440static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8441{
8442 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8443
1da177e4
LT		 8444 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8445 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8446 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8447 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8448 else
8449 ering->rx_jumbo_max_pending = 0;
8450
8451 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8452
8453 ering->rx_pending = tp->rx_pending;
8454 ering->rx_mini_pending = 0;
4f81c32b
MC		 8455 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8456 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8457 else
8458 ering->rx_jumbo_pending = 0;
8459
1da177e4
LT		 8460 ering->tx_pending = tp->tx_pending;
8461}
6aa20a22 8462
1da177e4
LT		 8463static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8464{
8465 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8466 int irq_sync = 0, err = 0;
6aa20a22 8467
1da177e4
LT		 8468 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8469 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8470 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8471 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8472 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8473 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8474 return -EINVAL;
6aa20a22 8475
bbe832c0 8476 if (netif_running(dev)) {
1da177e4 8477 tg3_netif_stop(tp);
bbe832c0
MC		 8478 irq_sync = 1;
8479 }
1da177e4 8480
bbe832c0 8481 tg3_full_lock(tp, irq_sync);
6aa20a22 8482
1da177e4
LT		 8483 tp->rx_pending = ering->rx_pending;
8484
8485 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8486 tp->rx_pending > 63)
8487 tp->rx_pending = 63;
8488 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8489 tp->tx_pending = ering->tx_pending;
8490
8491 if (netif_running(dev)) {
944d980e 8492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8493 err = tg3_restart_hw(tp, 1);
8494 if (!err)
8495 tg3_netif_start(tp);
1da177e4
LT		 8496 }
8497
f47c11ee 8498 tg3_full_unlock(tp);
6aa20a22 8499
b9ec6c1b 8500 return err;
1da177e4 8501}
6aa20a22 8502
1da177e4
LT		 8503static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8504{
8505 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8506
1da177e4
LT		 8507 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8508 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8509 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8510}
6aa20a22 8511
1da177e4
LT		 8512static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8513{
8514 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8515 int irq_sync = 0, err = 0;
6aa20a22 8516
bbe832c0 8517 if (netif_running(dev)) {
1da177e4 8518 tg3_netif_stop(tp);
bbe832c0
MC		 8519 irq_sync = 1;
8520 }
1da177e4 8521
bbe832c0 8522 tg3_full_lock(tp, irq_sync);
f47c11ee 8523
1da177e4
LT		 8524 if (epause->autoneg)
8525 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8526 else
8527 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8528 if (epause->rx_pause)
8529 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8530 else
8531 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8532 if (epause->tx_pause)
8533 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8534 else
8535 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8536
8537 if (netif_running(dev)) {
944d980e 8538 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8539 err = tg3_restart_hw(tp, 1);
8540 if (!err)
8541 tg3_netif_start(tp);
1da177e4 8542 }
f47c11ee
DM		 8543
8544 tg3_full_unlock(tp);
6aa20a22 8545
b9ec6c1b 8546 return err;
1da177e4 8547}
6aa20a22 8548
1da177e4
LT		 8549static u32 tg3_get_rx_csum(struct net_device *dev)
8550{
8551 struct tg3 *tp = netdev_priv(dev);
8552 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8553}
6aa20a22 8554
1da177e4
LT		 8555static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8556{
8557 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8558
1da177e4
LT		 8559 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8560 if (data != 0)
8561 return -EINVAL;
8562 return 0;
8563 }
6aa20a22 8564
f47c11ee 8565 spin_lock_bh(&tp->lock);
1da177e4
LT		 8566 if (data)
8567 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8568 else
8569 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8570 spin_unlock_bh(&tp->lock);
6aa20a22 8571
1da177e4
LT		 8572 return 0;
8573}
6aa20a22 8574
1da177e4
LT		 8575static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8576{
8577 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8578
1da177e4
LT		 8579 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8580 if (data != 0)
8581 return -EINVAL;
8582 return 0;
8583 }
6aa20a22 8584
af36e6b6 8585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 8586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 8587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8588 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
6460d948 8589 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 8590 else
9c27dbdf 8591 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8592
8593 return 0;
8594}
8595
b9f2c044 8596static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 8597{
b9f2c044
JG		 8598 switch (sset) {
8599 case ETH_SS_TEST:
8600 return TG3_NUM_TEST;
8601 case ETH_SS_STATS:
8602 return TG3_NUM_STATS;
8603 default:
8604 return -EOPNOTSUPP;
8605 }
4cafd3f5
MC		 8606}
8607
1da177e4
LT		 8608static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8609{
8610 switch (stringset) {
8611 case ETH_SS_STATS:
8612 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8613 break;
4cafd3f5
MC		 8614 case ETH_SS_TEST:
8615 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8616 break;
1da177e4
LT		 8617 default:
8618 WARN_ON(1); /* we need a WARN() */
8619 break;
8620 }
8621}
8622
4009a93d
MC		 8623static int tg3_phys_id(struct net_device *dev, u32 data)
8624{
8625 struct tg3 *tp = netdev_priv(dev);
8626 int i;
8627
8628 if (!netif_running(tp->dev))
8629 return -EAGAIN;
8630
8631 if (data == 0)
8632 data = 2;
8633
8634 for (i = 0; i < (data * 2); i++) {
8635 if ((i % 2) == 0)
8636 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8637 LED_CTRL_1000MBPS_ON |
8638 LED_CTRL_100MBPS_ON |
8639 LED_CTRL_10MBPS_ON |
8640 LED_CTRL_TRAFFIC_OVERRIDE |
8641 LED_CTRL_TRAFFIC_BLINK |
8642 LED_CTRL_TRAFFIC_LED);
6aa20a22 8643
4009a93d
MC		 8644 else
8645 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8646 LED_CTRL_TRAFFIC_OVERRIDE);
8647
8648 if (msleep_interruptible(500))
8649 break;
8650 }
8651 tw32(MAC_LED_CTRL, tp->led_ctrl);
8652 return 0;
8653}
8654
1da177e4
LT		 8655static void tg3_get_ethtool_stats (struct net_device *dev,
8656 struct ethtool_stats *estats, u64 *tmp_stats)
8657{
8658 struct tg3 *tp = netdev_priv(dev);
8659 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8660}
8661
566f86ad 8662#define NVRAM_TEST_SIZE 0x100
1b27777a 8663#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
b16250e3
MC		 8664#define NVRAM_SELFBOOT_HW_SIZE 0x20
8665#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8666
8667static int tg3_test_nvram(struct tg3 *tp)
8668{
1b27777a 8669 u32 *buf, csum, magic;
ab0049b4 8670 int i, j, k, err = 0, size;
566f86ad 8671
1820180b 8672 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8673 return -EIO;
8674
1b27777a
MC		 8675 if (magic == TG3_EEPROM_MAGIC)
8676 size = NVRAM_TEST_SIZE;
b16250e3 8677 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8678 if ((magic & 0xe00000) == 0x200000)
8679 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8680 else
8681 return 0;
b16250e3
MC		 8682 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8683 size = NVRAM_SELFBOOT_HW_SIZE;
8684 else
1b27777a
MC		 8685 return -EIO;
8686
8687 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8688 if (buf == NULL)
8689 return -ENOMEM;
8690
1b27777a
MC		 8691 err = -EIO;
8692 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8693 u32 val;
8694
8695 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8696 break;
8697 buf[j] = cpu_to_le32(val);
8698 }
1b27777a 8699 if (i < size)
566f86ad
MC		 8700 goto out;
8701
1b27777a 8702 /* Selfboot format */
b16250e3
MC		 8703 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8704 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8705 u8 *buf8 = (u8 *) buf, csum8 = 0;
8706
8707 for (i = 0; i < size; i++)
8708 csum8 += buf8[i];
8709
ad96b485
AB		 8710 if (csum8 == 0) {
8711 err = 0;
8712 goto out;
8713 }
8714
8715 err = -EIO;
8716 goto out;
1b27777a 8717 }
566f86ad 8718
b16250e3
MC		 8719 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8720 TG3_EEPROM_MAGIC_HW) {
8721 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8722 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8723 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 8724
8725 /* Separate the parity bits and the data bytes. */
8726 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8727 if ((i == 0) || (i == 8)) {
8728 int l;
8729 u8 msk;
8730
8731 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8732 parity[k++] = buf8[i] & msk;
8733 i++;
8734 }
8735 else if (i == 16) {
8736 int l;
8737 u8 msk;
8738
8739 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8740 parity[k++] = buf8[i] & msk;
8741 i++;
8742
8743 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8744 parity[k++] = buf8[i] & msk;
8745 i++;
8746 }
8747 data[j++] = buf8[i];
8748 }
8749
8750 err = -EIO;
8751 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8752 u8 hw8 = hweight8(data[i]);
8753
8754 if ((hw8 & 0x1) && parity[i])
8755 goto out;
8756 else if (!(hw8 & 0x1) && !parity[i])
8757 goto out;
8758 }
8759 err = 0;
8760 goto out;
8761 }
8762
566f86ad
MC		 8763 /* Bootstrap checksum at offset 0x10 */
8764 csum = calc_crc((unsigned char *) buf, 0x10);
8765 if(csum != cpu_to_le32(buf[0x10/4]))
8766 goto out;
8767
8768 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8769 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8770 if (csum != cpu_to_le32(buf[0xfc/4]))
8771 goto out;
8772
8773 err = 0;
8774
8775out:
8776 kfree(buf);
8777 return err;
8778}
8779
ca43007a
MC		 8780#define TG3_SERDES_TIMEOUT_SEC 2
8781#define TG3_COPPER_TIMEOUT_SEC 6
8782
8783static int tg3_test_link(struct tg3 *tp)
8784{
8785 int i, max;
8786
8787 if (!netif_running(tp->dev))
8788 return -ENODEV;
8789
4c987487 8790 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8791 max = TG3_SERDES_TIMEOUT_SEC;
8792 else
8793 max = TG3_COPPER_TIMEOUT_SEC;
8794
8795 for (i = 0; i < max; i++) {
8796 if (netif_carrier_ok(tp->dev))
8797 return 0;
8798
8799 if (msleep_interruptible(1000))
8800 break;
8801 }
8802
8803 return -EIO;
8804}
8805
a71116d1 8806/* Only test the commonly used registers */
30ca3e37 8807static int tg3_test_registers(struct tg3 *tp)
a71116d1 8808{
b16250e3 8809 int i, is_5705, is_5750;
a71116d1
MC		 8810 u32 offset, read_mask, write_mask, val, save_val, read_val;
8811 static struct {
8812 u16 offset;
8813 u16 flags;
8814#define TG3_FL_5705 0x1
8815#define TG3_FL_NOT_5705 0x2
8816#define TG3_FL_NOT_5788 0x4
b16250e3 8817#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8818 u32 read_mask;
8819 u32 write_mask;
8820 } reg_tbl[] = {
8821 /* MAC Control Registers */
8822 { MAC_MODE, TG3_FL_NOT_5705,
8823 0x00000000, 0x00ef6f8c },
8824 { MAC_MODE, TG3_FL_5705,
8825 0x00000000, 0x01ef6b8c },
8826 { MAC_STATUS, TG3_FL_NOT_5705,
8827 0x03800107, 0x00000000 },
8828 { MAC_STATUS, TG3_FL_5705,
8829 0x03800100, 0x00000000 },
8830 { MAC_ADDR_0_HIGH, 0x0000,
8831 0x00000000, 0x0000ffff },
8832 { MAC_ADDR_0_LOW, 0x0000,
8833 0x00000000, 0xffffffff },
8834 { MAC_RX_MTU_SIZE, 0x0000,
8835 0x00000000, 0x0000ffff },
8836 { MAC_TX_MODE, 0x0000,
8837 0x00000000, 0x00000070 },
8838 { MAC_TX_LENGTHS, 0x0000,
8839 0x00000000, 0x00003fff },
8840 { MAC_RX_MODE, TG3_FL_NOT_5705,
8841 0x00000000, 0x000007fc },
8842 { MAC_RX_MODE, TG3_FL_5705,
8843 0x00000000, 0x000007dc },
8844 { MAC_HASH_REG_0, 0x0000,
8845 0x00000000, 0xffffffff },
8846 { MAC_HASH_REG_1, 0x0000,
8847 0x00000000, 0xffffffff },
8848 { MAC_HASH_REG_2, 0x0000,
8849 0x00000000, 0xffffffff },
8850 { MAC_HASH_REG_3, 0x0000,
8851 0x00000000, 0xffffffff },
8852
8853 /* Receive Data and Receive BD Initiator Control Registers. */
8854 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8855 0x00000000, 0xffffffff },
8856 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8857 0x00000000, 0xffffffff },
8858 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8859 0x00000000, 0x00000003 },
8860 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8861 0x00000000, 0xffffffff },
8862 { RCVDBDI_STD_BD+0, 0x0000,
8863 0x00000000, 0xffffffff },
8864 { RCVDBDI_STD_BD+4, 0x0000,
8865 0x00000000, 0xffffffff },
8866 { RCVDBDI_STD_BD+8, 0x0000,
8867 0x00000000, 0xffff0002 },
8868 { RCVDBDI_STD_BD+0xc, 0x0000,
8869 0x00000000, 0xffffffff },
6aa20a22 8870
a71116d1
MC		 8871 /* Receive BD Initiator Control Registers. */
8872 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8873 0x00000000, 0xffffffff },
8874 { RCVBDI_STD_THRESH, TG3_FL_5705,
8875 0x00000000, 0x000003ff },
8876 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8877 0x00000000, 0xffffffff },
6aa20a22 8878
a71116d1
MC		 8879 /* Host Coalescing Control Registers. */
8880 { HOSTCC_MODE, TG3_FL_NOT_5705,
8881 0x00000000, 0x00000004 },
8882 { HOSTCC_MODE, TG3_FL_5705,
8883 0x00000000, 0x000000f6 },
8884 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8885 0x00000000, 0xffffffff },
8886 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8887 0x00000000, 0x000003ff },
8888 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8889 0x00000000, 0xffffffff },
8890 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8891 0x00000000, 0x000003ff },
8892 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8893 0x00000000, 0xffffffff },
8894 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8895 0x00000000, 0x000000ff },
8896 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8897 0x00000000, 0xffffffff },
8898 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8899 0x00000000, 0x000000ff },
8900 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8901 0x00000000, 0xffffffff },
8902 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8903 0x00000000, 0xffffffff },
8904 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8905 0x00000000, 0xffffffff },
8906 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8907 0x00000000, 0x000000ff },
8908 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8909 0x00000000, 0xffffffff },
8910 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8911 0x00000000, 0x000000ff },
8912 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8913 0x00000000, 0xffffffff },
8914 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8915 0x00000000, 0xffffffff },
8916 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8917 0x00000000, 0xffffffff },
8918 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8919 0x00000000, 0xffffffff },
8920 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8921 0x00000000, 0xffffffff },
8922 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8923 0xffffffff, 0x00000000 },
8924 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8925 0xffffffff, 0x00000000 },
8926
8927 /* Buffer Manager Control Registers. */
b16250e3 8928 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 8929 0x00000000, 0x007fff80 },
b16250e3 8930 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 8931 0x00000000, 0x007fffff },
8932 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8933 0x00000000, 0x0000003f },
8934 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8935 0x00000000, 0x000001ff },
8936 { BUFMGR_MB_HIGH_WATER, 0x0000,
8937 0x00000000, 0x000001ff },
8938 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8939 0xffffffff, 0x00000000 },
8940 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8941 0xffffffff, 0x00000000 },
6aa20a22 8942
a71116d1
MC		 8943 /* Mailbox Registers */
8944 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8945 0x00000000, 0x000001ff },
8946 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8947 0x00000000, 0x000001ff },
8948 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8949 0x00000000, 0x000007ff },
8950 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8951 0x00000000, 0x000001ff },
8952
8953 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8954 };
8955
b16250e3
MC		 8956 is_5705 = is_5750 = 0;
8957 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 8958 is_5705 = 1;
b16250e3
MC		 8959 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8960 is_5750 = 1;
8961 }
a71116d1
MC		 8962
8963 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8964 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8965 continue;
8966
8967 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8968 continue;
8969
8970 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8971 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8972 continue;
8973
b16250e3
MC		 8974 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8975 continue;
8976
a71116d1
MC		 8977 offset = (u32) reg_tbl[i].offset;
8978 read_mask = reg_tbl[i].read_mask;
8979 write_mask = reg_tbl[i].write_mask;
8980
8981 /* Save the original register content */
8982 save_val = tr32(offset);
8983
8984 /* Determine the read-only value. */
8985 read_val = save_val & read_mask;
8986
8987 /* Write zero to the register, then make sure the read-only bits
8988 * are not changed and the read/write bits are all zeros.
8989 */
8990 tw32(offset, 0);
8991
8992 val = tr32(offset);
8993
8994 /* Test the read-only and read/write bits. */
8995 if (((val & read_mask) != read_val) || (val & write_mask))
8996 goto out;
8997
8998 /* Write ones to all the bits defined by RdMask and WrMask, then
8999 * make sure the read-only bits are not changed and the
9000 * read/write bits are all ones.
9001 */
9002 tw32(offset, read_mask | write_mask);
9003
9004 val = tr32(offset);
9005
9006 /* Test the read-only bits. */
9007 if ((val & read_mask) != read_val)
9008 goto out;
9009
9010 /* Test the read/write bits. */
9011 if ((val & write_mask) != write_mask)
9012 goto out;
9013
9014 tw32(offset, save_val);
9015 }
9016
9017 return 0;
9018
9019out:
9f88f29f
MC		 9020 if (netif_msg_hw(tp))
9021 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9022 offset);
a71116d1
MC		 9023 tw32(offset, save_val);
9024 return -EIO;
9025}
9026
7942e1db
MC		 9027static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9028{
f71e1309 9029 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9030 int i;
9031 u32 j;
9032
9033 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
9034 for (j = 0; j < len; j += 4) {
9035 u32 val;
9036
9037 tg3_write_mem(tp, offset + j, test_pattern[i]);
9038 tg3_read_mem(tp, offset + j, &val);
9039 if (val != test_pattern[i])
9040 return -EIO;
9041 }
9042 }
9043 return 0;
9044}
9045
9046static int tg3_test_memory(struct tg3 *tp)
9047{
9048 static struct mem_entry {
9049 u32 offset;
9050 u32 len;
9051 } mem_tbl_570x[] = {
38690194 9052 { 0x00000000, 0x00b50},
7942e1db
MC		 9053 { 0x00002000, 0x1c000},
9054 { 0xffffffff, 0x00000}
9055 }, mem_tbl_5705[] = {
9056 { 0x00000100, 0x0000c},
9057 { 0x00000200, 0x00008},
7942e1db
MC		 9058 { 0x00004000, 0x00800},
9059 { 0x00006000, 0x01000},
9060 { 0x00008000, 0x02000},
9061 { 0x00010000, 0x0e000},
9062 { 0xffffffff, 0x00000}
79f4d13a
MC		 9063 }, mem_tbl_5755[] = {
9064 { 0x00000200, 0x00008},
9065 { 0x00004000, 0x00800},
9066 { 0x00006000, 0x00800},
9067 { 0x00008000, 0x02000},
9068 { 0x00010000, 0x0c000},
9069 { 0xffffffff, 0x00000}
b16250e3
MC		 9070 }, mem_tbl_5906[] = {
9071 { 0x00000200, 0x00008},
9072 { 0x00004000, 0x00400},
9073 { 0x00006000, 0x00400},
9074 { 0x00008000, 0x01000},
9075 { 0x00010000, 0x01000},
9076 { 0xffffffff, 0x00000}
7942e1db
MC		 9077 };
9078 struct mem_entry *mem_tbl;
9079 int err = 0;
9080 int i;
9081
79f4d13a 9082 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6 9083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 9084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 9085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
79f4d13a 9087 mem_tbl = mem_tbl_5755;
b16250e3
MC		 9088 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9089 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 9090 else
9091 mem_tbl = mem_tbl_5705;
9092 } else
7942e1db
MC		 9093 mem_tbl = mem_tbl_570x;
9094
9095 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9096 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9097 mem_tbl[i].len)) != 0)
9098 break;
9099 }
6aa20a22 9100
7942e1db
MC		 9101 return err;
9102}
9103
9f40dead
MC		 9104#define TG3_MAC_LOOPBACK 0
9105#define TG3_PHY_LOOPBACK 1
9106
9107static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9108{
9f40dead 9109 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9110 u32 desc_idx;
9111 struct sk_buff *skb, *rx_skb;
9112 u8 *tx_data;
9113 dma_addr_t map;
9114 int num_pkts, tx_len, rx_len, i, err;
9115 struct tg3_rx_buffer_desc *desc;
9116
9f40dead 9117 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9118 /* HW errata - mac loopback fails in some cases on 5780.
9119 * Normal traffic and PHY loopback are not affected by
9120 * errata.
9121 */
9122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9123 return 0;
9124
9f40dead 9125 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9126 MAC_MODE_PORT_INT_LPBACK;
9127 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9128 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9129 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9130 mac_mode |= MAC_MODE_PORT_MODE_MII;
9131 else
9132 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9133 tw32(MAC_MODE, mac_mode);
9134 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9135 u32 val;
9136
b16250e3
MC		 9137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9138 u32 phytest;
9139
9140 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9141 u32 phy;
9142
9143 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9144 phytest | MII_TG3_EPHY_SHADOW_EN);
9145 if (!tg3_readphy(tp, 0x1b, &phy))
9146 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9147 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9148 }
5d64ad34
MC		 9149 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9150 } else
9151 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9152
9ef8ca99
MC		 9153 tg3_phy_toggle_automdix(tp, 0);
9154
3f7045c1 9155 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9156 udelay(40);
5d64ad34 9157
e8f3f6ca 9158 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9160 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9161 mac_mode |= MAC_MODE_PORT_MODE_MII;
9162 } else
9163 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9164
c94e3941
MC		 9165 /* reset to prevent losing 1st rx packet intermittently */
9166 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9167 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9168 udelay(10);
9169 tw32_f(MAC_RX_MODE, tp->rx_mode);
9170 }
e8f3f6ca
MC		 9171 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9172 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9173 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9174 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9175 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9176 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9177 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9178 }
9f40dead 9179 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9180 }
9181 else
9182 return -EINVAL;
c76949a6
MC		 9183
9184 err = -EIO;
9185
c76949a6 9186 tx_len = 1514;
a20e9c62 9187 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9188 if (!skb)
9189 return -ENOMEM;
9190
c76949a6
MC		 9191 tx_data = skb_put(skb, tx_len);
9192 memcpy(tx_data, tp->dev->dev_addr, 6);
9193 memset(tx_data + 6, 0x0, 8);
9194
9195 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9196
9197 for (i = 14; i < tx_len; i++)
9198 tx_data[i] = (u8) (i & 0xff);
9199
9200 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9201
9202 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9203 HOSTCC_MODE_NOW);
9204
9205 udelay(10);
9206
9207 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9208
c76949a6
MC		 9209 num_pkts = 0;
9210
9f40dead 9211 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9212
9f40dead 9213 tp->tx_prod++;
c76949a6
MC		 9214 num_pkts++;
9215
9f40dead
MC		 9216 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9217 tp->tx_prod);
09ee929c 9218 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9219
9220 udelay(10);
9221
3f7045c1
MC		 9222 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9223 for (i = 0; i < 25; i++) {
c76949a6
MC		 9224 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9225 HOSTCC_MODE_NOW);
9226
9227 udelay(10);
9228
9229 tx_idx = tp->hw_status->idx[0].tx_consumer;
9230 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9231 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9232 (rx_idx == (rx_start_idx + num_pkts)))
9233 break;
9234 }
9235
9236 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9237 dev_kfree_skb(skb);
9238
9f40dead 9239 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9240 goto out;
9241
9242 if (rx_idx != rx_start_idx + num_pkts)
9243 goto out;
9244
9245 desc = &tp->rx_rcb[rx_start_idx];
9246 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9247 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9248 if (opaque_key != RXD_OPAQUE_RING_STD)
9249 goto out;
9250
9251 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9252 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9253 goto out;
9254
9255 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9256 if (rx_len != tx_len)
9257 goto out;
9258
9259 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9260
9261 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9262 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9263
9264 for (i = 14; i < tx_len; i++) {
9265 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9266 goto out;
9267 }
9268 err = 0;
6aa20a22 9269
c76949a6
MC		 9270 /* tg3_free_rings will unmap and free the rx_skb */
9271out:
9272 return err;
9273}
9274
9f40dead
MC		 9275#define TG3_MAC_LOOPBACK_FAILED 1
9276#define TG3_PHY_LOOPBACK_FAILED 2
9277#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9278 TG3_PHY_LOOPBACK_FAILED)
9279
9280static int tg3_test_loopback(struct tg3 *tp)
9281{
9282 int err = 0;
9936bcf6 9283 u32 cpmuctrl = 0;
9f40dead
MC		 9284
9285 if (!netif_running(tp->dev))
9286 return TG3_LOOPBACK_FAILED;
9287
b9ec6c1b
MC		 9288 err = tg3_reset_hw(tp, 1);
9289 if (err)
9290 return TG3_LOOPBACK_FAILED;
9f40dead 9291
9936bcf6
MC		 9292 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9293 int i;
9294 u32 status;
9295
9296 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9297
9298 /* Wait for up to 40 microseconds to acquire lock. */
9299 for (i = 0; i < 4; i++) {
9300 status = tr32(TG3_CPMU_MUTEX_GNT);
9301 if (status == CPMU_MUTEX_GNT_DRIVER)
9302 break;
9303 udelay(10);
9304 }
9305
9306 if (status != CPMU_MUTEX_GNT_DRIVER)
9307 return TG3_LOOPBACK_FAILED;
9308
9309 cpmuctrl = tr32(TG3_CPMU_CTRL);
9310
9311 /* Turn off power management based on link speed. */
9312 tw32(TG3_CPMU_CTRL,
9313 cpmuctrl & ~CPMU_CTRL_LINK_SPEED_MODE);
9314 }
9315
9f40dead
MC		 9316 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9317 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6
MC		 9318
9319 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9320 tw32(TG3_CPMU_CTRL, cpmuctrl);
9321
9322 /* Release the mutex */
9323 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9324 }
9325
9f40dead
MC		 9326 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9327 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9328 err |= TG3_PHY_LOOPBACK_FAILED;
9329 }
9330
9331 return err;
9332}
9333
4cafd3f5
MC		 9334static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9335 u64 *data)
9336{
566f86ad
MC		 9337 struct tg3 *tp = netdev_priv(dev);
9338
bc1c7567
MC		 9339 if (tp->link_config.phy_is_low_power)
9340 tg3_set_power_state(tp, PCI_D0);
9341
566f86ad
MC		 9342 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9343
9344 if (tg3_test_nvram(tp) != 0) {
9345 etest->flags |= ETH_TEST_FL_FAILED;
9346 data[0] = 1;
9347 }
ca43007a
MC		 9348 if (tg3_test_link(tp) != 0) {
9349 etest->flags |= ETH_TEST_FL_FAILED;
9350 data[1] = 1;
9351 }
a71116d1 9352 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 9353 int err, irq_sync = 0;
bbe832c0
MC		 9354
9355 if (netif_running(dev)) {
a71116d1 9356 tg3_netif_stop(tp);
bbe832c0
MC		 9357 irq_sync = 1;
9358 }
a71116d1 9359
bbe832c0 9360 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9361
9362 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9363 err = tg3_nvram_lock(tp);
a71116d1
MC		 9364 tg3_halt_cpu(tp, RX_CPU_BASE);
9365 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9366 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9367 if (!err)
9368 tg3_nvram_unlock(tp);
a71116d1 9369
d9ab5ad1
MC		 9370 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9371 tg3_phy_reset(tp);
9372
a71116d1
MC		 9373 if (tg3_test_registers(tp) != 0) {
9374 etest->flags |= ETH_TEST_FL_FAILED;
9375 data[2] = 1;
9376 }
7942e1db
MC		 9377 if (tg3_test_memory(tp) != 0) {
9378 etest->flags |= ETH_TEST_FL_FAILED;
9379 data[3] = 1;
9380 }
9f40dead 9381 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9382 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9383
f47c11ee
DM		 9384 tg3_full_unlock(tp);
9385
d4bc3927
MC		 9386 if (tg3_test_interrupt(tp) != 0) {
9387 etest->flags |= ETH_TEST_FL_FAILED;
9388 data[5] = 1;
9389 }
f47c11ee
DM		 9390
9391 tg3_full_lock(tp, 0);
d4bc3927 9392
a71116d1
MC		 9393 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9394 if (netif_running(dev)) {
9395 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9396 if (!tg3_restart_hw(tp, 1))
9397 tg3_netif_start(tp);
a71116d1 9398 }
f47c11ee
DM		 9399
9400 tg3_full_unlock(tp);
a71116d1 9401 }
bc1c7567
MC		 9402 if (tp->link_config.phy_is_low_power)
9403 tg3_set_power_state(tp, PCI_D3hot);
9404
4cafd3f5
MC		 9405}
9406
1da177e4
LT		 9407static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9408{
9409 struct mii_ioctl_data *data = if_mii(ifr);
9410 struct tg3 *tp = netdev_priv(dev);
9411 int err;
9412
9413 switch(cmd) {
9414 case SIOCGMIIPHY:
9415 data->phy_id = PHY_ADDR;
9416
9417 /* fallthru */
9418 case SIOCGMIIREG: {
9419 u32 mii_regval;
9420
9421 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9422 break; /* We have no PHY */
9423
bc1c7567
MC		 9424 if (tp->link_config.phy_is_low_power)
9425 return -EAGAIN;
9426
f47c11ee 9427 spin_lock_bh(&tp->lock);
1da177e4 9428 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9429 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9430
9431 data->val_out = mii_regval;
9432
9433 return err;
9434 }
9435
9436 case SIOCSMIIREG:
9437 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9438 break; /* We have no PHY */
9439
9440 if (!capable(CAP_NET_ADMIN))
9441 return -EPERM;
9442
bc1c7567
MC		 9443 if (tp->link_config.phy_is_low_power)
9444 return -EAGAIN;
9445
f47c11ee 9446 spin_lock_bh(&tp->lock);
1da177e4 9447 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9448 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9449
9450 return err;
9451
9452 default:
9453 /* do nothing */
9454 break;
9455 }
9456 return -EOPNOTSUPP;
9457}
9458
9459#if TG3_VLAN_TAG_USED
9460static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9461{
9462 struct tg3 *tp = netdev_priv(dev);
9463
29315e87
MC		 9464 if (netif_running(dev))
9465 tg3_netif_stop(tp);
9466
f47c11ee 9467 tg3_full_lock(tp, 0);
1da177e4
LT		 9468
9469 tp->vlgrp = grp;
9470
9471 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9472 __tg3_set_rx_mode(dev);
9473
29315e87
MC		 9474 if (netif_running(dev))
9475 tg3_netif_start(tp);
46966545
MC		 9476
9477 tg3_full_unlock(tp);
1da177e4 9478}
1da177e4
LT		 9479#endif
9480
15f9850d
DM		 9481static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9482{
9483 struct tg3 *tp = netdev_priv(dev);
9484
9485 memcpy(ec, &tp->coal, sizeof(*ec));
9486 return 0;
9487}
9488
d244c892
MC		 9489static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9490{
9491 struct tg3 *tp = netdev_priv(dev);
9492 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9493 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9494
9495 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9496 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9497 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9498 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9499 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9500 }
9501
9502 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9503 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9504 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9505 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9506 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9507 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9508 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9509 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9510 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9511 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9512 return -EINVAL;
9513
9514 /* No rx interrupts will be generated if both are zero */
9515 if ((ec->rx_coalesce_usecs == 0) &&
9516 (ec->rx_max_coalesced_frames == 0))
9517 return -EINVAL;
9518
9519 /* No tx interrupts will be generated if both are zero */
9520 if ((ec->tx_coalesce_usecs == 0) &&
9521 (ec->tx_max_coalesced_frames == 0))
9522 return -EINVAL;
9523
9524 /* Only copy relevant parameters, ignore all others. */
9525 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9526 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9527 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9528 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9529 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9530 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9531 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9532 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9533 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9534
9535 if (netif_running(dev)) {
9536 tg3_full_lock(tp, 0);
9537 __tg3_set_coalesce(tp, &tp->coal);
9538 tg3_full_unlock(tp);
9539 }
9540 return 0;
9541}
9542
7282d491 9543static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9544 .get_settings = tg3_get_settings,
9545 .set_settings = tg3_set_settings,
9546 .get_drvinfo = tg3_get_drvinfo,
9547 .get_regs_len = tg3_get_regs_len,
9548 .get_regs = tg3_get_regs,
9549 .get_wol = tg3_get_wol,
9550 .set_wol = tg3_set_wol,
9551 .get_msglevel = tg3_get_msglevel,
9552 .set_msglevel = tg3_set_msglevel,
9553 .nway_reset = tg3_nway_reset,
9554 .get_link = ethtool_op_get_link,
9555 .get_eeprom_len = tg3_get_eeprom_len,
9556 .get_eeprom = tg3_get_eeprom,
9557 .set_eeprom = tg3_set_eeprom,
9558 .get_ringparam = tg3_get_ringparam,
9559 .set_ringparam = tg3_set_ringparam,
9560 .get_pauseparam = tg3_get_pauseparam,
9561 .set_pauseparam = tg3_set_pauseparam,
9562 .get_rx_csum = tg3_get_rx_csum,
9563 .set_rx_csum = tg3_set_rx_csum,
1da177e4 9564 .set_tx_csum = tg3_set_tx_csum,
1da177e4 9565 .set_sg = ethtool_op_set_sg,
1da177e4 9566 .set_tso = tg3_set_tso,
4cafd3f5 9567 .self_test = tg3_self_test,
1da177e4 9568 .get_strings = tg3_get_strings,
4009a93d 9569 .phys_id = tg3_phys_id,
1da177e4 9570 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9571 .get_coalesce = tg3_get_coalesce,
d244c892 9572 .set_coalesce = tg3_set_coalesce,
b9f2c044 9573 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 9574};
9575
9576static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9577{
1b27777a 9578 u32 cursize, val, magic;
1da177e4
LT		 9579
9580 tp->nvram_size = EEPROM_CHIP_SIZE;
9581
1820180b 9582 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9583 return;
9584
b16250e3
MC		 9585 if ((magic != TG3_EEPROM_MAGIC) &&
9586 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9587 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9588 return;
9589
9590 /*
9591 * Size the chip by reading offsets at increasing powers of two.
9592 * When we encounter our validation signature, we know the addressing
9593 * has wrapped around, and thus have our chip size.
9594 */
1b27777a 9595 cursize = 0x10;
1da177e4
LT		 9596
9597 while (cursize < tp->nvram_size) {
1820180b 9598 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9599 return;
9600
1820180b 9601 if (val == magic)
1da177e4
LT		 9602 break;
9603
9604 cursize <<= 1;
9605 }
9606
9607 tp->nvram_size = cursize;
9608}
6aa20a22 9609
1da177e4
LT		 9610static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9611{
9612 u32 val;
9613
1820180b 9614 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9615 return;
9616
9617 /* Selfboot format */
1820180b 9618 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9619 tg3_get_eeprom_size(tp);
9620 return;
9621 }
9622
1da177e4
LT		 9623 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9624 if (val != 0) {
9625 tp->nvram_size = (val >> 16) * 1024;
9626 return;
9627 }
9628 }
989a9d23 9629 tp->nvram_size = 0x80000;
1da177e4
LT		 9630}
9631
9632static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9633{
9634 u32 nvcfg1;
9635
9636 nvcfg1 = tr32(NVRAM_CFG1);
9637 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9638 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9639 }
9640 else {
9641 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9642 tw32(NVRAM_CFG1, nvcfg1);
9643 }
9644
4c987487 9645 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9646 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9647 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9648 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9649 tp->nvram_jedecnum = JEDEC_ATMEL;
9650 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9651 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9652 break;
9653 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9654 tp->nvram_jedecnum = JEDEC_ATMEL;
9655 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9656 break;
9657 case FLASH_VENDOR_ATMEL_EEPROM:
9658 tp->nvram_jedecnum = JEDEC_ATMEL;
9659 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9660 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9661 break;
9662 case FLASH_VENDOR_ST:
9663 tp->nvram_jedecnum = JEDEC_ST;
9664 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9665 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9666 break;
9667 case FLASH_VENDOR_SAIFUN:
9668 tp->nvram_jedecnum = JEDEC_SAIFUN;
9669 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9670 break;
9671 case FLASH_VENDOR_SST_SMALL:
9672 case FLASH_VENDOR_SST_LARGE:
9673 tp->nvram_jedecnum = JEDEC_SST;
9674 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9675 break;
9676 }
9677 }
9678 else {
9679 tp->nvram_jedecnum = JEDEC_ATMEL;
9680 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9681 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9682 }
9683}
9684
361b4ac2
MC		 9685static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9686{
9687 u32 nvcfg1;
9688
9689 nvcfg1 = tr32(NVRAM_CFG1);
9690
e6af301b
MC		 9691 /* NVRAM protection for TPM */
9692 if (nvcfg1 & (1 << 27))
9693 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9694
361b4ac2
MC		 9695 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9696 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9697 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9698 tp->nvram_jedecnum = JEDEC_ATMEL;
9699 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9700 break;
9701 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9702 tp->nvram_jedecnum = JEDEC_ATMEL;
9703 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9704 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9705 break;
9706 case FLASH_5752VENDOR_ST_M45PE10:
9707 case FLASH_5752VENDOR_ST_M45PE20:
9708 case FLASH_5752VENDOR_ST_M45PE40:
9709 tp->nvram_jedecnum = JEDEC_ST;
9710 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9711 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9712 break;
9713 }
9714
9715 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9716 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9717 case FLASH_5752PAGE_SIZE_256:
9718 tp->nvram_pagesize = 256;
9719 break;
9720 case FLASH_5752PAGE_SIZE_512:
9721 tp->nvram_pagesize = 512;
9722 break;
9723 case FLASH_5752PAGE_SIZE_1K:
9724 tp->nvram_pagesize = 1024;
9725 break;
9726 case FLASH_5752PAGE_SIZE_2K:
9727 tp->nvram_pagesize = 2048;
9728 break;
9729 case FLASH_5752PAGE_SIZE_4K:
9730 tp->nvram_pagesize = 4096;
9731 break;
9732 case FLASH_5752PAGE_SIZE_264:
9733 tp->nvram_pagesize = 264;
9734 break;
9735 }
9736 }
9737 else {
9738 /* For eeprom, set pagesize to maximum eeprom size */
9739 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9740
9741 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9742 tw32(NVRAM_CFG1, nvcfg1);
9743 }
9744}
9745
d3c7b886
MC		 9746static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9747{
989a9d23 9748 u32 nvcfg1, protect = 0;
d3c7b886
MC		 9749
9750 nvcfg1 = tr32(NVRAM_CFG1);
9751
9752 /* NVRAM protection for TPM */
989a9d23 9753 if (nvcfg1 & (1 << 27)) {
d3c7b886 9754 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 9755 protect = 1;
9756 }
d3c7b886 9757
989a9d23
MC		 9758 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9759 switch (nvcfg1) {
d3c7b886
MC		 9760 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9761 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9762 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 9763 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 9764 tp->nvram_jedecnum = JEDEC_ATMEL;
9765 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9766 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9767 tp->nvram_pagesize = 264;
70b65a2d
MC		 9768 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9769 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
989a9d23
MC		 9770 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9771 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9772 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9773 else
9774 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
d3c7b886
MC		 9775 break;
9776 case FLASH_5752VENDOR_ST_M45PE10:
9777 case FLASH_5752VENDOR_ST_M45PE20:
9778 case FLASH_5752VENDOR_ST_M45PE40:
9779 tp->nvram_jedecnum = JEDEC_ST;
9780 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9781 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9782 tp->nvram_pagesize = 256;
989a9d23
MC		 9783 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9784 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9785 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9786 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9787 else
9788 tp->nvram_size = (protect ? 0x20000 : 0x80000);
d3c7b886
MC		 9789 break;
9790 }
9791}
9792
1b27777a
MC		 9793static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9794{
9795 u32 nvcfg1;
9796
9797 nvcfg1 = tr32(NVRAM_CFG1);
9798
9799 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9800 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9801 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9802 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9803 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9804 tp->nvram_jedecnum = JEDEC_ATMEL;
9805 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9806 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9807
9808 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9809 tw32(NVRAM_CFG1, nvcfg1);
9810 break;
9811 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9812 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9813 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9814 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9815 tp->nvram_jedecnum = JEDEC_ATMEL;
9816 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9817 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9818 tp->nvram_pagesize = 264;
9819 break;
9820 case FLASH_5752VENDOR_ST_M45PE10:
9821 case FLASH_5752VENDOR_ST_M45PE20:
9822 case FLASH_5752VENDOR_ST_M45PE40:
9823 tp->nvram_jedecnum = JEDEC_ST;
9824 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9825 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9826 tp->nvram_pagesize = 256;
9827 break;
9828 }
9829}
9830
6b91fa02
MC		 9831static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
9832{
9833 u32 nvcfg1, protect = 0;
9834
9835 nvcfg1 = tr32(NVRAM_CFG1);
9836
9837 /* NVRAM protection for TPM */
9838 if (nvcfg1 & (1 << 27)) {
9839 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9840 protect = 1;
9841 }
9842
9843 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9844 switch (nvcfg1) {
9845 case FLASH_5761VENDOR_ATMEL_ADB021D:
9846 case FLASH_5761VENDOR_ATMEL_ADB041D:
9847 case FLASH_5761VENDOR_ATMEL_ADB081D:
9848 case FLASH_5761VENDOR_ATMEL_ADB161D:
9849 case FLASH_5761VENDOR_ATMEL_MDB021D:
9850 case FLASH_5761VENDOR_ATMEL_MDB041D:
9851 case FLASH_5761VENDOR_ATMEL_MDB081D:
9852 case FLASH_5761VENDOR_ATMEL_MDB161D:
9853 tp->nvram_jedecnum = JEDEC_ATMEL;
9854 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9855 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9856 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
9857 tp->nvram_pagesize = 256;
9858 break;
9859 case FLASH_5761VENDOR_ST_A_M45PE20:
9860 case FLASH_5761VENDOR_ST_A_M45PE40:
9861 case FLASH_5761VENDOR_ST_A_M45PE80:
9862 case FLASH_5761VENDOR_ST_A_M45PE16:
9863 case FLASH_5761VENDOR_ST_M_M45PE20:
9864 case FLASH_5761VENDOR_ST_M_M45PE40:
9865 case FLASH_5761VENDOR_ST_M_M45PE80:
9866 case FLASH_5761VENDOR_ST_M_M45PE16:
9867 tp->nvram_jedecnum = JEDEC_ST;
9868 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9869 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9870 tp->nvram_pagesize = 256;
9871 break;
9872 }
9873
9874 if (protect) {
9875 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
9876 } else {
9877 switch (nvcfg1) {
9878 case FLASH_5761VENDOR_ATMEL_ADB161D:
9879 case FLASH_5761VENDOR_ATMEL_MDB161D:
9880 case FLASH_5761VENDOR_ST_A_M45PE16:
9881 case FLASH_5761VENDOR_ST_M_M45PE16:
9882 tp->nvram_size = 0x100000;
9883 break;
9884 case FLASH_5761VENDOR_ATMEL_ADB081D:
9885 case FLASH_5761VENDOR_ATMEL_MDB081D:
9886 case FLASH_5761VENDOR_ST_A_M45PE80:
9887 case FLASH_5761VENDOR_ST_M_M45PE80:
9888 tp->nvram_size = 0x80000;
9889 break;
9890 case FLASH_5761VENDOR_ATMEL_ADB041D:
9891 case FLASH_5761VENDOR_ATMEL_MDB041D:
9892 case FLASH_5761VENDOR_ST_A_M45PE40:
9893 case FLASH_5761VENDOR_ST_M_M45PE40:
9894 tp->nvram_size = 0x40000;
9895 break;
9896 case FLASH_5761VENDOR_ATMEL_ADB021D:
9897 case FLASH_5761VENDOR_ATMEL_MDB021D:
9898 case FLASH_5761VENDOR_ST_A_M45PE20:
9899 case FLASH_5761VENDOR_ST_M_M45PE20:
9900 tp->nvram_size = 0x20000;
9901 break;
9902 }
9903 }
9904}
9905
b5d3772c
MC		 9906static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9907{
9908 tp->nvram_jedecnum = JEDEC_ATMEL;
9909 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9910 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9911}
9912
1da177e4
LT		 9913/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9914static void __devinit tg3_nvram_init(struct tg3 *tp)
9915{
1da177e4
LT		 9916 tw32_f(GRC_EEPROM_ADDR,
9917 (EEPROM_ADDR_FSM_RESET |
9918 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9919 EEPROM_ADDR_CLKPERD_SHIFT)));
9920
9d57f01c 9921 msleep(1);
1da177e4
LT		 9922
9923 /* Enable seeprom accesses. */
9924 tw32_f(GRC_LOCAL_CTRL,
9925 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9926 udelay(100);
9927
9928 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9929 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9930 tp->tg3_flags |= TG3_FLAG_NVRAM;
9931
ec41c7df
MC		 9932 if (tg3_nvram_lock(tp)) {
9933 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9934 "tg3_nvram_init failed.\n", tp->dev->name);
9935 return;
9936 }
e6af301b 9937 tg3_enable_nvram_access(tp);
1da177e4 9938
989a9d23
MC		 9939 tp->nvram_size = 0;
9940
361b4ac2
MC		 9941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9942 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 9943 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9944 tg3_get_5755_nvram_info(tp);
d30cdd28
MC		 9945 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
1b27777a 9947 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 9948 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9949 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 9950 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9951 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 9952 else
9953 tg3_get_nvram_info(tp);
9954
989a9d23
MC		 9955 if (tp->nvram_size == 0)
9956 tg3_get_nvram_size(tp);
1da177e4 9957
e6af301b 9958 tg3_disable_nvram_access(tp);
381291b7 9959 tg3_nvram_unlock(tp);
1da177e4
LT		 9960
9961 } else {
9962 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9963
9964 tg3_get_eeprom_size(tp);
9965 }
9966}
9967
9968static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9969 u32 offset, u32 *val)
9970{
9971 u32 tmp;
9972 int i;
9973
9974 if (offset > EEPROM_ADDR_ADDR_MASK ||
9975 (offset % 4) != 0)
9976 return -EINVAL;
9977
9978 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9979 EEPROM_ADDR_DEVID_MASK |
9980 EEPROM_ADDR_READ);
9981 tw32(GRC_EEPROM_ADDR,
9982 tmp |
9983 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9984 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9985 EEPROM_ADDR_ADDR_MASK) |
9986 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9987
9d57f01c 9988 for (i = 0; i < 1000; i++) {
1da177e4
LT		 9989 tmp = tr32(GRC_EEPROM_ADDR);
9990
9991 if (tmp & EEPROM_ADDR_COMPLETE)
9992 break;
9d57f01c 9993 msleep(1);
1da177e4
LT		 9994 }
9995 if (!(tmp & EEPROM_ADDR_COMPLETE))
9996 return -EBUSY;
9997
9998 *val = tr32(GRC_EEPROM_DATA);
9999 return 0;
10000}
10001
10002#define NVRAM_CMD_TIMEOUT 10000
10003
10004static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10005{
10006 int i;
10007
10008 tw32(NVRAM_CMD, nvram_cmd);
10009 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10010 udelay(10);
10011 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10012 udelay(10);
10013 break;
10014 }
10015 }
10016 if (i == NVRAM_CMD_TIMEOUT) {
10017 return -EBUSY;
10018 }
10019 return 0;
10020}
10021
1820180b
MC		 10022static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10023{
10024 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10025 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10026 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10027 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1820180b
MC		 10028 (tp->nvram_jedecnum == JEDEC_ATMEL))
10029
10030 addr = ((addr / tp->nvram_pagesize) <<
10031 ATMEL_AT45DB0X1B_PAGE_POS) +
10032 (addr % tp->nvram_pagesize);
10033
10034 return addr;
10035}
10036
c4e6575c
MC		 10037static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10038{
10039 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10040 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10041 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10042 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
c4e6575c
MC		 10043 (tp->nvram_jedecnum == JEDEC_ATMEL))
10044
10045 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10046 tp->nvram_pagesize) +
10047 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10048
10049 return addr;
10050}
10051
1da177e4
LT		 10052static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10053{
10054 int ret;
10055
1da177e4
LT		 10056 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10057 return tg3_nvram_read_using_eeprom(tp, offset, val);
10058
1820180b 10059 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10060
10061 if (offset > NVRAM_ADDR_MSK)
10062 return -EINVAL;
10063
ec41c7df
MC		 10064 ret = tg3_nvram_lock(tp);
10065 if (ret)
10066 return ret;
1da177e4 10067
e6af301b 10068 tg3_enable_nvram_access(tp);
1da177e4
LT		 10069
10070 tw32(NVRAM_ADDR, offset);
10071 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10072 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10073
10074 if (ret == 0)
10075 *val = swab32(tr32(NVRAM_RDDATA));
10076
e6af301b 10077 tg3_disable_nvram_access(tp);
1da177e4 10078
381291b7
MC		 10079 tg3_nvram_unlock(tp);
10080
1da177e4
LT		 10081 return ret;
10082}
10083
1820180b
MC		 10084static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10085{
10086 int err;
10087 u32 tmp;
10088
10089 err = tg3_nvram_read(tp, offset, &tmp);
10090 *val = swab32(tmp);
10091 return err;
10092}
10093
1da177e4
LT		 10094static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10095 u32 offset, u32 len, u8 *buf)
10096{
10097 int i, j, rc = 0;
10098 u32 val;
10099
10100 for (i = 0; i < len; i += 4) {
10101 u32 addr, data;
10102
10103 addr = offset + i;
10104
10105 memcpy(&data, buf + i, 4);
10106
10107 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
10108
10109 val = tr32(GRC_EEPROM_ADDR);
10110 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10111
10112 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10113 EEPROM_ADDR_READ);
10114 tw32(GRC_EEPROM_ADDR, val |
10115 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10116 (addr & EEPROM_ADDR_ADDR_MASK) |
10117 EEPROM_ADDR_START |
10118 EEPROM_ADDR_WRITE);
6aa20a22 10119
9d57f01c 10120 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10121 val = tr32(GRC_EEPROM_ADDR);
10122
10123 if (val & EEPROM_ADDR_COMPLETE)
10124 break;
9d57f01c 10125 msleep(1);
1da177e4
LT		 10126 }
10127 if (!(val & EEPROM_ADDR_COMPLETE)) {
10128 rc = -EBUSY;
10129 break;
10130 }
10131 }
10132
10133 return rc;
10134}
10135
10136/* offset and length are dword aligned */
10137static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10138 u8 *buf)
10139{
10140 int ret = 0;
10141 u32 pagesize = tp->nvram_pagesize;
10142 u32 pagemask = pagesize - 1;
10143 u32 nvram_cmd;
10144 u8 *tmp;
10145
10146 tmp = kmalloc(pagesize, GFP_KERNEL);
10147 if (tmp == NULL)
10148 return -ENOMEM;
10149
10150 while (len) {
10151 int j;
e6af301b 10152 u32 phy_addr, page_off, size;
1da177e4
LT		 10153
10154 phy_addr = offset & ~pagemask;
6aa20a22 10155
1da177e4
LT		 10156 for (j = 0; j < pagesize; j += 4) {
10157 if ((ret = tg3_nvram_read(tp, phy_addr + j,
10158 (u32 *) (tmp + j))))
10159 break;
10160 }
10161 if (ret)
10162 break;
10163
10164 page_off = offset & pagemask;
10165 size = pagesize;
10166 if (len < size)
10167 size = len;
10168
10169 len -= size;
10170
10171 memcpy(tmp + page_off, buf, size);
10172
10173 offset = offset + (pagesize - page_off);
10174
e6af301b 10175 tg3_enable_nvram_access(tp);
1da177e4
LT		 10176
10177 /*
10178 * Before we can erase the flash page, we need
10179 * to issue a special "write enable" command.
10180 */
10181 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10182
10183 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10184 break;
10185
10186 /* Erase the target page */
10187 tw32(NVRAM_ADDR, phy_addr);
10188
10189 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10190 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10191
10192 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10193 break;
10194
10195 /* Issue another write enable to start the write. */
10196 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10197
10198 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10199 break;
10200
10201 for (j = 0; j < pagesize; j += 4) {
10202 u32 data;
10203
10204 data = *((u32 *) (tmp + j));
10205 tw32(NVRAM_WRDATA, cpu_to_be32(data));
10206
10207 tw32(NVRAM_ADDR, phy_addr + j);
10208
10209 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10210 NVRAM_CMD_WR;
10211
10212 if (j == 0)
10213 nvram_cmd |= NVRAM_CMD_FIRST;
10214 else if (j == (pagesize - 4))
10215 nvram_cmd |= NVRAM_CMD_LAST;
10216
10217 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10218 break;
10219 }
10220 if (ret)
10221 break;
10222 }
10223
10224 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10225 tg3_nvram_exec_cmd(tp, nvram_cmd);
10226
10227 kfree(tmp);
10228
10229 return ret;
10230}
10231
10232/* offset and length are dword aligned */
10233static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10234 u8 *buf)
10235{
10236 int i, ret = 0;
10237
10238 for (i = 0; i < len; i += 4, offset += 4) {
10239 u32 data, page_off, phy_addr, nvram_cmd;
10240
10241 memcpy(&data, buf + i, 4);
10242 tw32(NVRAM_WRDATA, cpu_to_be32(data));
10243
10244 page_off = offset % tp->nvram_pagesize;
10245
1820180b 10246 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10247
10248 tw32(NVRAM_ADDR, phy_addr);
10249
10250 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10251
10252 if ((page_off == 0) || (i == 0))
10253 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10254 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10255 nvram_cmd |= NVRAM_CMD_LAST;
10256
10257 if (i == (len - 4))
10258 nvram_cmd |= NVRAM_CMD_LAST;
10259
4c987487 10260 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 10261 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 10262 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
d30cdd28 10263 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
9936bcf6 10264 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
4c987487
MC		 10265 (tp->nvram_jedecnum == JEDEC_ST) &&
10266 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10267
10268 if ((ret = tg3_nvram_exec_cmd(tp,
10269 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10270 NVRAM_CMD_DONE)))
10271
10272 break;
10273 }
10274 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10275 /* We always do complete word writes to eeprom. */
10276 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10277 }
10278
10279 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10280 break;
10281 }
10282 return ret;
10283}
10284
10285/* offset and length are dword aligned */
10286static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10287{
10288 int ret;
10289
1da177e4 10290 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10291 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10292 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10293 udelay(40);
10294 }
10295
10296 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10297 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10298 }
10299 else {
10300 u32 grc_mode;
10301
ec41c7df
MC		 10302 ret = tg3_nvram_lock(tp);
10303 if (ret)
10304 return ret;
1da177e4 10305
e6af301b
MC		 10306 tg3_enable_nvram_access(tp);
10307 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10308 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10309 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10310
10311 grc_mode = tr32(GRC_MODE);
10312 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10313
10314 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10315 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10316
10317 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10318 buf);
10319 }
10320 else {
10321 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10322 buf);
10323 }
10324
10325 grc_mode = tr32(GRC_MODE);
10326 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10327
e6af301b 10328 tg3_disable_nvram_access(tp);
1da177e4
LT		 10329 tg3_nvram_unlock(tp);
10330 }
10331
10332 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10333 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10334 udelay(40);
10335 }
10336
10337 return ret;
10338}
10339
10340struct subsys_tbl_ent {
10341 u16 subsys_vendor, subsys_devid;
10342 u32 phy_id;
10343};
10344
10345static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10346 /* Broadcom boards. */
10347 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10348 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10349 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10350 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10351 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10352 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10353 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10354 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10355 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10356 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10357 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10358
10359 /* 3com boards. */
10360 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10361 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10362 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10363 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10364 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10365
10366 /* DELL boards. */
10367 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10368 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10369 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10370 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10371
10372 /* Compaq boards. */
10373 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10374 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10375 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10376 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10377 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10378
10379 /* IBM boards. */
10380 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10381};
10382
10383static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10384{
10385 int i;
10386
10387 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10388 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10389 tp->pdev->subsystem_vendor) &&
10390 (subsys_id_to_phy_id[i].subsys_devid ==
10391 tp->pdev->subsystem_device))
10392 return &subsys_id_to_phy_id[i];
10393 }
10394 return NULL;
10395}
10396
7d0c41ef 10397static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10398{
1da177e4 10399 u32 val;
caf636c7
MC		 10400 u16 pmcsr;
10401
10402 /* On some early chips the SRAM cannot be accessed in D3hot state,
10403 * so need make sure we're in D0.
10404 */
10405 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10406 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10407 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10408 msleep(1);
7d0c41ef
MC		 10409
10410 /* Make sure register accesses (indirect or otherwise)
10411 * will function correctly.
10412 */
10413 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10414 tp->misc_host_ctrl);
1da177e4 10415
f49639e6
DM		 10416 /* The memory arbiter has to be enabled in order for SRAM accesses
10417 * to succeed. Normally on powerup the tg3 chip firmware will make
10418 * sure it is enabled, but other entities such as system netboot
10419 * code might disable it.
10420 */
10421 val = tr32(MEMARB_MODE);
10422 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10423
1da177e4 10424 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10425 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10426
a85feb8c
GZ		 10427 /* Assume an onboard device and WOL capable by default. */
10428 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10429
b5d3772c 10430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10431 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10432 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10433 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10434 }
0527ba35
MC		 10435 val = tr32(VCPU_CFGSHDW);
10436 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 10437 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35
MC		 10438 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10439 (val & VCPU_CFGSHDW_WOL_MAGPKT))
10440 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
b5d3772c
MC		 10441 return;
10442 }
10443
1da177e4
LT		 10444 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10445 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10446 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 10447 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10448 int eeprom_phy_serdes = 0;
1da177e4
LT		 10449
10450 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10451 tp->nic_sram_data_cfg = nic_cfg;
10452
10453 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10454 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10455 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10456 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10457 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10458 (ver > 0) && (ver < 0x100))
10459 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10460
1da177e4
LT		 10461 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10462 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10463 eeprom_phy_serdes = 1;
10464
10465 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10466 if (nic_phy_id != 0) {
10467 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10468 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10469
10470 eeprom_phy_id = (id1 >> 16) << 10;
10471 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10472 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10473 } else
10474 eeprom_phy_id = 0;
10475
7d0c41ef 10476 tp->phy_id = eeprom_phy_id;
747e8f8b 10477 if (eeprom_phy_serdes) {
a4e2b347 10478 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10479 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10480 else
10481 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10482 }
7d0c41ef 10483
cbf46853 10484 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10485 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10486 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10487 else
1da177e4
LT		 10488 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10489
10490 switch (led_cfg) {
10491 default:
10492 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10493 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10494 break;
10495
10496 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10497 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10498 break;
10499
10500 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10501 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10502
10503 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10504 * read on some older 5700/5701 bootcode.
10505 */
10506 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10507 ASIC_REV_5700 ||
10508 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10509 ASIC_REV_5701)
10510 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10511
1da177e4
LT		 10512 break;
10513
10514 case SHASTA_EXT_LED_SHARED:
10515 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10516 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10517 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10518 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10519 LED_CTRL_MODE_PHY_2);
10520 break;
10521
10522 case SHASTA_EXT_LED_MAC:
10523 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10524 break;
10525
10526 case SHASTA_EXT_LED_COMBO:
10527 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10528 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10529 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10530 LED_CTRL_MODE_PHY_2);
10531 break;
10532
10533 };
10534
10535 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10537 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10538 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10539
9d26e213 10540 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10541 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10542 if ((tp->pdev->subsystem_vendor ==
10543 PCI_VENDOR_ID_ARIMA) &&
10544 (tp->pdev->subsystem_device == 0x205a ||
10545 tp->pdev->subsystem_device == 0x2063))
10546 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10547 } else {
f49639e6 10548 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10549 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10550 }
1da177e4
LT		 10551
10552 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10553 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10554 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10555 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10556 }
0d3031d9
MC		 10557 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
10558 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
a85feb8c
GZ		 10559 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10560 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10561 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 10562
0527ba35
MC		 10563 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
10564 nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
10565 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10566
1da177e4
LT		 10567 if (cfg2 & (1 << 17))
10568 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10569
10570 /* serdes signal pre-emphasis in register 0x590 set by */
10571 /* bootcode if bit 18 is set */
10572 if (cfg2 & (1 << 18))
10573 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e
MC		 10574
10575 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10576 u32 cfg3;
10577
10578 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10579 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10580 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10581 }
1da177e4 10582 }
7d0c41ef
MC		 10583}
10584
10585static int __devinit tg3_phy_probe(struct tg3 *tp)
10586{
10587 u32 hw_phy_id_1, hw_phy_id_2;
10588 u32 hw_phy_id, hw_phy_id_masked;
10589 int err;
1da177e4
LT		 10590
10591 /* Reading the PHY ID register can conflict with ASF
10592 * firwmare access to the PHY hardware.
10593 */
10594 err = 0;
0d3031d9
MC		 10595 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
10596 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 10597 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10598 } else {
10599 /* Now read the physical PHY_ID from the chip and verify
10600 * that it is sane. If it doesn't look good, we fall back
10601 * to either the hard-coded table based PHY_ID and failing
10602 * that the value found in the eeprom area.
10603 */
10604 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10605 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10606
10607 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10608 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10609 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10610
10611 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10612 }
10613
10614 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10615 tp->phy_id = hw_phy_id;
10616 if (hw_phy_id_masked == PHY_ID_BCM8002)
10617 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10618 else
10619 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10620 } else {
7d0c41ef
MC		 10621 if (tp->phy_id != PHY_ID_INVALID) {
10622 /* Do nothing, phy ID already set up in
10623 * tg3_get_eeprom_hw_cfg().
10624 */
1da177e4
LT		 10625 } else {
10626 struct subsys_tbl_ent *p;
10627
10628 /* No eeprom signature? Try the hardcoded
10629 * subsys device table.
10630 */
10631 p = lookup_by_subsys(tp);
10632 if (!p)
10633 return -ENODEV;
10634
10635 tp->phy_id = p->phy_id;
10636 if (!tp->phy_id ||
10637 tp->phy_id == PHY_ID_BCM8002)
10638 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10639 }
10640 }
10641
747e8f8b 10642 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 10643 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 10644 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10645 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10646
10647 tg3_readphy(tp, MII_BMSR, &bmsr);
10648 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10649 (bmsr & BMSR_LSTATUS))
10650 goto skip_phy_reset;
6aa20a22 10651
1da177e4
LT		 10652 err = tg3_phy_reset(tp);
10653 if (err)
10654 return err;
10655
10656 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10657 ADVERTISE_100HALF | ADVERTISE_100FULL |
10658 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10659 tg3_ctrl = 0;
10660 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10661 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10662 MII_TG3_CTRL_ADV_1000_FULL);
10663 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10664 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10665 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10666 MII_TG3_CTRL_ENABLE_AS_MASTER);
10667 }
10668
3600d918
MC		 10669 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10670 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10671 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10672 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10673 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10674
10675 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10676 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10677
10678 tg3_writephy(tp, MII_BMCR,
10679 BMCR_ANENABLE | BMCR_ANRESTART);
10680 }
10681 tg3_phy_set_wirespeed(tp);
10682
10683 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10684 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10685 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10686 }
10687
10688skip_phy_reset:
10689 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10690 err = tg3_init_5401phy_dsp(tp);
10691 if (err)
10692 return err;
10693 }
10694
10695 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10696 err = tg3_init_5401phy_dsp(tp);
10697 }
10698
747e8f8b 10699 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10700 tp->link_config.advertising =
10701 (ADVERTISED_1000baseT_Half |
10702 ADVERTISED_1000baseT_Full |
10703 ADVERTISED_Autoneg |
10704 ADVERTISED_FIBRE);
10705 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10706 tp->link_config.advertising &=
10707 ~(ADVERTISED_1000baseT_Half |
10708 ADVERTISED_1000baseT_Full);
10709
10710 return err;
10711}
10712
10713static void __devinit tg3_read_partno(struct tg3 *tp)
10714{
10715 unsigned char vpd_data[256];
af2c6a4a 10716 unsigned int i;
1b27777a 10717 u32 magic;
1da177e4 10718
1820180b 10719 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10720 goto out_not_found;
1da177e4 10721
1820180b 10722 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10723 for (i = 0; i < 256; i += 4) {
10724 u32 tmp;
1da177e4 10725
1b27777a
MC		 10726 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10727 goto out_not_found;
10728
10729 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10730 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10731 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10732 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10733 }
10734 } else {
10735 int vpd_cap;
10736
10737 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10738 for (i = 0; i < 256; i += 4) {
10739 u32 tmp, j = 0;
10740 u16 tmp16;
10741
10742 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10743 i);
10744 while (j++ < 100) {
10745 pci_read_config_word(tp->pdev, vpd_cap +
10746 PCI_VPD_ADDR, &tmp16);
10747 if (tmp16 & 0x8000)
10748 break;
10749 msleep(1);
10750 }
f49639e6
DM		 10751 if (!(tmp16 & 0x8000))
10752 goto out_not_found;
10753
1b27777a
MC		 10754 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10755 &tmp);
10756 tmp = cpu_to_le32(tmp);
10757 memcpy(&vpd_data[i], &tmp, 4);
10758 }
1da177e4
LT		 10759 }
10760
10761 /* Now parse and find the part number. */
af2c6a4a 10762 for (i = 0; i < 254; ) {
1da177e4 10763 unsigned char val = vpd_data[i];
af2c6a4a 10764 unsigned int block_end;
1da177e4
LT		 10765
10766 if (val == 0x82 || val == 0x91) {
10767 i = (i + 3 +
10768 (vpd_data[i + 1] +
10769 (vpd_data[i + 2] << 8)));
10770 continue;
10771 }
10772
10773 if (val != 0x90)
10774 goto out_not_found;
10775
10776 block_end = (i + 3 +
10777 (vpd_data[i + 1] +
10778 (vpd_data[i + 2] << 8)));
10779 i += 3;
af2c6a4a
MC		 10780
10781 if (block_end > 256)
10782 goto out_not_found;
10783
10784 while (i < (block_end - 2)) {
1da177e4
LT		 10785 if (vpd_data[i + 0] == 'P' &&
10786 vpd_data[i + 1] == 'N') {
10787 int partno_len = vpd_data[i + 2];
10788
af2c6a4a
MC		 10789 i += 3;
10790 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10791 goto out_not_found;
10792
10793 memcpy(tp->board_part_number,
af2c6a4a 10794 &vpd_data[i], partno_len);
1da177e4
LT		 10795
10796 /* Success. */
10797 return;
10798 }
af2c6a4a 10799 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10800 }
10801
10802 /* Part number not found. */
10803 goto out_not_found;
10804 }
10805
10806out_not_found:
b5d3772c
MC		 10807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10808 strcpy(tp->board_part_number, "BCM95906");
10809 else
10810 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10811}
10812
c4e6575c
MC		 10813static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10814{
10815 u32 val, offset, start;
10816
10817 if (tg3_nvram_read_swab(tp, 0, &val))
10818 return;
10819
10820 if (val != TG3_EEPROM_MAGIC)
10821 return;
10822
10823 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10824 tg3_nvram_read_swab(tp, 0x4, &start))
10825 return;
10826
10827 offset = tg3_nvram_logical_addr(tp, offset);
10828 if (tg3_nvram_read_swab(tp, offset, &val))
10829 return;
10830
10831 if ((val & 0xfc000000) == 0x0c000000) {
10832 u32 ver_offset, addr;
10833 int i;
10834
10835 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10836 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10837 return;
10838
10839 if (val != 0)
10840 return;
10841
10842 addr = offset + ver_offset - start;
10843 for (i = 0; i < 16; i += 4) {
10844 if (tg3_nvram_read(tp, addr + i, &val))
10845 return;
10846
10847 val = cpu_to_le32(val);
10848 memcpy(tp->fw_ver + i, &val, 4);
10849 }
10850 }
10851}
10852
7544b097
MC		 10853static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10854
1da177e4
LT		 10855static int __devinit tg3_get_invariants(struct tg3 *tp)
10856{
10857 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 10858 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10859 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 10860 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10861 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 10862 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10863 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 10864 { },
10865 };
10866 u32 misc_ctrl_reg;
10867 u32 cacheline_sz_reg;
10868 u32 pci_state_reg, grc_misc_cfg;
10869 u32 val;
10870 u16 pci_cmd;
c7835a77 10871 int err, pcie_cap;
1da177e4 10872
1da177e4
LT		 10873 /* Force memory write invalidate off. If we leave it on,
10874 * then on 5700_BX chips we have to enable a workaround.
10875 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10876 * to match the cacheline size. The Broadcom driver have this
10877 * workaround but turns MWI off all the times so never uses
10878 * it. This seems to suggest that the workaround is insufficient.
10879 */
10880 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10881 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10882 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10883
10884 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10885 * has the register indirect write enable bit set before
10886 * we try to access any of the MMIO registers. It is also
10887 * critical that the PCI-X hw workaround situation is decided
10888 * before that as well.
10889 */
10890 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10891 &misc_ctrl_reg);
10892
10893 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10894 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 10895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
10896 u32 prod_id_asic_rev;
10897
10898 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
10899 &prod_id_asic_rev);
10900 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
10901 }
1da177e4 10902
ff645bec
MC		 10903 /* Wrong chip ID in 5752 A0. This code can be removed later
10904 * as A0 is not in production.
10905 */
10906 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10907 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10908
6892914f
MC		 10909 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10910 * we need to disable memory and use config. cycles
10911 * only to access all registers. The 5702/03 chips
10912 * can mistakenly decode the special cycles from the
10913 * ICH chipsets as memory write cycles, causing corruption
10914 * of register and memory space. Only certain ICH bridges
10915 * will drive special cycles with non-zero data during the
10916 * address phase which can fall within the 5703's address
10917 * range. This is not an ICH bug as the PCI spec allows
10918 * non-zero address during special cycles. However, only
10919 * these ICH bridges are known to drive non-zero addresses
10920 * during special cycles.
10921 *
10922 * Since special cycles do not cross PCI bridges, we only
10923 * enable this workaround if the 5703 is on the secondary
10924 * bus of these ICH bridges.
10925 */
10926 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10927 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10928 static struct tg3_dev_id {
10929 u32 vendor;
10930 u32 device;
10931 u32 rev;
10932 } ich_chipsets[] = {
10933 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10934 PCI_ANY_ID },
10935 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10936 PCI_ANY_ID },
10937 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10938 0xa },
10939 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10940 PCI_ANY_ID },
10941 { },
10942 };
10943 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10944 struct pci_dev *bridge = NULL;
10945
10946 while (pci_id->vendor != 0) {
10947 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10948 bridge);
10949 if (!bridge) {
10950 pci_id++;
10951 continue;
10952 }
10953 if (pci_id->rev != PCI_ANY_ID) {
44c10138 10954 if (bridge->revision > pci_id->rev)
6892914f
MC		 10955 continue;
10956 }
10957 if (bridge->subordinate &&
10958 (bridge->subordinate->number ==
10959 tp->pdev->bus->number)) {
10960
10961 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10962 pci_dev_put(bridge);
10963 break;
10964 }
10965 }
10966 }
10967
4a29cc2e
MC		 10968 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10969 * DMA addresses > 40-bit. This bridge may have other additional
10970 * 57xx devices behind it in some 4-port NIC designs for example.
10971 * Any tg3 device found behind the bridge will also need the 40-bit
10972 * DMA workaround.
10973 */
a4e2b347
MC		 10974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10976 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 10977 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 10978 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 10979 }
4a29cc2e
MC		 10980 else {
10981 struct pci_dev *bridge = NULL;
10982
10983 do {
10984 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10985 PCI_DEVICE_ID_SERVERWORKS_EPB,
10986 bridge);
10987 if (bridge && bridge->subordinate &&
10988 (bridge->subordinate->number <=
10989 tp->pdev->bus->number) &&
10990 (bridge->subordinate->subordinate >=
10991 tp->pdev->bus->number)) {
10992 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10993 pci_dev_put(bridge);
10994 break;
10995 }
10996 } while (bridge);
10997 }
4cf78e4f 10998
1da177e4
LT		 10999 /* Initialize misc host control in PCI block. */
11000 tp->misc_host_ctrl |= (misc_ctrl_reg &
11001 MISC_HOST_CTRL_CHIPREV);
11002 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11003 tp->misc_host_ctrl);
11004
11005 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11006 &cacheline_sz_reg);
11007
11008 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
11009 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
11010 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
11011 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
11012
7544b097
MC		 11013 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11014 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11015 tp->pdev_peer = tg3_find_peer(tp);
11016
6708e5cc 11017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 11018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 11019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 11024 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11025 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11026
1b440c56
JL		 11027 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11028 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11029 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11030
5a6f3074 11031 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11032 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11033 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11034 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11035 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11036 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11037 tp->pdev_peer == tp->pdev))
11038 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11039
af36e6b6 11040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c 11041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11043 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11045 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11046 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11047 } else {
7f62ad5d 11048 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11049 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11050 ASIC_REV_5750 &&
11051 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11052 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11053 }
5a6f3074 11054 }
1da177e4 11055
0f893dc6
MC		 11056 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
11057 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 11058 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 11059 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c 11060 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
d30cdd28 11061 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
9936bcf6 11062 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
b5d3772c 11063 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 11064 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11065
c7835a77
MC		 11066 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11067 if (pcie_cap != 0) {
1da177e4 11068 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 11069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11070 u16 lnkctl;
11071
11072 pci_read_config_word(tp->pdev,
11073 pcie_cap + PCI_EXP_LNKCTL,
11074 &lnkctl);
11075 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11076 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11077 }
11078 }
1da177e4 11079
399de50b
MC		 11080 /* If we have an AMD 762 or VIA K8T800 chipset, write
11081 * reordering to the mailbox registers done by the host
11082 * controller can cause major troubles. We read back from
11083 * every mailbox register write to force the writes to be
11084 * posted to the chip in order.
11085 */
11086 if (pci_dev_present(write_reorder_chipsets) &&
11087 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11088 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11089
1da177e4
LT		 11090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11091 tp->pci_lat_timer < 64) {
11092 tp->pci_lat_timer = 64;
11093
11094 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
11095 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
11096 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
11097 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
11098
11099 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11100 cacheline_sz_reg);
11101 }
11102
9974a356
MC		 11103 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11104 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11105 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11106 if (!tp->pcix_cap) {
11107 printk(KERN_ERR PFX "Cannot find PCI-X "
11108 "capability, aborting.\n");
11109 return -EIO;
11110 }
11111 }
11112
1da177e4
LT		 11113 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11114 &pci_state_reg);
11115
9974a356 11116 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
1da177e4
LT		 11117 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11118
11119 /* If this is a 5700 BX chipset, and we are in PCI-X
11120 * mode, enable register write workaround.
11121 *
11122 * The workaround is to use indirect register accesses
11123 * for all chip writes not to mailbox registers.
11124 */
11125 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11126 u32 pm_reg;
1da177e4
LT		 11127
11128 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11129
11130 /* The chip can have it's power management PCI config
11131 * space registers clobbered due to this bug.
11132 * So explicitly force the chip into D0 here.
11133 */
9974a356
MC		 11134 pci_read_config_dword(tp->pdev,
11135 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11136 &pm_reg);
11137 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11138 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 11139 pci_write_config_dword(tp->pdev,
11140 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11141 pm_reg);
11142
11143 /* Also, force SERR#/PERR# in PCI command. */
11144 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11145 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11146 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11147 }
11148 }
11149
087fe256
MC		 11150 /* 5700 BX chips need to have their TX producer index mailboxes
11151 * written twice to workaround a bug.
11152 */
11153 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
11154 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11155
1da177e4
LT		 11156 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11157 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11158 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11159 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11160
11161 /* Chip-specific fixup from Broadcom driver */
11162 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11163 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11164 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11165 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11166 }
11167
1ee582d8 11168 /* Default fast path register access methods */
20094930 11169 tp->read32 = tg3_read32;
1ee582d8 11170 tp->write32 = tg3_write32;
09ee929c 11171 tp->read32_mbox = tg3_read32;
20094930 11172 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 11173 tp->write32_tx_mbox = tg3_write32;
11174 tp->write32_rx_mbox = tg3_write32;
11175
11176 /* Various workaround register access methods */
11177 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11178 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 11179 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11180 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11181 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11182 /*
11183 * Back to back register writes can cause problems on these
11184 * chips, the workaround is to read back all reg writes
11185 * except those to mailbox regs.
11186 *
11187 * See tg3_write_indirect_reg32().
11188 */
1ee582d8 11189 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 11190 }
11191
1ee582d8
MC		 11192
11193 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11194 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11195 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11196 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11197 tp->write32_rx_mbox = tg3_write_flush_reg32;
11198 }
20094930 11199
6892914f
MC		 11200 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11201 tp->read32 = tg3_read_indirect_reg32;
11202 tp->write32 = tg3_write_indirect_reg32;
11203 tp->read32_mbox = tg3_read_indirect_mbox;
11204 tp->write32_mbox = tg3_write_indirect_mbox;
11205 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11206 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11207
11208 iounmap(tp->regs);
22abe310 11209 tp->regs = NULL;
6892914f
MC		 11210
11211 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11212 pci_cmd &= ~PCI_COMMAND_MEMORY;
11213 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11214 }
b5d3772c
MC		 11215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11216 tp->read32_mbox = tg3_read32_mbox_5906;
11217 tp->write32_mbox = tg3_write32_mbox_5906;
11218 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11219 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11220 }
6892914f 11221
bbadf503
MC		 11222 if (tp->write32 == tg3_write_indirect_reg32 ||
11223 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11224 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 11225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 11226 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11227
7d0c41ef 11228 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 11229 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 11230 * determined before calling tg3_set_power_state() so that
11231 * we know whether or not to switch out of Vaux power.
11232 * When the flag is set, it means that GPIO1 is used for eeprom
11233 * write protect and also implies that it is a LOM where GPIOs
11234 * are not used to switch power.
6aa20a22 11235 */
7d0c41ef
MC		 11236 tg3_get_eeprom_hw_cfg(tp);
11237
0d3031d9
MC		 11238 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11239 /* Allow reads and writes to the
11240 * APE register and memory space.
11241 */
11242 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11243 PCISTATE_ALLOW_APE_SHMEM_WR;
11244 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11245 pci_state_reg);
11246 }
11247
9936bcf6
MC		 11248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d30cdd28
MC		 11250 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11251
314fba34
MC		 11252 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11253 * GPIO1 driven high will bring 5700's external PHY out of reset.
11254 * It is also used as eeprom write protect on LOMs.
11255 */
11256 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11257 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11258 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11259 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11260 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 11261 /* Unused GPIO3 must be driven as output on 5752 because there
11262 * are no pull-up resistors on unused GPIO pins.
11263 */
11264 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11265 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 11266
af36e6b6
MC		 11267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11268 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11269
1da177e4 11270 /* Force the chip into D0. */
bc1c7567 11271 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 11272 if (err) {
11273 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11274 pci_name(tp->pdev));
11275 return err;
11276 }
11277
11278 /* 5700 B0 chips do not support checksumming correctly due
11279 * to hardware bugs.
11280 */
11281 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11282 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11283
1da177e4
LT		 11284 /* Derive initial jumbo mode from MTU assigned in
11285 * ether_setup() via the alloc_etherdev() call
11286 */
0f893dc6 11287 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 11288 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 11289 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 11290
11291 /* Determine WakeOnLan speed to use. */
11292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11293 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11294 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11295 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11296 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11297 } else {
11298 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11299 }
11300
11301 /* A few boards don't want Ethernet@WireSpeed phy feature */
11302 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11303 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11304 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 11305 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 11306 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 11307 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 11308 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11309
11310 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
11311 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
11312 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
11313 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
11314 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
11315
c424cb24
MC		 11316 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 11318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 11319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11320 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 11321 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
11322 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
11323 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 11324 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11325 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11326 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 11327 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11328 }
1da177e4 11329
1da177e4 11330 tp->coalesce_mode = 0;
1da177e4
LT		 11331 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
11332 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11333 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11334
11335 /* Initialize MAC MI mode, polling disabled. */
11336 tw32_f(MAC_MI_MODE, tp->mi_mode);
11337 udelay(80);
11338
11339 /* Initialize data/descriptor byte/word swapping. */
11340 val = tr32(GRC_MODE);
11341 val &= GRC_MODE_HOST_STACKUP;
11342 tw32(GRC_MODE, val | tp->grc_mode);
11343
11344 tg3_switch_clocks(tp);
11345
11346 /* Clear this out for sanity. */
11347 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11348
11349 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11350 &pci_state_reg);
11351 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
11352 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
11353 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
11354
11355 if (chiprevid == CHIPREV_ID_5701_A0 ||
11356 chiprevid == CHIPREV_ID_5701_B0 ||
11357 chiprevid == CHIPREV_ID_5701_B2 ||
11358 chiprevid == CHIPREV_ID_5701_B5) {
11359 void __iomem *sram_base;
11360
11361 /* Write some dummy words into the SRAM status block
11362 * area, see if it reads back correctly. If the return
11363 * value is bad, force enable the PCIX workaround.
11364 */
11365 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
11366
11367 writel(0x00000000, sram_base);
11368 writel(0x00000000, sram_base + 4);
11369 writel(0xffffffff, sram_base + 4);
11370 if (readl(sram_base) != 0x00000000)
11371 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11372 }
11373 }
11374
11375 udelay(50);
11376 tg3_nvram_init(tp);
11377
11378 grc_misc_cfg = tr32(GRC_MISC_CFG);
11379 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
11380
1da177e4
LT		 11381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11382 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
11383 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
11384 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
11385
fac9b83e
DM		 11386 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
11387 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
11388 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
11389 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
11390 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
11391 HOSTCC_MODE_CLRTICK_TXBD);
11392
11393 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11394 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11395 tp->misc_host_ctrl);
11396 }
11397
1da177e4
LT		 11398 /* these are limited to 10/100 only */
11399 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11400 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11401 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11402 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11403 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11404 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11405 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11406 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11407 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 11408 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11409 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 11410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 11411 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11412
11413 err = tg3_phy_probe(tp);
11414 if (err) {
11415 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11416 pci_name(tp->pdev), err);
11417 /* ... but do not return immediately ... */
11418 }
11419
11420 tg3_read_partno(tp);
c4e6575c 11421 tg3_read_fw_ver(tp);
1da177e4
LT		 11422
11423 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11424 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11425 } else {
11426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11427 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11428 else
11429 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11430 }
11431
11432 /* 5700 {AX,BX} chips have a broken status block link
11433 * change bit implementation, so we must use the
11434 * status register in those cases.
11435 */
11436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11437 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11438 else
11439 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11440
11441 /* The led_ctrl is set during tg3_phy_probe, here we might
11442 * have to force the link status polling mechanism based
11443 * upon subsystem IDs.
11444 */
11445 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 11446 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 11447 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11448 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11449 TG3_FLAG_USE_LINKCHG_REG);
11450 }
11451
11452 /* For all SERDES we poll the MAC status register. */
11453 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11454 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11455 else
11456 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11457
5a6f3074 11458 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 11459 * straddle the 4GB address boundary in some cases.
11460 */
af36e6b6 11461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c 11462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11463 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 11466 tp->dev->hard_start_xmit = tg3_start_xmit;
11467 else
11468 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 11469
11470 tp->rx_offset = 2;
11471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11472 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11473 tp->rx_offset = 0;
11474
f92905de
MC		 11475 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11476
11477 /* Increment the rx prod index on the rx std ring by at most
11478 * 8 for these chips to workaround hw errata.
11479 */
11480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11483 tp->rx_std_max_post = 8;
11484
8ed5d97e
MC		 11485 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11486 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11487 PCIE_PWR_MGMT_L1_THRESH_MSK;
11488
1da177e4
LT		 11489 return err;
11490}
11491
49b6e95f 11492#ifdef CONFIG_SPARC
1da177e4
LT		 11493static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11494{
11495 struct net_device *dev = tp->dev;
11496 struct pci_dev *pdev = tp->pdev;
49b6e95f 11497 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 11498 const unsigned char *addr;
49b6e95f
DM		 11499 int len;
11500
11501 addr = of_get_property(dp, "local-mac-address", &len);
11502 if (addr && len == 6) {
11503 memcpy(dev->dev_addr, addr, 6);
11504 memcpy(dev->perm_addr, dev->dev_addr, 6);
11505 return 0;
1da177e4
LT		 11506 }
11507 return -ENODEV;
11508}
11509
11510static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11511{
11512 struct net_device *dev = tp->dev;
11513
11514 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 11515 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 11516 return 0;
11517}
11518#endif
11519
11520static int __devinit tg3_get_device_address(struct tg3 *tp)
11521{
11522 struct net_device *dev = tp->dev;
11523 u32 hi, lo, mac_offset;
008652b3 11524 int addr_ok = 0;
1da177e4 11525
49b6e95f 11526#ifdef CONFIG_SPARC
1da177e4
LT		 11527 if (!tg3_get_macaddr_sparc(tp))
11528 return 0;
11529#endif
11530
11531 mac_offset = 0x7c;
f49639e6 11532 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11533 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11534 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11535 mac_offset = 0xcc;
11536 if (tg3_nvram_lock(tp))
11537 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11538 else
11539 tg3_nvram_unlock(tp);
11540 }
b5d3772c
MC		 11541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11542 mac_offset = 0x10;
1da177e4
LT		 11543
11544 /* First try to get it from MAC address mailbox. */
11545 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11546 if ((hi >> 16) == 0x484b) {
11547 dev->dev_addr[0] = (hi >> 8) & 0xff;
11548 dev->dev_addr[1] = (hi >> 0) & 0xff;
11549
11550 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11551 dev->dev_addr[2] = (lo >> 24) & 0xff;
11552 dev->dev_addr[3] = (lo >> 16) & 0xff;
11553 dev->dev_addr[4] = (lo >> 8) & 0xff;
11554 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11555
008652b3
MC		 11556 /* Some old bootcode may report a 0 MAC address in SRAM */
11557 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11558 }
11559 if (!addr_ok) {
11560 /* Next, try NVRAM. */
f49639e6 11561 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11562 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11563 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11564 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11565 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11566 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11567 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11568 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11569 }
11570 /* Finally just fetch it out of the MAC control regs. */
11571 else {
11572 hi = tr32(MAC_ADDR_0_HIGH);
11573 lo = tr32(MAC_ADDR_0_LOW);
11574
11575 dev->dev_addr[5] = lo & 0xff;
11576 dev->dev_addr[4] = (lo >> 8) & 0xff;
11577 dev->dev_addr[3] = (lo >> 16) & 0xff;
11578 dev->dev_addr[2] = (lo >> 24) & 0xff;
11579 dev->dev_addr[1] = hi & 0xff;
11580 dev->dev_addr[0] = (hi >> 8) & 0xff;
11581 }
1da177e4
LT		 11582 }
11583
11584 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11585#ifdef CONFIG_SPARC64
11586 if (!tg3_get_default_macaddr_sparc(tp))
11587 return 0;
11588#endif
11589 return -EINVAL;
11590 }
2ff43697 11591 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11592 return 0;
11593}
11594
59e6b434
DM		 11595#define BOUNDARY_SINGLE_CACHELINE 1
11596#define BOUNDARY_MULTI_CACHELINE 2
11597
11598static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11599{
11600 int cacheline_size;
11601 u8 byte;
11602 int goal;
11603
11604 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11605 if (byte == 0)
11606 cacheline_size = 1024;
11607 else
11608 cacheline_size = (int) byte * 4;
11609
11610 /* On 5703 and later chips, the boundary bits have no
11611 * effect.
11612 */
11613 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11614 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11615 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11616 goto out;
11617
11618#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11619 goal = BOUNDARY_MULTI_CACHELINE;
11620#else
11621#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11622 goal = BOUNDARY_SINGLE_CACHELINE;
11623#else
11624 goal = 0;
11625#endif
11626#endif
11627
11628 if (!goal)
11629 goto out;
11630
11631 /* PCI controllers on most RISC systems tend to disconnect
11632 * when a device tries to burst across a cache-line boundary.
11633 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11634 *
11635 * Unfortunately, for PCI-E there are only limited
11636 * write-side controls for this, and thus for reads
11637 * we will still get the disconnects. We'll also waste
11638 * these PCI cycles for both read and write for chips
11639 * other than 5700 and 5701 which do not implement the
11640 * boundary bits.
11641 */
11642 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11643 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11644 switch (cacheline_size) {
11645 case 16:
11646 case 32:
11647 case 64:
11648 case 128:
11649 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11650 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11651 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11652 } else {
11653 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11654 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11655 }
11656 break;
11657
11658 case 256:
11659 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11660 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11661 break;
11662
11663 default:
11664 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11665 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11666 break;
11667 };
11668 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11669 switch (cacheline_size) {
11670 case 16:
11671 case 32:
11672 case 64:
11673 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11674 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11675 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11676 break;
11677 }
11678 /* fallthrough */
11679 case 128:
11680 default:
11681 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11682 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11683 break;
11684 };
11685 } else {
11686 switch (cacheline_size) {
11687 case 16:
11688 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11689 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11690 DMA_RWCTRL_WRITE_BNDRY_16);
11691 break;
11692 }
11693 /* fallthrough */
11694 case 32:
11695 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11696 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11697 DMA_RWCTRL_WRITE_BNDRY_32);
11698 break;
11699 }
11700 /* fallthrough */
11701 case 64:
11702 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11703 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11704 DMA_RWCTRL_WRITE_BNDRY_64);
11705 break;
11706 }
11707 /* fallthrough */
11708 case 128:
11709 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11710 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11711 DMA_RWCTRL_WRITE_BNDRY_128);
11712 break;
11713 }
11714 /* fallthrough */
11715 case 256:
11716 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11717 DMA_RWCTRL_WRITE_BNDRY_256);
11718 break;
11719 case 512:
11720 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11721 DMA_RWCTRL_WRITE_BNDRY_512);
11722 break;
11723 case 1024:
11724 default:
11725 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11726 DMA_RWCTRL_WRITE_BNDRY_1024);
11727 break;
11728 };
11729 }
11730
11731out:
11732 return val;
11733}
11734
1da177e4
LT		 11735static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11736{
11737 struct tg3_internal_buffer_desc test_desc;
11738 u32 sram_dma_descs;
11739 int i, ret;
11740
11741 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11742
11743 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11744 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11745 tw32(RDMAC_STATUS, 0);
11746 tw32(WDMAC_STATUS, 0);
11747
11748 tw32(BUFMGR_MODE, 0);
11749 tw32(FTQ_RESET, 0);
11750
11751 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11752 test_desc.addr_lo = buf_dma & 0xffffffff;
11753 test_desc.nic_mbuf = 0x00002100;
11754 test_desc.len = size;
11755
11756 /*
11757 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11758 * the *second* time the tg3 driver was getting loaded after an
11759 * initial scan.
11760 *
11761 * Broadcom tells me:
11762 * ...the DMA engine is connected to the GRC block and a DMA
11763 * reset may affect the GRC block in some unpredictable way...
11764 * The behavior of resets to individual blocks has not been tested.
11765 *
11766 * Broadcom noted the GRC reset will also reset all sub-components.
11767 */
11768 if (to_device) {
11769 test_desc.cqid_sqid = (13 << 8) | 2;
11770
11771 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11772 udelay(40);
11773 } else {
11774 test_desc.cqid_sqid = (16 << 8) | 7;
11775
11776 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11777 udelay(40);
11778 }
11779 test_desc.flags = 0x00000005;
11780
11781 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11782 u32 val;
11783
11784 val = *(((u32 *)&test_desc) + i);
11785 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11786 sram_dma_descs + (i * sizeof(u32)));
11787 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11788 }
11789 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11790
11791 if (to_device) {
11792 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11793 } else {
11794 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11795 }
11796
11797 ret = -ENODEV;
11798 for (i = 0; i < 40; i++) {
11799 u32 val;
11800
11801 if (to_device)
11802 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11803 else
11804 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11805 if ((val & 0xffff) == sram_dma_descs) {
11806 ret = 0;
11807 break;
11808 }
11809
11810 udelay(100);
11811 }
11812
11813 return ret;
11814}
11815
ded7340d 11816#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11817
11818static int __devinit tg3_test_dma(struct tg3 *tp)
11819{
11820 dma_addr_t buf_dma;
59e6b434 11821 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11822 int ret;
11823
11824 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11825 if (!buf) {
11826 ret = -ENOMEM;
11827 goto out_nofree;
11828 }
11829
11830 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11831 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11832
59e6b434 11833 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11834
11835 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11836 /* DMA read watermark not used on PCIE */
11837 tp->dma_rwctrl |= 0x00180000;
11838 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11841 tp->dma_rwctrl |= 0x003f0000;
11842 else
11843 tp->dma_rwctrl |= 0x003f000f;
11844 } else {
11845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11847 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11848 u32 read_water = 0x7;
1da177e4 11849
4a29cc2e
MC		 11850 /* If the 5704 is behind the EPB bridge, we can
11851 * do the less restrictive ONE_DMA workaround for
11852 * better performance.
11853 */
11854 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11856 tp->dma_rwctrl |= 0x8000;
11857 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 11858 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11859
49afdeb6
MC		 11860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11861 read_water = 4;
59e6b434 11862 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 11863 tp->dma_rwctrl |=
11864 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11865 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11866 (1 << 23);
4cf78e4f
MC		 11867 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11868 /* 5780 always in PCIX mode */
11869 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 11870 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11871 /* 5714 always in PCIX mode */
11872 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 11873 } else {
11874 tp->dma_rwctrl |= 0x001b000f;
11875 }
11876 }
11877
11878 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11880 tp->dma_rwctrl &= 0xfffffff0;
11881
11882 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11884 /* Remove this if it causes problems for some boards. */
11885 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11886
11887 /* On 5700/5701 chips, we need to set this bit.
11888 * Otherwise the chip will issue cacheline transactions
11889 * to streamable DMA memory with not all the byte
11890 * enables turned on. This is an error on several
11891 * RISC PCI controllers, in particular sparc64.
11892 *
11893 * On 5703/5704 chips, this bit has been reassigned
11894 * a different meaning. In particular, it is used
11895 * on those chips to enable a PCI-X workaround.
11896 */
11897 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11898 }
11899
11900 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11901
11902#if 0
11903 /* Unneeded, already done by tg3_get_invariants. */
11904 tg3_switch_clocks(tp);
11905#endif
11906
11907 ret = 0;
11908 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11909 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11910 goto out;
11911
59e6b434
DM		 11912 /* It is best to perform DMA test with maximum write burst size
11913 * to expose the 5700/5701 write DMA bug.
11914 */
11915 saved_dma_rwctrl = tp->dma_rwctrl;
11916 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11917 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11918
1da177e4
LT		 11919 while (1) {
11920 u32 *p = buf, i;
11921
11922 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11923 p[i] = i;
11924
11925 /* Send the buffer to the chip. */
11926 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11927 if (ret) {
11928 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11929 break;
11930 }
11931
11932#if 0
11933 /* validate data reached card RAM correctly. */
11934 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11935 u32 val;
11936 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11937 if (le32_to_cpu(val) != p[i]) {
11938 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11939 /* ret = -ENODEV here? */
11940 }
11941 p[i] = 0;
11942 }
11943#endif
11944 /* Now read it back. */
11945 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11946 if (ret) {
11947 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11948
11949 break;
11950 }
11951
11952 /* Verify it. */
11953 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11954 if (p[i] == i)
11955 continue;
11956
59e6b434
DM		 11957 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11958 DMA_RWCTRL_WRITE_BNDRY_16) {
11959 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 11960 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11961 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11962 break;
11963 } else {
11964 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11965 ret = -ENODEV;
11966 goto out;
11967 }
11968 }
11969
11970 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11971 /* Success. */
11972 ret = 0;
11973 break;
11974 }
11975 }
59e6b434
DM		 11976 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11977 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 11978 static struct pci_device_id dma_wait_state_chipsets[] = {
11979 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11980 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11981 { },
11982 };
11983
59e6b434 11984 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 11985 * now look for chipsets that are known to expose the
11986 * DMA bug without failing the test.
59e6b434 11987 */
6d1cfbab
MC		 11988 if (pci_dev_present(dma_wait_state_chipsets)) {
11989 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11990 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11991 }
11992 else
11993 /* Safe to use the calculated DMA boundary. */
11994 tp->dma_rwctrl = saved_dma_rwctrl;
11995
59e6b434
DM		 11996 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11997 }
1da177e4
LT		 11998
11999out:
12000 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12001out_nofree:
12002 return ret;
12003}
12004
12005static void __devinit tg3_init_link_config(struct tg3 *tp)
12006{
12007 tp->link_config.advertising =
12008 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12009 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12010 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12011 ADVERTISED_Autoneg | ADVERTISED_MII);
12012 tp->link_config.speed = SPEED_INVALID;
12013 tp->link_config.duplex = DUPLEX_INVALID;
12014 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12015 tp->link_config.active_speed = SPEED_INVALID;
12016 tp->link_config.active_duplex = DUPLEX_INVALID;
12017 tp->link_config.phy_is_low_power = 0;
12018 tp->link_config.orig_speed = SPEED_INVALID;
12019 tp->link_config.orig_duplex = DUPLEX_INVALID;
12020 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12021}
12022
12023static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12024{
fdfec172
MC		 12025 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12026 tp->bufmgr_config.mbuf_read_dma_low_water =
12027 DEFAULT_MB_RDMA_LOW_WATER_5705;
12028 tp->bufmgr_config.mbuf_mac_rx_low_water =
12029 DEFAULT_MB_MACRX_LOW_WATER_5705;
12030 tp->bufmgr_config.mbuf_high_water =
12031 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12033 tp->bufmgr_config.mbuf_mac_rx_low_water =
12034 DEFAULT_MB_MACRX_LOW_WATER_5906;
12035 tp->bufmgr_config.mbuf_high_water =
12036 DEFAULT_MB_HIGH_WATER_5906;
12037 }
fdfec172
MC		 12038
12039 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12040 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12041 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12042 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12043 tp->bufmgr_config.mbuf_high_water_jumbo =
12044 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12045 } else {
12046 tp->bufmgr_config.mbuf_read_dma_low_water =
12047 DEFAULT_MB_RDMA_LOW_WATER;
12048 tp->bufmgr_config.mbuf_mac_rx_low_water =
12049 DEFAULT_MB_MACRX_LOW_WATER;
12050 tp->bufmgr_config.mbuf_high_water =
12051 DEFAULT_MB_HIGH_WATER;
12052
12053 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12054 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12055 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12056 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12057 tp->bufmgr_config.mbuf_high_water_jumbo =
12058 DEFAULT_MB_HIGH_WATER_JUMBO;
12059 }
1da177e4
LT		 12060
12061 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12062 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12063}
12064
12065static char * __devinit tg3_phy_string(struct tg3 *tp)
12066{
12067 switch (tp->phy_id & PHY_ID_MASK) {
12068 case PHY_ID_BCM5400: return "5400";
12069 case PHY_ID_BCM5401: return "5401";
12070 case PHY_ID_BCM5411: return "5411";
12071 case PHY_ID_BCM5701: return "5701";
12072 case PHY_ID_BCM5703: return "5703";
12073 case PHY_ID_BCM5704: return "5704";
12074 case PHY_ID_BCM5705: return "5705";
12075 case PHY_ID_BCM5750: return "5750";
85e94ced 12076 case PHY_ID_BCM5752: return "5752";
a4e2b347 12077 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12078 case PHY_ID_BCM5780: return "5780";
af36e6b6 12079 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12080 case PHY_ID_BCM5787: return "5787";
d30cdd28 12081 case PHY_ID_BCM5784: return "5784";
126a3368 12082 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12083 case PHY_ID_BCM5906: return "5906";
9936bcf6 12084 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12085 case PHY_ID_BCM8002: return "8002/serdes";
12086 case 0: return "serdes";
12087 default: return "unknown";
12088 };
12089}
12090
f9804ddb
MC		 12091static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12092{
12093 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12094 strcpy(str, "PCI Express");
12095 return str;
12096 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12097 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12098
12099 strcpy(str, "PCIX:");
12100
12101 if ((clock_ctrl == 7) ||
12102 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12103 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12104 strcat(str, "133MHz");
12105 else if (clock_ctrl == 0)
12106 strcat(str, "33MHz");
12107 else if (clock_ctrl == 2)
12108 strcat(str, "50MHz");
12109 else if (clock_ctrl == 4)
12110 strcat(str, "66MHz");
12111 else if (clock_ctrl == 6)
12112 strcat(str, "100MHz");
f9804ddb
MC		 12113 } else {
12114 strcpy(str, "PCI:");
12115 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12116 strcat(str, "66MHz");
12117 else
12118 strcat(str, "33MHz");
12119 }
12120 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12121 strcat(str, ":32-bit");
12122 else
12123 strcat(str, ":64-bit");
12124 return str;
12125}
12126
8c2dc7e1 12127static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 12128{
12129 struct pci_dev *peer;
12130 unsigned int func, devnr = tp->pdev->devfn & ~7;
12131
12132 for (func = 0; func < 8; func++) {
12133 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12134 if (peer && peer != tp->pdev)
12135 break;
12136 pci_dev_put(peer);
12137 }
16fe9d74
MC		 12138 /* 5704 can be configured in single-port mode, set peer to
12139 * tp->pdev in that case.
12140 */
12141 if (!peer) {
12142 peer = tp->pdev;
12143 return peer;
12144 }
1da177e4
LT		 12145
12146 /*
12147 * We don't need to keep the refcount elevated; there's no way
12148 * to remove one half of this device without removing the other
12149 */
12150 pci_dev_put(peer);
12151
12152 return peer;
12153}
12154
15f9850d
DM		 12155static void __devinit tg3_init_coal(struct tg3 *tp)
12156{
12157 struct ethtool_coalesce *ec = &tp->coal;
12158
12159 memset(ec, 0, sizeof(*ec));
12160 ec->cmd = ETHTOOL_GCOALESCE;
12161 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12162 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12163 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12164 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12165 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12166 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12167 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12168 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12169 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12170
12171 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12172 HOSTCC_MODE_CLRTICK_TXBD)) {
12173 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12174 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12175 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12176 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12177 }
d244c892
MC		 12178
12179 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12180 ec->rx_coalesce_usecs_irq = 0;
12181 ec->tx_coalesce_usecs_irq = 0;
12182 ec->stats_block_coalesce_usecs = 0;
12183 }
15f9850d
DM		 12184}
12185
1da177e4
LT		 12186static int __devinit tg3_init_one(struct pci_dev *pdev,
12187 const struct pci_device_id *ent)
12188{
12189 static int tg3_version_printed = 0;
12190 unsigned long tg3reg_base, tg3reg_len;
12191 struct net_device *dev;
12192 struct tg3 *tp;
72f2afb8 12193 int i, err, pm_cap;
f9804ddb 12194 char str[40];
72f2afb8 12195 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 12196
12197 if (tg3_version_printed++ == 0)
12198 printk(KERN_INFO "%s", version);
12199
12200 err = pci_enable_device(pdev);
12201 if (err) {
12202 printk(KERN_ERR PFX "Cannot enable PCI device, "
12203 "aborting.\n");
12204 return err;
12205 }
12206
12207 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12208 printk(KERN_ERR PFX "Cannot find proper PCI device "
12209 "base address, aborting.\n");
12210 err = -ENODEV;
12211 goto err_out_disable_pdev;
12212 }
12213
12214 err = pci_request_regions(pdev, DRV_MODULE_NAME);
12215 if (err) {
12216 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12217 "aborting.\n");
12218 goto err_out_disable_pdev;
12219 }
12220
12221 pci_set_master(pdev);
12222
12223 /* Find power-management capability. */
12224 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12225 if (pm_cap == 0) {
12226 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12227 "aborting.\n");
12228 err = -EIO;
12229 goto err_out_free_res;
12230 }
12231
1da177e4
LT		 12232 tg3reg_base = pci_resource_start(pdev, 0);
12233 tg3reg_len = pci_resource_len(pdev, 0);
12234
12235 dev = alloc_etherdev(sizeof(*tp));
12236 if (!dev) {
12237 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12238 err = -ENOMEM;
12239 goto err_out_free_res;
12240 }
12241
1da177e4
LT		 12242 SET_NETDEV_DEV(dev, &pdev->dev);
12243
1da177e4
LT		 12244#if TG3_VLAN_TAG_USED
12245 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12246 dev->vlan_rx_register = tg3_vlan_rx_register;
1da177e4
LT		 12247#endif
12248
12249 tp = netdev_priv(dev);
12250 tp->pdev = pdev;
12251 tp->dev = dev;
12252 tp->pm_cap = pm_cap;
12253 tp->mac_mode = TG3_DEF_MAC_MODE;
12254 tp->rx_mode = TG3_DEF_RX_MODE;
12255 tp->tx_mode = TG3_DEF_TX_MODE;
12256 tp->mi_mode = MAC_MI_MODE_BASE;
12257 if (tg3_debug > 0)
12258 tp->msg_enable = tg3_debug;
12259 else
12260 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12261
12262 /* The word/byte swap controls here control register access byte
12263 * swapping. DMA data byte swapping is controlled in the GRC_MODE
12264 * setting below.
12265 */
12266 tp->misc_host_ctrl =
12267 MISC_HOST_CTRL_MASK_PCI_INT |
12268 MISC_HOST_CTRL_WORD_SWAP |
12269 MISC_HOST_CTRL_INDIR_ACCESS |
12270 MISC_HOST_CTRL_PCISTATE_RW;
12271
12272 /* The NONFRM (non-frame) byte/word swap controls take effect
12273 * on descriptor entries, anything which isn't packet data.
12274 *
12275 * The StrongARM chips on the board (one for tx, one for rx)
12276 * are running in big-endian mode.
12277 */
12278 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
12279 GRC_MODE_WSWAP_NONFRM_DATA);
12280#ifdef __BIG_ENDIAN
12281 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
12282#endif
12283 spin_lock_init(&tp->lock);
1da177e4 12284 spin_lock_init(&tp->indirect_lock);
c4028958 12285 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 12286
12287 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
ab0049b4 12288 if (!tp->regs) {
1da177e4
LT		 12289 printk(KERN_ERR PFX "Cannot map device registers, "
12290 "aborting.\n");
12291 err = -ENOMEM;
12292 goto err_out_free_dev;
12293 }
12294
12295 tg3_init_link_config(tp);
12296
1da177e4
LT		 12297 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
12298 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
12299 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
12300
12301 dev->open = tg3_open;
12302 dev->stop = tg3_close;
12303 dev->get_stats = tg3_get_stats;
12304 dev->set_multicast_list = tg3_set_rx_mode;
12305 dev->set_mac_address = tg3_set_mac_addr;
12306 dev->do_ioctl = tg3_ioctl;
12307 dev->tx_timeout = tg3_tx_timeout;
bea3348e 12308 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 12309 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4
LT		 12310 dev->watchdog_timeo = TG3_TX_TIMEOUT;
12311 dev->change_mtu = tg3_change_mtu;
12312 dev->irq = pdev->irq;
12313#ifdef CONFIG_NET_POLL_CONTROLLER
12314 dev->poll_controller = tg3_poll_controller;
12315#endif
12316
12317 err = tg3_get_invariants(tp);
12318 if (err) {
12319 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
12320 "aborting.\n");
12321 goto err_out_iounmap;
12322 }
12323
4a29cc2e
MC		 12324 /* The EPB bridge inside 5714, 5715, and 5780 and any
12325 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 12326 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
12327 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
12328 * do DMA address check in tg3_start_xmit().
12329 */
4a29cc2e
MC		 12330 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
12331 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
12332 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 12333 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
12334#ifdef CONFIG_HIGHMEM
12335 dma_mask = DMA_64BIT_MASK;
12336#endif
4a29cc2e 12337 } else
72f2afb8
MC		 12338 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
12339
12340 /* Configure DMA attributes. */
12341 if (dma_mask > DMA_32BIT_MASK) {
12342 err = pci_set_dma_mask(pdev, dma_mask);
12343 if (!err) {
12344 dev->features |= NETIF_F_HIGHDMA;
12345 err = pci_set_consistent_dma_mask(pdev,
12346 persist_dma_mask);
12347 if (err < 0) {
12348 printk(KERN_ERR PFX "Unable to obtain 64 bit "
12349 "DMA for consistent allocations\n");
12350 goto err_out_iounmap;
12351 }
12352 }
12353 }
12354 if (err || dma_mask == DMA_32BIT_MASK) {
12355 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
12356 if (err) {
12357 printk(KERN_ERR PFX "No usable DMA configuration, "
12358 "aborting.\n");
12359 goto err_out_iounmap;
12360 }
12361 }
12362
fdfec172 12363 tg3_init_bufmgr_config(tp);
1da177e4 12364
1da177e4
LT		 12365 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12366 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
12367 }
12368 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12369 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12370 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 12371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 12372 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
12373 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
12374 } else {
7f62ad5d 12375 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
1da177e4
LT		 12376 }
12377
4e3a7aaa
MC		 12378 /* TSO is on by default on chips that support hardware TSO.
12379 * Firmware TSO on older chips gives lower performance, so it
12380 * is off by default, but can be enabled using ethtool.
12381 */
b0026624 12382 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 12383 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 12384 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12385 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624 12386 dev->features |= NETIF_F_TSO6;
9936bcf6
MC		 12387 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12388 dev->features |= NETIF_F_TSO_ECN;
b0026624 12389 }
1da177e4 12390
1da177e4
LT		 12391
12392 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
12393 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
12394 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12395 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12396 tp->rx_pending = 63;
12397 }
12398
1da177e4
LT		 12399 err = tg3_get_device_address(tp);
12400 if (err) {
12401 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12402 "aborting.\n");
12403 goto err_out_iounmap;
12404 }
12405
12406 /*
12407 * Reset chip in case UNDI or EFI driver did not shutdown
12408 * DMA self test will enable WDMAC and we'll see (spurious)
12409 * pending DMA on the PCI bus at that point.
12410 */
12411 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12412 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 12413 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 12414 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 12415 }
12416
12417 err = tg3_test_dma(tp);
12418 if (err) {
12419 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12420 goto err_out_iounmap;
12421 }
12422
12423 /* Tigon3 can do ipv4 only... and some chips have buggy
12424 * checksumming.
12425 */
12426 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
d212f87b 12427 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
af36e6b6 12428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12431 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d212f87b
SH		 12432 dev->features |= NETIF_F_IPV6_CSUM;
12433
1da177e4
LT		 12434 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12435 } else
12436 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12437
1da177e4
LT		 12438 /* flow control autonegotiation is default behavior */
12439 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12440
15f9850d
DM		 12441 tg3_init_coal(tp);
12442
0d3031d9
MC		 12443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12444 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12445 printk(KERN_ERR PFX "Cannot find proper PCI device "
12446 "base address for APE, aborting.\n");
12447 err = -ENODEV;
12448 goto err_out_iounmap;
12449 }
12450
12451 tg3reg_base = pci_resource_start(pdev, 2);
12452 tg3reg_len = pci_resource_len(pdev, 2);
12453
12454 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
12455 if (tp->aperegs == 0UL) {
12456 printk(KERN_ERR PFX "Cannot map APE registers, "
12457 "aborting.\n");
12458 err = -ENOMEM;
12459 goto err_out_iounmap;
12460 }
12461
12462 tg3_ape_lock_init(tp);
12463 }
12464
c49a1561
MC		 12465 pci_set_drvdata(pdev, dev);
12466
1da177e4
LT		 12467 err = register_netdev(dev);
12468 if (err) {
12469 printk(KERN_ERR PFX "Cannot register net device, "
12470 "aborting.\n");
0d3031d9 12471 goto err_out_apeunmap;
1da177e4
LT		 12472 }
12473
cbb45d21 12474 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 12475 dev->name,
12476 tp->board_part_number,
12477 tp->pci_chip_rev_id,
12478 tg3_phy_string(tp),
f9804ddb 12479 tg3_bus_string(tp, str),
cbb45d21
MC		 12480 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12481 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12482 "10/100/1000Base-T")));
1da177e4
LT		 12483
12484 for (i = 0; i < 6; i++)
12485 printk("%2.2x%c", dev->dev_addr[i],
12486 i == 5 ? '\n' : ':');
12487
12488 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
1c46ae05 12489 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
1da177e4
LT		 12490 dev->name,
12491 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12492 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12493 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12494 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4
LT		 12495 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12496 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 12497 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12498 dev->name, tp->dma_rwctrl,
12499 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12500 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 12501
12502 return 0;
12503
0d3031d9
MC		 12504err_out_apeunmap:
12505 if (tp->aperegs) {
12506 iounmap(tp->aperegs);
12507 tp->aperegs = NULL;
12508 }
12509
1da177e4 12510err_out_iounmap:
6892914f
MC		 12511 if (tp->regs) {
12512 iounmap(tp->regs);
22abe310 12513 tp->regs = NULL;
6892914f 12514 }
1da177e4
LT		 12515
12516err_out_free_dev:
12517 free_netdev(dev);
12518
12519err_out_free_res:
12520 pci_release_regions(pdev);
12521
12522err_out_disable_pdev:
12523 pci_disable_device(pdev);
12524 pci_set_drvdata(pdev, NULL);
12525 return err;
12526}
12527
12528static void __devexit tg3_remove_one(struct pci_dev *pdev)
12529{
12530 struct net_device *dev = pci_get_drvdata(pdev);
12531
12532 if (dev) {
12533 struct tg3 *tp = netdev_priv(dev);
12534
7faa006f 12535 flush_scheduled_work();
1da177e4 12536 unregister_netdev(dev);
0d3031d9
MC		 12537 if (tp->aperegs) {
12538 iounmap(tp->aperegs);
12539 tp->aperegs = NULL;
12540 }
6892914f
MC		 12541 if (tp->regs) {
12542 iounmap(tp->regs);
22abe310 12543 tp->regs = NULL;
6892914f 12544 }
1da177e4
LT		 12545 free_netdev(dev);
12546 pci_release_regions(pdev);
12547 pci_disable_device(pdev);
12548 pci_set_drvdata(pdev, NULL);
12549 }
12550}
12551
12552static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12553{
12554 struct net_device *dev = pci_get_drvdata(pdev);
12555 struct tg3 *tp = netdev_priv(dev);
12556 int err;
12557
3e0c95fd
MC		 12558 /* PCI register 4 needs to be saved whether netif_running() or not.
12559 * MSI address and data need to be saved if using MSI and
12560 * netif_running().
12561 */
12562 pci_save_state(pdev);
12563
1da177e4
LT		 12564 if (!netif_running(dev))
12565 return 0;
12566
7faa006f 12567 flush_scheduled_work();
1da177e4
LT		 12568 tg3_netif_stop(tp);
12569
12570 del_timer_sync(&tp->timer);
12571
f47c11ee 12572 tg3_full_lock(tp, 1);
1da177e4 12573 tg3_disable_ints(tp);
f47c11ee 12574 tg3_full_unlock(tp);
1da177e4
LT		 12575
12576 netif_device_detach(dev);
12577
f47c11ee 12578 tg3_full_lock(tp, 0);
944d980e 12579 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12580 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12581 tg3_full_unlock(tp);
1da177e4
LT		 12582
12583 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12584 if (err) {
f47c11ee 12585 tg3_full_lock(tp, 0);
1da177e4 12586
6a9eba15 12587 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12588 if (tg3_restart_hw(tp, 1))
12589 goto out;
1da177e4
LT		 12590
12591 tp->timer.expires = jiffies + tp->timer_offset;
12592 add_timer(&tp->timer);
12593
12594 netif_device_attach(dev);
12595 tg3_netif_start(tp);
12596
b9ec6c1b 12597out:
f47c11ee 12598 tg3_full_unlock(tp);
1da177e4
LT		 12599 }
12600
12601 return err;
12602}
12603
12604static int tg3_resume(struct pci_dev *pdev)
12605{
12606 struct net_device *dev = pci_get_drvdata(pdev);
12607 struct tg3 *tp = netdev_priv(dev);
12608 int err;
12609
3e0c95fd
MC		 12610 pci_restore_state(tp->pdev);
12611
1da177e4
LT		 12612 if (!netif_running(dev))
12613 return 0;
12614
bc1c7567 12615 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12616 if (err)
12617 return err;
12618
2fbe43f6
MC		 12619 /* Hardware bug - MSI won't work if INTX disabled. */
12620 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
12621 (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
12622 pci_intx(tp->pdev, 1);
12623
1da177e4
LT		 12624 netif_device_attach(dev);
12625
f47c11ee 12626 tg3_full_lock(tp, 0);
1da177e4 12627
6a9eba15 12628 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12629 err = tg3_restart_hw(tp, 1);
12630 if (err)
12631 goto out;
1da177e4
LT		 12632
12633 tp->timer.expires = jiffies + tp->timer_offset;
12634 add_timer(&tp->timer);
12635
1da177e4
LT		 12636 tg3_netif_start(tp);
12637
b9ec6c1b 12638out:
f47c11ee 12639 tg3_full_unlock(tp);
1da177e4 12640
b9ec6c1b 12641 return err;
1da177e4
LT		 12642}
12643
12644static struct pci_driver tg3_driver = {
12645 .name = DRV_MODULE_NAME,
12646 .id_table = tg3_pci_tbl,
12647 .probe = tg3_init_one,
12648 .remove = __devexit_p(tg3_remove_one),
12649 .suspend = tg3_suspend,
12650 .resume = tg3_resume
12651};
12652
12653static int __init tg3_init(void)
12654{
29917620 12655 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12656}
12657
12658static void __exit tg3_cleanup(void)
12659{
12660 pci_unregister_driver(&tg3_driver);
12661}
12662
12663module_init(tg3_init);
12664module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree