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[TG3]: Prescaler fix
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
c9bdd4b5 43#include <net/ip.h>
1da177e4
LT		 44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
49b6e95f 50#ifdef CONFIG_SPARC
1da177e4 51#include <asm/idprom.h>
49b6e95f 52#include <asm/prom.h>
1da177e4
LT		 53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
33b0c4fe
MC		 67#define DRV_MODULE_VERSION "3.85"
68#define DRV_MODULE_RELDATE "October 18, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
212 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
213 {}
1da177e4
LT		 214};
215
216MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
217
50da859d 218static const struct {
1da177e4
LT		 219 const char string[ETH_GSTRING_LEN];
220} ethtool_stats_keys[TG3_NUM_STATS] = {
221 { "rx_octets" },
222 { "rx_fragments" },
223 { "rx_ucast_packets" },
224 { "rx_mcast_packets" },
225 { "rx_bcast_packets" },
226 { "rx_fcs_errors" },
227 { "rx_align_errors" },
228 { "rx_xon_pause_rcvd" },
229 { "rx_xoff_pause_rcvd" },
230 { "rx_mac_ctrl_rcvd" },
231 { "rx_xoff_entered" },
232 { "rx_frame_too_long_errors" },
233 { "rx_jabbers" },
234 { "rx_undersize_packets" },
235 { "rx_in_length_errors" },
236 { "rx_out_length_errors" },
237 { "rx_64_or_less_octet_packets" },
238 { "rx_65_to_127_octet_packets" },
239 { "rx_128_to_255_octet_packets" },
240 { "rx_256_to_511_octet_packets" },
241 { "rx_512_to_1023_octet_packets" },
242 { "rx_1024_to_1522_octet_packets" },
243 { "rx_1523_to_2047_octet_packets" },
244 { "rx_2048_to_4095_octet_packets" },
245 { "rx_4096_to_8191_octet_packets" },
246 { "rx_8192_to_9022_octet_packets" },
247
248 { "tx_octets" },
249 { "tx_collisions" },
250
251 { "tx_xon_sent" },
252 { "tx_xoff_sent" },
253 { "tx_flow_control" },
254 { "tx_mac_errors" },
255 { "tx_single_collisions" },
256 { "tx_mult_collisions" },
257 { "tx_deferred" },
258 { "tx_excessive_collisions" },
259 { "tx_late_collisions" },
260 { "tx_collide_2times" },
261 { "tx_collide_3times" },
262 { "tx_collide_4times" },
263 { "tx_collide_5times" },
264 { "tx_collide_6times" },
265 { "tx_collide_7times" },
266 { "tx_collide_8times" },
267 { "tx_collide_9times" },
268 { "tx_collide_10times" },
269 { "tx_collide_11times" },
270 { "tx_collide_12times" },
271 { "tx_collide_13times" },
272 { "tx_collide_14times" },
273 { "tx_collide_15times" },
274 { "tx_ucast_packets" },
275 { "tx_mcast_packets" },
276 { "tx_bcast_packets" },
277 { "tx_carrier_sense_errors" },
278 { "tx_discards" },
279 { "tx_errors" },
280
281 { "dma_writeq_full" },
282 { "dma_write_prioq_full" },
283 { "rxbds_empty" },
284 { "rx_discards" },
285 { "rx_errors" },
286 { "rx_threshold_hit" },
287
288 { "dma_readq_full" },
289 { "dma_read_prioq_full" },
290 { "tx_comp_queue_full" },
291
292 { "ring_set_send_prod_index" },
293 { "ring_status_update" },
294 { "nic_irqs" },
295 { "nic_avoided_irqs" },
296 { "nic_tx_threshold_hit" }
297};
298
50da859d 299static const struct {
4cafd3f5
MC		 300 const char string[ETH_GSTRING_LEN];
301} ethtool_test_keys[TG3_NUM_TEST] = {
302 { "nvram test (online) " },
303 { "link test (online) " },
304 { "register test (offline)" },
305 { "memory test (offline)" },
306 { "loopback test (offline)" },
307 { "interrupt test (offline)" },
308};
309
b401e9e2
MC		 310static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
311{
312 writel(val, tp->regs + off);
313}
314
315static u32 tg3_read32(struct tg3 *tp, u32 off)
316{
6aa20a22 317 return (readl(tp->regs + off));
b401e9e2
MC		 318}
319
0d3031d9
MC		 320static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
321{
322 writel(val, tp->aperegs + off);
323}
324
325static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
326{
327 return (readl(tp->aperegs + off));
328}
329
1da177e4
LT		 330static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
331{
6892914f
MC		 332 unsigned long flags;
333
334 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 335 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
336 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 337 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 338}
339
340static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
341{
342 writel(val, tp->regs + off);
343 readl(tp->regs + off);
1da177e4
LT		 344}
345
6892914f 346static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 347{
6892914f
MC		 348 unsigned long flags;
349 u32 val;
350
351 spin_lock_irqsave(&tp->indirect_lock, flags);
352 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
353 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
354 spin_unlock_irqrestore(&tp->indirect_lock, flags);
355 return val;
356}
357
358static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
359{
360 unsigned long flags;
361
362 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
363 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
364 TG3_64BIT_REG_LOW, val);
365 return;
366 }
367 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
369 TG3_64BIT_REG_LOW, val);
370 return;
1da177e4 371 }
6892914f
MC		 372
373 spin_lock_irqsave(&tp->indirect_lock, flags);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
375 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
376 spin_unlock_irqrestore(&tp->indirect_lock, flags);
377
378 /* In indirect mode when disabling interrupts, we also need
379 * to clear the interrupt bit in the GRC local ctrl register.
380 */
381 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
382 (val == 0x1)) {
383 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
384 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
385 }
386}
387
388static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
389{
390 unsigned long flags;
391 u32 val;
392
393 spin_lock_irqsave(&tp->indirect_lock, flags);
394 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
395 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
396 spin_unlock_irqrestore(&tp->indirect_lock, flags);
397 return val;
398}
399
b401e9e2
MC		 400/* usec_wait specifies the wait time in usec when writing to certain registers
401 * where it is unsafe to read back the register without some delay.
402 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
403 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
404 */
405static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 406{
b401e9e2
MC		 407 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
408 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
409 /* Non-posted methods */
410 tp->write32(tp, off, val);
411 else {
412 /* Posted method */
413 tg3_write32(tp, off, val);
414 if (usec_wait)
415 udelay(usec_wait);
416 tp->read32(tp, off);
417 }
418 /* Wait again after the read for the posted method to guarantee that
419 * the wait time is met.
420 */
421 if (usec_wait)
422 udelay(usec_wait);
1da177e4
LT		 423}
424
09ee929c
MC		 425static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
426{
427 tp->write32_mbox(tp, off, val);
6892914f
MC		 428 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
429 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 tp->read32_mbox(tp, off);
09ee929c
MC		 431}
432
20094930 433static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 434{
435 void __iomem *mbox = tp->regs + off;
436 writel(val, mbox);
437 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
438 writel(val, mbox);
439 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
440 readl(mbox);
441}
442
b5d3772c
MC		 443static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
444{
445 return (readl(tp->regs + off + GRCMBOX_BASE));
446}
447
448static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
449{
450 writel(val, tp->regs + off + GRCMBOX_BASE);
451}
452
20094930 453#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 454#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 455#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
456#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 457#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 458
459#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 460#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
461#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 462#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 463
464static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
465{
6892914f
MC		 466 unsigned long flags;
467
b5d3772c
MC		 468 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
469 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
470 return;
471
6892914f 472 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 473 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 476
bbadf503
MC		 477 /* Always leave this as zero. */
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
479 } else {
480 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
481 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 482
bbadf503
MC		 483 /* Always leave this as zero. */
484 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
485 }
486 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 487}
488
1da177e4
LT		 489static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
490{
6892914f
MC		 491 unsigned long flags;
492
b5d3772c
MC		 493 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
494 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
495 *val = 0;
496 return;
497 }
498
6892914f 499 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 } else {
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 *val = tr32(TG3PCI_MEM_WIN_DATA);
509
510 /* Always leave this as zero. */
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
512 }
6892914f 513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 514}
515
0d3031d9
MC		 516static void tg3_ape_lock_init(struct tg3 *tp)
517{
518 int i;
519
520 /* Make sure the driver hasn't any stale locks. */
521 for (i = 0; i < 8; i++)
522 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
523 APE_LOCK_GRANT_DRIVER);
524}
525
526static int tg3_ape_lock(struct tg3 *tp, int locknum)
527{
528 int i, off;
529 int ret = 0;
530 u32 status;
531
532 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
533 return 0;
534
535 switch (locknum) {
536 case TG3_APE_LOCK_MEM:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 off = 4 * locknum;
543
544 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
545
546 /* Wait for up to 1 millisecond to acquire lock. */
547 for (i = 0; i < 100; i++) {
548 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
549 if (status == APE_LOCK_GRANT_DRIVER)
550 break;
551 udelay(10);
552 }
553
554 if (status != APE_LOCK_GRANT_DRIVER) {
555 /* Revoke the lock request. */
556 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
557 APE_LOCK_GRANT_DRIVER);
558
559 ret = -EBUSY;
560 }
561
562 return ret;
563}
564
565static void tg3_ape_unlock(struct tg3 *tp, int locknum)
566{
567 int off;
568
569 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
570 return;
571
572 switch (locknum) {
573 case TG3_APE_LOCK_MEM:
574 break;
575 default:
576 return;
577 }
578
579 off = 4 * locknum;
580 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
581}
582
1da177e4
LT		 583static void tg3_disable_ints(struct tg3 *tp)
584{
585 tw32(TG3PCI_MISC_HOST_CTRL,
586 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 588}
589
590static inline void tg3_cond_int(struct tg3 *tp)
591{
38f3843e
MC		 592 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
593 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 594 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 595 else
596 tw32(HOSTCC_MODE, tp->coalesce_mode |
597 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 598}
599
600static void tg3_enable_ints(struct tg3 *tp)
601{
bbe832c0
MC		 602 tp->irq_sync = 0;
603 wmb();
604
1da177e4
LT		 605 tw32(TG3PCI_MISC_HOST_CTRL,
606 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 607 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
608 (tp->last_tag << 24));
fcfa0a32
MC		 609 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611 (tp->last_tag << 24));
1da177e4
LT		 612 tg3_cond_int(tp);
613}
614
04237ddd
MC		 615static inline unsigned int tg3_has_work(struct tg3 *tp)
616{
617 struct tg3_hw_status *sblk = tp->hw_status;
618 unsigned int work_exists = 0;
619
620 /* check for phy events */
621 if (!(tp->tg3_flags &
622 (TG3_FLAG_USE_LINKCHG_REG |
623 TG3_FLAG_POLL_SERDES))) {
624 if (sblk->status & SD_STATUS_LINK_CHG)
625 work_exists = 1;
626 }
627 /* check for RX/TX work to do */
628 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
629 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
630 work_exists = 1;
631
632 return work_exists;
633}
634
1da177e4 635/* tg3_restart_ints
04237ddd
MC		 636 * similar to tg3_enable_ints, but it accurately determines whether there
637 * is new work pending and can return without flushing the PIO write
6aa20a22 638 * which reenables interrupts
1da177e4
LT		 639 */
640static void tg3_restart_ints(struct tg3 *tp)
641{
fac9b83e
DM		 642 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
643 tp->last_tag << 24);
1da177e4
LT		 644 mmiowb();
645
fac9b83e
DM		 646 /* When doing tagged status, this work check is unnecessary.
647 * The last_tag we write above tells the chip which piece of
648 * work we've completed.
649 */
650 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
651 tg3_has_work(tp))
04237ddd
MC		 652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 654}
655
656static inline void tg3_netif_stop(struct tg3 *tp)
657{
bbe832c0 658 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 659 napi_disable(&tp->napi);
1da177e4
LT		 660 netif_tx_disable(tp->dev);
661}
662
663static inline void tg3_netif_start(struct tg3 *tp)
664{
665 netif_wake_queue(tp->dev);
666 /* NOTE: unconditional netif_wake_queue is only appropriate
667 * so long as all callers are assured to have free tx slots
668 * (such as after tg3_init_hw)
669 */
bea3348e 670 napi_enable(&tp->napi);
f47c11ee
DM		 671 tp->hw_status->status |= SD_STATUS_UPDATED;
672 tg3_enable_ints(tp);
1da177e4
LT		 673}
674
675static void tg3_switch_clocks(struct tg3 *tp)
676{
677 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
678 u32 orig_clock_ctrl;
679
795d01c5
MC		 680 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
681 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 682 return;
683
1da177e4
LT		 684 orig_clock_ctrl = clock_ctrl;
685 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
686 CLOCK_CTRL_CLKRUN_OENABLE |
687 0x1f);
688 tp->pci_clock_ctrl = clock_ctrl;
689
690 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
691 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 692 tw32_wait_f(TG3PCI_CLOCK_CTRL,
693 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 694 }
695 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 696 tw32_wait_f(TG3PCI_CLOCK_CTRL,
697 clock_ctrl |
698 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
699 40);
700 tw32_wait_f(TG3PCI_CLOCK_CTRL,
701 clock_ctrl | (CLOCK_CTRL_ALTCLK),
702 40);
1da177e4 703 }
b401e9e2 704 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 705}
706
707#define PHY_BUSY_LOOPS 5000
708
709static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
710{
711 u32 frame_val;
712 unsigned int loops;
713 int ret;
714
715 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
716 tw32_f(MAC_MI_MODE,
717 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
718 udelay(80);
719 }
720
721 *val = 0x0;
722
723 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
724 MI_COM_PHY_ADDR_MASK);
725 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
726 MI_COM_REG_ADDR_MASK);
727 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 728
1da177e4
LT		 729 tw32_f(MAC_MI_COM, frame_val);
730
731 loops = PHY_BUSY_LOOPS;
732 while (loops != 0) {
733 udelay(10);
734 frame_val = tr32(MAC_MI_COM);
735
736 if ((frame_val & MI_COM_BUSY) == 0) {
737 udelay(5);
738 frame_val = tr32(MAC_MI_COM);
739 break;
740 }
741 loops -= 1;
742 }
743
744 ret = -EBUSY;
745 if (loops != 0) {
746 *val = frame_val & MI_COM_DATA_MASK;
747 ret = 0;
748 }
749
750 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
751 tw32_f(MAC_MI_MODE, tp->mi_mode);
752 udelay(80);
753 }
754
755 return ret;
756}
757
758static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
759{
760 u32 frame_val;
761 unsigned int loops;
762 int ret;
763
b5d3772c
MC		 764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
765 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
766 return 0;
767
1da177e4
LT		 768 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
769 tw32_f(MAC_MI_MODE,
770 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
771 udelay(80);
772 }
773
774 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
775 MI_COM_PHY_ADDR_MASK);
776 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
777 MI_COM_REG_ADDR_MASK);
778 frame_val |= (val & MI_COM_DATA_MASK);
779 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 780
1da177e4
LT		 781 tw32_f(MAC_MI_COM, frame_val);
782
783 loops = PHY_BUSY_LOOPS;
784 while (loops != 0) {
785 udelay(10);
786 frame_val = tr32(MAC_MI_COM);
787 if ((frame_val & MI_COM_BUSY) == 0) {
788 udelay(5);
789 frame_val = tr32(MAC_MI_COM);
790 break;
791 }
792 loops -= 1;
793 }
794
795 ret = -EBUSY;
796 if (loops != 0)
797 ret = 0;
798
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE, tp->mi_mode);
801 udelay(80);
802 }
803
804 return ret;
805}
806
9ef8ca99
MC		 807static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
808{
809 u32 phy;
810
811 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
812 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
813 return;
814
815 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
816 u32 ephy;
817
818 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
819 tg3_writephy(tp, MII_TG3_EPHY_TEST,
820 ephy | MII_TG3_EPHY_SHADOW_EN);
821 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
822 if (enable)
823 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
824 else
825 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
826 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
827 }
828 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
829 }
830 } else {
831 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
832 MII_TG3_AUXCTL_SHDWSEL_MISC;
833 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
834 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
835 if (enable)
836 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
837 else
838 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
839 phy |= MII_TG3_AUXCTL_MISC_WREN;
840 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
841 }
842 }
843}
844
1da177e4
LT		 845static void tg3_phy_set_wirespeed(struct tg3 *tp)
846{
847 u32 val;
848
849 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
850 return;
851
852 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
853 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
854 tg3_writephy(tp, MII_TG3_AUX_CTRL,
855 (val | (1 << 15) | (1 << 4)));
856}
857
858static int tg3_bmcr_reset(struct tg3 *tp)
859{
860 u32 phy_control;
861 int limit, err;
862
863 /* OK, reset it, and poll the BMCR_RESET bit until it
864 * clears or we time out.
865 */
866 phy_control = BMCR_RESET;
867 err = tg3_writephy(tp, MII_BMCR, phy_control);
868 if (err != 0)
869 return -EBUSY;
870
871 limit = 5000;
872 while (limit--) {
873 err = tg3_readphy(tp, MII_BMCR, &phy_control);
874 if (err != 0)
875 return -EBUSY;
876
877 if ((phy_control & BMCR_RESET) == 0) {
878 udelay(40);
879 break;
880 }
881 udelay(10);
882 }
883 if (limit <= 0)
884 return -EBUSY;
885
886 return 0;
887}
888
889static int tg3_wait_macro_done(struct tg3 *tp)
890{
891 int limit = 100;
892
893 while (limit--) {
894 u32 tmp32;
895
896 if (!tg3_readphy(tp, 0x16, &tmp32)) {
897 if ((tmp32 & 0x1000) == 0)
898 break;
899 }
900 }
901 if (limit <= 0)
902 return -EBUSY;
903
904 return 0;
905}
906
907static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
908{
909 static const u32 test_pat[4][6] = {
910 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
911 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
912 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
913 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
914 };
915 int chan;
916
917 for (chan = 0; chan < 4; chan++) {
918 int i;
919
920 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
921 (chan * 0x2000) | 0x0200);
922 tg3_writephy(tp, 0x16, 0x0002);
923
924 for (i = 0; i < 6; i++)
925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
926 test_pat[chan][i]);
927
928 tg3_writephy(tp, 0x16, 0x0202);
929 if (tg3_wait_macro_done(tp)) {
930 *resetp = 1;
931 return -EBUSY;
932 }
933
934 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
935 (chan * 0x2000) | 0x0200);
936 tg3_writephy(tp, 0x16, 0x0082);
937 if (tg3_wait_macro_done(tp)) {
938 *resetp = 1;
939 return -EBUSY;
940 }
941
942 tg3_writephy(tp, 0x16, 0x0802);
943 if (tg3_wait_macro_done(tp)) {
944 *resetp = 1;
945 return -EBUSY;
946 }
947
948 for (i = 0; i < 6; i += 2) {
949 u32 low, high;
950
951 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
952 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
953 tg3_wait_macro_done(tp)) {
954 *resetp = 1;
955 return -EBUSY;
956 }
957 low &= 0x7fff;
958 high &= 0x000f;
959 if (low != test_pat[chan][i] ||
960 high != test_pat[chan][i+1]) {
961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
962 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
964
965 return -EBUSY;
966 }
967 }
968 }
969
970 return 0;
971}
972
973static int tg3_phy_reset_chanpat(struct tg3 *tp)
974{
975 int chan;
976
977 for (chan = 0; chan < 4; chan++) {
978 int i;
979
980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
981 (chan * 0x2000) | 0x0200);
982 tg3_writephy(tp, 0x16, 0x0002);
983 for (i = 0; i < 6; i++)
984 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
985 tg3_writephy(tp, 0x16, 0x0202);
986 if (tg3_wait_macro_done(tp))
987 return -EBUSY;
988 }
989
990 return 0;
991}
992
993static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
994{
995 u32 reg32, phy9_orig;
996 int retries, do_phy_reset, err;
997
998 retries = 10;
999 do_phy_reset = 1;
1000 do {
1001 if (do_phy_reset) {
1002 err = tg3_bmcr_reset(tp);
1003 if (err)
1004 return err;
1005 do_phy_reset = 0;
1006 }
1007
1008 /* Disable transmitter and interrupt. */
1009 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1010 continue;
1011
1012 reg32 |= 0x3000;
1013 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1014
1015 /* Set full-duplex, 1000 mbps. */
1016 tg3_writephy(tp, MII_BMCR,
1017 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1018
1019 /* Set to master mode. */
1020 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1021 continue;
1022
1023 tg3_writephy(tp, MII_TG3_CTRL,
1024 (MII_TG3_CTRL_AS_MASTER |
1025 MII_TG3_CTRL_ENABLE_AS_MASTER));
1026
1027 /* Enable SM_DSP_CLOCK and 6dB. */
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029
1030 /* Block the PHY control access. */
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1033
1034 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1035 if (!err)
1036 break;
1037 } while (--retries);
1038
1039 err = tg3_phy_reset_chanpat(tp);
1040 if (err)
1041 return err;
1042
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1045
1046 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1047 tg3_writephy(tp, 0x16, 0x0000);
1048
1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1051 /* Set Extended packet length bit for jumbo frames */
1052 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1053 }
1054 else {
1055 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1056 }
1057
1058 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1059
1060 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1061 reg32 &= ~0x3000;
1062 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063 } else if (!err)
1064 err = -EBUSY;
1065
1066 return err;
1067}
1068
c8e1e82b
MC		 1069static void tg3_link_report(struct tg3 *);
1070
1da177e4
LT		 1071/* This will reset the tigon3 PHY if there is no valid
1072 * link unless the FORCE argument is non-zero.
1073 */
1074static int tg3_phy_reset(struct tg3 *tp)
1075{
1076 u32 phy_status;
1077 int err;
1078
60189ddf
MC		 1079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1080 u32 val;
1081
1082 val = tr32(GRC_MISC_CFG);
1083 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1084 udelay(40);
1085 }
1da177e4
LT		 1086 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1087 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1088 if (err != 0)
1089 return -EBUSY;
1090
c8e1e82b
MC		 1091 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1092 netif_carrier_off(tp->dev);
1093 tg3_link_report(tp);
1094 }
1095
1da177e4
LT		 1096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1099 err = tg3_phy_reset_5703_4_5(tp);
1100 if (err)
1101 return err;
1102 goto out;
1103 }
1104
1105 err = tg3_bmcr_reset(tp);
1106 if (err)
1107 return err;
1108
ce057f01
MC		 1109 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
1110 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0) {
1111 u32 val;
1112
1113 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1114 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1115 CPMU_LSPD_1000MB_MACCLK_12_5) {
1116 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1117 udelay(40);
1118 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1119 }
662f38d2
MC		 1120
1121 /* Disable GPHY autopowerdown. */
1122 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1123 MII_TG3_MISC_SHDW_WREN |
1124 MII_TG3_MISC_SHDW_APD_SEL |
1125 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
ce057f01
MC		 1126 }
1127
1da177e4
LT		 1128out:
1129 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1130 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1131 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1132 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1133 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1134 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1135 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1136 }
1137 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1138 tg3_writephy(tp, 0x1c, 0x8d68);
1139 tg3_writephy(tp, 0x1c, 0x8d68);
1140 }
1141 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1142 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1143 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1144 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1145 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1146 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1147 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1148 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1149 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1150 }
c424cb24
MC		 1151 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1152 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1153 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1154 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1155 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1156 tg3_writephy(tp, MII_TG3_TEST1,
1157 MII_TG3_TEST1_TRIM_EN | 0x4);
1158 } else
1159 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1160 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1161 }
1da177e4
LT		 1162 /* Set Extended packet length bit (bit 14) on all chips that */
1163 /* support jumbo frames */
1164 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1165 /* Cannot do read-modify-write on 5401 */
1166 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1167 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1168 u32 phy_reg;
1169
1170 /* Set bit 14 with read-modify-write to preserve other bits */
1171 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1172 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1173 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1174 }
1175
1176 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1177 * jumbo frames transmission.
1178 */
0f893dc6 1179 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1180 u32 phy_reg;
1181
1182 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1183 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1184 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1185 }
1186
715116a1 1187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1188 /* adjust output voltage */
1189 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1190 }
1191
9ef8ca99 1192 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1193 tg3_phy_set_wirespeed(tp);
1194 return 0;
1195}
1196
1197static void tg3_frob_aux_power(struct tg3 *tp)
1198{
1199 struct tg3 *tp_peer = tp;
1200
9d26e213 1201 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1202 return;
1203
8c2dc7e1
MC		 1204 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1205 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1206 struct net_device *dev_peer;
1207
1208 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1209 /* remove_one() may have been run on the peer. */
8c2dc7e1 1210 if (!dev_peer)
bc1c7567
MC		 1211 tp_peer = tp;
1212 else
1213 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1214 }
1215
1da177e4 1216 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1217 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1218 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1219 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1222 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1223 (GRC_LCLCTRL_GPIO_OE0 |
1224 GRC_LCLCTRL_GPIO_OE1 |
1225 GRC_LCLCTRL_GPIO_OE2 |
1226 GRC_LCLCTRL_GPIO_OUTPUT0 |
1227 GRC_LCLCTRL_GPIO_OUTPUT1),
1228 100);
1da177e4
LT		 1229 } else {
1230 u32 no_gpio2;
dc56b7d4 1231 u32 grc_local_ctrl = 0;
1da177e4
LT		 1232
1233 if (tp_peer != tp &&
1234 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1235 return;
1236
dc56b7d4
MC		 1237 /* Workaround to prevent overdrawing Amps. */
1238 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1239 ASIC_REV_5714) {
1240 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1241 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1242 grc_local_ctrl, 100);
dc56b7d4
MC		 1243 }
1244
1da177e4
LT		 1245 /* On 5753 and variants, GPIO2 cannot be used. */
1246 no_gpio2 = tp->nic_sram_data_cfg &
1247 NIC_SRAM_DATA_CFG_NO_GPIO2;
1248
dc56b7d4 1249 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1250 GRC_LCLCTRL_GPIO_OE1 |
1251 GRC_LCLCTRL_GPIO_OE2 |
1252 GRC_LCLCTRL_GPIO_OUTPUT1 |
1253 GRC_LCLCTRL_GPIO_OUTPUT2;
1254 if (no_gpio2) {
1255 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1256 GRC_LCLCTRL_GPIO_OUTPUT2);
1257 }
b401e9e2
MC		 1258 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1259 grc_local_ctrl, 100);
1da177e4
LT		 1260
1261 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1262
b401e9e2
MC		 1263 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1264 grc_local_ctrl, 100);
1da177e4
LT		 1265
1266 if (!no_gpio2) {
1267 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1268 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1269 grc_local_ctrl, 100);
1da177e4
LT		 1270 }
1271 }
1272 } else {
1273 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1274 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1275 if (tp_peer != tp &&
1276 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1277 return;
1278
b401e9e2
MC		 1279 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1280 (GRC_LCLCTRL_GPIO_OE1 |
1281 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1282
b401e9e2
MC		 1283 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1284 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1285
b401e9e2
MC		 1286 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1287 (GRC_LCLCTRL_GPIO_OE1 |
1288 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1289 }
1290 }
1291}
1292
e8f3f6ca
MC		 1293static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1294{
1295 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1296 return 1;
1297 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1298 if (speed != SPEED_10)
1299 return 1;
1300 } else if (speed == SPEED_10)
1301 return 1;
1302
1303 return 0;
1304}
1305
1da177e4
LT		 1306static int tg3_setup_phy(struct tg3 *, int);
1307
1308#define RESET_KIND_SHUTDOWN 0
1309#define RESET_KIND_INIT 1
1310#define RESET_KIND_SUSPEND 2
1311
1312static void tg3_write_sig_post_reset(struct tg3 *, int);
1313static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1314static int tg3_nvram_lock(struct tg3 *);
1315static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1316
15c3b696
MC		 1317static void tg3_power_down_phy(struct tg3 *tp)
1318{
ce057f01
MC		 1319 u32 val;
1320
5129724a
MC		 1321 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1323 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1324 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1325
1326 sg_dig_ctrl |=
1327 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1328 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1329 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1330 }
3f7045c1 1331 return;
5129724a 1332 }
3f7045c1 1333
60189ddf 1334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 1335 tg3_bmcr_reset(tp);
1336 val = tr32(GRC_MISC_CFG);
1337 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1338 udelay(40);
1339 return;
1340 } else {
715116a1
MC		 1341 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1342 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1343 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1344 }
3f7045c1 1345
15c3b696
MC		 1346 /* The PHY should not be powered down on some chips because
1347 * of bugs.
1348 */
1349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1351 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1352 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1353 return;
ce057f01
MC		 1354
1355 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
1356 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0) {
1357 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1358 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1359 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1360 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1361 }
1362
15c3b696
MC		 1363 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1364}
1365
bc1c7567 1366static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1367{
1368 u32 misc_host_ctrl;
1369 u16 power_control, power_caps;
1370 int pm = tp->pm_cap;
1371
1372 /* Make sure register accesses (indirect or otherwise)
1373 * will function correctly.
1374 */
1375 pci_write_config_dword(tp->pdev,
1376 TG3PCI_MISC_HOST_CTRL,
1377 tp->misc_host_ctrl);
1378
1379 pci_read_config_word(tp->pdev,
1380 pm + PCI_PM_CTRL,
1381 &power_control);
1382 power_control |= PCI_PM_CTRL_PME_STATUS;
1383 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1384 switch (state) {
bc1c7567 1385 case PCI_D0:
1da177e4
LT		 1386 power_control |= 0;
1387 pci_write_config_word(tp->pdev,
1388 pm + PCI_PM_CTRL,
1389 power_control);
8c6bda1a
MC		 1390 udelay(100); /* Delay after power state change */
1391
9d26e213
MC		 1392 /* Switch out of Vaux if it is a NIC */
1393 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1394 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1395
1396 return 0;
1397
bc1c7567 1398 case PCI_D1:
1da177e4
LT		 1399 power_control |= 1;
1400 break;
1401
bc1c7567 1402 case PCI_D2:
1da177e4
LT		 1403 power_control |= 2;
1404 break;
1405
bc1c7567 1406 case PCI_D3hot:
1da177e4
LT		 1407 power_control |= 3;
1408 break;
1409
1410 default:
1411 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1412 "requested.\n",
1413 tp->dev->name, state);
1414 return -EINVAL;
1415 };
1416
1417 power_control |= PCI_PM_CTRL_PME_ENABLE;
1418
1419 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1420 tw32(TG3PCI_MISC_HOST_CTRL,
1421 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1422
1423 if (tp->link_config.phy_is_low_power == 0) {
1424 tp->link_config.phy_is_low_power = 1;
1425 tp->link_config.orig_speed = tp->link_config.speed;
1426 tp->link_config.orig_duplex = tp->link_config.duplex;
1427 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1428 }
1429
747e8f8b 1430 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1431 tp->link_config.speed = SPEED_10;
1432 tp->link_config.duplex = DUPLEX_HALF;
1433 tp->link_config.autoneg = AUTONEG_ENABLE;
1434 tg3_setup_phy(tp, 0);
1435 }
1436
b5d3772c
MC		 1437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1438 u32 val;
1439
1440 val = tr32(GRC_VCPU_EXT_CTRL);
1441 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1442 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1443 int i;
1444 u32 val;
1445
1446 for (i = 0; i < 200; i++) {
1447 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1448 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1449 break;
1450 msleep(1);
1451 }
1452 }
a85feb8c
GZ		 1453 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1454 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1455 WOL_DRV_STATE_SHUTDOWN |
1456 WOL_DRV_WOL |
1457 WOL_SET_MAGIC_PKT);
6921d201 1458
1da177e4
LT		 1459 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1460
1461 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1462 u32 mac_mode;
1463
1464 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1465 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1466 udelay(40);
1467
3f7045c1
MC		 1468 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1469 mac_mode = MAC_MODE_PORT_MODE_GMII;
1470 else
1471 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 1472
e8f3f6ca
MC		 1473 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1474 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1475 ASIC_REV_5700) {
1476 u32 speed = (tp->tg3_flags &
1477 TG3_FLAG_WOL_SPEED_100MB) ?
1478 SPEED_100 : SPEED_10;
1479 if (tg3_5700_link_polarity(tp, speed))
1480 mac_mode |= MAC_MODE_LINK_POLARITY;
1481 else
1482 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1483 }
1da177e4
LT		 1484 } else {
1485 mac_mode = MAC_MODE_PORT_MODE_TBI;
1486 }
1487
cbf46853 1488 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1489 tw32(MAC_LED_CTRL, tp->led_ctrl);
1490
1491 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1492 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1493 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1494
1495 tw32_f(MAC_MODE, mac_mode);
1496 udelay(100);
1497
1498 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1499 udelay(10);
1500 }
1501
1502 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1503 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1505 u32 base_val;
1506
1507 base_val = tp->pci_clock_ctrl;
1508 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1509 CLOCK_CTRL_TXCLK_DISABLE);
1510
b401e9e2
MC		 1511 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1512 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 1513 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 1514 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 1515 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1516 /* do nothing */
85e94ced 1517 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1518 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1519 u32 newbits1, newbits2;
1520
1521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1523 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1524 CLOCK_CTRL_TXCLK_DISABLE |
1525 CLOCK_CTRL_ALTCLK);
1526 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1527 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1528 newbits1 = CLOCK_CTRL_625_CORE;
1529 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1530 } else {
1531 newbits1 = CLOCK_CTRL_ALTCLK;
1532 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1533 }
1534
b401e9e2
MC		 1535 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1536 40);
1da177e4 1537
b401e9e2
MC		 1538 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1539 40);
1da177e4
LT		 1540
1541 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1542 u32 newbits3;
1543
1544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1546 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1547 CLOCK_CTRL_TXCLK_DISABLE |
1548 CLOCK_CTRL_44MHZ_CORE);
1549 } else {
1550 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1551 }
1552
b401e9e2
MC		 1553 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1554 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1555 }
1556 }
1557
6921d201 1558 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
0d3031d9
MC		 1559 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1560 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
3f7045c1 1561 tg3_power_down_phy(tp);
6921d201 1562
1da177e4
LT		 1563 tg3_frob_aux_power(tp);
1564
1565 /* Workaround for unstable PLL clock */
1566 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1567 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1568 u32 val = tr32(0x7d00);
1569
1570 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1571 tw32(0x7d00, val);
6921d201 1572 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1573 int err;
1574
1575 err = tg3_nvram_lock(tp);
1da177e4 1576 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1577 if (!err)
1578 tg3_nvram_unlock(tp);
6921d201 1579 }
1da177e4
LT		 1580 }
1581
bbadf503
MC		 1582 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1583
1da177e4
LT		 1584 /* Finally, set the new power state. */
1585 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1586 udelay(100); /* Delay after power state change */
1da177e4 1587
1da177e4
LT		 1588 return 0;
1589}
1590
1591static void tg3_link_report(struct tg3 *tp)
1592{
1593 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1594 if (netif_msg_link(tp))
1595 printk(KERN_INFO PFX "%s: Link is down.\n",
1596 tp->dev->name);
1597 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1598 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1599 tp->dev->name,
1600 (tp->link_config.active_speed == SPEED_1000 ?
1601 1000 :
1602 (tp->link_config.active_speed == SPEED_100 ?
1603 100 : 10)),
1604 (tp->link_config.active_duplex == DUPLEX_FULL ?
1605 "full" : "half"));
1606
1607 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1608 "%s for RX.\n",
1609 tp->dev->name,
1610 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1611 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1612 }
1613}
1614
1615static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1616{
1617 u32 new_tg3_flags = 0;
1618 u32 old_rx_mode = tp->rx_mode;
1619 u32 old_tx_mode = tp->tx_mode;
1620
1621 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1622
1623 /* Convert 1000BaseX flow control bits to 1000BaseT
1624 * bits before resolving flow control.
1625 */
1626 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1627 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1628 ADVERTISE_PAUSE_ASYM);
1629 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1630
1631 if (local_adv & ADVERTISE_1000XPAUSE)
1632 local_adv |= ADVERTISE_PAUSE_CAP;
1633 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1634 local_adv |= ADVERTISE_PAUSE_ASYM;
1635 if (remote_adv & LPA_1000XPAUSE)
1636 remote_adv |= LPA_PAUSE_CAP;
1637 if (remote_adv & LPA_1000XPAUSE_ASYM)
1638 remote_adv |= LPA_PAUSE_ASYM;
1639 }
1640
1da177e4
LT		 1641 if (local_adv & ADVERTISE_PAUSE_CAP) {
1642 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1643 if (remote_adv & LPA_PAUSE_CAP)
1644 new_tg3_flags |=
1645 (TG3_FLAG_RX_PAUSE |
1646 TG3_FLAG_TX_PAUSE);
1647 else if (remote_adv & LPA_PAUSE_ASYM)
1648 new_tg3_flags |=
1649 (TG3_FLAG_RX_PAUSE);
1650 } else {
1651 if (remote_adv & LPA_PAUSE_CAP)
1652 new_tg3_flags |=
1653 (TG3_FLAG_RX_PAUSE |
1654 TG3_FLAG_TX_PAUSE);
1655 }
1656 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1657 if ((remote_adv & LPA_PAUSE_CAP) &&
1658 (remote_adv & LPA_PAUSE_ASYM))
1659 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1660 }
1661
1662 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1663 tp->tg3_flags |= new_tg3_flags;
1664 } else {
1665 new_tg3_flags = tp->tg3_flags;
1666 }
1667
1668 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1669 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1670 else
1671 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1672
1673 if (old_rx_mode != tp->rx_mode) {
1674 tw32_f(MAC_RX_MODE, tp->rx_mode);
1675 }
6aa20a22 1676
1da177e4
LT		 1677 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1678 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1679 else
1680 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1681
1682 if (old_tx_mode != tp->tx_mode) {
1683 tw32_f(MAC_TX_MODE, tp->tx_mode);
1684 }
1685}
1686
1687static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1688{
1689 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1690 case MII_TG3_AUX_STAT_10HALF:
1691 *speed = SPEED_10;
1692 *duplex = DUPLEX_HALF;
1693 break;
1694
1695 case MII_TG3_AUX_STAT_10FULL:
1696 *speed = SPEED_10;
1697 *duplex = DUPLEX_FULL;
1698 break;
1699
1700 case MII_TG3_AUX_STAT_100HALF:
1701 *speed = SPEED_100;
1702 *duplex = DUPLEX_HALF;
1703 break;
1704
1705 case MII_TG3_AUX_STAT_100FULL:
1706 *speed = SPEED_100;
1707 *duplex = DUPLEX_FULL;
1708 break;
1709
1710 case MII_TG3_AUX_STAT_1000HALF:
1711 *speed = SPEED_1000;
1712 *duplex = DUPLEX_HALF;
1713 break;
1714
1715 case MII_TG3_AUX_STAT_1000FULL:
1716 *speed = SPEED_1000;
1717 *duplex = DUPLEX_FULL;
1718 break;
1719
1720 default:
715116a1
MC		 1721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1722 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1723 SPEED_10;
1724 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1725 DUPLEX_HALF;
1726 break;
1727 }
1da177e4
LT		 1728 *speed = SPEED_INVALID;
1729 *duplex = DUPLEX_INVALID;
1730 break;
1731 };
1732}
1733
1734static void tg3_phy_copper_begin(struct tg3 *tp)
1735{
1736 u32 new_adv;
1737 int i;
1738
1739 if (tp->link_config.phy_is_low_power) {
1740 /* Entering low power mode. Disable gigabit and
1741 * 100baseT advertisements.
1742 */
1743 tg3_writephy(tp, MII_TG3_CTRL, 0);
1744
1745 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1746 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1747 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1748 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1749
1750 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1751 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1752 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1753 tp->link_config.advertising &=
1754 ~(ADVERTISED_1000baseT_Half |
1755 ADVERTISED_1000baseT_Full);
1756
1757 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1758 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1759 new_adv |= ADVERTISE_10HALF;
1760 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1761 new_adv |= ADVERTISE_10FULL;
1762 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1763 new_adv |= ADVERTISE_100HALF;
1764 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1765 new_adv |= ADVERTISE_100FULL;
1766 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1767
1768 if (tp->link_config.advertising &
1769 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1770 new_adv = 0;
1771 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1772 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1773 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1774 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1775 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1776 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1777 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1778 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1779 MII_TG3_CTRL_ENABLE_AS_MASTER);
1780 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1781 } else {
1782 tg3_writephy(tp, MII_TG3_CTRL, 0);
1783 }
1784 } else {
1785 /* Asking for a specific link mode. */
1786 if (tp->link_config.speed == SPEED_1000) {
1787 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1788 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1789
1790 if (tp->link_config.duplex == DUPLEX_FULL)
1791 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1792 else
1793 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1794 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1795 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1796 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1797 MII_TG3_CTRL_ENABLE_AS_MASTER);
1798 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1799 } else {
1800 tg3_writephy(tp, MII_TG3_CTRL, 0);
1801
1802 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1803 if (tp->link_config.speed == SPEED_100) {
1804 if (tp->link_config.duplex == DUPLEX_FULL)
1805 new_adv |= ADVERTISE_100FULL;
1806 else
1807 new_adv |= ADVERTISE_100HALF;
1808 } else {
1809 if (tp->link_config.duplex == DUPLEX_FULL)
1810 new_adv |= ADVERTISE_10FULL;
1811 else
1812 new_adv |= ADVERTISE_10HALF;
1813 }
1814 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1815 }
1816 }
1817
1818 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1819 tp->link_config.speed != SPEED_INVALID) {
1820 u32 bmcr, orig_bmcr;
1821
1822 tp->link_config.active_speed = tp->link_config.speed;
1823 tp->link_config.active_duplex = tp->link_config.duplex;
1824
1825 bmcr = 0;
1826 switch (tp->link_config.speed) {
1827 default:
1828 case SPEED_10:
1829 break;
1830
1831 case SPEED_100:
1832 bmcr |= BMCR_SPEED100;
1833 break;
1834
1835 case SPEED_1000:
1836 bmcr |= TG3_BMCR_SPEED1000;
1837 break;
1838 };
1839
1840 if (tp->link_config.duplex == DUPLEX_FULL)
1841 bmcr |= BMCR_FULLDPLX;
1842
1843 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1844 (bmcr != orig_bmcr)) {
1845 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1846 for (i = 0; i < 1500; i++) {
1847 u32 tmp;
1848
1849 udelay(10);
1850 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1851 tg3_readphy(tp, MII_BMSR, &tmp))
1852 continue;
1853 if (!(tmp & BMSR_LSTATUS)) {
1854 udelay(40);
1855 break;
1856 }
1857 }
1858 tg3_writephy(tp, MII_BMCR, bmcr);
1859 udelay(40);
1860 }
1861 } else {
1862 tg3_writephy(tp, MII_BMCR,
1863 BMCR_ANENABLE | BMCR_ANRESTART);
1864 }
1865}
1866
1867static int tg3_init_5401phy_dsp(struct tg3 *tp)
1868{
1869 int err;
1870
1871 /* Turn off tap power management. */
1872 /* Set Extended packet length bit */
1873 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1874
1875 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1876 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1877
1878 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1879 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1880
1881 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1882 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1883
1884 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1885 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1886
1887 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1888 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1889
1890 udelay(40);
1891
1892 return err;
1893}
1894
3600d918 1895static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1896{
3600d918
MC		 1897 u32 adv_reg, all_mask = 0;
1898
1899 if (mask & ADVERTISED_10baseT_Half)
1900 all_mask |= ADVERTISE_10HALF;
1901 if (mask & ADVERTISED_10baseT_Full)
1902 all_mask |= ADVERTISE_10FULL;
1903 if (mask & ADVERTISED_100baseT_Half)
1904 all_mask |= ADVERTISE_100HALF;
1905 if (mask & ADVERTISED_100baseT_Full)
1906 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1907
1908 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1909 return 0;
1910
1da177e4
LT		 1911 if ((adv_reg & all_mask) != all_mask)
1912 return 0;
1913 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1914 u32 tg3_ctrl;
1915
3600d918
MC		 1916 all_mask = 0;
1917 if (mask & ADVERTISED_1000baseT_Half)
1918 all_mask |= ADVERTISE_1000HALF;
1919 if (mask & ADVERTISED_1000baseT_Full)
1920 all_mask |= ADVERTISE_1000FULL;
1921
1da177e4
LT		 1922 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1923 return 0;
1924
1da177e4
LT		 1925 if ((tg3_ctrl & all_mask) != all_mask)
1926 return 0;
1927 }
1928 return 1;
1929}
1930
1931static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1932{
1933 int current_link_up;
1934 u32 bmsr, dummy;
1935 u16 current_speed;
1936 u8 current_duplex;
1937 int i, err;
1938
1939 tw32(MAC_EVENT, 0);
1940
1941 tw32_f(MAC_STATUS,
1942 (MAC_STATUS_SYNC_CHANGED |
1943 MAC_STATUS_CFG_CHANGED |
1944 MAC_STATUS_MI_COMPLETION |
1945 MAC_STATUS_LNKSTATE_CHANGED));
1946 udelay(40);
1947
1948 tp->mi_mode = MAC_MI_MODE_BASE;
1949 tw32_f(MAC_MI_MODE, tp->mi_mode);
1950 udelay(80);
1951
1952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1953
1954 /* Some third-party PHYs need to be reset on link going
1955 * down.
1956 */
1957 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1960 netif_carrier_ok(tp->dev)) {
1961 tg3_readphy(tp, MII_BMSR, &bmsr);
1962 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1963 !(bmsr & BMSR_LSTATUS))
1964 force_reset = 1;
1965 }
1966 if (force_reset)
1967 tg3_phy_reset(tp);
1968
1969 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1970 tg3_readphy(tp, MII_BMSR, &bmsr);
1971 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1972 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1973 bmsr = 0;
1974
1975 if (!(bmsr & BMSR_LSTATUS)) {
1976 err = tg3_init_5401phy_dsp(tp);
1977 if (err)
1978 return err;
1979
1980 tg3_readphy(tp, MII_BMSR, &bmsr);
1981 for (i = 0; i < 1000; i++) {
1982 udelay(10);
1983 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1984 (bmsr & BMSR_LSTATUS)) {
1985 udelay(40);
1986 break;
1987 }
1988 }
1989
1990 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1991 !(bmsr & BMSR_LSTATUS) &&
1992 tp->link_config.active_speed == SPEED_1000) {
1993 err = tg3_phy_reset(tp);
1994 if (!err)
1995 err = tg3_init_5401phy_dsp(tp);
1996 if (err)
1997 return err;
1998 }
1999 }
2000 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2001 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2002 /* 5701 {A0,B0} CRC bug workaround */
2003 tg3_writephy(tp, 0x15, 0x0a75);
2004 tg3_writephy(tp, 0x1c, 0x8c68);
2005 tg3_writephy(tp, 0x1c, 0x8d68);
2006 tg3_writephy(tp, 0x1c, 0x8c68);
2007 }
2008
2009 /* Clear pending interrupts... */
2010 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2011 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2012
2013 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2014 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2015 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2016 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2017
2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2020 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2021 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2022 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2023 else
2024 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2025 }
2026
2027 current_link_up = 0;
2028 current_speed = SPEED_INVALID;
2029 current_duplex = DUPLEX_INVALID;
2030
2031 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2032 u32 val;
2033
2034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2035 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2036 if (!(val & (1 << 10))) {
2037 val |= (1 << 10);
2038 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2039 goto relink;
2040 }
2041 }
2042
2043 bmsr = 0;
2044 for (i = 0; i < 100; i++) {
2045 tg3_readphy(tp, MII_BMSR, &bmsr);
2046 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2047 (bmsr & BMSR_LSTATUS))
2048 break;
2049 udelay(40);
2050 }
2051
2052 if (bmsr & BMSR_LSTATUS) {
2053 u32 aux_stat, bmcr;
2054
2055 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2056 for (i = 0; i < 2000; i++) {
2057 udelay(10);
2058 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2059 aux_stat)
2060 break;
2061 }
2062
2063 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2064 &current_speed,
2065 &current_duplex);
2066
2067 bmcr = 0;
2068 for (i = 0; i < 200; i++) {
2069 tg3_readphy(tp, MII_BMCR, &bmcr);
2070 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2071 continue;
2072 if (bmcr && bmcr != 0x7fff)
2073 break;
2074 udelay(10);
2075 }
2076
2077 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2078 if (bmcr & BMCR_ANENABLE) {
2079 current_link_up = 1;
2080
2081 /* Force autoneg restart if we are exiting
2082 * low power mode.
2083 */
3600d918
MC		 2084 if (!tg3_copper_is_advertising_all(tp,
2085 tp->link_config.advertising))
1da177e4
LT		 2086 current_link_up = 0;
2087 } else {
2088 current_link_up = 0;
2089 }
2090 } else {
2091 if (!(bmcr & BMCR_ANENABLE) &&
2092 tp->link_config.speed == current_speed &&
2093 tp->link_config.duplex == current_duplex) {
2094 current_link_up = 1;
2095 } else {
2096 current_link_up = 0;
2097 }
2098 }
2099
2100 tp->link_config.active_speed = current_speed;
2101 tp->link_config.active_duplex = current_duplex;
2102 }
2103
2104 if (current_link_up == 1 &&
2105 (tp->link_config.active_duplex == DUPLEX_FULL) &&
2106 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2107 u32 local_adv, remote_adv;
2108
2109 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
2110 local_adv = 0;
2111 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2112
2113 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2114 remote_adv = 0;
2115
2116 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2117
2118 /* If we are not advertising full pause capability,
2119 * something is wrong. Bring the link down and reconfigure.
2120 */
2121 if (local_adv != ADVERTISE_PAUSE_CAP) {
2122 current_link_up = 0;
2123 } else {
2124 tg3_setup_flow_control(tp, local_adv, remote_adv);
2125 }
2126 }
2127relink:
6921d201 2128 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 2129 u32 tmp;
2130
2131 tg3_phy_copper_begin(tp);
2132
2133 tg3_readphy(tp, MII_BMSR, &tmp);
2134 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2135 (tmp & BMSR_LSTATUS))
2136 current_link_up = 1;
2137 }
2138
2139 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2140 if (current_link_up == 1) {
2141 if (tp->link_config.active_speed == SPEED_100 ||
2142 tp->link_config.active_speed == SPEED_10)
2143 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2144 else
2145 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2146 } else
2147 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2148
2149 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2150 if (tp->link_config.active_duplex == DUPLEX_HALF)
2151 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2152
1da177e4 2153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 2154 if (current_link_up == 1 &&
2155 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 2156 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 2157 else
2158 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 2159 }
2160
2161 /* ??? Without this setting Netgear GA302T PHY does not
2162 * ??? send/receive packets...
2163 */
2164 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2165 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2166 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2167 tw32_f(MAC_MI_MODE, tp->mi_mode);
2168 udelay(80);
2169 }
2170
2171 tw32_f(MAC_MODE, tp->mac_mode);
2172 udelay(40);
2173
2174 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2175 /* Polled via timer. */
2176 tw32_f(MAC_EVENT, 0);
2177 } else {
2178 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2179 }
2180 udelay(40);
2181
2182 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2183 current_link_up == 1 &&
2184 tp->link_config.active_speed == SPEED_1000 &&
2185 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2186 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2187 udelay(120);
2188 tw32_f(MAC_STATUS,
2189 (MAC_STATUS_SYNC_CHANGED |
2190 MAC_STATUS_CFG_CHANGED));
2191 udelay(40);
2192 tg3_write_mem(tp,
2193 NIC_SRAM_FIRMWARE_MBOX,
2194 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2195 }
2196
2197 if (current_link_up != netif_carrier_ok(tp->dev)) {
2198 if (current_link_up)
2199 netif_carrier_on(tp->dev);
2200 else
2201 netif_carrier_off(tp->dev);
2202 tg3_link_report(tp);
2203 }
2204
2205 return 0;
2206}
2207
2208struct tg3_fiber_aneginfo {
2209 int state;
2210#define ANEG_STATE_UNKNOWN 0
2211#define ANEG_STATE_AN_ENABLE 1
2212#define ANEG_STATE_RESTART_INIT 2
2213#define ANEG_STATE_RESTART 3
2214#define ANEG_STATE_DISABLE_LINK_OK 4
2215#define ANEG_STATE_ABILITY_DETECT_INIT 5
2216#define ANEG_STATE_ABILITY_DETECT 6
2217#define ANEG_STATE_ACK_DETECT_INIT 7
2218#define ANEG_STATE_ACK_DETECT 8
2219#define ANEG_STATE_COMPLETE_ACK_INIT 9
2220#define ANEG_STATE_COMPLETE_ACK 10
2221#define ANEG_STATE_IDLE_DETECT_INIT 11
2222#define ANEG_STATE_IDLE_DETECT 12
2223#define ANEG_STATE_LINK_OK 13
2224#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2225#define ANEG_STATE_NEXT_PAGE_WAIT 15
2226
2227 u32 flags;
2228#define MR_AN_ENABLE 0x00000001
2229#define MR_RESTART_AN 0x00000002
2230#define MR_AN_COMPLETE 0x00000004
2231#define MR_PAGE_RX 0x00000008
2232#define MR_NP_LOADED 0x00000010
2233#define MR_TOGGLE_TX 0x00000020
2234#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2235#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2236#define MR_LP_ADV_SYM_PAUSE 0x00000100
2237#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2238#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2239#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2240#define MR_LP_ADV_NEXT_PAGE 0x00001000
2241#define MR_TOGGLE_RX 0x00002000
2242#define MR_NP_RX 0x00004000
2243
2244#define MR_LINK_OK 0x80000000
2245
2246 unsigned long link_time, cur_time;
2247
2248 u32 ability_match_cfg;
2249 int ability_match_count;
2250
2251 char ability_match, idle_match, ack_match;
2252
2253 u32 txconfig, rxconfig;
2254#define ANEG_CFG_NP 0x00000080
2255#define ANEG_CFG_ACK 0x00000040
2256#define ANEG_CFG_RF2 0x00000020
2257#define ANEG_CFG_RF1 0x00000010
2258#define ANEG_CFG_PS2 0x00000001
2259#define ANEG_CFG_PS1 0x00008000
2260#define ANEG_CFG_HD 0x00004000
2261#define ANEG_CFG_FD 0x00002000
2262#define ANEG_CFG_INVAL 0x00001f06
2263
2264};
2265#define ANEG_OK 0
2266#define ANEG_DONE 1
2267#define ANEG_TIMER_ENAB 2
2268#define ANEG_FAILED -1
2269
2270#define ANEG_STATE_SETTLE_TIME 10000
2271
2272static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2273 struct tg3_fiber_aneginfo *ap)
2274{
2275 unsigned long delta;
2276 u32 rx_cfg_reg;
2277 int ret;
2278
2279 if (ap->state == ANEG_STATE_UNKNOWN) {
2280 ap->rxconfig = 0;
2281 ap->link_time = 0;
2282 ap->cur_time = 0;
2283 ap->ability_match_cfg = 0;
2284 ap->ability_match_count = 0;
2285 ap->ability_match = 0;
2286 ap->idle_match = 0;
2287 ap->ack_match = 0;
2288 }
2289 ap->cur_time++;
2290
2291 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2292 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2293
2294 if (rx_cfg_reg != ap->ability_match_cfg) {
2295 ap->ability_match_cfg = rx_cfg_reg;
2296 ap->ability_match = 0;
2297 ap->ability_match_count = 0;
2298 } else {
2299 if (++ap->ability_match_count > 1) {
2300 ap->ability_match = 1;
2301 ap->ability_match_cfg = rx_cfg_reg;
2302 }
2303 }
2304 if (rx_cfg_reg & ANEG_CFG_ACK)
2305 ap->ack_match = 1;
2306 else
2307 ap->ack_match = 0;
2308
2309 ap->idle_match = 0;
2310 } else {
2311 ap->idle_match = 1;
2312 ap->ability_match_cfg = 0;
2313 ap->ability_match_count = 0;
2314 ap->ability_match = 0;
2315 ap->ack_match = 0;
2316
2317 rx_cfg_reg = 0;
2318 }
2319
2320 ap->rxconfig = rx_cfg_reg;
2321 ret = ANEG_OK;
2322
2323 switch(ap->state) {
2324 case ANEG_STATE_UNKNOWN:
2325 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2326 ap->state = ANEG_STATE_AN_ENABLE;
2327
2328 /* fallthru */
2329 case ANEG_STATE_AN_ENABLE:
2330 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2331 if (ap->flags & MR_AN_ENABLE) {
2332 ap->link_time = 0;
2333 ap->cur_time = 0;
2334 ap->ability_match_cfg = 0;
2335 ap->ability_match_count = 0;
2336 ap->ability_match = 0;
2337 ap->idle_match = 0;
2338 ap->ack_match = 0;
2339
2340 ap->state = ANEG_STATE_RESTART_INIT;
2341 } else {
2342 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2343 }
2344 break;
2345
2346 case ANEG_STATE_RESTART_INIT:
2347 ap->link_time = ap->cur_time;
2348 ap->flags &= ~(MR_NP_LOADED);
2349 ap->txconfig = 0;
2350 tw32(MAC_TX_AUTO_NEG, 0);
2351 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2352 tw32_f(MAC_MODE, tp->mac_mode);
2353 udelay(40);
2354
2355 ret = ANEG_TIMER_ENAB;
2356 ap->state = ANEG_STATE_RESTART;
2357
2358 /* fallthru */
2359 case ANEG_STATE_RESTART:
2360 delta = ap->cur_time - ap->link_time;
2361 if (delta > ANEG_STATE_SETTLE_TIME) {
2362 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2363 } else {
2364 ret = ANEG_TIMER_ENAB;
2365 }
2366 break;
2367
2368 case ANEG_STATE_DISABLE_LINK_OK:
2369 ret = ANEG_DONE;
2370 break;
2371
2372 case ANEG_STATE_ABILITY_DETECT_INIT:
2373 ap->flags &= ~(MR_TOGGLE_TX);
2374 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2375 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2376 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2377 tw32_f(MAC_MODE, tp->mac_mode);
2378 udelay(40);
2379
2380 ap->state = ANEG_STATE_ABILITY_DETECT;
2381 break;
2382
2383 case ANEG_STATE_ABILITY_DETECT:
2384 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2385 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2386 }
2387 break;
2388
2389 case ANEG_STATE_ACK_DETECT_INIT:
2390 ap->txconfig |= ANEG_CFG_ACK;
2391 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2392 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2393 tw32_f(MAC_MODE, tp->mac_mode);
2394 udelay(40);
2395
2396 ap->state = ANEG_STATE_ACK_DETECT;
2397
2398 /* fallthru */
2399 case ANEG_STATE_ACK_DETECT:
2400 if (ap->ack_match != 0) {
2401 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2402 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2403 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2404 } else {
2405 ap->state = ANEG_STATE_AN_ENABLE;
2406 }
2407 } else if (ap->ability_match != 0 &&
2408 ap->rxconfig == 0) {
2409 ap->state = ANEG_STATE_AN_ENABLE;
2410 }
2411 break;
2412
2413 case ANEG_STATE_COMPLETE_ACK_INIT:
2414 if (ap->rxconfig & ANEG_CFG_INVAL) {
2415 ret = ANEG_FAILED;
2416 break;
2417 }
2418 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2419 MR_LP_ADV_HALF_DUPLEX |
2420 MR_LP_ADV_SYM_PAUSE |
2421 MR_LP_ADV_ASYM_PAUSE |
2422 MR_LP_ADV_REMOTE_FAULT1 |
2423 MR_LP_ADV_REMOTE_FAULT2 |
2424 MR_LP_ADV_NEXT_PAGE |
2425 MR_TOGGLE_RX |
2426 MR_NP_RX);
2427 if (ap->rxconfig & ANEG_CFG_FD)
2428 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2429 if (ap->rxconfig & ANEG_CFG_HD)
2430 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2431 if (ap->rxconfig & ANEG_CFG_PS1)
2432 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2433 if (ap->rxconfig & ANEG_CFG_PS2)
2434 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2435 if (ap->rxconfig & ANEG_CFG_RF1)
2436 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2437 if (ap->rxconfig & ANEG_CFG_RF2)
2438 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2439 if (ap->rxconfig & ANEG_CFG_NP)
2440 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2441
2442 ap->link_time = ap->cur_time;
2443
2444 ap->flags ^= (MR_TOGGLE_TX);
2445 if (ap->rxconfig & 0x0008)
2446 ap->flags |= MR_TOGGLE_RX;
2447 if (ap->rxconfig & ANEG_CFG_NP)
2448 ap->flags |= MR_NP_RX;
2449 ap->flags |= MR_PAGE_RX;
2450
2451 ap->state = ANEG_STATE_COMPLETE_ACK;
2452 ret = ANEG_TIMER_ENAB;
2453 break;
2454
2455 case ANEG_STATE_COMPLETE_ACK:
2456 if (ap->ability_match != 0 &&
2457 ap->rxconfig == 0) {
2458 ap->state = ANEG_STATE_AN_ENABLE;
2459 break;
2460 }
2461 delta = ap->cur_time - ap->link_time;
2462 if (delta > ANEG_STATE_SETTLE_TIME) {
2463 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2464 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2465 } else {
2466 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2467 !(ap->flags & MR_NP_RX)) {
2468 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2469 } else {
2470 ret = ANEG_FAILED;
2471 }
2472 }
2473 }
2474 break;
2475
2476 case ANEG_STATE_IDLE_DETECT_INIT:
2477 ap->link_time = ap->cur_time;
2478 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2479 tw32_f(MAC_MODE, tp->mac_mode);
2480 udelay(40);
2481
2482 ap->state = ANEG_STATE_IDLE_DETECT;
2483 ret = ANEG_TIMER_ENAB;
2484 break;
2485
2486 case ANEG_STATE_IDLE_DETECT:
2487 if (ap->ability_match != 0 &&
2488 ap->rxconfig == 0) {
2489 ap->state = ANEG_STATE_AN_ENABLE;
2490 break;
2491 }
2492 delta = ap->cur_time - ap->link_time;
2493 if (delta > ANEG_STATE_SETTLE_TIME) {
2494 /* XXX another gem from the Broadcom driver :( */
2495 ap->state = ANEG_STATE_LINK_OK;
2496 }
2497 break;
2498
2499 case ANEG_STATE_LINK_OK:
2500 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2501 ret = ANEG_DONE;
2502 break;
2503
2504 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2505 /* ??? unimplemented */
2506 break;
2507
2508 case ANEG_STATE_NEXT_PAGE_WAIT:
2509 /* ??? unimplemented */
2510 break;
2511
2512 default:
2513 ret = ANEG_FAILED;
2514 break;
2515 };
2516
2517 return ret;
2518}
2519
2520static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2521{
2522 int res = 0;
2523 struct tg3_fiber_aneginfo aninfo;
2524 int status = ANEG_FAILED;
2525 unsigned int tick;
2526 u32 tmp;
2527
2528 tw32_f(MAC_TX_AUTO_NEG, 0);
2529
2530 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2531 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2532 udelay(40);
2533
2534 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2535 udelay(40);
2536
2537 memset(&aninfo, 0, sizeof(aninfo));
2538 aninfo.flags |= MR_AN_ENABLE;
2539 aninfo.state = ANEG_STATE_UNKNOWN;
2540 aninfo.cur_time = 0;
2541 tick = 0;
2542 while (++tick < 195000) {
2543 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2544 if (status == ANEG_DONE || status == ANEG_FAILED)
2545 break;
2546
2547 udelay(1);
2548 }
2549
2550 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2551 tw32_f(MAC_MODE, tp->mac_mode);
2552 udelay(40);
2553
2554 *flags = aninfo.flags;
2555
2556 if (status == ANEG_DONE &&
2557 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2558 MR_LP_ADV_FULL_DUPLEX)))
2559 res = 1;
2560
2561 return res;
2562}
2563
2564static void tg3_init_bcm8002(struct tg3 *tp)
2565{
2566 u32 mac_status = tr32(MAC_STATUS);
2567 int i;
2568
2569 /* Reset when initting first time or we have a link. */
2570 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2571 !(mac_status & MAC_STATUS_PCS_SYNCED))
2572 return;
2573
2574 /* Set PLL lock range. */
2575 tg3_writephy(tp, 0x16, 0x8007);
2576
2577 /* SW reset */
2578 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2579
2580 /* Wait for reset to complete. */
2581 /* XXX schedule_timeout() ... */
2582 for (i = 0; i < 500; i++)
2583 udelay(10);
2584
2585 /* Config mode; select PMA/Ch 1 regs. */
2586 tg3_writephy(tp, 0x10, 0x8411);
2587
2588 /* Enable auto-lock and comdet, select txclk for tx. */
2589 tg3_writephy(tp, 0x11, 0x0a10);
2590
2591 tg3_writephy(tp, 0x18, 0x00a0);
2592 tg3_writephy(tp, 0x16, 0x41ff);
2593
2594 /* Assert and deassert POR. */
2595 tg3_writephy(tp, 0x13, 0x0400);
2596 udelay(40);
2597 tg3_writephy(tp, 0x13, 0x0000);
2598
2599 tg3_writephy(tp, 0x11, 0x0a50);
2600 udelay(40);
2601 tg3_writephy(tp, 0x11, 0x0a10);
2602
2603 /* Wait for signal to stabilize */
2604 /* XXX schedule_timeout() ... */
2605 for (i = 0; i < 15000; i++)
2606 udelay(10);
2607
2608 /* Deselect the channel register so we can read the PHYID
2609 * later.
2610 */
2611 tg3_writephy(tp, 0x10, 0x8011);
2612}
2613
2614static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2615{
2616 u32 sg_dig_ctrl, sg_dig_status;
2617 u32 serdes_cfg, expected_sg_dig_ctrl;
2618 int workaround, port_a;
2619 int current_link_up;
2620
2621 serdes_cfg = 0;
2622 expected_sg_dig_ctrl = 0;
2623 workaround = 0;
2624 port_a = 1;
2625 current_link_up = 0;
2626
2627 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2628 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2629 workaround = 1;
2630 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2631 port_a = 0;
2632
2633 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2634 /* preserve bits 20-23 for voltage regulator */
2635 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2636 }
2637
2638 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2639
2640 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2641 if (sg_dig_ctrl & (1 << 31)) {
2642 if (workaround) {
2643 u32 val = serdes_cfg;
2644
2645 if (port_a)
2646 val |= 0xc010000;
2647 else
2648 val |= 0x4010000;
2649 tw32_f(MAC_SERDES_CFG, val);
2650 }
2651 tw32_f(SG_DIG_CTRL, 0x01388400);
2652 }
2653 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2654 tg3_setup_flow_control(tp, 0, 0);
2655 current_link_up = 1;
2656 }
2657 goto out;
2658 }
2659
2660 /* Want auto-negotiation. */
2661 expected_sg_dig_ctrl = 0x81388400;
2662
2663 /* Pause capability */
2664 expected_sg_dig_ctrl |= (1 << 11);
2665
2666 /* Asymettric pause */
2667 expected_sg_dig_ctrl |= (1 << 12);
2668
2669 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2670 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2671 tp->serdes_counter &&
2672 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2673 MAC_STATUS_RCVD_CFG)) ==
2674 MAC_STATUS_PCS_SYNCED)) {
2675 tp->serdes_counter--;
2676 current_link_up = 1;
2677 goto out;
2678 }
2679restart_autoneg:
1da177e4
LT		 2680 if (workaround)
2681 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2682 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2683 udelay(5);
2684 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2685
3d3ebe74
MC		 2686 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2687 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2688 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2689 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2690 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2691 mac_status = tr32(MAC_STATUS);
2692
2693 if ((sg_dig_status & (1 << 1)) &&
2694 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2695 u32 local_adv, remote_adv;
2696
2697 local_adv = ADVERTISE_PAUSE_CAP;
2698 remote_adv = 0;
2699 if (sg_dig_status & (1 << 19))
2700 remote_adv |= LPA_PAUSE_CAP;
2701 if (sg_dig_status & (1 << 20))
2702 remote_adv |= LPA_PAUSE_ASYM;
2703
2704 tg3_setup_flow_control(tp, local_adv, remote_adv);
2705 current_link_up = 1;
3d3ebe74
MC		 2706 tp->serdes_counter = 0;
2707 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2708 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2709 if (tp->serdes_counter)
2710 tp->serdes_counter--;
1da177e4
LT		 2711 else {
2712 if (workaround) {
2713 u32 val = serdes_cfg;
2714
2715 if (port_a)
2716 val |= 0xc010000;
2717 else
2718 val |= 0x4010000;
2719
2720 tw32_f(MAC_SERDES_CFG, val);
2721 }
2722
2723 tw32_f(SG_DIG_CTRL, 0x01388400);
2724 udelay(40);
2725
2726 /* Link parallel detection - link is up */
2727 /* only if we have PCS_SYNC and not */
2728 /* receiving config code words */
2729 mac_status = tr32(MAC_STATUS);
2730 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2731 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2732 tg3_setup_flow_control(tp, 0, 0);
2733 current_link_up = 1;
3d3ebe74
MC		 2734 tp->tg3_flags2 |=
2735 TG3_FLG2_PARALLEL_DETECT;
2736 tp->serdes_counter =
2737 SERDES_PARALLEL_DET_TIMEOUT;
2738 } else
2739 goto restart_autoneg;
1da177e4
LT		 2740 }
2741 }
3d3ebe74
MC		 2742 } else {
2743 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2744 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2745 }
2746
2747out:
2748 return current_link_up;
2749}
2750
2751static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2752{
2753 int current_link_up = 0;
2754
5cf64b8a 2755 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 2756 goto out;
1da177e4
LT		 2757
2758 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2759 u32 flags;
2760 int i;
6aa20a22 2761
1da177e4
LT		 2762 if (fiber_autoneg(tp, &flags)) {
2763 u32 local_adv, remote_adv;
2764
2765 local_adv = ADVERTISE_PAUSE_CAP;
2766 remote_adv = 0;
2767 if (flags & MR_LP_ADV_SYM_PAUSE)
2768 remote_adv |= LPA_PAUSE_CAP;
2769 if (flags & MR_LP_ADV_ASYM_PAUSE)
2770 remote_adv |= LPA_PAUSE_ASYM;
2771
2772 tg3_setup_flow_control(tp, local_adv, remote_adv);
2773
1da177e4
LT		 2774 current_link_up = 1;
2775 }
2776 for (i = 0; i < 30; i++) {
2777 udelay(20);
2778 tw32_f(MAC_STATUS,
2779 (MAC_STATUS_SYNC_CHANGED |
2780 MAC_STATUS_CFG_CHANGED));
2781 udelay(40);
2782 if ((tr32(MAC_STATUS) &
2783 (MAC_STATUS_SYNC_CHANGED |
2784 MAC_STATUS_CFG_CHANGED)) == 0)
2785 break;
2786 }
2787
2788 mac_status = tr32(MAC_STATUS);
2789 if (current_link_up == 0 &&
2790 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2791 !(mac_status & MAC_STATUS_RCVD_CFG))
2792 current_link_up = 1;
2793 } else {
2794 /* Forcing 1000FD link up. */
2795 current_link_up = 1;
1da177e4
LT		 2796
2797 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2798 udelay(40);
e8f3f6ca
MC		 2799
2800 tw32_f(MAC_MODE, tp->mac_mode);
2801 udelay(40);
1da177e4
LT		 2802 }
2803
2804out:
2805 return current_link_up;
2806}
2807
2808static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2809{
2810 u32 orig_pause_cfg;
2811 u16 orig_active_speed;
2812 u8 orig_active_duplex;
2813 u32 mac_status;
2814 int current_link_up;
2815 int i;
2816
2817 orig_pause_cfg =
2818 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2819 TG3_FLAG_TX_PAUSE));
2820 orig_active_speed = tp->link_config.active_speed;
2821 orig_active_duplex = tp->link_config.active_duplex;
2822
2823 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2824 netif_carrier_ok(tp->dev) &&
2825 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2826 mac_status = tr32(MAC_STATUS);
2827 mac_status &= (MAC_STATUS_PCS_SYNCED |
2828 MAC_STATUS_SIGNAL_DET |
2829 MAC_STATUS_CFG_CHANGED |
2830 MAC_STATUS_RCVD_CFG);
2831 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2832 MAC_STATUS_SIGNAL_DET)) {
2833 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2834 MAC_STATUS_CFG_CHANGED));
2835 return 0;
2836 }
2837 }
2838
2839 tw32_f(MAC_TX_AUTO_NEG, 0);
2840
2841 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2842 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2843 tw32_f(MAC_MODE, tp->mac_mode);
2844 udelay(40);
2845
2846 if (tp->phy_id == PHY_ID_BCM8002)
2847 tg3_init_bcm8002(tp);
2848
2849 /* Enable link change event even when serdes polling. */
2850 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2851 udelay(40);
2852
2853 current_link_up = 0;
2854 mac_status = tr32(MAC_STATUS);
2855
2856 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2857 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2858 else
2859 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2860
1da177e4
LT		 2861 tp->hw_status->status =
2862 (SD_STATUS_UPDATED |
2863 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2864
2865 for (i = 0; i < 100; i++) {
2866 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2867 MAC_STATUS_CFG_CHANGED));
2868 udelay(5);
2869 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2870 MAC_STATUS_CFG_CHANGED |
2871 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2872 break;
2873 }
2874
2875 mac_status = tr32(MAC_STATUS);
2876 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2877 current_link_up = 0;
3d3ebe74
MC		 2878 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2879 tp->serdes_counter == 0) {
1da177e4
LT		 2880 tw32_f(MAC_MODE, (tp->mac_mode |
2881 MAC_MODE_SEND_CONFIGS));
2882 udelay(1);
2883 tw32_f(MAC_MODE, tp->mac_mode);
2884 }
2885 }
2886
2887 if (current_link_up == 1) {
2888 tp->link_config.active_speed = SPEED_1000;
2889 tp->link_config.active_duplex = DUPLEX_FULL;
2890 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2891 LED_CTRL_LNKLED_OVERRIDE |
2892 LED_CTRL_1000MBPS_ON));
2893 } else {
2894 tp->link_config.active_speed = SPEED_INVALID;
2895 tp->link_config.active_duplex = DUPLEX_INVALID;
2896 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2897 LED_CTRL_LNKLED_OVERRIDE |
2898 LED_CTRL_TRAFFIC_OVERRIDE));
2899 }
2900
2901 if (current_link_up != netif_carrier_ok(tp->dev)) {
2902 if (current_link_up)
2903 netif_carrier_on(tp->dev);
2904 else
2905 netif_carrier_off(tp->dev);
2906 tg3_link_report(tp);
2907 } else {
2908 u32 now_pause_cfg =
2909 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2910 TG3_FLAG_TX_PAUSE);
2911 if (orig_pause_cfg != now_pause_cfg ||
2912 orig_active_speed != tp->link_config.active_speed ||
2913 orig_active_duplex != tp->link_config.active_duplex)
2914 tg3_link_report(tp);
2915 }
2916
2917 return 0;
2918}
2919
747e8f8b
MC		 2920static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2921{
2922 int current_link_up, err = 0;
2923 u32 bmsr, bmcr;
2924 u16 current_speed;
2925 u8 current_duplex;
2926
2927 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2928 tw32_f(MAC_MODE, tp->mac_mode);
2929 udelay(40);
2930
2931 tw32(MAC_EVENT, 0);
2932
2933 tw32_f(MAC_STATUS,
2934 (MAC_STATUS_SYNC_CHANGED |
2935 MAC_STATUS_CFG_CHANGED |
2936 MAC_STATUS_MI_COMPLETION |
2937 MAC_STATUS_LNKSTATE_CHANGED));
2938 udelay(40);
2939
2940 if (force_reset)
2941 tg3_phy_reset(tp);
2942
2943 current_link_up = 0;
2944 current_speed = SPEED_INVALID;
2945 current_duplex = DUPLEX_INVALID;
2946
2947 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2948 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2950 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2951 bmsr |= BMSR_LSTATUS;
2952 else
2953 bmsr &= ~BMSR_LSTATUS;
2954 }
747e8f8b
MC		 2955
2956 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2957
2958 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2959 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2960 /* do nothing, just check for link up at the end */
2961 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2962 u32 adv, new_adv;
2963
2964 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2965 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2966 ADVERTISE_1000XPAUSE |
2967 ADVERTISE_1000XPSE_ASYM |
2968 ADVERTISE_SLCT);
2969
2970 /* Always advertise symmetric PAUSE just like copper */
2971 new_adv |= ADVERTISE_1000XPAUSE;
2972
2973 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2974 new_adv |= ADVERTISE_1000XHALF;
2975 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2976 new_adv |= ADVERTISE_1000XFULL;
2977
2978 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2979 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2980 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2981 tg3_writephy(tp, MII_BMCR, bmcr);
2982
2983 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2984 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2985 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2986
2987 return err;
2988 }
2989 } else {
2990 u32 new_bmcr;
2991
2992 bmcr &= ~BMCR_SPEED1000;
2993 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2994
2995 if (tp->link_config.duplex == DUPLEX_FULL)
2996 new_bmcr |= BMCR_FULLDPLX;
2997
2998 if (new_bmcr != bmcr) {
2999 /* BMCR_SPEED1000 is a reserved bit that needs
3000 * to be set on write.
3001 */
3002 new_bmcr |= BMCR_SPEED1000;
3003
3004 /* Force a linkdown */
3005 if (netif_carrier_ok(tp->dev)) {
3006 u32 adv;
3007
3008 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3009 adv &= ~(ADVERTISE_1000XFULL |
3010 ADVERTISE_1000XHALF |
3011 ADVERTISE_SLCT);
3012 tg3_writephy(tp, MII_ADVERTISE, adv);
3013 tg3_writephy(tp, MII_BMCR, bmcr |
3014 BMCR_ANRESTART |
3015 BMCR_ANENABLE);
3016 udelay(10);
3017 netif_carrier_off(tp->dev);
3018 }
3019 tg3_writephy(tp, MII_BMCR, new_bmcr);
3020 bmcr = new_bmcr;
3021 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3022 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3023 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3024 ASIC_REV_5714) {
3025 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3026 bmsr |= BMSR_LSTATUS;
3027 else
3028 bmsr &= ~BMSR_LSTATUS;
3029 }
747e8f8b
MC		 3030 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3031 }
3032 }
3033
3034 if (bmsr & BMSR_LSTATUS) {
3035 current_speed = SPEED_1000;
3036 current_link_up = 1;
3037 if (bmcr & BMCR_FULLDPLX)
3038 current_duplex = DUPLEX_FULL;
3039 else
3040 current_duplex = DUPLEX_HALF;
3041
3042 if (bmcr & BMCR_ANENABLE) {
3043 u32 local_adv, remote_adv, common;
3044
3045 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3046 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3047 common = local_adv & remote_adv;
3048 if (common & (ADVERTISE_1000XHALF |
3049 ADVERTISE_1000XFULL)) {
3050 if (common & ADVERTISE_1000XFULL)
3051 current_duplex = DUPLEX_FULL;
3052 else
3053 current_duplex = DUPLEX_HALF;
3054
3055 tg3_setup_flow_control(tp, local_adv,
3056 remote_adv);
3057 }
3058 else
3059 current_link_up = 0;
3060 }
3061 }
3062
3063 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3064 if (tp->link_config.active_duplex == DUPLEX_HALF)
3065 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3066
3067 tw32_f(MAC_MODE, tp->mac_mode);
3068 udelay(40);
3069
3070 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3071
3072 tp->link_config.active_speed = current_speed;
3073 tp->link_config.active_duplex = current_duplex;
3074
3075 if (current_link_up != netif_carrier_ok(tp->dev)) {
3076 if (current_link_up)
3077 netif_carrier_on(tp->dev);
3078 else {
3079 netif_carrier_off(tp->dev);
3080 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3081 }
3082 tg3_link_report(tp);
3083 }
3084 return err;
3085}
3086
3087static void tg3_serdes_parallel_detect(struct tg3 *tp)
3088{
3d3ebe74 3089 if (tp->serdes_counter) {
747e8f8b 3090 /* Give autoneg time to complete. */
3d3ebe74 3091 tp->serdes_counter--;
747e8f8b
MC		 3092 return;
3093 }
3094 if (!netif_carrier_ok(tp->dev) &&
3095 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3096 u32 bmcr;
3097
3098 tg3_readphy(tp, MII_BMCR, &bmcr);
3099 if (bmcr & BMCR_ANENABLE) {
3100 u32 phy1, phy2;
3101
3102 /* Select shadow register 0x1f */
3103 tg3_writephy(tp, 0x1c, 0x7c00);
3104 tg3_readphy(tp, 0x1c, &phy1);
3105
3106 /* Select expansion interrupt status register */
3107 tg3_writephy(tp, 0x17, 0x0f01);
3108 tg3_readphy(tp, 0x15, &phy2);
3109 tg3_readphy(tp, 0x15, &phy2);
3110
3111 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3112 /* We have signal detect and not receiving
3113 * config code words, link is up by parallel
3114 * detection.
3115 */
3116
3117 bmcr &= ~BMCR_ANENABLE;
3118 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3119 tg3_writephy(tp, MII_BMCR, bmcr);
3120 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3121 }
3122 }
3123 }
3124 else if (netif_carrier_ok(tp->dev) &&
3125 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3126 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3127 u32 phy2;
3128
3129 /* Select expansion interrupt status register */
3130 tg3_writephy(tp, 0x17, 0x0f01);
3131 tg3_readphy(tp, 0x15, &phy2);
3132 if (phy2 & 0x20) {
3133 u32 bmcr;
3134
3135 /* Config code words received, turn on autoneg. */
3136 tg3_readphy(tp, MII_BMCR, &bmcr);
3137 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3138
3139 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3140
3141 }
3142 }
3143}
3144
1da177e4
LT		 3145static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3146{
3147 int err;
3148
3149 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3150 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 3151 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3152 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 3153 } else {
3154 err = tg3_setup_copper_phy(tp, force_reset);
3155 }
3156
aa6c91fe
MC		 3157 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
3158 u32 val, scale;
3159
3160 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3161 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3162 scale = 65;
3163 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3164 scale = 6;
3165 else
3166 scale = 12;
3167
3168 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3169 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3170 tw32(GRC_MISC_CFG, val);
3171 }
3172
1da177e4
LT		 3173 if (tp->link_config.active_speed == SPEED_1000 &&
3174 tp->link_config.active_duplex == DUPLEX_HALF)
3175 tw32(MAC_TX_LENGTHS,
3176 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3177 (6 << TX_LENGTHS_IPG_SHIFT) |
3178 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3179 else
3180 tw32(MAC_TX_LENGTHS,
3181 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3182 (6 << TX_LENGTHS_IPG_SHIFT) |
3183 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3184
3185 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3186 if (netif_carrier_ok(tp->dev)) {
3187 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3188 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3189 } else {
3190 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3191 }
3192 }
3193
8ed5d97e
MC		 3194 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3195 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3196 if (!netif_carrier_ok(tp->dev))
3197 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3198 tp->pwrmgmt_thresh;
3199 else
3200 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3201 tw32(PCIE_PWR_MGMT_THRESH, val);
3202 }
3203
1da177e4
LT		 3204 return err;
3205}
3206
df3e6548
MC		 3207/* This is called whenever we suspect that the system chipset is re-
3208 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3209 * is bogus tx completions. We try to recover by setting the
3210 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3211 * in the workqueue.
3212 */
3213static void tg3_tx_recover(struct tg3 *tp)
3214{
3215 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3216 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3217
3218 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3219 "mapped I/O cycles to the network device, attempting to "
3220 "recover. Please report the problem to the driver maintainer "
3221 "and include system chipset information.\n", tp->dev->name);
3222
3223 spin_lock(&tp->lock);
df3e6548 3224 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3225 spin_unlock(&tp->lock);
3226}
3227
1b2a7205
MC		 3228static inline u32 tg3_tx_avail(struct tg3 *tp)
3229{
3230 smp_mb();
3231 return (tp->tx_pending -
3232 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3233}
3234
1da177e4
LT		 3235/* Tigon3 never reports partial packet sends. So we do not
3236 * need special logic to handle SKBs that have not had all
3237 * of their frags sent yet, like SunGEM does.
3238 */
3239static void tg3_tx(struct tg3 *tp)
3240{
3241 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3242 u32 sw_idx = tp->tx_cons;
3243
3244 while (sw_idx != hw_idx) {
3245 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3246 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3247 int i, tx_bug = 0;
3248
3249 if (unlikely(skb == NULL)) {
3250 tg3_tx_recover(tp);
3251 return;
3252 }
1da177e4 3253
1da177e4
LT		 3254 pci_unmap_single(tp->pdev,
3255 pci_unmap_addr(ri, mapping),
3256 skb_headlen(skb),
3257 PCI_DMA_TODEVICE);
3258
3259 ri->skb = NULL;
3260
3261 sw_idx = NEXT_TX(sw_idx);
3262
3263 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3264 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3265 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3266 tx_bug = 1;
1da177e4
LT		 3267
3268 pci_unmap_page(tp->pdev,
3269 pci_unmap_addr(ri, mapping),
3270 skb_shinfo(skb)->frags[i].size,
3271 PCI_DMA_TODEVICE);
3272
3273 sw_idx = NEXT_TX(sw_idx);
3274 }
3275
f47c11ee 3276 dev_kfree_skb(skb);
df3e6548
MC		 3277
3278 if (unlikely(tx_bug)) {
3279 tg3_tx_recover(tp);
3280 return;
3281 }
1da177e4
LT		 3282 }
3283
3284 tp->tx_cons = sw_idx;
3285
1b2a7205
MC		 3286 /* Need to make the tx_cons update visible to tg3_start_xmit()
3287 * before checking for netif_queue_stopped(). Without the
3288 * memory barrier, there is a small possibility that tg3_start_xmit()
3289 * will miss it and cause the queue to be stopped forever.
3290 */
3291 smp_mb();
3292
3293 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3294 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3295 netif_tx_lock(tp->dev);
51b91468 3296 if (netif_queue_stopped(tp->dev) &&
42952231 3297 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3298 netif_wake_queue(tp->dev);
1b2a7205 3299 netif_tx_unlock(tp->dev);
51b91468 3300 }
1da177e4
LT		 3301}
3302
3303/* Returns size of skb allocated or < 0 on error.
3304 *
3305 * We only need to fill in the address because the other members
3306 * of the RX descriptor are invariant, see tg3_init_rings.
3307 *
3308 * Note the purposeful assymetry of cpu vs. chip accesses. For
3309 * posting buffers we only dirty the first cache line of the RX
3310 * descriptor (containing the address). Whereas for the RX status
3311 * buffers the cpu only reads the last cacheline of the RX descriptor
3312 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3313 */
3314static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3315 int src_idx, u32 dest_idx_unmasked)
3316{
3317 struct tg3_rx_buffer_desc *desc;
3318 struct ring_info *map, *src_map;
3319 struct sk_buff *skb;
3320 dma_addr_t mapping;
3321 int skb_size, dest_idx;
3322
3323 src_map = NULL;
3324 switch (opaque_key) {
3325 case RXD_OPAQUE_RING_STD:
3326 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3327 desc = &tp->rx_std[dest_idx];
3328 map = &tp->rx_std_buffers[dest_idx];
3329 if (src_idx >= 0)
3330 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3331 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3332 break;
3333
3334 case RXD_OPAQUE_RING_JUMBO:
3335 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3336 desc = &tp->rx_jumbo[dest_idx];
3337 map = &tp->rx_jumbo_buffers[dest_idx];
3338 if (src_idx >= 0)
3339 src_map = &tp->rx_jumbo_buffers[src_idx];
3340 skb_size = RX_JUMBO_PKT_BUF_SZ;
3341 break;
3342
3343 default:
3344 return -EINVAL;
3345 };
3346
3347 /* Do not overwrite any of the map or rp information
3348 * until we are sure we can commit to a new buffer.
3349 *
3350 * Callers depend upon this behavior and assume that
3351 * we leave everything unchanged if we fail.
3352 */
a20e9c62 3353 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3354 if (skb == NULL)
3355 return -ENOMEM;
3356
1da177e4
LT		 3357 skb_reserve(skb, tp->rx_offset);
3358
3359 mapping = pci_map_single(tp->pdev, skb->data,
3360 skb_size - tp->rx_offset,
3361 PCI_DMA_FROMDEVICE);
3362
3363 map->skb = skb;
3364 pci_unmap_addr_set(map, mapping, mapping);
3365
3366 if (src_map != NULL)
3367 src_map->skb = NULL;
3368
3369 desc->addr_hi = ((u64)mapping >> 32);
3370 desc->addr_lo = ((u64)mapping & 0xffffffff);
3371
3372 return skb_size;
3373}
3374
3375/* We only need to move over in the address because the other
3376 * members of the RX descriptor are invariant. See notes above
3377 * tg3_alloc_rx_skb for full details.
3378 */
3379static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3380 int src_idx, u32 dest_idx_unmasked)
3381{
3382 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3383 struct ring_info *src_map, *dest_map;
3384 int dest_idx;
3385
3386 switch (opaque_key) {
3387 case RXD_OPAQUE_RING_STD:
3388 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3389 dest_desc = &tp->rx_std[dest_idx];
3390 dest_map = &tp->rx_std_buffers[dest_idx];
3391 src_desc = &tp->rx_std[src_idx];
3392 src_map = &tp->rx_std_buffers[src_idx];
3393 break;
3394
3395 case RXD_OPAQUE_RING_JUMBO:
3396 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3397 dest_desc = &tp->rx_jumbo[dest_idx];
3398 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3399 src_desc = &tp->rx_jumbo[src_idx];
3400 src_map = &tp->rx_jumbo_buffers[src_idx];
3401 break;
3402
3403 default:
3404 return;
3405 };
3406
3407 dest_map->skb = src_map->skb;
3408 pci_unmap_addr_set(dest_map, mapping,
3409 pci_unmap_addr(src_map, mapping));
3410 dest_desc->addr_hi = src_desc->addr_hi;
3411 dest_desc->addr_lo = src_desc->addr_lo;
3412
3413 src_map->skb = NULL;
3414}
3415
3416#if TG3_VLAN_TAG_USED
3417static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3418{
3419 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3420}
3421#endif
3422
3423/* The RX ring scheme is composed of multiple rings which post fresh
3424 * buffers to the chip, and one special ring the chip uses to report
3425 * status back to the host.
3426 *
3427 * The special ring reports the status of received packets to the
3428 * host. The chip does not write into the original descriptor the
3429 * RX buffer was obtained from. The chip simply takes the original
3430 * descriptor as provided by the host, updates the status and length
3431 * field, then writes this into the next status ring entry.
3432 *
3433 * Each ring the host uses to post buffers to the chip is described
3434 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3435 * it is first placed into the on-chip ram. When the packet's length
3436 * is known, it walks down the TG3_BDINFO entries to select the ring.
3437 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3438 * which is within the range of the new packet's length is chosen.
3439 *
3440 * The "separate ring for rx status" scheme may sound queer, but it makes
3441 * sense from a cache coherency perspective. If only the host writes
3442 * to the buffer post rings, and only the chip writes to the rx status
3443 * rings, then cache lines never move beyond shared-modified state.
3444 * If both the host and chip were to write into the same ring, cache line
3445 * eviction could occur since both entities want it in an exclusive state.
3446 */
3447static int tg3_rx(struct tg3 *tp, int budget)
3448{
f92905de 3449 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3450 u32 sw_idx = tp->rx_rcb_ptr;
3451 u16 hw_idx;
1da177e4
LT		 3452 int received;
3453
3454 hw_idx = tp->hw_status->idx[0].rx_producer;
3455 /*
3456 * We need to order the read of hw_idx and the read of
3457 * the opaque cookie.
3458 */
3459 rmb();
1da177e4
LT		 3460 work_mask = 0;
3461 received = 0;
3462 while (sw_idx != hw_idx && budget > 0) {
3463 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3464 unsigned int len;
3465 struct sk_buff *skb;
3466 dma_addr_t dma_addr;
3467 u32 opaque_key, desc_idx, *post_ptr;
3468
3469 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3470 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3471 if (opaque_key == RXD_OPAQUE_RING_STD) {
3472 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3473 mapping);
3474 skb = tp->rx_std_buffers[desc_idx].skb;
3475 post_ptr = &tp->rx_std_ptr;
f92905de 3476 rx_std_posted++;
1da177e4
LT		 3477 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3478 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3479 mapping);
3480 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3481 post_ptr = &tp->rx_jumbo_ptr;
3482 }
3483 else {
3484 goto next_pkt_nopost;
3485 }
3486
3487 work_mask |= opaque_key;
3488
3489 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3490 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3491 drop_it:
3492 tg3_recycle_rx(tp, opaque_key,
3493 desc_idx, *post_ptr);
3494 drop_it_no_recycle:
3495 /* Other statistics kept track of by card. */
3496 tp->net_stats.rx_dropped++;
3497 goto next_pkt;
3498 }
3499
3500 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3501
6aa20a22 3502 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3503 && tp->rx_offset == 2
3504 /* rx_offset != 2 iff this is a 5701 card running
3505 * in PCI-X mode [see tg3_get_invariants()] */
3506 ) {
3507 int skb_size;
3508
3509 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3510 desc_idx, *post_ptr);
3511 if (skb_size < 0)
3512 goto drop_it;
3513
3514 pci_unmap_single(tp->pdev, dma_addr,
3515 skb_size - tp->rx_offset,
3516 PCI_DMA_FROMDEVICE);
3517
3518 skb_put(skb, len);
3519 } else {
3520 struct sk_buff *copy_skb;
3521
3522 tg3_recycle_rx(tp, opaque_key,
3523 desc_idx, *post_ptr);
3524
a20e9c62 3525 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3526 if (copy_skb == NULL)
3527 goto drop_it_no_recycle;
3528
1da177e4
LT		 3529 skb_reserve(copy_skb, 2);
3530 skb_put(copy_skb, len);
3531 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 3532 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 3533 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3534
3535 /* We'll reuse the original ring buffer. */
3536 skb = copy_skb;
3537 }
3538
3539 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3540 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3541 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3542 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3543 skb->ip_summed = CHECKSUM_UNNECESSARY;
3544 else
3545 skb->ip_summed = CHECKSUM_NONE;
3546
3547 skb->protocol = eth_type_trans(skb, tp->dev);
3548#if TG3_VLAN_TAG_USED
3549 if (tp->vlgrp != NULL &&
3550 desc->type_flags & RXD_FLAG_VLAN) {
3551 tg3_vlan_rx(tp, skb,
3552 desc->err_vlan & RXD_VLAN_MASK);
3553 } else
3554#endif
3555 netif_receive_skb(skb);
3556
3557 tp->dev->last_rx = jiffies;
3558 received++;
3559 budget--;
3560
3561next_pkt:
3562 (*post_ptr)++;
f92905de
MC		 3563
3564 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3565 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3566
3567 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3568 TG3_64BIT_REG_LOW, idx);
3569 work_mask &= ~RXD_OPAQUE_RING_STD;
3570 rx_std_posted = 0;
3571 }
1da177e4 3572next_pkt_nopost:
483ba50b 3573 sw_idx++;
6b31a515 3574 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3575
3576 /* Refresh hw_idx to see if there is new work */
3577 if (sw_idx == hw_idx) {
3578 hw_idx = tp->hw_status->idx[0].rx_producer;
3579 rmb();
3580 }
1da177e4
LT		 3581 }
3582
3583 /* ACK the status ring. */
483ba50b
MC		 3584 tp->rx_rcb_ptr = sw_idx;
3585 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3586
3587 /* Refill RX ring(s). */
3588 if (work_mask & RXD_OPAQUE_RING_STD) {
3589 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3590 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3591 sw_idx);
3592 }
3593 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3594 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3595 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3596 sw_idx);
3597 }
3598 mmiowb();
3599
3600 return received;
3601}
3602
6f535763 3603static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 3604{
1da177e4 3605 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 3606
1da177e4
LT		 3607 /* handle link change and other phy events */
3608 if (!(tp->tg3_flags &
3609 (TG3_FLAG_USE_LINKCHG_REG |
3610 TG3_FLAG_POLL_SERDES))) {
3611 if (sblk->status & SD_STATUS_LINK_CHG) {
3612 sblk->status = SD_STATUS_UPDATED |
3613 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3614 spin_lock(&tp->lock);
1da177e4 3615 tg3_setup_phy(tp, 0);
f47c11ee 3616 spin_unlock(&tp->lock);
1da177e4
LT		 3617 }
3618 }
3619
3620 /* run TX completion thread */
3621 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3622 tg3_tx(tp);
6f535763 3623 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 3624 return work_done;
1da177e4
LT		 3625 }
3626
1da177e4
LT		 3627 /* run RX thread, within the bounds set by NAPI.
3628 * All RX "locking" is done by ensuring outside
bea3348e 3629 * code synchronizes with tg3->napi.poll()
1da177e4 3630 */
bea3348e 3631 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 3632 work_done += tg3_rx(tp, budget - work_done);
1da177e4 3633
6f535763
DM		 3634 return work_done;
3635}
3636
3637static int tg3_poll(struct napi_struct *napi, int budget)
3638{
3639 struct tg3 *tp = container_of(napi, struct tg3, napi);
3640 int work_done = 0;
4fd7ab59 3641 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 3642
3643 while (1) {
3644 work_done = tg3_poll_work(tp, work_done, budget);
3645
3646 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3647 goto tx_recovery;
3648
3649 if (unlikely(work_done >= budget))
3650 break;
3651
4fd7ab59
MC		 3652 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3653 /* tp->last_tag is used in tg3_restart_ints() below
3654 * to tell the hw how much work has been processed,
3655 * so we must read it before checking for more work.
3656 */
3657 tp->last_tag = sblk->status_tag;
3658 rmb();
3659 } else
3660 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 3661
4fd7ab59 3662 if (likely(!tg3_has_work(tp))) {
6f535763
DM		 3663 netif_rx_complete(tp->dev, napi);
3664 tg3_restart_ints(tp);
3665 break;
3666 }
1da177e4
LT		 3667 }
3668
bea3348e 3669 return work_done;
6f535763
DM		 3670
3671tx_recovery:
4fd7ab59 3672 /* work_done is guaranteed to be less than budget. */
6f535763
DM		 3673 netif_rx_complete(tp->dev, napi);
3674 schedule_work(&tp->reset_task);
4fd7ab59 3675 return work_done;
1da177e4
LT		 3676}
3677
f47c11ee
DM		 3678static void tg3_irq_quiesce(struct tg3 *tp)
3679{
3680 BUG_ON(tp->irq_sync);
3681
3682 tp->irq_sync = 1;
3683 smp_mb();
3684
3685 synchronize_irq(tp->pdev->irq);
3686}
3687
3688static inline int tg3_irq_sync(struct tg3 *tp)
3689{
3690 return tp->irq_sync;
3691}
3692
3693/* Fully shutdown all tg3 driver activity elsewhere in the system.
3694 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3695 * with as well. Most of the time, this is not necessary except when
3696 * shutting down the device.
3697 */
3698static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3699{
46966545 3700 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3701 if (irq_sync)
3702 tg3_irq_quiesce(tp);
f47c11ee
DM		 3703}
3704
3705static inline void tg3_full_unlock(struct tg3 *tp)
3706{
f47c11ee
DM		 3707 spin_unlock_bh(&tp->lock);
3708}
3709
fcfa0a32
MC		 3710/* One-shot MSI handler - Chip automatically disables interrupt
3711 * after sending MSI so driver doesn't have to do it.
3712 */
7d12e780 3713static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3714{
3715 struct net_device *dev = dev_id;
3716 struct tg3 *tp = netdev_priv(dev);
3717
3718 prefetch(tp->hw_status);
3719 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3720
3721 if (likely(!tg3_irq_sync(tp)))
bea3348e 3722 netif_rx_schedule(dev, &tp->napi);
fcfa0a32
MC		 3723
3724 return IRQ_HANDLED;
3725}
3726
88b06bc2
MC		 3727/* MSI ISR - No need to check for interrupt sharing and no need to
3728 * flush status block and interrupt mailbox. PCI ordering rules
3729 * guarantee that MSI will arrive after the status block.
3730 */
7d12e780 3731static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3732{
3733 struct net_device *dev = dev_id;
3734 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3735
61487480
MC		 3736 prefetch(tp->hw_status);
3737 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3738 /*
fac9b83e 3739 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3740 * chip-internal interrupt pending events.
fac9b83e 3741 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3742 * NIC to stop sending us irqs, engaging "in-intr-handler"
3743 * event coalescing.
3744 */
3745 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3746 if (likely(!tg3_irq_sync(tp)))
bea3348e 3747 netif_rx_schedule(dev, &tp->napi);
61487480 3748
88b06bc2
MC		 3749 return IRQ_RETVAL(1);
3750}
3751
7d12e780 3752static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3753{
3754 struct net_device *dev = dev_id;
3755 struct tg3 *tp = netdev_priv(dev);
3756 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3757 unsigned int handled = 1;
3758
1da177e4
LT		 3759 /* In INTx mode, it is possible for the interrupt to arrive at
3760 * the CPU before the status block posted prior to the interrupt.
3761 * Reading the PCI State register will confirm whether the
3762 * interrupt is ours and will flush the status block.
3763 */
d18edcb2
MC		 3764 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3765 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3766 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3767 handled = 0;
f47c11ee 3768 goto out;
fac9b83e 3769 }
d18edcb2
MC		 3770 }
3771
3772 /*
3773 * Writing any value to intr-mbox-0 clears PCI INTA# and
3774 * chip-internal interrupt pending events.
3775 * Writing non-zero to intr-mbox-0 additional tells the
3776 * NIC to stop sending us irqs, engaging "in-intr-handler"
3777 * event coalescing.
c04cb347
MC		 3778 *
3779 * Flush the mailbox to de-assert the IRQ immediately to prevent
3780 * spurious interrupts. The flush impacts performance but
3781 * excessive spurious interrupts can be worse in some cases.
d18edcb2 3782 */
c04cb347 3783 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 3784 if (tg3_irq_sync(tp))
3785 goto out;
3786 sblk->status &= ~SD_STATUS_UPDATED;
3787 if (likely(tg3_has_work(tp))) {
3788 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
bea3348e 3789 netif_rx_schedule(dev, &tp->napi);
d18edcb2
MC		 3790 } else {
3791 /* No work, shared interrupt perhaps? re-enable
3792 * interrupts, and flush that PCI write
3793 */
3794 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3795 0x00000000);
fac9b83e 3796 }
f47c11ee 3797out:
fac9b83e
DM		 3798 return IRQ_RETVAL(handled);
3799}
3800
7d12e780 3801static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3802{
3803 struct net_device *dev = dev_id;
3804 struct tg3 *tp = netdev_priv(dev);
3805 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3806 unsigned int handled = 1;
3807
fac9b83e
DM		 3808 /* In INTx mode, it is possible for the interrupt to arrive at
3809 * the CPU before the status block posted prior to the interrupt.
3810 * Reading the PCI State register will confirm whether the
3811 * interrupt is ours and will flush the status block.
3812 */
d18edcb2
MC		 3813 if (unlikely(sblk->status_tag == tp->last_tag)) {
3814 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3815 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3816 handled = 0;
f47c11ee 3817 goto out;
1da177e4 3818 }
d18edcb2
MC		 3819 }
3820
3821 /*
3822 * writing any value to intr-mbox-0 clears PCI INTA# and
3823 * chip-internal interrupt pending events.
3824 * writing non-zero to intr-mbox-0 additional tells the
3825 * NIC to stop sending us irqs, engaging "in-intr-handler"
3826 * event coalescing.
c04cb347
MC		 3827 *
3828 * Flush the mailbox to de-assert the IRQ immediately to prevent
3829 * spurious interrupts. The flush impacts performance but
3830 * excessive spurious interrupts can be worse in some cases.
d18edcb2 3831 */
c04cb347 3832 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 3833 if (tg3_irq_sync(tp))
3834 goto out;
bea3348e 3835 if (netif_rx_schedule_prep(dev, &tp->napi)) {
d18edcb2
MC		 3836 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3837 /* Update last_tag to mark that this status has been
3838 * seen. Because interrupt may be shared, we may be
3839 * racing with tg3_poll(), so only update last_tag
3840 * if tg3_poll() is not scheduled.
3841 */
3842 tp->last_tag = sblk->status_tag;
bea3348e 3843 __netif_rx_schedule(dev, &tp->napi);
1da177e4 3844 }
f47c11ee 3845out:
1da177e4
LT		 3846 return IRQ_RETVAL(handled);
3847}
3848
7938109f 3849/* ISR for interrupt test */
7d12e780 3850static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3851{
3852 struct net_device *dev = dev_id;
3853 struct tg3 *tp = netdev_priv(dev);
3854 struct tg3_hw_status *sblk = tp->hw_status;
3855
f9804ddb
MC		 3856 if ((sblk->status & SD_STATUS_UPDATED) ||
3857 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3858 tg3_disable_ints(tp);
7938109f
MC		 3859 return IRQ_RETVAL(1);
3860 }
3861 return IRQ_RETVAL(0);
3862}
3863
8e7a22e3 3864static int tg3_init_hw(struct tg3 *, int);
944d980e 3865static int tg3_halt(struct tg3 *, int, int);
1da177e4 3866
b9ec6c1b
MC		 3867/* Restart hardware after configuration changes, self-test, etc.
3868 * Invoked with tp->lock held.
3869 */
3870static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3871{
3872 int err;
3873
3874 err = tg3_init_hw(tp, reset_phy);
3875 if (err) {
3876 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3877 "aborting.\n", tp->dev->name);
3878 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3879 tg3_full_unlock(tp);
3880 del_timer_sync(&tp->timer);
3881 tp->irq_sync = 0;
bea3348e 3882 napi_enable(&tp->napi);
b9ec6c1b
MC		 3883 dev_close(tp->dev);
3884 tg3_full_lock(tp, 0);
3885 }
3886 return err;
3887}
3888
1da177e4
LT		 3889#ifdef CONFIG_NET_POLL_CONTROLLER
3890static void tg3_poll_controller(struct net_device *dev)
3891{
88b06bc2
MC		 3892 struct tg3 *tp = netdev_priv(dev);
3893
7d12e780 3894 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3895}
3896#endif
3897
c4028958 3898static void tg3_reset_task(struct work_struct *work)
1da177e4 3899{
c4028958 3900 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3901 unsigned int restart_timer;
3902
7faa006f 3903 tg3_full_lock(tp, 0);
7faa006f
MC		 3904
3905 if (!netif_running(tp->dev)) {
7faa006f
MC		 3906 tg3_full_unlock(tp);
3907 return;
3908 }
3909
3910 tg3_full_unlock(tp);
3911
1da177e4
LT		 3912 tg3_netif_stop(tp);
3913
f47c11ee 3914 tg3_full_lock(tp, 1);
1da177e4
LT		 3915
3916 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3917 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3918
df3e6548
MC		 3919 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3920 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3921 tp->write32_rx_mbox = tg3_write_flush_reg32;
3922 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3923 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3924 }
3925
944d980e 3926 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3927 if (tg3_init_hw(tp, 1))
3928 goto out;
1da177e4
LT		 3929
3930 tg3_netif_start(tp);
3931
1da177e4
LT		 3932 if (restart_timer)
3933 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3934
b9ec6c1b 3935out:
7faa006f 3936 tg3_full_unlock(tp);
1da177e4
LT		 3937}
3938
b0408751
MC		 3939static void tg3_dump_short_state(struct tg3 *tp)
3940{
3941 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3942 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3943 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3944 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3945}
3946
1da177e4
LT		 3947static void tg3_tx_timeout(struct net_device *dev)
3948{
3949 struct tg3 *tp = netdev_priv(dev);
3950
b0408751 3951 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 3952 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3953 dev->name);
b0408751
MC		 3954 tg3_dump_short_state(tp);
3955 }
1da177e4
LT		 3956
3957 schedule_work(&tp->reset_task);
3958}
3959
c58ec932
MC		 3960/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3961static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3962{
3963 u32 base = (u32) mapping & 0xffffffff;
3964
3965 return ((base > 0xffffdcc0) &&
3966 (base + len + 8 < base));
3967}
3968
72f2afb8
MC		 3969/* Test for DMA addresses > 40-bit */
3970static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3971 int len)
3972{
3973#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3974 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3975 return (((u64) mapping + len) > DMA_40BIT_MASK);
3976 return 0;
3977#else
3978 return 0;
3979#endif
3980}
3981
1da177e4
LT		 3982static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3983
72f2afb8
MC		 3984/* Workaround 4GB and 40-bit hardware DMA bugs. */
3985static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3986 u32 last_plus_one, u32 *start,
3987 u32 base_flags, u32 mss)
1da177e4
LT		 3988{
3989 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3990 dma_addr_t new_addr = 0;
1da177e4 3991 u32 entry = *start;
c58ec932 3992 int i, ret = 0;
1da177e4
LT		 3993
3994 if (!new_skb) {
c58ec932
MC		 3995 ret = -1;
3996 } else {
3997 /* New SKB is guaranteed to be linear. */
3998 entry = *start;
3999 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4000 PCI_DMA_TODEVICE);
4001 /* Make sure new skb does not cross any 4G boundaries.
4002 * Drop the packet if it does.
4003 */
4004 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4005 ret = -1;
4006 dev_kfree_skb(new_skb);
4007 new_skb = NULL;
4008 } else {
4009 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4010 base_flags, 1 | (mss << 1));
4011 *start = NEXT_TX(entry);
4012 }
1da177e4
LT		 4013 }
4014
1da177e4
LT		 4015 /* Now clean up the sw ring entries. */
4016 i = 0;
4017 while (entry != last_plus_one) {
4018 int len;
4019
4020 if (i == 0)
4021 len = skb_headlen(skb);
4022 else
4023 len = skb_shinfo(skb)->frags[i-1].size;
4024 pci_unmap_single(tp->pdev,
4025 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4026 len, PCI_DMA_TODEVICE);
4027 if (i == 0) {
4028 tp->tx_buffers[entry].skb = new_skb;
4029 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4030 } else {
4031 tp->tx_buffers[entry].skb = NULL;
4032 }
4033 entry = NEXT_TX(entry);
4034 i++;
4035 }
4036
4037 dev_kfree_skb(skb);
4038
c58ec932 4039 return ret;
1da177e4
LT		 4040}
4041
4042static void tg3_set_txd(struct tg3 *tp, int entry,
4043 dma_addr_t mapping, int len, u32 flags,
4044 u32 mss_and_is_end)
4045{
4046 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4047 int is_end = (mss_and_is_end & 0x1);
4048 u32 mss = (mss_and_is_end >> 1);
4049 u32 vlan_tag = 0;
4050
4051 if (is_end)
4052 flags |= TXD_FLAG_END;
4053 if (flags & TXD_FLAG_VLAN) {
4054 vlan_tag = flags >> 16;
4055 flags &= 0xffff;
4056 }
4057 vlan_tag |= (mss << TXD_MSS_SHIFT);
4058
4059 txd->addr_hi = ((u64) mapping >> 32);
4060 txd->addr_lo = ((u64) mapping & 0xffffffff);
4061 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4062 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4063}
4064
5a6f3074
MC		 4065/* hard_start_xmit for devices that don't have any bugs and
4066 * support TG3_FLG2_HW_TSO_2 only.
4067 */
1da177e4 4068static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 4069{
4070 struct tg3 *tp = netdev_priv(dev);
4071 dma_addr_t mapping;
4072 u32 len, entry, base_flags, mss;
4073
4074 len = skb_headlen(skb);
4075
00b70504 4076 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4077 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 4078 * interrupt. Furthermore, IRQ processing runs lockless so we have
4079 * no IRQ context deadlocks to worry about either. Rejoice!
4080 */
1b2a7205 4081 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 4082 if (!netif_queue_stopped(dev)) {
4083 netif_stop_queue(dev);
4084
4085 /* This is a hard error, log it. */
4086 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4087 "queue awake!\n", dev->name);
4088 }
5a6f3074
MC		 4089 return NETDEV_TX_BUSY;
4090 }
4091
4092 entry = tp->tx_prod;
4093 base_flags = 0;
5a6f3074 4094 mss = 0;
c13e3713 4095 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 4096 int tcp_opt_len, ip_tcp_len;
4097
4098 if (skb_header_cloned(skb) &&
4099 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4100 dev_kfree_skb(skb);
4101 goto out_unlock;
4102 }
4103
b0026624
MC		 4104 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4105 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4106 else {
eddc9ec5
ACM		 4107 struct iphdr *iph = ip_hdr(skb);
4108
ab6a5bb6 4109 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4110 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 4111
eddc9ec5
ACM		 4112 iph->check = 0;
4113 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 4114 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4115 }
5a6f3074
MC		 4116
4117 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4118 TXD_FLAG_CPU_POST_DMA);
4119
aa8223c7 4120 tcp_hdr(skb)->check = 0;
5a6f3074 4121
5a6f3074 4122 }
84fa7933 4123 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 4124 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 4125#if TG3_VLAN_TAG_USED
4126 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4127 base_flags |= (TXD_FLAG_VLAN |
4128 (vlan_tx_tag_get(skb) << 16));
4129#endif
4130
4131 /* Queue skb data, a.k.a. the main skb fragment. */
4132 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4133
4134 tp->tx_buffers[entry].skb = skb;
4135 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4136
4137 tg3_set_txd(tp, entry, mapping, len, base_flags,
4138 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4139
4140 entry = NEXT_TX(entry);
4141
4142 /* Now loop through additional data fragments, and queue them. */
4143 if (skb_shinfo(skb)->nr_frags > 0) {
4144 unsigned int i, last;
4145
4146 last = skb_shinfo(skb)->nr_frags - 1;
4147 for (i = 0; i <= last; i++) {
4148 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4149
4150 len = frag->size;
4151 mapping = pci_map_page(tp->pdev,
4152 frag->page,
4153 frag->page_offset,
4154 len, PCI_DMA_TODEVICE);
4155
4156 tp->tx_buffers[entry].skb = NULL;
4157 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4158
4159 tg3_set_txd(tp, entry, mapping, len,
4160 base_flags, (i == last) | (mss << 1));
4161
4162 entry = NEXT_TX(entry);
4163 }
4164 }
4165
4166 /* Packets are ready, update Tx producer idx local and on card. */
4167 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4168
4169 tp->tx_prod = entry;
1b2a7205 4170 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 4171 netif_stop_queue(dev);
42952231 4172 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 4173 netif_wake_queue(tp->dev);
4174 }
4175
4176out_unlock:
4177 mmiowb();
5a6f3074
MC		 4178
4179 dev->trans_start = jiffies;
4180
4181 return NETDEV_TX_OK;
4182}
4183
52c0fd83
MC		 4184static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4185
4186/* Use GSO to workaround a rare TSO bug that may be triggered when the
4187 * TSO header is greater than 80 bytes.
4188 */
4189static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4190{
4191 struct sk_buff *segs, *nskb;
4192
4193 /* Estimate the number of fragments in the worst case */
1b2a7205 4194 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 4195 netif_stop_queue(tp->dev);
7f62ad5d
MC		 4196 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4197 return NETDEV_TX_BUSY;
4198
4199 netif_wake_queue(tp->dev);
52c0fd83
MC		 4200 }
4201
4202 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4203 if (unlikely(IS_ERR(segs)))
4204 goto tg3_tso_bug_end;
4205
4206 do {
4207 nskb = segs;
4208 segs = segs->next;
4209 nskb->next = NULL;
4210 tg3_start_xmit_dma_bug(nskb, tp->dev);
4211 } while (segs);
4212
4213tg3_tso_bug_end:
4214 dev_kfree_skb(skb);
4215
4216 return NETDEV_TX_OK;
4217}
52c0fd83 4218
5a6f3074
MC		 4219/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4220 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4221 */
4222static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4223{
4224 struct tg3 *tp = netdev_priv(dev);
4225 dma_addr_t mapping;
1da177e4
LT		 4226 u32 len, entry, base_flags, mss;
4227 int would_hit_hwbug;
1da177e4
LT		 4228
4229 len = skb_headlen(skb);
4230
00b70504 4231 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4232 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 4233 * interrupt. Furthermore, IRQ processing runs lockless so we have
4234 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4235 */
1b2a7205 4236 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4237 if (!netif_queue_stopped(dev)) {
4238 netif_stop_queue(dev);
4239
4240 /* This is a hard error, log it. */
4241 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4242 "queue awake!\n", dev->name);
4243 }
1da177e4
LT		 4244 return NETDEV_TX_BUSY;
4245 }
4246
4247 entry = tp->tx_prod;
4248 base_flags = 0;
84fa7933 4249 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4250 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 4251 mss = 0;
c13e3713 4252 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 4253 struct iphdr *iph;
52c0fd83 4254 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4255
4256 if (skb_header_cloned(skb) &&
4257 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4258 dev_kfree_skb(skb);
4259 goto out_unlock;
4260 }
4261
ab6a5bb6 4262 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4263 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 4264
52c0fd83
MC		 4265 hdr_len = ip_tcp_len + tcp_opt_len;
4266 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 4267 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 4268 return (tg3_tso_bug(tp, skb));
4269
1da177e4
LT		 4270 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4271 TXD_FLAG_CPU_POST_DMA);
4272
eddc9ec5
ACM		 4273 iph = ip_hdr(skb);
4274 iph->check = 0;
4275 iph->tot_len = htons(mss + hdr_len);
1da177e4 4276 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 4277 tcp_hdr(skb)->check = 0;
1da177e4 4278 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 4279 } else
4280 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4281 iph->daddr, 0,
4282 IPPROTO_TCP,
4283 0);
1da177e4
LT		 4284
4285 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4286 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 4287 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4288 int tsflags;
4289
eddc9ec5 4290 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4291 mss |= (tsflags << 11);
4292 }
4293 } else {
eddc9ec5 4294 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4295 int tsflags;
4296
eddc9ec5 4297 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4298 base_flags |= tsflags << 12;
4299 }
4300 }
4301 }
1da177e4
LT		 4302#if TG3_VLAN_TAG_USED
4303 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4304 base_flags |= (TXD_FLAG_VLAN |
4305 (vlan_tx_tag_get(skb) << 16));
4306#endif
4307
4308 /* Queue skb data, a.k.a. the main skb fragment. */
4309 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4310
4311 tp->tx_buffers[entry].skb = skb;
4312 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4313
4314 would_hit_hwbug = 0;
4315
4316 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4317 would_hit_hwbug = 1;
1da177e4
LT		 4318
4319 tg3_set_txd(tp, entry, mapping, len, base_flags,
4320 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4321
4322 entry = NEXT_TX(entry);
4323
4324 /* Now loop through additional data fragments, and queue them. */
4325 if (skb_shinfo(skb)->nr_frags > 0) {
4326 unsigned int i, last;
4327
4328 last = skb_shinfo(skb)->nr_frags - 1;
4329 for (i = 0; i <= last; i++) {
4330 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4331
4332 len = frag->size;
4333 mapping = pci_map_page(tp->pdev,
4334 frag->page,
4335 frag->page_offset,
4336 len, PCI_DMA_TODEVICE);
4337
4338 tp->tx_buffers[entry].skb = NULL;
4339 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4340
c58ec932
MC		 4341 if (tg3_4g_overflow_test(mapping, len))
4342 would_hit_hwbug = 1;
1da177e4 4343
72f2afb8
MC		 4344 if (tg3_40bit_overflow_test(tp, mapping, len))
4345 would_hit_hwbug = 1;
4346
1da177e4
LT		 4347 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4348 tg3_set_txd(tp, entry, mapping, len,
4349 base_flags, (i == last)|(mss << 1));
4350 else
4351 tg3_set_txd(tp, entry, mapping, len,
4352 base_flags, (i == last));
4353
4354 entry = NEXT_TX(entry);
4355 }
4356 }
4357
4358 if (would_hit_hwbug) {
4359 u32 last_plus_one = entry;
4360 u32 start;
1da177e4 4361
c58ec932
MC		 4362 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4363 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4364
4365 /* If the workaround fails due to memory/mapping
4366 * failure, silently drop this packet.
4367 */
72f2afb8 4368 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4369 &start, base_flags, mss))
1da177e4
LT		 4370 goto out_unlock;
4371
4372 entry = start;
4373 }
4374
4375 /* Packets are ready, update Tx producer idx local and on card. */
4376 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4377
4378 tp->tx_prod = entry;
1b2a7205 4379 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4380 netif_stop_queue(dev);
42952231 4381 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4382 netif_wake_queue(tp->dev);
4383 }
1da177e4
LT		 4384
4385out_unlock:
4386 mmiowb();
1da177e4
LT		 4387
4388 dev->trans_start = jiffies;
4389
4390 return NETDEV_TX_OK;
4391}
4392
4393static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4394 int new_mtu)
4395{
4396 dev->mtu = new_mtu;
4397
ef7f5ec0 4398 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4399 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4400 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4401 ethtool_op_set_tso(dev, 0);
4402 }
4403 else
4404 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4405 } else {
a4e2b347 4406 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4407 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4408 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4409 }
1da177e4
LT		 4410}
4411
4412static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4413{
4414 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4415 int err;
1da177e4
LT		 4416
4417 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4418 return -EINVAL;
4419
4420 if (!netif_running(dev)) {
4421 /* We'll just catch it later when the
4422 * device is up'd.
4423 */
4424 tg3_set_mtu(dev, tp, new_mtu);
4425 return 0;
4426 }
4427
4428 tg3_netif_stop(tp);
f47c11ee
DM		 4429
4430 tg3_full_lock(tp, 1);
1da177e4 4431
944d980e 4432 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4433
4434 tg3_set_mtu(dev, tp, new_mtu);
4435
b9ec6c1b 4436 err = tg3_restart_hw(tp, 0);
1da177e4 4437
b9ec6c1b
MC		 4438 if (!err)
4439 tg3_netif_start(tp);
1da177e4 4440
f47c11ee 4441 tg3_full_unlock(tp);
1da177e4 4442
b9ec6c1b 4443 return err;
1da177e4
LT		 4444}
4445
4446/* Free up pending packets in all rx/tx rings.
4447 *
4448 * The chip has been shut down and the driver detached from
4449 * the networking, so no interrupts or new tx packets will
4450 * end up in the driver. tp->{tx,}lock is not held and we are not
4451 * in an interrupt context and thus may sleep.
4452 */
4453static void tg3_free_rings(struct tg3 *tp)
4454{
4455 struct ring_info *rxp;
4456 int i;
4457
4458 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4459 rxp = &tp->rx_std_buffers[i];
4460
4461 if (rxp->skb == NULL)
4462 continue;
4463 pci_unmap_single(tp->pdev,
4464 pci_unmap_addr(rxp, mapping),
7e72aad4 4465 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4466 PCI_DMA_FROMDEVICE);
4467 dev_kfree_skb_any(rxp->skb);
4468 rxp->skb = NULL;
4469 }
4470
4471 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4472 rxp = &tp->rx_jumbo_buffers[i];
4473
4474 if (rxp->skb == NULL)
4475 continue;
4476 pci_unmap_single(tp->pdev,
4477 pci_unmap_addr(rxp, mapping),
4478 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4479 PCI_DMA_FROMDEVICE);
4480 dev_kfree_skb_any(rxp->skb);
4481 rxp->skb = NULL;
4482 }
4483
4484 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4485 struct tx_ring_info *txp;
4486 struct sk_buff *skb;
4487 int j;
4488
4489 txp = &tp->tx_buffers[i];
4490 skb = txp->skb;
4491
4492 if (skb == NULL) {
4493 i++;
4494 continue;
4495 }
4496
4497 pci_unmap_single(tp->pdev,
4498 pci_unmap_addr(txp, mapping),
4499 skb_headlen(skb),
4500 PCI_DMA_TODEVICE);
4501 txp->skb = NULL;
4502
4503 i++;
4504
4505 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4506 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4507 pci_unmap_page(tp->pdev,
4508 pci_unmap_addr(txp, mapping),
4509 skb_shinfo(skb)->frags[j].size,
4510 PCI_DMA_TODEVICE);
4511 i++;
4512 }
4513
4514 dev_kfree_skb_any(skb);
4515 }
4516}
4517
4518/* Initialize tx/rx rings for packet processing.
4519 *
4520 * The chip has been shut down and the driver detached from
4521 * the networking, so no interrupts or new tx packets will
4522 * end up in the driver. tp->{tx,}lock are held and thus
4523 * we may not sleep.
4524 */
32d8c572 4525static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4526{
4527 u32 i;
4528
4529 /* Free up all the SKBs. */
4530 tg3_free_rings(tp);
4531
4532 /* Zero out all descriptors. */
4533 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4534 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4535 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4536 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4537
7e72aad4 4538 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4539 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4540 (tp->dev->mtu > ETH_DATA_LEN))
4541 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4542
1da177e4
LT		 4543 /* Initialize invariants of the rings, we only set this
4544 * stuff once. This works because the card does not
4545 * write into the rx buffer posting rings.
4546 */
4547 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4548 struct tg3_rx_buffer_desc *rxd;
4549
4550 rxd = &tp->rx_std[i];
7e72aad4 4551 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4552 << RXD_LEN_SHIFT;
4553 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4554 rxd->opaque = (RXD_OPAQUE_RING_STD |
4555 (i << RXD_OPAQUE_INDEX_SHIFT));
4556 }
4557
0f893dc6 4558 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4559 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4560 struct tg3_rx_buffer_desc *rxd;
4561
4562 rxd = &tp->rx_jumbo[i];
4563 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4564 << RXD_LEN_SHIFT;
4565 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4566 RXD_FLAG_JUMBO;
4567 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4568 (i << RXD_OPAQUE_INDEX_SHIFT));
4569 }
4570 }
4571
4572 /* Now allocate fresh SKBs for each rx ring. */
4573 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4574 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4575 printk(KERN_WARNING PFX
4576 "%s: Using a smaller RX standard ring, "
4577 "only %d out of %d buffers were allocated "
4578 "successfully.\n",
4579 tp->dev->name, i, tp->rx_pending);
4580 if (i == 0)
4581 return -ENOMEM;
4582 tp->rx_pending = i;
1da177e4 4583 break;
32d8c572 4584 }
1da177e4
LT		 4585 }
4586
0f893dc6 4587 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4588 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4589 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4590 -1, i) < 0) {
4591 printk(KERN_WARNING PFX
4592 "%s: Using a smaller RX jumbo ring, "
4593 "only %d out of %d buffers were "
4594 "allocated successfully.\n",
4595 tp->dev->name, i, tp->rx_jumbo_pending);
4596 if (i == 0) {
4597 tg3_free_rings(tp);
4598 return -ENOMEM;
4599 }
4600 tp->rx_jumbo_pending = i;
1da177e4 4601 break;
32d8c572 4602 }
1da177e4
LT		 4603 }
4604 }
32d8c572 4605 return 0;
1da177e4
LT		 4606}
4607
4608/*
4609 * Must not be invoked with interrupt sources disabled and
4610 * the hardware shutdown down.
4611 */
4612static void tg3_free_consistent(struct tg3 *tp)
4613{
b4558ea9
JJ		 4614 kfree(tp->rx_std_buffers);
4615 tp->rx_std_buffers = NULL;
1da177e4
LT		 4616 if (tp->rx_std) {
4617 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4618 tp->rx_std, tp->rx_std_mapping);
4619 tp->rx_std = NULL;
4620 }
4621 if (tp->rx_jumbo) {
4622 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4623 tp->rx_jumbo, tp->rx_jumbo_mapping);
4624 tp->rx_jumbo = NULL;
4625 }
4626 if (tp->rx_rcb) {
4627 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4628 tp->rx_rcb, tp->rx_rcb_mapping);
4629 tp->rx_rcb = NULL;
4630 }
4631 if (tp->tx_ring) {
4632 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4633 tp->tx_ring, tp->tx_desc_mapping);
4634 tp->tx_ring = NULL;
4635 }
4636 if (tp->hw_status) {
4637 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4638 tp->hw_status, tp->status_mapping);
4639 tp->hw_status = NULL;
4640 }
4641 if (tp->hw_stats) {
4642 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4643 tp->hw_stats, tp->stats_mapping);
4644 tp->hw_stats = NULL;
4645 }
4646}
4647
4648/*
4649 * Must not be invoked with interrupt sources disabled and
4650 * the hardware shutdown down. Can sleep.
4651 */
4652static int tg3_alloc_consistent(struct tg3 *tp)
4653{
bd2b3343 4654 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4655 (TG3_RX_RING_SIZE +
4656 TG3_RX_JUMBO_RING_SIZE)) +
4657 (sizeof(struct tx_ring_info) *
4658 TG3_TX_RING_SIZE),
4659 GFP_KERNEL);
4660 if (!tp->rx_std_buffers)
4661 return -ENOMEM;
4662
1da177e4
LT		 4663 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4664 tp->tx_buffers = (struct tx_ring_info *)
4665 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4666
4667 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4668 &tp->rx_std_mapping);
4669 if (!tp->rx_std)
4670 goto err_out;
4671
4672 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4673 &tp->rx_jumbo_mapping);
4674
4675 if (!tp->rx_jumbo)
4676 goto err_out;
4677
4678 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4679 &tp->rx_rcb_mapping);
4680 if (!tp->rx_rcb)
4681 goto err_out;
4682
4683 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4684 &tp->tx_desc_mapping);
4685 if (!tp->tx_ring)
4686 goto err_out;
4687
4688 tp->hw_status = pci_alloc_consistent(tp->pdev,
4689 TG3_HW_STATUS_SIZE,
4690 &tp->status_mapping);
4691 if (!tp->hw_status)
4692 goto err_out;
4693
4694 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4695 sizeof(struct tg3_hw_stats),
4696 &tp->stats_mapping);
4697 if (!tp->hw_stats)
4698 goto err_out;
4699
4700 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4701 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4702
4703 return 0;
4704
4705err_out:
4706 tg3_free_consistent(tp);
4707 return -ENOMEM;
4708}
4709
4710#define MAX_WAIT_CNT 1000
4711
4712/* To stop a block, clear the enable bit and poll till it
4713 * clears. tp->lock is held.
4714 */
b3b7d6be 4715static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4716{
4717 unsigned int i;
4718 u32 val;
4719
4720 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4721 switch (ofs) {
4722 case RCVLSC_MODE:
4723 case DMAC_MODE:
4724 case MBFREE_MODE:
4725 case BUFMGR_MODE:
4726 case MEMARB_MODE:
4727 /* We can't enable/disable these bits of the
4728 * 5705/5750, just say success.
4729 */
4730 return 0;
4731
4732 default:
4733 break;
4734 };
4735 }
4736
4737 val = tr32(ofs);
4738 val &= ~enable_bit;
4739 tw32_f(ofs, val);
4740
4741 for (i = 0; i < MAX_WAIT_CNT; i++) {
4742 udelay(100);
4743 val = tr32(ofs);
4744 if ((val & enable_bit) == 0)
4745 break;
4746 }
4747
b3b7d6be 4748 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4749 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4750 "ofs=%lx enable_bit=%x\n",
4751 ofs, enable_bit);
4752 return -ENODEV;
4753 }
4754
4755 return 0;
4756}
4757
4758/* tp->lock is held. */
b3b7d6be 4759static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4760{
4761 int i, err;
4762
4763 tg3_disable_ints(tp);
4764
4765 tp->rx_mode &= ~RX_MODE_ENABLE;
4766 tw32_f(MAC_RX_MODE, tp->rx_mode);
4767 udelay(10);
4768
b3b7d6be
DM		 4769 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4770 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4771 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4772 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4773 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4774 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4775
4776 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4777 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4778 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4779 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4780 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4781 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4782 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4783
4784 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4785 tw32_f(MAC_MODE, tp->mac_mode);
4786 udelay(40);
4787
4788 tp->tx_mode &= ~TX_MODE_ENABLE;
4789 tw32_f(MAC_TX_MODE, tp->tx_mode);
4790
4791 for (i = 0; i < MAX_WAIT_CNT; i++) {
4792 udelay(100);
4793 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4794 break;
4795 }
4796 if (i >= MAX_WAIT_CNT) {
4797 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4798 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4799 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4800 err |= -ENODEV;
1da177e4
LT		 4801 }
4802
e6de8ad1 4803 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4804 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4805 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4806
4807 tw32(FTQ_RESET, 0xffffffff);
4808 tw32(FTQ_RESET, 0x00000000);
4809
b3b7d6be
DM		 4810 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4811 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4812
4813 if (tp->hw_status)
4814 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4815 if (tp->hw_stats)
4816 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4817
1da177e4
LT		 4818 return err;
4819}
4820
4821/* tp->lock is held. */
4822static int tg3_nvram_lock(struct tg3 *tp)
4823{
4824 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4825 int i;
4826
ec41c7df
MC		 4827 if (tp->nvram_lock_cnt == 0) {
4828 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4829 for (i = 0; i < 8000; i++) {
4830 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4831 break;
4832 udelay(20);
4833 }
4834 if (i == 8000) {
4835 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4836 return -ENODEV;
4837 }
1da177e4 4838 }
ec41c7df 4839 tp->nvram_lock_cnt++;
1da177e4
LT		 4840 }
4841 return 0;
4842}
4843
4844/* tp->lock is held. */
4845static void tg3_nvram_unlock(struct tg3 *tp)
4846{
ec41c7df
MC		 4847 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4848 if (tp->nvram_lock_cnt > 0)
4849 tp->nvram_lock_cnt--;
4850 if (tp->nvram_lock_cnt == 0)
4851 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4852 }
1da177e4
LT		 4853}
4854
e6af301b
MC		 4855/* tp->lock is held. */
4856static void tg3_enable_nvram_access(struct tg3 *tp)
4857{
4858 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4859 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4860 u32 nvaccess = tr32(NVRAM_ACCESS);
4861
4862 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4863 }
4864}
4865
4866/* tp->lock is held. */
4867static void tg3_disable_nvram_access(struct tg3 *tp)
4868{
4869 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4870 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4871 u32 nvaccess = tr32(NVRAM_ACCESS);
4872
4873 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4874 }
4875}
4876
0d3031d9
MC		 4877static void tg3_ape_send_event(struct tg3 *tp, u32 event)
4878{
4879 int i;
4880 u32 apedata;
4881
4882 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
4883 if (apedata != APE_SEG_SIG_MAGIC)
4884 return;
4885
4886 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
4887 if (apedata != APE_FW_STATUS_READY)
4888 return;
4889
4890 /* Wait for up to 1 millisecond for APE to service previous event. */
4891 for (i = 0; i < 10; i++) {
4892 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
4893 return;
4894
4895 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
4896
4897 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4898 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
4899 event | APE_EVENT_STATUS_EVENT_PENDING);
4900
4901 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
4902
4903 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4904 break;
4905
4906 udelay(100);
4907 }
4908
4909 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4910 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
4911}
4912
4913static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
4914{
4915 u32 event;
4916 u32 apedata;
4917
4918 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
4919 return;
4920
4921 switch (kind) {
4922 case RESET_KIND_INIT:
4923 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
4924 APE_HOST_SEG_SIG_MAGIC);
4925 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
4926 APE_HOST_SEG_LEN_MAGIC);
4927 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
4928 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
4929 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
4930 APE_HOST_DRIVER_ID_MAGIC);
4931 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
4932 APE_HOST_BEHAV_NO_PHYLOCK);
4933
4934 event = APE_EVENT_STATUS_STATE_START;
4935 break;
4936 case RESET_KIND_SHUTDOWN:
4937 event = APE_EVENT_STATUS_STATE_UNLOAD;
4938 break;
4939 case RESET_KIND_SUSPEND:
4940 event = APE_EVENT_STATUS_STATE_SUSPEND;
4941 break;
4942 default:
4943 return;
4944 }
4945
4946 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
4947
4948 tg3_ape_send_event(tp, event);
4949}
4950
1da177e4
LT		 4951/* tp->lock is held. */
4952static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4953{
f49639e6
DM		 4954 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4955 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4956
4957 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4958 switch (kind) {
4959 case RESET_KIND_INIT:
4960 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4961 DRV_STATE_START);
4962 break;
4963
4964 case RESET_KIND_SHUTDOWN:
4965 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4966 DRV_STATE_UNLOAD);
4967 break;
4968
4969 case RESET_KIND_SUSPEND:
4970 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4971 DRV_STATE_SUSPEND);
4972 break;
4973
4974 default:
4975 break;
4976 };
4977 }
0d3031d9
MC		 4978
4979 if (kind == RESET_KIND_INIT ||
4980 kind == RESET_KIND_SUSPEND)
4981 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 4982}
4983
4984/* tp->lock is held. */
4985static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4986{
4987 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4988 switch (kind) {
4989 case RESET_KIND_INIT:
4990 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4991 DRV_STATE_START_DONE);
4992 break;
4993
4994 case RESET_KIND_SHUTDOWN:
4995 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4996 DRV_STATE_UNLOAD_DONE);
4997 break;
4998
4999 default:
5000 break;
5001 };
5002 }
0d3031d9
MC		 5003
5004 if (kind == RESET_KIND_SHUTDOWN)
5005 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5006}
5007
5008/* tp->lock is held. */
5009static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5010{
5011 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5012 switch (kind) {
5013 case RESET_KIND_INIT:
5014 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5015 DRV_STATE_START);
5016 break;
5017
5018 case RESET_KIND_SHUTDOWN:
5019 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5020 DRV_STATE_UNLOAD);
5021 break;
5022
5023 case RESET_KIND_SUSPEND:
5024 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5025 DRV_STATE_SUSPEND);
5026 break;
5027
5028 default:
5029 break;
5030 };
5031 }
5032}
5033
7a6f4369
MC		 5034static int tg3_poll_fw(struct tg3 *tp)
5035{
5036 int i;
5037 u32 val;
5038
b5d3772c 5039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 5040 /* Wait up to 20ms for init done. */
5041 for (i = 0; i < 200; i++) {
b5d3772c
MC		 5042 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5043 return 0;
0ccead18 5044 udelay(100);
b5d3772c
MC		 5045 }
5046 return -ENODEV;
5047 }
5048
7a6f4369
MC		 5049 /* Wait for firmware initialization to complete. */
5050 for (i = 0; i < 100000; i++) {
5051 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5052 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5053 break;
5054 udelay(10);
5055 }
5056
5057 /* Chip might not be fitted with firmware. Some Sun onboard
5058 * parts are configured like that. So don't signal the timeout
5059 * of the above loop as an error, but do report the lack of
5060 * running firmware once.
5061 */
5062 if (i >= 100000 &&
5063 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5064 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5065
5066 printk(KERN_INFO PFX "%s: No firmware running.\n",
5067 tp->dev->name);
5068 }
5069
5070 return 0;
5071}
5072
ee6a99b5
MC		 5073/* Save PCI command register before chip reset */
5074static void tg3_save_pci_state(struct tg3 *tp)
5075{
8a6eac90 5076 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 5077}
5078
5079/* Restore PCI state after chip reset */
5080static void tg3_restore_pci_state(struct tg3 *tp)
5081{
5082 u32 val;
5083
5084 /* Re-enable indirect register accesses. */
5085 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5086 tp->misc_host_ctrl);
5087
5088 /* Set MAX PCI retry to zero. */
5089 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5090 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5091 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5092 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 5093 /* Allow reads and writes to the APE register and memory space. */
5094 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5095 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5096 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 5097 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5098
8a6eac90 5099 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 5100
114342f2
MC		 5101 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5102 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5103 tp->pci_cacheline_sz);
5104 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5105 tp->pci_lat_timer);
5106 }
ee6a99b5 5107 /* Make sure PCI-X relaxed ordering bit is clear. */
9974a356
MC		 5108 if (tp->pcix_cap) {
5109 u16 pcix_cmd;
5110
5111 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5112 &pcix_cmd);
5113 pcix_cmd &= ~PCI_X_CMD_ERO;
5114 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5115 pcix_cmd);
5116 }
ee6a99b5
MC		 5117
5118 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 5119
5120 /* Chip reset on 5780 will reset MSI enable bit,
5121 * so need to restore it.
5122 */
5123 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5124 u16 ctrl;
5125
5126 pci_read_config_word(tp->pdev,
5127 tp->msi_cap + PCI_MSI_FLAGS,
5128 &ctrl);
5129 pci_write_config_word(tp->pdev,
5130 tp->msi_cap + PCI_MSI_FLAGS,
5131 ctrl | PCI_MSI_FLAGS_ENABLE);
5132 val = tr32(MSGINT_MODE);
5133 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5134 }
5135 }
5136}
5137
1da177e4
LT		 5138static void tg3_stop_fw(struct tg3 *);
5139
5140/* tp->lock is held. */
5141static int tg3_chip_reset(struct tg3 *tp)
5142{
5143 u32 val;
1ee582d8 5144 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 5145 int err;
1da177e4 5146
f49639e6
DM		 5147 tg3_nvram_lock(tp);
5148
5149 /* No matching tg3_nvram_unlock() after this because
5150 * chip reset below will undo the nvram lock.
5151 */
5152 tp->nvram_lock_cnt = 0;
1da177e4 5153
ee6a99b5
MC		 5154 /* GRC_MISC_CFG core clock reset will clear the memory
5155 * enable bit in PCI register 4 and the MSI enable bit
5156 * on some chips, so we save relevant registers here.
5157 */
5158 tg3_save_pci_state(tp);
5159
d9ab5ad1 5160 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 5161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 5162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 5163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d9ab5ad1
MC		 5165 tw32(GRC_FASTBOOT_PC, 0);
5166
1da177e4
LT		 5167 /*
5168 * We must avoid the readl() that normally takes place.
5169 * It locks machines, causes machine checks, and other
5170 * fun things. So, temporarily disable the 5701
5171 * hardware workaround, while we do the reset.
5172 */
1ee582d8
MC		 5173 write_op = tp->write32;
5174 if (write_op == tg3_write_flush_reg32)
5175 tp->write32 = tg3_write32;
1da177e4 5176
d18edcb2
MC		 5177 /* Prevent the irq handler from reading or writing PCI registers
5178 * during chip reset when the memory enable bit in the PCI command
5179 * register may be cleared. The chip does not generate interrupt
5180 * at this time, but the irq handler may still be called due to irq
5181 * sharing or irqpoll.
5182 */
5183 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 5184 if (tp->hw_status) {
5185 tp->hw_status->status = 0;
5186 tp->hw_status->status_tag = 0;
5187 }
d18edcb2
MC		 5188 tp->last_tag = 0;
5189 smp_mb();
5190 synchronize_irq(tp->pdev->irq);
5191
1da177e4
LT		 5192 /* do the reset */
5193 val = GRC_MISC_CFG_CORECLK_RESET;
5194
5195 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5196 if (tr32(0x7e2c) == 0x60) {
5197 tw32(0x7e2c, 0x20);
5198 }
5199 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5200 tw32(GRC_MISC_CFG, (1 << 29));
5201 val |= (1 << 29);
5202 }
5203 }
5204
b5d3772c
MC		 5205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5206 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5207 tw32(GRC_VCPU_EXT_CTRL,
5208 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5209 }
5210
1da177e4
LT		 5211 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5212 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5213 tw32(GRC_MISC_CFG, val);
5214
1ee582d8
MC		 5215 /* restore 5701 hardware bug workaround write method */
5216 tp->write32 = write_op;
1da177e4
LT		 5217
5218 /* Unfortunately, we have to delay before the PCI read back.
5219 * Some 575X chips even will not respond to a PCI cfg access
5220 * when the reset command is given to the chip.
5221 *
5222 * How do these hardware designers expect things to work
5223 * properly if the PCI write is posted for a long period
5224 * of time? It is always necessary to have some method by
5225 * which a register read back can occur to push the write
5226 * out which does the reset.
5227 *
5228 * For most tg3 variants the trick below was working.
5229 * Ho hum...
5230 */
5231 udelay(120);
5232
5233 /* Flush PCI posted writes. The normal MMIO registers
5234 * are inaccessible at this time so this is the only
5235 * way to make this reliably (actually, this is no longer
5236 * the case, see above). I tried to use indirect
5237 * register read/write but this upset some 5701 variants.
5238 */
5239 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5240
5241 udelay(120);
5242
5243 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5244 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5245 int i;
5246 u32 cfg_val;
5247
5248 /* Wait for link training to complete. */
5249 for (i = 0; i < 5000; i++)
5250 udelay(100);
5251
5252 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5253 pci_write_config_dword(tp->pdev, 0xc4,
5254 cfg_val | (1 << 15));
5255 }
5256 /* Set PCIE max payload size and clear error status. */
5257 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5258 }
5259
ee6a99b5 5260 tg3_restore_pci_state(tp);
1da177e4 5261
d18edcb2
MC		 5262 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5263
ee6a99b5
MC		 5264 val = 0;
5265 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 5266 val = tr32(MEMARB_MODE);
ee6a99b5 5267 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 5268
5269 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5270 tg3_stop_fw(tp);
5271 tw32(0x5000, 0x400);
5272 }
5273
5274 tw32(GRC_MODE, tp->grc_mode);
5275
5276 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 5277 val = tr32(0xc4);
1da177e4
LT		 5278
5279 tw32(0xc4, val | (1 << 15));
5280 }
5281
5282 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5283 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5284 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5285 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5286 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5287 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5288 }
5289
5290 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5291 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5292 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 5293 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5294 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5295 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 5296 } else
5297 tw32_f(MAC_MODE, 0);
5298 udelay(40);
5299
7a6f4369
MC		 5300 err = tg3_poll_fw(tp);
5301 if (err)
5302 return err;
1da177e4
LT		 5303
5304 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5305 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 5306 val = tr32(0x7c00);
1da177e4
LT		 5307
5308 tw32(0x7c00, val | (1 << 25));
5309 }
5310
5311 /* Reprobe ASF enable state. */
5312 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5313 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5314 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5315 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5316 u32 nic_cfg;
5317
5318 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5319 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5320 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 5321 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 5322 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5323 }
5324 }
5325
5326 return 0;
5327}
5328
5329/* tp->lock is held. */
5330static void tg3_stop_fw(struct tg3 *tp)
5331{
0d3031d9
MC		 5332 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5333 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 5334 u32 val;
5335 int i;
5336
5337 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5338 val = tr32(GRC_RX_CPU_EVENT);
5339 val |= (1 << 14);
5340 tw32(GRC_RX_CPU_EVENT, val);
5341
5342 /* Wait for RX cpu to ACK the event. */
5343 for (i = 0; i < 100; i++) {
5344 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5345 break;
5346 udelay(1);
5347 }
5348 }
5349}
5350
5351/* tp->lock is held. */
944d980e 5352static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 5353{
5354 int err;
5355
5356 tg3_stop_fw(tp);
5357
944d980e 5358 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5359
b3b7d6be 5360 tg3_abort_hw(tp, silent);
1da177e4
LT		 5361 err = tg3_chip_reset(tp);
5362
944d980e
MC		 5363 tg3_write_sig_legacy(tp, kind);
5364 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5365
5366 if (err)
5367 return err;
5368
5369 return 0;
5370}
5371
5372#define TG3_FW_RELEASE_MAJOR 0x0
5373#define TG3_FW_RELASE_MINOR 0x0
5374#define TG3_FW_RELEASE_FIX 0x0
5375#define TG3_FW_START_ADDR 0x08000000
5376#define TG3_FW_TEXT_ADDR 0x08000000
5377#define TG3_FW_TEXT_LEN 0x9c0
5378#define TG3_FW_RODATA_ADDR 0x080009c0
5379#define TG3_FW_RODATA_LEN 0x60
5380#define TG3_FW_DATA_ADDR 0x08000a40
5381#define TG3_FW_DATA_LEN 0x20
5382#define TG3_FW_SBSS_ADDR 0x08000a60
5383#define TG3_FW_SBSS_LEN 0xc
5384#define TG3_FW_BSS_ADDR 0x08000a70
5385#define TG3_FW_BSS_LEN 0x10
5386
50da859d 5387static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5388 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5389 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5390 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5391 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5392 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5393 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5394 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5395 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5396 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5397 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5398 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5399 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5400 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5401 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5402 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5403 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5404 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5405 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5406 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5407 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5408 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5409 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5410 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5411 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5412 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5413 0, 0, 0, 0, 0, 0,
5414 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5415 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5416 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5417 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5418 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5419 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5420 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5421 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5422 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5423 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5424 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5426 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5427 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5428 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5429 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5430 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5431 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5432 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5433 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5434 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5435 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5436 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5437 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5438 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5439 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5440 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5441 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5442 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5443 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5444 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5445 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5446 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5447 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5448 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5449 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5450 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5451 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5452 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5453 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5454 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5455 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5456 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5457 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5458 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5459 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5460 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5461 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5462 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5463 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5464 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5465 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5466 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5467 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5468 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5469 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5470 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5471 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5472 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5473 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5474 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5475 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5476 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5477 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5478 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5479};
5480
50da859d 5481static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5482 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5483 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5484 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5485 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5486 0x00000000
5487};
5488
5489#if 0 /* All zeros, don't eat up space with it. */
5490u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5491 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5492 0x00000000, 0x00000000, 0x00000000, 0x00000000
5493};
5494#endif
5495
5496#define RX_CPU_SCRATCH_BASE 0x30000
5497#define RX_CPU_SCRATCH_SIZE 0x04000
5498#define TX_CPU_SCRATCH_BASE 0x34000
5499#define TX_CPU_SCRATCH_SIZE 0x04000
5500
5501/* tp->lock is held. */
5502static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5503{
5504 int i;
5505
5d9428de
ES		 5506 BUG_ON(offset == TX_CPU_BASE &&
5507 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5508
b5d3772c
MC		 5509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5510 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5511
5512 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5513 return 0;
5514 }
1da177e4
LT		 5515 if (offset == RX_CPU_BASE) {
5516 for (i = 0; i < 10000; i++) {
5517 tw32(offset + CPU_STATE, 0xffffffff);
5518 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5519 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5520 break;
5521 }
5522
5523 tw32(offset + CPU_STATE, 0xffffffff);
5524 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5525 udelay(10);
5526 } else {
5527 for (i = 0; i < 10000; i++) {
5528 tw32(offset + CPU_STATE, 0xffffffff);
5529 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5530 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5531 break;
5532 }
5533 }
5534
5535 if (i >= 10000) {
5536 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5537 "and %s CPU\n",
5538 tp->dev->name,
5539 (offset == RX_CPU_BASE ? "RX" : "TX"));
5540 return -ENODEV;
5541 }
ec41c7df
MC		 5542
5543 /* Clear firmware's nvram arbitration. */
5544 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5545 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5546 return 0;
5547}
5548
5549struct fw_info {
5550 unsigned int text_base;
5551 unsigned int text_len;
50da859d 5552 const u32 *text_data;
1da177e4
LT		 5553 unsigned int rodata_base;
5554 unsigned int rodata_len;
50da859d 5555 const u32 *rodata_data;
1da177e4
LT		 5556 unsigned int data_base;
5557 unsigned int data_len;
50da859d 5558 const u32 *data_data;
1da177e4
LT		 5559};
5560
5561/* tp->lock is held. */
5562static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5563 int cpu_scratch_size, struct fw_info *info)
5564{
ec41c7df 5565 int err, lock_err, i;
1da177e4
LT		 5566 void (*write_op)(struct tg3 *, u32, u32);
5567
5568 if (cpu_base == TX_CPU_BASE &&
5569 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5570 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5571 "TX cpu firmware on %s which is 5705.\n",
5572 tp->dev->name);
5573 return -EINVAL;
5574 }
5575
5576 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5577 write_op = tg3_write_mem;
5578 else
5579 write_op = tg3_write_indirect_reg32;
5580
1b628151
MC		 5581 /* It is possible that bootcode is still loading at this point.
5582 * Get the nvram lock first before halting the cpu.
5583 */
ec41c7df 5584 lock_err = tg3_nvram_lock(tp);
1da177e4 5585 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5586 if (!lock_err)
5587 tg3_nvram_unlock(tp);
1da177e4
LT		 5588 if (err)
5589 goto out;
5590
5591 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5592 write_op(tp, cpu_scratch_base + i, 0);
5593 tw32(cpu_base + CPU_STATE, 0xffffffff);
5594 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5595 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5596 write_op(tp, (cpu_scratch_base +
5597 (info->text_base & 0xffff) +
5598 (i * sizeof(u32))),
5599 (info->text_data ?
5600 info->text_data[i] : 0));
5601 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5602 write_op(tp, (cpu_scratch_base +
5603 (info->rodata_base & 0xffff) +
5604 (i * sizeof(u32))),
5605 (info->rodata_data ?
5606 info->rodata_data[i] : 0));
5607 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5608 write_op(tp, (cpu_scratch_base +
5609 (info->data_base & 0xffff) +
5610 (i * sizeof(u32))),
5611 (info->data_data ?
5612 info->data_data[i] : 0));
5613
5614 err = 0;
5615
5616out:
1da177e4
LT		 5617 return err;
5618}
5619
5620/* tp->lock is held. */
5621static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5622{
5623 struct fw_info info;
5624 int err, i;
5625
5626 info.text_base = TG3_FW_TEXT_ADDR;
5627 info.text_len = TG3_FW_TEXT_LEN;
5628 info.text_data = &tg3FwText[0];
5629 info.rodata_base = TG3_FW_RODATA_ADDR;
5630 info.rodata_len = TG3_FW_RODATA_LEN;
5631 info.rodata_data = &tg3FwRodata[0];
5632 info.data_base = TG3_FW_DATA_ADDR;
5633 info.data_len = TG3_FW_DATA_LEN;
5634 info.data_data = NULL;
5635
5636 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5637 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5638 &info);
5639 if (err)
5640 return err;
5641
5642 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5643 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5644 &info);
5645 if (err)
5646 return err;
5647
5648 /* Now startup only the RX cpu. */
5649 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5650 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5651
5652 for (i = 0; i < 5; i++) {
5653 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5654 break;
5655 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5656 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5657 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5658 udelay(1000);
5659 }
5660 if (i >= 5) {
5661 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5662 "to set RX CPU PC, is %08x should be %08x\n",
5663 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5664 TG3_FW_TEXT_ADDR);
5665 return -ENODEV;
5666 }
5667 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5668 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5669
5670 return 0;
5671}
5672
1da177e4
LT		 5673
5674#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5675#define TG3_TSO_FW_RELASE_MINOR 0x6
5676#define TG3_TSO_FW_RELEASE_FIX 0x0
5677#define TG3_TSO_FW_START_ADDR 0x08000000
5678#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5679#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5680#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5681#define TG3_TSO_FW_RODATA_LEN 0x60
5682#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5683#define TG3_TSO_FW_DATA_LEN 0x30
5684#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5685#define TG3_TSO_FW_SBSS_LEN 0x2c
5686#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5687#define TG3_TSO_FW_BSS_LEN 0x894
5688
50da859d 5689static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5690 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5691 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5692 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5693 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5694 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5695 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5696 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5697 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5698 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5699 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5700 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5701 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5702 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5703 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5704 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5705 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5706 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5707 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5708 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5709 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5710 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5711 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5712 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5713 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5714 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5715 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5716 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5717 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5718 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5719 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5720 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5721 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5722 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5723 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5724 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5725 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5726 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5727 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5728 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5729 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5730 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5731 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5732 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5733 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5734 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5735 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5736 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5737 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5738 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5739 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5740 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5741 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5742 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5743 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5744 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5745 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5746 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5747 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5748 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5749 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5750 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5751 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5752 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5753 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5754 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5755 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5756 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5757 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5758 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5759 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5760 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5761 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5762 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5763 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5764 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5765 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5766 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5767 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5768 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5769 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5770 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5771 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5772 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5773 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5774 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5775 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5776 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5777 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5778 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5779 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5780 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5781 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5782 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5783 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5784 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5785 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5786 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5787 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5788 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5789 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5790 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5791 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5792 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5793 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5794 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5795 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5796 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5797 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5798 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5799 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5800 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5801 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5802 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5803 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5804 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5805 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5806 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5807 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5808 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5809 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5810 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5811 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5812 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5813 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5814 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5815 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5816 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5817 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5818 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5819 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5820 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5821 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5822 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5823 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5824 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5825 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5826 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5827 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5828 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5829 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5830 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5831 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5832 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5833 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5834 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5835 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5836 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5837 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5838 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5839 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5840 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5841 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5842 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5843 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5844 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5845 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5846 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5847 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5848 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5849 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5850 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5851 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5852 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5853 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5854 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5855 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5856 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5857 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5858 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5859 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5860 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5861 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5862 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5863 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5864 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5865 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5866 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5867 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5868 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5869 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5870 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5871 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5872 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5873 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5874 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5875 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5876 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5877 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5878 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5879 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5880 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5881 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5882 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5883 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5884 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5885 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5886 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5887 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5888 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5889 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5890 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5891 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5892 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5893 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5894 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5895 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5896 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5897 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5898 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5899 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5900 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5901 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5902 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5903 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5904 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5905 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5906 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5907 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5908 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5909 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5910 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5911 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5912 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5913 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5914 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5915 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5916 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5917 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5918 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5919 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5920 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5921 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5922 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5923 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5924 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5925 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5926 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5927 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5928 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5929 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5930 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5931 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5932 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5933 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5934 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5935 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5936 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5937 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5938 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5939 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5940 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5941 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5942 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5943 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5944 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5945 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5946 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5947 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5948 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5949 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5950 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5951 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5952 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5953 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5954 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5955 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5956 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5957 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5958 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5959 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5960 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5961 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5962 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5963 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5964 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5965 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5966 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5967 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5968 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5969 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5970 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5971 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5972 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5973 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5974};
5975
50da859d 5976static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5977 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5978 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5979 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5980 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5981 0x00000000,
5982};
5983
50da859d 5984static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5985 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5986 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5987 0x00000000,
5988};
5989
5990/* 5705 needs a special version of the TSO firmware. */
5991#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5992#define TG3_TSO5_FW_RELASE_MINOR 0x2
5993#define TG3_TSO5_FW_RELEASE_FIX 0x0
5994#define TG3_TSO5_FW_START_ADDR 0x00010000
5995#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5996#define TG3_TSO5_FW_TEXT_LEN 0xe90
5997#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5998#define TG3_TSO5_FW_RODATA_LEN 0x50
5999#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6000#define TG3_TSO5_FW_DATA_LEN 0x20
6001#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6002#define TG3_TSO5_FW_SBSS_LEN 0x28
6003#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6004#define TG3_TSO5_FW_BSS_LEN 0x88
6005
50da859d 6006static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 6007 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6008 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6009 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6010 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6011 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6012 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6013 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6014 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6015 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6016 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6017 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6018 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6019 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6020 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6021 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6022 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6023 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6024 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6025 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6026 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6027 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6028 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6029 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6030 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6031 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6032 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6033 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6034 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6035 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6036 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6037 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6038 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6039 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6040 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6041 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6042 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6043 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6044 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6045 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6046 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6047 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6048 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6049 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6050 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6051 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6052 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6053 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6054 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6055 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6056 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6057 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6058 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6059 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6060 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6061 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6062 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6063 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6064 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6065 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6066 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6067 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6068 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6069 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6070 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6071 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6072 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6073 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6074 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6075 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6076 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6077 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6078 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6079 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6080 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6081 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6082 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6083 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6084 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6085 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6086 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6087 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6088 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6089 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6090 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6091 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6092 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6093 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6094 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6095 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6096 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6097 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6098 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6099 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6100 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6101 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6102 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6103 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6104 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6105 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6106 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6107 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6108 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6109 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6110 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6111 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6112 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6113 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6114 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6115 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6116 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6117 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6118 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6119 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6120 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6121 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6122 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6123 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6124 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6125 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6126 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6127 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6128 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6129 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6130 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6131 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6132 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6133 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6134 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6135 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6136 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6137 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6138 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6139 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6140 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6141 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6142 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6143 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6144 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6145 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6146 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6147 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6148 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6149 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6150 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6151 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6152 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6153 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6154 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6155 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6156 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6157 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6158 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6159 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6160 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6161 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6162 0x00000000, 0x00000000, 0x00000000,
6163};
6164
50da859d 6165static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 6166 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6167 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6168 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6169 0x00000000, 0x00000000, 0x00000000,
6170};
6171
50da859d 6172static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 6173 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6174 0x00000000, 0x00000000, 0x00000000,
6175};
6176
6177/* tp->lock is held. */
6178static int tg3_load_tso_firmware(struct tg3 *tp)
6179{
6180 struct fw_info info;
6181 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6182 int err, i;
6183
6184 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6185 return 0;
6186
6187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6188 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6189 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6190 info.text_data = &tg3Tso5FwText[0];
6191 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6192 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6193 info.rodata_data = &tg3Tso5FwRodata[0];
6194 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6195 info.data_len = TG3_TSO5_FW_DATA_LEN;
6196 info.data_data = &tg3Tso5FwData[0];
6197 cpu_base = RX_CPU_BASE;
6198 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6199 cpu_scratch_size = (info.text_len +
6200 info.rodata_len +
6201 info.data_len +
6202 TG3_TSO5_FW_SBSS_LEN +
6203 TG3_TSO5_FW_BSS_LEN);
6204 } else {
6205 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6206 info.text_len = TG3_TSO_FW_TEXT_LEN;
6207 info.text_data = &tg3TsoFwText[0];
6208 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6209 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6210 info.rodata_data = &tg3TsoFwRodata[0];
6211 info.data_base = TG3_TSO_FW_DATA_ADDR;
6212 info.data_len = TG3_TSO_FW_DATA_LEN;
6213 info.data_data = &tg3TsoFwData[0];
6214 cpu_base = TX_CPU_BASE;
6215 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6216 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6217 }
6218
6219 err = tg3_load_firmware_cpu(tp, cpu_base,
6220 cpu_scratch_base, cpu_scratch_size,
6221 &info);
6222 if (err)
6223 return err;
6224
6225 /* Now startup the cpu. */
6226 tw32(cpu_base + CPU_STATE, 0xffffffff);
6227 tw32_f(cpu_base + CPU_PC, info.text_base);
6228
6229 for (i = 0; i < 5; i++) {
6230 if (tr32(cpu_base + CPU_PC) == info.text_base)
6231 break;
6232 tw32(cpu_base + CPU_STATE, 0xffffffff);
6233 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6234 tw32_f(cpu_base + CPU_PC, info.text_base);
6235 udelay(1000);
6236 }
6237 if (i >= 5) {
6238 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6239 "to set CPU PC, is %08x should be %08x\n",
6240 tp->dev->name, tr32(cpu_base + CPU_PC),
6241 info.text_base);
6242 return -ENODEV;
6243 }
6244 tw32(cpu_base + CPU_STATE, 0xffffffff);
6245 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6246 return 0;
6247}
6248
1da177e4
LT		 6249
6250/* tp->lock is held. */
986e0aeb 6251static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
1da177e4
LT		 6252{
6253 u32 addr_high, addr_low;
6254 int i;
6255
6256 addr_high = ((tp->dev->dev_addr[0] << 8) |
6257 tp->dev->dev_addr[1]);
6258 addr_low = ((tp->dev->dev_addr[2] << 24) |
6259 (tp->dev->dev_addr[3] << 16) |
6260 (tp->dev->dev_addr[4] << 8) |
6261 (tp->dev->dev_addr[5] << 0));
6262 for (i = 0; i < 4; i++) {
986e0aeb
MC		 6263 if (i == 1 && skip_mac_1)
6264 continue;
1da177e4
LT		 6265 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6266 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6267 }
6268
6269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6271 for (i = 0; i < 12; i++) {
6272 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6273 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6274 }
6275 }
6276
6277 addr_high = (tp->dev->dev_addr[0] +
6278 tp->dev->dev_addr[1] +
6279 tp->dev->dev_addr[2] +
6280 tp->dev->dev_addr[3] +
6281 tp->dev->dev_addr[4] +
6282 tp->dev->dev_addr[5]) &
6283 TX_BACKOFF_SEED_MASK;
6284 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6285}
6286
6287static int tg3_set_mac_addr(struct net_device *dev, void *p)
6288{
6289 struct tg3 *tp = netdev_priv(dev);
6290 struct sockaddr *addr = p;
986e0aeb 6291 int err = 0, skip_mac_1 = 0;
1da177e4 6292
f9804ddb
MC		 6293 if (!is_valid_ether_addr(addr->sa_data))
6294 return -EINVAL;
6295
1da177e4
LT		 6296 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6297
e75f7c90
MC		 6298 if (!netif_running(dev))
6299 return 0;
6300
58712ef9 6301 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6302 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6303
986e0aeb
MC		 6304 addr0_high = tr32(MAC_ADDR_0_HIGH);
6305 addr0_low = tr32(MAC_ADDR_0_LOW);
6306 addr1_high = tr32(MAC_ADDR_1_HIGH);
6307 addr1_low = tr32(MAC_ADDR_1_LOW);
6308
6309 /* Skip MAC addr 1 if ASF is using it. */
6310 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6311 !(addr1_high == 0 && addr1_low == 0))
6312 skip_mac_1 = 1;
58712ef9 6313 }
986e0aeb
MC		 6314 spin_lock_bh(&tp->lock);
6315 __tg3_set_mac_addr(tp, skip_mac_1);
6316 spin_unlock_bh(&tp->lock);
1da177e4 6317
b9ec6c1b 6318 return err;
1da177e4
LT		 6319}
6320
6321/* tp->lock is held. */
6322static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6323 dma_addr_t mapping, u32 maxlen_flags,
6324 u32 nic_addr)
6325{
6326 tg3_write_mem(tp,
6327 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6328 ((u64) mapping >> 32));
6329 tg3_write_mem(tp,
6330 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6331 ((u64) mapping & 0xffffffff));
6332 tg3_write_mem(tp,
6333 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6334 maxlen_flags);
6335
6336 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6337 tg3_write_mem(tp,
6338 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6339 nic_addr);
6340}
6341
6342static void __tg3_set_rx_mode(struct net_device *);
d244c892 6343static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6344{
6345 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6346 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6347 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6348 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6349 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6350 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6351 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6352 }
6353 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6354 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6355 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6356 u32 val = ec->stats_block_coalesce_usecs;
6357
6358 if (!netif_carrier_ok(tp->dev))
6359 val = 0;
6360
6361 tw32(HOSTCC_STAT_COAL_TICKS, val);
6362 }
6363}
1da177e4
LT		 6364
6365/* tp->lock is held. */
8e7a22e3 6366static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6367{
6368 u32 val, rdmac_mode;
6369 int i, err, limit;
6370
6371 tg3_disable_ints(tp);
6372
6373 tg3_stop_fw(tp);
6374
6375 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6376
6377 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6378 tg3_abort_hw(tp, 1);
1da177e4
LT		 6379 }
6380
36da4d86 6381 if (reset_phy)
d4d2c558
MC		 6382 tg3_phy_reset(tp);
6383
1da177e4
LT		 6384 err = tg3_chip_reset(tp);
6385 if (err)
6386 return err;
6387
6388 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6389
d30cdd28
MC		 6390 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
6391 val = tr32(TG3_CPMU_CTRL);
6392 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6393 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6394
6395 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6396 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6397 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6398 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6399
6400 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6401 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6402 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6403 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6404
6405 val = tr32(TG3_CPMU_HST_ACC);
6406 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6407 val |= CPMU_HST_ACC_MACCLK_6_25;
6408 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6409 }
6410
1da177e4
LT		 6411 /* This works around an issue with Athlon chipsets on
6412 * B3 tigon3 silicon. This bit has no effect on any
6413 * other revision. But do not set this on PCI Express
795d01c5 6414 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6415 */
795d01c5
MC		 6416 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6417 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6418 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6419 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6420 }
1da177e4
LT		 6421
6422 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6423 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6424 val = tr32(TG3PCI_PCISTATE);
6425 val |= PCISTATE_RETRY_SAME_DMA;
6426 tw32(TG3PCI_PCISTATE, val);
6427 }
6428
0d3031d9
MC		 6429 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6430 /* Allow reads and writes to the
6431 * APE register and memory space.
6432 */
6433 val = tr32(TG3PCI_PCISTATE);
6434 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6435 PCISTATE_ALLOW_APE_SHMEM_WR;
6436 tw32(TG3PCI_PCISTATE, val);
6437 }
6438
1da177e4
LT		 6439 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6440 /* Enable some hw fixes. */
6441 val = tr32(TG3PCI_MSI_DATA);
6442 val |= (1 << 26) | (1 << 28) | (1 << 29);
6443 tw32(TG3PCI_MSI_DATA, val);
6444 }
6445
6446 /* Descriptor ring init may make accesses to the
6447 * NIC SRAM area to setup the TX descriptors, so we
6448 * can only do this after the hardware has been
6449 * successfully reset.
6450 */
32d8c572
MC		 6451 err = tg3_init_rings(tp);
6452 if (err)
6453 return err;
1da177e4 6454
9936bcf6
MC		 6455 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6456 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6457 /* This value is determined during the probe time DMA
6458 * engine test, tg3_test_dma.
6459 */
6460 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6461 }
1da177e4
LT		 6462
6463 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6464 GRC_MODE_4X_NIC_SEND_RINGS |
6465 GRC_MODE_NO_TX_PHDR_CSUM |
6466 GRC_MODE_NO_RX_PHDR_CSUM);
6467 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6468
6469 /* Pseudo-header checksum is done by hardware logic and not
6470 * the offload processers, so make the chip do the pseudo-
6471 * header checksums on receive. For transmit it is more
6472 * convenient to do the pseudo-header checksum in software
6473 * as Linux does that on transmit for us in all cases.
6474 */
6475 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6476
6477 tw32(GRC_MODE,
6478 tp->grc_mode |
6479 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6480
6481 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6482 val = tr32(GRC_MISC_CFG);
6483 val &= ~0xff;
6484 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6485 tw32(GRC_MISC_CFG, val);
6486
6487 /* Initialize MBUF/DESC pool. */
cbf46853 6488 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6489 /* Do nothing. */
6490 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6491 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6492 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6493 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6494 else
6495 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6496 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6497 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6498 }
1da177e4
LT		 6499 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6500 int fw_len;
6501
6502 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6503 TG3_TSO5_FW_RODATA_LEN +
6504 TG3_TSO5_FW_DATA_LEN +
6505 TG3_TSO5_FW_SBSS_LEN +
6506 TG3_TSO5_FW_BSS_LEN);
6507 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6508 tw32(BUFMGR_MB_POOL_ADDR,
6509 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6510 tw32(BUFMGR_MB_POOL_SIZE,
6511 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6512 }
1da177e4 6513
0f893dc6 6514 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6515 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6516 tp->bufmgr_config.mbuf_read_dma_low_water);
6517 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6518 tp->bufmgr_config.mbuf_mac_rx_low_water);
6519 tw32(BUFMGR_MB_HIGH_WATER,
6520 tp->bufmgr_config.mbuf_high_water);
6521 } else {
6522 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6523 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6524 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6525 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6526 tw32(BUFMGR_MB_HIGH_WATER,
6527 tp->bufmgr_config.mbuf_high_water_jumbo);
6528 }
6529 tw32(BUFMGR_DMA_LOW_WATER,
6530 tp->bufmgr_config.dma_low_water);
6531 tw32(BUFMGR_DMA_HIGH_WATER,
6532 tp->bufmgr_config.dma_high_water);
6533
6534 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6535 for (i = 0; i < 2000; i++) {
6536 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6537 break;
6538 udelay(10);
6539 }
6540 if (i >= 2000) {
6541 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6542 tp->dev->name);
6543 return -ENODEV;
6544 }
6545
6546 /* Setup replenish threshold. */
f92905de
MC		 6547 val = tp->rx_pending / 8;
6548 if (val == 0)
6549 val = 1;
6550 else if (val > tp->rx_std_max_post)
6551 val = tp->rx_std_max_post;
b5d3772c
MC		 6552 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6553 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6554 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6555
6556 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6557 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6558 }
f92905de
MC		 6559
6560 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6561
6562 /* Initialize TG3_BDINFO's at:
6563 * RCVDBDI_STD_BD: standard eth size rx ring
6564 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6565 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6566 *
6567 * like so:
6568 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6569 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6570 * ring attribute flags
6571 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6572 *
6573 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6574 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6575 *
6576 * The size of each ring is fixed in the firmware, but the location is
6577 * configurable.
6578 */
6579 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6580 ((u64) tp->rx_std_mapping >> 32));
6581 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6582 ((u64) tp->rx_std_mapping & 0xffffffff));
6583 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6584 NIC_SRAM_RX_BUFFER_DESC);
6585
6586 /* Don't even try to program the JUMBO/MINI buffer descriptor
6587 * configs on 5705.
6588 */
6589 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6590 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6591 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6592 } else {
6593 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6594 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6595
6596 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6597 BDINFO_FLAGS_DISABLED);
6598
6599 /* Setup replenish threshold. */
6600 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6601
0f893dc6 6602 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6603 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6604 ((u64) tp->rx_jumbo_mapping >> 32));
6605 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6606 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6607 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6608 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6609 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6610 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6611 } else {
6612 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6613 BDINFO_FLAGS_DISABLED);
6614 }
6615
6616 }
6617
6618 /* There is only one send ring on 5705/5750, no need to explicitly
6619 * disable the others.
6620 */
6621 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6622 /* Clear out send RCB ring in SRAM. */
6623 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6624 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6625 BDINFO_FLAGS_DISABLED);
6626 }
6627
6628 tp->tx_prod = 0;
6629 tp->tx_cons = 0;
6630 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6631 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6632
6633 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6634 tp->tx_desc_mapping,
6635 (TG3_TX_RING_SIZE <<
6636 BDINFO_FLAGS_MAXLEN_SHIFT),
6637 NIC_SRAM_TX_BUFFER_DESC);
6638
6639 /* There is only one receive return ring on 5705/5750, no need
6640 * to explicitly disable the others.
6641 */
6642 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6643 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6644 i += TG3_BDINFO_SIZE) {
6645 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6646 BDINFO_FLAGS_DISABLED);
6647 }
6648 }
6649
6650 tp->rx_rcb_ptr = 0;
6651 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6652
6653 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6654 tp->rx_rcb_mapping,
6655 (TG3_RX_RCB_RING_SIZE(tp) <<
6656 BDINFO_FLAGS_MAXLEN_SHIFT),
6657 0);
6658
6659 tp->rx_std_ptr = tp->rx_pending;
6660 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6661 tp->rx_std_ptr);
6662
0f893dc6 6663 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6664 tp->rx_jumbo_pending : 0;
6665 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6666 tp->rx_jumbo_ptr);
6667
6668 /* Initialize MAC address and backoff seed. */
986e0aeb 6669 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6670
6671 /* MTU + ethernet header + FCS + optional VLAN tag */
6672 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6673
6674 /* The slot time is changed by tg3_setup_phy if we
6675 * run at gigabit with half duplex.
6676 */
6677 tw32(MAC_TX_LENGTHS,
6678 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6679 (6 << TX_LENGTHS_IPG_SHIFT) |
6680 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6681
6682 /* Receive rules. */
6683 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6684 tw32(RCVLPC_CONFIG, 0x0181);
6685
6686 /* Calculate RDMAC_MODE setting early, we need it to determine
6687 * the RCVLPC_STATE_ENABLE mask.
6688 */
6689 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6690 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6691 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6692 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6693 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6694
d30cdd28
MC		 6695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
6696 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6697 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6698 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6699
85e94ced
MC		 6700 /* If statement applies to 5705 and 5750 PCI devices only */
6701 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6702 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6703 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 6704 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 6705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6706 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6707 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6708 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6709 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6710 }
6711 }
6712
85e94ced
MC		 6713 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6714 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6715
1da177e4
LT		 6716 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6717 rdmac_mode |= (1 << 27);
1da177e4
LT		 6718
6719 /* Receive/send statistics. */
1661394e
MC		 6720 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6721 val = tr32(RCVLPC_STATS_ENABLE);
6722 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6723 tw32(RCVLPC_STATS_ENABLE, val);
6724 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6725 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6726 val = tr32(RCVLPC_STATS_ENABLE);
6727 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6728 tw32(RCVLPC_STATS_ENABLE, val);
6729 } else {
6730 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6731 }
6732 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6733 tw32(SNDDATAI_STATSENAB, 0xffffff);
6734 tw32(SNDDATAI_STATSCTRL,
6735 (SNDDATAI_SCTRL_ENABLE |
6736 SNDDATAI_SCTRL_FASTUPD));
6737
6738 /* Setup host coalescing engine. */
6739 tw32(HOSTCC_MODE, 0);
6740 for (i = 0; i < 2000; i++) {
6741 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6742 break;
6743 udelay(10);
6744 }
6745
d244c892 6746 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6747
6748 /* set status block DMA address */
6749 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6750 ((u64) tp->status_mapping >> 32));
6751 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6752 ((u64) tp->status_mapping & 0xffffffff));
6753
6754 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6755 /* Status/statistics block address. See tg3_timer,
6756 * the tg3_periodic_fetch_stats call there, and
6757 * tg3_get_stats to see how this works for 5705/5750 chips.
6758 */
1da177e4
LT		 6759 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6760 ((u64) tp->stats_mapping >> 32));
6761 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6762 ((u64) tp->stats_mapping & 0xffffffff));
6763 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6764 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6765 }
6766
6767 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6768
6769 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6770 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6771 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6772 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6773
6774 /* Clear statistics/status block in chip, and status block in ram. */
6775 for (i = NIC_SRAM_STATS_BLK;
6776 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6777 i += sizeof(u32)) {
6778 tg3_write_mem(tp, i, 0);
6779 udelay(40);
6780 }
6781 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6782
c94e3941
MC		 6783 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6785 /* reset to prevent losing 1st rx packet intermittently */
6786 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6787 udelay(10);
6788 }
6789
1da177e4
LT		 6790 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6791 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 6792 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6793 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6794 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6795 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 6796 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6797 udelay(40);
6798
314fba34 6799 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6800 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6801 * register to preserve the GPIO settings for LOMs. The GPIOs,
6802 * whether used as inputs or outputs, are set by boot code after
6803 * reset.
6804 */
9d26e213 6805 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6806 u32 gpio_mask;
6807
9d26e213
MC		 6808 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6809 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6810 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6811
6812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6813 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6814 GRC_LCLCTRL_GPIO_OUTPUT3;
6815
af36e6b6
MC		 6816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6817 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6818
aaf84465 6819 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 6820 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6821
6822 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6823 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6824 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6825 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6826 }
1da177e4
LT		 6827 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6828 udelay(100);
6829
09ee929c 6830 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6831 tp->last_tag = 0;
1da177e4
LT		 6832
6833 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6834 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6835 udelay(40);
6836 }
6837
6838 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6839 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6840 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6841 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6842 WDMAC_MODE_LNGREAD_ENAB);
6843
85e94ced
MC		 6844 /* If statement applies to 5705 and 5750 PCI devices only */
6845 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6846 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6848 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6849 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6850 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6851 /* nothing */
6852 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6853 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6854 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6855 val |= WDMAC_MODE_RX_ACCEL;
6856 }
6857 }
6858
d9ab5ad1 6859 /* Enable host coalescing bug fix */
af36e6b6 6860 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
d30cdd28 6861 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
9936bcf6
MC		 6862 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
6863 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
d9ab5ad1
MC		 6864 val |= (1 << 29);
6865
1da177e4
LT		 6866 tw32_f(WDMAC_MODE, val);
6867 udelay(40);
6868
9974a356
MC		 6869 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6870 u16 pcix_cmd;
6871
6872 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6873 &pcix_cmd);
1da177e4 6874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 6875 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
6876 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 6877 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 6878 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
6879 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 6880 }
9974a356
MC		 6881 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6882 pcix_cmd);
1da177e4
LT		 6883 }
6884
6885 tw32_f(RDMAC_MODE, rdmac_mode);
6886 udelay(40);
6887
6888 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6889 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6890 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 6891
6892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
6893 tw32(SNDDATAC_MODE,
6894 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
6895 else
6896 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6897
1da177e4
LT		 6898 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6899 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6900 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6901 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6902 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6903 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6904 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6905 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6906
6907 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6908 err = tg3_load_5701_a0_firmware_fix(tp);
6909 if (err)
6910 return err;
6911 }
6912
1da177e4
LT		 6913 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6914 err = tg3_load_tso_firmware(tp);
6915 if (err)
6916 return err;
6917 }
1da177e4
LT		 6918
6919 tp->tx_mode = TX_MODE_ENABLE;
6920 tw32_f(MAC_TX_MODE, tp->tx_mode);
6921 udelay(100);
6922
6923 tp->rx_mode = RX_MODE_ENABLE;
9936bcf6
MC		 6924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
6925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
af36e6b6
MC		 6926 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6927
1da177e4
LT		 6928 tw32_f(MAC_RX_MODE, tp->rx_mode);
6929 udelay(10);
6930
6931 if (tp->link_config.phy_is_low_power) {
6932 tp->link_config.phy_is_low_power = 0;
6933 tp->link_config.speed = tp->link_config.orig_speed;
6934 tp->link_config.duplex = tp->link_config.orig_duplex;
6935 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6936 }
6937
6938 tp->mi_mode = MAC_MI_MODE_BASE;
6939 tw32_f(MAC_MI_MODE, tp->mi_mode);
6940 udelay(80);
6941
6942 tw32(MAC_LED_CTRL, tp->led_ctrl);
6943
6944 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6945 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6946 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6947 udelay(10);
6948 }
6949 tw32_f(MAC_RX_MODE, tp->rx_mode);
6950 udelay(10);
6951
6952 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6953 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6954 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6955 /* Set drive transmission level to 1.2V */
6956 /* only if the signal pre-emphasis bit is not set */
6957 val = tr32(MAC_SERDES_CFG);
6958 val &= 0xfffff000;
6959 val |= 0x880;
6960 tw32(MAC_SERDES_CFG, val);
6961 }
6962 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6963 tw32(MAC_SERDES_CFG, 0x616000);
6964 }
6965
6966 /* Prevent chip from dropping frames when flow control
6967 * is enabled.
6968 */
6969 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6970
6971 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6972 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6973 /* Use hardware link auto-negotiation */
6974 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6975 }
6976
d4d2c558
MC		 6977 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6978 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6979 u32 tmp;
6980
6981 tmp = tr32(SERDES_RX_CTRL);
6982 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6983 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6984 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6985 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6986 }
6987
36da4d86 6988 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6989 if (err)
6990 return err;
6991
715116a1
MC		 6992 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6993 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6994 u32 tmp;
6995
6996 /* Clear CRC stats. */
569a5df8
MC		 6997 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6998 tg3_writephy(tp, MII_TG3_TEST1,
6999 tmp | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7000 tg3_readphy(tp, 0x14, &tmp);
7001 }
7002 }
7003
7004 __tg3_set_rx_mode(tp->dev);
7005
7006 /* Initialize receive rules. */
7007 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7008 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7009 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7010 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7011
4cf78e4f 7012 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7013 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7014 limit = 8;
7015 else
7016 limit = 16;
7017 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7018 limit -= 4;
7019 switch (limit) {
7020 case 16:
7021 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7022 case 15:
7023 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7024 case 14:
7025 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7026 case 13:
7027 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7028 case 12:
7029 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7030 case 11:
7031 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7032 case 10:
7033 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7034 case 9:
7035 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7036 case 8:
7037 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7038 case 7:
7039 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7040 case 6:
7041 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7042 case 5:
7043 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7044 case 4:
7045 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7046 case 3:
7047 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7048 case 2:
7049 case 1:
7050
7051 default:
7052 break;
7053 };
7054
9ce768ea
MC		 7055 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7056 /* Write our heartbeat update interval to APE. */
7057 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7058 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7059
1da177e4
LT		 7060 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7061
1da177e4
LT		 7062 return 0;
7063}
7064
7065/* Called at device open time to get the chip ready for
7066 * packet processing. Invoked with tp->lock held.
7067 */
8e7a22e3 7068static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7069{
7070 int err;
7071
7072 /* Force the chip into D0. */
bc1c7567 7073 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 7074 if (err)
7075 goto out;
7076
7077 tg3_switch_clocks(tp);
7078
7079 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7080
8e7a22e3 7081 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7082
7083out:
7084 return err;
7085}
7086
7087#define TG3_STAT_ADD32(PSTAT, REG) \
7088do { u32 __val = tr32(REG); \
7089 (PSTAT)->low += __val; \
7090 if ((PSTAT)->low < __val) \
7091 (PSTAT)->high += 1; \
7092} while (0)
7093
7094static void tg3_periodic_fetch_stats(struct tg3 *tp)
7095{
7096 struct tg3_hw_stats *sp = tp->hw_stats;
7097
7098 if (!netif_carrier_ok(tp->dev))
7099 return;
7100
7101 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7102 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7103 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7104 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7105 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7106 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7107 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7108 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7109 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7110 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7111 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7112 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7113 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7114
7115 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7116 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7117 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7118 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7119 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7120 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7121 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7122 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7123 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7124 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7125 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7126 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7127 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7128 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7129
7130 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7131 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7132 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7133}
7134
7135static void tg3_timer(unsigned long __opaque)
7136{
7137 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7138
f475f163
MC		 7139 if (tp->irq_sync)
7140 goto restart_timer;
7141
f47c11ee 7142 spin_lock(&tp->lock);
1da177e4 7143
fac9b83e
DM		 7144 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7145 /* All of this garbage is because when using non-tagged
7146 * IRQ status the mailbox/status_block protocol the chip
7147 * uses with the cpu is race prone.
7148 */
7149 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7150 tw32(GRC_LOCAL_CTRL,
7151 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7152 } else {
7153 tw32(HOSTCC_MODE, tp->coalesce_mode |
7154 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7155 }
1da177e4 7156
fac9b83e
DM		 7157 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7158 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7159 spin_unlock(&tp->lock);
fac9b83e
DM		 7160 schedule_work(&tp->reset_task);
7161 return;
7162 }
1da177e4
LT		 7163 }
7164
1da177e4
LT		 7165 /* This part only runs once per second. */
7166 if (!--tp->timer_counter) {
fac9b83e
DM		 7167 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7168 tg3_periodic_fetch_stats(tp);
7169
1da177e4
LT		 7170 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7171 u32 mac_stat;
7172 int phy_event;
7173
7174 mac_stat = tr32(MAC_STATUS);
7175
7176 phy_event = 0;
7177 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7178 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7179 phy_event = 1;
7180 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7181 phy_event = 1;
7182
7183 if (phy_event)
7184 tg3_setup_phy(tp, 0);
7185 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7186 u32 mac_stat = tr32(MAC_STATUS);
7187 int need_setup = 0;
7188
7189 if (netif_carrier_ok(tp->dev) &&
7190 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7191 need_setup = 1;
7192 }
7193 if (! netif_carrier_ok(tp->dev) &&
7194 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7195 MAC_STATUS_SIGNAL_DET))) {
7196 need_setup = 1;
7197 }
7198 if (need_setup) {
3d3ebe74
MC		 7199 if (!tp->serdes_counter) {
7200 tw32_f(MAC_MODE,
7201 (tp->mac_mode &
7202 ~MAC_MODE_PORT_MODE_MASK));
7203 udelay(40);
7204 tw32_f(MAC_MODE, tp->mac_mode);
7205 udelay(40);
7206 }
1da177e4
LT		 7207 tg3_setup_phy(tp, 0);
7208 }
747e8f8b
MC		 7209 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7210 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7211
7212 tp->timer_counter = tp->timer_multiplier;
7213 }
7214
130b8e4d
MC		 7215 /* Heartbeat is only sent once every 2 seconds.
7216 *
7217 * The heartbeat is to tell the ASF firmware that the host
7218 * driver is still alive. In the event that the OS crashes,
7219 * ASF needs to reset the hardware to free up the FIFO space
7220 * that may be filled with rx packets destined for the host.
7221 * If the FIFO is full, ASF will no longer function properly.
7222 *
7223 * Unintended resets have been reported on real time kernels
7224 * where the timer doesn't run on time. Netpoll will also have
7225 * same problem.
7226 *
7227 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7228 * to check the ring condition when the heartbeat is expiring
7229 * before doing the reset. This will prevent most unintended
7230 * resets.
7231 */
1da177e4
LT		 7232 if (!--tp->asf_counter) {
7233 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7234 u32 val;
7235
bbadf503 7236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7237 FWCMD_NICDRV_ALIVE3);
bbadf503 7238 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7239 /* 5 seconds timeout */
bbadf503 7240 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 7241 val = tr32(GRC_RX_CPU_EVENT);
7242 val |= (1 << 14);
7243 tw32(GRC_RX_CPU_EVENT, val);
7244 }
7245 tp->asf_counter = tp->asf_multiplier;
7246 }
7247
f47c11ee 7248 spin_unlock(&tp->lock);
1da177e4 7249
f475f163 7250restart_timer:
1da177e4
LT		 7251 tp->timer.expires = jiffies + tp->timer_offset;
7252 add_timer(&tp->timer);
7253}
7254
81789ef5 7255static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7256{
7d12e780 7257 irq_handler_t fn;
fcfa0a32
MC		 7258 unsigned long flags;
7259 struct net_device *dev = tp->dev;
7260
7261 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7262 fn = tg3_msi;
7263 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7264 fn = tg3_msi_1shot;
1fb9df5d 7265 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7266 } else {
7267 fn = tg3_interrupt;
7268 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7269 fn = tg3_interrupt_tagged;
1fb9df5d 7270 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7271 }
7272 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7273}
7274
7938109f
MC		 7275static int tg3_test_interrupt(struct tg3 *tp)
7276{
7277 struct net_device *dev = tp->dev;
b16250e3 7278 int err, i, intr_ok = 0;
7938109f 7279
d4bc3927
MC		 7280 if (!netif_running(dev))
7281 return -ENODEV;
7282
7938109f
MC		 7283 tg3_disable_ints(tp);
7284
7285 free_irq(tp->pdev->irq, dev);
7286
7287 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7288 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7289 if (err)
7290 return err;
7291
38f3843e 7292 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7293 tg3_enable_ints(tp);
7294
7295 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7296 HOSTCC_MODE_NOW);
7297
7298 for (i = 0; i < 5; i++) {
b16250e3
MC		 7299 u32 int_mbox, misc_host_ctrl;
7300
09ee929c
MC		 7301 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7302 TG3_64BIT_REG_LOW);
b16250e3
MC		 7303 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7304
7305 if ((int_mbox != 0) ||
7306 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7307 intr_ok = 1;
7938109f 7308 break;
b16250e3
MC		 7309 }
7310
7938109f
MC		 7311 msleep(10);
7312 }
7313
7314 tg3_disable_ints(tp);
7315
7316 free_irq(tp->pdev->irq, dev);
6aa20a22 7317
fcfa0a32 7318 err = tg3_request_irq(tp);
7938109f
MC		 7319
7320 if (err)
7321 return err;
7322
b16250e3 7323 if (intr_ok)
7938109f
MC		 7324 return 0;
7325
7326 return -EIO;
7327}
7328
7329/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7330 * successfully restored
7331 */
7332static int tg3_test_msi(struct tg3 *tp)
7333{
7334 struct net_device *dev = tp->dev;
7335 int err;
7336 u16 pci_cmd;
7337
7338 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7339 return 0;
7340
7341 /* Turn off SERR reporting in case MSI terminates with Master
7342 * Abort.
7343 */
7344 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7345 pci_write_config_word(tp->pdev, PCI_COMMAND,
7346 pci_cmd & ~PCI_COMMAND_SERR);
7347
7348 err = tg3_test_interrupt(tp);
7349
7350 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7351
7352 if (!err)
7353 return 0;
7354
7355 /* other failures */
7356 if (err != -EIO)
7357 return err;
7358
7359 /* MSI test failed, go back to INTx mode */
7360 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7361 "switching to INTx mode. Please report this failure to "
7362 "the PCI maintainer and include system chipset information.\n",
7363 tp->dev->name);
7364
7365 free_irq(tp->pdev->irq, dev);
7366 pci_disable_msi(tp->pdev);
7367
7368 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7369
fcfa0a32 7370 err = tg3_request_irq(tp);
7938109f
MC		 7371 if (err)
7372 return err;
7373
7374 /* Need to reset the chip because the MSI cycle may have terminated
7375 * with Master Abort.
7376 */
f47c11ee 7377 tg3_full_lock(tp, 1);
7938109f 7378
944d980e 7379 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7380 err = tg3_init_hw(tp, 1);
7938109f 7381
f47c11ee 7382 tg3_full_unlock(tp);
7938109f
MC		 7383
7384 if (err)
7385 free_irq(tp->pdev->irq, dev);
7386
7387 return err;
7388}
7389
1da177e4
LT		 7390static int tg3_open(struct net_device *dev)
7391{
7392 struct tg3 *tp = netdev_priv(dev);
7393 int err;
7394
c49a1561
MC		 7395 netif_carrier_off(tp->dev);
7396
f47c11ee 7397 tg3_full_lock(tp, 0);
1da177e4 7398
bc1c7567 7399 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 7400 if (err) {
7401 tg3_full_unlock(tp);
bc1c7567 7402 return err;
12862086 7403 }
bc1c7567 7404
1da177e4
LT		 7405 tg3_disable_ints(tp);
7406 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7407
f47c11ee 7408 tg3_full_unlock(tp);
1da177e4
LT		 7409
7410 /* The placement of this call is tied
7411 * to the setup and use of Host TX descriptors.
7412 */
7413 err = tg3_alloc_consistent(tp);
7414 if (err)
7415 return err;
7416
7544b097 7417 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7418 /* All MSI supporting chips should support tagged
7419 * status. Assert that this is the case.
7420 */
7421 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7422 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7423 "Not using MSI.\n", tp->dev->name);
7424 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7425 u32 msi_mode;
7426
7427 msi_mode = tr32(MSGINT_MODE);
7428 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7429 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7430 }
7431 }
fcfa0a32 7432 err = tg3_request_irq(tp);
1da177e4
LT		 7433
7434 if (err) {
88b06bc2
MC		 7435 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7436 pci_disable_msi(tp->pdev);
7437 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7438 }
1da177e4
LT		 7439 tg3_free_consistent(tp);
7440 return err;
7441 }
7442
bea3348e
SH		 7443 napi_enable(&tp->napi);
7444
f47c11ee 7445 tg3_full_lock(tp, 0);
1da177e4 7446
8e7a22e3 7447 err = tg3_init_hw(tp, 1);
1da177e4 7448 if (err) {
944d980e 7449 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7450 tg3_free_rings(tp);
7451 } else {
fac9b83e
DM		 7452 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7453 tp->timer_offset = HZ;
7454 else
7455 tp->timer_offset = HZ / 10;
7456
7457 BUG_ON(tp->timer_offset > HZ);
7458 tp->timer_counter = tp->timer_multiplier =
7459 (HZ / tp->timer_offset);
7460 tp->asf_counter = tp->asf_multiplier =
28fbef78 7461 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7462
7463 init_timer(&tp->timer);
7464 tp->timer.expires = jiffies + tp->timer_offset;
7465 tp->timer.data = (unsigned long) tp;
7466 tp->timer.function = tg3_timer;
1da177e4
LT		 7467 }
7468
f47c11ee 7469 tg3_full_unlock(tp);
1da177e4
LT		 7470
7471 if (err) {
bea3348e 7472 napi_disable(&tp->napi);
88b06bc2
MC		 7473 free_irq(tp->pdev->irq, dev);
7474 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7475 pci_disable_msi(tp->pdev);
7476 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7477 }
1da177e4
LT		 7478 tg3_free_consistent(tp);
7479 return err;
7480 }
7481
7938109f
MC		 7482 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7483 err = tg3_test_msi(tp);
fac9b83e 7484
7938109f 7485 if (err) {
f47c11ee 7486 tg3_full_lock(tp, 0);
7938109f
MC		 7487
7488 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7489 pci_disable_msi(tp->pdev);
7490 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7491 }
944d980e 7492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7493 tg3_free_rings(tp);
7494 tg3_free_consistent(tp);
7495
f47c11ee 7496 tg3_full_unlock(tp);
7938109f 7497
bea3348e
SH		 7498 napi_disable(&tp->napi);
7499
7938109f
MC		 7500 return err;
7501 }
fcfa0a32
MC		 7502
7503 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7504 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7505 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7506
b5d3772c
MC		 7507 tw32(PCIE_TRANSACTION_CFG,
7508 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7509 }
7510 }
7938109f
MC		 7511 }
7512
f47c11ee 7513 tg3_full_lock(tp, 0);
1da177e4 7514
7938109f
MC		 7515 add_timer(&tp->timer);
7516 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7517 tg3_enable_ints(tp);
7518
f47c11ee 7519 tg3_full_unlock(tp);
1da177e4
LT		 7520
7521 netif_start_queue(dev);
7522
7523 return 0;
7524}
7525
7526#if 0
7527/*static*/ void tg3_dump_state(struct tg3 *tp)
7528{
7529 u32 val32, val32_2, val32_3, val32_4, val32_5;
7530 u16 val16;
7531 int i;
7532
7533 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7534 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7535 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7536 val16, val32);
7537
7538 /* MAC block */
7539 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7540 tr32(MAC_MODE), tr32(MAC_STATUS));
7541 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7542 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7543 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7544 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7545 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7546 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7547
7548 /* Send data initiator control block */
7549 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7550 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7551 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7552 tr32(SNDDATAI_STATSCTRL));
7553
7554 /* Send data completion control block */
7555 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7556
7557 /* Send BD ring selector block */
7558 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7559 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7560
7561 /* Send BD initiator control block */
7562 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7563 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7564
7565 /* Send BD completion control block */
7566 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7567
7568 /* Receive list placement control block */
7569 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7570 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7571 printk(" RCVLPC_STATSCTRL[%08x]\n",
7572 tr32(RCVLPC_STATSCTRL));
7573
7574 /* Receive data and receive BD initiator control block */
7575 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7576 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7577
7578 /* Receive data completion control block */
7579 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7580 tr32(RCVDCC_MODE));
7581
7582 /* Receive BD initiator control block */
7583 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7584 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7585
7586 /* Receive BD completion control block */
7587 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7588 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7589
7590 /* Receive list selector control block */
7591 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7592 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7593
7594 /* Mbuf cluster free block */
7595 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7596 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7597
7598 /* Host coalescing control block */
7599 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7600 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7601 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7602 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7603 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7604 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7605 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7606 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7607 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7608 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7609 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7610 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7611
7612 /* Memory arbiter control block */
7613 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7614 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7615
7616 /* Buffer manager control block */
7617 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7618 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7619 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7620 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7621 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7622 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7623 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7624 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7625
7626 /* Read DMA control block */
7627 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7628 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7629
7630 /* Write DMA control block */
7631 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7632 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7633
7634 /* DMA completion block */
7635 printk("DEBUG: DMAC_MODE[%08x]\n",
7636 tr32(DMAC_MODE));
7637
7638 /* GRC block */
7639 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7640 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7641 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7642 tr32(GRC_LOCAL_CTRL));
7643
7644 /* TG3_BDINFOs */
7645 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7646 tr32(RCVDBDI_JUMBO_BD + 0x0),
7647 tr32(RCVDBDI_JUMBO_BD + 0x4),
7648 tr32(RCVDBDI_JUMBO_BD + 0x8),
7649 tr32(RCVDBDI_JUMBO_BD + 0xc));
7650 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7651 tr32(RCVDBDI_STD_BD + 0x0),
7652 tr32(RCVDBDI_STD_BD + 0x4),
7653 tr32(RCVDBDI_STD_BD + 0x8),
7654 tr32(RCVDBDI_STD_BD + 0xc));
7655 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7656 tr32(RCVDBDI_MINI_BD + 0x0),
7657 tr32(RCVDBDI_MINI_BD + 0x4),
7658 tr32(RCVDBDI_MINI_BD + 0x8),
7659 tr32(RCVDBDI_MINI_BD + 0xc));
7660
7661 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7662 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7663 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7664 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7665 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7666 val32, val32_2, val32_3, val32_4);
7667
7668 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7669 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7670 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7671 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7672 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7673 val32, val32_2, val32_3, val32_4);
7674
7675 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7676 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7677 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7678 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7679 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7680 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7681 val32, val32_2, val32_3, val32_4, val32_5);
7682
7683 /* SW status block */
7684 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7685 tp->hw_status->status,
7686 tp->hw_status->status_tag,
7687 tp->hw_status->rx_jumbo_consumer,
7688 tp->hw_status->rx_consumer,
7689 tp->hw_status->rx_mini_consumer,
7690 tp->hw_status->idx[0].rx_producer,
7691 tp->hw_status->idx[0].tx_consumer);
7692
7693 /* SW statistics block */
7694 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7695 ((u32 *)tp->hw_stats)[0],
7696 ((u32 *)tp->hw_stats)[1],
7697 ((u32 *)tp->hw_stats)[2],
7698 ((u32 *)tp->hw_stats)[3]);
7699
7700 /* Mailboxes */
7701 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7702 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7703 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7704 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7705 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7706
7707 /* NIC side send descriptors. */
7708 for (i = 0; i < 6; i++) {
7709 unsigned long txd;
7710
7711 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7712 + (i * sizeof(struct tg3_tx_buffer_desc));
7713 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7714 i,
7715 readl(txd + 0x0), readl(txd + 0x4),
7716 readl(txd + 0x8), readl(txd + 0xc));
7717 }
7718
7719 /* NIC side RX descriptors. */
7720 for (i = 0; i < 6; i++) {
7721 unsigned long rxd;
7722
7723 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7724 + (i * sizeof(struct tg3_rx_buffer_desc));
7725 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7726 i,
7727 readl(rxd + 0x0), readl(rxd + 0x4),
7728 readl(rxd + 0x8), readl(rxd + 0xc));
7729 rxd += (4 * sizeof(u32));
7730 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7731 i,
7732 readl(rxd + 0x0), readl(rxd + 0x4),
7733 readl(rxd + 0x8), readl(rxd + 0xc));
7734 }
7735
7736 for (i = 0; i < 6; i++) {
7737 unsigned long rxd;
7738
7739 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7740 + (i * sizeof(struct tg3_rx_buffer_desc));
7741 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7742 i,
7743 readl(rxd + 0x0), readl(rxd + 0x4),
7744 readl(rxd + 0x8), readl(rxd + 0xc));
7745 rxd += (4 * sizeof(u32));
7746 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7747 i,
7748 readl(rxd + 0x0), readl(rxd + 0x4),
7749 readl(rxd + 0x8), readl(rxd + 0xc));
7750 }
7751}
7752#endif
7753
7754static struct net_device_stats *tg3_get_stats(struct net_device *);
7755static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7756
7757static int tg3_close(struct net_device *dev)
7758{
7759 struct tg3 *tp = netdev_priv(dev);
7760
bea3348e 7761 napi_disable(&tp->napi);
28e53bdd 7762 cancel_work_sync(&tp->reset_task);
7faa006f 7763
1da177e4
LT		 7764 netif_stop_queue(dev);
7765
7766 del_timer_sync(&tp->timer);
7767
f47c11ee 7768 tg3_full_lock(tp, 1);
1da177e4
LT		 7769#if 0
7770 tg3_dump_state(tp);
7771#endif
7772
7773 tg3_disable_ints(tp);
7774
944d980e 7775 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 7776 tg3_free_rings(tp);
5cf64b8a 7777 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 7778
f47c11ee 7779 tg3_full_unlock(tp);
1da177e4 7780
88b06bc2
MC		 7781 free_irq(tp->pdev->irq, dev);
7782 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7783 pci_disable_msi(tp->pdev);
7784 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7785 }
1da177e4
LT		 7786
7787 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7788 sizeof(tp->net_stats_prev));
7789 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7790 sizeof(tp->estats_prev));
7791
7792 tg3_free_consistent(tp);
7793
bc1c7567
MC		 7794 tg3_set_power_state(tp, PCI_D3hot);
7795
7796 netif_carrier_off(tp->dev);
7797
1da177e4
LT		 7798 return 0;
7799}
7800
7801static inline unsigned long get_stat64(tg3_stat64_t *val)
7802{
7803 unsigned long ret;
7804
7805#if (BITS_PER_LONG == 32)
7806 ret = val->low;
7807#else
7808 ret = ((u64)val->high << 32) | ((u64)val->low);
7809#endif
7810 return ret;
7811}
7812
7813static unsigned long calc_crc_errors(struct tg3 *tp)
7814{
7815 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7816
7817 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7818 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7819 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7820 u32 val;
7821
f47c11ee 7822 spin_lock_bh(&tp->lock);
569a5df8
MC		 7823 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7824 tg3_writephy(tp, MII_TG3_TEST1,
7825 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7826 tg3_readphy(tp, 0x14, &val);
7827 } else
7828 val = 0;
f47c11ee 7829 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7830
7831 tp->phy_crc_errors += val;
7832
7833 return tp->phy_crc_errors;
7834 }
7835
7836 return get_stat64(&hw_stats->rx_fcs_errors);
7837}
7838
7839#define ESTAT_ADD(member) \
7840 estats->member = old_estats->member + \
7841 get_stat64(&hw_stats->member)
7842
7843static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7844{
7845 struct tg3_ethtool_stats *estats = &tp->estats;
7846 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7847 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7848
7849 if (!hw_stats)
7850 return old_estats;
7851
7852 ESTAT_ADD(rx_octets);
7853 ESTAT_ADD(rx_fragments);
7854 ESTAT_ADD(rx_ucast_packets);
7855 ESTAT_ADD(rx_mcast_packets);
7856 ESTAT_ADD(rx_bcast_packets);
7857 ESTAT_ADD(rx_fcs_errors);
7858 ESTAT_ADD(rx_align_errors);
7859 ESTAT_ADD(rx_xon_pause_rcvd);
7860 ESTAT_ADD(rx_xoff_pause_rcvd);
7861 ESTAT_ADD(rx_mac_ctrl_rcvd);
7862 ESTAT_ADD(rx_xoff_entered);
7863 ESTAT_ADD(rx_frame_too_long_errors);
7864 ESTAT_ADD(rx_jabbers);
7865 ESTAT_ADD(rx_undersize_packets);
7866 ESTAT_ADD(rx_in_length_errors);
7867 ESTAT_ADD(rx_out_length_errors);
7868 ESTAT_ADD(rx_64_or_less_octet_packets);
7869 ESTAT_ADD(rx_65_to_127_octet_packets);
7870 ESTAT_ADD(rx_128_to_255_octet_packets);
7871 ESTAT_ADD(rx_256_to_511_octet_packets);
7872 ESTAT_ADD(rx_512_to_1023_octet_packets);
7873 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7874 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7875 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7876 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7877 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7878
7879 ESTAT_ADD(tx_octets);
7880 ESTAT_ADD(tx_collisions);
7881 ESTAT_ADD(tx_xon_sent);
7882 ESTAT_ADD(tx_xoff_sent);
7883 ESTAT_ADD(tx_flow_control);
7884 ESTAT_ADD(tx_mac_errors);
7885 ESTAT_ADD(tx_single_collisions);
7886 ESTAT_ADD(tx_mult_collisions);
7887 ESTAT_ADD(tx_deferred);
7888 ESTAT_ADD(tx_excessive_collisions);
7889 ESTAT_ADD(tx_late_collisions);
7890 ESTAT_ADD(tx_collide_2times);
7891 ESTAT_ADD(tx_collide_3times);
7892 ESTAT_ADD(tx_collide_4times);
7893 ESTAT_ADD(tx_collide_5times);
7894 ESTAT_ADD(tx_collide_6times);
7895 ESTAT_ADD(tx_collide_7times);
7896 ESTAT_ADD(tx_collide_8times);
7897 ESTAT_ADD(tx_collide_9times);
7898 ESTAT_ADD(tx_collide_10times);
7899 ESTAT_ADD(tx_collide_11times);
7900 ESTAT_ADD(tx_collide_12times);
7901 ESTAT_ADD(tx_collide_13times);
7902 ESTAT_ADD(tx_collide_14times);
7903 ESTAT_ADD(tx_collide_15times);
7904 ESTAT_ADD(tx_ucast_packets);
7905 ESTAT_ADD(tx_mcast_packets);
7906 ESTAT_ADD(tx_bcast_packets);
7907 ESTAT_ADD(tx_carrier_sense_errors);
7908 ESTAT_ADD(tx_discards);
7909 ESTAT_ADD(tx_errors);
7910
7911 ESTAT_ADD(dma_writeq_full);
7912 ESTAT_ADD(dma_write_prioq_full);
7913 ESTAT_ADD(rxbds_empty);
7914 ESTAT_ADD(rx_discards);
7915 ESTAT_ADD(rx_errors);
7916 ESTAT_ADD(rx_threshold_hit);
7917
7918 ESTAT_ADD(dma_readq_full);
7919 ESTAT_ADD(dma_read_prioq_full);
7920 ESTAT_ADD(tx_comp_queue_full);
7921
7922 ESTAT_ADD(ring_set_send_prod_index);
7923 ESTAT_ADD(ring_status_update);
7924 ESTAT_ADD(nic_irqs);
7925 ESTAT_ADD(nic_avoided_irqs);
7926 ESTAT_ADD(nic_tx_threshold_hit);
7927
7928 return estats;
7929}
7930
7931static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7932{
7933 struct tg3 *tp = netdev_priv(dev);
7934 struct net_device_stats *stats = &tp->net_stats;
7935 struct net_device_stats *old_stats = &tp->net_stats_prev;
7936 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7937
7938 if (!hw_stats)
7939 return old_stats;
7940
7941 stats->rx_packets = old_stats->rx_packets +
7942 get_stat64(&hw_stats->rx_ucast_packets) +
7943 get_stat64(&hw_stats->rx_mcast_packets) +
7944 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7945
1da177e4
LT		 7946 stats->tx_packets = old_stats->tx_packets +
7947 get_stat64(&hw_stats->tx_ucast_packets) +
7948 get_stat64(&hw_stats->tx_mcast_packets) +
7949 get_stat64(&hw_stats->tx_bcast_packets);
7950
7951 stats->rx_bytes = old_stats->rx_bytes +
7952 get_stat64(&hw_stats->rx_octets);
7953 stats->tx_bytes = old_stats->tx_bytes +
7954 get_stat64(&hw_stats->tx_octets);
7955
7956 stats->rx_errors = old_stats->rx_errors +
4f63b877 7957 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7958 stats->tx_errors = old_stats->tx_errors +
7959 get_stat64(&hw_stats->tx_errors) +
7960 get_stat64(&hw_stats->tx_mac_errors) +
7961 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7962 get_stat64(&hw_stats->tx_discards);
7963
7964 stats->multicast = old_stats->multicast +
7965 get_stat64(&hw_stats->rx_mcast_packets);
7966 stats->collisions = old_stats->collisions +
7967 get_stat64(&hw_stats->tx_collisions);
7968
7969 stats->rx_length_errors = old_stats->rx_length_errors +
7970 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7971 get_stat64(&hw_stats->rx_undersize_packets);
7972
7973 stats->rx_over_errors = old_stats->rx_over_errors +
7974 get_stat64(&hw_stats->rxbds_empty);
7975 stats->rx_frame_errors = old_stats->rx_frame_errors +
7976 get_stat64(&hw_stats->rx_align_errors);
7977 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7978 get_stat64(&hw_stats->tx_discards);
7979 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7980 get_stat64(&hw_stats->tx_carrier_sense_errors);
7981
7982 stats->rx_crc_errors = old_stats->rx_crc_errors +
7983 calc_crc_errors(tp);
7984
4f63b877
JL		 7985 stats->rx_missed_errors = old_stats->rx_missed_errors +
7986 get_stat64(&hw_stats->rx_discards);
7987
1da177e4
LT		 7988 return stats;
7989}
7990
7991static inline u32 calc_crc(unsigned char *buf, int len)
7992{
7993 u32 reg;
7994 u32 tmp;
7995 int j, k;
7996
7997 reg = 0xffffffff;
7998
7999 for (j = 0; j < len; j++) {
8000 reg ^= buf[j];
8001
8002 for (k = 0; k < 8; k++) {
8003 tmp = reg & 0x01;
8004
8005 reg >>= 1;
8006
8007 if (tmp) {
8008 reg ^= 0xedb88320;
8009 }
8010 }
8011 }
8012
8013 return ~reg;
8014}
8015
8016static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8017{
8018 /* accept or reject all multicast frames */
8019 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8020 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8021 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8022 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8023}
8024
8025static void __tg3_set_rx_mode(struct net_device *dev)
8026{
8027 struct tg3 *tp = netdev_priv(dev);
8028 u32 rx_mode;
8029
8030 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8031 RX_MODE_KEEP_VLAN_TAG);
8032
8033 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8034 * flag clear.
8035 */
8036#if TG3_VLAN_TAG_USED
8037 if (!tp->vlgrp &&
8038 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8039 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8040#else
8041 /* By definition, VLAN is disabled always in this
8042 * case.
8043 */
8044 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8045 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8046#endif
8047
8048 if (dev->flags & IFF_PROMISC) {
8049 /* Promiscuous mode. */
8050 rx_mode |= RX_MODE_PROMISC;
8051 } else if (dev->flags & IFF_ALLMULTI) {
8052 /* Accept all multicast. */
8053 tg3_set_multi (tp, 1);
8054 } else if (dev->mc_count < 1) {
8055 /* Reject all multicast. */
8056 tg3_set_multi (tp, 0);
8057 } else {
8058 /* Accept one or more multicast(s). */
8059 struct dev_mc_list *mclist;
8060 unsigned int i;
8061 u32 mc_filter[4] = { 0, };
8062 u32 regidx;
8063 u32 bit;
8064 u32 crc;
8065
8066 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8067 i++, mclist = mclist->next) {
8068
8069 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8070 bit = ~crc & 0x7f;
8071 regidx = (bit & 0x60) >> 5;
8072 bit &= 0x1f;
8073 mc_filter[regidx] |= (1 << bit);
8074 }
8075
8076 tw32(MAC_HASH_REG_0, mc_filter[0]);
8077 tw32(MAC_HASH_REG_1, mc_filter[1]);
8078 tw32(MAC_HASH_REG_2, mc_filter[2]);
8079 tw32(MAC_HASH_REG_3, mc_filter[3]);
8080 }
8081
8082 if (rx_mode != tp->rx_mode) {
8083 tp->rx_mode = rx_mode;
8084 tw32_f(MAC_RX_MODE, rx_mode);
8085 udelay(10);
8086 }
8087}
8088
8089static void tg3_set_rx_mode(struct net_device *dev)
8090{
8091 struct tg3 *tp = netdev_priv(dev);
8092
e75f7c90
MC		 8093 if (!netif_running(dev))
8094 return;
8095
f47c11ee 8096 tg3_full_lock(tp, 0);
1da177e4 8097 __tg3_set_rx_mode(dev);
f47c11ee 8098 tg3_full_unlock(tp);
1da177e4
LT		 8099}
8100
8101#define TG3_REGDUMP_LEN (32 * 1024)
8102
8103static int tg3_get_regs_len(struct net_device *dev)
8104{
8105 return TG3_REGDUMP_LEN;
8106}
8107
8108static void tg3_get_regs(struct net_device *dev,
8109 struct ethtool_regs *regs, void *_p)
8110{
8111 u32 *p = _p;
8112 struct tg3 *tp = netdev_priv(dev);
8113 u8 *orig_p = _p;
8114 int i;
8115
8116 regs->version = 0;
8117
8118 memset(p, 0, TG3_REGDUMP_LEN);
8119
bc1c7567
MC		 8120 if (tp->link_config.phy_is_low_power)
8121 return;
8122
f47c11ee 8123 tg3_full_lock(tp, 0);
1da177e4
LT		 8124
8125#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8126#define GET_REG32_LOOP(base,len) \
8127do { p = (u32 *)(orig_p + (base)); \
8128 for (i = 0; i < len; i += 4) \
8129 __GET_REG32((base) + i); \
8130} while (0)
8131#define GET_REG32_1(reg) \
8132do { p = (u32 *)(orig_p + (reg)); \
8133 __GET_REG32((reg)); \
8134} while (0)
8135
8136 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8137 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8138 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8139 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8140 GET_REG32_1(SNDDATAC_MODE);
8141 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8142 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8143 GET_REG32_1(SNDBDC_MODE);
8144 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8145 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8146 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8147 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8148 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8149 GET_REG32_1(RCVDCC_MODE);
8150 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8151 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8152 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8153 GET_REG32_1(MBFREE_MODE);
8154 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8155 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8156 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8157 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8158 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8159 GET_REG32_1(RX_CPU_MODE);
8160 GET_REG32_1(RX_CPU_STATE);
8161 GET_REG32_1(RX_CPU_PGMCTR);
8162 GET_REG32_1(RX_CPU_HWBKPT);
8163 GET_REG32_1(TX_CPU_MODE);
8164 GET_REG32_1(TX_CPU_STATE);
8165 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8166 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8167 GET_REG32_LOOP(FTQ_RESET, 0x120);
8168 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8169 GET_REG32_1(DMAC_MODE);
8170 GET_REG32_LOOP(GRC_MODE, 0x4c);
8171 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8172 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8173
8174#undef __GET_REG32
8175#undef GET_REG32_LOOP
8176#undef GET_REG32_1
8177
f47c11ee 8178 tg3_full_unlock(tp);
1da177e4
LT		 8179}
8180
8181static int tg3_get_eeprom_len(struct net_device *dev)
8182{
8183 struct tg3 *tp = netdev_priv(dev);
8184
8185 return tp->nvram_size;
8186}
8187
8188static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 8189static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 8190
8191static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8192{
8193 struct tg3 *tp = netdev_priv(dev);
8194 int ret;
8195 u8 *pd;
8196 u32 i, offset, len, val, b_offset, b_count;
8197
bc1c7567
MC		 8198 if (tp->link_config.phy_is_low_power)
8199 return -EAGAIN;
8200
1da177e4
LT		 8201 offset = eeprom->offset;
8202 len = eeprom->len;
8203 eeprom->len = 0;
8204
8205 eeprom->magic = TG3_EEPROM_MAGIC;
8206
8207 if (offset & 3) {
8208 /* adjustments to start on required 4 byte boundary */
8209 b_offset = offset & 3;
8210 b_count = 4 - b_offset;
8211 if (b_count > len) {
8212 /* i.e. offset=1 len=2 */
8213 b_count = len;
8214 }
8215 ret = tg3_nvram_read(tp, offset-b_offset, &val);
8216 if (ret)
8217 return ret;
8218 val = cpu_to_le32(val);
8219 memcpy(data, ((char*)&val) + b_offset, b_count);
8220 len -= b_count;
8221 offset += b_count;
8222 eeprom->len += b_count;
8223 }
8224
8225 /* read bytes upto the last 4 byte boundary */
8226 pd = &data[eeprom->len];
8227 for (i = 0; i < (len - (len & 3)); i += 4) {
8228 ret = tg3_nvram_read(tp, offset + i, &val);
8229 if (ret) {
8230 eeprom->len += i;
8231 return ret;
8232 }
8233 val = cpu_to_le32(val);
8234 memcpy(pd + i, &val, 4);
8235 }
8236 eeprom->len += i;
8237
8238 if (len & 3) {
8239 /* read last bytes not ending on 4 byte boundary */
8240 pd = &data[eeprom->len];
8241 b_count = len & 3;
8242 b_offset = offset + len - b_count;
8243 ret = tg3_nvram_read(tp, b_offset, &val);
8244 if (ret)
8245 return ret;
8246 val = cpu_to_le32(val);
8247 memcpy(pd, ((char*)&val), b_count);
8248 eeprom->len += b_count;
8249 }
8250 return 0;
8251}
8252
6aa20a22 8253static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8254
8255static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8256{
8257 struct tg3 *tp = netdev_priv(dev);
8258 int ret;
8259 u32 offset, len, b_offset, odd_len, start, end;
8260 u8 *buf;
8261
bc1c7567
MC		 8262 if (tp->link_config.phy_is_low_power)
8263 return -EAGAIN;
8264
1da177e4
LT		 8265 if (eeprom->magic != TG3_EEPROM_MAGIC)
8266 return -EINVAL;
8267
8268 offset = eeprom->offset;
8269 len = eeprom->len;
8270
8271 if ((b_offset = (offset & 3))) {
8272 /* adjustments to start on required 4 byte boundary */
8273 ret = tg3_nvram_read(tp, offset-b_offset, &start);
8274 if (ret)
8275 return ret;
8276 start = cpu_to_le32(start);
8277 len += b_offset;
8278 offset &= ~3;
1c8594b4
MC		 8279 if (len < 4)
8280 len = 4;
1da177e4
LT		 8281 }
8282
8283 odd_len = 0;
1c8594b4 8284 if (len & 3) {
1da177e4
LT		 8285 /* adjustments to end on required 4 byte boundary */
8286 odd_len = 1;
8287 len = (len + 3) & ~3;
8288 ret = tg3_nvram_read(tp, offset+len-4, &end);
8289 if (ret)
8290 return ret;
8291 end = cpu_to_le32(end);
8292 }
8293
8294 buf = data;
8295 if (b_offset || odd_len) {
8296 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8297 if (!buf)
1da177e4
LT		 8298 return -ENOMEM;
8299 if (b_offset)
8300 memcpy(buf, &start, 4);
8301 if (odd_len)
8302 memcpy(buf+len-4, &end, 4);
8303 memcpy(buf + b_offset, data, eeprom->len);
8304 }
8305
8306 ret = tg3_nvram_write_block(tp, offset, len, buf);
8307
8308 if (buf != data)
8309 kfree(buf);
8310
8311 return ret;
8312}
8313
8314static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8315{
8316 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8317
1da177e4
LT		 8318 cmd->supported = (SUPPORTED_Autoneg);
8319
8320 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8321 cmd->supported |= (SUPPORTED_1000baseT_Half |
8322 SUPPORTED_1000baseT_Full);
8323
ef348144 8324 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8325 cmd->supported |= (SUPPORTED_100baseT_Half |
8326 SUPPORTED_100baseT_Full |
8327 SUPPORTED_10baseT_Half |
8328 SUPPORTED_10baseT_Full |
8329 SUPPORTED_MII);
ef348144
KK		 8330 cmd->port = PORT_TP;
8331 } else {
1da177e4 8332 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8333 cmd->port = PORT_FIBRE;
8334 }
6aa20a22 8335
1da177e4
LT		 8336 cmd->advertising = tp->link_config.advertising;
8337 if (netif_running(dev)) {
8338 cmd->speed = tp->link_config.active_speed;
8339 cmd->duplex = tp->link_config.active_duplex;
8340 }
1da177e4
LT		 8341 cmd->phy_address = PHY_ADDR;
8342 cmd->transceiver = 0;
8343 cmd->autoneg = tp->link_config.autoneg;
8344 cmd->maxtxpkt = 0;
8345 cmd->maxrxpkt = 0;
8346 return 0;
8347}
6aa20a22 8348
1da177e4
LT		 8349static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8350{
8351 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 8352
8353 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 8354 /* These are the only valid advertisement bits allowed. */
8355 if (cmd->autoneg == AUTONEG_ENABLE &&
8356 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8357 ADVERTISED_1000baseT_Full |
8358 ADVERTISED_Autoneg |
8359 ADVERTISED_FIBRE)))
8360 return -EINVAL;
37ff238d
MC		 8361 /* Fiber can only do SPEED_1000. */
8362 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8363 (cmd->speed != SPEED_1000))
8364 return -EINVAL;
8365 /* Copper cannot force SPEED_1000. */
8366 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8367 (cmd->speed == SPEED_1000))
8368 return -EINVAL;
8369 else if ((cmd->speed == SPEED_1000) &&
8370 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8371 return -EINVAL;
1da177e4 8372
f47c11ee 8373 tg3_full_lock(tp, 0);
1da177e4
LT		 8374
8375 tp->link_config.autoneg = cmd->autoneg;
8376 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8377 tp->link_config.advertising = (cmd->advertising |
8378 ADVERTISED_Autoneg);
1da177e4
LT		 8379 tp->link_config.speed = SPEED_INVALID;
8380 tp->link_config.duplex = DUPLEX_INVALID;
8381 } else {
8382 tp->link_config.advertising = 0;
8383 tp->link_config.speed = cmd->speed;
8384 tp->link_config.duplex = cmd->duplex;
8385 }
6aa20a22 8386
24fcad6b
MC		 8387 tp->link_config.orig_speed = tp->link_config.speed;
8388 tp->link_config.orig_duplex = tp->link_config.duplex;
8389 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8390
1da177e4
LT		 8391 if (netif_running(dev))
8392 tg3_setup_phy(tp, 1);
8393
f47c11ee 8394 tg3_full_unlock(tp);
6aa20a22 8395
1da177e4
LT		 8396 return 0;
8397}
6aa20a22 8398
1da177e4
LT		 8399static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8400{
8401 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8402
1da177e4
LT		 8403 strcpy(info->driver, DRV_MODULE_NAME);
8404 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8405 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8406 strcpy(info->bus_info, pci_name(tp->pdev));
8407}
6aa20a22 8408
1da177e4
LT		 8409static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8410{
8411 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8412
a85feb8c
GZ		 8413 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8414 wol->supported = WAKE_MAGIC;
8415 else
8416 wol->supported = 0;
1da177e4
LT		 8417 wol->wolopts = 0;
8418 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8419 wol->wolopts = WAKE_MAGIC;
8420 memset(&wol->sopass, 0, sizeof(wol->sopass));
8421}
6aa20a22 8422
1da177e4
LT		 8423static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8424{
8425 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8426
1da177e4
LT		 8427 if (wol->wolopts & ~WAKE_MAGIC)
8428 return -EINVAL;
8429 if ((wol->wolopts & WAKE_MAGIC) &&
a85feb8c 8430 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
1da177e4 8431 return -EINVAL;
6aa20a22 8432
f47c11ee 8433 spin_lock_bh(&tp->lock);
1da177e4
LT		 8434 if (wol->wolopts & WAKE_MAGIC)
8435 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8436 else
8437 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8438 spin_unlock_bh(&tp->lock);
6aa20a22 8439
1da177e4
LT		 8440 return 0;
8441}
6aa20a22 8442
1da177e4
LT		 8443static u32 tg3_get_msglevel(struct net_device *dev)
8444{
8445 struct tg3 *tp = netdev_priv(dev);
8446 return tp->msg_enable;
8447}
6aa20a22 8448
1da177e4
LT		 8449static void tg3_set_msglevel(struct net_device *dev, u32 value)
8450{
8451 struct tg3 *tp = netdev_priv(dev);
8452 tp->msg_enable = value;
8453}
6aa20a22 8454
1da177e4
LT		 8455static int tg3_set_tso(struct net_device *dev, u32 value)
8456{
8457 struct tg3 *tp = netdev_priv(dev);
8458
8459 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8460 if (value)
8461 return -EINVAL;
8462 return 0;
8463 }
b5d3772c
MC		 8464 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8465 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9936bcf6 8466 if (value) {
b0026624 8467 dev->features |= NETIF_F_TSO6;
9936bcf6
MC		 8468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8469 dev->features |= NETIF_F_TSO_ECN;
8470 } else
8471 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8472 }
1da177e4
LT		 8473 return ethtool_op_set_tso(dev, value);
8474}
6aa20a22 8475
1da177e4
LT		 8476static int tg3_nway_reset(struct net_device *dev)
8477{
8478 struct tg3 *tp = netdev_priv(dev);
8479 u32 bmcr;
8480 int r;
6aa20a22 8481
1da177e4
LT		 8482 if (!netif_running(dev))
8483 return -EAGAIN;
8484
c94e3941
MC		 8485 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8486 return -EINVAL;
8487
f47c11ee 8488 spin_lock_bh(&tp->lock);
1da177e4
LT		 8489 r = -EINVAL;
8490 tg3_readphy(tp, MII_BMCR, &bmcr);
8491 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8492 ((bmcr & BMCR_ANENABLE) ||
8493 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8494 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8495 BMCR_ANENABLE);
1da177e4
LT		 8496 r = 0;
8497 }
f47c11ee 8498 spin_unlock_bh(&tp->lock);
6aa20a22 8499
1da177e4
LT		 8500 return r;
8501}
6aa20a22 8502
1da177e4
LT		 8503static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8504{
8505 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8506
1da177e4
LT		 8507 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8508 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8509 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8510 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8511 else
8512 ering->rx_jumbo_max_pending = 0;
8513
8514 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8515
8516 ering->rx_pending = tp->rx_pending;
8517 ering->rx_mini_pending = 0;
4f81c32b
MC		 8518 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8519 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8520 else
8521 ering->rx_jumbo_pending = 0;
8522
1da177e4
LT		 8523 ering->tx_pending = tp->tx_pending;
8524}
6aa20a22 8525
1da177e4
LT		 8526static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8527{
8528 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8529 int irq_sync = 0, err = 0;
6aa20a22 8530
1da177e4
LT		 8531 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8532 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8533 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8534 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8535 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8536 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8537 return -EINVAL;
6aa20a22 8538
bbe832c0 8539 if (netif_running(dev)) {
1da177e4 8540 tg3_netif_stop(tp);
bbe832c0
MC		 8541 irq_sync = 1;
8542 }
1da177e4 8543
bbe832c0 8544 tg3_full_lock(tp, irq_sync);
6aa20a22 8545
1da177e4
LT		 8546 tp->rx_pending = ering->rx_pending;
8547
8548 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8549 tp->rx_pending > 63)
8550 tp->rx_pending = 63;
8551 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8552 tp->tx_pending = ering->tx_pending;
8553
8554 if (netif_running(dev)) {
944d980e 8555 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8556 err = tg3_restart_hw(tp, 1);
8557 if (!err)
8558 tg3_netif_start(tp);
1da177e4
LT		 8559 }
8560
f47c11ee 8561 tg3_full_unlock(tp);
6aa20a22 8562
b9ec6c1b 8563 return err;
1da177e4 8564}
6aa20a22 8565
1da177e4
LT		 8566static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8567{
8568 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8569
1da177e4
LT		 8570 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8571 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8572 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8573}
6aa20a22 8574
1da177e4
LT		 8575static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8576{
8577 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8578 int irq_sync = 0, err = 0;
6aa20a22 8579
bbe832c0 8580 if (netif_running(dev)) {
1da177e4 8581 tg3_netif_stop(tp);
bbe832c0
MC		 8582 irq_sync = 1;
8583 }
1da177e4 8584
bbe832c0 8585 tg3_full_lock(tp, irq_sync);
f47c11ee 8586
1da177e4
LT		 8587 if (epause->autoneg)
8588 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8589 else
8590 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8591 if (epause->rx_pause)
8592 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8593 else
8594 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8595 if (epause->tx_pause)
8596 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8597 else
8598 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8599
8600 if (netif_running(dev)) {
944d980e 8601 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8602 err = tg3_restart_hw(tp, 1);
8603 if (!err)
8604 tg3_netif_start(tp);
1da177e4 8605 }
f47c11ee
DM		 8606
8607 tg3_full_unlock(tp);
6aa20a22 8608
b9ec6c1b 8609 return err;
1da177e4 8610}
6aa20a22 8611
1da177e4
LT		 8612static u32 tg3_get_rx_csum(struct net_device *dev)
8613{
8614 struct tg3 *tp = netdev_priv(dev);
8615 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8616}
6aa20a22 8617
1da177e4
LT		 8618static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8619{
8620 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8621
1da177e4
LT		 8622 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8623 if (data != 0)
8624 return -EINVAL;
8625 return 0;
8626 }
6aa20a22 8627
f47c11ee 8628 spin_lock_bh(&tp->lock);
1da177e4
LT		 8629 if (data)
8630 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8631 else
8632 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8633 spin_unlock_bh(&tp->lock);
6aa20a22 8634
1da177e4
LT		 8635 return 0;
8636}
6aa20a22 8637
1da177e4
LT		 8638static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8639{
8640 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8641
1da177e4
LT		 8642 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8643 if (data != 0)
8644 return -EINVAL;
8645 return 0;
8646 }
6aa20a22 8647
af36e6b6 8648 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 8649 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 8650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
6460d948 8652 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 8653 else
9c27dbdf 8654 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8655
8656 return 0;
8657}
8658
b9f2c044 8659static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 8660{
b9f2c044
JG		 8661 switch (sset) {
8662 case ETH_SS_TEST:
8663 return TG3_NUM_TEST;
8664 case ETH_SS_STATS:
8665 return TG3_NUM_STATS;
8666 default:
8667 return -EOPNOTSUPP;
8668 }
4cafd3f5
MC		 8669}
8670
1da177e4
LT		 8671static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8672{
8673 switch (stringset) {
8674 case ETH_SS_STATS:
8675 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8676 break;
4cafd3f5
MC		 8677 case ETH_SS_TEST:
8678 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8679 break;
1da177e4
LT		 8680 default:
8681 WARN_ON(1); /* we need a WARN() */
8682 break;
8683 }
8684}
8685
4009a93d
MC		 8686static int tg3_phys_id(struct net_device *dev, u32 data)
8687{
8688 struct tg3 *tp = netdev_priv(dev);
8689 int i;
8690
8691 if (!netif_running(tp->dev))
8692 return -EAGAIN;
8693
8694 if (data == 0)
8695 data = 2;
8696
8697 for (i = 0; i < (data * 2); i++) {
8698 if ((i % 2) == 0)
8699 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8700 LED_CTRL_1000MBPS_ON |
8701 LED_CTRL_100MBPS_ON |
8702 LED_CTRL_10MBPS_ON |
8703 LED_CTRL_TRAFFIC_OVERRIDE |
8704 LED_CTRL_TRAFFIC_BLINK |
8705 LED_CTRL_TRAFFIC_LED);
6aa20a22 8706
4009a93d
MC		 8707 else
8708 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8709 LED_CTRL_TRAFFIC_OVERRIDE);
8710
8711 if (msleep_interruptible(500))
8712 break;
8713 }
8714 tw32(MAC_LED_CTRL, tp->led_ctrl);
8715 return 0;
8716}
8717
1da177e4
LT		 8718static void tg3_get_ethtool_stats (struct net_device *dev,
8719 struct ethtool_stats *estats, u64 *tmp_stats)
8720{
8721 struct tg3 *tp = netdev_priv(dev);
8722 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8723}
8724
566f86ad 8725#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 8726#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
8727#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
8728#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 8729#define NVRAM_SELFBOOT_HW_SIZE 0x20
8730#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8731
8732static int tg3_test_nvram(struct tg3 *tp)
8733{
1b27777a 8734 u32 *buf, csum, magic;
ab0049b4 8735 int i, j, k, err = 0, size;
566f86ad 8736
1820180b 8737 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8738 return -EIO;
8739
1b27777a
MC		 8740 if (magic == TG3_EEPROM_MAGIC)
8741 size = NVRAM_TEST_SIZE;
b16250e3 8742 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 8743 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
8744 TG3_EEPROM_SB_FORMAT_1) {
8745 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
8746 case TG3_EEPROM_SB_REVISION_0:
8747 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
8748 break;
8749 case TG3_EEPROM_SB_REVISION_2:
8750 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
8751 break;
8752 case TG3_EEPROM_SB_REVISION_3:
8753 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
8754 break;
8755 default:
8756 return 0;
8757 }
8758 } else
1b27777a 8759 return 0;
b16250e3
MC		 8760 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8761 size = NVRAM_SELFBOOT_HW_SIZE;
8762 else
1b27777a
MC		 8763 return -EIO;
8764
8765 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8766 if (buf == NULL)
8767 return -ENOMEM;
8768
1b27777a
MC		 8769 err = -EIO;
8770 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8771 u32 val;
8772
8773 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8774 break;
8775 buf[j] = cpu_to_le32(val);
8776 }
1b27777a 8777 if (i < size)
566f86ad
MC		 8778 goto out;
8779
1b27777a 8780 /* Selfboot format */
b16250e3
MC		 8781 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8782 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8783 u8 *buf8 = (u8 *) buf, csum8 = 0;
8784
a5767dec
MC		 8785 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_SB_REVISION_MASK) ==
8786 TG3_EEPROM_SB_REVISION_2) {
8787 /* For rev 2, the csum doesn't include the MBA. */
8788 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
8789 csum8 += buf8[i];
8790 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
8791 csum8 += buf8[i];
8792 } else {
8793 for (i = 0; i < size; i++)
8794 csum8 += buf8[i];
8795 }
1b27777a 8796
ad96b485
AB		 8797 if (csum8 == 0) {
8798 err = 0;
8799 goto out;
8800 }
8801
8802 err = -EIO;
8803 goto out;
1b27777a 8804 }
566f86ad 8805
b16250e3
MC		 8806 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8807 TG3_EEPROM_MAGIC_HW) {
8808 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8809 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8810 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 8811
8812 /* Separate the parity bits and the data bytes. */
8813 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8814 if ((i == 0) || (i == 8)) {
8815 int l;
8816 u8 msk;
8817
8818 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8819 parity[k++] = buf8[i] & msk;
8820 i++;
8821 }
8822 else if (i == 16) {
8823 int l;
8824 u8 msk;
8825
8826 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8827 parity[k++] = buf8[i] & msk;
8828 i++;
8829
8830 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8831 parity[k++] = buf8[i] & msk;
8832 i++;
8833 }
8834 data[j++] = buf8[i];
8835 }
8836
8837 err = -EIO;
8838 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8839 u8 hw8 = hweight8(data[i]);
8840
8841 if ((hw8 & 0x1) && parity[i])
8842 goto out;
8843 else if (!(hw8 & 0x1) && !parity[i])
8844 goto out;
8845 }
8846 err = 0;
8847 goto out;
8848 }
8849
566f86ad
MC		 8850 /* Bootstrap checksum at offset 0x10 */
8851 csum = calc_crc((unsigned char *) buf, 0x10);
8852 if(csum != cpu_to_le32(buf[0x10/4]))
8853 goto out;
8854
8855 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8856 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8857 if (csum != cpu_to_le32(buf[0xfc/4]))
8858 goto out;
8859
8860 err = 0;
8861
8862out:
8863 kfree(buf);
8864 return err;
8865}
8866
ca43007a
MC		 8867#define TG3_SERDES_TIMEOUT_SEC 2
8868#define TG3_COPPER_TIMEOUT_SEC 6
8869
8870static int tg3_test_link(struct tg3 *tp)
8871{
8872 int i, max;
8873
8874 if (!netif_running(tp->dev))
8875 return -ENODEV;
8876
4c987487 8877 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8878 max = TG3_SERDES_TIMEOUT_SEC;
8879 else
8880 max = TG3_COPPER_TIMEOUT_SEC;
8881
8882 for (i = 0; i < max; i++) {
8883 if (netif_carrier_ok(tp->dev))
8884 return 0;
8885
8886 if (msleep_interruptible(1000))
8887 break;
8888 }
8889
8890 return -EIO;
8891}
8892
a71116d1 8893/* Only test the commonly used registers */
30ca3e37 8894static int tg3_test_registers(struct tg3 *tp)
a71116d1 8895{
b16250e3 8896 int i, is_5705, is_5750;
a71116d1
MC		 8897 u32 offset, read_mask, write_mask, val, save_val, read_val;
8898 static struct {
8899 u16 offset;
8900 u16 flags;
8901#define TG3_FL_5705 0x1
8902#define TG3_FL_NOT_5705 0x2
8903#define TG3_FL_NOT_5788 0x4
b16250e3 8904#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8905 u32 read_mask;
8906 u32 write_mask;
8907 } reg_tbl[] = {
8908 /* MAC Control Registers */
8909 { MAC_MODE, TG3_FL_NOT_5705,
8910 0x00000000, 0x00ef6f8c },
8911 { MAC_MODE, TG3_FL_5705,
8912 0x00000000, 0x01ef6b8c },
8913 { MAC_STATUS, TG3_FL_NOT_5705,
8914 0x03800107, 0x00000000 },
8915 { MAC_STATUS, TG3_FL_5705,
8916 0x03800100, 0x00000000 },
8917 { MAC_ADDR_0_HIGH, 0x0000,
8918 0x00000000, 0x0000ffff },
8919 { MAC_ADDR_0_LOW, 0x0000,
8920 0x00000000, 0xffffffff },
8921 { MAC_RX_MTU_SIZE, 0x0000,
8922 0x00000000, 0x0000ffff },
8923 { MAC_TX_MODE, 0x0000,
8924 0x00000000, 0x00000070 },
8925 { MAC_TX_LENGTHS, 0x0000,
8926 0x00000000, 0x00003fff },
8927 { MAC_RX_MODE, TG3_FL_NOT_5705,
8928 0x00000000, 0x000007fc },
8929 { MAC_RX_MODE, TG3_FL_5705,
8930 0x00000000, 0x000007dc },
8931 { MAC_HASH_REG_0, 0x0000,
8932 0x00000000, 0xffffffff },
8933 { MAC_HASH_REG_1, 0x0000,
8934 0x00000000, 0xffffffff },
8935 { MAC_HASH_REG_2, 0x0000,
8936 0x00000000, 0xffffffff },
8937 { MAC_HASH_REG_3, 0x0000,
8938 0x00000000, 0xffffffff },
8939
8940 /* Receive Data and Receive BD Initiator Control Registers. */
8941 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8942 0x00000000, 0xffffffff },
8943 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8944 0x00000000, 0xffffffff },
8945 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8946 0x00000000, 0x00000003 },
8947 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8948 0x00000000, 0xffffffff },
8949 { RCVDBDI_STD_BD+0, 0x0000,
8950 0x00000000, 0xffffffff },
8951 { RCVDBDI_STD_BD+4, 0x0000,
8952 0x00000000, 0xffffffff },
8953 { RCVDBDI_STD_BD+8, 0x0000,
8954 0x00000000, 0xffff0002 },
8955 { RCVDBDI_STD_BD+0xc, 0x0000,
8956 0x00000000, 0xffffffff },
6aa20a22 8957
a71116d1
MC		 8958 /* Receive BD Initiator Control Registers. */
8959 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8960 0x00000000, 0xffffffff },
8961 { RCVBDI_STD_THRESH, TG3_FL_5705,
8962 0x00000000, 0x000003ff },
8963 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8964 0x00000000, 0xffffffff },
6aa20a22 8965
a71116d1
MC		 8966 /* Host Coalescing Control Registers. */
8967 { HOSTCC_MODE, TG3_FL_NOT_5705,
8968 0x00000000, 0x00000004 },
8969 { HOSTCC_MODE, TG3_FL_5705,
8970 0x00000000, 0x000000f6 },
8971 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8972 0x00000000, 0xffffffff },
8973 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8974 0x00000000, 0x000003ff },
8975 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8976 0x00000000, 0xffffffff },
8977 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8978 0x00000000, 0x000003ff },
8979 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8980 0x00000000, 0xffffffff },
8981 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8982 0x00000000, 0x000000ff },
8983 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8984 0x00000000, 0xffffffff },
8985 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8986 0x00000000, 0x000000ff },
8987 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8988 0x00000000, 0xffffffff },
8989 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8990 0x00000000, 0xffffffff },
8991 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8992 0x00000000, 0xffffffff },
8993 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8994 0x00000000, 0x000000ff },
8995 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8996 0x00000000, 0xffffffff },
8997 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8998 0x00000000, 0x000000ff },
8999 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9000 0x00000000, 0xffffffff },
9001 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9002 0x00000000, 0xffffffff },
9003 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9004 0x00000000, 0xffffffff },
9005 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9006 0x00000000, 0xffffffff },
9007 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9008 0x00000000, 0xffffffff },
9009 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9010 0xffffffff, 0x00000000 },
9011 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9012 0xffffffff, 0x00000000 },
9013
9014 /* Buffer Manager Control Registers. */
b16250e3 9015 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9016 0x00000000, 0x007fff80 },
b16250e3 9017 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9018 0x00000000, 0x007fffff },
9019 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9020 0x00000000, 0x0000003f },
9021 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9022 0x00000000, 0x000001ff },
9023 { BUFMGR_MB_HIGH_WATER, 0x0000,
9024 0x00000000, 0x000001ff },
9025 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9026 0xffffffff, 0x00000000 },
9027 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9028 0xffffffff, 0x00000000 },
6aa20a22 9029
a71116d1
MC		 9030 /* Mailbox Registers */
9031 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9032 0x00000000, 0x000001ff },
9033 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9034 0x00000000, 0x000001ff },
9035 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9036 0x00000000, 0x000007ff },
9037 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9038 0x00000000, 0x000001ff },
9039
9040 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9041 };
9042
b16250e3
MC		 9043 is_5705 = is_5750 = 0;
9044 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9045 is_5705 = 1;
b16250e3
MC		 9046 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9047 is_5750 = 1;
9048 }
a71116d1
MC		 9049
9050 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9051 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9052 continue;
9053
9054 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9055 continue;
9056
9057 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9058 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9059 continue;
9060
b16250e3
MC		 9061 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9062 continue;
9063
a71116d1
MC		 9064 offset = (u32) reg_tbl[i].offset;
9065 read_mask = reg_tbl[i].read_mask;
9066 write_mask = reg_tbl[i].write_mask;
9067
9068 /* Save the original register content */
9069 save_val = tr32(offset);
9070
9071 /* Determine the read-only value. */
9072 read_val = save_val & read_mask;
9073
9074 /* Write zero to the register, then make sure the read-only bits
9075 * are not changed and the read/write bits are all zeros.
9076 */
9077 tw32(offset, 0);
9078
9079 val = tr32(offset);
9080
9081 /* Test the read-only and read/write bits. */
9082 if (((val & read_mask) != read_val) || (val & write_mask))
9083 goto out;
9084
9085 /* Write ones to all the bits defined by RdMask and WrMask, then
9086 * make sure the read-only bits are not changed and the
9087 * read/write bits are all ones.
9088 */
9089 tw32(offset, read_mask | write_mask);
9090
9091 val = tr32(offset);
9092
9093 /* Test the read-only bits. */
9094 if ((val & read_mask) != read_val)
9095 goto out;
9096
9097 /* Test the read/write bits. */
9098 if ((val & write_mask) != write_mask)
9099 goto out;
9100
9101 tw32(offset, save_val);
9102 }
9103
9104 return 0;
9105
9106out:
9f88f29f
MC		 9107 if (netif_msg_hw(tp))
9108 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9109 offset);
a71116d1
MC		 9110 tw32(offset, save_val);
9111 return -EIO;
9112}
9113
7942e1db
MC		 9114static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9115{
f71e1309 9116 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9117 int i;
9118 u32 j;
9119
e9edda69 9120 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9121 for (j = 0; j < len; j += 4) {
9122 u32 val;
9123
9124 tg3_write_mem(tp, offset + j, test_pattern[i]);
9125 tg3_read_mem(tp, offset + j, &val);
9126 if (val != test_pattern[i])
9127 return -EIO;
9128 }
9129 }
9130 return 0;
9131}
9132
9133static int tg3_test_memory(struct tg3 *tp)
9134{
9135 static struct mem_entry {
9136 u32 offset;
9137 u32 len;
9138 } mem_tbl_570x[] = {
38690194 9139 { 0x00000000, 0x00b50},
7942e1db
MC		 9140 { 0x00002000, 0x1c000},
9141 { 0xffffffff, 0x00000}
9142 }, mem_tbl_5705[] = {
9143 { 0x00000100, 0x0000c},
9144 { 0x00000200, 0x00008},
7942e1db
MC		 9145 { 0x00004000, 0x00800},
9146 { 0x00006000, 0x01000},
9147 { 0x00008000, 0x02000},
9148 { 0x00010000, 0x0e000},
9149 { 0xffffffff, 0x00000}
79f4d13a
MC		 9150 }, mem_tbl_5755[] = {
9151 { 0x00000200, 0x00008},
9152 { 0x00004000, 0x00800},
9153 { 0x00006000, 0x00800},
9154 { 0x00008000, 0x02000},
9155 { 0x00010000, 0x0c000},
9156 { 0xffffffff, 0x00000}
b16250e3
MC		 9157 }, mem_tbl_5906[] = {
9158 { 0x00000200, 0x00008},
9159 { 0x00004000, 0x00400},
9160 { 0x00006000, 0x00400},
9161 { 0x00008000, 0x01000},
9162 { 0x00010000, 0x01000},
9163 { 0xffffffff, 0x00000}
7942e1db
MC		 9164 };
9165 struct mem_entry *mem_tbl;
9166 int err = 0;
9167 int i;
9168
79f4d13a 9169 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6 9170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 9171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 9172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
79f4d13a 9174 mem_tbl = mem_tbl_5755;
b16250e3
MC		 9175 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9176 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 9177 else
9178 mem_tbl = mem_tbl_5705;
9179 } else
7942e1db
MC		 9180 mem_tbl = mem_tbl_570x;
9181
9182 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9183 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9184 mem_tbl[i].len)) != 0)
9185 break;
9186 }
6aa20a22 9187
7942e1db
MC		 9188 return err;
9189}
9190
9f40dead
MC		 9191#define TG3_MAC_LOOPBACK 0
9192#define TG3_PHY_LOOPBACK 1
9193
9194static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9195{
9f40dead 9196 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9197 u32 desc_idx;
9198 struct sk_buff *skb, *rx_skb;
9199 u8 *tx_data;
9200 dma_addr_t map;
9201 int num_pkts, tx_len, rx_len, i, err;
9202 struct tg3_rx_buffer_desc *desc;
9203
9f40dead 9204 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9205 /* HW errata - mac loopback fails in some cases on 5780.
9206 * Normal traffic and PHY loopback are not affected by
9207 * errata.
9208 */
9209 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9210 return 0;
9211
9f40dead 9212 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9213 MAC_MODE_PORT_INT_LPBACK;
9214 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9215 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9216 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9217 mac_mode |= MAC_MODE_PORT_MODE_MII;
9218 else
9219 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9220 tw32(MAC_MODE, mac_mode);
9221 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9222 u32 val;
9223
b16250e3
MC		 9224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9225 u32 phytest;
9226
9227 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9228 u32 phy;
9229
9230 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9231 phytest | MII_TG3_EPHY_SHADOW_EN);
9232 if (!tg3_readphy(tp, 0x1b, &phy))
9233 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9234 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9235 }
5d64ad34
MC		 9236 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9237 } else
9238 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9239
9ef8ca99
MC		 9240 tg3_phy_toggle_automdix(tp, 0);
9241
3f7045c1 9242 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9243 udelay(40);
5d64ad34 9244
e8f3f6ca 9245 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9247 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9248 mac_mode |= MAC_MODE_PORT_MODE_MII;
9249 } else
9250 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9251
c94e3941
MC		 9252 /* reset to prevent losing 1st rx packet intermittently */
9253 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9254 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9255 udelay(10);
9256 tw32_f(MAC_RX_MODE, tp->rx_mode);
9257 }
e8f3f6ca
MC		 9258 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9259 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9260 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9261 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9262 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9263 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9264 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9265 }
9f40dead 9266 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9267 }
9268 else
9269 return -EINVAL;
c76949a6
MC		 9270
9271 err = -EIO;
9272
c76949a6 9273 tx_len = 1514;
a20e9c62 9274 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9275 if (!skb)
9276 return -ENOMEM;
9277
c76949a6
MC		 9278 tx_data = skb_put(skb, tx_len);
9279 memcpy(tx_data, tp->dev->dev_addr, 6);
9280 memset(tx_data + 6, 0x0, 8);
9281
9282 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9283
9284 for (i = 14; i < tx_len; i++)
9285 tx_data[i] = (u8) (i & 0xff);
9286
9287 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9288
9289 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9290 HOSTCC_MODE_NOW);
9291
9292 udelay(10);
9293
9294 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9295
c76949a6
MC		 9296 num_pkts = 0;
9297
9f40dead 9298 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9299
9f40dead 9300 tp->tx_prod++;
c76949a6
MC		 9301 num_pkts++;
9302
9f40dead
MC		 9303 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9304 tp->tx_prod);
09ee929c 9305 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9306
9307 udelay(10);
9308
3f7045c1
MC		 9309 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9310 for (i = 0; i < 25; i++) {
c76949a6
MC		 9311 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9312 HOSTCC_MODE_NOW);
9313
9314 udelay(10);
9315
9316 tx_idx = tp->hw_status->idx[0].tx_consumer;
9317 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9318 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9319 (rx_idx == (rx_start_idx + num_pkts)))
9320 break;
9321 }
9322
9323 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9324 dev_kfree_skb(skb);
9325
9f40dead 9326 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9327 goto out;
9328
9329 if (rx_idx != rx_start_idx + num_pkts)
9330 goto out;
9331
9332 desc = &tp->rx_rcb[rx_start_idx];
9333 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9334 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9335 if (opaque_key != RXD_OPAQUE_RING_STD)
9336 goto out;
9337
9338 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9339 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9340 goto out;
9341
9342 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9343 if (rx_len != tx_len)
9344 goto out;
9345
9346 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9347
9348 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9349 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9350
9351 for (i = 14; i < tx_len; i++) {
9352 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9353 goto out;
9354 }
9355 err = 0;
6aa20a22 9356
c76949a6
MC		 9357 /* tg3_free_rings will unmap and free the rx_skb */
9358out:
9359 return err;
9360}
9361
9f40dead
MC		 9362#define TG3_MAC_LOOPBACK_FAILED 1
9363#define TG3_PHY_LOOPBACK_FAILED 2
9364#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9365 TG3_PHY_LOOPBACK_FAILED)
9366
9367static int tg3_test_loopback(struct tg3 *tp)
9368{
9369 int err = 0;
9936bcf6 9370 u32 cpmuctrl = 0;
9f40dead
MC		 9371
9372 if (!netif_running(tp->dev))
9373 return TG3_LOOPBACK_FAILED;
9374
b9ec6c1b
MC		 9375 err = tg3_reset_hw(tp, 1);
9376 if (err)
9377 return TG3_LOOPBACK_FAILED;
9f40dead 9378
e875093c
MC		 9379 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
9380 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0) {
9936bcf6
MC		 9381 int i;
9382 u32 status;
9383
9384 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9385
9386 /* Wait for up to 40 microseconds to acquire lock. */
9387 for (i = 0; i < 4; i++) {
9388 status = tr32(TG3_CPMU_MUTEX_GNT);
9389 if (status == CPMU_MUTEX_GNT_DRIVER)
9390 break;
9391 udelay(10);
9392 }
9393
9394 if (status != CPMU_MUTEX_GNT_DRIVER)
9395 return TG3_LOOPBACK_FAILED;
9396
9936bcf6 9397 /* Turn off power management based on link speed. */
e875093c 9398 cpmuctrl = tr32(TG3_CPMU_CTRL);
9936bcf6 9399 tw32(TG3_CPMU_CTRL,
e875093c
MC		 9400 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9401 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9402 }
9403
9f40dead
MC		 9404 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9405 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9406
e875093c
MC		 9407 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
9408 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0) {
9936bcf6
MC		 9409 tw32(TG3_CPMU_CTRL, cpmuctrl);
9410
9411 /* Release the mutex */
9412 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9413 }
9414
9f40dead
MC		 9415 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9416 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9417 err |= TG3_PHY_LOOPBACK_FAILED;
9418 }
9419
9420 return err;
9421}
9422
4cafd3f5
MC		 9423static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9424 u64 *data)
9425{
566f86ad
MC		 9426 struct tg3 *tp = netdev_priv(dev);
9427
bc1c7567
MC		 9428 if (tp->link_config.phy_is_low_power)
9429 tg3_set_power_state(tp, PCI_D0);
9430
566f86ad
MC		 9431 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9432
9433 if (tg3_test_nvram(tp) != 0) {
9434 etest->flags |= ETH_TEST_FL_FAILED;
9435 data[0] = 1;
9436 }
ca43007a
MC		 9437 if (tg3_test_link(tp) != 0) {
9438 etest->flags |= ETH_TEST_FL_FAILED;
9439 data[1] = 1;
9440 }
a71116d1 9441 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 9442 int err, irq_sync = 0;
bbe832c0
MC		 9443
9444 if (netif_running(dev)) {
a71116d1 9445 tg3_netif_stop(tp);
bbe832c0
MC		 9446 irq_sync = 1;
9447 }
a71116d1 9448
bbe832c0 9449 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9450
9451 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9452 err = tg3_nvram_lock(tp);
a71116d1
MC		 9453 tg3_halt_cpu(tp, RX_CPU_BASE);
9454 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9455 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9456 if (!err)
9457 tg3_nvram_unlock(tp);
a71116d1 9458
d9ab5ad1
MC		 9459 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9460 tg3_phy_reset(tp);
9461
a71116d1
MC		 9462 if (tg3_test_registers(tp) != 0) {
9463 etest->flags |= ETH_TEST_FL_FAILED;
9464 data[2] = 1;
9465 }
7942e1db
MC		 9466 if (tg3_test_memory(tp) != 0) {
9467 etest->flags |= ETH_TEST_FL_FAILED;
9468 data[3] = 1;
9469 }
9f40dead 9470 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9471 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9472
f47c11ee
DM		 9473 tg3_full_unlock(tp);
9474
d4bc3927
MC		 9475 if (tg3_test_interrupt(tp) != 0) {
9476 etest->flags |= ETH_TEST_FL_FAILED;
9477 data[5] = 1;
9478 }
f47c11ee
DM		 9479
9480 tg3_full_lock(tp, 0);
d4bc3927 9481
a71116d1
MC		 9482 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9483 if (netif_running(dev)) {
9484 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9485 if (!tg3_restart_hw(tp, 1))
9486 tg3_netif_start(tp);
a71116d1 9487 }
f47c11ee
DM		 9488
9489 tg3_full_unlock(tp);
a71116d1 9490 }
bc1c7567
MC		 9491 if (tp->link_config.phy_is_low_power)
9492 tg3_set_power_state(tp, PCI_D3hot);
9493
4cafd3f5
MC		 9494}
9495
1da177e4
LT		 9496static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9497{
9498 struct mii_ioctl_data *data = if_mii(ifr);
9499 struct tg3 *tp = netdev_priv(dev);
9500 int err;
9501
9502 switch(cmd) {
9503 case SIOCGMIIPHY:
9504 data->phy_id = PHY_ADDR;
9505
9506 /* fallthru */
9507 case SIOCGMIIREG: {
9508 u32 mii_regval;
9509
9510 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9511 break; /* We have no PHY */
9512
bc1c7567
MC		 9513 if (tp->link_config.phy_is_low_power)
9514 return -EAGAIN;
9515
f47c11ee 9516 spin_lock_bh(&tp->lock);
1da177e4 9517 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9518 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9519
9520 data->val_out = mii_regval;
9521
9522 return err;
9523 }
9524
9525 case SIOCSMIIREG:
9526 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9527 break; /* We have no PHY */
9528
9529 if (!capable(CAP_NET_ADMIN))
9530 return -EPERM;
9531
bc1c7567
MC		 9532 if (tp->link_config.phy_is_low_power)
9533 return -EAGAIN;
9534
f47c11ee 9535 spin_lock_bh(&tp->lock);
1da177e4 9536 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9537 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9538
9539 return err;
9540
9541 default:
9542 /* do nothing */
9543 break;
9544 }
9545 return -EOPNOTSUPP;
9546}
9547
9548#if TG3_VLAN_TAG_USED
9549static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9550{
9551 struct tg3 *tp = netdev_priv(dev);
9552
29315e87
MC		 9553 if (netif_running(dev))
9554 tg3_netif_stop(tp);
9555
f47c11ee 9556 tg3_full_lock(tp, 0);
1da177e4
LT		 9557
9558 tp->vlgrp = grp;
9559
9560 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9561 __tg3_set_rx_mode(dev);
9562
29315e87
MC		 9563 if (netif_running(dev))
9564 tg3_netif_start(tp);
46966545
MC		 9565
9566 tg3_full_unlock(tp);
1da177e4 9567}
1da177e4
LT		 9568#endif
9569
15f9850d
DM		 9570static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9571{
9572 struct tg3 *tp = netdev_priv(dev);
9573
9574 memcpy(ec, &tp->coal, sizeof(*ec));
9575 return 0;
9576}
9577
d244c892
MC		 9578static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9579{
9580 struct tg3 *tp = netdev_priv(dev);
9581 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9582 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9583
9584 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9585 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9586 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9587 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9588 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9589 }
9590
9591 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9592 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9593 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9594 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9595 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9596 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9597 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9598 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9599 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9600 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9601 return -EINVAL;
9602
9603 /* No rx interrupts will be generated if both are zero */
9604 if ((ec->rx_coalesce_usecs == 0) &&
9605 (ec->rx_max_coalesced_frames == 0))
9606 return -EINVAL;
9607
9608 /* No tx interrupts will be generated if both are zero */
9609 if ((ec->tx_coalesce_usecs == 0) &&
9610 (ec->tx_max_coalesced_frames == 0))
9611 return -EINVAL;
9612
9613 /* Only copy relevant parameters, ignore all others. */
9614 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9615 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9616 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9617 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9618 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9619 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9620 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9621 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9622 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9623
9624 if (netif_running(dev)) {
9625 tg3_full_lock(tp, 0);
9626 __tg3_set_coalesce(tp, &tp->coal);
9627 tg3_full_unlock(tp);
9628 }
9629 return 0;
9630}
9631
7282d491 9632static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9633 .get_settings = tg3_get_settings,
9634 .set_settings = tg3_set_settings,
9635 .get_drvinfo = tg3_get_drvinfo,
9636 .get_regs_len = tg3_get_regs_len,
9637 .get_regs = tg3_get_regs,
9638 .get_wol = tg3_get_wol,
9639 .set_wol = tg3_set_wol,
9640 .get_msglevel = tg3_get_msglevel,
9641 .set_msglevel = tg3_set_msglevel,
9642 .nway_reset = tg3_nway_reset,
9643 .get_link = ethtool_op_get_link,
9644 .get_eeprom_len = tg3_get_eeprom_len,
9645 .get_eeprom = tg3_get_eeprom,
9646 .set_eeprom = tg3_set_eeprom,
9647 .get_ringparam = tg3_get_ringparam,
9648 .set_ringparam = tg3_set_ringparam,
9649 .get_pauseparam = tg3_get_pauseparam,
9650 .set_pauseparam = tg3_set_pauseparam,
9651 .get_rx_csum = tg3_get_rx_csum,
9652 .set_rx_csum = tg3_set_rx_csum,
1da177e4 9653 .set_tx_csum = tg3_set_tx_csum,
1da177e4 9654 .set_sg = ethtool_op_set_sg,
1da177e4 9655 .set_tso = tg3_set_tso,
4cafd3f5 9656 .self_test = tg3_self_test,
1da177e4 9657 .get_strings = tg3_get_strings,
4009a93d 9658 .phys_id = tg3_phys_id,
1da177e4 9659 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9660 .get_coalesce = tg3_get_coalesce,
d244c892 9661 .set_coalesce = tg3_set_coalesce,
b9f2c044 9662 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 9663};
9664
9665static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9666{
1b27777a 9667 u32 cursize, val, magic;
1da177e4
LT		 9668
9669 tp->nvram_size = EEPROM_CHIP_SIZE;
9670
1820180b 9671 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9672 return;
9673
b16250e3
MC		 9674 if ((magic != TG3_EEPROM_MAGIC) &&
9675 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9676 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9677 return;
9678
9679 /*
9680 * Size the chip by reading offsets at increasing powers of two.
9681 * When we encounter our validation signature, we know the addressing
9682 * has wrapped around, and thus have our chip size.
9683 */
1b27777a 9684 cursize = 0x10;
1da177e4
LT		 9685
9686 while (cursize < tp->nvram_size) {
1820180b 9687 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9688 return;
9689
1820180b 9690 if (val == magic)
1da177e4
LT		 9691 break;
9692
9693 cursize <<= 1;
9694 }
9695
9696 tp->nvram_size = cursize;
9697}
6aa20a22 9698
1da177e4
LT		 9699static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9700{
9701 u32 val;
9702
1820180b 9703 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9704 return;
9705
9706 /* Selfboot format */
1820180b 9707 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9708 tg3_get_eeprom_size(tp);
9709 return;
9710 }
9711
1da177e4
LT		 9712 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9713 if (val != 0) {
9714 tp->nvram_size = (val >> 16) * 1024;
9715 return;
9716 }
9717 }
989a9d23 9718 tp->nvram_size = 0x80000;
1da177e4
LT		 9719}
9720
9721static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9722{
9723 u32 nvcfg1;
9724
9725 nvcfg1 = tr32(NVRAM_CFG1);
9726 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9727 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9728 }
9729 else {
9730 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9731 tw32(NVRAM_CFG1, nvcfg1);
9732 }
9733
4c987487 9734 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9735 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9736 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9737 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9738 tp->nvram_jedecnum = JEDEC_ATMEL;
9739 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9740 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9741 break;
9742 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9743 tp->nvram_jedecnum = JEDEC_ATMEL;
9744 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9745 break;
9746 case FLASH_VENDOR_ATMEL_EEPROM:
9747 tp->nvram_jedecnum = JEDEC_ATMEL;
9748 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9749 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9750 break;
9751 case FLASH_VENDOR_ST:
9752 tp->nvram_jedecnum = JEDEC_ST;
9753 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9754 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9755 break;
9756 case FLASH_VENDOR_SAIFUN:
9757 tp->nvram_jedecnum = JEDEC_SAIFUN;
9758 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9759 break;
9760 case FLASH_VENDOR_SST_SMALL:
9761 case FLASH_VENDOR_SST_LARGE:
9762 tp->nvram_jedecnum = JEDEC_SST;
9763 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9764 break;
9765 }
9766 }
9767 else {
9768 tp->nvram_jedecnum = JEDEC_ATMEL;
9769 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9770 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9771 }
9772}
9773
361b4ac2
MC		 9774static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9775{
9776 u32 nvcfg1;
9777
9778 nvcfg1 = tr32(NVRAM_CFG1);
9779
e6af301b
MC		 9780 /* NVRAM protection for TPM */
9781 if (nvcfg1 & (1 << 27))
9782 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9783
361b4ac2
MC		 9784 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9785 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9786 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9787 tp->nvram_jedecnum = JEDEC_ATMEL;
9788 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9789 break;
9790 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9791 tp->nvram_jedecnum = JEDEC_ATMEL;
9792 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9793 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9794 break;
9795 case FLASH_5752VENDOR_ST_M45PE10:
9796 case FLASH_5752VENDOR_ST_M45PE20:
9797 case FLASH_5752VENDOR_ST_M45PE40:
9798 tp->nvram_jedecnum = JEDEC_ST;
9799 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9800 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9801 break;
9802 }
9803
9804 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9805 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9806 case FLASH_5752PAGE_SIZE_256:
9807 tp->nvram_pagesize = 256;
9808 break;
9809 case FLASH_5752PAGE_SIZE_512:
9810 tp->nvram_pagesize = 512;
9811 break;
9812 case FLASH_5752PAGE_SIZE_1K:
9813 tp->nvram_pagesize = 1024;
9814 break;
9815 case FLASH_5752PAGE_SIZE_2K:
9816 tp->nvram_pagesize = 2048;
9817 break;
9818 case FLASH_5752PAGE_SIZE_4K:
9819 tp->nvram_pagesize = 4096;
9820 break;
9821 case FLASH_5752PAGE_SIZE_264:
9822 tp->nvram_pagesize = 264;
9823 break;
9824 }
9825 }
9826 else {
9827 /* For eeprom, set pagesize to maximum eeprom size */
9828 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9829
9830 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9831 tw32(NVRAM_CFG1, nvcfg1);
9832 }
9833}
9834
d3c7b886
MC		 9835static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9836{
989a9d23 9837 u32 nvcfg1, protect = 0;
d3c7b886
MC		 9838
9839 nvcfg1 = tr32(NVRAM_CFG1);
9840
9841 /* NVRAM protection for TPM */
989a9d23 9842 if (nvcfg1 & (1 << 27)) {
d3c7b886 9843 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 9844 protect = 1;
9845 }
d3c7b886 9846
989a9d23
MC		 9847 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9848 switch (nvcfg1) {
d3c7b886
MC		 9849 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9850 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9851 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 9852 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 9853 tp->nvram_jedecnum = JEDEC_ATMEL;
9854 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9855 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9856 tp->nvram_pagesize = 264;
70b65a2d
MC		 9857 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9858 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
989a9d23
MC		 9859 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9860 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9861 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9862 else
9863 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
d3c7b886
MC		 9864 break;
9865 case FLASH_5752VENDOR_ST_M45PE10:
9866 case FLASH_5752VENDOR_ST_M45PE20:
9867 case FLASH_5752VENDOR_ST_M45PE40:
9868 tp->nvram_jedecnum = JEDEC_ST;
9869 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9870 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9871 tp->nvram_pagesize = 256;
989a9d23
MC		 9872 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9873 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9874 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9875 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9876 else
9877 tp->nvram_size = (protect ? 0x20000 : 0x80000);
d3c7b886
MC		 9878 break;
9879 }
9880}
9881
1b27777a
MC		 9882static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9883{
9884 u32 nvcfg1;
9885
9886 nvcfg1 = tr32(NVRAM_CFG1);
9887
9888 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9889 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9890 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9891 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9892 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9893 tp->nvram_jedecnum = JEDEC_ATMEL;
9894 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9895 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9896
9897 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9898 tw32(NVRAM_CFG1, nvcfg1);
9899 break;
9900 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9901 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9902 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9903 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9904 tp->nvram_jedecnum = JEDEC_ATMEL;
9905 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9906 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9907 tp->nvram_pagesize = 264;
9908 break;
9909 case FLASH_5752VENDOR_ST_M45PE10:
9910 case FLASH_5752VENDOR_ST_M45PE20:
9911 case FLASH_5752VENDOR_ST_M45PE40:
9912 tp->nvram_jedecnum = JEDEC_ST;
9913 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9914 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9915 tp->nvram_pagesize = 256;
9916 break;
9917 }
9918}
9919
6b91fa02
MC		 9920static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
9921{
9922 u32 nvcfg1, protect = 0;
9923
9924 nvcfg1 = tr32(NVRAM_CFG1);
9925
9926 /* NVRAM protection for TPM */
9927 if (nvcfg1 & (1 << 27)) {
9928 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9929 protect = 1;
9930 }
9931
9932 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9933 switch (nvcfg1) {
9934 case FLASH_5761VENDOR_ATMEL_ADB021D:
9935 case FLASH_5761VENDOR_ATMEL_ADB041D:
9936 case FLASH_5761VENDOR_ATMEL_ADB081D:
9937 case FLASH_5761VENDOR_ATMEL_ADB161D:
9938 case FLASH_5761VENDOR_ATMEL_MDB021D:
9939 case FLASH_5761VENDOR_ATMEL_MDB041D:
9940 case FLASH_5761VENDOR_ATMEL_MDB081D:
9941 case FLASH_5761VENDOR_ATMEL_MDB161D:
9942 tp->nvram_jedecnum = JEDEC_ATMEL;
9943 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9944 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9945 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
9946 tp->nvram_pagesize = 256;
9947 break;
9948 case FLASH_5761VENDOR_ST_A_M45PE20:
9949 case FLASH_5761VENDOR_ST_A_M45PE40:
9950 case FLASH_5761VENDOR_ST_A_M45PE80:
9951 case FLASH_5761VENDOR_ST_A_M45PE16:
9952 case FLASH_5761VENDOR_ST_M_M45PE20:
9953 case FLASH_5761VENDOR_ST_M_M45PE40:
9954 case FLASH_5761VENDOR_ST_M_M45PE80:
9955 case FLASH_5761VENDOR_ST_M_M45PE16:
9956 tp->nvram_jedecnum = JEDEC_ST;
9957 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9958 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9959 tp->nvram_pagesize = 256;
9960 break;
9961 }
9962
9963 if (protect) {
9964 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
9965 } else {
9966 switch (nvcfg1) {
9967 case FLASH_5761VENDOR_ATMEL_ADB161D:
9968 case FLASH_5761VENDOR_ATMEL_MDB161D:
9969 case FLASH_5761VENDOR_ST_A_M45PE16:
9970 case FLASH_5761VENDOR_ST_M_M45PE16:
9971 tp->nvram_size = 0x100000;
9972 break;
9973 case FLASH_5761VENDOR_ATMEL_ADB081D:
9974 case FLASH_5761VENDOR_ATMEL_MDB081D:
9975 case FLASH_5761VENDOR_ST_A_M45PE80:
9976 case FLASH_5761VENDOR_ST_M_M45PE80:
9977 tp->nvram_size = 0x80000;
9978 break;
9979 case FLASH_5761VENDOR_ATMEL_ADB041D:
9980 case FLASH_5761VENDOR_ATMEL_MDB041D:
9981 case FLASH_5761VENDOR_ST_A_M45PE40:
9982 case FLASH_5761VENDOR_ST_M_M45PE40:
9983 tp->nvram_size = 0x40000;
9984 break;
9985 case FLASH_5761VENDOR_ATMEL_ADB021D:
9986 case FLASH_5761VENDOR_ATMEL_MDB021D:
9987 case FLASH_5761VENDOR_ST_A_M45PE20:
9988 case FLASH_5761VENDOR_ST_M_M45PE20:
9989 tp->nvram_size = 0x20000;
9990 break;
9991 }
9992 }
9993}
9994
b5d3772c
MC		 9995static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9996{
9997 tp->nvram_jedecnum = JEDEC_ATMEL;
9998 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9999 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10000}
10001
1da177e4
LT		 10002/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10003static void __devinit tg3_nvram_init(struct tg3 *tp)
10004{
1da177e4
LT		 10005 tw32_f(GRC_EEPROM_ADDR,
10006 (EEPROM_ADDR_FSM_RESET |
10007 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10008 EEPROM_ADDR_CLKPERD_SHIFT)));
10009
9d57f01c 10010 msleep(1);
1da177e4
LT		 10011
10012 /* Enable seeprom accesses. */
10013 tw32_f(GRC_LOCAL_CTRL,
10014 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10015 udelay(100);
10016
10017 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10018 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10019 tp->tg3_flags |= TG3_FLAG_NVRAM;
10020
ec41c7df
MC		 10021 if (tg3_nvram_lock(tp)) {
10022 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10023 "tg3_nvram_init failed.\n", tp->dev->name);
10024 return;
10025 }
e6af301b 10026 tg3_enable_nvram_access(tp);
1da177e4 10027
989a9d23
MC		 10028 tp->nvram_size = 0;
10029
361b4ac2
MC		 10030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10031 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10032 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10033 tg3_get_5755_nvram_info(tp);
d30cdd28
MC		 10034 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
1b27777a 10036 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10037 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10038 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10039 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10040 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 10041 else
10042 tg3_get_nvram_info(tp);
10043
989a9d23
MC		 10044 if (tp->nvram_size == 0)
10045 tg3_get_nvram_size(tp);
1da177e4 10046
e6af301b 10047 tg3_disable_nvram_access(tp);
381291b7 10048 tg3_nvram_unlock(tp);
1da177e4
LT		 10049
10050 } else {
10051 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10052
10053 tg3_get_eeprom_size(tp);
10054 }
10055}
10056
10057static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10058 u32 offset, u32 *val)
10059{
10060 u32 tmp;
10061 int i;
10062
10063 if (offset > EEPROM_ADDR_ADDR_MASK ||
10064 (offset % 4) != 0)
10065 return -EINVAL;
10066
10067 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10068 EEPROM_ADDR_DEVID_MASK |
10069 EEPROM_ADDR_READ);
10070 tw32(GRC_EEPROM_ADDR,
10071 tmp |
10072 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10073 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10074 EEPROM_ADDR_ADDR_MASK) |
10075 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10076
9d57f01c 10077 for (i = 0; i < 1000; i++) {
1da177e4
LT		 10078 tmp = tr32(GRC_EEPROM_ADDR);
10079
10080 if (tmp & EEPROM_ADDR_COMPLETE)
10081 break;
9d57f01c 10082 msleep(1);
1da177e4
LT		 10083 }
10084 if (!(tmp & EEPROM_ADDR_COMPLETE))
10085 return -EBUSY;
10086
10087 *val = tr32(GRC_EEPROM_DATA);
10088 return 0;
10089}
10090
10091#define NVRAM_CMD_TIMEOUT 10000
10092
10093static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10094{
10095 int i;
10096
10097 tw32(NVRAM_CMD, nvram_cmd);
10098 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10099 udelay(10);
10100 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10101 udelay(10);
10102 break;
10103 }
10104 }
10105 if (i == NVRAM_CMD_TIMEOUT) {
10106 return -EBUSY;
10107 }
10108 return 0;
10109}
10110
1820180b
MC		 10111static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10112{
10113 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10114 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10115 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10116 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1820180b
MC		 10117 (tp->nvram_jedecnum == JEDEC_ATMEL))
10118
10119 addr = ((addr / tp->nvram_pagesize) <<
10120 ATMEL_AT45DB0X1B_PAGE_POS) +
10121 (addr % tp->nvram_pagesize);
10122
10123 return addr;
10124}
10125
c4e6575c
MC		 10126static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10127{
10128 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10129 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10130 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10131 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
c4e6575c
MC		 10132 (tp->nvram_jedecnum == JEDEC_ATMEL))
10133
10134 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10135 tp->nvram_pagesize) +
10136 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10137
10138 return addr;
10139}
10140
1da177e4
LT		 10141static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10142{
10143 int ret;
10144
1da177e4
LT		 10145 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10146 return tg3_nvram_read_using_eeprom(tp, offset, val);
10147
1820180b 10148 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10149
10150 if (offset > NVRAM_ADDR_MSK)
10151 return -EINVAL;
10152
ec41c7df
MC		 10153 ret = tg3_nvram_lock(tp);
10154 if (ret)
10155 return ret;
1da177e4 10156
e6af301b 10157 tg3_enable_nvram_access(tp);
1da177e4
LT		 10158
10159 tw32(NVRAM_ADDR, offset);
10160 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10161 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10162
10163 if (ret == 0)
10164 *val = swab32(tr32(NVRAM_RDDATA));
10165
e6af301b 10166 tg3_disable_nvram_access(tp);
1da177e4 10167
381291b7
MC		 10168 tg3_nvram_unlock(tp);
10169
1da177e4
LT		 10170 return ret;
10171}
10172
1820180b
MC		 10173static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10174{
10175 int err;
10176 u32 tmp;
10177
10178 err = tg3_nvram_read(tp, offset, &tmp);
10179 *val = swab32(tmp);
10180 return err;
10181}
10182
1da177e4
LT		 10183static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10184 u32 offset, u32 len, u8 *buf)
10185{
10186 int i, j, rc = 0;
10187 u32 val;
10188
10189 for (i = 0; i < len; i += 4) {
10190 u32 addr, data;
10191
10192 addr = offset + i;
10193
10194 memcpy(&data, buf + i, 4);
10195
10196 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
10197
10198 val = tr32(GRC_EEPROM_ADDR);
10199 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10200
10201 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10202 EEPROM_ADDR_READ);
10203 tw32(GRC_EEPROM_ADDR, val |
10204 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10205 (addr & EEPROM_ADDR_ADDR_MASK) |
10206 EEPROM_ADDR_START |
10207 EEPROM_ADDR_WRITE);
6aa20a22 10208
9d57f01c 10209 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10210 val = tr32(GRC_EEPROM_ADDR);
10211
10212 if (val & EEPROM_ADDR_COMPLETE)
10213 break;
9d57f01c 10214 msleep(1);
1da177e4
LT		 10215 }
10216 if (!(val & EEPROM_ADDR_COMPLETE)) {
10217 rc = -EBUSY;
10218 break;
10219 }
10220 }
10221
10222 return rc;
10223}
10224
10225/* offset and length are dword aligned */
10226static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10227 u8 *buf)
10228{
10229 int ret = 0;
10230 u32 pagesize = tp->nvram_pagesize;
10231 u32 pagemask = pagesize - 1;
10232 u32 nvram_cmd;
10233 u8 *tmp;
10234
10235 tmp = kmalloc(pagesize, GFP_KERNEL);
10236 if (tmp == NULL)
10237 return -ENOMEM;
10238
10239 while (len) {
10240 int j;
e6af301b 10241 u32 phy_addr, page_off, size;
1da177e4
LT		 10242
10243 phy_addr = offset & ~pagemask;
6aa20a22 10244
1da177e4
LT		 10245 for (j = 0; j < pagesize; j += 4) {
10246 if ((ret = tg3_nvram_read(tp, phy_addr + j,
10247 (u32 *) (tmp + j))))
10248 break;
10249 }
10250 if (ret)
10251 break;
10252
10253 page_off = offset & pagemask;
10254 size = pagesize;
10255 if (len < size)
10256 size = len;
10257
10258 len -= size;
10259
10260 memcpy(tmp + page_off, buf, size);
10261
10262 offset = offset + (pagesize - page_off);
10263
e6af301b 10264 tg3_enable_nvram_access(tp);
1da177e4
LT		 10265
10266 /*
10267 * Before we can erase the flash page, we need
10268 * to issue a special "write enable" command.
10269 */
10270 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10271
10272 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10273 break;
10274
10275 /* Erase the target page */
10276 tw32(NVRAM_ADDR, phy_addr);
10277
10278 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10279 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10280
10281 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10282 break;
10283
10284 /* Issue another write enable to start the write. */
10285 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10286
10287 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10288 break;
10289
10290 for (j = 0; j < pagesize; j += 4) {
10291 u32 data;
10292
10293 data = *((u32 *) (tmp + j));
10294 tw32(NVRAM_WRDATA, cpu_to_be32(data));
10295
10296 tw32(NVRAM_ADDR, phy_addr + j);
10297
10298 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10299 NVRAM_CMD_WR;
10300
10301 if (j == 0)
10302 nvram_cmd |= NVRAM_CMD_FIRST;
10303 else if (j == (pagesize - 4))
10304 nvram_cmd |= NVRAM_CMD_LAST;
10305
10306 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10307 break;
10308 }
10309 if (ret)
10310 break;
10311 }
10312
10313 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10314 tg3_nvram_exec_cmd(tp, nvram_cmd);
10315
10316 kfree(tmp);
10317
10318 return ret;
10319}
10320
10321/* offset and length are dword aligned */
10322static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10323 u8 *buf)
10324{
10325 int i, ret = 0;
10326
10327 for (i = 0; i < len; i += 4, offset += 4) {
10328 u32 data, page_off, phy_addr, nvram_cmd;
10329
10330 memcpy(&data, buf + i, 4);
10331 tw32(NVRAM_WRDATA, cpu_to_be32(data));
10332
10333 page_off = offset % tp->nvram_pagesize;
10334
1820180b 10335 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10336
10337 tw32(NVRAM_ADDR, phy_addr);
10338
10339 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10340
10341 if ((page_off == 0) || (i == 0))
10342 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10343 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10344 nvram_cmd |= NVRAM_CMD_LAST;
10345
10346 if (i == (len - 4))
10347 nvram_cmd |= NVRAM_CMD_LAST;
10348
4c987487 10349 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 10350 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 10351 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
d30cdd28 10352 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
9936bcf6 10353 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
4c987487
MC		 10354 (tp->nvram_jedecnum == JEDEC_ST) &&
10355 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10356
10357 if ((ret = tg3_nvram_exec_cmd(tp,
10358 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10359 NVRAM_CMD_DONE)))
10360
10361 break;
10362 }
10363 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10364 /* We always do complete word writes to eeprom. */
10365 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10366 }
10367
10368 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10369 break;
10370 }
10371 return ret;
10372}
10373
10374/* offset and length are dword aligned */
10375static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10376{
10377 int ret;
10378
1da177e4 10379 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10380 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10381 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10382 udelay(40);
10383 }
10384
10385 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10386 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10387 }
10388 else {
10389 u32 grc_mode;
10390
ec41c7df
MC		 10391 ret = tg3_nvram_lock(tp);
10392 if (ret)
10393 return ret;
1da177e4 10394
e6af301b
MC		 10395 tg3_enable_nvram_access(tp);
10396 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10397 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10398 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10399
10400 grc_mode = tr32(GRC_MODE);
10401 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10402
10403 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10404 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10405
10406 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10407 buf);
10408 }
10409 else {
10410 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10411 buf);
10412 }
10413
10414 grc_mode = tr32(GRC_MODE);
10415 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10416
e6af301b 10417 tg3_disable_nvram_access(tp);
1da177e4
LT		 10418 tg3_nvram_unlock(tp);
10419 }
10420
10421 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10422 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10423 udelay(40);
10424 }
10425
10426 return ret;
10427}
10428
10429struct subsys_tbl_ent {
10430 u16 subsys_vendor, subsys_devid;
10431 u32 phy_id;
10432};
10433
10434static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10435 /* Broadcom boards. */
10436 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10437 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10438 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10439 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10440 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10441 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10442 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10443 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10444 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10445 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10446 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10447
10448 /* 3com boards. */
10449 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10450 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10451 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10452 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10453 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10454
10455 /* DELL boards. */
10456 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10457 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10458 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10459 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10460
10461 /* Compaq boards. */
10462 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10463 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10464 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10465 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10466 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10467
10468 /* IBM boards. */
10469 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10470};
10471
10472static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10473{
10474 int i;
10475
10476 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10477 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10478 tp->pdev->subsystem_vendor) &&
10479 (subsys_id_to_phy_id[i].subsys_devid ==
10480 tp->pdev->subsystem_device))
10481 return &subsys_id_to_phy_id[i];
10482 }
10483 return NULL;
10484}
10485
7d0c41ef 10486static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10487{
1da177e4 10488 u32 val;
caf636c7
MC		 10489 u16 pmcsr;
10490
10491 /* On some early chips the SRAM cannot be accessed in D3hot state,
10492 * so need make sure we're in D0.
10493 */
10494 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10495 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10496 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10497 msleep(1);
7d0c41ef
MC		 10498
10499 /* Make sure register accesses (indirect or otherwise)
10500 * will function correctly.
10501 */
10502 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10503 tp->misc_host_ctrl);
1da177e4 10504
f49639e6
DM		 10505 /* The memory arbiter has to be enabled in order for SRAM accesses
10506 * to succeed. Normally on powerup the tg3 chip firmware will make
10507 * sure it is enabled, but other entities such as system netboot
10508 * code might disable it.
10509 */
10510 val = tr32(MEMARB_MODE);
10511 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10512
1da177e4 10513 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10514 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10515
a85feb8c
GZ		 10516 /* Assume an onboard device and WOL capable by default. */
10517 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10518
b5d3772c 10519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10520 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10521 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10522 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10523 }
0527ba35
MC		 10524 val = tr32(VCPU_CFGSHDW);
10525 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 10526 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35
MC		 10527 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10528 (val & VCPU_CFGSHDW_WOL_MAGPKT))
10529 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
b5d3772c
MC		 10530 return;
10531 }
10532
1da177e4
LT		 10533 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10534 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10535 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 10536 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10537 int eeprom_phy_serdes = 0;
1da177e4
LT		 10538
10539 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10540 tp->nic_sram_data_cfg = nic_cfg;
10541
10542 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10543 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10544 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10545 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10546 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10547 (ver > 0) && (ver < 0x100))
10548 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10549
1da177e4
LT		 10550 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10551 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10552 eeprom_phy_serdes = 1;
10553
10554 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10555 if (nic_phy_id != 0) {
10556 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10557 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10558
10559 eeprom_phy_id = (id1 >> 16) << 10;
10560 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10561 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10562 } else
10563 eeprom_phy_id = 0;
10564
7d0c41ef 10565 tp->phy_id = eeprom_phy_id;
747e8f8b 10566 if (eeprom_phy_serdes) {
a4e2b347 10567 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10568 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10569 else
10570 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10571 }
7d0c41ef 10572
cbf46853 10573 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10574 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10575 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10576 else
1da177e4
LT		 10577 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10578
10579 switch (led_cfg) {
10580 default:
10581 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10582 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10583 break;
10584
10585 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10586 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10587 break;
10588
10589 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10590 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10591
10592 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10593 * read on some older 5700/5701 bootcode.
10594 */
10595 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10596 ASIC_REV_5700 ||
10597 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10598 ASIC_REV_5701)
10599 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10600
1da177e4
LT		 10601 break;
10602
10603 case SHASTA_EXT_LED_SHARED:
10604 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10605 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10606 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10607 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10608 LED_CTRL_MODE_PHY_2);
10609 break;
10610
10611 case SHASTA_EXT_LED_MAC:
10612 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10613 break;
10614
10615 case SHASTA_EXT_LED_COMBO:
10616 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10617 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10618 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10619 LED_CTRL_MODE_PHY_2);
10620 break;
10621
10622 };
10623
10624 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10626 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10627 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10628
5f60891b
MC		 10629 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0)
10630 tp->led_ctrl = LED_CTRL_MODE_MAC;
10631
9d26e213 10632 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10633 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10634 if ((tp->pdev->subsystem_vendor ==
10635 PCI_VENDOR_ID_ARIMA) &&
10636 (tp->pdev->subsystem_device == 0x205a ||
10637 tp->pdev->subsystem_device == 0x2063))
10638 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10639 } else {
f49639e6 10640 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10641 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10642 }
1da177e4
LT		 10643
10644 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10645 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10646 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10647 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10648 }
0d3031d9
MC		 10649 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
10650 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
a85feb8c
GZ		 10651 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10652 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10653 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 10654
0527ba35
MC		 10655 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
10656 nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
10657 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10658
1da177e4
LT		 10659 if (cfg2 & (1 << 17))
10660 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10661
10662 /* serdes signal pre-emphasis in register 0x590 set by */
10663 /* bootcode if bit 18 is set */
10664 if (cfg2 & (1 << 18))
10665 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e
MC		 10666
10667 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10668 u32 cfg3;
10669
10670 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10671 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10672 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10673 }
1da177e4 10674 }
7d0c41ef
MC		 10675}
10676
10677static int __devinit tg3_phy_probe(struct tg3 *tp)
10678{
10679 u32 hw_phy_id_1, hw_phy_id_2;
10680 u32 hw_phy_id, hw_phy_id_masked;
10681 int err;
1da177e4
LT		 10682
10683 /* Reading the PHY ID register can conflict with ASF
10684 * firwmare access to the PHY hardware.
10685 */
10686 err = 0;
0d3031d9
MC		 10687 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
10688 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 10689 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10690 } else {
10691 /* Now read the physical PHY_ID from the chip and verify
10692 * that it is sane. If it doesn't look good, we fall back
10693 * to either the hard-coded table based PHY_ID and failing
10694 * that the value found in the eeprom area.
10695 */
10696 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10697 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10698
10699 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10700 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10701 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10702
10703 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10704 }
10705
10706 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10707 tp->phy_id = hw_phy_id;
10708 if (hw_phy_id_masked == PHY_ID_BCM8002)
10709 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10710 else
10711 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10712 } else {
7d0c41ef
MC		 10713 if (tp->phy_id != PHY_ID_INVALID) {
10714 /* Do nothing, phy ID already set up in
10715 * tg3_get_eeprom_hw_cfg().
10716 */
1da177e4
LT		 10717 } else {
10718 struct subsys_tbl_ent *p;
10719
10720 /* No eeprom signature? Try the hardcoded
10721 * subsys device table.
10722 */
10723 p = lookup_by_subsys(tp);
10724 if (!p)
10725 return -ENODEV;
10726
10727 tp->phy_id = p->phy_id;
10728 if (!tp->phy_id ||
10729 tp->phy_id == PHY_ID_BCM8002)
10730 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10731 }
10732 }
10733
747e8f8b 10734 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 10735 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 10736 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10737 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10738
10739 tg3_readphy(tp, MII_BMSR, &bmsr);
10740 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10741 (bmsr & BMSR_LSTATUS))
10742 goto skip_phy_reset;
6aa20a22 10743
1da177e4
LT		 10744 err = tg3_phy_reset(tp);
10745 if (err)
10746 return err;
10747
10748 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10749 ADVERTISE_100HALF | ADVERTISE_100FULL |
10750 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10751 tg3_ctrl = 0;
10752 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10753 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10754 MII_TG3_CTRL_ADV_1000_FULL);
10755 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10756 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10757 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10758 MII_TG3_CTRL_ENABLE_AS_MASTER);
10759 }
10760
3600d918
MC		 10761 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10762 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10763 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10764 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10765 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10766
10767 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10768 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10769
10770 tg3_writephy(tp, MII_BMCR,
10771 BMCR_ANENABLE | BMCR_ANRESTART);
10772 }
10773 tg3_phy_set_wirespeed(tp);
10774
10775 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10776 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10777 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10778 }
10779
10780skip_phy_reset:
10781 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10782 err = tg3_init_5401phy_dsp(tp);
10783 if (err)
10784 return err;
10785 }
10786
10787 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10788 err = tg3_init_5401phy_dsp(tp);
10789 }
10790
747e8f8b 10791 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10792 tp->link_config.advertising =
10793 (ADVERTISED_1000baseT_Half |
10794 ADVERTISED_1000baseT_Full |
10795 ADVERTISED_Autoneg |
10796 ADVERTISED_FIBRE);
10797 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10798 tp->link_config.advertising &=
10799 ~(ADVERTISED_1000baseT_Half |
10800 ADVERTISED_1000baseT_Full);
10801
10802 return err;
10803}
10804
10805static void __devinit tg3_read_partno(struct tg3 *tp)
10806{
10807 unsigned char vpd_data[256];
af2c6a4a 10808 unsigned int i;
1b27777a 10809 u32 magic;
1da177e4 10810
1820180b 10811 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10812 goto out_not_found;
1da177e4 10813
1820180b 10814 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10815 for (i = 0; i < 256; i += 4) {
10816 u32 tmp;
1da177e4 10817
1b27777a
MC		 10818 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10819 goto out_not_found;
10820
10821 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10822 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10823 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10824 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10825 }
10826 } else {
10827 int vpd_cap;
10828
10829 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10830 for (i = 0; i < 256; i += 4) {
10831 u32 tmp, j = 0;
10832 u16 tmp16;
10833
10834 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10835 i);
10836 while (j++ < 100) {
10837 pci_read_config_word(tp->pdev, vpd_cap +
10838 PCI_VPD_ADDR, &tmp16);
10839 if (tmp16 & 0x8000)
10840 break;
10841 msleep(1);
10842 }
f49639e6
DM		 10843 if (!(tmp16 & 0x8000))
10844 goto out_not_found;
10845
1b27777a
MC		 10846 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10847 &tmp);
10848 tmp = cpu_to_le32(tmp);
10849 memcpy(&vpd_data[i], &tmp, 4);
10850 }
1da177e4
LT		 10851 }
10852
10853 /* Now parse and find the part number. */
af2c6a4a 10854 for (i = 0; i < 254; ) {
1da177e4 10855 unsigned char val = vpd_data[i];
af2c6a4a 10856 unsigned int block_end;
1da177e4
LT		 10857
10858 if (val == 0x82 || val == 0x91) {
10859 i = (i + 3 +
10860 (vpd_data[i + 1] +
10861 (vpd_data[i + 2] << 8)));
10862 continue;
10863 }
10864
10865 if (val != 0x90)
10866 goto out_not_found;
10867
10868 block_end = (i + 3 +
10869 (vpd_data[i + 1] +
10870 (vpd_data[i + 2] << 8)));
10871 i += 3;
af2c6a4a
MC		 10872
10873 if (block_end > 256)
10874 goto out_not_found;
10875
10876 while (i < (block_end - 2)) {
1da177e4
LT		 10877 if (vpd_data[i + 0] == 'P' &&
10878 vpd_data[i + 1] == 'N') {
10879 int partno_len = vpd_data[i + 2];
10880
af2c6a4a
MC		 10881 i += 3;
10882 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10883 goto out_not_found;
10884
10885 memcpy(tp->board_part_number,
af2c6a4a 10886 &vpd_data[i], partno_len);
1da177e4
LT		 10887
10888 /* Success. */
10889 return;
10890 }
af2c6a4a 10891 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10892 }
10893
10894 /* Part number not found. */
10895 goto out_not_found;
10896 }
10897
10898out_not_found:
b5d3772c
MC		 10899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10900 strcpy(tp->board_part_number, "BCM95906");
10901 else
10902 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10903}
10904
9c8a620e
MC		 10905static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
10906{
10907 u32 val;
10908
10909 if (tg3_nvram_read_swab(tp, offset, &val) ||
10910 (val & 0xfc000000) != 0x0c000000 ||
10911 tg3_nvram_read_swab(tp, offset + 4, &val) ||
10912 val != 0)
10913 return 0;
10914
10915 return 1;
10916}
10917
c4e6575c
MC		 10918static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10919{
10920 u32 val, offset, start;
9c8a620e
MC		 10921 u32 ver_offset;
10922 int i, bcnt;
c4e6575c
MC		 10923
10924 if (tg3_nvram_read_swab(tp, 0, &val))
10925 return;
10926
10927 if (val != TG3_EEPROM_MAGIC)
10928 return;
10929
10930 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10931 tg3_nvram_read_swab(tp, 0x4, &start))
10932 return;
10933
10934 offset = tg3_nvram_logical_addr(tp, offset);
9c8a620e
MC		 10935
10936 if (!tg3_fw_img_is_valid(tp, offset) ||
10937 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
c4e6575c
MC		 10938 return;
10939
9c8a620e
MC		 10940 offset = offset + ver_offset - start;
10941 for (i = 0; i < 16; i += 4) {
10942 if (tg3_nvram_read(tp, offset + i, &val))
10943 return;
10944
10945 val = le32_to_cpu(val);
10946 memcpy(tp->fw_ver + i, &val, 4);
10947 }
c4e6575c 10948
9c8a620e 10949 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
84af67fd 10950 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
9c8a620e
MC		 10951 return;
10952
10953 for (offset = TG3_NVM_DIR_START;
10954 offset < TG3_NVM_DIR_END;
10955 offset += TG3_NVM_DIRENT_SIZE) {
10956 if (tg3_nvram_read_swab(tp, offset, &val))
c4e6575c
MC		 10957 return;
10958
9c8a620e
MC		 10959 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
10960 break;
10961 }
10962
10963 if (offset == TG3_NVM_DIR_END)
10964 return;
10965
10966 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10967 start = 0x08000000;
10968 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
10969 return;
10970
10971 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
10972 !tg3_fw_img_is_valid(tp, offset) ||
10973 tg3_nvram_read_swab(tp, offset + 8, &val))
10974 return;
10975
10976 offset += val - start;
10977
10978 bcnt = strlen(tp->fw_ver);
10979
10980 tp->fw_ver[bcnt++] = ',';
10981 tp->fw_ver[bcnt++] = ' ';
10982
10983 for (i = 0; i < 4; i++) {
10984 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 10985 return;
10986
9c8a620e
MC		 10987 val = le32_to_cpu(val);
10988 offset += sizeof(val);
c4e6575c 10989
9c8a620e
MC		 10990 if (bcnt > TG3_VER_SIZE - sizeof(val)) {
10991 memcpy(&tp->fw_ver[bcnt], &val, TG3_VER_SIZE - bcnt);
10992 break;
c4e6575c 10993 }
9c8a620e
MC		 10994
10995 memcpy(&tp->fw_ver[bcnt], &val, sizeof(val));
10996 bcnt += sizeof(val);
c4e6575c 10997 }
9c8a620e
MC		 10998
10999 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11000}
11001
7544b097
MC		 11002static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11003
1da177e4
LT		 11004static int __devinit tg3_get_invariants(struct tg3 *tp)
11005{
11006 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11007 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11008 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11009 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11010 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11011 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11012 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11013 { },
11014 };
11015 u32 misc_ctrl_reg;
11016 u32 cacheline_sz_reg;
11017 u32 pci_state_reg, grc_misc_cfg;
11018 u32 val;
11019 u16 pci_cmd;
c7835a77 11020 int err, pcie_cap;
1da177e4 11021
1da177e4
LT		 11022 /* Force memory write invalidate off. If we leave it on,
11023 * then on 5700_BX chips we have to enable a workaround.
11024 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11025 * to match the cacheline size. The Broadcom driver have this
11026 * workaround but turns MWI off all the times so never uses
11027 * it. This seems to suggest that the workaround is insufficient.
11028 */
11029 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11030 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11031 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11032
11033 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11034 * has the register indirect write enable bit set before
11035 * we try to access any of the MMIO registers. It is also
11036 * critical that the PCI-X hw workaround situation is decided
11037 * before that as well.
11038 */
11039 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11040 &misc_ctrl_reg);
11041
11042 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11043 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11045 u32 prod_id_asic_rev;
11046
11047 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11048 &prod_id_asic_rev);
11049 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11050 }
1da177e4 11051
ff645bec
MC		 11052 /* Wrong chip ID in 5752 A0. This code can be removed later
11053 * as A0 is not in production.
11054 */
11055 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11056 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11057
6892914f
MC		 11058 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11059 * we need to disable memory and use config. cycles
11060 * only to access all registers. The 5702/03 chips
11061 * can mistakenly decode the special cycles from the
11062 * ICH chipsets as memory write cycles, causing corruption
11063 * of register and memory space. Only certain ICH bridges
11064 * will drive special cycles with non-zero data during the
11065 * address phase which can fall within the 5703's address
11066 * range. This is not an ICH bug as the PCI spec allows
11067 * non-zero address during special cycles. However, only
11068 * these ICH bridges are known to drive non-zero addresses
11069 * during special cycles.
11070 *
11071 * Since special cycles do not cross PCI bridges, we only
11072 * enable this workaround if the 5703 is on the secondary
11073 * bus of these ICH bridges.
11074 */
11075 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11076 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11077 static struct tg3_dev_id {
11078 u32 vendor;
11079 u32 device;
11080 u32 rev;
11081 } ich_chipsets[] = {
11082 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11083 PCI_ANY_ID },
11084 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11085 PCI_ANY_ID },
11086 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11087 0xa },
11088 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11089 PCI_ANY_ID },
11090 { },
11091 };
11092 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11093 struct pci_dev *bridge = NULL;
11094
11095 while (pci_id->vendor != 0) {
11096 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11097 bridge);
11098 if (!bridge) {
11099 pci_id++;
11100 continue;
11101 }
11102 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11103 if (bridge->revision > pci_id->rev)
6892914f
MC		 11104 continue;
11105 }
11106 if (bridge->subordinate &&
11107 (bridge->subordinate->number ==
11108 tp->pdev->bus->number)) {
11109
11110 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11111 pci_dev_put(bridge);
11112 break;
11113 }
11114 }
11115 }
11116
4a29cc2e
MC		 11117 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11118 * DMA addresses > 40-bit. This bridge may have other additional
11119 * 57xx devices behind it in some 4-port NIC designs for example.
11120 * Any tg3 device found behind the bridge will also need the 40-bit
11121 * DMA workaround.
11122 */
a4e2b347
MC		 11123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11125 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11126 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11127 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11128 }
4a29cc2e
MC		 11129 else {
11130 struct pci_dev *bridge = NULL;
11131
11132 do {
11133 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11134 PCI_DEVICE_ID_SERVERWORKS_EPB,
11135 bridge);
11136 if (bridge && bridge->subordinate &&
11137 (bridge->subordinate->number <=
11138 tp->pdev->bus->number) &&
11139 (bridge->subordinate->subordinate >=
11140 tp->pdev->bus->number)) {
11141 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11142 pci_dev_put(bridge);
11143 break;
11144 }
11145 } while (bridge);
11146 }
4cf78e4f 11147
1da177e4
LT		 11148 /* Initialize misc host control in PCI block. */
11149 tp->misc_host_ctrl |= (misc_ctrl_reg &
11150 MISC_HOST_CTRL_CHIPREV);
11151 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11152 tp->misc_host_ctrl);
11153
11154 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11155 &cacheline_sz_reg);
11156
11157 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
11158 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
11159 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
11160 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
11161
7544b097
MC		 11162 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11163 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11164 tp->pdev_peer = tg3_find_peer(tp);
11165
6708e5cc 11166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 11167 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 11168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 11173 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11174 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11175
1b440c56
JL		 11176 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11177 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11178 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11179
5a6f3074 11180 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11181 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11182 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11183 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11184 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11185 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11186 tp->pdev_peer == tp->pdev))
11187 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11188
af36e6b6 11189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c 11190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11193 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11194 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11195 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11196 } else {
7f62ad5d 11197 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11198 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11199 ASIC_REV_5750 &&
11200 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11201 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11202 }
5a6f3074 11203 }
1da177e4 11204
0f893dc6
MC		 11205 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
11206 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 11207 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 11208 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c 11209 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
d30cdd28 11210 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
9936bcf6 11211 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
b5d3772c 11212 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 11213 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11214
c7835a77
MC		 11215 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11216 if (pcie_cap != 0) {
1da177e4 11217 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 11218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11219 u16 lnkctl;
11220
11221 pci_read_config_word(tp->pdev,
11222 pcie_cap + PCI_EXP_LNKCTL,
11223 &lnkctl);
11224 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11225 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11226 }
11227 }
1da177e4 11228
399de50b
MC		 11229 /* If we have an AMD 762 or VIA K8T800 chipset, write
11230 * reordering to the mailbox registers done by the host
11231 * controller can cause major troubles. We read back from
11232 * every mailbox register write to force the writes to be
11233 * posted to the chip in order.
11234 */
11235 if (pci_dev_present(write_reorder_chipsets) &&
11236 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11237 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11238
1da177e4
LT		 11239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11240 tp->pci_lat_timer < 64) {
11241 tp->pci_lat_timer = 64;
11242
11243 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
11244 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
11245 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
11246 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
11247
11248 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11249 cacheline_sz_reg);
11250 }
11251
9974a356
MC		 11252 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11253 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11254 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11255 if (!tp->pcix_cap) {
11256 printk(KERN_ERR PFX "Cannot find PCI-X "
11257 "capability, aborting.\n");
11258 return -EIO;
11259 }
11260 }
11261
1da177e4
LT		 11262 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11263 &pci_state_reg);
11264
9974a356 11265 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
1da177e4
LT		 11266 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11267
11268 /* If this is a 5700 BX chipset, and we are in PCI-X
11269 * mode, enable register write workaround.
11270 *
11271 * The workaround is to use indirect register accesses
11272 * for all chip writes not to mailbox registers.
11273 */
11274 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11275 u32 pm_reg;
1da177e4
LT		 11276
11277 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11278
11279 /* The chip can have it's power management PCI config
11280 * space registers clobbered due to this bug.
11281 * So explicitly force the chip into D0 here.
11282 */
9974a356
MC		 11283 pci_read_config_dword(tp->pdev,
11284 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11285 &pm_reg);
11286 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11287 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 11288 pci_write_config_dword(tp->pdev,
11289 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11290 pm_reg);
11291
11292 /* Also, force SERR#/PERR# in PCI command. */
11293 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11294 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11295 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11296 }
11297 }
11298
087fe256
MC		 11299 /* 5700 BX chips need to have their TX producer index mailboxes
11300 * written twice to workaround a bug.
11301 */
11302 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
11303 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11304
1da177e4
LT		 11305 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11306 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11307 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11308 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11309
11310 /* Chip-specific fixup from Broadcom driver */
11311 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11312 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11313 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11314 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11315 }
11316
1ee582d8 11317 /* Default fast path register access methods */
20094930 11318 tp->read32 = tg3_read32;
1ee582d8 11319 tp->write32 = tg3_write32;
09ee929c 11320 tp->read32_mbox = tg3_read32;
20094930 11321 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 11322 tp->write32_tx_mbox = tg3_write32;
11323 tp->write32_rx_mbox = tg3_write32;
11324
11325 /* Various workaround register access methods */
11326 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11327 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 11328 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11329 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11330 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11331 /*
11332 * Back to back register writes can cause problems on these
11333 * chips, the workaround is to read back all reg writes
11334 * except those to mailbox regs.
11335 *
11336 * See tg3_write_indirect_reg32().
11337 */
1ee582d8 11338 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 11339 }
11340
1ee582d8
MC		 11341
11342 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11343 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11344 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11345 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11346 tp->write32_rx_mbox = tg3_write_flush_reg32;
11347 }
20094930 11348
6892914f
MC		 11349 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11350 tp->read32 = tg3_read_indirect_reg32;
11351 tp->write32 = tg3_write_indirect_reg32;
11352 tp->read32_mbox = tg3_read_indirect_mbox;
11353 tp->write32_mbox = tg3_write_indirect_mbox;
11354 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11355 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11356
11357 iounmap(tp->regs);
22abe310 11358 tp->regs = NULL;
6892914f
MC		 11359
11360 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11361 pci_cmd &= ~PCI_COMMAND_MEMORY;
11362 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11363 }
b5d3772c
MC		 11364 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11365 tp->read32_mbox = tg3_read32_mbox_5906;
11366 tp->write32_mbox = tg3_write32_mbox_5906;
11367 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11368 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11369 }
6892914f 11370
bbadf503
MC		 11371 if (tp->write32 == tg3_write_indirect_reg32 ||
11372 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11373 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 11374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 11375 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11376
7d0c41ef 11377 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 11378 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 11379 * determined before calling tg3_set_power_state() so that
11380 * we know whether or not to switch out of Vaux power.
11381 * When the flag is set, it means that GPIO1 is used for eeprom
11382 * write protect and also implies that it is a LOM where GPIOs
11383 * are not used to switch power.
6aa20a22 11384 */
7d0c41ef
MC		 11385 tg3_get_eeprom_hw_cfg(tp);
11386
0d3031d9
MC		 11387 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11388 /* Allow reads and writes to the
11389 * APE register and memory space.
11390 */
11391 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11392 PCISTATE_ALLOW_APE_SHMEM_WR;
11393 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11394 pci_state_reg);
11395 }
11396
9936bcf6
MC		 11397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d30cdd28
MC		 11399 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11400
314fba34
MC		 11401 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11402 * GPIO1 driven high will bring 5700's external PHY out of reset.
11403 * It is also used as eeprom write protect on LOMs.
11404 */
11405 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11406 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11407 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11408 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11409 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 11410 /* Unused GPIO3 must be driven as output on 5752 because there
11411 * are no pull-up resistors on unused GPIO pins.
11412 */
11413 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11414 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 11415
af36e6b6
MC		 11416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11417 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11418
1da177e4 11419 /* Force the chip into D0. */
bc1c7567 11420 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 11421 if (err) {
11422 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11423 pci_name(tp->pdev));
11424 return err;
11425 }
11426
11427 /* 5700 B0 chips do not support checksumming correctly due
11428 * to hardware bugs.
11429 */
11430 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11431 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11432
1da177e4
LT		 11433 /* Derive initial jumbo mode from MTU assigned in
11434 * ether_setup() via the alloc_etherdev() call
11435 */
0f893dc6 11436 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 11437 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 11438 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 11439
11440 /* Determine WakeOnLan speed to use. */
11441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11442 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11443 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11444 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11445 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11446 } else {
11447 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11448 }
11449
11450 /* A few boards don't want Ethernet@WireSpeed phy feature */
11451 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11452 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11453 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 11454 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 11455 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 11456 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 11457 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11458
11459 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
11460 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
11461 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
11462 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
11463 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
11464
c424cb24
MC		 11465 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 11467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 11468 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11469 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 11470 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
11471 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
11472 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 11473 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11474 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11475 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 11476 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11477 }
1da177e4 11478
1da177e4 11479 tp->coalesce_mode = 0;
1da177e4
LT		 11480 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
11481 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11482 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11483
11484 /* Initialize MAC MI mode, polling disabled. */
11485 tw32_f(MAC_MI_MODE, tp->mi_mode);
11486 udelay(80);
11487
11488 /* Initialize data/descriptor byte/word swapping. */
11489 val = tr32(GRC_MODE);
11490 val &= GRC_MODE_HOST_STACKUP;
11491 tw32(GRC_MODE, val | tp->grc_mode);
11492
11493 tg3_switch_clocks(tp);
11494
11495 /* Clear this out for sanity. */
11496 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11497
11498 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11499 &pci_state_reg);
11500 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
11501 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
11502 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
11503
11504 if (chiprevid == CHIPREV_ID_5701_A0 ||
11505 chiprevid == CHIPREV_ID_5701_B0 ||
11506 chiprevid == CHIPREV_ID_5701_B2 ||
11507 chiprevid == CHIPREV_ID_5701_B5) {
11508 void __iomem *sram_base;
11509
11510 /* Write some dummy words into the SRAM status block
11511 * area, see if it reads back correctly. If the return
11512 * value is bad, force enable the PCIX workaround.
11513 */
11514 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
11515
11516 writel(0x00000000, sram_base);
11517 writel(0x00000000, sram_base + 4);
11518 writel(0xffffffff, sram_base + 4);
11519 if (readl(sram_base) != 0x00000000)
11520 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11521 }
11522 }
11523
11524 udelay(50);
11525 tg3_nvram_init(tp);
11526
11527 grc_misc_cfg = tr32(GRC_MISC_CFG);
11528 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
11529
1da177e4
LT		 11530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11531 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
11532 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
11533 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
11534
fac9b83e
DM		 11535 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
11536 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
11537 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
11538 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
11539 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
11540 HOSTCC_MODE_CLRTICK_TXBD);
11541
11542 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11544 tp->misc_host_ctrl);
11545 }
11546
1da177e4
LT		 11547 /* these are limited to 10/100 only */
11548 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11549 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11550 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11551 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11552 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11553 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11554 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11555 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11556 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 11557 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11558 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 11559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 11560 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11561
11562 err = tg3_phy_probe(tp);
11563 if (err) {
11564 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11565 pci_name(tp->pdev), err);
11566 /* ... but do not return immediately ... */
11567 }
11568
11569 tg3_read_partno(tp);
c4e6575c 11570 tg3_read_fw_ver(tp);
1da177e4
LT		 11571
11572 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11573 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11574 } else {
11575 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11576 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11577 else
11578 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11579 }
11580
11581 /* 5700 {AX,BX} chips have a broken status block link
11582 * change bit implementation, so we must use the
11583 * status register in those cases.
11584 */
11585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11586 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11587 else
11588 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11589
11590 /* The led_ctrl is set during tg3_phy_probe, here we might
11591 * have to force the link status polling mechanism based
11592 * upon subsystem IDs.
11593 */
11594 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 11595 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 11596 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11597 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11598 TG3_FLAG_USE_LINKCHG_REG);
11599 }
11600
11601 /* For all SERDES we poll the MAC status register. */
11602 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11603 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11604 else
11605 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11606
5a6f3074 11607 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 11608 * straddle the 4GB address boundary in some cases.
11609 */
af36e6b6 11610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c 11611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11614 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 11615 tp->dev->hard_start_xmit = tg3_start_xmit;
11616 else
11617 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 11618
11619 tp->rx_offset = 2;
11620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11621 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11622 tp->rx_offset = 0;
11623
f92905de
MC		 11624 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11625
11626 /* Increment the rx prod index on the rx std ring by at most
11627 * 8 for these chips to workaround hw errata.
11628 */
11629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11632 tp->rx_std_max_post = 8;
11633
8ed5d97e
MC		 11634 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11635 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11636 PCIE_PWR_MGMT_L1_THRESH_MSK;
11637
1da177e4
LT		 11638 return err;
11639}
11640
49b6e95f 11641#ifdef CONFIG_SPARC
1da177e4
LT		 11642static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11643{
11644 struct net_device *dev = tp->dev;
11645 struct pci_dev *pdev = tp->pdev;
49b6e95f 11646 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 11647 const unsigned char *addr;
49b6e95f
DM		 11648 int len;
11649
11650 addr = of_get_property(dp, "local-mac-address", &len);
11651 if (addr && len == 6) {
11652 memcpy(dev->dev_addr, addr, 6);
11653 memcpy(dev->perm_addr, dev->dev_addr, 6);
11654 return 0;
1da177e4
LT		 11655 }
11656 return -ENODEV;
11657}
11658
11659static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11660{
11661 struct net_device *dev = tp->dev;
11662
11663 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 11664 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 11665 return 0;
11666}
11667#endif
11668
11669static int __devinit tg3_get_device_address(struct tg3 *tp)
11670{
11671 struct net_device *dev = tp->dev;
11672 u32 hi, lo, mac_offset;
008652b3 11673 int addr_ok = 0;
1da177e4 11674
49b6e95f 11675#ifdef CONFIG_SPARC
1da177e4
LT		 11676 if (!tg3_get_macaddr_sparc(tp))
11677 return 0;
11678#endif
11679
11680 mac_offset = 0x7c;
f49639e6 11681 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11682 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11683 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11684 mac_offset = 0xcc;
11685 if (tg3_nvram_lock(tp))
11686 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11687 else
11688 tg3_nvram_unlock(tp);
11689 }
b5d3772c
MC		 11690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11691 mac_offset = 0x10;
1da177e4
LT		 11692
11693 /* First try to get it from MAC address mailbox. */
11694 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11695 if ((hi >> 16) == 0x484b) {
11696 dev->dev_addr[0] = (hi >> 8) & 0xff;
11697 dev->dev_addr[1] = (hi >> 0) & 0xff;
11698
11699 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11700 dev->dev_addr[2] = (lo >> 24) & 0xff;
11701 dev->dev_addr[3] = (lo >> 16) & 0xff;
11702 dev->dev_addr[4] = (lo >> 8) & 0xff;
11703 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11704
008652b3
MC		 11705 /* Some old bootcode may report a 0 MAC address in SRAM */
11706 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11707 }
11708 if (!addr_ok) {
11709 /* Next, try NVRAM. */
f49639e6 11710 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11711 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11712 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11713 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11714 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11715 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11716 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11717 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11718 }
11719 /* Finally just fetch it out of the MAC control regs. */
11720 else {
11721 hi = tr32(MAC_ADDR_0_HIGH);
11722 lo = tr32(MAC_ADDR_0_LOW);
11723
11724 dev->dev_addr[5] = lo & 0xff;
11725 dev->dev_addr[4] = (lo >> 8) & 0xff;
11726 dev->dev_addr[3] = (lo >> 16) & 0xff;
11727 dev->dev_addr[2] = (lo >> 24) & 0xff;
11728 dev->dev_addr[1] = hi & 0xff;
11729 dev->dev_addr[0] = (hi >> 8) & 0xff;
11730 }
1da177e4
LT		 11731 }
11732
11733 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11734#ifdef CONFIG_SPARC64
11735 if (!tg3_get_default_macaddr_sparc(tp))
11736 return 0;
11737#endif
11738 return -EINVAL;
11739 }
2ff43697 11740 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11741 return 0;
11742}
11743
59e6b434
DM		 11744#define BOUNDARY_SINGLE_CACHELINE 1
11745#define BOUNDARY_MULTI_CACHELINE 2
11746
11747static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11748{
11749 int cacheline_size;
11750 u8 byte;
11751 int goal;
11752
11753 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11754 if (byte == 0)
11755 cacheline_size = 1024;
11756 else
11757 cacheline_size = (int) byte * 4;
11758
11759 /* On 5703 and later chips, the boundary bits have no
11760 * effect.
11761 */
11762 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11763 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11764 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11765 goto out;
11766
11767#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11768 goal = BOUNDARY_MULTI_CACHELINE;
11769#else
11770#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11771 goal = BOUNDARY_SINGLE_CACHELINE;
11772#else
11773 goal = 0;
11774#endif
11775#endif
11776
11777 if (!goal)
11778 goto out;
11779
11780 /* PCI controllers on most RISC systems tend to disconnect
11781 * when a device tries to burst across a cache-line boundary.
11782 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11783 *
11784 * Unfortunately, for PCI-E there are only limited
11785 * write-side controls for this, and thus for reads
11786 * we will still get the disconnects. We'll also waste
11787 * these PCI cycles for both read and write for chips
11788 * other than 5700 and 5701 which do not implement the
11789 * boundary bits.
11790 */
11791 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11792 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11793 switch (cacheline_size) {
11794 case 16:
11795 case 32:
11796 case 64:
11797 case 128:
11798 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11799 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11800 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11801 } else {
11802 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11803 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11804 }
11805 break;
11806
11807 case 256:
11808 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11809 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11810 break;
11811
11812 default:
11813 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11814 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11815 break;
11816 };
11817 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11818 switch (cacheline_size) {
11819 case 16:
11820 case 32:
11821 case 64:
11822 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11823 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11824 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11825 break;
11826 }
11827 /* fallthrough */
11828 case 128:
11829 default:
11830 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11831 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11832 break;
11833 };
11834 } else {
11835 switch (cacheline_size) {
11836 case 16:
11837 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11838 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11839 DMA_RWCTRL_WRITE_BNDRY_16);
11840 break;
11841 }
11842 /* fallthrough */
11843 case 32:
11844 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11845 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11846 DMA_RWCTRL_WRITE_BNDRY_32);
11847 break;
11848 }
11849 /* fallthrough */
11850 case 64:
11851 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11852 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11853 DMA_RWCTRL_WRITE_BNDRY_64);
11854 break;
11855 }
11856 /* fallthrough */
11857 case 128:
11858 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11859 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11860 DMA_RWCTRL_WRITE_BNDRY_128);
11861 break;
11862 }
11863 /* fallthrough */
11864 case 256:
11865 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11866 DMA_RWCTRL_WRITE_BNDRY_256);
11867 break;
11868 case 512:
11869 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11870 DMA_RWCTRL_WRITE_BNDRY_512);
11871 break;
11872 case 1024:
11873 default:
11874 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11875 DMA_RWCTRL_WRITE_BNDRY_1024);
11876 break;
11877 };
11878 }
11879
11880out:
11881 return val;
11882}
11883
1da177e4
LT		 11884static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11885{
11886 struct tg3_internal_buffer_desc test_desc;
11887 u32 sram_dma_descs;
11888 int i, ret;
11889
11890 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11891
11892 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11893 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11894 tw32(RDMAC_STATUS, 0);
11895 tw32(WDMAC_STATUS, 0);
11896
11897 tw32(BUFMGR_MODE, 0);
11898 tw32(FTQ_RESET, 0);
11899
11900 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11901 test_desc.addr_lo = buf_dma & 0xffffffff;
11902 test_desc.nic_mbuf = 0x00002100;
11903 test_desc.len = size;
11904
11905 /*
11906 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11907 * the *second* time the tg3 driver was getting loaded after an
11908 * initial scan.
11909 *
11910 * Broadcom tells me:
11911 * ...the DMA engine is connected to the GRC block and a DMA
11912 * reset may affect the GRC block in some unpredictable way...
11913 * The behavior of resets to individual blocks has not been tested.
11914 *
11915 * Broadcom noted the GRC reset will also reset all sub-components.
11916 */
11917 if (to_device) {
11918 test_desc.cqid_sqid = (13 << 8) | 2;
11919
11920 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11921 udelay(40);
11922 } else {
11923 test_desc.cqid_sqid = (16 << 8) | 7;
11924
11925 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11926 udelay(40);
11927 }
11928 test_desc.flags = 0x00000005;
11929
11930 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11931 u32 val;
11932
11933 val = *(((u32 *)&test_desc) + i);
11934 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11935 sram_dma_descs + (i * sizeof(u32)));
11936 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11937 }
11938 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11939
11940 if (to_device) {
11941 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11942 } else {
11943 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11944 }
11945
11946 ret = -ENODEV;
11947 for (i = 0; i < 40; i++) {
11948 u32 val;
11949
11950 if (to_device)
11951 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11952 else
11953 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11954 if ((val & 0xffff) == sram_dma_descs) {
11955 ret = 0;
11956 break;
11957 }
11958
11959 udelay(100);
11960 }
11961
11962 return ret;
11963}
11964
ded7340d 11965#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11966
11967static int __devinit tg3_test_dma(struct tg3 *tp)
11968{
11969 dma_addr_t buf_dma;
59e6b434 11970 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11971 int ret;
11972
11973 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11974 if (!buf) {
11975 ret = -ENOMEM;
11976 goto out_nofree;
11977 }
11978
11979 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11980 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11981
59e6b434 11982 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11983
11984 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11985 /* DMA read watermark not used on PCIE */
11986 tp->dma_rwctrl |= 0x00180000;
11987 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11988 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11990 tp->dma_rwctrl |= 0x003f0000;
11991 else
11992 tp->dma_rwctrl |= 0x003f000f;
11993 } else {
11994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11996 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11997 u32 read_water = 0x7;
1da177e4 11998
4a29cc2e
MC		 11999 /* If the 5704 is behind the EPB bridge, we can
12000 * do the less restrictive ONE_DMA workaround for
12001 * better performance.
12002 */
12003 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12004 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12005 tp->dma_rwctrl |= 0x8000;
12006 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12007 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12008
49afdeb6
MC		 12009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12010 read_water = 4;
59e6b434 12011 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12012 tp->dma_rwctrl |=
12013 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12014 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12015 (1 << 23);
4cf78e4f
MC		 12016 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12017 /* 5780 always in PCIX mode */
12018 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12019 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12020 /* 5714 always in PCIX mode */
12021 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12022 } else {
12023 tp->dma_rwctrl |= 0x001b000f;
12024 }
12025 }
12026
12027 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12029 tp->dma_rwctrl &= 0xfffffff0;
12030
12031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12033 /* Remove this if it causes problems for some boards. */
12034 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12035
12036 /* On 5700/5701 chips, we need to set this bit.
12037 * Otherwise the chip will issue cacheline transactions
12038 * to streamable DMA memory with not all the byte
12039 * enables turned on. This is an error on several
12040 * RISC PCI controllers, in particular sparc64.
12041 *
12042 * On 5703/5704 chips, this bit has been reassigned
12043 * a different meaning. In particular, it is used
12044 * on those chips to enable a PCI-X workaround.
12045 */
12046 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12047 }
12048
12049 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12050
12051#if 0
12052 /* Unneeded, already done by tg3_get_invariants. */
12053 tg3_switch_clocks(tp);
12054#endif
12055
12056 ret = 0;
12057 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12058 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12059 goto out;
12060
59e6b434
DM		 12061 /* It is best to perform DMA test with maximum write burst size
12062 * to expose the 5700/5701 write DMA bug.
12063 */
12064 saved_dma_rwctrl = tp->dma_rwctrl;
12065 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12066 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12067
1da177e4
LT		 12068 while (1) {
12069 u32 *p = buf, i;
12070
12071 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12072 p[i] = i;
12073
12074 /* Send the buffer to the chip. */
12075 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12076 if (ret) {
12077 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12078 break;
12079 }
12080
12081#if 0
12082 /* validate data reached card RAM correctly. */
12083 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12084 u32 val;
12085 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12086 if (le32_to_cpu(val) != p[i]) {
12087 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12088 /* ret = -ENODEV here? */
12089 }
12090 p[i] = 0;
12091 }
12092#endif
12093 /* Now read it back. */
12094 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12095 if (ret) {
12096 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12097
12098 break;
12099 }
12100
12101 /* Verify it. */
12102 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12103 if (p[i] == i)
12104 continue;
12105
59e6b434
DM		 12106 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12107 DMA_RWCTRL_WRITE_BNDRY_16) {
12108 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12109 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12110 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12111 break;
12112 } else {
12113 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12114 ret = -ENODEV;
12115 goto out;
12116 }
12117 }
12118
12119 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12120 /* Success. */
12121 ret = 0;
12122 break;
12123 }
12124 }
59e6b434
DM		 12125 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12126 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12127 static struct pci_device_id dma_wait_state_chipsets[] = {
12128 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12129 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12130 { },
12131 };
12132
59e6b434 12133 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12134 * now look for chipsets that are known to expose the
12135 * DMA bug without failing the test.
59e6b434 12136 */
6d1cfbab
MC		 12137 if (pci_dev_present(dma_wait_state_chipsets)) {
12138 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12139 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12140 }
12141 else
12142 /* Safe to use the calculated DMA boundary. */
12143 tp->dma_rwctrl = saved_dma_rwctrl;
12144
59e6b434
DM		 12145 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12146 }
1da177e4
LT		 12147
12148out:
12149 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12150out_nofree:
12151 return ret;
12152}
12153
12154static void __devinit tg3_init_link_config(struct tg3 *tp)
12155{
12156 tp->link_config.advertising =
12157 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12158 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12159 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12160 ADVERTISED_Autoneg | ADVERTISED_MII);
12161 tp->link_config.speed = SPEED_INVALID;
12162 tp->link_config.duplex = DUPLEX_INVALID;
12163 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12164 tp->link_config.active_speed = SPEED_INVALID;
12165 tp->link_config.active_duplex = DUPLEX_INVALID;
12166 tp->link_config.phy_is_low_power = 0;
12167 tp->link_config.orig_speed = SPEED_INVALID;
12168 tp->link_config.orig_duplex = DUPLEX_INVALID;
12169 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12170}
12171
12172static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12173{
fdfec172
MC		 12174 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12175 tp->bufmgr_config.mbuf_read_dma_low_water =
12176 DEFAULT_MB_RDMA_LOW_WATER_5705;
12177 tp->bufmgr_config.mbuf_mac_rx_low_water =
12178 DEFAULT_MB_MACRX_LOW_WATER_5705;
12179 tp->bufmgr_config.mbuf_high_water =
12180 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12182 tp->bufmgr_config.mbuf_mac_rx_low_water =
12183 DEFAULT_MB_MACRX_LOW_WATER_5906;
12184 tp->bufmgr_config.mbuf_high_water =
12185 DEFAULT_MB_HIGH_WATER_5906;
12186 }
fdfec172
MC		 12187
12188 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12189 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12190 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12191 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12192 tp->bufmgr_config.mbuf_high_water_jumbo =
12193 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12194 } else {
12195 tp->bufmgr_config.mbuf_read_dma_low_water =
12196 DEFAULT_MB_RDMA_LOW_WATER;
12197 tp->bufmgr_config.mbuf_mac_rx_low_water =
12198 DEFAULT_MB_MACRX_LOW_WATER;
12199 tp->bufmgr_config.mbuf_high_water =
12200 DEFAULT_MB_HIGH_WATER;
12201
12202 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12203 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12204 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12205 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12206 tp->bufmgr_config.mbuf_high_water_jumbo =
12207 DEFAULT_MB_HIGH_WATER_JUMBO;
12208 }
1da177e4
LT		 12209
12210 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12211 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12212}
12213
12214static char * __devinit tg3_phy_string(struct tg3 *tp)
12215{
12216 switch (tp->phy_id & PHY_ID_MASK) {
12217 case PHY_ID_BCM5400: return "5400";
12218 case PHY_ID_BCM5401: return "5401";
12219 case PHY_ID_BCM5411: return "5411";
12220 case PHY_ID_BCM5701: return "5701";
12221 case PHY_ID_BCM5703: return "5703";
12222 case PHY_ID_BCM5704: return "5704";
12223 case PHY_ID_BCM5705: return "5705";
12224 case PHY_ID_BCM5750: return "5750";
85e94ced 12225 case PHY_ID_BCM5752: return "5752";
a4e2b347 12226 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12227 case PHY_ID_BCM5780: return "5780";
af36e6b6 12228 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12229 case PHY_ID_BCM5787: return "5787";
d30cdd28 12230 case PHY_ID_BCM5784: return "5784";
126a3368 12231 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12232 case PHY_ID_BCM5906: return "5906";
9936bcf6 12233 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12234 case PHY_ID_BCM8002: return "8002/serdes";
12235 case 0: return "serdes";
12236 default: return "unknown";
12237 };
12238}
12239
f9804ddb
MC		 12240static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12241{
12242 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12243 strcpy(str, "PCI Express");
12244 return str;
12245 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12246 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12247
12248 strcpy(str, "PCIX:");
12249
12250 if ((clock_ctrl == 7) ||
12251 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12252 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12253 strcat(str, "133MHz");
12254 else if (clock_ctrl == 0)
12255 strcat(str, "33MHz");
12256 else if (clock_ctrl == 2)
12257 strcat(str, "50MHz");
12258 else if (clock_ctrl == 4)
12259 strcat(str, "66MHz");
12260 else if (clock_ctrl == 6)
12261 strcat(str, "100MHz");
f9804ddb
MC		 12262 } else {
12263 strcpy(str, "PCI:");
12264 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12265 strcat(str, "66MHz");
12266 else
12267 strcat(str, "33MHz");
12268 }
12269 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12270 strcat(str, ":32-bit");
12271 else
12272 strcat(str, ":64-bit");
12273 return str;
12274}
12275
8c2dc7e1 12276static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 12277{
12278 struct pci_dev *peer;
12279 unsigned int func, devnr = tp->pdev->devfn & ~7;
12280
12281 for (func = 0; func < 8; func++) {
12282 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12283 if (peer && peer != tp->pdev)
12284 break;
12285 pci_dev_put(peer);
12286 }
16fe9d74
MC		 12287 /* 5704 can be configured in single-port mode, set peer to
12288 * tp->pdev in that case.
12289 */
12290 if (!peer) {
12291 peer = tp->pdev;
12292 return peer;
12293 }
1da177e4
LT		 12294
12295 /*
12296 * We don't need to keep the refcount elevated; there's no way
12297 * to remove one half of this device without removing the other
12298 */
12299 pci_dev_put(peer);
12300
12301 return peer;
12302}
12303
15f9850d
DM		 12304static void __devinit tg3_init_coal(struct tg3 *tp)
12305{
12306 struct ethtool_coalesce *ec = &tp->coal;
12307
12308 memset(ec, 0, sizeof(*ec));
12309 ec->cmd = ETHTOOL_GCOALESCE;
12310 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12311 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12312 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12313 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12314 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12315 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12316 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12317 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12318 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12319
12320 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12321 HOSTCC_MODE_CLRTICK_TXBD)) {
12322 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12323 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12324 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12325 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12326 }
d244c892
MC		 12327
12328 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12329 ec->rx_coalesce_usecs_irq = 0;
12330 ec->tx_coalesce_usecs_irq = 0;
12331 ec->stats_block_coalesce_usecs = 0;
12332 }
15f9850d
DM		 12333}
12334
1da177e4
LT		 12335static int __devinit tg3_init_one(struct pci_dev *pdev,
12336 const struct pci_device_id *ent)
12337{
12338 static int tg3_version_printed = 0;
12339 unsigned long tg3reg_base, tg3reg_len;
12340 struct net_device *dev;
12341 struct tg3 *tp;
72f2afb8 12342 int i, err, pm_cap;
f9804ddb 12343 char str[40];
72f2afb8 12344 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 12345
12346 if (tg3_version_printed++ == 0)
12347 printk(KERN_INFO "%s", version);
12348
12349 err = pci_enable_device(pdev);
12350 if (err) {
12351 printk(KERN_ERR PFX "Cannot enable PCI device, "
12352 "aborting.\n");
12353 return err;
12354 }
12355
12356 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12357 printk(KERN_ERR PFX "Cannot find proper PCI device "
12358 "base address, aborting.\n");
12359 err = -ENODEV;
12360 goto err_out_disable_pdev;
12361 }
12362
12363 err = pci_request_regions(pdev, DRV_MODULE_NAME);
12364 if (err) {
12365 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12366 "aborting.\n");
12367 goto err_out_disable_pdev;
12368 }
12369
12370 pci_set_master(pdev);
12371
12372 /* Find power-management capability. */
12373 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12374 if (pm_cap == 0) {
12375 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12376 "aborting.\n");
12377 err = -EIO;
12378 goto err_out_free_res;
12379 }
12380
1da177e4
LT		 12381 tg3reg_base = pci_resource_start(pdev, 0);
12382 tg3reg_len = pci_resource_len(pdev, 0);
12383
12384 dev = alloc_etherdev(sizeof(*tp));
12385 if (!dev) {
12386 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12387 err = -ENOMEM;
12388 goto err_out_free_res;
12389 }
12390
1da177e4
LT		 12391 SET_NETDEV_DEV(dev, &pdev->dev);
12392
1da177e4
LT		 12393#if TG3_VLAN_TAG_USED
12394 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12395 dev->vlan_rx_register = tg3_vlan_rx_register;
1da177e4
LT		 12396#endif
12397
12398 tp = netdev_priv(dev);
12399 tp->pdev = pdev;
12400 tp->dev = dev;
12401 tp->pm_cap = pm_cap;
12402 tp->mac_mode = TG3_DEF_MAC_MODE;
12403 tp->rx_mode = TG3_DEF_RX_MODE;
12404 tp->tx_mode = TG3_DEF_TX_MODE;
12405 tp->mi_mode = MAC_MI_MODE_BASE;
12406 if (tg3_debug > 0)
12407 tp->msg_enable = tg3_debug;
12408 else
12409 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12410
12411 /* The word/byte swap controls here control register access byte
12412 * swapping. DMA data byte swapping is controlled in the GRC_MODE
12413 * setting below.
12414 */
12415 tp->misc_host_ctrl =
12416 MISC_HOST_CTRL_MASK_PCI_INT |
12417 MISC_HOST_CTRL_WORD_SWAP |
12418 MISC_HOST_CTRL_INDIR_ACCESS |
12419 MISC_HOST_CTRL_PCISTATE_RW;
12420
12421 /* The NONFRM (non-frame) byte/word swap controls take effect
12422 * on descriptor entries, anything which isn't packet data.
12423 *
12424 * The StrongARM chips on the board (one for tx, one for rx)
12425 * are running in big-endian mode.
12426 */
12427 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
12428 GRC_MODE_WSWAP_NONFRM_DATA);
12429#ifdef __BIG_ENDIAN
12430 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
12431#endif
12432 spin_lock_init(&tp->lock);
1da177e4 12433 spin_lock_init(&tp->indirect_lock);
c4028958 12434 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 12435
12436 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
ab0049b4 12437 if (!tp->regs) {
1da177e4
LT		 12438 printk(KERN_ERR PFX "Cannot map device registers, "
12439 "aborting.\n");
12440 err = -ENOMEM;
12441 goto err_out_free_dev;
12442 }
12443
12444 tg3_init_link_config(tp);
12445
1da177e4
LT		 12446 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
12447 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
12448 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
12449
12450 dev->open = tg3_open;
12451 dev->stop = tg3_close;
12452 dev->get_stats = tg3_get_stats;
12453 dev->set_multicast_list = tg3_set_rx_mode;
12454 dev->set_mac_address = tg3_set_mac_addr;
12455 dev->do_ioctl = tg3_ioctl;
12456 dev->tx_timeout = tg3_tx_timeout;
bea3348e 12457 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 12458 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4
LT		 12459 dev->watchdog_timeo = TG3_TX_TIMEOUT;
12460 dev->change_mtu = tg3_change_mtu;
12461 dev->irq = pdev->irq;
12462#ifdef CONFIG_NET_POLL_CONTROLLER
12463 dev->poll_controller = tg3_poll_controller;
12464#endif
12465
12466 err = tg3_get_invariants(tp);
12467 if (err) {
12468 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
12469 "aborting.\n");
12470 goto err_out_iounmap;
12471 }
12472
4a29cc2e
MC		 12473 /* The EPB bridge inside 5714, 5715, and 5780 and any
12474 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 12475 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
12476 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
12477 * do DMA address check in tg3_start_xmit().
12478 */
4a29cc2e
MC		 12479 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
12480 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
12481 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 12482 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
12483#ifdef CONFIG_HIGHMEM
12484 dma_mask = DMA_64BIT_MASK;
12485#endif
4a29cc2e 12486 } else
72f2afb8
MC		 12487 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
12488
12489 /* Configure DMA attributes. */
12490 if (dma_mask > DMA_32BIT_MASK) {
12491 err = pci_set_dma_mask(pdev, dma_mask);
12492 if (!err) {
12493 dev->features |= NETIF_F_HIGHDMA;
12494 err = pci_set_consistent_dma_mask(pdev,
12495 persist_dma_mask);
12496 if (err < 0) {
12497 printk(KERN_ERR PFX "Unable to obtain 64 bit "
12498 "DMA for consistent allocations\n");
12499 goto err_out_iounmap;
12500 }
12501 }
12502 }
12503 if (err || dma_mask == DMA_32BIT_MASK) {
12504 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
12505 if (err) {
12506 printk(KERN_ERR PFX "No usable DMA configuration, "
12507 "aborting.\n");
12508 goto err_out_iounmap;
12509 }
12510 }
12511
fdfec172 12512 tg3_init_bufmgr_config(tp);
1da177e4 12513
1da177e4
LT		 12514 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12515 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
12516 }
12517 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12519 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 12520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 12521 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
12522 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
12523 } else {
7f62ad5d 12524 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
1da177e4
LT		 12525 }
12526
4e3a7aaa
MC		 12527 /* TSO is on by default on chips that support hardware TSO.
12528 * Firmware TSO on older chips gives lower performance, so it
12529 * is off by default, but can be enabled using ethtool.
12530 */
b0026624 12531 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 12532 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 12533 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12534 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624 12535 dev->features |= NETIF_F_TSO6;
9936bcf6
MC		 12536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12537 dev->features |= NETIF_F_TSO_ECN;
b0026624 12538 }
1da177e4 12539
1da177e4
LT		 12540
12541 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
12542 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
12543 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12544 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12545 tp->rx_pending = 63;
12546 }
12547
1da177e4
LT		 12548 err = tg3_get_device_address(tp);
12549 if (err) {
12550 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12551 "aborting.\n");
12552 goto err_out_iounmap;
12553 }
12554
c88864df
MC		 12555 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12556 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12557 printk(KERN_ERR PFX "Cannot find proper PCI device "
12558 "base address for APE, aborting.\n");
12559 err = -ENODEV;
12560 goto err_out_iounmap;
12561 }
12562
12563 tg3reg_base = pci_resource_start(pdev, 2);
12564 tg3reg_len = pci_resource_len(pdev, 2);
12565
12566 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
12567 if (tp->aperegs == 0UL) {
12568 printk(KERN_ERR PFX "Cannot map APE registers, "
12569 "aborting.\n");
12570 err = -ENOMEM;
12571 goto err_out_iounmap;
12572 }
12573
12574 tg3_ape_lock_init(tp);
12575 }
12576
1da177e4
LT		 12577 /*
12578 * Reset chip in case UNDI or EFI driver did not shutdown
12579 * DMA self test will enable WDMAC and we'll see (spurious)
12580 * pending DMA on the PCI bus at that point.
12581 */
12582 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12583 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 12584 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 12585 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 12586 }
12587
12588 err = tg3_test_dma(tp);
12589 if (err) {
12590 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 12591 goto err_out_apeunmap;
1da177e4
LT		 12592 }
12593
12594 /* Tigon3 can do ipv4 only... and some chips have buggy
12595 * checksumming.
12596 */
12597 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
d212f87b 12598 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
af36e6b6 12599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12600 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d212f87b
SH		 12603 dev->features |= NETIF_F_IPV6_CSUM;
12604
1da177e4
LT		 12605 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12606 } else
12607 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12608
1da177e4
LT		 12609 /* flow control autonegotiation is default behavior */
12610 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12611
15f9850d
DM		 12612 tg3_init_coal(tp);
12613
c49a1561
MC		 12614 pci_set_drvdata(pdev, dev);
12615
1da177e4
LT		 12616 err = register_netdev(dev);
12617 if (err) {
12618 printk(KERN_ERR PFX "Cannot register net device, "
12619 "aborting.\n");
0d3031d9 12620 goto err_out_apeunmap;
1da177e4
LT		 12621 }
12622
cbb45d21 12623 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 12624 dev->name,
12625 tp->board_part_number,
12626 tp->pci_chip_rev_id,
12627 tg3_phy_string(tp),
f9804ddb 12628 tg3_bus_string(tp, str),
cbb45d21
MC		 12629 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12630 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12631 "10/100/1000Base-T")));
1da177e4
LT		 12632
12633 for (i = 0; i < 6; i++)
12634 printk("%2.2x%c", dev->dev_addr[i],
12635 i == 5 ? '\n' : ':');
12636
12637 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
1c46ae05 12638 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
1da177e4
LT		 12639 dev->name,
12640 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12641 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12642 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12643 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4
LT		 12644 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12645 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 12646 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12647 dev->name, tp->dma_rwctrl,
12648 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12649 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 12650
12651 return 0;
12652
0d3031d9
MC		 12653err_out_apeunmap:
12654 if (tp->aperegs) {
12655 iounmap(tp->aperegs);
12656 tp->aperegs = NULL;
12657 }
12658
1da177e4 12659err_out_iounmap:
6892914f
MC		 12660 if (tp->regs) {
12661 iounmap(tp->regs);
22abe310 12662 tp->regs = NULL;
6892914f 12663 }
1da177e4
LT		 12664
12665err_out_free_dev:
12666 free_netdev(dev);
12667
12668err_out_free_res:
12669 pci_release_regions(pdev);
12670
12671err_out_disable_pdev:
12672 pci_disable_device(pdev);
12673 pci_set_drvdata(pdev, NULL);
12674 return err;
12675}
12676
12677static void __devexit tg3_remove_one(struct pci_dev *pdev)
12678{
12679 struct net_device *dev = pci_get_drvdata(pdev);
12680
12681 if (dev) {
12682 struct tg3 *tp = netdev_priv(dev);
12683
7faa006f 12684 flush_scheduled_work();
1da177e4 12685 unregister_netdev(dev);
0d3031d9
MC		 12686 if (tp->aperegs) {
12687 iounmap(tp->aperegs);
12688 tp->aperegs = NULL;
12689 }
6892914f
MC		 12690 if (tp->regs) {
12691 iounmap(tp->regs);
22abe310 12692 tp->regs = NULL;
6892914f 12693 }
1da177e4
LT		 12694 free_netdev(dev);
12695 pci_release_regions(pdev);
12696 pci_disable_device(pdev);
12697 pci_set_drvdata(pdev, NULL);
12698 }
12699}
12700
12701static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12702{
12703 struct net_device *dev = pci_get_drvdata(pdev);
12704 struct tg3 *tp = netdev_priv(dev);
12705 int err;
12706
3e0c95fd
MC		 12707 /* PCI register 4 needs to be saved whether netif_running() or not.
12708 * MSI address and data need to be saved if using MSI and
12709 * netif_running().
12710 */
12711 pci_save_state(pdev);
12712
1da177e4
LT		 12713 if (!netif_running(dev))
12714 return 0;
12715
7faa006f 12716 flush_scheduled_work();
1da177e4
LT		 12717 tg3_netif_stop(tp);
12718
12719 del_timer_sync(&tp->timer);
12720
f47c11ee 12721 tg3_full_lock(tp, 1);
1da177e4 12722 tg3_disable_ints(tp);
f47c11ee 12723 tg3_full_unlock(tp);
1da177e4
LT		 12724
12725 netif_device_detach(dev);
12726
f47c11ee 12727 tg3_full_lock(tp, 0);
944d980e 12728 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12729 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12730 tg3_full_unlock(tp);
1da177e4
LT		 12731
12732 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12733 if (err) {
f47c11ee 12734 tg3_full_lock(tp, 0);
1da177e4 12735
6a9eba15 12736 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12737 if (tg3_restart_hw(tp, 1))
12738 goto out;
1da177e4
LT		 12739
12740 tp->timer.expires = jiffies + tp->timer_offset;
12741 add_timer(&tp->timer);
12742
12743 netif_device_attach(dev);
12744 tg3_netif_start(tp);
12745
b9ec6c1b 12746out:
f47c11ee 12747 tg3_full_unlock(tp);
1da177e4
LT		 12748 }
12749
12750 return err;
12751}
12752
12753static int tg3_resume(struct pci_dev *pdev)
12754{
12755 struct net_device *dev = pci_get_drvdata(pdev);
12756 struct tg3 *tp = netdev_priv(dev);
12757 int err;
12758
3e0c95fd
MC		 12759 pci_restore_state(tp->pdev);
12760
1da177e4
LT		 12761 if (!netif_running(dev))
12762 return 0;
12763
bc1c7567 12764 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12765 if (err)
12766 return err;
12767
12768 netif_device_attach(dev);
12769
f47c11ee 12770 tg3_full_lock(tp, 0);
1da177e4 12771
6a9eba15 12772 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12773 err = tg3_restart_hw(tp, 1);
12774 if (err)
12775 goto out;
1da177e4
LT		 12776
12777 tp->timer.expires = jiffies + tp->timer_offset;
12778 add_timer(&tp->timer);
12779
1da177e4
LT		 12780 tg3_netif_start(tp);
12781
b9ec6c1b 12782out:
f47c11ee 12783 tg3_full_unlock(tp);
1da177e4 12784
b9ec6c1b 12785 return err;
1da177e4
LT		 12786}
12787
12788static struct pci_driver tg3_driver = {
12789 .name = DRV_MODULE_NAME,
12790 .id_table = tg3_pci_tbl,
12791 .probe = tg3_init_one,
12792 .remove = __devexit_p(tg3_remove_one),
12793 .suspend = tg3_suspend,
12794 .resume = tg3_resume
12795};
12796
12797static int __init tg3_init(void)
12798{
29917620 12799 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12800}
12801
12802static void __exit tg3_cleanup(void)
12803{
12804 pci_unregister_driver(&tg3_driver);
12805}
12806
12807module_init(tg3_init);
12808module_exit(tg3_cleanup);
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