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pkt_sched: Annotate uninitialized var in sfq_enqueue()
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
1da177e4
LT		 43
44#include <net/checksum.h>
c9bdd4b5 45#include <net/ip.h>
1da177e4
LT		 46
47#include <asm/system.h>
48#include <asm/io.h>
49#include <asm/byteorder.h>
50#include <asm/uaccess.h>
51
49b6e95f 52#ifdef CONFIG_SPARC
1da177e4 53#include <asm/idprom.h>
49b6e95f 54#include <asm/prom.h>
1da177e4
LT		 55#endif
56
63532394
MC		 57#define BAR_0 0
58#define BAR_2 2
59
1da177e4
LT		 60#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
61#define TG3_VLAN_TAG_USED 1
62#else
63#define TG3_VLAN_TAG_USED 0
64#endif
65
1da177e4 66#define TG3_TSO_SUPPORT 1
1da177e4
LT		 67
68#include "tg3.h"
69
70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": "
e245a385
MC		 72#define DRV_MODULE_VERSION "3.96"
73#define DRV_MODULE_RELDATE "November 21, 2008"
1da177e4
LT		 74
75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0
77#define TG3_DEF_TX_MODE 0
78#define TG3_DEF_MSG_ENABLE \
79 (NETIF_MSG_DRV | \
80 NETIF_MSG_PROBE | \
81 NETIF_MSG_LINK | \
82 NETIF_MSG_TIMER | \
83 NETIF_MSG_IFDOWN | \
84 NETIF_MSG_IFUP | \
85 NETIF_MSG_RX_ERR | \
86 NETIF_MSG_TX_ERR)
87
88/* length of time before we decide the hardware is borked,
89 * and dev->tx_timeout() should be called to fix the problem
90 */
91#define TG3_TX_TIMEOUT (5 * HZ)
92
93/* hardware minimum and maximum for a single frame's data payload */
94#define TG3_MIN_MTU 60
95#define TG3_MAX_MTU(tp) \
0f893dc6 96 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 97
98/* These numbers seem to be hard coded in the NIC firmware somehow.
99 * You can't change the ring sizes, but you can change where you place
100 * them in the NIC onboard memory.
101 */
102#define TG3_RX_RING_SIZE 512
103#define TG3_DEF_RX_RING_PENDING 200
104#define TG3_RX_JUMBO_RING_SIZE 256
105#define TG3_DEF_RX_JUMBO_RING_PENDING 100
106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
114 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
1da177e4
LT		 127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
130#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
131
132/* minimum number of free TX descriptors required to wake up TX process */
42952231 133#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 134
ad829268
MC		 135#define TG3_RAW_IP_ALIGN 2
136
1da177e4
LT		 137/* number of ETHTOOL_GSTATS u64's */
138#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139
4cafd3f5
MC		 140#define TG3_NUM_TEST 6
141
1da177e4
LT		 142static char version[] __devinitdata =
143 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
144
145MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
146MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
147MODULE_LICENSE("GPL");
148MODULE_VERSION(DRV_MODULE_VERSION);
149
150static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
151module_param(tg3_debug, int, 0);
152MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
153
154static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 220 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
221 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
222 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
223 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
224 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
225 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
226 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
227 {}
1da177e4
LT		 228};
229
230MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
231
50da859d 232static const struct {
1da177e4
LT		 233 const char string[ETH_GSTRING_LEN];
234} ethtool_stats_keys[TG3_NUM_STATS] = {
235 { "rx_octets" },
236 { "rx_fragments" },
237 { "rx_ucast_packets" },
238 { "rx_mcast_packets" },
239 { "rx_bcast_packets" },
240 { "rx_fcs_errors" },
241 { "rx_align_errors" },
242 { "rx_xon_pause_rcvd" },
243 { "rx_xoff_pause_rcvd" },
244 { "rx_mac_ctrl_rcvd" },
245 { "rx_xoff_entered" },
246 { "rx_frame_too_long_errors" },
247 { "rx_jabbers" },
248 { "rx_undersize_packets" },
249 { "rx_in_length_errors" },
250 { "rx_out_length_errors" },
251 { "rx_64_or_less_octet_packets" },
252 { "rx_65_to_127_octet_packets" },
253 { "rx_128_to_255_octet_packets" },
254 { "rx_256_to_511_octet_packets" },
255 { "rx_512_to_1023_octet_packets" },
256 { "rx_1024_to_1522_octet_packets" },
257 { "rx_1523_to_2047_octet_packets" },
258 { "rx_2048_to_4095_octet_packets" },
259 { "rx_4096_to_8191_octet_packets" },
260 { "rx_8192_to_9022_octet_packets" },
261
262 { "tx_octets" },
263 { "tx_collisions" },
264
265 { "tx_xon_sent" },
266 { "tx_xoff_sent" },
267 { "tx_flow_control" },
268 { "tx_mac_errors" },
269 { "tx_single_collisions" },
270 { "tx_mult_collisions" },
271 { "tx_deferred" },
272 { "tx_excessive_collisions" },
273 { "tx_late_collisions" },
274 { "tx_collide_2times" },
275 { "tx_collide_3times" },
276 { "tx_collide_4times" },
277 { "tx_collide_5times" },
278 { "tx_collide_6times" },
279 { "tx_collide_7times" },
280 { "tx_collide_8times" },
281 { "tx_collide_9times" },
282 { "tx_collide_10times" },
283 { "tx_collide_11times" },
284 { "tx_collide_12times" },
285 { "tx_collide_13times" },
286 { "tx_collide_14times" },
287 { "tx_collide_15times" },
288 { "tx_ucast_packets" },
289 { "tx_mcast_packets" },
290 { "tx_bcast_packets" },
291 { "tx_carrier_sense_errors" },
292 { "tx_discards" },
293 { "tx_errors" },
294
295 { "dma_writeq_full" },
296 { "dma_write_prioq_full" },
297 { "rxbds_empty" },
298 { "rx_discards" },
299 { "rx_errors" },
300 { "rx_threshold_hit" },
301
302 { "dma_readq_full" },
303 { "dma_read_prioq_full" },
304 { "tx_comp_queue_full" },
305
306 { "ring_set_send_prod_index" },
307 { "ring_status_update" },
308 { "nic_irqs" },
309 { "nic_avoided_irqs" },
310 { "nic_tx_threshold_hit" }
311};
312
50da859d 313static const struct {
4cafd3f5
MC		 314 const char string[ETH_GSTRING_LEN];
315} ethtool_test_keys[TG3_NUM_TEST] = {
316 { "nvram test (online) " },
317 { "link test (online) " },
318 { "register test (offline)" },
319 { "memory test (offline)" },
320 { "loopback test (offline)" },
321 { "interrupt test (offline)" },
322};
323
b401e9e2
MC		 324static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
325{
326 writel(val, tp->regs + off);
327}
328
329static u32 tg3_read32(struct tg3 *tp, u32 off)
330{
6aa20a22 331 return (readl(tp->regs + off));
b401e9e2
MC		 332}
333
0d3031d9
MC		 334static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
335{
336 writel(val, tp->aperegs + off);
337}
338
339static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
340{
341 return (readl(tp->aperegs + off));
342}
343
1da177e4
LT		 344static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
345{
6892914f
MC		 346 unsigned long flags;
347
348 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 349 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
350 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 351 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 352}
353
354static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
355{
356 writel(val, tp->regs + off);
357 readl(tp->regs + off);
1da177e4
LT		 358}
359
6892914f 360static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 361{
6892914f
MC		 362 unsigned long flags;
363 u32 val;
364
365 spin_lock_irqsave(&tp->indirect_lock, flags);
366 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
367 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
368 spin_unlock_irqrestore(&tp->indirect_lock, flags);
369 return val;
370}
371
372static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
373{
374 unsigned long flags;
375
376 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
377 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
378 TG3_64BIT_REG_LOW, val);
379 return;
380 }
381 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
382 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
383 TG3_64BIT_REG_LOW, val);
384 return;
1da177e4 385 }
6892914f
MC		 386
387 spin_lock_irqsave(&tp->indirect_lock, flags);
388 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
389 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
390 spin_unlock_irqrestore(&tp->indirect_lock, flags);
391
392 /* In indirect mode when disabling interrupts, we also need
393 * to clear the interrupt bit in the GRC local ctrl register.
394 */
395 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
396 (val == 0x1)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
398 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
399 }
400}
401
402static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
403{
404 unsigned long flags;
405 u32 val;
406
407 spin_lock_irqsave(&tp->indirect_lock, flags);
408 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
409 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
410 spin_unlock_irqrestore(&tp->indirect_lock, flags);
411 return val;
412}
413
b401e9e2
MC		 414/* usec_wait specifies the wait time in usec when writing to certain registers
415 * where it is unsafe to read back the register without some delay.
416 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
417 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
418 */
419static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 420{
b401e9e2
MC		 421 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
422 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
423 /* Non-posted methods */
424 tp->write32(tp, off, val);
425 else {
426 /* Posted method */
427 tg3_write32(tp, off, val);
428 if (usec_wait)
429 udelay(usec_wait);
430 tp->read32(tp, off);
431 }
432 /* Wait again after the read for the posted method to guarantee that
433 * the wait time is met.
434 */
435 if (usec_wait)
436 udelay(usec_wait);
1da177e4
LT		 437}
438
09ee929c
MC		 439static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
440{
441 tp->write32_mbox(tp, off, val);
6892914f
MC		 442 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
443 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
444 tp->read32_mbox(tp, off);
09ee929c
MC		 445}
446
20094930 447static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 448{
449 void __iomem *mbox = tp->regs + off;
450 writel(val, mbox);
451 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
452 writel(val, mbox);
453 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
454 readl(mbox);
455}
456
b5d3772c
MC		 457static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
458{
459 return (readl(tp->regs + off + GRCMBOX_BASE));
460}
461
462static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
463{
464 writel(val, tp->regs + off + GRCMBOX_BASE);
465}
466
20094930 467#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 468#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 469#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
470#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 471#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 472
473#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 474#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
475#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 476#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 477
478static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
479{
6892914f
MC		 480 unsigned long flags;
481
b5d3772c
MC		 482 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
483 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
484 return;
485
6892914f 486 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 487 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
488 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
489 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 490
bbadf503
MC		 491 /* Always leave this as zero. */
492 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
493 } else {
494 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
495 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 496
bbadf503
MC		 497 /* Always leave this as zero. */
498 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
499 }
500 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 501}
502
1da177e4
LT		 503static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
504{
6892914f
MC		 505 unsigned long flags;
506
b5d3772c
MC		 507 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
508 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
509 *val = 0;
510 return;
511 }
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 *val = tr32(TG3PCI_MEM_WIN_DATA);
523
524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
6892914f 527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 528}
529
0d3031d9
MC		 530static void tg3_ape_lock_init(struct tg3 *tp)
531{
532 int i;
533
534 /* Make sure the driver hasn't any stale locks. */
535 for (i = 0; i < 8; i++)
536 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
537 APE_LOCK_GRANT_DRIVER);
538}
539
540static int tg3_ape_lock(struct tg3 *tp, int locknum)
541{
542 int i, off;
543 int ret = 0;
544 u32 status;
545
546 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
547 return 0;
548
549 switch (locknum) {
77b483f1 550 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 551 case TG3_APE_LOCK_MEM:
552 break;
553 default:
554 return -EINVAL;
555 }
556
557 off = 4 * locknum;
558
559 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
560
561 /* Wait for up to 1 millisecond to acquire lock. */
562 for (i = 0; i < 100; i++) {
563 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
564 if (status == APE_LOCK_GRANT_DRIVER)
565 break;
566 udelay(10);
567 }
568
569 if (status != APE_LOCK_GRANT_DRIVER) {
570 /* Revoke the lock request. */
571 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
572 APE_LOCK_GRANT_DRIVER);
573
574 ret = -EBUSY;
575 }
576
577 return ret;
578}
579
580static void tg3_ape_unlock(struct tg3 *tp, int locknum)
581{
582 int off;
583
584 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
585 return;
586
587 switch (locknum) {
77b483f1 588 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 589 case TG3_APE_LOCK_MEM:
590 break;
591 default:
592 return;
593 }
594
595 off = 4 * locknum;
596 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
597}
598
1da177e4
LT		 599static void tg3_disable_ints(struct tg3 *tp)
600{
601 tw32(TG3PCI_MISC_HOST_CTRL,
602 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 603 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 604}
605
606static inline void tg3_cond_int(struct tg3 *tp)
607{
38f3843e
MC		 608 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
609 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 610 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 611 else
612 tw32(HOSTCC_MODE, tp->coalesce_mode |
613 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 614}
615
616static void tg3_enable_ints(struct tg3 *tp)
617{
bbe832c0
MC		 618 tp->irq_sync = 0;
619 wmb();
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 623 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
624 (tp->last_tag << 24));
fcfa0a32
MC		 625 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
626 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
627 (tp->last_tag << 24));
1da177e4
LT		 628 tg3_cond_int(tp);
629}
630
04237ddd
MC		 631static inline unsigned int tg3_has_work(struct tg3 *tp)
632{
633 struct tg3_hw_status *sblk = tp->hw_status;
634 unsigned int work_exists = 0;
635
636 /* check for phy events */
637 if (!(tp->tg3_flags &
638 (TG3_FLAG_USE_LINKCHG_REG |
639 TG3_FLAG_POLL_SERDES))) {
640 if (sblk->status & SD_STATUS_LINK_CHG)
641 work_exists = 1;
642 }
643 /* check for RX/TX work to do */
644 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
645 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
646 work_exists = 1;
647
648 return work_exists;
649}
650
1da177e4 651/* tg3_restart_ints
04237ddd
MC		 652 * similar to tg3_enable_ints, but it accurately determines whether there
653 * is new work pending and can return without flushing the PIO write
6aa20a22 654 * which reenables interrupts
1da177e4
LT		 655 */
656static void tg3_restart_ints(struct tg3 *tp)
657{
fac9b83e
DM		 658 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
659 tp->last_tag << 24);
1da177e4
LT		 660 mmiowb();
661
fac9b83e
DM		 662 /* When doing tagged status, this work check is unnecessary.
663 * The last_tag we write above tells the chip which piece of
664 * work we've completed.
665 */
666 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
667 tg3_has_work(tp))
04237ddd
MC		 668 tw32(HOSTCC_MODE, tp->coalesce_mode |
669 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 670}
671
672static inline void tg3_netif_stop(struct tg3 *tp)
673{
bbe832c0 674 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 675 napi_disable(&tp->napi);
1da177e4
LT		 676 netif_tx_disable(tp->dev);
677}
678
679static inline void tg3_netif_start(struct tg3 *tp)
680{
681 netif_wake_queue(tp->dev);
682 /* NOTE: unconditional netif_wake_queue is only appropriate
683 * so long as all callers are assured to have free tx slots
684 * (such as after tg3_init_hw)
685 */
bea3348e 686 napi_enable(&tp->napi);
f47c11ee
DM		 687 tp->hw_status->status |= SD_STATUS_UPDATED;
688 tg3_enable_ints(tp);
1da177e4
LT		 689}
690
691static void tg3_switch_clocks(struct tg3 *tp)
692{
693 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
694 u32 orig_clock_ctrl;
695
795d01c5
MC		 696 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
697 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 698 return;
699
1da177e4
LT		 700 orig_clock_ctrl = clock_ctrl;
701 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
702 CLOCK_CTRL_CLKRUN_OENABLE |
703 0x1f);
704 tp->pci_clock_ctrl = clock_ctrl;
705
706 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
707 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 708 tw32_wait_f(TG3PCI_CLOCK_CTRL,
709 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 710 }
711 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 712 tw32_wait_f(TG3PCI_CLOCK_CTRL,
713 clock_ctrl |
714 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
715 40);
716 tw32_wait_f(TG3PCI_CLOCK_CTRL,
717 clock_ctrl | (CLOCK_CTRL_ALTCLK),
718 40);
1da177e4 719 }
b401e9e2 720 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 721}
722
723#define PHY_BUSY_LOOPS 5000
724
725static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
726{
727 u32 frame_val;
728 unsigned int loops;
729 int ret;
730
731 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
732 tw32_f(MAC_MI_MODE,
733 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
734 udelay(80);
735 }
736
737 *val = 0x0;
738
739 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
740 MI_COM_PHY_ADDR_MASK);
741 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
742 MI_COM_REG_ADDR_MASK);
743 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 744
1da177e4
LT		 745 tw32_f(MAC_MI_COM, frame_val);
746
747 loops = PHY_BUSY_LOOPS;
748 while (loops != 0) {
749 udelay(10);
750 frame_val = tr32(MAC_MI_COM);
751
752 if ((frame_val & MI_COM_BUSY) == 0) {
753 udelay(5);
754 frame_val = tr32(MAC_MI_COM);
755 break;
756 }
757 loops -= 1;
758 }
759
760 ret = -EBUSY;
761 if (loops != 0) {
762 *val = frame_val & MI_COM_DATA_MASK;
763 ret = 0;
764 }
765
766 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
767 tw32_f(MAC_MI_MODE, tp->mi_mode);
768 udelay(80);
769 }
770
771 return ret;
772}
773
774static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
775{
776 u32 frame_val;
777 unsigned int loops;
778 int ret;
779
b5d3772c
MC		 780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
781 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
782 return 0;
783
1da177e4
LT		 784 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
785 tw32_f(MAC_MI_MODE,
786 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
787 udelay(80);
788 }
789
790 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
791 MI_COM_PHY_ADDR_MASK);
792 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
793 MI_COM_REG_ADDR_MASK);
794 frame_val |= (val & MI_COM_DATA_MASK);
795 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 796
1da177e4
LT		 797 tw32_f(MAC_MI_COM, frame_val);
798
799 loops = PHY_BUSY_LOOPS;
800 while (loops != 0) {
801 udelay(10);
802 frame_val = tr32(MAC_MI_COM);
803 if ((frame_val & MI_COM_BUSY) == 0) {
804 udelay(5);
805 frame_val = tr32(MAC_MI_COM);
806 break;
807 }
808 loops -= 1;
809 }
810
811 ret = -EBUSY;
812 if (loops != 0)
813 ret = 0;
814
815 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
816 tw32_f(MAC_MI_MODE, tp->mi_mode);
817 udelay(80);
818 }
819
820 return ret;
821}
822
95e2869a
MC		 823static int tg3_bmcr_reset(struct tg3 *tp)
824{
825 u32 phy_control;
826 int limit, err;
827
828 /* OK, reset it, and poll the BMCR_RESET bit until it
829 * clears or we time out.
830 */
831 phy_control = BMCR_RESET;
832 err = tg3_writephy(tp, MII_BMCR, phy_control);
833 if (err != 0)
834 return -EBUSY;
835
836 limit = 5000;
837 while (limit--) {
838 err = tg3_readphy(tp, MII_BMCR, &phy_control);
839 if (err != 0)
840 return -EBUSY;
841
842 if ((phy_control & BMCR_RESET) == 0) {
843 udelay(40);
844 break;
845 }
846 udelay(10);
847 }
848 if (limit <= 0)
849 return -EBUSY;
850
851 return 0;
852}
853
158d7abd
MC		 854static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
855{
856 struct tg3 *tp = (struct tg3 *)bp->priv;
857 u32 val;
858
859 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860 return -EAGAIN;
861
862 if (tg3_readphy(tp, reg, &val))
863 return -EIO;
864
865 return val;
866}
867
868static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
869{
870 struct tg3 *tp = (struct tg3 *)bp->priv;
871
872 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
873 return -EAGAIN;
874
875 if (tg3_writephy(tp, reg, val))
876 return -EIO;
877
878 return 0;
879}
880
881static int tg3_mdio_reset(struct mii_bus *bp)
882{
883 return 0;
884}
885
9c61d6bc 886static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 887{
888 u32 val;
fcb389df 889 struct phy_device *phydev;
a9daf367 890
fcb389df
MC		 891 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
892 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
893 case TG3_PHY_ID_BCM50610:
894 val = MAC_PHYCFG2_50610_LED_MODES;
895 break;
896 case TG3_PHY_ID_BCMAC131:
897 val = MAC_PHYCFG2_AC131_LED_MODES;
898 break;
899 case TG3_PHY_ID_RTL8211C:
900 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
901 break;
902 case TG3_PHY_ID_RTL8201E:
903 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
904 break;
905 default:
a9daf367 906 return;
fcb389df
MC		 907 }
908
909 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
910 tw32(MAC_PHYCFG2, val);
911
912 val = tr32(MAC_PHYCFG1);
913 val &= ~MAC_PHYCFG1_RGMII_INT;
914 tw32(MAC_PHYCFG1, val);
915
916 return;
917 }
918
919 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
920 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
921 MAC_PHYCFG2_FMODE_MASK_MASK |
922 MAC_PHYCFG2_GMODE_MASK_MASK |
923 MAC_PHYCFG2_ACT_MASK_MASK |
924 MAC_PHYCFG2_QUAL_MASK_MASK |
925 MAC_PHYCFG2_INBAND_ENABLE;
926
927 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 928
929 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
930 MAC_PHYCFG1_RGMII_SND_STAT_EN);
931 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
932 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
933 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
934 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
935 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
936 }
937 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
938
a9daf367
MC		 939 val = tr32(MAC_EXT_RGMII_MODE);
940 val &= ~(MAC_RGMII_MODE_RX_INT_B |
941 MAC_RGMII_MODE_RX_QUALITY |
942 MAC_RGMII_MODE_RX_ACTIVITY |
943 MAC_RGMII_MODE_RX_ENG_DET |
944 MAC_RGMII_MODE_TX_ENABLE |
945 MAC_RGMII_MODE_TX_LOWPWR |
946 MAC_RGMII_MODE_TX_RESET);
fcb389df 947 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 948 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
949 val |= MAC_RGMII_MODE_RX_INT_B |
950 MAC_RGMII_MODE_RX_QUALITY |
951 MAC_RGMII_MODE_RX_ACTIVITY |
952 MAC_RGMII_MODE_RX_ENG_DET;
953 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
954 val |= MAC_RGMII_MODE_TX_ENABLE |
955 MAC_RGMII_MODE_TX_LOWPWR |
956 MAC_RGMII_MODE_TX_RESET;
957 }
958 tw32(MAC_EXT_RGMII_MODE, val);
959}
960
158d7abd
MC		 961static void tg3_mdio_start(struct tg3 *tp)
962{
963 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 964 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 965 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 966 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 967 }
968
969 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
970 tw32_f(MAC_MI_MODE, tp->mi_mode);
971 udelay(80);
a9daf367 972
9c61d6bc
MC		 973 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
975 tg3_mdio_config_5785(tp);
158d7abd
MC		 976}
977
978static void tg3_mdio_stop(struct tg3 *tp)
979{
980 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 981 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 982 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 983 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 984 }
985}
986
987static int tg3_mdio_init(struct tg3 *tp)
988{
989 int i;
990 u32 reg;
a9daf367 991 struct phy_device *phydev;
158d7abd
MC		 992
993 tg3_mdio_start(tp);
994
995 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
996 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
997 return 0;
998
298cf9be
LB		 999 tp->mdio_bus = mdiobus_alloc();
1000 if (tp->mdio_bus == NULL)
1001 return -ENOMEM;
158d7abd 1002
298cf9be
LB		 1003 tp->mdio_bus->name = "tg3 mdio bus";
1004 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1005 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1006 tp->mdio_bus->priv = tp;
1007 tp->mdio_bus->parent = &tp->pdev->dev;
1008 tp->mdio_bus->read = &tg3_mdio_read;
1009 tp->mdio_bus->write = &tg3_mdio_write;
1010 tp->mdio_bus->reset = &tg3_mdio_reset;
1011 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1012 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1013
1014 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1015 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1016
1017 /* The bus registration will look for all the PHYs on the mdio bus.
1018 * Unfortunately, it does not ensure the PHY is powered up before
1019 * accessing the PHY ID registers. A chip reset is the
1020 * quickest way to bring the device back to an operational state..
1021 */
1022 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1023 tg3_bmcr_reset(tp);
1024
298cf9be 1025 i = mdiobus_register(tp->mdio_bus);
a9daf367 1026 if (i) {
158d7abd
MC		 1027 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1028 tp->dev->name, i);
9c61d6bc 1029 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1030 return i;
1031 }
158d7abd 1032
298cf9be 1033 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1034
9c61d6bc
MC		 1035 if (!phydev || !phydev->drv) {
1036 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1037 mdiobus_unregister(tp->mdio_bus);
1038 mdiobus_free(tp->mdio_bus);
1039 return -ENODEV;
1040 }
1041
1042 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1043 case TG3_PHY_ID_BCM57780:
1044 phydev->interface = PHY_INTERFACE_MODE_GMII;
1045 break;
a9daf367 1046 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1047 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1048 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1049 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1050 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1051 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1052 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1053 /* fallthru */
1054 case TG3_PHY_ID_RTL8211C:
1055 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1056 break;
fcb389df 1057 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1058 case TG3_PHY_ID_BCMAC131:
1059 phydev->interface = PHY_INTERFACE_MODE_MII;
1060 break;
1061 }
1062
9c61d6bc
MC		 1063 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1064
1065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1066 tg3_mdio_config_5785(tp);
a9daf367
MC		 1067
1068 return 0;
158d7abd
MC		 1069}
1070
1071static void tg3_mdio_fini(struct tg3 *tp)
1072{
1073 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1074 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1075 mdiobus_unregister(tp->mdio_bus);
1076 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1077 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1078 }
1079}
1080
4ba526ce
MC		 1081/* tp->lock is held. */
1082static inline void tg3_generate_fw_event(struct tg3 *tp)
1083{
1084 u32 val;
1085
1086 val = tr32(GRC_RX_CPU_EVENT);
1087 val |= GRC_RX_CPU_DRIVER_EVENT;
1088 tw32_f(GRC_RX_CPU_EVENT, val);
1089
1090 tp->last_event_jiffies = jiffies;
1091}
1092
1093#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1094
95e2869a
MC		 1095/* tp->lock is held. */
1096static void tg3_wait_for_event_ack(struct tg3 *tp)
1097{
1098 int i;
4ba526ce
MC		 1099 unsigned int delay_cnt;
1100 long time_remain;
1101
1102 /* If enough time has passed, no wait is necessary. */
1103 time_remain = (long)(tp->last_event_jiffies + 1 +
1104 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1105 (long)jiffies;
1106 if (time_remain < 0)
1107 return;
1108
1109 /* Check if we can shorten the wait time. */
1110 delay_cnt = jiffies_to_usecs(time_remain);
1111 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1112 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1113 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1114
4ba526ce 1115 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1116 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1117 break;
4ba526ce 1118 udelay(8);
95e2869a
MC		 1119 }
1120}
1121
1122/* tp->lock is held. */
1123static void tg3_ump_link_report(struct tg3 *tp)
1124{
1125 u32 reg;
1126 u32 val;
1127
1128 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1129 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1130 return;
1131
1132 tg3_wait_for_event_ack(tp);
1133
1134 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1135
1136 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1137
1138 val = 0;
1139 if (!tg3_readphy(tp, MII_BMCR, &reg))
1140 val = reg << 16;
1141 if (!tg3_readphy(tp, MII_BMSR, &reg))
1142 val |= (reg & 0xffff);
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_LPA, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1151
1152 val = 0;
1153 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1154 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1155 val = reg << 16;
1156 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1157 val |= (reg & 0xffff);
1158 }
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1160
1161 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1162 val = reg << 16;
1163 else
1164 val = 0;
1165 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1166
4ba526ce 1167 tg3_generate_fw_event(tp);
95e2869a
MC		 1168}
1169
1170static void tg3_link_report(struct tg3 *tp)
1171{
1172 if (!netif_carrier_ok(tp->dev)) {
1173 if (netif_msg_link(tp))
1174 printk(KERN_INFO PFX "%s: Link is down.\n",
1175 tp->dev->name);
1176 tg3_ump_link_report(tp);
1177 } else if (netif_msg_link(tp)) {
1178 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1179 tp->dev->name,
1180 (tp->link_config.active_speed == SPEED_1000 ?
1181 1000 :
1182 (tp->link_config.active_speed == SPEED_100 ?
1183 100 : 10)),
1184 (tp->link_config.active_duplex == DUPLEX_FULL ?
1185 "full" : "half"));
1186
1187 printk(KERN_INFO PFX
1188 "%s: Flow control is %s for TX and %s for RX.\n",
1189 tp->dev->name,
e18ce346 1190 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1191 "on" : "off",
e18ce346 1192 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1193 "on" : "off");
1194 tg3_ump_link_report(tp);
1195 }
1196}
1197
1198static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1199{
1200 u16 miireg;
1201
e18ce346 1202 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1203 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1204 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1205 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1206 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1207 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1208 else
1209 miireg = 0;
1210
1211 return miireg;
1212}
1213
1214static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1215{
1216 u16 miireg;
1217
e18ce346 1218 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1219 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1220 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1221 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1222 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1223 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1224 else
1225 miireg = 0;
1226
1227 return miireg;
1228}
1229
95e2869a
MC		 1230static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1231{
1232 u8 cap = 0;
1233
1234 if (lcladv & ADVERTISE_1000XPAUSE) {
1235 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1236 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1237 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1238 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1239 cap = FLOW_CTRL_RX;
95e2869a
MC		 1240 } else {
1241 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1242 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1243 }
1244 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1245 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1246 cap = FLOW_CTRL_TX;
95e2869a
MC		 1247 }
1248
1249 return cap;
1250}
1251
f51f3562 1252static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1253{
b02fd9e3 1254 u8 autoneg;
f51f3562 1255 u8 flowctrl = 0;
95e2869a
MC		 1256 u32 old_rx_mode = tp->rx_mode;
1257 u32 old_tx_mode = tp->tx_mode;
1258
b02fd9e3 1259 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1260 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1261 else
1262 autoneg = tp->link_config.autoneg;
1263
1264 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1265 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1266 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1267 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1268 else
bc02ff95 1269 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1270 } else
1271 flowctrl = tp->link_config.flowctrl;
95e2869a 1272
f51f3562 1273 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1274
e18ce346 1275 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1276 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1277 else
1278 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1279
f51f3562 1280 if (old_rx_mode != tp->rx_mode)
95e2869a 1281 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1282
e18ce346 1283 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1284 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1285 else
1286 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1287
f51f3562 1288 if (old_tx_mode != tp->tx_mode)
95e2869a 1289 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1290}
1291
b02fd9e3
MC		 1292static void tg3_adjust_link(struct net_device *dev)
1293{
1294 u8 oldflowctrl, linkmesg = 0;
1295 u32 mac_mode, lcl_adv, rmt_adv;
1296 struct tg3 *tp = netdev_priv(dev);
298cf9be 1297 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1298
1299 spin_lock(&tp->lock);
1300
1301 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1302 MAC_MODE_HALF_DUPLEX);
1303
1304 oldflowctrl = tp->link_config.active_flowctrl;
1305
1306 if (phydev->link) {
1307 lcl_adv = 0;
1308 rmt_adv = 0;
1309
1310 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1311 mac_mode |= MAC_MODE_PORT_MODE_MII;
1312 else
1313 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1314
1315 if (phydev->duplex == DUPLEX_HALF)
1316 mac_mode |= MAC_MODE_HALF_DUPLEX;
1317 else {
1318 lcl_adv = tg3_advert_flowctrl_1000T(
1319 tp->link_config.flowctrl);
1320
1321 if (phydev->pause)
1322 rmt_adv = LPA_PAUSE_CAP;
1323 if (phydev->asym_pause)
1324 rmt_adv |= LPA_PAUSE_ASYM;
1325 }
1326
1327 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1328 } else
1329 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1330
1331 if (mac_mode != tp->mac_mode) {
1332 tp->mac_mode = mac_mode;
1333 tw32_f(MAC_MODE, tp->mac_mode);
1334 udelay(40);
1335 }
1336
fcb389df
MC		 1337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1338 if (phydev->speed == SPEED_10)
1339 tw32(MAC_MI_STAT,
1340 MAC_MI_STAT_10MBPS_MODE |
1341 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1342 else
1343 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1344 }
1345
b02fd9e3
MC		 1346 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1347 tw32(MAC_TX_LENGTHS,
1348 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1349 (6 << TX_LENGTHS_IPG_SHIFT) |
1350 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1351 else
1352 tw32(MAC_TX_LENGTHS,
1353 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1354 (6 << TX_LENGTHS_IPG_SHIFT) |
1355 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1356
1357 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1358 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1359 phydev->speed != tp->link_config.active_speed ||
1360 phydev->duplex != tp->link_config.active_duplex ||
1361 oldflowctrl != tp->link_config.active_flowctrl)
1362 linkmesg = 1;
1363
1364 tp->link_config.active_speed = phydev->speed;
1365 tp->link_config.active_duplex = phydev->duplex;
1366
1367 spin_unlock(&tp->lock);
1368
1369 if (linkmesg)
1370 tg3_link_report(tp);
1371}
1372
1373static int tg3_phy_init(struct tg3 *tp)
1374{
1375 struct phy_device *phydev;
1376
1377 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1378 return 0;
1379
1380 /* Bring the PHY back to a known state. */
1381 tg3_bmcr_reset(tp);
1382
298cf9be 1383 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1384
1385 /* Attach the MAC to the PHY. */
fb28ad35 1386 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1387 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1388 if (IS_ERR(phydev)) {
1389 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1390 return PTR_ERR(phydev);
1391 }
1392
b02fd9e3 1393 /* Mask with MAC supported features. */
9c61d6bc
MC		 1394 switch (phydev->interface) {
1395 case PHY_INTERFACE_MODE_GMII:
1396 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1397 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1398 phydev->supported &= (PHY_GBIT_FEATURES |
1399 SUPPORTED_Pause |
1400 SUPPORTED_Asym_Pause);
1401 break;
1402 }
1403 /* fallthru */
9c61d6bc
MC		 1404 case PHY_INTERFACE_MODE_MII:
1405 phydev->supported &= (PHY_BASIC_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 default:
1410 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1411 return -EINVAL;
1412 }
1413
1414 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1415
1416 phydev->advertising = phydev->supported;
1417
b02fd9e3
MC		 1418 return 0;
1419}
1420
1421static void tg3_phy_start(struct tg3 *tp)
1422{
1423 struct phy_device *phydev;
1424
1425 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1426 return;
1427
298cf9be 1428 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1429
1430 if (tp->link_config.phy_is_low_power) {
1431 tp->link_config.phy_is_low_power = 0;
1432 phydev->speed = tp->link_config.orig_speed;
1433 phydev->duplex = tp->link_config.orig_duplex;
1434 phydev->autoneg = tp->link_config.orig_autoneg;
1435 phydev->advertising = tp->link_config.orig_advertising;
1436 }
1437
1438 phy_start(phydev);
1439
1440 phy_start_aneg(phydev);
1441}
1442
1443static void tg3_phy_stop(struct tg3 *tp)
1444{
1445 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1446 return;
1447
298cf9be 1448 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1449}
1450
1451static void tg3_phy_fini(struct tg3 *tp)
1452{
1453 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1454 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1455 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1456 }
1457}
1458
b2a5c19c
MC		 1459static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1460{
1461 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1462 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1463}
1464
6833c043
MC		 1465static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1466{
1467 u32 reg;
1468
1469 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1470 return;
1471
1472 reg = MII_TG3_MISC_SHDW_WREN |
1473 MII_TG3_MISC_SHDW_SCR5_SEL |
1474 MII_TG3_MISC_SHDW_SCR5_LPED |
1475 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1476 MII_TG3_MISC_SHDW_SCR5_SDTL |
1477 MII_TG3_MISC_SHDW_SCR5_C125OE;
1478 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1479 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1480
1481 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1482
1483
1484 reg = MII_TG3_MISC_SHDW_WREN |
1485 MII_TG3_MISC_SHDW_APD_SEL |
1486 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1487 if (enable)
1488 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1489
1490 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1491}
1492
9ef8ca99
MC		 1493static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1494{
1495 u32 phy;
1496
1497 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1498 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1499 return;
1500
1501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1502 u32 ephy;
1503
1504 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1505 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1506 ephy | MII_TG3_EPHY_SHADOW_EN);
1507 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1508 if (enable)
1509 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1510 else
1511 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1512 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1513 }
1514 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1515 }
1516 } else {
1517 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1518 MII_TG3_AUXCTL_SHDWSEL_MISC;
1519 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1520 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1521 if (enable)
1522 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1523 else
1524 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1525 phy |= MII_TG3_AUXCTL_MISC_WREN;
1526 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1527 }
1528 }
1529}
1530
1da177e4
LT		 1531static void tg3_phy_set_wirespeed(struct tg3 *tp)
1532{
1533 u32 val;
1534
1535 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1536 return;
1537
1538 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1539 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1540 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1541 (val | (1 << 15) | (1 << 4)));
1542}
1543
b2a5c19c
MC		 1544static void tg3_phy_apply_otp(struct tg3 *tp)
1545{
1546 u32 otp, phy;
1547
1548 if (!tp->phy_otp)
1549 return;
1550
1551 otp = tp->phy_otp;
1552
1553 /* Enable SM_DSP clock and tx 6dB coding. */
1554 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1555 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1556 MII_TG3_AUXCTL_ACTL_TX_6DB;
1557 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1558
1559 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1560 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1561 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1562
1563 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1564 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1565 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1566
1567 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1568 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1570
1571 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1572 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1573
1574 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1575 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1576
1577 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1578 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1579 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1580
1581 /* Turn off SM_DSP clock. */
1582 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1583 MII_TG3_AUXCTL_ACTL_TX_6DB;
1584 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1585}
1586
1da177e4
LT		 1587static int tg3_wait_macro_done(struct tg3 *tp)
1588{
1589 int limit = 100;
1590
1591 while (limit--) {
1592 u32 tmp32;
1593
1594 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1595 if ((tmp32 & 0x1000) == 0)
1596 break;
1597 }
1598 }
1599 if (limit <= 0)
1600 return -EBUSY;
1601
1602 return 0;
1603}
1604
1605static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1606{
1607 static const u32 test_pat[4][6] = {
1608 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1609 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1610 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1611 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1612 };
1613 int chan;
1614
1615 for (chan = 0; chan < 4; chan++) {
1616 int i;
1617
1618 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1619 (chan * 0x2000) | 0x0200);
1620 tg3_writephy(tp, 0x16, 0x0002);
1621
1622 for (i = 0; i < 6; i++)
1623 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1624 test_pat[chan][i]);
1625
1626 tg3_writephy(tp, 0x16, 0x0202);
1627 if (tg3_wait_macro_done(tp)) {
1628 *resetp = 1;
1629 return -EBUSY;
1630 }
1631
1632 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1633 (chan * 0x2000) | 0x0200);
1634 tg3_writephy(tp, 0x16, 0x0082);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, 0x16, 0x0802);
1641 if (tg3_wait_macro_done(tp)) {
1642 *resetp = 1;
1643 return -EBUSY;
1644 }
1645
1646 for (i = 0; i < 6; i += 2) {
1647 u32 low, high;
1648
1649 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1650 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1651 tg3_wait_macro_done(tp)) {
1652 *resetp = 1;
1653 return -EBUSY;
1654 }
1655 low &= 0x7fff;
1656 high &= 0x000f;
1657 if (low != test_pat[chan][i] ||
1658 high != test_pat[chan][i+1]) {
1659 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1660 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1661 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1662
1663 return -EBUSY;
1664 }
1665 }
1666 }
1667
1668 return 0;
1669}
1670
1671static int tg3_phy_reset_chanpat(struct tg3 *tp)
1672{
1673 int chan;
1674
1675 for (chan = 0; chan < 4; chan++) {
1676 int i;
1677
1678 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1679 (chan * 0x2000) | 0x0200);
1680 tg3_writephy(tp, 0x16, 0x0002);
1681 for (i = 0; i < 6; i++)
1682 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1683 tg3_writephy(tp, 0x16, 0x0202);
1684 if (tg3_wait_macro_done(tp))
1685 return -EBUSY;
1686 }
1687
1688 return 0;
1689}
1690
1691static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1692{
1693 u32 reg32, phy9_orig;
1694 int retries, do_phy_reset, err;
1695
1696 retries = 10;
1697 do_phy_reset = 1;
1698 do {
1699 if (do_phy_reset) {
1700 err = tg3_bmcr_reset(tp);
1701 if (err)
1702 return err;
1703 do_phy_reset = 0;
1704 }
1705
1706 /* Disable transmitter and interrupt. */
1707 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1708 continue;
1709
1710 reg32 |= 0x3000;
1711 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1712
1713 /* Set full-duplex, 1000 mbps. */
1714 tg3_writephy(tp, MII_BMCR,
1715 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1716
1717 /* Set to master mode. */
1718 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1719 continue;
1720
1721 tg3_writephy(tp, MII_TG3_CTRL,
1722 (MII_TG3_CTRL_AS_MASTER |
1723 MII_TG3_CTRL_ENABLE_AS_MASTER));
1724
1725 /* Enable SM_DSP_CLOCK and 6dB. */
1726 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1727
1728 /* Block the PHY control access. */
1729 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1731
1732 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1733 if (!err)
1734 break;
1735 } while (--retries);
1736
1737 err = tg3_phy_reset_chanpat(tp);
1738 if (err)
1739 return err;
1740
1741 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1743
1744 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1745 tg3_writephy(tp, 0x16, 0x0000);
1746
1747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1748 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1749 /* Set Extended packet length bit for jumbo frames */
1750 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1751 }
1752 else {
1753 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1754 }
1755
1756 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1757
1758 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1759 reg32 &= ~0x3000;
1760 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1761 } else if (!err)
1762 err = -EBUSY;
1763
1764 return err;
1765}
1766
1767/* This will reset the tigon3 PHY if there is no valid
1768 * link unless the FORCE argument is non-zero.
1769 */
1770static int tg3_phy_reset(struct tg3 *tp)
1771{
b2a5c19c 1772 u32 cpmuctrl;
1da177e4
LT		 1773 u32 phy_status;
1774 int err;
1775
60189ddf
MC		 1776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1777 u32 val;
1778
1779 val = tr32(GRC_MISC_CFG);
1780 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1781 udelay(40);
1782 }
1da177e4
LT		 1783 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1784 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1785 if (err != 0)
1786 return -EBUSY;
1787
c8e1e82b
MC		 1788 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1789 netif_carrier_off(tp->dev);
1790 tg3_link_report(tp);
1791 }
1792
1da177e4
LT		 1793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1794 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1796 err = tg3_phy_reset_5703_4_5(tp);
1797 if (err)
1798 return err;
1799 goto out;
1800 }
1801
b2a5c19c
MC		 1802 cpmuctrl = 0;
1803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1804 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1805 cpmuctrl = tr32(TG3_CPMU_CTRL);
1806 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1807 tw32(TG3_CPMU_CTRL,
1808 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1809 }
1810
1da177e4
LT		 1811 err = tg3_bmcr_reset(tp);
1812 if (err)
1813 return err;
1814
b2a5c19c
MC		 1815 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1816 u32 phy;
1817
1818 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1819 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1820
1821 tw32(TG3_CPMU_CTRL, cpmuctrl);
1822 }
1823
bcb37f6c
MC		 1824 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1825 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1826 u32 val;
1827
1828 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1829 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1830 CPMU_LSPD_1000MB_MACCLK_12_5) {
1831 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1832 udelay(40);
1833 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1834 }
1835 }
1836
b2a5c19c
MC		 1837 tg3_phy_apply_otp(tp);
1838
6833c043
MC		 1839 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1840 tg3_phy_toggle_apd(tp, true);
1841 else
1842 tg3_phy_toggle_apd(tp, false);
1843
1da177e4
LT		 1844out:
1845 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1846 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1847 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1848 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1849 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1850 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1852 }
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1854 tg3_writephy(tp, 0x1c, 0x8d68);
1855 tg3_writephy(tp, 0x1c, 0x8d68);
1856 }
1857 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1858 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1860 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1861 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1862 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1863 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1864 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1865 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1866 }
c424cb24
MC		 1867 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1868 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1870 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1872 tg3_writephy(tp, MII_TG3_TEST1,
1873 MII_TG3_TEST1_TRIM_EN | 0x4);
1874 } else
1875 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1877 }
1da177e4
LT		 1878 /* Set Extended packet length bit (bit 14) on all chips that */
1879 /* support jumbo frames */
1880 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1881 /* Cannot do read-modify-write on 5401 */
1882 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1883 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1884 u32 phy_reg;
1885
1886 /* Set bit 14 with read-modify-write to preserve other bits */
1887 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1888 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1889 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1890 }
1891
1892 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1893 * jumbo frames transmission.
1894 */
0f893dc6 1895 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1896 u32 phy_reg;
1897
1898 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1899 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1900 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1901 }
1902
715116a1 1903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1904 /* adjust output voltage */
1905 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1906 }
1907
9ef8ca99 1908 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1909 tg3_phy_set_wirespeed(tp);
1910 return 0;
1911}
1912
1913static void tg3_frob_aux_power(struct tg3 *tp)
1914{
1915 struct tg3 *tp_peer = tp;
1916
9d26e213 1917 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1918 return;
1919
8c2dc7e1
MC		 1920 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1921 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1922 struct net_device *dev_peer;
1923
1924 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1925 /* remove_one() may have been run on the peer. */
8c2dc7e1 1926 if (!dev_peer)
bc1c7567
MC		 1927 tp_peer = tp;
1928 else
1929 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1930 }
1931
1da177e4 1932 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1933 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1934 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1935 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1938 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1939 (GRC_LCLCTRL_GPIO_OE0 |
1940 GRC_LCLCTRL_GPIO_OE1 |
1941 GRC_LCLCTRL_GPIO_OE2 |
1942 GRC_LCLCTRL_GPIO_OUTPUT0 |
1943 GRC_LCLCTRL_GPIO_OUTPUT1),
1944 100);
5f0c4a3c
MC		 1945 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1946 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1947 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1 |
1952 tp->grc_local_ctrl;
1953 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1954
1955 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1956 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1957
1958 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1959 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1960 } else {
1961 u32 no_gpio2;
dc56b7d4 1962 u32 grc_local_ctrl = 0;
1da177e4
LT		 1963
1964 if (tp_peer != tp &&
1965 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1966 return;
1967
dc56b7d4
MC		 1968 /* Workaround to prevent overdrawing Amps. */
1969 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1970 ASIC_REV_5714) {
1971 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1972 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1973 grc_local_ctrl, 100);
dc56b7d4
MC		 1974 }
1975
1da177e4
LT		 1976 /* On 5753 and variants, GPIO2 cannot be used. */
1977 no_gpio2 = tp->nic_sram_data_cfg &
1978 NIC_SRAM_DATA_CFG_NO_GPIO2;
1979
dc56b7d4 1980 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1981 GRC_LCLCTRL_GPIO_OE1 |
1982 GRC_LCLCTRL_GPIO_OE2 |
1983 GRC_LCLCTRL_GPIO_OUTPUT1 |
1984 GRC_LCLCTRL_GPIO_OUTPUT2;
1985 if (no_gpio2) {
1986 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1987 GRC_LCLCTRL_GPIO_OUTPUT2);
1988 }
b401e9e2
MC		 1989 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1990 grc_local_ctrl, 100);
1da177e4
LT		 1991
1992 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1993
b401e9e2
MC		 1994 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1995 grc_local_ctrl, 100);
1da177e4
LT		 1996
1997 if (!no_gpio2) {
1998 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1999 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2000 grc_local_ctrl, 100);
1da177e4
LT		 2001 }
2002 }
2003 } else {
2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2005 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2006 if (tp_peer != tp &&
2007 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2008 return;
2009
b401e9e2
MC		 2010 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2011 (GRC_LCLCTRL_GPIO_OE1 |
2012 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2013
b401e9e2
MC		 2014 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2015 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2016
b401e9e2
MC		 2017 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2018 (GRC_LCLCTRL_GPIO_OE1 |
2019 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2020 }
2021 }
2022}
2023
e8f3f6ca
MC		 2024static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2025{
2026 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2027 return 1;
2028 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2029 if (speed != SPEED_10)
2030 return 1;
2031 } else if (speed == SPEED_10)
2032 return 1;
2033
2034 return 0;
2035}
2036
1da177e4
LT		 2037static int tg3_setup_phy(struct tg3 *, int);
2038
2039#define RESET_KIND_SHUTDOWN 0
2040#define RESET_KIND_INIT 1
2041#define RESET_KIND_SUSPEND 2
2042
2043static void tg3_write_sig_post_reset(struct tg3 *, int);
2044static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 2045static int tg3_nvram_lock(struct tg3 *);
2046static void tg3_nvram_unlock(struct tg3 *);
1da177e4 2047
0a459aac 2048static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2049{
ce057f01
MC		 2050 u32 val;
2051
5129724a
MC		 2052 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2054 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2055 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2056
2057 sg_dig_ctrl |=
2058 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2059 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2060 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2061 }
3f7045c1 2062 return;
5129724a 2063 }
3f7045c1 2064
60189ddf 2065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2066 tg3_bmcr_reset(tp);
2067 val = tr32(GRC_MISC_CFG);
2068 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2069 udelay(40);
2070 return;
0a459aac 2071 } else if (do_low_power) {
715116a1
MC		 2072 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2073 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2074
2075 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2076 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2077 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2078 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2079 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2080 }
3f7045c1 2081
15c3b696
MC		 2082 /* The PHY should not be powered down on some chips because
2083 * of bugs.
2084 */
2085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2087 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2088 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2089 return;
ce057f01 2090
bcb37f6c
MC		 2091 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2092 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2093 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2094 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2095 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2096 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2097 }
2098
15c3b696
MC		 2099 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2100}
2101
3f007891
MC		 2102/* tp->lock is held. */
2103static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2104{
2105 u32 addr_high, addr_low;
2106 int i;
2107
2108 addr_high = ((tp->dev->dev_addr[0] << 8) |
2109 tp->dev->dev_addr[1]);
2110 addr_low = ((tp->dev->dev_addr[2] << 24) |
2111 (tp->dev->dev_addr[3] << 16) |
2112 (tp->dev->dev_addr[4] << 8) |
2113 (tp->dev->dev_addr[5] << 0));
2114 for (i = 0; i < 4; i++) {
2115 if (i == 1 && skip_mac_1)
2116 continue;
2117 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2118 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2119 }
2120
2121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2123 for (i = 0; i < 12; i++) {
2124 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2125 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2126 }
2127 }
2128
2129 addr_high = (tp->dev->dev_addr[0] +
2130 tp->dev->dev_addr[1] +
2131 tp->dev->dev_addr[2] +
2132 tp->dev->dev_addr[3] +
2133 tp->dev->dev_addr[4] +
2134 tp->dev->dev_addr[5]) &
2135 TX_BACKOFF_SEED_MASK;
2136 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2137}
2138
bc1c7567 2139static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2140{
2141 u32 misc_host_ctrl;
0a459aac 2142 bool device_should_wake, do_low_power;
1da177e4
LT		 2143
2144 /* Make sure register accesses (indirect or otherwise)
2145 * will function correctly.
2146 */
2147 pci_write_config_dword(tp->pdev,
2148 TG3PCI_MISC_HOST_CTRL,
2149 tp->misc_host_ctrl);
2150
1da177e4 2151 switch (state) {
bc1c7567 2152 case PCI_D0:
12dac075
RW		 2153 pci_enable_wake(tp->pdev, state, false);
2154 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2155
9d26e213
MC		 2156 /* Switch out of Vaux if it is a NIC */
2157 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2159
2160 return 0;
2161
bc1c7567 2162 case PCI_D1:
bc1c7567 2163 case PCI_D2:
bc1c7567 2164 case PCI_D3hot:
1da177e4
LT		 2165 break;
2166
2167 default:
12dac075
RW		 2168 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2169 tp->dev->name, state);
1da177e4 2170 return -EINVAL;
855e1111 2171 }
5e7dfd0f
MC		 2172
2173 /* Restore the CLKREQ setting. */
2174 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2175 u16 lnkctl;
2176
2177 pci_read_config_word(tp->pdev,
2178 tp->pcie_cap + PCI_EXP_LNKCTL,
2179 &lnkctl);
2180 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2181 pci_write_config_word(tp->pdev,
2182 tp->pcie_cap + PCI_EXP_LNKCTL,
2183 lnkctl);
2184 }
2185
1da177e4
LT		 2186 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2187 tw32(TG3PCI_MISC_HOST_CTRL,
2188 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2189
05ac4cb7
MC		 2190 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2191 device_may_wakeup(&tp->pdev->dev) &&
2192 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2193
dd477003 2194 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2195 do_low_power = false;
b02fd9e3
MC		 2196 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2197 !tp->link_config.phy_is_low_power) {
2198 struct phy_device *phydev;
0a459aac 2199 u32 phyid, advertising;
b02fd9e3 2200
298cf9be 2201 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2202
2203 tp->link_config.phy_is_low_power = 1;
2204
2205 tp->link_config.orig_speed = phydev->speed;
2206 tp->link_config.orig_duplex = phydev->duplex;
2207 tp->link_config.orig_autoneg = phydev->autoneg;
2208 tp->link_config.orig_advertising = phydev->advertising;
2209
2210 advertising = ADVERTISED_TP |
2211 ADVERTISED_Pause |
2212 ADVERTISED_Autoneg |
2213 ADVERTISED_10baseT_Half;
2214
2215 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2216 device_should_wake) {
b02fd9e3
MC		 2217 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2218 advertising |=
2219 ADVERTISED_100baseT_Half |
2220 ADVERTISED_100baseT_Full |
2221 ADVERTISED_10baseT_Full;
2222 else
2223 advertising |= ADVERTISED_10baseT_Full;
2224 }
2225
2226 phydev->advertising = advertising;
2227
2228 phy_start_aneg(phydev);
0a459aac
MC		 2229
2230 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2231 if (phyid != TG3_PHY_ID_BCMAC131) {
2232 phyid &= TG3_PHY_OUI_MASK;
2233 if (phyid == TG3_PHY_OUI_1 &&
2234 phyid == TG3_PHY_OUI_2 &&
2235 phyid == TG3_PHY_OUI_3)
2236 do_low_power = true;
2237 }
b02fd9e3 2238 }
dd477003 2239 } else {
0a459aac
MC		 2240 do_low_power = false;
2241
dd477003
MC		 2242 if (tp->link_config.phy_is_low_power == 0) {
2243 tp->link_config.phy_is_low_power = 1;
2244 tp->link_config.orig_speed = tp->link_config.speed;
2245 tp->link_config.orig_duplex = tp->link_config.duplex;
2246 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2247 }
1da177e4 2248
dd477003
MC		 2249 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2250 tp->link_config.speed = SPEED_10;
2251 tp->link_config.duplex = DUPLEX_HALF;
2252 tp->link_config.autoneg = AUTONEG_ENABLE;
2253 tg3_setup_phy(tp, 0);
2254 }
1da177e4
LT		 2255 }
2256
3f007891
MC		 2257 __tg3_set_mac_addr(tp, 0);
2258
b5d3772c
MC		 2259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2260 u32 val;
2261
2262 val = tr32(GRC_VCPU_EXT_CTRL);
2263 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2264 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2265 int i;
2266 u32 val;
2267
2268 for (i = 0; i < 200; i++) {
2269 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2270 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2271 break;
2272 msleep(1);
2273 }
2274 }
a85feb8c
GZ		 2275 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2276 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2277 WOL_DRV_STATE_SHUTDOWN |
2278 WOL_DRV_WOL |
2279 WOL_SET_MAGIC_PKT);
6921d201 2280
05ac4cb7 2281 if (device_should_wake) {
1da177e4
LT		 2282 u32 mac_mode;
2283
2284 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2285 if (do_low_power) {
dd477003
MC		 2286 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2287 udelay(40);
2288 }
1da177e4 2289
3f7045c1
MC		 2290 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2291 mac_mode = MAC_MODE_PORT_MODE_GMII;
2292 else
2293 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2294
e8f3f6ca
MC		 2295 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2296 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2297 ASIC_REV_5700) {
2298 u32 speed = (tp->tg3_flags &
2299 TG3_FLAG_WOL_SPEED_100MB) ?
2300 SPEED_100 : SPEED_10;
2301 if (tg3_5700_link_polarity(tp, speed))
2302 mac_mode |= MAC_MODE_LINK_POLARITY;
2303 else
2304 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2305 }
1da177e4
LT		 2306 } else {
2307 mac_mode = MAC_MODE_PORT_MODE_TBI;
2308 }
2309
cbf46853 2310 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2311 tw32(MAC_LED_CTRL, tp->led_ctrl);
2312
05ac4cb7
MC		 2313 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2314 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2315 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2316 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2317 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2318 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2319
3bda1258
MC		 2320 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2321 mac_mode |= tp->mac_mode &
2322 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2323 if (mac_mode & MAC_MODE_APE_TX_EN)
2324 mac_mode |= MAC_MODE_TDE_ENABLE;
2325 }
2326
1da177e4
LT		 2327 tw32_f(MAC_MODE, mac_mode);
2328 udelay(100);
2329
2330 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2331 udelay(10);
2332 }
2333
2334 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2335 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2337 u32 base_val;
2338
2339 base_val = tp->pci_clock_ctrl;
2340 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2341 CLOCK_CTRL_TXCLK_DISABLE);
2342
b401e9e2
MC		 2343 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2344 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2345 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2346 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2347 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2348 /* do nothing */
85e94ced 2349 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2350 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2351 u32 newbits1, newbits2;
2352
2353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2355 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2356 CLOCK_CTRL_TXCLK_DISABLE |
2357 CLOCK_CTRL_ALTCLK);
2358 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2359 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2360 newbits1 = CLOCK_CTRL_625_CORE;
2361 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2362 } else {
2363 newbits1 = CLOCK_CTRL_ALTCLK;
2364 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2365 }
2366
b401e9e2
MC		 2367 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2368 40);
1da177e4 2369
b401e9e2
MC		 2370 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2371 40);
1da177e4
LT		 2372
2373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2374 u32 newbits3;
2375
2376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2378 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2379 CLOCK_CTRL_TXCLK_DISABLE |
2380 CLOCK_CTRL_44MHZ_CORE);
2381 } else {
2382 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2383 }
2384
b401e9e2
MC		 2385 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2386 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2387 }
2388 }
2389
05ac4cb7 2390 if (!(device_should_wake) &&
22435849 2391 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2392 tg3_power_down_phy(tp, do_low_power);
6921d201 2393
1da177e4
LT		 2394 tg3_frob_aux_power(tp);
2395
2396 /* Workaround for unstable PLL clock */
2397 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2398 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2399 u32 val = tr32(0x7d00);
2400
2401 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2402 tw32(0x7d00, val);
6921d201 2403 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2404 int err;
2405
2406 err = tg3_nvram_lock(tp);
1da177e4 2407 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2408 if (!err)
2409 tg3_nvram_unlock(tp);
6921d201 2410 }
1da177e4
LT		 2411 }
2412
bbadf503
MC		 2413 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2414
05ac4cb7 2415 if (device_should_wake)
12dac075
RW		 2416 pci_enable_wake(tp->pdev, state, true);
2417
1da177e4 2418 /* Finally, set the new power state. */
12dac075 2419 pci_set_power_state(tp->pdev, state);
1da177e4 2420
1da177e4
LT		 2421 return 0;
2422}
2423
1da177e4
LT		 2424static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2425{
2426 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2427 case MII_TG3_AUX_STAT_10HALF:
2428 *speed = SPEED_10;
2429 *duplex = DUPLEX_HALF;
2430 break;
2431
2432 case MII_TG3_AUX_STAT_10FULL:
2433 *speed = SPEED_10;
2434 *duplex = DUPLEX_FULL;
2435 break;
2436
2437 case MII_TG3_AUX_STAT_100HALF:
2438 *speed = SPEED_100;
2439 *duplex = DUPLEX_HALF;
2440 break;
2441
2442 case MII_TG3_AUX_STAT_100FULL:
2443 *speed = SPEED_100;
2444 *duplex = DUPLEX_FULL;
2445 break;
2446
2447 case MII_TG3_AUX_STAT_1000HALF:
2448 *speed = SPEED_1000;
2449 *duplex = DUPLEX_HALF;
2450 break;
2451
2452 case MII_TG3_AUX_STAT_1000FULL:
2453 *speed = SPEED_1000;
2454 *duplex = DUPLEX_FULL;
2455 break;
2456
2457 default:
715116a1
MC		 2458 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2459 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2460 SPEED_10;
2461 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2462 DUPLEX_HALF;
2463 break;
2464 }
1da177e4
LT		 2465 *speed = SPEED_INVALID;
2466 *duplex = DUPLEX_INVALID;
2467 break;
855e1111 2468 }
1da177e4
LT		 2469}
2470
2471static void tg3_phy_copper_begin(struct tg3 *tp)
2472{
2473 u32 new_adv;
2474 int i;
2475
2476 if (tp->link_config.phy_is_low_power) {
2477 /* Entering low power mode. Disable gigabit and
2478 * 100baseT advertisements.
2479 */
2480 tg3_writephy(tp, MII_TG3_CTRL, 0);
2481
2482 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2483 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2484 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2485 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2486
2487 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2488 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2489 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2490 tp->link_config.advertising &=
2491 ~(ADVERTISED_1000baseT_Half |
2492 ADVERTISED_1000baseT_Full);
2493
ba4d07a8 2494 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2495 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2496 new_adv |= ADVERTISE_10HALF;
2497 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2498 new_adv |= ADVERTISE_10FULL;
2499 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2500 new_adv |= ADVERTISE_100HALF;
2501 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2502 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2503
2504 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2505
1da177e4
LT		 2506 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2507
2508 if (tp->link_config.advertising &
2509 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2510 new_adv = 0;
2511 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2512 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2513 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2514 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2515 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2516 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2517 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2518 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2519 MII_TG3_CTRL_ENABLE_AS_MASTER);
2520 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2521 } else {
2522 tg3_writephy(tp, MII_TG3_CTRL, 0);
2523 }
2524 } else {
ba4d07a8
MC		 2525 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2526 new_adv |= ADVERTISE_CSMA;
2527
1da177e4
LT		 2528 /* Asking for a specific link mode. */
2529 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2530 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2531
2532 if (tp->link_config.duplex == DUPLEX_FULL)
2533 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2534 else
2535 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2536 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2537 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2538 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2539 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2540 } else {
1da177e4
LT		 2541 if (tp->link_config.speed == SPEED_100) {
2542 if (tp->link_config.duplex == DUPLEX_FULL)
2543 new_adv |= ADVERTISE_100FULL;
2544 else
2545 new_adv |= ADVERTISE_100HALF;
2546 } else {
2547 if (tp->link_config.duplex == DUPLEX_FULL)
2548 new_adv |= ADVERTISE_10FULL;
2549 else
2550 new_adv |= ADVERTISE_10HALF;
2551 }
2552 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2553
2554 new_adv = 0;
1da177e4 2555 }
ba4d07a8
MC		 2556
2557 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2558 }
2559
2560 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2561 tp->link_config.speed != SPEED_INVALID) {
2562 u32 bmcr, orig_bmcr;
2563
2564 tp->link_config.active_speed = tp->link_config.speed;
2565 tp->link_config.active_duplex = tp->link_config.duplex;
2566
2567 bmcr = 0;
2568 switch (tp->link_config.speed) {
2569 default:
2570 case SPEED_10:
2571 break;
2572
2573 case SPEED_100:
2574 bmcr |= BMCR_SPEED100;
2575 break;
2576
2577 case SPEED_1000:
2578 bmcr |= TG3_BMCR_SPEED1000;
2579 break;
855e1111 2580 }
1da177e4
LT		 2581
2582 if (tp->link_config.duplex == DUPLEX_FULL)
2583 bmcr |= BMCR_FULLDPLX;
2584
2585 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2586 (bmcr != orig_bmcr)) {
2587 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2588 for (i = 0; i < 1500; i++) {
2589 u32 tmp;
2590
2591 udelay(10);
2592 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2593 tg3_readphy(tp, MII_BMSR, &tmp))
2594 continue;
2595 if (!(tmp & BMSR_LSTATUS)) {
2596 udelay(40);
2597 break;
2598 }
2599 }
2600 tg3_writephy(tp, MII_BMCR, bmcr);
2601 udelay(40);
2602 }
2603 } else {
2604 tg3_writephy(tp, MII_BMCR,
2605 BMCR_ANENABLE | BMCR_ANRESTART);
2606 }
2607}
2608
2609static int tg3_init_5401phy_dsp(struct tg3 *tp)
2610{
2611 int err;
2612
2613 /* Turn off tap power management. */
2614 /* Set Extended packet length bit */
2615 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2616
2617 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2618 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2619
2620 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2621 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2622
2623 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2624 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2625
2626 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2627 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2628
2629 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2630 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2631
2632 udelay(40);
2633
2634 return err;
2635}
2636
3600d918 2637static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2638{
3600d918
MC		 2639 u32 adv_reg, all_mask = 0;
2640
2641 if (mask & ADVERTISED_10baseT_Half)
2642 all_mask |= ADVERTISE_10HALF;
2643 if (mask & ADVERTISED_10baseT_Full)
2644 all_mask |= ADVERTISE_10FULL;
2645 if (mask & ADVERTISED_100baseT_Half)
2646 all_mask |= ADVERTISE_100HALF;
2647 if (mask & ADVERTISED_100baseT_Full)
2648 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2649
2650 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2651 return 0;
2652
1da177e4
LT		 2653 if ((adv_reg & all_mask) != all_mask)
2654 return 0;
2655 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2656 u32 tg3_ctrl;
2657
3600d918
MC		 2658 all_mask = 0;
2659 if (mask & ADVERTISED_1000baseT_Half)
2660 all_mask |= ADVERTISE_1000HALF;
2661 if (mask & ADVERTISED_1000baseT_Full)
2662 all_mask |= ADVERTISE_1000FULL;
2663
1da177e4
LT		 2664 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2665 return 0;
2666
1da177e4
LT		 2667 if ((tg3_ctrl & all_mask) != all_mask)
2668 return 0;
2669 }
2670 return 1;
2671}
2672
ef167e27
MC		 2673static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2674{
2675 u32 curadv, reqadv;
2676
2677 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2678 return 1;
2679
2680 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2681 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2682
2683 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2684 if (curadv != reqadv)
2685 return 0;
2686
2687 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2688 tg3_readphy(tp, MII_LPA, rmtadv);
2689 } else {
2690 /* Reprogram the advertisement register, even if it
2691 * does not affect the current link. If the link
2692 * gets renegotiated in the future, we can save an
2693 * additional renegotiation cycle by advertising
2694 * it correctly in the first place.
2695 */
2696 if (curadv != reqadv) {
2697 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2698 ADVERTISE_PAUSE_ASYM);
2699 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2700 }
2701 }
2702
2703 return 1;
2704}
2705
1da177e4
LT		 2706static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2707{
2708 int current_link_up;
2709 u32 bmsr, dummy;
ef167e27 2710 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2711 u16 current_speed;
2712 u8 current_duplex;
2713 int i, err;
2714
2715 tw32(MAC_EVENT, 0);
2716
2717 tw32_f(MAC_STATUS,
2718 (MAC_STATUS_SYNC_CHANGED |
2719 MAC_STATUS_CFG_CHANGED |
2720 MAC_STATUS_MI_COMPLETION |
2721 MAC_STATUS_LNKSTATE_CHANGED));
2722 udelay(40);
2723
8ef21428
MC		 2724 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2725 tw32_f(MAC_MI_MODE,
2726 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2727 udelay(80);
2728 }
1da177e4
LT		 2729
2730 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2731
2732 /* Some third-party PHYs need to be reset on link going
2733 * down.
2734 */
2735 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2736 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2738 netif_carrier_ok(tp->dev)) {
2739 tg3_readphy(tp, MII_BMSR, &bmsr);
2740 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2741 !(bmsr & BMSR_LSTATUS))
2742 force_reset = 1;
2743 }
2744 if (force_reset)
2745 tg3_phy_reset(tp);
2746
2747 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2748 tg3_readphy(tp, MII_BMSR, &bmsr);
2749 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2750 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2751 bmsr = 0;
2752
2753 if (!(bmsr & BMSR_LSTATUS)) {
2754 err = tg3_init_5401phy_dsp(tp);
2755 if (err)
2756 return err;
2757
2758 tg3_readphy(tp, MII_BMSR, &bmsr);
2759 for (i = 0; i < 1000; i++) {
2760 udelay(10);
2761 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2762 (bmsr & BMSR_LSTATUS)) {
2763 udelay(40);
2764 break;
2765 }
2766 }
2767
2768 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2769 !(bmsr & BMSR_LSTATUS) &&
2770 tp->link_config.active_speed == SPEED_1000) {
2771 err = tg3_phy_reset(tp);
2772 if (!err)
2773 err = tg3_init_5401phy_dsp(tp);
2774 if (err)
2775 return err;
2776 }
2777 }
2778 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2780 /* 5701 {A0,B0} CRC bug workaround */
2781 tg3_writephy(tp, 0x15, 0x0a75);
2782 tg3_writephy(tp, 0x1c, 0x8c68);
2783 tg3_writephy(tp, 0x1c, 0x8d68);
2784 tg3_writephy(tp, 0x1c, 0x8c68);
2785 }
2786
2787 /* Clear pending interrupts... */
2788 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2789 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2790
2791 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2792 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2793 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2794 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2795
2796 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2797 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2798 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2799 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2800 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2801 else
2802 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2803 }
2804
2805 current_link_up = 0;
2806 current_speed = SPEED_INVALID;
2807 current_duplex = DUPLEX_INVALID;
2808
2809 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2810 u32 val;
2811
2812 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2813 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2814 if (!(val & (1 << 10))) {
2815 val |= (1 << 10);
2816 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2817 goto relink;
2818 }
2819 }
2820
2821 bmsr = 0;
2822 for (i = 0; i < 100; i++) {
2823 tg3_readphy(tp, MII_BMSR, &bmsr);
2824 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2825 (bmsr & BMSR_LSTATUS))
2826 break;
2827 udelay(40);
2828 }
2829
2830 if (bmsr & BMSR_LSTATUS) {
2831 u32 aux_stat, bmcr;
2832
2833 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2834 for (i = 0; i < 2000; i++) {
2835 udelay(10);
2836 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2837 aux_stat)
2838 break;
2839 }
2840
2841 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2842 &current_speed,
2843 &current_duplex);
2844
2845 bmcr = 0;
2846 for (i = 0; i < 200; i++) {
2847 tg3_readphy(tp, MII_BMCR, &bmcr);
2848 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2849 continue;
2850 if (bmcr && bmcr != 0x7fff)
2851 break;
2852 udelay(10);
2853 }
2854
ef167e27
MC		 2855 lcl_adv = 0;
2856 rmt_adv = 0;
1da177e4 2857
ef167e27
MC		 2858 tp->link_config.active_speed = current_speed;
2859 tp->link_config.active_duplex = current_duplex;
2860
2861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2862 if ((bmcr & BMCR_ANENABLE) &&
2863 tg3_copper_is_advertising_all(tp,
2864 tp->link_config.advertising)) {
2865 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2866 &rmt_adv))
2867 current_link_up = 1;
1da177e4
LT		 2868 }
2869 } else {
2870 if (!(bmcr & BMCR_ANENABLE) &&
2871 tp->link_config.speed == current_speed &&
ef167e27
MC		 2872 tp->link_config.duplex == current_duplex &&
2873 tp->link_config.flowctrl ==
2874 tp->link_config.active_flowctrl) {
1da177e4 2875 current_link_up = 1;
1da177e4
LT		 2876 }
2877 }
2878
ef167e27
MC		 2879 if (current_link_up == 1 &&
2880 tp->link_config.active_duplex == DUPLEX_FULL)
2881 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 2882 }
2883
1da177e4 2884relink:
6921d201 2885 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 2886 u32 tmp;
2887
2888 tg3_phy_copper_begin(tp);
2889
2890 tg3_readphy(tp, MII_BMSR, &tmp);
2891 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2892 (tmp & BMSR_LSTATUS))
2893 current_link_up = 1;
2894 }
2895
2896 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2897 if (current_link_up == 1) {
2898 if (tp->link_config.active_speed == SPEED_100 ||
2899 tp->link_config.active_speed == SPEED_10)
2900 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2901 else
2902 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2903 } else
2904 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2905
2906 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2907 if (tp->link_config.active_duplex == DUPLEX_HALF)
2908 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2909
1da177e4 2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 2911 if (current_link_up == 1 &&
2912 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 2913 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 2914 else
2915 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 2916 }
2917
2918 /* ??? Without this setting Netgear GA302T PHY does not
2919 * ??? send/receive packets...
2920 */
2921 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2922 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2923 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2924 tw32_f(MAC_MI_MODE, tp->mi_mode);
2925 udelay(80);
2926 }
2927
2928 tw32_f(MAC_MODE, tp->mac_mode);
2929 udelay(40);
2930
2931 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2932 /* Polled via timer. */
2933 tw32_f(MAC_EVENT, 0);
2934 } else {
2935 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2936 }
2937 udelay(40);
2938
2939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2940 current_link_up == 1 &&
2941 tp->link_config.active_speed == SPEED_1000 &&
2942 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2943 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2944 udelay(120);
2945 tw32_f(MAC_STATUS,
2946 (MAC_STATUS_SYNC_CHANGED |
2947 MAC_STATUS_CFG_CHANGED));
2948 udelay(40);
2949 tg3_write_mem(tp,
2950 NIC_SRAM_FIRMWARE_MBOX,
2951 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2952 }
2953
5e7dfd0f
MC		 2954 /* Prevent send BD corruption. */
2955 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2956 u16 oldlnkctl, newlnkctl;
2957
2958 pci_read_config_word(tp->pdev,
2959 tp->pcie_cap + PCI_EXP_LNKCTL,
2960 &oldlnkctl);
2961 if (tp->link_config.active_speed == SPEED_100 ||
2962 tp->link_config.active_speed == SPEED_10)
2963 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2964 else
2965 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2966 if (newlnkctl != oldlnkctl)
2967 pci_write_config_word(tp->pdev,
2968 tp->pcie_cap + PCI_EXP_LNKCTL,
2969 newlnkctl);
2970 }
2971
1da177e4
LT		 2972 if (current_link_up != netif_carrier_ok(tp->dev)) {
2973 if (current_link_up)
2974 netif_carrier_on(tp->dev);
2975 else
2976 netif_carrier_off(tp->dev);
2977 tg3_link_report(tp);
2978 }
2979
2980 return 0;
2981}
2982
2983struct tg3_fiber_aneginfo {
2984 int state;
2985#define ANEG_STATE_UNKNOWN 0
2986#define ANEG_STATE_AN_ENABLE 1
2987#define ANEG_STATE_RESTART_INIT 2
2988#define ANEG_STATE_RESTART 3
2989#define ANEG_STATE_DISABLE_LINK_OK 4
2990#define ANEG_STATE_ABILITY_DETECT_INIT 5
2991#define ANEG_STATE_ABILITY_DETECT 6
2992#define ANEG_STATE_ACK_DETECT_INIT 7
2993#define ANEG_STATE_ACK_DETECT 8
2994#define ANEG_STATE_COMPLETE_ACK_INIT 9
2995#define ANEG_STATE_COMPLETE_ACK 10
2996#define ANEG_STATE_IDLE_DETECT_INIT 11
2997#define ANEG_STATE_IDLE_DETECT 12
2998#define ANEG_STATE_LINK_OK 13
2999#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3000#define ANEG_STATE_NEXT_PAGE_WAIT 15
3001
3002 u32 flags;
3003#define MR_AN_ENABLE 0x00000001
3004#define MR_RESTART_AN 0x00000002
3005#define MR_AN_COMPLETE 0x00000004
3006#define MR_PAGE_RX 0x00000008
3007#define MR_NP_LOADED 0x00000010
3008#define MR_TOGGLE_TX 0x00000020
3009#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3010#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3011#define MR_LP_ADV_SYM_PAUSE 0x00000100
3012#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3013#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3014#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3015#define MR_LP_ADV_NEXT_PAGE 0x00001000
3016#define MR_TOGGLE_RX 0x00002000
3017#define MR_NP_RX 0x00004000
3018
3019#define MR_LINK_OK 0x80000000
3020
3021 unsigned long link_time, cur_time;
3022
3023 u32 ability_match_cfg;
3024 int ability_match_count;
3025
3026 char ability_match, idle_match, ack_match;
3027
3028 u32 txconfig, rxconfig;
3029#define ANEG_CFG_NP 0x00000080
3030#define ANEG_CFG_ACK 0x00000040
3031#define ANEG_CFG_RF2 0x00000020
3032#define ANEG_CFG_RF1 0x00000010
3033#define ANEG_CFG_PS2 0x00000001
3034#define ANEG_CFG_PS1 0x00008000
3035#define ANEG_CFG_HD 0x00004000
3036#define ANEG_CFG_FD 0x00002000
3037#define ANEG_CFG_INVAL 0x00001f06
3038
3039};
3040#define ANEG_OK 0
3041#define ANEG_DONE 1
3042#define ANEG_TIMER_ENAB 2
3043#define ANEG_FAILED -1
3044
3045#define ANEG_STATE_SETTLE_TIME 10000
3046
3047static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3048 struct tg3_fiber_aneginfo *ap)
3049{
5be73b47 3050 u16 flowctrl;
1da177e4
LT		 3051 unsigned long delta;
3052 u32 rx_cfg_reg;
3053 int ret;
3054
3055 if (ap->state == ANEG_STATE_UNKNOWN) {
3056 ap->rxconfig = 0;
3057 ap->link_time = 0;
3058 ap->cur_time = 0;
3059 ap->ability_match_cfg = 0;
3060 ap->ability_match_count = 0;
3061 ap->ability_match = 0;
3062 ap->idle_match = 0;
3063 ap->ack_match = 0;
3064 }
3065 ap->cur_time++;
3066
3067 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3068 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3069
3070 if (rx_cfg_reg != ap->ability_match_cfg) {
3071 ap->ability_match_cfg = rx_cfg_reg;
3072 ap->ability_match = 0;
3073 ap->ability_match_count = 0;
3074 } else {
3075 if (++ap->ability_match_count > 1) {
3076 ap->ability_match = 1;
3077 ap->ability_match_cfg = rx_cfg_reg;
3078 }
3079 }
3080 if (rx_cfg_reg & ANEG_CFG_ACK)
3081 ap->ack_match = 1;
3082 else
3083 ap->ack_match = 0;
3084
3085 ap->idle_match = 0;
3086 } else {
3087 ap->idle_match = 1;
3088 ap->ability_match_cfg = 0;
3089 ap->ability_match_count = 0;
3090 ap->ability_match = 0;
3091 ap->ack_match = 0;
3092
3093 rx_cfg_reg = 0;
3094 }
3095
3096 ap->rxconfig = rx_cfg_reg;
3097 ret = ANEG_OK;
3098
3099 switch(ap->state) {
3100 case ANEG_STATE_UNKNOWN:
3101 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3102 ap->state = ANEG_STATE_AN_ENABLE;
3103
3104 /* fallthru */
3105 case ANEG_STATE_AN_ENABLE:
3106 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3107 if (ap->flags & MR_AN_ENABLE) {
3108 ap->link_time = 0;
3109 ap->cur_time = 0;
3110 ap->ability_match_cfg = 0;
3111 ap->ability_match_count = 0;
3112 ap->ability_match = 0;
3113 ap->idle_match = 0;
3114 ap->ack_match = 0;
3115
3116 ap->state = ANEG_STATE_RESTART_INIT;
3117 } else {
3118 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3119 }
3120 break;
3121
3122 case ANEG_STATE_RESTART_INIT:
3123 ap->link_time = ap->cur_time;
3124 ap->flags &= ~(MR_NP_LOADED);
3125 ap->txconfig = 0;
3126 tw32(MAC_TX_AUTO_NEG, 0);
3127 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3128 tw32_f(MAC_MODE, tp->mac_mode);
3129 udelay(40);
3130
3131 ret = ANEG_TIMER_ENAB;
3132 ap->state = ANEG_STATE_RESTART;
3133
3134 /* fallthru */
3135 case ANEG_STATE_RESTART:
3136 delta = ap->cur_time - ap->link_time;
3137 if (delta > ANEG_STATE_SETTLE_TIME) {
3138 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3139 } else {
3140 ret = ANEG_TIMER_ENAB;
3141 }
3142 break;
3143
3144 case ANEG_STATE_DISABLE_LINK_OK:
3145 ret = ANEG_DONE;
3146 break;
3147
3148 case ANEG_STATE_ABILITY_DETECT_INIT:
3149 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3150 ap->txconfig = ANEG_CFG_FD;
3151 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3152 if (flowctrl & ADVERTISE_1000XPAUSE)
3153 ap->txconfig |= ANEG_CFG_PS1;
3154 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3155 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3156 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3157 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3158 tw32_f(MAC_MODE, tp->mac_mode);
3159 udelay(40);
3160
3161 ap->state = ANEG_STATE_ABILITY_DETECT;
3162 break;
3163
3164 case ANEG_STATE_ABILITY_DETECT:
3165 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3166 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3167 }
3168 break;
3169
3170 case ANEG_STATE_ACK_DETECT_INIT:
3171 ap->txconfig |= ANEG_CFG_ACK;
3172 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3173 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3174 tw32_f(MAC_MODE, tp->mac_mode);
3175 udelay(40);
3176
3177 ap->state = ANEG_STATE_ACK_DETECT;
3178
3179 /* fallthru */
3180 case ANEG_STATE_ACK_DETECT:
3181 if (ap->ack_match != 0) {
3182 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3183 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3184 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3185 } else {
3186 ap->state = ANEG_STATE_AN_ENABLE;
3187 }
3188 } else if (ap->ability_match != 0 &&
3189 ap->rxconfig == 0) {
3190 ap->state = ANEG_STATE_AN_ENABLE;
3191 }
3192 break;
3193
3194 case ANEG_STATE_COMPLETE_ACK_INIT:
3195 if (ap->rxconfig & ANEG_CFG_INVAL) {
3196 ret = ANEG_FAILED;
3197 break;
3198 }
3199 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3200 MR_LP_ADV_HALF_DUPLEX |
3201 MR_LP_ADV_SYM_PAUSE |
3202 MR_LP_ADV_ASYM_PAUSE |
3203 MR_LP_ADV_REMOTE_FAULT1 |
3204 MR_LP_ADV_REMOTE_FAULT2 |
3205 MR_LP_ADV_NEXT_PAGE |
3206 MR_TOGGLE_RX |
3207 MR_NP_RX);
3208 if (ap->rxconfig & ANEG_CFG_FD)
3209 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3210 if (ap->rxconfig & ANEG_CFG_HD)
3211 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3212 if (ap->rxconfig & ANEG_CFG_PS1)
3213 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3214 if (ap->rxconfig & ANEG_CFG_PS2)
3215 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3216 if (ap->rxconfig & ANEG_CFG_RF1)
3217 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3218 if (ap->rxconfig & ANEG_CFG_RF2)
3219 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3220 if (ap->rxconfig & ANEG_CFG_NP)
3221 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3222
3223 ap->link_time = ap->cur_time;
3224
3225 ap->flags ^= (MR_TOGGLE_TX);
3226 if (ap->rxconfig & 0x0008)
3227 ap->flags |= MR_TOGGLE_RX;
3228 if (ap->rxconfig & ANEG_CFG_NP)
3229 ap->flags |= MR_NP_RX;
3230 ap->flags |= MR_PAGE_RX;
3231
3232 ap->state = ANEG_STATE_COMPLETE_ACK;
3233 ret = ANEG_TIMER_ENAB;
3234 break;
3235
3236 case ANEG_STATE_COMPLETE_ACK:
3237 if (ap->ability_match != 0 &&
3238 ap->rxconfig == 0) {
3239 ap->state = ANEG_STATE_AN_ENABLE;
3240 break;
3241 }
3242 delta = ap->cur_time - ap->link_time;
3243 if (delta > ANEG_STATE_SETTLE_TIME) {
3244 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3245 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3246 } else {
3247 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3248 !(ap->flags & MR_NP_RX)) {
3249 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3250 } else {
3251 ret = ANEG_FAILED;
3252 }
3253 }
3254 }
3255 break;
3256
3257 case ANEG_STATE_IDLE_DETECT_INIT:
3258 ap->link_time = ap->cur_time;
3259 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3260 tw32_f(MAC_MODE, tp->mac_mode);
3261 udelay(40);
3262
3263 ap->state = ANEG_STATE_IDLE_DETECT;
3264 ret = ANEG_TIMER_ENAB;
3265 break;
3266
3267 case ANEG_STATE_IDLE_DETECT:
3268 if (ap->ability_match != 0 &&
3269 ap->rxconfig == 0) {
3270 ap->state = ANEG_STATE_AN_ENABLE;
3271 break;
3272 }
3273 delta = ap->cur_time - ap->link_time;
3274 if (delta > ANEG_STATE_SETTLE_TIME) {
3275 /* XXX another gem from the Broadcom driver :( */
3276 ap->state = ANEG_STATE_LINK_OK;
3277 }
3278 break;
3279
3280 case ANEG_STATE_LINK_OK:
3281 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3282 ret = ANEG_DONE;
3283 break;
3284
3285 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3286 /* ??? unimplemented */
3287 break;
3288
3289 case ANEG_STATE_NEXT_PAGE_WAIT:
3290 /* ??? unimplemented */
3291 break;
3292
3293 default:
3294 ret = ANEG_FAILED;
3295 break;
855e1111 3296 }
1da177e4
LT		 3297
3298 return ret;
3299}
3300
5be73b47 3301static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3302{
3303 int res = 0;
3304 struct tg3_fiber_aneginfo aninfo;
3305 int status = ANEG_FAILED;
3306 unsigned int tick;
3307 u32 tmp;
3308
3309 tw32_f(MAC_TX_AUTO_NEG, 0);
3310
3311 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3312 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3313 udelay(40);
3314
3315 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3316 udelay(40);
3317
3318 memset(&aninfo, 0, sizeof(aninfo));
3319 aninfo.flags |= MR_AN_ENABLE;
3320 aninfo.state = ANEG_STATE_UNKNOWN;
3321 aninfo.cur_time = 0;
3322 tick = 0;
3323 while (++tick < 195000) {
3324 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3325 if (status == ANEG_DONE || status == ANEG_FAILED)
3326 break;
3327
3328 udelay(1);
3329 }
3330
3331 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3332 tw32_f(MAC_MODE, tp->mac_mode);
3333 udelay(40);
3334
5be73b47
MC		 3335 *txflags = aninfo.txconfig;
3336 *rxflags = aninfo.flags;
1da177e4
LT		 3337
3338 if (status == ANEG_DONE &&
3339 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3340 MR_LP_ADV_FULL_DUPLEX)))
3341 res = 1;
3342
3343 return res;
3344}
3345
3346static void tg3_init_bcm8002(struct tg3 *tp)
3347{
3348 u32 mac_status = tr32(MAC_STATUS);
3349 int i;
3350
3351 /* Reset when initting first time or we have a link. */
3352 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3353 !(mac_status & MAC_STATUS_PCS_SYNCED))
3354 return;
3355
3356 /* Set PLL lock range. */
3357 tg3_writephy(tp, 0x16, 0x8007);
3358
3359 /* SW reset */
3360 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3361
3362 /* Wait for reset to complete. */
3363 /* XXX schedule_timeout() ... */
3364 for (i = 0; i < 500; i++)
3365 udelay(10);
3366
3367 /* Config mode; select PMA/Ch 1 regs. */
3368 tg3_writephy(tp, 0x10, 0x8411);
3369
3370 /* Enable auto-lock and comdet, select txclk for tx. */
3371 tg3_writephy(tp, 0x11, 0x0a10);
3372
3373 tg3_writephy(tp, 0x18, 0x00a0);
3374 tg3_writephy(tp, 0x16, 0x41ff);
3375
3376 /* Assert and deassert POR. */
3377 tg3_writephy(tp, 0x13, 0x0400);
3378 udelay(40);
3379 tg3_writephy(tp, 0x13, 0x0000);
3380
3381 tg3_writephy(tp, 0x11, 0x0a50);
3382 udelay(40);
3383 tg3_writephy(tp, 0x11, 0x0a10);
3384
3385 /* Wait for signal to stabilize */
3386 /* XXX schedule_timeout() ... */
3387 for (i = 0; i < 15000; i++)
3388 udelay(10);
3389
3390 /* Deselect the channel register so we can read the PHYID
3391 * later.
3392 */
3393 tg3_writephy(tp, 0x10, 0x8011);
3394}
3395
3396static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3397{
82cd3d11 3398 u16 flowctrl;
1da177e4
LT		 3399 u32 sg_dig_ctrl, sg_dig_status;
3400 u32 serdes_cfg, expected_sg_dig_ctrl;
3401 int workaround, port_a;
3402 int current_link_up;
3403
3404 serdes_cfg = 0;
3405 expected_sg_dig_ctrl = 0;
3406 workaround = 0;
3407 port_a = 1;
3408 current_link_up = 0;
3409
3410 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3411 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3412 workaround = 1;
3413 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3414 port_a = 0;
3415
3416 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3417 /* preserve bits 20-23 for voltage regulator */
3418 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3419 }
3420
3421 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3422
3423 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3424 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3425 if (workaround) {
3426 u32 val = serdes_cfg;
3427
3428 if (port_a)
3429 val |= 0xc010000;
3430 else
3431 val |= 0x4010000;
3432 tw32_f(MAC_SERDES_CFG, val);
3433 }
c98f6e3b
MC		 3434
3435 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3436 }
3437 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3438 tg3_setup_flow_control(tp, 0, 0);
3439 current_link_up = 1;
3440 }
3441 goto out;
3442 }
3443
3444 /* Want auto-negotiation. */
c98f6e3b 3445 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3446
82cd3d11
MC		 3447 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3448 if (flowctrl & ADVERTISE_1000XPAUSE)
3449 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3450 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3451 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3452
3453 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3454 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3455 tp->serdes_counter &&
3456 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3457 MAC_STATUS_RCVD_CFG)) ==
3458 MAC_STATUS_PCS_SYNCED)) {
3459 tp->serdes_counter--;
3460 current_link_up = 1;
3461 goto out;
3462 }
3463restart_autoneg:
1da177e4
LT		 3464 if (workaround)
3465 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3466 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3467 udelay(5);
3468 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3469
3d3ebe74
MC		 3470 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3471 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3472 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3473 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3474 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3475 mac_status = tr32(MAC_STATUS);
3476
c98f6e3b 3477 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3478 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3479 u32 local_adv = 0, remote_adv = 0;
3480
3481 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3482 local_adv |= ADVERTISE_1000XPAUSE;
3483 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3484 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3485
c98f6e3b 3486 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3487 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3488 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3489 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3490
3491 tg3_setup_flow_control(tp, local_adv, remote_adv);
3492 current_link_up = 1;
3d3ebe74
MC		 3493 tp->serdes_counter = 0;
3494 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3495 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3496 if (tp->serdes_counter)
3497 tp->serdes_counter--;
1da177e4
LT		 3498 else {
3499 if (workaround) {
3500 u32 val = serdes_cfg;
3501
3502 if (port_a)
3503 val |= 0xc010000;
3504 else
3505 val |= 0x4010000;
3506
3507 tw32_f(MAC_SERDES_CFG, val);
3508 }
3509
c98f6e3b 3510 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3511 udelay(40);
3512
3513 /* Link parallel detection - link is up */
3514 /* only if we have PCS_SYNC and not */
3515 /* receiving config code words */
3516 mac_status = tr32(MAC_STATUS);
3517 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3518 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3519 tg3_setup_flow_control(tp, 0, 0);
3520 current_link_up = 1;
3d3ebe74
MC		 3521 tp->tg3_flags2 |=
3522 TG3_FLG2_PARALLEL_DETECT;
3523 tp->serdes_counter =
3524 SERDES_PARALLEL_DET_TIMEOUT;
3525 } else
3526 goto restart_autoneg;
1da177e4
LT		 3527 }
3528 }
3d3ebe74
MC		 3529 } else {
3530 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3531 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3532 }
3533
3534out:
3535 return current_link_up;
3536}
3537
3538static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3539{
3540 int current_link_up = 0;
3541
5cf64b8a 3542 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3543 goto out;
1da177e4
LT		 3544
3545 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3546 u32 txflags, rxflags;
1da177e4 3547 int i;
6aa20a22 3548
5be73b47
MC		 3549 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3550 u32 local_adv = 0, remote_adv = 0;
1da177e4 3551
5be73b47
MC		 3552 if (txflags & ANEG_CFG_PS1)
3553 local_adv |= ADVERTISE_1000XPAUSE;
3554 if (txflags & ANEG_CFG_PS2)
3555 local_adv |= ADVERTISE_1000XPSE_ASYM;
3556
3557 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3558 remote_adv |= LPA_1000XPAUSE;
3559 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3560 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3561
3562 tg3_setup_flow_control(tp, local_adv, remote_adv);
3563
1da177e4
LT		 3564 current_link_up = 1;
3565 }
3566 for (i = 0; i < 30; i++) {
3567 udelay(20);
3568 tw32_f(MAC_STATUS,
3569 (MAC_STATUS_SYNC_CHANGED |
3570 MAC_STATUS_CFG_CHANGED));
3571 udelay(40);
3572 if ((tr32(MAC_STATUS) &
3573 (MAC_STATUS_SYNC_CHANGED |
3574 MAC_STATUS_CFG_CHANGED)) == 0)
3575 break;
3576 }
3577
3578 mac_status = tr32(MAC_STATUS);
3579 if (current_link_up == 0 &&
3580 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3581 !(mac_status & MAC_STATUS_RCVD_CFG))
3582 current_link_up = 1;
3583 } else {
5be73b47
MC		 3584 tg3_setup_flow_control(tp, 0, 0);
3585
1da177e4
LT		 3586 /* Forcing 1000FD link up. */
3587 current_link_up = 1;
1da177e4
LT		 3588
3589 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3590 udelay(40);
e8f3f6ca
MC		 3591
3592 tw32_f(MAC_MODE, tp->mac_mode);
3593 udelay(40);
1da177e4
LT		 3594 }
3595
3596out:
3597 return current_link_up;
3598}
3599
3600static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3601{
3602 u32 orig_pause_cfg;
3603 u16 orig_active_speed;
3604 u8 orig_active_duplex;
3605 u32 mac_status;
3606 int current_link_up;
3607 int i;
3608
8d018621 3609 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3610 orig_active_speed = tp->link_config.active_speed;
3611 orig_active_duplex = tp->link_config.active_duplex;
3612
3613 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3614 netif_carrier_ok(tp->dev) &&
3615 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3616 mac_status = tr32(MAC_STATUS);
3617 mac_status &= (MAC_STATUS_PCS_SYNCED |
3618 MAC_STATUS_SIGNAL_DET |
3619 MAC_STATUS_CFG_CHANGED |
3620 MAC_STATUS_RCVD_CFG);
3621 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3622 MAC_STATUS_SIGNAL_DET)) {
3623 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3624 MAC_STATUS_CFG_CHANGED));
3625 return 0;
3626 }
3627 }
3628
3629 tw32_f(MAC_TX_AUTO_NEG, 0);
3630
3631 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3632 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3633 tw32_f(MAC_MODE, tp->mac_mode);
3634 udelay(40);
3635
3636 if (tp->phy_id == PHY_ID_BCM8002)
3637 tg3_init_bcm8002(tp);
3638
3639 /* Enable link change event even when serdes polling. */
3640 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3641 udelay(40);
3642
3643 current_link_up = 0;
3644 mac_status = tr32(MAC_STATUS);
3645
3646 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3647 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3648 else
3649 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3650
1da177e4
LT		 3651 tp->hw_status->status =
3652 (SD_STATUS_UPDATED |
3653 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3654
3655 for (i = 0; i < 100; i++) {
3656 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3657 MAC_STATUS_CFG_CHANGED));
3658 udelay(5);
3659 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3660 MAC_STATUS_CFG_CHANGED |
3661 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3662 break;
3663 }
3664
3665 mac_status = tr32(MAC_STATUS);
3666 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3667 current_link_up = 0;
3d3ebe74
MC		 3668 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3669 tp->serdes_counter == 0) {
1da177e4
LT		 3670 tw32_f(MAC_MODE, (tp->mac_mode |
3671 MAC_MODE_SEND_CONFIGS));
3672 udelay(1);
3673 tw32_f(MAC_MODE, tp->mac_mode);
3674 }
3675 }
3676
3677 if (current_link_up == 1) {
3678 tp->link_config.active_speed = SPEED_1000;
3679 tp->link_config.active_duplex = DUPLEX_FULL;
3680 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3681 LED_CTRL_LNKLED_OVERRIDE |
3682 LED_CTRL_1000MBPS_ON));
3683 } else {
3684 tp->link_config.active_speed = SPEED_INVALID;
3685 tp->link_config.active_duplex = DUPLEX_INVALID;
3686 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3687 LED_CTRL_LNKLED_OVERRIDE |
3688 LED_CTRL_TRAFFIC_OVERRIDE));
3689 }
3690
3691 if (current_link_up != netif_carrier_ok(tp->dev)) {
3692 if (current_link_up)
3693 netif_carrier_on(tp->dev);
3694 else
3695 netif_carrier_off(tp->dev);
3696 tg3_link_report(tp);
3697 } else {
8d018621 3698 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3699 if (orig_pause_cfg != now_pause_cfg ||
3700 orig_active_speed != tp->link_config.active_speed ||
3701 orig_active_duplex != tp->link_config.active_duplex)
3702 tg3_link_report(tp);
3703 }
3704
3705 return 0;
3706}
3707
747e8f8b
MC		 3708static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3709{
3710 int current_link_up, err = 0;
3711 u32 bmsr, bmcr;
3712 u16 current_speed;
3713 u8 current_duplex;
ef167e27 3714 u32 local_adv, remote_adv;
747e8f8b
MC		 3715
3716 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3717 tw32_f(MAC_MODE, tp->mac_mode);
3718 udelay(40);
3719
3720 tw32(MAC_EVENT, 0);
3721
3722 tw32_f(MAC_STATUS,
3723 (MAC_STATUS_SYNC_CHANGED |
3724 MAC_STATUS_CFG_CHANGED |
3725 MAC_STATUS_MI_COMPLETION |
3726 MAC_STATUS_LNKSTATE_CHANGED));
3727 udelay(40);
3728
3729 if (force_reset)
3730 tg3_phy_reset(tp);
3731
3732 current_link_up = 0;
3733 current_speed = SPEED_INVALID;
3734 current_duplex = DUPLEX_INVALID;
3735
3736 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3737 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3739 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3740 bmsr |= BMSR_LSTATUS;
3741 else
3742 bmsr &= ~BMSR_LSTATUS;
3743 }
747e8f8b
MC		 3744
3745 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3746
3747 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3748 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3749 /* do nothing, just check for link up at the end */
3750 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3751 u32 adv, new_adv;
3752
3753 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3754 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3755 ADVERTISE_1000XPAUSE |
3756 ADVERTISE_1000XPSE_ASYM |
3757 ADVERTISE_SLCT);
3758
ba4d07a8 3759 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3760
3761 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3762 new_adv |= ADVERTISE_1000XHALF;
3763 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3764 new_adv |= ADVERTISE_1000XFULL;
3765
3766 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3767 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3768 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3769 tg3_writephy(tp, MII_BMCR, bmcr);
3770
3771 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3772 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3773 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3774
3775 return err;
3776 }
3777 } else {
3778 u32 new_bmcr;
3779
3780 bmcr &= ~BMCR_SPEED1000;
3781 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3782
3783 if (tp->link_config.duplex == DUPLEX_FULL)
3784 new_bmcr |= BMCR_FULLDPLX;
3785
3786 if (new_bmcr != bmcr) {
3787 /* BMCR_SPEED1000 is a reserved bit that needs
3788 * to be set on write.
3789 */
3790 new_bmcr |= BMCR_SPEED1000;
3791
3792 /* Force a linkdown */
3793 if (netif_carrier_ok(tp->dev)) {
3794 u32 adv;
3795
3796 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3797 adv &= ~(ADVERTISE_1000XFULL |
3798 ADVERTISE_1000XHALF |
3799 ADVERTISE_SLCT);
3800 tg3_writephy(tp, MII_ADVERTISE, adv);
3801 tg3_writephy(tp, MII_BMCR, bmcr |
3802 BMCR_ANRESTART |
3803 BMCR_ANENABLE);
3804 udelay(10);
3805 netif_carrier_off(tp->dev);
3806 }
3807 tg3_writephy(tp, MII_BMCR, new_bmcr);
3808 bmcr = new_bmcr;
3809 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3810 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3811 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3812 ASIC_REV_5714) {
3813 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3814 bmsr |= BMSR_LSTATUS;
3815 else
3816 bmsr &= ~BMSR_LSTATUS;
3817 }
747e8f8b
MC		 3818 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3819 }
3820 }
3821
3822 if (bmsr & BMSR_LSTATUS) {
3823 current_speed = SPEED_1000;
3824 current_link_up = 1;
3825 if (bmcr & BMCR_FULLDPLX)
3826 current_duplex = DUPLEX_FULL;
3827 else
3828 current_duplex = DUPLEX_HALF;
3829
ef167e27
MC		 3830 local_adv = 0;
3831 remote_adv = 0;
3832
747e8f8b 3833 if (bmcr & BMCR_ANENABLE) {
ef167e27 3834 u32 common;
747e8f8b
MC		 3835
3836 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3837 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3838 common = local_adv & remote_adv;
3839 if (common & (ADVERTISE_1000XHALF |
3840 ADVERTISE_1000XFULL)) {
3841 if (common & ADVERTISE_1000XFULL)
3842 current_duplex = DUPLEX_FULL;
3843 else
3844 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 3845 }
3846 else
3847 current_link_up = 0;
3848 }
3849 }
3850
ef167e27
MC		 3851 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3852 tg3_setup_flow_control(tp, local_adv, remote_adv);
3853
747e8f8b
MC		 3854 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3855 if (tp->link_config.active_duplex == DUPLEX_HALF)
3856 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3857
3858 tw32_f(MAC_MODE, tp->mac_mode);
3859 udelay(40);
3860
3861 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3862
3863 tp->link_config.active_speed = current_speed;
3864 tp->link_config.active_duplex = current_duplex;
3865
3866 if (current_link_up != netif_carrier_ok(tp->dev)) {
3867 if (current_link_up)
3868 netif_carrier_on(tp->dev);
3869 else {
3870 netif_carrier_off(tp->dev);
3871 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3872 }
3873 tg3_link_report(tp);
3874 }
3875 return err;
3876}
3877
3878static void tg3_serdes_parallel_detect(struct tg3 *tp)
3879{
3d3ebe74 3880 if (tp->serdes_counter) {
747e8f8b 3881 /* Give autoneg time to complete. */
3d3ebe74 3882 tp->serdes_counter--;
747e8f8b
MC		 3883 return;
3884 }
3885 if (!netif_carrier_ok(tp->dev) &&
3886 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3887 u32 bmcr;
3888
3889 tg3_readphy(tp, MII_BMCR, &bmcr);
3890 if (bmcr & BMCR_ANENABLE) {
3891 u32 phy1, phy2;
3892
3893 /* Select shadow register 0x1f */
3894 tg3_writephy(tp, 0x1c, 0x7c00);
3895 tg3_readphy(tp, 0x1c, &phy1);
3896
3897 /* Select expansion interrupt status register */
3898 tg3_writephy(tp, 0x17, 0x0f01);
3899 tg3_readphy(tp, 0x15, &phy2);
3900 tg3_readphy(tp, 0x15, &phy2);
3901
3902 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3903 /* We have signal detect and not receiving
3904 * config code words, link is up by parallel
3905 * detection.
3906 */
3907
3908 bmcr &= ~BMCR_ANENABLE;
3909 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3910 tg3_writephy(tp, MII_BMCR, bmcr);
3911 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3912 }
3913 }
3914 }
3915 else if (netif_carrier_ok(tp->dev) &&
3916 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3917 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3918 u32 phy2;
3919
3920 /* Select expansion interrupt status register */
3921 tg3_writephy(tp, 0x17, 0x0f01);
3922 tg3_readphy(tp, 0x15, &phy2);
3923 if (phy2 & 0x20) {
3924 u32 bmcr;
3925
3926 /* Config code words received, turn on autoneg. */
3927 tg3_readphy(tp, MII_BMCR, &bmcr);
3928 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3929
3930 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3931
3932 }
3933 }
3934}
3935
1da177e4
LT		 3936static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3937{
3938 int err;
3939
3940 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3941 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 3942 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3943 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 3944 } else {
3945 err = tg3_setup_copper_phy(tp, force_reset);
3946 }
3947
bcb37f6c 3948 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 3949 u32 val, scale;
3950
3951 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3952 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3953 scale = 65;
3954 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3955 scale = 6;
3956 else
3957 scale = 12;
3958
3959 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3960 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3961 tw32(GRC_MISC_CFG, val);
3962 }
3963
1da177e4
LT		 3964 if (tp->link_config.active_speed == SPEED_1000 &&
3965 tp->link_config.active_duplex == DUPLEX_HALF)
3966 tw32(MAC_TX_LENGTHS,
3967 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3968 (6 << TX_LENGTHS_IPG_SHIFT) |
3969 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3970 else
3971 tw32(MAC_TX_LENGTHS,
3972 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3973 (6 << TX_LENGTHS_IPG_SHIFT) |
3974 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3975
3976 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3977 if (netif_carrier_ok(tp->dev)) {
3978 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3979 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3980 } else {
3981 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3982 }
3983 }
3984
8ed5d97e
MC		 3985 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3986 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3987 if (!netif_carrier_ok(tp->dev))
3988 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3989 tp->pwrmgmt_thresh;
3990 else
3991 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3992 tw32(PCIE_PWR_MGMT_THRESH, val);
3993 }
3994
1da177e4
LT		 3995 return err;
3996}
3997
df3e6548
MC		 3998/* This is called whenever we suspect that the system chipset is re-
3999 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4000 * is bogus tx completions. We try to recover by setting the
4001 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4002 * in the workqueue.
4003 */
4004static void tg3_tx_recover(struct tg3 *tp)
4005{
4006 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4007 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4008
4009 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4010 "mapped I/O cycles to the network device, attempting to "
4011 "recover. Please report the problem to the driver maintainer "
4012 "and include system chipset information.\n", tp->dev->name);
4013
4014 spin_lock(&tp->lock);
df3e6548 4015 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4016 spin_unlock(&tp->lock);
4017}
4018
1b2a7205
MC		 4019static inline u32 tg3_tx_avail(struct tg3 *tp)
4020{
4021 smp_mb();
4022 return (tp->tx_pending -
4023 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4024}
4025
1da177e4
LT		 4026/* Tigon3 never reports partial packet sends. So we do not
4027 * need special logic to handle SKBs that have not had all
4028 * of their frags sent yet, like SunGEM does.
4029 */
4030static void tg3_tx(struct tg3 *tp)
4031{
4032 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4033 u32 sw_idx = tp->tx_cons;
4034
4035 while (sw_idx != hw_idx) {
4036 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4037 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4038 int i, tx_bug = 0;
4039
4040 if (unlikely(skb == NULL)) {
4041 tg3_tx_recover(tp);
4042 return;
4043 }
1da177e4 4044
90079ce8 4045 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4046
4047 ri->skb = NULL;
4048
4049 sw_idx = NEXT_TX(sw_idx);
4050
4051 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4052 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4053 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4054 tx_bug = 1;
1da177e4
LT		 4055 sw_idx = NEXT_TX(sw_idx);
4056 }
4057
f47c11ee 4058 dev_kfree_skb(skb);
df3e6548
MC		 4059
4060 if (unlikely(tx_bug)) {
4061 tg3_tx_recover(tp);
4062 return;
4063 }
1da177e4
LT		 4064 }
4065
4066 tp->tx_cons = sw_idx;
4067
1b2a7205
MC		 4068 /* Need to make the tx_cons update visible to tg3_start_xmit()
4069 * before checking for netif_queue_stopped(). Without the
4070 * memory barrier, there is a small possibility that tg3_start_xmit()
4071 * will miss it and cause the queue to be stopped forever.
4072 */
4073 smp_mb();
4074
4075 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4076 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4077 netif_tx_lock(tp->dev);
51b91468 4078 if (netif_queue_stopped(tp->dev) &&
42952231 4079 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4080 netif_wake_queue(tp->dev);
1b2a7205 4081 netif_tx_unlock(tp->dev);
51b91468 4082 }
1da177e4
LT		 4083}
4084
4085/* Returns size of skb allocated or < 0 on error.
4086 *
4087 * We only need to fill in the address because the other members
4088 * of the RX descriptor are invariant, see tg3_init_rings.
4089 *
4090 * Note the purposeful assymetry of cpu vs. chip accesses. For
4091 * posting buffers we only dirty the first cache line of the RX
4092 * descriptor (containing the address). Whereas for the RX status
4093 * buffers the cpu only reads the last cacheline of the RX descriptor
4094 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4095 */
4096static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4097 int src_idx, u32 dest_idx_unmasked)
4098{
4099 struct tg3_rx_buffer_desc *desc;
4100 struct ring_info *map, *src_map;
4101 struct sk_buff *skb;
4102 dma_addr_t mapping;
4103 int skb_size, dest_idx;
4104
4105 src_map = NULL;
4106 switch (opaque_key) {
4107 case RXD_OPAQUE_RING_STD:
4108 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4109 desc = &tp->rx_std[dest_idx];
4110 map = &tp->rx_std_buffers[dest_idx];
4111 if (src_idx >= 0)
4112 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4113 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4114 break;
4115
4116 case RXD_OPAQUE_RING_JUMBO:
4117 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4118 desc = &tp->rx_jumbo[dest_idx];
4119 map = &tp->rx_jumbo_buffers[dest_idx];
4120 if (src_idx >= 0)
4121 src_map = &tp->rx_jumbo_buffers[src_idx];
4122 skb_size = RX_JUMBO_PKT_BUF_SZ;
4123 break;
4124
4125 default:
4126 return -EINVAL;
855e1111 4127 }
1da177e4
LT		 4128
4129 /* Do not overwrite any of the map or rp information
4130 * until we are sure we can commit to a new buffer.
4131 *
4132 * Callers depend upon this behavior and assume that
4133 * we leave everything unchanged if we fail.
4134 */
a20e9c62 4135 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4136 if (skb == NULL)
4137 return -ENOMEM;
4138
1da177e4
LT		 4139 skb_reserve(skb, tp->rx_offset);
4140
4141 mapping = pci_map_single(tp->pdev, skb->data,
4142 skb_size - tp->rx_offset,
4143 PCI_DMA_FROMDEVICE);
4144
4145 map->skb = skb;
4146 pci_unmap_addr_set(map, mapping, mapping);
4147
4148 if (src_map != NULL)
4149 src_map->skb = NULL;
4150
4151 desc->addr_hi = ((u64)mapping >> 32);
4152 desc->addr_lo = ((u64)mapping & 0xffffffff);
4153
4154 return skb_size;
4155}
4156
4157/* We only need to move over in the address because the other
4158 * members of the RX descriptor are invariant. See notes above
4159 * tg3_alloc_rx_skb for full details.
4160 */
4161static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4162 int src_idx, u32 dest_idx_unmasked)
4163{
4164 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4165 struct ring_info *src_map, *dest_map;
4166 int dest_idx;
4167
4168 switch (opaque_key) {
4169 case RXD_OPAQUE_RING_STD:
4170 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4171 dest_desc = &tp->rx_std[dest_idx];
4172 dest_map = &tp->rx_std_buffers[dest_idx];
4173 src_desc = &tp->rx_std[src_idx];
4174 src_map = &tp->rx_std_buffers[src_idx];
4175 break;
4176
4177 case RXD_OPAQUE_RING_JUMBO:
4178 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4179 dest_desc = &tp->rx_jumbo[dest_idx];
4180 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4181 src_desc = &tp->rx_jumbo[src_idx];
4182 src_map = &tp->rx_jumbo_buffers[src_idx];
4183 break;
4184
4185 default:
4186 return;
855e1111 4187 }
1da177e4
LT		 4188
4189 dest_map->skb = src_map->skb;
4190 pci_unmap_addr_set(dest_map, mapping,
4191 pci_unmap_addr(src_map, mapping));
4192 dest_desc->addr_hi = src_desc->addr_hi;
4193 dest_desc->addr_lo = src_desc->addr_lo;
4194
4195 src_map->skb = NULL;
4196}
4197
4198#if TG3_VLAN_TAG_USED
4199static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4200{
4201 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4202}
4203#endif
4204
4205/* The RX ring scheme is composed of multiple rings which post fresh
4206 * buffers to the chip, and one special ring the chip uses to report
4207 * status back to the host.
4208 *
4209 * The special ring reports the status of received packets to the
4210 * host. The chip does not write into the original descriptor the
4211 * RX buffer was obtained from. The chip simply takes the original
4212 * descriptor as provided by the host, updates the status and length
4213 * field, then writes this into the next status ring entry.
4214 *
4215 * Each ring the host uses to post buffers to the chip is described
4216 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4217 * it is first placed into the on-chip ram. When the packet's length
4218 * is known, it walks down the TG3_BDINFO entries to select the ring.
4219 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4220 * which is within the range of the new packet's length is chosen.
4221 *
4222 * The "separate ring for rx status" scheme may sound queer, but it makes
4223 * sense from a cache coherency perspective. If only the host writes
4224 * to the buffer post rings, and only the chip writes to the rx status
4225 * rings, then cache lines never move beyond shared-modified state.
4226 * If both the host and chip were to write into the same ring, cache line
4227 * eviction could occur since both entities want it in an exclusive state.
4228 */
4229static int tg3_rx(struct tg3 *tp, int budget)
4230{
f92905de 4231 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4232 u32 sw_idx = tp->rx_rcb_ptr;
4233 u16 hw_idx;
1da177e4
LT		 4234 int received;
4235
4236 hw_idx = tp->hw_status->idx[0].rx_producer;
4237 /*
4238 * We need to order the read of hw_idx and the read of
4239 * the opaque cookie.
4240 */
4241 rmb();
1da177e4
LT		 4242 work_mask = 0;
4243 received = 0;
4244 while (sw_idx != hw_idx && budget > 0) {
4245 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4246 unsigned int len;
4247 struct sk_buff *skb;
4248 dma_addr_t dma_addr;
4249 u32 opaque_key, desc_idx, *post_ptr;
4250
4251 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4252 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4253 if (opaque_key == RXD_OPAQUE_RING_STD) {
4254 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4255 mapping);
4256 skb = tp->rx_std_buffers[desc_idx].skb;
4257 post_ptr = &tp->rx_std_ptr;
f92905de 4258 rx_std_posted++;
1da177e4
LT		 4259 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4260 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4261 mapping);
4262 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4263 post_ptr = &tp->rx_jumbo_ptr;
4264 }
4265 else {
4266 goto next_pkt_nopost;
4267 }
4268
4269 work_mask |= opaque_key;
4270
4271 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4272 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4273 drop_it:
4274 tg3_recycle_rx(tp, opaque_key,
4275 desc_idx, *post_ptr);
4276 drop_it_no_recycle:
4277 /* Other statistics kept track of by card. */
4278 tp->net_stats.rx_dropped++;
4279 goto next_pkt;
4280 }
4281
ad829268
MC		 4282 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4283 ETH_FCS_LEN;
1da177e4 4284
6aa20a22 4285 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4286 && tp->rx_offset == NET_IP_ALIGN
4287 /* rx_offset will likely not equal NET_IP_ALIGN
4288 * if this is a 5701 card running in PCI-X mode
4289 * [see tg3_get_invariants()]
4290 */
1da177e4
LT		 4291 ) {
4292 int skb_size;
4293
4294 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4295 desc_idx, *post_ptr);
4296 if (skb_size < 0)
4297 goto drop_it;
4298
4299 pci_unmap_single(tp->pdev, dma_addr,
4300 skb_size - tp->rx_offset,
4301 PCI_DMA_FROMDEVICE);
4302
4303 skb_put(skb, len);
4304 } else {
4305 struct sk_buff *copy_skb;
4306
4307 tg3_recycle_rx(tp, opaque_key,
4308 desc_idx, *post_ptr);
4309
ad829268
MC		 4310 copy_skb = netdev_alloc_skb(tp->dev,
4311 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4312 if (copy_skb == NULL)
4313 goto drop_it_no_recycle;
4314
ad829268 4315 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4316 skb_put(copy_skb, len);
4317 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4318 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4319 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4320
4321 /* We'll reuse the original ring buffer. */
4322 skb = copy_skb;
4323 }
4324
4325 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4326 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4327 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4328 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4329 skb->ip_summed = CHECKSUM_UNNECESSARY;
4330 else
4331 skb->ip_summed = CHECKSUM_NONE;
4332
4333 skb->protocol = eth_type_trans(skb, tp->dev);
4334#if TG3_VLAN_TAG_USED
4335 if (tp->vlgrp != NULL &&
4336 desc->type_flags & RXD_FLAG_VLAN) {
4337 tg3_vlan_rx(tp, skb,
4338 desc->err_vlan & RXD_VLAN_MASK);
4339 } else
4340#endif
4341 netif_receive_skb(skb);
4342
1da177e4
LT		 4343 received++;
4344 budget--;
4345
4346next_pkt:
4347 (*post_ptr)++;
f92905de
MC		 4348
4349 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4350 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4351
4352 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4353 TG3_64BIT_REG_LOW, idx);
4354 work_mask &= ~RXD_OPAQUE_RING_STD;
4355 rx_std_posted = 0;
4356 }
1da177e4 4357next_pkt_nopost:
483ba50b 4358 sw_idx++;
6b31a515 4359 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4360
4361 /* Refresh hw_idx to see if there is new work */
4362 if (sw_idx == hw_idx) {
4363 hw_idx = tp->hw_status->idx[0].rx_producer;
4364 rmb();
4365 }
1da177e4
LT		 4366 }
4367
4368 /* ACK the status ring. */
483ba50b
MC		 4369 tp->rx_rcb_ptr = sw_idx;
4370 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4371
4372 /* Refill RX ring(s). */
4373 if (work_mask & RXD_OPAQUE_RING_STD) {
4374 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4375 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4376 sw_idx);
4377 }
4378 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4379 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4380 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4381 sw_idx);
4382 }
4383 mmiowb();
4384
4385 return received;
4386}
4387
6f535763 4388static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4389{
1da177e4 4390 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4391
1da177e4
LT		 4392 /* handle link change and other phy events */
4393 if (!(tp->tg3_flags &
4394 (TG3_FLAG_USE_LINKCHG_REG |
4395 TG3_FLAG_POLL_SERDES))) {
4396 if (sblk->status & SD_STATUS_LINK_CHG) {
4397 sblk->status = SD_STATUS_UPDATED |
4398 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4399 spin_lock(&tp->lock);
dd477003
MC		 4400 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4401 tw32_f(MAC_STATUS,
4402 (MAC_STATUS_SYNC_CHANGED |
4403 MAC_STATUS_CFG_CHANGED |
4404 MAC_STATUS_MI_COMPLETION |
4405 MAC_STATUS_LNKSTATE_CHANGED));
4406 udelay(40);
4407 } else
4408 tg3_setup_phy(tp, 0);
f47c11ee 4409 spin_unlock(&tp->lock);
1da177e4
LT		 4410 }
4411 }
4412
4413 /* run TX completion thread */
4414 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4415 tg3_tx(tp);
6f535763 4416 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4417 return work_done;
1da177e4
LT		 4418 }
4419
1da177e4
LT		 4420 /* run RX thread, within the bounds set by NAPI.
4421 * All RX "locking" is done by ensuring outside
bea3348e 4422 * code synchronizes with tg3->napi.poll()
1da177e4 4423 */
bea3348e 4424 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4425 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4426
6f535763
DM		 4427 return work_done;
4428}
4429
4430static int tg3_poll(struct napi_struct *napi, int budget)
4431{
4432 struct tg3 *tp = container_of(napi, struct tg3, napi);
4433 int work_done = 0;
4fd7ab59 4434 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4435
4436 while (1) {
4437 work_done = tg3_poll_work(tp, work_done, budget);
4438
4439 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4440 goto tx_recovery;
4441
4442 if (unlikely(work_done >= budget))
4443 break;
4444
4fd7ab59
MC		 4445 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4446 /* tp->last_tag is used in tg3_restart_ints() below
4447 * to tell the hw how much work has been processed,
4448 * so we must read it before checking for more work.
4449 */
4450 tp->last_tag = sblk->status_tag;
4451 rmb();
4452 } else
4453 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4454
4fd7ab59 4455 if (likely(!tg3_has_work(tp))) {
6f535763
DM		 4456 netif_rx_complete(tp->dev, napi);
4457 tg3_restart_ints(tp);
4458 break;
4459 }
1da177e4
LT		 4460 }
4461
bea3348e 4462 return work_done;
6f535763
DM		 4463
4464tx_recovery:
4fd7ab59 4465 /* work_done is guaranteed to be less than budget. */
6f535763
DM		 4466 netif_rx_complete(tp->dev, napi);
4467 schedule_work(&tp->reset_task);
4fd7ab59 4468 return work_done;
1da177e4
LT		 4469}
4470
f47c11ee
DM		 4471static void tg3_irq_quiesce(struct tg3 *tp)
4472{
4473 BUG_ON(tp->irq_sync);
4474
4475 tp->irq_sync = 1;
4476 smp_mb();
4477
4478 synchronize_irq(tp->pdev->irq);
4479}
4480
4481static inline int tg3_irq_sync(struct tg3 *tp)
4482{
4483 return tp->irq_sync;
4484}
4485
4486/* Fully shutdown all tg3 driver activity elsewhere in the system.
4487 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4488 * with as well. Most of the time, this is not necessary except when
4489 * shutting down the device.
4490 */
4491static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4492{
46966545 4493 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4494 if (irq_sync)
4495 tg3_irq_quiesce(tp);
f47c11ee
DM		 4496}
4497
4498static inline void tg3_full_unlock(struct tg3 *tp)
4499{
f47c11ee
DM		 4500 spin_unlock_bh(&tp->lock);
4501}
4502
fcfa0a32
MC		 4503/* One-shot MSI handler - Chip automatically disables interrupt
4504 * after sending MSI so driver doesn't have to do it.
4505 */
7d12e780 4506static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4507{
4508 struct net_device *dev = dev_id;
4509 struct tg3 *tp = netdev_priv(dev);
4510
4511 prefetch(tp->hw_status);
4512 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4513
4514 if (likely(!tg3_irq_sync(tp)))
bea3348e 4515 netif_rx_schedule(dev, &tp->napi);
fcfa0a32
MC		 4516
4517 return IRQ_HANDLED;
4518}
4519
88b06bc2
MC		 4520/* MSI ISR - No need to check for interrupt sharing and no need to
4521 * flush status block and interrupt mailbox. PCI ordering rules
4522 * guarantee that MSI will arrive after the status block.
4523 */
7d12e780 4524static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4525{
4526 struct net_device *dev = dev_id;
4527 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4528
61487480
MC		 4529 prefetch(tp->hw_status);
4530 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4531 /*
fac9b83e 4532 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4533 * chip-internal interrupt pending events.
fac9b83e 4534 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4535 * NIC to stop sending us irqs, engaging "in-intr-handler"
4536 * event coalescing.
4537 */
4538 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4539 if (likely(!tg3_irq_sync(tp)))
bea3348e 4540 netif_rx_schedule(dev, &tp->napi);
61487480 4541
88b06bc2
MC		 4542 return IRQ_RETVAL(1);
4543}
4544
7d12e780 4545static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4546{
4547 struct net_device *dev = dev_id;
4548 struct tg3 *tp = netdev_priv(dev);
4549 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4550 unsigned int handled = 1;
4551
1da177e4
LT		 4552 /* In INTx mode, it is possible for the interrupt to arrive at
4553 * the CPU before the status block posted prior to the interrupt.
4554 * Reading the PCI State register will confirm whether the
4555 * interrupt is ours and will flush the status block.
4556 */
d18edcb2
MC		 4557 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4558 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4559 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4560 handled = 0;
f47c11ee 4561 goto out;
fac9b83e 4562 }
d18edcb2
MC		 4563 }
4564
4565 /*
4566 * Writing any value to intr-mbox-0 clears PCI INTA# and
4567 * chip-internal interrupt pending events.
4568 * Writing non-zero to intr-mbox-0 additional tells the
4569 * NIC to stop sending us irqs, engaging "in-intr-handler"
4570 * event coalescing.
c04cb347
MC		 4571 *
4572 * Flush the mailbox to de-assert the IRQ immediately to prevent
4573 * spurious interrupts. The flush impacts performance but
4574 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4575 */
c04cb347 4576 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4577 if (tg3_irq_sync(tp))
4578 goto out;
4579 sblk->status &= ~SD_STATUS_UPDATED;
4580 if (likely(tg3_has_work(tp))) {
4581 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
bea3348e 4582 netif_rx_schedule(dev, &tp->napi);
d18edcb2
MC		 4583 } else {
4584 /* No work, shared interrupt perhaps? re-enable
4585 * interrupts, and flush that PCI write
4586 */
4587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4588 0x00000000);
fac9b83e 4589 }
f47c11ee 4590out:
fac9b83e
DM		 4591 return IRQ_RETVAL(handled);
4592}
4593
7d12e780 4594static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4595{
4596 struct net_device *dev = dev_id;
4597 struct tg3 *tp = netdev_priv(dev);
4598 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4599 unsigned int handled = 1;
4600
fac9b83e
DM		 4601 /* In INTx mode, it is possible for the interrupt to arrive at
4602 * the CPU before the status block posted prior to the interrupt.
4603 * Reading the PCI State register will confirm whether the
4604 * interrupt is ours and will flush the status block.
4605 */
d18edcb2
MC		 4606 if (unlikely(sblk->status_tag == tp->last_tag)) {
4607 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4608 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4609 handled = 0;
f47c11ee 4610 goto out;
1da177e4 4611 }
d18edcb2
MC		 4612 }
4613
4614 /*
4615 * writing any value to intr-mbox-0 clears PCI INTA# and
4616 * chip-internal interrupt pending events.
4617 * writing non-zero to intr-mbox-0 additional tells the
4618 * NIC to stop sending us irqs, engaging "in-intr-handler"
4619 * event coalescing.
c04cb347
MC		 4620 *
4621 * Flush the mailbox to de-assert the IRQ immediately to prevent
4622 * spurious interrupts. The flush impacts performance but
4623 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4624 */
c04cb347 4625 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4626 if (tg3_irq_sync(tp))
4627 goto out;
bea3348e 4628 if (netif_rx_schedule_prep(dev, &tp->napi)) {
d18edcb2
MC		 4629 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4630 /* Update last_tag to mark that this status has been
4631 * seen. Because interrupt may be shared, we may be
4632 * racing with tg3_poll(), so only update last_tag
4633 * if tg3_poll() is not scheduled.
4634 */
4635 tp->last_tag = sblk->status_tag;
bea3348e 4636 __netif_rx_schedule(dev, &tp->napi);
1da177e4 4637 }
f47c11ee 4638out:
1da177e4
LT		 4639 return IRQ_RETVAL(handled);
4640}
4641
7938109f 4642/* ISR for interrupt test */
7d12e780 4643static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4644{
4645 struct net_device *dev = dev_id;
4646 struct tg3 *tp = netdev_priv(dev);
4647 struct tg3_hw_status *sblk = tp->hw_status;
4648
f9804ddb
MC		 4649 if ((sblk->status & SD_STATUS_UPDATED) ||
4650 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4651 tg3_disable_ints(tp);
7938109f
MC		 4652 return IRQ_RETVAL(1);
4653 }
4654 return IRQ_RETVAL(0);
4655}
4656
8e7a22e3 4657static int tg3_init_hw(struct tg3 *, int);
944d980e 4658static int tg3_halt(struct tg3 *, int, int);
1da177e4 4659
b9ec6c1b
MC		 4660/* Restart hardware after configuration changes, self-test, etc.
4661 * Invoked with tp->lock held.
4662 */
4663static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4664 __releases(tp->lock)
4665 __acquires(tp->lock)
b9ec6c1b
MC		 4666{
4667 int err;
4668
4669 err = tg3_init_hw(tp, reset_phy);
4670 if (err) {
4671 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4672 "aborting.\n", tp->dev->name);
4673 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4674 tg3_full_unlock(tp);
4675 del_timer_sync(&tp->timer);
4676 tp->irq_sync = 0;
bea3348e 4677 napi_enable(&tp->napi);
b9ec6c1b
MC		 4678 dev_close(tp->dev);
4679 tg3_full_lock(tp, 0);
4680 }
4681 return err;
4682}
4683
1da177e4
LT		 4684#ifdef CONFIG_NET_POLL_CONTROLLER
4685static void tg3_poll_controller(struct net_device *dev)
4686{
88b06bc2
MC		 4687 struct tg3 *tp = netdev_priv(dev);
4688
7d12e780 4689 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4690}
4691#endif
4692
c4028958 4693static void tg3_reset_task(struct work_struct *work)
1da177e4 4694{
c4028958 4695 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4696 int err;
1da177e4
LT		 4697 unsigned int restart_timer;
4698
7faa006f 4699 tg3_full_lock(tp, 0);
7faa006f
MC		 4700
4701 if (!netif_running(tp->dev)) {
7faa006f
MC		 4702 tg3_full_unlock(tp);
4703 return;
4704 }
4705
4706 tg3_full_unlock(tp);
4707
b02fd9e3
MC		 4708 tg3_phy_stop(tp);
4709
1da177e4
LT		 4710 tg3_netif_stop(tp);
4711
f47c11ee 4712 tg3_full_lock(tp, 1);
1da177e4
LT		 4713
4714 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4715 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4716
df3e6548
MC		 4717 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4718 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4719 tp->write32_rx_mbox = tg3_write_flush_reg32;
4720 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4721 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4722 }
4723
944d980e 4724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4725 err = tg3_init_hw(tp, 1);
4726 if (err)
b9ec6c1b 4727 goto out;
1da177e4
LT		 4728
4729 tg3_netif_start(tp);
4730
1da177e4
LT		 4731 if (restart_timer)
4732 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4733
b9ec6c1b 4734out:
7faa006f 4735 tg3_full_unlock(tp);
b02fd9e3
MC		 4736
4737 if (!err)
4738 tg3_phy_start(tp);
1da177e4
LT		 4739}
4740
b0408751
MC		 4741static void tg3_dump_short_state(struct tg3 *tp)
4742{
4743 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4744 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4745 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4746 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4747}
4748
1da177e4
LT		 4749static void tg3_tx_timeout(struct net_device *dev)
4750{
4751 struct tg3 *tp = netdev_priv(dev);
4752
b0408751 4753 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4754 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4755 dev->name);
b0408751
MC		 4756 tg3_dump_short_state(tp);
4757 }
1da177e4
LT		 4758
4759 schedule_work(&tp->reset_task);
4760}
4761
c58ec932
MC		 4762/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4763static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4764{
4765 u32 base = (u32) mapping & 0xffffffff;
4766
4767 return ((base > 0xffffdcc0) &&
4768 (base + len + 8 < base));
4769}
4770
72f2afb8
MC		 4771/* Test for DMA addresses > 40-bit */
4772static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4773 int len)
4774{
4775#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4776 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 4777 return (((u64) mapping + len) > DMA_40BIT_MASK);
4778 return 0;
4779#else
4780 return 0;
4781#endif
4782}
4783
1da177e4
LT		 4784static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4785
72f2afb8
MC		 4786/* Workaround 4GB and 40-bit hardware DMA bugs. */
4787static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 4788 u32 last_plus_one, u32 *start,
4789 u32 base_flags, u32 mss)
1da177e4 4790{
41588ba1 4791 struct sk_buff *new_skb;
c58ec932 4792 dma_addr_t new_addr = 0;
1da177e4 4793 u32 entry = *start;
c58ec932 4794 int i, ret = 0;
1da177e4 4795
41588ba1
MC		 4796 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4797 new_skb = skb_copy(skb, GFP_ATOMIC);
4798 else {
4799 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4800
4801 new_skb = skb_copy_expand(skb,
4802 skb_headroom(skb) + more_headroom,
4803 skb_tailroom(skb), GFP_ATOMIC);
4804 }
4805
1da177e4 4806 if (!new_skb) {
c58ec932
MC		 4807 ret = -1;
4808 } else {
4809 /* New SKB is guaranteed to be linear. */
4810 entry = *start;
90079ce8
DM		 4811 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
4812 new_addr = skb_shinfo(new_skb)->dma_maps[0];
4813
c58ec932
MC		 4814 /* Make sure new skb does not cross any 4G boundaries.
4815 * Drop the packet if it does.
4816 */
90079ce8 4817 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 4818 if (!ret)
4819 skb_dma_unmap(&tp->pdev->dev, new_skb,
4820 DMA_TO_DEVICE);
c58ec932
MC		 4821 ret = -1;
4822 dev_kfree_skb(new_skb);
4823 new_skb = NULL;
4824 } else {
4825 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4826 base_flags, 1 | (mss << 1));
4827 *start = NEXT_TX(entry);
4828 }
1da177e4
LT		 4829 }
4830
1da177e4
LT		 4831 /* Now clean up the sw ring entries. */
4832 i = 0;
4833 while (entry != last_plus_one) {
1da177e4
LT		 4834 if (i == 0) {
4835 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 4836 } else {
4837 tp->tx_buffers[entry].skb = NULL;
4838 }
4839 entry = NEXT_TX(entry);
4840 i++;
4841 }
4842
90079ce8 4843 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4844 dev_kfree_skb(skb);
4845
c58ec932 4846 return ret;
1da177e4
LT		 4847}
4848
4849static void tg3_set_txd(struct tg3 *tp, int entry,
4850 dma_addr_t mapping, int len, u32 flags,
4851 u32 mss_and_is_end)
4852{
4853 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4854 int is_end = (mss_and_is_end & 0x1);
4855 u32 mss = (mss_and_is_end >> 1);
4856 u32 vlan_tag = 0;
4857
4858 if (is_end)
4859 flags |= TXD_FLAG_END;
4860 if (flags & TXD_FLAG_VLAN) {
4861 vlan_tag = flags >> 16;
4862 flags &= 0xffff;
4863 }
4864 vlan_tag |= (mss << TXD_MSS_SHIFT);
4865
4866 txd->addr_hi = ((u64) mapping >> 32);
4867 txd->addr_lo = ((u64) mapping & 0xffffffff);
4868 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4869 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4870}
4871
5a6f3074
MC		 4872/* hard_start_xmit for devices that don't have any bugs and
4873 * support TG3_FLG2_HW_TSO_2 only.
4874 */
1da177e4 4875static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 4876{
4877 struct tg3 *tp = netdev_priv(dev);
5a6f3074 4878 u32 len, entry, base_flags, mss;
90079ce8
DM		 4879 struct skb_shared_info *sp;
4880 dma_addr_t mapping;
5a6f3074
MC		 4881
4882 len = skb_headlen(skb);
4883
00b70504 4884 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4885 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 4886 * interrupt. Furthermore, IRQ processing runs lockless so we have
4887 * no IRQ context deadlocks to worry about either. Rejoice!
4888 */
1b2a7205 4889 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 4890 if (!netif_queue_stopped(dev)) {
4891 netif_stop_queue(dev);
4892
4893 /* This is a hard error, log it. */
4894 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4895 "queue awake!\n", dev->name);
4896 }
5a6f3074
MC		 4897 return NETDEV_TX_BUSY;
4898 }
4899
4900 entry = tp->tx_prod;
4901 base_flags = 0;
5a6f3074 4902 mss = 0;
c13e3713 4903 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 4904 int tcp_opt_len, ip_tcp_len;
4905
4906 if (skb_header_cloned(skb) &&
4907 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4908 dev_kfree_skb(skb);
4909 goto out_unlock;
4910 }
4911
b0026624
MC		 4912 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4913 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4914 else {
eddc9ec5
ACM		 4915 struct iphdr *iph = ip_hdr(skb);
4916
ab6a5bb6 4917 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4918 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 4919
eddc9ec5
ACM		 4920 iph->check = 0;
4921 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 4922 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4923 }
5a6f3074
MC		 4924
4925 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4926 TXD_FLAG_CPU_POST_DMA);
4927
aa8223c7 4928 tcp_hdr(skb)->check = 0;
5a6f3074 4929
5a6f3074 4930 }
84fa7933 4931 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 4932 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 4933#if TG3_VLAN_TAG_USED
4934 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4935 base_flags |= (TXD_FLAG_VLAN |
4936 (vlan_tx_tag_get(skb) << 16));
4937#endif
4938
90079ce8
DM		 4939 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
4940 dev_kfree_skb(skb);
4941 goto out_unlock;
4942 }
4943
4944 sp = skb_shinfo(skb);
4945
4946 mapping = sp->dma_maps[0];
5a6f3074
MC		 4947
4948 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 4949
4950 tg3_set_txd(tp, entry, mapping, len, base_flags,
4951 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4952
4953 entry = NEXT_TX(entry);
4954
4955 /* Now loop through additional data fragments, and queue them. */
4956 if (skb_shinfo(skb)->nr_frags > 0) {
4957 unsigned int i, last;
4958
4959 last = skb_shinfo(skb)->nr_frags - 1;
4960 for (i = 0; i <= last; i++) {
4961 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4962
4963 len = frag->size;
90079ce8 4964 mapping = sp->dma_maps[i + 1];
5a6f3074 4965 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 4966
4967 tg3_set_txd(tp, entry, mapping, len,
4968 base_flags, (i == last) | (mss << 1));
4969
4970 entry = NEXT_TX(entry);
4971 }
4972 }
4973
4974 /* Packets are ready, update Tx producer idx local and on card. */
4975 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4976
4977 tp->tx_prod = entry;
1b2a7205 4978 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 4979 netif_stop_queue(dev);
42952231 4980 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 4981 netif_wake_queue(tp->dev);
4982 }
4983
4984out_unlock:
4985 mmiowb();
5a6f3074
MC		 4986
4987 dev->trans_start = jiffies;
4988
4989 return NETDEV_TX_OK;
4990}
4991
52c0fd83
MC		 4992static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4993
4994/* Use GSO to workaround a rare TSO bug that may be triggered when the
4995 * TSO header is greater than 80 bytes.
4996 */
4997static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4998{
4999 struct sk_buff *segs, *nskb;
5000
5001 /* Estimate the number of fragments in the worst case */
1b2a7205 5002 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5003 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5004 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5005 return NETDEV_TX_BUSY;
5006
5007 netif_wake_queue(tp->dev);
52c0fd83
MC		 5008 }
5009
5010 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5011 if (IS_ERR(segs))
52c0fd83
MC		 5012 goto tg3_tso_bug_end;
5013
5014 do {
5015 nskb = segs;
5016 segs = segs->next;
5017 nskb->next = NULL;
5018 tg3_start_xmit_dma_bug(nskb, tp->dev);
5019 } while (segs);
5020
5021tg3_tso_bug_end:
5022 dev_kfree_skb(skb);
5023
5024 return NETDEV_TX_OK;
5025}
52c0fd83 5026
5a6f3074
MC		 5027/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5028 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5029 */
5030static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5031{
5032 struct tg3 *tp = netdev_priv(dev);
1da177e4 5033 u32 len, entry, base_flags, mss;
90079ce8 5034 struct skb_shared_info *sp;
1da177e4 5035 int would_hit_hwbug;
90079ce8 5036 dma_addr_t mapping;
1da177e4
LT		 5037
5038 len = skb_headlen(skb);
5039
00b70504 5040 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5041 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5042 * interrupt. Furthermore, IRQ processing runs lockless so we have
5043 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5044 */
1b2a7205 5045 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5046 if (!netif_queue_stopped(dev)) {
5047 netif_stop_queue(dev);
5048
5049 /* This is a hard error, log it. */
5050 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5051 "queue awake!\n", dev->name);
5052 }
1da177e4
LT		 5053 return NETDEV_TX_BUSY;
5054 }
5055
5056 entry = tp->tx_prod;
5057 base_flags = 0;
84fa7933 5058 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5059 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5060 mss = 0;
c13e3713 5061 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5062 struct iphdr *iph;
52c0fd83 5063 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5064
5065 if (skb_header_cloned(skb) &&
5066 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5067 dev_kfree_skb(skb);
5068 goto out_unlock;
5069 }
5070
ab6a5bb6 5071 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5072 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5073
52c0fd83
MC		 5074 hdr_len = ip_tcp_len + tcp_opt_len;
5075 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5076 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5077 return (tg3_tso_bug(tp, skb));
5078
1da177e4
LT		 5079 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5080 TXD_FLAG_CPU_POST_DMA);
5081
eddc9ec5
ACM		 5082 iph = ip_hdr(skb);
5083 iph->check = 0;
5084 iph->tot_len = htons(mss + hdr_len);
1da177e4 5085 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5086 tcp_hdr(skb)->check = 0;
1da177e4 5087 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5088 } else
5089 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5090 iph->daddr, 0,
5091 IPPROTO_TCP,
5092 0);
1da177e4
LT		 5093
5094 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5095 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5096 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5097 int tsflags;
5098
eddc9ec5 5099 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5100 mss |= (tsflags << 11);
5101 }
5102 } else {
eddc9ec5 5103 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5104 int tsflags;
5105
eddc9ec5 5106 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5107 base_flags |= tsflags << 12;
5108 }
5109 }
5110 }
1da177e4
LT		 5111#if TG3_VLAN_TAG_USED
5112 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5113 base_flags |= (TXD_FLAG_VLAN |
5114 (vlan_tx_tag_get(skb) << 16));
5115#endif
5116
90079ce8
DM		 5117 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5118 dev_kfree_skb(skb);
5119 goto out_unlock;
5120 }
5121
5122 sp = skb_shinfo(skb);
5123
5124 mapping = sp->dma_maps[0];
1da177e4
LT		 5125
5126 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5127
5128 would_hit_hwbug = 0;
5129
41588ba1
MC		 5130 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5131 would_hit_hwbug = 1;
5132 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5133 would_hit_hwbug = 1;
1da177e4
LT		 5134
5135 tg3_set_txd(tp, entry, mapping, len, base_flags,
5136 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5137
5138 entry = NEXT_TX(entry);
5139
5140 /* Now loop through additional data fragments, and queue them. */
5141 if (skb_shinfo(skb)->nr_frags > 0) {
5142 unsigned int i, last;
5143
5144 last = skb_shinfo(skb)->nr_frags - 1;
5145 for (i = 0; i <= last; i++) {
5146 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5147
5148 len = frag->size;
90079ce8 5149 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5150
5151 tp->tx_buffers[entry].skb = NULL;
1da177e4 5152
c58ec932
MC		 5153 if (tg3_4g_overflow_test(mapping, len))
5154 would_hit_hwbug = 1;
1da177e4 5155
72f2afb8
MC		 5156 if (tg3_40bit_overflow_test(tp, mapping, len))
5157 would_hit_hwbug = 1;
5158
1da177e4
LT		 5159 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5160 tg3_set_txd(tp, entry, mapping, len,
5161 base_flags, (i == last)|(mss << 1));
5162 else
5163 tg3_set_txd(tp, entry, mapping, len,
5164 base_flags, (i == last));
5165
5166 entry = NEXT_TX(entry);
5167 }
5168 }
5169
5170 if (would_hit_hwbug) {
5171 u32 last_plus_one = entry;
5172 u32 start;
1da177e4 5173
c58ec932
MC		 5174 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5175 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5176
5177 /* If the workaround fails due to memory/mapping
5178 * failure, silently drop this packet.
5179 */
72f2afb8 5180 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5181 &start, base_flags, mss))
1da177e4
LT		 5182 goto out_unlock;
5183
5184 entry = start;
5185 }
5186
5187 /* Packets are ready, update Tx producer idx local and on card. */
5188 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5189
5190 tp->tx_prod = entry;
1b2a7205 5191 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5192 netif_stop_queue(dev);
42952231 5193 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5194 netif_wake_queue(tp->dev);
5195 }
1da177e4
LT		 5196
5197out_unlock:
5198 mmiowb();
1da177e4
LT		 5199
5200 dev->trans_start = jiffies;
5201
5202 return NETDEV_TX_OK;
5203}
5204
5205static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5206 int new_mtu)
5207{
5208 dev->mtu = new_mtu;
5209
ef7f5ec0 5210 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5211 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5212 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5213 ethtool_op_set_tso(dev, 0);
5214 }
5215 else
5216 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5217 } else {
a4e2b347 5218 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5219 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5220 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5221 }
1da177e4
LT		 5222}
5223
5224static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5225{
5226 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5227 int err;
1da177e4
LT		 5228
5229 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5230 return -EINVAL;
5231
5232 if (!netif_running(dev)) {
5233 /* We'll just catch it later when the
5234 * device is up'd.
5235 */
5236 tg3_set_mtu(dev, tp, new_mtu);
5237 return 0;
5238 }
5239
b02fd9e3
MC		 5240 tg3_phy_stop(tp);
5241
1da177e4 5242 tg3_netif_stop(tp);
f47c11ee
DM		 5243
5244 tg3_full_lock(tp, 1);
1da177e4 5245
944d980e 5246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5247
5248 tg3_set_mtu(dev, tp, new_mtu);
5249
b9ec6c1b 5250 err = tg3_restart_hw(tp, 0);
1da177e4 5251
b9ec6c1b
MC		 5252 if (!err)
5253 tg3_netif_start(tp);
1da177e4 5254
f47c11ee 5255 tg3_full_unlock(tp);
1da177e4 5256
b02fd9e3
MC		 5257 if (!err)
5258 tg3_phy_start(tp);
5259
b9ec6c1b 5260 return err;
1da177e4
LT		 5261}
5262
5263/* Free up pending packets in all rx/tx rings.
5264 *
5265 * The chip has been shut down and the driver detached from
5266 * the networking, so no interrupts or new tx packets will
5267 * end up in the driver. tp->{tx,}lock is not held and we are not
5268 * in an interrupt context and thus may sleep.
5269 */
5270static void tg3_free_rings(struct tg3 *tp)
5271{
5272 struct ring_info *rxp;
5273 int i;
5274
5275 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5276 rxp = &tp->rx_std_buffers[i];
5277
5278 if (rxp->skb == NULL)
5279 continue;
5280 pci_unmap_single(tp->pdev,
5281 pci_unmap_addr(rxp, mapping),
7e72aad4 5282 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5283 PCI_DMA_FROMDEVICE);
5284 dev_kfree_skb_any(rxp->skb);
5285 rxp->skb = NULL;
5286 }
5287
5288 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5289 rxp = &tp->rx_jumbo_buffers[i];
5290
5291 if (rxp->skb == NULL)
5292 continue;
5293 pci_unmap_single(tp->pdev,
5294 pci_unmap_addr(rxp, mapping),
5295 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5296 PCI_DMA_FROMDEVICE);
5297 dev_kfree_skb_any(rxp->skb);
5298 rxp->skb = NULL;
5299 }
5300
5301 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5302 struct tx_ring_info *txp;
5303 struct sk_buff *skb;
1da177e4
LT		 5304
5305 txp = &tp->tx_buffers[i];
5306 skb = txp->skb;
5307
5308 if (skb == NULL) {
5309 i++;
5310 continue;
5311 }
5312
90079ce8 5313 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5314
90079ce8 5315 txp->skb = NULL;
1da177e4 5316
90079ce8 5317 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5318
5319 dev_kfree_skb_any(skb);
5320 }
5321}
5322
5323/* Initialize tx/rx rings for packet processing.
5324 *
5325 * The chip has been shut down and the driver detached from
5326 * the networking, so no interrupts or new tx packets will
5327 * end up in the driver. tp->{tx,}lock are held and thus
5328 * we may not sleep.
5329 */
32d8c572 5330static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5331{
5332 u32 i;
5333
5334 /* Free up all the SKBs. */
5335 tg3_free_rings(tp);
5336
5337 /* Zero out all descriptors. */
5338 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5339 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5340 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5341 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5342
7e72aad4 5343 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5344 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5345 (tp->dev->mtu > ETH_DATA_LEN))
5346 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5347
1da177e4
LT		 5348 /* Initialize invariants of the rings, we only set this
5349 * stuff once. This works because the card does not
5350 * write into the rx buffer posting rings.
5351 */
5352 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5353 struct tg3_rx_buffer_desc *rxd;
5354
5355 rxd = &tp->rx_std[i];
7e72aad4 5356 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5357 << RXD_LEN_SHIFT;
5358 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5359 rxd->opaque = (RXD_OPAQUE_RING_STD |
5360 (i << RXD_OPAQUE_INDEX_SHIFT));
5361 }
5362
0f893dc6 5363 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5364 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5365 struct tg3_rx_buffer_desc *rxd;
5366
5367 rxd = &tp->rx_jumbo[i];
5368 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5369 << RXD_LEN_SHIFT;
5370 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5371 RXD_FLAG_JUMBO;
5372 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5373 (i << RXD_OPAQUE_INDEX_SHIFT));
5374 }
5375 }
5376
5377 /* Now allocate fresh SKBs for each rx ring. */
5378 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5379 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5380 printk(KERN_WARNING PFX
5381 "%s: Using a smaller RX standard ring, "
5382 "only %d out of %d buffers were allocated "
5383 "successfully.\n",
5384 tp->dev->name, i, tp->rx_pending);
5385 if (i == 0)
5386 return -ENOMEM;
5387 tp->rx_pending = i;
1da177e4 5388 break;
32d8c572 5389 }
1da177e4
LT		 5390 }
5391
0f893dc6 5392 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5393 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5394 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5395 -1, i) < 0) {
5396 printk(KERN_WARNING PFX
5397 "%s: Using a smaller RX jumbo ring, "
5398 "only %d out of %d buffers were "
5399 "allocated successfully.\n",
5400 tp->dev->name, i, tp->rx_jumbo_pending);
5401 if (i == 0) {
5402 tg3_free_rings(tp);
5403 return -ENOMEM;
5404 }
5405 tp->rx_jumbo_pending = i;
1da177e4 5406 break;
32d8c572 5407 }
1da177e4
LT		 5408 }
5409 }
32d8c572 5410 return 0;
1da177e4
LT		 5411}
5412
5413/*
5414 * Must not be invoked with interrupt sources disabled and
5415 * the hardware shutdown down.
5416 */
5417static void tg3_free_consistent(struct tg3 *tp)
5418{
b4558ea9
JJ		 5419 kfree(tp->rx_std_buffers);
5420 tp->rx_std_buffers = NULL;
1da177e4
LT		 5421 if (tp->rx_std) {
5422 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5423 tp->rx_std, tp->rx_std_mapping);
5424 tp->rx_std = NULL;
5425 }
5426 if (tp->rx_jumbo) {
5427 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5428 tp->rx_jumbo, tp->rx_jumbo_mapping);
5429 tp->rx_jumbo = NULL;
5430 }
5431 if (tp->rx_rcb) {
5432 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5433 tp->rx_rcb, tp->rx_rcb_mapping);
5434 tp->rx_rcb = NULL;
5435 }
5436 if (tp->tx_ring) {
5437 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5438 tp->tx_ring, tp->tx_desc_mapping);
5439 tp->tx_ring = NULL;
5440 }
5441 if (tp->hw_status) {
5442 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5443 tp->hw_status, tp->status_mapping);
5444 tp->hw_status = NULL;
5445 }
5446 if (tp->hw_stats) {
5447 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5448 tp->hw_stats, tp->stats_mapping);
5449 tp->hw_stats = NULL;
5450 }
5451}
5452
5453/*
5454 * Must not be invoked with interrupt sources disabled and
5455 * the hardware shutdown down. Can sleep.
5456 */
5457static int tg3_alloc_consistent(struct tg3 *tp)
5458{
bd2b3343 5459 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5460 (TG3_RX_RING_SIZE +
5461 TG3_RX_JUMBO_RING_SIZE)) +
5462 (sizeof(struct tx_ring_info) *
5463 TG3_TX_RING_SIZE),
5464 GFP_KERNEL);
5465 if (!tp->rx_std_buffers)
5466 return -ENOMEM;
5467
1da177e4
LT		 5468 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5469 tp->tx_buffers = (struct tx_ring_info *)
5470 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5471
5472 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5473 &tp->rx_std_mapping);
5474 if (!tp->rx_std)
5475 goto err_out;
5476
5477 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5478 &tp->rx_jumbo_mapping);
5479
5480 if (!tp->rx_jumbo)
5481 goto err_out;
5482
5483 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5484 &tp->rx_rcb_mapping);
5485 if (!tp->rx_rcb)
5486 goto err_out;
5487
5488 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5489 &tp->tx_desc_mapping);
5490 if (!tp->tx_ring)
5491 goto err_out;
5492
5493 tp->hw_status = pci_alloc_consistent(tp->pdev,
5494 TG3_HW_STATUS_SIZE,
5495 &tp->status_mapping);
5496 if (!tp->hw_status)
5497 goto err_out;
5498
5499 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5500 sizeof(struct tg3_hw_stats),
5501 &tp->stats_mapping);
5502 if (!tp->hw_stats)
5503 goto err_out;
5504
5505 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5506 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5507
5508 return 0;
5509
5510err_out:
5511 tg3_free_consistent(tp);
5512 return -ENOMEM;
5513}
5514
5515#define MAX_WAIT_CNT 1000
5516
5517/* To stop a block, clear the enable bit and poll till it
5518 * clears. tp->lock is held.
5519 */
b3b7d6be 5520static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5521{
5522 unsigned int i;
5523 u32 val;
5524
5525 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5526 switch (ofs) {
5527 case RCVLSC_MODE:
5528 case DMAC_MODE:
5529 case MBFREE_MODE:
5530 case BUFMGR_MODE:
5531 case MEMARB_MODE:
5532 /* We can't enable/disable these bits of the
5533 * 5705/5750, just say success.
5534 */
5535 return 0;
5536
5537 default:
5538 break;
855e1111 5539 }
1da177e4
LT		 5540 }
5541
5542 val = tr32(ofs);
5543 val &= ~enable_bit;
5544 tw32_f(ofs, val);
5545
5546 for (i = 0; i < MAX_WAIT_CNT; i++) {
5547 udelay(100);
5548 val = tr32(ofs);
5549 if ((val & enable_bit) == 0)
5550 break;
5551 }
5552
b3b7d6be 5553 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5554 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5555 "ofs=%lx enable_bit=%x\n",
5556 ofs, enable_bit);
5557 return -ENODEV;
5558 }
5559
5560 return 0;
5561}
5562
5563/* tp->lock is held. */
b3b7d6be 5564static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5565{
5566 int i, err;
5567
5568 tg3_disable_ints(tp);
5569
5570 tp->rx_mode &= ~RX_MODE_ENABLE;
5571 tw32_f(MAC_RX_MODE, tp->rx_mode);
5572 udelay(10);
5573
b3b7d6be
DM		 5574 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5575 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5576 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5577 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5578 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5579 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5580
5581 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5582 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5583 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5584 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5585 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5586 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5587 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5588
5589 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5590 tw32_f(MAC_MODE, tp->mac_mode);
5591 udelay(40);
5592
5593 tp->tx_mode &= ~TX_MODE_ENABLE;
5594 tw32_f(MAC_TX_MODE, tp->tx_mode);
5595
5596 for (i = 0; i < MAX_WAIT_CNT; i++) {
5597 udelay(100);
5598 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5599 break;
5600 }
5601 if (i >= MAX_WAIT_CNT) {
5602 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5603 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5604 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5605 err |= -ENODEV;
1da177e4
LT		 5606 }
5607
e6de8ad1 5608 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5609 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5610 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5611
5612 tw32(FTQ_RESET, 0xffffffff);
5613 tw32(FTQ_RESET, 0x00000000);
5614
b3b7d6be
DM		 5615 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5616 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5617
5618 if (tp->hw_status)
5619 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5620 if (tp->hw_stats)
5621 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5622
1da177e4
LT		 5623 return err;
5624}
5625
5626/* tp->lock is held. */
5627static int tg3_nvram_lock(struct tg3 *tp)
5628{
5629 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5630 int i;
5631
ec41c7df
MC		 5632 if (tp->nvram_lock_cnt == 0) {
5633 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5634 for (i = 0; i < 8000; i++) {
5635 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5636 break;
5637 udelay(20);
5638 }
5639 if (i == 8000) {
5640 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5641 return -ENODEV;
5642 }
1da177e4 5643 }
ec41c7df 5644 tp->nvram_lock_cnt++;
1da177e4
LT		 5645 }
5646 return 0;
5647}
5648
5649/* tp->lock is held. */
5650static void tg3_nvram_unlock(struct tg3 *tp)
5651{
ec41c7df
MC		 5652 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5653 if (tp->nvram_lock_cnt > 0)
5654 tp->nvram_lock_cnt--;
5655 if (tp->nvram_lock_cnt == 0)
5656 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5657 }
1da177e4
LT		 5658}
5659
e6af301b
MC		 5660/* tp->lock is held. */
5661static void tg3_enable_nvram_access(struct tg3 *tp)
5662{
5663 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5664 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5665 u32 nvaccess = tr32(NVRAM_ACCESS);
5666
5667 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5668 }
5669}
5670
5671/* tp->lock is held. */
5672static void tg3_disable_nvram_access(struct tg3 *tp)
5673{
5674 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5675 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5676 u32 nvaccess = tr32(NVRAM_ACCESS);
5677
5678 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5679 }
5680}
5681
0d3031d9
MC		 5682static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5683{
5684 int i;
5685 u32 apedata;
5686
5687 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5688 if (apedata != APE_SEG_SIG_MAGIC)
5689 return;
5690
5691 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5692 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5693 return;
5694
5695 /* Wait for up to 1 millisecond for APE to service previous event. */
5696 for (i = 0; i < 10; i++) {
5697 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5698 return;
5699
5700 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5701
5702 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5703 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5704 event | APE_EVENT_STATUS_EVENT_PENDING);
5705
5706 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5707
5708 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5709 break;
5710
5711 udelay(100);
5712 }
5713
5714 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5715 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5716}
5717
5718static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5719{
5720 u32 event;
5721 u32 apedata;
5722
5723 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5724 return;
5725
5726 switch (kind) {
5727 case RESET_KIND_INIT:
5728 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5729 APE_HOST_SEG_SIG_MAGIC);
5730 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5731 APE_HOST_SEG_LEN_MAGIC);
5732 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5733 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5734 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5735 APE_HOST_DRIVER_ID_MAGIC);
5736 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5737 APE_HOST_BEHAV_NO_PHYLOCK);
5738
5739 event = APE_EVENT_STATUS_STATE_START;
5740 break;
5741 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5742 /* With the interface we are currently using,
5743 * APE does not track driver state. Wiping
5744 * out the HOST SEGMENT SIGNATURE forces
5745 * the APE to assume OS absent status.
5746 */
5747 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5748
0d3031d9
MC		 5749 event = APE_EVENT_STATUS_STATE_UNLOAD;
5750 break;
5751 case RESET_KIND_SUSPEND:
5752 event = APE_EVENT_STATUS_STATE_SUSPEND;
5753 break;
5754 default:
5755 return;
5756 }
5757
5758 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5759
5760 tg3_ape_send_event(tp, event);
5761}
5762
1da177e4
LT		 5763/* tp->lock is held. */
5764static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5765{
f49639e6
DM		 5766 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5767 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5768
5769 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5770 switch (kind) {
5771 case RESET_KIND_INIT:
5772 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5773 DRV_STATE_START);
5774 break;
5775
5776 case RESET_KIND_SHUTDOWN:
5777 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5778 DRV_STATE_UNLOAD);
5779 break;
5780
5781 case RESET_KIND_SUSPEND:
5782 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5783 DRV_STATE_SUSPEND);
5784 break;
5785
5786 default:
5787 break;
855e1111 5788 }
1da177e4 5789 }
0d3031d9
MC		 5790
5791 if (kind == RESET_KIND_INIT ||
5792 kind == RESET_KIND_SUSPEND)
5793 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5794}
5795
5796/* tp->lock is held. */
5797static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5798{
5799 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5800 switch (kind) {
5801 case RESET_KIND_INIT:
5802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5803 DRV_STATE_START_DONE);
5804 break;
5805
5806 case RESET_KIND_SHUTDOWN:
5807 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5808 DRV_STATE_UNLOAD_DONE);
5809 break;
5810
5811 default:
5812 break;
855e1111 5813 }
1da177e4 5814 }
0d3031d9
MC		 5815
5816 if (kind == RESET_KIND_SHUTDOWN)
5817 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5818}
5819
5820/* tp->lock is held. */
5821static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5822{
5823 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5824 switch (kind) {
5825 case RESET_KIND_INIT:
5826 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5827 DRV_STATE_START);
5828 break;
5829
5830 case RESET_KIND_SHUTDOWN:
5831 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5832 DRV_STATE_UNLOAD);
5833 break;
5834
5835 case RESET_KIND_SUSPEND:
5836 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5837 DRV_STATE_SUSPEND);
5838 break;
5839
5840 default:
5841 break;
855e1111 5842 }
1da177e4
LT		 5843 }
5844}
5845
7a6f4369
MC		 5846static int tg3_poll_fw(struct tg3 *tp)
5847{
5848 int i;
5849 u32 val;
5850
b5d3772c 5851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 5852 /* Wait up to 20ms for init done. */
5853 for (i = 0; i < 200; i++) {
b5d3772c
MC		 5854 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5855 return 0;
0ccead18 5856 udelay(100);
b5d3772c
MC		 5857 }
5858 return -ENODEV;
5859 }
5860
7a6f4369
MC		 5861 /* Wait for firmware initialization to complete. */
5862 for (i = 0; i < 100000; i++) {
5863 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5864 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5865 break;
5866 udelay(10);
5867 }
5868
5869 /* Chip might not be fitted with firmware. Some Sun onboard
5870 * parts are configured like that. So don't signal the timeout
5871 * of the above loop as an error, but do report the lack of
5872 * running firmware once.
5873 */
5874 if (i >= 100000 &&
5875 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5876 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5877
5878 printk(KERN_INFO PFX "%s: No firmware running.\n",
5879 tp->dev->name);
5880 }
5881
5882 return 0;
5883}
5884
ee6a99b5
MC		 5885/* Save PCI command register before chip reset */
5886static void tg3_save_pci_state(struct tg3 *tp)
5887{
8a6eac90 5888 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 5889}
5890
5891/* Restore PCI state after chip reset */
5892static void tg3_restore_pci_state(struct tg3 *tp)
5893{
5894 u32 val;
5895
5896 /* Re-enable indirect register accesses. */
5897 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5898 tp->misc_host_ctrl);
5899
5900 /* Set MAX PCI retry to zero. */
5901 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5902 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5903 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5904 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 5905 /* Allow reads and writes to the APE register and memory space. */
5906 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5907 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5908 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 5909 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5910
8a6eac90 5911 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 5912
fcb389df
MC		 5913 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
5914 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5915 pcie_set_readrq(tp->pdev, 4096);
5916 else {
5917 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5918 tp->pci_cacheline_sz);
5919 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5920 tp->pci_lat_timer);
5921 }
114342f2 5922 }
5f5c51e3 5923
ee6a99b5 5924 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 5925 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 5926 u16 pcix_cmd;
5927
5928 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5929 &pcix_cmd);
5930 pcix_cmd &= ~PCI_X_CMD_ERO;
5931 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5932 pcix_cmd);
5933 }
ee6a99b5
MC		 5934
5935 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 5936
5937 /* Chip reset on 5780 will reset MSI enable bit,
5938 * so need to restore it.
5939 */
5940 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5941 u16 ctrl;
5942
5943 pci_read_config_word(tp->pdev,
5944 tp->msi_cap + PCI_MSI_FLAGS,
5945 &ctrl);
5946 pci_write_config_word(tp->pdev,
5947 tp->msi_cap + PCI_MSI_FLAGS,
5948 ctrl | PCI_MSI_FLAGS_ENABLE);
5949 val = tr32(MSGINT_MODE);
5950 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5951 }
5952 }
5953}
5954
1da177e4
LT		 5955static void tg3_stop_fw(struct tg3 *);
5956
5957/* tp->lock is held. */
5958static int tg3_chip_reset(struct tg3 *tp)
5959{
5960 u32 val;
1ee582d8 5961 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 5962 int err;
1da177e4 5963
f49639e6
DM		 5964 tg3_nvram_lock(tp);
5965
158d7abd
MC		 5966 tg3_mdio_stop(tp);
5967
77b483f1
MC		 5968 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5969
f49639e6
DM		 5970 /* No matching tg3_nvram_unlock() after this because
5971 * chip reset below will undo the nvram lock.
5972 */
5973 tp->nvram_lock_cnt = 0;
1da177e4 5974
ee6a99b5
MC		 5975 /* GRC_MISC_CFG core clock reset will clear the memory
5976 * enable bit in PCI register 4 and the MSI enable bit
5977 * on some chips, so we save relevant registers here.
5978 */
5979 tg3_save_pci_state(tp);
5980
d9ab5ad1 5981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 5982 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 5983 tw32(GRC_FASTBOOT_PC, 0);
5984
1da177e4
LT		 5985 /*
5986 * We must avoid the readl() that normally takes place.
5987 * It locks machines, causes machine checks, and other
5988 * fun things. So, temporarily disable the 5701
5989 * hardware workaround, while we do the reset.
5990 */
1ee582d8
MC		 5991 write_op = tp->write32;
5992 if (write_op == tg3_write_flush_reg32)
5993 tp->write32 = tg3_write32;
1da177e4 5994
d18edcb2
MC		 5995 /* Prevent the irq handler from reading or writing PCI registers
5996 * during chip reset when the memory enable bit in the PCI command
5997 * register may be cleared. The chip does not generate interrupt
5998 * at this time, but the irq handler may still be called due to irq
5999 * sharing or irqpoll.
6000 */
6001 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6002 if (tp->hw_status) {
6003 tp->hw_status->status = 0;
6004 tp->hw_status->status_tag = 0;
6005 }
d18edcb2
MC		 6006 tp->last_tag = 0;
6007 smp_mb();
6008 synchronize_irq(tp->pdev->irq);
6009
1da177e4
LT		 6010 /* do the reset */
6011 val = GRC_MISC_CFG_CORECLK_RESET;
6012
6013 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6014 if (tr32(0x7e2c) == 0x60) {
6015 tw32(0x7e2c, 0x20);
6016 }
6017 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6018 tw32(GRC_MISC_CFG, (1 << 29));
6019 val |= (1 << 29);
6020 }
6021 }
6022
b5d3772c
MC		 6023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6024 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6025 tw32(GRC_VCPU_EXT_CTRL,
6026 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6027 }
6028
1da177e4
LT		 6029 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6030 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6031 tw32(GRC_MISC_CFG, val);
6032
1ee582d8
MC		 6033 /* restore 5701 hardware bug workaround write method */
6034 tp->write32 = write_op;
1da177e4
LT		 6035
6036 /* Unfortunately, we have to delay before the PCI read back.
6037 * Some 575X chips even will not respond to a PCI cfg access
6038 * when the reset command is given to the chip.
6039 *
6040 * How do these hardware designers expect things to work
6041 * properly if the PCI write is posted for a long period
6042 * of time? It is always necessary to have some method by
6043 * which a register read back can occur to push the write
6044 * out which does the reset.
6045 *
6046 * For most tg3 variants the trick below was working.
6047 * Ho hum...
6048 */
6049 udelay(120);
6050
6051 /* Flush PCI posted writes. The normal MMIO registers
6052 * are inaccessible at this time so this is the only
6053 * way to make this reliably (actually, this is no longer
6054 * the case, see above). I tried to use indirect
6055 * register read/write but this upset some 5701 variants.
6056 */
6057 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6058
6059 udelay(120);
6060
5e7dfd0f 6061 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6062 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6063 int i;
6064 u32 cfg_val;
6065
6066 /* Wait for link training to complete. */
6067 for (i = 0; i < 5000; i++)
6068 udelay(100);
6069
6070 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6071 pci_write_config_dword(tp->pdev, 0xc4,
6072 cfg_val | (1 << 15));
6073 }
5e7dfd0f
MC		 6074
6075 /* Set PCIE max payload size to 128 bytes and
6076 * clear the "no snoop" and "relaxed ordering" bits.
6077 */
6078 pci_write_config_word(tp->pdev,
6079 tp->pcie_cap + PCI_EXP_DEVCTL,
6080 0);
6081
6082 pcie_set_readrq(tp->pdev, 4096);
6083
6084 /* Clear error status */
6085 pci_write_config_word(tp->pdev,
6086 tp->pcie_cap + PCI_EXP_DEVSTA,
6087 PCI_EXP_DEVSTA_CED |
6088 PCI_EXP_DEVSTA_NFED |
6089 PCI_EXP_DEVSTA_FED |
6090 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6091 }
6092
ee6a99b5 6093 tg3_restore_pci_state(tp);
1da177e4 6094
d18edcb2
MC		 6095 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6096
ee6a99b5
MC		 6097 val = 0;
6098 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6099 val = tr32(MEMARB_MODE);
ee6a99b5 6100 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6101
6102 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6103 tg3_stop_fw(tp);
6104 tw32(0x5000, 0x400);
6105 }
6106
6107 tw32(GRC_MODE, tp->grc_mode);
6108
6109 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6110 val = tr32(0xc4);
1da177e4
LT		 6111
6112 tw32(0xc4, val | (1 << 15));
6113 }
6114
6115 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6117 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6118 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6119 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6120 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6121 }
6122
6123 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6124 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6125 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6126 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6127 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6128 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6129 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6130 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6131 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6132 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6133 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6134 } else
6135 tw32_f(MAC_MODE, 0);
6136 udelay(40);
6137
158d7abd
MC		 6138 tg3_mdio_start(tp);
6139
77b483f1
MC		 6140 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6141
7a6f4369
MC		 6142 err = tg3_poll_fw(tp);
6143 if (err)
6144 return err;
1da177e4
LT		 6145
6146 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6147 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6148 val = tr32(0x7c00);
1da177e4
LT		 6149
6150 tw32(0x7c00, val | (1 << 25));
6151 }
6152
6153 /* Reprobe ASF enable state. */
6154 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6155 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6156 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6157 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6158 u32 nic_cfg;
6159
6160 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6161 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6162 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6163 tp->last_event_jiffies = jiffies;
cbf46853 6164 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6165 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6166 }
6167 }
6168
6169 return 0;
6170}
6171
6172/* tp->lock is held. */
6173static void tg3_stop_fw(struct tg3 *tp)
6174{
0d3031d9
MC		 6175 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6176 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6177 /* Wait for RX cpu to ACK the previous event. */
6178 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6179
6180 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6181
6182 tg3_generate_fw_event(tp);
1da177e4 6183
7c5026aa
MC		 6184 /* Wait for RX cpu to ACK this event. */
6185 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6186 }
6187}
6188
6189/* tp->lock is held. */
944d980e 6190static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6191{
6192 int err;
6193
6194 tg3_stop_fw(tp);
6195
944d980e 6196 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6197
b3b7d6be 6198 tg3_abort_hw(tp, silent);
1da177e4
LT		 6199 err = tg3_chip_reset(tp);
6200
944d980e
MC		 6201 tg3_write_sig_legacy(tp, kind);
6202 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6203
6204 if (err)
6205 return err;
6206
6207 return 0;
6208}
6209
6210#define TG3_FW_RELEASE_MAJOR 0x0
6211#define TG3_FW_RELASE_MINOR 0x0
6212#define TG3_FW_RELEASE_FIX 0x0
6213#define TG3_FW_START_ADDR 0x08000000
6214#define TG3_FW_TEXT_ADDR 0x08000000
6215#define TG3_FW_TEXT_LEN 0x9c0
6216#define TG3_FW_RODATA_ADDR 0x080009c0
6217#define TG3_FW_RODATA_LEN 0x60
6218#define TG3_FW_DATA_ADDR 0x08000a40
6219#define TG3_FW_DATA_LEN 0x20
6220#define TG3_FW_SBSS_ADDR 0x08000a60
6221#define TG3_FW_SBSS_LEN 0xc
6222#define TG3_FW_BSS_ADDR 0x08000a70
6223#define TG3_FW_BSS_LEN 0x10
6224
50da859d 6225static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 6226 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6227 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6228 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6229 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6230 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6231 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6232 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6233 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6234 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6235 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6236 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6237 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6238 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6239 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6240 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6241 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6242 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6243 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6244 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6245 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6246 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6247 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6248 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6251 0, 0, 0, 0, 0, 0,
6252 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6253 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6254 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6255 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6256 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6257 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6258 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6259 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6260 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6261 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6262 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6266 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6267 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6268 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6269 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6270 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6271 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6272 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6273 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6274 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6275 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6276 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6277 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6278 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6279 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6280 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6281 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6282 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6283 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6284 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6285 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6286 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6287 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6288 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6289 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6290 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6291 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6292 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6293 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6294 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6295 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6296 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6297 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6298 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6299 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6300 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6301 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6302 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6303 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6304 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6305 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6306 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6307 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6308 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6309 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6310 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6311 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6312 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6313 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6314 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6315 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6316 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6317};
6318
50da859d 6319static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 6320 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6321 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6322 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6323 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6324 0x00000000
6325};
6326
6327#if 0 /* All zeros, don't eat up space with it. */
6328u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6329 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6330 0x00000000, 0x00000000, 0x00000000, 0x00000000
6331};
6332#endif
6333
6334#define RX_CPU_SCRATCH_BASE 0x30000
6335#define RX_CPU_SCRATCH_SIZE 0x04000
6336#define TX_CPU_SCRATCH_BASE 0x34000
6337#define TX_CPU_SCRATCH_SIZE 0x04000
6338
6339/* tp->lock is held. */
6340static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6341{
6342 int i;
6343
5d9428de
ES		 6344 BUG_ON(offset == TX_CPU_BASE &&
6345 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6346
b5d3772c
MC		 6347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6348 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6349
6350 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6351 return 0;
6352 }
1da177e4
LT		 6353 if (offset == RX_CPU_BASE) {
6354 for (i = 0; i < 10000; i++) {
6355 tw32(offset + CPU_STATE, 0xffffffff);
6356 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6357 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6358 break;
6359 }
6360
6361 tw32(offset + CPU_STATE, 0xffffffff);
6362 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6363 udelay(10);
6364 } else {
6365 for (i = 0; i < 10000; i++) {
6366 tw32(offset + CPU_STATE, 0xffffffff);
6367 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6368 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6369 break;
6370 }
6371 }
6372
6373 if (i >= 10000) {
6374 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6375 "and %s CPU\n",
6376 tp->dev->name,
6377 (offset == RX_CPU_BASE ? "RX" : "TX"));
6378 return -ENODEV;
6379 }
ec41c7df
MC		 6380
6381 /* Clear firmware's nvram arbitration. */
6382 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6383 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6384 return 0;
6385}
6386
6387struct fw_info {
6388 unsigned int text_base;
6389 unsigned int text_len;
50da859d 6390 const u32 *text_data;
1da177e4
LT		 6391 unsigned int rodata_base;
6392 unsigned int rodata_len;
50da859d 6393 const u32 *rodata_data;
1da177e4
LT		 6394 unsigned int data_base;
6395 unsigned int data_len;
50da859d 6396 const u32 *data_data;
1da177e4
LT		 6397};
6398
6399/* tp->lock is held. */
6400static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6401 int cpu_scratch_size, struct fw_info *info)
6402{
ec41c7df 6403 int err, lock_err, i;
1da177e4
LT		 6404 void (*write_op)(struct tg3 *, u32, u32);
6405
6406 if (cpu_base == TX_CPU_BASE &&
6407 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6408 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6409 "TX cpu firmware on %s which is 5705.\n",
6410 tp->dev->name);
6411 return -EINVAL;
6412 }
6413
6414 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6415 write_op = tg3_write_mem;
6416 else
6417 write_op = tg3_write_indirect_reg32;
6418
1b628151
MC		 6419 /* It is possible that bootcode is still loading at this point.
6420 * Get the nvram lock first before halting the cpu.
6421 */
ec41c7df 6422 lock_err = tg3_nvram_lock(tp);
1da177e4 6423 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6424 if (!lock_err)
6425 tg3_nvram_unlock(tp);
1da177e4
LT		 6426 if (err)
6427 goto out;
6428
6429 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6430 write_op(tp, cpu_scratch_base + i, 0);
6431 tw32(cpu_base + CPU_STATE, 0xffffffff);
6432 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6433 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6434 write_op(tp, (cpu_scratch_base +
6435 (info->text_base & 0xffff) +
6436 (i * sizeof(u32))),
6437 (info->text_data ?
6438 info->text_data[i] : 0));
6439 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6440 write_op(tp, (cpu_scratch_base +
6441 (info->rodata_base & 0xffff) +
6442 (i * sizeof(u32))),
6443 (info->rodata_data ?
6444 info->rodata_data[i] : 0));
6445 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6446 write_op(tp, (cpu_scratch_base +
6447 (info->data_base & 0xffff) +
6448 (i * sizeof(u32))),
6449 (info->data_data ?
6450 info->data_data[i] : 0));
6451
6452 err = 0;
6453
6454out:
1da177e4
LT		 6455 return err;
6456}
6457
6458/* tp->lock is held. */
6459static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6460{
6461 struct fw_info info;
6462 int err, i;
6463
6464 info.text_base = TG3_FW_TEXT_ADDR;
6465 info.text_len = TG3_FW_TEXT_LEN;
6466 info.text_data = &tg3FwText[0];
6467 info.rodata_base = TG3_FW_RODATA_ADDR;
6468 info.rodata_len = TG3_FW_RODATA_LEN;
6469 info.rodata_data = &tg3FwRodata[0];
6470 info.data_base = TG3_FW_DATA_ADDR;
6471 info.data_len = TG3_FW_DATA_LEN;
6472 info.data_data = NULL;
6473
6474 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6475 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6476 &info);
6477 if (err)
6478 return err;
6479
6480 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6481 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6482 &info);
6483 if (err)
6484 return err;
6485
6486 /* Now startup only the RX cpu. */
6487 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6488 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6489
6490 for (i = 0; i < 5; i++) {
6491 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6492 break;
6493 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6494 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6495 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6496 udelay(1000);
6497 }
6498 if (i >= 5) {
6499 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6500 "to set RX CPU PC, is %08x should be %08x\n",
6501 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6502 TG3_FW_TEXT_ADDR);
6503 return -ENODEV;
6504 }
6505 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6506 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6507
6508 return 0;
6509}
6510
1da177e4
LT		 6511
6512#define TG3_TSO_FW_RELEASE_MAJOR 0x1
6513#define TG3_TSO_FW_RELASE_MINOR 0x6
6514#define TG3_TSO_FW_RELEASE_FIX 0x0
6515#define TG3_TSO_FW_START_ADDR 0x08000000
6516#define TG3_TSO_FW_TEXT_ADDR 0x08000000
6517#define TG3_TSO_FW_TEXT_LEN 0x1aa0
6518#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
6519#define TG3_TSO_FW_RODATA_LEN 0x60
6520#define TG3_TSO_FW_DATA_ADDR 0x08001b20
6521#define TG3_TSO_FW_DATA_LEN 0x30
6522#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
6523#define TG3_TSO_FW_SBSS_LEN 0x2c
6524#define TG3_TSO_FW_BSS_ADDR 0x08001b80
6525#define TG3_TSO_FW_BSS_LEN 0x894
6526
50da859d 6527static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 6528 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6529 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6530 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6531 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6532 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6533 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6534 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6535 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6536 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6537 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6538 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6539 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6540 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6541 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6542 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6543 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6544 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6545 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6546 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6547 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6548 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6549 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6550 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6551 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6552 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6553 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6554 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6555 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6556 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6557 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6558 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6559 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6560 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6561 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6562 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6563 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6564 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6565 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6566 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6567 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6568 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6569 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6570 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6571 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6572 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6573 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6574 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6575 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6576 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6577 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6578 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6579 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6580 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6581 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6582 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6583 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6584 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6585 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6586 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6587 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6588 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6589 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6590 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6591 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6592 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6593 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6594 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6595 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6596 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6597 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6598 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6599 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6600 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6601 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6602 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6603 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6604 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6605 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6606 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6607 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6608 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6609 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6610 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6611 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6612 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6613 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6614 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6615 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6616 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6617 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6618 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6619 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6620 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6621 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6622 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6623 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6624 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6625 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6626 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6627 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6628 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6629 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6630 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6631 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6632 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6633 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6634 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6635 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6636 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6637 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6638 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6639 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6640 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6641 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6642 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6643 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6644 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6645 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6646 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6647 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6648 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6649 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6650 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6651 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6652 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6653 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6654 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6655 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6656 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6657 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6658 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6659 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6660 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6661 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6662 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6663 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6664 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6665 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6666 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6667 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6668 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6669 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6670 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6671 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6672 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6673 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6674 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6675 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6676 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6677 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6678 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6679 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6680 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6681 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6682 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6683 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6684 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6685 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6686 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6687 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6688 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6689 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6690 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6691 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6692 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6693 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6694 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6695 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6696 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6697 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6698 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6699 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6700 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6701 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6702 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6703 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6704 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6705 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6706 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6707 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6708 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6709 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6710 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6711 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6712 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6713 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6714 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6715 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6716 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6717 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6718 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6719 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6720 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6721 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6722 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6723 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6724 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6725 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6726 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6727 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6728 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6729 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6730 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6731 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6732 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6733 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6734 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6735 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6736 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6737 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6738 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6739 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6740 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6741 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6742 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6743 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6744 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6745 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6746 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6747 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6748 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6749 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6750 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6751 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6752 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6753 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6754 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6755 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6756 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6757 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6758 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6759 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6760 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6761 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6762 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6763 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6764 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6765 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6766 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6767 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6768 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6769 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6770 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6771 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6772 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6773 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6774 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6775 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6776 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6777 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6778 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6779 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6780 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6781 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6782 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6783 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6784 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6785 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6786 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6787 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6788 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6789 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6790 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6791 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6792 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6793 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6794 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6795 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6796 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6797 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6798 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6799 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6800 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6801 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6802 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6803 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6804 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6805 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6806 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6807 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6808 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6809 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6810 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6811 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6812};
6813
50da859d 6814static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 6815 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6816 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6817 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6818 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6819 0x00000000,
6820};
6821
50da859d 6822static const u32 tg3TsoFwData[] = {
1da177e4
LT		 6823 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6824 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6825 0x00000000,
6826};
6827
6828/* 5705 needs a special version of the TSO firmware. */
6829#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6830#define TG3_TSO5_FW_RELASE_MINOR 0x2
6831#define TG3_TSO5_FW_RELEASE_FIX 0x0
6832#define TG3_TSO5_FW_START_ADDR 0x00010000
6833#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6834#define TG3_TSO5_FW_TEXT_LEN 0xe90
6835#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6836#define TG3_TSO5_FW_RODATA_LEN 0x50
6837#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6838#define TG3_TSO5_FW_DATA_LEN 0x20
6839#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6840#define TG3_TSO5_FW_SBSS_LEN 0x28
6841#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6842#define TG3_TSO5_FW_BSS_LEN 0x88
6843
50da859d 6844static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 6845 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6846 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6847 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6848 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6849 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6850 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6851 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6852 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6853 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6854 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6855 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6856 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6857 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6858 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6859 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6860 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6861 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6862 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6863 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6864 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6865 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6866 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6867 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6868 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6869 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6870 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6871 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6872 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6873 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6874 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6875 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6876 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6877 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6878 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6879 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6880 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6881 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6882 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6883 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6884 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6885 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6886 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6887 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6888 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6889 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6890 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6891 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6892 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6893 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6894 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6895 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6896 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6897 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6898 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6899 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6900 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6901 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6902 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6903 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6904 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6905 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6906 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6907 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6908 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6909 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6910 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6911 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6912 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6913 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6914 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6915 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6916 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6917 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6918 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6919 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6920 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6921 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6922 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6923 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6924 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6925 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6926 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6927 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6928 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6929 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6930 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6931 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6932 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6933 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6934 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6935 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6936 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6937 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6938 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6939 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6940 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6941 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6942 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6943 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6944 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6945 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6946 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6947 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6948 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6949 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6950 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6951 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6952 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6953 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6954 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6955 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6956 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6957 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6958 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6959 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6960 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6961 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6962 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6963 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6964 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6965 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6966 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6967 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6968 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6969 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6970 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6971 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6972 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6973 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6974 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6975 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6976 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6977 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6978 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6979 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6980 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6981 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6982 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6983 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6984 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6985 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6986 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6987 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6988 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6989 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6990 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6991 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6992 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6993 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6994 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6995 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6996 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6997 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6998 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6999 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
7000 0x00000000, 0x00000000, 0x00000000,
7001};
7002
50da859d 7003static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 7004 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
7005 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
7006 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
7007 0x00000000, 0x00000000, 0x00000000,
7008};
7009
50da859d 7010static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 7011 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
7012 0x00000000, 0x00000000, 0x00000000,
7013};
7014
7015/* tp->lock is held. */
7016static int tg3_load_tso_firmware(struct tg3 *tp)
7017{
7018 struct fw_info info;
7019 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7020 int err, i;
7021
7022 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7023 return 0;
7024
7025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7026 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
7027 info.text_len = TG3_TSO5_FW_TEXT_LEN;
7028 info.text_data = &tg3Tso5FwText[0];
7029 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
7030 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
7031 info.rodata_data = &tg3Tso5FwRodata[0];
7032 info.data_base = TG3_TSO5_FW_DATA_ADDR;
7033 info.data_len = TG3_TSO5_FW_DATA_LEN;
7034 info.data_data = &tg3Tso5FwData[0];
7035 cpu_base = RX_CPU_BASE;
7036 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7037 cpu_scratch_size = (info.text_len +
7038 info.rodata_len +
7039 info.data_len +
7040 TG3_TSO5_FW_SBSS_LEN +
7041 TG3_TSO5_FW_BSS_LEN);
7042 } else {
7043 info.text_base = TG3_TSO_FW_TEXT_ADDR;
7044 info.text_len = TG3_TSO_FW_TEXT_LEN;
7045 info.text_data = &tg3TsoFwText[0];
7046 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
7047 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
7048 info.rodata_data = &tg3TsoFwRodata[0];
7049 info.data_base = TG3_TSO_FW_DATA_ADDR;
7050 info.data_len = TG3_TSO_FW_DATA_LEN;
7051 info.data_data = &tg3TsoFwData[0];
7052 cpu_base = TX_CPU_BASE;
7053 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7054 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7055 }
7056
7057 err = tg3_load_firmware_cpu(tp, cpu_base,
7058 cpu_scratch_base, cpu_scratch_size,
7059 &info);
7060 if (err)
7061 return err;
7062
7063 /* Now startup the cpu. */
7064 tw32(cpu_base + CPU_STATE, 0xffffffff);
7065 tw32_f(cpu_base + CPU_PC, info.text_base);
7066
7067 for (i = 0; i < 5; i++) {
7068 if (tr32(cpu_base + CPU_PC) == info.text_base)
7069 break;
7070 tw32(cpu_base + CPU_STATE, 0xffffffff);
7071 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7072 tw32_f(cpu_base + CPU_PC, info.text_base);
7073 udelay(1000);
7074 }
7075 if (i >= 5) {
7076 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7077 "to set CPU PC, is %08x should be %08x\n",
7078 tp->dev->name, tr32(cpu_base + CPU_PC),
7079 info.text_base);
7080 return -ENODEV;
7081 }
7082 tw32(cpu_base + CPU_STATE, 0xffffffff);
7083 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7084 return 0;
7085}
7086
1da177e4 7087
1da177e4
LT		 7088static int tg3_set_mac_addr(struct net_device *dev, void *p)
7089{
7090 struct tg3 *tp = netdev_priv(dev);
7091 struct sockaddr *addr = p;
986e0aeb 7092 int err = 0, skip_mac_1 = 0;
1da177e4 7093
f9804ddb
MC		 7094 if (!is_valid_ether_addr(addr->sa_data))
7095 return -EINVAL;
7096
1da177e4
LT		 7097 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7098
e75f7c90
MC		 7099 if (!netif_running(dev))
7100 return 0;
7101
58712ef9 7102 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7103 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7104
986e0aeb
MC		 7105 addr0_high = tr32(MAC_ADDR_0_HIGH);
7106 addr0_low = tr32(MAC_ADDR_0_LOW);
7107 addr1_high = tr32(MAC_ADDR_1_HIGH);
7108 addr1_low = tr32(MAC_ADDR_1_LOW);
7109
7110 /* Skip MAC addr 1 if ASF is using it. */
7111 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7112 !(addr1_high == 0 && addr1_low == 0))
7113 skip_mac_1 = 1;
58712ef9 7114 }
986e0aeb
MC		 7115 spin_lock_bh(&tp->lock);
7116 __tg3_set_mac_addr(tp, skip_mac_1);
7117 spin_unlock_bh(&tp->lock);
1da177e4 7118
b9ec6c1b 7119 return err;
1da177e4
LT		 7120}
7121
7122/* tp->lock is held. */
7123static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7124 dma_addr_t mapping, u32 maxlen_flags,
7125 u32 nic_addr)
7126{
7127 tg3_write_mem(tp,
7128 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7129 ((u64) mapping >> 32));
7130 tg3_write_mem(tp,
7131 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7132 ((u64) mapping & 0xffffffff));
7133 tg3_write_mem(tp,
7134 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7135 maxlen_flags);
7136
7137 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7138 tg3_write_mem(tp,
7139 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7140 nic_addr);
7141}
7142
7143static void __tg3_set_rx_mode(struct net_device *);
d244c892 7144static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 7145{
7146 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7147 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7148 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7149 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7150 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7151 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7152 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7153 }
7154 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7155 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7157 u32 val = ec->stats_block_coalesce_usecs;
7158
7159 if (!netif_carrier_ok(tp->dev))
7160 val = 0;
7161
7162 tw32(HOSTCC_STAT_COAL_TICKS, val);
7163 }
7164}
1da177e4
LT		 7165
7166/* tp->lock is held. */
8e7a22e3 7167static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7168{
7169 u32 val, rdmac_mode;
7170 int i, err, limit;
7171
7172 tg3_disable_ints(tp);
7173
7174 tg3_stop_fw(tp);
7175
7176 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7177
7178 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7179 tg3_abort_hw(tp, 1);
1da177e4
LT		 7180 }
7181
dd477003
MC		 7182 if (reset_phy &&
7183 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7184 tg3_phy_reset(tp);
7185
1da177e4
LT		 7186 err = tg3_chip_reset(tp);
7187 if (err)
7188 return err;
7189
7190 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7191
bcb37f6c 7192 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7193 val = tr32(TG3_CPMU_CTRL);
7194 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7195 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7196
7197 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7198 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7199 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7200 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7201
7202 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7203 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7204 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7205 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7206
7207 val = tr32(TG3_CPMU_HST_ACC);
7208 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7209 val |= CPMU_HST_ACC_MACCLK_6_25;
7210 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7211 }
7212
1da177e4
LT		 7213 /* This works around an issue with Athlon chipsets on
7214 * B3 tigon3 silicon. This bit has no effect on any
7215 * other revision. But do not set this on PCI Express
795d01c5 7216 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7217 */
795d01c5
MC		 7218 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7219 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7220 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7221 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7222 }
1da177e4
LT		 7223
7224 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7225 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7226 val = tr32(TG3PCI_PCISTATE);
7227 val |= PCISTATE_RETRY_SAME_DMA;
7228 tw32(TG3PCI_PCISTATE, val);
7229 }
7230
0d3031d9
MC		 7231 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7232 /* Allow reads and writes to the
7233 * APE register and memory space.
7234 */
7235 val = tr32(TG3PCI_PCISTATE);
7236 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7237 PCISTATE_ALLOW_APE_SHMEM_WR;
7238 tw32(TG3PCI_PCISTATE, val);
7239 }
7240
1da177e4
LT		 7241 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7242 /* Enable some hw fixes. */
7243 val = tr32(TG3PCI_MSI_DATA);
7244 val |= (1 << 26) | (1 << 28) | (1 << 29);
7245 tw32(TG3PCI_MSI_DATA, val);
7246 }
7247
7248 /* Descriptor ring init may make accesses to the
7249 * NIC SRAM area to setup the TX descriptors, so we
7250 * can only do this after the hardware has been
7251 * successfully reset.
7252 */
32d8c572
MC		 7253 err = tg3_init_rings(tp);
7254 if (err)
7255 return err;
1da177e4 7256
9936bcf6 7257 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 7258 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7259 /* This value is determined during the probe time DMA
7260 * engine test, tg3_test_dma.
7261 */
7262 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7263 }
1da177e4
LT		 7264
7265 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7266 GRC_MODE_4X_NIC_SEND_RINGS |
7267 GRC_MODE_NO_TX_PHDR_CSUM |
7268 GRC_MODE_NO_RX_PHDR_CSUM);
7269 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7270
7271 /* Pseudo-header checksum is done by hardware logic and not
7272 * the offload processers, so make the chip do the pseudo-
7273 * header checksums on receive. For transmit it is more
7274 * convenient to do the pseudo-header checksum in software
7275 * as Linux does that on transmit for us in all cases.
7276 */
7277 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7278
7279 tw32(GRC_MODE,
7280 tp->grc_mode |
7281 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7282
7283 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7284 val = tr32(GRC_MISC_CFG);
7285 val &= ~0xff;
7286 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7287 tw32(GRC_MISC_CFG, val);
7288
7289 /* Initialize MBUF/DESC pool. */
cbf46853 7290 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7291 /* Do nothing. */
7292 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7293 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7295 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7296 else
7297 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7298 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7299 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7300 }
1da177e4
LT		 7301 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7302 int fw_len;
7303
7304 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7305 TG3_TSO5_FW_RODATA_LEN +
7306 TG3_TSO5_FW_DATA_LEN +
7307 TG3_TSO5_FW_SBSS_LEN +
7308 TG3_TSO5_FW_BSS_LEN);
7309 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7310 tw32(BUFMGR_MB_POOL_ADDR,
7311 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7312 tw32(BUFMGR_MB_POOL_SIZE,
7313 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7314 }
1da177e4 7315
0f893dc6 7316 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7317 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7318 tp->bufmgr_config.mbuf_read_dma_low_water);
7319 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7320 tp->bufmgr_config.mbuf_mac_rx_low_water);
7321 tw32(BUFMGR_MB_HIGH_WATER,
7322 tp->bufmgr_config.mbuf_high_water);
7323 } else {
7324 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7325 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7326 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7327 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7328 tw32(BUFMGR_MB_HIGH_WATER,
7329 tp->bufmgr_config.mbuf_high_water_jumbo);
7330 }
7331 tw32(BUFMGR_DMA_LOW_WATER,
7332 tp->bufmgr_config.dma_low_water);
7333 tw32(BUFMGR_DMA_HIGH_WATER,
7334 tp->bufmgr_config.dma_high_water);
7335
7336 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7337 for (i = 0; i < 2000; i++) {
7338 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7339 break;
7340 udelay(10);
7341 }
7342 if (i >= 2000) {
7343 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7344 tp->dev->name);
7345 return -ENODEV;
7346 }
7347
7348 /* Setup replenish threshold. */
f92905de
MC		 7349 val = tp->rx_pending / 8;
7350 if (val == 0)
7351 val = 1;
7352 else if (val > tp->rx_std_max_post)
7353 val = tp->rx_std_max_post;
b5d3772c
MC		 7354 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7355 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7356 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7357
7358 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7359 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7360 }
f92905de
MC		 7361
7362 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7363
7364 /* Initialize TG3_BDINFO's at:
7365 * RCVDBDI_STD_BD: standard eth size rx ring
7366 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7367 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7368 *
7369 * like so:
7370 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7371 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7372 * ring attribute flags
7373 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7374 *
7375 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7376 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7377 *
7378 * The size of each ring is fixed in the firmware, but the location is
7379 * configurable.
7380 */
7381 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7382 ((u64) tp->rx_std_mapping >> 32));
7383 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7384 ((u64) tp->rx_std_mapping & 0xffffffff));
7385 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7386 NIC_SRAM_RX_BUFFER_DESC);
7387
7388 /* Don't even try to program the JUMBO/MINI buffer descriptor
7389 * configs on 5705.
7390 */
7391 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7392 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7393 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7394 } else {
7395 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7396 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7397
7398 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7399 BDINFO_FLAGS_DISABLED);
7400
7401 /* Setup replenish threshold. */
7402 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7403
0f893dc6 7404 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 7405 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7406 ((u64) tp->rx_jumbo_mapping >> 32));
7407 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7408 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7409 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7410 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7411 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7412 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7413 } else {
7414 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7415 BDINFO_FLAGS_DISABLED);
7416 }
7417
7418 }
7419
7420 /* There is only one send ring on 5705/5750, no need to explicitly
7421 * disable the others.
7422 */
7423 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7424 /* Clear out send RCB ring in SRAM. */
7425 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7426 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7427 BDINFO_FLAGS_DISABLED);
7428 }
7429
7430 tp->tx_prod = 0;
7431 tp->tx_cons = 0;
7432 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7433 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7434
7435 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7436 tp->tx_desc_mapping,
7437 (TG3_TX_RING_SIZE <<
7438 BDINFO_FLAGS_MAXLEN_SHIFT),
7439 NIC_SRAM_TX_BUFFER_DESC);
7440
7441 /* There is only one receive return ring on 5705/5750, no need
7442 * to explicitly disable the others.
7443 */
7444 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7445 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7446 i += TG3_BDINFO_SIZE) {
7447 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7448 BDINFO_FLAGS_DISABLED);
7449 }
7450 }
7451
7452 tp->rx_rcb_ptr = 0;
7453 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7454
7455 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7456 tp->rx_rcb_mapping,
7457 (TG3_RX_RCB_RING_SIZE(tp) <<
7458 BDINFO_FLAGS_MAXLEN_SHIFT),
7459 0);
7460
7461 tp->rx_std_ptr = tp->rx_pending;
7462 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7463 tp->rx_std_ptr);
7464
0f893dc6 7465 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 7466 tp->rx_jumbo_pending : 0;
7467 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7468 tp->rx_jumbo_ptr);
7469
7470 /* Initialize MAC address and backoff seed. */
986e0aeb 7471 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7472
7473 /* MTU + ethernet header + FCS + optional VLAN tag */
7474 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7475
7476 /* The slot time is changed by tg3_setup_phy if we
7477 * run at gigabit with half duplex.
7478 */
7479 tw32(MAC_TX_LENGTHS,
7480 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7481 (6 << TX_LENGTHS_IPG_SHIFT) |
7482 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7483
7484 /* Receive rules. */
7485 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7486 tw32(RCVLPC_CONFIG, 0x0181);
7487
7488 /* Calculate RDMAC_MODE setting early, we need it to determine
7489 * the RCVLPC_STATE_ENABLE mask.
7490 */
7491 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7492 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7493 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7494 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7495 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7496
57e6983c 7497 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7499 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7500 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7501 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7502 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7503
85e94ced
MC		 7504 /* If statement applies to 5705 and 5750 PCI devices only */
7505 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7506 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7507 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7508 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7510 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7511 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7512 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7513 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7514 }
7515 }
7516
85e94ced
MC		 7517 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7518 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7519
1da177e4
LT		 7520 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7521 rdmac_mode |= (1 << 27);
1da177e4
LT		 7522
7523 /* Receive/send statistics. */
1661394e
MC		 7524 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7525 val = tr32(RCVLPC_STATS_ENABLE);
7526 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7527 tw32(RCVLPC_STATS_ENABLE, val);
7528 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7529 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7530 val = tr32(RCVLPC_STATS_ENABLE);
7531 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7532 tw32(RCVLPC_STATS_ENABLE, val);
7533 } else {
7534 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7535 }
7536 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7537 tw32(SNDDATAI_STATSENAB, 0xffffff);
7538 tw32(SNDDATAI_STATSCTRL,
7539 (SNDDATAI_SCTRL_ENABLE |
7540 SNDDATAI_SCTRL_FASTUPD));
7541
7542 /* Setup host coalescing engine. */
7543 tw32(HOSTCC_MODE, 0);
7544 for (i = 0; i < 2000; i++) {
7545 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7546 break;
7547 udelay(10);
7548 }
7549
d244c892 7550 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7551
7552 /* set status block DMA address */
7553 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7554 ((u64) tp->status_mapping >> 32));
7555 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7556 ((u64) tp->status_mapping & 0xffffffff));
7557
7558 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7559 /* Status/statistics block address. See tg3_timer,
7560 * the tg3_periodic_fetch_stats call there, and
7561 * tg3_get_stats to see how this works for 5705/5750 chips.
7562 */
1da177e4
LT		 7563 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7564 ((u64) tp->stats_mapping >> 32));
7565 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7566 ((u64) tp->stats_mapping & 0xffffffff));
7567 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7568 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7569 }
7570
7571 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7572
7573 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7574 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7575 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7576 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7577
7578 /* Clear statistics/status block in chip, and status block in ram. */
7579 for (i = NIC_SRAM_STATS_BLK;
7580 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7581 i += sizeof(u32)) {
7582 tg3_write_mem(tp, i, 0);
7583 udelay(40);
7584 }
7585 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7586
c94e3941
MC		 7587 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7588 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7589 /* reset to prevent losing 1st rx packet intermittently */
7590 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7591 udelay(10);
7592 }
7593
3bda1258
MC		 7594 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7595 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7596 else
7597 tp->mac_mode = 0;
7598 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7599 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7600 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7601 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7602 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7603 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7604 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7605 udelay(40);
7606
314fba34 7607 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7608 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7609 * register to preserve the GPIO settings for LOMs. The GPIOs,
7610 * whether used as inputs or outputs, are set by boot code after
7611 * reset.
7612 */
9d26e213 7613 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7614 u32 gpio_mask;
7615
9d26e213
MC		 7616 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7617 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7618 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7619
7620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7621 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7622 GRC_LCLCTRL_GPIO_OUTPUT3;
7623
af36e6b6
MC		 7624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7625 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7626
aaf84465 7627 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7628 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7629
7630 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7631 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7632 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7633 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7634 }
1da177e4
LT		 7635 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7636 udelay(100);
7637
09ee929c 7638 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 7639 tp->last_tag = 0;
1da177e4
LT		 7640
7641 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7642 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7643 udelay(40);
7644 }
7645
7646 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7647 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7648 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7649 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7650 WDMAC_MODE_LNGREAD_ENAB);
7651
85e94ced
MC		 7652 /* If statement applies to 5705 and 5750 PCI devices only */
7653 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7654 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7656 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7657 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7658 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7659 /* nothing */
7660 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7661 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7662 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7663 val |= WDMAC_MODE_RX_ACCEL;
7664 }
7665 }
7666
d9ab5ad1 7667 /* Enable host coalescing bug fix */
321d32a0 7668 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7669 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7670
1da177e4
LT		 7671 tw32_f(WDMAC_MODE, val);
7672 udelay(40);
7673
9974a356
MC		 7674 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7675 u16 pcix_cmd;
7676
7677 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7678 &pcix_cmd);
1da177e4 7679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7680 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7681 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7682 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7683 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7684 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7685 }
9974a356
MC		 7686 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7687 pcix_cmd);
1da177e4
LT		 7688 }
7689
7690 tw32_f(RDMAC_MODE, rdmac_mode);
7691 udelay(40);
7692
7693 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7694 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7695 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7696
7697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7698 tw32(SNDDATAC_MODE,
7699 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7700 else
7701 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7702
1da177e4
LT		 7703 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7704 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7705 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7706 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7707 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7708 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7709 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7710 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7711
7712 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7713 err = tg3_load_5701_a0_firmware_fix(tp);
7714 if (err)
7715 return err;
7716 }
7717
1da177e4
LT		 7718 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7719 err = tg3_load_tso_firmware(tp);
7720 if (err)
7721 return err;
7722 }
1da177e4
LT		 7723
7724 tp->tx_mode = TX_MODE_ENABLE;
7725 tw32_f(MAC_TX_MODE, tp->tx_mode);
7726 udelay(100);
7727
7728 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7729 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7730 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7731
1da177e4
LT		 7732 tw32_f(MAC_RX_MODE, tp->rx_mode);
7733 udelay(10);
7734
1da177e4
LT		 7735 tw32(MAC_LED_CTRL, tp->led_ctrl);
7736
7737 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7738 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7739 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7740 udelay(10);
7741 }
7742 tw32_f(MAC_RX_MODE, tp->rx_mode);
7743 udelay(10);
7744
7745 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7746 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7747 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7748 /* Set drive transmission level to 1.2V */
7749 /* only if the signal pre-emphasis bit is not set */
7750 val = tr32(MAC_SERDES_CFG);
7751 val &= 0xfffff000;
7752 val |= 0x880;
7753 tw32(MAC_SERDES_CFG, val);
7754 }
7755 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7756 tw32(MAC_SERDES_CFG, 0x616000);
7757 }
7758
7759 /* Prevent chip from dropping frames when flow control
7760 * is enabled.
7761 */
7762 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7763
7764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7765 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7766 /* Use hardware link auto-negotiation */
7767 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7768 }
7769
d4d2c558
MC		 7770 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7771 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7772 u32 tmp;
7773
7774 tmp = tr32(SERDES_RX_CTRL);
7775 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7776 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7777 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7778 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7779 }
7780
dd477003
MC		 7781 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7782 if (tp->link_config.phy_is_low_power) {
7783 tp->link_config.phy_is_low_power = 0;
7784 tp->link_config.speed = tp->link_config.orig_speed;
7785 tp->link_config.duplex = tp->link_config.orig_duplex;
7786 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7787 }
1da177e4 7788
dd477003
MC		 7789 err = tg3_setup_phy(tp, 0);
7790 if (err)
7791 return err;
1da177e4 7792
dd477003
MC		 7793 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7794 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7795 u32 tmp;
7796
7797 /* Clear CRC stats. */
7798 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7799 tg3_writephy(tp, MII_TG3_TEST1,
7800 tmp | MII_TG3_TEST1_CRC_EN);
7801 tg3_readphy(tp, 0x14, &tmp);
7802 }
1da177e4
LT		 7803 }
7804 }
7805
7806 __tg3_set_rx_mode(tp->dev);
7807
7808 /* Initialize receive rules. */
7809 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7810 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7811 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7812 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7813
4cf78e4f 7814 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7815 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7816 limit = 8;
7817 else
7818 limit = 16;
7819 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7820 limit -= 4;
7821 switch (limit) {
7822 case 16:
7823 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7824 case 15:
7825 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7826 case 14:
7827 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7828 case 13:
7829 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7830 case 12:
7831 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7832 case 11:
7833 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7834 case 10:
7835 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7836 case 9:
7837 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7838 case 8:
7839 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7840 case 7:
7841 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7842 case 6:
7843 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7844 case 5:
7845 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7846 case 4:
7847 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7848 case 3:
7849 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7850 case 2:
7851 case 1:
7852
7853 default:
7854 break;
855e1111 7855 }
1da177e4 7856
9ce768ea
MC		 7857 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7858 /* Write our heartbeat update interval to APE. */
7859 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7860 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7861
1da177e4
LT		 7862 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7863
1da177e4
LT		 7864 return 0;
7865}
7866
7867/* Called at device open time to get the chip ready for
7868 * packet processing. Invoked with tp->lock held.
7869 */
8e7a22e3 7870static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7871{
1da177e4
LT		 7872 tg3_switch_clocks(tp);
7873
7874 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7875
2f751b67 7876 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7877}
7878
7879#define TG3_STAT_ADD32(PSTAT, REG) \
7880do { u32 __val = tr32(REG); \
7881 (PSTAT)->low += __val; \
7882 if ((PSTAT)->low < __val) \
7883 (PSTAT)->high += 1; \
7884} while (0)
7885
7886static void tg3_periodic_fetch_stats(struct tg3 *tp)
7887{
7888 struct tg3_hw_stats *sp = tp->hw_stats;
7889
7890 if (!netif_carrier_ok(tp->dev))
7891 return;
7892
7893 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7894 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7895 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7896 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7897 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7898 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7899 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7900 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7901 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7902 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7903 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7904 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7905 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7906
7907 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7908 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7909 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7910 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7911 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7912 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7913 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7914 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7915 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7916 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7917 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7918 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7919 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7920 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7921
7922 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7923 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7924 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7925}
7926
7927static void tg3_timer(unsigned long __opaque)
7928{
7929 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7930
f475f163
MC		 7931 if (tp->irq_sync)
7932 goto restart_timer;
7933
f47c11ee 7934 spin_lock(&tp->lock);
1da177e4 7935
fac9b83e
DM		 7936 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7937 /* All of this garbage is because when using non-tagged
7938 * IRQ status the mailbox/status_block protocol the chip
7939 * uses with the cpu is race prone.
7940 */
7941 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7942 tw32(GRC_LOCAL_CTRL,
7943 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7944 } else {
7945 tw32(HOSTCC_MODE, tp->coalesce_mode |
7946 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7947 }
1da177e4 7948
fac9b83e
DM		 7949 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7950 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7951 spin_unlock(&tp->lock);
fac9b83e
DM		 7952 schedule_work(&tp->reset_task);
7953 return;
7954 }
1da177e4
LT		 7955 }
7956
1da177e4
LT		 7957 /* This part only runs once per second. */
7958 if (!--tp->timer_counter) {
fac9b83e
DM		 7959 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7960 tg3_periodic_fetch_stats(tp);
7961
1da177e4
LT		 7962 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7963 u32 mac_stat;
7964 int phy_event;
7965
7966 mac_stat = tr32(MAC_STATUS);
7967
7968 phy_event = 0;
7969 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7970 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7971 phy_event = 1;
7972 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7973 phy_event = 1;
7974
7975 if (phy_event)
7976 tg3_setup_phy(tp, 0);
7977 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7978 u32 mac_stat = tr32(MAC_STATUS);
7979 int need_setup = 0;
7980
7981 if (netif_carrier_ok(tp->dev) &&
7982 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7983 need_setup = 1;
7984 }
7985 if (! netif_carrier_ok(tp->dev) &&
7986 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7987 MAC_STATUS_SIGNAL_DET))) {
7988 need_setup = 1;
7989 }
7990 if (need_setup) {
3d3ebe74
MC		 7991 if (!tp->serdes_counter) {
7992 tw32_f(MAC_MODE,
7993 (tp->mac_mode &
7994 ~MAC_MODE_PORT_MODE_MASK));
7995 udelay(40);
7996 tw32_f(MAC_MODE, tp->mac_mode);
7997 udelay(40);
7998 }
1da177e4
LT		 7999 tg3_setup_phy(tp, 0);
8000 }
747e8f8b
MC		 8001 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8002 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8003
8004 tp->timer_counter = tp->timer_multiplier;
8005 }
8006
130b8e4d
MC		 8007 /* Heartbeat is only sent once every 2 seconds.
8008 *
8009 * The heartbeat is to tell the ASF firmware that the host
8010 * driver is still alive. In the event that the OS crashes,
8011 * ASF needs to reset the hardware to free up the FIFO space
8012 * that may be filled with rx packets destined for the host.
8013 * If the FIFO is full, ASF will no longer function properly.
8014 *
8015 * Unintended resets have been reported on real time kernels
8016 * where the timer doesn't run on time. Netpoll will also have
8017 * same problem.
8018 *
8019 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8020 * to check the ring condition when the heartbeat is expiring
8021 * before doing the reset. This will prevent most unintended
8022 * resets.
8023 */
1da177e4 8024 if (!--tp->asf_counter) {
bc7959b2
MC		 8025 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8026 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8027 tg3_wait_for_event_ack(tp);
8028
bbadf503 8029 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8030 FWCMD_NICDRV_ALIVE3);
bbadf503 8031 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8032 /* 5 seconds timeout */
bbadf503 8033 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8034
8035 tg3_generate_fw_event(tp);
1da177e4
LT		 8036 }
8037 tp->asf_counter = tp->asf_multiplier;
8038 }
8039
f47c11ee 8040 spin_unlock(&tp->lock);
1da177e4 8041
f475f163 8042restart_timer:
1da177e4
LT		 8043 tp->timer.expires = jiffies + tp->timer_offset;
8044 add_timer(&tp->timer);
8045}
8046
81789ef5 8047static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 8048{
7d12e780 8049 irq_handler_t fn;
fcfa0a32
MC		 8050 unsigned long flags;
8051 struct net_device *dev = tp->dev;
8052
8053 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8054 fn = tg3_msi;
8055 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8056 fn = tg3_msi_1shot;
1fb9df5d 8057 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8058 } else {
8059 fn = tg3_interrupt;
8060 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8061 fn = tg3_interrupt_tagged;
1fb9df5d 8062 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8063 }
8064 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
8065}
8066
7938109f
MC		 8067static int tg3_test_interrupt(struct tg3 *tp)
8068{
8069 struct net_device *dev = tp->dev;
b16250e3 8070 int err, i, intr_ok = 0;
7938109f 8071
d4bc3927
MC		 8072 if (!netif_running(dev))
8073 return -ENODEV;
8074
7938109f
MC		 8075 tg3_disable_ints(tp);
8076
8077 free_irq(tp->pdev->irq, dev);
8078
8079 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 8080 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 8081 if (err)
8082 return err;
8083
38f3843e 8084 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8085 tg3_enable_ints(tp);
8086
8087 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8088 HOSTCC_MODE_NOW);
8089
8090 for (i = 0; i < 5; i++) {
b16250e3
MC		 8091 u32 int_mbox, misc_host_ctrl;
8092
09ee929c
MC		 8093 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
8094 TG3_64BIT_REG_LOW);
b16250e3
MC		 8095 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8096
8097 if ((int_mbox != 0) ||
8098 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8099 intr_ok = 1;
7938109f 8100 break;
b16250e3
MC		 8101 }
8102
7938109f
MC		 8103 msleep(10);
8104 }
8105
8106 tg3_disable_ints(tp);
8107
8108 free_irq(tp->pdev->irq, dev);
6aa20a22 8109
fcfa0a32 8110 err = tg3_request_irq(tp);
7938109f
MC		 8111
8112 if (err)
8113 return err;
8114
b16250e3 8115 if (intr_ok)
7938109f
MC		 8116 return 0;
8117
8118 return -EIO;
8119}
8120
8121/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8122 * successfully restored
8123 */
8124static int tg3_test_msi(struct tg3 *tp)
8125{
8126 struct net_device *dev = tp->dev;
8127 int err;
8128 u16 pci_cmd;
8129
8130 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8131 return 0;
8132
8133 /* Turn off SERR reporting in case MSI terminates with Master
8134 * Abort.
8135 */
8136 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8137 pci_write_config_word(tp->pdev, PCI_COMMAND,
8138 pci_cmd & ~PCI_COMMAND_SERR);
8139
8140 err = tg3_test_interrupt(tp);
8141
8142 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8143
8144 if (!err)
8145 return 0;
8146
8147 /* other failures */
8148 if (err != -EIO)
8149 return err;
8150
8151 /* MSI test failed, go back to INTx mode */
8152 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8153 "switching to INTx mode. Please report this failure to "
8154 "the PCI maintainer and include system chipset information.\n",
8155 tp->dev->name);
8156
8157 free_irq(tp->pdev->irq, dev);
8158 pci_disable_msi(tp->pdev);
8159
8160 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8161
fcfa0a32 8162 err = tg3_request_irq(tp);
7938109f
MC		 8163 if (err)
8164 return err;
8165
8166 /* Need to reset the chip because the MSI cycle may have terminated
8167 * with Master Abort.
8168 */
f47c11ee 8169 tg3_full_lock(tp, 1);
7938109f 8170
944d980e 8171 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8172 err = tg3_init_hw(tp, 1);
7938109f 8173
f47c11ee 8174 tg3_full_unlock(tp);
7938109f
MC		 8175
8176 if (err)
8177 free_irq(tp->pdev->irq, dev);
8178
8179 return err;
8180}
8181
1da177e4
LT		 8182static int tg3_open(struct net_device *dev)
8183{
8184 struct tg3 *tp = netdev_priv(dev);
8185 int err;
8186
c49a1561
MC		 8187 netif_carrier_off(tp->dev);
8188
bc1c7567 8189 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8190 if (err)
bc1c7567 8191 return err;
2f751b67
MC		 8192
8193 tg3_full_lock(tp, 0);
bc1c7567 8194
1da177e4
LT		 8195 tg3_disable_ints(tp);
8196 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8197
f47c11ee 8198 tg3_full_unlock(tp);
1da177e4
LT		 8199
8200 /* The placement of this call is tied
8201 * to the setup and use of Host TX descriptors.
8202 */
8203 err = tg3_alloc_consistent(tp);
8204 if (err)
8205 return err;
8206
7544b097 8207 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 8208 /* All MSI supporting chips should support tagged
8209 * status. Assert that this is the case.
8210 */
8211 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8212 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8213 "Not using MSI.\n", tp->dev->name);
8214 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 8215 u32 msi_mode;
8216
8217 msi_mode = tr32(MSGINT_MODE);
8218 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8219 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8220 }
8221 }
fcfa0a32 8222 err = tg3_request_irq(tp);
1da177e4
LT		 8223
8224 if (err) {
88b06bc2
MC		 8225 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8226 pci_disable_msi(tp->pdev);
8227 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8228 }
1da177e4
LT		 8229 tg3_free_consistent(tp);
8230 return err;
8231 }
8232
bea3348e
SH		 8233 napi_enable(&tp->napi);
8234
f47c11ee 8235 tg3_full_lock(tp, 0);
1da177e4 8236
8e7a22e3 8237 err = tg3_init_hw(tp, 1);
1da177e4 8238 if (err) {
944d980e 8239 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8240 tg3_free_rings(tp);
8241 } else {
fac9b83e
DM		 8242 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8243 tp->timer_offset = HZ;
8244 else
8245 tp->timer_offset = HZ / 10;
8246
8247 BUG_ON(tp->timer_offset > HZ);
8248 tp->timer_counter = tp->timer_multiplier =
8249 (HZ / tp->timer_offset);
8250 tp->asf_counter = tp->asf_multiplier =
28fbef78 8251 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8252
8253 init_timer(&tp->timer);
8254 tp->timer.expires = jiffies + tp->timer_offset;
8255 tp->timer.data = (unsigned long) tp;
8256 tp->timer.function = tg3_timer;
1da177e4
LT		 8257 }
8258
f47c11ee 8259 tg3_full_unlock(tp);
1da177e4
LT		 8260
8261 if (err) {
bea3348e 8262 napi_disable(&tp->napi);
88b06bc2
MC		 8263 free_irq(tp->pdev->irq, dev);
8264 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8265 pci_disable_msi(tp->pdev);
8266 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8267 }
1da177e4
LT		 8268 tg3_free_consistent(tp);
8269 return err;
8270 }
8271
7938109f
MC		 8272 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8273 err = tg3_test_msi(tp);
fac9b83e 8274
7938109f 8275 if (err) {
f47c11ee 8276 tg3_full_lock(tp, 0);
7938109f
MC		 8277
8278 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8279 pci_disable_msi(tp->pdev);
8280 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8281 }
944d980e 8282 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 8283 tg3_free_rings(tp);
8284 tg3_free_consistent(tp);
8285
f47c11ee 8286 tg3_full_unlock(tp);
7938109f 8287
bea3348e
SH		 8288 napi_disable(&tp->napi);
8289
7938109f
MC		 8290 return err;
8291 }
fcfa0a32
MC		 8292
8293 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8294 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 8295 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8296
b5d3772c
MC		 8297 tw32(PCIE_TRANSACTION_CFG,
8298 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 8299 }
8300 }
7938109f
MC		 8301 }
8302
b02fd9e3
MC		 8303 tg3_phy_start(tp);
8304
f47c11ee 8305 tg3_full_lock(tp, 0);
1da177e4 8306
7938109f
MC		 8307 add_timer(&tp->timer);
8308 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8309 tg3_enable_ints(tp);
8310
f47c11ee 8311 tg3_full_unlock(tp);
1da177e4
LT		 8312
8313 netif_start_queue(dev);
8314
8315 return 0;
8316}
8317
8318#if 0
8319/*static*/ void tg3_dump_state(struct tg3 *tp)
8320{
8321 u32 val32, val32_2, val32_3, val32_4, val32_5;
8322 u16 val16;
8323 int i;
8324
8325 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8326 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8327 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8328 val16, val32);
8329
8330 /* MAC block */
8331 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8332 tr32(MAC_MODE), tr32(MAC_STATUS));
8333 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8334 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8335 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8336 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8337 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8338 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8339
8340 /* Send data initiator control block */
8341 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8342 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8343 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8344 tr32(SNDDATAI_STATSCTRL));
8345
8346 /* Send data completion control block */
8347 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8348
8349 /* Send BD ring selector block */
8350 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8351 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8352
8353 /* Send BD initiator control block */
8354 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8355 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8356
8357 /* Send BD completion control block */
8358 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8359
8360 /* Receive list placement control block */
8361 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8362 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8363 printk(" RCVLPC_STATSCTRL[%08x]\n",
8364 tr32(RCVLPC_STATSCTRL));
8365
8366 /* Receive data and receive BD initiator control block */
8367 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8368 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8369
8370 /* Receive data completion control block */
8371 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8372 tr32(RCVDCC_MODE));
8373
8374 /* Receive BD initiator control block */
8375 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8376 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8377
8378 /* Receive BD completion control block */
8379 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8380 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8381
8382 /* Receive list selector control block */
8383 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8384 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8385
8386 /* Mbuf cluster free block */
8387 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8388 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8389
8390 /* Host coalescing control block */
8391 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8392 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8393 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8394 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8395 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8396 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8397 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8398 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8399 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8400 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8401 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8402 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8403
8404 /* Memory arbiter control block */
8405 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8406 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8407
8408 /* Buffer manager control block */
8409 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8410 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8411 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8412 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8413 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8414 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8415 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8416 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8417
8418 /* Read DMA control block */
8419 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8420 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8421
8422 /* Write DMA control block */
8423 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8424 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8425
8426 /* DMA completion block */
8427 printk("DEBUG: DMAC_MODE[%08x]\n",
8428 tr32(DMAC_MODE));
8429
8430 /* GRC block */
8431 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8432 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8433 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8434 tr32(GRC_LOCAL_CTRL));
8435
8436 /* TG3_BDINFOs */
8437 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8438 tr32(RCVDBDI_JUMBO_BD + 0x0),
8439 tr32(RCVDBDI_JUMBO_BD + 0x4),
8440 tr32(RCVDBDI_JUMBO_BD + 0x8),
8441 tr32(RCVDBDI_JUMBO_BD + 0xc));
8442 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8443 tr32(RCVDBDI_STD_BD + 0x0),
8444 tr32(RCVDBDI_STD_BD + 0x4),
8445 tr32(RCVDBDI_STD_BD + 0x8),
8446 tr32(RCVDBDI_STD_BD + 0xc));
8447 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8448 tr32(RCVDBDI_MINI_BD + 0x0),
8449 tr32(RCVDBDI_MINI_BD + 0x4),
8450 tr32(RCVDBDI_MINI_BD + 0x8),
8451 tr32(RCVDBDI_MINI_BD + 0xc));
8452
8453 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8454 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8455 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8456 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8457 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8458 val32, val32_2, val32_3, val32_4);
8459
8460 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8461 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8462 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8463 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8464 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8465 val32, val32_2, val32_3, val32_4);
8466
8467 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8468 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8469 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8470 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8471 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8472 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8473 val32, val32_2, val32_3, val32_4, val32_5);
8474
8475 /* SW status block */
8476 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8477 tp->hw_status->status,
8478 tp->hw_status->status_tag,
8479 tp->hw_status->rx_jumbo_consumer,
8480 tp->hw_status->rx_consumer,
8481 tp->hw_status->rx_mini_consumer,
8482 tp->hw_status->idx[0].rx_producer,
8483 tp->hw_status->idx[0].tx_consumer);
8484
8485 /* SW statistics block */
8486 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8487 ((u32 *)tp->hw_stats)[0],
8488 ((u32 *)tp->hw_stats)[1],
8489 ((u32 *)tp->hw_stats)[2],
8490 ((u32 *)tp->hw_stats)[3]);
8491
8492 /* Mailboxes */
8493 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8494 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8495 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8496 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8497 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8498
8499 /* NIC side send descriptors. */
8500 for (i = 0; i < 6; i++) {
8501 unsigned long txd;
8502
8503 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8504 + (i * sizeof(struct tg3_tx_buffer_desc));
8505 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8506 i,
8507 readl(txd + 0x0), readl(txd + 0x4),
8508 readl(txd + 0x8), readl(txd + 0xc));
8509 }
8510
8511 /* NIC side RX descriptors. */
8512 for (i = 0; i < 6; i++) {
8513 unsigned long rxd;
8514
8515 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8516 + (i * sizeof(struct tg3_rx_buffer_desc));
8517 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8518 i,
8519 readl(rxd + 0x0), readl(rxd + 0x4),
8520 readl(rxd + 0x8), readl(rxd + 0xc));
8521 rxd += (4 * sizeof(u32));
8522 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8523 i,
8524 readl(rxd + 0x0), readl(rxd + 0x4),
8525 readl(rxd + 0x8), readl(rxd + 0xc));
8526 }
8527
8528 for (i = 0; i < 6; i++) {
8529 unsigned long rxd;
8530
8531 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8532 + (i * sizeof(struct tg3_rx_buffer_desc));
8533 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8534 i,
8535 readl(rxd + 0x0), readl(rxd + 0x4),
8536 readl(rxd + 0x8), readl(rxd + 0xc));
8537 rxd += (4 * sizeof(u32));
8538 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8539 i,
8540 readl(rxd + 0x0), readl(rxd + 0x4),
8541 readl(rxd + 0x8), readl(rxd + 0xc));
8542 }
8543}
8544#endif
8545
8546static struct net_device_stats *tg3_get_stats(struct net_device *);
8547static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8548
8549static int tg3_close(struct net_device *dev)
8550{
8551 struct tg3 *tp = netdev_priv(dev);
8552
bea3348e 8553 napi_disable(&tp->napi);
28e53bdd 8554 cancel_work_sync(&tp->reset_task);
7faa006f 8555
1da177e4
LT		 8556 netif_stop_queue(dev);
8557
8558 del_timer_sync(&tp->timer);
8559
f47c11ee 8560 tg3_full_lock(tp, 1);
1da177e4
LT		 8561#if 0
8562 tg3_dump_state(tp);
8563#endif
8564
8565 tg3_disable_ints(tp);
8566
944d980e 8567 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8568 tg3_free_rings(tp);
5cf64b8a 8569 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8570
f47c11ee 8571 tg3_full_unlock(tp);
1da177e4 8572
88b06bc2
MC		 8573 free_irq(tp->pdev->irq, dev);
8574 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8575 pci_disable_msi(tp->pdev);
8576 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8577 }
1da177e4
LT		 8578
8579 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8580 sizeof(tp->net_stats_prev));
8581 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8582 sizeof(tp->estats_prev));
8583
8584 tg3_free_consistent(tp);
8585
bc1c7567
MC		 8586 tg3_set_power_state(tp, PCI_D3hot);
8587
8588 netif_carrier_off(tp->dev);
8589
1da177e4
LT		 8590 return 0;
8591}
8592
8593static inline unsigned long get_stat64(tg3_stat64_t *val)
8594{
8595 unsigned long ret;
8596
8597#if (BITS_PER_LONG == 32)
8598 ret = val->low;
8599#else
8600 ret = ((u64)val->high << 32) | ((u64)val->low);
8601#endif
8602 return ret;
8603}
8604
816f8b86
SB		 8605static inline u64 get_estat64(tg3_stat64_t *val)
8606{
8607 return ((u64)val->high << 32) | ((u64)val->low);
8608}
8609
1da177e4
LT		 8610static unsigned long calc_crc_errors(struct tg3 *tp)
8611{
8612 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8613
8614 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8615 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8617 u32 val;
8618
f47c11ee 8619 spin_lock_bh(&tp->lock);
569a5df8
MC		 8620 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8621 tg3_writephy(tp, MII_TG3_TEST1,
8622 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8623 tg3_readphy(tp, 0x14, &val);
8624 } else
8625 val = 0;
f47c11ee 8626 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8627
8628 tp->phy_crc_errors += val;
8629
8630 return tp->phy_crc_errors;
8631 }
8632
8633 return get_stat64(&hw_stats->rx_fcs_errors);
8634}
8635
8636#define ESTAT_ADD(member) \
8637 estats->member = old_estats->member + \
816f8b86 8638 get_estat64(&hw_stats->member)
1da177e4
LT		 8639
8640static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8641{
8642 struct tg3_ethtool_stats *estats = &tp->estats;
8643 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8644 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8645
8646 if (!hw_stats)
8647 return old_estats;
8648
8649 ESTAT_ADD(rx_octets);
8650 ESTAT_ADD(rx_fragments);
8651 ESTAT_ADD(rx_ucast_packets);
8652 ESTAT_ADD(rx_mcast_packets);
8653 ESTAT_ADD(rx_bcast_packets);
8654 ESTAT_ADD(rx_fcs_errors);
8655 ESTAT_ADD(rx_align_errors);
8656 ESTAT_ADD(rx_xon_pause_rcvd);
8657 ESTAT_ADD(rx_xoff_pause_rcvd);
8658 ESTAT_ADD(rx_mac_ctrl_rcvd);
8659 ESTAT_ADD(rx_xoff_entered);
8660 ESTAT_ADD(rx_frame_too_long_errors);
8661 ESTAT_ADD(rx_jabbers);
8662 ESTAT_ADD(rx_undersize_packets);
8663 ESTAT_ADD(rx_in_length_errors);
8664 ESTAT_ADD(rx_out_length_errors);
8665 ESTAT_ADD(rx_64_or_less_octet_packets);
8666 ESTAT_ADD(rx_65_to_127_octet_packets);
8667 ESTAT_ADD(rx_128_to_255_octet_packets);
8668 ESTAT_ADD(rx_256_to_511_octet_packets);
8669 ESTAT_ADD(rx_512_to_1023_octet_packets);
8670 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8671 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8672 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8673 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8674 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8675
8676 ESTAT_ADD(tx_octets);
8677 ESTAT_ADD(tx_collisions);
8678 ESTAT_ADD(tx_xon_sent);
8679 ESTAT_ADD(tx_xoff_sent);
8680 ESTAT_ADD(tx_flow_control);
8681 ESTAT_ADD(tx_mac_errors);
8682 ESTAT_ADD(tx_single_collisions);
8683 ESTAT_ADD(tx_mult_collisions);
8684 ESTAT_ADD(tx_deferred);
8685 ESTAT_ADD(tx_excessive_collisions);
8686 ESTAT_ADD(tx_late_collisions);
8687 ESTAT_ADD(tx_collide_2times);
8688 ESTAT_ADD(tx_collide_3times);
8689 ESTAT_ADD(tx_collide_4times);
8690 ESTAT_ADD(tx_collide_5times);
8691 ESTAT_ADD(tx_collide_6times);
8692 ESTAT_ADD(tx_collide_7times);
8693 ESTAT_ADD(tx_collide_8times);
8694 ESTAT_ADD(tx_collide_9times);
8695 ESTAT_ADD(tx_collide_10times);
8696 ESTAT_ADD(tx_collide_11times);
8697 ESTAT_ADD(tx_collide_12times);
8698 ESTAT_ADD(tx_collide_13times);
8699 ESTAT_ADD(tx_collide_14times);
8700 ESTAT_ADD(tx_collide_15times);
8701 ESTAT_ADD(tx_ucast_packets);
8702 ESTAT_ADD(tx_mcast_packets);
8703 ESTAT_ADD(tx_bcast_packets);
8704 ESTAT_ADD(tx_carrier_sense_errors);
8705 ESTAT_ADD(tx_discards);
8706 ESTAT_ADD(tx_errors);
8707
8708 ESTAT_ADD(dma_writeq_full);
8709 ESTAT_ADD(dma_write_prioq_full);
8710 ESTAT_ADD(rxbds_empty);
8711 ESTAT_ADD(rx_discards);
8712 ESTAT_ADD(rx_errors);
8713 ESTAT_ADD(rx_threshold_hit);
8714
8715 ESTAT_ADD(dma_readq_full);
8716 ESTAT_ADD(dma_read_prioq_full);
8717 ESTAT_ADD(tx_comp_queue_full);
8718
8719 ESTAT_ADD(ring_set_send_prod_index);
8720 ESTAT_ADD(ring_status_update);
8721 ESTAT_ADD(nic_irqs);
8722 ESTAT_ADD(nic_avoided_irqs);
8723 ESTAT_ADD(nic_tx_threshold_hit);
8724
8725 return estats;
8726}
8727
8728static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8729{
8730 struct tg3 *tp = netdev_priv(dev);
8731 struct net_device_stats *stats = &tp->net_stats;
8732 struct net_device_stats *old_stats = &tp->net_stats_prev;
8733 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8734
8735 if (!hw_stats)
8736 return old_stats;
8737
8738 stats->rx_packets = old_stats->rx_packets +
8739 get_stat64(&hw_stats->rx_ucast_packets) +
8740 get_stat64(&hw_stats->rx_mcast_packets) +
8741 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8742
1da177e4
LT		 8743 stats->tx_packets = old_stats->tx_packets +
8744 get_stat64(&hw_stats->tx_ucast_packets) +
8745 get_stat64(&hw_stats->tx_mcast_packets) +
8746 get_stat64(&hw_stats->tx_bcast_packets);
8747
8748 stats->rx_bytes = old_stats->rx_bytes +
8749 get_stat64(&hw_stats->rx_octets);
8750 stats->tx_bytes = old_stats->tx_bytes +
8751 get_stat64(&hw_stats->tx_octets);
8752
8753 stats->rx_errors = old_stats->rx_errors +
4f63b877 8754 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8755 stats->tx_errors = old_stats->tx_errors +
8756 get_stat64(&hw_stats->tx_errors) +
8757 get_stat64(&hw_stats->tx_mac_errors) +
8758 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8759 get_stat64(&hw_stats->tx_discards);
8760
8761 stats->multicast = old_stats->multicast +
8762 get_stat64(&hw_stats->rx_mcast_packets);
8763 stats->collisions = old_stats->collisions +
8764 get_stat64(&hw_stats->tx_collisions);
8765
8766 stats->rx_length_errors = old_stats->rx_length_errors +
8767 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8768 get_stat64(&hw_stats->rx_undersize_packets);
8769
8770 stats->rx_over_errors = old_stats->rx_over_errors +
8771 get_stat64(&hw_stats->rxbds_empty);
8772 stats->rx_frame_errors = old_stats->rx_frame_errors +
8773 get_stat64(&hw_stats->rx_align_errors);
8774 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8775 get_stat64(&hw_stats->tx_discards);
8776 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8777 get_stat64(&hw_stats->tx_carrier_sense_errors);
8778
8779 stats->rx_crc_errors = old_stats->rx_crc_errors +
8780 calc_crc_errors(tp);
8781
4f63b877
JL		 8782 stats->rx_missed_errors = old_stats->rx_missed_errors +
8783 get_stat64(&hw_stats->rx_discards);
8784
1da177e4
LT		 8785 return stats;
8786}
8787
8788static inline u32 calc_crc(unsigned char *buf, int len)
8789{
8790 u32 reg;
8791 u32 tmp;
8792 int j, k;
8793
8794 reg = 0xffffffff;
8795
8796 for (j = 0; j < len; j++) {
8797 reg ^= buf[j];
8798
8799 for (k = 0; k < 8; k++) {
8800 tmp = reg & 0x01;
8801
8802 reg >>= 1;
8803
8804 if (tmp) {
8805 reg ^= 0xedb88320;
8806 }
8807 }
8808 }
8809
8810 return ~reg;
8811}
8812
8813static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8814{
8815 /* accept or reject all multicast frames */
8816 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8817 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8818 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8819 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8820}
8821
8822static void __tg3_set_rx_mode(struct net_device *dev)
8823{
8824 struct tg3 *tp = netdev_priv(dev);
8825 u32 rx_mode;
8826
8827 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8828 RX_MODE_KEEP_VLAN_TAG);
8829
8830 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8831 * flag clear.
8832 */
8833#if TG3_VLAN_TAG_USED
8834 if (!tp->vlgrp &&
8835 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8836 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8837#else
8838 /* By definition, VLAN is disabled always in this
8839 * case.
8840 */
8841 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8842 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8843#endif
8844
8845 if (dev->flags & IFF_PROMISC) {
8846 /* Promiscuous mode. */
8847 rx_mode |= RX_MODE_PROMISC;
8848 } else if (dev->flags & IFF_ALLMULTI) {
8849 /* Accept all multicast. */
8850 tg3_set_multi (tp, 1);
8851 } else if (dev->mc_count < 1) {
8852 /* Reject all multicast. */
8853 tg3_set_multi (tp, 0);
8854 } else {
8855 /* Accept one or more multicast(s). */
8856 struct dev_mc_list *mclist;
8857 unsigned int i;
8858 u32 mc_filter[4] = { 0, };
8859 u32 regidx;
8860 u32 bit;
8861 u32 crc;
8862
8863 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8864 i++, mclist = mclist->next) {
8865
8866 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8867 bit = ~crc & 0x7f;
8868 regidx = (bit & 0x60) >> 5;
8869 bit &= 0x1f;
8870 mc_filter[regidx] |= (1 << bit);
8871 }
8872
8873 tw32(MAC_HASH_REG_0, mc_filter[0]);
8874 tw32(MAC_HASH_REG_1, mc_filter[1]);
8875 tw32(MAC_HASH_REG_2, mc_filter[2]);
8876 tw32(MAC_HASH_REG_3, mc_filter[3]);
8877 }
8878
8879 if (rx_mode != tp->rx_mode) {
8880 tp->rx_mode = rx_mode;
8881 tw32_f(MAC_RX_MODE, rx_mode);
8882 udelay(10);
8883 }
8884}
8885
8886static void tg3_set_rx_mode(struct net_device *dev)
8887{
8888 struct tg3 *tp = netdev_priv(dev);
8889
e75f7c90
MC		 8890 if (!netif_running(dev))
8891 return;
8892
f47c11ee 8893 tg3_full_lock(tp, 0);
1da177e4 8894 __tg3_set_rx_mode(dev);
f47c11ee 8895 tg3_full_unlock(tp);
1da177e4
LT		 8896}
8897
8898#define TG3_REGDUMP_LEN (32 * 1024)
8899
8900static int tg3_get_regs_len(struct net_device *dev)
8901{
8902 return TG3_REGDUMP_LEN;
8903}
8904
8905static void tg3_get_regs(struct net_device *dev,
8906 struct ethtool_regs *regs, void *_p)
8907{
8908 u32 *p = _p;
8909 struct tg3 *tp = netdev_priv(dev);
8910 u8 *orig_p = _p;
8911 int i;
8912
8913 regs->version = 0;
8914
8915 memset(p, 0, TG3_REGDUMP_LEN);
8916
bc1c7567
MC		 8917 if (tp->link_config.phy_is_low_power)
8918 return;
8919
f47c11ee 8920 tg3_full_lock(tp, 0);
1da177e4
LT		 8921
8922#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8923#define GET_REG32_LOOP(base,len) \
8924do { p = (u32 *)(orig_p + (base)); \
8925 for (i = 0; i < len; i += 4) \
8926 __GET_REG32((base) + i); \
8927} while (0)
8928#define GET_REG32_1(reg) \
8929do { p = (u32 *)(orig_p + (reg)); \
8930 __GET_REG32((reg)); \
8931} while (0)
8932
8933 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8934 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8935 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8936 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8937 GET_REG32_1(SNDDATAC_MODE);
8938 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8939 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8940 GET_REG32_1(SNDBDC_MODE);
8941 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8942 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8943 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8944 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8945 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8946 GET_REG32_1(RCVDCC_MODE);
8947 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8948 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8949 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8950 GET_REG32_1(MBFREE_MODE);
8951 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8952 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8953 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8954 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8955 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8956 GET_REG32_1(RX_CPU_MODE);
8957 GET_REG32_1(RX_CPU_STATE);
8958 GET_REG32_1(RX_CPU_PGMCTR);
8959 GET_REG32_1(RX_CPU_HWBKPT);
8960 GET_REG32_1(TX_CPU_MODE);
8961 GET_REG32_1(TX_CPU_STATE);
8962 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8963 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8964 GET_REG32_LOOP(FTQ_RESET, 0x120);
8965 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8966 GET_REG32_1(DMAC_MODE);
8967 GET_REG32_LOOP(GRC_MODE, 0x4c);
8968 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8969 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8970
8971#undef __GET_REG32
8972#undef GET_REG32_LOOP
8973#undef GET_REG32_1
8974
f47c11ee 8975 tg3_full_unlock(tp);
1da177e4
LT		 8976}
8977
8978static int tg3_get_eeprom_len(struct net_device *dev)
8979{
8980 struct tg3 *tp = netdev_priv(dev);
8981
8982 return tp->nvram_size;
8983}
8984
8985static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
b9fc7dc5 8986static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
1820180b 8987static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 8988
8989static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8990{
8991 struct tg3 *tp = netdev_priv(dev);
8992 int ret;
8993 u8 *pd;
b9fc7dc5
AV		 8994 u32 i, offset, len, b_offset, b_count;
8995 __le32 val;
1da177e4 8996
bc1c7567
MC		 8997 if (tp->link_config.phy_is_low_power)
8998 return -EAGAIN;
8999
1da177e4
LT		 9000 offset = eeprom->offset;
9001 len = eeprom->len;
9002 eeprom->len = 0;
9003
9004 eeprom->magic = TG3_EEPROM_MAGIC;
9005
9006 if (offset & 3) {
9007 /* adjustments to start on required 4 byte boundary */
9008 b_offset = offset & 3;
9009 b_count = 4 - b_offset;
9010 if (b_count > len) {
9011 /* i.e. offset=1 len=2 */
9012 b_count = len;
9013 }
b9fc7dc5 9014 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
1da177e4
LT		 9015 if (ret)
9016 return ret;
1da177e4
LT		 9017 memcpy(data, ((char*)&val) + b_offset, b_count);
9018 len -= b_count;
9019 offset += b_count;
9020 eeprom->len += b_count;
9021 }
9022
9023 /* read bytes upto the last 4 byte boundary */
9024 pd = &data[eeprom->len];
9025 for (i = 0; i < (len - (len & 3)); i += 4) {
b9fc7dc5 9026 ret = tg3_nvram_read_le(tp, offset + i, &val);
1da177e4
LT		 9027 if (ret) {
9028 eeprom->len += i;
9029 return ret;
9030 }
1da177e4
LT		 9031 memcpy(pd + i, &val, 4);
9032 }
9033 eeprom->len += i;
9034
9035 if (len & 3) {
9036 /* read last bytes not ending on 4 byte boundary */
9037 pd = &data[eeprom->len];
9038 b_count = len & 3;
9039 b_offset = offset + len - b_count;
b9fc7dc5 9040 ret = tg3_nvram_read_le(tp, b_offset, &val);
1da177e4
LT		 9041 if (ret)
9042 return ret;
b9fc7dc5 9043 memcpy(pd, &val, b_count);
1da177e4
LT		 9044 eeprom->len += b_count;
9045 }
9046 return 0;
9047}
9048
6aa20a22 9049static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9050
9051static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9052{
9053 struct tg3 *tp = netdev_priv(dev);
9054 int ret;
b9fc7dc5 9055 u32 offset, len, b_offset, odd_len;
1da177e4 9056 u8 *buf;
b9fc7dc5 9057 __le32 start, end;
1da177e4 9058
bc1c7567
MC		 9059 if (tp->link_config.phy_is_low_power)
9060 return -EAGAIN;
9061
1da177e4
LT		 9062 if (eeprom->magic != TG3_EEPROM_MAGIC)
9063 return -EINVAL;
9064
9065 offset = eeprom->offset;
9066 len = eeprom->len;
9067
9068 if ((b_offset = (offset & 3))) {
9069 /* adjustments to start on required 4 byte boundary */
b9fc7dc5 9070 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
1da177e4
LT		 9071 if (ret)
9072 return ret;
1da177e4
LT		 9073 len += b_offset;
9074 offset &= ~3;
1c8594b4
MC		 9075 if (len < 4)
9076 len = 4;
1da177e4
LT		 9077 }
9078
9079 odd_len = 0;
1c8594b4 9080 if (len & 3) {
1da177e4
LT		 9081 /* adjustments to end on required 4 byte boundary */
9082 odd_len = 1;
9083 len = (len + 3) & ~3;
b9fc7dc5 9084 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
1da177e4
LT		 9085 if (ret)
9086 return ret;
1da177e4
LT		 9087 }
9088
9089 buf = data;
9090 if (b_offset || odd_len) {
9091 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9092 if (!buf)
1da177e4
LT		 9093 return -ENOMEM;
9094 if (b_offset)
9095 memcpy(buf, &start, 4);
9096 if (odd_len)
9097 memcpy(buf+len-4, &end, 4);
9098 memcpy(buf + b_offset, data, eeprom->len);
9099 }
9100
9101 ret = tg3_nvram_write_block(tp, offset, len, buf);
9102
9103 if (buf != data)
9104 kfree(buf);
9105
9106 return ret;
9107}
9108
9109static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9110{
b02fd9e3
MC		 9111 struct tg3 *tp = netdev_priv(dev);
9112
9113 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9114 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9115 return -EAGAIN;
298cf9be 9116 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 9117 }
6aa20a22 9118
1da177e4
LT		 9119 cmd->supported = (SUPPORTED_Autoneg);
9120
9121 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9122 cmd->supported |= (SUPPORTED_1000baseT_Half |
9123 SUPPORTED_1000baseT_Full);
9124
ef348144 9125 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9126 cmd->supported |= (SUPPORTED_100baseT_Half |
9127 SUPPORTED_100baseT_Full |
9128 SUPPORTED_10baseT_Half |
9129 SUPPORTED_10baseT_Full |
3bebab59 9130 SUPPORTED_TP);
ef348144
KK		 9131 cmd->port = PORT_TP;
9132 } else {
1da177e4 9133 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9134 cmd->port = PORT_FIBRE;
9135 }
6aa20a22 9136
1da177e4
LT		 9137 cmd->advertising = tp->link_config.advertising;
9138 if (netif_running(dev)) {
9139 cmd->speed = tp->link_config.active_speed;
9140 cmd->duplex = tp->link_config.active_duplex;
9141 }
1da177e4
LT		 9142 cmd->phy_address = PHY_ADDR;
9143 cmd->transceiver = 0;
9144 cmd->autoneg = tp->link_config.autoneg;
9145 cmd->maxtxpkt = 0;
9146 cmd->maxrxpkt = 0;
9147 return 0;
9148}
6aa20a22 9149
1da177e4
LT		 9150static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9151{
9152 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9153
b02fd9e3
MC		 9154 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9155 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9156 return -EAGAIN;
298cf9be 9157 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 9158 }
9159
6aa20a22 9160 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 9161 /* These are the only valid advertisement bits allowed. */
9162 if (cmd->autoneg == AUTONEG_ENABLE &&
9163 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
9164 ADVERTISED_1000baseT_Full |
9165 ADVERTISED_Autoneg |
9166 ADVERTISED_FIBRE)))
9167 return -EINVAL;
37ff238d
MC		 9168 /* Fiber can only do SPEED_1000. */
9169 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9170 (cmd->speed != SPEED_1000))
9171 return -EINVAL;
9172 /* Copper cannot force SPEED_1000. */
9173 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9174 (cmd->speed == SPEED_1000))
9175 return -EINVAL;
9176 else if ((cmd->speed == SPEED_1000) &&
0ba11fb3 9177 (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
37ff238d 9178 return -EINVAL;
1da177e4 9179
f47c11ee 9180 tg3_full_lock(tp, 0);
1da177e4
LT		 9181
9182 tp->link_config.autoneg = cmd->autoneg;
9183 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9184 tp->link_config.advertising = (cmd->advertising |
9185 ADVERTISED_Autoneg);
1da177e4
LT		 9186 tp->link_config.speed = SPEED_INVALID;
9187 tp->link_config.duplex = DUPLEX_INVALID;
9188 } else {
9189 tp->link_config.advertising = 0;
9190 tp->link_config.speed = cmd->speed;
9191 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9192 }
6aa20a22 9193
24fcad6b
MC		 9194 tp->link_config.orig_speed = tp->link_config.speed;
9195 tp->link_config.orig_duplex = tp->link_config.duplex;
9196 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9197
1da177e4
LT		 9198 if (netif_running(dev))
9199 tg3_setup_phy(tp, 1);
9200
f47c11ee 9201 tg3_full_unlock(tp);
6aa20a22 9202
1da177e4
LT		 9203 return 0;
9204}
6aa20a22 9205
1da177e4
LT		 9206static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9207{
9208 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9209
1da177e4
LT		 9210 strcpy(info->driver, DRV_MODULE_NAME);
9211 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9212 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9213 strcpy(info->bus_info, pci_name(tp->pdev));
9214}
6aa20a22 9215
1da177e4
LT		 9216static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9217{
9218 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9219
12dac075
RW		 9220 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9221 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9222 wol->supported = WAKE_MAGIC;
9223 else
9224 wol->supported = 0;
1da177e4 9225 wol->wolopts = 0;
05ac4cb7
MC		 9226 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9227 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9228 wol->wolopts = WAKE_MAGIC;
9229 memset(&wol->sopass, 0, sizeof(wol->sopass));
9230}
6aa20a22 9231
1da177e4
LT		 9232static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9233{
9234 struct tg3 *tp = netdev_priv(dev);
12dac075 9235 struct device *dp = &tp->pdev->dev;
6aa20a22 9236
1da177e4
LT		 9237 if (wol->wolopts & ~WAKE_MAGIC)
9238 return -EINVAL;
9239 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9240 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9241 return -EINVAL;
6aa20a22 9242
f47c11ee 9243 spin_lock_bh(&tp->lock);
12dac075 9244 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9245 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9246 device_set_wakeup_enable(dp, true);
9247 } else {
1da177e4 9248 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9249 device_set_wakeup_enable(dp, false);
9250 }
f47c11ee 9251 spin_unlock_bh(&tp->lock);
6aa20a22 9252
1da177e4
LT		 9253 return 0;
9254}
6aa20a22 9255
1da177e4
LT		 9256static u32 tg3_get_msglevel(struct net_device *dev)
9257{
9258 struct tg3 *tp = netdev_priv(dev);
9259 return tp->msg_enable;
9260}
6aa20a22 9261
1da177e4
LT		 9262static void tg3_set_msglevel(struct net_device *dev, u32 value)
9263{
9264 struct tg3 *tp = netdev_priv(dev);
9265 tp->msg_enable = value;
9266}
6aa20a22 9267
1da177e4
LT		 9268static int tg3_set_tso(struct net_device *dev, u32 value)
9269{
9270 struct tg3 *tp = netdev_priv(dev);
9271
9272 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9273 if (value)
9274 return -EINVAL;
9275 return 0;
9276 }
b5d3772c
MC		 9277 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9278 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9936bcf6 9279 if (value) {
b0026624 9280 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9282 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9283 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 9284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9286 dev->features |= NETIF_F_TSO_ECN;
9287 } else
9288 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9289 }
1da177e4
LT		 9290 return ethtool_op_set_tso(dev, value);
9291}
6aa20a22 9292
1da177e4
LT		 9293static int tg3_nway_reset(struct net_device *dev)
9294{
9295 struct tg3 *tp = netdev_priv(dev);
1da177e4 9296 int r;
6aa20a22 9297
1da177e4
LT		 9298 if (!netif_running(dev))
9299 return -EAGAIN;
9300
c94e3941
MC		 9301 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9302 return -EINVAL;
9303
b02fd9e3
MC		 9304 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9305 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9306 return -EAGAIN;
298cf9be 9307 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9308 } else {
9309 u32 bmcr;
9310
9311 spin_lock_bh(&tp->lock);
9312 r = -EINVAL;
9313 tg3_readphy(tp, MII_BMCR, &bmcr);
9314 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9315 ((bmcr & BMCR_ANENABLE) ||
9316 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9317 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9318 BMCR_ANENABLE);
9319 r = 0;
9320 }
9321 spin_unlock_bh(&tp->lock);
1da177e4 9322 }
6aa20a22 9323
1da177e4
LT		 9324 return r;
9325}
6aa20a22 9326
1da177e4
LT		 9327static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9328{
9329 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9330
1da177e4
LT		 9331 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9332 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9333 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9334 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9335 else
9336 ering->rx_jumbo_max_pending = 0;
9337
9338 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9339
9340 ering->rx_pending = tp->rx_pending;
9341 ering->rx_mini_pending = 0;
4f81c32b
MC		 9342 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9343 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9344 else
9345 ering->rx_jumbo_pending = 0;
9346
1da177e4
LT		 9347 ering->tx_pending = tp->tx_pending;
9348}
6aa20a22 9349
1da177e4
LT		 9350static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9351{
9352 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9353 int irq_sync = 0, err = 0;
6aa20a22 9354
1da177e4
LT		 9355 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9356 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9357 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9358 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9359 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9360 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9361 return -EINVAL;
6aa20a22 9362
bbe832c0 9363 if (netif_running(dev)) {
b02fd9e3 9364 tg3_phy_stop(tp);
1da177e4 9365 tg3_netif_stop(tp);
bbe832c0
MC		 9366 irq_sync = 1;
9367 }
1da177e4 9368
bbe832c0 9369 tg3_full_lock(tp, irq_sync);
6aa20a22 9370
1da177e4
LT		 9371 tp->rx_pending = ering->rx_pending;
9372
9373 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9374 tp->rx_pending > 63)
9375 tp->rx_pending = 63;
9376 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9377 tp->tx_pending = ering->tx_pending;
9378
9379 if (netif_running(dev)) {
944d980e 9380 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9381 err = tg3_restart_hw(tp, 1);
9382 if (!err)
9383 tg3_netif_start(tp);
1da177e4
LT		 9384 }
9385
f47c11ee 9386 tg3_full_unlock(tp);
6aa20a22 9387
b02fd9e3
MC		 9388 if (irq_sync && !err)
9389 tg3_phy_start(tp);
9390
b9ec6c1b 9391 return err;
1da177e4 9392}
6aa20a22 9393
1da177e4
LT		 9394static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9395{
9396 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9397
1da177e4 9398 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9399
e18ce346 9400 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9401 epause->rx_pause = 1;
9402 else
9403 epause->rx_pause = 0;
9404
e18ce346 9405 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9406 epause->tx_pause = 1;
9407 else
9408 epause->tx_pause = 0;
1da177e4 9409}
6aa20a22 9410
1da177e4
LT		 9411static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9412{
9413 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9414 int err = 0;
6aa20a22 9415
b02fd9e3
MC		 9416 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9417 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9418 return -EAGAIN;
1da177e4 9419
b02fd9e3
MC		 9420 if (epause->autoneg) {
9421 u32 newadv;
9422 struct phy_device *phydev;
f47c11ee 9423
298cf9be 9424 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9425
b02fd9e3
MC		 9426 if (epause->rx_pause) {
9427 if (epause->tx_pause)
9428 newadv = ADVERTISED_Pause;
9429 else
9430 newadv = ADVERTISED_Pause |
9431 ADVERTISED_Asym_Pause;
9432 } else if (epause->tx_pause) {
9433 newadv = ADVERTISED_Asym_Pause;
9434 } else
9435 newadv = 0;
9436
9437 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9438 u32 oldadv = phydev->advertising &
9439 (ADVERTISED_Pause |
9440 ADVERTISED_Asym_Pause);
9441 if (oldadv != newadv) {
9442 phydev->advertising &=
9443 ~(ADVERTISED_Pause |
9444 ADVERTISED_Asym_Pause);
9445 phydev->advertising |= newadv;
9446 err = phy_start_aneg(phydev);
9447 }
9448 } else {
9449 tp->link_config.advertising &=
9450 ~(ADVERTISED_Pause |
9451 ADVERTISED_Asym_Pause);
9452 tp->link_config.advertising |= newadv;
9453 }
9454 } else {
9455 if (epause->rx_pause)
e18ce346 9456 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9457 else
e18ce346 9458 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9459
b02fd9e3 9460 if (epause->tx_pause)
e18ce346 9461 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9462 else
e18ce346 9463 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9464
9465 if (netif_running(dev))
9466 tg3_setup_flow_control(tp, 0, 0);
9467 }
9468 } else {
9469 int irq_sync = 0;
9470
9471 if (netif_running(dev)) {
9472 tg3_netif_stop(tp);
9473 irq_sync = 1;
9474 }
9475
9476 tg3_full_lock(tp, irq_sync);
9477
9478 if (epause->autoneg)
9479 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9480 else
9481 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9482 if (epause->rx_pause)
e18ce346 9483 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9484 else
e18ce346 9485 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9486 if (epause->tx_pause)
e18ce346 9487 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9488 else
e18ce346 9489 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9490
9491 if (netif_running(dev)) {
9492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9493 err = tg3_restart_hw(tp, 1);
9494 if (!err)
9495 tg3_netif_start(tp);
9496 }
9497
9498 tg3_full_unlock(tp);
9499 }
6aa20a22 9500
b9ec6c1b 9501 return err;
1da177e4 9502}
6aa20a22 9503
1da177e4
LT		 9504static u32 tg3_get_rx_csum(struct net_device *dev)
9505{
9506 struct tg3 *tp = netdev_priv(dev);
9507 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9508}
6aa20a22 9509
1da177e4
LT		 9510static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9511{
9512 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9513
1da177e4
LT		 9514 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9515 if (data != 0)
9516 return -EINVAL;
9517 return 0;
9518 }
6aa20a22 9519
f47c11ee 9520 spin_lock_bh(&tp->lock);
1da177e4
LT		 9521 if (data)
9522 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9523 else
9524 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9525 spin_unlock_bh(&tp->lock);
6aa20a22 9526
1da177e4
LT		 9527 return 0;
9528}
6aa20a22 9529
1da177e4
LT		 9530static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9531{
9532 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9533
1da177e4
LT		 9534 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9535 if (data != 0)
9536 return -EINVAL;
9537 return 0;
9538 }
6aa20a22 9539
321d32a0 9540 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9541 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9542 else
9c27dbdf 9543 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9544
9545 return 0;
9546}
9547
b9f2c044 9548static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9549{
b9f2c044
JG		 9550 switch (sset) {
9551 case ETH_SS_TEST:
9552 return TG3_NUM_TEST;
9553 case ETH_SS_STATS:
9554 return TG3_NUM_STATS;
9555 default:
9556 return -EOPNOTSUPP;
9557 }
4cafd3f5
MC		 9558}
9559
1da177e4
LT		 9560static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9561{
9562 switch (stringset) {
9563 case ETH_SS_STATS:
9564 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9565 break;
4cafd3f5
MC		 9566 case ETH_SS_TEST:
9567 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9568 break;
1da177e4
LT		 9569 default:
9570 WARN_ON(1); /* we need a WARN() */
9571 break;
9572 }
9573}
9574
4009a93d
MC		 9575static int tg3_phys_id(struct net_device *dev, u32 data)
9576{
9577 struct tg3 *tp = netdev_priv(dev);
9578 int i;
9579
9580 if (!netif_running(tp->dev))
9581 return -EAGAIN;
9582
9583 if (data == 0)
759afc31 9584 data = UINT_MAX / 2;
4009a93d
MC		 9585
9586 for (i = 0; i < (data * 2); i++) {
9587 if ((i % 2) == 0)
9588 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9589 LED_CTRL_1000MBPS_ON |
9590 LED_CTRL_100MBPS_ON |
9591 LED_CTRL_10MBPS_ON |
9592 LED_CTRL_TRAFFIC_OVERRIDE |
9593 LED_CTRL_TRAFFIC_BLINK |
9594 LED_CTRL_TRAFFIC_LED);
6aa20a22 9595
4009a93d
MC		 9596 else
9597 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9598 LED_CTRL_TRAFFIC_OVERRIDE);
9599
9600 if (msleep_interruptible(500))
9601 break;
9602 }
9603 tw32(MAC_LED_CTRL, tp->led_ctrl);
9604 return 0;
9605}
9606
1da177e4
LT		 9607static void tg3_get_ethtool_stats (struct net_device *dev,
9608 struct ethtool_stats *estats, u64 *tmp_stats)
9609{
9610 struct tg3 *tp = netdev_priv(dev);
9611 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9612}
9613
566f86ad 9614#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9615#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9616#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9617#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9618#define NVRAM_SELFBOOT_HW_SIZE 0x20
9619#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9620
9621static int tg3_test_nvram(struct tg3 *tp)
9622{
b9fc7dc5
AV		 9623 u32 csum, magic;
9624 __le32 *buf;
ab0049b4 9625 int i, j, k, err = 0, size;
566f86ad 9626
1820180b 9627 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 9628 return -EIO;
9629
1b27777a
MC		 9630 if (magic == TG3_EEPROM_MAGIC)
9631 size = NVRAM_TEST_SIZE;
b16250e3 9632 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9633 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9634 TG3_EEPROM_SB_FORMAT_1) {
9635 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9636 case TG3_EEPROM_SB_REVISION_0:
9637 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9638 break;
9639 case TG3_EEPROM_SB_REVISION_2:
9640 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9641 break;
9642 case TG3_EEPROM_SB_REVISION_3:
9643 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9644 break;
9645 default:
9646 return 0;
9647 }
9648 } else
1b27777a 9649 return 0;
b16250e3
MC		 9650 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9651 size = NVRAM_SELFBOOT_HW_SIZE;
9652 else
1b27777a
MC		 9653 return -EIO;
9654
9655 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9656 if (buf == NULL)
9657 return -ENOMEM;
9658
1b27777a
MC		 9659 err = -EIO;
9660 for (i = 0, j = 0; i < size; i += 4, j++) {
b9fc7dc5 9661 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
566f86ad 9662 break;
566f86ad 9663 }
1b27777a 9664 if (i < size)
566f86ad
MC		 9665 goto out;
9666
1b27777a 9667 /* Selfboot format */
b9fc7dc5
AV		 9668 magic = swab32(le32_to_cpu(buf[0]));
9669 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9670 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9671 u8 *buf8 = (u8 *) buf, csum8 = 0;
9672
b9fc7dc5 9673 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9674 TG3_EEPROM_SB_REVISION_2) {
9675 /* For rev 2, the csum doesn't include the MBA. */
9676 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9677 csum8 += buf8[i];
9678 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9679 csum8 += buf8[i];
9680 } else {
9681 for (i = 0; i < size; i++)
9682 csum8 += buf8[i];
9683 }
1b27777a 9684
ad96b485
AB		 9685 if (csum8 == 0) {
9686 err = 0;
9687 goto out;
9688 }
9689
9690 err = -EIO;
9691 goto out;
1b27777a 9692 }
566f86ad 9693
b9fc7dc5 9694 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9695 TG3_EEPROM_MAGIC_HW) {
9696 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9697 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9698 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9699
9700 /* Separate the parity bits and the data bytes. */
9701 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9702 if ((i == 0) || (i == 8)) {
9703 int l;
9704 u8 msk;
9705
9706 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9707 parity[k++] = buf8[i] & msk;
9708 i++;
9709 }
9710 else if (i == 16) {
9711 int l;
9712 u8 msk;
9713
9714 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9715 parity[k++] = buf8[i] & msk;
9716 i++;
9717
9718 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9719 parity[k++] = buf8[i] & msk;
9720 i++;
9721 }
9722 data[j++] = buf8[i];
9723 }
9724
9725 err = -EIO;
9726 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9727 u8 hw8 = hweight8(data[i]);
9728
9729 if ((hw8 & 0x1) && parity[i])
9730 goto out;
9731 else if (!(hw8 & 0x1) && !parity[i])
9732 goto out;
9733 }
9734 err = 0;
9735 goto out;
9736 }
9737
566f86ad
MC		 9738 /* Bootstrap checksum at offset 0x10 */
9739 csum = calc_crc((unsigned char *) buf, 0x10);
b9fc7dc5 9740 if(csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9741 goto out;
9742
9743 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9744 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
b9fc7dc5 9745 if (csum != le32_to_cpu(buf[0xfc/4]))
566f86ad
MC		 9746 goto out;
9747
9748 err = 0;
9749
9750out:
9751 kfree(buf);
9752 return err;
9753}
9754
ca43007a
MC		 9755#define TG3_SERDES_TIMEOUT_SEC 2
9756#define TG3_COPPER_TIMEOUT_SEC 6
9757
9758static int tg3_test_link(struct tg3 *tp)
9759{
9760 int i, max;
9761
9762 if (!netif_running(tp->dev))
9763 return -ENODEV;
9764
4c987487 9765 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9766 max = TG3_SERDES_TIMEOUT_SEC;
9767 else
9768 max = TG3_COPPER_TIMEOUT_SEC;
9769
9770 for (i = 0; i < max; i++) {
9771 if (netif_carrier_ok(tp->dev))
9772 return 0;
9773
9774 if (msleep_interruptible(1000))
9775 break;
9776 }
9777
9778 return -EIO;
9779}
9780
a71116d1 9781/* Only test the commonly used registers */
30ca3e37 9782static int tg3_test_registers(struct tg3 *tp)
a71116d1 9783{
b16250e3 9784 int i, is_5705, is_5750;
a71116d1
MC		 9785 u32 offset, read_mask, write_mask, val, save_val, read_val;
9786 static struct {
9787 u16 offset;
9788 u16 flags;
9789#define TG3_FL_5705 0x1
9790#define TG3_FL_NOT_5705 0x2
9791#define TG3_FL_NOT_5788 0x4
b16250e3 9792#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9793 u32 read_mask;
9794 u32 write_mask;
9795 } reg_tbl[] = {
9796 /* MAC Control Registers */
9797 { MAC_MODE, TG3_FL_NOT_5705,
9798 0x00000000, 0x00ef6f8c },
9799 { MAC_MODE, TG3_FL_5705,
9800 0x00000000, 0x01ef6b8c },
9801 { MAC_STATUS, TG3_FL_NOT_5705,
9802 0x03800107, 0x00000000 },
9803 { MAC_STATUS, TG3_FL_5705,
9804 0x03800100, 0x00000000 },
9805 { MAC_ADDR_0_HIGH, 0x0000,
9806 0x00000000, 0x0000ffff },
9807 { MAC_ADDR_0_LOW, 0x0000,
9808 0x00000000, 0xffffffff },
9809 { MAC_RX_MTU_SIZE, 0x0000,
9810 0x00000000, 0x0000ffff },
9811 { MAC_TX_MODE, 0x0000,
9812 0x00000000, 0x00000070 },
9813 { MAC_TX_LENGTHS, 0x0000,
9814 0x00000000, 0x00003fff },
9815 { MAC_RX_MODE, TG3_FL_NOT_5705,
9816 0x00000000, 0x000007fc },
9817 { MAC_RX_MODE, TG3_FL_5705,
9818 0x00000000, 0x000007dc },
9819 { MAC_HASH_REG_0, 0x0000,
9820 0x00000000, 0xffffffff },
9821 { MAC_HASH_REG_1, 0x0000,
9822 0x00000000, 0xffffffff },
9823 { MAC_HASH_REG_2, 0x0000,
9824 0x00000000, 0xffffffff },
9825 { MAC_HASH_REG_3, 0x0000,
9826 0x00000000, 0xffffffff },
9827
9828 /* Receive Data and Receive BD Initiator Control Registers. */
9829 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9830 0x00000000, 0xffffffff },
9831 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9832 0x00000000, 0xffffffff },
9833 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9834 0x00000000, 0x00000003 },
9835 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9836 0x00000000, 0xffffffff },
9837 { RCVDBDI_STD_BD+0, 0x0000,
9838 0x00000000, 0xffffffff },
9839 { RCVDBDI_STD_BD+4, 0x0000,
9840 0x00000000, 0xffffffff },
9841 { RCVDBDI_STD_BD+8, 0x0000,
9842 0x00000000, 0xffff0002 },
9843 { RCVDBDI_STD_BD+0xc, 0x0000,
9844 0x00000000, 0xffffffff },
6aa20a22 9845
a71116d1
MC		 9846 /* Receive BD Initiator Control Registers. */
9847 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9848 0x00000000, 0xffffffff },
9849 { RCVBDI_STD_THRESH, TG3_FL_5705,
9850 0x00000000, 0x000003ff },
9851 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9852 0x00000000, 0xffffffff },
6aa20a22 9853
a71116d1
MC		 9854 /* Host Coalescing Control Registers. */
9855 { HOSTCC_MODE, TG3_FL_NOT_5705,
9856 0x00000000, 0x00000004 },
9857 { HOSTCC_MODE, TG3_FL_5705,
9858 0x00000000, 0x000000f6 },
9859 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9860 0x00000000, 0xffffffff },
9861 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9862 0x00000000, 0x000003ff },
9863 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9864 0x00000000, 0xffffffff },
9865 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9866 0x00000000, 0x000003ff },
9867 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9868 0x00000000, 0xffffffff },
9869 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9870 0x00000000, 0x000000ff },
9871 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9872 0x00000000, 0xffffffff },
9873 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9874 0x00000000, 0x000000ff },
9875 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9876 0x00000000, 0xffffffff },
9877 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9878 0x00000000, 0xffffffff },
9879 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9880 0x00000000, 0xffffffff },
9881 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9882 0x00000000, 0x000000ff },
9883 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9884 0x00000000, 0xffffffff },
9885 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9886 0x00000000, 0x000000ff },
9887 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9888 0x00000000, 0xffffffff },
9889 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9890 0x00000000, 0xffffffff },
9891 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9892 0x00000000, 0xffffffff },
9893 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9894 0x00000000, 0xffffffff },
9895 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9896 0x00000000, 0xffffffff },
9897 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9898 0xffffffff, 0x00000000 },
9899 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9900 0xffffffff, 0x00000000 },
9901
9902 /* Buffer Manager Control Registers. */
b16250e3 9903 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9904 0x00000000, 0x007fff80 },
b16250e3 9905 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9906 0x00000000, 0x007fffff },
9907 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9908 0x00000000, 0x0000003f },
9909 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9910 0x00000000, 0x000001ff },
9911 { BUFMGR_MB_HIGH_WATER, 0x0000,
9912 0x00000000, 0x000001ff },
9913 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9914 0xffffffff, 0x00000000 },
9915 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9916 0xffffffff, 0x00000000 },
6aa20a22 9917
a71116d1
MC		 9918 /* Mailbox Registers */
9919 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9920 0x00000000, 0x000001ff },
9921 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9922 0x00000000, 0x000001ff },
9923 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9924 0x00000000, 0x000007ff },
9925 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9926 0x00000000, 0x000001ff },
9927
9928 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9929 };
9930
b16250e3
MC		 9931 is_5705 = is_5750 = 0;
9932 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9933 is_5705 = 1;
b16250e3
MC		 9934 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9935 is_5750 = 1;
9936 }
a71116d1
MC		 9937
9938 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9939 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9940 continue;
9941
9942 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9943 continue;
9944
9945 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9946 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9947 continue;
9948
b16250e3
MC		 9949 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9950 continue;
9951
a71116d1
MC		 9952 offset = (u32) reg_tbl[i].offset;
9953 read_mask = reg_tbl[i].read_mask;
9954 write_mask = reg_tbl[i].write_mask;
9955
9956 /* Save the original register content */
9957 save_val = tr32(offset);
9958
9959 /* Determine the read-only value. */
9960 read_val = save_val & read_mask;
9961
9962 /* Write zero to the register, then make sure the read-only bits
9963 * are not changed and the read/write bits are all zeros.
9964 */
9965 tw32(offset, 0);
9966
9967 val = tr32(offset);
9968
9969 /* Test the read-only and read/write bits. */
9970 if (((val & read_mask) != read_val) || (val & write_mask))
9971 goto out;
9972
9973 /* Write ones to all the bits defined by RdMask and WrMask, then
9974 * make sure the read-only bits are not changed and the
9975 * read/write bits are all ones.
9976 */
9977 tw32(offset, read_mask | write_mask);
9978
9979 val = tr32(offset);
9980
9981 /* Test the read-only bits. */
9982 if ((val & read_mask) != read_val)
9983 goto out;
9984
9985 /* Test the read/write bits. */
9986 if ((val & write_mask) != write_mask)
9987 goto out;
9988
9989 tw32(offset, save_val);
9990 }
9991
9992 return 0;
9993
9994out:
9f88f29f
MC		 9995 if (netif_msg_hw(tp))
9996 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9997 offset);
a71116d1
MC		 9998 tw32(offset, save_val);
9999 return -EIO;
10000}
10001
7942e1db
MC		 10002static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10003{
f71e1309 10004 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10005 int i;
10006 u32 j;
10007
e9edda69 10008 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10009 for (j = 0; j < len; j += 4) {
10010 u32 val;
10011
10012 tg3_write_mem(tp, offset + j, test_pattern[i]);
10013 tg3_read_mem(tp, offset + j, &val);
10014 if (val != test_pattern[i])
10015 return -EIO;
10016 }
10017 }
10018 return 0;
10019}
10020
10021static int tg3_test_memory(struct tg3 *tp)
10022{
10023 static struct mem_entry {
10024 u32 offset;
10025 u32 len;
10026 } mem_tbl_570x[] = {
38690194 10027 { 0x00000000, 0x00b50},
7942e1db
MC		 10028 { 0x00002000, 0x1c000},
10029 { 0xffffffff, 0x00000}
10030 }, mem_tbl_5705[] = {
10031 { 0x00000100, 0x0000c},
10032 { 0x00000200, 0x00008},
7942e1db
MC		 10033 { 0x00004000, 0x00800},
10034 { 0x00006000, 0x01000},
10035 { 0x00008000, 0x02000},
10036 { 0x00010000, 0x0e000},
10037 { 0xffffffff, 0x00000}
79f4d13a
MC		 10038 }, mem_tbl_5755[] = {
10039 { 0x00000200, 0x00008},
10040 { 0x00004000, 0x00800},
10041 { 0x00006000, 0x00800},
10042 { 0x00008000, 0x02000},
10043 { 0x00010000, 0x0c000},
10044 { 0xffffffff, 0x00000}
b16250e3
MC		 10045 }, mem_tbl_5906[] = {
10046 { 0x00000200, 0x00008},
10047 { 0x00004000, 0x00400},
10048 { 0x00006000, 0x00400},
10049 { 0x00008000, 0x01000},
10050 { 0x00010000, 0x01000},
10051 { 0xffffffff, 0x00000}
7942e1db
MC		 10052 };
10053 struct mem_entry *mem_tbl;
10054 int err = 0;
10055 int i;
10056
321d32a0
MC		 10057 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10058 mem_tbl = mem_tbl_5755;
10059 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10060 mem_tbl = mem_tbl_5906;
10061 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10062 mem_tbl = mem_tbl_5705;
10063 else
7942e1db
MC		 10064 mem_tbl = mem_tbl_570x;
10065
10066 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10067 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10068 mem_tbl[i].len)) != 0)
10069 break;
10070 }
6aa20a22 10071
7942e1db
MC		 10072 return err;
10073}
10074
9f40dead
MC		 10075#define TG3_MAC_LOOPBACK 0
10076#define TG3_PHY_LOOPBACK 1
10077
10078static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10079{
9f40dead 10080 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 10081 u32 desc_idx;
10082 struct sk_buff *skb, *rx_skb;
10083 u8 *tx_data;
10084 dma_addr_t map;
10085 int num_pkts, tx_len, rx_len, i, err;
10086 struct tg3_rx_buffer_desc *desc;
10087
9f40dead 10088 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10089 /* HW errata - mac loopback fails in some cases on 5780.
10090 * Normal traffic and PHY loopback are not affected by
10091 * errata.
10092 */
10093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10094 return 0;
10095
9f40dead 10096 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10097 MAC_MODE_PORT_INT_LPBACK;
10098 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10099 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10100 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10101 mac_mode |= MAC_MODE_PORT_MODE_MII;
10102 else
10103 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10104 tw32(MAC_MODE, mac_mode);
10105 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10106 u32 val;
10107
b16250e3
MC		 10108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10109 u32 phytest;
10110
10111 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
10112 u32 phy;
10113
10114 tg3_writephy(tp, MII_TG3_EPHY_TEST,
10115 phytest | MII_TG3_EPHY_SHADOW_EN);
10116 if (!tg3_readphy(tp, 0x1b, &phy))
10117 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 10118 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
10119 }
5d64ad34
MC		 10120 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10121 } else
10122 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10123
9ef8ca99
MC		 10124 tg3_phy_toggle_automdix(tp, 0);
10125
3f7045c1 10126 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10127 udelay(40);
5d64ad34 10128
e8f3f6ca 10129 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 10130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 10131 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 10132 mac_mode |= MAC_MODE_PORT_MODE_MII;
10133 } else
10134 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10135
c94e3941
MC		 10136 /* reset to prevent losing 1st rx packet intermittently */
10137 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10138 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10139 udelay(10);
10140 tw32_f(MAC_RX_MODE, tp->rx_mode);
10141 }
e8f3f6ca
MC		 10142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10143 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10144 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10145 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10146 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10147 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10148 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10149 }
9f40dead 10150 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10151 }
10152 else
10153 return -EINVAL;
c76949a6
MC		 10154
10155 err = -EIO;
10156
c76949a6 10157 tx_len = 1514;
a20e9c62 10158 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10159 if (!skb)
10160 return -ENOMEM;
10161
c76949a6
MC		 10162 tx_data = skb_put(skb, tx_len);
10163 memcpy(tx_data, tp->dev->dev_addr, 6);
10164 memset(tx_data + 6, 0x0, 8);
10165
10166 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10167
10168 for (i = 14; i < tx_len; i++)
10169 tx_data[i] = (u8) (i & 0xff);
10170
10171 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10172
10173 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10174 HOSTCC_MODE_NOW);
10175
10176 udelay(10);
10177
10178 rx_start_idx = tp->hw_status->idx[0].rx_producer;
10179
c76949a6
MC		 10180 num_pkts = 0;
10181
9f40dead 10182 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 10183
9f40dead 10184 tp->tx_prod++;
c76949a6
MC		 10185 num_pkts++;
10186
9f40dead
MC		 10187 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10188 tp->tx_prod);
09ee929c 10189 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 10190
10191 udelay(10);
10192
3f7045c1
MC		 10193 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10194 for (i = 0; i < 25; i++) {
c76949a6
MC		 10195 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10196 HOSTCC_MODE_NOW);
10197
10198 udelay(10);
10199
10200 tx_idx = tp->hw_status->idx[0].tx_consumer;
10201 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 10202 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 10203 (rx_idx == (rx_start_idx + num_pkts)))
10204 break;
10205 }
10206
10207 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10208 dev_kfree_skb(skb);
10209
9f40dead 10210 if (tx_idx != tp->tx_prod)
c76949a6
MC		 10211 goto out;
10212
10213 if (rx_idx != rx_start_idx + num_pkts)
10214 goto out;
10215
10216 desc = &tp->rx_rcb[rx_start_idx];
10217 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10218 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10219 if (opaque_key != RXD_OPAQUE_RING_STD)
10220 goto out;
10221
10222 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10223 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10224 goto out;
10225
10226 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10227 if (rx_len != tx_len)
10228 goto out;
10229
10230 rx_skb = tp->rx_std_buffers[desc_idx].skb;
10231
10232 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10233 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10234
10235 for (i = 14; i < tx_len; i++) {
10236 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10237 goto out;
10238 }
10239 err = 0;
6aa20a22 10240
c76949a6
MC		 10241 /* tg3_free_rings will unmap and free the rx_skb */
10242out:
10243 return err;
10244}
10245
9f40dead
MC		 10246#define TG3_MAC_LOOPBACK_FAILED 1
10247#define TG3_PHY_LOOPBACK_FAILED 2
10248#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10249 TG3_PHY_LOOPBACK_FAILED)
10250
10251static int tg3_test_loopback(struct tg3 *tp)
10252{
10253 int err = 0;
9936bcf6 10254 u32 cpmuctrl = 0;
9f40dead
MC		 10255
10256 if (!netif_running(tp->dev))
10257 return TG3_LOOPBACK_FAILED;
10258
b9ec6c1b
MC		 10259 err = tg3_reset_hw(tp, 1);
10260 if (err)
10261 return TG3_LOOPBACK_FAILED;
9f40dead 10262
6833c043
MC		 10263 /* Turn off gphy autopowerdown. */
10264 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10265 tg3_phy_toggle_apd(tp, false);
10266
321d32a0 10267 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10268 int i;
10269 u32 status;
10270
10271 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10272
10273 /* Wait for up to 40 microseconds to acquire lock. */
10274 for (i = 0; i < 4; i++) {
10275 status = tr32(TG3_CPMU_MUTEX_GNT);
10276 if (status == CPMU_MUTEX_GNT_DRIVER)
10277 break;
10278 udelay(10);
10279 }
10280
10281 if (status != CPMU_MUTEX_GNT_DRIVER)
10282 return TG3_LOOPBACK_FAILED;
10283
b2a5c19c 10284 /* Turn off link-based power management. */
e875093c 10285 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10286 tw32(TG3_CPMU_CTRL,
10287 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10288 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10289 }
10290
9f40dead
MC		 10291 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10292 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10293
321d32a0 10294 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10295 tw32(TG3_CPMU_CTRL, cpmuctrl);
10296
10297 /* Release the mutex */
10298 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10299 }
10300
dd477003
MC		 10301 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10302 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10303 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10304 err |= TG3_PHY_LOOPBACK_FAILED;
10305 }
10306
6833c043
MC		 10307 /* Re-enable gphy autopowerdown. */
10308 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10309 tg3_phy_toggle_apd(tp, true);
10310
9f40dead
MC		 10311 return err;
10312}
10313
4cafd3f5
MC		 10314static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10315 u64 *data)
10316{
566f86ad
MC		 10317 struct tg3 *tp = netdev_priv(dev);
10318
bc1c7567
MC		 10319 if (tp->link_config.phy_is_low_power)
10320 tg3_set_power_state(tp, PCI_D0);
10321
566f86ad
MC		 10322 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10323
10324 if (tg3_test_nvram(tp) != 0) {
10325 etest->flags |= ETH_TEST_FL_FAILED;
10326 data[0] = 1;
10327 }
ca43007a
MC		 10328 if (tg3_test_link(tp) != 0) {
10329 etest->flags |= ETH_TEST_FL_FAILED;
10330 data[1] = 1;
10331 }
a71116d1 10332 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10333 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10334
10335 if (netif_running(dev)) {
b02fd9e3 10336 tg3_phy_stop(tp);
a71116d1 10337 tg3_netif_stop(tp);
bbe832c0
MC		 10338 irq_sync = 1;
10339 }
a71116d1 10340
bbe832c0 10341 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10342
10343 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10344 err = tg3_nvram_lock(tp);
a71116d1
MC		 10345 tg3_halt_cpu(tp, RX_CPU_BASE);
10346 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10347 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10348 if (!err)
10349 tg3_nvram_unlock(tp);
a71116d1 10350
d9ab5ad1
MC		 10351 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10352 tg3_phy_reset(tp);
10353
a71116d1
MC		 10354 if (tg3_test_registers(tp) != 0) {
10355 etest->flags |= ETH_TEST_FL_FAILED;
10356 data[2] = 1;
10357 }
7942e1db
MC		 10358 if (tg3_test_memory(tp) != 0) {
10359 etest->flags |= ETH_TEST_FL_FAILED;
10360 data[3] = 1;
10361 }
9f40dead 10362 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10363 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10364
f47c11ee
DM		 10365 tg3_full_unlock(tp);
10366
d4bc3927
MC		 10367 if (tg3_test_interrupt(tp) != 0) {
10368 etest->flags |= ETH_TEST_FL_FAILED;
10369 data[5] = 1;
10370 }
f47c11ee
DM		 10371
10372 tg3_full_lock(tp, 0);
d4bc3927 10373
a71116d1
MC		 10374 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10375 if (netif_running(dev)) {
10376 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10377 err2 = tg3_restart_hw(tp, 1);
10378 if (!err2)
b9ec6c1b 10379 tg3_netif_start(tp);
a71116d1 10380 }
f47c11ee
DM		 10381
10382 tg3_full_unlock(tp);
b02fd9e3
MC		 10383
10384 if (irq_sync && !err2)
10385 tg3_phy_start(tp);
a71116d1 10386 }
bc1c7567
MC		 10387 if (tp->link_config.phy_is_low_power)
10388 tg3_set_power_state(tp, PCI_D3hot);
10389
4cafd3f5
MC		 10390}
10391
1da177e4
LT		 10392static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10393{
10394 struct mii_ioctl_data *data = if_mii(ifr);
10395 struct tg3 *tp = netdev_priv(dev);
10396 int err;
10397
b02fd9e3
MC		 10398 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10399 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10400 return -EAGAIN;
298cf9be 10401 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10402 }
10403
1da177e4
LT		 10404 switch(cmd) {
10405 case SIOCGMIIPHY:
10406 data->phy_id = PHY_ADDR;
10407
10408 /* fallthru */
10409 case SIOCGMIIREG: {
10410 u32 mii_regval;
10411
10412 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10413 break; /* We have no PHY */
10414
bc1c7567
MC		 10415 if (tp->link_config.phy_is_low_power)
10416 return -EAGAIN;
10417
f47c11ee 10418 spin_lock_bh(&tp->lock);
1da177e4 10419 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10420 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10421
10422 data->val_out = mii_regval;
10423
10424 return err;
10425 }
10426
10427 case SIOCSMIIREG:
10428 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10429 break; /* We have no PHY */
10430
10431 if (!capable(CAP_NET_ADMIN))
10432 return -EPERM;
10433
bc1c7567
MC		 10434 if (tp->link_config.phy_is_low_power)
10435 return -EAGAIN;
10436
f47c11ee 10437 spin_lock_bh(&tp->lock);
1da177e4 10438 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10439 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10440
10441 return err;
10442
10443 default:
10444 /* do nothing */
10445 break;
10446 }
10447 return -EOPNOTSUPP;
10448}
10449
10450#if TG3_VLAN_TAG_USED
10451static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10452{
10453 struct tg3 *tp = netdev_priv(dev);
10454
29315e87
MC		 10455 if (netif_running(dev))
10456 tg3_netif_stop(tp);
10457
f47c11ee 10458 tg3_full_lock(tp, 0);
1da177e4
LT		 10459
10460 tp->vlgrp = grp;
10461
10462 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10463 __tg3_set_rx_mode(dev);
10464
29315e87
MC		 10465 if (netif_running(dev))
10466 tg3_netif_start(tp);
46966545
MC		 10467
10468 tg3_full_unlock(tp);
1da177e4 10469}
1da177e4
LT		 10470#endif
10471
15f9850d
DM		 10472static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10473{
10474 struct tg3 *tp = netdev_priv(dev);
10475
10476 memcpy(ec, &tp->coal, sizeof(*ec));
10477 return 0;
10478}
10479
d244c892
MC		 10480static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10481{
10482 struct tg3 *tp = netdev_priv(dev);
10483 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10484 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10485
10486 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10487 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10488 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10489 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10490 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10491 }
10492
10493 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10494 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10495 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10496 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10497 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10498 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10499 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10500 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10501 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10502 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10503 return -EINVAL;
10504
10505 /* No rx interrupts will be generated if both are zero */
10506 if ((ec->rx_coalesce_usecs == 0) &&
10507 (ec->rx_max_coalesced_frames == 0))
10508 return -EINVAL;
10509
10510 /* No tx interrupts will be generated if both are zero */
10511 if ((ec->tx_coalesce_usecs == 0) &&
10512 (ec->tx_max_coalesced_frames == 0))
10513 return -EINVAL;
10514
10515 /* Only copy relevant parameters, ignore all others. */
10516 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10517 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10518 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10519 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10520 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10521 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10522 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10523 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10524 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10525
10526 if (netif_running(dev)) {
10527 tg3_full_lock(tp, 0);
10528 __tg3_set_coalesce(tp, &tp->coal);
10529 tg3_full_unlock(tp);
10530 }
10531 return 0;
10532}
10533
7282d491 10534static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10535 .get_settings = tg3_get_settings,
10536 .set_settings = tg3_set_settings,
10537 .get_drvinfo = tg3_get_drvinfo,
10538 .get_regs_len = tg3_get_regs_len,
10539 .get_regs = tg3_get_regs,
10540 .get_wol = tg3_get_wol,
10541 .set_wol = tg3_set_wol,
10542 .get_msglevel = tg3_get_msglevel,
10543 .set_msglevel = tg3_set_msglevel,
10544 .nway_reset = tg3_nway_reset,
10545 .get_link = ethtool_op_get_link,
10546 .get_eeprom_len = tg3_get_eeprom_len,
10547 .get_eeprom = tg3_get_eeprom,
10548 .set_eeprom = tg3_set_eeprom,
10549 .get_ringparam = tg3_get_ringparam,
10550 .set_ringparam = tg3_set_ringparam,
10551 .get_pauseparam = tg3_get_pauseparam,
10552 .set_pauseparam = tg3_set_pauseparam,
10553 .get_rx_csum = tg3_get_rx_csum,
10554 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10555 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10556 .set_sg = ethtool_op_set_sg,
1da177e4 10557 .set_tso = tg3_set_tso,
4cafd3f5 10558 .self_test = tg3_self_test,
1da177e4 10559 .get_strings = tg3_get_strings,
4009a93d 10560 .phys_id = tg3_phys_id,
1da177e4 10561 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10562 .get_coalesce = tg3_get_coalesce,
d244c892 10563 .set_coalesce = tg3_set_coalesce,
b9f2c044 10564 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10565};
10566
10567static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10568{
1b27777a 10569 u32 cursize, val, magic;
1da177e4
LT		 10570
10571 tp->nvram_size = EEPROM_CHIP_SIZE;
10572
1820180b 10573 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 10574 return;
10575
b16250e3
MC		 10576 if ((magic != TG3_EEPROM_MAGIC) &&
10577 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10578 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10579 return;
10580
10581 /*
10582 * Size the chip by reading offsets at increasing powers of two.
10583 * When we encounter our validation signature, we know the addressing
10584 * has wrapped around, and thus have our chip size.
10585 */
1b27777a 10586 cursize = 0x10;
1da177e4
LT		 10587
10588 while (cursize < tp->nvram_size) {
1820180b 10589 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 10590 return;
10591
1820180b 10592 if (val == magic)
1da177e4
LT		 10593 break;
10594
10595 cursize <<= 1;
10596 }
10597
10598 tp->nvram_size = cursize;
10599}
6aa20a22 10600
1da177e4
LT		 10601static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10602{
10603 u32 val;
10604
1820180b 10605 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 10606 return;
10607
10608 /* Selfboot format */
1820180b 10609 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10610 tg3_get_eeprom_size(tp);
10611 return;
10612 }
10613
1da177e4
LT		 10614 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10615 if (val != 0) {
10616 tp->nvram_size = (val >> 16) * 1024;
10617 return;
10618 }
10619 }
fd1122a2 10620 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10621}
10622
10623static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10624{
10625 u32 nvcfg1;
10626
10627 nvcfg1 = tr32(NVRAM_CFG1);
10628 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10629 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10630 }
10631 else {
10632 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10633 tw32(NVRAM_CFG1, nvcfg1);
10634 }
10635
4c987487 10636 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10637 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10638 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10639 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10640 tp->nvram_jedecnum = JEDEC_ATMEL;
10641 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10642 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10643 break;
10644 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10645 tp->nvram_jedecnum = JEDEC_ATMEL;
10646 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10647 break;
10648 case FLASH_VENDOR_ATMEL_EEPROM:
10649 tp->nvram_jedecnum = JEDEC_ATMEL;
10650 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10651 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10652 break;
10653 case FLASH_VENDOR_ST:
10654 tp->nvram_jedecnum = JEDEC_ST;
10655 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10656 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10657 break;
10658 case FLASH_VENDOR_SAIFUN:
10659 tp->nvram_jedecnum = JEDEC_SAIFUN;
10660 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10661 break;
10662 case FLASH_VENDOR_SST_SMALL:
10663 case FLASH_VENDOR_SST_LARGE:
10664 tp->nvram_jedecnum = JEDEC_SST;
10665 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10666 break;
10667 }
10668 }
10669 else {
10670 tp->nvram_jedecnum = JEDEC_ATMEL;
10671 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10672 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10673 }
10674}
10675
361b4ac2
MC		 10676static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10677{
10678 u32 nvcfg1;
10679
10680 nvcfg1 = tr32(NVRAM_CFG1);
10681
e6af301b
MC		 10682 /* NVRAM protection for TPM */
10683 if (nvcfg1 & (1 << 27))
10684 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10685
361b4ac2
MC		 10686 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10687 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10688 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10689 tp->nvram_jedecnum = JEDEC_ATMEL;
10690 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10691 break;
10692 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10693 tp->nvram_jedecnum = JEDEC_ATMEL;
10694 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10695 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10696 break;
10697 case FLASH_5752VENDOR_ST_M45PE10:
10698 case FLASH_5752VENDOR_ST_M45PE20:
10699 case FLASH_5752VENDOR_ST_M45PE40:
10700 tp->nvram_jedecnum = JEDEC_ST;
10701 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10702 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10703 break;
10704 }
10705
10706 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10707 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10708 case FLASH_5752PAGE_SIZE_256:
10709 tp->nvram_pagesize = 256;
10710 break;
10711 case FLASH_5752PAGE_SIZE_512:
10712 tp->nvram_pagesize = 512;
10713 break;
10714 case FLASH_5752PAGE_SIZE_1K:
10715 tp->nvram_pagesize = 1024;
10716 break;
10717 case FLASH_5752PAGE_SIZE_2K:
10718 tp->nvram_pagesize = 2048;
10719 break;
10720 case FLASH_5752PAGE_SIZE_4K:
10721 tp->nvram_pagesize = 4096;
10722 break;
10723 case FLASH_5752PAGE_SIZE_264:
10724 tp->nvram_pagesize = 264;
10725 break;
10726 }
10727 }
10728 else {
10729 /* For eeprom, set pagesize to maximum eeprom size */
10730 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10731
10732 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10733 tw32(NVRAM_CFG1, nvcfg1);
10734 }
10735}
10736
d3c7b886
MC		 10737static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10738{
989a9d23 10739 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10740
10741 nvcfg1 = tr32(NVRAM_CFG1);
10742
10743 /* NVRAM protection for TPM */
989a9d23 10744 if (nvcfg1 & (1 << 27)) {
d3c7b886 10745 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10746 protect = 1;
10747 }
d3c7b886 10748
989a9d23
MC		 10749 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10750 switch (nvcfg1) {
d3c7b886
MC		 10751 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10752 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10753 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10754 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10755 tp->nvram_jedecnum = JEDEC_ATMEL;
10756 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10757 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10758 tp->nvram_pagesize = 264;
70b65a2d
MC		 10759 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10760 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10761 tp->nvram_size = (protect ? 0x3e200 :
10762 TG3_NVRAM_SIZE_512KB);
989a9d23 10763 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10764 tp->nvram_size = (protect ? 0x1f200 :
10765 TG3_NVRAM_SIZE_256KB);
989a9d23 10766 else
fd1122a2
MC		 10767 tp->nvram_size = (protect ? 0x1f200 :
10768 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10769 break;
10770 case FLASH_5752VENDOR_ST_M45PE10:
10771 case FLASH_5752VENDOR_ST_M45PE20:
10772 case FLASH_5752VENDOR_ST_M45PE40:
10773 tp->nvram_jedecnum = JEDEC_ST;
10774 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10775 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10776 tp->nvram_pagesize = 256;
989a9d23 10777 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10778 tp->nvram_size = (protect ?
10779 TG3_NVRAM_SIZE_64KB :
10780 TG3_NVRAM_SIZE_128KB);
989a9d23 10781 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10782 tp->nvram_size = (protect ?
10783 TG3_NVRAM_SIZE_64KB :
10784 TG3_NVRAM_SIZE_256KB);
989a9d23 10785 else
fd1122a2
MC		 10786 tp->nvram_size = (protect ?
10787 TG3_NVRAM_SIZE_128KB :
10788 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10789 break;
10790 }
10791}
10792
1b27777a
MC		 10793static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10794{
10795 u32 nvcfg1;
10796
10797 nvcfg1 = tr32(NVRAM_CFG1);
10798
10799 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10800 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10801 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10802 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10803 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10804 tp->nvram_jedecnum = JEDEC_ATMEL;
10805 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10806 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10807
10808 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10809 tw32(NVRAM_CFG1, nvcfg1);
10810 break;
10811 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10812 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10813 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10814 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10815 tp->nvram_jedecnum = JEDEC_ATMEL;
10816 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10817 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10818 tp->nvram_pagesize = 264;
10819 break;
10820 case FLASH_5752VENDOR_ST_M45PE10:
10821 case FLASH_5752VENDOR_ST_M45PE20:
10822 case FLASH_5752VENDOR_ST_M45PE40:
10823 tp->nvram_jedecnum = JEDEC_ST;
10824 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10825 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10826 tp->nvram_pagesize = 256;
10827 break;
10828 }
10829}
10830
6b91fa02
MC		 10831static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10832{
10833 u32 nvcfg1, protect = 0;
10834
10835 nvcfg1 = tr32(NVRAM_CFG1);
10836
10837 /* NVRAM protection for TPM */
10838 if (nvcfg1 & (1 << 27)) {
10839 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10840 protect = 1;
10841 }
10842
10843 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10844 switch (nvcfg1) {
10845 case FLASH_5761VENDOR_ATMEL_ADB021D:
10846 case FLASH_5761VENDOR_ATMEL_ADB041D:
10847 case FLASH_5761VENDOR_ATMEL_ADB081D:
10848 case FLASH_5761VENDOR_ATMEL_ADB161D:
10849 case FLASH_5761VENDOR_ATMEL_MDB021D:
10850 case FLASH_5761VENDOR_ATMEL_MDB041D:
10851 case FLASH_5761VENDOR_ATMEL_MDB081D:
10852 case FLASH_5761VENDOR_ATMEL_MDB161D:
10853 tp->nvram_jedecnum = JEDEC_ATMEL;
10854 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10855 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10856 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10857 tp->nvram_pagesize = 256;
10858 break;
10859 case FLASH_5761VENDOR_ST_A_M45PE20:
10860 case FLASH_5761VENDOR_ST_A_M45PE40:
10861 case FLASH_5761VENDOR_ST_A_M45PE80:
10862 case FLASH_5761VENDOR_ST_A_M45PE16:
10863 case FLASH_5761VENDOR_ST_M_M45PE20:
10864 case FLASH_5761VENDOR_ST_M_M45PE40:
10865 case FLASH_5761VENDOR_ST_M_M45PE80:
10866 case FLASH_5761VENDOR_ST_M_M45PE16:
10867 tp->nvram_jedecnum = JEDEC_ST;
10868 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10869 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10870 tp->nvram_pagesize = 256;
10871 break;
10872 }
10873
10874 if (protect) {
10875 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10876 } else {
10877 switch (nvcfg1) {
10878 case FLASH_5761VENDOR_ATMEL_ADB161D:
10879 case FLASH_5761VENDOR_ATMEL_MDB161D:
10880 case FLASH_5761VENDOR_ST_A_M45PE16:
10881 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10882 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10883 break;
10884 case FLASH_5761VENDOR_ATMEL_ADB081D:
10885 case FLASH_5761VENDOR_ATMEL_MDB081D:
10886 case FLASH_5761VENDOR_ST_A_M45PE80:
10887 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10888 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10889 break;
10890 case FLASH_5761VENDOR_ATMEL_ADB041D:
10891 case FLASH_5761VENDOR_ATMEL_MDB041D:
10892 case FLASH_5761VENDOR_ST_A_M45PE40:
10893 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10894 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10895 break;
10896 case FLASH_5761VENDOR_ATMEL_ADB021D:
10897 case FLASH_5761VENDOR_ATMEL_MDB021D:
10898 case FLASH_5761VENDOR_ST_A_M45PE20:
10899 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10900 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10901 break;
10902 }
10903 }
10904}
10905
b5d3772c
MC		 10906static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10907{
10908 tp->nvram_jedecnum = JEDEC_ATMEL;
10909 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10910 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10911}
10912
321d32a0
MC		 10913static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10914{
10915 u32 nvcfg1;
10916
10917 nvcfg1 = tr32(NVRAM_CFG1);
10918
10919 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10920 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10921 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10922 tp->nvram_jedecnum = JEDEC_ATMEL;
10923 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10924 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10925
10926 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10927 tw32(NVRAM_CFG1, nvcfg1);
10928 return;
10929 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10930 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10931 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10932 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10933 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10934 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10935 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10936 tp->nvram_jedecnum = JEDEC_ATMEL;
10937 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10938 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10939
10940 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10941 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10942 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10943 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10944 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10945 break;
10946 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10947 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10948 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10949 break;
10950 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10951 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10952 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10953 break;
10954 }
10955 break;
10956 case FLASH_5752VENDOR_ST_M45PE10:
10957 case FLASH_5752VENDOR_ST_M45PE20:
10958 case FLASH_5752VENDOR_ST_M45PE40:
10959 tp->nvram_jedecnum = JEDEC_ST;
10960 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10961 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10962
10963 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10964 case FLASH_5752VENDOR_ST_M45PE10:
10965 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10966 break;
10967 case FLASH_5752VENDOR_ST_M45PE20:
10968 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10969 break;
10970 case FLASH_5752VENDOR_ST_M45PE40:
10971 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10972 break;
10973 }
10974 break;
10975 default:
10976 return;
10977 }
10978
10979 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10980 case FLASH_5752PAGE_SIZE_256:
10981 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10982 tp->nvram_pagesize = 256;
10983 break;
10984 case FLASH_5752PAGE_SIZE_512:
10985 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10986 tp->nvram_pagesize = 512;
10987 break;
10988 case FLASH_5752PAGE_SIZE_1K:
10989 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10990 tp->nvram_pagesize = 1024;
10991 break;
10992 case FLASH_5752PAGE_SIZE_2K:
10993 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10994 tp->nvram_pagesize = 2048;
10995 break;
10996 case FLASH_5752PAGE_SIZE_4K:
10997 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10998 tp->nvram_pagesize = 4096;
10999 break;
11000 case FLASH_5752PAGE_SIZE_264:
11001 tp->nvram_pagesize = 264;
11002 break;
11003 case FLASH_5752PAGE_SIZE_528:
11004 tp->nvram_pagesize = 528;
11005 break;
11006 }
11007}
11008
1da177e4
LT		 11009/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11010static void __devinit tg3_nvram_init(struct tg3 *tp)
11011{
1da177e4
LT		 11012 tw32_f(GRC_EEPROM_ADDR,
11013 (EEPROM_ADDR_FSM_RESET |
11014 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11015 EEPROM_ADDR_CLKPERD_SHIFT)));
11016
9d57f01c 11017 msleep(1);
1da177e4
LT		 11018
11019 /* Enable seeprom accesses. */
11020 tw32_f(GRC_LOCAL_CTRL,
11021 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11022 udelay(100);
11023
11024 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11025 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11026 tp->tg3_flags |= TG3_FLAG_NVRAM;
11027
ec41c7df
MC		 11028 if (tg3_nvram_lock(tp)) {
11029 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11030 "tg3_nvram_init failed.\n", tp->dev->name);
11031 return;
11032 }
e6af301b 11033 tg3_enable_nvram_access(tp);
1da177e4 11034
989a9d23
MC		 11035 tp->nvram_size = 0;
11036
361b4ac2
MC		 11037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11038 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11039 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11040 tg3_get_5755_nvram_info(tp);
d30cdd28 11041 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11043 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11044 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11045 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11046 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11047 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11048 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11049 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11050 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 11051 else
11052 tg3_get_nvram_info(tp);
11053
989a9d23
MC		 11054 if (tp->nvram_size == 0)
11055 tg3_get_nvram_size(tp);
1da177e4 11056
e6af301b 11057 tg3_disable_nvram_access(tp);
381291b7 11058 tg3_nvram_unlock(tp);
1da177e4
LT		 11059
11060 } else {
11061 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11062
11063 tg3_get_eeprom_size(tp);
11064 }
11065}
11066
11067static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
11068 u32 offset, u32 *val)
11069{
11070 u32 tmp;
11071 int i;
11072
11073 if (offset > EEPROM_ADDR_ADDR_MASK ||
11074 (offset % 4) != 0)
11075 return -EINVAL;
11076
11077 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
11078 EEPROM_ADDR_DEVID_MASK |
11079 EEPROM_ADDR_READ);
11080 tw32(GRC_EEPROM_ADDR,
11081 tmp |
11082 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11083 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
11084 EEPROM_ADDR_ADDR_MASK) |
11085 EEPROM_ADDR_READ | EEPROM_ADDR_START);
11086
9d57f01c 11087 for (i = 0; i < 1000; i++) {
1da177e4
LT		 11088 tmp = tr32(GRC_EEPROM_ADDR);
11089
11090 if (tmp & EEPROM_ADDR_COMPLETE)
11091 break;
9d57f01c 11092 msleep(1);
1da177e4
LT		 11093 }
11094 if (!(tmp & EEPROM_ADDR_COMPLETE))
11095 return -EBUSY;
11096
11097 *val = tr32(GRC_EEPROM_DATA);
11098 return 0;
11099}
11100
11101#define NVRAM_CMD_TIMEOUT 10000
11102
11103static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
11104{
11105 int i;
11106
11107 tw32(NVRAM_CMD, nvram_cmd);
11108 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
11109 udelay(10);
11110 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
11111 udelay(10);
11112 break;
11113 }
11114 }
11115 if (i == NVRAM_CMD_TIMEOUT) {
11116 return -EBUSY;
11117 }
11118 return 0;
11119}
11120
1820180b
MC		 11121static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
11122{
11123 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
11124 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
11125 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 11126 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1820180b
MC		 11127 (tp->nvram_jedecnum == JEDEC_ATMEL))
11128
11129 addr = ((addr / tp->nvram_pagesize) <<
11130 ATMEL_AT45DB0X1B_PAGE_POS) +
11131 (addr % tp->nvram_pagesize);
11132
11133 return addr;
11134}
11135
c4e6575c
MC		 11136static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
11137{
11138 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
11139 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
11140 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 11141 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
c4e6575c
MC		 11142 (tp->nvram_jedecnum == JEDEC_ATMEL))
11143
11144 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
11145 tp->nvram_pagesize) +
11146 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
11147
11148 return addr;
11149}
11150
1da177e4
LT		 11151static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
11152{
11153 int ret;
11154
1da177e4
LT		 11155 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
11156 return tg3_nvram_read_using_eeprom(tp, offset, val);
11157
1820180b 11158 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11159
11160 if (offset > NVRAM_ADDR_MSK)
11161 return -EINVAL;
11162
ec41c7df
MC		 11163 ret = tg3_nvram_lock(tp);
11164 if (ret)
11165 return ret;
1da177e4 11166
e6af301b 11167 tg3_enable_nvram_access(tp);
1da177e4
LT		 11168
11169 tw32(NVRAM_ADDR, offset);
11170 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
11171 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
11172
11173 if (ret == 0)
11174 *val = swab32(tr32(NVRAM_RDDATA));
11175
e6af301b 11176 tg3_disable_nvram_access(tp);
1da177e4 11177
381291b7
MC		 11178 tg3_nvram_unlock(tp);
11179
1da177e4
LT		 11180 return ret;
11181}
11182
b9fc7dc5
AV		 11183static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
11184{
11185 u32 v;
11186 int res = tg3_nvram_read(tp, offset, &v);
11187 if (!res)
11188 *val = cpu_to_le32(v);
11189 return res;
11190}
11191
1820180b
MC		 11192static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
11193{
11194 int err;
11195 u32 tmp;
11196
11197 err = tg3_nvram_read(tp, offset, &tmp);
11198 *val = swab32(tmp);
11199 return err;
11200}
11201
1da177e4
LT		 11202static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11203 u32 offset, u32 len, u8 *buf)
11204{
11205 int i, j, rc = 0;
11206 u32 val;
11207
11208 for (i = 0; i < len; i += 4) {
b9fc7dc5
AV		 11209 u32 addr;
11210 __le32 data;
1da177e4
LT		 11211
11212 addr = offset + i;
11213
11214 memcpy(&data, buf + i, 4);
11215
b9fc7dc5 11216 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
1da177e4
LT		 11217
11218 val = tr32(GRC_EEPROM_ADDR);
11219 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11220
11221 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11222 EEPROM_ADDR_READ);
11223 tw32(GRC_EEPROM_ADDR, val |
11224 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11225 (addr & EEPROM_ADDR_ADDR_MASK) |
11226 EEPROM_ADDR_START |
11227 EEPROM_ADDR_WRITE);
6aa20a22 11228
9d57f01c 11229 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11230 val = tr32(GRC_EEPROM_ADDR);
11231
11232 if (val & EEPROM_ADDR_COMPLETE)
11233 break;
9d57f01c 11234 msleep(1);
1da177e4
LT		 11235 }
11236 if (!(val & EEPROM_ADDR_COMPLETE)) {
11237 rc = -EBUSY;
11238 break;
11239 }
11240 }
11241
11242 return rc;
11243}
11244
11245/* offset and length are dword aligned */
11246static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11247 u8 *buf)
11248{
11249 int ret = 0;
11250 u32 pagesize = tp->nvram_pagesize;
11251 u32 pagemask = pagesize - 1;
11252 u32 nvram_cmd;
11253 u8 *tmp;
11254
11255 tmp = kmalloc(pagesize, GFP_KERNEL);
11256 if (tmp == NULL)
11257 return -ENOMEM;
11258
11259 while (len) {
11260 int j;
e6af301b 11261 u32 phy_addr, page_off, size;
1da177e4
LT		 11262
11263 phy_addr = offset & ~pagemask;
6aa20a22 11264
1da177e4 11265 for (j = 0; j < pagesize; j += 4) {
286e310f 11266 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
b9fc7dc5 11267 (__le32 *) (tmp + j))))
1da177e4
LT		 11268 break;
11269 }
11270 if (ret)
11271 break;
11272
11273 page_off = offset & pagemask;
11274 size = pagesize;
11275 if (len < size)
11276 size = len;
11277
11278 len -= size;
11279
11280 memcpy(tmp + page_off, buf, size);
11281
11282 offset = offset + (pagesize - page_off);
11283
e6af301b 11284 tg3_enable_nvram_access(tp);
1da177e4
LT		 11285
11286 /*
11287 * Before we can erase the flash page, we need
11288 * to issue a special "write enable" command.
11289 */
11290 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11291
11292 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11293 break;
11294
11295 /* Erase the target page */
11296 tw32(NVRAM_ADDR, phy_addr);
11297
11298 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11299 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11300
11301 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11302 break;
11303
11304 /* Issue another write enable to start the write. */
11305 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11306
11307 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11308 break;
11309
11310 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11311 __be32 data;
1da177e4 11312
b9fc7dc5
AV		 11313 data = *((__be32 *) (tmp + j));
11314 /* swab32(le32_to_cpu(data)), actually */
11315 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11316
11317 tw32(NVRAM_ADDR, phy_addr + j);
11318
11319 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11320 NVRAM_CMD_WR;
11321
11322 if (j == 0)
11323 nvram_cmd |= NVRAM_CMD_FIRST;
11324 else if (j == (pagesize - 4))
11325 nvram_cmd |= NVRAM_CMD_LAST;
11326
11327 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11328 break;
11329 }
11330 if (ret)
11331 break;
11332 }
11333
11334 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11335 tg3_nvram_exec_cmd(tp, nvram_cmd);
11336
11337 kfree(tmp);
11338
11339 return ret;
11340}
11341
11342/* offset and length are dword aligned */
11343static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11344 u8 *buf)
11345{
11346 int i, ret = 0;
11347
11348 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11349 u32 page_off, phy_addr, nvram_cmd;
11350 __be32 data;
1da177e4
LT		 11351
11352 memcpy(&data, buf + i, 4);
b9fc7dc5 11353 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11354
11355 page_off = offset % tp->nvram_pagesize;
11356
1820180b 11357 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11358
11359 tw32(NVRAM_ADDR, phy_addr);
11360
11361 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11362
11363 if ((page_off == 0) || (i == 0))
11364 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11365 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11366 nvram_cmd |= NVRAM_CMD_LAST;
11367
11368 if (i == (len - 4))
11369 nvram_cmd |= NVRAM_CMD_LAST;
11370
321d32a0
MC		 11371 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11372 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11373 (tp->nvram_jedecnum == JEDEC_ST) &&
11374 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11375
11376 if ((ret = tg3_nvram_exec_cmd(tp,
11377 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11378 NVRAM_CMD_DONE)))
11379
11380 break;
11381 }
11382 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11383 /* We always do complete word writes to eeprom. */
11384 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11385 }
11386
11387 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11388 break;
11389 }
11390 return ret;
11391}
11392
11393/* offset and length are dword aligned */
11394static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11395{
11396 int ret;
11397
1da177e4 11398 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11399 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11400 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11401 udelay(40);
11402 }
11403
11404 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11405 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11406 }
11407 else {
11408 u32 grc_mode;
11409
ec41c7df
MC		 11410 ret = tg3_nvram_lock(tp);
11411 if (ret)
11412 return ret;
1da177e4 11413
e6af301b
MC		 11414 tg3_enable_nvram_access(tp);
11415 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11416 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11417 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11418
11419 grc_mode = tr32(GRC_MODE);
11420 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11421
11422 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11423 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11424
11425 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11426 buf);
11427 }
11428 else {
11429 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11430 buf);
11431 }
11432
11433 grc_mode = tr32(GRC_MODE);
11434 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11435
e6af301b 11436 tg3_disable_nvram_access(tp);
1da177e4
LT		 11437 tg3_nvram_unlock(tp);
11438 }
11439
11440 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11441 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11442 udelay(40);
11443 }
11444
11445 return ret;
11446}
11447
11448struct subsys_tbl_ent {
11449 u16 subsys_vendor, subsys_devid;
11450 u32 phy_id;
11451};
11452
11453static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11454 /* Broadcom boards. */
11455 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11456 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11457 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11458 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11459 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11460 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11461 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11462 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11463 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11464 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11465 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11466
11467 /* 3com boards. */
11468 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11469 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11470 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11471 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11472 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11473
11474 /* DELL boards. */
11475 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11476 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11477 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11478 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11479
11480 /* Compaq boards. */
11481 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11482 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11483 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11484 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11485 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11486
11487 /* IBM boards. */
11488 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11489};
11490
11491static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11492{
11493 int i;
11494
11495 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11496 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11497 tp->pdev->subsystem_vendor) &&
11498 (subsys_id_to_phy_id[i].subsys_devid ==
11499 tp->pdev->subsystem_device))
11500 return &subsys_id_to_phy_id[i];
11501 }
11502 return NULL;
11503}
11504
7d0c41ef 11505static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11506{
1da177e4 11507 u32 val;
caf636c7
MC		 11508 u16 pmcsr;
11509
11510 /* On some early chips the SRAM cannot be accessed in D3hot state,
11511 * so need make sure we're in D0.
11512 */
11513 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11514 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11515 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11516 msleep(1);
7d0c41ef
MC		 11517
11518 /* Make sure register accesses (indirect or otherwise)
11519 * will function correctly.
11520 */
11521 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11522 tp->misc_host_ctrl);
1da177e4 11523
f49639e6
DM		 11524 /* The memory arbiter has to be enabled in order for SRAM accesses
11525 * to succeed. Normally on powerup the tg3 chip firmware will make
11526 * sure it is enabled, but other entities such as system netboot
11527 * code might disable it.
11528 */
11529 val = tr32(MEMARB_MODE);
11530 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11531
1da177e4 11532 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11533 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11534
a85feb8c
GZ		 11535 /* Assume an onboard device and WOL capable by default. */
11536 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11537
b5d3772c 11538 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11539 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11540 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11541 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11542 }
0527ba35
MC		 11543 val = tr32(VCPU_CFGSHDW);
11544 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11545 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11546 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12dac075
RW		 11547 (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11548 device_may_wakeup(&tp->pdev->dev))
0527ba35 11549 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11550 goto done;
b5d3772c
MC		 11551 }
11552
1da177e4
LT		 11553 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11554 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11555 u32 nic_cfg, led_cfg;
a9daf367 11556 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11557 int eeprom_phy_serdes = 0;
1da177e4
LT		 11558
11559 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11560 tp->nic_sram_data_cfg = nic_cfg;
11561
11562 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11563 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11564 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11565 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11566 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11567 (ver > 0) && (ver < 0x100))
11568 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11569
a9daf367
MC		 11570 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11571 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11572
1da177e4
LT		 11573 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11574 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11575 eeprom_phy_serdes = 1;
11576
11577 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11578 if (nic_phy_id != 0) {
11579 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11580 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11581
11582 eeprom_phy_id = (id1 >> 16) << 10;
11583 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11584 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11585 } else
11586 eeprom_phy_id = 0;
11587
7d0c41ef 11588 tp->phy_id = eeprom_phy_id;
747e8f8b 11589 if (eeprom_phy_serdes) {
a4e2b347 11590 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11591 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11592 else
11593 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11594 }
7d0c41ef 11595
cbf46853 11596 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11597 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11598 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11599 else
1da177e4
LT		 11600 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11601
11602 switch (led_cfg) {
11603 default:
11604 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11605 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11606 break;
11607
11608 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11609 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11610 break;
11611
11612 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11613 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11614
11615 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11616 * read on some older 5700/5701 bootcode.
11617 */
11618 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11619 ASIC_REV_5700 ||
11620 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11621 ASIC_REV_5701)
11622 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11623
1da177e4
LT		 11624 break;
11625
11626 case SHASTA_EXT_LED_SHARED:
11627 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11628 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11629 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11630 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11631 LED_CTRL_MODE_PHY_2);
11632 break;
11633
11634 case SHASTA_EXT_LED_MAC:
11635 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11636 break;
11637
11638 case SHASTA_EXT_LED_COMBO:
11639 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11640 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11641 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11642 LED_CTRL_MODE_PHY_2);
11643 break;
11644
855e1111 11645 }
1da177e4
LT		 11646
11647 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11648 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11649 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11650 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11651
b2a5c19c
MC		 11652 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11653 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11654
9d26e213 11655 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11656 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11657 if ((tp->pdev->subsystem_vendor ==
11658 PCI_VENDOR_ID_ARIMA) &&
11659 (tp->pdev->subsystem_device == 0x205a ||
11660 tp->pdev->subsystem_device == 0x2063))
11661 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11662 } else {
f49639e6 11663 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11664 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11665 }
1da177e4
LT		 11666
11667 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11668 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11669 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11670 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11671 }
b2b98d4a
MC		 11672
11673 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11674 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11675 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11676
a85feb8c
GZ		 11677 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11678 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11679 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11680
12dac075 11681 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11682 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11683 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11684
1da177e4
LT		 11685 if (cfg2 & (1 << 17))
11686 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11687
11688 /* serdes signal pre-emphasis in register 0x590 set by */
11689 /* bootcode if bit 18 is set */
11690 if (cfg2 & (1 << 18))
11691 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11692
321d32a0
MC		 11693 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11694 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11695 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11696 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11697
8ed5d97e
MC		 11698 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11699 u32 cfg3;
11700
11701 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11702 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11703 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11704 }
a9daf367
MC		 11705
11706 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11707 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11708 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11709 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11710 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11711 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11712 }
05ac4cb7
MC		 11713done:
11714 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11715 device_set_wakeup_enable(&tp->pdev->dev,
11716 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11717}
11718
b2a5c19c
MC		 11719static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11720{
11721 int i;
11722 u32 val;
11723
11724 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11725 tw32(OTP_CTRL, cmd);
11726
11727 /* Wait for up to 1 ms for command to execute. */
11728 for (i = 0; i < 100; i++) {
11729 val = tr32(OTP_STATUS);
11730 if (val & OTP_STATUS_CMD_DONE)
11731 break;
11732 udelay(10);
11733 }
11734
11735 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11736}
11737
11738/* Read the gphy configuration from the OTP region of the chip. The gphy
11739 * configuration is a 32-bit value that straddles the alignment boundary.
11740 * We do two 32-bit reads and then shift and merge the results.
11741 */
11742static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11743{
11744 u32 bhalf_otp, thalf_otp;
11745
11746 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11747
11748 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11749 return 0;
11750
11751 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11752
11753 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11754 return 0;
11755
11756 thalf_otp = tr32(OTP_READ_DATA);
11757
11758 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11759
11760 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11761 return 0;
11762
11763 bhalf_otp = tr32(OTP_READ_DATA);
11764
11765 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11766}
11767
7d0c41ef
MC		 11768static int __devinit tg3_phy_probe(struct tg3 *tp)
11769{
11770 u32 hw_phy_id_1, hw_phy_id_2;
11771 u32 hw_phy_id, hw_phy_id_masked;
11772 int err;
1da177e4 11773
b02fd9e3
MC		 11774 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11775 return tg3_phy_init(tp);
11776
1da177e4
LT		 11777 /* Reading the PHY ID register can conflict with ASF
11778 * firwmare access to the PHY hardware.
11779 */
11780 err = 0;
0d3031d9
MC		 11781 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11782 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11783 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11784 } else {
11785 /* Now read the physical PHY_ID from the chip and verify
11786 * that it is sane. If it doesn't look good, we fall back
11787 * to either the hard-coded table based PHY_ID and failing
11788 * that the value found in the eeprom area.
11789 */
11790 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11791 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11792
11793 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11794 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11795 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11796
11797 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11798 }
11799
11800 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11801 tp->phy_id = hw_phy_id;
11802 if (hw_phy_id_masked == PHY_ID_BCM8002)
11803 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11804 else
11805 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11806 } else {
7d0c41ef
MC		 11807 if (tp->phy_id != PHY_ID_INVALID) {
11808 /* Do nothing, phy ID already set up in
11809 * tg3_get_eeprom_hw_cfg().
11810 */
1da177e4
LT		 11811 } else {
11812 struct subsys_tbl_ent *p;
11813
11814 /* No eeprom signature? Try the hardcoded
11815 * subsys device table.
11816 */
11817 p = lookup_by_subsys(tp);
11818 if (!p)
11819 return -ENODEV;
11820
11821 tp->phy_id = p->phy_id;
11822 if (!tp->phy_id ||
11823 tp->phy_id == PHY_ID_BCM8002)
11824 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11825 }
11826 }
11827
747e8f8b 11828 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11829 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11830 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11831 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11832
11833 tg3_readphy(tp, MII_BMSR, &bmsr);
11834 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11835 (bmsr & BMSR_LSTATUS))
11836 goto skip_phy_reset;
6aa20a22 11837
1da177e4
LT		 11838 err = tg3_phy_reset(tp);
11839 if (err)
11840 return err;
11841
11842 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11843 ADVERTISE_100HALF | ADVERTISE_100FULL |
11844 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11845 tg3_ctrl = 0;
11846 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11847 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11848 MII_TG3_CTRL_ADV_1000_FULL);
11849 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11850 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11851 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11852 MII_TG3_CTRL_ENABLE_AS_MASTER);
11853 }
11854
3600d918
MC		 11855 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11856 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11857 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11858 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11859 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11860
11861 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11862 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11863
11864 tg3_writephy(tp, MII_BMCR,
11865 BMCR_ANENABLE | BMCR_ANRESTART);
11866 }
11867 tg3_phy_set_wirespeed(tp);
11868
11869 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11870 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11871 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11872 }
11873
11874skip_phy_reset:
11875 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11876 err = tg3_init_5401phy_dsp(tp);
11877 if (err)
11878 return err;
11879 }
11880
11881 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11882 err = tg3_init_5401phy_dsp(tp);
11883 }
11884
747e8f8b 11885 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11886 tp->link_config.advertising =
11887 (ADVERTISED_1000baseT_Half |
11888 ADVERTISED_1000baseT_Full |
11889 ADVERTISED_Autoneg |
11890 ADVERTISED_FIBRE);
11891 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11892 tp->link_config.advertising &=
11893 ~(ADVERTISED_1000baseT_Half |
11894 ADVERTISED_1000baseT_Full);
11895
11896 return err;
11897}
11898
11899static void __devinit tg3_read_partno(struct tg3 *tp)
11900{
11901 unsigned char vpd_data[256];
af2c6a4a 11902 unsigned int i;
1b27777a 11903 u32 magic;
1da177e4 11904
1820180b 11905 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 11906 goto out_not_found;
1da177e4 11907
1820180b 11908 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11909 for (i = 0; i < 256; i += 4) {
11910 u32 tmp;
1da177e4 11911
1b27777a
MC		 11912 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11913 goto out_not_found;
11914
11915 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11916 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11917 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11918 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11919 }
11920 } else {
11921 int vpd_cap;
11922
11923 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11924 for (i = 0; i < 256; i += 4) {
11925 u32 tmp, j = 0;
b9fc7dc5 11926 __le32 v;
1b27777a
MC		 11927 u16 tmp16;
11928
11929 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11930 i);
11931 while (j++ < 100) {
11932 pci_read_config_word(tp->pdev, vpd_cap +
11933 PCI_VPD_ADDR, &tmp16);
11934 if (tmp16 & 0x8000)
11935 break;
11936 msleep(1);
11937 }
f49639e6
DM		 11938 if (!(tmp16 & 0x8000))
11939 goto out_not_found;
11940
1b27777a
MC		 11941 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11942 &tmp);
b9fc7dc5
AV		 11943 v = cpu_to_le32(tmp);
11944 memcpy(&vpd_data[i], &v, 4);
1b27777a 11945 }
1da177e4
LT		 11946 }
11947
11948 /* Now parse and find the part number. */
af2c6a4a 11949 for (i = 0; i < 254; ) {
1da177e4 11950 unsigned char val = vpd_data[i];
af2c6a4a 11951 unsigned int block_end;
1da177e4
LT		 11952
11953 if (val == 0x82 || val == 0x91) {
11954 i = (i + 3 +
11955 (vpd_data[i + 1] +
11956 (vpd_data[i + 2] << 8)));
11957 continue;
11958 }
11959
11960 if (val != 0x90)
11961 goto out_not_found;
11962
11963 block_end = (i + 3 +
11964 (vpd_data[i + 1] +
11965 (vpd_data[i + 2] << 8)));
11966 i += 3;
af2c6a4a
MC		 11967
11968 if (block_end > 256)
11969 goto out_not_found;
11970
11971 while (i < (block_end - 2)) {
1da177e4
LT		 11972 if (vpd_data[i + 0] == 'P' &&
11973 vpd_data[i + 1] == 'N') {
11974 int partno_len = vpd_data[i + 2];
11975
af2c6a4a
MC		 11976 i += 3;
11977 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11978 goto out_not_found;
11979
11980 memcpy(tp->board_part_number,
af2c6a4a 11981 &vpd_data[i], partno_len);
1da177e4
LT		 11982
11983 /* Success. */
11984 return;
11985 }
af2c6a4a 11986 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11987 }
11988
11989 /* Part number not found. */
11990 goto out_not_found;
11991 }
11992
11993out_not_found:
b5d3772c
MC		 11994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11995 strcpy(tp->board_part_number, "BCM95906");
11996 else
11997 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11998}
11999
9c8a620e
MC		 12000static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12001{
12002 u32 val;
12003
12004 if (tg3_nvram_read_swab(tp, offset, &val) ||
12005 (val & 0xfc000000) != 0x0c000000 ||
12006 tg3_nvram_read_swab(tp, offset + 4, &val) ||
12007 val != 0)
12008 return 0;
12009
12010 return 1;
12011}
12012
dfe00d7d
MC		 12013static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12014{
12015 u32 offset, major, minor, build;
12016
12017 tp->fw_ver[0] = 's';
12018 tp->fw_ver[1] = 'b';
12019 tp->fw_ver[2] = '\0';
12020
12021 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12022 return;
12023
12024 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12025 case TG3_EEPROM_SB_REVISION_0:
12026 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12027 break;
12028 case TG3_EEPROM_SB_REVISION_2:
12029 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12030 break;
12031 case TG3_EEPROM_SB_REVISION_3:
12032 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12033 break;
12034 default:
12035 return;
12036 }
12037
12038 if (tg3_nvram_read_swab(tp, offset, &val))
12039 return;
12040
12041 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12042 TG3_EEPROM_SB_EDH_BLD_SHFT;
12043 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12044 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12045 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12046
12047 if (minor > 99 || build > 26)
12048 return;
12049
12050 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12051
12052 if (build > 0) {
12053 tp->fw_ver[8] = 'a' + build - 1;
12054 tp->fw_ver[9] = '\0';
12055 }
12056}
12057
c4e6575c
MC		 12058static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12059{
12060 u32 val, offset, start;
9c8a620e
MC		 12061 u32 ver_offset;
12062 int i, bcnt;
c4e6575c
MC		 12063
12064 if (tg3_nvram_read_swab(tp, 0, &val))
12065 return;
12066
dfe00d7d
MC		 12067 if (val != TG3_EEPROM_MAGIC) {
12068 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12069 tg3_read_sb_ver(tp, val);
12070
c4e6575c 12071 return;
dfe00d7d 12072 }
c4e6575c
MC		 12073
12074 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
12075 tg3_nvram_read_swab(tp, 0x4, &start))
12076 return;
12077
12078 offset = tg3_nvram_logical_addr(tp, offset);
9c8a620e
MC		 12079
12080 if (!tg3_fw_img_is_valid(tp, offset) ||
12081 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
c4e6575c
MC		 12082 return;
12083
9c8a620e
MC		 12084 offset = offset + ver_offset - start;
12085 for (i = 0; i < 16; i += 4) {
b9fc7dc5
AV		 12086 __le32 v;
12087 if (tg3_nvram_read_le(tp, offset + i, &v))
9c8a620e
MC		 12088 return;
12089
b9fc7dc5 12090 memcpy(tp->fw_ver + i, &v, 4);
9c8a620e 12091 }
c4e6575c 12092
9c8a620e 12093 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
84af67fd 12094 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
9c8a620e
MC		 12095 return;
12096
12097 for (offset = TG3_NVM_DIR_START;
12098 offset < TG3_NVM_DIR_END;
12099 offset += TG3_NVM_DIRENT_SIZE) {
12100 if (tg3_nvram_read_swab(tp, offset, &val))
c4e6575c
MC		 12101 return;
12102
9c8a620e
MC		 12103 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12104 break;
12105 }
12106
12107 if (offset == TG3_NVM_DIR_END)
12108 return;
12109
12110 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12111 start = 0x08000000;
12112 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
12113 return;
12114
12115 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
12116 !tg3_fw_img_is_valid(tp, offset) ||
12117 tg3_nvram_read_swab(tp, offset + 8, &val))
12118 return;
12119
12120 offset += val - start;
12121
12122 bcnt = strlen(tp->fw_ver);
12123
12124 tp->fw_ver[bcnt++] = ',';
12125 tp->fw_ver[bcnt++] = ' ';
12126
12127 for (i = 0; i < 4; i++) {
b9fc7dc5
AV		 12128 __le32 v;
12129 if (tg3_nvram_read_le(tp, offset, &v))
c4e6575c
MC		 12130 return;
12131
b9fc7dc5 12132 offset += sizeof(v);
c4e6575c 12133
b9fc7dc5
AV		 12134 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
12135 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
9c8a620e 12136 break;
c4e6575c 12137 }
9c8a620e 12138
b9fc7dc5
AV		 12139 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
12140 bcnt += sizeof(v);
c4e6575c 12141 }
9c8a620e
MC		 12142
12143 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12144}
12145
7544b097
MC		 12146static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12147
1da177e4
LT		 12148static int __devinit tg3_get_invariants(struct tg3 *tp)
12149{
12150 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12151 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12152 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12153 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12154 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12155 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12156 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12157 { },
12158 };
12159 u32 misc_ctrl_reg;
12160 u32 cacheline_sz_reg;
12161 u32 pci_state_reg, grc_misc_cfg;
12162 u32 val;
12163 u16 pci_cmd;
5e7dfd0f 12164 int err;
1da177e4 12165
1da177e4
LT		 12166 /* Force memory write invalidate off. If we leave it on,
12167 * then on 5700_BX chips we have to enable a workaround.
12168 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12169 * to match the cacheline size. The Broadcom driver have this
12170 * workaround but turns MWI off all the times so never uses
12171 * it. This seems to suggest that the workaround is insufficient.
12172 */
12173 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12174 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12175 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12176
12177 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12178 * has the register indirect write enable bit set before
12179 * we try to access any of the MMIO registers. It is also
12180 * critical that the PCI-X hw workaround situation is decided
12181 * before that as well.
12182 */
12183 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12184 &misc_ctrl_reg);
12185
12186 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12187 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12189 u32 prod_id_asic_rev;
12190
12191 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12192 &prod_id_asic_rev);
321d32a0 12193 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12194 }
1da177e4 12195
ff645bec
MC		 12196 /* Wrong chip ID in 5752 A0. This code can be removed later
12197 * as A0 is not in production.
12198 */
12199 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12200 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12201
6892914f
MC		 12202 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12203 * we need to disable memory and use config. cycles
12204 * only to access all registers. The 5702/03 chips
12205 * can mistakenly decode the special cycles from the
12206 * ICH chipsets as memory write cycles, causing corruption
12207 * of register and memory space. Only certain ICH bridges
12208 * will drive special cycles with non-zero data during the
12209 * address phase which can fall within the 5703's address
12210 * range. This is not an ICH bug as the PCI spec allows
12211 * non-zero address during special cycles. However, only
12212 * these ICH bridges are known to drive non-zero addresses
12213 * during special cycles.
12214 *
12215 * Since special cycles do not cross PCI bridges, we only
12216 * enable this workaround if the 5703 is on the secondary
12217 * bus of these ICH bridges.
12218 */
12219 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12220 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12221 static struct tg3_dev_id {
12222 u32 vendor;
12223 u32 device;
12224 u32 rev;
12225 } ich_chipsets[] = {
12226 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12227 PCI_ANY_ID },
12228 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12229 PCI_ANY_ID },
12230 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12231 0xa },
12232 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12233 PCI_ANY_ID },
12234 { },
12235 };
12236 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12237 struct pci_dev *bridge = NULL;
12238
12239 while (pci_id->vendor != 0) {
12240 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12241 bridge);
12242 if (!bridge) {
12243 pci_id++;
12244 continue;
12245 }
12246 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12247 if (bridge->revision > pci_id->rev)
6892914f
MC		 12248 continue;
12249 }
12250 if (bridge->subordinate &&
12251 (bridge->subordinate->number ==
12252 tp->pdev->bus->number)) {
12253
12254 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12255 pci_dev_put(bridge);
12256 break;
12257 }
12258 }
12259 }
12260
41588ba1
MC		 12261 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12262 static struct tg3_dev_id {
12263 u32 vendor;
12264 u32 device;
12265 } bridge_chipsets[] = {
12266 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12267 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12268 { },
12269 };
12270 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12271 struct pci_dev *bridge = NULL;
12272
12273 while (pci_id->vendor != 0) {
12274 bridge = pci_get_device(pci_id->vendor,
12275 pci_id->device,
12276 bridge);
12277 if (!bridge) {
12278 pci_id++;
12279 continue;
12280 }
12281 if (bridge->subordinate &&
12282 (bridge->subordinate->number <=
12283 tp->pdev->bus->number) &&
12284 (bridge->subordinate->subordinate >=
12285 tp->pdev->bus->number)) {
12286 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12287 pci_dev_put(bridge);
12288 break;
12289 }
12290 }
12291 }
12292
4a29cc2e
MC		 12293 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12294 * DMA addresses > 40-bit. This bridge may have other additional
12295 * 57xx devices behind it in some 4-port NIC designs for example.
12296 * Any tg3 device found behind the bridge will also need the 40-bit
12297 * DMA workaround.
12298 */
a4e2b347
MC		 12299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12301 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12302 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12303 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12304 }
4a29cc2e
MC		 12305 else {
12306 struct pci_dev *bridge = NULL;
12307
12308 do {
12309 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12310 PCI_DEVICE_ID_SERVERWORKS_EPB,
12311 bridge);
12312 if (bridge && bridge->subordinate &&
12313 (bridge->subordinate->number <=
12314 tp->pdev->bus->number) &&
12315 (bridge->subordinate->subordinate >=
12316 tp->pdev->bus->number)) {
12317 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12318 pci_dev_put(bridge);
12319 break;
12320 }
12321 } while (bridge);
12322 }
4cf78e4f 12323
1da177e4
LT		 12324 /* Initialize misc host control in PCI block. */
12325 tp->misc_host_ctrl |= (misc_ctrl_reg &
12326 MISC_HOST_CTRL_CHIPREV);
12327 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12328 tp->misc_host_ctrl);
12329
12330 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12331 &cacheline_sz_reg);
12332
12333 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
12334 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
12335 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
12336 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
12337
7544b097
MC		 12338 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12339 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12340 tp->pdev_peer = tg3_find_peer(tp);
12341
321d32a0
MC		 12342 /* Intentionally exclude ASIC_REV_5906 */
12343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12345 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 12348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12349 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12350
12351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12354 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12355 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12356 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12357
1b440c56
JL		 12358 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12359 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12360 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12361
5a6f3074 12362 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12363 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12364 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12365 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12366 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12367 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12368 tp->pdev_peer == tp->pdev))
12369 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12370
321d32a0 12371 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12372 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12373 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12374 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12375 } else {
7f62ad5d 12376 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12377 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12378 ASIC_REV_5750 &&
12379 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12380 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12381 }
5a6f3074 12382 }
1da177e4 12383
f51f3562
MC		 12384 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12385 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 12386 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12387
52f4490c
MC		 12388 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12389 &pci_state_reg);
12390
5e7dfd0f
MC		 12391 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12392 if (tp->pcie_cap != 0) {
12393 u16 lnkctl;
12394
1da177e4 12395 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12396
12397 pcie_set_readrq(tp->pdev, 4096);
12398
5e7dfd0f
MC		 12399 pci_read_config_word(tp->pdev,
12400 tp->pcie_cap + PCI_EXP_LNKCTL,
12401 &lnkctl);
12402 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12404 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 12406 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
5e7dfd0f 12408 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12409 }
52f4490c 12410 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12411 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12412 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12413 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12414 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12415 if (!tp->pcix_cap) {
12416 printk(KERN_ERR PFX "Cannot find PCI-X "
12417 "capability, aborting.\n");
12418 return -EIO;
12419 }
12420
12421 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12422 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12423 }
1da177e4 12424
399de50b
MC		 12425 /* If we have an AMD 762 or VIA K8T800 chipset, write
12426 * reordering to the mailbox registers done by the host
12427 * controller can cause major troubles. We read back from
12428 * every mailbox register write to force the writes to be
12429 * posted to the chip in order.
12430 */
12431 if (pci_dev_present(write_reorder_chipsets) &&
12432 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12433 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12434
1da177e4
LT		 12435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12436 tp->pci_lat_timer < 64) {
12437 tp->pci_lat_timer = 64;
12438
12439 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
12440 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
12441 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
12442 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
12443
12444 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12445 cacheline_sz_reg);
12446 }
12447
52f4490c
MC		 12448 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12449 /* 5700 BX chips need to have their TX producer index
12450 * mailboxes written twice to workaround a bug.
12451 */
12452 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12453
52f4490c 12454 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12455 *
12456 * The workaround is to use indirect register accesses
12457 * for all chip writes not to mailbox registers.
12458 */
52f4490c 12459 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12460 u32 pm_reg;
1da177e4
LT		 12461
12462 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12463
12464 /* The chip can have it's power management PCI config
12465 * space registers clobbered due to this bug.
12466 * So explicitly force the chip into D0 here.
12467 */
9974a356
MC		 12468 pci_read_config_dword(tp->pdev,
12469 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12470 &pm_reg);
12471 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12472 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12473 pci_write_config_dword(tp->pdev,
12474 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12475 pm_reg);
12476
12477 /* Also, force SERR#/PERR# in PCI command. */
12478 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12479 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12480 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12481 }
12482 }
12483
1da177e4
LT		 12484 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12485 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12486 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12487 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12488
12489 /* Chip-specific fixup from Broadcom driver */
12490 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12491 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12492 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12493 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12494 }
12495
1ee582d8 12496 /* Default fast path register access methods */
20094930 12497 tp->read32 = tg3_read32;
1ee582d8 12498 tp->write32 = tg3_write32;
09ee929c 12499 tp->read32_mbox = tg3_read32;
20094930 12500 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12501 tp->write32_tx_mbox = tg3_write32;
12502 tp->write32_rx_mbox = tg3_write32;
12503
12504 /* Various workaround register access methods */
12505 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12506 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12507 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12508 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12509 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12510 /*
12511 * Back to back register writes can cause problems on these
12512 * chips, the workaround is to read back all reg writes
12513 * except those to mailbox regs.
12514 *
12515 * See tg3_write_indirect_reg32().
12516 */
1ee582d8 12517 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12518 }
12519
1ee582d8
MC		 12520
12521 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12522 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12523 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12524 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12525 tp->write32_rx_mbox = tg3_write_flush_reg32;
12526 }
20094930 12527
6892914f
MC		 12528 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12529 tp->read32 = tg3_read_indirect_reg32;
12530 tp->write32 = tg3_write_indirect_reg32;
12531 tp->read32_mbox = tg3_read_indirect_mbox;
12532 tp->write32_mbox = tg3_write_indirect_mbox;
12533 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12534 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12535
12536 iounmap(tp->regs);
22abe310 12537 tp->regs = NULL;
6892914f
MC		 12538
12539 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12540 pci_cmd &= ~PCI_COMMAND_MEMORY;
12541 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12542 }
b5d3772c
MC		 12543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12544 tp->read32_mbox = tg3_read32_mbox_5906;
12545 tp->write32_mbox = tg3_write32_mbox_5906;
12546 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12547 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12548 }
6892914f 12549
bbadf503
MC		 12550 if (tp->write32 == tg3_write_indirect_reg32 ||
12551 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12552 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12553 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12554 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12555
7d0c41ef 12556 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12557 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12558 * determined before calling tg3_set_power_state() so that
12559 * we know whether or not to switch out of Vaux power.
12560 * When the flag is set, it means that GPIO1 is used for eeprom
12561 * write protect and also implies that it is a LOM where GPIOs
12562 * are not used to switch power.
6aa20a22 12563 */
7d0c41ef
MC		 12564 tg3_get_eeprom_hw_cfg(tp);
12565
0d3031d9
MC		 12566 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12567 /* Allow reads and writes to the
12568 * APE register and memory space.
12569 */
12570 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12571 PCISTATE_ALLOW_APE_SHMEM_WR;
12572 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12573 pci_state_reg);
12574 }
12575
9936bcf6 12576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12577 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12580 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12581
314fba34
MC		 12582 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12583 * GPIO1 driven high will bring 5700's external PHY out of reset.
12584 * It is also used as eeprom write protect on LOMs.
12585 */
12586 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12587 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12588 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12589 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12590 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12591 /* Unused GPIO3 must be driven as output on 5752 because there
12592 * are no pull-up resistors on unused GPIO pins.
12593 */
12594 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12595 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12596
321d32a0
MC		 12597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12599 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12600
5f0c4a3c
MC		 12601 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12602 /* Turn off the debug UART. */
12603 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12604 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12605 /* Keep VMain power. */
12606 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12607 GRC_LCLCTRL_GPIO_OUTPUT0;
12608 }
12609
1da177e4 12610 /* Force the chip into D0. */
bc1c7567 12611 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12612 if (err) {
12613 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12614 pci_name(tp->pdev));
12615 return err;
12616 }
12617
12618 /* 5700 B0 chips do not support checksumming correctly due
12619 * to hardware bugs.
12620 */
12621 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12622 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12623
1da177e4
LT		 12624 /* Derive initial jumbo mode from MTU assigned in
12625 * ether_setup() via the alloc_etherdev() call
12626 */
0f893dc6 12627 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12628 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12629 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12630
12631 /* Determine WakeOnLan speed to use. */
12632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12633 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12634 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12635 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12636 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12637 } else {
12638 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12639 }
12640
12641 /* A few boards don't want Ethernet@WireSpeed phy feature */
12642 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12643 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12644 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12645 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12646 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12647 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12648 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12649
12650 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12651 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12652 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12653 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12654 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12655
321d32a0
MC		 12656 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12657 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12658 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12659 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12663 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12664 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12665 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12666 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12667 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12668 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12669 } else
c424cb24
MC		 12670 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12671 }
1da177e4 12672
b2a5c19c
MC		 12673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12674 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12675 tp->phy_otp = tg3_read_otp_phycfg(tp);
12676 if (tp->phy_otp == 0)
12677 tp->phy_otp = TG3_OTP_DEFAULT;
12678 }
12679
f51f3562 12680 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12681 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12682 else
12683 tp->mi_mode = MAC_MI_MODE_BASE;
12684
1da177e4 12685 tp->coalesce_mode = 0;
1da177e4
LT		 12686 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12687 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12688 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12689
321d32a0
MC		 12690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12692 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12693
158d7abd
MC		 12694 err = tg3_mdio_init(tp);
12695 if (err)
12696 return err;
1da177e4
LT		 12697
12698 /* Initialize data/descriptor byte/word swapping. */
12699 val = tr32(GRC_MODE);
12700 val &= GRC_MODE_HOST_STACKUP;
12701 tw32(GRC_MODE, val | tp->grc_mode);
12702
12703 tg3_switch_clocks(tp);
12704
12705 /* Clear this out for sanity. */
12706 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12707
12708 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12709 &pci_state_reg);
12710 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12711 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12712 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12713
12714 if (chiprevid == CHIPREV_ID_5701_A0 ||
12715 chiprevid == CHIPREV_ID_5701_B0 ||
12716 chiprevid == CHIPREV_ID_5701_B2 ||
12717 chiprevid == CHIPREV_ID_5701_B5) {
12718 void __iomem *sram_base;
12719
12720 /* Write some dummy words into the SRAM status block
12721 * area, see if it reads back correctly. If the return
12722 * value is bad, force enable the PCIX workaround.
12723 */
12724 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12725
12726 writel(0x00000000, sram_base);
12727 writel(0x00000000, sram_base + 4);
12728 writel(0xffffffff, sram_base + 4);
12729 if (readl(sram_base) != 0x00000000)
12730 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12731 }
12732 }
12733
12734 udelay(50);
12735 tg3_nvram_init(tp);
12736
12737 grc_misc_cfg = tr32(GRC_MISC_CFG);
12738 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12739
1da177e4
LT		 12740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12741 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12742 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12743 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12744
fac9b83e
DM		 12745 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12746 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12747 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12748 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12749 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12750 HOSTCC_MODE_CLRTICK_TXBD);
12751
12752 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12753 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12754 tp->misc_host_ctrl);
12755 }
12756
3bda1258
MC		 12757 /* Preserve the APE MAC_MODE bits */
12758 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12759 tp->mac_mode = tr32(MAC_MODE) |
12760 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12761 else
12762 tp->mac_mode = TG3_DEF_MAC_MODE;
12763
1da177e4
LT		 12764 /* these are limited to 10/100 only */
12765 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12766 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12767 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12768 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12769 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12770 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12771 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12772 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12773 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12774 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12775 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12776 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12778 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12779
12780 err = tg3_phy_probe(tp);
12781 if (err) {
12782 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12783 pci_name(tp->pdev), err);
12784 /* ... but do not return immediately ... */
b02fd9e3 12785 tg3_mdio_fini(tp);
1da177e4
LT		 12786 }
12787
12788 tg3_read_partno(tp);
c4e6575c 12789 tg3_read_fw_ver(tp);
1da177e4
LT		 12790
12791 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12792 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12793 } else {
12794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12795 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12796 else
12797 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12798 }
12799
12800 /* 5700 {AX,BX} chips have a broken status block link
12801 * change bit implementation, so we must use the
12802 * status register in those cases.
12803 */
12804 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12805 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12806 else
12807 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12808
12809 /* The led_ctrl is set during tg3_phy_probe, here we might
12810 * have to force the link status polling mechanism based
12811 * upon subsystem IDs.
12812 */
12813 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12815 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12816 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12817 TG3_FLAG_USE_LINKCHG_REG);
12818 }
12819
12820 /* For all SERDES we poll the MAC status register. */
12821 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12822 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12823 else
12824 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12825
ad829268 12826 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12827 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12828 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12829 tp->rx_offset = 0;
12830
f92905de
MC		 12831 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12832
12833 /* Increment the rx prod index on the rx std ring by at most
12834 * 8 for these chips to workaround hw errata.
12835 */
12836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12839 tp->rx_std_max_post = 8;
12840
8ed5d97e
MC		 12841 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12842 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12843 PCIE_PWR_MGMT_L1_THRESH_MSK;
12844
1da177e4
LT		 12845 return err;
12846}
12847
49b6e95f 12848#ifdef CONFIG_SPARC
1da177e4
LT		 12849static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12850{
12851 struct net_device *dev = tp->dev;
12852 struct pci_dev *pdev = tp->pdev;
49b6e95f 12853 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12854 const unsigned char *addr;
49b6e95f
DM		 12855 int len;
12856
12857 addr = of_get_property(dp, "local-mac-address", &len);
12858 if (addr && len == 6) {
12859 memcpy(dev->dev_addr, addr, 6);
12860 memcpy(dev->perm_addr, dev->dev_addr, 6);
12861 return 0;
1da177e4
LT		 12862 }
12863 return -ENODEV;
12864}
12865
12866static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12867{
12868 struct net_device *dev = tp->dev;
12869
12870 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12871 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12872 return 0;
12873}
12874#endif
12875
12876static int __devinit tg3_get_device_address(struct tg3 *tp)
12877{
12878 struct net_device *dev = tp->dev;
12879 u32 hi, lo, mac_offset;
008652b3 12880 int addr_ok = 0;
1da177e4 12881
49b6e95f 12882#ifdef CONFIG_SPARC
1da177e4
LT		 12883 if (!tg3_get_macaddr_sparc(tp))
12884 return 0;
12885#endif
12886
12887 mac_offset = 0x7c;
f49639e6 12888 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12889 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12890 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12891 mac_offset = 0xcc;
12892 if (tg3_nvram_lock(tp))
12893 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12894 else
12895 tg3_nvram_unlock(tp);
12896 }
b5d3772c
MC		 12897 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12898 mac_offset = 0x10;
1da177e4
LT		 12899
12900 /* First try to get it from MAC address mailbox. */
12901 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12902 if ((hi >> 16) == 0x484b) {
12903 dev->dev_addr[0] = (hi >> 8) & 0xff;
12904 dev->dev_addr[1] = (hi >> 0) & 0xff;
12905
12906 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12907 dev->dev_addr[2] = (lo >> 24) & 0xff;
12908 dev->dev_addr[3] = (lo >> 16) & 0xff;
12909 dev->dev_addr[4] = (lo >> 8) & 0xff;
12910 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12911
008652b3
MC		 12912 /* Some old bootcode may report a 0 MAC address in SRAM */
12913 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12914 }
12915 if (!addr_ok) {
12916 /* Next, try NVRAM. */
f49639e6 12917 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 12918 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12919 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12920 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12921 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12922 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12923 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12924 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12925 }
12926 /* Finally just fetch it out of the MAC control regs. */
12927 else {
12928 hi = tr32(MAC_ADDR_0_HIGH);
12929 lo = tr32(MAC_ADDR_0_LOW);
12930
12931 dev->dev_addr[5] = lo & 0xff;
12932 dev->dev_addr[4] = (lo >> 8) & 0xff;
12933 dev->dev_addr[3] = (lo >> 16) & 0xff;
12934 dev->dev_addr[2] = (lo >> 24) & 0xff;
12935 dev->dev_addr[1] = hi & 0xff;
12936 dev->dev_addr[0] = (hi >> 8) & 0xff;
12937 }
1da177e4
LT		 12938 }
12939
12940 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12941#ifdef CONFIG_SPARC
1da177e4
LT		 12942 if (!tg3_get_default_macaddr_sparc(tp))
12943 return 0;
12944#endif
12945 return -EINVAL;
12946 }
2ff43697 12947 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12948 return 0;
12949}
12950
59e6b434
DM		 12951#define BOUNDARY_SINGLE_CACHELINE 1
12952#define BOUNDARY_MULTI_CACHELINE 2
12953
12954static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12955{
12956 int cacheline_size;
12957 u8 byte;
12958 int goal;
12959
12960 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12961 if (byte == 0)
12962 cacheline_size = 1024;
12963 else
12964 cacheline_size = (int) byte * 4;
12965
12966 /* On 5703 and later chips, the boundary bits have no
12967 * effect.
12968 */
12969 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12970 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12971 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12972 goto out;
12973
12974#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12975 goal = BOUNDARY_MULTI_CACHELINE;
12976#else
12977#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12978 goal = BOUNDARY_SINGLE_CACHELINE;
12979#else
12980 goal = 0;
12981#endif
12982#endif
12983
12984 if (!goal)
12985 goto out;
12986
12987 /* PCI controllers on most RISC systems tend to disconnect
12988 * when a device tries to burst across a cache-line boundary.
12989 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12990 *
12991 * Unfortunately, for PCI-E there are only limited
12992 * write-side controls for this, and thus for reads
12993 * we will still get the disconnects. We'll also waste
12994 * these PCI cycles for both read and write for chips
12995 * other than 5700 and 5701 which do not implement the
12996 * boundary bits.
12997 */
12998 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12999 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13000 switch (cacheline_size) {
13001 case 16:
13002 case 32:
13003 case 64:
13004 case 128:
13005 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13006 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13007 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13008 } else {
13009 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13010 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13011 }
13012 break;
13013
13014 case 256:
13015 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13016 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13017 break;
13018
13019 default:
13020 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13021 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13022 break;
855e1111 13023 }
59e6b434
DM		 13024 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13025 switch (cacheline_size) {
13026 case 16:
13027 case 32:
13028 case 64:
13029 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13030 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13031 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13032 break;
13033 }
13034 /* fallthrough */
13035 case 128:
13036 default:
13037 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13038 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13039 break;
855e1111 13040 }
59e6b434
DM		 13041 } else {
13042 switch (cacheline_size) {
13043 case 16:
13044 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13045 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13046 DMA_RWCTRL_WRITE_BNDRY_16);
13047 break;
13048 }
13049 /* fallthrough */
13050 case 32:
13051 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13052 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13053 DMA_RWCTRL_WRITE_BNDRY_32);
13054 break;
13055 }
13056 /* fallthrough */
13057 case 64:
13058 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13059 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13060 DMA_RWCTRL_WRITE_BNDRY_64);
13061 break;
13062 }
13063 /* fallthrough */
13064 case 128:
13065 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13066 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13067 DMA_RWCTRL_WRITE_BNDRY_128);
13068 break;
13069 }
13070 /* fallthrough */
13071 case 256:
13072 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13073 DMA_RWCTRL_WRITE_BNDRY_256);
13074 break;
13075 case 512:
13076 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13077 DMA_RWCTRL_WRITE_BNDRY_512);
13078 break;
13079 case 1024:
13080 default:
13081 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13082 DMA_RWCTRL_WRITE_BNDRY_1024);
13083 break;
855e1111 13084 }
59e6b434
DM		 13085 }
13086
13087out:
13088 return val;
13089}
13090
1da177e4
LT		 13091static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13092{
13093 struct tg3_internal_buffer_desc test_desc;
13094 u32 sram_dma_descs;
13095 int i, ret;
13096
13097 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13098
13099 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13100 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13101 tw32(RDMAC_STATUS, 0);
13102 tw32(WDMAC_STATUS, 0);
13103
13104 tw32(BUFMGR_MODE, 0);
13105 tw32(FTQ_RESET, 0);
13106
13107 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13108 test_desc.addr_lo = buf_dma & 0xffffffff;
13109 test_desc.nic_mbuf = 0x00002100;
13110 test_desc.len = size;
13111
13112 /*
13113 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13114 * the *second* time the tg3 driver was getting loaded after an
13115 * initial scan.
13116 *
13117 * Broadcom tells me:
13118 * ...the DMA engine is connected to the GRC block and a DMA
13119 * reset may affect the GRC block in some unpredictable way...
13120 * The behavior of resets to individual blocks has not been tested.
13121 *
13122 * Broadcom noted the GRC reset will also reset all sub-components.
13123 */
13124 if (to_device) {
13125 test_desc.cqid_sqid = (13 << 8) | 2;
13126
13127 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13128 udelay(40);
13129 } else {
13130 test_desc.cqid_sqid = (16 << 8) | 7;
13131
13132 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13133 udelay(40);
13134 }
13135 test_desc.flags = 0x00000005;
13136
13137 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13138 u32 val;
13139
13140 val = *(((u32 *)&test_desc) + i);
13141 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13142 sram_dma_descs + (i * sizeof(u32)));
13143 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13144 }
13145 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13146
13147 if (to_device) {
13148 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13149 } else {
13150 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13151 }
13152
13153 ret = -ENODEV;
13154 for (i = 0; i < 40; i++) {
13155 u32 val;
13156
13157 if (to_device)
13158 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13159 else
13160 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13161 if ((val & 0xffff) == sram_dma_descs) {
13162 ret = 0;
13163 break;
13164 }
13165
13166 udelay(100);
13167 }
13168
13169 return ret;
13170}
13171
ded7340d 13172#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13173
13174static int __devinit tg3_test_dma(struct tg3 *tp)
13175{
13176 dma_addr_t buf_dma;
59e6b434 13177 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13178 int ret;
13179
13180 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13181 if (!buf) {
13182 ret = -ENOMEM;
13183 goto out_nofree;
13184 }
13185
13186 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13187 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13188
59e6b434 13189 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13190
13191 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13192 /* DMA read watermark not used on PCIE */
13193 tp->dma_rwctrl |= 0x00180000;
13194 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13196 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13197 tp->dma_rwctrl |= 0x003f0000;
13198 else
13199 tp->dma_rwctrl |= 0x003f000f;
13200 } else {
13201 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13203 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13204 u32 read_water = 0x7;
1da177e4 13205
4a29cc2e
MC		 13206 /* If the 5704 is behind the EPB bridge, we can
13207 * do the less restrictive ONE_DMA workaround for
13208 * better performance.
13209 */
13210 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13212 tp->dma_rwctrl |= 0x8000;
13213 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13214 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13215
49afdeb6
MC		 13216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13217 read_water = 4;
59e6b434 13218 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13219 tp->dma_rwctrl |=
13220 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13221 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13222 (1 << 23);
4cf78e4f
MC		 13223 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13224 /* 5780 always in PCIX mode */
13225 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13226 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13227 /* 5714 always in PCIX mode */
13228 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13229 } else {
13230 tp->dma_rwctrl |= 0x001b000f;
13231 }
13232 }
13233
13234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13235 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13236 tp->dma_rwctrl &= 0xfffffff0;
13237
13238 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13239 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13240 /* Remove this if it causes problems for some boards. */
13241 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13242
13243 /* On 5700/5701 chips, we need to set this bit.
13244 * Otherwise the chip will issue cacheline transactions
13245 * to streamable DMA memory with not all the byte
13246 * enables turned on. This is an error on several
13247 * RISC PCI controllers, in particular sparc64.
13248 *
13249 * On 5703/5704 chips, this bit has been reassigned
13250 * a different meaning. In particular, it is used
13251 * on those chips to enable a PCI-X workaround.
13252 */
13253 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13254 }
13255
13256 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13257
13258#if 0
13259 /* Unneeded, already done by tg3_get_invariants. */
13260 tg3_switch_clocks(tp);
13261#endif
13262
13263 ret = 0;
13264 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13265 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13266 goto out;
13267
59e6b434
DM		 13268 /* It is best to perform DMA test with maximum write burst size
13269 * to expose the 5700/5701 write DMA bug.
13270 */
13271 saved_dma_rwctrl = tp->dma_rwctrl;
13272 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13273 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13274
1da177e4
LT		 13275 while (1) {
13276 u32 *p = buf, i;
13277
13278 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13279 p[i] = i;
13280
13281 /* Send the buffer to the chip. */
13282 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13283 if (ret) {
13284 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13285 break;
13286 }
13287
13288#if 0
13289 /* validate data reached card RAM correctly. */
13290 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13291 u32 val;
13292 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13293 if (le32_to_cpu(val) != p[i]) {
13294 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13295 /* ret = -ENODEV here? */
13296 }
13297 p[i] = 0;
13298 }
13299#endif
13300 /* Now read it back. */
13301 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13302 if (ret) {
13303 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13304
13305 break;
13306 }
13307
13308 /* Verify it. */
13309 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13310 if (p[i] == i)
13311 continue;
13312
59e6b434
DM		 13313 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13314 DMA_RWCTRL_WRITE_BNDRY_16) {
13315 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13316 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13317 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13318 break;
13319 } else {
13320 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13321 ret = -ENODEV;
13322 goto out;
13323 }
13324 }
13325
13326 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13327 /* Success. */
13328 ret = 0;
13329 break;
13330 }
13331 }
59e6b434
DM		 13332 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13333 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13334 static struct pci_device_id dma_wait_state_chipsets[] = {
13335 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13336 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13337 { },
13338 };
13339
59e6b434 13340 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13341 * now look for chipsets that are known to expose the
13342 * DMA bug without failing the test.
59e6b434 13343 */
6d1cfbab
MC		 13344 if (pci_dev_present(dma_wait_state_chipsets)) {
13345 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13346 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13347 }
13348 else
13349 /* Safe to use the calculated DMA boundary. */
13350 tp->dma_rwctrl = saved_dma_rwctrl;
13351
59e6b434
DM		 13352 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13353 }
1da177e4
LT		 13354
13355out:
13356 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13357out_nofree:
13358 return ret;
13359}
13360
13361static void __devinit tg3_init_link_config(struct tg3 *tp)
13362{
13363 tp->link_config.advertising =
13364 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13365 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13366 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13367 ADVERTISED_Autoneg | ADVERTISED_MII);
13368 tp->link_config.speed = SPEED_INVALID;
13369 tp->link_config.duplex = DUPLEX_INVALID;
13370 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13371 tp->link_config.active_speed = SPEED_INVALID;
13372 tp->link_config.active_duplex = DUPLEX_INVALID;
13373 tp->link_config.phy_is_low_power = 0;
13374 tp->link_config.orig_speed = SPEED_INVALID;
13375 tp->link_config.orig_duplex = DUPLEX_INVALID;
13376 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13377}
13378
13379static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13380{
fdfec172
MC		 13381 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13382 tp->bufmgr_config.mbuf_read_dma_low_water =
13383 DEFAULT_MB_RDMA_LOW_WATER_5705;
13384 tp->bufmgr_config.mbuf_mac_rx_low_water =
13385 DEFAULT_MB_MACRX_LOW_WATER_5705;
13386 tp->bufmgr_config.mbuf_high_water =
13387 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13389 tp->bufmgr_config.mbuf_mac_rx_low_water =
13390 DEFAULT_MB_MACRX_LOW_WATER_5906;
13391 tp->bufmgr_config.mbuf_high_water =
13392 DEFAULT_MB_HIGH_WATER_5906;
13393 }
fdfec172
MC		 13394
13395 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13396 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13397 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13398 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13399 tp->bufmgr_config.mbuf_high_water_jumbo =
13400 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13401 } else {
13402 tp->bufmgr_config.mbuf_read_dma_low_water =
13403 DEFAULT_MB_RDMA_LOW_WATER;
13404 tp->bufmgr_config.mbuf_mac_rx_low_water =
13405 DEFAULT_MB_MACRX_LOW_WATER;
13406 tp->bufmgr_config.mbuf_high_water =
13407 DEFAULT_MB_HIGH_WATER;
13408
13409 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13410 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13411 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13412 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13413 tp->bufmgr_config.mbuf_high_water_jumbo =
13414 DEFAULT_MB_HIGH_WATER_JUMBO;
13415 }
1da177e4
LT		 13416
13417 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13418 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13419}
13420
13421static char * __devinit tg3_phy_string(struct tg3 *tp)
13422{
13423 switch (tp->phy_id & PHY_ID_MASK) {
13424 case PHY_ID_BCM5400: return "5400";
13425 case PHY_ID_BCM5401: return "5401";
13426 case PHY_ID_BCM5411: return "5411";
13427 case PHY_ID_BCM5701: return "5701";
13428 case PHY_ID_BCM5703: return "5703";
13429 case PHY_ID_BCM5704: return "5704";
13430 case PHY_ID_BCM5705: return "5705";
13431 case PHY_ID_BCM5750: return "5750";
85e94ced 13432 case PHY_ID_BCM5752: return "5752";
a4e2b347 13433 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13434 case PHY_ID_BCM5780: return "5780";
af36e6b6 13435 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13436 case PHY_ID_BCM5787: return "5787";
d30cdd28 13437 case PHY_ID_BCM5784: return "5784";
126a3368 13438 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13439 case PHY_ID_BCM5906: return "5906";
9936bcf6 13440 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13441 case PHY_ID_BCM8002: return "8002/serdes";
13442 case 0: return "serdes";
13443 default: return "unknown";
855e1111 13444 }
1da177e4
LT		 13445}
13446
f9804ddb
MC		 13447static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13448{
13449 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13450 strcpy(str, "PCI Express");
13451 return str;
13452 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13453 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13454
13455 strcpy(str, "PCIX:");
13456
13457 if ((clock_ctrl == 7) ||
13458 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13459 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13460 strcat(str, "133MHz");
13461 else if (clock_ctrl == 0)
13462 strcat(str, "33MHz");
13463 else if (clock_ctrl == 2)
13464 strcat(str, "50MHz");
13465 else if (clock_ctrl == 4)
13466 strcat(str, "66MHz");
13467 else if (clock_ctrl == 6)
13468 strcat(str, "100MHz");
f9804ddb
MC		 13469 } else {
13470 strcpy(str, "PCI:");
13471 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13472 strcat(str, "66MHz");
13473 else
13474 strcat(str, "33MHz");
13475 }
13476 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13477 strcat(str, ":32-bit");
13478 else
13479 strcat(str, ":64-bit");
13480 return str;
13481}
13482
8c2dc7e1 13483static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13484{
13485 struct pci_dev *peer;
13486 unsigned int func, devnr = tp->pdev->devfn & ~7;
13487
13488 for (func = 0; func < 8; func++) {
13489 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13490 if (peer && peer != tp->pdev)
13491 break;
13492 pci_dev_put(peer);
13493 }
16fe9d74
MC		 13494 /* 5704 can be configured in single-port mode, set peer to
13495 * tp->pdev in that case.
13496 */
13497 if (!peer) {
13498 peer = tp->pdev;
13499 return peer;
13500 }
1da177e4
LT		 13501
13502 /*
13503 * We don't need to keep the refcount elevated; there's no way
13504 * to remove one half of this device without removing the other
13505 */
13506 pci_dev_put(peer);
13507
13508 return peer;
13509}
13510
15f9850d
DM		 13511static void __devinit tg3_init_coal(struct tg3 *tp)
13512{
13513 struct ethtool_coalesce *ec = &tp->coal;
13514
13515 memset(ec, 0, sizeof(*ec));
13516 ec->cmd = ETHTOOL_GCOALESCE;
13517 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13518 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13519 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13520 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13521 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13522 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13523 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13524 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13525 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13526
13527 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13528 HOSTCC_MODE_CLRTICK_TXBD)) {
13529 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13530 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13531 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13532 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13533 }
d244c892
MC		 13534
13535 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13536 ec->rx_coalesce_usecs_irq = 0;
13537 ec->tx_coalesce_usecs_irq = 0;
13538 ec->stats_block_coalesce_usecs = 0;
13539 }
15f9850d
DM		 13540}
13541
7c7d64b8
SH		 13542static const struct net_device_ops tg3_netdev_ops = {
13543 .ndo_open = tg3_open,
13544 .ndo_stop = tg3_close,
00829823
SH		 13545 .ndo_start_xmit = tg3_start_xmit,
13546 .ndo_get_stats = tg3_get_stats,
13547 .ndo_validate_addr = eth_validate_addr,
13548 .ndo_set_multicast_list = tg3_set_rx_mode,
13549 .ndo_set_mac_address = tg3_set_mac_addr,
13550 .ndo_do_ioctl = tg3_ioctl,
13551 .ndo_tx_timeout = tg3_tx_timeout,
13552 .ndo_change_mtu = tg3_change_mtu,
13553#if TG3_VLAN_TAG_USED
13554 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13555#endif
13556#ifdef CONFIG_NET_POLL_CONTROLLER
13557 .ndo_poll_controller = tg3_poll_controller,
13558#endif
13559};
13560
13561static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13562 .ndo_open = tg3_open,
13563 .ndo_stop = tg3_close,
13564 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13565 .ndo_get_stats = tg3_get_stats,
13566 .ndo_validate_addr = eth_validate_addr,
13567 .ndo_set_multicast_list = tg3_set_rx_mode,
13568 .ndo_set_mac_address = tg3_set_mac_addr,
13569 .ndo_do_ioctl = tg3_ioctl,
13570 .ndo_tx_timeout = tg3_tx_timeout,
13571 .ndo_change_mtu = tg3_change_mtu,
13572#if TG3_VLAN_TAG_USED
13573 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13574#endif
13575#ifdef CONFIG_NET_POLL_CONTROLLER
13576 .ndo_poll_controller = tg3_poll_controller,
13577#endif
13578};
13579
1da177e4
LT		 13580static int __devinit tg3_init_one(struct pci_dev *pdev,
13581 const struct pci_device_id *ent)
13582{
13583 static int tg3_version_printed = 0;
1da177e4
LT		 13584 struct net_device *dev;
13585 struct tg3 *tp;
d6645372 13586 int err, pm_cap;
f9804ddb 13587 char str[40];
72f2afb8 13588 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13589
13590 if (tg3_version_printed++ == 0)
13591 printk(KERN_INFO "%s", version);
13592
13593 err = pci_enable_device(pdev);
13594 if (err) {
13595 printk(KERN_ERR PFX "Cannot enable PCI device, "
13596 "aborting.\n");
13597 return err;
13598 }
13599
1da177e4
LT		 13600 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13601 if (err) {
13602 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13603 "aborting.\n");
13604 goto err_out_disable_pdev;
13605 }
13606
13607 pci_set_master(pdev);
13608
13609 /* Find power-management capability. */
13610 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13611 if (pm_cap == 0) {
13612 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13613 "aborting.\n");
13614 err = -EIO;
13615 goto err_out_free_res;
13616 }
13617
1da177e4
LT		 13618 dev = alloc_etherdev(sizeof(*tp));
13619 if (!dev) {
13620 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13621 err = -ENOMEM;
13622 goto err_out_free_res;
13623 }
13624
1da177e4
LT		 13625 SET_NETDEV_DEV(dev, &pdev->dev);
13626
1da177e4
LT		 13627#if TG3_VLAN_TAG_USED
13628 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13629#endif
13630
13631 tp = netdev_priv(dev);
13632 tp->pdev = pdev;
13633 tp->dev = dev;
13634 tp->pm_cap = pm_cap;
1da177e4
LT		 13635 tp->rx_mode = TG3_DEF_RX_MODE;
13636 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13637
1da177e4
LT		 13638 if (tg3_debug > 0)
13639 tp->msg_enable = tg3_debug;
13640 else
13641 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13642
13643 /* The word/byte swap controls here control register access byte
13644 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13645 * setting below.
13646 */
13647 tp->misc_host_ctrl =
13648 MISC_HOST_CTRL_MASK_PCI_INT |
13649 MISC_HOST_CTRL_WORD_SWAP |
13650 MISC_HOST_CTRL_INDIR_ACCESS |
13651 MISC_HOST_CTRL_PCISTATE_RW;
13652
13653 /* The NONFRM (non-frame) byte/word swap controls take effect
13654 * on descriptor entries, anything which isn't packet data.
13655 *
13656 * The StrongARM chips on the board (one for tx, one for rx)
13657 * are running in big-endian mode.
13658 */
13659 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13660 GRC_MODE_WSWAP_NONFRM_DATA);
13661#ifdef __BIG_ENDIAN
13662 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13663#endif
13664 spin_lock_init(&tp->lock);
1da177e4 13665 spin_lock_init(&tp->indirect_lock);
c4028958 13666 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13667
d5fe488a 13668 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13669 if (!tp->regs) {
1da177e4
LT		 13670 printk(KERN_ERR PFX "Cannot map device registers, "
13671 "aborting.\n");
13672 err = -ENOMEM;
13673 goto err_out_free_dev;
13674 }
13675
13676 tg3_init_link_config(tp);
13677
1da177e4
LT		 13678 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13679 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13680 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13681
bea3348e 13682 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13683 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13684 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13685 dev->irq = pdev->irq;
1da177e4
LT		 13686
13687 err = tg3_get_invariants(tp);
13688 if (err) {
13689 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13690 "aborting.\n");
13691 goto err_out_iounmap;
13692 }
13693
321d32a0 13694 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13696 dev->netdev_ops = &tg3_netdev_ops;
13697 else
13698 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13699
13700
4a29cc2e
MC		 13701 /* The EPB bridge inside 5714, 5715, and 5780 and any
13702 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13703 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13704 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13705 * do DMA address check in tg3_start_xmit().
13706 */
4a29cc2e
MC		 13707 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13708 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13709 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 13710 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13711#ifdef CONFIG_HIGHMEM
13712 dma_mask = DMA_64BIT_MASK;
13713#endif
4a29cc2e 13714 } else
72f2afb8
MC		 13715 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13716
13717 /* Configure DMA attributes. */
13718 if (dma_mask > DMA_32BIT_MASK) {
13719 err = pci_set_dma_mask(pdev, dma_mask);
13720 if (!err) {
13721 dev->features |= NETIF_F_HIGHDMA;
13722 err = pci_set_consistent_dma_mask(pdev,
13723 persist_dma_mask);
13724 if (err < 0) {
13725 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13726 "DMA for consistent allocations\n");
13727 goto err_out_iounmap;
13728 }
13729 }
13730 }
13731 if (err || dma_mask == DMA_32BIT_MASK) {
13732 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13733 if (err) {
13734 printk(KERN_ERR PFX "No usable DMA configuration, "
13735 "aborting.\n");
13736 goto err_out_iounmap;
13737 }
13738 }
13739
fdfec172 13740 tg3_init_bufmgr_config(tp);
1da177e4 13741
1da177e4
LT		 13742 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13743 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13744 }
13745 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13746 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13747 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13748 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13749 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13750 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13751 } else {
7f62ad5d 13752 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
1da177e4
LT		 13753 }
13754
4e3a7aaa
MC		 13755 /* TSO is on by default on chips that support hardware TSO.
13756 * Firmware TSO on older chips gives lower performance, so it
13757 * is off by default, but can be enabled using ethtool.
13758 */
b0026624 13759 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 13760 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 13761 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13762 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624 13763 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13765 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13766 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13767 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13768 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13769 dev->features |= NETIF_F_TSO_ECN;
b0026624 13770 }
1da177e4 13771
1da177e4
LT		 13772
13773 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13774 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13775 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13776 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13777 tp->rx_pending = 63;
13778 }
13779
1da177e4
LT		 13780 err = tg3_get_device_address(tp);
13781 if (err) {
13782 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13783 "aborting.\n");
13784 goto err_out_iounmap;
13785 }
13786
c88864df 13787 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13788 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13789 if (!tp->aperegs) {
c88864df
MC		 13790 printk(KERN_ERR PFX "Cannot map APE registers, "
13791 "aborting.\n");
13792 err = -ENOMEM;
13793 goto err_out_iounmap;
13794 }
13795
13796 tg3_ape_lock_init(tp);
13797 }
13798
1da177e4
LT		 13799 /*
13800 * Reset chip in case UNDI or EFI driver did not shutdown
13801 * DMA self test will enable WDMAC and we'll see (spurious)
13802 * pending DMA on the PCI bus at that point.
13803 */
13804 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13805 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13806 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13807 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13808 }
13809
13810 err = tg3_test_dma(tp);
13811 if (err) {
13812 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13813 goto err_out_apeunmap;
1da177e4
LT		 13814 }
13815
13816 /* Tigon3 can do ipv4 only... and some chips have buggy
13817 * checksumming.
13818 */
13819 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
d212f87b 13820 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
321d32a0 13821 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
d212f87b
SH		 13822 dev->features |= NETIF_F_IPV6_CSUM;
13823
1da177e4
LT		 13824 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13825 } else
13826 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13827
1da177e4
LT		 13828 /* flow control autonegotiation is default behavior */
13829 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13830 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13831
15f9850d
DM		 13832 tg3_init_coal(tp);
13833
c49a1561
MC		 13834 pci_set_drvdata(pdev, dev);
13835
1da177e4
LT		 13836 err = register_netdev(dev);
13837 if (err) {
13838 printk(KERN_ERR PFX "Cannot register net device, "
13839 "aborting.\n");
0d3031d9 13840 goto err_out_apeunmap;
1da177e4
LT		 13841 }
13842
df59c940 13843 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13844 dev->name,
13845 tp->board_part_number,
13846 tp->pci_chip_rev_id,
f9804ddb 13847 tg3_bus_string(tp, str),
e174961c 13848 dev->dev_addr);
1da177e4 13849
df59c940
MC		 13850 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13851 printk(KERN_INFO
13852 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13853 tp->dev->name,
13854 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13855 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13856 else
13857 printk(KERN_INFO
13858 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13859 tp->dev->name, tg3_phy_string(tp),
13860 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13861 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13862 "10/100/1000Base-T")),
13863 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13864
13865 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13866 dev->name,
13867 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13868 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13869 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13870 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13871 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13872 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13873 dev->name, tp->dma_rwctrl,
13874 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13875 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 13876
13877 return 0;
13878
0d3031d9
MC		 13879err_out_apeunmap:
13880 if (tp->aperegs) {
13881 iounmap(tp->aperegs);
13882 tp->aperegs = NULL;
13883 }
13884
1da177e4 13885err_out_iounmap:
6892914f
MC		 13886 if (tp->regs) {
13887 iounmap(tp->regs);
22abe310 13888 tp->regs = NULL;
6892914f 13889 }
1da177e4
LT		 13890
13891err_out_free_dev:
13892 free_netdev(dev);
13893
13894err_out_free_res:
13895 pci_release_regions(pdev);
13896
13897err_out_disable_pdev:
13898 pci_disable_device(pdev);
13899 pci_set_drvdata(pdev, NULL);
13900 return err;
13901}
13902
13903static void __devexit tg3_remove_one(struct pci_dev *pdev)
13904{
13905 struct net_device *dev = pci_get_drvdata(pdev);
13906
13907 if (dev) {
13908 struct tg3 *tp = netdev_priv(dev);
13909
7faa006f 13910 flush_scheduled_work();
158d7abd 13911
b02fd9e3
MC		 13912 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13913 tg3_phy_fini(tp);
158d7abd 13914 tg3_mdio_fini(tp);
b02fd9e3 13915 }
158d7abd 13916
1da177e4 13917 unregister_netdev(dev);
0d3031d9
MC		 13918 if (tp->aperegs) {
13919 iounmap(tp->aperegs);
13920 tp->aperegs = NULL;
13921 }
6892914f
MC		 13922 if (tp->regs) {
13923 iounmap(tp->regs);
22abe310 13924 tp->regs = NULL;
6892914f 13925 }
1da177e4
LT		 13926 free_netdev(dev);
13927 pci_release_regions(pdev);
13928 pci_disable_device(pdev);
13929 pci_set_drvdata(pdev, NULL);
13930 }
13931}
13932
13933static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13934{
13935 struct net_device *dev = pci_get_drvdata(pdev);
13936 struct tg3 *tp = netdev_priv(dev);
12dac075 13937 pci_power_t target_state;
1da177e4
LT		 13938 int err;
13939
3e0c95fd
MC		 13940 /* PCI register 4 needs to be saved whether netif_running() or not.
13941 * MSI address and data need to be saved if using MSI and
13942 * netif_running().
13943 */
13944 pci_save_state(pdev);
13945
1da177e4
LT		 13946 if (!netif_running(dev))
13947 return 0;
13948
7faa006f 13949 flush_scheduled_work();
b02fd9e3 13950 tg3_phy_stop(tp);
1da177e4
LT		 13951 tg3_netif_stop(tp);
13952
13953 del_timer_sync(&tp->timer);
13954
f47c11ee 13955 tg3_full_lock(tp, 1);
1da177e4 13956 tg3_disable_ints(tp);
f47c11ee 13957 tg3_full_unlock(tp);
1da177e4
LT		 13958
13959 netif_device_detach(dev);
13960
f47c11ee 13961 tg3_full_lock(tp, 0);
944d980e 13962 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13963 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13964 tg3_full_unlock(tp);
1da177e4 13965
12dac075
RW		 13966 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13967
13968 err = tg3_set_power_state(tp, target_state);
1da177e4 13969 if (err) {
b02fd9e3
MC		 13970 int err2;
13971
f47c11ee 13972 tg3_full_lock(tp, 0);
1da177e4 13973
6a9eba15 13974 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13975 err2 = tg3_restart_hw(tp, 1);
13976 if (err2)
b9ec6c1b 13977 goto out;
1da177e4
LT		 13978
13979 tp->timer.expires = jiffies + tp->timer_offset;
13980 add_timer(&tp->timer);
13981
13982 netif_device_attach(dev);
13983 tg3_netif_start(tp);
13984
b9ec6c1b 13985out:
f47c11ee 13986 tg3_full_unlock(tp);
b02fd9e3
MC		 13987
13988 if (!err2)
13989 tg3_phy_start(tp);
1da177e4
LT		 13990 }
13991
13992 return err;
13993}
13994
13995static int tg3_resume(struct pci_dev *pdev)
13996{
13997 struct net_device *dev = pci_get_drvdata(pdev);
13998 struct tg3 *tp = netdev_priv(dev);
13999 int err;
14000
3e0c95fd
MC		 14001 pci_restore_state(tp->pdev);
14002
1da177e4
LT		 14003 if (!netif_running(dev))
14004 return 0;
14005
bc1c7567 14006 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14007 if (err)
14008 return err;
14009
14010 netif_device_attach(dev);
14011
f47c11ee 14012 tg3_full_lock(tp, 0);
1da177e4 14013
6a9eba15 14014 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14015 err = tg3_restart_hw(tp, 1);
14016 if (err)
14017 goto out;
1da177e4
LT		 14018
14019 tp->timer.expires = jiffies + tp->timer_offset;
14020 add_timer(&tp->timer);
14021
1da177e4
LT		 14022 tg3_netif_start(tp);
14023
b9ec6c1b 14024out:
f47c11ee 14025 tg3_full_unlock(tp);
1da177e4 14026
b02fd9e3
MC		 14027 if (!err)
14028 tg3_phy_start(tp);
14029
b9ec6c1b 14030 return err;
1da177e4
LT		 14031}
14032
14033static struct pci_driver tg3_driver = {
14034 .name = DRV_MODULE_NAME,
14035 .id_table = tg3_pci_tbl,
14036 .probe = tg3_init_one,
14037 .remove = __devexit_p(tg3_remove_one),
14038 .suspend = tg3_suspend,
14039 .resume = tg3_resume
14040};
14041
14042static int __init tg3_init(void)
14043{
29917620 14044 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14045}
14046
14047static void __exit tg3_cleanup(void)
14048{
14049 pci_unregister_driver(&tg3_driver);
14050}
14051
14052module_init(tg3_init);
14053module_exit(tg3_cleanup);
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