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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
0d2a5068
MC		 71#define DRV_MODULE_VERSION "3.98"
72#define DRV_MODULE_RELDATE "February 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
1da177e4
LT		 235};
236
237MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
50da859d 239static const struct {
1da177e4
LT		 240 const char string[ETH_GSTRING_LEN];
241} ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318};
319
50da859d 320static const struct {
4cafd3f5
MC		 321 const char string[ETH_GSTRING_LEN];
322} ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329};
330
b401e9e2
MC		 331static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332{
333 writel(val, tp->regs + off);
334}
335
336static u32 tg3_read32(struct tg3 *tp, u32 off)
337{
6aa20a22 338 return (readl(tp->regs + off));
b401e9e2
MC		 339}
340
0d3031d9
MC		 341static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342{
343 writel(val, tp->aperegs + off);
344}
345
346static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347{
348 return (readl(tp->aperegs + off));
349}
350
1da177e4
LT		 351static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352{
6892914f
MC		 353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 359}
360
361static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
1da177e4
LT		 365}
366
6892914f 367static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 368{
6892914f
MC		 369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377}
378
379static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
1da177e4 392 }
6892914f
MC		 393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407}
408
409static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410{
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419}
420
b401e9e2
MC		 421/* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 427{
b401e9e2
MC		 428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
1da177e4
LT		 444}
445
09ee929c
MC		 446static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447{
448 tp->write32_mbox(tp, off, val);
6892914f
MC		 449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
09ee929c
MC		 452}
453
20094930 454static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 455{
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462}
463
b5d3772c
MC		 464static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465{
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467}
468
469static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472}
473
20094930 474#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 475#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 476#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 478#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 479
480#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 481#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 483#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 484
485static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486{
6892914f
MC		 487 unsigned long flags;
488
b5d3772c
MC		 489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
6892914f 493 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 497
bbadf503
MC		 498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 508}
509
1da177e4
LT		 510static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
6892914f 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 535}
536
0d3031d9
MC		 537static void tg3_ape_lock_init(struct tg3 *tp)
538{
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545}
546
547static int tg3_ape_lock(struct tg3 *tp, int locknum)
548{
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
77b483f1 557 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585}
586
587static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588{
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
77b483f1 595 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604}
605
1da177e4
LT		 606static void tg3_disable_ints(struct tg3 *tp)
607{
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 611}
612
613static inline void tg3_cond_int(struct tg3 *tp)
614{
38f3843e
MC		 615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 621}
622
623static void tg3_enable_ints(struct tg3 *tp)
624{
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
fcfa0a32
MC		 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
1da177e4
LT		 635 tg3_cond_int(tp);
636}
637
04237ddd
MC		 638static inline unsigned int tg3_has_work(struct tg3 *tp)
639{
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656}
657
1da177e4 658/* tg3_restart_ints
04237ddd
MC		 659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
6aa20a22 661 * which reenables interrupts
1da177e4
LT		 662 */
663static void tg3_restart_ints(struct tg3 *tp)
664{
fac9b83e
DM		 665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
1da177e4
LT		 667 mmiowb();
668
fac9b83e
DM		 669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
04237ddd
MC		 675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 677}
678
679static inline void tg3_netif_stop(struct tg3 *tp)
680{
bbe832c0 681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 682 napi_disable(&tp->napi);
1da177e4
LT		 683 netif_tx_disable(tp->dev);
684}
685
686static inline void tg3_netif_start(struct tg3 *tp)
687{
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
bea3348e 693 napi_enable(&tp->napi);
f47c11ee
DM		 694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
1da177e4
LT		 696}
697
698static void tg3_switch_clocks(struct tg3 *tp)
699{
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
795d01c5
MC		 703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 705 return;
706
1da177e4
LT		 707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
1da177e4 726 }
b401e9e2 727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 728}
729
730#define PHY_BUSY_LOOPS 5000
731
732static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733{
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 751
1da177e4
LT		 752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779}
780
781static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782{
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
b5d3772c
MC		 787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
1da177e4
LT		 791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 803
1da177e4
LT		 804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828}
829
95e2869a
MC		 830static int tg3_bmcr_reset(struct tg3 *tp)
831{
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
d4675b52 855 if (limit < 0)
95e2869a
MC		 856 return -EBUSY;
857
858 return 0;
859}
860
158d7abd
MC		 861static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862{
3d16543d 863 struct tg3 *tp = bp->priv;
158d7abd
MC		 864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873}
874
875static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876{
3d16543d 877 struct tg3 *tp = bp->priv;
158d7abd
MC		 878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886}
887
888static int tg3_mdio_reset(struct mii_bus *bp)
889{
890 return 0;
891}
892
9c61d6bc 893static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 894{
895 u32 val;
fcb389df 896 struct phy_device *phydev;
a9daf367 897
fcb389df
MC		 898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
a9daf367 913 return;
fcb389df
MC		 914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
a9daf367
MC		 946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
fcb389df 954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966}
967
158d7abd
MC		 968static void tg3_mdio_start(struct tg3 *tp)
969{
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 971 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 973 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
a9daf367 979
9c61d6bc
MC		 980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
158d7abd
MC		 983}
984
985static void tg3_mdio_stop(struct tg3 *tp)
986{
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 988 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 990 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 991 }
992}
993
994static int tg3_mdio_init(struct tg3 *tp)
995{
996 int i;
997 u32 reg;
a9daf367 998 struct phy_device *phydev;
158d7abd
MC		 999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
298cf9be
LB		 1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
158d7abd 1009
298cf9be
LB		 1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1022 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
298cf9be 1032 i = mdiobus_register(tp->mdio_bus);
a9daf367 1033 if (i) {
158d7abd
MC		 1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
9c61d6bc 1036 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1037 return i;
1038 }
158d7abd 1039
298cf9be 1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1041
9c61d6bc
MC		 1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
a9daf367 1053 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1063 break;
fcb389df 1064 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
9c61d6bc
MC		 1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
a9daf367
MC		 1074
1075 return 0;
158d7abd
MC		 1076}
1077
1078static void tg3_mdio_fini(struct tg3 *tp)
1079{
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086}
1087
4ba526ce
MC		 1088/* tp->lock is held. */
1089static inline void tg3_generate_fw_event(struct tg3 *tp)
1090{
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098}
1099
1100#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
95e2869a
MC		 1102/* tp->lock is held. */
1103static void tg3_wait_for_event_ack(struct tg3 *tp)
1104{
1105 int i;
4ba526ce
MC		 1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1121
4ba526ce 1122 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
4ba526ce 1125 udelay(8);
95e2869a
MC		 1126 }
1127}
1128
1129/* tp->lock is held. */
1130static void tg3_ump_link_report(struct tg3 *tp)
1131{
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
4ba526ce 1174 tg3_generate_fw_event(tp);
95e2869a
MC		 1175}
1176
1177static void tg3_link_report(struct tg3 *tp)
1178{
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
e18ce346 1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1198 "on" : "off",
e18ce346 1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203}
1204
1205static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206{
1207 u16 miireg;
1208
e18ce346 1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1210 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1211 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1212 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1213 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219}
1220
1221static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
95e2869a
MC		 1237static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238{
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1246 cap = FLOW_CTRL_RX;
95e2869a
MC		 1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1253 cap = FLOW_CTRL_TX;
95e2869a
MC		 1254 }
1255
1256 return cap;
1257}
1258
f51f3562 1259static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1260{
b02fd9e3 1261 u8 autoneg;
f51f3562 1262 u8 flowctrl = 0;
95e2869a
MC		 1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
b02fd9e3 1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1275 else
bc02ff95 1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1277 } else
1278 flowctrl = tp->link_config.flowctrl;
95e2869a 1279
f51f3562 1280 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1281
e18ce346 1282 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
f51f3562 1287 if (old_rx_mode != tp->rx_mode)
95e2869a 1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1289
e18ce346 1290 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
f51f3562 1295 if (old_tx_mode != tp->tx_mode)
95e2869a 1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1297}
1298
b02fd9e3
MC		 1299static void tg3_adjust_link(struct net_device *dev)
1300{
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
298cf9be 1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
fcb389df
MC		 1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
b02fd9e3
MC		 1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378}
1379
1380static int tg3_phy_init(struct tg3 *tp)
1381{
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
298cf9be 1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1391
1392 /* Attach the MAC to the PHY. */
fb28ad35 1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1394 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
b02fd9e3 1400 /* Mask with MAC supported features. */
9c61d6bc
MC		 1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
9c61d6bc
MC		 1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1422
1423 phydev->advertising = phydev->supported;
1424
b02fd9e3
MC		 1425 return 0;
1426}
1427
1428static void tg3_phy_start(struct tg3 *tp)
1429{
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
298cf9be 1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448}
1449
1450static void tg3_phy_stop(struct tg3 *tp)
1451{
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
298cf9be 1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1456}
1457
1458static void tg3_phy_fini(struct tg3 *tp)
1459{
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464}
1465
b2a5c19c
MC		 1466static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467{
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470}
1471
6833c043
MC		 1472static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473{
1474 u32 reg;
1475
a6435f3a
MC		 1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6833c043
MC		 1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499}
1500
9ef8ca99
MC		 1501static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502{
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537}
1538
1da177e4
LT		 1539static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540{
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550}
1551
b2a5c19c
MC		 1552static void tg3_phy_apply_otp(struct tg3 *tp)
1553{
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593}
1594
1da177e4
LT		 1595static int tg3_wait_macro_done(struct tg3 *tp)
1596{
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
d4675b52 1607 if (limit < 0)
1da177e4
LT		 1608 return -EBUSY;
1609
1610 return 0;
1611}
1612
1613static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614{
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680{
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697}
1698
1699static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700{
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773}
1774
1775/* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778static int tg3_phy_reset(struct tg3 *tp)
1779{
b2a5c19c 1780 u32 cpmuctrl;
1da177e4
LT		 1781 u32 phy_status;
1782 int err;
1783
60189ddf
MC		 1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1da177e4
LT		 1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
c8e1e82b
MC		 1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1da177e4
LT		 1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
b2a5c19c
MC		 1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1da177e4
LT		 1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
b2a5c19c
MC		 1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
bcb37f6c
MC		 1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
b2a5c19c
MC		 1845 tg3_phy_apply_otp(tp);
1846
6833c043
MC		 1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1da177e4
LT		 1852out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
c424cb24
MC		 1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1da177e4
LT		 1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
0f893dc6 1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
715116a1 1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1914 }
1915
9ef8ca99 1916 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919}
1920
1921static void tg3_frob_aux_power(struct tg3 *tp)
1922{
1923 struct tg3 *tp_peer = tp;
1924
9d26e213 1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1926 return;
1927
8c2dc7e1
MC		 1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1933 /* remove_one() may have been run on the peer. */
8c2dc7e1 1934 if (!dev_peer)
bc1c7567
MC		 1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1938 }
1939
1da177e4 1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
5f0c4a3c
MC		 1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956 GRC_LCLCTRL_GPIO_OE1 |
1957 GRC_LCLCTRL_GPIO_OE2 |
1958 GRC_LCLCTRL_GPIO_OUTPUT0 |
1959 GRC_LCLCTRL_GPIO_OUTPUT1 |
1960 tp->grc_local_ctrl;
1961 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1968 } else {
1969 u32 no_gpio2;
dc56b7d4 1970 u32 grc_local_ctrl = 0;
1da177e4
LT		 1971
1972 if (tp_peer != tp &&
1973 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974 return;
1975
dc56b7d4
MC		 1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978 ASIC_REV_5714) {
1979 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1980 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981 grc_local_ctrl, 100);
dc56b7d4
MC		 1982 }
1983
1da177e4
LT		 1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2 = tp->nic_sram_data_cfg &
1986 NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
dc56b7d4 1988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1 |
1992 GRC_LCLCTRL_GPIO_OUTPUT2;
1993 if (no_gpio2) {
1994 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995 GRC_LCLCTRL_GPIO_OUTPUT2);
1996 }
b401e9e2
MC		 1997 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998 grc_local_ctrl, 100);
1da177e4
LT		 1999
2000 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
b401e9e2
MC		 2002 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003 grc_local_ctrl, 100);
1da177e4
LT		 2004
2005 if (!no_gpio2) {
2006 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2007 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008 grc_local_ctrl, 100);
1da177e4
LT		 2009 }
2010 }
2011 } else {
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014 if (tp_peer != tp &&
2015 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016 return;
2017
b401e9e2
MC		 2018 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019 (GRC_LCLCTRL_GPIO_OE1 |
2020 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2021
b401e9e2
MC		 2022 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2024
b401e9e2
MC		 2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE1 |
2027 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2028 }
2029 }
2030}
2031
e8f3f6ca
MC		 2032static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033{
2034 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035 return 1;
2036 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037 if (speed != SPEED_10)
2038 return 1;
2039 } else if (speed == SPEED_10)
2040 return 1;
2041
2042 return 0;
2043}
2044
1da177e4
LT		 2045static int tg3_setup_phy(struct tg3 *, int);
2046
2047#define RESET_KIND_SHUTDOWN 0
2048#define RESET_KIND_INIT 1
2049#define RESET_KIND_SUSPEND 2
2050
2051static void tg3_write_sig_post_reset(struct tg3 *, int);
2052static int tg3_halt_cpu(struct tg3 *, u32);
2053
0a459aac 2054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2055{
ce057f01
MC		 2056 u32 val;
2057
5129724a
MC		 2058 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063 sg_dig_ctrl |=
2064 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067 }
3f7045c1 2068 return;
5129724a 2069 }
3f7045c1 2070
60189ddf 2071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2072 tg3_bmcr_reset(tp);
2073 val = tr32(GRC_MISC_CFG);
2074 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075 udelay(40);
2076 return;
0a459aac 2077 } else if (do_low_power) {
715116a1
MC		 2078 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2080
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2086 }
3f7045c1 2087
15c3b696
MC		 2088 /* The PHY should not be powered down on some chips because
2089 * of bugs.
2090 */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095 return;
ce057f01 2096
bcb37f6c
MC		 2097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2099 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103 }
2104
15c3b696
MC		 2105 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106}
2107
ffbcfed4
MC		 2108/* tp->lock is held. */
2109static int tg3_nvram_lock(struct tg3 *tp)
2110{
2111 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112 int i;
2113
2114 if (tp->nvram_lock_cnt == 0) {
2115 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116 for (i = 0; i < 8000; i++) {
2117 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118 break;
2119 udelay(20);
2120 }
2121 if (i == 8000) {
2122 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123 return -ENODEV;
2124 }
2125 }
2126 tp->nvram_lock_cnt++;
2127 }
2128 return 0;
2129}
2130
2131/* tp->lock is held. */
2132static void tg3_nvram_unlock(struct tg3 *tp)
2133{
2134 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135 if (tp->nvram_lock_cnt > 0)
2136 tp->nvram_lock_cnt--;
2137 if (tp->nvram_lock_cnt == 0)
2138 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139 }
2140}
2141
2142/* tp->lock is held. */
2143static void tg3_enable_nvram_access(struct tg3 *tp)
2144{
2145 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150 }
2151}
2152
2153/* tp->lock is held. */
2154static void tg3_disable_nvram_access(struct tg3 *tp)
2155{
2156 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161 }
2162}
2163
2164static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165 u32 offset, u32 *val)
2166{
2167 u32 tmp;
2168 int i;
2169
2170 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171 return -EINVAL;
2172
2173 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174 EEPROM_ADDR_DEVID_MASK |
2175 EEPROM_ADDR_READ);
2176 tw32(GRC_EEPROM_ADDR,
2177 tmp |
2178 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180 EEPROM_ADDR_ADDR_MASK) |
2181 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183 for (i = 0; i < 1000; i++) {
2184 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186 if (tmp & EEPROM_ADDR_COMPLETE)
2187 break;
2188 msleep(1);
2189 }
2190 if (!(tmp & EEPROM_ADDR_COMPLETE))
2191 return -EBUSY;
2192
62cedd11
MC		 2193 tmp = tr32(GRC_EEPROM_DATA);
2194
2195 /*
2196 * The data will always be opposite the native endian
2197 * format. Perform a blind byteswap to compensate.
2198 */
2199 *val = swab32(tmp);
2200
ffbcfed4
MC		 2201 return 0;
2202}
2203
2204#define NVRAM_CMD_TIMEOUT 10000
2205
2206static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2207{
2208 int i;
2209
2210 tw32(NVRAM_CMD, nvram_cmd);
2211 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2212 udelay(10);
2213 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2214 udelay(10);
2215 break;
2216 }
2217 }
2218
2219 if (i == NVRAM_CMD_TIMEOUT)
2220 return -EBUSY;
2221
2222 return 0;
2223}
2224
2225static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2226{
2227 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2228 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2229 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2230 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2231 (tp->nvram_jedecnum == JEDEC_ATMEL))
2232
2233 addr = ((addr / tp->nvram_pagesize) <<
2234 ATMEL_AT45DB0X1B_PAGE_POS) +
2235 (addr % tp->nvram_pagesize);
2236
2237 return addr;
2238}
2239
2240static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2241{
2242 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2243 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2244 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2245 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2246 (tp->nvram_jedecnum == JEDEC_ATMEL))
2247
2248 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2249 tp->nvram_pagesize) +
2250 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2251
2252 return addr;
2253}
2254
e4f34110
MC		 2255/* NOTE: Data read in from NVRAM is byteswapped according to
2256 * the byteswapping settings for all other register accesses.
2257 * tg3 devices are BE devices, so on a BE machine, the data
2258 * returned will be exactly as it is seen in NVRAM. On a LE
2259 * machine, the 32-bit value will be byteswapped.
2260 */
ffbcfed4
MC		 2261static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2262{
2263 int ret;
2264
2265 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2266 return tg3_nvram_read_using_eeprom(tp, offset, val);
2267
2268 offset = tg3_nvram_phys_addr(tp, offset);
2269
2270 if (offset > NVRAM_ADDR_MSK)
2271 return -EINVAL;
2272
2273 ret = tg3_nvram_lock(tp);
2274 if (ret)
2275 return ret;
2276
2277 tg3_enable_nvram_access(tp);
2278
2279 tw32(NVRAM_ADDR, offset);
2280 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2281 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2282
2283 if (ret == 0)
e4f34110 2284 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2285
2286 tg3_disable_nvram_access(tp);
2287
2288 tg3_nvram_unlock(tp);
2289
2290 return ret;
2291}
2292
a9dc529d
MC		 2293/* Ensures NVRAM data is in bytestream format. */
2294static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2295{
2296 u32 v;
a9dc529d 2297 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2298 if (!res)
a9dc529d 2299 *val = cpu_to_be32(v);
ffbcfed4
MC		 2300 return res;
2301}
2302
3f007891
MC		 2303/* tp->lock is held. */
2304static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2305{
2306 u32 addr_high, addr_low;
2307 int i;
2308
2309 addr_high = ((tp->dev->dev_addr[0] << 8) |
2310 tp->dev->dev_addr[1]);
2311 addr_low = ((tp->dev->dev_addr[2] << 24) |
2312 (tp->dev->dev_addr[3] << 16) |
2313 (tp->dev->dev_addr[4] << 8) |
2314 (tp->dev->dev_addr[5] << 0));
2315 for (i = 0; i < 4; i++) {
2316 if (i == 1 && skip_mac_1)
2317 continue;
2318 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2319 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2320 }
2321
2322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2324 for (i = 0; i < 12; i++) {
2325 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2326 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2327 }
2328 }
2329
2330 addr_high = (tp->dev->dev_addr[0] +
2331 tp->dev->dev_addr[1] +
2332 tp->dev->dev_addr[2] +
2333 tp->dev->dev_addr[3] +
2334 tp->dev->dev_addr[4] +
2335 tp->dev->dev_addr[5]) &
2336 TX_BACKOFF_SEED_MASK;
2337 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2338}
2339
bc1c7567 2340static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2341{
2342 u32 misc_host_ctrl;
0a459aac 2343 bool device_should_wake, do_low_power;
1da177e4
LT		 2344
2345 /* Make sure register accesses (indirect or otherwise)
2346 * will function correctly.
2347 */
2348 pci_write_config_dword(tp->pdev,
2349 TG3PCI_MISC_HOST_CTRL,
2350 tp->misc_host_ctrl);
2351
1da177e4 2352 switch (state) {
bc1c7567 2353 case PCI_D0:
12dac075
RW		 2354 pci_enable_wake(tp->pdev, state, false);
2355 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2356
9d26e213
MC		 2357 /* Switch out of Vaux if it is a NIC */
2358 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2359 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2360
2361 return 0;
2362
bc1c7567 2363 case PCI_D1:
bc1c7567 2364 case PCI_D2:
bc1c7567 2365 case PCI_D3hot:
1da177e4
LT		 2366 break;
2367
2368 default:
12dac075
RW		 2369 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2370 tp->dev->name, state);
1da177e4 2371 return -EINVAL;
855e1111 2372 }
5e7dfd0f
MC		 2373
2374 /* Restore the CLKREQ setting. */
2375 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2376 u16 lnkctl;
2377
2378 pci_read_config_word(tp->pdev,
2379 tp->pcie_cap + PCI_EXP_LNKCTL,
2380 &lnkctl);
2381 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2382 pci_write_config_word(tp->pdev,
2383 tp->pcie_cap + PCI_EXP_LNKCTL,
2384 lnkctl);
2385 }
2386
1da177e4
LT		 2387 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2388 tw32(TG3PCI_MISC_HOST_CTRL,
2389 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2390
05ac4cb7
MC		 2391 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2392 device_may_wakeup(&tp->pdev->dev) &&
2393 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2394
dd477003 2395 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2396 do_low_power = false;
b02fd9e3
MC		 2397 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2398 !tp->link_config.phy_is_low_power) {
2399 struct phy_device *phydev;
0a459aac 2400 u32 phyid, advertising;
b02fd9e3 2401
298cf9be 2402 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2403
2404 tp->link_config.phy_is_low_power = 1;
2405
2406 tp->link_config.orig_speed = phydev->speed;
2407 tp->link_config.orig_duplex = phydev->duplex;
2408 tp->link_config.orig_autoneg = phydev->autoneg;
2409 tp->link_config.orig_advertising = phydev->advertising;
2410
2411 advertising = ADVERTISED_TP |
2412 ADVERTISED_Pause |
2413 ADVERTISED_Autoneg |
2414 ADVERTISED_10baseT_Half;
2415
2416 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2417 device_should_wake) {
b02fd9e3
MC		 2418 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2419 advertising |=
2420 ADVERTISED_100baseT_Half |
2421 ADVERTISED_100baseT_Full |
2422 ADVERTISED_10baseT_Full;
2423 else
2424 advertising |= ADVERTISED_10baseT_Full;
2425 }
2426
2427 phydev->advertising = advertising;
2428
2429 phy_start_aneg(phydev);
0a459aac
MC		 2430
2431 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2432 if (phyid != TG3_PHY_ID_BCMAC131) {
2433 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2434 if (phyid == TG3_PHY_OUI_1 ||
2435 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2436 phyid == TG3_PHY_OUI_3)
2437 do_low_power = true;
2438 }
b02fd9e3 2439 }
dd477003 2440 } else {
2023276e 2441 do_low_power = true;
0a459aac 2442
dd477003
MC		 2443 if (tp->link_config.phy_is_low_power == 0) {
2444 tp->link_config.phy_is_low_power = 1;
2445 tp->link_config.orig_speed = tp->link_config.speed;
2446 tp->link_config.orig_duplex = tp->link_config.duplex;
2447 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2448 }
1da177e4 2449
dd477003
MC		 2450 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2451 tp->link_config.speed = SPEED_10;
2452 tp->link_config.duplex = DUPLEX_HALF;
2453 tp->link_config.autoneg = AUTONEG_ENABLE;
2454 tg3_setup_phy(tp, 0);
2455 }
1da177e4
LT		 2456 }
2457
3f007891
MC		 2458 __tg3_set_mac_addr(tp, 0);
2459
b5d3772c
MC		 2460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2461 u32 val;
2462
2463 val = tr32(GRC_VCPU_EXT_CTRL);
2464 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2465 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2466 int i;
2467 u32 val;
2468
2469 for (i = 0; i < 200; i++) {
2470 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2471 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2472 break;
2473 msleep(1);
2474 }
2475 }
a85feb8c
GZ		 2476 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2477 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2478 WOL_DRV_STATE_SHUTDOWN |
2479 WOL_DRV_WOL |
2480 WOL_SET_MAGIC_PKT);
6921d201 2481
05ac4cb7 2482 if (device_should_wake) {
1da177e4
LT		 2483 u32 mac_mode;
2484
2485 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2486 if (do_low_power) {
dd477003
MC		 2487 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2488 udelay(40);
2489 }
1da177e4 2490
3f7045c1
MC		 2491 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2492 mac_mode = MAC_MODE_PORT_MODE_GMII;
2493 else
2494 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2495
e8f3f6ca
MC		 2496 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2497 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2498 ASIC_REV_5700) {
2499 u32 speed = (tp->tg3_flags &
2500 TG3_FLAG_WOL_SPEED_100MB) ?
2501 SPEED_100 : SPEED_10;
2502 if (tg3_5700_link_polarity(tp, speed))
2503 mac_mode |= MAC_MODE_LINK_POLARITY;
2504 else
2505 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2506 }
1da177e4
LT		 2507 } else {
2508 mac_mode = MAC_MODE_PORT_MODE_TBI;
2509 }
2510
cbf46853 2511 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2512 tw32(MAC_LED_CTRL, tp->led_ctrl);
2513
05ac4cb7
MC		 2514 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2515 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2516 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2517 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2518 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2519 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2520
3bda1258
MC		 2521 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2522 mac_mode |= tp->mac_mode &
2523 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2524 if (mac_mode & MAC_MODE_APE_TX_EN)
2525 mac_mode |= MAC_MODE_TDE_ENABLE;
2526 }
2527
1da177e4
LT		 2528 tw32_f(MAC_MODE, mac_mode);
2529 udelay(100);
2530
2531 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2532 udelay(10);
2533 }
2534
2535 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2536 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2538 u32 base_val;
2539
2540 base_val = tp->pci_clock_ctrl;
2541 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2542 CLOCK_CTRL_TXCLK_DISABLE);
2543
b401e9e2
MC		 2544 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2545 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2546 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2547 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2548 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2549 /* do nothing */
85e94ced 2550 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2551 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2552 u32 newbits1, newbits2;
2553
2554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2555 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2556 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2557 CLOCK_CTRL_TXCLK_DISABLE |
2558 CLOCK_CTRL_ALTCLK);
2559 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2560 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2561 newbits1 = CLOCK_CTRL_625_CORE;
2562 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2563 } else {
2564 newbits1 = CLOCK_CTRL_ALTCLK;
2565 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2566 }
2567
b401e9e2
MC		 2568 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2569 40);
1da177e4 2570
b401e9e2
MC		 2571 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2572 40);
1da177e4
LT		 2573
2574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2575 u32 newbits3;
2576
2577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2579 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2580 CLOCK_CTRL_TXCLK_DISABLE |
2581 CLOCK_CTRL_44MHZ_CORE);
2582 } else {
2583 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2584 }
2585
b401e9e2
MC		 2586 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2587 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2588 }
2589 }
2590
05ac4cb7 2591 if (!(device_should_wake) &&
22435849 2592 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2593 tg3_power_down_phy(tp, do_low_power);
6921d201 2594
1da177e4
LT		 2595 tg3_frob_aux_power(tp);
2596
2597 /* Workaround for unstable PLL clock */
2598 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2599 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2600 u32 val = tr32(0x7d00);
2601
2602 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2603 tw32(0x7d00, val);
6921d201 2604 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2605 int err;
2606
2607 err = tg3_nvram_lock(tp);
1da177e4 2608 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2609 if (!err)
2610 tg3_nvram_unlock(tp);
6921d201 2611 }
1da177e4
LT		 2612 }
2613
bbadf503
MC		 2614 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2615
05ac4cb7 2616 if (device_should_wake)
12dac075
RW		 2617 pci_enable_wake(tp->pdev, state, true);
2618
1da177e4 2619 /* Finally, set the new power state. */
12dac075 2620 pci_set_power_state(tp->pdev, state);
1da177e4 2621
1da177e4
LT		 2622 return 0;
2623}
2624
1da177e4
LT		 2625static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2626{
2627 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2628 case MII_TG3_AUX_STAT_10HALF:
2629 *speed = SPEED_10;
2630 *duplex = DUPLEX_HALF;
2631 break;
2632
2633 case MII_TG3_AUX_STAT_10FULL:
2634 *speed = SPEED_10;
2635 *duplex = DUPLEX_FULL;
2636 break;
2637
2638 case MII_TG3_AUX_STAT_100HALF:
2639 *speed = SPEED_100;
2640 *duplex = DUPLEX_HALF;
2641 break;
2642
2643 case MII_TG3_AUX_STAT_100FULL:
2644 *speed = SPEED_100;
2645 *duplex = DUPLEX_FULL;
2646 break;
2647
2648 case MII_TG3_AUX_STAT_1000HALF:
2649 *speed = SPEED_1000;
2650 *duplex = DUPLEX_HALF;
2651 break;
2652
2653 case MII_TG3_AUX_STAT_1000FULL:
2654 *speed = SPEED_1000;
2655 *duplex = DUPLEX_FULL;
2656 break;
2657
2658 default:
715116a1
MC		 2659 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2660 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2661 SPEED_10;
2662 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2663 DUPLEX_HALF;
2664 break;
2665 }
1da177e4
LT		 2666 *speed = SPEED_INVALID;
2667 *duplex = DUPLEX_INVALID;
2668 break;
855e1111 2669 }
1da177e4
LT		 2670}
2671
2672static void tg3_phy_copper_begin(struct tg3 *tp)
2673{
2674 u32 new_adv;
2675 int i;
2676
2677 if (tp->link_config.phy_is_low_power) {
2678 /* Entering low power mode. Disable gigabit and
2679 * 100baseT advertisements.
2680 */
2681 tg3_writephy(tp, MII_TG3_CTRL, 0);
2682
2683 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2684 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2685 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2686 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2687
2688 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2689 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2690 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2691 tp->link_config.advertising &=
2692 ~(ADVERTISED_1000baseT_Half |
2693 ADVERTISED_1000baseT_Full);
2694
ba4d07a8 2695 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2696 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2697 new_adv |= ADVERTISE_10HALF;
2698 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2699 new_adv |= ADVERTISE_10FULL;
2700 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2701 new_adv |= ADVERTISE_100HALF;
2702 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2703 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2704
2705 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2706
1da177e4
LT		 2707 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2708
2709 if (tp->link_config.advertising &
2710 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2711 new_adv = 0;
2712 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2713 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2714 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2715 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2716 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2717 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2718 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2719 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2720 MII_TG3_CTRL_ENABLE_AS_MASTER);
2721 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2722 } else {
2723 tg3_writephy(tp, MII_TG3_CTRL, 0);
2724 }
2725 } else {
ba4d07a8
MC		 2726 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2727 new_adv |= ADVERTISE_CSMA;
2728
1da177e4
LT		 2729 /* Asking for a specific link mode. */
2730 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2731 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2732
2733 if (tp->link_config.duplex == DUPLEX_FULL)
2734 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2735 else
2736 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2737 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2738 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2739 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2740 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2741 } else {
1da177e4
LT		 2742 if (tp->link_config.speed == SPEED_100) {
2743 if (tp->link_config.duplex == DUPLEX_FULL)
2744 new_adv |= ADVERTISE_100FULL;
2745 else
2746 new_adv |= ADVERTISE_100HALF;
2747 } else {
2748 if (tp->link_config.duplex == DUPLEX_FULL)
2749 new_adv |= ADVERTISE_10FULL;
2750 else
2751 new_adv |= ADVERTISE_10HALF;
2752 }
2753 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2754
2755 new_adv = 0;
1da177e4 2756 }
ba4d07a8
MC		 2757
2758 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2759 }
2760
2761 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2762 tp->link_config.speed != SPEED_INVALID) {
2763 u32 bmcr, orig_bmcr;
2764
2765 tp->link_config.active_speed = tp->link_config.speed;
2766 tp->link_config.active_duplex = tp->link_config.duplex;
2767
2768 bmcr = 0;
2769 switch (tp->link_config.speed) {
2770 default:
2771 case SPEED_10:
2772 break;
2773
2774 case SPEED_100:
2775 bmcr |= BMCR_SPEED100;
2776 break;
2777
2778 case SPEED_1000:
2779 bmcr |= TG3_BMCR_SPEED1000;
2780 break;
855e1111 2781 }
1da177e4
LT		 2782
2783 if (tp->link_config.duplex == DUPLEX_FULL)
2784 bmcr |= BMCR_FULLDPLX;
2785
2786 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2787 (bmcr != orig_bmcr)) {
2788 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2789 for (i = 0; i < 1500; i++) {
2790 u32 tmp;
2791
2792 udelay(10);
2793 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2794 tg3_readphy(tp, MII_BMSR, &tmp))
2795 continue;
2796 if (!(tmp & BMSR_LSTATUS)) {
2797 udelay(40);
2798 break;
2799 }
2800 }
2801 tg3_writephy(tp, MII_BMCR, bmcr);
2802 udelay(40);
2803 }
2804 } else {
2805 tg3_writephy(tp, MII_BMCR,
2806 BMCR_ANENABLE | BMCR_ANRESTART);
2807 }
2808}
2809
2810static int tg3_init_5401phy_dsp(struct tg3 *tp)
2811{
2812 int err;
2813
2814 /* Turn off tap power management. */
2815 /* Set Extended packet length bit */
2816 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2817
2818 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2819 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2820
2821 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2822 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2823
2824 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2825 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2826
2827 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2828 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2829
2830 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2831 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2832
2833 udelay(40);
2834
2835 return err;
2836}
2837
3600d918 2838static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2839{
3600d918
MC		 2840 u32 adv_reg, all_mask = 0;
2841
2842 if (mask & ADVERTISED_10baseT_Half)
2843 all_mask |= ADVERTISE_10HALF;
2844 if (mask & ADVERTISED_10baseT_Full)
2845 all_mask |= ADVERTISE_10FULL;
2846 if (mask & ADVERTISED_100baseT_Half)
2847 all_mask |= ADVERTISE_100HALF;
2848 if (mask & ADVERTISED_100baseT_Full)
2849 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2850
2851 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2852 return 0;
2853
1da177e4
LT		 2854 if ((adv_reg & all_mask) != all_mask)
2855 return 0;
2856 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2857 u32 tg3_ctrl;
2858
3600d918
MC		 2859 all_mask = 0;
2860 if (mask & ADVERTISED_1000baseT_Half)
2861 all_mask |= ADVERTISE_1000HALF;
2862 if (mask & ADVERTISED_1000baseT_Full)
2863 all_mask |= ADVERTISE_1000FULL;
2864
1da177e4
LT		 2865 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2866 return 0;
2867
1da177e4
LT		 2868 if ((tg3_ctrl & all_mask) != all_mask)
2869 return 0;
2870 }
2871 return 1;
2872}
2873
ef167e27
MC		 2874static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2875{
2876 u32 curadv, reqadv;
2877
2878 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2879 return 1;
2880
2881 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2882 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2883
2884 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2885 if (curadv != reqadv)
2886 return 0;
2887
2888 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2889 tg3_readphy(tp, MII_LPA, rmtadv);
2890 } else {
2891 /* Reprogram the advertisement register, even if it
2892 * does not affect the current link. If the link
2893 * gets renegotiated in the future, we can save an
2894 * additional renegotiation cycle by advertising
2895 * it correctly in the first place.
2896 */
2897 if (curadv != reqadv) {
2898 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2899 ADVERTISE_PAUSE_ASYM);
2900 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2901 }
2902 }
2903
2904 return 1;
2905}
2906
1da177e4
LT		 2907static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2908{
2909 int current_link_up;
2910 u32 bmsr, dummy;
ef167e27 2911 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2912 u16 current_speed;
2913 u8 current_duplex;
2914 int i, err;
2915
2916 tw32(MAC_EVENT, 0);
2917
2918 tw32_f(MAC_STATUS,
2919 (MAC_STATUS_SYNC_CHANGED |
2920 MAC_STATUS_CFG_CHANGED |
2921 MAC_STATUS_MI_COMPLETION |
2922 MAC_STATUS_LNKSTATE_CHANGED));
2923 udelay(40);
2924
8ef21428
MC		 2925 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2926 tw32_f(MAC_MI_MODE,
2927 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2928 udelay(80);
2929 }
1da177e4
LT		 2930
2931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2932
2933 /* Some third-party PHYs need to be reset on link going
2934 * down.
2935 */
2936 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2939 netif_carrier_ok(tp->dev)) {
2940 tg3_readphy(tp, MII_BMSR, &bmsr);
2941 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2942 !(bmsr & BMSR_LSTATUS))
2943 force_reset = 1;
2944 }
2945 if (force_reset)
2946 tg3_phy_reset(tp);
2947
2948 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2949 tg3_readphy(tp, MII_BMSR, &bmsr);
2950 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2951 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2952 bmsr = 0;
2953
2954 if (!(bmsr & BMSR_LSTATUS)) {
2955 err = tg3_init_5401phy_dsp(tp);
2956 if (err)
2957 return err;
2958
2959 tg3_readphy(tp, MII_BMSR, &bmsr);
2960 for (i = 0; i < 1000; i++) {
2961 udelay(10);
2962 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2963 (bmsr & BMSR_LSTATUS)) {
2964 udelay(40);
2965 break;
2966 }
2967 }
2968
2969 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2970 !(bmsr & BMSR_LSTATUS) &&
2971 tp->link_config.active_speed == SPEED_1000) {
2972 err = tg3_phy_reset(tp);
2973 if (!err)
2974 err = tg3_init_5401phy_dsp(tp);
2975 if (err)
2976 return err;
2977 }
2978 }
2979 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2980 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2981 /* 5701 {A0,B0} CRC bug workaround */
2982 tg3_writephy(tp, 0x15, 0x0a75);
2983 tg3_writephy(tp, 0x1c, 0x8c68);
2984 tg3_writephy(tp, 0x1c, 0x8d68);
2985 tg3_writephy(tp, 0x1c, 0x8c68);
2986 }
2987
2988 /* Clear pending interrupts... */
2989 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2990 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2991
2992 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2993 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2994 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2995 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2996
2997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2999 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3001 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3002 else
3003 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3004 }
3005
3006 current_link_up = 0;
3007 current_speed = SPEED_INVALID;
3008 current_duplex = DUPLEX_INVALID;
3009
3010 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3011 u32 val;
3012
3013 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3014 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3015 if (!(val & (1 << 10))) {
3016 val |= (1 << 10);
3017 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3018 goto relink;
3019 }
3020 }
3021
3022 bmsr = 0;
3023 for (i = 0; i < 100; i++) {
3024 tg3_readphy(tp, MII_BMSR, &bmsr);
3025 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3026 (bmsr & BMSR_LSTATUS))
3027 break;
3028 udelay(40);
3029 }
3030
3031 if (bmsr & BMSR_LSTATUS) {
3032 u32 aux_stat, bmcr;
3033
3034 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3035 for (i = 0; i < 2000; i++) {
3036 udelay(10);
3037 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3038 aux_stat)
3039 break;
3040 }
3041
3042 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3043 &current_speed,
3044 &current_duplex);
3045
3046 bmcr = 0;
3047 for (i = 0; i < 200; i++) {
3048 tg3_readphy(tp, MII_BMCR, &bmcr);
3049 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3050 continue;
3051 if (bmcr && bmcr != 0x7fff)
3052 break;
3053 udelay(10);
3054 }
3055
ef167e27
MC		 3056 lcl_adv = 0;
3057 rmt_adv = 0;
1da177e4 3058
ef167e27
MC		 3059 tp->link_config.active_speed = current_speed;
3060 tp->link_config.active_duplex = current_duplex;
3061
3062 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3063 if ((bmcr & BMCR_ANENABLE) &&
3064 tg3_copper_is_advertising_all(tp,
3065 tp->link_config.advertising)) {
3066 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3067 &rmt_adv))
3068 current_link_up = 1;
1da177e4
LT		 3069 }
3070 } else {
3071 if (!(bmcr & BMCR_ANENABLE) &&
3072 tp->link_config.speed == current_speed &&
ef167e27
MC		 3073 tp->link_config.duplex == current_duplex &&
3074 tp->link_config.flowctrl ==
3075 tp->link_config.active_flowctrl) {
1da177e4 3076 current_link_up = 1;
1da177e4
LT		 3077 }
3078 }
3079
ef167e27
MC		 3080 if (current_link_up == 1 &&
3081 tp->link_config.active_duplex == DUPLEX_FULL)
3082 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3083 }
3084
1da177e4 3085relink:
6921d201 3086 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3087 u32 tmp;
3088
3089 tg3_phy_copper_begin(tp);
3090
3091 tg3_readphy(tp, MII_BMSR, &tmp);
3092 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3093 (tmp & BMSR_LSTATUS))
3094 current_link_up = 1;
3095 }
3096
3097 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3098 if (current_link_up == 1) {
3099 if (tp->link_config.active_speed == SPEED_100 ||
3100 tp->link_config.active_speed == SPEED_10)
3101 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3102 else
3103 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3104 } else
3105 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3106
3107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3108 if (tp->link_config.active_duplex == DUPLEX_HALF)
3109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3110
1da177e4 3111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3112 if (current_link_up == 1 &&
3113 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3114 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3115 else
3116 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3117 }
3118
3119 /* ??? Without this setting Netgear GA302T PHY does not
3120 * ??? send/receive packets...
3121 */
3122 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3123 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3124 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3125 tw32_f(MAC_MI_MODE, tp->mi_mode);
3126 udelay(80);
3127 }
3128
3129 tw32_f(MAC_MODE, tp->mac_mode);
3130 udelay(40);
3131
3132 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3133 /* Polled via timer. */
3134 tw32_f(MAC_EVENT, 0);
3135 } else {
3136 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3137 }
3138 udelay(40);
3139
3140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3141 current_link_up == 1 &&
3142 tp->link_config.active_speed == SPEED_1000 &&
3143 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3144 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3145 udelay(120);
3146 tw32_f(MAC_STATUS,
3147 (MAC_STATUS_SYNC_CHANGED |
3148 MAC_STATUS_CFG_CHANGED));
3149 udelay(40);
3150 tg3_write_mem(tp,
3151 NIC_SRAM_FIRMWARE_MBOX,
3152 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3153 }
3154
5e7dfd0f
MC		 3155 /* Prevent send BD corruption. */
3156 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3157 u16 oldlnkctl, newlnkctl;
3158
3159 pci_read_config_word(tp->pdev,
3160 tp->pcie_cap + PCI_EXP_LNKCTL,
3161 &oldlnkctl);
3162 if (tp->link_config.active_speed == SPEED_100 ||
3163 tp->link_config.active_speed == SPEED_10)
3164 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3165 else
3166 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3167 if (newlnkctl != oldlnkctl)
3168 pci_write_config_word(tp->pdev,
3169 tp->pcie_cap + PCI_EXP_LNKCTL,
3170 newlnkctl);
3171 }
3172
1da177e4
LT		 3173 if (current_link_up != netif_carrier_ok(tp->dev)) {
3174 if (current_link_up)
3175 netif_carrier_on(tp->dev);
3176 else
3177 netif_carrier_off(tp->dev);
3178 tg3_link_report(tp);
3179 }
3180
3181 return 0;
3182}
3183
3184struct tg3_fiber_aneginfo {
3185 int state;
3186#define ANEG_STATE_UNKNOWN 0
3187#define ANEG_STATE_AN_ENABLE 1
3188#define ANEG_STATE_RESTART_INIT 2
3189#define ANEG_STATE_RESTART 3
3190#define ANEG_STATE_DISABLE_LINK_OK 4
3191#define ANEG_STATE_ABILITY_DETECT_INIT 5
3192#define ANEG_STATE_ABILITY_DETECT 6
3193#define ANEG_STATE_ACK_DETECT_INIT 7
3194#define ANEG_STATE_ACK_DETECT 8
3195#define ANEG_STATE_COMPLETE_ACK_INIT 9
3196#define ANEG_STATE_COMPLETE_ACK 10
3197#define ANEG_STATE_IDLE_DETECT_INIT 11
3198#define ANEG_STATE_IDLE_DETECT 12
3199#define ANEG_STATE_LINK_OK 13
3200#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3201#define ANEG_STATE_NEXT_PAGE_WAIT 15
3202
3203 u32 flags;
3204#define MR_AN_ENABLE 0x00000001
3205#define MR_RESTART_AN 0x00000002
3206#define MR_AN_COMPLETE 0x00000004
3207#define MR_PAGE_RX 0x00000008
3208#define MR_NP_LOADED 0x00000010
3209#define MR_TOGGLE_TX 0x00000020
3210#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3211#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3212#define MR_LP_ADV_SYM_PAUSE 0x00000100
3213#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3214#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3215#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3216#define MR_LP_ADV_NEXT_PAGE 0x00001000
3217#define MR_TOGGLE_RX 0x00002000
3218#define MR_NP_RX 0x00004000
3219
3220#define MR_LINK_OK 0x80000000
3221
3222 unsigned long link_time, cur_time;
3223
3224 u32 ability_match_cfg;
3225 int ability_match_count;
3226
3227 char ability_match, idle_match, ack_match;
3228
3229 u32 txconfig, rxconfig;
3230#define ANEG_CFG_NP 0x00000080
3231#define ANEG_CFG_ACK 0x00000040
3232#define ANEG_CFG_RF2 0x00000020
3233#define ANEG_CFG_RF1 0x00000010
3234#define ANEG_CFG_PS2 0x00000001
3235#define ANEG_CFG_PS1 0x00008000
3236#define ANEG_CFG_HD 0x00004000
3237#define ANEG_CFG_FD 0x00002000
3238#define ANEG_CFG_INVAL 0x00001f06
3239
3240};
3241#define ANEG_OK 0
3242#define ANEG_DONE 1
3243#define ANEG_TIMER_ENAB 2
3244#define ANEG_FAILED -1
3245
3246#define ANEG_STATE_SETTLE_TIME 10000
3247
3248static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3249 struct tg3_fiber_aneginfo *ap)
3250{
5be73b47 3251 u16 flowctrl;
1da177e4
LT		 3252 unsigned long delta;
3253 u32 rx_cfg_reg;
3254 int ret;
3255
3256 if (ap->state == ANEG_STATE_UNKNOWN) {
3257 ap->rxconfig = 0;
3258 ap->link_time = 0;
3259 ap->cur_time = 0;
3260 ap->ability_match_cfg = 0;
3261 ap->ability_match_count = 0;
3262 ap->ability_match = 0;
3263 ap->idle_match = 0;
3264 ap->ack_match = 0;
3265 }
3266 ap->cur_time++;
3267
3268 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3269 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3270
3271 if (rx_cfg_reg != ap->ability_match_cfg) {
3272 ap->ability_match_cfg = rx_cfg_reg;
3273 ap->ability_match = 0;
3274 ap->ability_match_count = 0;
3275 } else {
3276 if (++ap->ability_match_count > 1) {
3277 ap->ability_match = 1;
3278 ap->ability_match_cfg = rx_cfg_reg;
3279 }
3280 }
3281 if (rx_cfg_reg & ANEG_CFG_ACK)
3282 ap->ack_match = 1;
3283 else
3284 ap->ack_match = 0;
3285
3286 ap->idle_match = 0;
3287 } else {
3288 ap->idle_match = 1;
3289 ap->ability_match_cfg = 0;
3290 ap->ability_match_count = 0;
3291 ap->ability_match = 0;
3292 ap->ack_match = 0;
3293
3294 rx_cfg_reg = 0;
3295 }
3296
3297 ap->rxconfig = rx_cfg_reg;
3298 ret = ANEG_OK;
3299
3300 switch(ap->state) {
3301 case ANEG_STATE_UNKNOWN:
3302 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3303 ap->state = ANEG_STATE_AN_ENABLE;
3304
3305 /* fallthru */
3306 case ANEG_STATE_AN_ENABLE:
3307 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3308 if (ap->flags & MR_AN_ENABLE) {
3309 ap->link_time = 0;
3310 ap->cur_time = 0;
3311 ap->ability_match_cfg = 0;
3312 ap->ability_match_count = 0;
3313 ap->ability_match = 0;
3314 ap->idle_match = 0;
3315 ap->ack_match = 0;
3316
3317 ap->state = ANEG_STATE_RESTART_INIT;
3318 } else {
3319 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3320 }
3321 break;
3322
3323 case ANEG_STATE_RESTART_INIT:
3324 ap->link_time = ap->cur_time;
3325 ap->flags &= ~(MR_NP_LOADED);
3326 ap->txconfig = 0;
3327 tw32(MAC_TX_AUTO_NEG, 0);
3328 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3329 tw32_f(MAC_MODE, tp->mac_mode);
3330 udelay(40);
3331
3332 ret = ANEG_TIMER_ENAB;
3333 ap->state = ANEG_STATE_RESTART;
3334
3335 /* fallthru */
3336 case ANEG_STATE_RESTART:
3337 delta = ap->cur_time - ap->link_time;
3338 if (delta > ANEG_STATE_SETTLE_TIME) {
3339 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3340 } else {
3341 ret = ANEG_TIMER_ENAB;
3342 }
3343 break;
3344
3345 case ANEG_STATE_DISABLE_LINK_OK:
3346 ret = ANEG_DONE;
3347 break;
3348
3349 case ANEG_STATE_ABILITY_DETECT_INIT:
3350 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3351 ap->txconfig = ANEG_CFG_FD;
3352 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3353 if (flowctrl & ADVERTISE_1000XPAUSE)
3354 ap->txconfig |= ANEG_CFG_PS1;
3355 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3356 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3357 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3358 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3359 tw32_f(MAC_MODE, tp->mac_mode);
3360 udelay(40);
3361
3362 ap->state = ANEG_STATE_ABILITY_DETECT;
3363 break;
3364
3365 case ANEG_STATE_ABILITY_DETECT:
3366 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3367 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3368 }
3369 break;
3370
3371 case ANEG_STATE_ACK_DETECT_INIT:
3372 ap->txconfig |= ANEG_CFG_ACK;
3373 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3374 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3375 tw32_f(MAC_MODE, tp->mac_mode);
3376 udelay(40);
3377
3378 ap->state = ANEG_STATE_ACK_DETECT;
3379
3380 /* fallthru */
3381 case ANEG_STATE_ACK_DETECT:
3382 if (ap->ack_match != 0) {
3383 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3384 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3385 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3386 } else {
3387 ap->state = ANEG_STATE_AN_ENABLE;
3388 }
3389 } else if (ap->ability_match != 0 &&
3390 ap->rxconfig == 0) {
3391 ap->state = ANEG_STATE_AN_ENABLE;
3392 }
3393 break;
3394
3395 case ANEG_STATE_COMPLETE_ACK_INIT:
3396 if (ap->rxconfig & ANEG_CFG_INVAL) {
3397 ret = ANEG_FAILED;
3398 break;
3399 }
3400 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3401 MR_LP_ADV_HALF_DUPLEX |
3402 MR_LP_ADV_SYM_PAUSE |
3403 MR_LP_ADV_ASYM_PAUSE |
3404 MR_LP_ADV_REMOTE_FAULT1 |
3405 MR_LP_ADV_REMOTE_FAULT2 |
3406 MR_LP_ADV_NEXT_PAGE |
3407 MR_TOGGLE_RX |
3408 MR_NP_RX);
3409 if (ap->rxconfig & ANEG_CFG_FD)
3410 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3411 if (ap->rxconfig & ANEG_CFG_HD)
3412 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3413 if (ap->rxconfig & ANEG_CFG_PS1)
3414 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3415 if (ap->rxconfig & ANEG_CFG_PS2)
3416 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3417 if (ap->rxconfig & ANEG_CFG_RF1)
3418 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3419 if (ap->rxconfig & ANEG_CFG_RF2)
3420 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3421 if (ap->rxconfig & ANEG_CFG_NP)
3422 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3423
3424 ap->link_time = ap->cur_time;
3425
3426 ap->flags ^= (MR_TOGGLE_TX);
3427 if (ap->rxconfig & 0x0008)
3428 ap->flags |= MR_TOGGLE_RX;
3429 if (ap->rxconfig & ANEG_CFG_NP)
3430 ap->flags |= MR_NP_RX;
3431 ap->flags |= MR_PAGE_RX;
3432
3433 ap->state = ANEG_STATE_COMPLETE_ACK;
3434 ret = ANEG_TIMER_ENAB;
3435 break;
3436
3437 case ANEG_STATE_COMPLETE_ACK:
3438 if (ap->ability_match != 0 &&
3439 ap->rxconfig == 0) {
3440 ap->state = ANEG_STATE_AN_ENABLE;
3441 break;
3442 }
3443 delta = ap->cur_time - ap->link_time;
3444 if (delta > ANEG_STATE_SETTLE_TIME) {
3445 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3446 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3447 } else {
3448 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3449 !(ap->flags & MR_NP_RX)) {
3450 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3451 } else {
3452 ret = ANEG_FAILED;
3453 }
3454 }
3455 }
3456 break;
3457
3458 case ANEG_STATE_IDLE_DETECT_INIT:
3459 ap->link_time = ap->cur_time;
3460 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3461 tw32_f(MAC_MODE, tp->mac_mode);
3462 udelay(40);
3463
3464 ap->state = ANEG_STATE_IDLE_DETECT;
3465 ret = ANEG_TIMER_ENAB;
3466 break;
3467
3468 case ANEG_STATE_IDLE_DETECT:
3469 if (ap->ability_match != 0 &&
3470 ap->rxconfig == 0) {
3471 ap->state = ANEG_STATE_AN_ENABLE;
3472 break;
3473 }
3474 delta = ap->cur_time - ap->link_time;
3475 if (delta > ANEG_STATE_SETTLE_TIME) {
3476 /* XXX another gem from the Broadcom driver :( */
3477 ap->state = ANEG_STATE_LINK_OK;
3478 }
3479 break;
3480
3481 case ANEG_STATE_LINK_OK:
3482 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3483 ret = ANEG_DONE;
3484 break;
3485
3486 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3487 /* ??? unimplemented */
3488 break;
3489
3490 case ANEG_STATE_NEXT_PAGE_WAIT:
3491 /* ??? unimplemented */
3492 break;
3493
3494 default:
3495 ret = ANEG_FAILED;
3496 break;
855e1111 3497 }
1da177e4
LT		 3498
3499 return ret;
3500}
3501
5be73b47 3502static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3503{
3504 int res = 0;
3505 struct tg3_fiber_aneginfo aninfo;
3506 int status = ANEG_FAILED;
3507 unsigned int tick;
3508 u32 tmp;
3509
3510 tw32_f(MAC_TX_AUTO_NEG, 0);
3511
3512 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3513 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3514 udelay(40);
3515
3516 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3517 udelay(40);
3518
3519 memset(&aninfo, 0, sizeof(aninfo));
3520 aninfo.flags |= MR_AN_ENABLE;
3521 aninfo.state = ANEG_STATE_UNKNOWN;
3522 aninfo.cur_time = 0;
3523 tick = 0;
3524 while (++tick < 195000) {
3525 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3526 if (status == ANEG_DONE || status == ANEG_FAILED)
3527 break;
3528
3529 udelay(1);
3530 }
3531
3532 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3533 tw32_f(MAC_MODE, tp->mac_mode);
3534 udelay(40);
3535
5be73b47
MC		 3536 *txflags = aninfo.txconfig;
3537 *rxflags = aninfo.flags;
1da177e4
LT		 3538
3539 if (status == ANEG_DONE &&
3540 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3541 MR_LP_ADV_FULL_DUPLEX)))
3542 res = 1;
3543
3544 return res;
3545}
3546
3547static void tg3_init_bcm8002(struct tg3 *tp)
3548{
3549 u32 mac_status = tr32(MAC_STATUS);
3550 int i;
3551
3552 /* Reset when initting first time or we have a link. */
3553 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3554 !(mac_status & MAC_STATUS_PCS_SYNCED))
3555 return;
3556
3557 /* Set PLL lock range. */
3558 tg3_writephy(tp, 0x16, 0x8007);
3559
3560 /* SW reset */
3561 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3562
3563 /* Wait for reset to complete. */
3564 /* XXX schedule_timeout() ... */
3565 for (i = 0; i < 500; i++)
3566 udelay(10);
3567
3568 /* Config mode; select PMA/Ch 1 regs. */
3569 tg3_writephy(tp, 0x10, 0x8411);
3570
3571 /* Enable auto-lock and comdet, select txclk for tx. */
3572 tg3_writephy(tp, 0x11, 0x0a10);
3573
3574 tg3_writephy(tp, 0x18, 0x00a0);
3575 tg3_writephy(tp, 0x16, 0x41ff);
3576
3577 /* Assert and deassert POR. */
3578 tg3_writephy(tp, 0x13, 0x0400);
3579 udelay(40);
3580 tg3_writephy(tp, 0x13, 0x0000);
3581
3582 tg3_writephy(tp, 0x11, 0x0a50);
3583 udelay(40);
3584 tg3_writephy(tp, 0x11, 0x0a10);
3585
3586 /* Wait for signal to stabilize */
3587 /* XXX schedule_timeout() ... */
3588 for (i = 0; i < 15000; i++)
3589 udelay(10);
3590
3591 /* Deselect the channel register so we can read the PHYID
3592 * later.
3593 */
3594 tg3_writephy(tp, 0x10, 0x8011);
3595}
3596
3597static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3598{
82cd3d11 3599 u16 flowctrl;
1da177e4
LT		 3600 u32 sg_dig_ctrl, sg_dig_status;
3601 u32 serdes_cfg, expected_sg_dig_ctrl;
3602 int workaround, port_a;
3603 int current_link_up;
3604
3605 serdes_cfg = 0;
3606 expected_sg_dig_ctrl = 0;
3607 workaround = 0;
3608 port_a = 1;
3609 current_link_up = 0;
3610
3611 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3612 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3613 workaround = 1;
3614 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3615 port_a = 0;
3616
3617 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3618 /* preserve bits 20-23 for voltage regulator */
3619 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3620 }
3621
3622 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3623
3624 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3625 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3626 if (workaround) {
3627 u32 val = serdes_cfg;
3628
3629 if (port_a)
3630 val |= 0xc010000;
3631 else
3632 val |= 0x4010000;
3633 tw32_f(MAC_SERDES_CFG, val);
3634 }
c98f6e3b
MC		 3635
3636 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3637 }
3638 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3639 tg3_setup_flow_control(tp, 0, 0);
3640 current_link_up = 1;
3641 }
3642 goto out;
3643 }
3644
3645 /* Want auto-negotiation. */
c98f6e3b 3646 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3647
82cd3d11
MC		 3648 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3649 if (flowctrl & ADVERTISE_1000XPAUSE)
3650 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3651 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3652 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3653
3654 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3655 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3656 tp->serdes_counter &&
3657 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3658 MAC_STATUS_RCVD_CFG)) ==
3659 MAC_STATUS_PCS_SYNCED)) {
3660 tp->serdes_counter--;
3661 current_link_up = 1;
3662 goto out;
3663 }
3664restart_autoneg:
1da177e4
LT		 3665 if (workaround)
3666 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3667 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3668 udelay(5);
3669 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3670
3d3ebe74
MC		 3671 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3672 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3673 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3674 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3675 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3676 mac_status = tr32(MAC_STATUS);
3677
c98f6e3b 3678 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3679 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3680 u32 local_adv = 0, remote_adv = 0;
3681
3682 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3683 local_adv |= ADVERTISE_1000XPAUSE;
3684 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3685 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3686
c98f6e3b 3687 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3688 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3689 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3690 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3691
3692 tg3_setup_flow_control(tp, local_adv, remote_adv);
3693 current_link_up = 1;
3d3ebe74
MC		 3694 tp->serdes_counter = 0;
3695 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3696 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3697 if (tp->serdes_counter)
3698 tp->serdes_counter--;
1da177e4
LT		 3699 else {
3700 if (workaround) {
3701 u32 val = serdes_cfg;
3702
3703 if (port_a)
3704 val |= 0xc010000;
3705 else
3706 val |= 0x4010000;
3707
3708 tw32_f(MAC_SERDES_CFG, val);
3709 }
3710
c98f6e3b 3711 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3712 udelay(40);
3713
3714 /* Link parallel detection - link is up */
3715 /* only if we have PCS_SYNC and not */
3716 /* receiving config code words */
3717 mac_status = tr32(MAC_STATUS);
3718 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3719 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3720 tg3_setup_flow_control(tp, 0, 0);
3721 current_link_up = 1;
3d3ebe74
MC		 3722 tp->tg3_flags2 |=
3723 TG3_FLG2_PARALLEL_DETECT;
3724 tp->serdes_counter =
3725 SERDES_PARALLEL_DET_TIMEOUT;
3726 } else
3727 goto restart_autoneg;
1da177e4
LT		 3728 }
3729 }
3d3ebe74
MC		 3730 } else {
3731 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3732 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3733 }
3734
3735out:
3736 return current_link_up;
3737}
3738
3739static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3740{
3741 int current_link_up = 0;
3742
5cf64b8a 3743 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3744 goto out;
1da177e4
LT		 3745
3746 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3747 u32 txflags, rxflags;
1da177e4 3748 int i;
6aa20a22 3749
5be73b47
MC		 3750 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3751 u32 local_adv = 0, remote_adv = 0;
1da177e4 3752
5be73b47
MC		 3753 if (txflags & ANEG_CFG_PS1)
3754 local_adv |= ADVERTISE_1000XPAUSE;
3755 if (txflags & ANEG_CFG_PS2)
3756 local_adv |= ADVERTISE_1000XPSE_ASYM;
3757
3758 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3759 remote_adv |= LPA_1000XPAUSE;
3760 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3761 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3762
3763 tg3_setup_flow_control(tp, local_adv, remote_adv);
3764
1da177e4
LT		 3765 current_link_up = 1;
3766 }
3767 for (i = 0; i < 30; i++) {
3768 udelay(20);
3769 tw32_f(MAC_STATUS,
3770 (MAC_STATUS_SYNC_CHANGED |
3771 MAC_STATUS_CFG_CHANGED));
3772 udelay(40);
3773 if ((tr32(MAC_STATUS) &
3774 (MAC_STATUS_SYNC_CHANGED |
3775 MAC_STATUS_CFG_CHANGED)) == 0)
3776 break;
3777 }
3778
3779 mac_status = tr32(MAC_STATUS);
3780 if (current_link_up == 0 &&
3781 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3782 !(mac_status & MAC_STATUS_RCVD_CFG))
3783 current_link_up = 1;
3784 } else {
5be73b47
MC		 3785 tg3_setup_flow_control(tp, 0, 0);
3786
1da177e4
LT		 3787 /* Forcing 1000FD link up. */
3788 current_link_up = 1;
1da177e4
LT		 3789
3790 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3791 udelay(40);
e8f3f6ca
MC		 3792
3793 tw32_f(MAC_MODE, tp->mac_mode);
3794 udelay(40);
1da177e4
LT		 3795 }
3796
3797out:
3798 return current_link_up;
3799}
3800
3801static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3802{
3803 u32 orig_pause_cfg;
3804 u16 orig_active_speed;
3805 u8 orig_active_duplex;
3806 u32 mac_status;
3807 int current_link_up;
3808 int i;
3809
8d018621 3810 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3811 orig_active_speed = tp->link_config.active_speed;
3812 orig_active_duplex = tp->link_config.active_duplex;
3813
3814 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3815 netif_carrier_ok(tp->dev) &&
3816 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3817 mac_status = tr32(MAC_STATUS);
3818 mac_status &= (MAC_STATUS_PCS_SYNCED |
3819 MAC_STATUS_SIGNAL_DET |
3820 MAC_STATUS_CFG_CHANGED |
3821 MAC_STATUS_RCVD_CFG);
3822 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3823 MAC_STATUS_SIGNAL_DET)) {
3824 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3825 MAC_STATUS_CFG_CHANGED));
3826 return 0;
3827 }
3828 }
3829
3830 tw32_f(MAC_TX_AUTO_NEG, 0);
3831
3832 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3833 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3834 tw32_f(MAC_MODE, tp->mac_mode);
3835 udelay(40);
3836
3837 if (tp->phy_id == PHY_ID_BCM8002)
3838 tg3_init_bcm8002(tp);
3839
3840 /* Enable link change event even when serdes polling. */
3841 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3842 udelay(40);
3843
3844 current_link_up = 0;
3845 mac_status = tr32(MAC_STATUS);
3846
3847 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3848 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3849 else
3850 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3851
1da177e4
LT		 3852 tp->hw_status->status =
3853 (SD_STATUS_UPDATED |
3854 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3855
3856 for (i = 0; i < 100; i++) {
3857 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3858 MAC_STATUS_CFG_CHANGED));
3859 udelay(5);
3860 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3861 MAC_STATUS_CFG_CHANGED |
3862 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3863 break;
3864 }
3865
3866 mac_status = tr32(MAC_STATUS);
3867 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3868 current_link_up = 0;
3d3ebe74
MC		 3869 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3870 tp->serdes_counter == 0) {
1da177e4
LT		 3871 tw32_f(MAC_MODE, (tp->mac_mode |
3872 MAC_MODE_SEND_CONFIGS));
3873 udelay(1);
3874 tw32_f(MAC_MODE, tp->mac_mode);
3875 }
3876 }
3877
3878 if (current_link_up == 1) {
3879 tp->link_config.active_speed = SPEED_1000;
3880 tp->link_config.active_duplex = DUPLEX_FULL;
3881 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3882 LED_CTRL_LNKLED_OVERRIDE |
3883 LED_CTRL_1000MBPS_ON));
3884 } else {
3885 tp->link_config.active_speed = SPEED_INVALID;
3886 tp->link_config.active_duplex = DUPLEX_INVALID;
3887 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3888 LED_CTRL_LNKLED_OVERRIDE |
3889 LED_CTRL_TRAFFIC_OVERRIDE));
3890 }
3891
3892 if (current_link_up != netif_carrier_ok(tp->dev)) {
3893 if (current_link_up)
3894 netif_carrier_on(tp->dev);
3895 else
3896 netif_carrier_off(tp->dev);
3897 tg3_link_report(tp);
3898 } else {
8d018621 3899 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3900 if (orig_pause_cfg != now_pause_cfg ||
3901 orig_active_speed != tp->link_config.active_speed ||
3902 orig_active_duplex != tp->link_config.active_duplex)
3903 tg3_link_report(tp);
3904 }
3905
3906 return 0;
3907}
3908
747e8f8b
MC		 3909static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3910{
3911 int current_link_up, err = 0;
3912 u32 bmsr, bmcr;
3913 u16 current_speed;
3914 u8 current_duplex;
ef167e27 3915 u32 local_adv, remote_adv;
747e8f8b
MC		 3916
3917 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3918 tw32_f(MAC_MODE, tp->mac_mode);
3919 udelay(40);
3920
3921 tw32(MAC_EVENT, 0);
3922
3923 tw32_f(MAC_STATUS,
3924 (MAC_STATUS_SYNC_CHANGED |
3925 MAC_STATUS_CFG_CHANGED |
3926 MAC_STATUS_MI_COMPLETION |
3927 MAC_STATUS_LNKSTATE_CHANGED));
3928 udelay(40);
3929
3930 if (force_reset)
3931 tg3_phy_reset(tp);
3932
3933 current_link_up = 0;
3934 current_speed = SPEED_INVALID;
3935 current_duplex = DUPLEX_INVALID;
3936
3937 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3938 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3940 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3941 bmsr |= BMSR_LSTATUS;
3942 else
3943 bmsr &= ~BMSR_LSTATUS;
3944 }
747e8f8b
MC		 3945
3946 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3947
3948 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3949 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3950 /* do nothing, just check for link up at the end */
3951 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3952 u32 adv, new_adv;
3953
3954 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3955 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3956 ADVERTISE_1000XPAUSE |
3957 ADVERTISE_1000XPSE_ASYM |
3958 ADVERTISE_SLCT);
3959
ba4d07a8 3960 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3961
3962 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3963 new_adv |= ADVERTISE_1000XHALF;
3964 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3965 new_adv |= ADVERTISE_1000XFULL;
3966
3967 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3968 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3969 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3970 tg3_writephy(tp, MII_BMCR, bmcr);
3971
3972 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3973 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3974 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3975
3976 return err;
3977 }
3978 } else {
3979 u32 new_bmcr;
3980
3981 bmcr &= ~BMCR_SPEED1000;
3982 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3983
3984 if (tp->link_config.duplex == DUPLEX_FULL)
3985 new_bmcr |= BMCR_FULLDPLX;
3986
3987 if (new_bmcr != bmcr) {
3988 /* BMCR_SPEED1000 is a reserved bit that needs
3989 * to be set on write.
3990 */
3991 new_bmcr |= BMCR_SPEED1000;
3992
3993 /* Force a linkdown */
3994 if (netif_carrier_ok(tp->dev)) {
3995 u32 adv;
3996
3997 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3998 adv &= ~(ADVERTISE_1000XFULL |
3999 ADVERTISE_1000XHALF |
4000 ADVERTISE_SLCT);
4001 tg3_writephy(tp, MII_ADVERTISE, adv);
4002 tg3_writephy(tp, MII_BMCR, bmcr |
4003 BMCR_ANRESTART |
4004 BMCR_ANENABLE);
4005 udelay(10);
4006 netif_carrier_off(tp->dev);
4007 }
4008 tg3_writephy(tp, MII_BMCR, new_bmcr);
4009 bmcr = new_bmcr;
4010 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4011 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4012 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4013 ASIC_REV_5714) {
4014 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4015 bmsr |= BMSR_LSTATUS;
4016 else
4017 bmsr &= ~BMSR_LSTATUS;
4018 }
747e8f8b
MC		 4019 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4020 }
4021 }
4022
4023 if (bmsr & BMSR_LSTATUS) {
4024 current_speed = SPEED_1000;
4025 current_link_up = 1;
4026 if (bmcr & BMCR_FULLDPLX)
4027 current_duplex = DUPLEX_FULL;
4028 else
4029 current_duplex = DUPLEX_HALF;
4030
ef167e27
MC		 4031 local_adv = 0;
4032 remote_adv = 0;
4033
747e8f8b 4034 if (bmcr & BMCR_ANENABLE) {
ef167e27 4035 u32 common;
747e8f8b
MC		 4036
4037 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4038 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4039 common = local_adv & remote_adv;
4040 if (common & (ADVERTISE_1000XHALF |
4041 ADVERTISE_1000XFULL)) {
4042 if (common & ADVERTISE_1000XFULL)
4043 current_duplex = DUPLEX_FULL;
4044 else
4045 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4046 }
4047 else
4048 current_link_up = 0;
4049 }
4050 }
4051
ef167e27
MC		 4052 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4053 tg3_setup_flow_control(tp, local_adv, remote_adv);
4054
747e8f8b
MC		 4055 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4056 if (tp->link_config.active_duplex == DUPLEX_HALF)
4057 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4058
4059 tw32_f(MAC_MODE, tp->mac_mode);
4060 udelay(40);
4061
4062 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4063
4064 tp->link_config.active_speed = current_speed;
4065 tp->link_config.active_duplex = current_duplex;
4066
4067 if (current_link_up != netif_carrier_ok(tp->dev)) {
4068 if (current_link_up)
4069 netif_carrier_on(tp->dev);
4070 else {
4071 netif_carrier_off(tp->dev);
4072 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4073 }
4074 tg3_link_report(tp);
4075 }
4076 return err;
4077}
4078
4079static void tg3_serdes_parallel_detect(struct tg3 *tp)
4080{
3d3ebe74 4081 if (tp->serdes_counter) {
747e8f8b 4082 /* Give autoneg time to complete. */
3d3ebe74 4083 tp->serdes_counter--;
747e8f8b
MC		 4084 return;
4085 }
4086 if (!netif_carrier_ok(tp->dev) &&
4087 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4088 u32 bmcr;
4089
4090 tg3_readphy(tp, MII_BMCR, &bmcr);
4091 if (bmcr & BMCR_ANENABLE) {
4092 u32 phy1, phy2;
4093
4094 /* Select shadow register 0x1f */
4095 tg3_writephy(tp, 0x1c, 0x7c00);
4096 tg3_readphy(tp, 0x1c, &phy1);
4097
4098 /* Select expansion interrupt status register */
4099 tg3_writephy(tp, 0x17, 0x0f01);
4100 tg3_readphy(tp, 0x15, &phy2);
4101 tg3_readphy(tp, 0x15, &phy2);
4102
4103 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4104 /* We have signal detect and not receiving
4105 * config code words, link is up by parallel
4106 * detection.
4107 */
4108
4109 bmcr &= ~BMCR_ANENABLE;
4110 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4111 tg3_writephy(tp, MII_BMCR, bmcr);
4112 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4113 }
4114 }
4115 }
4116 else if (netif_carrier_ok(tp->dev) &&
4117 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4118 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4119 u32 phy2;
4120
4121 /* Select expansion interrupt status register */
4122 tg3_writephy(tp, 0x17, 0x0f01);
4123 tg3_readphy(tp, 0x15, &phy2);
4124 if (phy2 & 0x20) {
4125 u32 bmcr;
4126
4127 /* Config code words received, turn on autoneg. */
4128 tg3_readphy(tp, MII_BMCR, &bmcr);
4129 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4130
4131 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4132
4133 }
4134 }
4135}
4136
1da177e4
LT		 4137static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4138{
4139 int err;
4140
4141 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4142 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4143 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4144 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4145 } else {
4146 err = tg3_setup_copper_phy(tp, force_reset);
4147 }
4148
bcb37f6c 4149 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4150 u32 val, scale;
4151
4152 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4153 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4154 scale = 65;
4155 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4156 scale = 6;
4157 else
4158 scale = 12;
4159
4160 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4161 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4162 tw32(GRC_MISC_CFG, val);
4163 }
4164
1da177e4
LT		 4165 if (tp->link_config.active_speed == SPEED_1000 &&
4166 tp->link_config.active_duplex == DUPLEX_HALF)
4167 tw32(MAC_TX_LENGTHS,
4168 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4169 (6 << TX_LENGTHS_IPG_SHIFT) |
4170 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4171 else
4172 tw32(MAC_TX_LENGTHS,
4173 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4174 (6 << TX_LENGTHS_IPG_SHIFT) |
4175 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4176
4177 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4178 if (netif_carrier_ok(tp->dev)) {
4179 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4180 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4181 } else {
4182 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4183 }
4184 }
4185
8ed5d97e
MC		 4186 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4187 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4188 if (!netif_carrier_ok(tp->dev))
4189 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4190 tp->pwrmgmt_thresh;
4191 else
4192 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4193 tw32(PCIE_PWR_MGMT_THRESH, val);
4194 }
4195
1da177e4
LT		 4196 return err;
4197}
4198
df3e6548
MC		 4199/* This is called whenever we suspect that the system chipset is re-
4200 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4201 * is bogus tx completions. We try to recover by setting the
4202 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4203 * in the workqueue.
4204 */
4205static void tg3_tx_recover(struct tg3 *tp)
4206{
4207 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4208 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4209
4210 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4211 "mapped I/O cycles to the network device, attempting to "
4212 "recover. Please report the problem to the driver maintainer "
4213 "and include system chipset information.\n", tp->dev->name);
4214
4215 spin_lock(&tp->lock);
df3e6548 4216 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4217 spin_unlock(&tp->lock);
4218}
4219
1b2a7205
MC		 4220static inline u32 tg3_tx_avail(struct tg3 *tp)
4221{
4222 smp_mb();
4223 return (tp->tx_pending -
4224 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4225}
4226
1da177e4
LT		 4227/* Tigon3 never reports partial packet sends. So we do not
4228 * need special logic to handle SKBs that have not had all
4229 * of their frags sent yet, like SunGEM does.
4230 */
4231static void tg3_tx(struct tg3 *tp)
4232{
4233 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4234 u32 sw_idx = tp->tx_cons;
4235
4236 while (sw_idx != hw_idx) {
4237 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4238 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4239 int i, tx_bug = 0;
4240
4241 if (unlikely(skb == NULL)) {
4242 tg3_tx_recover(tp);
4243 return;
4244 }
1da177e4 4245
90079ce8 4246 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4247
4248 ri->skb = NULL;
4249
4250 sw_idx = NEXT_TX(sw_idx);
4251
4252 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4253 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4254 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4255 tx_bug = 1;
1da177e4
LT		 4256 sw_idx = NEXT_TX(sw_idx);
4257 }
4258
f47c11ee 4259 dev_kfree_skb(skb);
df3e6548
MC		 4260
4261 if (unlikely(tx_bug)) {
4262 tg3_tx_recover(tp);
4263 return;
4264 }
1da177e4
LT		 4265 }
4266
4267 tp->tx_cons = sw_idx;
4268
1b2a7205
MC		 4269 /* Need to make the tx_cons update visible to tg3_start_xmit()
4270 * before checking for netif_queue_stopped(). Without the
4271 * memory barrier, there is a small possibility that tg3_start_xmit()
4272 * will miss it and cause the queue to be stopped forever.
4273 */
4274 smp_mb();
4275
4276 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4277 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4278 netif_tx_lock(tp->dev);
51b91468 4279 if (netif_queue_stopped(tp->dev) &&
42952231 4280 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4281 netif_wake_queue(tp->dev);
1b2a7205 4282 netif_tx_unlock(tp->dev);
51b91468 4283 }
1da177e4
LT		 4284}
4285
4286/* Returns size of skb allocated or < 0 on error.
4287 *
4288 * We only need to fill in the address because the other members
4289 * of the RX descriptor are invariant, see tg3_init_rings.
4290 *
4291 * Note the purposeful assymetry of cpu vs. chip accesses. For
4292 * posting buffers we only dirty the first cache line of the RX
4293 * descriptor (containing the address). Whereas for the RX status
4294 * buffers the cpu only reads the last cacheline of the RX descriptor
4295 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4296 */
4297static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4298 int src_idx, u32 dest_idx_unmasked)
4299{
4300 struct tg3_rx_buffer_desc *desc;
4301 struct ring_info *map, *src_map;
4302 struct sk_buff *skb;
4303 dma_addr_t mapping;
4304 int skb_size, dest_idx;
4305
4306 src_map = NULL;
4307 switch (opaque_key) {
4308 case RXD_OPAQUE_RING_STD:
4309 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4310 desc = &tp->rx_std[dest_idx];
4311 map = &tp->rx_std_buffers[dest_idx];
4312 if (src_idx >= 0)
4313 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4314 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4315 break;
4316
4317 case RXD_OPAQUE_RING_JUMBO:
4318 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4319 desc = &tp->rx_jumbo[dest_idx];
4320 map = &tp->rx_jumbo_buffers[dest_idx];
4321 if (src_idx >= 0)
4322 src_map = &tp->rx_jumbo_buffers[src_idx];
4323 skb_size = RX_JUMBO_PKT_BUF_SZ;
4324 break;
4325
4326 default:
4327 return -EINVAL;
855e1111 4328 }
1da177e4
LT		 4329
4330 /* Do not overwrite any of the map or rp information
4331 * until we are sure we can commit to a new buffer.
4332 *
4333 * Callers depend upon this behavior and assume that
4334 * we leave everything unchanged if we fail.
4335 */
a20e9c62 4336 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4337 if (skb == NULL)
4338 return -ENOMEM;
4339
1da177e4
LT		 4340 skb_reserve(skb, tp->rx_offset);
4341
4342 mapping = pci_map_single(tp->pdev, skb->data,
4343 skb_size - tp->rx_offset,
4344 PCI_DMA_FROMDEVICE);
4345
4346 map->skb = skb;
4347 pci_unmap_addr_set(map, mapping, mapping);
4348
4349 if (src_map != NULL)
4350 src_map->skb = NULL;
4351
4352 desc->addr_hi = ((u64)mapping >> 32);
4353 desc->addr_lo = ((u64)mapping & 0xffffffff);
4354
4355 return skb_size;
4356}
4357
4358/* We only need to move over in the address because the other
4359 * members of the RX descriptor are invariant. See notes above
4360 * tg3_alloc_rx_skb for full details.
4361 */
4362static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4363 int src_idx, u32 dest_idx_unmasked)
4364{
4365 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4366 struct ring_info *src_map, *dest_map;
4367 int dest_idx;
4368
4369 switch (opaque_key) {
4370 case RXD_OPAQUE_RING_STD:
4371 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4372 dest_desc = &tp->rx_std[dest_idx];
4373 dest_map = &tp->rx_std_buffers[dest_idx];
4374 src_desc = &tp->rx_std[src_idx];
4375 src_map = &tp->rx_std_buffers[src_idx];
4376 break;
4377
4378 case RXD_OPAQUE_RING_JUMBO:
4379 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4380 dest_desc = &tp->rx_jumbo[dest_idx];
4381 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4382 src_desc = &tp->rx_jumbo[src_idx];
4383 src_map = &tp->rx_jumbo_buffers[src_idx];
4384 break;
4385
4386 default:
4387 return;
855e1111 4388 }
1da177e4
LT		 4389
4390 dest_map->skb = src_map->skb;
4391 pci_unmap_addr_set(dest_map, mapping,
4392 pci_unmap_addr(src_map, mapping));
4393 dest_desc->addr_hi = src_desc->addr_hi;
4394 dest_desc->addr_lo = src_desc->addr_lo;
4395
4396 src_map->skb = NULL;
4397}
4398
4399#if TG3_VLAN_TAG_USED
4400static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4401{
1383bdb9 4402 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
1da177e4
LT		 4403}
4404#endif
4405
4406/* The RX ring scheme is composed of multiple rings which post fresh
4407 * buffers to the chip, and one special ring the chip uses to report
4408 * status back to the host.
4409 *
4410 * The special ring reports the status of received packets to the
4411 * host. The chip does not write into the original descriptor the
4412 * RX buffer was obtained from. The chip simply takes the original
4413 * descriptor as provided by the host, updates the status and length
4414 * field, then writes this into the next status ring entry.
4415 *
4416 * Each ring the host uses to post buffers to the chip is described
4417 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4418 * it is first placed into the on-chip ram. When the packet's length
4419 * is known, it walks down the TG3_BDINFO entries to select the ring.
4420 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4421 * which is within the range of the new packet's length is chosen.
4422 *
4423 * The "separate ring for rx status" scheme may sound queer, but it makes
4424 * sense from a cache coherency perspective. If only the host writes
4425 * to the buffer post rings, and only the chip writes to the rx status
4426 * rings, then cache lines never move beyond shared-modified state.
4427 * If both the host and chip were to write into the same ring, cache line
4428 * eviction could occur since both entities want it in an exclusive state.
4429 */
4430static int tg3_rx(struct tg3 *tp, int budget)
4431{
f92905de 4432 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4433 u32 sw_idx = tp->rx_rcb_ptr;
4434 u16 hw_idx;
1da177e4
LT		 4435 int received;
4436
4437 hw_idx = tp->hw_status->idx[0].rx_producer;
4438 /*
4439 * We need to order the read of hw_idx and the read of
4440 * the opaque cookie.
4441 */
4442 rmb();
1da177e4
LT		 4443 work_mask = 0;
4444 received = 0;
4445 while (sw_idx != hw_idx && budget > 0) {
4446 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4447 unsigned int len;
4448 struct sk_buff *skb;
4449 dma_addr_t dma_addr;
4450 u32 opaque_key, desc_idx, *post_ptr;
4451
4452 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4453 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4454 if (opaque_key == RXD_OPAQUE_RING_STD) {
4455 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4456 mapping);
4457 skb = tp->rx_std_buffers[desc_idx].skb;
4458 post_ptr = &tp->rx_std_ptr;
f92905de 4459 rx_std_posted++;
1da177e4
LT		 4460 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4461 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4462 mapping);
4463 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4464 post_ptr = &tp->rx_jumbo_ptr;
4465 }
4466 else {
4467 goto next_pkt_nopost;
4468 }
4469
4470 work_mask |= opaque_key;
4471
4472 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4473 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4474 drop_it:
4475 tg3_recycle_rx(tp, opaque_key,
4476 desc_idx, *post_ptr);
4477 drop_it_no_recycle:
4478 /* Other statistics kept track of by card. */
4479 tp->net_stats.rx_dropped++;
4480 goto next_pkt;
4481 }
4482
ad829268
MC		 4483 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4484 ETH_FCS_LEN;
1da177e4 4485
6aa20a22 4486 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4487 && tp->rx_offset == NET_IP_ALIGN
4488 /* rx_offset will likely not equal NET_IP_ALIGN
4489 * if this is a 5701 card running in PCI-X mode
4490 * [see tg3_get_invariants()]
4491 */
1da177e4
LT		 4492 ) {
4493 int skb_size;
4494
4495 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4496 desc_idx, *post_ptr);
4497 if (skb_size < 0)
4498 goto drop_it;
4499
4500 pci_unmap_single(tp->pdev, dma_addr,
4501 skb_size - tp->rx_offset,
4502 PCI_DMA_FROMDEVICE);
4503
4504 skb_put(skb, len);
4505 } else {
4506 struct sk_buff *copy_skb;
4507
4508 tg3_recycle_rx(tp, opaque_key,
4509 desc_idx, *post_ptr);
4510
ad829268
MC		 4511 copy_skb = netdev_alloc_skb(tp->dev,
4512 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4513 if (copy_skb == NULL)
4514 goto drop_it_no_recycle;
4515
ad829268 4516 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4517 skb_put(copy_skb, len);
4518 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4519 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4520 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4521
4522 /* We'll reuse the original ring buffer. */
4523 skb = copy_skb;
4524 }
4525
4526 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4527 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4528 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4529 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4530 skb->ip_summed = CHECKSUM_UNNECESSARY;
4531 else
4532 skb->ip_summed = CHECKSUM_NONE;
4533
4534 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4535
4536 if (len > (tp->dev->mtu + ETH_HLEN) &&
4537 skb->protocol != htons(ETH_P_8021Q)) {
4538 dev_kfree_skb(skb);
4539 goto next_pkt;
4540 }
4541
1da177e4
LT		 4542#if TG3_VLAN_TAG_USED
4543 if (tp->vlgrp != NULL &&
4544 desc->type_flags & RXD_FLAG_VLAN) {
4545 tg3_vlan_rx(tp, skb,
4546 desc->err_vlan & RXD_VLAN_MASK);
4547 } else
4548#endif
1383bdb9 4549 napi_gro_receive(&tp->napi, skb);
1da177e4 4550
1da177e4
LT		 4551 received++;
4552 budget--;
4553
4554next_pkt:
4555 (*post_ptr)++;
f92905de
MC		 4556
4557 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4558 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4559
4560 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4561 TG3_64BIT_REG_LOW, idx);
4562 work_mask &= ~RXD_OPAQUE_RING_STD;
4563 rx_std_posted = 0;
4564 }
1da177e4 4565next_pkt_nopost:
483ba50b 4566 sw_idx++;
6b31a515 4567 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4568
4569 /* Refresh hw_idx to see if there is new work */
4570 if (sw_idx == hw_idx) {
4571 hw_idx = tp->hw_status->idx[0].rx_producer;
4572 rmb();
4573 }
1da177e4
LT		 4574 }
4575
4576 /* ACK the status ring. */
483ba50b
MC		 4577 tp->rx_rcb_ptr = sw_idx;
4578 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4579
4580 /* Refill RX ring(s). */
4581 if (work_mask & RXD_OPAQUE_RING_STD) {
4582 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4583 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4584 sw_idx);
4585 }
4586 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4587 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4588 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4589 sw_idx);
4590 }
4591 mmiowb();
4592
4593 return received;
4594}
4595
6f535763 4596static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4597{
1da177e4 4598 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4599
1da177e4
LT		 4600 /* handle link change and other phy events */
4601 if (!(tp->tg3_flags &
4602 (TG3_FLAG_USE_LINKCHG_REG |
4603 TG3_FLAG_POLL_SERDES))) {
4604 if (sblk->status & SD_STATUS_LINK_CHG) {
4605 sblk->status = SD_STATUS_UPDATED |
4606 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4607 spin_lock(&tp->lock);
dd477003
MC		 4608 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4609 tw32_f(MAC_STATUS,
4610 (MAC_STATUS_SYNC_CHANGED |
4611 MAC_STATUS_CFG_CHANGED |
4612 MAC_STATUS_MI_COMPLETION |
4613 MAC_STATUS_LNKSTATE_CHANGED));
4614 udelay(40);
4615 } else
4616 tg3_setup_phy(tp, 0);
f47c11ee 4617 spin_unlock(&tp->lock);
1da177e4
LT		 4618 }
4619 }
4620
4621 /* run TX completion thread */
4622 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4623 tg3_tx(tp);
6f535763 4624 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4625 return work_done;
1da177e4
LT		 4626 }
4627
1da177e4
LT		 4628 /* run RX thread, within the bounds set by NAPI.
4629 * All RX "locking" is done by ensuring outside
bea3348e 4630 * code synchronizes with tg3->napi.poll()
1da177e4 4631 */
bea3348e 4632 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4633 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4634
6f535763
DM		 4635 return work_done;
4636}
4637
4638static int tg3_poll(struct napi_struct *napi, int budget)
4639{
4640 struct tg3 *tp = container_of(napi, struct tg3, napi);
4641 int work_done = 0;
4fd7ab59 4642 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4643
4644 while (1) {
4645 work_done = tg3_poll_work(tp, work_done, budget);
4646
4647 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4648 goto tx_recovery;
4649
4650 if (unlikely(work_done >= budget))
4651 break;
4652
4fd7ab59
MC		 4653 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4654 /* tp->last_tag is used in tg3_restart_ints() below
4655 * to tell the hw how much work has been processed,
4656 * so we must read it before checking for more work.
4657 */
4658 tp->last_tag = sblk->status_tag;
4659 rmb();
4660 } else
4661 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4662
4fd7ab59 4663 if (likely(!tg3_has_work(tp))) {
288379f0 4664 napi_complete(napi);
6f535763
DM		 4665 tg3_restart_ints(tp);
4666 break;
4667 }
1da177e4
LT		 4668 }
4669
bea3348e 4670 return work_done;
6f535763
DM		 4671
4672tx_recovery:
4fd7ab59 4673 /* work_done is guaranteed to be less than budget. */
288379f0 4674 napi_complete(napi);
6f535763 4675 schedule_work(&tp->reset_task);
4fd7ab59 4676 return work_done;
1da177e4
LT		 4677}
4678
f47c11ee
DM		 4679static void tg3_irq_quiesce(struct tg3 *tp)
4680{
4681 BUG_ON(tp->irq_sync);
4682
4683 tp->irq_sync = 1;
4684 smp_mb();
4685
4686 synchronize_irq(tp->pdev->irq);
4687}
4688
4689static inline int tg3_irq_sync(struct tg3 *tp)
4690{
4691 return tp->irq_sync;
4692}
4693
4694/* Fully shutdown all tg3 driver activity elsewhere in the system.
4695 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4696 * with as well. Most of the time, this is not necessary except when
4697 * shutting down the device.
4698 */
4699static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4700{
46966545 4701 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4702 if (irq_sync)
4703 tg3_irq_quiesce(tp);
f47c11ee
DM		 4704}
4705
4706static inline void tg3_full_unlock(struct tg3 *tp)
4707{
f47c11ee
DM		 4708 spin_unlock_bh(&tp->lock);
4709}
4710
fcfa0a32
MC		 4711/* One-shot MSI handler - Chip automatically disables interrupt
4712 * after sending MSI so driver doesn't have to do it.
4713 */
7d12e780 4714static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4715{
4716 struct net_device *dev = dev_id;
4717 struct tg3 *tp = netdev_priv(dev);
4718
4719 prefetch(tp->hw_status);
4720 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4721
4722 if (likely(!tg3_irq_sync(tp)))
288379f0 4723 napi_schedule(&tp->napi);
fcfa0a32
MC		 4724
4725 return IRQ_HANDLED;
4726}
4727
88b06bc2
MC		 4728/* MSI ISR - No need to check for interrupt sharing and no need to
4729 * flush status block and interrupt mailbox. PCI ordering rules
4730 * guarantee that MSI will arrive after the status block.
4731 */
7d12e780 4732static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4733{
4734 struct net_device *dev = dev_id;
4735 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4736
61487480
MC		 4737 prefetch(tp->hw_status);
4738 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4739 /*
fac9b83e 4740 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4741 * chip-internal interrupt pending events.
fac9b83e 4742 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4743 * NIC to stop sending us irqs, engaging "in-intr-handler"
4744 * event coalescing.
4745 */
4746 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4747 if (likely(!tg3_irq_sync(tp)))
288379f0 4748 napi_schedule(&tp->napi);
61487480 4749
88b06bc2
MC		 4750 return IRQ_RETVAL(1);
4751}
4752
7d12e780 4753static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4754{
4755 struct net_device *dev = dev_id;
4756 struct tg3 *tp = netdev_priv(dev);
4757 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4758 unsigned int handled = 1;
4759
1da177e4
LT		 4760 /* In INTx mode, it is possible for the interrupt to arrive at
4761 * the CPU before the status block posted prior to the interrupt.
4762 * Reading the PCI State register will confirm whether the
4763 * interrupt is ours and will flush the status block.
4764 */
d18edcb2
MC		 4765 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4766 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4767 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4768 handled = 0;
f47c11ee 4769 goto out;
fac9b83e 4770 }
d18edcb2
MC		 4771 }
4772
4773 /*
4774 * Writing any value to intr-mbox-0 clears PCI INTA# and
4775 * chip-internal interrupt pending events.
4776 * Writing non-zero to intr-mbox-0 additional tells the
4777 * NIC to stop sending us irqs, engaging "in-intr-handler"
4778 * event coalescing.
c04cb347
MC		 4779 *
4780 * Flush the mailbox to de-assert the IRQ immediately to prevent
4781 * spurious interrupts. The flush impacts performance but
4782 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4783 */
c04cb347 4784 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4785 if (tg3_irq_sync(tp))
4786 goto out;
4787 sblk->status &= ~SD_STATUS_UPDATED;
4788 if (likely(tg3_has_work(tp))) {
4789 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4790 napi_schedule(&tp->napi);
d18edcb2
MC		 4791 } else {
4792 /* No work, shared interrupt perhaps? re-enable
4793 * interrupts, and flush that PCI write
4794 */
4795 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4796 0x00000000);
fac9b83e 4797 }
f47c11ee 4798out:
fac9b83e
DM		 4799 return IRQ_RETVAL(handled);
4800}
4801
7d12e780 4802static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4803{
4804 struct net_device *dev = dev_id;
4805 struct tg3 *tp = netdev_priv(dev);
4806 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4807 unsigned int handled = 1;
4808
fac9b83e
DM		 4809 /* In INTx mode, it is possible for the interrupt to arrive at
4810 * the CPU before the status block posted prior to the interrupt.
4811 * Reading the PCI State register will confirm whether the
4812 * interrupt is ours and will flush the status block.
4813 */
d18edcb2
MC		 4814 if (unlikely(sblk->status_tag == tp->last_tag)) {
4815 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4816 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4817 handled = 0;
f47c11ee 4818 goto out;
1da177e4 4819 }
d18edcb2
MC		 4820 }
4821
4822 /*
4823 * writing any value to intr-mbox-0 clears PCI INTA# and
4824 * chip-internal interrupt pending events.
4825 * writing non-zero to intr-mbox-0 additional tells the
4826 * NIC to stop sending us irqs, engaging "in-intr-handler"
4827 * event coalescing.
c04cb347
MC		 4828 *
4829 * Flush the mailbox to de-assert the IRQ immediately to prevent
4830 * spurious interrupts. The flush impacts performance but
4831 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4832 */
c04cb347 4833 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4834 if (tg3_irq_sync(tp))
4835 goto out;
288379f0 4836 if (napi_schedule_prep(&tp->napi)) {
d18edcb2
MC		 4837 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4838 /* Update last_tag to mark that this status has been
4839 * seen. Because interrupt may be shared, we may be
4840 * racing with tg3_poll(), so only update last_tag
4841 * if tg3_poll() is not scheduled.
4842 */
4843 tp->last_tag = sblk->status_tag;
288379f0 4844 __napi_schedule(&tp->napi);
1da177e4 4845 }
f47c11ee 4846out:
1da177e4
LT		 4847 return IRQ_RETVAL(handled);
4848}
4849
7938109f 4850/* ISR for interrupt test */
7d12e780 4851static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4852{
4853 struct net_device *dev = dev_id;
4854 struct tg3 *tp = netdev_priv(dev);
4855 struct tg3_hw_status *sblk = tp->hw_status;
4856
f9804ddb
MC		 4857 if ((sblk->status & SD_STATUS_UPDATED) ||
4858 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4859 tg3_disable_ints(tp);
7938109f
MC		 4860 return IRQ_RETVAL(1);
4861 }
4862 return IRQ_RETVAL(0);
4863}
4864
8e7a22e3 4865static int tg3_init_hw(struct tg3 *, int);
944d980e 4866static int tg3_halt(struct tg3 *, int, int);
1da177e4 4867
b9ec6c1b
MC		 4868/* Restart hardware after configuration changes, self-test, etc.
4869 * Invoked with tp->lock held.
4870 */
4871static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4872 __releases(tp->lock)
4873 __acquires(tp->lock)
b9ec6c1b
MC		 4874{
4875 int err;
4876
4877 err = tg3_init_hw(tp, reset_phy);
4878 if (err) {
4879 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4880 "aborting.\n", tp->dev->name);
4881 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4882 tg3_full_unlock(tp);
4883 del_timer_sync(&tp->timer);
4884 tp->irq_sync = 0;
bea3348e 4885 napi_enable(&tp->napi);
b9ec6c1b
MC		 4886 dev_close(tp->dev);
4887 tg3_full_lock(tp, 0);
4888 }
4889 return err;
4890}
4891
1da177e4
LT		 4892#ifdef CONFIG_NET_POLL_CONTROLLER
4893static void tg3_poll_controller(struct net_device *dev)
4894{
88b06bc2
MC		 4895 struct tg3 *tp = netdev_priv(dev);
4896
7d12e780 4897 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4898}
4899#endif
4900
c4028958 4901static void tg3_reset_task(struct work_struct *work)
1da177e4 4902{
c4028958 4903 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4904 int err;
1da177e4
LT		 4905 unsigned int restart_timer;
4906
7faa006f 4907 tg3_full_lock(tp, 0);
7faa006f
MC		 4908
4909 if (!netif_running(tp->dev)) {
7faa006f
MC		 4910 tg3_full_unlock(tp);
4911 return;
4912 }
4913
4914 tg3_full_unlock(tp);
4915
b02fd9e3
MC		 4916 tg3_phy_stop(tp);
4917
1da177e4
LT		 4918 tg3_netif_stop(tp);
4919
f47c11ee 4920 tg3_full_lock(tp, 1);
1da177e4
LT		 4921
4922 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4923 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4924
df3e6548
MC		 4925 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4926 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4927 tp->write32_rx_mbox = tg3_write_flush_reg32;
4928 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4929 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4930 }
4931
944d980e 4932 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4933 err = tg3_init_hw(tp, 1);
4934 if (err)
b9ec6c1b 4935 goto out;
1da177e4
LT		 4936
4937 tg3_netif_start(tp);
4938
1da177e4
LT		 4939 if (restart_timer)
4940 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4941
b9ec6c1b 4942out:
7faa006f 4943 tg3_full_unlock(tp);
b02fd9e3
MC		 4944
4945 if (!err)
4946 tg3_phy_start(tp);
1da177e4
LT		 4947}
4948
b0408751
MC		 4949static void tg3_dump_short_state(struct tg3 *tp)
4950{
4951 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4952 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4953 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4954 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4955}
4956
1da177e4
LT		 4957static void tg3_tx_timeout(struct net_device *dev)
4958{
4959 struct tg3 *tp = netdev_priv(dev);
4960
b0408751 4961 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4962 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4963 dev->name);
b0408751
MC		 4964 tg3_dump_short_state(tp);
4965 }
1da177e4
LT		 4966
4967 schedule_work(&tp->reset_task);
4968}
4969
c58ec932
MC		 4970/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4971static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4972{
4973 u32 base = (u32) mapping & 0xffffffff;
4974
4975 return ((base > 0xffffdcc0) &&
4976 (base + len + 8 < base));
4977}
4978
72f2afb8
MC		 4979/* Test for DMA addresses > 40-bit */
4980static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4981 int len)
4982{
4983#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4984 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 4985 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 4986 return 0;
4987#else
4988 return 0;
4989#endif
4990}
4991
1da177e4
LT		 4992static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4993
72f2afb8
MC		 4994/* Workaround 4GB and 40-bit hardware DMA bugs. */
4995static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 4996 u32 last_plus_one, u32 *start,
4997 u32 base_flags, u32 mss)
1da177e4 4998{
41588ba1 4999 struct sk_buff *new_skb;
c58ec932 5000 dma_addr_t new_addr = 0;
1da177e4 5001 u32 entry = *start;
c58ec932 5002 int i, ret = 0;
1da177e4 5003
41588ba1
MC		 5004 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5005 new_skb = skb_copy(skb, GFP_ATOMIC);
5006 else {
5007 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5008
5009 new_skb = skb_copy_expand(skb,
5010 skb_headroom(skb) + more_headroom,
5011 skb_tailroom(skb), GFP_ATOMIC);
5012 }
5013
1da177e4 5014 if (!new_skb) {
c58ec932
MC		 5015 ret = -1;
5016 } else {
5017 /* New SKB is guaranteed to be linear. */
5018 entry = *start;
90079ce8
DM		 5019 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5020 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5021
c58ec932
MC		 5022 /* Make sure new skb does not cross any 4G boundaries.
5023 * Drop the packet if it does.
5024 */
90079ce8 5025 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5026 if (!ret)
5027 skb_dma_unmap(&tp->pdev->dev, new_skb,
5028 DMA_TO_DEVICE);
c58ec932
MC		 5029 ret = -1;
5030 dev_kfree_skb(new_skb);
5031 new_skb = NULL;
5032 } else {
5033 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5034 base_flags, 1 | (mss << 1));
5035 *start = NEXT_TX(entry);
5036 }
1da177e4
LT		 5037 }
5038
1da177e4
LT		 5039 /* Now clean up the sw ring entries. */
5040 i = 0;
5041 while (entry != last_plus_one) {
1da177e4
LT		 5042 if (i == 0) {
5043 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5044 } else {
5045 tp->tx_buffers[entry].skb = NULL;
5046 }
5047 entry = NEXT_TX(entry);
5048 i++;
5049 }
5050
90079ce8 5051 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5052 dev_kfree_skb(skb);
5053
c58ec932 5054 return ret;
1da177e4
LT		 5055}
5056
5057static void tg3_set_txd(struct tg3 *tp, int entry,
5058 dma_addr_t mapping, int len, u32 flags,
5059 u32 mss_and_is_end)
5060{
5061 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5062 int is_end = (mss_and_is_end & 0x1);
5063 u32 mss = (mss_and_is_end >> 1);
5064 u32 vlan_tag = 0;
5065
5066 if (is_end)
5067 flags |= TXD_FLAG_END;
5068 if (flags & TXD_FLAG_VLAN) {
5069 vlan_tag = flags >> 16;
5070 flags &= 0xffff;
5071 }
5072 vlan_tag |= (mss << TXD_MSS_SHIFT);
5073
5074 txd->addr_hi = ((u64) mapping >> 32);
5075 txd->addr_lo = ((u64) mapping & 0xffffffff);
5076 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5077 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5078}
5079
5a6f3074
MC		 5080/* hard_start_xmit for devices that don't have any bugs and
5081 * support TG3_FLG2_HW_TSO_2 only.
5082 */
1da177e4 5083static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5084{
5085 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5086 u32 len, entry, base_flags, mss;
90079ce8
DM		 5087 struct skb_shared_info *sp;
5088 dma_addr_t mapping;
5a6f3074
MC		 5089
5090 len = skb_headlen(skb);
5091
00b70504 5092 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5093 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5094 * interrupt. Furthermore, IRQ processing runs lockless so we have
5095 * no IRQ context deadlocks to worry about either. Rejoice!
5096 */
1b2a7205 5097 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5098 if (!netif_queue_stopped(dev)) {
5099 netif_stop_queue(dev);
5100
5101 /* This is a hard error, log it. */
5102 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5103 "queue awake!\n", dev->name);
5104 }
5a6f3074
MC		 5105 return NETDEV_TX_BUSY;
5106 }
5107
5108 entry = tp->tx_prod;
5109 base_flags = 0;
5a6f3074 5110 mss = 0;
c13e3713 5111 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5112 int tcp_opt_len, ip_tcp_len;
5113
5114 if (skb_header_cloned(skb) &&
5115 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5116 dev_kfree_skb(skb);
5117 goto out_unlock;
5118 }
5119
b0026624
MC		 5120 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5121 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5122 else {
eddc9ec5
ACM		 5123 struct iphdr *iph = ip_hdr(skb);
5124
ab6a5bb6 5125 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5126 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5127
eddc9ec5
ACM		 5128 iph->check = 0;
5129 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5130 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5131 }
5a6f3074
MC		 5132
5133 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5134 TXD_FLAG_CPU_POST_DMA);
5135
aa8223c7 5136 tcp_hdr(skb)->check = 0;
5a6f3074 5137
5a6f3074 5138 }
84fa7933 5139 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5140 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5141#if TG3_VLAN_TAG_USED
5142 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5143 base_flags |= (TXD_FLAG_VLAN |
5144 (vlan_tx_tag_get(skb) << 16));
5145#endif
5146
90079ce8
DM		 5147 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5148 dev_kfree_skb(skb);
5149 goto out_unlock;
5150 }
5151
5152 sp = skb_shinfo(skb);
5153
5154 mapping = sp->dma_maps[0];
5a6f3074
MC		 5155
5156 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5157
5158 tg3_set_txd(tp, entry, mapping, len, base_flags,
5159 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5160
5161 entry = NEXT_TX(entry);
5162
5163 /* Now loop through additional data fragments, and queue them. */
5164 if (skb_shinfo(skb)->nr_frags > 0) {
5165 unsigned int i, last;
5166
5167 last = skb_shinfo(skb)->nr_frags - 1;
5168 for (i = 0; i <= last; i++) {
5169 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5170
5171 len = frag->size;
90079ce8 5172 mapping = sp->dma_maps[i + 1];
5a6f3074 5173 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5174
5175 tg3_set_txd(tp, entry, mapping, len,
5176 base_flags, (i == last) | (mss << 1));
5177
5178 entry = NEXT_TX(entry);
5179 }
5180 }
5181
5182 /* Packets are ready, update Tx producer idx local and on card. */
5183 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5184
5185 tp->tx_prod = entry;
1b2a7205 5186 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5187 netif_stop_queue(dev);
42952231 5188 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5189 netif_wake_queue(tp->dev);
5190 }
5191
5192out_unlock:
5193 mmiowb();
5a6f3074
MC		 5194
5195 dev->trans_start = jiffies;
5196
5197 return NETDEV_TX_OK;
5198}
5199
52c0fd83
MC		 5200static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5201
5202/* Use GSO to workaround a rare TSO bug that may be triggered when the
5203 * TSO header is greater than 80 bytes.
5204 */
5205static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5206{
5207 struct sk_buff *segs, *nskb;
5208
5209 /* Estimate the number of fragments in the worst case */
1b2a7205 5210 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5211 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5212 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5213 return NETDEV_TX_BUSY;
5214
5215 netif_wake_queue(tp->dev);
52c0fd83
MC		 5216 }
5217
5218 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5219 if (IS_ERR(segs))
52c0fd83
MC		 5220 goto tg3_tso_bug_end;
5221
5222 do {
5223 nskb = segs;
5224 segs = segs->next;
5225 nskb->next = NULL;
5226 tg3_start_xmit_dma_bug(nskb, tp->dev);
5227 } while (segs);
5228
5229tg3_tso_bug_end:
5230 dev_kfree_skb(skb);
5231
5232 return NETDEV_TX_OK;
5233}
52c0fd83 5234
5a6f3074
MC		 5235/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5236 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5237 */
5238static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5239{
5240 struct tg3 *tp = netdev_priv(dev);
1da177e4 5241 u32 len, entry, base_flags, mss;
90079ce8 5242 struct skb_shared_info *sp;
1da177e4 5243 int would_hit_hwbug;
90079ce8 5244 dma_addr_t mapping;
1da177e4
LT		 5245
5246 len = skb_headlen(skb);
5247
00b70504 5248 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5249 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5250 * interrupt. Furthermore, IRQ processing runs lockless so we have
5251 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5252 */
1b2a7205 5253 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5254 if (!netif_queue_stopped(dev)) {
5255 netif_stop_queue(dev);
5256
5257 /* This is a hard error, log it. */
5258 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5259 "queue awake!\n", dev->name);
5260 }
1da177e4
LT		 5261 return NETDEV_TX_BUSY;
5262 }
5263
5264 entry = tp->tx_prod;
5265 base_flags = 0;
84fa7933 5266 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5267 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5268 mss = 0;
c13e3713 5269 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5270 struct iphdr *iph;
52c0fd83 5271 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5272
5273 if (skb_header_cloned(skb) &&
5274 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5275 dev_kfree_skb(skb);
5276 goto out_unlock;
5277 }
5278
ab6a5bb6 5279 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5280 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5281
52c0fd83
MC		 5282 hdr_len = ip_tcp_len + tcp_opt_len;
5283 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5284 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5285 return (tg3_tso_bug(tp, skb));
5286
1da177e4
LT		 5287 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5288 TXD_FLAG_CPU_POST_DMA);
5289
eddc9ec5
ACM		 5290 iph = ip_hdr(skb);
5291 iph->check = 0;
5292 iph->tot_len = htons(mss + hdr_len);
1da177e4 5293 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5294 tcp_hdr(skb)->check = 0;
1da177e4 5295 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5296 } else
5297 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5298 iph->daddr, 0,
5299 IPPROTO_TCP,
5300 0);
1da177e4
LT		 5301
5302 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5303 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5304 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5305 int tsflags;
5306
eddc9ec5 5307 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5308 mss |= (tsflags << 11);
5309 }
5310 } else {
eddc9ec5 5311 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5312 int tsflags;
5313
eddc9ec5 5314 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5315 base_flags |= tsflags << 12;
5316 }
5317 }
5318 }
1da177e4
LT		 5319#if TG3_VLAN_TAG_USED
5320 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5321 base_flags |= (TXD_FLAG_VLAN |
5322 (vlan_tx_tag_get(skb) << 16));
5323#endif
5324
90079ce8
DM		 5325 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5326 dev_kfree_skb(skb);
5327 goto out_unlock;
5328 }
5329
5330 sp = skb_shinfo(skb);
5331
5332 mapping = sp->dma_maps[0];
1da177e4
LT		 5333
5334 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5335
5336 would_hit_hwbug = 0;
5337
41588ba1
MC		 5338 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5339 would_hit_hwbug = 1;
5340 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5341 would_hit_hwbug = 1;
1da177e4
LT		 5342
5343 tg3_set_txd(tp, entry, mapping, len, base_flags,
5344 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5345
5346 entry = NEXT_TX(entry);
5347
5348 /* Now loop through additional data fragments, and queue them. */
5349 if (skb_shinfo(skb)->nr_frags > 0) {
5350 unsigned int i, last;
5351
5352 last = skb_shinfo(skb)->nr_frags - 1;
5353 for (i = 0; i <= last; i++) {
5354 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5355
5356 len = frag->size;
90079ce8 5357 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5358
5359 tp->tx_buffers[entry].skb = NULL;
1da177e4 5360
c58ec932
MC		 5361 if (tg3_4g_overflow_test(mapping, len))
5362 would_hit_hwbug = 1;
1da177e4 5363
72f2afb8
MC		 5364 if (tg3_40bit_overflow_test(tp, mapping, len))
5365 would_hit_hwbug = 1;
5366
1da177e4
LT		 5367 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5368 tg3_set_txd(tp, entry, mapping, len,
5369 base_flags, (i == last)|(mss << 1));
5370 else
5371 tg3_set_txd(tp, entry, mapping, len,
5372 base_flags, (i == last));
5373
5374 entry = NEXT_TX(entry);
5375 }
5376 }
5377
5378 if (would_hit_hwbug) {
5379 u32 last_plus_one = entry;
5380 u32 start;
1da177e4 5381
c58ec932
MC		 5382 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5383 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5384
5385 /* If the workaround fails due to memory/mapping
5386 * failure, silently drop this packet.
5387 */
72f2afb8 5388 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5389 &start, base_flags, mss))
1da177e4
LT		 5390 goto out_unlock;
5391
5392 entry = start;
5393 }
5394
5395 /* Packets are ready, update Tx producer idx local and on card. */
5396 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5397
5398 tp->tx_prod = entry;
1b2a7205 5399 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5400 netif_stop_queue(dev);
42952231 5401 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5402 netif_wake_queue(tp->dev);
5403 }
1da177e4
LT		 5404
5405out_unlock:
5406 mmiowb();
1da177e4
LT		 5407
5408 dev->trans_start = jiffies;
5409
5410 return NETDEV_TX_OK;
5411}
5412
5413static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5414 int new_mtu)
5415{
5416 dev->mtu = new_mtu;
5417
ef7f5ec0 5418 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5419 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5420 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5421 ethtool_op_set_tso(dev, 0);
5422 }
5423 else
5424 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5425 } else {
a4e2b347 5426 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5427 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5428 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5429 }
1da177e4
LT		 5430}
5431
5432static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5433{
5434 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5435 int err;
1da177e4
LT		 5436
5437 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5438 return -EINVAL;
5439
5440 if (!netif_running(dev)) {
5441 /* We'll just catch it later when the
5442 * device is up'd.
5443 */
5444 tg3_set_mtu(dev, tp, new_mtu);
5445 return 0;
5446 }
5447
b02fd9e3
MC		 5448 tg3_phy_stop(tp);
5449
1da177e4 5450 tg3_netif_stop(tp);
f47c11ee
DM		 5451
5452 tg3_full_lock(tp, 1);
1da177e4 5453
944d980e 5454 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5455
5456 tg3_set_mtu(dev, tp, new_mtu);
5457
b9ec6c1b 5458 err = tg3_restart_hw(tp, 0);
1da177e4 5459
b9ec6c1b
MC		 5460 if (!err)
5461 tg3_netif_start(tp);
1da177e4 5462
f47c11ee 5463 tg3_full_unlock(tp);
1da177e4 5464
b02fd9e3
MC		 5465 if (!err)
5466 tg3_phy_start(tp);
5467
b9ec6c1b 5468 return err;
1da177e4
LT		 5469}
5470
5471/* Free up pending packets in all rx/tx rings.
5472 *
5473 * The chip has been shut down and the driver detached from
5474 * the networking, so no interrupts or new tx packets will
5475 * end up in the driver. tp->{tx,}lock is not held and we are not
5476 * in an interrupt context and thus may sleep.
5477 */
5478static void tg3_free_rings(struct tg3 *tp)
5479{
5480 struct ring_info *rxp;
5481 int i;
5482
5483 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5484 rxp = &tp->rx_std_buffers[i];
5485
5486 if (rxp->skb == NULL)
5487 continue;
5488 pci_unmap_single(tp->pdev,
5489 pci_unmap_addr(rxp, mapping),
7e72aad4 5490 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5491 PCI_DMA_FROMDEVICE);
5492 dev_kfree_skb_any(rxp->skb);
5493 rxp->skb = NULL;
5494 }
5495
5496 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5497 rxp = &tp->rx_jumbo_buffers[i];
5498
5499 if (rxp->skb == NULL)
5500 continue;
5501 pci_unmap_single(tp->pdev,
5502 pci_unmap_addr(rxp, mapping),
5503 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5504 PCI_DMA_FROMDEVICE);
5505 dev_kfree_skb_any(rxp->skb);
5506 rxp->skb = NULL;
5507 }
5508
5509 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5510 struct tx_ring_info *txp;
5511 struct sk_buff *skb;
1da177e4
LT		 5512
5513 txp = &tp->tx_buffers[i];
5514 skb = txp->skb;
5515
5516 if (skb == NULL) {
5517 i++;
5518 continue;
5519 }
5520
90079ce8 5521 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5522
90079ce8 5523 txp->skb = NULL;
1da177e4 5524
90079ce8 5525 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5526
5527 dev_kfree_skb_any(skb);
5528 }
5529}
5530
5531/* Initialize tx/rx rings for packet processing.
5532 *
5533 * The chip has been shut down and the driver detached from
5534 * the networking, so no interrupts or new tx packets will
5535 * end up in the driver. tp->{tx,}lock are held and thus
5536 * we may not sleep.
5537 */
32d8c572 5538static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5539{
5540 u32 i;
5541
5542 /* Free up all the SKBs. */
5543 tg3_free_rings(tp);
5544
5545 /* Zero out all descriptors. */
5546 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5547 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5548 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5549 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5550
7e72aad4 5551 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5552 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5553 (tp->dev->mtu > ETH_DATA_LEN))
5554 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5555
1da177e4
LT		 5556 /* Initialize invariants of the rings, we only set this
5557 * stuff once. This works because the card does not
5558 * write into the rx buffer posting rings.
5559 */
5560 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5561 struct tg3_rx_buffer_desc *rxd;
5562
5563 rxd = &tp->rx_std[i];
7e72aad4 5564 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5565 << RXD_LEN_SHIFT;
5566 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5567 rxd->opaque = (RXD_OPAQUE_RING_STD |
5568 (i << RXD_OPAQUE_INDEX_SHIFT));
5569 }
5570
0f893dc6 5571 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5572 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5573 struct tg3_rx_buffer_desc *rxd;
5574
5575 rxd = &tp->rx_jumbo[i];
5576 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5577 << RXD_LEN_SHIFT;
5578 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5579 RXD_FLAG_JUMBO;
5580 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5581 (i << RXD_OPAQUE_INDEX_SHIFT));
5582 }
5583 }
5584
5585 /* Now allocate fresh SKBs for each rx ring. */
5586 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5587 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5588 printk(KERN_WARNING PFX
5589 "%s: Using a smaller RX standard ring, "
5590 "only %d out of %d buffers were allocated "
5591 "successfully.\n",
5592 tp->dev->name, i, tp->rx_pending);
5593 if (i == 0)
5594 return -ENOMEM;
5595 tp->rx_pending = i;
1da177e4 5596 break;
32d8c572 5597 }
1da177e4
LT		 5598 }
5599
0f893dc6 5600 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5601 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5602 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5603 -1, i) < 0) {
5604 printk(KERN_WARNING PFX
5605 "%s: Using a smaller RX jumbo ring, "
5606 "only %d out of %d buffers were "
5607 "allocated successfully.\n",
5608 tp->dev->name, i, tp->rx_jumbo_pending);
5609 if (i == 0) {
5610 tg3_free_rings(tp);
5611 return -ENOMEM;
5612 }
5613 tp->rx_jumbo_pending = i;
1da177e4 5614 break;
32d8c572 5615 }
1da177e4
LT		 5616 }
5617 }
32d8c572 5618 return 0;
1da177e4
LT		 5619}
5620
5621/*
5622 * Must not be invoked with interrupt sources disabled and
5623 * the hardware shutdown down.
5624 */
5625static void tg3_free_consistent(struct tg3 *tp)
5626{
b4558ea9
JJ		 5627 kfree(tp->rx_std_buffers);
5628 tp->rx_std_buffers = NULL;
1da177e4
LT		 5629 if (tp->rx_std) {
5630 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5631 tp->rx_std, tp->rx_std_mapping);
5632 tp->rx_std = NULL;
5633 }
5634 if (tp->rx_jumbo) {
5635 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5636 tp->rx_jumbo, tp->rx_jumbo_mapping);
5637 tp->rx_jumbo = NULL;
5638 }
5639 if (tp->rx_rcb) {
5640 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5641 tp->rx_rcb, tp->rx_rcb_mapping);
5642 tp->rx_rcb = NULL;
5643 }
5644 if (tp->tx_ring) {
5645 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5646 tp->tx_ring, tp->tx_desc_mapping);
5647 tp->tx_ring = NULL;
5648 }
5649 if (tp->hw_status) {
5650 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5651 tp->hw_status, tp->status_mapping);
5652 tp->hw_status = NULL;
5653 }
5654 if (tp->hw_stats) {
5655 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5656 tp->hw_stats, tp->stats_mapping);
5657 tp->hw_stats = NULL;
5658 }
5659}
5660
5661/*
5662 * Must not be invoked with interrupt sources disabled and
5663 * the hardware shutdown down. Can sleep.
5664 */
5665static int tg3_alloc_consistent(struct tg3 *tp)
5666{
bd2b3343 5667 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5668 (TG3_RX_RING_SIZE +
5669 TG3_RX_JUMBO_RING_SIZE)) +
5670 (sizeof(struct tx_ring_info) *
5671 TG3_TX_RING_SIZE),
5672 GFP_KERNEL);
5673 if (!tp->rx_std_buffers)
5674 return -ENOMEM;
5675
1da177e4
LT		 5676 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5677 tp->tx_buffers = (struct tx_ring_info *)
5678 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5679
5680 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5681 &tp->rx_std_mapping);
5682 if (!tp->rx_std)
5683 goto err_out;
5684
5685 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5686 &tp->rx_jumbo_mapping);
5687
5688 if (!tp->rx_jumbo)
5689 goto err_out;
5690
5691 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5692 &tp->rx_rcb_mapping);
5693 if (!tp->rx_rcb)
5694 goto err_out;
5695
5696 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5697 &tp->tx_desc_mapping);
5698 if (!tp->tx_ring)
5699 goto err_out;
5700
5701 tp->hw_status = pci_alloc_consistent(tp->pdev,
5702 TG3_HW_STATUS_SIZE,
5703 &tp->status_mapping);
5704 if (!tp->hw_status)
5705 goto err_out;
5706
5707 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5708 sizeof(struct tg3_hw_stats),
5709 &tp->stats_mapping);
5710 if (!tp->hw_stats)
5711 goto err_out;
5712
5713 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5714 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5715
5716 return 0;
5717
5718err_out:
5719 tg3_free_consistent(tp);
5720 return -ENOMEM;
5721}
5722
5723#define MAX_WAIT_CNT 1000
5724
5725/* To stop a block, clear the enable bit and poll till it
5726 * clears. tp->lock is held.
5727 */
b3b7d6be 5728static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5729{
5730 unsigned int i;
5731 u32 val;
5732
5733 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5734 switch (ofs) {
5735 case RCVLSC_MODE:
5736 case DMAC_MODE:
5737 case MBFREE_MODE:
5738 case BUFMGR_MODE:
5739 case MEMARB_MODE:
5740 /* We can't enable/disable these bits of the
5741 * 5705/5750, just say success.
5742 */
5743 return 0;
5744
5745 default:
5746 break;
855e1111 5747 }
1da177e4
LT		 5748 }
5749
5750 val = tr32(ofs);
5751 val &= ~enable_bit;
5752 tw32_f(ofs, val);
5753
5754 for (i = 0; i < MAX_WAIT_CNT; i++) {
5755 udelay(100);
5756 val = tr32(ofs);
5757 if ((val & enable_bit) == 0)
5758 break;
5759 }
5760
b3b7d6be 5761 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5762 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5763 "ofs=%lx enable_bit=%x\n",
5764 ofs, enable_bit);
5765 return -ENODEV;
5766 }
5767
5768 return 0;
5769}
5770
5771/* tp->lock is held. */
b3b7d6be 5772static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5773{
5774 int i, err;
5775
5776 tg3_disable_ints(tp);
5777
5778 tp->rx_mode &= ~RX_MODE_ENABLE;
5779 tw32_f(MAC_RX_MODE, tp->rx_mode);
5780 udelay(10);
5781
b3b7d6be
DM		 5782 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5783 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5784 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5785 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5786 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5787 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5788
5789 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5790 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5791 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5792 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5793 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5794 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5795 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5796
5797 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5798 tw32_f(MAC_MODE, tp->mac_mode);
5799 udelay(40);
5800
5801 tp->tx_mode &= ~TX_MODE_ENABLE;
5802 tw32_f(MAC_TX_MODE, tp->tx_mode);
5803
5804 for (i = 0; i < MAX_WAIT_CNT; i++) {
5805 udelay(100);
5806 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5807 break;
5808 }
5809 if (i >= MAX_WAIT_CNT) {
5810 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5811 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5812 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5813 err |= -ENODEV;
1da177e4
LT		 5814 }
5815
e6de8ad1 5816 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5817 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5818 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5819
5820 tw32(FTQ_RESET, 0xffffffff);
5821 tw32(FTQ_RESET, 0x00000000);
5822
b3b7d6be
DM		 5823 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5824 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5825
5826 if (tp->hw_status)
5827 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5828 if (tp->hw_stats)
5829 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5830
1da177e4
LT		 5831 return err;
5832}
5833
0d3031d9
MC		 5834static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5835{
5836 int i;
5837 u32 apedata;
5838
5839 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5840 if (apedata != APE_SEG_SIG_MAGIC)
5841 return;
5842
5843 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5844 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5845 return;
5846
5847 /* Wait for up to 1 millisecond for APE to service previous event. */
5848 for (i = 0; i < 10; i++) {
5849 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5850 return;
5851
5852 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5853
5854 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5855 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5856 event | APE_EVENT_STATUS_EVENT_PENDING);
5857
5858 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5859
5860 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5861 break;
5862
5863 udelay(100);
5864 }
5865
5866 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5867 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5868}
5869
5870static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5871{
5872 u32 event;
5873 u32 apedata;
5874
5875 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5876 return;
5877
5878 switch (kind) {
5879 case RESET_KIND_INIT:
5880 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5881 APE_HOST_SEG_SIG_MAGIC);
5882 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5883 APE_HOST_SEG_LEN_MAGIC);
5884 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5885 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5886 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5887 APE_HOST_DRIVER_ID_MAGIC);
5888 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5889 APE_HOST_BEHAV_NO_PHYLOCK);
5890
5891 event = APE_EVENT_STATUS_STATE_START;
5892 break;
5893 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5894 /* With the interface we are currently using,
5895 * APE does not track driver state. Wiping
5896 * out the HOST SEGMENT SIGNATURE forces
5897 * the APE to assume OS absent status.
5898 */
5899 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5900
0d3031d9
MC		 5901 event = APE_EVENT_STATUS_STATE_UNLOAD;
5902 break;
5903 case RESET_KIND_SUSPEND:
5904 event = APE_EVENT_STATUS_STATE_SUSPEND;
5905 break;
5906 default:
5907 return;
5908 }
5909
5910 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5911
5912 tg3_ape_send_event(tp, event);
5913}
5914
1da177e4
LT		 5915/* tp->lock is held. */
5916static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5917{
f49639e6
DM		 5918 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5919 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5920
5921 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5922 switch (kind) {
5923 case RESET_KIND_INIT:
5924 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5925 DRV_STATE_START);
5926 break;
5927
5928 case RESET_KIND_SHUTDOWN:
5929 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5930 DRV_STATE_UNLOAD);
5931 break;
5932
5933 case RESET_KIND_SUSPEND:
5934 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5935 DRV_STATE_SUSPEND);
5936 break;
5937
5938 default:
5939 break;
855e1111 5940 }
1da177e4 5941 }
0d3031d9
MC		 5942
5943 if (kind == RESET_KIND_INIT ||
5944 kind == RESET_KIND_SUSPEND)
5945 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5946}
5947
5948/* tp->lock is held. */
5949static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5950{
5951 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5952 switch (kind) {
5953 case RESET_KIND_INIT:
5954 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5955 DRV_STATE_START_DONE);
5956 break;
5957
5958 case RESET_KIND_SHUTDOWN:
5959 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5960 DRV_STATE_UNLOAD_DONE);
5961 break;
5962
5963 default:
5964 break;
855e1111 5965 }
1da177e4 5966 }
0d3031d9
MC		 5967
5968 if (kind == RESET_KIND_SHUTDOWN)
5969 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5970}
5971
5972/* tp->lock is held. */
5973static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5974{
5975 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5976 switch (kind) {
5977 case RESET_KIND_INIT:
5978 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5979 DRV_STATE_START);
5980 break;
5981
5982 case RESET_KIND_SHUTDOWN:
5983 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5984 DRV_STATE_UNLOAD);
5985 break;
5986
5987 case RESET_KIND_SUSPEND:
5988 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5989 DRV_STATE_SUSPEND);
5990 break;
5991
5992 default:
5993 break;
855e1111 5994 }
1da177e4
LT		 5995 }
5996}
5997
7a6f4369
MC		 5998static int tg3_poll_fw(struct tg3 *tp)
5999{
6000 int i;
6001 u32 val;
6002
b5d3772c 6003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6004 /* Wait up to 20ms for init done. */
6005 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6006 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6007 return 0;
0ccead18 6008 udelay(100);
b5d3772c
MC		 6009 }
6010 return -ENODEV;
6011 }
6012
7a6f4369
MC		 6013 /* Wait for firmware initialization to complete. */
6014 for (i = 0; i < 100000; i++) {
6015 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6016 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6017 break;
6018 udelay(10);
6019 }
6020
6021 /* Chip might not be fitted with firmware. Some Sun onboard
6022 * parts are configured like that. So don't signal the timeout
6023 * of the above loop as an error, but do report the lack of
6024 * running firmware once.
6025 */
6026 if (i >= 100000 &&
6027 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6028 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6029
6030 printk(KERN_INFO PFX "%s: No firmware running.\n",
6031 tp->dev->name);
6032 }
6033
6034 return 0;
6035}
6036
ee6a99b5
MC		 6037/* Save PCI command register before chip reset */
6038static void tg3_save_pci_state(struct tg3 *tp)
6039{
8a6eac90 6040 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6041}
6042
6043/* Restore PCI state after chip reset */
6044static void tg3_restore_pci_state(struct tg3 *tp)
6045{
6046 u32 val;
6047
6048 /* Re-enable indirect register accesses. */
6049 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6050 tp->misc_host_ctrl);
6051
6052 /* Set MAX PCI retry to zero. */
6053 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6054 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6055 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6056 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6057 /* Allow reads and writes to the APE register and memory space. */
6058 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6059 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6060 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6061 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6062
8a6eac90 6063 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6064
fcb389df
MC		 6065 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6066 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6067 pcie_set_readrq(tp->pdev, 4096);
6068 else {
6069 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6070 tp->pci_cacheline_sz);
6071 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6072 tp->pci_lat_timer);
6073 }
114342f2 6074 }
5f5c51e3 6075
ee6a99b5 6076 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6077 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6078 u16 pcix_cmd;
6079
6080 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6081 &pcix_cmd);
6082 pcix_cmd &= ~PCI_X_CMD_ERO;
6083 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6084 pcix_cmd);
6085 }
ee6a99b5
MC		 6086
6087 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6088
6089 /* Chip reset on 5780 will reset MSI enable bit,
6090 * so need to restore it.
6091 */
6092 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6093 u16 ctrl;
6094
6095 pci_read_config_word(tp->pdev,
6096 tp->msi_cap + PCI_MSI_FLAGS,
6097 &ctrl);
6098 pci_write_config_word(tp->pdev,
6099 tp->msi_cap + PCI_MSI_FLAGS,
6100 ctrl | PCI_MSI_FLAGS_ENABLE);
6101 val = tr32(MSGINT_MODE);
6102 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6103 }
6104 }
6105}
6106
1da177e4
LT		 6107static void tg3_stop_fw(struct tg3 *);
6108
6109/* tp->lock is held. */
6110static int tg3_chip_reset(struct tg3 *tp)
6111{
6112 u32 val;
1ee582d8 6113 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6114 int err;
1da177e4 6115
f49639e6
DM		 6116 tg3_nvram_lock(tp);
6117
158d7abd
MC		 6118 tg3_mdio_stop(tp);
6119
77b483f1
MC		 6120 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6121
f49639e6
DM		 6122 /* No matching tg3_nvram_unlock() after this because
6123 * chip reset below will undo the nvram lock.
6124 */
6125 tp->nvram_lock_cnt = 0;
1da177e4 6126
ee6a99b5
MC		 6127 /* GRC_MISC_CFG core clock reset will clear the memory
6128 * enable bit in PCI register 4 and the MSI enable bit
6129 * on some chips, so we save relevant registers here.
6130 */
6131 tg3_save_pci_state(tp);
6132
d9ab5ad1 6133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6134 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6135 tw32(GRC_FASTBOOT_PC, 0);
6136
1da177e4
LT		 6137 /*
6138 * We must avoid the readl() that normally takes place.
6139 * It locks machines, causes machine checks, and other
6140 * fun things. So, temporarily disable the 5701
6141 * hardware workaround, while we do the reset.
6142 */
1ee582d8
MC		 6143 write_op = tp->write32;
6144 if (write_op == tg3_write_flush_reg32)
6145 tp->write32 = tg3_write32;
1da177e4 6146
d18edcb2
MC		 6147 /* Prevent the irq handler from reading or writing PCI registers
6148 * during chip reset when the memory enable bit in the PCI command
6149 * register may be cleared. The chip does not generate interrupt
6150 * at this time, but the irq handler may still be called due to irq
6151 * sharing or irqpoll.
6152 */
6153 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6154 if (tp->hw_status) {
6155 tp->hw_status->status = 0;
6156 tp->hw_status->status_tag = 0;
6157 }
d18edcb2
MC		 6158 tp->last_tag = 0;
6159 smp_mb();
6160 synchronize_irq(tp->pdev->irq);
6161
1da177e4
LT		 6162 /* do the reset */
6163 val = GRC_MISC_CFG_CORECLK_RESET;
6164
6165 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6166 if (tr32(0x7e2c) == 0x60) {
6167 tw32(0x7e2c, 0x20);
6168 }
6169 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6170 tw32(GRC_MISC_CFG, (1 << 29));
6171 val |= (1 << 29);
6172 }
6173 }
6174
b5d3772c
MC		 6175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6176 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6177 tw32(GRC_VCPU_EXT_CTRL,
6178 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6179 }
6180
1da177e4
LT		 6181 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6182 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6183 tw32(GRC_MISC_CFG, val);
6184
1ee582d8
MC		 6185 /* restore 5701 hardware bug workaround write method */
6186 tp->write32 = write_op;
1da177e4
LT		 6187
6188 /* Unfortunately, we have to delay before the PCI read back.
6189 * Some 575X chips even will not respond to a PCI cfg access
6190 * when the reset command is given to the chip.
6191 *
6192 * How do these hardware designers expect things to work
6193 * properly if the PCI write is posted for a long period
6194 * of time? It is always necessary to have some method by
6195 * which a register read back can occur to push the write
6196 * out which does the reset.
6197 *
6198 * For most tg3 variants the trick below was working.
6199 * Ho hum...
6200 */
6201 udelay(120);
6202
6203 /* Flush PCI posted writes. The normal MMIO registers
6204 * are inaccessible at this time so this is the only
6205 * way to make this reliably (actually, this is no longer
6206 * the case, see above). I tried to use indirect
6207 * register read/write but this upset some 5701 variants.
6208 */
6209 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6210
6211 udelay(120);
6212
5e7dfd0f 6213 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6214 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6215 int i;
6216 u32 cfg_val;
6217
6218 /* Wait for link training to complete. */
6219 for (i = 0; i < 5000; i++)
6220 udelay(100);
6221
6222 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6223 pci_write_config_dword(tp->pdev, 0xc4,
6224 cfg_val | (1 << 15));
6225 }
5e7dfd0f
MC		 6226
6227 /* Set PCIE max payload size to 128 bytes and
6228 * clear the "no snoop" and "relaxed ordering" bits.
6229 */
6230 pci_write_config_word(tp->pdev,
6231 tp->pcie_cap + PCI_EXP_DEVCTL,
6232 0);
6233
6234 pcie_set_readrq(tp->pdev, 4096);
6235
6236 /* Clear error status */
6237 pci_write_config_word(tp->pdev,
6238 tp->pcie_cap + PCI_EXP_DEVSTA,
6239 PCI_EXP_DEVSTA_CED |
6240 PCI_EXP_DEVSTA_NFED |
6241 PCI_EXP_DEVSTA_FED |
6242 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6243 }
6244
ee6a99b5 6245 tg3_restore_pci_state(tp);
1da177e4 6246
d18edcb2
MC		 6247 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6248
ee6a99b5
MC		 6249 val = 0;
6250 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6251 val = tr32(MEMARB_MODE);
ee6a99b5 6252 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6253
6254 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6255 tg3_stop_fw(tp);
6256 tw32(0x5000, 0x400);
6257 }
6258
6259 tw32(GRC_MODE, tp->grc_mode);
6260
6261 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6262 val = tr32(0xc4);
1da177e4
LT		 6263
6264 tw32(0xc4, val | (1 << 15));
6265 }
6266
6267 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6268 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6269 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6270 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6271 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6272 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6273 }
6274
6275 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6276 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6277 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6278 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6279 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6280 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6281 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6282 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6283 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6284 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6285 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6286 } else
6287 tw32_f(MAC_MODE, 0);
6288 udelay(40);
6289
158d7abd
MC		 6290 tg3_mdio_start(tp);
6291
77b483f1
MC		 6292 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6293
7a6f4369
MC		 6294 err = tg3_poll_fw(tp);
6295 if (err)
6296 return err;
1da177e4
LT		 6297
6298 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6299 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6300 val = tr32(0x7c00);
1da177e4
LT		 6301
6302 tw32(0x7c00, val | (1 << 25));
6303 }
6304
6305 /* Reprobe ASF enable state. */
6306 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6307 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6308 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6309 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6310 u32 nic_cfg;
6311
6312 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6313 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6314 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6315 tp->last_event_jiffies = jiffies;
cbf46853 6316 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6317 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6318 }
6319 }
6320
6321 return 0;
6322}
6323
6324/* tp->lock is held. */
6325static void tg3_stop_fw(struct tg3 *tp)
6326{
0d3031d9
MC		 6327 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6328 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6329 /* Wait for RX cpu to ACK the previous event. */
6330 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6331
6332 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6333
6334 tg3_generate_fw_event(tp);
1da177e4 6335
7c5026aa
MC		 6336 /* Wait for RX cpu to ACK this event. */
6337 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6338 }
6339}
6340
6341/* tp->lock is held. */
944d980e 6342static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6343{
6344 int err;
6345
6346 tg3_stop_fw(tp);
6347
944d980e 6348 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6349
b3b7d6be 6350 tg3_abort_hw(tp, silent);
1da177e4
LT		 6351 err = tg3_chip_reset(tp);
6352
944d980e
MC		 6353 tg3_write_sig_legacy(tp, kind);
6354 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6355
6356 if (err)
6357 return err;
6358
6359 return 0;
6360}
6361
1da177e4
LT		 6362#define RX_CPU_SCRATCH_BASE 0x30000
6363#define RX_CPU_SCRATCH_SIZE 0x04000
6364#define TX_CPU_SCRATCH_BASE 0x34000
6365#define TX_CPU_SCRATCH_SIZE 0x04000
6366
6367/* tp->lock is held. */
6368static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6369{
6370 int i;
6371
5d9428de
ES		 6372 BUG_ON(offset == TX_CPU_BASE &&
6373 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6374
b5d3772c
MC		 6375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6376 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6377
6378 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6379 return 0;
6380 }
1da177e4
LT		 6381 if (offset == RX_CPU_BASE) {
6382 for (i = 0; i < 10000; i++) {
6383 tw32(offset + CPU_STATE, 0xffffffff);
6384 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6385 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6386 break;
6387 }
6388
6389 tw32(offset + CPU_STATE, 0xffffffff);
6390 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6391 udelay(10);
6392 } else {
6393 for (i = 0; i < 10000; i++) {
6394 tw32(offset + CPU_STATE, 0xffffffff);
6395 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6396 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6397 break;
6398 }
6399 }
6400
6401 if (i >= 10000) {
6402 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6403 "and %s CPU\n",
6404 tp->dev->name,
6405 (offset == RX_CPU_BASE ? "RX" : "TX"));
6406 return -ENODEV;
6407 }
ec41c7df
MC		 6408
6409 /* Clear firmware's nvram arbitration. */
6410 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6411 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6412 return 0;
6413}
6414
6415struct fw_info {
077f849d
JSR		 6416 unsigned int fw_base;
6417 unsigned int fw_len;
6418 const __be32 *fw_data;
1da177e4
LT		 6419};
6420
6421/* tp->lock is held. */
6422static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6423 int cpu_scratch_size, struct fw_info *info)
6424{
ec41c7df 6425 int err, lock_err, i;
1da177e4
LT		 6426 void (*write_op)(struct tg3 *, u32, u32);
6427
6428 if (cpu_base == TX_CPU_BASE &&
6429 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6430 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6431 "TX cpu firmware on %s which is 5705.\n",
6432 tp->dev->name);
6433 return -EINVAL;
6434 }
6435
6436 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6437 write_op = tg3_write_mem;
6438 else
6439 write_op = tg3_write_indirect_reg32;
6440
1b628151
MC		 6441 /* It is possible that bootcode is still loading at this point.
6442 * Get the nvram lock first before halting the cpu.
6443 */
ec41c7df 6444 lock_err = tg3_nvram_lock(tp);
1da177e4 6445 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6446 if (!lock_err)
6447 tg3_nvram_unlock(tp);
1da177e4
LT		 6448 if (err)
6449 goto out;
6450
6451 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6452 write_op(tp, cpu_scratch_base + i, 0);
6453 tw32(cpu_base + CPU_STATE, 0xffffffff);
6454 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6455 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6456 write_op(tp, (cpu_scratch_base +
077f849d 6457 (info->fw_base & 0xffff) +
1da177e4 6458 (i * sizeof(u32))),
077f849d 6459 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6460
6461 err = 0;
6462
6463out:
1da177e4
LT		 6464 return err;
6465}
6466
6467/* tp->lock is held. */
6468static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6469{
6470 struct fw_info info;
077f849d 6471 const __be32 *fw_data;
1da177e4
LT		 6472 int err, i;
6473
077f849d
JSR		 6474 fw_data = (void *)tp->fw->data;
6475
6476 /* Firmware blob starts with version numbers, followed by
6477 start address and length. We are setting complete length.
6478 length = end_address_of_bss - start_address_of_text.
6479 Remainder is the blob to be loaded contiguously
6480 from start address. */
6481
6482 info.fw_base = be32_to_cpu(fw_data[1]);
6483 info.fw_len = tp->fw->size - 12;
6484 info.fw_data = &fw_data[3];
1da177e4
LT		 6485
6486 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6487 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6488 &info);
6489 if (err)
6490 return err;
6491
6492 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6493 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6494 &info);
6495 if (err)
6496 return err;
6497
6498 /* Now startup only the RX cpu. */
6499 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6500 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6501
6502 for (i = 0; i < 5; i++) {
077f849d 6503 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6504 break;
6505 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6506 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6507 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6508 udelay(1000);
6509 }
6510 if (i >= 5) {
6511 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6512 "to set RX CPU PC, is %08x should be %08x\n",
6513 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6514 info.fw_base);
1da177e4
LT		 6515 return -ENODEV;
6516 }
6517 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6518 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6519
6520 return 0;
6521}
6522
1da177e4 6523/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6524
6525/* tp->lock is held. */
6526static int tg3_load_tso_firmware(struct tg3 *tp)
6527{
6528 struct fw_info info;
077f849d 6529 const __be32 *fw_data;
1da177e4
LT		 6530 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6531 int err, i;
6532
6533 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6534 return 0;
6535
077f849d
JSR		 6536 fw_data = (void *)tp->fw->data;
6537
6538 /* Firmware blob starts with version numbers, followed by
6539 start address and length. We are setting complete length.
6540 length = end_address_of_bss - start_address_of_text.
6541 Remainder is the blob to be loaded contiguously
6542 from start address. */
6543
6544 info.fw_base = be32_to_cpu(fw_data[1]);
6545 cpu_scratch_size = tp->fw_len;
6546 info.fw_len = tp->fw->size - 12;
6547 info.fw_data = &fw_data[3];
6548
1da177e4 6549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6550 cpu_base = RX_CPU_BASE;
6551 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6552 } else {
1da177e4
LT		 6553 cpu_base = TX_CPU_BASE;
6554 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6555 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6556 }
6557
6558 err = tg3_load_firmware_cpu(tp, cpu_base,
6559 cpu_scratch_base, cpu_scratch_size,
6560 &info);
6561 if (err)
6562 return err;
6563
6564 /* Now startup the cpu. */
6565 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6566 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6567
6568 for (i = 0; i < 5; i++) {
077f849d 6569 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6570 break;
6571 tw32(cpu_base + CPU_STATE, 0xffffffff);
6572 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6573 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6574 udelay(1000);
6575 }
6576 if (i >= 5) {
6577 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6578 "to set CPU PC, is %08x should be %08x\n",
6579 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6580 info.fw_base);
1da177e4
LT		 6581 return -ENODEV;
6582 }
6583 tw32(cpu_base + CPU_STATE, 0xffffffff);
6584 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6585 return 0;
6586}
6587
1da177e4 6588
1da177e4
LT		 6589static int tg3_set_mac_addr(struct net_device *dev, void *p)
6590{
6591 struct tg3 *tp = netdev_priv(dev);
6592 struct sockaddr *addr = p;
986e0aeb 6593 int err = 0, skip_mac_1 = 0;
1da177e4 6594
f9804ddb
MC		 6595 if (!is_valid_ether_addr(addr->sa_data))
6596 return -EINVAL;
6597
1da177e4
LT		 6598 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6599
e75f7c90
MC		 6600 if (!netif_running(dev))
6601 return 0;
6602
58712ef9 6603 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6604 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6605
986e0aeb
MC		 6606 addr0_high = tr32(MAC_ADDR_0_HIGH);
6607 addr0_low = tr32(MAC_ADDR_0_LOW);
6608 addr1_high = tr32(MAC_ADDR_1_HIGH);
6609 addr1_low = tr32(MAC_ADDR_1_LOW);
6610
6611 /* Skip MAC addr 1 if ASF is using it. */
6612 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6613 !(addr1_high == 0 && addr1_low == 0))
6614 skip_mac_1 = 1;
58712ef9 6615 }
986e0aeb
MC		 6616 spin_lock_bh(&tp->lock);
6617 __tg3_set_mac_addr(tp, skip_mac_1);
6618 spin_unlock_bh(&tp->lock);
1da177e4 6619
b9ec6c1b 6620 return err;
1da177e4
LT		 6621}
6622
6623/* tp->lock is held. */
6624static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6625 dma_addr_t mapping, u32 maxlen_flags,
6626 u32 nic_addr)
6627{
6628 tg3_write_mem(tp,
6629 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6630 ((u64) mapping >> 32));
6631 tg3_write_mem(tp,
6632 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6633 ((u64) mapping & 0xffffffff));
6634 tg3_write_mem(tp,
6635 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6636 maxlen_flags);
6637
6638 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6639 tg3_write_mem(tp,
6640 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6641 nic_addr);
6642}
6643
6644static void __tg3_set_rx_mode(struct net_device *);
d244c892 6645static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6646{
6647 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6648 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6649 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6650 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6651 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6652 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6653 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6654 }
6655 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6656 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6657 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6658 u32 val = ec->stats_block_coalesce_usecs;
6659
6660 if (!netif_carrier_ok(tp->dev))
6661 val = 0;
6662
6663 tw32(HOSTCC_STAT_COAL_TICKS, val);
6664 }
6665}
1da177e4
LT		 6666
6667/* tp->lock is held. */
8e7a22e3 6668static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6669{
6670 u32 val, rdmac_mode;
6671 int i, err, limit;
6672
6673 tg3_disable_ints(tp);
6674
6675 tg3_stop_fw(tp);
6676
6677 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6678
6679 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6680 tg3_abort_hw(tp, 1);
1da177e4
LT		 6681 }
6682
dd477003
MC		 6683 if (reset_phy &&
6684 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6685 tg3_phy_reset(tp);
6686
1da177e4
LT		 6687 err = tg3_chip_reset(tp);
6688 if (err)
6689 return err;
6690
6691 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6692
bcb37f6c 6693 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6694 val = tr32(TG3_CPMU_CTRL);
6695 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6696 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6697
6698 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6699 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6700 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6701 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6702
6703 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6704 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6705 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6706 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6707
6708 val = tr32(TG3_CPMU_HST_ACC);
6709 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6710 val |= CPMU_HST_ACC_MACCLK_6_25;
6711 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6712 }
6713
1da177e4
LT		 6714 /* This works around an issue with Athlon chipsets on
6715 * B3 tigon3 silicon. This bit has no effect on any
6716 * other revision. But do not set this on PCI Express
795d01c5 6717 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6718 */
795d01c5
MC		 6719 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6720 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6721 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6722 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6723 }
1da177e4
LT		 6724
6725 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6726 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6727 val = tr32(TG3PCI_PCISTATE);
6728 val |= PCISTATE_RETRY_SAME_DMA;
6729 tw32(TG3PCI_PCISTATE, val);
6730 }
6731
0d3031d9
MC		 6732 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6733 /* Allow reads and writes to the
6734 * APE register and memory space.
6735 */
6736 val = tr32(TG3PCI_PCISTATE);
6737 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6738 PCISTATE_ALLOW_APE_SHMEM_WR;
6739 tw32(TG3PCI_PCISTATE, val);
6740 }
6741
1da177e4
LT		 6742 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6743 /* Enable some hw fixes. */
6744 val = tr32(TG3PCI_MSI_DATA);
6745 val |= (1 << 26) | (1 << 28) | (1 << 29);
6746 tw32(TG3PCI_MSI_DATA, val);
6747 }
6748
6749 /* Descriptor ring init may make accesses to the
6750 * NIC SRAM area to setup the TX descriptors, so we
6751 * can only do this after the hardware has been
6752 * successfully reset.
6753 */
32d8c572
MC		 6754 err = tg3_init_rings(tp);
6755 if (err)
6756 return err;
1da177e4 6757
9936bcf6 6758 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6759 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6760 /* This value is determined during the probe time DMA
6761 * engine test, tg3_test_dma.
6762 */
6763 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6764 }
1da177e4
LT		 6765
6766 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6767 GRC_MODE_4X_NIC_SEND_RINGS |
6768 GRC_MODE_NO_TX_PHDR_CSUM |
6769 GRC_MODE_NO_RX_PHDR_CSUM);
6770 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6771
6772 /* Pseudo-header checksum is done by hardware logic and not
6773 * the offload processers, so make the chip do the pseudo-
6774 * header checksums on receive. For transmit it is more
6775 * convenient to do the pseudo-header checksum in software
6776 * as Linux does that on transmit for us in all cases.
6777 */
6778 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6779
6780 tw32(GRC_MODE,
6781 tp->grc_mode |
6782 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6783
6784 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6785 val = tr32(GRC_MISC_CFG);
6786 val &= ~0xff;
6787 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6788 tw32(GRC_MISC_CFG, val);
6789
6790 /* Initialize MBUF/DESC pool. */
cbf46853 6791 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6792 /* Do nothing. */
6793 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6794 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6796 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6797 else
6798 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6799 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6800 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6801 }
1da177e4
LT		 6802 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6803 int fw_len;
6804
077f849d 6805 fw_len = tp->fw_len;
1da177e4
LT		 6806 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6807 tw32(BUFMGR_MB_POOL_ADDR,
6808 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6809 tw32(BUFMGR_MB_POOL_SIZE,
6810 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6811 }
1da177e4 6812
0f893dc6 6813 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6814 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6815 tp->bufmgr_config.mbuf_read_dma_low_water);
6816 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6817 tp->bufmgr_config.mbuf_mac_rx_low_water);
6818 tw32(BUFMGR_MB_HIGH_WATER,
6819 tp->bufmgr_config.mbuf_high_water);
6820 } else {
6821 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6822 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6823 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6824 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6825 tw32(BUFMGR_MB_HIGH_WATER,
6826 tp->bufmgr_config.mbuf_high_water_jumbo);
6827 }
6828 tw32(BUFMGR_DMA_LOW_WATER,
6829 tp->bufmgr_config.dma_low_water);
6830 tw32(BUFMGR_DMA_HIGH_WATER,
6831 tp->bufmgr_config.dma_high_water);
6832
6833 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6834 for (i = 0; i < 2000; i++) {
6835 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6836 break;
6837 udelay(10);
6838 }
6839 if (i >= 2000) {
6840 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6841 tp->dev->name);
6842 return -ENODEV;
6843 }
6844
6845 /* Setup replenish threshold. */
f92905de
MC		 6846 val = tp->rx_pending / 8;
6847 if (val == 0)
6848 val = 1;
6849 else if (val > tp->rx_std_max_post)
6850 val = tp->rx_std_max_post;
b5d3772c
MC		 6851 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6852 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6853 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6854
6855 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6856 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6857 }
f92905de
MC		 6858
6859 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6860
6861 /* Initialize TG3_BDINFO's at:
6862 * RCVDBDI_STD_BD: standard eth size rx ring
6863 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6864 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6865 *
6866 * like so:
6867 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6868 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6869 * ring attribute flags
6870 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6871 *
6872 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6873 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6874 *
6875 * The size of each ring is fixed in the firmware, but the location is
6876 * configurable.
6877 */
6878 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6879 ((u64) tp->rx_std_mapping >> 32));
6880 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6881 ((u64) tp->rx_std_mapping & 0xffffffff));
6882 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6883 NIC_SRAM_RX_BUFFER_DESC);
6884
6885 /* Don't even try to program the JUMBO/MINI buffer descriptor
6886 * configs on 5705.
6887 */
6888 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6889 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6890 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6891 } else {
6892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6893 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6894
6895 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6896 BDINFO_FLAGS_DISABLED);
6897
6898 /* Setup replenish threshold. */
6899 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6900
0f893dc6 6901 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6902 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6903 ((u64) tp->rx_jumbo_mapping >> 32));
6904 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6905 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6906 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6907 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6908 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6909 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6910 } else {
6911 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6912 BDINFO_FLAGS_DISABLED);
6913 }
6914
6915 }
6916
6917 /* There is only one send ring on 5705/5750, no need to explicitly
6918 * disable the others.
6919 */
6920 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6921 /* Clear out send RCB ring in SRAM. */
6922 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6923 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6924 BDINFO_FLAGS_DISABLED);
6925 }
6926
6927 tp->tx_prod = 0;
6928 tp->tx_cons = 0;
6929 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6930 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6931
6932 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6933 tp->tx_desc_mapping,
6934 (TG3_TX_RING_SIZE <<
6935 BDINFO_FLAGS_MAXLEN_SHIFT),
6936 NIC_SRAM_TX_BUFFER_DESC);
6937
6938 /* There is only one receive return ring on 5705/5750, no need
6939 * to explicitly disable the others.
6940 */
6941 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6942 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6943 i += TG3_BDINFO_SIZE) {
6944 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6945 BDINFO_FLAGS_DISABLED);
6946 }
6947 }
6948
6949 tp->rx_rcb_ptr = 0;
6950 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6951
6952 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6953 tp->rx_rcb_mapping,
6954 (TG3_RX_RCB_RING_SIZE(tp) <<
6955 BDINFO_FLAGS_MAXLEN_SHIFT),
6956 0);
6957
6958 tp->rx_std_ptr = tp->rx_pending;
6959 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6960 tp->rx_std_ptr);
6961
0f893dc6 6962 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6963 tp->rx_jumbo_pending : 0;
6964 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6965 tp->rx_jumbo_ptr);
6966
6967 /* Initialize MAC address and backoff seed. */
986e0aeb 6968 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6969
6970 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 6971 tw32(MAC_RX_MTU_SIZE,
6972 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 6973
6974 /* The slot time is changed by tg3_setup_phy if we
6975 * run at gigabit with half duplex.
6976 */
6977 tw32(MAC_TX_LENGTHS,
6978 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6979 (6 << TX_LENGTHS_IPG_SHIFT) |
6980 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6981
6982 /* Receive rules. */
6983 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6984 tw32(RCVLPC_CONFIG, 0x0181);
6985
6986 /* Calculate RDMAC_MODE setting early, we need it to determine
6987 * the RCVLPC_STATE_ENABLE mask.
6988 */
6989 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6990 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6991 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6992 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6993 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6994
57e6983c 6995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 6996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 6998 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6999 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7000 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7001
85e94ced
MC		 7002 /* If statement applies to 5705 and 5750 PCI devices only */
7003 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7004 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7005 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7006 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7008 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7009 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7010 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7011 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7012 }
7013 }
7014
85e94ced
MC		 7015 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7016 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7017
1da177e4 7018 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7019 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7020
7021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7023 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7024
7025 /* Receive/send statistics. */
1661394e
MC		 7026 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7027 val = tr32(RCVLPC_STATS_ENABLE);
7028 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7029 tw32(RCVLPC_STATS_ENABLE, val);
7030 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7031 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7032 val = tr32(RCVLPC_STATS_ENABLE);
7033 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7034 tw32(RCVLPC_STATS_ENABLE, val);
7035 } else {
7036 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7037 }
7038 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7039 tw32(SNDDATAI_STATSENAB, 0xffffff);
7040 tw32(SNDDATAI_STATSCTRL,
7041 (SNDDATAI_SCTRL_ENABLE |
7042 SNDDATAI_SCTRL_FASTUPD));
7043
7044 /* Setup host coalescing engine. */
7045 tw32(HOSTCC_MODE, 0);
7046 for (i = 0; i < 2000; i++) {
7047 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7048 break;
7049 udelay(10);
7050 }
7051
d244c892 7052 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7053
7054 /* set status block DMA address */
7055 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7056 ((u64) tp->status_mapping >> 32));
7057 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7058 ((u64) tp->status_mapping & 0xffffffff));
7059
7060 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7061 /* Status/statistics block address. See tg3_timer,
7062 * the tg3_periodic_fetch_stats call there, and
7063 * tg3_get_stats to see how this works for 5705/5750 chips.
7064 */
1da177e4
LT		 7065 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7066 ((u64) tp->stats_mapping >> 32));
7067 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7068 ((u64) tp->stats_mapping & 0xffffffff));
7069 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7070 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7071 }
7072
7073 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7074
7075 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7076 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7077 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7078 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7079
7080 /* Clear statistics/status block in chip, and status block in ram. */
7081 for (i = NIC_SRAM_STATS_BLK;
7082 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7083 i += sizeof(u32)) {
7084 tg3_write_mem(tp, i, 0);
7085 udelay(40);
7086 }
7087 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7088
c94e3941
MC		 7089 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7090 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7091 /* reset to prevent losing 1st rx packet intermittently */
7092 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7093 udelay(10);
7094 }
7095
3bda1258
MC		 7096 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7097 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7098 else
7099 tp->mac_mode = 0;
7100 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7101 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7102 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7103 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7104 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7105 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7106 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7107 udelay(40);
7108
314fba34 7109 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7110 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7111 * register to preserve the GPIO settings for LOMs. The GPIOs,
7112 * whether used as inputs or outputs, are set by boot code after
7113 * reset.
7114 */
9d26e213 7115 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7116 u32 gpio_mask;
7117
9d26e213
MC		 7118 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7119 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7120 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7121
7122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7123 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7124 GRC_LCLCTRL_GPIO_OUTPUT3;
7125
af36e6b6
MC		 7126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7127 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7128
aaf84465 7129 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7130 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7131
7132 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7133 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7134 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7135 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7136 }
1da177e4
LT		 7137 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7138 udelay(100);
7139
09ee929c 7140 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 7141 tp->last_tag = 0;
1da177e4
LT		 7142
7143 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7144 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7145 udelay(40);
7146 }
7147
7148 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7149 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7150 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7151 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7152 WDMAC_MODE_LNGREAD_ENAB);
7153
85e94ced
MC		 7154 /* If statement applies to 5705 and 5750 PCI devices only */
7155 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7156 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7158 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7159 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7160 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7161 /* nothing */
7162 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7163 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7164 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7165 val |= WDMAC_MODE_RX_ACCEL;
7166 }
7167 }
7168
d9ab5ad1 7169 /* Enable host coalescing bug fix */
321d32a0 7170 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7171 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7172
1da177e4
LT		 7173 tw32_f(WDMAC_MODE, val);
7174 udelay(40);
7175
9974a356
MC		 7176 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7177 u16 pcix_cmd;
7178
7179 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7180 &pcix_cmd);
1da177e4 7181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7182 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7183 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7184 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7185 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7186 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7187 }
9974a356
MC		 7188 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7189 pcix_cmd);
1da177e4
LT		 7190 }
7191
7192 tw32_f(RDMAC_MODE, rdmac_mode);
7193 udelay(40);
7194
7195 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7196 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7197 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7198
7199 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7200 tw32(SNDDATAC_MODE,
7201 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7202 else
7203 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7204
1da177e4
LT		 7205 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7206 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7207 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7208 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7209 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7210 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7211 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7212 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7213
7214 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7215 err = tg3_load_5701_a0_firmware_fix(tp);
7216 if (err)
7217 return err;
7218 }
7219
1da177e4
LT		 7220 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7221 err = tg3_load_tso_firmware(tp);
7222 if (err)
7223 return err;
7224 }
1da177e4
LT		 7225
7226 tp->tx_mode = TX_MODE_ENABLE;
7227 tw32_f(MAC_TX_MODE, tp->tx_mode);
7228 udelay(100);
7229
7230 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7231 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7232 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7233
1da177e4
LT		 7234 tw32_f(MAC_RX_MODE, tp->rx_mode);
7235 udelay(10);
7236
1da177e4
LT		 7237 tw32(MAC_LED_CTRL, tp->led_ctrl);
7238
7239 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7240 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7241 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7242 udelay(10);
7243 }
7244 tw32_f(MAC_RX_MODE, tp->rx_mode);
7245 udelay(10);
7246
7247 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7248 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7249 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7250 /* Set drive transmission level to 1.2V */
7251 /* only if the signal pre-emphasis bit is not set */
7252 val = tr32(MAC_SERDES_CFG);
7253 val &= 0xfffff000;
7254 val |= 0x880;
7255 tw32(MAC_SERDES_CFG, val);
7256 }
7257 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7258 tw32(MAC_SERDES_CFG, 0x616000);
7259 }
7260
7261 /* Prevent chip from dropping frames when flow control
7262 * is enabled.
7263 */
7264 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7265
7266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7267 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7268 /* Use hardware link auto-negotiation */
7269 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7270 }
7271
d4d2c558
MC		 7272 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7273 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7274 u32 tmp;
7275
7276 tmp = tr32(SERDES_RX_CTRL);
7277 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7278 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7279 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7280 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7281 }
7282
dd477003
MC		 7283 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7284 if (tp->link_config.phy_is_low_power) {
7285 tp->link_config.phy_is_low_power = 0;
7286 tp->link_config.speed = tp->link_config.orig_speed;
7287 tp->link_config.duplex = tp->link_config.orig_duplex;
7288 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7289 }
1da177e4 7290
dd477003
MC		 7291 err = tg3_setup_phy(tp, 0);
7292 if (err)
7293 return err;
1da177e4 7294
dd477003
MC		 7295 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7296 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7297 u32 tmp;
7298
7299 /* Clear CRC stats. */
7300 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7301 tg3_writephy(tp, MII_TG3_TEST1,
7302 tmp | MII_TG3_TEST1_CRC_EN);
7303 tg3_readphy(tp, 0x14, &tmp);
7304 }
1da177e4
LT		 7305 }
7306 }
7307
7308 __tg3_set_rx_mode(tp->dev);
7309
7310 /* Initialize receive rules. */
7311 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7312 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7313 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7314 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7315
4cf78e4f 7316 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7317 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7318 limit = 8;
7319 else
7320 limit = 16;
7321 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7322 limit -= 4;
7323 switch (limit) {
7324 case 16:
7325 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7326 case 15:
7327 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7328 case 14:
7329 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7330 case 13:
7331 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7332 case 12:
7333 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7334 case 11:
7335 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7336 case 10:
7337 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7338 case 9:
7339 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7340 case 8:
7341 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7342 case 7:
7343 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7344 case 6:
7345 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7346 case 5:
7347 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7348 case 4:
7349 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7350 case 3:
7351 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7352 case 2:
7353 case 1:
7354
7355 default:
7356 break;
855e1111 7357 }
1da177e4 7358
9ce768ea
MC		 7359 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7360 /* Write our heartbeat update interval to APE. */
7361 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7362 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7363
1da177e4
LT		 7364 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7365
1da177e4
LT		 7366 return 0;
7367}
7368
7369/* Called at device open time to get the chip ready for
7370 * packet processing. Invoked with tp->lock held.
7371 */
8e7a22e3 7372static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7373{
1da177e4
LT		 7374 tg3_switch_clocks(tp);
7375
7376 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7377
2f751b67 7378 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7379}
7380
7381#define TG3_STAT_ADD32(PSTAT, REG) \
7382do { u32 __val = tr32(REG); \
7383 (PSTAT)->low += __val; \
7384 if ((PSTAT)->low < __val) \
7385 (PSTAT)->high += 1; \
7386} while (0)
7387
7388static void tg3_periodic_fetch_stats(struct tg3 *tp)
7389{
7390 struct tg3_hw_stats *sp = tp->hw_stats;
7391
7392 if (!netif_carrier_ok(tp->dev))
7393 return;
7394
7395 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7396 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7397 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7398 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7399 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7400 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7401 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7402 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7403 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7404 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7405 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7406 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7407 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7408
7409 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7410 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7411 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7412 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7413 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7414 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7415 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7416 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7417 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7418 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7419 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7420 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7421 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7422 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7423
7424 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7425 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7426 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7427}
7428
7429static void tg3_timer(unsigned long __opaque)
7430{
7431 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7432
f475f163
MC		 7433 if (tp->irq_sync)
7434 goto restart_timer;
7435
f47c11ee 7436 spin_lock(&tp->lock);
1da177e4 7437
fac9b83e
DM		 7438 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7439 /* All of this garbage is because when using non-tagged
7440 * IRQ status the mailbox/status_block protocol the chip
7441 * uses with the cpu is race prone.
7442 */
7443 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7444 tw32(GRC_LOCAL_CTRL,
7445 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7446 } else {
7447 tw32(HOSTCC_MODE, tp->coalesce_mode |
7448 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7449 }
1da177e4 7450
fac9b83e
DM		 7451 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7452 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7453 spin_unlock(&tp->lock);
fac9b83e
DM		 7454 schedule_work(&tp->reset_task);
7455 return;
7456 }
1da177e4
LT		 7457 }
7458
1da177e4
LT		 7459 /* This part only runs once per second. */
7460 if (!--tp->timer_counter) {
fac9b83e
DM		 7461 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7462 tg3_periodic_fetch_stats(tp);
7463
1da177e4
LT		 7464 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7465 u32 mac_stat;
7466 int phy_event;
7467
7468 mac_stat = tr32(MAC_STATUS);
7469
7470 phy_event = 0;
7471 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7472 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7473 phy_event = 1;
7474 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7475 phy_event = 1;
7476
7477 if (phy_event)
7478 tg3_setup_phy(tp, 0);
7479 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7480 u32 mac_stat = tr32(MAC_STATUS);
7481 int need_setup = 0;
7482
7483 if (netif_carrier_ok(tp->dev) &&
7484 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7485 need_setup = 1;
7486 }
7487 if (! netif_carrier_ok(tp->dev) &&
7488 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7489 MAC_STATUS_SIGNAL_DET))) {
7490 need_setup = 1;
7491 }
7492 if (need_setup) {
3d3ebe74
MC		 7493 if (!tp->serdes_counter) {
7494 tw32_f(MAC_MODE,
7495 (tp->mac_mode &
7496 ~MAC_MODE_PORT_MODE_MASK));
7497 udelay(40);
7498 tw32_f(MAC_MODE, tp->mac_mode);
7499 udelay(40);
7500 }
1da177e4
LT		 7501 tg3_setup_phy(tp, 0);
7502 }
747e8f8b
MC		 7503 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7504 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7505
7506 tp->timer_counter = tp->timer_multiplier;
7507 }
7508
130b8e4d
MC		 7509 /* Heartbeat is only sent once every 2 seconds.
7510 *
7511 * The heartbeat is to tell the ASF firmware that the host
7512 * driver is still alive. In the event that the OS crashes,
7513 * ASF needs to reset the hardware to free up the FIFO space
7514 * that may be filled with rx packets destined for the host.
7515 * If the FIFO is full, ASF will no longer function properly.
7516 *
7517 * Unintended resets have been reported on real time kernels
7518 * where the timer doesn't run on time. Netpoll will also have
7519 * same problem.
7520 *
7521 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7522 * to check the ring condition when the heartbeat is expiring
7523 * before doing the reset. This will prevent most unintended
7524 * resets.
7525 */
1da177e4 7526 if (!--tp->asf_counter) {
bc7959b2
MC		 7527 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7528 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7529 tg3_wait_for_event_ack(tp);
7530
bbadf503 7531 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7532 FWCMD_NICDRV_ALIVE3);
bbadf503 7533 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7534 /* 5 seconds timeout */
bbadf503 7535 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7536
7537 tg3_generate_fw_event(tp);
1da177e4
LT		 7538 }
7539 tp->asf_counter = tp->asf_multiplier;
7540 }
7541
f47c11ee 7542 spin_unlock(&tp->lock);
1da177e4 7543
f475f163 7544restart_timer:
1da177e4
LT		 7545 tp->timer.expires = jiffies + tp->timer_offset;
7546 add_timer(&tp->timer);
7547}
7548
81789ef5 7549static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7550{
7d12e780 7551 irq_handler_t fn;
fcfa0a32
MC		 7552 unsigned long flags;
7553 struct net_device *dev = tp->dev;
7554
7555 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7556 fn = tg3_msi;
7557 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7558 fn = tg3_msi_1shot;
1fb9df5d 7559 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7560 } else {
7561 fn = tg3_interrupt;
7562 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7563 fn = tg3_interrupt_tagged;
1fb9df5d 7564 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7565 }
7566 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7567}
7568
7938109f
MC		 7569static int tg3_test_interrupt(struct tg3 *tp)
7570{
7571 struct net_device *dev = tp->dev;
b16250e3 7572 int err, i, intr_ok = 0;
7938109f 7573
d4bc3927
MC		 7574 if (!netif_running(dev))
7575 return -ENODEV;
7576
7938109f
MC		 7577 tg3_disable_ints(tp);
7578
7579 free_irq(tp->pdev->irq, dev);
7580
7581 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7582 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7583 if (err)
7584 return err;
7585
38f3843e 7586 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7587 tg3_enable_ints(tp);
7588
7589 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7590 HOSTCC_MODE_NOW);
7591
7592 for (i = 0; i < 5; i++) {
b16250e3
MC		 7593 u32 int_mbox, misc_host_ctrl;
7594
09ee929c
MC		 7595 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7596 TG3_64BIT_REG_LOW);
b16250e3
MC		 7597 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7598
7599 if ((int_mbox != 0) ||
7600 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7601 intr_ok = 1;
7938109f 7602 break;
b16250e3
MC		 7603 }
7604
7938109f
MC		 7605 msleep(10);
7606 }
7607
7608 tg3_disable_ints(tp);
7609
7610 free_irq(tp->pdev->irq, dev);
6aa20a22 7611
fcfa0a32 7612 err = tg3_request_irq(tp);
7938109f
MC		 7613
7614 if (err)
7615 return err;
7616
b16250e3 7617 if (intr_ok)
7938109f
MC		 7618 return 0;
7619
7620 return -EIO;
7621}
7622
7623/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7624 * successfully restored
7625 */
7626static int tg3_test_msi(struct tg3 *tp)
7627{
7628 struct net_device *dev = tp->dev;
7629 int err;
7630 u16 pci_cmd;
7631
7632 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7633 return 0;
7634
7635 /* Turn off SERR reporting in case MSI terminates with Master
7636 * Abort.
7637 */
7638 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7639 pci_write_config_word(tp->pdev, PCI_COMMAND,
7640 pci_cmd & ~PCI_COMMAND_SERR);
7641
7642 err = tg3_test_interrupt(tp);
7643
7644 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7645
7646 if (!err)
7647 return 0;
7648
7649 /* other failures */
7650 if (err != -EIO)
7651 return err;
7652
7653 /* MSI test failed, go back to INTx mode */
7654 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7655 "switching to INTx mode. Please report this failure to "
7656 "the PCI maintainer and include system chipset information.\n",
7657 tp->dev->name);
7658
7659 free_irq(tp->pdev->irq, dev);
7660 pci_disable_msi(tp->pdev);
7661
7662 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7663
fcfa0a32 7664 err = tg3_request_irq(tp);
7938109f
MC		 7665 if (err)
7666 return err;
7667
7668 /* Need to reset the chip because the MSI cycle may have terminated
7669 * with Master Abort.
7670 */
f47c11ee 7671 tg3_full_lock(tp, 1);
7938109f 7672
944d980e 7673 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7674 err = tg3_init_hw(tp, 1);
7938109f 7675
f47c11ee 7676 tg3_full_unlock(tp);
7938109f
MC		 7677
7678 if (err)
7679 free_irq(tp->pdev->irq, dev);
7680
7681 return err;
7682}
7683
9e9fd12d
MC		 7684static int tg3_request_firmware(struct tg3 *tp)
7685{
7686 const __be32 *fw_data;
7687
7688 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7689 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7690 tp->dev->name, tp->fw_needed);
7691 return -ENOENT;
7692 }
7693
7694 fw_data = (void *)tp->fw->data;
7695
7696 /* Firmware blob starts with version numbers, followed by
7697 * start address and _full_ length including BSS sections
7698 * (which must be longer than the actual data, of course
7699 */
7700
7701 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7702 if (tp->fw_len < (tp->fw->size - 12)) {
7703 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7704 tp->dev->name, tp->fw_len, tp->fw_needed);
7705 release_firmware(tp->fw);
7706 tp->fw = NULL;
7707 return -EINVAL;
7708 }
7709
7710 /* We no longer need firmware; we have it. */
7711 tp->fw_needed = NULL;
7712 return 0;
7713}
7714
1da177e4
LT		 7715static int tg3_open(struct net_device *dev)
7716{
7717 struct tg3 *tp = netdev_priv(dev);
7718 int err;
7719
9e9fd12d
MC		 7720 if (tp->fw_needed) {
7721 err = tg3_request_firmware(tp);
7722 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7723 if (err)
7724 return err;
7725 } else if (err) {
7726 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7727 tp->dev->name);
7728 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7729 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7730 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7731 tp->dev->name);
7732 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7733 }
7734 }
7735
c49a1561
MC		 7736 netif_carrier_off(tp->dev);
7737
bc1c7567 7738 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7739 if (err)
bc1c7567 7740 return err;
2f751b67
MC		 7741
7742 tg3_full_lock(tp, 0);
bc1c7567 7743
1da177e4
LT		 7744 tg3_disable_ints(tp);
7745 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7746
f47c11ee 7747 tg3_full_unlock(tp);
1da177e4
LT		 7748
7749 /* The placement of this call is tied
7750 * to the setup and use of Host TX descriptors.
7751 */
7752 err = tg3_alloc_consistent(tp);
7753 if (err)
7754 return err;
7755
7544b097 7756 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7757 /* All MSI supporting chips should support tagged
7758 * status. Assert that this is the case.
7759 */
7760 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7761 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7762 "Not using MSI.\n", tp->dev->name);
7763 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7764 u32 msi_mode;
7765
7766 msi_mode = tr32(MSGINT_MODE);
7767 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7768 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7769 }
7770 }
fcfa0a32 7771 err = tg3_request_irq(tp);
1da177e4
LT		 7772
7773 if (err) {
88b06bc2
MC		 7774 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7775 pci_disable_msi(tp->pdev);
7776 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7777 }
1da177e4
LT		 7778 tg3_free_consistent(tp);
7779 return err;
7780 }
7781
bea3348e
SH		 7782 napi_enable(&tp->napi);
7783
f47c11ee 7784 tg3_full_lock(tp, 0);
1da177e4 7785
8e7a22e3 7786 err = tg3_init_hw(tp, 1);
1da177e4 7787 if (err) {
944d980e 7788 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7789 tg3_free_rings(tp);
7790 } else {
fac9b83e
DM		 7791 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7792 tp->timer_offset = HZ;
7793 else
7794 tp->timer_offset = HZ / 10;
7795
7796 BUG_ON(tp->timer_offset > HZ);
7797 tp->timer_counter = tp->timer_multiplier =
7798 (HZ / tp->timer_offset);
7799 tp->asf_counter = tp->asf_multiplier =
28fbef78 7800 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7801
7802 init_timer(&tp->timer);
7803 tp->timer.expires = jiffies + tp->timer_offset;
7804 tp->timer.data = (unsigned long) tp;
7805 tp->timer.function = tg3_timer;
1da177e4
LT		 7806 }
7807
f47c11ee 7808 tg3_full_unlock(tp);
1da177e4
LT		 7809
7810 if (err) {
bea3348e 7811 napi_disable(&tp->napi);
88b06bc2
MC		 7812 free_irq(tp->pdev->irq, dev);
7813 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7814 pci_disable_msi(tp->pdev);
7815 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7816 }
1da177e4
LT		 7817 tg3_free_consistent(tp);
7818 return err;
7819 }
7820
7938109f
MC		 7821 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7822 err = tg3_test_msi(tp);
fac9b83e 7823
7938109f 7824 if (err) {
f47c11ee 7825 tg3_full_lock(tp, 0);
7938109f
MC		 7826
7827 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7828 pci_disable_msi(tp->pdev);
7829 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7830 }
944d980e 7831 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7832 tg3_free_rings(tp);
7833 tg3_free_consistent(tp);
7834
f47c11ee 7835 tg3_full_unlock(tp);
7938109f 7836
bea3348e
SH		 7837 napi_disable(&tp->napi);
7838
7938109f
MC		 7839 return err;
7840 }
fcfa0a32
MC		 7841
7842 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7843 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7844 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7845
b5d3772c
MC		 7846 tw32(PCIE_TRANSACTION_CFG,
7847 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7848 }
7849 }
7938109f
MC		 7850 }
7851
b02fd9e3
MC		 7852 tg3_phy_start(tp);
7853
f47c11ee 7854 tg3_full_lock(tp, 0);
1da177e4 7855
7938109f
MC		 7856 add_timer(&tp->timer);
7857 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7858 tg3_enable_ints(tp);
7859
f47c11ee 7860 tg3_full_unlock(tp);
1da177e4
LT		 7861
7862 netif_start_queue(dev);
7863
7864 return 0;
7865}
7866
7867#if 0
7868/*static*/ void tg3_dump_state(struct tg3 *tp)
7869{
7870 u32 val32, val32_2, val32_3, val32_4, val32_5;
7871 u16 val16;
7872 int i;
7873
7874 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7875 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7876 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7877 val16, val32);
7878
7879 /* MAC block */
7880 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7881 tr32(MAC_MODE), tr32(MAC_STATUS));
7882 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7883 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7884 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7885 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7886 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7887 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7888
7889 /* Send data initiator control block */
7890 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7891 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7892 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7893 tr32(SNDDATAI_STATSCTRL));
7894
7895 /* Send data completion control block */
7896 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7897
7898 /* Send BD ring selector block */
7899 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7900 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7901
7902 /* Send BD initiator control block */
7903 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7904 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7905
7906 /* Send BD completion control block */
7907 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7908
7909 /* Receive list placement control block */
7910 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7911 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7912 printk(" RCVLPC_STATSCTRL[%08x]\n",
7913 tr32(RCVLPC_STATSCTRL));
7914
7915 /* Receive data and receive BD initiator control block */
7916 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7917 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7918
7919 /* Receive data completion control block */
7920 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7921 tr32(RCVDCC_MODE));
7922
7923 /* Receive BD initiator control block */
7924 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7925 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7926
7927 /* Receive BD completion control block */
7928 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7929 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7930
7931 /* Receive list selector control block */
7932 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7933 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7934
7935 /* Mbuf cluster free block */
7936 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7937 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7938
7939 /* Host coalescing control block */
7940 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7941 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7942 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7943 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7944 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7945 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7946 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7947 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7948 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7949 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7950 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7951 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7952
7953 /* Memory arbiter control block */
7954 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7955 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7956
7957 /* Buffer manager control block */
7958 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7959 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7960 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7961 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7962 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7963 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7964 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7965 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7966
7967 /* Read DMA control block */
7968 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7969 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7970
7971 /* Write DMA control block */
7972 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7973 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7974
7975 /* DMA completion block */
7976 printk("DEBUG: DMAC_MODE[%08x]\n",
7977 tr32(DMAC_MODE));
7978
7979 /* GRC block */
7980 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7981 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7982 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7983 tr32(GRC_LOCAL_CTRL));
7984
7985 /* TG3_BDINFOs */
7986 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7987 tr32(RCVDBDI_JUMBO_BD + 0x0),
7988 tr32(RCVDBDI_JUMBO_BD + 0x4),
7989 tr32(RCVDBDI_JUMBO_BD + 0x8),
7990 tr32(RCVDBDI_JUMBO_BD + 0xc));
7991 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7992 tr32(RCVDBDI_STD_BD + 0x0),
7993 tr32(RCVDBDI_STD_BD + 0x4),
7994 tr32(RCVDBDI_STD_BD + 0x8),
7995 tr32(RCVDBDI_STD_BD + 0xc));
7996 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7997 tr32(RCVDBDI_MINI_BD + 0x0),
7998 tr32(RCVDBDI_MINI_BD + 0x4),
7999 tr32(RCVDBDI_MINI_BD + 0x8),
8000 tr32(RCVDBDI_MINI_BD + 0xc));
8001
8002 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8003 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8004 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8005 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8006 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8007 val32, val32_2, val32_3, val32_4);
8008
8009 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8010 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8011 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8012 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8013 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8014 val32, val32_2, val32_3, val32_4);
8015
8016 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8017 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8018 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8019 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8020 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8021 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8022 val32, val32_2, val32_3, val32_4, val32_5);
8023
8024 /* SW status block */
8025 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8026 tp->hw_status->status,
8027 tp->hw_status->status_tag,
8028 tp->hw_status->rx_jumbo_consumer,
8029 tp->hw_status->rx_consumer,
8030 tp->hw_status->rx_mini_consumer,
8031 tp->hw_status->idx[0].rx_producer,
8032 tp->hw_status->idx[0].tx_consumer);
8033
8034 /* SW statistics block */
8035 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8036 ((u32 *)tp->hw_stats)[0],
8037 ((u32 *)tp->hw_stats)[1],
8038 ((u32 *)tp->hw_stats)[2],
8039 ((u32 *)tp->hw_stats)[3]);
8040
8041 /* Mailboxes */
8042 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8043 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8044 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8045 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8046 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8047
8048 /* NIC side send descriptors. */
8049 for (i = 0; i < 6; i++) {
8050 unsigned long txd;
8051
8052 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8053 + (i * sizeof(struct tg3_tx_buffer_desc));
8054 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8055 i,
8056 readl(txd + 0x0), readl(txd + 0x4),
8057 readl(txd + 0x8), readl(txd + 0xc));
8058 }
8059
8060 /* NIC side RX descriptors. */
8061 for (i = 0; i < 6; i++) {
8062 unsigned long rxd;
8063
8064 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8065 + (i * sizeof(struct tg3_rx_buffer_desc));
8066 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8067 i,
8068 readl(rxd + 0x0), readl(rxd + 0x4),
8069 readl(rxd + 0x8), readl(rxd + 0xc));
8070 rxd += (4 * sizeof(u32));
8071 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8072 i,
8073 readl(rxd + 0x0), readl(rxd + 0x4),
8074 readl(rxd + 0x8), readl(rxd + 0xc));
8075 }
8076
8077 for (i = 0; i < 6; i++) {
8078 unsigned long rxd;
8079
8080 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8081 + (i * sizeof(struct tg3_rx_buffer_desc));
8082 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8083 i,
8084 readl(rxd + 0x0), readl(rxd + 0x4),
8085 readl(rxd + 0x8), readl(rxd + 0xc));
8086 rxd += (4 * sizeof(u32));
8087 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8088 i,
8089 readl(rxd + 0x0), readl(rxd + 0x4),
8090 readl(rxd + 0x8), readl(rxd + 0xc));
8091 }
8092}
8093#endif
8094
8095static struct net_device_stats *tg3_get_stats(struct net_device *);
8096static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8097
8098static int tg3_close(struct net_device *dev)
8099{
8100 struct tg3 *tp = netdev_priv(dev);
8101
bea3348e 8102 napi_disable(&tp->napi);
28e53bdd 8103 cancel_work_sync(&tp->reset_task);
7faa006f 8104
1da177e4
LT		 8105 netif_stop_queue(dev);
8106
8107 del_timer_sync(&tp->timer);
8108
f47c11ee 8109 tg3_full_lock(tp, 1);
1da177e4
LT		 8110#if 0
8111 tg3_dump_state(tp);
8112#endif
8113
8114 tg3_disable_ints(tp);
8115
944d980e 8116 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8117 tg3_free_rings(tp);
5cf64b8a 8118 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8119
f47c11ee 8120 tg3_full_unlock(tp);
1da177e4 8121
88b06bc2
MC		 8122 free_irq(tp->pdev->irq, dev);
8123 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8124 pci_disable_msi(tp->pdev);
8125 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8126 }
1da177e4
LT		 8127
8128 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8129 sizeof(tp->net_stats_prev));
8130 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8131 sizeof(tp->estats_prev));
8132
8133 tg3_free_consistent(tp);
8134
bc1c7567
MC		 8135 tg3_set_power_state(tp, PCI_D3hot);
8136
8137 netif_carrier_off(tp->dev);
8138
1da177e4
LT		 8139 return 0;
8140}
8141
8142static inline unsigned long get_stat64(tg3_stat64_t *val)
8143{
8144 unsigned long ret;
8145
8146#if (BITS_PER_LONG == 32)
8147 ret = val->low;
8148#else
8149 ret = ((u64)val->high << 32) | ((u64)val->low);
8150#endif
8151 return ret;
8152}
8153
816f8b86
SB		 8154static inline u64 get_estat64(tg3_stat64_t *val)
8155{
8156 return ((u64)val->high << 32) | ((u64)val->low);
8157}
8158
1da177e4
LT		 8159static unsigned long calc_crc_errors(struct tg3 *tp)
8160{
8161 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8162
8163 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8164 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8165 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8166 u32 val;
8167
f47c11ee 8168 spin_lock_bh(&tp->lock);
569a5df8
MC		 8169 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8170 tg3_writephy(tp, MII_TG3_TEST1,
8171 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8172 tg3_readphy(tp, 0x14, &val);
8173 } else
8174 val = 0;
f47c11ee 8175 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8176
8177 tp->phy_crc_errors += val;
8178
8179 return tp->phy_crc_errors;
8180 }
8181
8182 return get_stat64(&hw_stats->rx_fcs_errors);
8183}
8184
8185#define ESTAT_ADD(member) \
8186 estats->member = old_estats->member + \
816f8b86 8187 get_estat64(&hw_stats->member)
1da177e4
LT		 8188
8189static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8190{
8191 struct tg3_ethtool_stats *estats = &tp->estats;
8192 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8193 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8194
8195 if (!hw_stats)
8196 return old_estats;
8197
8198 ESTAT_ADD(rx_octets);
8199 ESTAT_ADD(rx_fragments);
8200 ESTAT_ADD(rx_ucast_packets);
8201 ESTAT_ADD(rx_mcast_packets);
8202 ESTAT_ADD(rx_bcast_packets);
8203 ESTAT_ADD(rx_fcs_errors);
8204 ESTAT_ADD(rx_align_errors);
8205 ESTAT_ADD(rx_xon_pause_rcvd);
8206 ESTAT_ADD(rx_xoff_pause_rcvd);
8207 ESTAT_ADD(rx_mac_ctrl_rcvd);
8208 ESTAT_ADD(rx_xoff_entered);
8209 ESTAT_ADD(rx_frame_too_long_errors);
8210 ESTAT_ADD(rx_jabbers);
8211 ESTAT_ADD(rx_undersize_packets);
8212 ESTAT_ADD(rx_in_length_errors);
8213 ESTAT_ADD(rx_out_length_errors);
8214 ESTAT_ADD(rx_64_or_less_octet_packets);
8215 ESTAT_ADD(rx_65_to_127_octet_packets);
8216 ESTAT_ADD(rx_128_to_255_octet_packets);
8217 ESTAT_ADD(rx_256_to_511_octet_packets);
8218 ESTAT_ADD(rx_512_to_1023_octet_packets);
8219 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8220 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8221 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8222 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8223 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8224
8225 ESTAT_ADD(tx_octets);
8226 ESTAT_ADD(tx_collisions);
8227 ESTAT_ADD(tx_xon_sent);
8228 ESTAT_ADD(tx_xoff_sent);
8229 ESTAT_ADD(tx_flow_control);
8230 ESTAT_ADD(tx_mac_errors);
8231 ESTAT_ADD(tx_single_collisions);
8232 ESTAT_ADD(tx_mult_collisions);
8233 ESTAT_ADD(tx_deferred);
8234 ESTAT_ADD(tx_excessive_collisions);
8235 ESTAT_ADD(tx_late_collisions);
8236 ESTAT_ADD(tx_collide_2times);
8237 ESTAT_ADD(tx_collide_3times);
8238 ESTAT_ADD(tx_collide_4times);
8239 ESTAT_ADD(tx_collide_5times);
8240 ESTAT_ADD(tx_collide_6times);
8241 ESTAT_ADD(tx_collide_7times);
8242 ESTAT_ADD(tx_collide_8times);
8243 ESTAT_ADD(tx_collide_9times);
8244 ESTAT_ADD(tx_collide_10times);
8245 ESTAT_ADD(tx_collide_11times);
8246 ESTAT_ADD(tx_collide_12times);
8247 ESTAT_ADD(tx_collide_13times);
8248 ESTAT_ADD(tx_collide_14times);
8249 ESTAT_ADD(tx_collide_15times);
8250 ESTAT_ADD(tx_ucast_packets);
8251 ESTAT_ADD(tx_mcast_packets);
8252 ESTAT_ADD(tx_bcast_packets);
8253 ESTAT_ADD(tx_carrier_sense_errors);
8254 ESTAT_ADD(tx_discards);
8255 ESTAT_ADD(tx_errors);
8256
8257 ESTAT_ADD(dma_writeq_full);
8258 ESTAT_ADD(dma_write_prioq_full);
8259 ESTAT_ADD(rxbds_empty);
8260 ESTAT_ADD(rx_discards);
8261 ESTAT_ADD(rx_errors);
8262 ESTAT_ADD(rx_threshold_hit);
8263
8264 ESTAT_ADD(dma_readq_full);
8265 ESTAT_ADD(dma_read_prioq_full);
8266 ESTAT_ADD(tx_comp_queue_full);
8267
8268 ESTAT_ADD(ring_set_send_prod_index);
8269 ESTAT_ADD(ring_status_update);
8270 ESTAT_ADD(nic_irqs);
8271 ESTAT_ADD(nic_avoided_irqs);
8272 ESTAT_ADD(nic_tx_threshold_hit);
8273
8274 return estats;
8275}
8276
8277static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8278{
8279 struct tg3 *tp = netdev_priv(dev);
8280 struct net_device_stats *stats = &tp->net_stats;
8281 struct net_device_stats *old_stats = &tp->net_stats_prev;
8282 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8283
8284 if (!hw_stats)
8285 return old_stats;
8286
8287 stats->rx_packets = old_stats->rx_packets +
8288 get_stat64(&hw_stats->rx_ucast_packets) +
8289 get_stat64(&hw_stats->rx_mcast_packets) +
8290 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8291
1da177e4
LT		 8292 stats->tx_packets = old_stats->tx_packets +
8293 get_stat64(&hw_stats->tx_ucast_packets) +
8294 get_stat64(&hw_stats->tx_mcast_packets) +
8295 get_stat64(&hw_stats->tx_bcast_packets);
8296
8297 stats->rx_bytes = old_stats->rx_bytes +
8298 get_stat64(&hw_stats->rx_octets);
8299 stats->tx_bytes = old_stats->tx_bytes +
8300 get_stat64(&hw_stats->tx_octets);
8301
8302 stats->rx_errors = old_stats->rx_errors +
4f63b877 8303 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8304 stats->tx_errors = old_stats->tx_errors +
8305 get_stat64(&hw_stats->tx_errors) +
8306 get_stat64(&hw_stats->tx_mac_errors) +
8307 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8308 get_stat64(&hw_stats->tx_discards);
8309
8310 stats->multicast = old_stats->multicast +
8311 get_stat64(&hw_stats->rx_mcast_packets);
8312 stats->collisions = old_stats->collisions +
8313 get_stat64(&hw_stats->tx_collisions);
8314
8315 stats->rx_length_errors = old_stats->rx_length_errors +
8316 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8317 get_stat64(&hw_stats->rx_undersize_packets);
8318
8319 stats->rx_over_errors = old_stats->rx_over_errors +
8320 get_stat64(&hw_stats->rxbds_empty);
8321 stats->rx_frame_errors = old_stats->rx_frame_errors +
8322 get_stat64(&hw_stats->rx_align_errors);
8323 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8324 get_stat64(&hw_stats->tx_discards);
8325 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8326 get_stat64(&hw_stats->tx_carrier_sense_errors);
8327
8328 stats->rx_crc_errors = old_stats->rx_crc_errors +
8329 calc_crc_errors(tp);
8330
4f63b877
JL		 8331 stats->rx_missed_errors = old_stats->rx_missed_errors +
8332 get_stat64(&hw_stats->rx_discards);
8333
1da177e4
LT		 8334 return stats;
8335}
8336
8337static inline u32 calc_crc(unsigned char *buf, int len)
8338{
8339 u32 reg;
8340 u32 tmp;
8341 int j, k;
8342
8343 reg = 0xffffffff;
8344
8345 for (j = 0; j < len; j++) {
8346 reg ^= buf[j];
8347
8348 for (k = 0; k < 8; k++) {
8349 tmp = reg & 0x01;
8350
8351 reg >>= 1;
8352
8353 if (tmp) {
8354 reg ^= 0xedb88320;
8355 }
8356 }
8357 }
8358
8359 return ~reg;
8360}
8361
8362static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8363{
8364 /* accept or reject all multicast frames */
8365 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8366 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8367 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8368 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8369}
8370
8371static void __tg3_set_rx_mode(struct net_device *dev)
8372{
8373 struct tg3 *tp = netdev_priv(dev);
8374 u32 rx_mode;
8375
8376 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8377 RX_MODE_KEEP_VLAN_TAG);
8378
8379 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8380 * flag clear.
8381 */
8382#if TG3_VLAN_TAG_USED
8383 if (!tp->vlgrp &&
8384 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8385 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8386#else
8387 /* By definition, VLAN is disabled always in this
8388 * case.
8389 */
8390 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8391 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8392#endif
8393
8394 if (dev->flags & IFF_PROMISC) {
8395 /* Promiscuous mode. */
8396 rx_mode |= RX_MODE_PROMISC;
8397 } else if (dev->flags & IFF_ALLMULTI) {
8398 /* Accept all multicast. */
8399 tg3_set_multi (tp, 1);
8400 } else if (dev->mc_count < 1) {
8401 /* Reject all multicast. */
8402 tg3_set_multi (tp, 0);
8403 } else {
8404 /* Accept one or more multicast(s). */
8405 struct dev_mc_list *mclist;
8406 unsigned int i;
8407 u32 mc_filter[4] = { 0, };
8408 u32 regidx;
8409 u32 bit;
8410 u32 crc;
8411
8412 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8413 i++, mclist = mclist->next) {
8414
8415 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8416 bit = ~crc & 0x7f;
8417 regidx = (bit & 0x60) >> 5;
8418 bit &= 0x1f;
8419 mc_filter[regidx] |= (1 << bit);
8420 }
8421
8422 tw32(MAC_HASH_REG_0, mc_filter[0]);
8423 tw32(MAC_HASH_REG_1, mc_filter[1]);
8424 tw32(MAC_HASH_REG_2, mc_filter[2]);
8425 tw32(MAC_HASH_REG_3, mc_filter[3]);
8426 }
8427
8428 if (rx_mode != tp->rx_mode) {
8429 tp->rx_mode = rx_mode;
8430 tw32_f(MAC_RX_MODE, rx_mode);
8431 udelay(10);
8432 }
8433}
8434
8435static void tg3_set_rx_mode(struct net_device *dev)
8436{
8437 struct tg3 *tp = netdev_priv(dev);
8438
e75f7c90
MC		 8439 if (!netif_running(dev))
8440 return;
8441
f47c11ee 8442 tg3_full_lock(tp, 0);
1da177e4 8443 __tg3_set_rx_mode(dev);
f47c11ee 8444 tg3_full_unlock(tp);
1da177e4
LT		 8445}
8446
8447#define TG3_REGDUMP_LEN (32 * 1024)
8448
8449static int tg3_get_regs_len(struct net_device *dev)
8450{
8451 return TG3_REGDUMP_LEN;
8452}
8453
8454static void tg3_get_regs(struct net_device *dev,
8455 struct ethtool_regs *regs, void *_p)
8456{
8457 u32 *p = _p;
8458 struct tg3 *tp = netdev_priv(dev);
8459 u8 *orig_p = _p;
8460 int i;
8461
8462 regs->version = 0;
8463
8464 memset(p, 0, TG3_REGDUMP_LEN);
8465
bc1c7567
MC		 8466 if (tp->link_config.phy_is_low_power)
8467 return;
8468
f47c11ee 8469 tg3_full_lock(tp, 0);
1da177e4
LT		 8470
8471#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8472#define GET_REG32_LOOP(base,len) \
8473do { p = (u32 *)(orig_p + (base)); \
8474 for (i = 0; i < len; i += 4) \
8475 __GET_REG32((base) + i); \
8476} while (0)
8477#define GET_REG32_1(reg) \
8478do { p = (u32 *)(orig_p + (reg)); \
8479 __GET_REG32((reg)); \
8480} while (0)
8481
8482 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8483 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8484 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8485 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8486 GET_REG32_1(SNDDATAC_MODE);
8487 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8488 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8489 GET_REG32_1(SNDBDC_MODE);
8490 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8491 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8492 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8493 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8494 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8495 GET_REG32_1(RCVDCC_MODE);
8496 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8497 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8498 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8499 GET_REG32_1(MBFREE_MODE);
8500 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8501 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8502 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8503 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8504 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8505 GET_REG32_1(RX_CPU_MODE);
8506 GET_REG32_1(RX_CPU_STATE);
8507 GET_REG32_1(RX_CPU_PGMCTR);
8508 GET_REG32_1(RX_CPU_HWBKPT);
8509 GET_REG32_1(TX_CPU_MODE);
8510 GET_REG32_1(TX_CPU_STATE);
8511 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8512 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8513 GET_REG32_LOOP(FTQ_RESET, 0x120);
8514 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8515 GET_REG32_1(DMAC_MODE);
8516 GET_REG32_LOOP(GRC_MODE, 0x4c);
8517 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8518 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8519
8520#undef __GET_REG32
8521#undef GET_REG32_LOOP
8522#undef GET_REG32_1
8523
f47c11ee 8524 tg3_full_unlock(tp);
1da177e4
LT		 8525}
8526
8527static int tg3_get_eeprom_len(struct net_device *dev)
8528{
8529 struct tg3 *tp = netdev_priv(dev);
8530
8531 return tp->nvram_size;
8532}
8533
1da177e4
LT		 8534static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8535{
8536 struct tg3 *tp = netdev_priv(dev);
8537 int ret;
8538 u8 *pd;
b9fc7dc5 8539 u32 i, offset, len, b_offset, b_count;
a9dc529d 8540 __be32 val;
1da177e4 8541
bc1c7567
MC		 8542 if (tp->link_config.phy_is_low_power)
8543 return -EAGAIN;
8544
1da177e4
LT		 8545 offset = eeprom->offset;
8546 len = eeprom->len;
8547 eeprom->len = 0;
8548
8549 eeprom->magic = TG3_EEPROM_MAGIC;
8550
8551 if (offset & 3) {
8552 /* adjustments to start on required 4 byte boundary */
8553 b_offset = offset & 3;
8554 b_count = 4 - b_offset;
8555 if (b_count > len) {
8556 /* i.e. offset=1 len=2 */
8557 b_count = len;
8558 }
a9dc529d 8559 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8560 if (ret)
8561 return ret;
1da177e4
LT		 8562 memcpy(data, ((char*)&val) + b_offset, b_count);
8563 len -= b_count;
8564 offset += b_count;
8565 eeprom->len += b_count;
8566 }
8567
8568 /* read bytes upto the last 4 byte boundary */
8569 pd = &data[eeprom->len];
8570 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8571 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8572 if (ret) {
8573 eeprom->len += i;
8574 return ret;
8575 }
1da177e4
LT		 8576 memcpy(pd + i, &val, 4);
8577 }
8578 eeprom->len += i;
8579
8580 if (len & 3) {
8581 /* read last bytes not ending on 4 byte boundary */
8582 pd = &data[eeprom->len];
8583 b_count = len & 3;
8584 b_offset = offset + len - b_count;
a9dc529d 8585 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8586 if (ret)
8587 return ret;
b9fc7dc5 8588 memcpy(pd, &val, b_count);
1da177e4
LT		 8589 eeprom->len += b_count;
8590 }
8591 return 0;
8592}
8593
6aa20a22 8594static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8595
8596static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8597{
8598 struct tg3 *tp = netdev_priv(dev);
8599 int ret;
b9fc7dc5 8600 u32 offset, len, b_offset, odd_len;
1da177e4 8601 u8 *buf;
a9dc529d 8602 __be32 start, end;
1da177e4 8603
bc1c7567
MC		 8604 if (tp->link_config.phy_is_low_power)
8605 return -EAGAIN;
8606
1da177e4
LT		 8607 if (eeprom->magic != TG3_EEPROM_MAGIC)
8608 return -EINVAL;
8609
8610 offset = eeprom->offset;
8611 len = eeprom->len;
8612
8613 if ((b_offset = (offset & 3))) {
8614 /* adjustments to start on required 4 byte boundary */
a9dc529d 8615 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8616 if (ret)
8617 return ret;
1da177e4
LT		 8618 len += b_offset;
8619 offset &= ~3;
1c8594b4
MC		 8620 if (len < 4)
8621 len = 4;
1da177e4
LT		 8622 }
8623
8624 odd_len = 0;
1c8594b4 8625 if (len & 3) {
1da177e4
LT		 8626 /* adjustments to end on required 4 byte boundary */
8627 odd_len = 1;
8628 len = (len + 3) & ~3;
a9dc529d 8629 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8630 if (ret)
8631 return ret;
1da177e4
LT		 8632 }
8633
8634 buf = data;
8635 if (b_offset || odd_len) {
8636 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8637 if (!buf)
1da177e4
LT		 8638 return -ENOMEM;
8639 if (b_offset)
8640 memcpy(buf, &start, 4);
8641 if (odd_len)
8642 memcpy(buf+len-4, &end, 4);
8643 memcpy(buf + b_offset, data, eeprom->len);
8644 }
8645
8646 ret = tg3_nvram_write_block(tp, offset, len, buf);
8647
8648 if (buf != data)
8649 kfree(buf);
8650
8651 return ret;
8652}
8653
8654static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8655{
b02fd9e3
MC		 8656 struct tg3 *tp = netdev_priv(dev);
8657
8658 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8659 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8660 return -EAGAIN;
298cf9be 8661 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8662 }
6aa20a22 8663
1da177e4
LT		 8664 cmd->supported = (SUPPORTED_Autoneg);
8665
8666 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8667 cmd->supported |= (SUPPORTED_1000baseT_Half |
8668 SUPPORTED_1000baseT_Full);
8669
ef348144 8670 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8671 cmd->supported |= (SUPPORTED_100baseT_Half |
8672 SUPPORTED_100baseT_Full |
8673 SUPPORTED_10baseT_Half |
8674 SUPPORTED_10baseT_Full |
3bebab59 8675 SUPPORTED_TP);
ef348144
KK		 8676 cmd->port = PORT_TP;
8677 } else {
1da177e4 8678 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8679 cmd->port = PORT_FIBRE;
8680 }
6aa20a22 8681
1da177e4
LT		 8682 cmd->advertising = tp->link_config.advertising;
8683 if (netif_running(dev)) {
8684 cmd->speed = tp->link_config.active_speed;
8685 cmd->duplex = tp->link_config.active_duplex;
8686 }
1da177e4 8687 cmd->phy_address = PHY_ADDR;
7e5856bd 8688 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8689 cmd->autoneg = tp->link_config.autoneg;
8690 cmd->maxtxpkt = 0;
8691 cmd->maxrxpkt = 0;
8692 return 0;
8693}
6aa20a22 8694
1da177e4
LT		 8695static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8696{
8697 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8698
b02fd9e3
MC		 8699 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8700 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8701 return -EAGAIN;
298cf9be 8702 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8703 }
8704
7e5856bd
MC		 8705 if (cmd->autoneg != AUTONEG_ENABLE &&
8706 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8707 return -EINVAL;
7e5856bd
MC		 8708
8709 if (cmd->autoneg == AUTONEG_DISABLE &&
8710 cmd->duplex != DUPLEX_FULL &&
8711 cmd->duplex != DUPLEX_HALF)
37ff238d 8712 return -EINVAL;
1da177e4 8713
7e5856bd
MC		 8714 if (cmd->autoneg == AUTONEG_ENABLE) {
8715 u32 mask = ADVERTISED_Autoneg |
8716 ADVERTISED_Pause |
8717 ADVERTISED_Asym_Pause;
8718
8719 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8720 mask |= ADVERTISED_1000baseT_Half |
8721 ADVERTISED_1000baseT_Full;
8722
8723 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8724 mask |= ADVERTISED_100baseT_Half |
8725 ADVERTISED_100baseT_Full |
8726 ADVERTISED_10baseT_Half |
8727 ADVERTISED_10baseT_Full |
8728 ADVERTISED_TP;
8729 else
8730 mask |= ADVERTISED_FIBRE;
8731
8732 if (cmd->advertising & ~mask)
8733 return -EINVAL;
8734
8735 mask &= (ADVERTISED_1000baseT_Half |
8736 ADVERTISED_1000baseT_Full |
8737 ADVERTISED_100baseT_Half |
8738 ADVERTISED_100baseT_Full |
8739 ADVERTISED_10baseT_Half |
8740 ADVERTISED_10baseT_Full);
8741
8742 cmd->advertising &= mask;
8743 } else {
8744 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8745 if (cmd->speed != SPEED_1000)
8746 return -EINVAL;
8747
8748 if (cmd->duplex != DUPLEX_FULL)
8749 return -EINVAL;
8750 } else {
8751 if (cmd->speed != SPEED_100 &&
8752 cmd->speed != SPEED_10)
8753 return -EINVAL;
8754 }
8755 }
8756
f47c11ee 8757 tg3_full_lock(tp, 0);
1da177e4
LT		 8758
8759 tp->link_config.autoneg = cmd->autoneg;
8760 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8761 tp->link_config.advertising = (cmd->advertising |
8762 ADVERTISED_Autoneg);
1da177e4
LT		 8763 tp->link_config.speed = SPEED_INVALID;
8764 tp->link_config.duplex = DUPLEX_INVALID;
8765 } else {
8766 tp->link_config.advertising = 0;
8767 tp->link_config.speed = cmd->speed;
8768 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8769 }
6aa20a22 8770
24fcad6b
MC		 8771 tp->link_config.orig_speed = tp->link_config.speed;
8772 tp->link_config.orig_duplex = tp->link_config.duplex;
8773 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8774
1da177e4
LT		 8775 if (netif_running(dev))
8776 tg3_setup_phy(tp, 1);
8777
f47c11ee 8778 tg3_full_unlock(tp);
6aa20a22 8779
1da177e4
LT		 8780 return 0;
8781}
6aa20a22 8782
1da177e4
LT		 8783static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8784{
8785 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8786
1da177e4
LT		 8787 strcpy(info->driver, DRV_MODULE_NAME);
8788 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8789 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8790 strcpy(info->bus_info, pci_name(tp->pdev));
8791}
6aa20a22 8792
1da177e4
LT		 8793static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8794{
8795 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8796
12dac075
RW		 8797 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8798 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8799 wol->supported = WAKE_MAGIC;
8800 else
8801 wol->supported = 0;
1da177e4 8802 wol->wolopts = 0;
05ac4cb7
MC		 8803 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8804 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8805 wol->wolopts = WAKE_MAGIC;
8806 memset(&wol->sopass, 0, sizeof(wol->sopass));
8807}
6aa20a22 8808
1da177e4
LT		 8809static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8810{
8811 struct tg3 *tp = netdev_priv(dev);
12dac075 8812 struct device *dp = &tp->pdev->dev;
6aa20a22 8813
1da177e4
LT		 8814 if (wol->wolopts & ~WAKE_MAGIC)
8815 return -EINVAL;
8816 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8817 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8818 return -EINVAL;
6aa20a22 8819
f47c11ee 8820 spin_lock_bh(&tp->lock);
12dac075 8821 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8822 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8823 device_set_wakeup_enable(dp, true);
8824 } else {
1da177e4 8825 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8826 device_set_wakeup_enable(dp, false);
8827 }
f47c11ee 8828 spin_unlock_bh(&tp->lock);
6aa20a22 8829
1da177e4
LT		 8830 return 0;
8831}
6aa20a22 8832
1da177e4
LT		 8833static u32 tg3_get_msglevel(struct net_device *dev)
8834{
8835 struct tg3 *tp = netdev_priv(dev);
8836 return tp->msg_enable;
8837}
6aa20a22 8838
1da177e4
LT		 8839static void tg3_set_msglevel(struct net_device *dev, u32 value)
8840{
8841 struct tg3 *tp = netdev_priv(dev);
8842 tp->msg_enable = value;
8843}
6aa20a22 8844
1da177e4
LT		 8845static int tg3_set_tso(struct net_device *dev, u32 value)
8846{
8847 struct tg3 *tp = netdev_priv(dev);
8848
8849 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8850 if (value)
8851 return -EINVAL;
8852 return 0;
8853 }
027455ad
MC		 8854 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8855 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8856 if (value) {
b0026624 8857 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8859 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8860 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8861 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8863 dev->features |= NETIF_F_TSO_ECN;
8864 } else
8865 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8866 }
1da177e4
LT		 8867 return ethtool_op_set_tso(dev, value);
8868}
6aa20a22 8869
1da177e4
LT		 8870static int tg3_nway_reset(struct net_device *dev)
8871{
8872 struct tg3 *tp = netdev_priv(dev);
1da177e4 8873 int r;
6aa20a22 8874
1da177e4
LT		 8875 if (!netif_running(dev))
8876 return -EAGAIN;
8877
c94e3941
MC		 8878 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8879 return -EINVAL;
8880
b02fd9e3
MC		 8881 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8882 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8883 return -EAGAIN;
298cf9be 8884 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8885 } else {
8886 u32 bmcr;
8887
8888 spin_lock_bh(&tp->lock);
8889 r = -EINVAL;
8890 tg3_readphy(tp, MII_BMCR, &bmcr);
8891 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8892 ((bmcr & BMCR_ANENABLE) ||
8893 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8894 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8895 BMCR_ANENABLE);
8896 r = 0;
8897 }
8898 spin_unlock_bh(&tp->lock);
1da177e4 8899 }
6aa20a22 8900
1da177e4
LT		 8901 return r;
8902}
6aa20a22 8903
1da177e4
LT		 8904static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8905{
8906 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8907
1da177e4
LT		 8908 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8909 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8910 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8911 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8912 else
8913 ering->rx_jumbo_max_pending = 0;
8914
8915 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8916
8917 ering->rx_pending = tp->rx_pending;
8918 ering->rx_mini_pending = 0;
4f81c32b
MC		 8919 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8920 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8921 else
8922 ering->rx_jumbo_pending = 0;
8923
1da177e4
LT		 8924 ering->tx_pending = tp->tx_pending;
8925}
6aa20a22 8926
1da177e4
LT		 8927static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8928{
8929 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8930 int irq_sync = 0, err = 0;
6aa20a22 8931
1da177e4
LT		 8932 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8933 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8934 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8935 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8936 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8937 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8938 return -EINVAL;
6aa20a22 8939
bbe832c0 8940 if (netif_running(dev)) {
b02fd9e3 8941 tg3_phy_stop(tp);
1da177e4 8942 tg3_netif_stop(tp);
bbe832c0
MC		 8943 irq_sync = 1;
8944 }
1da177e4 8945
bbe832c0 8946 tg3_full_lock(tp, irq_sync);
6aa20a22 8947
1da177e4
LT		 8948 tp->rx_pending = ering->rx_pending;
8949
8950 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8951 tp->rx_pending > 63)
8952 tp->rx_pending = 63;
8953 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8954 tp->tx_pending = ering->tx_pending;
8955
8956 if (netif_running(dev)) {
944d980e 8957 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8958 err = tg3_restart_hw(tp, 1);
8959 if (!err)
8960 tg3_netif_start(tp);
1da177e4
LT		 8961 }
8962
f47c11ee 8963 tg3_full_unlock(tp);
6aa20a22 8964
b02fd9e3
MC		 8965 if (irq_sync && !err)
8966 tg3_phy_start(tp);
8967
b9ec6c1b 8968 return err;
1da177e4 8969}
6aa20a22 8970
1da177e4
LT		 8971static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8972{
8973 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8974
1da177e4 8975 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 8976
e18ce346 8977 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 8978 epause->rx_pause = 1;
8979 else
8980 epause->rx_pause = 0;
8981
e18ce346 8982 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 8983 epause->tx_pause = 1;
8984 else
8985 epause->tx_pause = 0;
1da177e4 8986}
6aa20a22 8987
1da177e4
LT		 8988static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8989{
8990 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 8991 int err = 0;
6aa20a22 8992
b02fd9e3
MC		 8993 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8994 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8995 return -EAGAIN;
1da177e4 8996
b02fd9e3
MC		 8997 if (epause->autoneg) {
8998 u32 newadv;
8999 struct phy_device *phydev;
f47c11ee 9000
298cf9be 9001 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9002
b02fd9e3
MC		 9003 if (epause->rx_pause) {
9004 if (epause->tx_pause)
9005 newadv = ADVERTISED_Pause;
9006 else
9007 newadv = ADVERTISED_Pause |
9008 ADVERTISED_Asym_Pause;
9009 } else if (epause->tx_pause) {
9010 newadv = ADVERTISED_Asym_Pause;
9011 } else
9012 newadv = 0;
9013
9014 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9015 u32 oldadv = phydev->advertising &
9016 (ADVERTISED_Pause |
9017 ADVERTISED_Asym_Pause);
9018 if (oldadv != newadv) {
9019 phydev->advertising &=
9020 ~(ADVERTISED_Pause |
9021 ADVERTISED_Asym_Pause);
9022 phydev->advertising |= newadv;
9023 err = phy_start_aneg(phydev);
9024 }
9025 } else {
9026 tp->link_config.advertising &=
9027 ~(ADVERTISED_Pause |
9028 ADVERTISED_Asym_Pause);
9029 tp->link_config.advertising |= newadv;
9030 }
9031 } else {
9032 if (epause->rx_pause)
e18ce346 9033 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9034 else
e18ce346 9035 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9036
b02fd9e3 9037 if (epause->tx_pause)
e18ce346 9038 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9039 else
e18ce346 9040 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9041
9042 if (netif_running(dev))
9043 tg3_setup_flow_control(tp, 0, 0);
9044 }
9045 } else {
9046 int irq_sync = 0;
9047
9048 if (netif_running(dev)) {
9049 tg3_netif_stop(tp);
9050 irq_sync = 1;
9051 }
9052
9053 tg3_full_lock(tp, irq_sync);
9054
9055 if (epause->autoneg)
9056 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9057 else
9058 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9059 if (epause->rx_pause)
e18ce346 9060 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9061 else
e18ce346 9062 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9063 if (epause->tx_pause)
e18ce346 9064 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9065 else
e18ce346 9066 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9067
9068 if (netif_running(dev)) {
9069 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9070 err = tg3_restart_hw(tp, 1);
9071 if (!err)
9072 tg3_netif_start(tp);
9073 }
9074
9075 tg3_full_unlock(tp);
9076 }
6aa20a22 9077
b9ec6c1b 9078 return err;
1da177e4 9079}
6aa20a22 9080
1da177e4
LT		 9081static u32 tg3_get_rx_csum(struct net_device *dev)
9082{
9083 struct tg3 *tp = netdev_priv(dev);
9084 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9085}
6aa20a22 9086
1da177e4
LT		 9087static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9088{
9089 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9090
1da177e4
LT		 9091 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9092 if (data != 0)
9093 return -EINVAL;
9094 return 0;
9095 }
6aa20a22 9096
f47c11ee 9097 spin_lock_bh(&tp->lock);
1da177e4
LT		 9098 if (data)
9099 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9100 else
9101 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9102 spin_unlock_bh(&tp->lock);
6aa20a22 9103
1da177e4
LT		 9104 return 0;
9105}
6aa20a22 9106
1da177e4
LT		 9107static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9108{
9109 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9110
1da177e4
LT		 9111 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9112 if (data != 0)
9113 return -EINVAL;
9114 return 0;
9115 }
6aa20a22 9116
321d32a0 9117 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9118 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9119 else
9c27dbdf 9120 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9121
9122 return 0;
9123}
9124
b9f2c044 9125static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9126{
b9f2c044
JG		 9127 switch (sset) {
9128 case ETH_SS_TEST:
9129 return TG3_NUM_TEST;
9130 case ETH_SS_STATS:
9131 return TG3_NUM_STATS;
9132 default:
9133 return -EOPNOTSUPP;
9134 }
4cafd3f5
MC		 9135}
9136
1da177e4
LT		 9137static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9138{
9139 switch (stringset) {
9140 case ETH_SS_STATS:
9141 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9142 break;
4cafd3f5
MC		 9143 case ETH_SS_TEST:
9144 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9145 break;
1da177e4
LT		 9146 default:
9147 WARN_ON(1); /* we need a WARN() */
9148 break;
9149 }
9150}
9151
4009a93d
MC		 9152static int tg3_phys_id(struct net_device *dev, u32 data)
9153{
9154 struct tg3 *tp = netdev_priv(dev);
9155 int i;
9156
9157 if (!netif_running(tp->dev))
9158 return -EAGAIN;
9159
9160 if (data == 0)
759afc31 9161 data = UINT_MAX / 2;
4009a93d
MC		 9162
9163 for (i = 0; i < (data * 2); i++) {
9164 if ((i % 2) == 0)
9165 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9166 LED_CTRL_1000MBPS_ON |
9167 LED_CTRL_100MBPS_ON |
9168 LED_CTRL_10MBPS_ON |
9169 LED_CTRL_TRAFFIC_OVERRIDE |
9170 LED_CTRL_TRAFFIC_BLINK |
9171 LED_CTRL_TRAFFIC_LED);
6aa20a22 9172
4009a93d
MC		 9173 else
9174 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9175 LED_CTRL_TRAFFIC_OVERRIDE);
9176
9177 if (msleep_interruptible(500))
9178 break;
9179 }
9180 tw32(MAC_LED_CTRL, tp->led_ctrl);
9181 return 0;
9182}
9183
1da177e4
LT		 9184static void tg3_get_ethtool_stats (struct net_device *dev,
9185 struct ethtool_stats *estats, u64 *tmp_stats)
9186{
9187 struct tg3 *tp = netdev_priv(dev);
9188 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9189}
9190
566f86ad 9191#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9192#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9193#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9194#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9195#define NVRAM_SELFBOOT_HW_SIZE 0x20
9196#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9197
9198static int tg3_test_nvram(struct tg3 *tp)
9199{
b9fc7dc5 9200 u32 csum, magic;
a9dc529d 9201 __be32 *buf;
ab0049b4 9202 int i, j, k, err = 0, size;
566f86ad 9203
e4f34110 9204 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9205 return -EIO;
9206
1b27777a
MC		 9207 if (magic == TG3_EEPROM_MAGIC)
9208 size = NVRAM_TEST_SIZE;
b16250e3 9209 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9210 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9211 TG3_EEPROM_SB_FORMAT_1) {
9212 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9213 case TG3_EEPROM_SB_REVISION_0:
9214 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9215 break;
9216 case TG3_EEPROM_SB_REVISION_2:
9217 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9218 break;
9219 case TG3_EEPROM_SB_REVISION_3:
9220 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9221 break;
9222 default:
9223 return 0;
9224 }
9225 } else
1b27777a 9226 return 0;
b16250e3
MC		 9227 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9228 size = NVRAM_SELFBOOT_HW_SIZE;
9229 else
1b27777a
MC		 9230 return -EIO;
9231
9232 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9233 if (buf == NULL)
9234 return -ENOMEM;
9235
1b27777a
MC		 9236 err = -EIO;
9237 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9238 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9239 if (err)
566f86ad 9240 break;
566f86ad 9241 }
1b27777a 9242 if (i < size)
566f86ad
MC		 9243 goto out;
9244
1b27777a 9245 /* Selfboot format */
a9dc529d 9246 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9247 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9248 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9249 u8 *buf8 = (u8 *) buf, csum8 = 0;
9250
b9fc7dc5 9251 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9252 TG3_EEPROM_SB_REVISION_2) {
9253 /* For rev 2, the csum doesn't include the MBA. */
9254 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9255 csum8 += buf8[i];
9256 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9257 csum8 += buf8[i];
9258 } else {
9259 for (i = 0; i < size; i++)
9260 csum8 += buf8[i];
9261 }
1b27777a 9262
ad96b485
AB		 9263 if (csum8 == 0) {
9264 err = 0;
9265 goto out;
9266 }
9267
9268 err = -EIO;
9269 goto out;
1b27777a 9270 }
566f86ad 9271
b9fc7dc5 9272 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9273 TG3_EEPROM_MAGIC_HW) {
9274 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9275 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9276 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9277
9278 /* Separate the parity bits and the data bytes. */
9279 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9280 if ((i == 0) || (i == 8)) {
9281 int l;
9282 u8 msk;
9283
9284 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9285 parity[k++] = buf8[i] & msk;
9286 i++;
9287 }
9288 else if (i == 16) {
9289 int l;
9290 u8 msk;
9291
9292 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9293 parity[k++] = buf8[i] & msk;
9294 i++;
9295
9296 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9297 parity[k++] = buf8[i] & msk;
9298 i++;
9299 }
9300 data[j++] = buf8[i];
9301 }
9302
9303 err = -EIO;
9304 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9305 u8 hw8 = hweight8(data[i]);
9306
9307 if ((hw8 & 0x1) && parity[i])
9308 goto out;
9309 else if (!(hw8 & 0x1) && !parity[i])
9310 goto out;
9311 }
9312 err = 0;
9313 goto out;
9314 }
9315
566f86ad
MC		 9316 /* Bootstrap checksum at offset 0x10 */
9317 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9318 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9319 goto out;
9320
9321 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9322 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9323 if (csum != be32_to_cpu(buf[0xfc/4]))
9324 goto out;
566f86ad
MC		 9325
9326 err = 0;
9327
9328out:
9329 kfree(buf);
9330 return err;
9331}
9332
ca43007a
MC		 9333#define TG3_SERDES_TIMEOUT_SEC 2
9334#define TG3_COPPER_TIMEOUT_SEC 6
9335
9336static int tg3_test_link(struct tg3 *tp)
9337{
9338 int i, max;
9339
9340 if (!netif_running(tp->dev))
9341 return -ENODEV;
9342
4c987487 9343 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9344 max = TG3_SERDES_TIMEOUT_SEC;
9345 else
9346 max = TG3_COPPER_TIMEOUT_SEC;
9347
9348 for (i = 0; i < max; i++) {
9349 if (netif_carrier_ok(tp->dev))
9350 return 0;
9351
9352 if (msleep_interruptible(1000))
9353 break;
9354 }
9355
9356 return -EIO;
9357}
9358
a71116d1 9359/* Only test the commonly used registers */
30ca3e37 9360static int tg3_test_registers(struct tg3 *tp)
a71116d1 9361{
b16250e3 9362 int i, is_5705, is_5750;
a71116d1
MC		 9363 u32 offset, read_mask, write_mask, val, save_val, read_val;
9364 static struct {
9365 u16 offset;
9366 u16 flags;
9367#define TG3_FL_5705 0x1
9368#define TG3_FL_NOT_5705 0x2
9369#define TG3_FL_NOT_5788 0x4
b16250e3 9370#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9371 u32 read_mask;
9372 u32 write_mask;
9373 } reg_tbl[] = {
9374 /* MAC Control Registers */
9375 { MAC_MODE, TG3_FL_NOT_5705,
9376 0x00000000, 0x00ef6f8c },
9377 { MAC_MODE, TG3_FL_5705,
9378 0x00000000, 0x01ef6b8c },
9379 { MAC_STATUS, TG3_FL_NOT_5705,
9380 0x03800107, 0x00000000 },
9381 { MAC_STATUS, TG3_FL_5705,
9382 0x03800100, 0x00000000 },
9383 { MAC_ADDR_0_HIGH, 0x0000,
9384 0x00000000, 0x0000ffff },
9385 { MAC_ADDR_0_LOW, 0x0000,
9386 0x00000000, 0xffffffff },
9387 { MAC_RX_MTU_SIZE, 0x0000,
9388 0x00000000, 0x0000ffff },
9389 { MAC_TX_MODE, 0x0000,
9390 0x00000000, 0x00000070 },
9391 { MAC_TX_LENGTHS, 0x0000,
9392 0x00000000, 0x00003fff },
9393 { MAC_RX_MODE, TG3_FL_NOT_5705,
9394 0x00000000, 0x000007fc },
9395 { MAC_RX_MODE, TG3_FL_5705,
9396 0x00000000, 0x000007dc },
9397 { MAC_HASH_REG_0, 0x0000,
9398 0x00000000, 0xffffffff },
9399 { MAC_HASH_REG_1, 0x0000,
9400 0x00000000, 0xffffffff },
9401 { MAC_HASH_REG_2, 0x0000,
9402 0x00000000, 0xffffffff },
9403 { MAC_HASH_REG_3, 0x0000,
9404 0x00000000, 0xffffffff },
9405
9406 /* Receive Data and Receive BD Initiator Control Registers. */
9407 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9408 0x00000000, 0xffffffff },
9409 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9410 0x00000000, 0xffffffff },
9411 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9412 0x00000000, 0x00000003 },
9413 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9414 0x00000000, 0xffffffff },
9415 { RCVDBDI_STD_BD+0, 0x0000,
9416 0x00000000, 0xffffffff },
9417 { RCVDBDI_STD_BD+4, 0x0000,
9418 0x00000000, 0xffffffff },
9419 { RCVDBDI_STD_BD+8, 0x0000,
9420 0x00000000, 0xffff0002 },
9421 { RCVDBDI_STD_BD+0xc, 0x0000,
9422 0x00000000, 0xffffffff },
6aa20a22 9423
a71116d1
MC		 9424 /* Receive BD Initiator Control Registers. */
9425 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9426 0x00000000, 0xffffffff },
9427 { RCVBDI_STD_THRESH, TG3_FL_5705,
9428 0x00000000, 0x000003ff },
9429 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9430 0x00000000, 0xffffffff },
6aa20a22 9431
a71116d1
MC		 9432 /* Host Coalescing Control Registers. */
9433 { HOSTCC_MODE, TG3_FL_NOT_5705,
9434 0x00000000, 0x00000004 },
9435 { HOSTCC_MODE, TG3_FL_5705,
9436 0x00000000, 0x000000f6 },
9437 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9438 0x00000000, 0xffffffff },
9439 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9440 0x00000000, 0x000003ff },
9441 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9442 0x00000000, 0xffffffff },
9443 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9444 0x00000000, 0x000003ff },
9445 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9446 0x00000000, 0xffffffff },
9447 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9448 0x00000000, 0x000000ff },
9449 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9450 0x00000000, 0xffffffff },
9451 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9452 0x00000000, 0x000000ff },
9453 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9454 0x00000000, 0xffffffff },
9455 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9456 0x00000000, 0xffffffff },
9457 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9458 0x00000000, 0xffffffff },
9459 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9460 0x00000000, 0x000000ff },
9461 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9462 0x00000000, 0xffffffff },
9463 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9464 0x00000000, 0x000000ff },
9465 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9466 0x00000000, 0xffffffff },
9467 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9468 0x00000000, 0xffffffff },
9469 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9470 0x00000000, 0xffffffff },
9471 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9472 0x00000000, 0xffffffff },
9473 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9474 0x00000000, 0xffffffff },
9475 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9476 0xffffffff, 0x00000000 },
9477 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9478 0xffffffff, 0x00000000 },
9479
9480 /* Buffer Manager Control Registers. */
b16250e3 9481 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9482 0x00000000, 0x007fff80 },
b16250e3 9483 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9484 0x00000000, 0x007fffff },
9485 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9486 0x00000000, 0x0000003f },
9487 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9488 0x00000000, 0x000001ff },
9489 { BUFMGR_MB_HIGH_WATER, 0x0000,
9490 0x00000000, 0x000001ff },
9491 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9492 0xffffffff, 0x00000000 },
9493 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9494 0xffffffff, 0x00000000 },
6aa20a22 9495
a71116d1
MC		 9496 /* Mailbox Registers */
9497 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9498 0x00000000, 0x000001ff },
9499 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9500 0x00000000, 0x000001ff },
9501 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9502 0x00000000, 0x000007ff },
9503 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9504 0x00000000, 0x000001ff },
9505
9506 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9507 };
9508
b16250e3
MC		 9509 is_5705 = is_5750 = 0;
9510 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9511 is_5705 = 1;
b16250e3
MC		 9512 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9513 is_5750 = 1;
9514 }
a71116d1
MC		 9515
9516 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9517 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9518 continue;
9519
9520 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9521 continue;
9522
9523 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9524 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9525 continue;
9526
b16250e3
MC		 9527 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9528 continue;
9529
a71116d1
MC		 9530 offset = (u32) reg_tbl[i].offset;
9531 read_mask = reg_tbl[i].read_mask;
9532 write_mask = reg_tbl[i].write_mask;
9533
9534 /* Save the original register content */
9535 save_val = tr32(offset);
9536
9537 /* Determine the read-only value. */
9538 read_val = save_val & read_mask;
9539
9540 /* Write zero to the register, then make sure the read-only bits
9541 * are not changed and the read/write bits are all zeros.
9542 */
9543 tw32(offset, 0);
9544
9545 val = tr32(offset);
9546
9547 /* Test the read-only and read/write bits. */
9548 if (((val & read_mask) != read_val) || (val & write_mask))
9549 goto out;
9550
9551 /* Write ones to all the bits defined by RdMask and WrMask, then
9552 * make sure the read-only bits are not changed and the
9553 * read/write bits are all ones.
9554 */
9555 tw32(offset, read_mask | write_mask);
9556
9557 val = tr32(offset);
9558
9559 /* Test the read-only bits. */
9560 if ((val & read_mask) != read_val)
9561 goto out;
9562
9563 /* Test the read/write bits. */
9564 if ((val & write_mask) != write_mask)
9565 goto out;
9566
9567 tw32(offset, save_val);
9568 }
9569
9570 return 0;
9571
9572out:
9f88f29f
MC		 9573 if (netif_msg_hw(tp))
9574 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9575 offset);
a71116d1
MC		 9576 tw32(offset, save_val);
9577 return -EIO;
9578}
9579
7942e1db
MC		 9580static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9581{
f71e1309 9582 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9583 int i;
9584 u32 j;
9585
e9edda69 9586 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9587 for (j = 0; j < len; j += 4) {
9588 u32 val;
9589
9590 tg3_write_mem(tp, offset + j, test_pattern[i]);
9591 tg3_read_mem(tp, offset + j, &val);
9592 if (val != test_pattern[i])
9593 return -EIO;
9594 }
9595 }
9596 return 0;
9597}
9598
9599static int tg3_test_memory(struct tg3 *tp)
9600{
9601 static struct mem_entry {
9602 u32 offset;
9603 u32 len;
9604 } mem_tbl_570x[] = {
38690194 9605 { 0x00000000, 0x00b50},
7942e1db
MC		 9606 { 0x00002000, 0x1c000},
9607 { 0xffffffff, 0x00000}
9608 }, mem_tbl_5705[] = {
9609 { 0x00000100, 0x0000c},
9610 { 0x00000200, 0x00008},
7942e1db
MC		 9611 { 0x00004000, 0x00800},
9612 { 0x00006000, 0x01000},
9613 { 0x00008000, 0x02000},
9614 { 0x00010000, 0x0e000},
9615 { 0xffffffff, 0x00000}
79f4d13a
MC		 9616 }, mem_tbl_5755[] = {
9617 { 0x00000200, 0x00008},
9618 { 0x00004000, 0x00800},
9619 { 0x00006000, 0x00800},
9620 { 0x00008000, 0x02000},
9621 { 0x00010000, 0x0c000},
9622 { 0xffffffff, 0x00000}
b16250e3
MC		 9623 }, mem_tbl_5906[] = {
9624 { 0x00000200, 0x00008},
9625 { 0x00004000, 0x00400},
9626 { 0x00006000, 0x00400},
9627 { 0x00008000, 0x01000},
9628 { 0x00010000, 0x01000},
9629 { 0xffffffff, 0x00000}
7942e1db
MC		 9630 };
9631 struct mem_entry *mem_tbl;
9632 int err = 0;
9633 int i;
9634
321d32a0
MC		 9635 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9636 mem_tbl = mem_tbl_5755;
9637 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9638 mem_tbl = mem_tbl_5906;
9639 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9640 mem_tbl = mem_tbl_5705;
9641 else
7942e1db
MC		 9642 mem_tbl = mem_tbl_570x;
9643
9644 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9645 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9646 mem_tbl[i].len)) != 0)
9647 break;
9648 }
6aa20a22 9649
7942e1db
MC		 9650 return err;
9651}
9652
9f40dead
MC		 9653#define TG3_MAC_LOOPBACK 0
9654#define TG3_PHY_LOOPBACK 1
9655
9656static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9657{
9f40dead 9658 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9659 u32 desc_idx;
9660 struct sk_buff *skb, *rx_skb;
9661 u8 *tx_data;
9662 dma_addr_t map;
9663 int num_pkts, tx_len, rx_len, i, err;
9664 struct tg3_rx_buffer_desc *desc;
9665
9f40dead 9666 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9667 /* HW errata - mac loopback fails in some cases on 5780.
9668 * Normal traffic and PHY loopback are not affected by
9669 * errata.
9670 */
9671 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9672 return 0;
9673
9f40dead 9674 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9675 MAC_MODE_PORT_INT_LPBACK;
9676 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9677 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9678 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9679 mac_mode |= MAC_MODE_PORT_MODE_MII;
9680 else
9681 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9682 tw32(MAC_MODE, mac_mode);
9683 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9684 u32 val;
9685
b16250e3
MC		 9686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9687 u32 phytest;
9688
9689 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9690 u32 phy;
9691
9692 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9693 phytest | MII_TG3_EPHY_SHADOW_EN);
9694 if (!tg3_readphy(tp, 0x1b, &phy))
9695 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9696 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9697 }
5d64ad34
MC		 9698 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9699 } else
9700 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9701
9ef8ca99
MC		 9702 tg3_phy_toggle_automdix(tp, 0);
9703
3f7045c1 9704 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9705 udelay(40);
5d64ad34 9706
e8f3f6ca 9707 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9709 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9710 mac_mode |= MAC_MODE_PORT_MODE_MII;
9711 } else
9712 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9713
c94e3941
MC		 9714 /* reset to prevent losing 1st rx packet intermittently */
9715 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9716 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9717 udelay(10);
9718 tw32_f(MAC_RX_MODE, tp->rx_mode);
9719 }
e8f3f6ca
MC		 9720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9721 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9722 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9723 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9724 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9725 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9726 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9727 }
9f40dead 9728 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9729 }
9730 else
9731 return -EINVAL;
c76949a6
MC		 9732
9733 err = -EIO;
9734
c76949a6 9735 tx_len = 1514;
a20e9c62 9736 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9737 if (!skb)
9738 return -ENOMEM;
9739
c76949a6
MC		 9740 tx_data = skb_put(skb, tx_len);
9741 memcpy(tx_data, tp->dev->dev_addr, 6);
9742 memset(tx_data + 6, 0x0, 8);
9743
9744 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9745
9746 for (i = 14; i < tx_len; i++)
9747 tx_data[i] = (u8) (i & 0xff);
9748
9749 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9750
9751 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9752 HOSTCC_MODE_NOW);
9753
9754 udelay(10);
9755
9756 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9757
c76949a6
MC		 9758 num_pkts = 0;
9759
9f40dead 9760 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9761
9f40dead 9762 tp->tx_prod++;
c76949a6
MC		 9763 num_pkts++;
9764
9f40dead
MC		 9765 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9766 tp->tx_prod);
09ee929c 9767 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9768
9769 udelay(10);
9770
3f7045c1
MC		 9771 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9772 for (i = 0; i < 25; i++) {
c76949a6
MC		 9773 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9774 HOSTCC_MODE_NOW);
9775
9776 udelay(10);
9777
9778 tx_idx = tp->hw_status->idx[0].tx_consumer;
9779 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9780 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9781 (rx_idx == (rx_start_idx + num_pkts)))
9782 break;
9783 }
9784
9785 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9786 dev_kfree_skb(skb);
9787
9f40dead 9788 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9789 goto out;
9790
9791 if (rx_idx != rx_start_idx + num_pkts)
9792 goto out;
9793
9794 desc = &tp->rx_rcb[rx_start_idx];
9795 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9796 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9797 if (opaque_key != RXD_OPAQUE_RING_STD)
9798 goto out;
9799
9800 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9801 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9802 goto out;
9803
9804 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9805 if (rx_len != tx_len)
9806 goto out;
9807
9808 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9809
9810 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9811 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9812
9813 for (i = 14; i < tx_len; i++) {
9814 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9815 goto out;
9816 }
9817 err = 0;
6aa20a22 9818
c76949a6
MC		 9819 /* tg3_free_rings will unmap and free the rx_skb */
9820out:
9821 return err;
9822}
9823
9f40dead
MC		 9824#define TG3_MAC_LOOPBACK_FAILED 1
9825#define TG3_PHY_LOOPBACK_FAILED 2
9826#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9827 TG3_PHY_LOOPBACK_FAILED)
9828
9829static int tg3_test_loopback(struct tg3 *tp)
9830{
9831 int err = 0;
9936bcf6 9832 u32 cpmuctrl = 0;
9f40dead
MC		 9833
9834 if (!netif_running(tp->dev))
9835 return TG3_LOOPBACK_FAILED;
9836
b9ec6c1b
MC		 9837 err = tg3_reset_hw(tp, 1);
9838 if (err)
9839 return TG3_LOOPBACK_FAILED;
9f40dead 9840
6833c043
MC		 9841 /* Turn off gphy autopowerdown. */
9842 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9843 tg3_phy_toggle_apd(tp, false);
9844
321d32a0 9845 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9846 int i;
9847 u32 status;
9848
9849 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9850
9851 /* Wait for up to 40 microseconds to acquire lock. */
9852 for (i = 0; i < 4; i++) {
9853 status = tr32(TG3_CPMU_MUTEX_GNT);
9854 if (status == CPMU_MUTEX_GNT_DRIVER)
9855 break;
9856 udelay(10);
9857 }
9858
9859 if (status != CPMU_MUTEX_GNT_DRIVER)
9860 return TG3_LOOPBACK_FAILED;
9861
b2a5c19c 9862 /* Turn off link-based power management. */
e875093c 9863 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9864 tw32(TG3_CPMU_CTRL,
9865 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9866 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9867 }
9868
9f40dead
MC		 9869 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9870 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9871
321d32a0 9872 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9873 tw32(TG3_CPMU_CTRL, cpmuctrl);
9874
9875 /* Release the mutex */
9876 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9877 }
9878
dd477003
MC		 9879 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9880 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9881 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9882 err |= TG3_PHY_LOOPBACK_FAILED;
9883 }
9884
6833c043
MC		 9885 /* Re-enable gphy autopowerdown. */
9886 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9887 tg3_phy_toggle_apd(tp, true);
9888
9f40dead
MC		 9889 return err;
9890}
9891
4cafd3f5
MC		 9892static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9893 u64 *data)
9894{
566f86ad
MC		 9895 struct tg3 *tp = netdev_priv(dev);
9896
bc1c7567
MC		 9897 if (tp->link_config.phy_is_low_power)
9898 tg3_set_power_state(tp, PCI_D0);
9899
566f86ad
MC		 9900 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9901
9902 if (tg3_test_nvram(tp) != 0) {
9903 etest->flags |= ETH_TEST_FL_FAILED;
9904 data[0] = 1;
9905 }
ca43007a
MC		 9906 if (tg3_test_link(tp) != 0) {
9907 etest->flags |= ETH_TEST_FL_FAILED;
9908 data[1] = 1;
9909 }
a71116d1 9910 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9911 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9912
9913 if (netif_running(dev)) {
b02fd9e3 9914 tg3_phy_stop(tp);
a71116d1 9915 tg3_netif_stop(tp);
bbe832c0
MC		 9916 irq_sync = 1;
9917 }
a71116d1 9918
bbe832c0 9919 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9920
9921 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9922 err = tg3_nvram_lock(tp);
a71116d1
MC		 9923 tg3_halt_cpu(tp, RX_CPU_BASE);
9924 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9925 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9926 if (!err)
9927 tg3_nvram_unlock(tp);
a71116d1 9928
d9ab5ad1
MC		 9929 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9930 tg3_phy_reset(tp);
9931
a71116d1
MC		 9932 if (tg3_test_registers(tp) != 0) {
9933 etest->flags |= ETH_TEST_FL_FAILED;
9934 data[2] = 1;
9935 }
7942e1db
MC		 9936 if (tg3_test_memory(tp) != 0) {
9937 etest->flags |= ETH_TEST_FL_FAILED;
9938 data[3] = 1;
9939 }
9f40dead 9940 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9941 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9942
f47c11ee
DM		 9943 tg3_full_unlock(tp);
9944
d4bc3927
MC		 9945 if (tg3_test_interrupt(tp) != 0) {
9946 etest->flags |= ETH_TEST_FL_FAILED;
9947 data[5] = 1;
9948 }
f47c11ee
DM		 9949
9950 tg3_full_lock(tp, 0);
d4bc3927 9951
a71116d1
MC		 9952 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9953 if (netif_running(dev)) {
9954 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 9955 err2 = tg3_restart_hw(tp, 1);
9956 if (!err2)
b9ec6c1b 9957 tg3_netif_start(tp);
a71116d1 9958 }
f47c11ee
DM		 9959
9960 tg3_full_unlock(tp);
b02fd9e3
MC		 9961
9962 if (irq_sync && !err2)
9963 tg3_phy_start(tp);
a71116d1 9964 }
bc1c7567
MC		 9965 if (tp->link_config.phy_is_low_power)
9966 tg3_set_power_state(tp, PCI_D3hot);
9967
4cafd3f5
MC		 9968}
9969
1da177e4
LT		 9970static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9971{
9972 struct mii_ioctl_data *data = if_mii(ifr);
9973 struct tg3 *tp = netdev_priv(dev);
9974 int err;
9975
b02fd9e3
MC		 9976 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9977 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9978 return -EAGAIN;
298cf9be 9979 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 9980 }
9981
1da177e4
LT		 9982 switch(cmd) {
9983 case SIOCGMIIPHY:
9984 data->phy_id = PHY_ADDR;
9985
9986 /* fallthru */
9987 case SIOCGMIIREG: {
9988 u32 mii_regval;
9989
9990 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9991 break; /* We have no PHY */
9992
bc1c7567
MC		 9993 if (tp->link_config.phy_is_low_power)
9994 return -EAGAIN;
9995
f47c11ee 9996 spin_lock_bh(&tp->lock);
1da177e4 9997 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9998 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9999
10000 data->val_out = mii_regval;
10001
10002 return err;
10003 }
10004
10005 case SIOCSMIIREG:
10006 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10007 break; /* We have no PHY */
10008
10009 if (!capable(CAP_NET_ADMIN))
10010 return -EPERM;
10011
bc1c7567
MC		 10012 if (tp->link_config.phy_is_low_power)
10013 return -EAGAIN;
10014
f47c11ee 10015 spin_lock_bh(&tp->lock);
1da177e4 10016 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10017 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10018
10019 return err;
10020
10021 default:
10022 /* do nothing */
10023 break;
10024 }
10025 return -EOPNOTSUPP;
10026}
10027
10028#if TG3_VLAN_TAG_USED
10029static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10030{
10031 struct tg3 *tp = netdev_priv(dev);
10032
844b3eed
MC		 10033 if (!netif_running(dev)) {
10034 tp->vlgrp = grp;
10035 return;
10036 }
10037
10038 tg3_netif_stop(tp);
29315e87 10039
f47c11ee 10040 tg3_full_lock(tp, 0);
1da177e4
LT		 10041
10042 tp->vlgrp = grp;
10043
10044 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10045 __tg3_set_rx_mode(dev);
10046
844b3eed 10047 tg3_netif_start(tp);
46966545
MC		 10048
10049 tg3_full_unlock(tp);
1da177e4 10050}
1da177e4
LT		 10051#endif
10052
15f9850d
DM		 10053static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10054{
10055 struct tg3 *tp = netdev_priv(dev);
10056
10057 memcpy(ec, &tp->coal, sizeof(*ec));
10058 return 0;
10059}
10060
d244c892
MC		 10061static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10062{
10063 struct tg3 *tp = netdev_priv(dev);
10064 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10065 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10066
10067 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10068 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10069 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10070 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10071 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10072 }
10073
10074 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10075 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10076 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10077 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10078 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10079 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10080 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10081 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10082 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10083 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10084 return -EINVAL;
10085
10086 /* No rx interrupts will be generated if both are zero */
10087 if ((ec->rx_coalesce_usecs == 0) &&
10088 (ec->rx_max_coalesced_frames == 0))
10089 return -EINVAL;
10090
10091 /* No tx interrupts will be generated if both are zero */
10092 if ((ec->tx_coalesce_usecs == 0) &&
10093 (ec->tx_max_coalesced_frames == 0))
10094 return -EINVAL;
10095
10096 /* Only copy relevant parameters, ignore all others. */
10097 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10098 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10099 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10100 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10101 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10102 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10103 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10104 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10105 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10106
10107 if (netif_running(dev)) {
10108 tg3_full_lock(tp, 0);
10109 __tg3_set_coalesce(tp, &tp->coal);
10110 tg3_full_unlock(tp);
10111 }
10112 return 0;
10113}
10114
7282d491 10115static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10116 .get_settings = tg3_get_settings,
10117 .set_settings = tg3_set_settings,
10118 .get_drvinfo = tg3_get_drvinfo,
10119 .get_regs_len = tg3_get_regs_len,
10120 .get_regs = tg3_get_regs,
10121 .get_wol = tg3_get_wol,
10122 .set_wol = tg3_set_wol,
10123 .get_msglevel = tg3_get_msglevel,
10124 .set_msglevel = tg3_set_msglevel,
10125 .nway_reset = tg3_nway_reset,
10126 .get_link = ethtool_op_get_link,
10127 .get_eeprom_len = tg3_get_eeprom_len,
10128 .get_eeprom = tg3_get_eeprom,
10129 .set_eeprom = tg3_set_eeprom,
10130 .get_ringparam = tg3_get_ringparam,
10131 .set_ringparam = tg3_set_ringparam,
10132 .get_pauseparam = tg3_get_pauseparam,
10133 .set_pauseparam = tg3_set_pauseparam,
10134 .get_rx_csum = tg3_get_rx_csum,
10135 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10136 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10137 .set_sg = ethtool_op_set_sg,
1da177e4 10138 .set_tso = tg3_set_tso,
4cafd3f5 10139 .self_test = tg3_self_test,
1da177e4 10140 .get_strings = tg3_get_strings,
4009a93d 10141 .phys_id = tg3_phys_id,
1da177e4 10142 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10143 .get_coalesce = tg3_get_coalesce,
d244c892 10144 .set_coalesce = tg3_set_coalesce,
b9f2c044 10145 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10146};
10147
10148static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10149{
1b27777a 10150 u32 cursize, val, magic;
1da177e4
LT		 10151
10152 tp->nvram_size = EEPROM_CHIP_SIZE;
10153
e4f34110 10154 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10155 return;
10156
b16250e3
MC		 10157 if ((magic != TG3_EEPROM_MAGIC) &&
10158 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10159 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10160 return;
10161
10162 /*
10163 * Size the chip by reading offsets at increasing powers of two.
10164 * When we encounter our validation signature, we know the addressing
10165 * has wrapped around, and thus have our chip size.
10166 */
1b27777a 10167 cursize = 0x10;
1da177e4
LT		 10168
10169 while (cursize < tp->nvram_size) {
e4f34110 10170 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10171 return;
10172
1820180b 10173 if (val == magic)
1da177e4
LT		 10174 break;
10175
10176 cursize <<= 1;
10177 }
10178
10179 tp->nvram_size = cursize;
10180}
6aa20a22 10181
1da177e4
LT		 10182static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10183{
10184 u32 val;
10185
e4f34110 10186 if (tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10187 return;
10188
10189 /* Selfboot format */
1820180b 10190 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10191 tg3_get_eeprom_size(tp);
10192 return;
10193 }
10194
6d348f2c 10195 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10196 if (val != 0) {
6d348f2c
MC		 10197 /* This is confusing. We want to operate on the
10198 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10199 * call will read from NVRAM and byteswap the data
10200 * according to the byteswapping settings for all
10201 * other register accesses. This ensures the data we
10202 * want will always reside in the lower 16-bits.
10203 * However, the data in NVRAM is in LE format, which
10204 * means the data from the NVRAM read will always be
10205 * opposite the endianness of the CPU. The 16-bit
10206 * byteswap then brings the data to CPU endianness.
10207 */
10208 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10209 return;
10210 }
10211 }
fd1122a2 10212 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10213}
10214
10215static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10216{
10217 u32 nvcfg1;
10218
10219 nvcfg1 = tr32(NVRAM_CFG1);
10220 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10221 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10222 }
10223 else {
10224 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10225 tw32(NVRAM_CFG1, nvcfg1);
10226 }
10227
4c987487 10228 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10229 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10230 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10231 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10232 tp->nvram_jedecnum = JEDEC_ATMEL;
10233 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10234 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10235 break;
10236 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10237 tp->nvram_jedecnum = JEDEC_ATMEL;
10238 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10239 break;
10240 case FLASH_VENDOR_ATMEL_EEPROM:
10241 tp->nvram_jedecnum = JEDEC_ATMEL;
10242 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10243 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10244 break;
10245 case FLASH_VENDOR_ST:
10246 tp->nvram_jedecnum = JEDEC_ST;
10247 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10248 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10249 break;
10250 case FLASH_VENDOR_SAIFUN:
10251 tp->nvram_jedecnum = JEDEC_SAIFUN;
10252 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10253 break;
10254 case FLASH_VENDOR_SST_SMALL:
10255 case FLASH_VENDOR_SST_LARGE:
10256 tp->nvram_jedecnum = JEDEC_SST;
10257 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10258 break;
10259 }
10260 }
10261 else {
10262 tp->nvram_jedecnum = JEDEC_ATMEL;
10263 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10264 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10265 }
10266}
10267
361b4ac2
MC		 10268static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10269{
10270 u32 nvcfg1;
10271
10272 nvcfg1 = tr32(NVRAM_CFG1);
10273
e6af301b
MC		 10274 /* NVRAM protection for TPM */
10275 if (nvcfg1 & (1 << 27))
10276 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10277
361b4ac2
MC		 10278 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10279 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10280 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10281 tp->nvram_jedecnum = JEDEC_ATMEL;
10282 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10283 break;
10284 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10285 tp->nvram_jedecnum = JEDEC_ATMEL;
10286 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10287 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10288 break;
10289 case FLASH_5752VENDOR_ST_M45PE10:
10290 case FLASH_5752VENDOR_ST_M45PE20:
10291 case FLASH_5752VENDOR_ST_M45PE40:
10292 tp->nvram_jedecnum = JEDEC_ST;
10293 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10294 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10295 break;
10296 }
10297
10298 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10299 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10300 case FLASH_5752PAGE_SIZE_256:
10301 tp->nvram_pagesize = 256;
10302 break;
10303 case FLASH_5752PAGE_SIZE_512:
10304 tp->nvram_pagesize = 512;
10305 break;
10306 case FLASH_5752PAGE_SIZE_1K:
10307 tp->nvram_pagesize = 1024;
10308 break;
10309 case FLASH_5752PAGE_SIZE_2K:
10310 tp->nvram_pagesize = 2048;
10311 break;
10312 case FLASH_5752PAGE_SIZE_4K:
10313 tp->nvram_pagesize = 4096;
10314 break;
10315 case FLASH_5752PAGE_SIZE_264:
10316 tp->nvram_pagesize = 264;
10317 break;
10318 }
10319 }
10320 else {
10321 /* For eeprom, set pagesize to maximum eeprom size */
10322 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10323
10324 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10325 tw32(NVRAM_CFG1, nvcfg1);
10326 }
10327}
10328
d3c7b886
MC		 10329static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10330{
989a9d23 10331 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10332
10333 nvcfg1 = tr32(NVRAM_CFG1);
10334
10335 /* NVRAM protection for TPM */
989a9d23 10336 if (nvcfg1 & (1 << 27)) {
d3c7b886 10337 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10338 protect = 1;
10339 }
d3c7b886 10340
989a9d23
MC		 10341 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10342 switch (nvcfg1) {
d3c7b886
MC		 10343 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10344 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10345 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10346 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10347 tp->nvram_jedecnum = JEDEC_ATMEL;
10348 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10349 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10350 tp->nvram_pagesize = 264;
70b65a2d
MC		 10351 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10352 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10353 tp->nvram_size = (protect ? 0x3e200 :
10354 TG3_NVRAM_SIZE_512KB);
989a9d23 10355 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10356 tp->nvram_size = (protect ? 0x1f200 :
10357 TG3_NVRAM_SIZE_256KB);
989a9d23 10358 else
fd1122a2
MC		 10359 tp->nvram_size = (protect ? 0x1f200 :
10360 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10361 break;
10362 case FLASH_5752VENDOR_ST_M45PE10:
10363 case FLASH_5752VENDOR_ST_M45PE20:
10364 case FLASH_5752VENDOR_ST_M45PE40:
10365 tp->nvram_jedecnum = JEDEC_ST;
10366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10368 tp->nvram_pagesize = 256;
989a9d23 10369 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10370 tp->nvram_size = (protect ?
10371 TG3_NVRAM_SIZE_64KB :
10372 TG3_NVRAM_SIZE_128KB);
989a9d23 10373 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10374 tp->nvram_size = (protect ?
10375 TG3_NVRAM_SIZE_64KB :
10376 TG3_NVRAM_SIZE_256KB);
989a9d23 10377 else
fd1122a2
MC		 10378 tp->nvram_size = (protect ?
10379 TG3_NVRAM_SIZE_128KB :
10380 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10381 break;
10382 }
10383}
10384
1b27777a
MC		 10385static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10386{
10387 u32 nvcfg1;
10388
10389 nvcfg1 = tr32(NVRAM_CFG1);
10390
10391 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10392 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10393 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10394 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10395 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10396 tp->nvram_jedecnum = JEDEC_ATMEL;
10397 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10398 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10399
10400 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10401 tw32(NVRAM_CFG1, nvcfg1);
10402 break;
10403 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10404 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10405 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10406 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10407 tp->nvram_jedecnum = JEDEC_ATMEL;
10408 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10409 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10410 tp->nvram_pagesize = 264;
10411 break;
10412 case FLASH_5752VENDOR_ST_M45PE10:
10413 case FLASH_5752VENDOR_ST_M45PE20:
10414 case FLASH_5752VENDOR_ST_M45PE40:
10415 tp->nvram_jedecnum = JEDEC_ST;
10416 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10417 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10418 tp->nvram_pagesize = 256;
10419 break;
10420 }
10421}
10422
6b91fa02
MC		 10423static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10424{
10425 u32 nvcfg1, protect = 0;
10426
10427 nvcfg1 = tr32(NVRAM_CFG1);
10428
10429 /* NVRAM protection for TPM */
10430 if (nvcfg1 & (1 << 27)) {
10431 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10432 protect = 1;
10433 }
10434
10435 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10436 switch (nvcfg1) {
10437 case FLASH_5761VENDOR_ATMEL_ADB021D:
10438 case FLASH_5761VENDOR_ATMEL_ADB041D:
10439 case FLASH_5761VENDOR_ATMEL_ADB081D:
10440 case FLASH_5761VENDOR_ATMEL_ADB161D:
10441 case FLASH_5761VENDOR_ATMEL_MDB021D:
10442 case FLASH_5761VENDOR_ATMEL_MDB041D:
10443 case FLASH_5761VENDOR_ATMEL_MDB081D:
10444 case FLASH_5761VENDOR_ATMEL_MDB161D:
10445 tp->nvram_jedecnum = JEDEC_ATMEL;
10446 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10447 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10448 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10449 tp->nvram_pagesize = 256;
10450 break;
10451 case FLASH_5761VENDOR_ST_A_M45PE20:
10452 case FLASH_5761VENDOR_ST_A_M45PE40:
10453 case FLASH_5761VENDOR_ST_A_M45PE80:
10454 case FLASH_5761VENDOR_ST_A_M45PE16:
10455 case FLASH_5761VENDOR_ST_M_M45PE20:
10456 case FLASH_5761VENDOR_ST_M_M45PE40:
10457 case FLASH_5761VENDOR_ST_M_M45PE80:
10458 case FLASH_5761VENDOR_ST_M_M45PE16:
10459 tp->nvram_jedecnum = JEDEC_ST;
10460 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10461 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10462 tp->nvram_pagesize = 256;
10463 break;
10464 }
10465
10466 if (protect) {
10467 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10468 } else {
10469 switch (nvcfg1) {
10470 case FLASH_5761VENDOR_ATMEL_ADB161D:
10471 case FLASH_5761VENDOR_ATMEL_MDB161D:
10472 case FLASH_5761VENDOR_ST_A_M45PE16:
10473 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10474 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10475 break;
10476 case FLASH_5761VENDOR_ATMEL_ADB081D:
10477 case FLASH_5761VENDOR_ATMEL_MDB081D:
10478 case FLASH_5761VENDOR_ST_A_M45PE80:
10479 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10480 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10481 break;
10482 case FLASH_5761VENDOR_ATMEL_ADB041D:
10483 case FLASH_5761VENDOR_ATMEL_MDB041D:
10484 case FLASH_5761VENDOR_ST_A_M45PE40:
10485 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10486 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10487 break;
10488 case FLASH_5761VENDOR_ATMEL_ADB021D:
10489 case FLASH_5761VENDOR_ATMEL_MDB021D:
10490 case FLASH_5761VENDOR_ST_A_M45PE20:
10491 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10492 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10493 break;
10494 }
10495 }
10496}
10497
b5d3772c
MC		 10498static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10499{
10500 tp->nvram_jedecnum = JEDEC_ATMEL;
10501 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10502 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10503}
10504
321d32a0
MC		 10505static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10506{
10507 u32 nvcfg1;
10508
10509 nvcfg1 = tr32(NVRAM_CFG1);
10510
10511 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10512 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10513 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10514 tp->nvram_jedecnum = JEDEC_ATMEL;
10515 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10516 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10517
10518 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10519 tw32(NVRAM_CFG1, nvcfg1);
10520 return;
10521 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10522 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10523 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10524 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10525 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10526 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10527 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10528 tp->nvram_jedecnum = JEDEC_ATMEL;
10529 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10530 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10531
10532 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10533 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10534 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10535 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10536 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10537 break;
10538 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10539 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10540 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10541 break;
10542 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10543 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10544 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10545 break;
10546 }
10547 break;
10548 case FLASH_5752VENDOR_ST_M45PE10:
10549 case FLASH_5752VENDOR_ST_M45PE20:
10550 case FLASH_5752VENDOR_ST_M45PE40:
10551 tp->nvram_jedecnum = JEDEC_ST;
10552 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10553 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10554
10555 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10556 case FLASH_5752VENDOR_ST_M45PE10:
10557 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10558 break;
10559 case FLASH_5752VENDOR_ST_M45PE20:
10560 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10561 break;
10562 case FLASH_5752VENDOR_ST_M45PE40:
10563 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10564 break;
10565 }
10566 break;
10567 default:
10568 return;
10569 }
10570
10571 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10572 case FLASH_5752PAGE_SIZE_256:
10573 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10574 tp->nvram_pagesize = 256;
10575 break;
10576 case FLASH_5752PAGE_SIZE_512:
10577 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10578 tp->nvram_pagesize = 512;
10579 break;
10580 case FLASH_5752PAGE_SIZE_1K:
10581 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10582 tp->nvram_pagesize = 1024;
10583 break;
10584 case FLASH_5752PAGE_SIZE_2K:
10585 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10586 tp->nvram_pagesize = 2048;
10587 break;
10588 case FLASH_5752PAGE_SIZE_4K:
10589 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10590 tp->nvram_pagesize = 4096;
10591 break;
10592 case FLASH_5752PAGE_SIZE_264:
10593 tp->nvram_pagesize = 264;
10594 break;
10595 case FLASH_5752PAGE_SIZE_528:
10596 tp->nvram_pagesize = 528;
10597 break;
10598 }
10599}
10600
1da177e4
LT		 10601/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10602static void __devinit tg3_nvram_init(struct tg3 *tp)
10603{
1da177e4
LT		 10604 tw32_f(GRC_EEPROM_ADDR,
10605 (EEPROM_ADDR_FSM_RESET |
10606 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10607 EEPROM_ADDR_CLKPERD_SHIFT)));
10608
9d57f01c 10609 msleep(1);
1da177e4
LT		 10610
10611 /* Enable seeprom accesses. */
10612 tw32_f(GRC_LOCAL_CTRL,
10613 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10614 udelay(100);
10615
10616 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10617 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10618 tp->tg3_flags |= TG3_FLAG_NVRAM;
10619
ec41c7df
MC		 10620 if (tg3_nvram_lock(tp)) {
10621 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10622 "tg3_nvram_init failed.\n", tp->dev->name);
10623 return;
10624 }
e6af301b 10625 tg3_enable_nvram_access(tp);
1da177e4 10626
989a9d23
MC		 10627 tp->nvram_size = 0;
10628
361b4ac2
MC		 10629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10630 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10631 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10632 tg3_get_5755_nvram_info(tp);
d30cdd28 10633 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10636 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10637 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10638 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10639 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10640 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10641 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10642 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10643 else
10644 tg3_get_nvram_info(tp);
10645
989a9d23
MC		 10646 if (tp->nvram_size == 0)
10647 tg3_get_nvram_size(tp);
1da177e4 10648
e6af301b 10649 tg3_disable_nvram_access(tp);
381291b7 10650 tg3_nvram_unlock(tp);
1da177e4
LT		 10651
10652 } else {
10653 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10654
10655 tg3_get_eeprom_size(tp);
10656 }
10657}
10658
1da177e4
LT		 10659static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10660 u32 offset, u32 len, u8 *buf)
10661{
10662 int i, j, rc = 0;
10663 u32 val;
10664
10665 for (i = 0; i < len; i += 4) {
b9fc7dc5 10666 u32 addr;
a9dc529d 10667 __be32 data;
1da177e4
LT		 10668
10669 addr = offset + i;
10670
10671 memcpy(&data, buf + i, 4);
10672
62cedd11
MC		 10673 /*
10674 * The SEEPROM interface expects the data to always be opposite
10675 * the native endian format. We accomplish this by reversing
10676 * all the operations that would have been performed on the
10677 * data from a call to tg3_nvram_read_be32().
10678 */
10679 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10680
10681 val = tr32(GRC_EEPROM_ADDR);
10682 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10683
10684 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10685 EEPROM_ADDR_READ);
10686 tw32(GRC_EEPROM_ADDR, val |
10687 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10688 (addr & EEPROM_ADDR_ADDR_MASK) |
10689 EEPROM_ADDR_START |
10690 EEPROM_ADDR_WRITE);
6aa20a22 10691
9d57f01c 10692 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10693 val = tr32(GRC_EEPROM_ADDR);
10694
10695 if (val & EEPROM_ADDR_COMPLETE)
10696 break;
9d57f01c 10697 msleep(1);
1da177e4
LT		 10698 }
10699 if (!(val & EEPROM_ADDR_COMPLETE)) {
10700 rc = -EBUSY;
10701 break;
10702 }
10703 }
10704
10705 return rc;
10706}
10707
10708/* offset and length are dword aligned */
10709static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10710 u8 *buf)
10711{
10712 int ret = 0;
10713 u32 pagesize = tp->nvram_pagesize;
10714 u32 pagemask = pagesize - 1;
10715 u32 nvram_cmd;
10716 u8 *tmp;
10717
10718 tmp = kmalloc(pagesize, GFP_KERNEL);
10719 if (tmp == NULL)
10720 return -ENOMEM;
10721
10722 while (len) {
10723 int j;
e6af301b 10724 u32 phy_addr, page_off, size;
1da177e4
LT		 10725
10726 phy_addr = offset & ~pagemask;
6aa20a22 10727
1da177e4 10728 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10729 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10730 (__be32 *) (tmp + j));
10731 if (ret)
1da177e4
LT		 10732 break;
10733 }
10734 if (ret)
10735 break;
10736
10737 page_off = offset & pagemask;
10738 size = pagesize;
10739 if (len < size)
10740 size = len;
10741
10742 len -= size;
10743
10744 memcpy(tmp + page_off, buf, size);
10745
10746 offset = offset + (pagesize - page_off);
10747
e6af301b 10748 tg3_enable_nvram_access(tp);
1da177e4
LT		 10749
10750 /*
10751 * Before we can erase the flash page, we need
10752 * to issue a special "write enable" command.
10753 */
10754 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10755
10756 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10757 break;
10758
10759 /* Erase the target page */
10760 tw32(NVRAM_ADDR, phy_addr);
10761
10762 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10763 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10764
10765 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10766 break;
10767
10768 /* Issue another write enable to start the write. */
10769 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10770
10771 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10772 break;
10773
10774 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10775 __be32 data;
1da177e4 10776
b9fc7dc5 10777 data = *((__be32 *) (tmp + j));
a9dc529d 10778
b9fc7dc5 10779 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10780
10781 tw32(NVRAM_ADDR, phy_addr + j);
10782
10783 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10784 NVRAM_CMD_WR;
10785
10786 if (j == 0)
10787 nvram_cmd |= NVRAM_CMD_FIRST;
10788 else if (j == (pagesize - 4))
10789 nvram_cmd |= NVRAM_CMD_LAST;
10790
10791 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10792 break;
10793 }
10794 if (ret)
10795 break;
10796 }
10797
10798 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10799 tg3_nvram_exec_cmd(tp, nvram_cmd);
10800
10801 kfree(tmp);
10802
10803 return ret;
10804}
10805
10806/* offset and length are dword aligned */
10807static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10808 u8 *buf)
10809{
10810 int i, ret = 0;
10811
10812 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10813 u32 page_off, phy_addr, nvram_cmd;
10814 __be32 data;
1da177e4
LT		 10815
10816 memcpy(&data, buf + i, 4);
b9fc7dc5 10817 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10818
10819 page_off = offset % tp->nvram_pagesize;
10820
1820180b 10821 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10822
10823 tw32(NVRAM_ADDR, phy_addr);
10824
10825 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10826
10827 if ((page_off == 0) || (i == 0))
10828 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10829 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10830 nvram_cmd |= NVRAM_CMD_LAST;
10831
10832 if (i == (len - 4))
10833 nvram_cmd |= NVRAM_CMD_LAST;
10834
321d32a0
MC		 10835 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10836 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10837 (tp->nvram_jedecnum == JEDEC_ST) &&
10838 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10839
10840 if ((ret = tg3_nvram_exec_cmd(tp,
10841 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10842 NVRAM_CMD_DONE)))
10843
10844 break;
10845 }
10846 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10847 /* We always do complete word writes to eeprom. */
10848 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10849 }
10850
10851 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10852 break;
10853 }
10854 return ret;
10855}
10856
10857/* offset and length are dword aligned */
10858static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10859{
10860 int ret;
10861
1da177e4 10862 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10863 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10864 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10865 udelay(40);
10866 }
10867
10868 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10869 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10870 }
10871 else {
10872 u32 grc_mode;
10873
ec41c7df
MC		 10874 ret = tg3_nvram_lock(tp);
10875 if (ret)
10876 return ret;
1da177e4 10877
e6af301b
MC		 10878 tg3_enable_nvram_access(tp);
10879 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10880 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10881 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10882
10883 grc_mode = tr32(GRC_MODE);
10884 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10885
10886 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10887 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10888
10889 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10890 buf);
10891 }
10892 else {
10893 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10894 buf);
10895 }
10896
10897 grc_mode = tr32(GRC_MODE);
10898 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10899
e6af301b 10900 tg3_disable_nvram_access(tp);
1da177e4
LT		 10901 tg3_nvram_unlock(tp);
10902 }
10903
10904 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10905 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10906 udelay(40);
10907 }
10908
10909 return ret;
10910}
10911
10912struct subsys_tbl_ent {
10913 u16 subsys_vendor, subsys_devid;
10914 u32 phy_id;
10915};
10916
10917static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10918 /* Broadcom boards. */
10919 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10920 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10921 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10922 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10923 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10924 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10925 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10926 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10927 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10928 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10929 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10930
10931 /* 3com boards. */
10932 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10933 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10934 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10935 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10936 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10937
10938 /* DELL boards. */
10939 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10940 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10941 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10942 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10943
10944 /* Compaq boards. */
10945 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10946 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10947 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10948 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10949 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10950
10951 /* IBM boards. */
10952 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10953};
10954
10955static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10956{
10957 int i;
10958
10959 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10960 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10961 tp->pdev->subsystem_vendor) &&
10962 (subsys_id_to_phy_id[i].subsys_devid ==
10963 tp->pdev->subsystem_device))
10964 return &subsys_id_to_phy_id[i];
10965 }
10966 return NULL;
10967}
10968
7d0c41ef 10969static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10970{
1da177e4 10971 u32 val;
caf636c7
MC		 10972 u16 pmcsr;
10973
10974 /* On some early chips the SRAM cannot be accessed in D3hot state,
10975 * so need make sure we're in D0.
10976 */
10977 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10978 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10979 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10980 msleep(1);
7d0c41ef
MC		 10981
10982 /* Make sure register accesses (indirect or otherwise)
10983 * will function correctly.
10984 */
10985 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10986 tp->misc_host_ctrl);
1da177e4 10987
f49639e6
DM		 10988 /* The memory arbiter has to be enabled in order for SRAM accesses
10989 * to succeed. Normally on powerup the tg3 chip firmware will make
10990 * sure it is enabled, but other entities such as system netboot
10991 * code might disable it.
10992 */
10993 val = tr32(MEMARB_MODE);
10994 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10995
1da177e4 10996 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10997 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10998
a85feb8c
GZ		 10999 /* Assume an onboard device and WOL capable by default. */
11000 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11001
b5d3772c 11002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11003 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11004 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11005 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11006 }
0527ba35
MC		 11007 val = tr32(VCPU_CFGSHDW);
11008 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11009 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11010 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11011 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11012 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11013 goto done;
b5d3772c
MC		 11014 }
11015
1da177e4
LT		 11016 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11017 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11018 u32 nic_cfg, led_cfg;
a9daf367 11019 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11020 int eeprom_phy_serdes = 0;
1da177e4
LT		 11021
11022 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11023 tp->nic_sram_data_cfg = nic_cfg;
11024
11025 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11026 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11027 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11028 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11029 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11030 (ver > 0) && (ver < 0x100))
11031 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11032
a9daf367
MC		 11033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11034 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11035
1da177e4
LT		 11036 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11037 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11038 eeprom_phy_serdes = 1;
11039
11040 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11041 if (nic_phy_id != 0) {
11042 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11043 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11044
11045 eeprom_phy_id = (id1 >> 16) << 10;
11046 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11047 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11048 } else
11049 eeprom_phy_id = 0;
11050
7d0c41ef 11051 tp->phy_id = eeprom_phy_id;
747e8f8b 11052 if (eeprom_phy_serdes) {
a4e2b347 11053 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11054 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11055 else
11056 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11057 }
7d0c41ef 11058
cbf46853 11059 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11060 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11061 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11062 else
1da177e4
LT		 11063 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11064
11065 switch (led_cfg) {
11066 default:
11067 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11068 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11069 break;
11070
11071 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11072 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11073 break;
11074
11075 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11076 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11077
11078 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11079 * read on some older 5700/5701 bootcode.
11080 */
11081 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11082 ASIC_REV_5700 ||
11083 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11084 ASIC_REV_5701)
11085 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11086
1da177e4
LT		 11087 break;
11088
11089 case SHASTA_EXT_LED_SHARED:
11090 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11091 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11092 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11093 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11094 LED_CTRL_MODE_PHY_2);
11095 break;
11096
11097 case SHASTA_EXT_LED_MAC:
11098 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11099 break;
11100
11101 case SHASTA_EXT_LED_COMBO:
11102 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11103 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11104 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11105 LED_CTRL_MODE_PHY_2);
11106 break;
11107
855e1111 11108 }
1da177e4
LT		 11109
11110 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11112 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11113 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11114
b2a5c19c
MC		 11115 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11116 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11117
9d26e213 11118 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11119 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11120 if ((tp->pdev->subsystem_vendor ==
11121 PCI_VENDOR_ID_ARIMA) &&
11122 (tp->pdev->subsystem_device == 0x205a ||
11123 tp->pdev->subsystem_device == 0x2063))
11124 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11125 } else {
f49639e6 11126 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11127 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11128 }
1da177e4
LT		 11129
11130 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11131 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11132 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11133 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11134 }
b2b98d4a
MC		 11135
11136 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11137 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11138 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11139
a85feb8c
GZ		 11140 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11141 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11142 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11143
12dac075 11144 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11145 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11146 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11147
1da177e4
LT		 11148 if (cfg2 & (1 << 17))
11149 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11150
11151 /* serdes signal pre-emphasis in register 0x590 set by */
11152 /* bootcode if bit 18 is set */
11153 if (cfg2 & (1 << 18))
11154 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11155
321d32a0
MC		 11156 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11157 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11158 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11159 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11160
8ed5d97e
MC		 11161 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11162 u32 cfg3;
11163
11164 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11165 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11166 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11167 }
a9daf367
MC		 11168
11169 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11170 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11171 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11172 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11173 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11174 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11175 }
05ac4cb7
MC		 11176done:
11177 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11178 device_set_wakeup_enable(&tp->pdev->dev,
11179 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11180}
11181
b2a5c19c
MC		 11182static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11183{
11184 int i;
11185 u32 val;
11186
11187 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11188 tw32(OTP_CTRL, cmd);
11189
11190 /* Wait for up to 1 ms for command to execute. */
11191 for (i = 0; i < 100; i++) {
11192 val = tr32(OTP_STATUS);
11193 if (val & OTP_STATUS_CMD_DONE)
11194 break;
11195 udelay(10);
11196 }
11197
11198 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11199}
11200
11201/* Read the gphy configuration from the OTP region of the chip. The gphy
11202 * configuration is a 32-bit value that straddles the alignment boundary.
11203 * We do two 32-bit reads and then shift and merge the results.
11204 */
11205static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11206{
11207 u32 bhalf_otp, thalf_otp;
11208
11209 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11210
11211 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11212 return 0;
11213
11214 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11215
11216 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11217 return 0;
11218
11219 thalf_otp = tr32(OTP_READ_DATA);
11220
11221 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11222
11223 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11224 return 0;
11225
11226 bhalf_otp = tr32(OTP_READ_DATA);
11227
11228 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11229}
11230
7d0c41ef
MC		 11231static int __devinit tg3_phy_probe(struct tg3 *tp)
11232{
11233 u32 hw_phy_id_1, hw_phy_id_2;
11234 u32 hw_phy_id, hw_phy_id_masked;
11235 int err;
1da177e4 11236
b02fd9e3
MC		 11237 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11238 return tg3_phy_init(tp);
11239
1da177e4 11240 /* Reading the PHY ID register can conflict with ASF
877d0310 11241 * firmware access to the PHY hardware.
1da177e4
LT		 11242 */
11243 err = 0;
0d3031d9
MC		 11244 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11245 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11246 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11247 } else {
11248 /* Now read the physical PHY_ID from the chip and verify
11249 * that it is sane. If it doesn't look good, we fall back
11250 * to either the hard-coded table based PHY_ID and failing
11251 * that the value found in the eeprom area.
11252 */
11253 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11254 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11255
11256 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11257 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11258 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11259
11260 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11261 }
11262
11263 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11264 tp->phy_id = hw_phy_id;
11265 if (hw_phy_id_masked == PHY_ID_BCM8002)
11266 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11267 else
11268 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11269 } else {
7d0c41ef
MC		 11270 if (tp->phy_id != PHY_ID_INVALID) {
11271 /* Do nothing, phy ID already set up in
11272 * tg3_get_eeprom_hw_cfg().
11273 */
1da177e4
LT		 11274 } else {
11275 struct subsys_tbl_ent *p;
11276
11277 /* No eeprom signature? Try the hardcoded
11278 * subsys device table.
11279 */
11280 p = lookup_by_subsys(tp);
11281 if (!p)
11282 return -ENODEV;
11283
11284 tp->phy_id = p->phy_id;
11285 if (!tp->phy_id ||
11286 tp->phy_id == PHY_ID_BCM8002)
11287 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11288 }
11289 }
11290
747e8f8b 11291 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11292 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11293 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11294 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11295
11296 tg3_readphy(tp, MII_BMSR, &bmsr);
11297 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11298 (bmsr & BMSR_LSTATUS))
11299 goto skip_phy_reset;
6aa20a22 11300
1da177e4
LT		 11301 err = tg3_phy_reset(tp);
11302 if (err)
11303 return err;
11304
11305 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11306 ADVERTISE_100HALF | ADVERTISE_100FULL |
11307 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11308 tg3_ctrl = 0;
11309 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11310 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11311 MII_TG3_CTRL_ADV_1000_FULL);
11312 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11313 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11314 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11315 MII_TG3_CTRL_ENABLE_AS_MASTER);
11316 }
11317
3600d918
MC		 11318 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11319 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11320 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11321 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11322 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11323
11324 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11325 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11326
11327 tg3_writephy(tp, MII_BMCR,
11328 BMCR_ANENABLE | BMCR_ANRESTART);
11329 }
11330 tg3_phy_set_wirespeed(tp);
11331
11332 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11333 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11334 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11335 }
11336
11337skip_phy_reset:
11338 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11339 err = tg3_init_5401phy_dsp(tp);
11340 if (err)
11341 return err;
11342 }
11343
11344 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11345 err = tg3_init_5401phy_dsp(tp);
11346 }
11347
747e8f8b 11348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11349 tp->link_config.advertising =
11350 (ADVERTISED_1000baseT_Half |
11351 ADVERTISED_1000baseT_Full |
11352 ADVERTISED_Autoneg |
11353 ADVERTISED_FIBRE);
11354 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11355 tp->link_config.advertising &=
11356 ~(ADVERTISED_1000baseT_Half |
11357 ADVERTISED_1000baseT_Full);
11358
11359 return err;
11360}
11361
11362static void __devinit tg3_read_partno(struct tg3 *tp)
11363{
6d348f2c 11364 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11365 unsigned int i;
1b27777a 11366 u32 magic;
1da177e4 11367
e4f34110 11368 if (tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11369 goto out_not_found;
1da177e4 11370
1820180b 11371 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11372 for (i = 0; i < 256; i += 4) {
11373 u32 tmp;
1da177e4 11374
6d348f2c
MC		 11375 /* The data is in little-endian format in NVRAM.
11376 * Use the big-endian read routines to preserve
11377 * the byte order as it exists in NVRAM.
11378 */
11379 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11380 goto out_not_found;
11381
6d348f2c 11382 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11383 }
11384 } else {
11385 int vpd_cap;
11386
11387 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11388 for (i = 0; i < 256; i += 4) {
11389 u32 tmp, j = 0;
b9fc7dc5 11390 __le32 v;
1b27777a
MC		 11391 u16 tmp16;
11392
11393 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11394 i);
11395 while (j++ < 100) {
11396 pci_read_config_word(tp->pdev, vpd_cap +
11397 PCI_VPD_ADDR, &tmp16);
11398 if (tmp16 & 0x8000)
11399 break;
11400 msleep(1);
11401 }
f49639e6
DM		 11402 if (!(tmp16 & 0x8000))
11403 goto out_not_found;
11404
1b27777a
MC		 11405 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11406 &tmp);
b9fc7dc5 11407 v = cpu_to_le32(tmp);
6d348f2c 11408 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11409 }
1da177e4
LT		 11410 }
11411
11412 /* Now parse and find the part number. */
af2c6a4a 11413 for (i = 0; i < 254; ) {
1da177e4 11414 unsigned char val = vpd_data[i];
af2c6a4a 11415 unsigned int block_end;
1da177e4
LT		 11416
11417 if (val == 0x82 || val == 0x91) {
11418 i = (i + 3 +
11419 (vpd_data[i + 1] +
11420 (vpd_data[i + 2] << 8)));
11421 continue;
11422 }
11423
11424 if (val != 0x90)
11425 goto out_not_found;
11426
11427 block_end = (i + 3 +
11428 (vpd_data[i + 1] +
11429 (vpd_data[i + 2] << 8)));
11430 i += 3;
af2c6a4a
MC		 11431
11432 if (block_end > 256)
11433 goto out_not_found;
11434
11435 while (i < (block_end - 2)) {
1da177e4
LT		 11436 if (vpd_data[i + 0] == 'P' &&
11437 vpd_data[i + 1] == 'N') {
11438 int partno_len = vpd_data[i + 2];
11439
af2c6a4a
MC		 11440 i += 3;
11441 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11442 goto out_not_found;
11443
11444 memcpy(tp->board_part_number,
af2c6a4a 11445 &vpd_data[i], partno_len);
1da177e4
LT		 11446
11447 /* Success. */
11448 return;
11449 }
af2c6a4a 11450 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11451 }
11452
11453 /* Part number not found. */
11454 goto out_not_found;
11455 }
11456
11457out_not_found:
b5d3772c
MC		 11458 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11459 strcpy(tp->board_part_number, "BCM95906");
11460 else
11461 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11462}
11463
9c8a620e
MC		 11464static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11465{
11466 u32 val;
11467
e4f34110 11468 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11469 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11470 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11471 val != 0)
11472 return 0;
11473
11474 return 1;
11475}
11476
acd9c119
MC		 11477static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11478{
ff3a7cb2 11479 u32 val, offset, start, ver_offset;
acd9c119 11480 int i;
ff3a7cb2 11481 bool newver = false;
acd9c119
MC		 11482
11483 if (tg3_nvram_read(tp, 0xc, &offset) ||
11484 tg3_nvram_read(tp, 0x4, &start))
11485 return;
11486
11487 offset = tg3_nvram_logical_addr(tp, offset);
11488
ff3a7cb2 11489 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11490 return;
11491
ff3a7cb2
MC		 11492 if ((val & 0xfc000000) == 0x0c000000) {
11493 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11494 return;
11495
ff3a7cb2
MC		 11496 if (val == 0)
11497 newver = true;
11498 }
11499
11500 if (newver) {
11501 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11502 return;
11503
11504 offset = offset + ver_offset - start;
11505 for (i = 0; i < 16; i += 4) {
11506 __be32 v;
11507 if (tg3_nvram_read_be32(tp, offset + i, &v))
11508 return;
11509
11510 memcpy(tp->fw_ver + i, &v, sizeof(v));
11511 }
11512 } else {
11513 u32 major, minor;
11514
11515 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11516 return;
11517
11518 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11519 TG3_NVM_BCVER_MAJSFT;
11520 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11521 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11522 }
11523}
11524
a6f6cb1c
MC		 11525static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11526{
11527 u32 val, major, minor;
11528
11529 /* Use native endian representation */
11530 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11531 return;
11532
11533 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11534 TG3_NVM_HWSB_CFG1_MAJSFT;
11535 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11536 TG3_NVM_HWSB_CFG1_MINSFT;
11537
11538 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11539}
11540
dfe00d7d
MC		 11541static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11542{
11543 u32 offset, major, minor, build;
11544
11545 tp->fw_ver[0] = 's';
11546 tp->fw_ver[1] = 'b';
11547 tp->fw_ver[2] = '\0';
11548
11549 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11550 return;
11551
11552 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11553 case TG3_EEPROM_SB_REVISION_0:
11554 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11555 break;
11556 case TG3_EEPROM_SB_REVISION_2:
11557 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11558 break;
11559 case TG3_EEPROM_SB_REVISION_3:
11560 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11561 break;
11562 default:
11563 return;
11564 }
11565
e4f34110 11566 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11567 return;
11568
11569 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11570 TG3_EEPROM_SB_EDH_BLD_SHFT;
11571 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11572 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11573 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11574
11575 if (minor > 99 || build > 26)
11576 return;
11577
11578 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11579
11580 if (build > 0) {
11581 tp->fw_ver[8] = 'a' + build - 1;
11582 tp->fw_ver[9] = '\0';
11583 }
11584}
11585
acd9c119 11586static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11587{
11588 u32 val, offset, start;
acd9c119 11589 int i, vlen;
9c8a620e
MC		 11590
11591 for (offset = TG3_NVM_DIR_START;
11592 offset < TG3_NVM_DIR_END;
11593 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11594 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11595 return;
11596
9c8a620e
MC		 11597 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11598 break;
11599 }
11600
11601 if (offset == TG3_NVM_DIR_END)
11602 return;
11603
11604 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11605 start = 0x08000000;
e4f34110 11606 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11607 return;
11608
e4f34110 11609 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11610 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11611 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11612 return;
11613
11614 offset += val - start;
11615
acd9c119 11616 vlen = strlen(tp->fw_ver);
9c8a620e 11617
acd9c119
MC		 11618 tp->fw_ver[vlen++] = ',';
11619 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11620
11621 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11622 __be32 v;
11623 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11624 return;
11625
b9fc7dc5 11626 offset += sizeof(v);
c4e6575c 11627
acd9c119
MC		 11628 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11629 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11630 break;
c4e6575c 11631 }
9c8a620e 11632
acd9c119
MC		 11633 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11634 vlen += sizeof(v);
c4e6575c 11635 }
acd9c119
MC		 11636}
11637
7fd76445
MC		 11638static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11639{
11640 int vlen;
11641 u32 apedata;
11642
11643 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11644 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11645 return;
11646
11647 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11648 if (apedata != APE_SEG_SIG_MAGIC)
11649 return;
11650
11651 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11652 if (!(apedata & APE_FW_STATUS_READY))
11653 return;
11654
11655 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11656
11657 vlen = strlen(tp->fw_ver);
11658
11659 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11660 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11661 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11662 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11663 (apedata & APE_FW_VERSION_BLDMSK));
11664}
11665
acd9c119
MC		 11666static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11667{
11668 u32 val;
11669
11670 if (tg3_nvram_read(tp, 0, &val))
11671 return;
11672
11673 if (val == TG3_EEPROM_MAGIC)
11674 tg3_read_bc_ver(tp);
11675 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11676 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11677 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11678 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11679 else
11680 return;
11681
11682 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11683 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11684 return;
11685
11686 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11687
11688 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11689}
11690
7544b097
MC		 11691static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11692
1da177e4
LT		 11693static int __devinit tg3_get_invariants(struct tg3 *tp)
11694{
11695 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11696 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11697 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11698 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11699 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11700 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11701 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11702 { },
11703 };
11704 u32 misc_ctrl_reg;
1da177e4
LT		 11705 u32 pci_state_reg, grc_misc_cfg;
11706 u32 val;
11707 u16 pci_cmd;
5e7dfd0f 11708 int err;
1da177e4 11709
1da177e4
LT		 11710 /* Force memory write invalidate off. If we leave it on,
11711 * then on 5700_BX chips we have to enable a workaround.
11712 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11713 * to match the cacheline size. The Broadcom driver have this
11714 * workaround but turns MWI off all the times so never uses
11715 * it. This seems to suggest that the workaround is insufficient.
11716 */
11717 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11718 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11719 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11720
11721 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11722 * has the register indirect write enable bit set before
11723 * we try to access any of the MMIO registers. It is also
11724 * critical that the PCI-X hw workaround situation is decided
11725 * before that as well.
11726 */
11727 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11728 &misc_ctrl_reg);
11729
11730 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11731 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11733 u32 prod_id_asic_rev;
11734
11735 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11736 &prod_id_asic_rev);
321d32a0 11737 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11738 }
1da177e4 11739
ff645bec
MC		 11740 /* Wrong chip ID in 5752 A0. This code can be removed later
11741 * as A0 is not in production.
11742 */
11743 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11744 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11745
6892914f
MC		 11746 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11747 * we need to disable memory and use config. cycles
11748 * only to access all registers. The 5702/03 chips
11749 * can mistakenly decode the special cycles from the
11750 * ICH chipsets as memory write cycles, causing corruption
11751 * of register and memory space. Only certain ICH bridges
11752 * will drive special cycles with non-zero data during the
11753 * address phase which can fall within the 5703's address
11754 * range. This is not an ICH bug as the PCI spec allows
11755 * non-zero address during special cycles. However, only
11756 * these ICH bridges are known to drive non-zero addresses
11757 * during special cycles.
11758 *
11759 * Since special cycles do not cross PCI bridges, we only
11760 * enable this workaround if the 5703 is on the secondary
11761 * bus of these ICH bridges.
11762 */
11763 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11764 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11765 static struct tg3_dev_id {
11766 u32 vendor;
11767 u32 device;
11768 u32 rev;
11769 } ich_chipsets[] = {
11770 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11771 PCI_ANY_ID },
11772 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11773 PCI_ANY_ID },
11774 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11775 0xa },
11776 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11777 PCI_ANY_ID },
11778 { },
11779 };
11780 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11781 struct pci_dev *bridge = NULL;
11782
11783 while (pci_id->vendor != 0) {
11784 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11785 bridge);
11786 if (!bridge) {
11787 pci_id++;
11788 continue;
11789 }
11790 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11791 if (bridge->revision > pci_id->rev)
6892914f
MC		 11792 continue;
11793 }
11794 if (bridge->subordinate &&
11795 (bridge->subordinate->number ==
11796 tp->pdev->bus->number)) {
11797
11798 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11799 pci_dev_put(bridge);
11800 break;
11801 }
11802 }
11803 }
11804
41588ba1
MC		 11805 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11806 static struct tg3_dev_id {
11807 u32 vendor;
11808 u32 device;
11809 } bridge_chipsets[] = {
11810 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11811 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11812 { },
11813 };
11814 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11815 struct pci_dev *bridge = NULL;
11816
11817 while (pci_id->vendor != 0) {
11818 bridge = pci_get_device(pci_id->vendor,
11819 pci_id->device,
11820 bridge);
11821 if (!bridge) {
11822 pci_id++;
11823 continue;
11824 }
11825 if (bridge->subordinate &&
11826 (bridge->subordinate->number <=
11827 tp->pdev->bus->number) &&
11828 (bridge->subordinate->subordinate >=
11829 tp->pdev->bus->number)) {
11830 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11831 pci_dev_put(bridge);
11832 break;
11833 }
11834 }
11835 }
11836
4a29cc2e
MC		 11837 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11838 * DMA addresses > 40-bit. This bridge may have other additional
11839 * 57xx devices behind it in some 4-port NIC designs for example.
11840 * Any tg3 device found behind the bridge will also need the 40-bit
11841 * DMA workaround.
11842 */
a4e2b347
MC		 11843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11845 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11846 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11847 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11848 }
4a29cc2e
MC		 11849 else {
11850 struct pci_dev *bridge = NULL;
11851
11852 do {
11853 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11854 PCI_DEVICE_ID_SERVERWORKS_EPB,
11855 bridge);
11856 if (bridge && bridge->subordinate &&
11857 (bridge->subordinate->number <=
11858 tp->pdev->bus->number) &&
11859 (bridge->subordinate->subordinate >=
11860 tp->pdev->bus->number)) {
11861 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11862 pci_dev_put(bridge);
11863 break;
11864 }
11865 } while (bridge);
11866 }
4cf78e4f 11867
1da177e4
LT		 11868 /* Initialize misc host control in PCI block. */
11869 tp->misc_host_ctrl |= (misc_ctrl_reg &
11870 MISC_HOST_CTRL_CHIPREV);
11871 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11872 tp->misc_host_ctrl);
11873
7544b097
MC		 11874 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11875 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11876 tp->pdev_peer = tg3_find_peer(tp);
11877
321d32a0
MC		 11878 /* Intentionally exclude ASIC_REV_5906 */
11879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11880 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11885 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11886
11887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11890 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11891 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11892 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11893
1b440c56
JL		 11894 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11895 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11896 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11897
027455ad
MC		 11898 /* 5700 B0 chips do not support checksumming correctly due
11899 * to hardware bugs.
11900 */
11901 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11902 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11903 else {
11904 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11905 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11906 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11907 tp->dev->features |= NETIF_F_IPV6_CSUM;
11908 }
11909
5a6f3074 11910 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11911 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11912 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11913 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11914 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11915 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11916 tp->pdev_peer == tp->pdev))
11917 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11918
321d32a0 11919 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 11920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11921 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11922 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11923 } else {
7f62ad5d 11924 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11925 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11926 ASIC_REV_5750 &&
11927 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11928 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11929 }
5a6f3074 11930 }
1da177e4 11931
f51f3562
MC		 11932 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11933 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 11934 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11935
52f4490c
MC		 11936 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11937 &pci_state_reg);
11938
5e7dfd0f
MC		 11939 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11940 if (tp->pcie_cap != 0) {
11941 u16 lnkctl;
11942
1da177e4 11943 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11944
11945 pcie_set_readrq(tp->pdev, 4096);
11946
5e7dfd0f
MC		 11947 pci_read_config_word(tp->pdev,
11948 tp->pcie_cap + PCI_EXP_LNKCTL,
11949 &lnkctl);
11950 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 11952 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 11953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 11954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
5e7dfd0f 11956 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 11957 }
52f4490c 11958 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 11959 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 11960 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11961 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11962 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11963 if (!tp->pcix_cap) {
11964 printk(KERN_ERR PFX "Cannot find PCI-X "
11965 "capability, aborting.\n");
11966 return -EIO;
11967 }
11968
11969 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11970 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11971 }
1da177e4 11972
399de50b
MC		 11973 /* If we have an AMD 762 or VIA K8T800 chipset, write
11974 * reordering to the mailbox registers done by the host
11975 * controller can cause major troubles. We read back from
11976 * every mailbox register write to force the writes to be
11977 * posted to the chip in order.
11978 */
11979 if (pci_dev_present(write_reorder_chipsets) &&
11980 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11981 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11982
69fc4053
MC		 11983 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11984 &tp->pci_cacheline_sz);
11985 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11986 &tp->pci_lat_timer);
1da177e4
LT		 11987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11988 tp->pci_lat_timer < 64) {
11989 tp->pci_lat_timer = 64;
69fc4053
MC		 11990 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11991 tp->pci_lat_timer);
1da177e4
LT		 11992 }
11993
52f4490c
MC		 11994 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11995 /* 5700 BX chips need to have their TX producer index
11996 * mailboxes written twice to workaround a bug.
11997 */
11998 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 11999
52f4490c 12000 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12001 *
12002 * The workaround is to use indirect register accesses
12003 * for all chip writes not to mailbox registers.
12004 */
52f4490c 12005 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12006 u32 pm_reg;
1da177e4
LT		 12007
12008 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12009
12010 /* The chip can have it's power management PCI config
12011 * space registers clobbered due to this bug.
12012 * So explicitly force the chip into D0 here.
12013 */
9974a356
MC		 12014 pci_read_config_dword(tp->pdev,
12015 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12016 &pm_reg);
12017 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12018 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12019 pci_write_config_dword(tp->pdev,
12020 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12021 pm_reg);
12022
12023 /* Also, force SERR#/PERR# in PCI command. */
12024 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12025 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12026 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12027 }
12028 }
12029
1da177e4
LT		 12030 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12031 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12032 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12033 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12034
12035 /* Chip-specific fixup from Broadcom driver */
12036 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12037 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12038 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12039 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12040 }
12041
1ee582d8 12042 /* Default fast path register access methods */
20094930 12043 tp->read32 = tg3_read32;
1ee582d8 12044 tp->write32 = tg3_write32;
09ee929c 12045 tp->read32_mbox = tg3_read32;
20094930 12046 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12047 tp->write32_tx_mbox = tg3_write32;
12048 tp->write32_rx_mbox = tg3_write32;
12049
12050 /* Various workaround register access methods */
12051 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12052 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12053 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12054 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12055 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12056 /*
12057 * Back to back register writes can cause problems on these
12058 * chips, the workaround is to read back all reg writes
12059 * except those to mailbox regs.
12060 *
12061 * See tg3_write_indirect_reg32().
12062 */
1ee582d8 12063 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12064 }
12065
1ee582d8
MC		 12066
12067 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12068 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12069 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12070 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12071 tp->write32_rx_mbox = tg3_write_flush_reg32;
12072 }
20094930 12073
6892914f
MC		 12074 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12075 tp->read32 = tg3_read_indirect_reg32;
12076 tp->write32 = tg3_write_indirect_reg32;
12077 tp->read32_mbox = tg3_read_indirect_mbox;
12078 tp->write32_mbox = tg3_write_indirect_mbox;
12079 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12080 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12081
12082 iounmap(tp->regs);
22abe310 12083 tp->regs = NULL;
6892914f
MC		 12084
12085 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12086 pci_cmd &= ~PCI_COMMAND_MEMORY;
12087 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12088 }
b5d3772c
MC		 12089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12090 tp->read32_mbox = tg3_read32_mbox_5906;
12091 tp->write32_mbox = tg3_write32_mbox_5906;
12092 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12093 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12094 }
6892914f 12095
bbadf503
MC		 12096 if (tp->write32 == tg3_write_indirect_reg32 ||
12097 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12098 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12100 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12101
7d0c41ef 12102 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12103 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12104 * determined before calling tg3_set_power_state() so that
12105 * we know whether or not to switch out of Vaux power.
12106 * When the flag is set, it means that GPIO1 is used for eeprom
12107 * write protect and also implies that it is a LOM where GPIOs
12108 * are not used to switch power.
6aa20a22 12109 */
7d0c41ef
MC		 12110 tg3_get_eeprom_hw_cfg(tp);
12111
0d3031d9
MC		 12112 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12113 /* Allow reads and writes to the
12114 * APE register and memory space.
12115 */
12116 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12117 PCISTATE_ALLOW_APE_SHMEM_WR;
12118 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12119 pci_state_reg);
12120 }
12121
9936bcf6 12122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12126 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12127
314fba34
MC		 12128 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12129 * GPIO1 driven high will bring 5700's external PHY out of reset.
12130 * It is also used as eeprom write protect on LOMs.
12131 */
12132 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12133 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12134 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12135 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12136 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12137 /* Unused GPIO3 must be driven as output on 5752 because there
12138 * are no pull-up resistors on unused GPIO pins.
12139 */
12140 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12141 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12142
321d32a0
MC		 12143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12145 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12146
5f0c4a3c
MC		 12147 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12148 /* Turn off the debug UART. */
12149 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12150 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12151 /* Keep VMain power. */
12152 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12153 GRC_LCLCTRL_GPIO_OUTPUT0;
12154 }
12155
1da177e4 12156 /* Force the chip into D0. */
bc1c7567 12157 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12158 if (err) {
12159 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12160 pci_name(tp->pdev));
12161 return err;
12162 }
12163
1da177e4
LT		 12164 /* Derive initial jumbo mode from MTU assigned in
12165 * ether_setup() via the alloc_etherdev() call
12166 */
0f893dc6 12167 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12168 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12169 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12170
12171 /* Determine WakeOnLan speed to use. */
12172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12173 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12174 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12175 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12176 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12177 } else {
12178 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12179 }
12180
12181 /* A few boards don't want Ethernet@WireSpeed phy feature */
12182 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12183 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12184 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12185 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12186 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12187 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12188 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12189
12190 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12191 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12192 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12193 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12194 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12195
321d32a0
MC		 12196 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12197 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12198 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12199 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12204 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12205 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12206 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12207 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12208 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12209 } else
c424cb24
MC		 12210 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12211 }
1da177e4 12212
b2a5c19c
MC		 12213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12214 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12215 tp->phy_otp = tg3_read_otp_phycfg(tp);
12216 if (tp->phy_otp == 0)
12217 tp->phy_otp = TG3_OTP_DEFAULT;
12218 }
12219
f51f3562 12220 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12221 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12222 else
12223 tp->mi_mode = MAC_MI_MODE_BASE;
12224
1da177e4 12225 tp->coalesce_mode = 0;
1da177e4
LT		 12226 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12227 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12228 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12229
321d32a0
MC		 12230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12232 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12233
158d7abd
MC		 12234 err = tg3_mdio_init(tp);
12235 if (err)
12236 return err;
1da177e4
LT		 12237
12238 /* Initialize data/descriptor byte/word swapping. */
12239 val = tr32(GRC_MODE);
12240 val &= GRC_MODE_HOST_STACKUP;
12241 tw32(GRC_MODE, val | tp->grc_mode);
12242
12243 tg3_switch_clocks(tp);
12244
12245 /* Clear this out for sanity. */
12246 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12247
12248 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12249 &pci_state_reg);
12250 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12251 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12252 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12253
12254 if (chiprevid == CHIPREV_ID_5701_A0 ||
12255 chiprevid == CHIPREV_ID_5701_B0 ||
12256 chiprevid == CHIPREV_ID_5701_B2 ||
12257 chiprevid == CHIPREV_ID_5701_B5) {
12258 void __iomem *sram_base;
12259
12260 /* Write some dummy words into the SRAM status block
12261 * area, see if it reads back correctly. If the return
12262 * value is bad, force enable the PCIX workaround.
12263 */
12264 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12265
12266 writel(0x00000000, sram_base);
12267 writel(0x00000000, sram_base + 4);
12268 writel(0xffffffff, sram_base + 4);
12269 if (readl(sram_base) != 0x00000000)
12270 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12271 }
12272 }
12273
12274 udelay(50);
12275 tg3_nvram_init(tp);
12276
12277 grc_misc_cfg = tr32(GRC_MISC_CFG);
12278 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12279
1da177e4
LT		 12280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12281 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12282 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12283 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12284
fac9b83e
DM		 12285 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12286 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12287 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12288 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12289 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12290 HOSTCC_MODE_CLRTICK_TXBD);
12291
12292 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12293 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12294 tp->misc_host_ctrl);
12295 }
12296
3bda1258
MC		 12297 /* Preserve the APE MAC_MODE bits */
12298 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12299 tp->mac_mode = tr32(MAC_MODE) |
12300 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12301 else
12302 tp->mac_mode = TG3_DEF_MAC_MODE;
12303
1da177e4
LT		 12304 /* these are limited to 10/100 only */
12305 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12306 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12307 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12308 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12309 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12310 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12311 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12312 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12313 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12314 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12315 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12316 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12318 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12319
12320 err = tg3_phy_probe(tp);
12321 if (err) {
12322 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12323 pci_name(tp->pdev), err);
12324 /* ... but do not return immediately ... */
b02fd9e3 12325 tg3_mdio_fini(tp);
1da177e4
LT		 12326 }
12327
12328 tg3_read_partno(tp);
c4e6575c 12329 tg3_read_fw_ver(tp);
1da177e4
LT		 12330
12331 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12332 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12333 } else {
12334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12335 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12336 else
12337 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12338 }
12339
12340 /* 5700 {AX,BX} chips have a broken status block link
12341 * change bit implementation, so we must use the
12342 * status register in those cases.
12343 */
12344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12345 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12346 else
12347 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12348
12349 /* The led_ctrl is set during tg3_phy_probe, here we might
12350 * have to force the link status polling mechanism based
12351 * upon subsystem IDs.
12352 */
12353 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12355 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12356 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12357 TG3_FLAG_USE_LINKCHG_REG);
12358 }
12359
12360 /* For all SERDES we poll the MAC status register. */
12361 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12362 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12363 else
12364 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12365
ad829268 12366 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12368 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12369 tp->rx_offset = 0;
12370
f92905de
MC		 12371 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12372
12373 /* Increment the rx prod index on the rx std ring by at most
12374 * 8 for these chips to workaround hw errata.
12375 */
12376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12379 tp->rx_std_max_post = 8;
12380
8ed5d97e
MC		 12381 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12382 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12383 PCIE_PWR_MGMT_L1_THRESH_MSK;
12384
1da177e4
LT		 12385 return err;
12386}
12387
49b6e95f 12388#ifdef CONFIG_SPARC
1da177e4
LT		 12389static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12390{
12391 struct net_device *dev = tp->dev;
12392 struct pci_dev *pdev = tp->pdev;
49b6e95f 12393 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12394 const unsigned char *addr;
49b6e95f
DM		 12395 int len;
12396
12397 addr = of_get_property(dp, "local-mac-address", &len);
12398 if (addr && len == 6) {
12399 memcpy(dev->dev_addr, addr, 6);
12400 memcpy(dev->perm_addr, dev->dev_addr, 6);
12401 return 0;
1da177e4
LT		 12402 }
12403 return -ENODEV;
12404}
12405
12406static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12407{
12408 struct net_device *dev = tp->dev;
12409
12410 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12411 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12412 return 0;
12413}
12414#endif
12415
12416static int __devinit tg3_get_device_address(struct tg3 *tp)
12417{
12418 struct net_device *dev = tp->dev;
12419 u32 hi, lo, mac_offset;
008652b3 12420 int addr_ok = 0;
1da177e4 12421
49b6e95f 12422#ifdef CONFIG_SPARC
1da177e4
LT		 12423 if (!tg3_get_macaddr_sparc(tp))
12424 return 0;
12425#endif
12426
12427 mac_offset = 0x7c;
f49639e6 12428 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12429 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12430 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12431 mac_offset = 0xcc;
12432 if (tg3_nvram_lock(tp))
12433 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12434 else
12435 tg3_nvram_unlock(tp);
12436 }
b5d3772c
MC		 12437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12438 mac_offset = 0x10;
1da177e4
LT		 12439
12440 /* First try to get it from MAC address mailbox. */
12441 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12442 if ((hi >> 16) == 0x484b) {
12443 dev->dev_addr[0] = (hi >> 8) & 0xff;
12444 dev->dev_addr[1] = (hi >> 0) & 0xff;
12445
12446 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12447 dev->dev_addr[2] = (lo >> 24) & 0xff;
12448 dev->dev_addr[3] = (lo >> 16) & 0xff;
12449 dev->dev_addr[4] = (lo >> 8) & 0xff;
12450 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12451
008652b3
MC		 12452 /* Some old bootcode may report a 0 MAC address in SRAM */
12453 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12454 }
12455 if (!addr_ok) {
12456 /* Next, try NVRAM. */
6d348f2c
MC		 12457 if (!tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12458 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12459 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12460 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12461 }
12462 /* Finally just fetch it out of the MAC control regs. */
12463 else {
12464 hi = tr32(MAC_ADDR_0_HIGH);
12465 lo = tr32(MAC_ADDR_0_LOW);
12466
12467 dev->dev_addr[5] = lo & 0xff;
12468 dev->dev_addr[4] = (lo >> 8) & 0xff;
12469 dev->dev_addr[3] = (lo >> 16) & 0xff;
12470 dev->dev_addr[2] = (lo >> 24) & 0xff;
12471 dev->dev_addr[1] = hi & 0xff;
12472 dev->dev_addr[0] = (hi >> 8) & 0xff;
12473 }
1da177e4
LT		 12474 }
12475
12476 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12477#ifdef CONFIG_SPARC
1da177e4
LT		 12478 if (!tg3_get_default_macaddr_sparc(tp))
12479 return 0;
12480#endif
12481 return -EINVAL;
12482 }
2ff43697 12483 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12484 return 0;
12485}
12486
59e6b434
DM		 12487#define BOUNDARY_SINGLE_CACHELINE 1
12488#define BOUNDARY_MULTI_CACHELINE 2
12489
12490static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12491{
12492 int cacheline_size;
12493 u8 byte;
12494 int goal;
12495
12496 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12497 if (byte == 0)
12498 cacheline_size = 1024;
12499 else
12500 cacheline_size = (int) byte * 4;
12501
12502 /* On 5703 and later chips, the boundary bits have no
12503 * effect.
12504 */
12505 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12506 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12507 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12508 goto out;
12509
12510#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12511 goal = BOUNDARY_MULTI_CACHELINE;
12512#else
12513#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12514 goal = BOUNDARY_SINGLE_CACHELINE;
12515#else
12516 goal = 0;
12517#endif
12518#endif
12519
12520 if (!goal)
12521 goto out;
12522
12523 /* PCI controllers on most RISC systems tend to disconnect
12524 * when a device tries to burst across a cache-line boundary.
12525 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12526 *
12527 * Unfortunately, for PCI-E there are only limited
12528 * write-side controls for this, and thus for reads
12529 * we will still get the disconnects. We'll also waste
12530 * these PCI cycles for both read and write for chips
12531 * other than 5700 and 5701 which do not implement the
12532 * boundary bits.
12533 */
12534 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12535 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12536 switch (cacheline_size) {
12537 case 16:
12538 case 32:
12539 case 64:
12540 case 128:
12541 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12542 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12543 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12544 } else {
12545 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12546 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12547 }
12548 break;
12549
12550 case 256:
12551 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12552 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12553 break;
12554
12555 default:
12556 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12557 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12558 break;
855e1111 12559 }
59e6b434
DM		 12560 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12561 switch (cacheline_size) {
12562 case 16:
12563 case 32:
12564 case 64:
12565 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12566 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12567 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12568 break;
12569 }
12570 /* fallthrough */
12571 case 128:
12572 default:
12573 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12574 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12575 break;
855e1111 12576 }
59e6b434
DM		 12577 } else {
12578 switch (cacheline_size) {
12579 case 16:
12580 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12581 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12582 DMA_RWCTRL_WRITE_BNDRY_16);
12583 break;
12584 }
12585 /* fallthrough */
12586 case 32:
12587 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12588 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12589 DMA_RWCTRL_WRITE_BNDRY_32);
12590 break;
12591 }
12592 /* fallthrough */
12593 case 64:
12594 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12595 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12596 DMA_RWCTRL_WRITE_BNDRY_64);
12597 break;
12598 }
12599 /* fallthrough */
12600 case 128:
12601 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12602 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12603 DMA_RWCTRL_WRITE_BNDRY_128);
12604 break;
12605 }
12606 /* fallthrough */
12607 case 256:
12608 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12609 DMA_RWCTRL_WRITE_BNDRY_256);
12610 break;
12611 case 512:
12612 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12613 DMA_RWCTRL_WRITE_BNDRY_512);
12614 break;
12615 case 1024:
12616 default:
12617 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12618 DMA_RWCTRL_WRITE_BNDRY_1024);
12619 break;
855e1111 12620 }
59e6b434
DM		 12621 }
12622
12623out:
12624 return val;
12625}
12626
1da177e4
LT		 12627static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12628{
12629 struct tg3_internal_buffer_desc test_desc;
12630 u32 sram_dma_descs;
12631 int i, ret;
12632
12633 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12634
12635 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12636 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12637 tw32(RDMAC_STATUS, 0);
12638 tw32(WDMAC_STATUS, 0);
12639
12640 tw32(BUFMGR_MODE, 0);
12641 tw32(FTQ_RESET, 0);
12642
12643 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12644 test_desc.addr_lo = buf_dma & 0xffffffff;
12645 test_desc.nic_mbuf = 0x00002100;
12646 test_desc.len = size;
12647
12648 /*
12649 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12650 * the *second* time the tg3 driver was getting loaded after an
12651 * initial scan.
12652 *
12653 * Broadcom tells me:
12654 * ...the DMA engine is connected to the GRC block and a DMA
12655 * reset may affect the GRC block in some unpredictable way...
12656 * The behavior of resets to individual blocks has not been tested.
12657 *
12658 * Broadcom noted the GRC reset will also reset all sub-components.
12659 */
12660 if (to_device) {
12661 test_desc.cqid_sqid = (13 << 8) | 2;
12662
12663 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12664 udelay(40);
12665 } else {
12666 test_desc.cqid_sqid = (16 << 8) | 7;
12667
12668 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12669 udelay(40);
12670 }
12671 test_desc.flags = 0x00000005;
12672
12673 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12674 u32 val;
12675
12676 val = *(((u32 *)&test_desc) + i);
12677 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12678 sram_dma_descs + (i * sizeof(u32)));
12679 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12680 }
12681 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12682
12683 if (to_device) {
12684 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12685 } else {
12686 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12687 }
12688
12689 ret = -ENODEV;
12690 for (i = 0; i < 40; i++) {
12691 u32 val;
12692
12693 if (to_device)
12694 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12695 else
12696 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12697 if ((val & 0xffff) == sram_dma_descs) {
12698 ret = 0;
12699 break;
12700 }
12701
12702 udelay(100);
12703 }
12704
12705 return ret;
12706}
12707
ded7340d 12708#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12709
12710static int __devinit tg3_test_dma(struct tg3 *tp)
12711{
12712 dma_addr_t buf_dma;
59e6b434 12713 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12714 int ret;
12715
12716 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12717 if (!buf) {
12718 ret = -ENOMEM;
12719 goto out_nofree;
12720 }
12721
12722 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12723 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12724
59e6b434 12725 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12726
12727 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12728 /* DMA read watermark not used on PCIE */
12729 tp->dma_rwctrl |= 0x00180000;
12730 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12732 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12733 tp->dma_rwctrl |= 0x003f0000;
12734 else
12735 tp->dma_rwctrl |= 0x003f000f;
12736 } else {
12737 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12738 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12739 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12740 u32 read_water = 0x7;
1da177e4 12741
4a29cc2e
MC		 12742 /* If the 5704 is behind the EPB bridge, we can
12743 * do the less restrictive ONE_DMA workaround for
12744 * better performance.
12745 */
12746 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12747 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12748 tp->dma_rwctrl |= 0x8000;
12749 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12750 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12751
49afdeb6
MC		 12752 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12753 read_water = 4;
59e6b434 12754 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12755 tp->dma_rwctrl |=
12756 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12757 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12758 (1 << 23);
4cf78e4f
MC		 12759 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12760 /* 5780 always in PCIX mode */
12761 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12762 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12763 /* 5714 always in PCIX mode */
12764 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12765 } else {
12766 tp->dma_rwctrl |= 0x001b000f;
12767 }
12768 }
12769
12770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12772 tp->dma_rwctrl &= 0xfffffff0;
12773
12774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12776 /* Remove this if it causes problems for some boards. */
12777 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12778
12779 /* On 5700/5701 chips, we need to set this bit.
12780 * Otherwise the chip will issue cacheline transactions
12781 * to streamable DMA memory with not all the byte
12782 * enables turned on. This is an error on several
12783 * RISC PCI controllers, in particular sparc64.
12784 *
12785 * On 5703/5704 chips, this bit has been reassigned
12786 * a different meaning. In particular, it is used
12787 * on those chips to enable a PCI-X workaround.
12788 */
12789 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12790 }
12791
12792 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12793
12794#if 0
12795 /* Unneeded, already done by tg3_get_invariants. */
12796 tg3_switch_clocks(tp);
12797#endif
12798
12799 ret = 0;
12800 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12801 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12802 goto out;
12803
59e6b434
DM		 12804 /* It is best to perform DMA test with maximum write burst size
12805 * to expose the 5700/5701 write DMA bug.
12806 */
12807 saved_dma_rwctrl = tp->dma_rwctrl;
12808 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12809 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12810
1da177e4
LT		 12811 while (1) {
12812 u32 *p = buf, i;
12813
12814 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12815 p[i] = i;
12816
12817 /* Send the buffer to the chip. */
12818 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12819 if (ret) {
12820 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12821 break;
12822 }
12823
12824#if 0
12825 /* validate data reached card RAM correctly. */
12826 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12827 u32 val;
12828 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12829 if (le32_to_cpu(val) != p[i]) {
12830 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12831 /* ret = -ENODEV here? */
12832 }
12833 p[i] = 0;
12834 }
12835#endif
12836 /* Now read it back. */
12837 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12838 if (ret) {
12839 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12840
12841 break;
12842 }
12843
12844 /* Verify it. */
12845 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12846 if (p[i] == i)
12847 continue;
12848
59e6b434
DM		 12849 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12850 DMA_RWCTRL_WRITE_BNDRY_16) {
12851 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12852 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12853 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12854 break;
12855 } else {
12856 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12857 ret = -ENODEV;
12858 goto out;
12859 }
12860 }
12861
12862 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12863 /* Success. */
12864 ret = 0;
12865 break;
12866 }
12867 }
59e6b434
DM		 12868 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12869 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12870 static struct pci_device_id dma_wait_state_chipsets[] = {
12871 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12872 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12873 { },
12874 };
12875
59e6b434 12876 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12877 * now look for chipsets that are known to expose the
12878 * DMA bug without failing the test.
59e6b434 12879 */
6d1cfbab
MC		 12880 if (pci_dev_present(dma_wait_state_chipsets)) {
12881 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12882 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12883 }
12884 else
12885 /* Safe to use the calculated DMA boundary. */
12886 tp->dma_rwctrl = saved_dma_rwctrl;
12887
59e6b434
DM		 12888 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12889 }
1da177e4
LT		 12890
12891out:
12892 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12893out_nofree:
12894 return ret;
12895}
12896
12897static void __devinit tg3_init_link_config(struct tg3 *tp)
12898{
12899 tp->link_config.advertising =
12900 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12901 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12902 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12903 ADVERTISED_Autoneg | ADVERTISED_MII);
12904 tp->link_config.speed = SPEED_INVALID;
12905 tp->link_config.duplex = DUPLEX_INVALID;
12906 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12907 tp->link_config.active_speed = SPEED_INVALID;
12908 tp->link_config.active_duplex = DUPLEX_INVALID;
12909 tp->link_config.phy_is_low_power = 0;
12910 tp->link_config.orig_speed = SPEED_INVALID;
12911 tp->link_config.orig_duplex = DUPLEX_INVALID;
12912 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12913}
12914
12915static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12916{
fdfec172
MC		 12917 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12918 tp->bufmgr_config.mbuf_read_dma_low_water =
12919 DEFAULT_MB_RDMA_LOW_WATER_5705;
12920 tp->bufmgr_config.mbuf_mac_rx_low_water =
12921 DEFAULT_MB_MACRX_LOW_WATER_5705;
12922 tp->bufmgr_config.mbuf_high_water =
12923 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12925 tp->bufmgr_config.mbuf_mac_rx_low_water =
12926 DEFAULT_MB_MACRX_LOW_WATER_5906;
12927 tp->bufmgr_config.mbuf_high_water =
12928 DEFAULT_MB_HIGH_WATER_5906;
12929 }
fdfec172
MC		 12930
12931 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12932 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12933 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12934 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12935 tp->bufmgr_config.mbuf_high_water_jumbo =
12936 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12937 } else {
12938 tp->bufmgr_config.mbuf_read_dma_low_water =
12939 DEFAULT_MB_RDMA_LOW_WATER;
12940 tp->bufmgr_config.mbuf_mac_rx_low_water =
12941 DEFAULT_MB_MACRX_LOW_WATER;
12942 tp->bufmgr_config.mbuf_high_water =
12943 DEFAULT_MB_HIGH_WATER;
12944
12945 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12946 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12947 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12948 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12949 tp->bufmgr_config.mbuf_high_water_jumbo =
12950 DEFAULT_MB_HIGH_WATER_JUMBO;
12951 }
1da177e4
LT		 12952
12953 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12954 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12955}
12956
12957static char * __devinit tg3_phy_string(struct tg3 *tp)
12958{
12959 switch (tp->phy_id & PHY_ID_MASK) {
12960 case PHY_ID_BCM5400: return "5400";
12961 case PHY_ID_BCM5401: return "5401";
12962 case PHY_ID_BCM5411: return "5411";
12963 case PHY_ID_BCM5701: return "5701";
12964 case PHY_ID_BCM5703: return "5703";
12965 case PHY_ID_BCM5704: return "5704";
12966 case PHY_ID_BCM5705: return "5705";
12967 case PHY_ID_BCM5750: return "5750";
85e94ced 12968 case PHY_ID_BCM5752: return "5752";
a4e2b347 12969 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12970 case PHY_ID_BCM5780: return "5780";
af36e6b6 12971 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12972 case PHY_ID_BCM5787: return "5787";
d30cdd28 12973 case PHY_ID_BCM5784: return "5784";
126a3368 12974 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12975 case PHY_ID_BCM5906: return "5906";
9936bcf6 12976 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12977 case PHY_ID_BCM8002: return "8002/serdes";
12978 case 0: return "serdes";
12979 default: return "unknown";
855e1111 12980 }
1da177e4
LT		 12981}
12982
f9804ddb
MC		 12983static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12984{
12985 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12986 strcpy(str, "PCI Express");
12987 return str;
12988 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12989 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12990
12991 strcpy(str, "PCIX:");
12992
12993 if ((clock_ctrl == 7) ||
12994 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12995 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12996 strcat(str, "133MHz");
12997 else if (clock_ctrl == 0)
12998 strcat(str, "33MHz");
12999 else if (clock_ctrl == 2)
13000 strcat(str, "50MHz");
13001 else if (clock_ctrl == 4)
13002 strcat(str, "66MHz");
13003 else if (clock_ctrl == 6)
13004 strcat(str, "100MHz");
f9804ddb
MC		 13005 } else {
13006 strcpy(str, "PCI:");
13007 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13008 strcat(str, "66MHz");
13009 else
13010 strcat(str, "33MHz");
13011 }
13012 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13013 strcat(str, ":32-bit");
13014 else
13015 strcat(str, ":64-bit");
13016 return str;
13017}
13018
8c2dc7e1 13019static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13020{
13021 struct pci_dev *peer;
13022 unsigned int func, devnr = tp->pdev->devfn & ~7;
13023
13024 for (func = 0; func < 8; func++) {
13025 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13026 if (peer && peer != tp->pdev)
13027 break;
13028 pci_dev_put(peer);
13029 }
16fe9d74
MC		 13030 /* 5704 can be configured in single-port mode, set peer to
13031 * tp->pdev in that case.
13032 */
13033 if (!peer) {
13034 peer = tp->pdev;
13035 return peer;
13036 }
1da177e4
LT		 13037
13038 /*
13039 * We don't need to keep the refcount elevated; there's no way
13040 * to remove one half of this device without removing the other
13041 */
13042 pci_dev_put(peer);
13043
13044 return peer;
13045}
13046
15f9850d
DM		 13047static void __devinit tg3_init_coal(struct tg3 *tp)
13048{
13049 struct ethtool_coalesce *ec = &tp->coal;
13050
13051 memset(ec, 0, sizeof(*ec));
13052 ec->cmd = ETHTOOL_GCOALESCE;
13053 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13054 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13055 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13056 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13057 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13058 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13059 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13060 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13061 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13062
13063 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13064 HOSTCC_MODE_CLRTICK_TXBD)) {
13065 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13066 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13067 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13068 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13069 }
d244c892
MC		 13070
13071 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13072 ec->rx_coalesce_usecs_irq = 0;
13073 ec->tx_coalesce_usecs_irq = 0;
13074 ec->stats_block_coalesce_usecs = 0;
13075 }
15f9850d
DM		 13076}
13077
7c7d64b8
SH		 13078static const struct net_device_ops tg3_netdev_ops = {
13079 .ndo_open = tg3_open,
13080 .ndo_stop = tg3_close,
00829823
SH		 13081 .ndo_start_xmit = tg3_start_xmit,
13082 .ndo_get_stats = tg3_get_stats,
13083 .ndo_validate_addr = eth_validate_addr,
13084 .ndo_set_multicast_list = tg3_set_rx_mode,
13085 .ndo_set_mac_address = tg3_set_mac_addr,
13086 .ndo_do_ioctl = tg3_ioctl,
13087 .ndo_tx_timeout = tg3_tx_timeout,
13088 .ndo_change_mtu = tg3_change_mtu,
13089#if TG3_VLAN_TAG_USED
13090 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13091#endif
13092#ifdef CONFIG_NET_POLL_CONTROLLER
13093 .ndo_poll_controller = tg3_poll_controller,
13094#endif
13095};
13096
13097static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13098 .ndo_open = tg3_open,
13099 .ndo_stop = tg3_close,
13100 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13101 .ndo_get_stats = tg3_get_stats,
13102 .ndo_validate_addr = eth_validate_addr,
13103 .ndo_set_multicast_list = tg3_set_rx_mode,
13104 .ndo_set_mac_address = tg3_set_mac_addr,
13105 .ndo_do_ioctl = tg3_ioctl,
13106 .ndo_tx_timeout = tg3_tx_timeout,
13107 .ndo_change_mtu = tg3_change_mtu,
13108#if TG3_VLAN_TAG_USED
13109 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13110#endif
13111#ifdef CONFIG_NET_POLL_CONTROLLER
13112 .ndo_poll_controller = tg3_poll_controller,
13113#endif
13114};
13115
1da177e4
LT		 13116static int __devinit tg3_init_one(struct pci_dev *pdev,
13117 const struct pci_device_id *ent)
13118{
13119 static int tg3_version_printed = 0;
1da177e4
LT		 13120 struct net_device *dev;
13121 struct tg3 *tp;
d6645372 13122 int err, pm_cap;
f9804ddb 13123 char str[40];
72f2afb8 13124 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13125
13126 if (tg3_version_printed++ == 0)
13127 printk(KERN_INFO "%s", version);
13128
13129 err = pci_enable_device(pdev);
13130 if (err) {
13131 printk(KERN_ERR PFX "Cannot enable PCI device, "
13132 "aborting.\n");
13133 return err;
13134 }
13135
1da177e4
LT		 13136 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13137 if (err) {
13138 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13139 "aborting.\n");
13140 goto err_out_disable_pdev;
13141 }
13142
13143 pci_set_master(pdev);
13144
13145 /* Find power-management capability. */
13146 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13147 if (pm_cap == 0) {
13148 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13149 "aborting.\n");
13150 err = -EIO;
13151 goto err_out_free_res;
13152 }
13153
1da177e4
LT		 13154 dev = alloc_etherdev(sizeof(*tp));
13155 if (!dev) {
13156 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13157 err = -ENOMEM;
13158 goto err_out_free_res;
13159 }
13160
1da177e4
LT		 13161 SET_NETDEV_DEV(dev, &pdev->dev);
13162
1da177e4
LT		 13163#if TG3_VLAN_TAG_USED
13164 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13165#endif
13166
13167 tp = netdev_priv(dev);
13168 tp->pdev = pdev;
13169 tp->dev = dev;
13170 tp->pm_cap = pm_cap;
1da177e4
LT		 13171 tp->rx_mode = TG3_DEF_RX_MODE;
13172 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13173
1da177e4
LT		 13174 if (tg3_debug > 0)
13175 tp->msg_enable = tg3_debug;
13176 else
13177 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13178
13179 /* The word/byte swap controls here control register access byte
13180 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13181 * setting below.
13182 */
13183 tp->misc_host_ctrl =
13184 MISC_HOST_CTRL_MASK_PCI_INT |
13185 MISC_HOST_CTRL_WORD_SWAP |
13186 MISC_HOST_CTRL_INDIR_ACCESS |
13187 MISC_HOST_CTRL_PCISTATE_RW;
13188
13189 /* The NONFRM (non-frame) byte/word swap controls take effect
13190 * on descriptor entries, anything which isn't packet data.
13191 *
13192 * The StrongARM chips on the board (one for tx, one for rx)
13193 * are running in big-endian mode.
13194 */
13195 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13196 GRC_MODE_WSWAP_NONFRM_DATA);
13197#ifdef __BIG_ENDIAN
13198 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13199#endif
13200 spin_lock_init(&tp->lock);
1da177e4 13201 spin_lock_init(&tp->indirect_lock);
c4028958 13202 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13203
d5fe488a 13204 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13205 if (!tp->regs) {
1da177e4
LT		 13206 printk(KERN_ERR PFX "Cannot map device registers, "
13207 "aborting.\n");
13208 err = -ENOMEM;
13209 goto err_out_free_dev;
13210 }
13211
13212 tg3_init_link_config(tp);
13213
1da177e4
LT		 13214 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13215 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13216 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13217
bea3348e 13218 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13219 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13220 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13221 dev->irq = pdev->irq;
1da177e4
LT		 13222
13223 err = tg3_get_invariants(tp);
13224 if (err) {
13225 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13226 "aborting.\n");
13227 goto err_out_iounmap;
13228 }
13229
321d32a0 13230 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13232 dev->netdev_ops = &tg3_netdev_ops;
13233 else
13234 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13235
13236
4a29cc2e
MC		 13237 /* The EPB bridge inside 5714, 5715, and 5780 and any
13238 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13239 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13240 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13241 * do DMA address check in tg3_start_xmit().
13242 */
4a29cc2e 13243 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13244 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13245 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13246 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13247#ifdef CONFIG_HIGHMEM
6a35528a 13248 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13249#endif
4a29cc2e 13250 } else
6a35528a 13251 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13252
13253 /* Configure DMA attributes. */
284901a9 13254 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13255 err = pci_set_dma_mask(pdev, dma_mask);
13256 if (!err) {
13257 dev->features |= NETIF_F_HIGHDMA;
13258 err = pci_set_consistent_dma_mask(pdev,
13259 persist_dma_mask);
13260 if (err < 0) {
13261 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13262 "DMA for consistent allocations\n");
13263 goto err_out_iounmap;
13264 }
13265 }
13266 }
284901a9
YH		 13267 if (err || dma_mask == DMA_BIT_MASK(32)) {
13268 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13269 if (err) {
13270 printk(KERN_ERR PFX "No usable DMA configuration, "
13271 "aborting.\n");
13272 goto err_out_iounmap;
13273 }
13274 }
13275
fdfec172 13276 tg3_init_bufmgr_config(tp);
1da177e4 13277
077f849d 13278 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13279 tp->fw_needed = FIRMWARE_TG3;
077f849d 13280
1da177e4
LT		 13281 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13282 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13283 }
13284 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13286 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13287 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13288 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13289 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13290 } else {
7f62ad5d 13291 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13293 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13294 else
9e9fd12d 13295 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13296 }
1da177e4 13297
4e3a7aaa
MC		 13298 /* TSO is on by default on chips that support hardware TSO.
13299 * Firmware TSO on older chips gives lower performance, so it
13300 * is off by default, but can be enabled using ethtool.
13301 */
b0026624 13302 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13303 if (dev->features & NETIF_F_IP_CSUM)
13304 dev->features |= NETIF_F_TSO;
13305 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13306 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13307 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13309 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13310 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13313 dev->features |= NETIF_F_TSO_ECN;
b0026624 13314 }
1da177e4 13315
1da177e4
LT		 13316
13317 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13318 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13319 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13320 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13321 tp->rx_pending = 63;
13322 }
13323
1da177e4
LT		 13324 err = tg3_get_device_address(tp);
13325 if (err) {
13326 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13327 "aborting.\n");
077f849d 13328 goto err_out_fw;
1da177e4
LT		 13329 }
13330
c88864df 13331 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13332 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13333 if (!tp->aperegs) {
c88864df
MC		 13334 printk(KERN_ERR PFX "Cannot map APE registers, "
13335 "aborting.\n");
13336 err = -ENOMEM;
077f849d 13337 goto err_out_fw;
c88864df
MC		 13338 }
13339
13340 tg3_ape_lock_init(tp);
7fd76445
MC		 13341
13342 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13343 tg3_read_dash_ver(tp);
c88864df
MC		 13344 }
13345
1da177e4
LT		 13346 /*
13347 * Reset chip in case UNDI or EFI driver did not shutdown
13348 * DMA self test will enable WDMAC and we'll see (spurious)
13349 * pending DMA on the PCI bus at that point.
13350 */
13351 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13352 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13353 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13354 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13355 }
13356
13357 err = tg3_test_dma(tp);
13358 if (err) {
13359 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13360 goto err_out_apeunmap;
1da177e4
LT		 13361 }
13362
1da177e4
LT		 13363 /* flow control autonegotiation is default behavior */
13364 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13365 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13366
15f9850d
DM		 13367 tg3_init_coal(tp);
13368
c49a1561
MC		 13369 pci_set_drvdata(pdev, dev);
13370
1da177e4
LT		 13371 err = register_netdev(dev);
13372 if (err) {
13373 printk(KERN_ERR PFX "Cannot register net device, "
13374 "aborting.\n");
0d3031d9 13375 goto err_out_apeunmap;
1da177e4
LT		 13376 }
13377
df59c940 13378 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13379 dev->name,
13380 tp->board_part_number,
13381 tp->pci_chip_rev_id,
f9804ddb 13382 tg3_bus_string(tp, str),
e174961c 13383 dev->dev_addr);
1da177e4 13384
df59c940
MC		 13385 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13386 printk(KERN_INFO
13387 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13388 tp->dev->name,
13389 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13390 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13391 else
13392 printk(KERN_INFO
13393 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13394 tp->dev->name, tg3_phy_string(tp),
13395 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13396 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13397 "10/100/1000Base-T")),
13398 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13399
13400 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13401 dev->name,
13402 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13403 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13404 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13405 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13406 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13407 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13408 dev->name, tp->dma_rwctrl,
284901a9 13409 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13410 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13411
13412 return 0;
13413
0d3031d9
MC		 13414err_out_apeunmap:
13415 if (tp->aperegs) {
13416 iounmap(tp->aperegs);
13417 tp->aperegs = NULL;
13418 }
13419
077f849d
JSR		 13420err_out_fw:
13421 if (tp->fw)
13422 release_firmware(tp->fw);
13423
1da177e4 13424err_out_iounmap:
6892914f
MC		 13425 if (tp->regs) {
13426 iounmap(tp->regs);
22abe310 13427 tp->regs = NULL;
6892914f 13428 }
1da177e4
LT		 13429
13430err_out_free_dev:
13431 free_netdev(dev);
13432
13433err_out_free_res:
13434 pci_release_regions(pdev);
13435
13436err_out_disable_pdev:
13437 pci_disable_device(pdev);
13438 pci_set_drvdata(pdev, NULL);
13439 return err;
13440}
13441
13442static void __devexit tg3_remove_one(struct pci_dev *pdev)
13443{
13444 struct net_device *dev = pci_get_drvdata(pdev);
13445
13446 if (dev) {
13447 struct tg3 *tp = netdev_priv(dev);
13448
077f849d
JSR		 13449 if (tp->fw)
13450 release_firmware(tp->fw);
13451
7faa006f 13452 flush_scheduled_work();
158d7abd 13453
b02fd9e3
MC		 13454 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13455 tg3_phy_fini(tp);
158d7abd 13456 tg3_mdio_fini(tp);
b02fd9e3 13457 }
158d7abd 13458
1da177e4 13459 unregister_netdev(dev);
0d3031d9
MC		 13460 if (tp->aperegs) {
13461 iounmap(tp->aperegs);
13462 tp->aperegs = NULL;
13463 }
6892914f
MC		 13464 if (tp->regs) {
13465 iounmap(tp->regs);
22abe310 13466 tp->regs = NULL;
6892914f 13467 }
1da177e4
LT		 13468 free_netdev(dev);
13469 pci_release_regions(pdev);
13470 pci_disable_device(pdev);
13471 pci_set_drvdata(pdev, NULL);
13472 }
13473}
13474
13475static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13476{
13477 struct net_device *dev = pci_get_drvdata(pdev);
13478 struct tg3 *tp = netdev_priv(dev);
12dac075 13479 pci_power_t target_state;
1da177e4
LT		 13480 int err;
13481
3e0c95fd
MC		 13482 /* PCI register 4 needs to be saved whether netif_running() or not.
13483 * MSI address and data need to be saved if using MSI and
13484 * netif_running().
13485 */
13486 pci_save_state(pdev);
13487
1da177e4
LT		 13488 if (!netif_running(dev))
13489 return 0;
13490
7faa006f 13491 flush_scheduled_work();
b02fd9e3 13492 tg3_phy_stop(tp);
1da177e4
LT		 13493 tg3_netif_stop(tp);
13494
13495 del_timer_sync(&tp->timer);
13496
f47c11ee 13497 tg3_full_lock(tp, 1);
1da177e4 13498 tg3_disable_ints(tp);
f47c11ee 13499 tg3_full_unlock(tp);
1da177e4
LT		 13500
13501 netif_device_detach(dev);
13502
f47c11ee 13503 tg3_full_lock(tp, 0);
944d980e 13504 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13505 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13506 tg3_full_unlock(tp);
1da177e4 13507
12dac075
RW		 13508 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13509
13510 err = tg3_set_power_state(tp, target_state);
1da177e4 13511 if (err) {
b02fd9e3
MC		 13512 int err2;
13513
f47c11ee 13514 tg3_full_lock(tp, 0);
1da177e4 13515
6a9eba15 13516 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13517 err2 = tg3_restart_hw(tp, 1);
13518 if (err2)
b9ec6c1b 13519 goto out;
1da177e4
LT		 13520
13521 tp->timer.expires = jiffies + tp->timer_offset;
13522 add_timer(&tp->timer);
13523
13524 netif_device_attach(dev);
13525 tg3_netif_start(tp);
13526
b9ec6c1b 13527out:
f47c11ee 13528 tg3_full_unlock(tp);
b02fd9e3
MC		 13529
13530 if (!err2)
13531 tg3_phy_start(tp);
1da177e4
LT		 13532 }
13533
13534 return err;
13535}
13536
13537static int tg3_resume(struct pci_dev *pdev)
13538{
13539 struct net_device *dev = pci_get_drvdata(pdev);
13540 struct tg3 *tp = netdev_priv(dev);
13541 int err;
13542
3e0c95fd
MC		 13543 pci_restore_state(tp->pdev);
13544
1da177e4
LT		 13545 if (!netif_running(dev))
13546 return 0;
13547
bc1c7567 13548 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13549 if (err)
13550 return err;
13551
13552 netif_device_attach(dev);
13553
f47c11ee 13554 tg3_full_lock(tp, 0);
1da177e4 13555
6a9eba15 13556 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13557 err = tg3_restart_hw(tp, 1);
13558 if (err)
13559 goto out;
1da177e4
LT		 13560
13561 tp->timer.expires = jiffies + tp->timer_offset;
13562 add_timer(&tp->timer);
13563
1da177e4
LT		 13564 tg3_netif_start(tp);
13565
b9ec6c1b 13566out:
f47c11ee 13567 tg3_full_unlock(tp);
1da177e4 13568
b02fd9e3
MC		 13569 if (!err)
13570 tg3_phy_start(tp);
13571
b9ec6c1b 13572 return err;
1da177e4
LT		 13573}
13574
13575static struct pci_driver tg3_driver = {
13576 .name = DRV_MODULE_NAME,
13577 .id_table = tg3_pci_tbl,
13578 .probe = tg3_init_one,
13579 .remove = __devexit_p(tg3_remove_one),
13580 .suspend = tg3_suspend,
13581 .resume = tg3_resume
13582};
13583
13584static int __init tg3_init(void)
13585{
29917620 13586 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13587}
13588
13589static void __exit tg3_cleanup(void)
13590{
13591 pci_unregister_driver(&tg3_driver);
13592}
13593
13594module_init(tg3_init);
13595module_exit(tg3_cleanup);
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