]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tg3: Use ext rx bds
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
f656f398
MC		 71#define DRV_MODULE_VERSION "3.100"
72#define DRV_MODULE_RELDATE "August 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
79ed5ac7
MC		 120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
1da177e4 122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 123 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC		 128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 137
138/* minimum number of free TX descriptors required to wake up TX process */
42952231 139#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 140
ad829268
MC		 141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT		 143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC		 146#define TG3_NUM_TEST 6
147
077f849d
JSR		 148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT		 152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
1da177e4
LT		 163
164static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165module_param(tg3_debug, int, 0);
166MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
1da177e4
LT		 243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
50da859d 247static const struct {
1da177e4
LT		 248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
50da859d 328static const struct {
4cafd3f5
MC		 329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
b401e9e2
MC		 339static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342}
343
344static u32 tg3_read32(struct tg3 *tp, u32 off)
345{
6aa20a22 346 return (readl(tp->regs + off));
b401e9e2
MC		 347}
348
0d3031d9
MC		 349static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->aperegs + off);
352}
353
354static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355{
356 return (readl(tp->aperegs + off));
357}
358
1da177e4
LT		 359static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360{
6892914f
MC		 361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 367}
368
369static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370{
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
1da177e4
LT		 373}
374
6892914f 375static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 376{
6892914f
MC		 377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385}
386
387static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388{
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
1da177e4 400 }
6892914f
MC		 401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415}
416
417static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418{
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427}
428
b401e9e2
MC		 429/* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 435{
b401e9e2
MC		 436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
1da177e4
LT		 452}
453
09ee929c
MC		 454static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455{
456 tp->write32_mbox(tp, off, val);
6892914f
MC		 457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
09ee929c
MC		 460}
461
20094930 462static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 463{
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470}
471
b5d3772c
MC		 472static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473{
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475}
476
477static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478{
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480}
481
20094930 482#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 483#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 484#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 486#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 487
488#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 489#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 491#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 492
493static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494{
6892914f
MC		 495 unsigned long flags;
496
b5d3772c
MC		 497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
6892914f 501 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 505
bbadf503
MC		 506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 511
bbadf503
MC		 512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 516}
517
1da177e4
LT		 518static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519{
6892914f
MC		 520 unsigned long flags;
521
b5d3772c
MC		 522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
6892914f 528 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 532
bbadf503
MC		 533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
6892914f 542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 543}
544
0d3031d9
MC		 545static void tg3_ape_lock_init(struct tg3 *tp)
546{
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553}
554
555static int tg3_ape_lock(struct tg3 *tp, int locknum)
556{
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
77b483f1 565 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593}
594
595static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596{
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
77b483f1 603 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612}
613
1da177e4
LT		 614static void tg3_disable_ints(struct tg3 *tp)
615{
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 618 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 619}
620
621static inline void tg3_cond_int(struct tg3 *tp)
622{
38f3843e
MC		 623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
624 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 626 else
627 tw32(HOSTCC_MODE, tp->coalesce_mode |
628 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 629}
630
631static void tg3_enable_ints(struct tg3 *tp)
632{
bbe832c0
MC		 633 tp->irq_sync = 0;
634 wmb();
635
1da177e4
LT		 636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 638 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
639 (tp->last_tag << 24));
fcfa0a32
MC		 640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
642 (tp->last_tag << 24));
1da177e4
LT		 643 tg3_cond_int(tp);
644}
645
04237ddd
MC		 646static inline unsigned int tg3_has_work(struct tg3 *tp)
647{
648 struct tg3_hw_status *sblk = tp->hw_status;
649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
659 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
660 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
661 work_exists = 1;
662
663 return work_exists;
664}
665
1da177e4 666/* tg3_restart_ints
04237ddd
MC		 667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
6aa20a22 669 * which reenables interrupts
1da177e4
LT		 670 */
671static void tg3_restart_ints(struct tg3 *tp)
672{
fac9b83e
DM		 673 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
674 tp->last_tag << 24);
1da177e4
LT		 675 mmiowb();
676
fac9b83e
DM		 677 /* When doing tagged status, this work check is unnecessary.
678 * The last_tag we write above tells the chip which piece of
679 * work we've completed.
680 */
681 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
682 tg3_has_work(tp))
04237ddd
MC		 683 tw32(HOSTCC_MODE, tp->coalesce_mode |
684 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 685}
686
687static inline void tg3_netif_stop(struct tg3 *tp)
688{
bbe832c0 689 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 690 napi_disable(&tp->napi);
1da177e4
LT		 691 netif_tx_disable(tp->dev);
692}
693
694static inline void tg3_netif_start(struct tg3 *tp)
695{
696 netif_wake_queue(tp->dev);
697 /* NOTE: unconditional netif_wake_queue is only appropriate
698 * so long as all callers are assured to have free tx slots
699 * (such as after tg3_init_hw)
700 */
bea3348e 701 napi_enable(&tp->napi);
f47c11ee
DM		 702 tp->hw_status->status |= SD_STATUS_UPDATED;
703 tg3_enable_ints(tp);
1da177e4
LT		 704}
705
706static void tg3_switch_clocks(struct tg3 *tp)
707{
708 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
709 u32 orig_clock_ctrl;
710
795d01c5
MC		 711 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
712 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 713 return;
714
1da177e4
LT		 715 orig_clock_ctrl = clock_ctrl;
716 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
717 CLOCK_CTRL_CLKRUN_OENABLE |
718 0x1f);
719 tp->pci_clock_ctrl = clock_ctrl;
720
721 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
722 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 725 }
726 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 727 tw32_wait_f(TG3PCI_CLOCK_CTRL,
728 clock_ctrl |
729 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
730 40);
731 tw32_wait_f(TG3PCI_CLOCK_CTRL,
732 clock_ctrl | (CLOCK_CTRL_ALTCLK),
733 40);
1da177e4 734 }
b401e9e2 735 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 736}
737
738#define PHY_BUSY_LOOPS 5000
739
740static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
741{
742 u32 frame_val;
743 unsigned int loops;
744 int ret;
745
746 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
747 tw32_f(MAC_MI_MODE,
748 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
749 udelay(80);
750 }
751
752 *val = 0x0;
753
754 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
755 MI_COM_PHY_ADDR_MASK);
756 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
757 MI_COM_REG_ADDR_MASK);
758 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 759
1da177e4
LT		 760 tw32_f(MAC_MI_COM, frame_val);
761
762 loops = PHY_BUSY_LOOPS;
763 while (loops != 0) {
764 udelay(10);
765 frame_val = tr32(MAC_MI_COM);
766
767 if ((frame_val & MI_COM_BUSY) == 0) {
768 udelay(5);
769 frame_val = tr32(MAC_MI_COM);
770 break;
771 }
772 loops -= 1;
773 }
774
775 ret = -EBUSY;
776 if (loops != 0) {
777 *val = frame_val & MI_COM_DATA_MASK;
778 ret = 0;
779 }
780
781 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
782 tw32_f(MAC_MI_MODE, tp->mi_mode);
783 udelay(80);
784 }
785
786 return ret;
787}
788
789static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
790{
791 u32 frame_val;
792 unsigned int loops;
793 int ret;
794
7f97a4bd 795 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 796 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
797 return 0;
798
1da177e4
LT		 799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE,
801 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802 udelay(80);
803 }
804
805 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
806 MI_COM_PHY_ADDR_MASK);
807 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
808 MI_COM_REG_ADDR_MASK);
809 frame_val |= (val & MI_COM_DATA_MASK);
810 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 811
1da177e4
LT		 812 tw32_f(MAC_MI_COM, frame_val);
813
814 loops = PHY_BUSY_LOOPS;
815 while (loops != 0) {
816 udelay(10);
817 frame_val = tr32(MAC_MI_COM);
818 if ((frame_val & MI_COM_BUSY) == 0) {
819 udelay(5);
820 frame_val = tr32(MAC_MI_COM);
821 break;
822 }
823 loops -= 1;
824 }
825
826 ret = -EBUSY;
827 if (loops != 0)
828 ret = 0;
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE, tp->mi_mode);
832 udelay(80);
833 }
834
835 return ret;
836}
837
95e2869a
MC		 838static int tg3_bmcr_reset(struct tg3 *tp)
839{
840 u32 phy_control;
841 int limit, err;
842
843 /* OK, reset it, and poll the BMCR_RESET bit until it
844 * clears or we time out.
845 */
846 phy_control = BMCR_RESET;
847 err = tg3_writephy(tp, MII_BMCR, phy_control);
848 if (err != 0)
849 return -EBUSY;
850
851 limit = 5000;
852 while (limit--) {
853 err = tg3_readphy(tp, MII_BMCR, &phy_control);
854 if (err != 0)
855 return -EBUSY;
856
857 if ((phy_control & BMCR_RESET) == 0) {
858 udelay(40);
859 break;
860 }
861 udelay(10);
862 }
d4675b52 863 if (limit < 0)
95e2869a
MC		 864 return -EBUSY;
865
866 return 0;
867}
868
158d7abd
MC		 869static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
870{
3d16543d 871 struct tg3 *tp = bp->priv;
158d7abd
MC		 872 u32 val;
873
874 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
875 return -EAGAIN;
876
877 if (tg3_readphy(tp, reg, &val))
878 return -EIO;
879
880 return val;
881}
882
883static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
884{
3d16543d 885 struct tg3 *tp = bp->priv;
158d7abd
MC		 886
887 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
888 return -EAGAIN;
889
890 if (tg3_writephy(tp, reg, val))
891 return -EIO;
892
893 return 0;
894}
895
896static int tg3_mdio_reset(struct mii_bus *bp)
897{
898 return 0;
899}
900
9c61d6bc 901static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 902{
903 u32 val;
fcb389df 904 struct phy_device *phydev;
a9daf367 905
fcb389df
MC		 906 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
907 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
908 case TG3_PHY_ID_BCM50610:
909 val = MAC_PHYCFG2_50610_LED_MODES;
910 break;
911 case TG3_PHY_ID_BCMAC131:
912 val = MAC_PHYCFG2_AC131_LED_MODES;
913 break;
914 case TG3_PHY_ID_RTL8211C:
915 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
916 break;
917 case TG3_PHY_ID_RTL8201E:
918 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
919 break;
920 default:
a9daf367 921 return;
fcb389df
MC		 922 }
923
924 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
925 tw32(MAC_PHYCFG2, val);
926
927 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 928 val &= ~(MAC_PHYCFG1_RGMII_INT |
929 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
930 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 931 tw32(MAC_PHYCFG1, val);
932
933 return;
934 }
935
936 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
937 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
938 MAC_PHYCFG2_FMODE_MASK_MASK |
939 MAC_PHYCFG2_GMODE_MASK_MASK |
940 MAC_PHYCFG2_ACT_MASK_MASK |
941 MAC_PHYCFG2_QUAL_MASK_MASK |
942 MAC_PHYCFG2_INBAND_ENABLE;
943
944 tw32(MAC_PHYCFG2, val);
a9daf367 945
bb85fbb6
MC		 946 val = tr32(MAC_PHYCFG1);
947 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
948 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
949 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 950 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
951 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
953 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
954 }
bb85fbb6
MC		 955 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
956 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
957 tw32(MAC_PHYCFG1, val);
a9daf367 958
a9daf367
MC		 959 val = tr32(MAC_EXT_RGMII_MODE);
960 val &= ~(MAC_RGMII_MODE_RX_INT_B |
961 MAC_RGMII_MODE_RX_QUALITY |
962 MAC_RGMII_MODE_RX_ACTIVITY |
963 MAC_RGMII_MODE_RX_ENG_DET |
964 MAC_RGMII_MODE_TX_ENABLE |
965 MAC_RGMII_MODE_TX_LOWPWR |
966 MAC_RGMII_MODE_TX_RESET);
fcb389df 967 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 968 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
969 val |= MAC_RGMII_MODE_RX_INT_B |
970 MAC_RGMII_MODE_RX_QUALITY |
971 MAC_RGMII_MODE_RX_ACTIVITY |
972 MAC_RGMII_MODE_RX_ENG_DET;
973 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
974 val |= MAC_RGMII_MODE_TX_ENABLE |
975 MAC_RGMII_MODE_TX_LOWPWR |
976 MAC_RGMII_MODE_TX_RESET;
977 }
978 tw32(MAC_EXT_RGMII_MODE, val);
979}
980
158d7abd
MC		 981static void tg3_mdio_start(struct tg3 *tp)
982{
983 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 984 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 985 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 986 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 987 }
988
989 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
990 tw32_f(MAC_MI_MODE, tp->mi_mode);
991 udelay(80);
a9daf367 992
9c61d6bc
MC		 993 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
995 tg3_mdio_config_5785(tp);
158d7abd
MC		 996}
997
998static void tg3_mdio_stop(struct tg3 *tp)
999{
1000 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1001 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1002 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1003 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 1004 }
1005}
1006
1007static int tg3_mdio_init(struct tg3 *tp)
1008{
1009 int i;
1010 u32 reg;
a9daf367 1011 struct phy_device *phydev;
158d7abd
MC		 1012
1013 tg3_mdio_start(tp);
1014
1015 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1016 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1017 return 0;
1018
298cf9be
LB		 1019 tp->mdio_bus = mdiobus_alloc();
1020 if (tp->mdio_bus == NULL)
1021 return -ENOMEM;
158d7abd 1022
298cf9be
LB		 1023 tp->mdio_bus->name = "tg3 mdio bus";
1024 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1025 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1026 tp->mdio_bus->priv = tp;
1027 tp->mdio_bus->parent = &tp->pdev->dev;
1028 tp->mdio_bus->read = &tg3_mdio_read;
1029 tp->mdio_bus->write = &tg3_mdio_write;
1030 tp->mdio_bus->reset = &tg3_mdio_reset;
1031 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1032 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1033
1034 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1035 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1036
1037 /* The bus registration will look for all the PHYs on the mdio bus.
1038 * Unfortunately, it does not ensure the PHY is powered up before
1039 * accessing the PHY ID registers. A chip reset is the
1040 * quickest way to bring the device back to an operational state..
1041 */
1042 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1043 tg3_bmcr_reset(tp);
1044
298cf9be 1045 i = mdiobus_register(tp->mdio_bus);
a9daf367 1046 if (i) {
158d7abd
MC		 1047 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1048 tp->dev->name, i);
9c61d6bc 1049 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1050 return i;
1051 }
158d7abd 1052
298cf9be 1053 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1054
9c61d6bc
MC		 1055 if (!phydev || !phydev->drv) {
1056 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1057 mdiobus_unregister(tp->mdio_bus);
1058 mdiobus_free(tp->mdio_bus);
1059 return -ENODEV;
1060 }
1061
1062 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1063 case TG3_PHY_ID_BCM57780:
1064 phydev->interface = PHY_INTERFACE_MODE_GMII;
1065 break;
a9daf367 1066 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1067 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1068 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1070 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1073 /* fallthru */
1074 case TG3_PHY_ID_RTL8211C:
1075 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1076 break;
fcb389df 1077 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1078 case TG3_PHY_ID_BCMAC131:
1079 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1080 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1081 break;
1082 }
1083
9c61d6bc
MC		 1084 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1085
1086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1087 tg3_mdio_config_5785(tp);
a9daf367
MC		 1088
1089 return 0;
158d7abd
MC		 1090}
1091
1092static void tg3_mdio_fini(struct tg3 *tp)
1093{
1094 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1095 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1096 mdiobus_unregister(tp->mdio_bus);
1097 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1098 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1099 }
1100}
1101
4ba526ce
MC		 1102/* tp->lock is held. */
1103static inline void tg3_generate_fw_event(struct tg3 *tp)
1104{
1105 u32 val;
1106
1107 val = tr32(GRC_RX_CPU_EVENT);
1108 val |= GRC_RX_CPU_DRIVER_EVENT;
1109 tw32_f(GRC_RX_CPU_EVENT, val);
1110
1111 tp->last_event_jiffies = jiffies;
1112}
1113
1114#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1115
95e2869a
MC		 1116/* tp->lock is held. */
1117static void tg3_wait_for_event_ack(struct tg3 *tp)
1118{
1119 int i;
4ba526ce
MC		 1120 unsigned int delay_cnt;
1121 long time_remain;
1122
1123 /* If enough time has passed, no wait is necessary. */
1124 time_remain = (long)(tp->last_event_jiffies + 1 +
1125 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1126 (long)jiffies;
1127 if (time_remain < 0)
1128 return;
1129
1130 /* Check if we can shorten the wait time. */
1131 delay_cnt = jiffies_to_usecs(time_remain);
1132 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1133 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1134 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1135
4ba526ce 1136 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1137 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1138 break;
4ba526ce 1139 udelay(8);
95e2869a
MC		 1140 }
1141}
1142
1143/* tp->lock is held. */
1144static void tg3_ump_link_report(struct tg3 *tp)
1145{
1146 u32 reg;
1147 u32 val;
1148
1149 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1150 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1151 return;
1152
1153 tg3_wait_for_event_ack(tp);
1154
1155 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1158
1159 val = 0;
1160 if (!tg3_readphy(tp, MII_BMCR, &reg))
1161 val = reg << 16;
1162 if (!tg3_readphy(tp, MII_BMSR, &reg))
1163 val |= (reg & 0xffff);
1164 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1165
1166 val = 0;
1167 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1168 val = reg << 16;
1169 if (!tg3_readphy(tp, MII_LPA, &reg))
1170 val |= (reg & 0xffff);
1171 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1172
1173 val = 0;
1174 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1175 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1176 val = reg << 16;
1177 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1178 val |= (reg & 0xffff);
1179 }
1180 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1181
1182 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1183 val = reg << 16;
1184 else
1185 val = 0;
1186 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1187
4ba526ce 1188 tg3_generate_fw_event(tp);
95e2869a
MC		 1189}
1190
1191static void tg3_link_report(struct tg3 *tp)
1192{
1193 if (!netif_carrier_ok(tp->dev)) {
1194 if (netif_msg_link(tp))
1195 printk(KERN_INFO PFX "%s: Link is down.\n",
1196 tp->dev->name);
1197 tg3_ump_link_report(tp);
1198 } else if (netif_msg_link(tp)) {
1199 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1200 tp->dev->name,
1201 (tp->link_config.active_speed == SPEED_1000 ?
1202 1000 :
1203 (tp->link_config.active_speed == SPEED_100 ?
1204 100 : 10)),
1205 (tp->link_config.active_duplex == DUPLEX_FULL ?
1206 "full" : "half"));
1207
1208 printk(KERN_INFO PFX
1209 "%s: Flow control is %s for TX and %s for RX.\n",
1210 tp->dev->name,
e18ce346 1211 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1212 "on" : "off",
e18ce346 1213 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1214 "on" : "off");
1215 tg3_ump_link_report(tp);
1216 }
1217}
1218
1219static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1220{
1221 u16 miireg;
1222
e18ce346 1223 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1224 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1225 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1226 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1228 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1229 else
1230 miireg = 0;
1231
1232 return miireg;
1233}
1234
1235static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1236{
1237 u16 miireg;
1238
e18ce346 1239 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1240 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1241 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1242 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1243 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1244 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1245 else
1246 miireg = 0;
1247
1248 return miireg;
1249}
1250
95e2869a
MC		 1251static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1252{
1253 u8 cap = 0;
1254
1255 if (lcladv & ADVERTISE_1000XPAUSE) {
1256 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1257 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1258 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1259 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1260 cap = FLOW_CTRL_RX;
95e2869a
MC		 1261 } else {
1262 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1263 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1264 }
1265 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1266 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1267 cap = FLOW_CTRL_TX;
95e2869a
MC		 1268 }
1269
1270 return cap;
1271}
1272
f51f3562 1273static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1274{
b02fd9e3 1275 u8 autoneg;
f51f3562 1276 u8 flowctrl = 0;
95e2869a
MC		 1277 u32 old_rx_mode = tp->rx_mode;
1278 u32 old_tx_mode = tp->tx_mode;
1279
b02fd9e3 1280 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1281 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1282 else
1283 autoneg = tp->link_config.autoneg;
1284
1285 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1286 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1287 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1288 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1289 else
bc02ff95 1290 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1291 } else
1292 flowctrl = tp->link_config.flowctrl;
95e2869a 1293
f51f3562 1294 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1295
e18ce346 1296 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1297 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1298 else
1299 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1300
f51f3562 1301 if (old_rx_mode != tp->rx_mode)
95e2869a 1302 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1303
e18ce346 1304 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1305 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1306 else
1307 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1308
f51f3562 1309 if (old_tx_mode != tp->tx_mode)
95e2869a 1310 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1311}
1312
b02fd9e3
MC		 1313static void tg3_adjust_link(struct net_device *dev)
1314{
1315 u8 oldflowctrl, linkmesg = 0;
1316 u32 mac_mode, lcl_adv, rmt_adv;
1317 struct tg3 *tp = netdev_priv(dev);
298cf9be 1318 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1319
1320 spin_lock(&tp->lock);
1321
1322 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1323 MAC_MODE_HALF_DUPLEX);
1324
1325 oldflowctrl = tp->link_config.active_flowctrl;
1326
1327 if (phydev->link) {
1328 lcl_adv = 0;
1329 rmt_adv = 0;
1330
1331 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1332 mac_mode |= MAC_MODE_PORT_MODE_MII;
1333 else
1334 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1335
1336 if (phydev->duplex == DUPLEX_HALF)
1337 mac_mode |= MAC_MODE_HALF_DUPLEX;
1338 else {
1339 lcl_adv = tg3_advert_flowctrl_1000T(
1340 tp->link_config.flowctrl);
1341
1342 if (phydev->pause)
1343 rmt_adv = LPA_PAUSE_CAP;
1344 if (phydev->asym_pause)
1345 rmt_adv |= LPA_PAUSE_ASYM;
1346 }
1347
1348 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1349 } else
1350 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1351
1352 if (mac_mode != tp->mac_mode) {
1353 tp->mac_mode = mac_mode;
1354 tw32_f(MAC_MODE, tp->mac_mode);
1355 udelay(40);
1356 }
1357
fcb389df
MC		 1358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1359 if (phydev->speed == SPEED_10)
1360 tw32(MAC_MI_STAT,
1361 MAC_MI_STAT_10MBPS_MODE |
1362 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1363 else
1364 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 }
1366
b02fd9e3
MC		 1367 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1368 tw32(MAC_TX_LENGTHS,
1369 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1370 (6 << TX_LENGTHS_IPG_SHIFT) |
1371 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1372 else
1373 tw32(MAC_TX_LENGTHS,
1374 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1375 (6 << TX_LENGTHS_IPG_SHIFT) |
1376 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1377
1378 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1379 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1380 phydev->speed != tp->link_config.active_speed ||
1381 phydev->duplex != tp->link_config.active_duplex ||
1382 oldflowctrl != tp->link_config.active_flowctrl)
1383 linkmesg = 1;
1384
1385 tp->link_config.active_speed = phydev->speed;
1386 tp->link_config.active_duplex = phydev->duplex;
1387
1388 spin_unlock(&tp->lock);
1389
1390 if (linkmesg)
1391 tg3_link_report(tp);
1392}
1393
1394static int tg3_phy_init(struct tg3 *tp)
1395{
1396 struct phy_device *phydev;
1397
1398 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1399 return 0;
1400
1401 /* Bring the PHY back to a known state. */
1402 tg3_bmcr_reset(tp);
1403
298cf9be 1404 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1405
1406 /* Attach the MAC to the PHY. */
fb28ad35 1407 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1408 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1409 if (IS_ERR(phydev)) {
1410 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1411 return PTR_ERR(phydev);
1412 }
1413
b02fd9e3 1414 /* Mask with MAC supported features. */
9c61d6bc
MC		 1415 switch (phydev->interface) {
1416 case PHY_INTERFACE_MODE_GMII:
1417 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1418 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1419 phydev->supported &= (PHY_GBIT_FEATURES |
1420 SUPPORTED_Pause |
1421 SUPPORTED_Asym_Pause);
1422 break;
1423 }
1424 /* fallthru */
9c61d6bc
MC		 1425 case PHY_INTERFACE_MODE_MII:
1426 phydev->supported &= (PHY_BASIC_FEATURES |
1427 SUPPORTED_Pause |
1428 SUPPORTED_Asym_Pause);
1429 break;
1430 default:
1431 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1432 return -EINVAL;
1433 }
1434
1435 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1436
1437 phydev->advertising = phydev->supported;
1438
b02fd9e3
MC		 1439 return 0;
1440}
1441
1442static void tg3_phy_start(struct tg3 *tp)
1443{
1444 struct phy_device *phydev;
1445
1446 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1447 return;
1448
298cf9be 1449 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1450
1451 if (tp->link_config.phy_is_low_power) {
1452 tp->link_config.phy_is_low_power = 0;
1453 phydev->speed = tp->link_config.orig_speed;
1454 phydev->duplex = tp->link_config.orig_duplex;
1455 phydev->autoneg = tp->link_config.orig_autoneg;
1456 phydev->advertising = tp->link_config.orig_advertising;
1457 }
1458
1459 phy_start(phydev);
1460
1461 phy_start_aneg(phydev);
1462}
1463
1464static void tg3_phy_stop(struct tg3 *tp)
1465{
1466 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1467 return;
1468
298cf9be 1469 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1470}
1471
1472static void tg3_phy_fini(struct tg3 *tp)
1473{
1474 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1475 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1476 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1477 }
1478}
1479
b2a5c19c
MC		 1480static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1481{
1482 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1483 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1484}
1485
7f97a4bd
MC		 1486static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1487{
1488 u32 phytest;
1489
1490 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1491 u32 phy;
1492
1493 tg3_writephy(tp, MII_TG3_FET_TEST,
1494 phytest | MII_TG3_FET_SHADOW_EN);
1495 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1496 if (enable)
1497 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1498 else
1499 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1501 }
1502 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1503 }
1504}
1505
6833c043
MC		 1506static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1507{
1508 u32 reg;
1509
7f97a4bd 1510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1511 return;
1512
7f97a4bd
MC		 1513 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1514 tg3_phy_fet_toggle_apd(tp, enable);
1515 return;
1516 }
1517
6833c043
MC		 1518 reg = MII_TG3_MISC_SHDW_WREN |
1519 MII_TG3_MISC_SHDW_SCR5_SEL |
1520 MII_TG3_MISC_SHDW_SCR5_LPED |
1521 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1522 MII_TG3_MISC_SHDW_SCR5_SDTL |
1523 MII_TG3_MISC_SHDW_SCR5_C125OE;
1524 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1525 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1526
1527 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1528
1529
1530 reg = MII_TG3_MISC_SHDW_WREN |
1531 MII_TG3_MISC_SHDW_APD_SEL |
1532 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1533 if (enable)
1534 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1535
1536 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1537}
1538
9ef8ca99
MC		 1539static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1540{
1541 u32 phy;
1542
1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1544 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1545 return;
1546
7f97a4bd 1547 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1548 u32 ephy;
1549
535ef6e1
MC		 1550 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1551 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1552
1553 tg3_writephy(tp, MII_TG3_FET_TEST,
1554 ephy | MII_TG3_FET_SHADOW_EN);
1555 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1556 if (enable)
535ef6e1 1557 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1558 else
535ef6e1
MC		 1559 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1560 tg3_writephy(tp, reg, phy);
9ef8ca99 1561 }
535ef6e1 1562 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1563 }
1564 } else {
1565 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1566 MII_TG3_AUXCTL_SHDWSEL_MISC;
1567 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1568 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1569 if (enable)
1570 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1571 else
1572 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 phy |= MII_TG3_AUXCTL_MISC_WREN;
1574 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1575 }
1576 }
1577}
1578
1da177e4
LT		 1579static void tg3_phy_set_wirespeed(struct tg3 *tp)
1580{
1581 u32 val;
1582
1583 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1584 return;
1585
1586 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1587 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1588 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1589 (val | (1 << 15) | (1 << 4)));
1590}
1591
b2a5c19c
MC		 1592static void tg3_phy_apply_otp(struct tg3 *tp)
1593{
1594 u32 otp, phy;
1595
1596 if (!tp->phy_otp)
1597 return;
1598
1599 otp = tp->phy_otp;
1600
1601 /* Enable SM_DSP clock and tx 6dB coding. */
1602 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1603 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1604 MII_TG3_AUXCTL_ACTL_TX_6DB;
1605 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1606
1607 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1608 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1609 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1610
1611 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1612 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1613 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1614
1615 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1616 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1617 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1618
1619 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1620 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1621
1622 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1623 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1624
1625 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1626 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1627 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1628
1629 /* Turn off SM_DSP clock. */
1630 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1631 MII_TG3_AUXCTL_ACTL_TX_6DB;
1632 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1633}
1634
1da177e4
LT		 1635static int tg3_wait_macro_done(struct tg3 *tp)
1636{
1637 int limit = 100;
1638
1639 while (limit--) {
1640 u32 tmp32;
1641
1642 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1643 if ((tmp32 & 0x1000) == 0)
1644 break;
1645 }
1646 }
d4675b52 1647 if (limit < 0)
1da177e4
LT		 1648 return -EBUSY;
1649
1650 return 0;
1651}
1652
1653static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1654{
1655 static const u32 test_pat[4][6] = {
1656 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1657 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1658 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1659 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1660 };
1661 int chan;
1662
1663 for (chan = 0; chan < 4; chan++) {
1664 int i;
1665
1666 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1667 (chan * 0x2000) | 0x0200);
1668 tg3_writephy(tp, 0x16, 0x0002);
1669
1670 for (i = 0; i < 6; i++)
1671 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1672 test_pat[chan][i]);
1673
1674 tg3_writephy(tp, 0x16, 0x0202);
1675 if (tg3_wait_macro_done(tp)) {
1676 *resetp = 1;
1677 return -EBUSY;
1678 }
1679
1680 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1681 (chan * 0x2000) | 0x0200);
1682 tg3_writephy(tp, 0x16, 0x0082);
1683 if (tg3_wait_macro_done(tp)) {
1684 *resetp = 1;
1685 return -EBUSY;
1686 }
1687
1688 tg3_writephy(tp, 0x16, 0x0802);
1689 if (tg3_wait_macro_done(tp)) {
1690 *resetp = 1;
1691 return -EBUSY;
1692 }
1693
1694 for (i = 0; i < 6; i += 2) {
1695 u32 low, high;
1696
1697 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1698 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1699 tg3_wait_macro_done(tp)) {
1700 *resetp = 1;
1701 return -EBUSY;
1702 }
1703 low &= 0x7fff;
1704 high &= 0x000f;
1705 if (low != test_pat[chan][i] ||
1706 high != test_pat[chan][i+1]) {
1707 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1708 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1709 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1710
1711 return -EBUSY;
1712 }
1713 }
1714 }
1715
1716 return 0;
1717}
1718
1719static int tg3_phy_reset_chanpat(struct tg3 *tp)
1720{
1721 int chan;
1722
1723 for (chan = 0; chan < 4; chan++) {
1724 int i;
1725
1726 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1727 (chan * 0x2000) | 0x0200);
1728 tg3_writephy(tp, 0x16, 0x0002);
1729 for (i = 0; i < 6; i++)
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1731 tg3_writephy(tp, 0x16, 0x0202);
1732 if (tg3_wait_macro_done(tp))
1733 return -EBUSY;
1734 }
1735
1736 return 0;
1737}
1738
1739static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1740{
1741 u32 reg32, phy9_orig;
1742 int retries, do_phy_reset, err;
1743
1744 retries = 10;
1745 do_phy_reset = 1;
1746 do {
1747 if (do_phy_reset) {
1748 err = tg3_bmcr_reset(tp);
1749 if (err)
1750 return err;
1751 do_phy_reset = 0;
1752 }
1753
1754 /* Disable transmitter and interrupt. */
1755 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1756 continue;
1757
1758 reg32 |= 0x3000;
1759 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1760
1761 /* Set full-duplex, 1000 mbps. */
1762 tg3_writephy(tp, MII_BMCR,
1763 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1764
1765 /* Set to master mode. */
1766 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1767 continue;
1768
1769 tg3_writephy(tp, MII_TG3_CTRL,
1770 (MII_TG3_CTRL_AS_MASTER |
1771 MII_TG3_CTRL_ENABLE_AS_MASTER));
1772
1773 /* Enable SM_DSP_CLOCK and 6dB. */
1774 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1775
1776 /* Block the PHY control access. */
1777 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1778 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1779
1780 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1781 if (!err)
1782 break;
1783 } while (--retries);
1784
1785 err = tg3_phy_reset_chanpat(tp);
1786 if (err)
1787 return err;
1788
1789 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1790 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1793 tg3_writephy(tp, 0x16, 0x0000);
1794
1795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1797 /* Set Extended packet length bit for jumbo frames */
1798 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1799 }
1800 else {
1801 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1802 }
1803
1804 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1805
1806 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1807 reg32 &= ~0x3000;
1808 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1809 } else if (!err)
1810 err = -EBUSY;
1811
1812 return err;
1813}
1814
1815/* This will reset the tigon3 PHY if there is no valid
1816 * link unless the FORCE argument is non-zero.
1817 */
1818static int tg3_phy_reset(struct tg3 *tp)
1819{
b2a5c19c 1820 u32 cpmuctrl;
1da177e4
LT		 1821 u32 phy_status;
1822 int err;
1823
60189ddf
MC		 1824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1825 u32 val;
1826
1827 val = tr32(GRC_MISC_CFG);
1828 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1829 udelay(40);
1830 }
1da177e4
LT		 1831 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1832 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1833 if (err != 0)
1834 return -EBUSY;
1835
c8e1e82b
MC		 1836 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1837 netif_carrier_off(tp->dev);
1838 tg3_link_report(tp);
1839 }
1840
1da177e4
LT		 1841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1843 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1844 err = tg3_phy_reset_5703_4_5(tp);
1845 if (err)
1846 return err;
1847 goto out;
1848 }
1849
b2a5c19c
MC		 1850 cpmuctrl = 0;
1851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1852 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1853 cpmuctrl = tr32(TG3_CPMU_CTRL);
1854 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1855 tw32(TG3_CPMU_CTRL,
1856 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1857 }
1858
1da177e4
LT		 1859 err = tg3_bmcr_reset(tp);
1860 if (err)
1861 return err;
1862
b2a5c19c
MC		 1863 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1864 u32 phy;
1865
1866 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1867 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1868
1869 tw32(TG3_CPMU_CTRL, cpmuctrl);
1870 }
1871
bcb37f6c
MC		 1872 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1873 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1874 u32 val;
1875
1876 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1877 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1878 CPMU_LSPD_1000MB_MACCLK_12_5) {
1879 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1880 udelay(40);
1881 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1882 }
1883 }
1884
b2a5c19c
MC		 1885 tg3_phy_apply_otp(tp);
1886
6833c043
MC		 1887 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1888 tg3_phy_toggle_apd(tp, true);
1889 else
1890 tg3_phy_toggle_apd(tp, false);
1891
1da177e4
LT		 1892out:
1893 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1894 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1895 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1896 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1900 }
1901 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1902 tg3_writephy(tp, 0x1c, 0x8d68);
1903 tg3_writephy(tp, 0x1c, 0x8d68);
1904 }
1905 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1906 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1907 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1908 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1913 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1914 }
c424cb24
MC		 1915 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1917 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1918 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1919 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1920 tg3_writephy(tp, MII_TG3_TEST1,
1921 MII_TG3_TEST1_TRIM_EN | 0x4);
1922 } else
1923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1924 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1925 }
1da177e4
LT		 1926 /* Set Extended packet length bit (bit 14) on all chips that */
1927 /* support jumbo frames */
1928 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1929 /* Cannot do read-modify-write on 5401 */
1930 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1931 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1932 u32 phy_reg;
1933
1934 /* Set bit 14 with read-modify-write to preserve other bits */
1935 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1936 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1937 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1938 }
1939
1940 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1941 * jumbo frames transmission.
1942 */
8f666b07 1943 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1944 u32 phy_reg;
1945
1946 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1947 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1948 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1949 }
1950
715116a1 1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1952 /* adjust output voltage */
535ef6e1 1953 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1954 }
1955
9ef8ca99 1956 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1957 tg3_phy_set_wirespeed(tp);
1958 return 0;
1959}
1960
1961static void tg3_frob_aux_power(struct tg3 *tp)
1962{
1963 struct tg3 *tp_peer = tp;
1964
9d26e213 1965 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1966 return;
1967
8c2dc7e1
MC		 1968 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1969 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1970 struct net_device *dev_peer;
1971
1972 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1973 /* remove_one() may have been run on the peer. */
8c2dc7e1 1974 if (!dev_peer)
bc1c7567
MC		 1975 tp_peer = tp;
1976 else
1977 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1978 }
1979
1da177e4 1980 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1981 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1982 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1983 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1986 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1987 (GRC_LCLCTRL_GPIO_OE0 |
1988 GRC_LCLCTRL_GPIO_OE1 |
1989 GRC_LCLCTRL_GPIO_OE2 |
1990 GRC_LCLCTRL_GPIO_OUTPUT0 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1),
1992 100);
8d519ab2
MC		 1993 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1994 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1995 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1996 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1997 GRC_LCLCTRL_GPIO_OE1 |
1998 GRC_LCLCTRL_GPIO_OE2 |
1999 GRC_LCLCTRL_GPIO_OUTPUT0 |
2000 GRC_LCLCTRL_GPIO_OUTPUT1 |
2001 tp->grc_local_ctrl;
2002 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2003
2004 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2005 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006
2007 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2008 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2009 } else {
2010 u32 no_gpio2;
dc56b7d4 2011 u32 grc_local_ctrl = 0;
1da177e4
LT		 2012
2013 if (tp_peer != tp &&
2014 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2015 return;
2016
dc56b7d4
MC		 2017 /* Workaround to prevent overdrawing Amps. */
2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2019 ASIC_REV_5714) {
2020 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2021 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022 grc_local_ctrl, 100);
dc56b7d4
MC		 2023 }
2024
1da177e4
LT		 2025 /* On 5753 and variants, GPIO2 cannot be used. */
2026 no_gpio2 = tp->nic_sram_data_cfg &
2027 NIC_SRAM_DATA_CFG_NO_GPIO2;
2028
dc56b7d4 2029 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2030 GRC_LCLCTRL_GPIO_OE1 |
2031 GRC_LCLCTRL_GPIO_OE2 |
2032 GRC_LCLCTRL_GPIO_OUTPUT1 |
2033 GRC_LCLCTRL_GPIO_OUTPUT2;
2034 if (no_gpio2) {
2035 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2036 GRC_LCLCTRL_GPIO_OUTPUT2);
2037 }
b401e9e2
MC		 2038 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2039 grc_local_ctrl, 100);
1da177e4
LT		 2040
2041 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2042
b401e9e2
MC		 2043 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2044 grc_local_ctrl, 100);
1da177e4
LT		 2045
2046 if (!no_gpio2) {
2047 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2048 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2049 grc_local_ctrl, 100);
1da177e4
LT		 2050 }
2051 }
2052 } else {
2053 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2054 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2055 if (tp_peer != tp &&
2056 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2057 return;
2058
b401e9e2
MC		 2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE1 |
2061 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2062
b401e9e2
MC		 2063 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2064 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2065
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 (GRC_LCLCTRL_GPIO_OE1 |
2068 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2069 }
2070 }
2071}
2072
e8f3f6ca
MC		 2073static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2074{
2075 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2076 return 1;
2077 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2078 if (speed != SPEED_10)
2079 return 1;
2080 } else if (speed == SPEED_10)
2081 return 1;
2082
2083 return 0;
2084}
2085
1da177e4
LT		 2086static int tg3_setup_phy(struct tg3 *, int);
2087
2088#define RESET_KIND_SHUTDOWN 0
2089#define RESET_KIND_INIT 1
2090#define RESET_KIND_SUSPEND 2
2091
2092static void tg3_write_sig_post_reset(struct tg3 *, int);
2093static int tg3_halt_cpu(struct tg3 *, u32);
2094
0a459aac 2095static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2096{
ce057f01
MC		 2097 u32 val;
2098
5129724a
MC		 2099 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2101 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2102 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2103
2104 sg_dig_ctrl |=
2105 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2106 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2107 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2108 }
3f7045c1 2109 return;
5129724a 2110 }
3f7045c1 2111
60189ddf 2112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2113 tg3_bmcr_reset(tp);
2114 val = tr32(GRC_MISC_CFG);
2115 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2116 udelay(40);
2117 return;
0a459aac 2118 } else if (do_low_power) {
715116a1
MC		 2119 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2120 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2121
2122 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2123 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2124 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2125 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2126 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2127 }
3f7045c1 2128
15c3b696
MC		 2129 /* The PHY should not be powered down on some chips because
2130 * of bugs.
2131 */
2132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2135 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2136 return;
ce057f01 2137
bcb37f6c
MC		 2138 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2139 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2140 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2141 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2142 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2143 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2144 }
2145
15c3b696
MC		 2146 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2147}
2148
ffbcfed4
MC		 2149/* tp->lock is held. */
2150static int tg3_nvram_lock(struct tg3 *tp)
2151{
2152 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2153 int i;
2154
2155 if (tp->nvram_lock_cnt == 0) {
2156 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2157 for (i = 0; i < 8000; i++) {
2158 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2159 break;
2160 udelay(20);
2161 }
2162 if (i == 8000) {
2163 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2164 return -ENODEV;
2165 }
2166 }
2167 tp->nvram_lock_cnt++;
2168 }
2169 return 0;
2170}
2171
2172/* tp->lock is held. */
2173static void tg3_nvram_unlock(struct tg3 *tp)
2174{
2175 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2176 if (tp->nvram_lock_cnt > 0)
2177 tp->nvram_lock_cnt--;
2178 if (tp->nvram_lock_cnt == 0)
2179 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2180 }
2181}
2182
2183/* tp->lock is held. */
2184static void tg3_enable_nvram_access(struct tg3 *tp)
2185{
2186 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2187 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2188 u32 nvaccess = tr32(NVRAM_ACCESS);
2189
2190 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2191 }
2192}
2193
2194/* tp->lock is held. */
2195static void tg3_disable_nvram_access(struct tg3 *tp)
2196{
2197 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2198 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2199 u32 nvaccess = tr32(NVRAM_ACCESS);
2200
2201 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2202 }
2203}
2204
2205static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2206 u32 offset, u32 *val)
2207{
2208 u32 tmp;
2209 int i;
2210
2211 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2212 return -EINVAL;
2213
2214 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2215 EEPROM_ADDR_DEVID_MASK |
2216 EEPROM_ADDR_READ);
2217 tw32(GRC_EEPROM_ADDR,
2218 tmp |
2219 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2220 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2221 EEPROM_ADDR_ADDR_MASK) |
2222 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2223
2224 for (i = 0; i < 1000; i++) {
2225 tmp = tr32(GRC_EEPROM_ADDR);
2226
2227 if (tmp & EEPROM_ADDR_COMPLETE)
2228 break;
2229 msleep(1);
2230 }
2231 if (!(tmp & EEPROM_ADDR_COMPLETE))
2232 return -EBUSY;
2233
62cedd11
MC		 2234 tmp = tr32(GRC_EEPROM_DATA);
2235
2236 /*
2237 * The data will always be opposite the native endian
2238 * format. Perform a blind byteswap to compensate.
2239 */
2240 *val = swab32(tmp);
2241
ffbcfed4
MC		 2242 return 0;
2243}
2244
2245#define NVRAM_CMD_TIMEOUT 10000
2246
2247static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2248{
2249 int i;
2250
2251 tw32(NVRAM_CMD, nvram_cmd);
2252 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2253 udelay(10);
2254 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2255 udelay(10);
2256 break;
2257 }
2258 }
2259
2260 if (i == NVRAM_CMD_TIMEOUT)
2261 return -EBUSY;
2262
2263 return 0;
2264}
2265
2266static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2267{
2268 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2269 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2270 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2271 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2272 (tp->nvram_jedecnum == JEDEC_ATMEL))
2273
2274 addr = ((addr / tp->nvram_pagesize) <<
2275 ATMEL_AT45DB0X1B_PAGE_POS) +
2276 (addr % tp->nvram_pagesize);
2277
2278 return addr;
2279}
2280
2281static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2282{
2283 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2284 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2285 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2286 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2287 (tp->nvram_jedecnum == JEDEC_ATMEL))
2288
2289 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2290 tp->nvram_pagesize) +
2291 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2292
2293 return addr;
2294}
2295
e4f34110
MC		 2296/* NOTE: Data read in from NVRAM is byteswapped according to
2297 * the byteswapping settings for all other register accesses.
2298 * tg3 devices are BE devices, so on a BE machine, the data
2299 * returned will be exactly as it is seen in NVRAM. On a LE
2300 * machine, the 32-bit value will be byteswapped.
2301 */
ffbcfed4
MC		 2302static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2303{
2304 int ret;
2305
2306 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2307 return tg3_nvram_read_using_eeprom(tp, offset, val);
2308
2309 offset = tg3_nvram_phys_addr(tp, offset);
2310
2311 if (offset > NVRAM_ADDR_MSK)
2312 return -EINVAL;
2313
2314 ret = tg3_nvram_lock(tp);
2315 if (ret)
2316 return ret;
2317
2318 tg3_enable_nvram_access(tp);
2319
2320 tw32(NVRAM_ADDR, offset);
2321 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2322 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2323
2324 if (ret == 0)
e4f34110 2325 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2326
2327 tg3_disable_nvram_access(tp);
2328
2329 tg3_nvram_unlock(tp);
2330
2331 return ret;
2332}
2333
a9dc529d
MC		 2334/* Ensures NVRAM data is in bytestream format. */
2335static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2336{
2337 u32 v;
a9dc529d 2338 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2339 if (!res)
a9dc529d 2340 *val = cpu_to_be32(v);
ffbcfed4
MC		 2341 return res;
2342}
2343
3f007891
MC		 2344/* tp->lock is held. */
2345static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2346{
2347 u32 addr_high, addr_low;
2348 int i;
2349
2350 addr_high = ((tp->dev->dev_addr[0] << 8) |
2351 tp->dev->dev_addr[1]);
2352 addr_low = ((tp->dev->dev_addr[2] << 24) |
2353 (tp->dev->dev_addr[3] << 16) |
2354 (tp->dev->dev_addr[4] << 8) |
2355 (tp->dev->dev_addr[5] << 0));
2356 for (i = 0; i < 4; i++) {
2357 if (i == 1 && skip_mac_1)
2358 continue;
2359 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2360 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2361 }
2362
2363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2365 for (i = 0; i < 12; i++) {
2366 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2367 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2368 }
2369 }
2370
2371 addr_high = (tp->dev->dev_addr[0] +
2372 tp->dev->dev_addr[1] +
2373 tp->dev->dev_addr[2] +
2374 tp->dev->dev_addr[3] +
2375 tp->dev->dev_addr[4] +
2376 tp->dev->dev_addr[5]) &
2377 TX_BACKOFF_SEED_MASK;
2378 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2379}
2380
bc1c7567 2381static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2382{
2383 u32 misc_host_ctrl;
0a459aac 2384 bool device_should_wake, do_low_power;
1da177e4
LT		 2385
2386 /* Make sure register accesses (indirect or otherwise)
2387 * will function correctly.
2388 */
2389 pci_write_config_dword(tp->pdev,
2390 TG3PCI_MISC_HOST_CTRL,
2391 tp->misc_host_ctrl);
2392
1da177e4 2393 switch (state) {
bc1c7567 2394 case PCI_D0:
12dac075
RW		 2395 pci_enable_wake(tp->pdev, state, false);
2396 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2397
9d26e213
MC		 2398 /* Switch out of Vaux if it is a NIC */
2399 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2400 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2401
2402 return 0;
2403
bc1c7567 2404 case PCI_D1:
bc1c7567 2405 case PCI_D2:
bc1c7567 2406 case PCI_D3hot:
1da177e4
LT		 2407 break;
2408
2409 default:
12dac075
RW		 2410 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2411 tp->dev->name, state);
1da177e4 2412 return -EINVAL;
855e1111 2413 }
5e7dfd0f
MC		 2414
2415 /* Restore the CLKREQ setting. */
2416 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2417 u16 lnkctl;
2418
2419 pci_read_config_word(tp->pdev,
2420 tp->pcie_cap + PCI_EXP_LNKCTL,
2421 &lnkctl);
2422 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2423 pci_write_config_word(tp->pdev,
2424 tp->pcie_cap + PCI_EXP_LNKCTL,
2425 lnkctl);
2426 }
2427
1da177e4
LT		 2428 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2429 tw32(TG3PCI_MISC_HOST_CTRL,
2430 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2431
05ac4cb7
MC		 2432 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2433 device_may_wakeup(&tp->pdev->dev) &&
2434 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2435
dd477003 2436 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2437 do_low_power = false;
b02fd9e3
MC		 2438 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2439 !tp->link_config.phy_is_low_power) {
2440 struct phy_device *phydev;
0a459aac 2441 u32 phyid, advertising;
b02fd9e3 2442
298cf9be 2443 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2444
2445 tp->link_config.phy_is_low_power = 1;
2446
2447 tp->link_config.orig_speed = phydev->speed;
2448 tp->link_config.orig_duplex = phydev->duplex;
2449 tp->link_config.orig_autoneg = phydev->autoneg;
2450 tp->link_config.orig_advertising = phydev->advertising;
2451
2452 advertising = ADVERTISED_TP |
2453 ADVERTISED_Pause |
2454 ADVERTISED_Autoneg |
2455 ADVERTISED_10baseT_Half;
2456
2457 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2458 device_should_wake) {
b02fd9e3
MC		 2459 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2460 advertising |=
2461 ADVERTISED_100baseT_Half |
2462 ADVERTISED_100baseT_Full |
2463 ADVERTISED_10baseT_Full;
2464 else
2465 advertising |= ADVERTISED_10baseT_Full;
2466 }
2467
2468 phydev->advertising = advertising;
2469
2470 phy_start_aneg(phydev);
0a459aac
MC		 2471
2472 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2473 if (phyid != TG3_PHY_ID_BCMAC131) {
2474 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2475 if (phyid == TG3_PHY_OUI_1 ||
2476 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2477 phyid == TG3_PHY_OUI_3)
2478 do_low_power = true;
2479 }
b02fd9e3 2480 }
dd477003 2481 } else {
2023276e 2482 do_low_power = true;
0a459aac 2483
dd477003
MC		 2484 if (tp->link_config.phy_is_low_power == 0) {
2485 tp->link_config.phy_is_low_power = 1;
2486 tp->link_config.orig_speed = tp->link_config.speed;
2487 tp->link_config.orig_duplex = tp->link_config.duplex;
2488 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2489 }
1da177e4 2490
dd477003
MC		 2491 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2492 tp->link_config.speed = SPEED_10;
2493 tp->link_config.duplex = DUPLEX_HALF;
2494 tp->link_config.autoneg = AUTONEG_ENABLE;
2495 tg3_setup_phy(tp, 0);
2496 }
1da177e4
LT		 2497 }
2498
b5d3772c
MC		 2499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2500 u32 val;
2501
2502 val = tr32(GRC_VCPU_EXT_CTRL);
2503 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2504 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2505 int i;
2506 u32 val;
2507
2508 for (i = 0; i < 200; i++) {
2509 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2510 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2511 break;
2512 msleep(1);
2513 }
2514 }
a85feb8c
GZ		 2515 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2516 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2517 WOL_DRV_STATE_SHUTDOWN |
2518 WOL_DRV_WOL |
2519 WOL_SET_MAGIC_PKT);
6921d201 2520
05ac4cb7 2521 if (device_should_wake) {
1da177e4
LT		 2522 u32 mac_mode;
2523
2524 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2525 if (do_low_power) {
dd477003
MC		 2526 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2527 udelay(40);
2528 }
1da177e4 2529
3f7045c1
MC		 2530 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2531 mac_mode = MAC_MODE_PORT_MODE_GMII;
2532 else
2533 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2534
e8f3f6ca
MC		 2535 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2536 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2537 ASIC_REV_5700) {
2538 u32 speed = (tp->tg3_flags &
2539 TG3_FLAG_WOL_SPEED_100MB) ?
2540 SPEED_100 : SPEED_10;
2541 if (tg3_5700_link_polarity(tp, speed))
2542 mac_mode |= MAC_MODE_LINK_POLARITY;
2543 else
2544 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2545 }
1da177e4
LT		 2546 } else {
2547 mac_mode = MAC_MODE_PORT_MODE_TBI;
2548 }
2549
cbf46853 2550 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2551 tw32(MAC_LED_CTRL, tp->led_ctrl);
2552
05ac4cb7
MC		 2553 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2554 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2555 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2556 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2557 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2558 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2559
3bda1258
MC		 2560 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2561 mac_mode |= tp->mac_mode &
2562 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2563 if (mac_mode & MAC_MODE_APE_TX_EN)
2564 mac_mode |= MAC_MODE_TDE_ENABLE;
2565 }
2566
1da177e4
LT		 2567 tw32_f(MAC_MODE, mac_mode);
2568 udelay(100);
2569
2570 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2571 udelay(10);
2572 }
2573
2574 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2577 u32 base_val;
2578
2579 base_val = tp->pci_clock_ctrl;
2580 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2581 CLOCK_CTRL_TXCLK_DISABLE);
2582
b401e9e2
MC		 2583 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2584 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2585 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2586 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2587 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2588 /* do nothing */
85e94ced 2589 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2590 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2591 u32 newbits1, newbits2;
2592
2593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2595 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2596 CLOCK_CTRL_TXCLK_DISABLE |
2597 CLOCK_CTRL_ALTCLK);
2598 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2599 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2600 newbits1 = CLOCK_CTRL_625_CORE;
2601 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2602 } else {
2603 newbits1 = CLOCK_CTRL_ALTCLK;
2604 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2605 }
2606
b401e9e2
MC		 2607 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2608 40);
1da177e4 2609
b401e9e2
MC		 2610 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2611 40);
1da177e4
LT		 2612
2613 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2614 u32 newbits3;
2615
2616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2618 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2619 CLOCK_CTRL_TXCLK_DISABLE |
2620 CLOCK_CTRL_44MHZ_CORE);
2621 } else {
2622 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2623 }
2624
b401e9e2
MC		 2625 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2626 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2627 }
2628 }
2629
05ac4cb7 2630 if (!(device_should_wake) &&
22435849 2631 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2632 tg3_power_down_phy(tp, do_low_power);
6921d201 2633
1da177e4
LT		 2634 tg3_frob_aux_power(tp);
2635
2636 /* Workaround for unstable PLL clock */
2637 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2638 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2639 u32 val = tr32(0x7d00);
2640
2641 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2642 tw32(0x7d00, val);
6921d201 2643 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2644 int err;
2645
2646 err = tg3_nvram_lock(tp);
1da177e4 2647 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2648 if (!err)
2649 tg3_nvram_unlock(tp);
6921d201 2650 }
1da177e4
LT		 2651 }
2652
bbadf503
MC		 2653 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2654
05ac4cb7 2655 if (device_should_wake)
12dac075
RW		 2656 pci_enable_wake(tp->pdev, state, true);
2657
1da177e4 2658 /* Finally, set the new power state. */
12dac075 2659 pci_set_power_state(tp->pdev, state);
1da177e4 2660
1da177e4
LT		 2661 return 0;
2662}
2663
1da177e4
LT		 2664static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2665{
2666 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2667 case MII_TG3_AUX_STAT_10HALF:
2668 *speed = SPEED_10;
2669 *duplex = DUPLEX_HALF;
2670 break;
2671
2672 case MII_TG3_AUX_STAT_10FULL:
2673 *speed = SPEED_10;
2674 *duplex = DUPLEX_FULL;
2675 break;
2676
2677 case MII_TG3_AUX_STAT_100HALF:
2678 *speed = SPEED_100;
2679 *duplex = DUPLEX_HALF;
2680 break;
2681
2682 case MII_TG3_AUX_STAT_100FULL:
2683 *speed = SPEED_100;
2684 *duplex = DUPLEX_FULL;
2685 break;
2686
2687 case MII_TG3_AUX_STAT_1000HALF:
2688 *speed = SPEED_1000;
2689 *duplex = DUPLEX_HALF;
2690 break;
2691
2692 case MII_TG3_AUX_STAT_1000FULL:
2693 *speed = SPEED_1000;
2694 *duplex = DUPLEX_FULL;
2695 break;
2696
2697 default:
7f97a4bd 2698 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2699 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2700 SPEED_10;
2701 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2702 DUPLEX_HALF;
2703 break;
2704 }
1da177e4
LT		 2705 *speed = SPEED_INVALID;
2706 *duplex = DUPLEX_INVALID;
2707 break;
855e1111 2708 }
1da177e4
LT		 2709}
2710
2711static void tg3_phy_copper_begin(struct tg3 *tp)
2712{
2713 u32 new_adv;
2714 int i;
2715
2716 if (tp->link_config.phy_is_low_power) {
2717 /* Entering low power mode. Disable gigabit and
2718 * 100baseT advertisements.
2719 */
2720 tg3_writephy(tp, MII_TG3_CTRL, 0);
2721
2722 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2723 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2724 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2725 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2726
2727 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2728 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2729 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2730 tp->link_config.advertising &=
2731 ~(ADVERTISED_1000baseT_Half |
2732 ADVERTISED_1000baseT_Full);
2733
ba4d07a8 2734 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2735 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2736 new_adv |= ADVERTISE_10HALF;
2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2738 new_adv |= ADVERTISE_10FULL;
2739 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2740 new_adv |= ADVERTISE_100HALF;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2742 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2743
2744 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2745
1da177e4
LT		 2746 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747
2748 if (tp->link_config.advertising &
2749 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2750 new_adv = 0;
2751 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2752 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2755 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2756 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2757 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2758 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2759 MII_TG3_CTRL_ENABLE_AS_MASTER);
2760 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2761 } else {
2762 tg3_writephy(tp, MII_TG3_CTRL, 0);
2763 }
2764 } else {
ba4d07a8
MC		 2765 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2766 new_adv |= ADVERTISE_CSMA;
2767
1da177e4
LT		 2768 /* Asking for a specific link mode. */
2769 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2770 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2771
2772 if (tp->link_config.duplex == DUPLEX_FULL)
2773 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2774 else
2775 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2776 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2777 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2778 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2779 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2780 } else {
1da177e4
LT		 2781 if (tp->link_config.speed == SPEED_100) {
2782 if (tp->link_config.duplex == DUPLEX_FULL)
2783 new_adv |= ADVERTISE_100FULL;
2784 else
2785 new_adv |= ADVERTISE_100HALF;
2786 } else {
2787 if (tp->link_config.duplex == DUPLEX_FULL)
2788 new_adv |= ADVERTISE_10FULL;
2789 else
2790 new_adv |= ADVERTISE_10HALF;
2791 }
2792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2793
2794 new_adv = 0;
1da177e4 2795 }
ba4d07a8
MC		 2796
2797 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2798 }
2799
2800 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2801 tp->link_config.speed != SPEED_INVALID) {
2802 u32 bmcr, orig_bmcr;
2803
2804 tp->link_config.active_speed = tp->link_config.speed;
2805 tp->link_config.active_duplex = tp->link_config.duplex;
2806
2807 bmcr = 0;
2808 switch (tp->link_config.speed) {
2809 default:
2810 case SPEED_10:
2811 break;
2812
2813 case SPEED_100:
2814 bmcr |= BMCR_SPEED100;
2815 break;
2816
2817 case SPEED_1000:
2818 bmcr |= TG3_BMCR_SPEED1000;
2819 break;
855e1111 2820 }
1da177e4
LT		 2821
2822 if (tp->link_config.duplex == DUPLEX_FULL)
2823 bmcr |= BMCR_FULLDPLX;
2824
2825 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2826 (bmcr != orig_bmcr)) {
2827 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2828 for (i = 0; i < 1500; i++) {
2829 u32 tmp;
2830
2831 udelay(10);
2832 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2833 tg3_readphy(tp, MII_BMSR, &tmp))
2834 continue;
2835 if (!(tmp & BMSR_LSTATUS)) {
2836 udelay(40);
2837 break;
2838 }
2839 }
2840 tg3_writephy(tp, MII_BMCR, bmcr);
2841 udelay(40);
2842 }
2843 } else {
2844 tg3_writephy(tp, MII_BMCR,
2845 BMCR_ANENABLE | BMCR_ANRESTART);
2846 }
2847}
2848
2849static int tg3_init_5401phy_dsp(struct tg3 *tp)
2850{
2851 int err;
2852
2853 /* Turn off tap power management. */
2854 /* Set Extended packet length bit */
2855 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2856
2857 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2858 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2859
2860 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2861 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2862
2863 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2864 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2865
2866 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2867 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2868
2869 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2870 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2871
2872 udelay(40);
2873
2874 return err;
2875}
2876
3600d918 2877static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2878{
3600d918
MC		 2879 u32 adv_reg, all_mask = 0;
2880
2881 if (mask & ADVERTISED_10baseT_Half)
2882 all_mask |= ADVERTISE_10HALF;
2883 if (mask & ADVERTISED_10baseT_Full)
2884 all_mask |= ADVERTISE_10FULL;
2885 if (mask & ADVERTISED_100baseT_Half)
2886 all_mask |= ADVERTISE_100HALF;
2887 if (mask & ADVERTISED_100baseT_Full)
2888 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2889
2890 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2891 return 0;
2892
1da177e4
LT		 2893 if ((adv_reg & all_mask) != all_mask)
2894 return 0;
2895 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2896 u32 tg3_ctrl;
2897
3600d918
MC		 2898 all_mask = 0;
2899 if (mask & ADVERTISED_1000baseT_Half)
2900 all_mask |= ADVERTISE_1000HALF;
2901 if (mask & ADVERTISED_1000baseT_Full)
2902 all_mask |= ADVERTISE_1000FULL;
2903
1da177e4
LT		 2904 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2905 return 0;
2906
1da177e4
LT		 2907 if ((tg3_ctrl & all_mask) != all_mask)
2908 return 0;
2909 }
2910 return 1;
2911}
2912
ef167e27
MC		 2913static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2914{
2915 u32 curadv, reqadv;
2916
2917 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2918 return 1;
2919
2920 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2921 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2922
2923 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2924 if (curadv != reqadv)
2925 return 0;
2926
2927 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2928 tg3_readphy(tp, MII_LPA, rmtadv);
2929 } else {
2930 /* Reprogram the advertisement register, even if it
2931 * does not affect the current link. If the link
2932 * gets renegotiated in the future, we can save an
2933 * additional renegotiation cycle by advertising
2934 * it correctly in the first place.
2935 */
2936 if (curadv != reqadv) {
2937 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2938 ADVERTISE_PAUSE_ASYM);
2939 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2940 }
2941 }
2942
2943 return 1;
2944}
2945
1da177e4
LT		 2946static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2947{
2948 int current_link_up;
2949 u32 bmsr, dummy;
ef167e27 2950 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2951 u16 current_speed;
2952 u8 current_duplex;
2953 int i, err;
2954
2955 tw32(MAC_EVENT, 0);
2956
2957 tw32_f(MAC_STATUS,
2958 (MAC_STATUS_SYNC_CHANGED |
2959 MAC_STATUS_CFG_CHANGED |
2960 MAC_STATUS_MI_COMPLETION |
2961 MAC_STATUS_LNKSTATE_CHANGED));
2962 udelay(40);
2963
8ef21428
MC		 2964 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2965 tw32_f(MAC_MI_MODE,
2966 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2967 udelay(80);
2968 }
1da177e4
LT		 2969
2970 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2971
2972 /* Some third-party PHYs need to be reset on link going
2973 * down.
2974 */
2975 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2978 netif_carrier_ok(tp->dev)) {
2979 tg3_readphy(tp, MII_BMSR, &bmsr);
2980 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2981 !(bmsr & BMSR_LSTATUS))
2982 force_reset = 1;
2983 }
2984 if (force_reset)
2985 tg3_phy_reset(tp);
2986
2987 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2988 tg3_readphy(tp, MII_BMSR, &bmsr);
2989 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2990 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2991 bmsr = 0;
2992
2993 if (!(bmsr & BMSR_LSTATUS)) {
2994 err = tg3_init_5401phy_dsp(tp);
2995 if (err)
2996 return err;
2997
2998 tg3_readphy(tp, MII_BMSR, &bmsr);
2999 for (i = 0; i < 1000; i++) {
3000 udelay(10);
3001 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3002 (bmsr & BMSR_LSTATUS)) {
3003 udelay(40);
3004 break;
3005 }
3006 }
3007
3008 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3009 !(bmsr & BMSR_LSTATUS) &&
3010 tp->link_config.active_speed == SPEED_1000) {
3011 err = tg3_phy_reset(tp);
3012 if (!err)
3013 err = tg3_init_5401phy_dsp(tp);
3014 if (err)
3015 return err;
3016 }
3017 }
3018 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3019 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3020 /* 5701 {A0,B0} CRC bug workaround */
3021 tg3_writephy(tp, 0x15, 0x0a75);
3022 tg3_writephy(tp, 0x1c, 0x8c68);
3023 tg3_writephy(tp, 0x1c, 0x8d68);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 }
3026
3027 /* Clear pending interrupts... */
3028 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3029 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3030
3031 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3032 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3033 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3034 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3035
3036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3038 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3039 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3040 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3041 else
3042 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3043 }
3044
3045 current_link_up = 0;
3046 current_speed = SPEED_INVALID;
3047 current_duplex = DUPLEX_INVALID;
3048
3049 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3050 u32 val;
3051
3052 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3053 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3054 if (!(val & (1 << 10))) {
3055 val |= (1 << 10);
3056 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3057 goto relink;
3058 }
3059 }
3060
3061 bmsr = 0;
3062 for (i = 0; i < 100; i++) {
3063 tg3_readphy(tp, MII_BMSR, &bmsr);
3064 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3065 (bmsr & BMSR_LSTATUS))
3066 break;
3067 udelay(40);
3068 }
3069
3070 if (bmsr & BMSR_LSTATUS) {
3071 u32 aux_stat, bmcr;
3072
3073 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3074 for (i = 0; i < 2000; i++) {
3075 udelay(10);
3076 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3077 aux_stat)
3078 break;
3079 }
3080
3081 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3082 &current_speed,
3083 &current_duplex);
3084
3085 bmcr = 0;
3086 for (i = 0; i < 200; i++) {
3087 tg3_readphy(tp, MII_BMCR, &bmcr);
3088 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3089 continue;
3090 if (bmcr && bmcr != 0x7fff)
3091 break;
3092 udelay(10);
3093 }
3094
ef167e27
MC		 3095 lcl_adv = 0;
3096 rmt_adv = 0;
1da177e4 3097
ef167e27
MC		 3098 tp->link_config.active_speed = current_speed;
3099 tp->link_config.active_duplex = current_duplex;
3100
3101 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3102 if ((bmcr & BMCR_ANENABLE) &&
3103 tg3_copper_is_advertising_all(tp,
3104 tp->link_config.advertising)) {
3105 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3106 &rmt_adv))
3107 current_link_up = 1;
1da177e4
LT		 3108 }
3109 } else {
3110 if (!(bmcr & BMCR_ANENABLE) &&
3111 tp->link_config.speed == current_speed &&
ef167e27
MC		 3112 tp->link_config.duplex == current_duplex &&
3113 tp->link_config.flowctrl ==
3114 tp->link_config.active_flowctrl) {
1da177e4 3115 current_link_up = 1;
1da177e4
LT		 3116 }
3117 }
3118
ef167e27
MC		 3119 if (current_link_up == 1 &&
3120 tp->link_config.active_duplex == DUPLEX_FULL)
3121 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3122 }
3123
1da177e4 3124relink:
6921d201 3125 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3126 u32 tmp;
3127
3128 tg3_phy_copper_begin(tp);
3129
3130 tg3_readphy(tp, MII_BMSR, &tmp);
3131 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3132 (tmp & BMSR_LSTATUS))
3133 current_link_up = 1;
3134 }
3135
3136 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3137 if (current_link_up == 1) {
3138 if (tp->link_config.active_speed == SPEED_100 ||
3139 tp->link_config.active_speed == SPEED_10)
3140 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3141 else
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3143 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3145 else
1da177e4
LT		 3146 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3147
3148 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3149 if (tp->link_config.active_duplex == DUPLEX_HALF)
3150 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3151
1da177e4 3152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3153 if (current_link_up == 1 &&
3154 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3155 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3156 else
3157 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3158 }
3159
3160 /* ??? Without this setting Netgear GA302T PHY does not
3161 * ??? send/receive packets...
3162 */
3163 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3164 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3165 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3166 tw32_f(MAC_MI_MODE, tp->mi_mode);
3167 udelay(80);
3168 }
3169
3170 tw32_f(MAC_MODE, tp->mac_mode);
3171 udelay(40);
3172
3173 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3174 /* Polled via timer. */
3175 tw32_f(MAC_EVENT, 0);
3176 } else {
3177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3178 }
3179 udelay(40);
3180
3181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3182 current_link_up == 1 &&
3183 tp->link_config.active_speed == SPEED_1000 &&
3184 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3185 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3186 udelay(120);
3187 tw32_f(MAC_STATUS,
3188 (MAC_STATUS_SYNC_CHANGED |
3189 MAC_STATUS_CFG_CHANGED));
3190 udelay(40);
3191 tg3_write_mem(tp,
3192 NIC_SRAM_FIRMWARE_MBOX,
3193 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3194 }
3195
5e7dfd0f
MC		 3196 /* Prevent send BD corruption. */
3197 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3198 u16 oldlnkctl, newlnkctl;
3199
3200 pci_read_config_word(tp->pdev,
3201 tp->pcie_cap + PCI_EXP_LNKCTL,
3202 &oldlnkctl);
3203 if (tp->link_config.active_speed == SPEED_100 ||
3204 tp->link_config.active_speed == SPEED_10)
3205 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3206 else
3207 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3208 if (newlnkctl != oldlnkctl)
3209 pci_write_config_word(tp->pdev,
3210 tp->pcie_cap + PCI_EXP_LNKCTL,
3211 newlnkctl);
255ca311
MC		 3212 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3213 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3214 if (tp->link_config.active_speed == SPEED_100 ||
3215 tp->link_config.active_speed == SPEED_10)
3216 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3217 else
3218 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 if (newreg != oldreg)
3220 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3221 }
3222
1da177e4
LT		 3223 if (current_link_up != netif_carrier_ok(tp->dev)) {
3224 if (current_link_up)
3225 netif_carrier_on(tp->dev);
3226 else
3227 netif_carrier_off(tp->dev);
3228 tg3_link_report(tp);
3229 }
3230
3231 return 0;
3232}
3233
3234struct tg3_fiber_aneginfo {
3235 int state;
3236#define ANEG_STATE_UNKNOWN 0
3237#define ANEG_STATE_AN_ENABLE 1
3238#define ANEG_STATE_RESTART_INIT 2
3239#define ANEG_STATE_RESTART 3
3240#define ANEG_STATE_DISABLE_LINK_OK 4
3241#define ANEG_STATE_ABILITY_DETECT_INIT 5
3242#define ANEG_STATE_ABILITY_DETECT 6
3243#define ANEG_STATE_ACK_DETECT_INIT 7
3244#define ANEG_STATE_ACK_DETECT 8
3245#define ANEG_STATE_COMPLETE_ACK_INIT 9
3246#define ANEG_STATE_COMPLETE_ACK 10
3247#define ANEG_STATE_IDLE_DETECT_INIT 11
3248#define ANEG_STATE_IDLE_DETECT 12
3249#define ANEG_STATE_LINK_OK 13
3250#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3251#define ANEG_STATE_NEXT_PAGE_WAIT 15
3252
3253 u32 flags;
3254#define MR_AN_ENABLE 0x00000001
3255#define MR_RESTART_AN 0x00000002
3256#define MR_AN_COMPLETE 0x00000004
3257#define MR_PAGE_RX 0x00000008
3258#define MR_NP_LOADED 0x00000010
3259#define MR_TOGGLE_TX 0x00000020
3260#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3261#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3262#define MR_LP_ADV_SYM_PAUSE 0x00000100
3263#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3264#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3265#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3266#define MR_LP_ADV_NEXT_PAGE 0x00001000
3267#define MR_TOGGLE_RX 0x00002000
3268#define MR_NP_RX 0x00004000
3269
3270#define MR_LINK_OK 0x80000000
3271
3272 unsigned long link_time, cur_time;
3273
3274 u32 ability_match_cfg;
3275 int ability_match_count;
3276
3277 char ability_match, idle_match, ack_match;
3278
3279 u32 txconfig, rxconfig;
3280#define ANEG_CFG_NP 0x00000080
3281#define ANEG_CFG_ACK 0x00000040
3282#define ANEG_CFG_RF2 0x00000020
3283#define ANEG_CFG_RF1 0x00000010
3284#define ANEG_CFG_PS2 0x00000001
3285#define ANEG_CFG_PS1 0x00008000
3286#define ANEG_CFG_HD 0x00004000
3287#define ANEG_CFG_FD 0x00002000
3288#define ANEG_CFG_INVAL 0x00001f06
3289
3290};
3291#define ANEG_OK 0
3292#define ANEG_DONE 1
3293#define ANEG_TIMER_ENAB 2
3294#define ANEG_FAILED -1
3295
3296#define ANEG_STATE_SETTLE_TIME 10000
3297
3298static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3299 struct tg3_fiber_aneginfo *ap)
3300{
5be73b47 3301 u16 flowctrl;
1da177e4
LT		 3302 unsigned long delta;
3303 u32 rx_cfg_reg;
3304 int ret;
3305
3306 if (ap->state == ANEG_STATE_UNKNOWN) {
3307 ap->rxconfig = 0;
3308 ap->link_time = 0;
3309 ap->cur_time = 0;
3310 ap->ability_match_cfg = 0;
3311 ap->ability_match_count = 0;
3312 ap->ability_match = 0;
3313 ap->idle_match = 0;
3314 ap->ack_match = 0;
3315 }
3316 ap->cur_time++;
3317
3318 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3319 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3320
3321 if (rx_cfg_reg != ap->ability_match_cfg) {
3322 ap->ability_match_cfg = rx_cfg_reg;
3323 ap->ability_match = 0;
3324 ap->ability_match_count = 0;
3325 } else {
3326 if (++ap->ability_match_count > 1) {
3327 ap->ability_match = 1;
3328 ap->ability_match_cfg = rx_cfg_reg;
3329 }
3330 }
3331 if (rx_cfg_reg & ANEG_CFG_ACK)
3332 ap->ack_match = 1;
3333 else
3334 ap->ack_match = 0;
3335
3336 ap->idle_match = 0;
3337 } else {
3338 ap->idle_match = 1;
3339 ap->ability_match_cfg = 0;
3340 ap->ability_match_count = 0;
3341 ap->ability_match = 0;
3342 ap->ack_match = 0;
3343
3344 rx_cfg_reg = 0;
3345 }
3346
3347 ap->rxconfig = rx_cfg_reg;
3348 ret = ANEG_OK;
3349
3350 switch(ap->state) {
3351 case ANEG_STATE_UNKNOWN:
3352 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3353 ap->state = ANEG_STATE_AN_ENABLE;
3354
3355 /* fallthru */
3356 case ANEG_STATE_AN_ENABLE:
3357 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3358 if (ap->flags & MR_AN_ENABLE) {
3359 ap->link_time = 0;
3360 ap->cur_time = 0;
3361 ap->ability_match_cfg = 0;
3362 ap->ability_match_count = 0;
3363 ap->ability_match = 0;
3364 ap->idle_match = 0;
3365 ap->ack_match = 0;
3366
3367 ap->state = ANEG_STATE_RESTART_INIT;
3368 } else {
3369 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3370 }
3371 break;
3372
3373 case ANEG_STATE_RESTART_INIT:
3374 ap->link_time = ap->cur_time;
3375 ap->flags &= ~(MR_NP_LOADED);
3376 ap->txconfig = 0;
3377 tw32(MAC_TX_AUTO_NEG, 0);
3378 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3379 tw32_f(MAC_MODE, tp->mac_mode);
3380 udelay(40);
3381
3382 ret = ANEG_TIMER_ENAB;
3383 ap->state = ANEG_STATE_RESTART;
3384
3385 /* fallthru */
3386 case ANEG_STATE_RESTART:
3387 delta = ap->cur_time - ap->link_time;
3388 if (delta > ANEG_STATE_SETTLE_TIME) {
3389 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3390 } else {
3391 ret = ANEG_TIMER_ENAB;
3392 }
3393 break;
3394
3395 case ANEG_STATE_DISABLE_LINK_OK:
3396 ret = ANEG_DONE;
3397 break;
3398
3399 case ANEG_STATE_ABILITY_DETECT_INIT:
3400 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3401 ap->txconfig = ANEG_CFG_FD;
3402 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3403 if (flowctrl & ADVERTISE_1000XPAUSE)
3404 ap->txconfig |= ANEG_CFG_PS1;
3405 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3406 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3407 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3408 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3409 tw32_f(MAC_MODE, tp->mac_mode);
3410 udelay(40);
3411
3412 ap->state = ANEG_STATE_ABILITY_DETECT;
3413 break;
3414
3415 case ANEG_STATE_ABILITY_DETECT:
3416 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3417 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3418 }
3419 break;
3420
3421 case ANEG_STATE_ACK_DETECT_INIT:
3422 ap->txconfig |= ANEG_CFG_ACK;
3423 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3424 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3425 tw32_f(MAC_MODE, tp->mac_mode);
3426 udelay(40);
3427
3428 ap->state = ANEG_STATE_ACK_DETECT;
3429
3430 /* fallthru */
3431 case ANEG_STATE_ACK_DETECT:
3432 if (ap->ack_match != 0) {
3433 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3434 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3435 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3436 } else {
3437 ap->state = ANEG_STATE_AN_ENABLE;
3438 }
3439 } else if (ap->ability_match != 0 &&
3440 ap->rxconfig == 0) {
3441 ap->state = ANEG_STATE_AN_ENABLE;
3442 }
3443 break;
3444
3445 case ANEG_STATE_COMPLETE_ACK_INIT:
3446 if (ap->rxconfig & ANEG_CFG_INVAL) {
3447 ret = ANEG_FAILED;
3448 break;
3449 }
3450 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3451 MR_LP_ADV_HALF_DUPLEX |
3452 MR_LP_ADV_SYM_PAUSE |
3453 MR_LP_ADV_ASYM_PAUSE |
3454 MR_LP_ADV_REMOTE_FAULT1 |
3455 MR_LP_ADV_REMOTE_FAULT2 |
3456 MR_LP_ADV_NEXT_PAGE |
3457 MR_TOGGLE_RX |
3458 MR_NP_RX);
3459 if (ap->rxconfig & ANEG_CFG_FD)
3460 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3461 if (ap->rxconfig & ANEG_CFG_HD)
3462 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_PS1)
3464 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3465 if (ap->rxconfig & ANEG_CFG_PS2)
3466 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_RF1)
3468 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3469 if (ap->rxconfig & ANEG_CFG_RF2)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3471 if (ap->rxconfig & ANEG_CFG_NP)
3472 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3473
3474 ap->link_time = ap->cur_time;
3475
3476 ap->flags ^= (MR_TOGGLE_TX);
3477 if (ap->rxconfig & 0x0008)
3478 ap->flags |= MR_TOGGLE_RX;
3479 if (ap->rxconfig & ANEG_CFG_NP)
3480 ap->flags |= MR_NP_RX;
3481 ap->flags |= MR_PAGE_RX;
3482
3483 ap->state = ANEG_STATE_COMPLETE_ACK;
3484 ret = ANEG_TIMER_ENAB;
3485 break;
3486
3487 case ANEG_STATE_COMPLETE_ACK:
3488 if (ap->ability_match != 0 &&
3489 ap->rxconfig == 0) {
3490 ap->state = ANEG_STATE_AN_ENABLE;
3491 break;
3492 }
3493 delta = ap->cur_time - ap->link_time;
3494 if (delta > ANEG_STATE_SETTLE_TIME) {
3495 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3496 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3497 } else {
3498 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3499 !(ap->flags & MR_NP_RX)) {
3500 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3501 } else {
3502 ret = ANEG_FAILED;
3503 }
3504 }
3505 }
3506 break;
3507
3508 case ANEG_STATE_IDLE_DETECT_INIT:
3509 ap->link_time = ap->cur_time;
3510 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3511 tw32_f(MAC_MODE, tp->mac_mode);
3512 udelay(40);
3513
3514 ap->state = ANEG_STATE_IDLE_DETECT;
3515 ret = ANEG_TIMER_ENAB;
3516 break;
3517
3518 case ANEG_STATE_IDLE_DETECT:
3519 if (ap->ability_match != 0 &&
3520 ap->rxconfig == 0) {
3521 ap->state = ANEG_STATE_AN_ENABLE;
3522 break;
3523 }
3524 delta = ap->cur_time - ap->link_time;
3525 if (delta > ANEG_STATE_SETTLE_TIME) {
3526 /* XXX another gem from the Broadcom driver :( */
3527 ap->state = ANEG_STATE_LINK_OK;
3528 }
3529 break;
3530
3531 case ANEG_STATE_LINK_OK:
3532 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3533 ret = ANEG_DONE;
3534 break;
3535
3536 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3537 /* ??? unimplemented */
3538 break;
3539
3540 case ANEG_STATE_NEXT_PAGE_WAIT:
3541 /* ??? unimplemented */
3542 break;
3543
3544 default:
3545 ret = ANEG_FAILED;
3546 break;
855e1111 3547 }
1da177e4
LT		 3548
3549 return ret;
3550}
3551
5be73b47 3552static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3553{
3554 int res = 0;
3555 struct tg3_fiber_aneginfo aninfo;
3556 int status = ANEG_FAILED;
3557 unsigned int tick;
3558 u32 tmp;
3559
3560 tw32_f(MAC_TX_AUTO_NEG, 0);
3561
3562 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3563 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3564 udelay(40);
3565
3566 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3567 udelay(40);
3568
3569 memset(&aninfo, 0, sizeof(aninfo));
3570 aninfo.flags |= MR_AN_ENABLE;
3571 aninfo.state = ANEG_STATE_UNKNOWN;
3572 aninfo.cur_time = 0;
3573 tick = 0;
3574 while (++tick < 195000) {
3575 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3576 if (status == ANEG_DONE || status == ANEG_FAILED)
3577 break;
3578
3579 udelay(1);
3580 }
3581
3582 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3583 tw32_f(MAC_MODE, tp->mac_mode);
3584 udelay(40);
3585
5be73b47
MC		 3586 *txflags = aninfo.txconfig;
3587 *rxflags = aninfo.flags;
1da177e4
LT		 3588
3589 if (status == ANEG_DONE &&
3590 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3591 MR_LP_ADV_FULL_DUPLEX)))
3592 res = 1;
3593
3594 return res;
3595}
3596
3597static void tg3_init_bcm8002(struct tg3 *tp)
3598{
3599 u32 mac_status = tr32(MAC_STATUS);
3600 int i;
3601
3602 /* Reset when initting first time or we have a link. */
3603 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3604 !(mac_status & MAC_STATUS_PCS_SYNCED))
3605 return;
3606
3607 /* Set PLL lock range. */
3608 tg3_writephy(tp, 0x16, 0x8007);
3609
3610 /* SW reset */
3611 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3612
3613 /* Wait for reset to complete. */
3614 /* XXX schedule_timeout() ... */
3615 for (i = 0; i < 500; i++)
3616 udelay(10);
3617
3618 /* Config mode; select PMA/Ch 1 regs. */
3619 tg3_writephy(tp, 0x10, 0x8411);
3620
3621 /* Enable auto-lock and comdet, select txclk for tx. */
3622 tg3_writephy(tp, 0x11, 0x0a10);
3623
3624 tg3_writephy(tp, 0x18, 0x00a0);
3625 tg3_writephy(tp, 0x16, 0x41ff);
3626
3627 /* Assert and deassert POR. */
3628 tg3_writephy(tp, 0x13, 0x0400);
3629 udelay(40);
3630 tg3_writephy(tp, 0x13, 0x0000);
3631
3632 tg3_writephy(tp, 0x11, 0x0a50);
3633 udelay(40);
3634 tg3_writephy(tp, 0x11, 0x0a10);
3635
3636 /* Wait for signal to stabilize */
3637 /* XXX schedule_timeout() ... */
3638 for (i = 0; i < 15000; i++)
3639 udelay(10);
3640
3641 /* Deselect the channel register so we can read the PHYID
3642 * later.
3643 */
3644 tg3_writephy(tp, 0x10, 0x8011);
3645}
3646
3647static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3648{
82cd3d11 3649 u16 flowctrl;
1da177e4
LT		 3650 u32 sg_dig_ctrl, sg_dig_status;
3651 u32 serdes_cfg, expected_sg_dig_ctrl;
3652 int workaround, port_a;
3653 int current_link_up;
3654
3655 serdes_cfg = 0;
3656 expected_sg_dig_ctrl = 0;
3657 workaround = 0;
3658 port_a = 1;
3659 current_link_up = 0;
3660
3661 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3662 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3663 workaround = 1;
3664 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3665 port_a = 0;
3666
3667 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3668 /* preserve bits 20-23 for voltage regulator */
3669 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3670 }
3671
3672 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3673
3674 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3675 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3676 if (workaround) {
3677 u32 val = serdes_cfg;
3678
3679 if (port_a)
3680 val |= 0xc010000;
3681 else
3682 val |= 0x4010000;
3683 tw32_f(MAC_SERDES_CFG, val);
3684 }
c98f6e3b
MC		 3685
3686 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3687 }
3688 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3689 tg3_setup_flow_control(tp, 0, 0);
3690 current_link_up = 1;
3691 }
3692 goto out;
3693 }
3694
3695 /* Want auto-negotiation. */
c98f6e3b 3696 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3697
82cd3d11
MC		 3698 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3699 if (flowctrl & ADVERTISE_1000XPAUSE)
3700 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3701 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3702 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3703
3704 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3705 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3706 tp->serdes_counter &&
3707 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3708 MAC_STATUS_RCVD_CFG)) ==
3709 MAC_STATUS_PCS_SYNCED)) {
3710 tp->serdes_counter--;
3711 current_link_up = 1;
3712 goto out;
3713 }
3714restart_autoneg:
1da177e4
LT		 3715 if (workaround)
3716 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3717 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3718 udelay(5);
3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3720
3d3ebe74
MC		 3721 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3722 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3723 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3724 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3725 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3726 mac_status = tr32(MAC_STATUS);
3727
c98f6e3b 3728 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3729 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3730 u32 local_adv = 0, remote_adv = 0;
3731
3732 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3733 local_adv |= ADVERTISE_1000XPAUSE;
3734 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3735 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3736
c98f6e3b 3737 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3738 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3739 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3740 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3741
3742 tg3_setup_flow_control(tp, local_adv, remote_adv);
3743 current_link_up = 1;
3d3ebe74
MC		 3744 tp->serdes_counter = 0;
3745 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3746 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3747 if (tp->serdes_counter)
3748 tp->serdes_counter--;
1da177e4
LT		 3749 else {
3750 if (workaround) {
3751 u32 val = serdes_cfg;
3752
3753 if (port_a)
3754 val |= 0xc010000;
3755 else
3756 val |= 0x4010000;
3757
3758 tw32_f(MAC_SERDES_CFG, val);
3759 }
3760
c98f6e3b 3761 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3762 udelay(40);
3763
3764 /* Link parallel detection - link is up */
3765 /* only if we have PCS_SYNC and not */
3766 /* receiving config code words */
3767 mac_status = tr32(MAC_STATUS);
3768 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3769 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3770 tg3_setup_flow_control(tp, 0, 0);
3771 current_link_up = 1;
3d3ebe74
MC		 3772 tp->tg3_flags2 |=
3773 TG3_FLG2_PARALLEL_DETECT;
3774 tp->serdes_counter =
3775 SERDES_PARALLEL_DET_TIMEOUT;
3776 } else
3777 goto restart_autoneg;
1da177e4
LT		 3778 }
3779 }
3d3ebe74
MC		 3780 } else {
3781 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3782 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3783 }
3784
3785out:
3786 return current_link_up;
3787}
3788
3789static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3790{
3791 int current_link_up = 0;
3792
5cf64b8a 3793 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3794 goto out;
1da177e4
LT		 3795
3796 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3797 u32 txflags, rxflags;
1da177e4 3798 int i;
6aa20a22 3799
5be73b47
MC		 3800 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3801 u32 local_adv = 0, remote_adv = 0;
1da177e4 3802
5be73b47
MC		 3803 if (txflags & ANEG_CFG_PS1)
3804 local_adv |= ADVERTISE_1000XPAUSE;
3805 if (txflags & ANEG_CFG_PS2)
3806 local_adv |= ADVERTISE_1000XPSE_ASYM;
3807
3808 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3809 remote_adv |= LPA_1000XPAUSE;
3810 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3812
3813 tg3_setup_flow_control(tp, local_adv, remote_adv);
3814
1da177e4
LT		 3815 current_link_up = 1;
3816 }
3817 for (i = 0; i < 30; i++) {
3818 udelay(20);
3819 tw32_f(MAC_STATUS,
3820 (MAC_STATUS_SYNC_CHANGED |
3821 MAC_STATUS_CFG_CHANGED));
3822 udelay(40);
3823 if ((tr32(MAC_STATUS) &
3824 (MAC_STATUS_SYNC_CHANGED |
3825 MAC_STATUS_CFG_CHANGED)) == 0)
3826 break;
3827 }
3828
3829 mac_status = tr32(MAC_STATUS);
3830 if (current_link_up == 0 &&
3831 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3832 !(mac_status & MAC_STATUS_RCVD_CFG))
3833 current_link_up = 1;
3834 } else {
5be73b47
MC		 3835 tg3_setup_flow_control(tp, 0, 0);
3836
1da177e4
LT		 3837 /* Forcing 1000FD link up. */
3838 current_link_up = 1;
1da177e4
LT		 3839
3840 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3841 udelay(40);
e8f3f6ca
MC		 3842
3843 tw32_f(MAC_MODE, tp->mac_mode);
3844 udelay(40);
1da177e4
LT		 3845 }
3846
3847out:
3848 return current_link_up;
3849}
3850
3851static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3852{
3853 u32 orig_pause_cfg;
3854 u16 orig_active_speed;
3855 u8 orig_active_duplex;
3856 u32 mac_status;
3857 int current_link_up;
3858 int i;
3859
8d018621 3860 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3861 orig_active_speed = tp->link_config.active_speed;
3862 orig_active_duplex = tp->link_config.active_duplex;
3863
3864 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3865 netif_carrier_ok(tp->dev) &&
3866 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3867 mac_status = tr32(MAC_STATUS);
3868 mac_status &= (MAC_STATUS_PCS_SYNCED |
3869 MAC_STATUS_SIGNAL_DET |
3870 MAC_STATUS_CFG_CHANGED |
3871 MAC_STATUS_RCVD_CFG);
3872 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3873 MAC_STATUS_SIGNAL_DET)) {
3874 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3875 MAC_STATUS_CFG_CHANGED));
3876 return 0;
3877 }
3878 }
3879
3880 tw32_f(MAC_TX_AUTO_NEG, 0);
3881
3882 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3883 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3884 tw32_f(MAC_MODE, tp->mac_mode);
3885 udelay(40);
3886
3887 if (tp->phy_id == PHY_ID_BCM8002)
3888 tg3_init_bcm8002(tp);
3889
3890 /* Enable link change event even when serdes polling. */
3891 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3892 udelay(40);
3893
3894 current_link_up = 0;
3895 mac_status = tr32(MAC_STATUS);
3896
3897 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3898 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3899 else
3900 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3901
1da177e4
LT		 3902 tp->hw_status->status =
3903 (SD_STATUS_UPDATED |
3904 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3905
3906 for (i = 0; i < 100; i++) {
3907 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3908 MAC_STATUS_CFG_CHANGED));
3909 udelay(5);
3910 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3911 MAC_STATUS_CFG_CHANGED |
3912 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3913 break;
3914 }
3915
3916 mac_status = tr32(MAC_STATUS);
3917 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3918 current_link_up = 0;
3d3ebe74
MC		 3919 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3920 tp->serdes_counter == 0) {
1da177e4
LT		 3921 tw32_f(MAC_MODE, (tp->mac_mode |
3922 MAC_MODE_SEND_CONFIGS));
3923 udelay(1);
3924 tw32_f(MAC_MODE, tp->mac_mode);
3925 }
3926 }
3927
3928 if (current_link_up == 1) {
3929 tp->link_config.active_speed = SPEED_1000;
3930 tp->link_config.active_duplex = DUPLEX_FULL;
3931 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3932 LED_CTRL_LNKLED_OVERRIDE |
3933 LED_CTRL_1000MBPS_ON));
3934 } else {
3935 tp->link_config.active_speed = SPEED_INVALID;
3936 tp->link_config.active_duplex = DUPLEX_INVALID;
3937 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3938 LED_CTRL_LNKLED_OVERRIDE |
3939 LED_CTRL_TRAFFIC_OVERRIDE));
3940 }
3941
3942 if (current_link_up != netif_carrier_ok(tp->dev)) {
3943 if (current_link_up)
3944 netif_carrier_on(tp->dev);
3945 else
3946 netif_carrier_off(tp->dev);
3947 tg3_link_report(tp);
3948 } else {
8d018621 3949 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3950 if (orig_pause_cfg != now_pause_cfg ||
3951 orig_active_speed != tp->link_config.active_speed ||
3952 orig_active_duplex != tp->link_config.active_duplex)
3953 tg3_link_report(tp);
3954 }
3955
3956 return 0;
3957}
3958
747e8f8b
MC		 3959static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3960{
3961 int current_link_up, err = 0;
3962 u32 bmsr, bmcr;
3963 u16 current_speed;
3964 u8 current_duplex;
ef167e27 3965 u32 local_adv, remote_adv;
747e8f8b
MC		 3966
3967 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3968 tw32_f(MAC_MODE, tp->mac_mode);
3969 udelay(40);
3970
3971 tw32(MAC_EVENT, 0);
3972
3973 tw32_f(MAC_STATUS,
3974 (MAC_STATUS_SYNC_CHANGED |
3975 MAC_STATUS_CFG_CHANGED |
3976 MAC_STATUS_MI_COMPLETION |
3977 MAC_STATUS_LNKSTATE_CHANGED));
3978 udelay(40);
3979
3980 if (force_reset)
3981 tg3_phy_reset(tp);
3982
3983 current_link_up = 0;
3984 current_speed = SPEED_INVALID;
3985 current_duplex = DUPLEX_INVALID;
3986
3987 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3988 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3990 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3991 bmsr |= BMSR_LSTATUS;
3992 else
3993 bmsr &= ~BMSR_LSTATUS;
3994 }
747e8f8b
MC		 3995
3996 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3997
3998 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3999 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4000 /* do nothing, just check for link up at the end */
4001 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4002 u32 adv, new_adv;
4003
4004 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4005 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4006 ADVERTISE_1000XPAUSE |
4007 ADVERTISE_1000XPSE_ASYM |
4008 ADVERTISE_SLCT);
4009
ba4d07a8 4010 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4011
4012 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4013 new_adv |= ADVERTISE_1000XHALF;
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4015 new_adv |= ADVERTISE_1000XFULL;
4016
4017 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4018 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4019 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4020 tg3_writephy(tp, MII_BMCR, bmcr);
4021
4022 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4023 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4024 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4025
4026 return err;
4027 }
4028 } else {
4029 u32 new_bmcr;
4030
4031 bmcr &= ~BMCR_SPEED1000;
4032 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4033
4034 if (tp->link_config.duplex == DUPLEX_FULL)
4035 new_bmcr |= BMCR_FULLDPLX;
4036
4037 if (new_bmcr != bmcr) {
4038 /* BMCR_SPEED1000 is a reserved bit that needs
4039 * to be set on write.
4040 */
4041 new_bmcr |= BMCR_SPEED1000;
4042
4043 /* Force a linkdown */
4044 if (netif_carrier_ok(tp->dev)) {
4045 u32 adv;
4046
4047 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4048 adv &= ~(ADVERTISE_1000XFULL |
4049 ADVERTISE_1000XHALF |
4050 ADVERTISE_SLCT);
4051 tg3_writephy(tp, MII_ADVERTISE, adv);
4052 tg3_writephy(tp, MII_BMCR, bmcr |
4053 BMCR_ANRESTART |
4054 BMCR_ANENABLE);
4055 udelay(10);
4056 netif_carrier_off(tp->dev);
4057 }
4058 tg3_writephy(tp, MII_BMCR, new_bmcr);
4059 bmcr = new_bmcr;
4060 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4061 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4062 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4063 ASIC_REV_5714) {
4064 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4065 bmsr |= BMSR_LSTATUS;
4066 else
4067 bmsr &= ~BMSR_LSTATUS;
4068 }
747e8f8b
MC		 4069 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4070 }
4071 }
4072
4073 if (bmsr & BMSR_LSTATUS) {
4074 current_speed = SPEED_1000;
4075 current_link_up = 1;
4076 if (bmcr & BMCR_FULLDPLX)
4077 current_duplex = DUPLEX_FULL;
4078 else
4079 current_duplex = DUPLEX_HALF;
4080
ef167e27
MC		 4081 local_adv = 0;
4082 remote_adv = 0;
4083
747e8f8b 4084 if (bmcr & BMCR_ANENABLE) {
ef167e27 4085 u32 common;
747e8f8b
MC		 4086
4087 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4088 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4089 common = local_adv & remote_adv;
4090 if (common & (ADVERTISE_1000XHALF |
4091 ADVERTISE_1000XFULL)) {
4092 if (common & ADVERTISE_1000XFULL)
4093 current_duplex = DUPLEX_FULL;
4094 else
4095 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4096 }
4097 else
4098 current_link_up = 0;
4099 }
4100 }
4101
ef167e27
MC		 4102 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4103 tg3_setup_flow_control(tp, local_adv, remote_adv);
4104
747e8f8b
MC		 4105 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4106 if (tp->link_config.active_duplex == DUPLEX_HALF)
4107 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4108
4109 tw32_f(MAC_MODE, tp->mac_mode);
4110 udelay(40);
4111
4112 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4113
4114 tp->link_config.active_speed = current_speed;
4115 tp->link_config.active_duplex = current_duplex;
4116
4117 if (current_link_up != netif_carrier_ok(tp->dev)) {
4118 if (current_link_up)
4119 netif_carrier_on(tp->dev);
4120 else {
4121 netif_carrier_off(tp->dev);
4122 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4123 }
4124 tg3_link_report(tp);
4125 }
4126 return err;
4127}
4128
4129static void tg3_serdes_parallel_detect(struct tg3 *tp)
4130{
3d3ebe74 4131 if (tp->serdes_counter) {
747e8f8b 4132 /* Give autoneg time to complete. */
3d3ebe74 4133 tp->serdes_counter--;
747e8f8b
MC		 4134 return;
4135 }
4136 if (!netif_carrier_ok(tp->dev) &&
4137 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4138 u32 bmcr;
4139
4140 tg3_readphy(tp, MII_BMCR, &bmcr);
4141 if (bmcr & BMCR_ANENABLE) {
4142 u32 phy1, phy2;
4143
4144 /* Select shadow register 0x1f */
4145 tg3_writephy(tp, 0x1c, 0x7c00);
4146 tg3_readphy(tp, 0x1c, &phy1);
4147
4148 /* Select expansion interrupt status register */
4149 tg3_writephy(tp, 0x17, 0x0f01);
4150 tg3_readphy(tp, 0x15, &phy2);
4151 tg3_readphy(tp, 0x15, &phy2);
4152
4153 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4154 /* We have signal detect and not receiving
4155 * config code words, link is up by parallel
4156 * detection.
4157 */
4158
4159 bmcr &= ~BMCR_ANENABLE;
4160 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4161 tg3_writephy(tp, MII_BMCR, bmcr);
4162 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4163 }
4164 }
4165 }
4166 else if (netif_carrier_ok(tp->dev) &&
4167 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4168 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4169 u32 phy2;
4170
4171 /* Select expansion interrupt status register */
4172 tg3_writephy(tp, 0x17, 0x0f01);
4173 tg3_readphy(tp, 0x15, &phy2);
4174 if (phy2 & 0x20) {
4175 u32 bmcr;
4176
4177 /* Config code words received, turn on autoneg. */
4178 tg3_readphy(tp, MII_BMCR, &bmcr);
4179 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4180
4181 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4182
4183 }
4184 }
4185}
4186
1da177e4
LT		 4187static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4188{
4189 int err;
4190
4191 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4192 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4193 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4194 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4195 } else {
4196 err = tg3_setup_copper_phy(tp, force_reset);
4197 }
4198
bcb37f6c 4199 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4200 u32 val, scale;
4201
4202 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4203 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4204 scale = 65;
4205 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4206 scale = 6;
4207 else
4208 scale = 12;
4209
4210 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4211 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4212 tw32(GRC_MISC_CFG, val);
4213 }
4214
1da177e4
LT		 4215 if (tp->link_config.active_speed == SPEED_1000 &&
4216 tp->link_config.active_duplex == DUPLEX_HALF)
4217 tw32(MAC_TX_LENGTHS,
4218 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4219 (6 << TX_LENGTHS_IPG_SHIFT) |
4220 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4221 else
4222 tw32(MAC_TX_LENGTHS,
4223 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4224 (6 << TX_LENGTHS_IPG_SHIFT) |
4225 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4226
4227 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4228 if (netif_carrier_ok(tp->dev)) {
4229 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4230 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4231 } else {
4232 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4233 }
4234 }
4235
8ed5d97e
MC		 4236 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4237 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4238 if (!netif_carrier_ok(tp->dev))
4239 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4240 tp->pwrmgmt_thresh;
4241 else
4242 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4243 tw32(PCIE_PWR_MGMT_THRESH, val);
4244 }
4245
1da177e4
LT		 4246 return err;
4247}
4248
df3e6548
MC		 4249/* This is called whenever we suspect that the system chipset is re-
4250 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4251 * is bogus tx completions. We try to recover by setting the
4252 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4253 * in the workqueue.
4254 */
4255static void tg3_tx_recover(struct tg3 *tp)
4256{
4257 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4258 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4259
4260 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4261 "mapped I/O cycles to the network device, attempting to "
4262 "recover. Please report the problem to the driver maintainer "
4263 "and include system chipset information.\n", tp->dev->name);
4264
4265 spin_lock(&tp->lock);
df3e6548 4266 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4267 spin_unlock(&tp->lock);
4268}
4269
1b2a7205
MC		 4270static inline u32 tg3_tx_avail(struct tg3 *tp)
4271{
4272 smp_mb();
4273 return (tp->tx_pending -
4274 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4275}
4276
1da177e4
LT		 4277/* Tigon3 never reports partial packet sends. So we do not
4278 * need special logic to handle SKBs that have not had all
4279 * of their frags sent yet, like SunGEM does.
4280 */
4281static void tg3_tx(struct tg3 *tp)
4282{
4283 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4284 u32 sw_idx = tp->tx_cons;
4285
4286 while (sw_idx != hw_idx) {
4287 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4288 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4289 int i, tx_bug = 0;
4290
4291 if (unlikely(skb == NULL)) {
4292 tg3_tx_recover(tp);
4293 return;
4294 }
1da177e4 4295
90079ce8 4296 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4297
4298 ri->skb = NULL;
4299
4300 sw_idx = NEXT_TX(sw_idx);
4301
4302 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4303 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4304 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4305 tx_bug = 1;
1da177e4
LT		 4306 sw_idx = NEXT_TX(sw_idx);
4307 }
4308
f47c11ee 4309 dev_kfree_skb(skb);
df3e6548
MC		 4310
4311 if (unlikely(tx_bug)) {
4312 tg3_tx_recover(tp);
4313 return;
4314 }
1da177e4
LT		 4315 }
4316
4317 tp->tx_cons = sw_idx;
4318
1b2a7205
MC		 4319 /* Need to make the tx_cons update visible to tg3_start_xmit()
4320 * before checking for netif_queue_stopped(). Without the
4321 * memory barrier, there is a small possibility that tg3_start_xmit()
4322 * will miss it and cause the queue to be stopped forever.
4323 */
4324 smp_mb();
4325
4326 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4327 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4328 netif_tx_lock(tp->dev);
51b91468 4329 if (netif_queue_stopped(tp->dev) &&
42952231 4330 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4331 netif_wake_queue(tp->dev);
1b2a7205 4332 netif_tx_unlock(tp->dev);
51b91468 4333 }
1da177e4
LT		 4334}
4335
4336/* Returns size of skb allocated or < 0 on error.
4337 *
4338 * We only need to fill in the address because the other members
4339 * of the RX descriptor are invariant, see tg3_init_rings.
4340 *
4341 * Note the purposeful assymetry of cpu vs. chip accesses. For
4342 * posting buffers we only dirty the first cache line of the RX
4343 * descriptor (containing the address). Whereas for the RX status
4344 * buffers the cpu only reads the last cacheline of the RX descriptor
4345 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4346 */
4347static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4348 int src_idx, u32 dest_idx_unmasked)
4349{
4350 struct tg3_rx_buffer_desc *desc;
4351 struct ring_info *map, *src_map;
4352 struct sk_buff *skb;
4353 dma_addr_t mapping;
4354 int skb_size, dest_idx;
21f581a5 4355 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4356
4357 src_map = NULL;
4358 switch (opaque_key) {
4359 case RXD_OPAQUE_RING_STD:
4360 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4361 desc = &tpr->rx_std[dest_idx];
4362 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4363 if (src_idx >= 0)
21f581a5 4364 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4365 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4366 break;
4367
4368 case RXD_OPAQUE_RING_JUMBO:
4369 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4370 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4371 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4372 if (src_idx >= 0)
21f581a5 4373 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4374 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4375 break;
4376
4377 default:
4378 return -EINVAL;
855e1111 4379 }
1da177e4
LT		 4380
4381 /* Do not overwrite any of the map or rp information
4382 * until we are sure we can commit to a new buffer.
4383 *
4384 * Callers depend upon this behavior and assume that
4385 * we leave everything unchanged if we fail.
4386 */
287be12e 4387 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4388 if (skb == NULL)
4389 return -ENOMEM;
4390
1da177e4
LT		 4391 skb_reserve(skb, tp->rx_offset);
4392
287be12e 4393 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4394 PCI_DMA_FROMDEVICE);
4395
4396 map->skb = skb;
4397 pci_unmap_addr_set(map, mapping, mapping);
4398
4399 if (src_map != NULL)
4400 src_map->skb = NULL;
4401
4402 desc->addr_hi = ((u64)mapping >> 32);
4403 desc->addr_lo = ((u64)mapping & 0xffffffff);
4404
4405 return skb_size;
4406}
4407
4408/* We only need to move over in the address because the other
4409 * members of the RX descriptor are invariant. See notes above
4410 * tg3_alloc_rx_skb for full details.
4411 */
4412static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4413 int src_idx, u32 dest_idx_unmasked)
4414{
4415 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4416 struct ring_info *src_map, *dest_map;
4417 int dest_idx;
21f581a5 4418 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4419
4420 switch (opaque_key) {
4421 case RXD_OPAQUE_RING_STD:
4422 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4423 dest_desc = &tpr->rx_std[dest_idx];
4424 dest_map = &tpr->rx_std_buffers[dest_idx];
4425 src_desc = &tpr->rx_std[src_idx];
4426 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4427 break;
4428
4429 case RXD_OPAQUE_RING_JUMBO:
4430 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4431 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4432 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4433 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4434 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4435 break;
4436
4437 default:
4438 return;
855e1111 4439 }
1da177e4
LT		 4440
4441 dest_map->skb = src_map->skb;
4442 pci_unmap_addr_set(dest_map, mapping,
4443 pci_unmap_addr(src_map, mapping));
4444 dest_desc->addr_hi = src_desc->addr_hi;
4445 dest_desc->addr_lo = src_desc->addr_lo;
4446
4447 src_map->skb = NULL;
4448}
4449
4450#if TG3_VLAN_TAG_USED
4451static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4452{
1383bdb9 4453 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
1da177e4
LT		 4454}
4455#endif
4456
4457/* The RX ring scheme is composed of multiple rings which post fresh
4458 * buffers to the chip, and one special ring the chip uses to report
4459 * status back to the host.
4460 *
4461 * The special ring reports the status of received packets to the
4462 * host. The chip does not write into the original descriptor the
4463 * RX buffer was obtained from. The chip simply takes the original
4464 * descriptor as provided by the host, updates the status and length
4465 * field, then writes this into the next status ring entry.
4466 *
4467 * Each ring the host uses to post buffers to the chip is described
4468 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4469 * it is first placed into the on-chip ram. When the packet's length
4470 * is known, it walks down the TG3_BDINFO entries to select the ring.
4471 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4472 * which is within the range of the new packet's length is chosen.
4473 *
4474 * The "separate ring for rx status" scheme may sound queer, but it makes
4475 * sense from a cache coherency perspective. If only the host writes
4476 * to the buffer post rings, and only the chip writes to the rx status
4477 * rings, then cache lines never move beyond shared-modified state.
4478 * If both the host and chip were to write into the same ring, cache line
4479 * eviction could occur since both entities want it in an exclusive state.
4480 */
4481static int tg3_rx(struct tg3 *tp, int budget)
4482{
f92905de 4483 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4484 u32 sw_idx = tp->rx_rcb_ptr;
4485 u16 hw_idx;
1da177e4 4486 int received;
21f581a5 4487 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4488
4489 hw_idx = tp->hw_status->idx[0].rx_producer;
4490 /*
4491 * We need to order the read of hw_idx and the read of
4492 * the opaque cookie.
4493 */
4494 rmb();
1da177e4
LT		 4495 work_mask = 0;
4496 received = 0;
4497 while (sw_idx != hw_idx && budget > 0) {
4498 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4499 unsigned int len;
4500 struct sk_buff *skb;
4501 dma_addr_t dma_addr;
4502 u32 opaque_key, desc_idx, *post_ptr;
4503
4504 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4505 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4506 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4507 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4508 dma_addr = pci_unmap_addr(ri, mapping);
4509 skb = ri->skb;
4510 post_ptr = &tpr->rx_std_ptr;
f92905de 4511 rx_std_posted++;
1da177e4 4512 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4513 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4514 dma_addr = pci_unmap_addr(ri, mapping);
4515 skb = ri->skb;
4516 post_ptr = &tpr->rx_jmb_ptr;
4517 } else
1da177e4 4518 goto next_pkt_nopost;
1da177e4
LT		 4519
4520 work_mask |= opaque_key;
4521
4522 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4523 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4524 drop_it:
4525 tg3_recycle_rx(tp, opaque_key,
4526 desc_idx, *post_ptr);
4527 drop_it_no_recycle:
4528 /* Other statistics kept track of by card. */
4529 tp->net_stats.rx_dropped++;
4530 goto next_pkt;
4531 }
4532
ad829268
MC		 4533 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4534 ETH_FCS_LEN;
1da177e4 4535
6aa20a22 4536 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4537 && tp->rx_offset == NET_IP_ALIGN
4538 /* rx_offset will likely not equal NET_IP_ALIGN
4539 * if this is a 5701 card running in PCI-X mode
4540 * [see tg3_get_invariants()]
4541 */
1da177e4
LT		 4542 ) {
4543 int skb_size;
4544
4545 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4546 desc_idx, *post_ptr);
4547 if (skb_size < 0)
4548 goto drop_it;
4549
287be12e 4550 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4551 PCI_DMA_FROMDEVICE);
4552
4553 skb_put(skb, len);
4554 } else {
4555 struct sk_buff *copy_skb;
4556
4557 tg3_recycle_rx(tp, opaque_key,
4558 desc_idx, *post_ptr);
4559
ad829268
MC		 4560 copy_skb = netdev_alloc_skb(tp->dev,
4561 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4562 if (copy_skb == NULL)
4563 goto drop_it_no_recycle;
4564
ad829268 4565 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4566 skb_put(copy_skb, len);
4567 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4568 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4569 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4570
4571 /* We'll reuse the original ring buffer. */
4572 skb = copy_skb;
4573 }
4574
4575 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4576 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4577 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4578 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4579 skb->ip_summed = CHECKSUM_UNNECESSARY;
4580 else
4581 skb->ip_summed = CHECKSUM_NONE;
4582
4583 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4584
4585 if (len > (tp->dev->mtu + ETH_HLEN) &&
4586 skb->protocol != htons(ETH_P_8021Q)) {
4587 dev_kfree_skb(skb);
4588 goto next_pkt;
4589 }
4590
1da177e4
LT		 4591#if TG3_VLAN_TAG_USED
4592 if (tp->vlgrp != NULL &&
4593 desc->type_flags & RXD_FLAG_VLAN) {
4594 tg3_vlan_rx(tp, skb,
4595 desc->err_vlan & RXD_VLAN_MASK);
4596 } else
4597#endif
1383bdb9 4598 napi_gro_receive(&tp->napi, skb);
1da177e4 4599
1da177e4
LT		 4600 received++;
4601 budget--;
4602
4603next_pkt:
4604 (*post_ptr)++;
f92905de
MC		 4605
4606 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4607 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4608
4609 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4610 TG3_64BIT_REG_LOW, idx);
4611 work_mask &= ~RXD_OPAQUE_RING_STD;
4612 rx_std_posted = 0;
4613 }
1da177e4 4614next_pkt_nopost:
483ba50b 4615 sw_idx++;
6b31a515 4616 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4617
4618 /* Refresh hw_idx to see if there is new work */
4619 if (sw_idx == hw_idx) {
4620 hw_idx = tp->hw_status->idx[0].rx_producer;
4621 rmb();
4622 }
1da177e4
LT		 4623 }
4624
4625 /* ACK the status ring. */
483ba50b
MC		 4626 tp->rx_rcb_ptr = sw_idx;
4627 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4628
4629 /* Refill RX ring(s). */
4630 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4631 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4632 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4633 sw_idx);
4634 }
4635 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4636 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4637 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4638 sw_idx);
4639 }
4640 mmiowb();
4641
4642 return received;
4643}
4644
6f535763 4645static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4646{
1da177e4 4647 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4648
1da177e4
LT		 4649 /* handle link change and other phy events */
4650 if (!(tp->tg3_flags &
4651 (TG3_FLAG_USE_LINKCHG_REG |
4652 TG3_FLAG_POLL_SERDES))) {
4653 if (sblk->status & SD_STATUS_LINK_CHG) {
4654 sblk->status = SD_STATUS_UPDATED |
4655 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4656 spin_lock(&tp->lock);
dd477003
MC		 4657 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4658 tw32_f(MAC_STATUS,
4659 (MAC_STATUS_SYNC_CHANGED |
4660 MAC_STATUS_CFG_CHANGED |
4661 MAC_STATUS_MI_COMPLETION |
4662 MAC_STATUS_LNKSTATE_CHANGED));
4663 udelay(40);
4664 } else
4665 tg3_setup_phy(tp, 0);
f47c11ee 4666 spin_unlock(&tp->lock);
1da177e4
LT		 4667 }
4668 }
4669
4670 /* run TX completion thread */
4671 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4672 tg3_tx(tp);
6f535763 4673 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4674 return work_done;
1da177e4
LT		 4675 }
4676
1da177e4
LT		 4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
bea3348e 4679 * code synchronizes with tg3->napi.poll()
1da177e4 4680 */
bea3348e 4681 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4682 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4683
6f535763
DM		 4684 return work_done;
4685}
4686
4687static int tg3_poll(struct napi_struct *napi, int budget)
4688{
4689 struct tg3 *tp = container_of(napi, struct tg3, napi);
4690 int work_done = 0;
4fd7ab59 4691 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4692
4693 while (1) {
4694 work_done = tg3_poll_work(tp, work_done, budget);
4695
4696 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4697 goto tx_recovery;
4698
4699 if (unlikely(work_done >= budget))
4700 break;
4701
4fd7ab59
MC		 4702 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4703 /* tp->last_tag is used in tg3_restart_ints() below
4704 * to tell the hw how much work has been processed,
4705 * so we must read it before checking for more work.
4706 */
4707 tp->last_tag = sblk->status_tag;
624f8e50 4708 tp->last_irq_tag = tp->last_tag;
4fd7ab59
MC		 4709 rmb();
4710 } else
4711 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4712
4fd7ab59 4713 if (likely(!tg3_has_work(tp))) {
288379f0 4714 napi_complete(napi);
6f535763
DM		 4715 tg3_restart_ints(tp);
4716 break;
4717 }
1da177e4
LT		 4718 }
4719
bea3348e 4720 return work_done;
6f535763
DM		 4721
4722tx_recovery:
4fd7ab59 4723 /* work_done is guaranteed to be less than budget. */
288379f0 4724 napi_complete(napi);
6f535763 4725 schedule_work(&tp->reset_task);
4fd7ab59 4726 return work_done;
1da177e4
LT		 4727}
4728
f47c11ee
DM		 4729static void tg3_irq_quiesce(struct tg3 *tp)
4730{
4731 BUG_ON(tp->irq_sync);
4732
4733 tp->irq_sync = 1;
4734 smp_mb();
4735
4736 synchronize_irq(tp->pdev->irq);
4737}
4738
4739static inline int tg3_irq_sync(struct tg3 *tp)
4740{
4741 return tp->irq_sync;
4742}
4743
4744/* Fully shutdown all tg3 driver activity elsewhere in the system.
4745 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4746 * with as well. Most of the time, this is not necessary except when
4747 * shutting down the device.
4748 */
4749static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4750{
46966545 4751 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4752 if (irq_sync)
4753 tg3_irq_quiesce(tp);
f47c11ee
DM		 4754}
4755
4756static inline void tg3_full_unlock(struct tg3 *tp)
4757{
f47c11ee
DM		 4758 spin_unlock_bh(&tp->lock);
4759}
4760
fcfa0a32
MC		 4761/* One-shot MSI handler - Chip automatically disables interrupt
4762 * after sending MSI so driver doesn't have to do it.
4763 */
7d12e780 4764static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4765{
4766 struct net_device *dev = dev_id;
4767 struct tg3 *tp = netdev_priv(dev);
4768
4769 prefetch(tp->hw_status);
4770 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4771
4772 if (likely(!tg3_irq_sync(tp)))
288379f0 4773 napi_schedule(&tp->napi);
fcfa0a32
MC		 4774
4775 return IRQ_HANDLED;
4776}
4777
88b06bc2
MC		 4778/* MSI ISR - No need to check for interrupt sharing and no need to
4779 * flush status block and interrupt mailbox. PCI ordering rules
4780 * guarantee that MSI will arrive after the status block.
4781 */
7d12e780 4782static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4783{
4784 struct net_device *dev = dev_id;
4785 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4786
61487480
MC		 4787 prefetch(tp->hw_status);
4788 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4789 /*
fac9b83e 4790 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4791 * chip-internal interrupt pending events.
fac9b83e 4792 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4793 * NIC to stop sending us irqs, engaging "in-intr-handler"
4794 * event coalescing.
4795 */
4796 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4797 if (likely(!tg3_irq_sync(tp)))
288379f0 4798 napi_schedule(&tp->napi);
61487480 4799
88b06bc2
MC		 4800 return IRQ_RETVAL(1);
4801}
4802
7d12e780 4803static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4804{
4805 struct net_device *dev = dev_id;
4806 struct tg3 *tp = netdev_priv(dev);
4807 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4808 unsigned int handled = 1;
4809
1da177e4
LT		 4810 /* In INTx mode, it is possible for the interrupt to arrive at
4811 * the CPU before the status block posted prior to the interrupt.
4812 * Reading the PCI State register will confirm whether the
4813 * interrupt is ours and will flush the status block.
4814 */
d18edcb2
MC		 4815 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4816 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4817 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4818 handled = 0;
f47c11ee 4819 goto out;
fac9b83e 4820 }
d18edcb2
MC		 4821 }
4822
4823 /*
4824 * Writing any value to intr-mbox-0 clears PCI INTA# and
4825 * chip-internal interrupt pending events.
4826 * Writing non-zero to intr-mbox-0 additional tells the
4827 * NIC to stop sending us irqs, engaging "in-intr-handler"
4828 * event coalescing.
c04cb347
MC		 4829 *
4830 * Flush the mailbox to de-assert the IRQ immediately to prevent
4831 * spurious interrupts. The flush impacts performance but
4832 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4833 */
c04cb347 4834 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4835 if (tg3_irq_sync(tp))
4836 goto out;
4837 sblk->status &= ~SD_STATUS_UPDATED;
4838 if (likely(tg3_has_work(tp))) {
4839 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4840 napi_schedule(&tp->napi);
d18edcb2
MC		 4841 } else {
4842 /* No work, shared interrupt perhaps? re-enable
4843 * interrupts, and flush that PCI write
4844 */
4845 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4846 0x00000000);
fac9b83e 4847 }
f47c11ee 4848out:
fac9b83e
DM		 4849 return IRQ_RETVAL(handled);
4850}
4851
7d12e780 4852static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4853{
4854 struct net_device *dev = dev_id;
4855 struct tg3 *tp = netdev_priv(dev);
4856 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4857 unsigned int handled = 1;
4858
fac9b83e
DM		 4859 /* In INTx mode, it is possible for the interrupt to arrive at
4860 * the CPU before the status block posted prior to the interrupt.
4861 * Reading the PCI State register will confirm whether the
4862 * interrupt is ours and will flush the status block.
4863 */
624f8e50 4864 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
d18edcb2
MC		 4865 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4866 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4867 handled = 0;
f47c11ee 4868 goto out;
1da177e4 4869 }
d18edcb2
MC		 4870 }
4871
4872 /*
4873 * writing any value to intr-mbox-0 clears PCI INTA# and
4874 * chip-internal interrupt pending events.
4875 * writing non-zero to intr-mbox-0 additional tells the
4876 * NIC to stop sending us irqs, engaging "in-intr-handler"
4877 * event coalescing.
c04cb347
MC		 4878 *
4879 * Flush the mailbox to de-assert the IRQ immediately to prevent
4880 * spurious interrupts. The flush impacts performance but
4881 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4882 */
c04cb347 4883 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4884
4885 /*
4886 * In a shared interrupt configuration, sometimes other devices'
4887 * interrupts will scream. We record the current status tag here
4888 * so that the above check can report that the screaming interrupts
4889 * are unhandled. Eventually they will be silenced.
4890 */
4891 tp->last_irq_tag = sblk->status_tag;
4892
d18edcb2
MC		 4893 if (tg3_irq_sync(tp))
4894 goto out;
624f8e50
MC		 4895
4896 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4897
4898 napi_schedule(&tp->napi);
4899
f47c11ee 4900out:
1da177e4
LT		 4901 return IRQ_RETVAL(handled);
4902}
4903
7938109f 4904/* ISR for interrupt test */
7d12e780 4905static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4906{
4907 struct net_device *dev = dev_id;
4908 struct tg3 *tp = netdev_priv(dev);
4909 struct tg3_hw_status *sblk = tp->hw_status;
4910
f9804ddb
MC		 4911 if ((sblk->status & SD_STATUS_UPDATED) ||
4912 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4913 tg3_disable_ints(tp);
7938109f
MC		 4914 return IRQ_RETVAL(1);
4915 }
4916 return IRQ_RETVAL(0);
4917}
4918
8e7a22e3 4919static int tg3_init_hw(struct tg3 *, int);
944d980e 4920static int tg3_halt(struct tg3 *, int, int);
1da177e4 4921
b9ec6c1b
MC		 4922/* Restart hardware after configuration changes, self-test, etc.
4923 * Invoked with tp->lock held.
4924 */
4925static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4926 __releases(tp->lock)
4927 __acquires(tp->lock)
b9ec6c1b
MC		 4928{
4929 int err;
4930
4931 err = tg3_init_hw(tp, reset_phy);
4932 if (err) {
4933 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4934 "aborting.\n", tp->dev->name);
4935 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4936 tg3_full_unlock(tp);
4937 del_timer_sync(&tp->timer);
4938 tp->irq_sync = 0;
bea3348e 4939 napi_enable(&tp->napi);
b9ec6c1b
MC		 4940 dev_close(tp->dev);
4941 tg3_full_lock(tp, 0);
4942 }
4943 return err;
4944}
4945
1da177e4
LT		 4946#ifdef CONFIG_NET_POLL_CONTROLLER
4947static void tg3_poll_controller(struct net_device *dev)
4948{
88b06bc2
MC		 4949 struct tg3 *tp = netdev_priv(dev);
4950
7d12e780 4951 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4952}
4953#endif
4954
c4028958 4955static void tg3_reset_task(struct work_struct *work)
1da177e4 4956{
c4028958 4957 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4958 int err;
1da177e4
LT		 4959 unsigned int restart_timer;
4960
7faa006f 4961 tg3_full_lock(tp, 0);
7faa006f
MC		 4962
4963 if (!netif_running(tp->dev)) {
7faa006f
MC		 4964 tg3_full_unlock(tp);
4965 return;
4966 }
4967
4968 tg3_full_unlock(tp);
4969
b02fd9e3
MC		 4970 tg3_phy_stop(tp);
4971
1da177e4
LT		 4972 tg3_netif_stop(tp);
4973
f47c11ee 4974 tg3_full_lock(tp, 1);
1da177e4
LT		 4975
4976 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4977 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4978
df3e6548
MC		 4979 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4980 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4981 tp->write32_rx_mbox = tg3_write_flush_reg32;
4982 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4983 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4984 }
4985
944d980e 4986 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4987 err = tg3_init_hw(tp, 1);
4988 if (err)
b9ec6c1b 4989 goto out;
1da177e4
LT		 4990
4991 tg3_netif_start(tp);
4992
1da177e4
LT		 4993 if (restart_timer)
4994 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4995
b9ec6c1b 4996out:
7faa006f 4997 tg3_full_unlock(tp);
b02fd9e3
MC		 4998
4999 if (!err)
5000 tg3_phy_start(tp);
1da177e4
LT		 5001}
5002
b0408751
MC		 5003static void tg3_dump_short_state(struct tg3 *tp)
5004{
5005 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5006 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5007 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5008 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5009}
5010
1da177e4
LT		 5011static void tg3_tx_timeout(struct net_device *dev)
5012{
5013 struct tg3 *tp = netdev_priv(dev);
5014
b0408751 5015 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5016 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5017 dev->name);
b0408751
MC		 5018 tg3_dump_short_state(tp);
5019 }
1da177e4
LT		 5020
5021 schedule_work(&tp->reset_task);
5022}
5023
c58ec932
MC		 5024/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5025static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5026{
5027 u32 base = (u32) mapping & 0xffffffff;
5028
5029 return ((base > 0xffffdcc0) &&
5030 (base + len + 8 < base));
5031}
5032
72f2afb8
MC		 5033/* Test for DMA addresses > 40-bit */
5034static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5035 int len)
5036{
5037#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5038 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5039 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5040 return 0;
5041#else
5042 return 0;
5043#endif
5044}
5045
1da177e4
LT		 5046static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5047
72f2afb8
MC		 5048/* Workaround 4GB and 40-bit hardware DMA bugs. */
5049static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5050 u32 last_plus_one, u32 *start,
5051 u32 base_flags, u32 mss)
1da177e4 5052{
41588ba1 5053 struct sk_buff *new_skb;
c58ec932 5054 dma_addr_t new_addr = 0;
1da177e4 5055 u32 entry = *start;
c58ec932 5056 int i, ret = 0;
1da177e4 5057
41588ba1
MC		 5058 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5059 new_skb = skb_copy(skb, GFP_ATOMIC);
5060 else {
5061 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5062
5063 new_skb = skb_copy_expand(skb,
5064 skb_headroom(skb) + more_headroom,
5065 skb_tailroom(skb), GFP_ATOMIC);
5066 }
5067
1da177e4 5068 if (!new_skb) {
c58ec932
MC		 5069 ret = -1;
5070 } else {
5071 /* New SKB is guaranteed to be linear. */
5072 entry = *start;
90079ce8 5073 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5074 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5075
c58ec932
MC		 5076 /* Make sure new skb does not cross any 4G boundaries.
5077 * Drop the packet if it does.
5078 */
90079ce8 5079 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5080 if (!ret)
5081 skb_dma_unmap(&tp->pdev->dev, new_skb,
5082 DMA_TO_DEVICE);
c58ec932
MC		 5083 ret = -1;
5084 dev_kfree_skb(new_skb);
5085 new_skb = NULL;
5086 } else {
5087 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5088 base_flags, 1 | (mss << 1));
5089 *start = NEXT_TX(entry);
5090 }
1da177e4
LT		 5091 }
5092
1da177e4
LT		 5093 /* Now clean up the sw ring entries. */
5094 i = 0;
5095 while (entry != last_plus_one) {
1da177e4
LT		 5096 if (i == 0) {
5097 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5098 } else {
5099 tp->tx_buffers[entry].skb = NULL;
5100 }
5101 entry = NEXT_TX(entry);
5102 i++;
5103 }
5104
90079ce8 5105 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5106 dev_kfree_skb(skb);
5107
c58ec932 5108 return ret;
1da177e4
LT		 5109}
5110
5111static void tg3_set_txd(struct tg3 *tp, int entry,
5112 dma_addr_t mapping, int len, u32 flags,
5113 u32 mss_and_is_end)
5114{
5115 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5116 int is_end = (mss_and_is_end & 0x1);
5117 u32 mss = (mss_and_is_end >> 1);
5118 u32 vlan_tag = 0;
5119
5120 if (is_end)
5121 flags |= TXD_FLAG_END;
5122 if (flags & TXD_FLAG_VLAN) {
5123 vlan_tag = flags >> 16;
5124 flags &= 0xffff;
5125 }
5126 vlan_tag |= (mss << TXD_MSS_SHIFT);
5127
5128 txd->addr_hi = ((u64) mapping >> 32);
5129 txd->addr_lo = ((u64) mapping & 0xffffffff);
5130 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5131 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5132}
5133
5a6f3074
MC		 5134/* hard_start_xmit for devices that don't have any bugs and
5135 * support TG3_FLG2_HW_TSO_2 only.
5136 */
1da177e4 5137static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5138{
5139 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5140 u32 len, entry, base_flags, mss;
90079ce8
DM		 5141 struct skb_shared_info *sp;
5142 dma_addr_t mapping;
5a6f3074
MC		 5143
5144 len = skb_headlen(skb);
5145
00b70504 5146 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5147 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5148 * interrupt. Furthermore, IRQ processing runs lockless so we have
5149 * no IRQ context deadlocks to worry about either. Rejoice!
5150 */
1b2a7205 5151 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5152 if (!netif_queue_stopped(dev)) {
5153 netif_stop_queue(dev);
5154
5155 /* This is a hard error, log it. */
5156 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5157 "queue awake!\n", dev->name);
5158 }
5a6f3074
MC		 5159 return NETDEV_TX_BUSY;
5160 }
5161
5162 entry = tp->tx_prod;
5163 base_flags = 0;
5a6f3074 5164 mss = 0;
c13e3713 5165 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5166 int tcp_opt_len, ip_tcp_len;
5167
5168 if (skb_header_cloned(skb) &&
5169 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5170 dev_kfree_skb(skb);
5171 goto out_unlock;
5172 }
5173
b0026624
MC		 5174 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5175 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5176 else {
eddc9ec5
ACM		 5177 struct iphdr *iph = ip_hdr(skb);
5178
ab6a5bb6 5179 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5180 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5181
eddc9ec5
ACM		 5182 iph->check = 0;
5183 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5184 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5185 }
5a6f3074
MC		 5186
5187 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5188 TXD_FLAG_CPU_POST_DMA);
5189
aa8223c7 5190 tcp_hdr(skb)->check = 0;
5a6f3074 5191
5a6f3074 5192 }
84fa7933 5193 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5194 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5195#if TG3_VLAN_TAG_USED
5196 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5197 base_flags |= (TXD_FLAG_VLAN |
5198 (vlan_tx_tag_get(skb) << 16));
5199#endif
5200
90079ce8
DM		 5201 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5202 dev_kfree_skb(skb);
5203 goto out_unlock;
5204 }
5205
5206 sp = skb_shinfo(skb);
5207
042a53a9 5208 mapping = sp->dma_head;
5a6f3074
MC		 5209
5210 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5211
5212 tg3_set_txd(tp, entry, mapping, len, base_flags,
5213 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5214
5215 entry = NEXT_TX(entry);
5216
5217 /* Now loop through additional data fragments, and queue them. */
5218 if (skb_shinfo(skb)->nr_frags > 0) {
5219 unsigned int i, last;
5220
5221 last = skb_shinfo(skb)->nr_frags - 1;
5222 for (i = 0; i <= last; i++) {
5223 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5224
5225 len = frag->size;
042a53a9 5226 mapping = sp->dma_maps[i];
5a6f3074 5227 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5228
5229 tg3_set_txd(tp, entry, mapping, len,
5230 base_flags, (i == last) | (mss << 1));
5231
5232 entry = NEXT_TX(entry);
5233 }
5234 }
5235
5236 /* Packets are ready, update Tx producer idx local and on card. */
5237 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5238
5239 tp->tx_prod = entry;
1b2a7205 5240 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5241 netif_stop_queue(dev);
42952231 5242 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5243 netif_wake_queue(tp->dev);
5244 }
5245
5246out_unlock:
cdd0db05 5247 mmiowb();
5a6f3074
MC		 5248
5249 return NETDEV_TX_OK;
5250}
5251
52c0fd83
MC		 5252static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5253
5254/* Use GSO to workaround a rare TSO bug that may be triggered when the
5255 * TSO header is greater than 80 bytes.
5256 */
5257static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5258{
5259 struct sk_buff *segs, *nskb;
5260
5261 /* Estimate the number of fragments in the worst case */
1b2a7205 5262 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5263 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5264 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5265 return NETDEV_TX_BUSY;
5266
5267 netif_wake_queue(tp->dev);
52c0fd83
MC		 5268 }
5269
5270 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5271 if (IS_ERR(segs))
52c0fd83
MC		 5272 goto tg3_tso_bug_end;
5273
5274 do {
5275 nskb = segs;
5276 segs = segs->next;
5277 nskb->next = NULL;
5278 tg3_start_xmit_dma_bug(nskb, tp->dev);
5279 } while (segs);
5280
5281tg3_tso_bug_end:
5282 dev_kfree_skb(skb);
5283
5284 return NETDEV_TX_OK;
5285}
52c0fd83 5286
5a6f3074
MC		 5287/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5288 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5289 */
5290static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5291{
5292 struct tg3 *tp = netdev_priv(dev);
1da177e4 5293 u32 len, entry, base_flags, mss;
90079ce8 5294 struct skb_shared_info *sp;
1da177e4 5295 int would_hit_hwbug;
90079ce8 5296 dma_addr_t mapping;
1da177e4
LT		 5297
5298 len = skb_headlen(skb);
5299
00b70504 5300 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5301 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5302 * interrupt. Furthermore, IRQ processing runs lockless so we have
5303 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5304 */
1b2a7205 5305 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5306 if (!netif_queue_stopped(dev)) {
5307 netif_stop_queue(dev);
5308
5309 /* This is a hard error, log it. */
5310 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5311 "queue awake!\n", dev->name);
5312 }
1da177e4
LT		 5313 return NETDEV_TX_BUSY;
5314 }
5315
5316 entry = tp->tx_prod;
5317 base_flags = 0;
84fa7933 5318 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5319 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5320 mss = 0;
c13e3713 5321 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5322 struct iphdr *iph;
52c0fd83 5323 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5324
5325 if (skb_header_cloned(skb) &&
5326 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5327 dev_kfree_skb(skb);
5328 goto out_unlock;
5329 }
5330
ab6a5bb6 5331 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5332 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5333
52c0fd83
MC		 5334 hdr_len = ip_tcp_len + tcp_opt_len;
5335 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5336 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5337 return (tg3_tso_bug(tp, skb));
5338
1da177e4
LT		 5339 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5340 TXD_FLAG_CPU_POST_DMA);
5341
eddc9ec5
ACM		 5342 iph = ip_hdr(skb);
5343 iph->check = 0;
5344 iph->tot_len = htons(mss + hdr_len);
1da177e4 5345 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5346 tcp_hdr(skb)->check = 0;
1da177e4 5347 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5348 } else
5349 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5350 iph->daddr, 0,
5351 IPPROTO_TCP,
5352 0);
1da177e4
LT		 5353
5354 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5355 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5356 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5357 int tsflags;
5358
eddc9ec5 5359 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5360 mss |= (tsflags << 11);
5361 }
5362 } else {
eddc9ec5 5363 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5364 int tsflags;
5365
eddc9ec5 5366 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5367 base_flags |= tsflags << 12;
5368 }
5369 }
5370 }
1da177e4
LT		 5371#if TG3_VLAN_TAG_USED
5372 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5373 base_flags |= (TXD_FLAG_VLAN |
5374 (vlan_tx_tag_get(skb) << 16));
5375#endif
5376
90079ce8
DM		 5377 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5378 dev_kfree_skb(skb);
5379 goto out_unlock;
5380 }
5381
5382 sp = skb_shinfo(skb);
5383
042a53a9 5384 mapping = sp->dma_head;
1da177e4
LT		 5385
5386 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5387
5388 would_hit_hwbug = 0;
5389
41588ba1
MC		 5390 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5391 would_hit_hwbug = 1;
5392 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5393 would_hit_hwbug = 1;
1da177e4
LT		 5394
5395 tg3_set_txd(tp, entry, mapping, len, base_flags,
5396 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5397
5398 entry = NEXT_TX(entry);
5399
5400 /* Now loop through additional data fragments, and queue them. */
5401 if (skb_shinfo(skb)->nr_frags > 0) {
5402 unsigned int i, last;
5403
5404 last = skb_shinfo(skb)->nr_frags - 1;
5405 for (i = 0; i <= last; i++) {
5406 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5407
5408 len = frag->size;
042a53a9 5409 mapping = sp->dma_maps[i];
1da177e4
LT		 5410
5411 tp->tx_buffers[entry].skb = NULL;
1da177e4 5412
c58ec932
MC		 5413 if (tg3_4g_overflow_test(mapping, len))
5414 would_hit_hwbug = 1;
1da177e4 5415
72f2afb8
MC		 5416 if (tg3_40bit_overflow_test(tp, mapping, len))
5417 would_hit_hwbug = 1;
5418
1da177e4
LT		 5419 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5420 tg3_set_txd(tp, entry, mapping, len,
5421 base_flags, (i == last)|(mss << 1));
5422 else
5423 tg3_set_txd(tp, entry, mapping, len,
5424 base_flags, (i == last));
5425
5426 entry = NEXT_TX(entry);
5427 }
5428 }
5429
5430 if (would_hit_hwbug) {
5431 u32 last_plus_one = entry;
5432 u32 start;
1da177e4 5433
c58ec932
MC		 5434 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5435 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5436
5437 /* If the workaround fails due to memory/mapping
5438 * failure, silently drop this packet.
5439 */
72f2afb8 5440 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5441 &start, base_flags, mss))
1da177e4
LT		 5442 goto out_unlock;
5443
5444 entry = start;
5445 }
5446
5447 /* Packets are ready, update Tx producer idx local and on card. */
5448 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5449
5450 tp->tx_prod = entry;
1b2a7205 5451 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5452 netif_stop_queue(dev);
42952231 5453 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5454 netif_wake_queue(tp->dev);
5455 }
1da177e4
LT		 5456
5457out_unlock:
cdd0db05 5458 mmiowb();
1da177e4
LT		 5459
5460 return NETDEV_TX_OK;
5461}
5462
5463static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5464 int new_mtu)
5465{
5466 dev->mtu = new_mtu;
5467
ef7f5ec0 5468 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5469 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5470 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5471 ethtool_op_set_tso(dev, 0);
5472 }
5473 else
5474 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5475 } else {
a4e2b347 5476 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5477 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5478 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5479 }
1da177e4
LT		 5480}
5481
5482static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5483{
5484 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5485 int err;
1da177e4
LT		 5486
5487 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5488 return -EINVAL;
5489
5490 if (!netif_running(dev)) {
5491 /* We'll just catch it later when the
5492 * device is up'd.
5493 */
5494 tg3_set_mtu(dev, tp, new_mtu);
5495 return 0;
5496 }
5497
b02fd9e3
MC		 5498 tg3_phy_stop(tp);
5499
1da177e4 5500 tg3_netif_stop(tp);
f47c11ee
DM		 5501
5502 tg3_full_lock(tp, 1);
1da177e4 5503
944d980e 5504 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5505
5506 tg3_set_mtu(dev, tp, new_mtu);
5507
b9ec6c1b 5508 err = tg3_restart_hw(tp, 0);
1da177e4 5509
b9ec6c1b
MC		 5510 if (!err)
5511 tg3_netif_start(tp);
1da177e4 5512
f47c11ee 5513 tg3_full_unlock(tp);
1da177e4 5514
b02fd9e3
MC		 5515 if (!err)
5516 tg3_phy_start(tp);
5517
b9ec6c1b 5518 return err;
1da177e4
LT		 5519}
5520
21f581a5
MC		 5521static void tg3_rx_prodring_free(struct tg3 *tp,
5522 struct tg3_rx_prodring_set *tpr)
1da177e4
LT		 5523{
5524 struct ring_info *rxp;
5525 int i;
5526
5527 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5528 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5529
5530 if (rxp->skb == NULL)
5531 continue;
1da177e4 5532
1da177e4
LT		 5533 pci_unmap_single(tp->pdev,
5534 pci_unmap_addr(rxp, mapping),
cf7a7298 5535 tp->rx_pkt_map_sz,
1da177e4
LT		 5536 PCI_DMA_FROMDEVICE);
5537 dev_kfree_skb_any(rxp->skb);
5538 rxp->skb = NULL;
5539 }
5540
cf7a7298
MC		 5541 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5542 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5543 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5544
cf7a7298
MC		 5545 if (rxp->skb == NULL)
5546 continue;
1da177e4 5547
cf7a7298
MC		 5548 pci_unmap_single(tp->pdev,
5549 pci_unmap_addr(rxp, mapping),
5550 TG3_RX_JMB_MAP_SZ,
5551 PCI_DMA_FROMDEVICE);
5552 dev_kfree_skb_any(rxp->skb);
5553 rxp->skb = NULL;
1da177e4 5554 }
1da177e4
LT		 5555 }
5556}
5557
5558/* Initialize tx/rx rings for packet processing.
5559 *
5560 * The chip has been shut down and the driver detached from
5561 * the networking, so no interrupts or new tx packets will
5562 * end up in the driver. tp->{tx,}lock are held and thus
5563 * we may not sleep.
5564 */
21f581a5
MC		 5565static int tg3_rx_prodring_alloc(struct tg3 *tp,
5566 struct tg3_rx_prodring_set *tpr)
1da177e4 5567{
287be12e 5568 u32 i, rx_pkt_dma_sz;
1da177e4 5569
1da177e4 5570 /* Zero out all descriptors. */
21f581a5 5571 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5572
287be12e 5573 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5574 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5575 tp->dev->mtu > ETH_DATA_LEN)
5576 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5577 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5578
1da177e4
LT		 5579 /* Initialize invariants of the rings, we only set this
5580 * stuff once. This works because the card does not
5581 * write into the rx buffer posting rings.
5582 */
5583 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5584 struct tg3_rx_buffer_desc *rxd;
5585
21f581a5 5586 rxd = &tpr->rx_std[i];
287be12e 5587 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5588 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5589 rxd->opaque = (RXD_OPAQUE_RING_STD |
5590 (i << RXD_OPAQUE_INDEX_SHIFT));
5591 }
5592
1da177e4
LT		 5593 /* Now allocate fresh SKBs for each rx ring. */
5594 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5595 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5596 printk(KERN_WARNING PFX
5597 "%s: Using a smaller RX standard ring, "
5598 "only %d out of %d buffers were allocated "
5599 "successfully.\n",
5600 tp->dev->name, i, tp->rx_pending);
5601 if (i == 0)
cf7a7298 5602 goto initfail;
32d8c572 5603 tp->rx_pending = i;
1da177e4 5604 break;
32d8c572 5605 }
1da177e4
LT		 5606 }
5607
cf7a7298
MC		 5608 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5609 goto done;
5610
21f581a5 5611 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5612
0f893dc6 5613 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5614 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5615 struct tg3_rx_buffer_desc *rxd;
5616
79ed5ac7 5617 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5618 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5619 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5620 RXD_FLAG_JUMBO;
5621 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5622 (i << RXD_OPAQUE_INDEX_SHIFT));
5623 }
5624
1da177e4
LT		 5625 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5626 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5627 -1, i) < 0) {
5628 printk(KERN_WARNING PFX
5629 "%s: Using a smaller RX jumbo ring, "
5630 "only %d out of %d buffers were "
5631 "allocated successfully.\n",
5632 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5633 if (i == 0)
5634 goto initfail;
32d8c572 5635 tp->rx_jumbo_pending = i;
1da177e4 5636 break;
32d8c572 5637 }
1da177e4
LT		 5638 }
5639 }
cf7a7298
MC		 5640
5641done:
32d8c572 5642 return 0;
cf7a7298
MC		 5643
5644initfail:
21f581a5 5645 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5646 return -ENOMEM;
1da177e4
LT		 5647}
5648
21f581a5
MC		 5649static void tg3_rx_prodring_fini(struct tg3 *tp,
5650 struct tg3_rx_prodring_set *tpr)
1da177e4 5651{
21f581a5
MC		 5652 kfree(tpr->rx_std_buffers);
5653 tpr->rx_std_buffers = NULL;
5654 kfree(tpr->rx_jmb_buffers);
5655 tpr->rx_jmb_buffers = NULL;
5656 if (tpr->rx_std) {
1da177e4 5657 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5658 tpr->rx_std, tpr->rx_std_mapping);
5659 tpr->rx_std = NULL;
1da177e4 5660 }
21f581a5 5661 if (tpr->rx_jmb) {
1da177e4 5662 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5663 tpr->rx_jmb, tpr->rx_jmb_mapping);
5664 tpr->rx_jmb = NULL;
1da177e4 5665 }
cf7a7298
MC		 5666}
5667
21f581a5
MC		 5668static int tg3_rx_prodring_init(struct tg3 *tp,
5669 struct tg3_rx_prodring_set *tpr)
cf7a7298 5670{
21f581a5
MC		 5671 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5672 TG3_RX_RING_SIZE, GFP_KERNEL);
5673 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5674 return -ENOMEM;
5675
21f581a5
MC		 5676 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5677 &tpr->rx_std_mapping);
5678 if (!tpr->rx_std)
cf7a7298
MC		 5679 goto err_out;
5680
5681 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5682 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5683 TG3_RX_JUMBO_RING_SIZE,
5684 GFP_KERNEL);
5685 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5686 goto err_out;
5687
21f581a5
MC		 5688 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5689 TG3_RX_JUMBO_RING_BYTES,
5690 &tpr->rx_jmb_mapping);
5691 if (!tpr->rx_jmb)
cf7a7298
MC		 5692 goto err_out;
5693 }
5694
5695 return 0;
5696
5697err_out:
21f581a5 5698 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5699 return -ENOMEM;
5700}
5701
5702/* Free up pending packets in all rx/tx rings.
5703 *
5704 * The chip has been shut down and the driver detached from
5705 * the networking, so no interrupts or new tx packets will
5706 * end up in the driver. tp->{tx,}lock is not held and we are not
5707 * in an interrupt context and thus may sleep.
5708 */
5709static void tg3_free_rings(struct tg3 *tp)
5710{
5711 int i;
5712
5713 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5714 struct tx_ring_info *txp;
5715 struct sk_buff *skb;
5716
5717 txp = &tp->tx_buffers[i];
5718 skb = txp->skb;
5719
5720 if (skb == NULL) {
5721 i++;
5722 continue;
5723 }
5724
5725 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5726
5727 txp->skb = NULL;
5728
5729 i += skb_shinfo(skb)->nr_frags + 1;
5730
5731 dev_kfree_skb_any(skb);
5732 }
5733
21f581a5 5734 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5735}
5736
5737/* Initialize tx/rx rings for packet processing.
5738 *
5739 * The chip has been shut down and the driver detached from
5740 * the networking, so no interrupts or new tx packets will
5741 * end up in the driver. tp->{tx,}lock are held and thus
5742 * we may not sleep.
5743 */
5744static int tg3_init_rings(struct tg3 *tp)
5745{
5746 /* Free up all the SKBs. */
5747 tg3_free_rings(tp);
5748
5749 /* Zero out all descriptors. */
5750 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5751 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5752
21f581a5 5753 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5754}
5755
5756/*
5757 * Must not be invoked with interrupt sources disabled and
5758 * the hardware shutdown down.
5759 */
5760static void tg3_free_consistent(struct tg3 *tp)
5761{
5762 kfree(tp->tx_buffers);
5763 tp->tx_buffers = NULL;
1da177e4
LT		 5764 if (tp->rx_rcb) {
5765 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5766 tp->rx_rcb, tp->rx_rcb_mapping);
5767 tp->rx_rcb = NULL;
5768 }
5769 if (tp->tx_ring) {
5770 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5771 tp->tx_ring, tp->tx_desc_mapping);
5772 tp->tx_ring = NULL;
5773 }
5774 if (tp->hw_status) {
5775 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5776 tp->hw_status, tp->status_mapping);
5777 tp->hw_status = NULL;
5778 }
5779 if (tp->hw_stats) {
5780 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5781 tp->hw_stats, tp->stats_mapping);
5782 tp->hw_stats = NULL;
5783 }
21f581a5 5784 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5785}
5786
5787/*
5788 * Must not be invoked with interrupt sources disabled and
5789 * the hardware shutdown down. Can sleep.
5790 */
5791static int tg3_alloc_consistent(struct tg3 *tp)
5792{
21f581a5 5793 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5794 return -ENOMEM;
5795
cf7a7298
MC		 5796 tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5797 TG3_TX_RING_SIZE, GFP_KERNEL);
5798 if (!tp->tx_buffers)
1da177e4
LT		 5799 goto err_out;
5800
5801 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5802 &tp->rx_rcb_mapping);
5803 if (!tp->rx_rcb)
5804 goto err_out;
5805
5806 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5807 &tp->tx_desc_mapping);
5808 if (!tp->tx_ring)
5809 goto err_out;
5810
5811 tp->hw_status = pci_alloc_consistent(tp->pdev,
5812 TG3_HW_STATUS_SIZE,
5813 &tp->status_mapping);
5814 if (!tp->hw_status)
5815 goto err_out;
5816
5817 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5818 sizeof(struct tg3_hw_stats),
5819 &tp->stats_mapping);
5820 if (!tp->hw_stats)
5821 goto err_out;
5822
5823 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5824 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5825
5826 return 0;
5827
5828err_out:
5829 tg3_free_consistent(tp);
5830 return -ENOMEM;
5831}
5832
5833#define MAX_WAIT_CNT 1000
5834
5835/* To stop a block, clear the enable bit and poll till it
5836 * clears. tp->lock is held.
5837 */
b3b7d6be 5838static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5839{
5840 unsigned int i;
5841 u32 val;
5842
5843 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5844 switch (ofs) {
5845 case RCVLSC_MODE:
5846 case DMAC_MODE:
5847 case MBFREE_MODE:
5848 case BUFMGR_MODE:
5849 case MEMARB_MODE:
5850 /* We can't enable/disable these bits of the
5851 * 5705/5750, just say success.
5852 */
5853 return 0;
5854
5855 default:
5856 break;
855e1111 5857 }
1da177e4
LT		 5858 }
5859
5860 val = tr32(ofs);
5861 val &= ~enable_bit;
5862 tw32_f(ofs, val);
5863
5864 for (i = 0; i < MAX_WAIT_CNT; i++) {
5865 udelay(100);
5866 val = tr32(ofs);
5867 if ((val & enable_bit) == 0)
5868 break;
5869 }
5870
b3b7d6be 5871 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5872 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5873 "ofs=%lx enable_bit=%x\n",
5874 ofs, enable_bit);
5875 return -ENODEV;
5876 }
5877
5878 return 0;
5879}
5880
5881/* tp->lock is held. */
b3b7d6be 5882static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5883{
5884 int i, err;
5885
5886 tg3_disable_ints(tp);
5887
5888 tp->rx_mode &= ~RX_MODE_ENABLE;
5889 tw32_f(MAC_RX_MODE, tp->rx_mode);
5890 udelay(10);
5891
b3b7d6be
DM		 5892 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5893 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5894 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5895 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5896 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5897 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5898
5899 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5900 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5901 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5902 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5903 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5904 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5905 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5906
5907 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5908 tw32_f(MAC_MODE, tp->mac_mode);
5909 udelay(40);
5910
5911 tp->tx_mode &= ~TX_MODE_ENABLE;
5912 tw32_f(MAC_TX_MODE, tp->tx_mode);
5913
5914 for (i = 0; i < MAX_WAIT_CNT; i++) {
5915 udelay(100);
5916 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5917 break;
5918 }
5919 if (i >= MAX_WAIT_CNT) {
5920 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5921 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5922 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5923 err |= -ENODEV;
1da177e4
LT		 5924 }
5925
e6de8ad1 5926 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5927 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5928 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5929
5930 tw32(FTQ_RESET, 0xffffffff);
5931 tw32(FTQ_RESET, 0x00000000);
5932
b3b7d6be
DM		 5933 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5934 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5935
5936 if (tp->hw_status)
5937 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5938 if (tp->hw_stats)
5939 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5940
1da177e4
LT		 5941 return err;
5942}
5943
0d3031d9
MC		 5944static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5945{
5946 int i;
5947 u32 apedata;
5948
5949 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5950 if (apedata != APE_SEG_SIG_MAGIC)
5951 return;
5952
5953 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5954 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5955 return;
5956
5957 /* Wait for up to 1 millisecond for APE to service previous event. */
5958 for (i = 0; i < 10; i++) {
5959 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5960 return;
5961
5962 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5963
5964 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5965 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5966 event | APE_EVENT_STATUS_EVENT_PENDING);
5967
5968 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5969
5970 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5971 break;
5972
5973 udelay(100);
5974 }
5975
5976 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5977 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5978}
5979
5980static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5981{
5982 u32 event;
5983 u32 apedata;
5984
5985 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5986 return;
5987
5988 switch (kind) {
5989 case RESET_KIND_INIT:
5990 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5991 APE_HOST_SEG_SIG_MAGIC);
5992 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5993 APE_HOST_SEG_LEN_MAGIC);
5994 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5995 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5996 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5997 APE_HOST_DRIVER_ID_MAGIC);
5998 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5999 APE_HOST_BEHAV_NO_PHYLOCK);
6000
6001 event = APE_EVENT_STATUS_STATE_START;
6002 break;
6003 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6004 /* With the interface we are currently using,
6005 * APE does not track driver state. Wiping
6006 * out the HOST SEGMENT SIGNATURE forces
6007 * the APE to assume OS absent status.
6008 */
6009 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6010
0d3031d9
MC		 6011 event = APE_EVENT_STATUS_STATE_UNLOAD;
6012 break;
6013 case RESET_KIND_SUSPEND:
6014 event = APE_EVENT_STATUS_STATE_SUSPEND;
6015 break;
6016 default:
6017 return;
6018 }
6019
6020 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6021
6022 tg3_ape_send_event(tp, event);
6023}
6024
1da177e4
LT		 6025/* tp->lock is held. */
6026static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6027{
f49639e6
DM		 6028 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6029 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6030
6031 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6032 switch (kind) {
6033 case RESET_KIND_INIT:
6034 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6035 DRV_STATE_START);
6036 break;
6037
6038 case RESET_KIND_SHUTDOWN:
6039 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6040 DRV_STATE_UNLOAD);
6041 break;
6042
6043 case RESET_KIND_SUSPEND:
6044 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6045 DRV_STATE_SUSPEND);
6046 break;
6047
6048 default:
6049 break;
855e1111 6050 }
1da177e4 6051 }
0d3031d9
MC		 6052
6053 if (kind == RESET_KIND_INIT ||
6054 kind == RESET_KIND_SUSPEND)
6055 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6056}
6057
6058/* tp->lock is held. */
6059static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6060{
6061 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6062 switch (kind) {
6063 case RESET_KIND_INIT:
6064 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6065 DRV_STATE_START_DONE);
6066 break;
6067
6068 case RESET_KIND_SHUTDOWN:
6069 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6070 DRV_STATE_UNLOAD_DONE);
6071 break;
6072
6073 default:
6074 break;
855e1111 6075 }
1da177e4 6076 }
0d3031d9
MC		 6077
6078 if (kind == RESET_KIND_SHUTDOWN)
6079 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6080}
6081
6082/* tp->lock is held. */
6083static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6084{
6085 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6086 switch (kind) {
6087 case RESET_KIND_INIT:
6088 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6089 DRV_STATE_START);
6090 break;
6091
6092 case RESET_KIND_SHUTDOWN:
6093 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6094 DRV_STATE_UNLOAD);
6095 break;
6096
6097 case RESET_KIND_SUSPEND:
6098 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6099 DRV_STATE_SUSPEND);
6100 break;
6101
6102 default:
6103 break;
855e1111 6104 }
1da177e4
LT		 6105 }
6106}
6107
7a6f4369
MC		 6108static int tg3_poll_fw(struct tg3 *tp)
6109{
6110 int i;
6111 u32 val;
6112
b5d3772c 6113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6114 /* Wait up to 20ms for init done. */
6115 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6116 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6117 return 0;
0ccead18 6118 udelay(100);
b5d3772c
MC		 6119 }
6120 return -ENODEV;
6121 }
6122
7a6f4369
MC		 6123 /* Wait for firmware initialization to complete. */
6124 for (i = 0; i < 100000; i++) {
6125 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6126 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6127 break;
6128 udelay(10);
6129 }
6130
6131 /* Chip might not be fitted with firmware. Some Sun onboard
6132 * parts are configured like that. So don't signal the timeout
6133 * of the above loop as an error, but do report the lack of
6134 * running firmware once.
6135 */
6136 if (i >= 100000 &&
6137 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6138 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6139
6140 printk(KERN_INFO PFX "%s: No firmware running.\n",
6141 tp->dev->name);
6142 }
6143
6144 return 0;
6145}
6146
ee6a99b5
MC		 6147/* Save PCI command register before chip reset */
6148static void tg3_save_pci_state(struct tg3 *tp)
6149{
8a6eac90 6150 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6151}
6152
6153/* Restore PCI state after chip reset */
6154static void tg3_restore_pci_state(struct tg3 *tp)
6155{
6156 u32 val;
6157
6158 /* Re-enable indirect register accesses. */
6159 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6160 tp->misc_host_ctrl);
6161
6162 /* Set MAX PCI retry to zero. */
6163 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6164 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6165 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6166 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6167 /* Allow reads and writes to the APE register and memory space. */
6168 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6169 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6170 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6171 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6172
8a6eac90 6173 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6174
fcb389df
MC		 6175 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6176 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6177 pcie_set_readrq(tp->pdev, 4096);
6178 else {
6179 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6180 tp->pci_cacheline_sz);
6181 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6182 tp->pci_lat_timer);
6183 }
114342f2 6184 }
5f5c51e3 6185
ee6a99b5 6186 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6187 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6188 u16 pcix_cmd;
6189
6190 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6191 &pcix_cmd);
6192 pcix_cmd &= ~PCI_X_CMD_ERO;
6193 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6194 pcix_cmd);
6195 }
ee6a99b5
MC		 6196
6197 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6198
6199 /* Chip reset on 5780 will reset MSI enable bit,
6200 * so need to restore it.
6201 */
6202 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6203 u16 ctrl;
6204
6205 pci_read_config_word(tp->pdev,
6206 tp->msi_cap + PCI_MSI_FLAGS,
6207 &ctrl);
6208 pci_write_config_word(tp->pdev,
6209 tp->msi_cap + PCI_MSI_FLAGS,
6210 ctrl | PCI_MSI_FLAGS_ENABLE);
6211 val = tr32(MSGINT_MODE);
6212 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6213 }
6214 }
6215}
6216
1da177e4
LT		 6217static void tg3_stop_fw(struct tg3 *);
6218
6219/* tp->lock is held. */
6220static int tg3_chip_reset(struct tg3 *tp)
6221{
6222 u32 val;
1ee582d8 6223 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6224 int err;
1da177e4 6225
f49639e6
DM		 6226 tg3_nvram_lock(tp);
6227
158d7abd
MC		 6228 tg3_mdio_stop(tp);
6229
77b483f1
MC		 6230 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6231
f49639e6
DM		 6232 /* No matching tg3_nvram_unlock() after this because
6233 * chip reset below will undo the nvram lock.
6234 */
6235 tp->nvram_lock_cnt = 0;
1da177e4 6236
ee6a99b5
MC		 6237 /* GRC_MISC_CFG core clock reset will clear the memory
6238 * enable bit in PCI register 4 and the MSI enable bit
6239 * on some chips, so we save relevant registers here.
6240 */
6241 tg3_save_pci_state(tp);
6242
d9ab5ad1 6243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6244 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6245 tw32(GRC_FASTBOOT_PC, 0);
6246
1da177e4
LT		 6247 /*
6248 * We must avoid the readl() that normally takes place.
6249 * It locks machines, causes machine checks, and other
6250 * fun things. So, temporarily disable the 5701
6251 * hardware workaround, while we do the reset.
6252 */
1ee582d8
MC		 6253 write_op = tp->write32;
6254 if (write_op == tg3_write_flush_reg32)
6255 tp->write32 = tg3_write32;
1da177e4 6256
d18edcb2
MC		 6257 /* Prevent the irq handler from reading or writing PCI registers
6258 * during chip reset when the memory enable bit in the PCI command
6259 * register may be cleared. The chip does not generate interrupt
6260 * at this time, but the irq handler may still be called due to irq
6261 * sharing or irqpoll.
6262 */
6263 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6264 if (tp->hw_status) {
6265 tp->hw_status->status = 0;
6266 tp->hw_status->status_tag = 0;
6267 }
d18edcb2 6268 tp->last_tag = 0;
624f8e50 6269 tp->last_irq_tag = 0;
d18edcb2
MC		 6270 smp_mb();
6271 synchronize_irq(tp->pdev->irq);
6272
255ca311
MC		 6273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6274 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6275 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6276 }
6277
1da177e4
LT		 6278 /* do the reset */
6279 val = GRC_MISC_CFG_CORECLK_RESET;
6280
6281 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6282 if (tr32(0x7e2c) == 0x60) {
6283 tw32(0x7e2c, 0x20);
6284 }
6285 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6286 tw32(GRC_MISC_CFG, (1 << 29));
6287 val |= (1 << 29);
6288 }
6289 }
6290
b5d3772c
MC		 6291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6292 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6293 tw32(GRC_VCPU_EXT_CTRL,
6294 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6295 }
6296
1da177e4
LT		 6297 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6298 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6299 tw32(GRC_MISC_CFG, val);
6300
1ee582d8
MC		 6301 /* restore 5701 hardware bug workaround write method */
6302 tp->write32 = write_op;
1da177e4
LT		 6303
6304 /* Unfortunately, we have to delay before the PCI read back.
6305 * Some 575X chips even will not respond to a PCI cfg access
6306 * when the reset command is given to the chip.
6307 *
6308 * How do these hardware designers expect things to work
6309 * properly if the PCI write is posted for a long period
6310 * of time? It is always necessary to have some method by
6311 * which a register read back can occur to push the write
6312 * out which does the reset.
6313 *
6314 * For most tg3 variants the trick below was working.
6315 * Ho hum...
6316 */
6317 udelay(120);
6318
6319 /* Flush PCI posted writes. The normal MMIO registers
6320 * are inaccessible at this time so this is the only
6321 * way to make this reliably (actually, this is no longer
6322 * the case, see above). I tried to use indirect
6323 * register read/write but this upset some 5701 variants.
6324 */
6325 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6326
6327 udelay(120);
6328
5e7dfd0f 6329 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6330 u16 val16;
6331
1da177e4
LT		 6332 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6333 int i;
6334 u32 cfg_val;
6335
6336 /* Wait for link training to complete. */
6337 for (i = 0; i < 5000; i++)
6338 udelay(100);
6339
6340 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6341 pci_write_config_dword(tp->pdev, 0xc4,
6342 cfg_val | (1 << 15));
6343 }
5e7dfd0f 6344
e7126997
MC		 6345 /* Clear the "no snoop" and "relaxed ordering" bits. */
6346 pci_read_config_word(tp->pdev,
6347 tp->pcie_cap + PCI_EXP_DEVCTL,
6348 &val16);
6349 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6350 PCI_EXP_DEVCTL_NOSNOOP_EN);
6351 /*
6352 * Older PCIe devices only support the 128 byte
6353 * MPS setting. Enforce the restriction.
5e7dfd0f 6354 */
e7126997
MC		 6355 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6357 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6358 pci_write_config_word(tp->pdev,
6359 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6360 val16);
5e7dfd0f
MC		 6361
6362 pcie_set_readrq(tp->pdev, 4096);
6363
6364 /* Clear error status */
6365 pci_write_config_word(tp->pdev,
6366 tp->pcie_cap + PCI_EXP_DEVSTA,
6367 PCI_EXP_DEVSTA_CED |
6368 PCI_EXP_DEVSTA_NFED |
6369 PCI_EXP_DEVSTA_FED |
6370 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6371 }
6372
ee6a99b5 6373 tg3_restore_pci_state(tp);
1da177e4 6374
d18edcb2
MC		 6375 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6376
ee6a99b5
MC		 6377 val = 0;
6378 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6379 val = tr32(MEMARB_MODE);
ee6a99b5 6380 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6381
6382 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6383 tg3_stop_fw(tp);
6384 tw32(0x5000, 0x400);
6385 }
6386
6387 tw32(GRC_MODE, tp->grc_mode);
6388
6389 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6390 val = tr32(0xc4);
1da177e4
LT		 6391
6392 tw32(0xc4, val | (1 << 15));
6393 }
6394
6395 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6397 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6398 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6399 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6400 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6401 }
6402
6403 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6404 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6405 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6406 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6407 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6408 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6409 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6410 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6411 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6412 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6413 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6414 } else
6415 tw32_f(MAC_MODE, 0);
6416 udelay(40);
6417
77b483f1
MC		 6418 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6419
7a6f4369
MC		 6420 err = tg3_poll_fw(tp);
6421 if (err)
6422 return err;
1da177e4 6423
0a9140cf
MC		 6424 tg3_mdio_start(tp);
6425
1da177e4
LT		 6426 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6427 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6428 val = tr32(0x7c00);
1da177e4
LT		 6429
6430 tw32(0x7c00, val | (1 << 25));
6431 }
6432
6433 /* Reprobe ASF enable state. */
6434 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6435 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6436 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6437 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6438 u32 nic_cfg;
6439
6440 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6441 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6442 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6443 tp->last_event_jiffies = jiffies;
cbf46853 6444 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6445 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6446 }
6447 }
6448
6449 return 0;
6450}
6451
6452/* tp->lock is held. */
6453static void tg3_stop_fw(struct tg3 *tp)
6454{
0d3031d9
MC		 6455 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6456 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6457 /* Wait for RX cpu to ACK the previous event. */
6458 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6459
6460 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6461
6462 tg3_generate_fw_event(tp);
1da177e4 6463
7c5026aa
MC		 6464 /* Wait for RX cpu to ACK this event. */
6465 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6466 }
6467}
6468
6469/* tp->lock is held. */
944d980e 6470static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6471{
6472 int err;
6473
6474 tg3_stop_fw(tp);
6475
944d980e 6476 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6477
b3b7d6be 6478 tg3_abort_hw(tp, silent);
1da177e4
LT		 6479 err = tg3_chip_reset(tp);
6480
daba2a63
MC		 6481 __tg3_set_mac_addr(tp, 0);
6482
944d980e
MC		 6483 tg3_write_sig_legacy(tp, kind);
6484 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6485
6486 if (err)
6487 return err;
6488
6489 return 0;
6490}
6491
1da177e4
LT		 6492#define RX_CPU_SCRATCH_BASE 0x30000
6493#define RX_CPU_SCRATCH_SIZE 0x04000
6494#define TX_CPU_SCRATCH_BASE 0x34000
6495#define TX_CPU_SCRATCH_SIZE 0x04000
6496
6497/* tp->lock is held. */
6498static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6499{
6500 int i;
6501
5d9428de
ES		 6502 BUG_ON(offset == TX_CPU_BASE &&
6503 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6504
b5d3772c
MC		 6505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6506 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6507
6508 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6509 return 0;
6510 }
1da177e4
LT		 6511 if (offset == RX_CPU_BASE) {
6512 for (i = 0; i < 10000; i++) {
6513 tw32(offset + CPU_STATE, 0xffffffff);
6514 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6515 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6516 break;
6517 }
6518
6519 tw32(offset + CPU_STATE, 0xffffffff);
6520 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6521 udelay(10);
6522 } else {
6523 for (i = 0; i < 10000; i++) {
6524 tw32(offset + CPU_STATE, 0xffffffff);
6525 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6526 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6527 break;
6528 }
6529 }
6530
6531 if (i >= 10000) {
6532 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6533 "and %s CPU\n",
6534 tp->dev->name,
6535 (offset == RX_CPU_BASE ? "RX" : "TX"));
6536 return -ENODEV;
6537 }
ec41c7df
MC		 6538
6539 /* Clear firmware's nvram arbitration. */
6540 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6541 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6542 return 0;
6543}
6544
6545struct fw_info {
077f849d
JSR		 6546 unsigned int fw_base;
6547 unsigned int fw_len;
6548 const __be32 *fw_data;
1da177e4
LT		 6549};
6550
6551/* tp->lock is held. */
6552static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6553 int cpu_scratch_size, struct fw_info *info)
6554{
ec41c7df 6555 int err, lock_err, i;
1da177e4
LT		 6556 void (*write_op)(struct tg3 *, u32, u32);
6557
6558 if (cpu_base == TX_CPU_BASE &&
6559 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6560 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6561 "TX cpu firmware on %s which is 5705.\n",
6562 tp->dev->name);
6563 return -EINVAL;
6564 }
6565
6566 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6567 write_op = tg3_write_mem;
6568 else
6569 write_op = tg3_write_indirect_reg32;
6570
1b628151
MC		 6571 /* It is possible that bootcode is still loading at this point.
6572 * Get the nvram lock first before halting the cpu.
6573 */
ec41c7df 6574 lock_err = tg3_nvram_lock(tp);
1da177e4 6575 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6576 if (!lock_err)
6577 tg3_nvram_unlock(tp);
1da177e4
LT		 6578 if (err)
6579 goto out;
6580
6581 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6582 write_op(tp, cpu_scratch_base + i, 0);
6583 tw32(cpu_base + CPU_STATE, 0xffffffff);
6584 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6585 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6586 write_op(tp, (cpu_scratch_base +
077f849d 6587 (info->fw_base & 0xffff) +
1da177e4 6588 (i * sizeof(u32))),
077f849d 6589 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6590
6591 err = 0;
6592
6593out:
1da177e4
LT		 6594 return err;
6595}
6596
6597/* tp->lock is held. */
6598static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6599{
6600 struct fw_info info;
077f849d 6601 const __be32 *fw_data;
1da177e4
LT		 6602 int err, i;
6603
077f849d
JSR		 6604 fw_data = (void *)tp->fw->data;
6605
6606 /* Firmware blob starts with version numbers, followed by
6607 start address and length. We are setting complete length.
6608 length = end_address_of_bss - start_address_of_text.
6609 Remainder is the blob to be loaded contiguously
6610 from start address. */
6611
6612 info.fw_base = be32_to_cpu(fw_data[1]);
6613 info.fw_len = tp->fw->size - 12;
6614 info.fw_data = &fw_data[3];
1da177e4
LT		 6615
6616 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6617 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6618 &info);
6619 if (err)
6620 return err;
6621
6622 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6623 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6624 &info);
6625 if (err)
6626 return err;
6627
6628 /* Now startup only the RX cpu. */
6629 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6630 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6631
6632 for (i = 0; i < 5; i++) {
077f849d 6633 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6634 break;
6635 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6636 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6637 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6638 udelay(1000);
6639 }
6640 if (i >= 5) {
6641 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6642 "to set RX CPU PC, is %08x should be %08x\n",
6643 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6644 info.fw_base);
1da177e4
LT		 6645 return -ENODEV;
6646 }
6647 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6648 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6649
6650 return 0;
6651}
6652
1da177e4 6653/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6654
6655/* tp->lock is held. */
6656static int tg3_load_tso_firmware(struct tg3 *tp)
6657{
6658 struct fw_info info;
077f849d 6659 const __be32 *fw_data;
1da177e4
LT		 6660 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6661 int err, i;
6662
6663 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6664 return 0;
6665
077f849d
JSR		 6666 fw_data = (void *)tp->fw->data;
6667
6668 /* Firmware blob starts with version numbers, followed by
6669 start address and length. We are setting complete length.
6670 length = end_address_of_bss - start_address_of_text.
6671 Remainder is the blob to be loaded contiguously
6672 from start address. */
6673
6674 info.fw_base = be32_to_cpu(fw_data[1]);
6675 cpu_scratch_size = tp->fw_len;
6676 info.fw_len = tp->fw->size - 12;
6677 info.fw_data = &fw_data[3];
6678
1da177e4 6679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6680 cpu_base = RX_CPU_BASE;
6681 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6682 } else {
1da177e4
LT		 6683 cpu_base = TX_CPU_BASE;
6684 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6685 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6686 }
6687
6688 err = tg3_load_firmware_cpu(tp, cpu_base,
6689 cpu_scratch_base, cpu_scratch_size,
6690 &info);
6691 if (err)
6692 return err;
6693
6694 /* Now startup the cpu. */
6695 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6696 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6697
6698 for (i = 0; i < 5; i++) {
077f849d 6699 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6700 break;
6701 tw32(cpu_base + CPU_STATE, 0xffffffff);
6702 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6703 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6704 udelay(1000);
6705 }
6706 if (i >= 5) {
6707 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6708 "to set CPU PC, is %08x should be %08x\n",
6709 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6710 info.fw_base);
1da177e4
LT		 6711 return -ENODEV;
6712 }
6713 tw32(cpu_base + CPU_STATE, 0xffffffff);
6714 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6715 return 0;
6716}
6717
1da177e4 6718
1da177e4
LT		 6719static int tg3_set_mac_addr(struct net_device *dev, void *p)
6720{
6721 struct tg3 *tp = netdev_priv(dev);
6722 struct sockaddr *addr = p;
986e0aeb 6723 int err = 0, skip_mac_1 = 0;
1da177e4 6724
f9804ddb
MC		 6725 if (!is_valid_ether_addr(addr->sa_data))
6726 return -EINVAL;
6727
1da177e4
LT		 6728 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6729
e75f7c90
MC		 6730 if (!netif_running(dev))
6731 return 0;
6732
58712ef9 6733 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6734 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6735
986e0aeb
MC		 6736 addr0_high = tr32(MAC_ADDR_0_HIGH);
6737 addr0_low = tr32(MAC_ADDR_0_LOW);
6738 addr1_high = tr32(MAC_ADDR_1_HIGH);
6739 addr1_low = tr32(MAC_ADDR_1_LOW);
6740
6741 /* Skip MAC addr 1 if ASF is using it. */
6742 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6743 !(addr1_high == 0 && addr1_low == 0))
6744 skip_mac_1 = 1;
58712ef9 6745 }
986e0aeb
MC		 6746 spin_lock_bh(&tp->lock);
6747 __tg3_set_mac_addr(tp, skip_mac_1);
6748 spin_unlock_bh(&tp->lock);
1da177e4 6749
b9ec6c1b 6750 return err;
1da177e4
LT		 6751}
6752
6753/* tp->lock is held. */
6754static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6755 dma_addr_t mapping, u32 maxlen_flags,
6756 u32 nic_addr)
6757{
6758 tg3_write_mem(tp,
6759 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6760 ((u64) mapping >> 32));
6761 tg3_write_mem(tp,
6762 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6763 ((u64) mapping & 0xffffffff));
6764 tg3_write_mem(tp,
6765 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6766 maxlen_flags);
6767
6768 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6769 tg3_write_mem(tp,
6770 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6771 nic_addr);
6772}
6773
6774static void __tg3_set_rx_mode(struct net_device *);
d244c892 6775static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6776{
6777 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6778 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6779 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6780 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6781 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6782 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6783 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6784 }
6785 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6786 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6787 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6788 u32 val = ec->stats_block_coalesce_usecs;
6789
6790 if (!netif_carrier_ok(tp->dev))
6791 val = 0;
6792
6793 tw32(HOSTCC_STAT_COAL_TICKS, val);
6794 }
6795}
1da177e4
LT		 6796
6797/* tp->lock is held. */
8e7a22e3 6798static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6799{
6800 u32 val, rdmac_mode;
6801 int i, err, limit;
21f581a5 6802 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 6803
6804 tg3_disable_ints(tp);
6805
6806 tg3_stop_fw(tp);
6807
6808 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6809
6810 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6811 tg3_abort_hw(tp, 1);
1da177e4
LT		 6812 }
6813
dd477003
MC		 6814 if (reset_phy &&
6815 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6816 tg3_phy_reset(tp);
6817
1da177e4
LT		 6818 err = tg3_chip_reset(tp);
6819 if (err)
6820 return err;
6821
6822 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6823
bcb37f6c 6824 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6825 val = tr32(TG3_CPMU_CTRL);
6826 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6827 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6828
6829 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6830 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6831 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6832 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6833
6834 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6835 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6836 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6837 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6838
6839 val = tr32(TG3_CPMU_HST_ACC);
6840 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6841 val |= CPMU_HST_ACC_MACCLK_6_25;
6842 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6843 }
6844
33466d93
MC		 6845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6846 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6847 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6848 PCIE_PWR_MGMT_L1_THRESH_4MS;
6849 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6850
6851 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6852 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6853
6854 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6855 }
6856
255ca311
MC		 6857 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6858 val = tr32(TG3_PCIE_LNKCTL);
6859 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6860 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6861 else
6862 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6863 tw32(TG3_PCIE_LNKCTL, val);
6864 }
6865
1da177e4
LT		 6866 /* This works around an issue with Athlon chipsets on
6867 * B3 tigon3 silicon. This bit has no effect on any
6868 * other revision. But do not set this on PCI Express
795d01c5 6869 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6870 */
795d01c5
MC		 6871 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6872 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6873 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6874 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6875 }
1da177e4
LT		 6876
6877 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6878 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6879 val = tr32(TG3PCI_PCISTATE);
6880 val |= PCISTATE_RETRY_SAME_DMA;
6881 tw32(TG3PCI_PCISTATE, val);
6882 }
6883
0d3031d9
MC		 6884 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6885 /* Allow reads and writes to the
6886 * APE register and memory space.
6887 */
6888 val = tr32(TG3PCI_PCISTATE);
6889 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6890 PCISTATE_ALLOW_APE_SHMEM_WR;
6891 tw32(TG3PCI_PCISTATE, val);
6892 }
6893
1da177e4
LT		 6894 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6895 /* Enable some hw fixes. */
6896 val = tr32(TG3PCI_MSI_DATA);
6897 val |= (1 << 26) | (1 << 28) | (1 << 29);
6898 tw32(TG3PCI_MSI_DATA, val);
6899 }
6900
6901 /* Descriptor ring init may make accesses to the
6902 * NIC SRAM area to setup the TX descriptors, so we
6903 * can only do this after the hardware has been
6904 * successfully reset.
6905 */
32d8c572
MC		 6906 err = tg3_init_rings(tp);
6907 if (err)
6908 return err;
1da177e4 6909
9936bcf6 6910 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6911 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6912 /* This value is determined during the probe time DMA
6913 * engine test, tg3_test_dma.
6914 */
6915 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6916 }
1da177e4
LT		 6917
6918 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6919 GRC_MODE_4X_NIC_SEND_RINGS |
6920 GRC_MODE_NO_TX_PHDR_CSUM |
6921 GRC_MODE_NO_RX_PHDR_CSUM);
6922 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6923
6924 /* Pseudo-header checksum is done by hardware logic and not
6925 * the offload processers, so make the chip do the pseudo-
6926 * header checksums on receive. For transmit it is more
6927 * convenient to do the pseudo-header checksum in software
6928 * as Linux does that on transmit for us in all cases.
6929 */
6930 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6931
6932 tw32(GRC_MODE,
6933 tp->grc_mode |
6934 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6935
6936 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6937 val = tr32(GRC_MISC_CFG);
6938 val &= ~0xff;
6939 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6940 tw32(GRC_MISC_CFG, val);
6941
6942 /* Initialize MBUF/DESC pool. */
cbf46853 6943 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6944 /* Do nothing. */
6945 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6946 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6948 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6949 else
6950 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6951 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6952 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6953 }
1da177e4
LT		 6954 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6955 int fw_len;
6956
077f849d 6957 fw_len = tp->fw_len;
1da177e4
LT		 6958 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6959 tw32(BUFMGR_MB_POOL_ADDR,
6960 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6961 tw32(BUFMGR_MB_POOL_SIZE,
6962 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6963 }
1da177e4 6964
0f893dc6 6965 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6966 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6967 tp->bufmgr_config.mbuf_read_dma_low_water);
6968 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6969 tp->bufmgr_config.mbuf_mac_rx_low_water);
6970 tw32(BUFMGR_MB_HIGH_WATER,
6971 tp->bufmgr_config.mbuf_high_water);
6972 } else {
6973 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6974 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6975 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6976 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6977 tw32(BUFMGR_MB_HIGH_WATER,
6978 tp->bufmgr_config.mbuf_high_water_jumbo);
6979 }
6980 tw32(BUFMGR_DMA_LOW_WATER,
6981 tp->bufmgr_config.dma_low_water);
6982 tw32(BUFMGR_DMA_HIGH_WATER,
6983 tp->bufmgr_config.dma_high_water);
6984
6985 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6986 for (i = 0; i < 2000; i++) {
6987 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6988 break;
6989 udelay(10);
6990 }
6991 if (i >= 2000) {
6992 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6993 tp->dev->name);
6994 return -ENODEV;
6995 }
6996
6997 /* Setup replenish threshold. */
f92905de
MC		 6998 val = tp->rx_pending / 8;
6999 if (val == 0)
7000 val = 1;
7001 else if (val > tp->rx_std_max_post)
7002 val = tp->rx_std_max_post;
b5d3772c
MC		 7003 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7004 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7005 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7006
7007 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7008 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7009 }
f92905de
MC		 7010
7011 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7012
7013 /* Initialize TG3_BDINFO's at:
7014 * RCVDBDI_STD_BD: standard eth size rx ring
7015 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7016 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7017 *
7018 * like so:
7019 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7020 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7021 * ring attribute flags
7022 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7023 *
7024 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7025 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7026 *
7027 * The size of each ring is fixed in the firmware, but the location is
7028 * configurable.
7029 */
7030 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7031 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7032 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7033 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7034 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7035 NIC_SRAM_RX_BUFFER_DESC);
7036
fdb72b38
MC		 7037 /* Disable the mini ring */
7038 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7039 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7040 BDINFO_FLAGS_DISABLED);
7041
fdb72b38
MC		 7042 /* Program the jumbo buffer descriptor ring control
7043 * blocks on those devices that have them.
7044 */
8f666b07 7045 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7046 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7047 /* Setup replenish threshold. */
7048 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7049
0f893dc6 7050 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7051 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7052 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7053 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7054 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7055 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7056 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7057 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7058 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7059 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7060 } else {
7061 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7062 BDINFO_FLAGS_DISABLED);
7063 }
7064
fdb72b38
MC		 7065 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7066 } else
7067 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7068
7069 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4
LT		 7070
7071 /* There is only one send ring on 5705/5750, no need to explicitly
7072 * disable the others.
7073 */
7074 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7075 /* Clear out send RCB ring in SRAM. */
7076 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7077 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7078 BDINFO_FLAGS_DISABLED);
7079 }
7080
7081 tp->tx_prod = 0;
7082 tp->tx_cons = 0;
7083 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7084 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7085
7086 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7087 tp->tx_desc_mapping,
7088 (TG3_TX_RING_SIZE <<
7089 BDINFO_FLAGS_MAXLEN_SHIFT),
7090 NIC_SRAM_TX_BUFFER_DESC);
7091
7092 /* There is only one receive return ring on 5705/5750, no need
7093 * to explicitly disable the others.
7094 */
7095 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7096 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7097 i += TG3_BDINFO_SIZE) {
7098 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7099 BDINFO_FLAGS_DISABLED);
7100 }
7101 }
7102
7103 tp->rx_rcb_ptr = 0;
7104 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7105
7106 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7107 tp->rx_rcb_mapping,
7108 (TG3_RX_RCB_RING_SIZE(tp) <<
7109 BDINFO_FLAGS_MAXLEN_SHIFT),
7110 0);
7111
21f581a5 7112 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7113 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7114 tpr->rx_std_ptr);
1da177e4 7115
21f581a5
MC		 7116 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7117 tp->rx_jumbo_pending : 0;
1da177e4 7118 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7119 tpr->rx_jmb_ptr);
1da177e4
LT		 7120
7121 /* Initialize MAC address and backoff seed. */
986e0aeb 7122 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7123
7124 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7125 tw32(MAC_RX_MTU_SIZE,
7126 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7127
7128 /* The slot time is changed by tg3_setup_phy if we
7129 * run at gigabit with half duplex.
7130 */
7131 tw32(MAC_TX_LENGTHS,
7132 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7133 (6 << TX_LENGTHS_IPG_SHIFT) |
7134 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7135
7136 /* Receive rules. */
7137 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7138 tw32(RCVLPC_CONFIG, 0x0181);
7139
7140 /* Calculate RDMAC_MODE setting early, we need it to determine
7141 * the RCVLPC_STATE_ENABLE mask.
7142 */
7143 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7144 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7145 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7146 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7147 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7148
57e6983c 7149 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7152 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7153 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7154 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7155
85e94ced
MC		 7156 /* If statement applies to 5705 and 5750 PCI devices only */
7157 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7158 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7159 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7160 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7162 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7163 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7164 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7165 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7166 }
7167 }
7168
85e94ced
MC		 7169 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7170 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7171
1da177e4 7172 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7173 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7174
7175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7177 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7178
7179 /* Receive/send statistics. */
1661394e
MC		 7180 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7181 val = tr32(RCVLPC_STATS_ENABLE);
7182 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7183 tw32(RCVLPC_STATS_ENABLE, val);
7184 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7185 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7186 val = tr32(RCVLPC_STATS_ENABLE);
7187 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7188 tw32(RCVLPC_STATS_ENABLE, val);
7189 } else {
7190 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7191 }
7192 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7193 tw32(SNDDATAI_STATSENAB, 0xffffff);
7194 tw32(SNDDATAI_STATSCTRL,
7195 (SNDDATAI_SCTRL_ENABLE |
7196 SNDDATAI_SCTRL_FASTUPD));
7197
7198 /* Setup host coalescing engine. */
7199 tw32(HOSTCC_MODE, 0);
7200 for (i = 0; i < 2000; i++) {
7201 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7202 break;
7203 udelay(10);
7204 }
7205
d244c892 7206 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7207
7208 /* set status block DMA address */
7209 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7210 ((u64) tp->status_mapping >> 32));
7211 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7212 ((u64) tp->status_mapping & 0xffffffff));
7213
7214 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7215 /* Status/statistics block address. See tg3_timer,
7216 * the tg3_periodic_fetch_stats call there, and
7217 * tg3_get_stats to see how this works for 5705/5750 chips.
7218 */
1da177e4
LT		 7219 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7220 ((u64) tp->stats_mapping >> 32));
7221 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7222 ((u64) tp->stats_mapping & 0xffffffff));
7223 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7224 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7225 }
7226
7227 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7228
7229 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7230 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7231 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7232 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7233
7234 /* Clear statistics/status block in chip, and status block in ram. */
7235 for (i = NIC_SRAM_STATS_BLK;
7236 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7237 i += sizeof(u32)) {
7238 tg3_write_mem(tp, i, 0);
7239 udelay(40);
7240 }
7241 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7242
c94e3941
MC		 7243 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7244 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7245 /* reset to prevent losing 1st rx packet intermittently */
7246 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7247 udelay(10);
7248 }
7249
3bda1258
MC		 7250 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7251 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7252 else
7253 tp->mac_mode = 0;
7254 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7255 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7256 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7257 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7258 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7259 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7260 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7261 udelay(40);
7262
314fba34 7263 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7264 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7265 * register to preserve the GPIO settings for LOMs. The GPIOs,
7266 * whether used as inputs or outputs, are set by boot code after
7267 * reset.
7268 */
9d26e213 7269 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7270 u32 gpio_mask;
7271
9d26e213
MC		 7272 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7273 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7274 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7275
7276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7277 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7278 GRC_LCLCTRL_GPIO_OUTPUT3;
7279
af36e6b6
MC		 7280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7281 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7282
aaf84465 7283 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7284 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7285
7286 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7287 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7288 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7289 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7290 }
1da177e4
LT		 7291 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7292 udelay(100);
7293
09ee929c 7294 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
1da177e4
LT		 7295
7296 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7297 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7298 udelay(40);
7299 }
7300
7301 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7302 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7303 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7304 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7305 WDMAC_MODE_LNGREAD_ENAB);
7306
85e94ced
MC		 7307 /* If statement applies to 5705 and 5750 PCI devices only */
7308 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7309 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7311 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7312 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7313 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7314 /* nothing */
7315 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7316 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7317 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7318 val |= WDMAC_MODE_RX_ACCEL;
7319 }
7320 }
7321
d9ab5ad1 7322 /* Enable host coalescing bug fix */
321d32a0 7323 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7324 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7325
1da177e4
LT		 7326 tw32_f(WDMAC_MODE, val);
7327 udelay(40);
7328
9974a356
MC		 7329 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7330 u16 pcix_cmd;
7331
7332 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7333 &pcix_cmd);
1da177e4 7334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7335 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7336 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7337 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7338 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7339 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7340 }
9974a356
MC		 7341 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7342 pcix_cmd);
1da177e4
LT		 7343 }
7344
7345 tw32_f(RDMAC_MODE, rdmac_mode);
7346 udelay(40);
7347
7348 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7349 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7350 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7351
7352 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7353 tw32(SNDDATAC_MODE,
7354 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7355 else
7356 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7357
1da177e4
LT		 7358 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7359 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7360 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7361 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7362 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7363 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7364 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7365 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7366
7367 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7368 err = tg3_load_5701_a0_firmware_fix(tp);
7369 if (err)
7370 return err;
7371 }
7372
1da177e4
LT		 7373 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7374 err = tg3_load_tso_firmware(tp);
7375 if (err)
7376 return err;
7377 }
1da177e4
LT		 7378
7379 tp->tx_mode = TX_MODE_ENABLE;
7380 tw32_f(MAC_TX_MODE, tp->tx_mode);
7381 udelay(100);
7382
7383 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7384 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7385 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7386
1da177e4
LT		 7387 tw32_f(MAC_RX_MODE, tp->rx_mode);
7388 udelay(10);
7389
1da177e4
LT		 7390 tw32(MAC_LED_CTRL, tp->led_ctrl);
7391
7392 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7393 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7394 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7395 udelay(10);
7396 }
7397 tw32_f(MAC_RX_MODE, tp->rx_mode);
7398 udelay(10);
7399
7400 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7401 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7402 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7403 /* Set drive transmission level to 1.2V */
7404 /* only if the signal pre-emphasis bit is not set */
7405 val = tr32(MAC_SERDES_CFG);
7406 val &= 0xfffff000;
7407 val |= 0x880;
7408 tw32(MAC_SERDES_CFG, val);
7409 }
7410 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7411 tw32(MAC_SERDES_CFG, 0x616000);
7412 }
7413
7414 /* Prevent chip from dropping frames when flow control
7415 * is enabled.
7416 */
7417 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7418
7419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7420 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7421 /* Use hardware link auto-negotiation */
7422 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7423 }
7424
d4d2c558
MC		 7425 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7426 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7427 u32 tmp;
7428
7429 tmp = tr32(SERDES_RX_CTRL);
7430 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7431 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7432 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7433 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7434 }
7435
dd477003
MC		 7436 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7437 if (tp->link_config.phy_is_low_power) {
7438 tp->link_config.phy_is_low_power = 0;
7439 tp->link_config.speed = tp->link_config.orig_speed;
7440 tp->link_config.duplex = tp->link_config.orig_duplex;
7441 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7442 }
1da177e4 7443
dd477003
MC		 7444 err = tg3_setup_phy(tp, 0);
7445 if (err)
7446 return err;
1da177e4 7447
dd477003 7448 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7449 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7450 u32 tmp;
7451
7452 /* Clear CRC stats. */
7453 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7454 tg3_writephy(tp, MII_TG3_TEST1,
7455 tmp | MII_TG3_TEST1_CRC_EN);
7456 tg3_readphy(tp, 0x14, &tmp);
7457 }
1da177e4
LT		 7458 }
7459 }
7460
7461 __tg3_set_rx_mode(tp->dev);
7462
7463 /* Initialize receive rules. */
7464 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7465 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7466 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7467 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7468
4cf78e4f 7469 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7470 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7471 limit = 8;
7472 else
7473 limit = 16;
7474 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7475 limit -= 4;
7476 switch (limit) {
7477 case 16:
7478 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7479 case 15:
7480 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7481 case 14:
7482 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7483 case 13:
7484 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7485 case 12:
7486 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7487 case 11:
7488 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7489 case 10:
7490 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7491 case 9:
7492 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7493 case 8:
7494 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7495 case 7:
7496 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7497 case 6:
7498 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7499 case 5:
7500 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7501 case 4:
7502 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7503 case 3:
7504 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7505 case 2:
7506 case 1:
7507
7508 default:
7509 break;
855e1111 7510 }
1da177e4 7511
9ce768ea
MC		 7512 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7513 /* Write our heartbeat update interval to APE. */
7514 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7515 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7516
1da177e4
LT		 7517 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7518
1da177e4
LT		 7519 return 0;
7520}
7521
7522/* Called at device open time to get the chip ready for
7523 * packet processing. Invoked with tp->lock held.
7524 */
8e7a22e3 7525static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7526{
1da177e4
LT		 7527 tg3_switch_clocks(tp);
7528
7529 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7530
2f751b67 7531 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7532}
7533
7534#define TG3_STAT_ADD32(PSTAT, REG) \
7535do { u32 __val = tr32(REG); \
7536 (PSTAT)->low += __val; \
7537 if ((PSTAT)->low < __val) \
7538 (PSTAT)->high += 1; \
7539} while (0)
7540
7541static void tg3_periodic_fetch_stats(struct tg3 *tp)
7542{
7543 struct tg3_hw_stats *sp = tp->hw_stats;
7544
7545 if (!netif_carrier_ok(tp->dev))
7546 return;
7547
7548 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7549 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7550 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7551 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7552 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7553 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7554 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7555 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7556 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7557 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7558 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7559 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7560 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7561
7562 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7563 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7564 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7565 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7566 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7567 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7568 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7569 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7570 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7571 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7572 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7573 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7574 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7575 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7576
7577 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7578 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7579 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7580}
7581
7582static void tg3_timer(unsigned long __opaque)
7583{
7584 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7585
f475f163
MC		 7586 if (tp->irq_sync)
7587 goto restart_timer;
7588
f47c11ee 7589 spin_lock(&tp->lock);
1da177e4 7590
fac9b83e
DM		 7591 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7592 /* All of this garbage is because when using non-tagged
7593 * IRQ status the mailbox/status_block protocol the chip
7594 * uses with the cpu is race prone.
7595 */
7596 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7597 tw32(GRC_LOCAL_CTRL,
7598 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7599 } else {
7600 tw32(HOSTCC_MODE, tp->coalesce_mode |
7601 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7602 }
1da177e4 7603
fac9b83e
DM		 7604 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7605 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7606 spin_unlock(&tp->lock);
fac9b83e
DM		 7607 schedule_work(&tp->reset_task);
7608 return;
7609 }
1da177e4
LT		 7610 }
7611
1da177e4
LT		 7612 /* This part only runs once per second. */
7613 if (!--tp->timer_counter) {
fac9b83e
DM		 7614 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7615 tg3_periodic_fetch_stats(tp);
7616
1da177e4
LT		 7617 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7618 u32 mac_stat;
7619 int phy_event;
7620
7621 mac_stat = tr32(MAC_STATUS);
7622
7623 phy_event = 0;
7624 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7625 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7626 phy_event = 1;
7627 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7628 phy_event = 1;
7629
7630 if (phy_event)
7631 tg3_setup_phy(tp, 0);
7632 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7633 u32 mac_stat = tr32(MAC_STATUS);
7634 int need_setup = 0;
7635
7636 if (netif_carrier_ok(tp->dev) &&
7637 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7638 need_setup = 1;
7639 }
7640 if (! netif_carrier_ok(tp->dev) &&
7641 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7642 MAC_STATUS_SIGNAL_DET))) {
7643 need_setup = 1;
7644 }
7645 if (need_setup) {
3d3ebe74
MC		 7646 if (!tp->serdes_counter) {
7647 tw32_f(MAC_MODE,
7648 (tp->mac_mode &
7649 ~MAC_MODE_PORT_MODE_MASK));
7650 udelay(40);
7651 tw32_f(MAC_MODE, tp->mac_mode);
7652 udelay(40);
7653 }
1da177e4
LT		 7654 tg3_setup_phy(tp, 0);
7655 }
747e8f8b
MC		 7656 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7657 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7658
7659 tp->timer_counter = tp->timer_multiplier;
7660 }
7661
130b8e4d
MC		 7662 /* Heartbeat is only sent once every 2 seconds.
7663 *
7664 * The heartbeat is to tell the ASF firmware that the host
7665 * driver is still alive. In the event that the OS crashes,
7666 * ASF needs to reset the hardware to free up the FIFO space
7667 * that may be filled with rx packets destined for the host.
7668 * If the FIFO is full, ASF will no longer function properly.
7669 *
7670 * Unintended resets have been reported on real time kernels
7671 * where the timer doesn't run on time. Netpoll will also have
7672 * same problem.
7673 *
7674 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7675 * to check the ring condition when the heartbeat is expiring
7676 * before doing the reset. This will prevent most unintended
7677 * resets.
7678 */
1da177e4 7679 if (!--tp->asf_counter) {
bc7959b2
MC		 7680 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7681 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7682 tg3_wait_for_event_ack(tp);
7683
bbadf503 7684 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7685 FWCMD_NICDRV_ALIVE3);
bbadf503 7686 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7687 /* 5 seconds timeout */
bbadf503 7688 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7689
7690 tg3_generate_fw_event(tp);
1da177e4
LT		 7691 }
7692 tp->asf_counter = tp->asf_multiplier;
7693 }
7694
f47c11ee 7695 spin_unlock(&tp->lock);
1da177e4 7696
f475f163 7697restart_timer:
1da177e4
LT		 7698 tp->timer.expires = jiffies + tp->timer_offset;
7699 add_timer(&tp->timer);
7700}
7701
81789ef5 7702static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7703{
7d12e780 7704 irq_handler_t fn;
fcfa0a32
MC		 7705 unsigned long flags;
7706 struct net_device *dev = tp->dev;
7707
7708 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7709 fn = tg3_msi;
7710 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7711 fn = tg3_msi_1shot;
1fb9df5d 7712 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7713 } else {
7714 fn = tg3_interrupt;
7715 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7716 fn = tg3_interrupt_tagged;
1fb9df5d 7717 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7718 }
7719 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7720}
7721
7938109f
MC		 7722static int tg3_test_interrupt(struct tg3 *tp)
7723{
7724 struct net_device *dev = tp->dev;
b16250e3 7725 int err, i, intr_ok = 0;
7938109f 7726
d4bc3927
MC		 7727 if (!netif_running(dev))
7728 return -ENODEV;
7729
7938109f
MC		 7730 tg3_disable_ints(tp);
7731
7732 free_irq(tp->pdev->irq, dev);
7733
7734 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7735 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7736 if (err)
7737 return err;
7738
38f3843e 7739 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7740 tg3_enable_ints(tp);
7741
7742 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7743 HOSTCC_MODE_NOW);
7744
7745 for (i = 0; i < 5; i++) {
b16250e3
MC		 7746 u32 int_mbox, misc_host_ctrl;
7747
09ee929c
MC		 7748 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7749 TG3_64BIT_REG_LOW);
b16250e3
MC		 7750 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7751
7752 if ((int_mbox != 0) ||
7753 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7754 intr_ok = 1;
7938109f 7755 break;
b16250e3
MC		 7756 }
7757
7938109f
MC		 7758 msleep(10);
7759 }
7760
7761 tg3_disable_ints(tp);
7762
7763 free_irq(tp->pdev->irq, dev);
6aa20a22 7764
fcfa0a32 7765 err = tg3_request_irq(tp);
7938109f
MC		 7766
7767 if (err)
7768 return err;
7769
b16250e3 7770 if (intr_ok)
7938109f
MC		 7771 return 0;
7772
7773 return -EIO;
7774}
7775
7776/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7777 * successfully restored
7778 */
7779static int tg3_test_msi(struct tg3 *tp)
7780{
7781 struct net_device *dev = tp->dev;
7782 int err;
7783 u16 pci_cmd;
7784
7785 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7786 return 0;
7787
7788 /* Turn off SERR reporting in case MSI terminates with Master
7789 * Abort.
7790 */
7791 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7792 pci_write_config_word(tp->pdev, PCI_COMMAND,
7793 pci_cmd & ~PCI_COMMAND_SERR);
7794
7795 err = tg3_test_interrupt(tp);
7796
7797 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7798
7799 if (!err)
7800 return 0;
7801
7802 /* other failures */
7803 if (err != -EIO)
7804 return err;
7805
7806 /* MSI test failed, go back to INTx mode */
7807 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7808 "switching to INTx mode. Please report this failure to "
7809 "the PCI maintainer and include system chipset information.\n",
7810 tp->dev->name);
7811
7812 free_irq(tp->pdev->irq, dev);
7813 pci_disable_msi(tp->pdev);
7814
7815 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7816
fcfa0a32 7817 err = tg3_request_irq(tp);
7938109f
MC		 7818 if (err)
7819 return err;
7820
7821 /* Need to reset the chip because the MSI cycle may have terminated
7822 * with Master Abort.
7823 */
f47c11ee 7824 tg3_full_lock(tp, 1);
7938109f 7825
944d980e 7826 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7827 err = tg3_init_hw(tp, 1);
7938109f 7828
f47c11ee 7829 tg3_full_unlock(tp);
7938109f
MC		 7830
7831 if (err)
7832 free_irq(tp->pdev->irq, dev);
7833
7834 return err;
7835}
7836
9e9fd12d
MC		 7837static int tg3_request_firmware(struct tg3 *tp)
7838{
7839 const __be32 *fw_data;
7840
7841 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7842 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7843 tp->dev->name, tp->fw_needed);
7844 return -ENOENT;
7845 }
7846
7847 fw_data = (void *)tp->fw->data;
7848
7849 /* Firmware blob starts with version numbers, followed by
7850 * start address and _full_ length including BSS sections
7851 * (which must be longer than the actual data, of course
7852 */
7853
7854 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7855 if (tp->fw_len < (tp->fw->size - 12)) {
7856 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7857 tp->dev->name, tp->fw_len, tp->fw_needed);
7858 release_firmware(tp->fw);
7859 tp->fw = NULL;
7860 return -EINVAL;
7861 }
7862
7863 /* We no longer need firmware; we have it. */
7864 tp->fw_needed = NULL;
7865 return 0;
7866}
7867
1da177e4
LT		 7868static int tg3_open(struct net_device *dev)
7869{
7870 struct tg3 *tp = netdev_priv(dev);
7871 int err;
7872
9e9fd12d
MC		 7873 if (tp->fw_needed) {
7874 err = tg3_request_firmware(tp);
7875 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7876 if (err)
7877 return err;
7878 } else if (err) {
7879 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7880 tp->dev->name);
7881 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7882 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7883 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7884 tp->dev->name);
7885 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7886 }
7887 }
7888
c49a1561
MC		 7889 netif_carrier_off(tp->dev);
7890
bc1c7567 7891 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7892 if (err)
bc1c7567 7893 return err;
2f751b67
MC		 7894
7895 tg3_full_lock(tp, 0);
bc1c7567 7896
1da177e4
LT		 7897 tg3_disable_ints(tp);
7898 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7899
f47c11ee 7900 tg3_full_unlock(tp);
1da177e4
LT		 7901
7902 /* The placement of this call is tied
7903 * to the setup and use of Host TX descriptors.
7904 */
7905 err = tg3_alloc_consistent(tp);
7906 if (err)
7907 return err;
7908
7544b097 7909 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7910 /* All MSI supporting chips should support tagged
7911 * status. Assert that this is the case.
7912 */
7913 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7914 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7915 "Not using MSI.\n", tp->dev->name);
7916 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7917 u32 msi_mode;
7918
7919 msi_mode = tr32(MSGINT_MODE);
7920 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7921 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7922 }
7923 }
fcfa0a32 7924 err = tg3_request_irq(tp);
1da177e4
LT		 7925
7926 if (err) {
88b06bc2
MC		 7927 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7928 pci_disable_msi(tp->pdev);
7929 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7930 }
1da177e4
LT		 7931 tg3_free_consistent(tp);
7932 return err;
7933 }
7934
bea3348e
SH		 7935 napi_enable(&tp->napi);
7936
f47c11ee 7937 tg3_full_lock(tp, 0);
1da177e4 7938
8e7a22e3 7939 err = tg3_init_hw(tp, 1);
1da177e4 7940 if (err) {
944d980e 7941 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7942 tg3_free_rings(tp);
7943 } else {
fac9b83e
DM		 7944 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7945 tp->timer_offset = HZ;
7946 else
7947 tp->timer_offset = HZ / 10;
7948
7949 BUG_ON(tp->timer_offset > HZ);
7950 tp->timer_counter = tp->timer_multiplier =
7951 (HZ / tp->timer_offset);
7952 tp->asf_counter = tp->asf_multiplier =
28fbef78 7953 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7954
7955 init_timer(&tp->timer);
7956 tp->timer.expires = jiffies + tp->timer_offset;
7957 tp->timer.data = (unsigned long) tp;
7958 tp->timer.function = tg3_timer;
1da177e4
LT		 7959 }
7960
f47c11ee 7961 tg3_full_unlock(tp);
1da177e4
LT		 7962
7963 if (err) {
bea3348e 7964 napi_disable(&tp->napi);
88b06bc2
MC		 7965 free_irq(tp->pdev->irq, dev);
7966 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7967 pci_disable_msi(tp->pdev);
7968 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7969 }
1da177e4
LT		 7970 tg3_free_consistent(tp);
7971 return err;
7972 }
7973
7938109f
MC		 7974 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7975 err = tg3_test_msi(tp);
fac9b83e 7976
7938109f 7977 if (err) {
f47c11ee 7978 tg3_full_lock(tp, 0);
7938109f
MC		 7979
7980 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7981 pci_disable_msi(tp->pdev);
7982 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7983 }
944d980e 7984 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7985 tg3_free_rings(tp);
7986 tg3_free_consistent(tp);
7987
f47c11ee 7988 tg3_full_unlock(tp);
7938109f 7989
bea3348e
SH		 7990 napi_disable(&tp->napi);
7991
7938109f
MC		 7992 return err;
7993 }
fcfa0a32
MC		 7994
7995 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7996 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7997 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7998
b5d3772c
MC		 7999 tw32(PCIE_TRANSACTION_CFG,
8000 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 8001 }
8002 }
7938109f
MC		 8003 }
8004
b02fd9e3
MC		 8005 tg3_phy_start(tp);
8006
f47c11ee 8007 tg3_full_lock(tp, 0);
1da177e4 8008
7938109f
MC		 8009 add_timer(&tp->timer);
8010 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8011 tg3_enable_ints(tp);
8012
f47c11ee 8013 tg3_full_unlock(tp);
1da177e4
LT		 8014
8015 netif_start_queue(dev);
8016
8017 return 0;
8018}
8019
8020#if 0
8021/*static*/ void tg3_dump_state(struct tg3 *tp)
8022{
8023 u32 val32, val32_2, val32_3, val32_4, val32_5;
8024 u16 val16;
8025 int i;
8026
8027 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8028 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8029 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8030 val16, val32);
8031
8032 /* MAC block */
8033 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8034 tr32(MAC_MODE), tr32(MAC_STATUS));
8035 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8036 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8037 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8038 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8039 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8040 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8041
8042 /* Send data initiator control block */
8043 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8044 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8045 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8046 tr32(SNDDATAI_STATSCTRL));
8047
8048 /* Send data completion control block */
8049 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8050
8051 /* Send BD ring selector block */
8052 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8053 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8054
8055 /* Send BD initiator control block */
8056 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8057 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8058
8059 /* Send BD completion control block */
8060 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8061
8062 /* Receive list placement control block */
8063 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8064 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8065 printk(" RCVLPC_STATSCTRL[%08x]\n",
8066 tr32(RCVLPC_STATSCTRL));
8067
8068 /* Receive data and receive BD initiator control block */
8069 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8070 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8071
8072 /* Receive data completion control block */
8073 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8074 tr32(RCVDCC_MODE));
8075
8076 /* Receive BD initiator control block */
8077 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8078 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8079
8080 /* Receive BD completion control block */
8081 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8082 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8083
8084 /* Receive list selector control block */
8085 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8086 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8087
8088 /* Mbuf cluster free block */
8089 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8090 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8091
8092 /* Host coalescing control block */
8093 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8094 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8095 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8096 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8097 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8098 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8099 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8100 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8101 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8102 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8103 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8104 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8105
8106 /* Memory arbiter control block */
8107 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8108 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8109
8110 /* Buffer manager control block */
8111 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8112 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8113 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8114 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8115 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8116 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8117 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8118 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8119
8120 /* Read DMA control block */
8121 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8122 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8123
8124 /* Write DMA control block */
8125 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8126 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8127
8128 /* DMA completion block */
8129 printk("DEBUG: DMAC_MODE[%08x]\n",
8130 tr32(DMAC_MODE));
8131
8132 /* GRC block */
8133 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8134 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8135 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8136 tr32(GRC_LOCAL_CTRL));
8137
8138 /* TG3_BDINFOs */
8139 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8140 tr32(RCVDBDI_JUMBO_BD + 0x0),
8141 tr32(RCVDBDI_JUMBO_BD + 0x4),
8142 tr32(RCVDBDI_JUMBO_BD + 0x8),
8143 tr32(RCVDBDI_JUMBO_BD + 0xc));
8144 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8145 tr32(RCVDBDI_STD_BD + 0x0),
8146 tr32(RCVDBDI_STD_BD + 0x4),
8147 tr32(RCVDBDI_STD_BD + 0x8),
8148 tr32(RCVDBDI_STD_BD + 0xc));
8149 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8150 tr32(RCVDBDI_MINI_BD + 0x0),
8151 tr32(RCVDBDI_MINI_BD + 0x4),
8152 tr32(RCVDBDI_MINI_BD + 0x8),
8153 tr32(RCVDBDI_MINI_BD + 0xc));
8154
8155 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8156 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8157 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8158 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8159 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8160 val32, val32_2, val32_3, val32_4);
8161
8162 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8163 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8164 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8165 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8166 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8167 val32, val32_2, val32_3, val32_4);
8168
8169 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8170 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8171 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8172 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8173 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8174 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8175 val32, val32_2, val32_3, val32_4, val32_5);
8176
8177 /* SW status block */
8178 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8179 tp->hw_status->status,
8180 tp->hw_status->status_tag,
8181 tp->hw_status->rx_jumbo_consumer,
8182 tp->hw_status->rx_consumer,
8183 tp->hw_status->rx_mini_consumer,
8184 tp->hw_status->idx[0].rx_producer,
8185 tp->hw_status->idx[0].tx_consumer);
8186
8187 /* SW statistics block */
8188 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8189 ((u32 *)tp->hw_stats)[0],
8190 ((u32 *)tp->hw_stats)[1],
8191 ((u32 *)tp->hw_stats)[2],
8192 ((u32 *)tp->hw_stats)[3]);
8193
8194 /* Mailboxes */
8195 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8196 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8197 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8198 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8199 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8200
8201 /* NIC side send descriptors. */
8202 for (i = 0; i < 6; i++) {
8203 unsigned long txd;
8204
8205 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8206 + (i * sizeof(struct tg3_tx_buffer_desc));
8207 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8208 i,
8209 readl(txd + 0x0), readl(txd + 0x4),
8210 readl(txd + 0x8), readl(txd + 0xc));
8211 }
8212
8213 /* NIC side RX descriptors. */
8214 for (i = 0; i < 6; i++) {
8215 unsigned long rxd;
8216
8217 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8218 + (i * sizeof(struct tg3_rx_buffer_desc));
8219 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8220 i,
8221 readl(rxd + 0x0), readl(rxd + 0x4),
8222 readl(rxd + 0x8), readl(rxd + 0xc));
8223 rxd += (4 * sizeof(u32));
8224 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8225 i,
8226 readl(rxd + 0x0), readl(rxd + 0x4),
8227 readl(rxd + 0x8), readl(rxd + 0xc));
8228 }
8229
8230 for (i = 0; i < 6; i++) {
8231 unsigned long rxd;
8232
8233 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8234 + (i * sizeof(struct tg3_rx_buffer_desc));
8235 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8236 i,
8237 readl(rxd + 0x0), readl(rxd + 0x4),
8238 readl(rxd + 0x8), readl(rxd + 0xc));
8239 rxd += (4 * sizeof(u32));
8240 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8241 i,
8242 readl(rxd + 0x0), readl(rxd + 0x4),
8243 readl(rxd + 0x8), readl(rxd + 0xc));
8244 }
8245}
8246#endif
8247
8248static struct net_device_stats *tg3_get_stats(struct net_device *);
8249static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8250
8251static int tg3_close(struct net_device *dev)
8252{
8253 struct tg3 *tp = netdev_priv(dev);
8254
bea3348e 8255 napi_disable(&tp->napi);
28e53bdd 8256 cancel_work_sync(&tp->reset_task);
7faa006f 8257
1da177e4
LT		 8258 netif_stop_queue(dev);
8259
8260 del_timer_sync(&tp->timer);
8261
f47c11ee 8262 tg3_full_lock(tp, 1);
1da177e4
LT		 8263#if 0
8264 tg3_dump_state(tp);
8265#endif
8266
8267 tg3_disable_ints(tp);
8268
944d980e 8269 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8270 tg3_free_rings(tp);
5cf64b8a 8271 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8272
f47c11ee 8273 tg3_full_unlock(tp);
1da177e4 8274
88b06bc2
MC		 8275 free_irq(tp->pdev->irq, dev);
8276 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8277 pci_disable_msi(tp->pdev);
8278 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8279 }
1da177e4
LT		 8280
8281 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8282 sizeof(tp->net_stats_prev));
8283 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8284 sizeof(tp->estats_prev));
8285
8286 tg3_free_consistent(tp);
8287
bc1c7567
MC		 8288 tg3_set_power_state(tp, PCI_D3hot);
8289
8290 netif_carrier_off(tp->dev);
8291
1da177e4
LT		 8292 return 0;
8293}
8294
8295static inline unsigned long get_stat64(tg3_stat64_t *val)
8296{
8297 unsigned long ret;
8298
8299#if (BITS_PER_LONG == 32)
8300 ret = val->low;
8301#else
8302 ret = ((u64)val->high << 32) | ((u64)val->low);
8303#endif
8304 return ret;
8305}
8306
816f8b86
SB		 8307static inline u64 get_estat64(tg3_stat64_t *val)
8308{
8309 return ((u64)val->high << 32) | ((u64)val->low);
8310}
8311
1da177e4
LT		 8312static unsigned long calc_crc_errors(struct tg3 *tp)
8313{
8314 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8315
8316 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8317 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8319 u32 val;
8320
f47c11ee 8321 spin_lock_bh(&tp->lock);
569a5df8
MC		 8322 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8323 tg3_writephy(tp, MII_TG3_TEST1,
8324 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8325 tg3_readphy(tp, 0x14, &val);
8326 } else
8327 val = 0;
f47c11ee 8328 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8329
8330 tp->phy_crc_errors += val;
8331
8332 return tp->phy_crc_errors;
8333 }
8334
8335 return get_stat64(&hw_stats->rx_fcs_errors);
8336}
8337
8338#define ESTAT_ADD(member) \
8339 estats->member = old_estats->member + \
816f8b86 8340 get_estat64(&hw_stats->member)
1da177e4
LT		 8341
8342static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8343{
8344 struct tg3_ethtool_stats *estats = &tp->estats;
8345 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8346 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8347
8348 if (!hw_stats)
8349 return old_estats;
8350
8351 ESTAT_ADD(rx_octets);
8352 ESTAT_ADD(rx_fragments);
8353 ESTAT_ADD(rx_ucast_packets);
8354 ESTAT_ADD(rx_mcast_packets);
8355 ESTAT_ADD(rx_bcast_packets);
8356 ESTAT_ADD(rx_fcs_errors);
8357 ESTAT_ADD(rx_align_errors);
8358 ESTAT_ADD(rx_xon_pause_rcvd);
8359 ESTAT_ADD(rx_xoff_pause_rcvd);
8360 ESTAT_ADD(rx_mac_ctrl_rcvd);
8361 ESTAT_ADD(rx_xoff_entered);
8362 ESTAT_ADD(rx_frame_too_long_errors);
8363 ESTAT_ADD(rx_jabbers);
8364 ESTAT_ADD(rx_undersize_packets);
8365 ESTAT_ADD(rx_in_length_errors);
8366 ESTAT_ADD(rx_out_length_errors);
8367 ESTAT_ADD(rx_64_or_less_octet_packets);
8368 ESTAT_ADD(rx_65_to_127_octet_packets);
8369 ESTAT_ADD(rx_128_to_255_octet_packets);
8370 ESTAT_ADD(rx_256_to_511_octet_packets);
8371 ESTAT_ADD(rx_512_to_1023_octet_packets);
8372 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8373 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8374 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8375 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8376 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8377
8378 ESTAT_ADD(tx_octets);
8379 ESTAT_ADD(tx_collisions);
8380 ESTAT_ADD(tx_xon_sent);
8381 ESTAT_ADD(tx_xoff_sent);
8382 ESTAT_ADD(tx_flow_control);
8383 ESTAT_ADD(tx_mac_errors);
8384 ESTAT_ADD(tx_single_collisions);
8385 ESTAT_ADD(tx_mult_collisions);
8386 ESTAT_ADD(tx_deferred);
8387 ESTAT_ADD(tx_excessive_collisions);
8388 ESTAT_ADD(tx_late_collisions);
8389 ESTAT_ADD(tx_collide_2times);
8390 ESTAT_ADD(tx_collide_3times);
8391 ESTAT_ADD(tx_collide_4times);
8392 ESTAT_ADD(tx_collide_5times);
8393 ESTAT_ADD(tx_collide_6times);
8394 ESTAT_ADD(tx_collide_7times);
8395 ESTAT_ADD(tx_collide_8times);
8396 ESTAT_ADD(tx_collide_9times);
8397 ESTAT_ADD(tx_collide_10times);
8398 ESTAT_ADD(tx_collide_11times);
8399 ESTAT_ADD(tx_collide_12times);
8400 ESTAT_ADD(tx_collide_13times);
8401 ESTAT_ADD(tx_collide_14times);
8402 ESTAT_ADD(tx_collide_15times);
8403 ESTAT_ADD(tx_ucast_packets);
8404 ESTAT_ADD(tx_mcast_packets);
8405 ESTAT_ADD(tx_bcast_packets);
8406 ESTAT_ADD(tx_carrier_sense_errors);
8407 ESTAT_ADD(tx_discards);
8408 ESTAT_ADD(tx_errors);
8409
8410 ESTAT_ADD(dma_writeq_full);
8411 ESTAT_ADD(dma_write_prioq_full);
8412 ESTAT_ADD(rxbds_empty);
8413 ESTAT_ADD(rx_discards);
8414 ESTAT_ADD(rx_errors);
8415 ESTAT_ADD(rx_threshold_hit);
8416
8417 ESTAT_ADD(dma_readq_full);
8418 ESTAT_ADD(dma_read_prioq_full);
8419 ESTAT_ADD(tx_comp_queue_full);
8420
8421 ESTAT_ADD(ring_set_send_prod_index);
8422 ESTAT_ADD(ring_status_update);
8423 ESTAT_ADD(nic_irqs);
8424 ESTAT_ADD(nic_avoided_irqs);
8425 ESTAT_ADD(nic_tx_threshold_hit);
8426
8427 return estats;
8428}
8429
8430static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8431{
8432 struct tg3 *tp = netdev_priv(dev);
8433 struct net_device_stats *stats = &tp->net_stats;
8434 struct net_device_stats *old_stats = &tp->net_stats_prev;
8435 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8436
8437 if (!hw_stats)
8438 return old_stats;
8439
8440 stats->rx_packets = old_stats->rx_packets +
8441 get_stat64(&hw_stats->rx_ucast_packets) +
8442 get_stat64(&hw_stats->rx_mcast_packets) +
8443 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8444
1da177e4
LT		 8445 stats->tx_packets = old_stats->tx_packets +
8446 get_stat64(&hw_stats->tx_ucast_packets) +
8447 get_stat64(&hw_stats->tx_mcast_packets) +
8448 get_stat64(&hw_stats->tx_bcast_packets);
8449
8450 stats->rx_bytes = old_stats->rx_bytes +
8451 get_stat64(&hw_stats->rx_octets);
8452 stats->tx_bytes = old_stats->tx_bytes +
8453 get_stat64(&hw_stats->tx_octets);
8454
8455 stats->rx_errors = old_stats->rx_errors +
4f63b877 8456 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8457 stats->tx_errors = old_stats->tx_errors +
8458 get_stat64(&hw_stats->tx_errors) +
8459 get_stat64(&hw_stats->tx_mac_errors) +
8460 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8461 get_stat64(&hw_stats->tx_discards);
8462
8463 stats->multicast = old_stats->multicast +
8464 get_stat64(&hw_stats->rx_mcast_packets);
8465 stats->collisions = old_stats->collisions +
8466 get_stat64(&hw_stats->tx_collisions);
8467
8468 stats->rx_length_errors = old_stats->rx_length_errors +
8469 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8470 get_stat64(&hw_stats->rx_undersize_packets);
8471
8472 stats->rx_over_errors = old_stats->rx_over_errors +
8473 get_stat64(&hw_stats->rxbds_empty);
8474 stats->rx_frame_errors = old_stats->rx_frame_errors +
8475 get_stat64(&hw_stats->rx_align_errors);
8476 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8477 get_stat64(&hw_stats->tx_discards);
8478 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8479 get_stat64(&hw_stats->tx_carrier_sense_errors);
8480
8481 stats->rx_crc_errors = old_stats->rx_crc_errors +
8482 calc_crc_errors(tp);
8483
4f63b877
JL		 8484 stats->rx_missed_errors = old_stats->rx_missed_errors +
8485 get_stat64(&hw_stats->rx_discards);
8486
1da177e4
LT		 8487 return stats;
8488}
8489
8490static inline u32 calc_crc(unsigned char *buf, int len)
8491{
8492 u32 reg;
8493 u32 tmp;
8494 int j, k;
8495
8496 reg = 0xffffffff;
8497
8498 for (j = 0; j < len; j++) {
8499 reg ^= buf[j];
8500
8501 for (k = 0; k < 8; k++) {
8502 tmp = reg & 0x01;
8503
8504 reg >>= 1;
8505
8506 if (tmp) {
8507 reg ^= 0xedb88320;
8508 }
8509 }
8510 }
8511
8512 return ~reg;
8513}
8514
8515static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8516{
8517 /* accept or reject all multicast frames */
8518 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8519 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8520 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8521 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8522}
8523
8524static void __tg3_set_rx_mode(struct net_device *dev)
8525{
8526 struct tg3 *tp = netdev_priv(dev);
8527 u32 rx_mode;
8528
8529 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8530 RX_MODE_KEEP_VLAN_TAG);
8531
8532 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8533 * flag clear.
8534 */
8535#if TG3_VLAN_TAG_USED
8536 if (!tp->vlgrp &&
8537 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8538 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8539#else
8540 /* By definition, VLAN is disabled always in this
8541 * case.
8542 */
8543 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8544 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8545#endif
8546
8547 if (dev->flags & IFF_PROMISC) {
8548 /* Promiscuous mode. */
8549 rx_mode |= RX_MODE_PROMISC;
8550 } else if (dev->flags & IFF_ALLMULTI) {
8551 /* Accept all multicast. */
8552 tg3_set_multi (tp, 1);
8553 } else if (dev->mc_count < 1) {
8554 /* Reject all multicast. */
8555 tg3_set_multi (tp, 0);
8556 } else {
8557 /* Accept one or more multicast(s). */
8558 struct dev_mc_list *mclist;
8559 unsigned int i;
8560 u32 mc_filter[4] = { 0, };
8561 u32 regidx;
8562 u32 bit;
8563 u32 crc;
8564
8565 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8566 i++, mclist = mclist->next) {
8567
8568 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8569 bit = ~crc & 0x7f;
8570 regidx = (bit & 0x60) >> 5;
8571 bit &= 0x1f;
8572 mc_filter[regidx] |= (1 << bit);
8573 }
8574
8575 tw32(MAC_HASH_REG_0, mc_filter[0]);
8576 tw32(MAC_HASH_REG_1, mc_filter[1]);
8577 tw32(MAC_HASH_REG_2, mc_filter[2]);
8578 tw32(MAC_HASH_REG_3, mc_filter[3]);
8579 }
8580
8581 if (rx_mode != tp->rx_mode) {
8582 tp->rx_mode = rx_mode;
8583 tw32_f(MAC_RX_MODE, rx_mode);
8584 udelay(10);
8585 }
8586}
8587
8588static void tg3_set_rx_mode(struct net_device *dev)
8589{
8590 struct tg3 *tp = netdev_priv(dev);
8591
e75f7c90
MC		 8592 if (!netif_running(dev))
8593 return;
8594
f47c11ee 8595 tg3_full_lock(tp, 0);
1da177e4 8596 __tg3_set_rx_mode(dev);
f47c11ee 8597 tg3_full_unlock(tp);
1da177e4
LT		 8598}
8599
8600#define TG3_REGDUMP_LEN (32 * 1024)
8601
8602static int tg3_get_regs_len(struct net_device *dev)
8603{
8604 return TG3_REGDUMP_LEN;
8605}
8606
8607static void tg3_get_regs(struct net_device *dev,
8608 struct ethtool_regs *regs, void *_p)
8609{
8610 u32 *p = _p;
8611 struct tg3 *tp = netdev_priv(dev);
8612 u8 *orig_p = _p;
8613 int i;
8614
8615 regs->version = 0;
8616
8617 memset(p, 0, TG3_REGDUMP_LEN);
8618
bc1c7567
MC		 8619 if (tp->link_config.phy_is_low_power)
8620 return;
8621
f47c11ee 8622 tg3_full_lock(tp, 0);
1da177e4
LT		 8623
8624#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8625#define GET_REG32_LOOP(base,len) \
8626do { p = (u32 *)(orig_p + (base)); \
8627 for (i = 0; i < len; i += 4) \
8628 __GET_REG32((base) + i); \
8629} while (0)
8630#define GET_REG32_1(reg) \
8631do { p = (u32 *)(orig_p + (reg)); \
8632 __GET_REG32((reg)); \
8633} while (0)
8634
8635 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8636 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8637 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8638 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8639 GET_REG32_1(SNDDATAC_MODE);
8640 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8641 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8642 GET_REG32_1(SNDBDC_MODE);
8643 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8644 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8645 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8646 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8647 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8648 GET_REG32_1(RCVDCC_MODE);
8649 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8650 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8651 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8652 GET_REG32_1(MBFREE_MODE);
8653 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8654 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8655 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8656 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8657 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8658 GET_REG32_1(RX_CPU_MODE);
8659 GET_REG32_1(RX_CPU_STATE);
8660 GET_REG32_1(RX_CPU_PGMCTR);
8661 GET_REG32_1(RX_CPU_HWBKPT);
8662 GET_REG32_1(TX_CPU_MODE);
8663 GET_REG32_1(TX_CPU_STATE);
8664 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8665 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8666 GET_REG32_LOOP(FTQ_RESET, 0x120);
8667 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8668 GET_REG32_1(DMAC_MODE);
8669 GET_REG32_LOOP(GRC_MODE, 0x4c);
8670 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8671 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8672
8673#undef __GET_REG32
8674#undef GET_REG32_LOOP
8675#undef GET_REG32_1
8676
f47c11ee 8677 tg3_full_unlock(tp);
1da177e4
LT		 8678}
8679
8680static int tg3_get_eeprom_len(struct net_device *dev)
8681{
8682 struct tg3 *tp = netdev_priv(dev);
8683
8684 return tp->nvram_size;
8685}
8686
1da177e4
LT		 8687static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8688{
8689 struct tg3 *tp = netdev_priv(dev);
8690 int ret;
8691 u8 *pd;
b9fc7dc5 8692 u32 i, offset, len, b_offset, b_count;
a9dc529d 8693 __be32 val;
1da177e4 8694
df259d8c
MC		 8695 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8696 return -EINVAL;
8697
bc1c7567
MC		 8698 if (tp->link_config.phy_is_low_power)
8699 return -EAGAIN;
8700
1da177e4
LT		 8701 offset = eeprom->offset;
8702 len = eeprom->len;
8703 eeprom->len = 0;
8704
8705 eeprom->magic = TG3_EEPROM_MAGIC;
8706
8707 if (offset & 3) {
8708 /* adjustments to start on required 4 byte boundary */
8709 b_offset = offset & 3;
8710 b_count = 4 - b_offset;
8711 if (b_count > len) {
8712 /* i.e. offset=1 len=2 */
8713 b_count = len;
8714 }
a9dc529d 8715 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8716 if (ret)
8717 return ret;
1da177e4
LT		 8718 memcpy(data, ((char*)&val) + b_offset, b_count);
8719 len -= b_count;
8720 offset += b_count;
8721 eeprom->len += b_count;
8722 }
8723
8724 /* read bytes upto the last 4 byte boundary */
8725 pd = &data[eeprom->len];
8726 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8727 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8728 if (ret) {
8729 eeprom->len += i;
8730 return ret;
8731 }
1da177e4
LT		 8732 memcpy(pd + i, &val, 4);
8733 }
8734 eeprom->len += i;
8735
8736 if (len & 3) {
8737 /* read last bytes not ending on 4 byte boundary */
8738 pd = &data[eeprom->len];
8739 b_count = len & 3;
8740 b_offset = offset + len - b_count;
a9dc529d 8741 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8742 if (ret)
8743 return ret;
b9fc7dc5 8744 memcpy(pd, &val, b_count);
1da177e4
LT		 8745 eeprom->len += b_count;
8746 }
8747 return 0;
8748}
8749
6aa20a22 8750static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8751
8752static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8753{
8754 struct tg3 *tp = netdev_priv(dev);
8755 int ret;
b9fc7dc5 8756 u32 offset, len, b_offset, odd_len;
1da177e4 8757 u8 *buf;
a9dc529d 8758 __be32 start, end;
1da177e4 8759
bc1c7567
MC		 8760 if (tp->link_config.phy_is_low_power)
8761 return -EAGAIN;
8762
df259d8c
MC		 8763 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8764 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8765 return -EINVAL;
8766
8767 offset = eeprom->offset;
8768 len = eeprom->len;
8769
8770 if ((b_offset = (offset & 3))) {
8771 /* adjustments to start on required 4 byte boundary */
a9dc529d 8772 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8773 if (ret)
8774 return ret;
1da177e4
LT		 8775 len += b_offset;
8776 offset &= ~3;
1c8594b4
MC		 8777 if (len < 4)
8778 len = 4;
1da177e4
LT		 8779 }
8780
8781 odd_len = 0;
1c8594b4 8782 if (len & 3) {
1da177e4
LT		 8783 /* adjustments to end on required 4 byte boundary */
8784 odd_len = 1;
8785 len = (len + 3) & ~3;
a9dc529d 8786 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8787 if (ret)
8788 return ret;
1da177e4
LT		 8789 }
8790
8791 buf = data;
8792 if (b_offset || odd_len) {
8793 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8794 if (!buf)
1da177e4
LT		 8795 return -ENOMEM;
8796 if (b_offset)
8797 memcpy(buf, &start, 4);
8798 if (odd_len)
8799 memcpy(buf+len-4, &end, 4);
8800 memcpy(buf + b_offset, data, eeprom->len);
8801 }
8802
8803 ret = tg3_nvram_write_block(tp, offset, len, buf);
8804
8805 if (buf != data)
8806 kfree(buf);
8807
8808 return ret;
8809}
8810
8811static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8812{
b02fd9e3
MC		 8813 struct tg3 *tp = netdev_priv(dev);
8814
8815 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8816 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8817 return -EAGAIN;
298cf9be 8818 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8819 }
6aa20a22 8820
1da177e4
LT		 8821 cmd->supported = (SUPPORTED_Autoneg);
8822
8823 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8824 cmd->supported |= (SUPPORTED_1000baseT_Half |
8825 SUPPORTED_1000baseT_Full);
8826
ef348144 8827 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8828 cmd->supported |= (SUPPORTED_100baseT_Half |
8829 SUPPORTED_100baseT_Full |
8830 SUPPORTED_10baseT_Half |
8831 SUPPORTED_10baseT_Full |
3bebab59 8832 SUPPORTED_TP);
ef348144
KK		 8833 cmd->port = PORT_TP;
8834 } else {
1da177e4 8835 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8836 cmd->port = PORT_FIBRE;
8837 }
6aa20a22 8838
1da177e4
LT		 8839 cmd->advertising = tp->link_config.advertising;
8840 if (netif_running(dev)) {
8841 cmd->speed = tp->link_config.active_speed;
8842 cmd->duplex = tp->link_config.active_duplex;
8843 }
1da177e4 8844 cmd->phy_address = PHY_ADDR;
7e5856bd 8845 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8846 cmd->autoneg = tp->link_config.autoneg;
8847 cmd->maxtxpkt = 0;
8848 cmd->maxrxpkt = 0;
8849 return 0;
8850}
6aa20a22 8851
1da177e4
LT		 8852static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8853{
8854 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8855
b02fd9e3
MC		 8856 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8857 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8858 return -EAGAIN;
298cf9be 8859 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8860 }
8861
7e5856bd
MC		 8862 if (cmd->autoneg != AUTONEG_ENABLE &&
8863 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8864 return -EINVAL;
7e5856bd
MC		 8865
8866 if (cmd->autoneg == AUTONEG_DISABLE &&
8867 cmd->duplex != DUPLEX_FULL &&
8868 cmd->duplex != DUPLEX_HALF)
37ff238d 8869 return -EINVAL;
1da177e4 8870
7e5856bd
MC		 8871 if (cmd->autoneg == AUTONEG_ENABLE) {
8872 u32 mask = ADVERTISED_Autoneg |
8873 ADVERTISED_Pause |
8874 ADVERTISED_Asym_Pause;
8875
8876 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8877 mask |= ADVERTISED_1000baseT_Half |
8878 ADVERTISED_1000baseT_Full;
8879
8880 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8881 mask |= ADVERTISED_100baseT_Half |
8882 ADVERTISED_100baseT_Full |
8883 ADVERTISED_10baseT_Half |
8884 ADVERTISED_10baseT_Full |
8885 ADVERTISED_TP;
8886 else
8887 mask |= ADVERTISED_FIBRE;
8888
8889 if (cmd->advertising & ~mask)
8890 return -EINVAL;
8891
8892 mask &= (ADVERTISED_1000baseT_Half |
8893 ADVERTISED_1000baseT_Full |
8894 ADVERTISED_100baseT_Half |
8895 ADVERTISED_100baseT_Full |
8896 ADVERTISED_10baseT_Half |
8897 ADVERTISED_10baseT_Full);
8898
8899 cmd->advertising &= mask;
8900 } else {
8901 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8902 if (cmd->speed != SPEED_1000)
8903 return -EINVAL;
8904
8905 if (cmd->duplex != DUPLEX_FULL)
8906 return -EINVAL;
8907 } else {
8908 if (cmd->speed != SPEED_100 &&
8909 cmd->speed != SPEED_10)
8910 return -EINVAL;
8911 }
8912 }
8913
f47c11ee 8914 tg3_full_lock(tp, 0);
1da177e4
LT		 8915
8916 tp->link_config.autoneg = cmd->autoneg;
8917 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8918 tp->link_config.advertising = (cmd->advertising |
8919 ADVERTISED_Autoneg);
1da177e4
LT		 8920 tp->link_config.speed = SPEED_INVALID;
8921 tp->link_config.duplex = DUPLEX_INVALID;
8922 } else {
8923 tp->link_config.advertising = 0;
8924 tp->link_config.speed = cmd->speed;
8925 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8926 }
6aa20a22 8927
24fcad6b
MC		 8928 tp->link_config.orig_speed = tp->link_config.speed;
8929 tp->link_config.orig_duplex = tp->link_config.duplex;
8930 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8931
1da177e4
LT		 8932 if (netif_running(dev))
8933 tg3_setup_phy(tp, 1);
8934
f47c11ee 8935 tg3_full_unlock(tp);
6aa20a22 8936
1da177e4
LT		 8937 return 0;
8938}
6aa20a22 8939
1da177e4
LT		 8940static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8941{
8942 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8943
1da177e4
LT		 8944 strcpy(info->driver, DRV_MODULE_NAME);
8945 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8946 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8947 strcpy(info->bus_info, pci_name(tp->pdev));
8948}
6aa20a22 8949
1da177e4
LT		 8950static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8951{
8952 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8953
12dac075
RW		 8954 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8955 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8956 wol->supported = WAKE_MAGIC;
8957 else
8958 wol->supported = 0;
1da177e4 8959 wol->wolopts = 0;
05ac4cb7
MC		 8960 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8961 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8962 wol->wolopts = WAKE_MAGIC;
8963 memset(&wol->sopass, 0, sizeof(wol->sopass));
8964}
6aa20a22 8965
1da177e4
LT		 8966static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8967{
8968 struct tg3 *tp = netdev_priv(dev);
12dac075 8969 struct device *dp = &tp->pdev->dev;
6aa20a22 8970
1da177e4
LT		 8971 if (wol->wolopts & ~WAKE_MAGIC)
8972 return -EINVAL;
8973 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8974 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8975 return -EINVAL;
6aa20a22 8976
f47c11ee 8977 spin_lock_bh(&tp->lock);
12dac075 8978 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8979 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8980 device_set_wakeup_enable(dp, true);
8981 } else {
1da177e4 8982 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8983 device_set_wakeup_enable(dp, false);
8984 }
f47c11ee 8985 spin_unlock_bh(&tp->lock);
6aa20a22 8986
1da177e4
LT		 8987 return 0;
8988}
6aa20a22 8989
1da177e4
LT		 8990static u32 tg3_get_msglevel(struct net_device *dev)
8991{
8992 struct tg3 *tp = netdev_priv(dev);
8993 return tp->msg_enable;
8994}
6aa20a22 8995
1da177e4
LT		 8996static void tg3_set_msglevel(struct net_device *dev, u32 value)
8997{
8998 struct tg3 *tp = netdev_priv(dev);
8999 tp->msg_enable = value;
9000}
6aa20a22 9001
1da177e4
LT		 9002static int tg3_set_tso(struct net_device *dev, u32 value)
9003{
9004 struct tg3 *tp = netdev_priv(dev);
9005
9006 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9007 if (value)
9008 return -EINVAL;
9009 return 0;
9010 }
027455ad
MC		 9011 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9012 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9013 if (value) {
b0026624 9014 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9016 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9017 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 9018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9020 dev->features |= NETIF_F_TSO_ECN;
9021 } else
9022 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9023 }
1da177e4
LT		 9024 return ethtool_op_set_tso(dev, value);
9025}
6aa20a22 9026
1da177e4
LT		 9027static int tg3_nway_reset(struct net_device *dev)
9028{
9029 struct tg3 *tp = netdev_priv(dev);
1da177e4 9030 int r;
6aa20a22 9031
1da177e4
LT		 9032 if (!netif_running(dev))
9033 return -EAGAIN;
9034
c94e3941
MC		 9035 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9036 return -EINVAL;
9037
b02fd9e3
MC		 9038 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9039 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9040 return -EAGAIN;
298cf9be 9041 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9042 } else {
9043 u32 bmcr;
9044
9045 spin_lock_bh(&tp->lock);
9046 r = -EINVAL;
9047 tg3_readphy(tp, MII_BMCR, &bmcr);
9048 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9049 ((bmcr & BMCR_ANENABLE) ||
9050 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9052 BMCR_ANENABLE);
9053 r = 0;
9054 }
9055 spin_unlock_bh(&tp->lock);
1da177e4 9056 }
6aa20a22 9057
1da177e4
LT		 9058 return r;
9059}
6aa20a22 9060
1da177e4
LT		 9061static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9062{
9063 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9064
1da177e4
LT		 9065 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9066 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9067 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9068 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9069 else
9070 ering->rx_jumbo_max_pending = 0;
9071
9072 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9073
9074 ering->rx_pending = tp->rx_pending;
9075 ering->rx_mini_pending = 0;
4f81c32b
MC		 9076 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9077 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9078 else
9079 ering->rx_jumbo_pending = 0;
9080
1da177e4
LT		 9081 ering->tx_pending = tp->tx_pending;
9082}
6aa20a22 9083
1da177e4
LT		 9084static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9085{
9086 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9087 int irq_sync = 0, err = 0;
6aa20a22 9088
1da177e4
LT		 9089 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9090 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9091 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9092 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9093 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9094 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9095 return -EINVAL;
6aa20a22 9096
bbe832c0 9097 if (netif_running(dev)) {
b02fd9e3 9098 tg3_phy_stop(tp);
1da177e4 9099 tg3_netif_stop(tp);
bbe832c0
MC		 9100 irq_sync = 1;
9101 }
1da177e4 9102
bbe832c0 9103 tg3_full_lock(tp, irq_sync);
6aa20a22 9104
1da177e4
LT		 9105 tp->rx_pending = ering->rx_pending;
9106
9107 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9108 tp->rx_pending > 63)
9109 tp->rx_pending = 63;
9110 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9111 tp->tx_pending = ering->tx_pending;
9112
9113 if (netif_running(dev)) {
944d980e 9114 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9115 err = tg3_restart_hw(tp, 1);
9116 if (!err)
9117 tg3_netif_start(tp);
1da177e4
LT		 9118 }
9119
f47c11ee 9120 tg3_full_unlock(tp);
6aa20a22 9121
b02fd9e3
MC		 9122 if (irq_sync && !err)
9123 tg3_phy_start(tp);
9124
b9ec6c1b 9125 return err;
1da177e4 9126}
6aa20a22 9127
1da177e4
LT		 9128static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9129{
9130 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9131
1da177e4 9132 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9133
e18ce346 9134 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9135 epause->rx_pause = 1;
9136 else
9137 epause->rx_pause = 0;
9138
e18ce346 9139 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9140 epause->tx_pause = 1;
9141 else
9142 epause->tx_pause = 0;
1da177e4 9143}
6aa20a22 9144
1da177e4
LT		 9145static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9146{
9147 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9148 int err = 0;
6aa20a22 9149
b02fd9e3
MC		 9150 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9151 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9152 return -EAGAIN;
1da177e4 9153
b02fd9e3
MC		 9154 if (epause->autoneg) {
9155 u32 newadv;
9156 struct phy_device *phydev;
f47c11ee 9157
298cf9be 9158 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9159
b02fd9e3
MC		 9160 if (epause->rx_pause) {
9161 if (epause->tx_pause)
9162 newadv = ADVERTISED_Pause;
9163 else
9164 newadv = ADVERTISED_Pause |
9165 ADVERTISED_Asym_Pause;
9166 } else if (epause->tx_pause) {
9167 newadv = ADVERTISED_Asym_Pause;
9168 } else
9169 newadv = 0;
9170
9171 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9172 u32 oldadv = phydev->advertising &
9173 (ADVERTISED_Pause |
9174 ADVERTISED_Asym_Pause);
9175 if (oldadv != newadv) {
9176 phydev->advertising &=
9177 ~(ADVERTISED_Pause |
9178 ADVERTISED_Asym_Pause);
9179 phydev->advertising |= newadv;
9180 err = phy_start_aneg(phydev);
9181 }
9182 } else {
9183 tp->link_config.advertising &=
9184 ~(ADVERTISED_Pause |
9185 ADVERTISED_Asym_Pause);
9186 tp->link_config.advertising |= newadv;
9187 }
9188 } else {
9189 if (epause->rx_pause)
e18ce346 9190 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9191 else
e18ce346 9192 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9193
b02fd9e3 9194 if (epause->tx_pause)
e18ce346 9195 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9196 else
e18ce346 9197 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9198
9199 if (netif_running(dev))
9200 tg3_setup_flow_control(tp, 0, 0);
9201 }
9202 } else {
9203 int irq_sync = 0;
9204
9205 if (netif_running(dev)) {
9206 tg3_netif_stop(tp);
9207 irq_sync = 1;
9208 }
9209
9210 tg3_full_lock(tp, irq_sync);
9211
9212 if (epause->autoneg)
9213 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9214 else
9215 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9216 if (epause->rx_pause)
e18ce346 9217 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9218 else
e18ce346 9219 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9220 if (epause->tx_pause)
e18ce346 9221 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9222 else
e18ce346 9223 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9224
9225 if (netif_running(dev)) {
9226 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9227 err = tg3_restart_hw(tp, 1);
9228 if (!err)
9229 tg3_netif_start(tp);
9230 }
9231
9232 tg3_full_unlock(tp);
9233 }
6aa20a22 9234
b9ec6c1b 9235 return err;
1da177e4 9236}
6aa20a22 9237
1da177e4
LT		 9238static u32 tg3_get_rx_csum(struct net_device *dev)
9239{
9240 struct tg3 *tp = netdev_priv(dev);
9241 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9242}
6aa20a22 9243
1da177e4
LT		 9244static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9245{
9246 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9247
1da177e4
LT		 9248 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9249 if (data != 0)
9250 return -EINVAL;
9251 return 0;
9252 }
6aa20a22 9253
f47c11ee 9254 spin_lock_bh(&tp->lock);
1da177e4
LT		 9255 if (data)
9256 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9257 else
9258 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9259 spin_unlock_bh(&tp->lock);
6aa20a22 9260
1da177e4
LT		 9261 return 0;
9262}
6aa20a22 9263
1da177e4
LT		 9264static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9265{
9266 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9267
1da177e4
LT		 9268 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9269 if (data != 0)
9270 return -EINVAL;
9271 return 0;
9272 }
6aa20a22 9273
321d32a0 9274 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9275 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9276 else
9c27dbdf 9277 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9278
9279 return 0;
9280}
9281
b9f2c044 9282static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9283{
b9f2c044
JG		 9284 switch (sset) {
9285 case ETH_SS_TEST:
9286 return TG3_NUM_TEST;
9287 case ETH_SS_STATS:
9288 return TG3_NUM_STATS;
9289 default:
9290 return -EOPNOTSUPP;
9291 }
4cafd3f5
MC		 9292}
9293
1da177e4
LT		 9294static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9295{
9296 switch (stringset) {
9297 case ETH_SS_STATS:
9298 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9299 break;
4cafd3f5
MC		 9300 case ETH_SS_TEST:
9301 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9302 break;
1da177e4
LT		 9303 default:
9304 WARN_ON(1); /* we need a WARN() */
9305 break;
9306 }
9307}
9308
4009a93d
MC		 9309static int tg3_phys_id(struct net_device *dev, u32 data)
9310{
9311 struct tg3 *tp = netdev_priv(dev);
9312 int i;
9313
9314 if (!netif_running(tp->dev))
9315 return -EAGAIN;
9316
9317 if (data == 0)
759afc31 9318 data = UINT_MAX / 2;
4009a93d
MC		 9319
9320 for (i = 0; i < (data * 2); i++) {
9321 if ((i % 2) == 0)
9322 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9323 LED_CTRL_1000MBPS_ON |
9324 LED_CTRL_100MBPS_ON |
9325 LED_CTRL_10MBPS_ON |
9326 LED_CTRL_TRAFFIC_OVERRIDE |
9327 LED_CTRL_TRAFFIC_BLINK |
9328 LED_CTRL_TRAFFIC_LED);
6aa20a22 9329
4009a93d
MC		 9330 else
9331 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9332 LED_CTRL_TRAFFIC_OVERRIDE);
9333
9334 if (msleep_interruptible(500))
9335 break;
9336 }
9337 tw32(MAC_LED_CTRL, tp->led_ctrl);
9338 return 0;
9339}
9340
1da177e4
LT		 9341static void tg3_get_ethtool_stats (struct net_device *dev,
9342 struct ethtool_stats *estats, u64 *tmp_stats)
9343{
9344 struct tg3 *tp = netdev_priv(dev);
9345 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9346}
9347
566f86ad 9348#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9349#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9350#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9351#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9352#define NVRAM_SELFBOOT_HW_SIZE 0x20
9353#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9354
9355static int tg3_test_nvram(struct tg3 *tp)
9356{
b9fc7dc5 9357 u32 csum, magic;
a9dc529d 9358 __be32 *buf;
ab0049b4 9359 int i, j, k, err = 0, size;
566f86ad 9360
df259d8c
MC		 9361 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9362 return 0;
9363
e4f34110 9364 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9365 return -EIO;
9366
1b27777a
MC		 9367 if (magic == TG3_EEPROM_MAGIC)
9368 size = NVRAM_TEST_SIZE;
b16250e3 9369 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9370 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9371 TG3_EEPROM_SB_FORMAT_1) {
9372 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9373 case TG3_EEPROM_SB_REVISION_0:
9374 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9375 break;
9376 case TG3_EEPROM_SB_REVISION_2:
9377 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9378 break;
9379 case TG3_EEPROM_SB_REVISION_3:
9380 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9381 break;
9382 default:
9383 return 0;
9384 }
9385 } else
1b27777a 9386 return 0;
b16250e3
MC		 9387 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9388 size = NVRAM_SELFBOOT_HW_SIZE;
9389 else
1b27777a
MC		 9390 return -EIO;
9391
9392 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9393 if (buf == NULL)
9394 return -ENOMEM;
9395
1b27777a
MC		 9396 err = -EIO;
9397 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9398 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9399 if (err)
566f86ad 9400 break;
566f86ad 9401 }
1b27777a 9402 if (i < size)
566f86ad
MC		 9403 goto out;
9404
1b27777a 9405 /* Selfboot format */
a9dc529d 9406 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9407 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9408 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9409 u8 *buf8 = (u8 *) buf, csum8 = 0;
9410
b9fc7dc5 9411 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9412 TG3_EEPROM_SB_REVISION_2) {
9413 /* For rev 2, the csum doesn't include the MBA. */
9414 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9415 csum8 += buf8[i];
9416 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9417 csum8 += buf8[i];
9418 } else {
9419 for (i = 0; i < size; i++)
9420 csum8 += buf8[i];
9421 }
1b27777a 9422
ad96b485
AB		 9423 if (csum8 == 0) {
9424 err = 0;
9425 goto out;
9426 }
9427
9428 err = -EIO;
9429 goto out;
1b27777a 9430 }
566f86ad 9431
b9fc7dc5 9432 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9433 TG3_EEPROM_MAGIC_HW) {
9434 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9435 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9436 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9437
9438 /* Separate the parity bits and the data bytes. */
9439 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9440 if ((i == 0) || (i == 8)) {
9441 int l;
9442 u8 msk;
9443
9444 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9445 parity[k++] = buf8[i] & msk;
9446 i++;
9447 }
9448 else if (i == 16) {
9449 int l;
9450 u8 msk;
9451
9452 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9453 parity[k++] = buf8[i] & msk;
9454 i++;
9455
9456 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9457 parity[k++] = buf8[i] & msk;
9458 i++;
9459 }
9460 data[j++] = buf8[i];
9461 }
9462
9463 err = -EIO;
9464 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9465 u8 hw8 = hweight8(data[i]);
9466
9467 if ((hw8 & 0x1) && parity[i])
9468 goto out;
9469 else if (!(hw8 & 0x1) && !parity[i])
9470 goto out;
9471 }
9472 err = 0;
9473 goto out;
9474 }
9475
566f86ad
MC		 9476 /* Bootstrap checksum at offset 0x10 */
9477 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9478 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9479 goto out;
9480
9481 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9482 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9483 if (csum != be32_to_cpu(buf[0xfc/4]))
9484 goto out;
566f86ad
MC		 9485
9486 err = 0;
9487
9488out:
9489 kfree(buf);
9490 return err;
9491}
9492
ca43007a
MC		 9493#define TG3_SERDES_TIMEOUT_SEC 2
9494#define TG3_COPPER_TIMEOUT_SEC 6
9495
9496static int tg3_test_link(struct tg3 *tp)
9497{
9498 int i, max;
9499
9500 if (!netif_running(tp->dev))
9501 return -ENODEV;
9502
4c987487 9503 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9504 max = TG3_SERDES_TIMEOUT_SEC;
9505 else
9506 max = TG3_COPPER_TIMEOUT_SEC;
9507
9508 for (i = 0; i < max; i++) {
9509 if (netif_carrier_ok(tp->dev))
9510 return 0;
9511
9512 if (msleep_interruptible(1000))
9513 break;
9514 }
9515
9516 return -EIO;
9517}
9518
a71116d1 9519/* Only test the commonly used registers */
30ca3e37 9520static int tg3_test_registers(struct tg3 *tp)
a71116d1 9521{
b16250e3 9522 int i, is_5705, is_5750;
a71116d1
MC		 9523 u32 offset, read_mask, write_mask, val, save_val, read_val;
9524 static struct {
9525 u16 offset;
9526 u16 flags;
9527#define TG3_FL_5705 0x1
9528#define TG3_FL_NOT_5705 0x2
9529#define TG3_FL_NOT_5788 0x4
b16250e3 9530#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9531 u32 read_mask;
9532 u32 write_mask;
9533 } reg_tbl[] = {
9534 /* MAC Control Registers */
9535 { MAC_MODE, TG3_FL_NOT_5705,
9536 0x00000000, 0x00ef6f8c },
9537 { MAC_MODE, TG3_FL_5705,
9538 0x00000000, 0x01ef6b8c },
9539 { MAC_STATUS, TG3_FL_NOT_5705,
9540 0x03800107, 0x00000000 },
9541 { MAC_STATUS, TG3_FL_5705,
9542 0x03800100, 0x00000000 },
9543 { MAC_ADDR_0_HIGH, 0x0000,
9544 0x00000000, 0x0000ffff },
9545 { MAC_ADDR_0_LOW, 0x0000,
9546 0x00000000, 0xffffffff },
9547 { MAC_RX_MTU_SIZE, 0x0000,
9548 0x00000000, 0x0000ffff },
9549 { MAC_TX_MODE, 0x0000,
9550 0x00000000, 0x00000070 },
9551 { MAC_TX_LENGTHS, 0x0000,
9552 0x00000000, 0x00003fff },
9553 { MAC_RX_MODE, TG3_FL_NOT_5705,
9554 0x00000000, 0x000007fc },
9555 { MAC_RX_MODE, TG3_FL_5705,
9556 0x00000000, 0x000007dc },
9557 { MAC_HASH_REG_0, 0x0000,
9558 0x00000000, 0xffffffff },
9559 { MAC_HASH_REG_1, 0x0000,
9560 0x00000000, 0xffffffff },
9561 { MAC_HASH_REG_2, 0x0000,
9562 0x00000000, 0xffffffff },
9563 { MAC_HASH_REG_3, 0x0000,
9564 0x00000000, 0xffffffff },
9565
9566 /* Receive Data and Receive BD Initiator Control Registers. */
9567 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9568 0x00000000, 0xffffffff },
9569 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9570 0x00000000, 0xffffffff },
9571 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9572 0x00000000, 0x00000003 },
9573 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9574 0x00000000, 0xffffffff },
9575 { RCVDBDI_STD_BD+0, 0x0000,
9576 0x00000000, 0xffffffff },
9577 { RCVDBDI_STD_BD+4, 0x0000,
9578 0x00000000, 0xffffffff },
9579 { RCVDBDI_STD_BD+8, 0x0000,
9580 0x00000000, 0xffff0002 },
9581 { RCVDBDI_STD_BD+0xc, 0x0000,
9582 0x00000000, 0xffffffff },
6aa20a22 9583
a71116d1
MC		 9584 /* Receive BD Initiator Control Registers. */
9585 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9586 0x00000000, 0xffffffff },
9587 { RCVBDI_STD_THRESH, TG3_FL_5705,
9588 0x00000000, 0x000003ff },
9589 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9590 0x00000000, 0xffffffff },
6aa20a22 9591
a71116d1
MC		 9592 /* Host Coalescing Control Registers. */
9593 { HOSTCC_MODE, TG3_FL_NOT_5705,
9594 0x00000000, 0x00000004 },
9595 { HOSTCC_MODE, TG3_FL_5705,
9596 0x00000000, 0x000000f6 },
9597 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9598 0x00000000, 0xffffffff },
9599 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9600 0x00000000, 0x000003ff },
9601 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9602 0x00000000, 0xffffffff },
9603 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9604 0x00000000, 0x000003ff },
9605 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9606 0x00000000, 0xffffffff },
9607 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9608 0x00000000, 0x000000ff },
9609 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9610 0x00000000, 0xffffffff },
9611 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9612 0x00000000, 0x000000ff },
9613 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9614 0x00000000, 0xffffffff },
9615 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9616 0x00000000, 0xffffffff },
9617 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9618 0x00000000, 0xffffffff },
9619 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9620 0x00000000, 0x000000ff },
9621 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9622 0x00000000, 0xffffffff },
9623 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9624 0x00000000, 0x000000ff },
9625 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9626 0x00000000, 0xffffffff },
9627 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9628 0x00000000, 0xffffffff },
9629 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9630 0x00000000, 0xffffffff },
9631 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9632 0x00000000, 0xffffffff },
9633 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9634 0x00000000, 0xffffffff },
9635 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9636 0xffffffff, 0x00000000 },
9637 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9638 0xffffffff, 0x00000000 },
9639
9640 /* Buffer Manager Control Registers. */
b16250e3 9641 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9642 0x00000000, 0x007fff80 },
b16250e3 9643 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9644 0x00000000, 0x007fffff },
9645 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9646 0x00000000, 0x0000003f },
9647 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9648 0x00000000, 0x000001ff },
9649 { BUFMGR_MB_HIGH_WATER, 0x0000,
9650 0x00000000, 0x000001ff },
9651 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9652 0xffffffff, 0x00000000 },
9653 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9654 0xffffffff, 0x00000000 },
6aa20a22 9655
a71116d1
MC		 9656 /* Mailbox Registers */
9657 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9658 0x00000000, 0x000001ff },
9659 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9660 0x00000000, 0x000001ff },
9661 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9662 0x00000000, 0x000007ff },
9663 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9664 0x00000000, 0x000001ff },
9665
9666 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9667 };
9668
b16250e3
MC		 9669 is_5705 = is_5750 = 0;
9670 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9671 is_5705 = 1;
b16250e3
MC		 9672 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9673 is_5750 = 1;
9674 }
a71116d1
MC		 9675
9676 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9677 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9678 continue;
9679
9680 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9681 continue;
9682
9683 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9684 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9685 continue;
9686
b16250e3
MC		 9687 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9688 continue;
9689
a71116d1
MC		 9690 offset = (u32) reg_tbl[i].offset;
9691 read_mask = reg_tbl[i].read_mask;
9692 write_mask = reg_tbl[i].write_mask;
9693
9694 /* Save the original register content */
9695 save_val = tr32(offset);
9696
9697 /* Determine the read-only value. */
9698 read_val = save_val & read_mask;
9699
9700 /* Write zero to the register, then make sure the read-only bits
9701 * are not changed and the read/write bits are all zeros.
9702 */
9703 tw32(offset, 0);
9704
9705 val = tr32(offset);
9706
9707 /* Test the read-only and read/write bits. */
9708 if (((val & read_mask) != read_val) || (val & write_mask))
9709 goto out;
9710
9711 /* Write ones to all the bits defined by RdMask and WrMask, then
9712 * make sure the read-only bits are not changed and the
9713 * read/write bits are all ones.
9714 */
9715 tw32(offset, read_mask | write_mask);
9716
9717 val = tr32(offset);
9718
9719 /* Test the read-only bits. */
9720 if ((val & read_mask) != read_val)
9721 goto out;
9722
9723 /* Test the read/write bits. */
9724 if ((val & write_mask) != write_mask)
9725 goto out;
9726
9727 tw32(offset, save_val);
9728 }
9729
9730 return 0;
9731
9732out:
9f88f29f
MC		 9733 if (netif_msg_hw(tp))
9734 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9735 offset);
a71116d1
MC		 9736 tw32(offset, save_val);
9737 return -EIO;
9738}
9739
7942e1db
MC		 9740static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9741{
f71e1309 9742 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9743 int i;
9744 u32 j;
9745
e9edda69 9746 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9747 for (j = 0; j < len; j += 4) {
9748 u32 val;
9749
9750 tg3_write_mem(tp, offset + j, test_pattern[i]);
9751 tg3_read_mem(tp, offset + j, &val);
9752 if (val != test_pattern[i])
9753 return -EIO;
9754 }
9755 }
9756 return 0;
9757}
9758
9759static int tg3_test_memory(struct tg3 *tp)
9760{
9761 static struct mem_entry {
9762 u32 offset;
9763 u32 len;
9764 } mem_tbl_570x[] = {
38690194 9765 { 0x00000000, 0x00b50},
7942e1db
MC		 9766 { 0x00002000, 0x1c000},
9767 { 0xffffffff, 0x00000}
9768 }, mem_tbl_5705[] = {
9769 { 0x00000100, 0x0000c},
9770 { 0x00000200, 0x00008},
7942e1db
MC		 9771 { 0x00004000, 0x00800},
9772 { 0x00006000, 0x01000},
9773 { 0x00008000, 0x02000},
9774 { 0x00010000, 0x0e000},
9775 { 0xffffffff, 0x00000}
79f4d13a
MC		 9776 }, mem_tbl_5755[] = {
9777 { 0x00000200, 0x00008},
9778 { 0x00004000, 0x00800},
9779 { 0x00006000, 0x00800},
9780 { 0x00008000, 0x02000},
9781 { 0x00010000, 0x0c000},
9782 { 0xffffffff, 0x00000}
b16250e3
MC		 9783 }, mem_tbl_5906[] = {
9784 { 0x00000200, 0x00008},
9785 { 0x00004000, 0x00400},
9786 { 0x00006000, 0x00400},
9787 { 0x00008000, 0x01000},
9788 { 0x00010000, 0x01000},
9789 { 0xffffffff, 0x00000}
7942e1db
MC		 9790 };
9791 struct mem_entry *mem_tbl;
9792 int err = 0;
9793 int i;
9794
321d32a0
MC		 9795 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9796 mem_tbl = mem_tbl_5755;
9797 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9798 mem_tbl = mem_tbl_5906;
9799 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9800 mem_tbl = mem_tbl_5705;
9801 else
7942e1db
MC		 9802 mem_tbl = mem_tbl_570x;
9803
9804 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9805 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9806 mem_tbl[i].len)) != 0)
9807 break;
9808 }
6aa20a22 9809
7942e1db
MC		 9810 return err;
9811}
9812
9f40dead
MC		 9813#define TG3_MAC_LOOPBACK 0
9814#define TG3_PHY_LOOPBACK 1
9815
9816static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9817{
9f40dead 9818 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9819 u32 desc_idx;
9820 struct sk_buff *skb, *rx_skb;
9821 u8 *tx_data;
9822 dma_addr_t map;
9823 int num_pkts, tx_len, rx_len, i, err;
9824 struct tg3_rx_buffer_desc *desc;
21f581a5 9825 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 9826
9f40dead 9827 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9828 /* HW errata - mac loopback fails in some cases on 5780.
9829 * Normal traffic and PHY loopback are not affected by
9830 * errata.
9831 */
9832 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9833 return 0;
9834
9f40dead 9835 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9836 MAC_MODE_PORT_INT_LPBACK;
9837 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9838 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9839 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9840 mac_mode |= MAC_MODE_PORT_MODE_MII;
9841 else
9842 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9843 tw32(MAC_MODE, mac_mode);
9844 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9845 u32 val;
9846
7f97a4bd
MC		 9847 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9848 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9849 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9850 } else
9851 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9852
9ef8ca99
MC		 9853 tg3_phy_toggle_automdix(tp, 0);
9854
3f7045c1 9855 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9856 udelay(40);
5d64ad34 9857
e8f3f6ca 9858 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 9859 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9861 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 9862 mac_mode |= MAC_MODE_PORT_MODE_MII;
9863 } else
9864 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9865
c94e3941
MC		 9866 /* reset to prevent losing 1st rx packet intermittently */
9867 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9868 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9869 udelay(10);
9870 tw32_f(MAC_RX_MODE, tp->rx_mode);
9871 }
e8f3f6ca
MC		 9872 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9873 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9874 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9875 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9876 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9877 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9878 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9879 }
9f40dead 9880 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9881 }
9882 else
9883 return -EINVAL;
c76949a6
MC		 9884
9885 err = -EIO;
9886
c76949a6 9887 tx_len = 1514;
a20e9c62 9888 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9889 if (!skb)
9890 return -ENOMEM;
9891
c76949a6
MC		 9892 tx_data = skb_put(skb, tx_len);
9893 memcpy(tx_data, tp->dev->dev_addr, 6);
9894 memset(tx_data + 6, 0x0, 8);
9895
9896 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9897
9898 for (i = 14; i < tx_len; i++)
9899 tx_data[i] = (u8) (i & 0xff);
9900
9901 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9902
9903 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9904 HOSTCC_MODE_NOW);
9905
9906 udelay(10);
9907
9908 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9909
c76949a6
MC		 9910 num_pkts = 0;
9911
9f40dead 9912 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9913
9f40dead 9914 tp->tx_prod++;
c76949a6
MC		 9915 num_pkts++;
9916
9f40dead
MC		 9917 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9918 tp->tx_prod);
09ee929c 9919 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9920
9921 udelay(10);
9922
3f7045c1
MC		 9923 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9924 for (i = 0; i < 25; i++) {
c76949a6
MC		 9925 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9926 HOSTCC_MODE_NOW);
9927
9928 udelay(10);
9929
9930 tx_idx = tp->hw_status->idx[0].tx_consumer;
9931 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9932 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9933 (rx_idx == (rx_start_idx + num_pkts)))
9934 break;
9935 }
9936
9937 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9938 dev_kfree_skb(skb);
9939
9f40dead 9940 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9941 goto out;
9942
9943 if (rx_idx != rx_start_idx + num_pkts)
9944 goto out;
9945
9946 desc = &tp->rx_rcb[rx_start_idx];
9947 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9948 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9949 if (opaque_key != RXD_OPAQUE_RING_STD)
9950 goto out;
9951
9952 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9953 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9954 goto out;
9955
9956 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9957 if (rx_len != tx_len)
9958 goto out;
9959
21f581a5 9960 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 9961
21f581a5 9962 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 9963 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9964
9965 for (i = 14; i < tx_len; i++) {
9966 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9967 goto out;
9968 }
9969 err = 0;
6aa20a22 9970
c76949a6
MC		 9971 /* tg3_free_rings will unmap and free the rx_skb */
9972out:
9973 return err;
9974}
9975
9f40dead
MC		 9976#define TG3_MAC_LOOPBACK_FAILED 1
9977#define TG3_PHY_LOOPBACK_FAILED 2
9978#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9979 TG3_PHY_LOOPBACK_FAILED)
9980
9981static int tg3_test_loopback(struct tg3 *tp)
9982{
9983 int err = 0;
9936bcf6 9984 u32 cpmuctrl = 0;
9f40dead
MC		 9985
9986 if (!netif_running(tp->dev))
9987 return TG3_LOOPBACK_FAILED;
9988
b9ec6c1b
MC		 9989 err = tg3_reset_hw(tp, 1);
9990 if (err)
9991 return TG3_LOOPBACK_FAILED;
9f40dead 9992
6833c043
MC		 9993 /* Turn off gphy autopowerdown. */
9994 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9995 tg3_phy_toggle_apd(tp, false);
9996
321d32a0 9997 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9998 int i;
9999 u32 status;
10000
10001 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10002
10003 /* Wait for up to 40 microseconds to acquire lock. */
10004 for (i = 0; i < 4; i++) {
10005 status = tr32(TG3_CPMU_MUTEX_GNT);
10006 if (status == CPMU_MUTEX_GNT_DRIVER)
10007 break;
10008 udelay(10);
10009 }
10010
10011 if (status != CPMU_MUTEX_GNT_DRIVER)
10012 return TG3_LOOPBACK_FAILED;
10013
b2a5c19c 10014 /* Turn off link-based power management. */
e875093c 10015 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10016 tw32(TG3_CPMU_CTRL,
10017 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10018 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10019 }
10020
9f40dead
MC		 10021 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10022 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10023
321d32a0 10024 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10025 tw32(TG3_CPMU_CTRL, cpmuctrl);
10026
10027 /* Release the mutex */
10028 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10029 }
10030
dd477003
MC		 10031 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10032 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10033 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10034 err |= TG3_PHY_LOOPBACK_FAILED;
10035 }
10036
6833c043
MC		 10037 /* Re-enable gphy autopowerdown. */
10038 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10039 tg3_phy_toggle_apd(tp, true);
10040
9f40dead
MC		 10041 return err;
10042}
10043
4cafd3f5
MC		 10044static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10045 u64 *data)
10046{
566f86ad
MC		 10047 struct tg3 *tp = netdev_priv(dev);
10048
bc1c7567
MC		 10049 if (tp->link_config.phy_is_low_power)
10050 tg3_set_power_state(tp, PCI_D0);
10051
566f86ad
MC		 10052 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10053
10054 if (tg3_test_nvram(tp) != 0) {
10055 etest->flags |= ETH_TEST_FL_FAILED;
10056 data[0] = 1;
10057 }
ca43007a
MC		 10058 if (tg3_test_link(tp) != 0) {
10059 etest->flags |= ETH_TEST_FL_FAILED;
10060 data[1] = 1;
10061 }
a71116d1 10062 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10063 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10064
10065 if (netif_running(dev)) {
b02fd9e3 10066 tg3_phy_stop(tp);
a71116d1 10067 tg3_netif_stop(tp);
bbe832c0
MC		 10068 irq_sync = 1;
10069 }
a71116d1 10070
bbe832c0 10071 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10072
10073 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10074 err = tg3_nvram_lock(tp);
a71116d1
MC		 10075 tg3_halt_cpu(tp, RX_CPU_BASE);
10076 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10077 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10078 if (!err)
10079 tg3_nvram_unlock(tp);
a71116d1 10080
d9ab5ad1
MC		 10081 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10082 tg3_phy_reset(tp);
10083
a71116d1
MC		 10084 if (tg3_test_registers(tp) != 0) {
10085 etest->flags |= ETH_TEST_FL_FAILED;
10086 data[2] = 1;
10087 }
7942e1db
MC		 10088 if (tg3_test_memory(tp) != 0) {
10089 etest->flags |= ETH_TEST_FL_FAILED;
10090 data[3] = 1;
10091 }
9f40dead 10092 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10093 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10094
f47c11ee
DM		 10095 tg3_full_unlock(tp);
10096
d4bc3927
MC		 10097 if (tg3_test_interrupt(tp) != 0) {
10098 etest->flags |= ETH_TEST_FL_FAILED;
10099 data[5] = 1;
10100 }
f47c11ee
DM		 10101
10102 tg3_full_lock(tp, 0);
d4bc3927 10103
a71116d1
MC		 10104 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10105 if (netif_running(dev)) {
10106 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10107 err2 = tg3_restart_hw(tp, 1);
10108 if (!err2)
b9ec6c1b 10109 tg3_netif_start(tp);
a71116d1 10110 }
f47c11ee
DM		 10111
10112 tg3_full_unlock(tp);
b02fd9e3
MC		 10113
10114 if (irq_sync && !err2)
10115 tg3_phy_start(tp);
a71116d1 10116 }
bc1c7567
MC		 10117 if (tp->link_config.phy_is_low_power)
10118 tg3_set_power_state(tp, PCI_D3hot);
10119
4cafd3f5
MC		 10120}
10121
1da177e4
LT		 10122static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10123{
10124 struct mii_ioctl_data *data = if_mii(ifr);
10125 struct tg3 *tp = netdev_priv(dev);
10126 int err;
10127
b02fd9e3
MC		 10128 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10129 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10130 return -EAGAIN;
298cf9be 10131 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10132 }
10133
1da177e4
LT		 10134 switch(cmd) {
10135 case SIOCGMIIPHY:
10136 data->phy_id = PHY_ADDR;
10137
10138 /* fallthru */
10139 case SIOCGMIIREG: {
10140 u32 mii_regval;
10141
10142 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10143 break; /* We have no PHY */
10144
bc1c7567
MC		 10145 if (tp->link_config.phy_is_low_power)
10146 return -EAGAIN;
10147
f47c11ee 10148 spin_lock_bh(&tp->lock);
1da177e4 10149 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10150 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10151
10152 data->val_out = mii_regval;
10153
10154 return err;
10155 }
10156
10157 case SIOCSMIIREG:
10158 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10159 break; /* We have no PHY */
10160
10161 if (!capable(CAP_NET_ADMIN))
10162 return -EPERM;
10163
bc1c7567
MC		 10164 if (tp->link_config.phy_is_low_power)
10165 return -EAGAIN;
10166
f47c11ee 10167 spin_lock_bh(&tp->lock);
1da177e4 10168 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10169 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10170
10171 return err;
10172
10173 default:
10174 /* do nothing */
10175 break;
10176 }
10177 return -EOPNOTSUPP;
10178}
10179
10180#if TG3_VLAN_TAG_USED
10181static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10182{
10183 struct tg3 *tp = netdev_priv(dev);
10184
844b3eed
MC		 10185 if (!netif_running(dev)) {
10186 tp->vlgrp = grp;
10187 return;
10188 }
10189
10190 tg3_netif_stop(tp);
29315e87 10191
f47c11ee 10192 tg3_full_lock(tp, 0);
1da177e4
LT		 10193
10194 tp->vlgrp = grp;
10195
10196 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10197 __tg3_set_rx_mode(dev);
10198
844b3eed 10199 tg3_netif_start(tp);
46966545
MC		 10200
10201 tg3_full_unlock(tp);
1da177e4 10202}
1da177e4
LT		 10203#endif
10204
15f9850d
DM		 10205static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10206{
10207 struct tg3 *tp = netdev_priv(dev);
10208
10209 memcpy(ec, &tp->coal, sizeof(*ec));
10210 return 0;
10211}
10212
d244c892
MC		 10213static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10214{
10215 struct tg3 *tp = netdev_priv(dev);
10216 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10217 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10218
10219 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10220 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10221 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10222 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10223 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10224 }
10225
10226 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10227 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10228 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10229 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10230 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10231 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10232 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10233 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10234 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10235 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10236 return -EINVAL;
10237
10238 /* No rx interrupts will be generated if both are zero */
10239 if ((ec->rx_coalesce_usecs == 0) &&
10240 (ec->rx_max_coalesced_frames == 0))
10241 return -EINVAL;
10242
10243 /* No tx interrupts will be generated if both are zero */
10244 if ((ec->tx_coalesce_usecs == 0) &&
10245 (ec->tx_max_coalesced_frames == 0))
10246 return -EINVAL;
10247
10248 /* Only copy relevant parameters, ignore all others. */
10249 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10250 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10251 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10252 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10253 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10254 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10255 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10256 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10257 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10258
10259 if (netif_running(dev)) {
10260 tg3_full_lock(tp, 0);
10261 __tg3_set_coalesce(tp, &tp->coal);
10262 tg3_full_unlock(tp);
10263 }
10264 return 0;
10265}
10266
7282d491 10267static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10268 .get_settings = tg3_get_settings,
10269 .set_settings = tg3_set_settings,
10270 .get_drvinfo = tg3_get_drvinfo,
10271 .get_regs_len = tg3_get_regs_len,
10272 .get_regs = tg3_get_regs,
10273 .get_wol = tg3_get_wol,
10274 .set_wol = tg3_set_wol,
10275 .get_msglevel = tg3_get_msglevel,
10276 .set_msglevel = tg3_set_msglevel,
10277 .nway_reset = tg3_nway_reset,
10278 .get_link = ethtool_op_get_link,
10279 .get_eeprom_len = tg3_get_eeprom_len,
10280 .get_eeprom = tg3_get_eeprom,
10281 .set_eeprom = tg3_set_eeprom,
10282 .get_ringparam = tg3_get_ringparam,
10283 .set_ringparam = tg3_set_ringparam,
10284 .get_pauseparam = tg3_get_pauseparam,
10285 .set_pauseparam = tg3_set_pauseparam,
10286 .get_rx_csum = tg3_get_rx_csum,
10287 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10288 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10289 .set_sg = ethtool_op_set_sg,
1da177e4 10290 .set_tso = tg3_set_tso,
4cafd3f5 10291 .self_test = tg3_self_test,
1da177e4 10292 .get_strings = tg3_get_strings,
4009a93d 10293 .phys_id = tg3_phys_id,
1da177e4 10294 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10295 .get_coalesce = tg3_get_coalesce,
d244c892 10296 .set_coalesce = tg3_set_coalesce,
b9f2c044 10297 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10298};
10299
10300static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10301{
1b27777a 10302 u32 cursize, val, magic;
1da177e4
LT		 10303
10304 tp->nvram_size = EEPROM_CHIP_SIZE;
10305
e4f34110 10306 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10307 return;
10308
b16250e3
MC		 10309 if ((magic != TG3_EEPROM_MAGIC) &&
10310 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10311 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10312 return;
10313
10314 /*
10315 * Size the chip by reading offsets at increasing powers of two.
10316 * When we encounter our validation signature, we know the addressing
10317 * has wrapped around, and thus have our chip size.
10318 */
1b27777a 10319 cursize = 0x10;
1da177e4
LT		 10320
10321 while (cursize < tp->nvram_size) {
e4f34110 10322 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10323 return;
10324
1820180b 10325 if (val == magic)
1da177e4
LT		 10326 break;
10327
10328 cursize <<= 1;
10329 }
10330
10331 tp->nvram_size = cursize;
10332}
6aa20a22 10333
1da177e4
LT		 10334static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10335{
10336 u32 val;
10337
df259d8c
MC		 10338 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10339 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10340 return;
10341
10342 /* Selfboot format */
1820180b 10343 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10344 tg3_get_eeprom_size(tp);
10345 return;
10346 }
10347
6d348f2c 10348 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10349 if (val != 0) {
6d348f2c
MC		 10350 /* This is confusing. We want to operate on the
10351 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10352 * call will read from NVRAM and byteswap the data
10353 * according to the byteswapping settings for all
10354 * other register accesses. This ensures the data we
10355 * want will always reside in the lower 16-bits.
10356 * However, the data in NVRAM is in LE format, which
10357 * means the data from the NVRAM read will always be
10358 * opposite the endianness of the CPU. The 16-bit
10359 * byteswap then brings the data to CPU endianness.
10360 */
10361 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10362 return;
10363 }
10364 }
fd1122a2 10365 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10366}
10367
10368static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10369{
10370 u32 nvcfg1;
10371
10372 nvcfg1 = tr32(NVRAM_CFG1);
10373 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10374 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10375 } else {
1da177e4
LT		 10376 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10377 tw32(NVRAM_CFG1, nvcfg1);
10378 }
10379
4c987487 10380 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10381 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10382 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10383 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10384 tp->nvram_jedecnum = JEDEC_ATMEL;
10385 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10386 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10387 break;
10388 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10389 tp->nvram_jedecnum = JEDEC_ATMEL;
10390 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10391 break;
10392 case FLASH_VENDOR_ATMEL_EEPROM:
10393 tp->nvram_jedecnum = JEDEC_ATMEL;
10394 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10395 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10396 break;
10397 case FLASH_VENDOR_ST:
10398 tp->nvram_jedecnum = JEDEC_ST;
10399 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10400 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10401 break;
10402 case FLASH_VENDOR_SAIFUN:
10403 tp->nvram_jedecnum = JEDEC_SAIFUN;
10404 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10405 break;
10406 case FLASH_VENDOR_SST_SMALL:
10407 case FLASH_VENDOR_SST_LARGE:
10408 tp->nvram_jedecnum = JEDEC_SST;
10409 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10410 break;
1da177e4 10411 }
8590a603 10412 } else {
1da177e4
LT		 10413 tp->nvram_jedecnum = JEDEC_ATMEL;
10414 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10415 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10416 }
10417}
10418
361b4ac2
MC		 10419static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10420{
10421 u32 nvcfg1;
10422
10423 nvcfg1 = tr32(NVRAM_CFG1);
10424
e6af301b
MC		 10425 /* NVRAM protection for TPM */
10426 if (nvcfg1 & (1 << 27))
10427 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10428
361b4ac2 10429 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10430 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10431 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10432 tp->nvram_jedecnum = JEDEC_ATMEL;
10433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10434 break;
10435 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10436 tp->nvram_jedecnum = JEDEC_ATMEL;
10437 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10438 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10439 break;
10440 case FLASH_5752VENDOR_ST_M45PE10:
10441 case FLASH_5752VENDOR_ST_M45PE20:
10442 case FLASH_5752VENDOR_ST_M45PE40:
10443 tp->nvram_jedecnum = JEDEC_ST;
10444 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10445 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10446 break;
361b4ac2
MC		 10447 }
10448
10449 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10450 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10451 case FLASH_5752PAGE_SIZE_256:
10452 tp->nvram_pagesize = 256;
10453 break;
10454 case FLASH_5752PAGE_SIZE_512:
10455 tp->nvram_pagesize = 512;
10456 break;
10457 case FLASH_5752PAGE_SIZE_1K:
10458 tp->nvram_pagesize = 1024;
10459 break;
10460 case FLASH_5752PAGE_SIZE_2K:
10461 tp->nvram_pagesize = 2048;
10462 break;
10463 case FLASH_5752PAGE_SIZE_4K:
10464 tp->nvram_pagesize = 4096;
10465 break;
10466 case FLASH_5752PAGE_SIZE_264:
10467 tp->nvram_pagesize = 264;
10468 break;
361b4ac2 10469 }
8590a603 10470 } else {
361b4ac2
MC		 10471 /* For eeprom, set pagesize to maximum eeprom size */
10472 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10473
10474 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10475 tw32(NVRAM_CFG1, nvcfg1);
10476 }
10477}
10478
d3c7b886
MC		 10479static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10480{
989a9d23 10481 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10482
10483 nvcfg1 = tr32(NVRAM_CFG1);
10484
10485 /* NVRAM protection for TPM */
989a9d23 10486 if (nvcfg1 & (1 << 27)) {
d3c7b886 10487 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10488 protect = 1;
10489 }
d3c7b886 10490
989a9d23
MC		 10491 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10492 switch (nvcfg1) {
8590a603
MC		 10493 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10494 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10495 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10496 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10497 tp->nvram_jedecnum = JEDEC_ATMEL;
10498 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10499 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10500 tp->nvram_pagesize = 264;
10501 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10502 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10503 tp->nvram_size = (protect ? 0x3e200 :
10504 TG3_NVRAM_SIZE_512KB);
10505 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10506 tp->nvram_size = (protect ? 0x1f200 :
10507 TG3_NVRAM_SIZE_256KB);
10508 else
10509 tp->nvram_size = (protect ? 0x1f200 :
10510 TG3_NVRAM_SIZE_128KB);
10511 break;
10512 case FLASH_5752VENDOR_ST_M45PE10:
10513 case FLASH_5752VENDOR_ST_M45PE20:
10514 case FLASH_5752VENDOR_ST_M45PE40:
10515 tp->nvram_jedecnum = JEDEC_ST;
10516 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10517 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10518 tp->nvram_pagesize = 256;
10519 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10520 tp->nvram_size = (protect ?
10521 TG3_NVRAM_SIZE_64KB :
10522 TG3_NVRAM_SIZE_128KB);
10523 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10524 tp->nvram_size = (protect ?
10525 TG3_NVRAM_SIZE_64KB :
10526 TG3_NVRAM_SIZE_256KB);
10527 else
10528 tp->nvram_size = (protect ?
10529 TG3_NVRAM_SIZE_128KB :
10530 TG3_NVRAM_SIZE_512KB);
10531 break;
d3c7b886
MC		 10532 }
10533}
10534
1b27777a
MC		 10535static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10536{
10537 u32 nvcfg1;
10538
10539 nvcfg1 = tr32(NVRAM_CFG1);
10540
10541 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10542 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10543 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10544 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10545 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10546 tp->nvram_jedecnum = JEDEC_ATMEL;
10547 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10548 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10549
8590a603
MC		 10550 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10551 tw32(NVRAM_CFG1, nvcfg1);
10552 break;
10553 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10554 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10555 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10556 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10557 tp->nvram_jedecnum = JEDEC_ATMEL;
10558 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10559 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10560 tp->nvram_pagesize = 264;
10561 break;
10562 case FLASH_5752VENDOR_ST_M45PE10:
10563 case FLASH_5752VENDOR_ST_M45PE20:
10564 case FLASH_5752VENDOR_ST_M45PE40:
10565 tp->nvram_jedecnum = JEDEC_ST;
10566 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10567 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10568 tp->nvram_pagesize = 256;
10569 break;
1b27777a
MC		 10570 }
10571}
10572
6b91fa02
MC		 10573static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10574{
10575 u32 nvcfg1, protect = 0;
10576
10577 nvcfg1 = tr32(NVRAM_CFG1);
10578
10579 /* NVRAM protection for TPM */
10580 if (nvcfg1 & (1 << 27)) {
10581 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10582 protect = 1;
10583 }
10584
10585 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10586 switch (nvcfg1) {
8590a603
MC		 10587 case FLASH_5761VENDOR_ATMEL_ADB021D:
10588 case FLASH_5761VENDOR_ATMEL_ADB041D:
10589 case FLASH_5761VENDOR_ATMEL_ADB081D:
10590 case FLASH_5761VENDOR_ATMEL_ADB161D:
10591 case FLASH_5761VENDOR_ATMEL_MDB021D:
10592 case FLASH_5761VENDOR_ATMEL_MDB041D:
10593 case FLASH_5761VENDOR_ATMEL_MDB081D:
10594 case FLASH_5761VENDOR_ATMEL_MDB161D:
10595 tp->nvram_jedecnum = JEDEC_ATMEL;
10596 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10597 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10598 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10599 tp->nvram_pagesize = 256;
10600 break;
10601 case FLASH_5761VENDOR_ST_A_M45PE20:
10602 case FLASH_5761VENDOR_ST_A_M45PE40:
10603 case FLASH_5761VENDOR_ST_A_M45PE80:
10604 case FLASH_5761VENDOR_ST_A_M45PE16:
10605 case FLASH_5761VENDOR_ST_M_M45PE20:
10606 case FLASH_5761VENDOR_ST_M_M45PE40:
10607 case FLASH_5761VENDOR_ST_M_M45PE80:
10608 case FLASH_5761VENDOR_ST_M_M45PE16:
10609 tp->nvram_jedecnum = JEDEC_ST;
10610 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10611 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10612 tp->nvram_pagesize = 256;
10613 break;
6b91fa02
MC		 10614 }
10615
10616 if (protect) {
10617 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10618 } else {
10619 switch (nvcfg1) {
8590a603
MC		 10620 case FLASH_5761VENDOR_ATMEL_ADB161D:
10621 case FLASH_5761VENDOR_ATMEL_MDB161D:
10622 case FLASH_5761VENDOR_ST_A_M45PE16:
10623 case FLASH_5761VENDOR_ST_M_M45PE16:
10624 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10625 break;
10626 case FLASH_5761VENDOR_ATMEL_ADB081D:
10627 case FLASH_5761VENDOR_ATMEL_MDB081D:
10628 case FLASH_5761VENDOR_ST_A_M45PE80:
10629 case FLASH_5761VENDOR_ST_M_M45PE80:
10630 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10631 break;
10632 case FLASH_5761VENDOR_ATMEL_ADB041D:
10633 case FLASH_5761VENDOR_ATMEL_MDB041D:
10634 case FLASH_5761VENDOR_ST_A_M45PE40:
10635 case FLASH_5761VENDOR_ST_M_M45PE40:
10636 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10637 break;
10638 case FLASH_5761VENDOR_ATMEL_ADB021D:
10639 case FLASH_5761VENDOR_ATMEL_MDB021D:
10640 case FLASH_5761VENDOR_ST_A_M45PE20:
10641 case FLASH_5761VENDOR_ST_M_M45PE20:
10642 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10643 break;
6b91fa02
MC		 10644 }
10645 }
10646}
10647
b5d3772c
MC		 10648static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10649{
10650 tp->nvram_jedecnum = JEDEC_ATMEL;
10651 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10652 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10653}
10654
321d32a0
MC		 10655static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10656{
10657 u32 nvcfg1;
10658
10659 nvcfg1 = tr32(NVRAM_CFG1);
10660
10661 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10662 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10663 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10664 tp->nvram_jedecnum = JEDEC_ATMEL;
10665 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10666 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10667
10668 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10669 tw32(NVRAM_CFG1, nvcfg1);
10670 return;
10671 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10672 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10673 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10674 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10675 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10676 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10677 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10678 tp->nvram_jedecnum = JEDEC_ATMEL;
10679 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10680 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10681
10682 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10683 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10684 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10685 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10686 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10687 break;
10688 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10689 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10690 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10691 break;
10692 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10693 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10694 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10695 break;
10696 }
10697 break;
10698 case FLASH_5752VENDOR_ST_M45PE10:
10699 case FLASH_5752VENDOR_ST_M45PE20:
10700 case FLASH_5752VENDOR_ST_M45PE40:
10701 tp->nvram_jedecnum = JEDEC_ST;
10702 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10703 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10704
10705 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10706 case FLASH_5752VENDOR_ST_M45PE10:
10707 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10708 break;
10709 case FLASH_5752VENDOR_ST_M45PE20:
10710 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10711 break;
10712 case FLASH_5752VENDOR_ST_M45PE40:
10713 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10714 break;
10715 }
10716 break;
10717 default:
df259d8c 10718 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10719 return;
10720 }
10721
10722 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10723 case FLASH_5752PAGE_SIZE_256:
10724 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10725 tp->nvram_pagesize = 256;
10726 break;
10727 case FLASH_5752PAGE_SIZE_512:
10728 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10729 tp->nvram_pagesize = 512;
10730 break;
10731 case FLASH_5752PAGE_SIZE_1K:
10732 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10733 tp->nvram_pagesize = 1024;
10734 break;
10735 case FLASH_5752PAGE_SIZE_2K:
10736 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10737 tp->nvram_pagesize = 2048;
10738 break;
10739 case FLASH_5752PAGE_SIZE_4K:
10740 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10741 tp->nvram_pagesize = 4096;
10742 break;
10743 case FLASH_5752PAGE_SIZE_264:
10744 tp->nvram_pagesize = 264;
10745 break;
10746 case FLASH_5752PAGE_SIZE_528:
10747 tp->nvram_pagesize = 528;
10748 break;
10749 }
10750}
10751
1da177e4
LT		 10752/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10753static void __devinit tg3_nvram_init(struct tg3 *tp)
10754{
1da177e4
LT		 10755 tw32_f(GRC_EEPROM_ADDR,
10756 (EEPROM_ADDR_FSM_RESET |
10757 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10758 EEPROM_ADDR_CLKPERD_SHIFT)));
10759
9d57f01c 10760 msleep(1);
1da177e4
LT		 10761
10762 /* Enable seeprom accesses. */
10763 tw32_f(GRC_LOCAL_CTRL,
10764 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10765 udelay(100);
10766
10767 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10768 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10769 tp->tg3_flags |= TG3_FLAG_NVRAM;
10770
ec41c7df
MC		 10771 if (tg3_nvram_lock(tp)) {
10772 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10773 "tg3_nvram_init failed.\n", tp->dev->name);
10774 return;
10775 }
e6af301b 10776 tg3_enable_nvram_access(tp);
1da177e4 10777
989a9d23
MC		 10778 tp->nvram_size = 0;
10779
361b4ac2
MC		 10780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10781 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10782 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10783 tg3_get_5755_nvram_info(tp);
d30cdd28 10784 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10785 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10786 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10787 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10788 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10789 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10790 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10791 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10792 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10793 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10794 else
10795 tg3_get_nvram_info(tp);
10796
989a9d23
MC		 10797 if (tp->nvram_size == 0)
10798 tg3_get_nvram_size(tp);
1da177e4 10799
e6af301b 10800 tg3_disable_nvram_access(tp);
381291b7 10801 tg3_nvram_unlock(tp);
1da177e4
LT		 10802
10803 } else {
10804 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10805
10806 tg3_get_eeprom_size(tp);
10807 }
10808}
10809
1da177e4
LT		 10810static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10811 u32 offset, u32 len, u8 *buf)
10812{
10813 int i, j, rc = 0;
10814 u32 val;
10815
10816 for (i = 0; i < len; i += 4) {
b9fc7dc5 10817 u32 addr;
a9dc529d 10818 __be32 data;
1da177e4
LT		 10819
10820 addr = offset + i;
10821
10822 memcpy(&data, buf + i, 4);
10823
62cedd11
MC		 10824 /*
10825 * The SEEPROM interface expects the data to always be opposite
10826 * the native endian format. We accomplish this by reversing
10827 * all the operations that would have been performed on the
10828 * data from a call to tg3_nvram_read_be32().
10829 */
10830 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10831
10832 val = tr32(GRC_EEPROM_ADDR);
10833 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10834
10835 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10836 EEPROM_ADDR_READ);
10837 tw32(GRC_EEPROM_ADDR, val |
10838 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10839 (addr & EEPROM_ADDR_ADDR_MASK) |
10840 EEPROM_ADDR_START |
10841 EEPROM_ADDR_WRITE);
6aa20a22 10842
9d57f01c 10843 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10844 val = tr32(GRC_EEPROM_ADDR);
10845
10846 if (val & EEPROM_ADDR_COMPLETE)
10847 break;
9d57f01c 10848 msleep(1);
1da177e4
LT		 10849 }
10850 if (!(val & EEPROM_ADDR_COMPLETE)) {
10851 rc = -EBUSY;
10852 break;
10853 }
10854 }
10855
10856 return rc;
10857}
10858
10859/* offset and length are dword aligned */
10860static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10861 u8 *buf)
10862{
10863 int ret = 0;
10864 u32 pagesize = tp->nvram_pagesize;
10865 u32 pagemask = pagesize - 1;
10866 u32 nvram_cmd;
10867 u8 *tmp;
10868
10869 tmp = kmalloc(pagesize, GFP_KERNEL);
10870 if (tmp == NULL)
10871 return -ENOMEM;
10872
10873 while (len) {
10874 int j;
e6af301b 10875 u32 phy_addr, page_off, size;
1da177e4
LT		 10876
10877 phy_addr = offset & ~pagemask;
6aa20a22 10878
1da177e4 10879 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10880 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10881 (__be32 *) (tmp + j));
10882 if (ret)
1da177e4
LT		 10883 break;
10884 }
10885 if (ret)
10886 break;
10887
10888 page_off = offset & pagemask;
10889 size = pagesize;
10890 if (len < size)
10891 size = len;
10892
10893 len -= size;
10894
10895 memcpy(tmp + page_off, buf, size);
10896
10897 offset = offset + (pagesize - page_off);
10898
e6af301b 10899 tg3_enable_nvram_access(tp);
1da177e4
LT		 10900
10901 /*
10902 * Before we can erase the flash page, we need
10903 * to issue a special "write enable" command.
10904 */
10905 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10906
10907 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10908 break;
10909
10910 /* Erase the target page */
10911 tw32(NVRAM_ADDR, phy_addr);
10912
10913 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10914 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10915
10916 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10917 break;
10918
10919 /* Issue another write enable to start the write. */
10920 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10921
10922 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10923 break;
10924
10925 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10926 __be32 data;
1da177e4 10927
b9fc7dc5 10928 data = *((__be32 *) (tmp + j));
a9dc529d 10929
b9fc7dc5 10930 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10931
10932 tw32(NVRAM_ADDR, phy_addr + j);
10933
10934 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10935 NVRAM_CMD_WR;
10936
10937 if (j == 0)
10938 nvram_cmd |= NVRAM_CMD_FIRST;
10939 else if (j == (pagesize - 4))
10940 nvram_cmd |= NVRAM_CMD_LAST;
10941
10942 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10943 break;
10944 }
10945 if (ret)
10946 break;
10947 }
10948
10949 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10950 tg3_nvram_exec_cmd(tp, nvram_cmd);
10951
10952 kfree(tmp);
10953
10954 return ret;
10955}
10956
10957/* offset and length are dword aligned */
10958static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10959 u8 *buf)
10960{
10961 int i, ret = 0;
10962
10963 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10964 u32 page_off, phy_addr, nvram_cmd;
10965 __be32 data;
1da177e4
LT		 10966
10967 memcpy(&data, buf + i, 4);
b9fc7dc5 10968 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10969
10970 page_off = offset % tp->nvram_pagesize;
10971
1820180b 10972 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10973
10974 tw32(NVRAM_ADDR, phy_addr);
10975
10976 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10977
10978 if ((page_off == 0) || (i == 0))
10979 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10980 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10981 nvram_cmd |= NVRAM_CMD_LAST;
10982
10983 if (i == (len - 4))
10984 nvram_cmd |= NVRAM_CMD_LAST;
10985
321d32a0
MC		 10986 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10987 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10988 (tp->nvram_jedecnum == JEDEC_ST) &&
10989 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10990
10991 if ((ret = tg3_nvram_exec_cmd(tp,
10992 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10993 NVRAM_CMD_DONE)))
10994
10995 break;
10996 }
10997 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10998 /* We always do complete word writes to eeprom. */
10999 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11000 }
11001
11002 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11003 break;
11004 }
11005 return ret;
11006}
11007
11008/* offset and length are dword aligned */
11009static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11010{
11011 int ret;
11012
1da177e4 11013 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11014 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11015 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11016 udelay(40);
11017 }
11018
11019 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11020 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11021 }
11022 else {
11023 u32 grc_mode;
11024
ec41c7df
MC		 11025 ret = tg3_nvram_lock(tp);
11026 if (ret)
11027 return ret;
1da177e4 11028
e6af301b
MC		 11029 tg3_enable_nvram_access(tp);
11030 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11031 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11032 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11033
11034 grc_mode = tr32(GRC_MODE);
11035 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11036
11037 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11038 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11039
11040 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11041 buf);
11042 }
11043 else {
11044 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11045 buf);
11046 }
11047
11048 grc_mode = tr32(GRC_MODE);
11049 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11050
e6af301b 11051 tg3_disable_nvram_access(tp);
1da177e4
LT		 11052 tg3_nvram_unlock(tp);
11053 }
11054
11055 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11056 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11057 udelay(40);
11058 }
11059
11060 return ret;
11061}
11062
11063struct subsys_tbl_ent {
11064 u16 subsys_vendor, subsys_devid;
11065 u32 phy_id;
11066};
11067
11068static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11069 /* Broadcom boards. */
11070 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11071 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11072 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11073 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11074 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11075 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11076 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11077 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11078 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11079 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11080 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11081
11082 /* 3com boards. */
11083 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11084 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11085 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11086 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11087 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11088
11089 /* DELL boards. */
11090 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11091 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11092 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11093 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11094
11095 /* Compaq boards. */
11096 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11097 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11098 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11099 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11100 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11101
11102 /* IBM boards. */
11103 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11104};
11105
11106static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11107{
11108 int i;
11109
11110 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11111 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11112 tp->pdev->subsystem_vendor) &&
11113 (subsys_id_to_phy_id[i].subsys_devid ==
11114 tp->pdev->subsystem_device))
11115 return &subsys_id_to_phy_id[i];
11116 }
11117 return NULL;
11118}
11119
7d0c41ef 11120static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11121{
1da177e4 11122 u32 val;
caf636c7
MC		 11123 u16 pmcsr;
11124
11125 /* On some early chips the SRAM cannot be accessed in D3hot state,
11126 * so need make sure we're in D0.
11127 */
11128 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11129 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11130 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11131 msleep(1);
7d0c41ef
MC		 11132
11133 /* Make sure register accesses (indirect or otherwise)
11134 * will function correctly.
11135 */
11136 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11137 tp->misc_host_ctrl);
1da177e4 11138
f49639e6
DM		 11139 /* The memory arbiter has to be enabled in order for SRAM accesses
11140 * to succeed. Normally on powerup the tg3 chip firmware will make
11141 * sure it is enabled, but other entities such as system netboot
11142 * code might disable it.
11143 */
11144 val = tr32(MEMARB_MODE);
11145 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11146
1da177e4 11147 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11148 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11149
a85feb8c
GZ		 11150 /* Assume an onboard device and WOL capable by default. */
11151 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11152
b5d3772c 11153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11154 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11155 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11156 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11157 }
0527ba35
MC		 11158 val = tr32(VCPU_CFGSHDW);
11159 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11160 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11161 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11162 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11163 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11164 goto done;
b5d3772c
MC		 11165 }
11166
1da177e4
LT		 11167 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11168 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11169 u32 nic_cfg, led_cfg;
a9daf367 11170 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11171 int eeprom_phy_serdes = 0;
1da177e4
LT		 11172
11173 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11174 tp->nic_sram_data_cfg = nic_cfg;
11175
11176 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11177 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11178 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11179 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11180 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11181 (ver > 0) && (ver < 0x100))
11182 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11183
a9daf367
MC		 11184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11185 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11186
1da177e4
LT		 11187 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11188 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11189 eeprom_phy_serdes = 1;
11190
11191 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11192 if (nic_phy_id != 0) {
11193 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11194 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11195
11196 eeprom_phy_id = (id1 >> 16) << 10;
11197 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11198 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11199 } else
11200 eeprom_phy_id = 0;
11201
7d0c41ef 11202 tp->phy_id = eeprom_phy_id;
747e8f8b 11203 if (eeprom_phy_serdes) {
a4e2b347 11204 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11205 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11206 else
11207 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11208 }
7d0c41ef 11209
cbf46853 11210 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11211 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11212 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11213 else
1da177e4
LT		 11214 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11215
11216 switch (led_cfg) {
11217 default:
11218 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11219 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11220 break;
11221
11222 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11223 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11224 break;
11225
11226 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11227 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11228
11229 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11230 * read on some older 5700/5701 bootcode.
11231 */
11232 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11233 ASIC_REV_5700 ||
11234 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11235 ASIC_REV_5701)
11236 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11237
1da177e4
LT		 11238 break;
11239
11240 case SHASTA_EXT_LED_SHARED:
11241 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11242 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11243 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11244 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11245 LED_CTRL_MODE_PHY_2);
11246 break;
11247
11248 case SHASTA_EXT_LED_MAC:
11249 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11250 break;
11251
11252 case SHASTA_EXT_LED_COMBO:
11253 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11254 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11255 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11256 LED_CTRL_MODE_PHY_2);
11257 break;
11258
855e1111 11259 }
1da177e4
LT		 11260
11261 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11262 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11263 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11264 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11265
b2a5c19c
MC		 11266 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11267 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11268
9d26e213 11269 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11270 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11271 if ((tp->pdev->subsystem_vendor ==
11272 PCI_VENDOR_ID_ARIMA) &&
11273 (tp->pdev->subsystem_device == 0x205a ||
11274 tp->pdev->subsystem_device == 0x2063))
11275 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11276 } else {
f49639e6 11277 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11278 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11279 }
1da177e4
LT		 11280
11281 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11282 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11283 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11284 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11285 }
b2b98d4a
MC		 11286
11287 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11288 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11289 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11290
a85feb8c
GZ		 11291 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11292 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11293 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11294
12dac075 11295 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11296 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11297 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11298
1da177e4
LT		 11299 if (cfg2 & (1 << 17))
11300 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11301
11302 /* serdes signal pre-emphasis in register 0x590 set by */
11303 /* bootcode if bit 18 is set */
11304 if (cfg2 & (1 << 18))
11305 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11306
321d32a0
MC		 11307 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11308 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11309 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11310 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11311
8ed5d97e
MC		 11312 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11313 u32 cfg3;
11314
11315 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11316 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11317 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11318 }
a9daf367
MC		 11319
11320 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11321 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11322 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11323 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11324 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11325 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11326 }
05ac4cb7
MC		 11327done:
11328 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11329 device_set_wakeup_enable(&tp->pdev->dev,
11330 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11331}
11332
b2a5c19c
MC		 11333static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11334{
11335 int i;
11336 u32 val;
11337
11338 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11339 tw32(OTP_CTRL, cmd);
11340
11341 /* Wait for up to 1 ms for command to execute. */
11342 for (i = 0; i < 100; i++) {
11343 val = tr32(OTP_STATUS);
11344 if (val & OTP_STATUS_CMD_DONE)
11345 break;
11346 udelay(10);
11347 }
11348
11349 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11350}
11351
11352/* Read the gphy configuration from the OTP region of the chip. The gphy
11353 * configuration is a 32-bit value that straddles the alignment boundary.
11354 * We do two 32-bit reads and then shift and merge the results.
11355 */
11356static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11357{
11358 u32 bhalf_otp, thalf_otp;
11359
11360 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11361
11362 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11363 return 0;
11364
11365 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11366
11367 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11368 return 0;
11369
11370 thalf_otp = tr32(OTP_READ_DATA);
11371
11372 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11373
11374 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11375 return 0;
11376
11377 bhalf_otp = tr32(OTP_READ_DATA);
11378
11379 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11380}
11381
7d0c41ef
MC		 11382static int __devinit tg3_phy_probe(struct tg3 *tp)
11383{
11384 u32 hw_phy_id_1, hw_phy_id_2;
11385 u32 hw_phy_id, hw_phy_id_masked;
11386 int err;
1da177e4 11387
b02fd9e3
MC		 11388 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11389 return tg3_phy_init(tp);
11390
1da177e4 11391 /* Reading the PHY ID register can conflict with ASF
877d0310 11392 * firmware access to the PHY hardware.
1da177e4
LT		 11393 */
11394 err = 0;
0d3031d9
MC		 11395 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11396 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11397 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11398 } else {
11399 /* Now read the physical PHY_ID from the chip and verify
11400 * that it is sane. If it doesn't look good, we fall back
11401 * to either the hard-coded table based PHY_ID and failing
11402 * that the value found in the eeprom area.
11403 */
11404 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11405 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11406
11407 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11408 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11409 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11410
11411 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11412 }
11413
11414 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11415 tp->phy_id = hw_phy_id;
11416 if (hw_phy_id_masked == PHY_ID_BCM8002)
11417 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11418 else
11419 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11420 } else {
7d0c41ef
MC		 11421 if (tp->phy_id != PHY_ID_INVALID) {
11422 /* Do nothing, phy ID already set up in
11423 * tg3_get_eeprom_hw_cfg().
11424 */
1da177e4
LT		 11425 } else {
11426 struct subsys_tbl_ent *p;
11427
11428 /* No eeprom signature? Try the hardcoded
11429 * subsys device table.
11430 */
11431 p = lookup_by_subsys(tp);
11432 if (!p)
11433 return -ENODEV;
11434
11435 tp->phy_id = p->phy_id;
11436 if (!tp->phy_id ||
11437 tp->phy_id == PHY_ID_BCM8002)
11438 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11439 }
11440 }
11441
747e8f8b 11442 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11443 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11444 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11445 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11446
11447 tg3_readphy(tp, MII_BMSR, &bmsr);
11448 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11449 (bmsr & BMSR_LSTATUS))
11450 goto skip_phy_reset;
6aa20a22 11451
1da177e4
LT		 11452 err = tg3_phy_reset(tp);
11453 if (err)
11454 return err;
11455
11456 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11457 ADVERTISE_100HALF | ADVERTISE_100FULL |
11458 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11459 tg3_ctrl = 0;
11460 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11461 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11462 MII_TG3_CTRL_ADV_1000_FULL);
11463 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11464 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11465 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11466 MII_TG3_CTRL_ENABLE_AS_MASTER);
11467 }
11468
3600d918
MC		 11469 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11470 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11471 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11472 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11473 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11474
11475 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11476 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11477
11478 tg3_writephy(tp, MII_BMCR,
11479 BMCR_ANENABLE | BMCR_ANRESTART);
11480 }
11481 tg3_phy_set_wirespeed(tp);
11482
11483 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11484 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11485 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11486 }
11487
11488skip_phy_reset:
11489 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11490 err = tg3_init_5401phy_dsp(tp);
11491 if (err)
11492 return err;
11493 }
11494
11495 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11496 err = tg3_init_5401phy_dsp(tp);
11497 }
11498
747e8f8b 11499 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11500 tp->link_config.advertising =
11501 (ADVERTISED_1000baseT_Half |
11502 ADVERTISED_1000baseT_Full |
11503 ADVERTISED_Autoneg |
11504 ADVERTISED_FIBRE);
11505 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11506 tp->link_config.advertising &=
11507 ~(ADVERTISED_1000baseT_Half |
11508 ADVERTISED_1000baseT_Full);
11509
11510 return err;
11511}
11512
11513static void __devinit tg3_read_partno(struct tg3 *tp)
11514{
6d348f2c 11515 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11516 unsigned int i;
1b27777a 11517 u32 magic;
1da177e4 11518
df259d8c
MC		 11519 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11520 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11521 goto out_not_found;
1da177e4 11522
1820180b 11523 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11524 for (i = 0; i < 256; i += 4) {
11525 u32 tmp;
1da177e4 11526
6d348f2c
MC		 11527 /* The data is in little-endian format in NVRAM.
11528 * Use the big-endian read routines to preserve
11529 * the byte order as it exists in NVRAM.
11530 */
11531 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11532 goto out_not_found;
11533
6d348f2c 11534 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11535 }
11536 } else {
11537 int vpd_cap;
11538
11539 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11540 for (i = 0; i < 256; i += 4) {
11541 u32 tmp, j = 0;
b9fc7dc5 11542 __le32 v;
1b27777a
MC		 11543 u16 tmp16;
11544
11545 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11546 i);
11547 while (j++ < 100) {
11548 pci_read_config_word(tp->pdev, vpd_cap +
11549 PCI_VPD_ADDR, &tmp16);
11550 if (tmp16 & 0x8000)
11551 break;
11552 msleep(1);
11553 }
f49639e6
DM		 11554 if (!(tmp16 & 0x8000))
11555 goto out_not_found;
11556
1b27777a
MC		 11557 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11558 &tmp);
b9fc7dc5 11559 v = cpu_to_le32(tmp);
6d348f2c 11560 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11561 }
1da177e4
LT		 11562 }
11563
11564 /* Now parse and find the part number. */
af2c6a4a 11565 for (i = 0; i < 254; ) {
1da177e4 11566 unsigned char val = vpd_data[i];
af2c6a4a 11567 unsigned int block_end;
1da177e4
LT		 11568
11569 if (val == 0x82 || val == 0x91) {
11570 i = (i + 3 +
11571 (vpd_data[i + 1] +
11572 (vpd_data[i + 2] << 8)));
11573 continue;
11574 }
11575
11576 if (val != 0x90)
11577 goto out_not_found;
11578
11579 block_end = (i + 3 +
11580 (vpd_data[i + 1] +
11581 (vpd_data[i + 2] << 8)));
11582 i += 3;
af2c6a4a
MC		 11583
11584 if (block_end > 256)
11585 goto out_not_found;
11586
11587 while (i < (block_end - 2)) {
1da177e4
LT		 11588 if (vpd_data[i + 0] == 'P' &&
11589 vpd_data[i + 1] == 'N') {
11590 int partno_len = vpd_data[i + 2];
11591
af2c6a4a
MC		 11592 i += 3;
11593 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11594 goto out_not_found;
11595
11596 memcpy(tp->board_part_number,
af2c6a4a 11597 &vpd_data[i], partno_len);
1da177e4
LT		 11598
11599 /* Success. */
11600 return;
11601 }
af2c6a4a 11602 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11603 }
11604
11605 /* Part number not found. */
11606 goto out_not_found;
11607 }
11608
11609out_not_found:
b5d3772c
MC		 11610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11611 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11612 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11613 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11614 strcpy(tp->board_part_number, "BCM57780");
11615 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11616 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11617 strcpy(tp->board_part_number, "BCM57760");
11618 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11619 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11620 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11621 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11622 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11623 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11624 else
11625 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11626}
11627
9c8a620e
MC		 11628static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11629{
11630 u32 val;
11631
e4f34110 11632 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11633 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11634 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11635 val != 0)
11636 return 0;
11637
11638 return 1;
11639}
11640
acd9c119
MC		 11641static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11642{
ff3a7cb2 11643 u32 val, offset, start, ver_offset;
acd9c119 11644 int i;
ff3a7cb2 11645 bool newver = false;
acd9c119
MC		 11646
11647 if (tg3_nvram_read(tp, 0xc, &offset) ||
11648 tg3_nvram_read(tp, 0x4, &start))
11649 return;
11650
11651 offset = tg3_nvram_logical_addr(tp, offset);
11652
ff3a7cb2 11653 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11654 return;
11655
ff3a7cb2
MC		 11656 if ((val & 0xfc000000) == 0x0c000000) {
11657 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11658 return;
11659
ff3a7cb2
MC		 11660 if (val == 0)
11661 newver = true;
11662 }
11663
11664 if (newver) {
11665 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11666 return;
11667
11668 offset = offset + ver_offset - start;
11669 for (i = 0; i < 16; i += 4) {
11670 __be32 v;
11671 if (tg3_nvram_read_be32(tp, offset + i, &v))
11672 return;
11673
11674 memcpy(tp->fw_ver + i, &v, sizeof(v));
11675 }
11676 } else {
11677 u32 major, minor;
11678
11679 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11680 return;
11681
11682 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11683 TG3_NVM_BCVER_MAJSFT;
11684 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11685 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11686 }
11687}
11688
a6f6cb1c
MC		 11689static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11690{
11691 u32 val, major, minor;
11692
11693 /* Use native endian representation */
11694 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11695 return;
11696
11697 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11698 TG3_NVM_HWSB_CFG1_MAJSFT;
11699 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11700 TG3_NVM_HWSB_CFG1_MINSFT;
11701
11702 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11703}
11704
dfe00d7d
MC		 11705static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11706{
11707 u32 offset, major, minor, build;
11708
11709 tp->fw_ver[0] = 's';
11710 tp->fw_ver[1] = 'b';
11711 tp->fw_ver[2] = '\0';
11712
11713 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11714 return;
11715
11716 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11717 case TG3_EEPROM_SB_REVISION_0:
11718 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11719 break;
11720 case TG3_EEPROM_SB_REVISION_2:
11721 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11722 break;
11723 case TG3_EEPROM_SB_REVISION_3:
11724 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11725 break;
11726 default:
11727 return;
11728 }
11729
e4f34110 11730 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11731 return;
11732
11733 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11734 TG3_EEPROM_SB_EDH_BLD_SHFT;
11735 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11736 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11737 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11738
11739 if (minor > 99 || build > 26)
11740 return;
11741
11742 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11743
11744 if (build > 0) {
11745 tp->fw_ver[8] = 'a' + build - 1;
11746 tp->fw_ver[9] = '\0';
11747 }
11748}
11749
acd9c119 11750static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11751{
11752 u32 val, offset, start;
acd9c119 11753 int i, vlen;
9c8a620e
MC		 11754
11755 for (offset = TG3_NVM_DIR_START;
11756 offset < TG3_NVM_DIR_END;
11757 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11758 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11759 return;
11760
9c8a620e
MC		 11761 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11762 break;
11763 }
11764
11765 if (offset == TG3_NVM_DIR_END)
11766 return;
11767
11768 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11769 start = 0x08000000;
e4f34110 11770 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11771 return;
11772
e4f34110 11773 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11774 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11775 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11776 return;
11777
11778 offset += val - start;
11779
acd9c119 11780 vlen = strlen(tp->fw_ver);
9c8a620e 11781
acd9c119
MC		 11782 tp->fw_ver[vlen++] = ',';
11783 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11784
11785 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11786 __be32 v;
11787 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11788 return;
11789
b9fc7dc5 11790 offset += sizeof(v);
c4e6575c 11791
acd9c119
MC		 11792 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11793 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11794 break;
c4e6575c 11795 }
9c8a620e 11796
acd9c119
MC		 11797 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11798 vlen += sizeof(v);
c4e6575c 11799 }
acd9c119
MC		 11800}
11801
7fd76445
MC		 11802static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11803{
11804 int vlen;
11805 u32 apedata;
11806
11807 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11808 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11809 return;
11810
11811 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11812 if (apedata != APE_SEG_SIG_MAGIC)
11813 return;
11814
11815 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11816 if (!(apedata & APE_FW_STATUS_READY))
11817 return;
11818
11819 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11820
11821 vlen = strlen(tp->fw_ver);
11822
11823 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11824 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11825 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11826 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11827 (apedata & APE_FW_VERSION_BLDMSK));
11828}
11829
acd9c119
MC		 11830static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11831{
11832 u32 val;
11833
df259d8c
MC		 11834 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11835 tp->fw_ver[0] = 's';
11836 tp->fw_ver[1] = 'b';
11837 tp->fw_ver[2] = '\0';
11838
11839 return;
11840 }
11841
acd9c119
MC		 11842 if (tg3_nvram_read(tp, 0, &val))
11843 return;
11844
11845 if (val == TG3_EEPROM_MAGIC)
11846 tg3_read_bc_ver(tp);
11847 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11848 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11849 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11850 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11851 else
11852 return;
11853
11854 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11855 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11856 return;
11857
11858 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11859
11860 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11861}
11862
7544b097
MC		 11863static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11864
1da177e4
LT		 11865static int __devinit tg3_get_invariants(struct tg3 *tp)
11866{
11867 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11868 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11869 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11870 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11871 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11872 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11873 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11874 { },
11875 };
11876 u32 misc_ctrl_reg;
1da177e4
LT		 11877 u32 pci_state_reg, grc_misc_cfg;
11878 u32 val;
11879 u16 pci_cmd;
5e7dfd0f 11880 int err;
1da177e4 11881
1da177e4
LT		 11882 /* Force memory write invalidate off. If we leave it on,
11883 * then on 5700_BX chips we have to enable a workaround.
11884 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11885 * to match the cacheline size. The Broadcom driver have this
11886 * workaround but turns MWI off all the times so never uses
11887 * it. This seems to suggest that the workaround is insufficient.
11888 */
11889 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11890 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11891 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11892
11893 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11894 * has the register indirect write enable bit set before
11895 * we try to access any of the MMIO registers. It is also
11896 * critical that the PCI-X hw workaround situation is decided
11897 * before that as well.
11898 */
11899 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11900 &misc_ctrl_reg);
11901
11902 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11903 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11905 u32 prod_id_asic_rev;
11906
11907 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11908 &prod_id_asic_rev);
321d32a0 11909 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11910 }
1da177e4 11911
ff645bec
MC		 11912 /* Wrong chip ID in 5752 A0. This code can be removed later
11913 * as A0 is not in production.
11914 */
11915 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11916 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11917
6892914f
MC		 11918 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11919 * we need to disable memory and use config. cycles
11920 * only to access all registers. The 5702/03 chips
11921 * can mistakenly decode the special cycles from the
11922 * ICH chipsets as memory write cycles, causing corruption
11923 * of register and memory space. Only certain ICH bridges
11924 * will drive special cycles with non-zero data during the
11925 * address phase which can fall within the 5703's address
11926 * range. This is not an ICH bug as the PCI spec allows
11927 * non-zero address during special cycles. However, only
11928 * these ICH bridges are known to drive non-zero addresses
11929 * during special cycles.
11930 *
11931 * Since special cycles do not cross PCI bridges, we only
11932 * enable this workaround if the 5703 is on the secondary
11933 * bus of these ICH bridges.
11934 */
11935 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11936 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11937 static struct tg3_dev_id {
11938 u32 vendor;
11939 u32 device;
11940 u32 rev;
11941 } ich_chipsets[] = {
11942 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11943 PCI_ANY_ID },
11944 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11945 PCI_ANY_ID },
11946 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11947 0xa },
11948 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11949 PCI_ANY_ID },
11950 { },
11951 };
11952 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11953 struct pci_dev *bridge = NULL;
11954
11955 while (pci_id->vendor != 0) {
11956 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11957 bridge);
11958 if (!bridge) {
11959 pci_id++;
11960 continue;
11961 }
11962 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11963 if (bridge->revision > pci_id->rev)
6892914f
MC		 11964 continue;
11965 }
11966 if (bridge->subordinate &&
11967 (bridge->subordinate->number ==
11968 tp->pdev->bus->number)) {
11969
11970 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11971 pci_dev_put(bridge);
11972 break;
11973 }
11974 }
11975 }
11976
41588ba1
MC		 11977 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11978 static struct tg3_dev_id {
11979 u32 vendor;
11980 u32 device;
11981 } bridge_chipsets[] = {
11982 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11983 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11984 { },
11985 };
11986 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11987 struct pci_dev *bridge = NULL;
11988
11989 while (pci_id->vendor != 0) {
11990 bridge = pci_get_device(pci_id->vendor,
11991 pci_id->device,
11992 bridge);
11993 if (!bridge) {
11994 pci_id++;
11995 continue;
11996 }
11997 if (bridge->subordinate &&
11998 (bridge->subordinate->number <=
11999 tp->pdev->bus->number) &&
12000 (bridge->subordinate->subordinate >=
12001 tp->pdev->bus->number)) {
12002 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12003 pci_dev_put(bridge);
12004 break;
12005 }
12006 }
12007 }
12008
4a29cc2e
MC		 12009 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12010 * DMA addresses > 40-bit. This bridge may have other additional
12011 * 57xx devices behind it in some 4-port NIC designs for example.
12012 * Any tg3 device found behind the bridge will also need the 40-bit
12013 * DMA workaround.
12014 */
a4e2b347
MC		 12015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12017 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12018 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12019 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12020 }
4a29cc2e
MC		 12021 else {
12022 struct pci_dev *bridge = NULL;
12023
12024 do {
12025 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12026 PCI_DEVICE_ID_SERVERWORKS_EPB,
12027 bridge);
12028 if (bridge && bridge->subordinate &&
12029 (bridge->subordinate->number <=
12030 tp->pdev->bus->number) &&
12031 (bridge->subordinate->subordinate >=
12032 tp->pdev->bus->number)) {
12033 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12034 pci_dev_put(bridge);
12035 break;
12036 }
12037 } while (bridge);
12038 }
4cf78e4f 12039
1da177e4
LT		 12040 /* Initialize misc host control in PCI block. */
12041 tp->misc_host_ctrl |= (misc_ctrl_reg &
12042 MISC_HOST_CTRL_CHIPREV);
12043 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12044 tp->misc_host_ctrl);
12045
7544b097
MC		 12046 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12047 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12048 tp->pdev_peer = tg3_find_peer(tp);
12049
321d32a0
MC		 12050 /* Intentionally exclude ASIC_REV_5906 */
12051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 12056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12057 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12058
12059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12062 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12063 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12064 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12065
1b440c56
JL		 12066 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12067 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12068 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12069
027455ad
MC		 12070 /* 5700 B0 chips do not support checksumming correctly due
12071 * to hardware bugs.
12072 */
12073 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12074 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12075 else {
12076 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12077 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12078 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12079 tp->dev->features |= NETIF_F_IPV6_CSUM;
12080 }
12081
5a6f3074 12082 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12083 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12084 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12085 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12086 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12087 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12088 tp->pdev_peer == tp->pdev))
12089 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12090
321d32a0 12091 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12093 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12094 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12095 } else {
7f62ad5d 12096 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12097 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12098 ASIC_REV_5750 &&
12099 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12100 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12101 }
5a6f3074 12102 }
1da177e4 12103
f51f3562
MC		 12104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12105 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12106 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12107
52f4490c
MC		 12108 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12109 &pci_state_reg);
12110
5e7dfd0f
MC		 12111 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12112 if (tp->pcie_cap != 0) {
12113 u16 lnkctl;
12114
1da177e4 12115 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12116
12117 pcie_set_readrq(tp->pdev, 4096);
12118
5e7dfd0f
MC		 12119 pci_read_config_word(tp->pdev,
12120 tp->pcie_cap + PCI_EXP_LNKCTL,
12121 &lnkctl);
12122 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12124 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12127 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12128 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12129 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12130 }
52f4490c 12131 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12132 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12133 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12134 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12135 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12136 if (!tp->pcix_cap) {
12137 printk(KERN_ERR PFX "Cannot find PCI-X "
12138 "capability, aborting.\n");
12139 return -EIO;
12140 }
12141
12142 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12143 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12144 }
1da177e4 12145
399de50b
MC		 12146 /* If we have an AMD 762 or VIA K8T800 chipset, write
12147 * reordering to the mailbox registers done by the host
12148 * controller can cause major troubles. We read back from
12149 * every mailbox register write to force the writes to be
12150 * posted to the chip in order.
12151 */
12152 if (pci_dev_present(write_reorder_chipsets) &&
12153 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12154 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12155
69fc4053
MC		 12156 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12157 &tp->pci_cacheline_sz);
12158 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12159 &tp->pci_lat_timer);
1da177e4
LT		 12160 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12161 tp->pci_lat_timer < 64) {
12162 tp->pci_lat_timer = 64;
69fc4053
MC		 12163 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12164 tp->pci_lat_timer);
1da177e4
LT		 12165 }
12166
52f4490c
MC		 12167 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12168 /* 5700 BX chips need to have their TX producer index
12169 * mailboxes written twice to workaround a bug.
12170 */
12171 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12172
52f4490c 12173 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12174 *
12175 * The workaround is to use indirect register accesses
12176 * for all chip writes not to mailbox registers.
12177 */
52f4490c 12178 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12179 u32 pm_reg;
1da177e4
LT		 12180
12181 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12182
12183 /* The chip can have it's power management PCI config
12184 * space registers clobbered due to this bug.
12185 * So explicitly force the chip into D0 here.
12186 */
9974a356
MC		 12187 pci_read_config_dword(tp->pdev,
12188 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12189 &pm_reg);
12190 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12191 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12192 pci_write_config_dword(tp->pdev,
12193 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12194 pm_reg);
12195
12196 /* Also, force SERR#/PERR# in PCI command. */
12197 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12198 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12199 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12200 }
12201 }
12202
1da177e4
LT		 12203 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12204 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12205 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12206 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12207
12208 /* Chip-specific fixup from Broadcom driver */
12209 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12210 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12211 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12212 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12213 }
12214
1ee582d8 12215 /* Default fast path register access methods */
20094930 12216 tp->read32 = tg3_read32;
1ee582d8 12217 tp->write32 = tg3_write32;
09ee929c 12218 tp->read32_mbox = tg3_read32;
20094930 12219 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12220 tp->write32_tx_mbox = tg3_write32;
12221 tp->write32_rx_mbox = tg3_write32;
12222
12223 /* Various workaround register access methods */
12224 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12225 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12226 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12227 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12228 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12229 /*
12230 * Back to back register writes can cause problems on these
12231 * chips, the workaround is to read back all reg writes
12232 * except those to mailbox regs.
12233 *
12234 * See tg3_write_indirect_reg32().
12235 */
1ee582d8 12236 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12237 }
12238
1ee582d8
MC		 12239
12240 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12241 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12242 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12243 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12244 tp->write32_rx_mbox = tg3_write_flush_reg32;
12245 }
20094930 12246
6892914f
MC		 12247 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12248 tp->read32 = tg3_read_indirect_reg32;
12249 tp->write32 = tg3_write_indirect_reg32;
12250 tp->read32_mbox = tg3_read_indirect_mbox;
12251 tp->write32_mbox = tg3_write_indirect_mbox;
12252 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12253 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12254
12255 iounmap(tp->regs);
22abe310 12256 tp->regs = NULL;
6892914f
MC		 12257
12258 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12259 pci_cmd &= ~PCI_COMMAND_MEMORY;
12260 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12261 }
b5d3772c
MC		 12262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12263 tp->read32_mbox = tg3_read32_mbox_5906;
12264 tp->write32_mbox = tg3_write32_mbox_5906;
12265 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12266 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12267 }
6892914f 12268
bbadf503
MC		 12269 if (tp->write32 == tg3_write_indirect_reg32 ||
12270 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12271 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12273 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12274
7d0c41ef 12275 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12276 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12277 * determined before calling tg3_set_power_state() so that
12278 * we know whether or not to switch out of Vaux power.
12279 * When the flag is set, it means that GPIO1 is used for eeprom
12280 * write protect and also implies that it is a LOM where GPIOs
12281 * are not used to switch power.
6aa20a22 12282 */
7d0c41ef
MC		 12283 tg3_get_eeprom_hw_cfg(tp);
12284
0d3031d9
MC		 12285 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12286 /* Allow reads and writes to the
12287 * APE register and memory space.
12288 */
12289 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12290 PCISTATE_ALLOW_APE_SHMEM_WR;
12291 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12292 pci_state_reg);
12293 }
12294
9936bcf6 12295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12299 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12300
314fba34
MC		 12301 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12302 * GPIO1 driven high will bring 5700's external PHY out of reset.
12303 * It is also used as eeprom write protect on LOMs.
12304 */
12305 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12306 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12307 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12308 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12309 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12310 /* Unused GPIO3 must be driven as output on 5752 because there
12311 * are no pull-up resistors on unused GPIO pins.
12312 */
12313 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12314 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12315
321d32a0
MC		 12316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12318 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12319
8d519ab2
MC		 12320 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12321 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12322 /* Turn off the debug UART. */
12323 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12324 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12325 /* Keep VMain power. */
12326 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12327 GRC_LCLCTRL_GPIO_OUTPUT0;
12328 }
12329
1da177e4 12330 /* Force the chip into D0. */
bc1c7567 12331 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12332 if (err) {
12333 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12334 pci_name(tp->pdev));
12335 return err;
12336 }
12337
1da177e4
LT		 12338 /* Derive initial jumbo mode from MTU assigned in
12339 * ether_setup() via the alloc_etherdev() call
12340 */
0f893dc6 12341 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12342 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12343 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12344
12345 /* Determine WakeOnLan speed to use. */
12346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12347 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12348 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12349 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12350 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12351 } else {
12352 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12353 }
12354
7f97a4bd
MC		 12355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12356 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12357
1da177e4
LT		 12358 /* A few boards don't want Ethernet@WireSpeed phy feature */
12359 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12360 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12361 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12362 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12363 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12364 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12365 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12366
12367 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12368 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12369 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12370 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12371 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12372
321d32a0 12373 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12374 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12375 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12376 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12380 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12381 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12382 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12383 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12384 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12385 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12386 } else
c424cb24
MC		 12387 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12388 }
1da177e4 12389
b2a5c19c
MC		 12390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12391 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12392 tp->phy_otp = tg3_read_otp_phycfg(tp);
12393 if (tp->phy_otp == 0)
12394 tp->phy_otp = TG3_OTP_DEFAULT;
12395 }
12396
f51f3562 12397 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12398 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12399 else
12400 tp->mi_mode = MAC_MI_MODE_BASE;
12401
1da177e4 12402 tp->coalesce_mode = 0;
1da177e4
LT		 12403 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12404 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12405 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12406
321d32a0
MC		 12407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12409 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12410
255ca311
MC		 12411 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12412 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12413 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12414 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12415
158d7abd
MC		 12416 err = tg3_mdio_init(tp);
12417 if (err)
12418 return err;
1da177e4
LT		 12419
12420 /* Initialize data/descriptor byte/word swapping. */
12421 val = tr32(GRC_MODE);
12422 val &= GRC_MODE_HOST_STACKUP;
12423 tw32(GRC_MODE, val | tp->grc_mode);
12424
12425 tg3_switch_clocks(tp);
12426
12427 /* Clear this out for sanity. */
12428 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12429
12430 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12431 &pci_state_reg);
12432 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12433 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12434 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12435
12436 if (chiprevid == CHIPREV_ID_5701_A0 ||
12437 chiprevid == CHIPREV_ID_5701_B0 ||
12438 chiprevid == CHIPREV_ID_5701_B2 ||
12439 chiprevid == CHIPREV_ID_5701_B5) {
12440 void __iomem *sram_base;
12441
12442 /* Write some dummy words into the SRAM status block
12443 * area, see if it reads back correctly. If the return
12444 * value is bad, force enable the PCIX workaround.
12445 */
12446 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12447
12448 writel(0x00000000, sram_base);
12449 writel(0x00000000, sram_base + 4);
12450 writel(0xffffffff, sram_base + 4);
12451 if (readl(sram_base) != 0x00000000)
12452 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12453 }
12454 }
12455
12456 udelay(50);
12457 tg3_nvram_init(tp);
12458
12459 grc_misc_cfg = tr32(GRC_MISC_CFG);
12460 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12461
1da177e4
LT		 12462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12463 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12464 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12465 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12466
fac9b83e
DM		 12467 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12468 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12469 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12470 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12471 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12472 HOSTCC_MODE_CLRTICK_TXBD);
12473
12474 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12475 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12476 tp->misc_host_ctrl);
12477 }
12478
3bda1258
MC		 12479 /* Preserve the APE MAC_MODE bits */
12480 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12481 tp->mac_mode = tr32(MAC_MODE) |
12482 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12483 else
12484 tp->mac_mode = TG3_DEF_MAC_MODE;
12485
1da177e4
LT		 12486 /* these are limited to 10/100 only */
12487 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12488 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12489 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12490 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12491 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12492 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12493 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12494 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12495 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12496 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12497 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12498 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12499 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12500 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12501
12502 err = tg3_phy_probe(tp);
12503 if (err) {
12504 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12505 pci_name(tp->pdev), err);
12506 /* ... but do not return immediately ... */
b02fd9e3 12507 tg3_mdio_fini(tp);
1da177e4
LT		 12508 }
12509
12510 tg3_read_partno(tp);
c4e6575c 12511 tg3_read_fw_ver(tp);
1da177e4
LT		 12512
12513 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12514 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12515 } else {
12516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12517 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12518 else
12519 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12520 }
12521
12522 /* 5700 {AX,BX} chips have a broken status block link
12523 * change bit implementation, so we must use the
12524 * status register in those cases.
12525 */
12526 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12527 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12528 else
12529 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12530
12531 /* The led_ctrl is set during tg3_phy_probe, here we might
12532 * have to force the link status polling mechanism based
12533 * upon subsystem IDs.
12534 */
12535 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12537 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12538 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12539 TG3_FLAG_USE_LINKCHG_REG);
12540 }
12541
12542 /* For all SERDES we poll the MAC status register. */
12543 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12544 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12545 else
12546 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12547
ad829268 12548 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12550 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12551 tp->rx_offset = 0;
12552
f92905de
MC		 12553 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12554
12555 /* Increment the rx prod index on the rx std ring by at most
12556 * 8 for these chips to workaround hw errata.
12557 */
12558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12560 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12561 tp->rx_std_max_post = 8;
12562
8ed5d97e
MC		 12563 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12564 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12565 PCIE_PWR_MGMT_L1_THRESH_MSK;
12566
1da177e4
LT		 12567 return err;
12568}
12569
49b6e95f 12570#ifdef CONFIG_SPARC
1da177e4
LT		 12571static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12572{
12573 struct net_device *dev = tp->dev;
12574 struct pci_dev *pdev = tp->pdev;
49b6e95f 12575 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12576 const unsigned char *addr;
49b6e95f
DM		 12577 int len;
12578
12579 addr = of_get_property(dp, "local-mac-address", &len);
12580 if (addr && len == 6) {
12581 memcpy(dev->dev_addr, addr, 6);
12582 memcpy(dev->perm_addr, dev->dev_addr, 6);
12583 return 0;
1da177e4
LT		 12584 }
12585 return -ENODEV;
12586}
12587
12588static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12589{
12590 struct net_device *dev = tp->dev;
12591
12592 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12593 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12594 return 0;
12595}
12596#endif
12597
12598static int __devinit tg3_get_device_address(struct tg3 *tp)
12599{
12600 struct net_device *dev = tp->dev;
12601 u32 hi, lo, mac_offset;
008652b3 12602 int addr_ok = 0;
1da177e4 12603
49b6e95f 12604#ifdef CONFIG_SPARC
1da177e4
LT		 12605 if (!tg3_get_macaddr_sparc(tp))
12606 return 0;
12607#endif
12608
12609 mac_offset = 0x7c;
f49639e6 12610 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12611 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12612 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12613 mac_offset = 0xcc;
12614 if (tg3_nvram_lock(tp))
12615 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12616 else
12617 tg3_nvram_unlock(tp);
12618 }
b5d3772c
MC		 12619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12620 mac_offset = 0x10;
1da177e4
LT		 12621
12622 /* First try to get it from MAC address mailbox. */
12623 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12624 if ((hi >> 16) == 0x484b) {
12625 dev->dev_addr[0] = (hi >> 8) & 0xff;
12626 dev->dev_addr[1] = (hi >> 0) & 0xff;
12627
12628 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12629 dev->dev_addr[2] = (lo >> 24) & 0xff;
12630 dev->dev_addr[3] = (lo >> 16) & 0xff;
12631 dev->dev_addr[4] = (lo >> 8) & 0xff;
12632 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12633
008652b3
MC		 12634 /* Some old bootcode may report a 0 MAC address in SRAM */
12635 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12636 }
12637 if (!addr_ok) {
12638 /* Next, try NVRAM. */
df259d8c
MC		 12639 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12640 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12641 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12642 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12643 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12644 }
12645 /* Finally just fetch it out of the MAC control regs. */
12646 else {
12647 hi = tr32(MAC_ADDR_0_HIGH);
12648 lo = tr32(MAC_ADDR_0_LOW);
12649
12650 dev->dev_addr[5] = lo & 0xff;
12651 dev->dev_addr[4] = (lo >> 8) & 0xff;
12652 dev->dev_addr[3] = (lo >> 16) & 0xff;
12653 dev->dev_addr[2] = (lo >> 24) & 0xff;
12654 dev->dev_addr[1] = hi & 0xff;
12655 dev->dev_addr[0] = (hi >> 8) & 0xff;
12656 }
1da177e4
LT		 12657 }
12658
12659 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12660#ifdef CONFIG_SPARC
1da177e4
LT		 12661 if (!tg3_get_default_macaddr_sparc(tp))
12662 return 0;
12663#endif
12664 return -EINVAL;
12665 }
2ff43697 12666 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12667 return 0;
12668}
12669
59e6b434
DM		 12670#define BOUNDARY_SINGLE_CACHELINE 1
12671#define BOUNDARY_MULTI_CACHELINE 2
12672
12673static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12674{
12675 int cacheline_size;
12676 u8 byte;
12677 int goal;
12678
12679 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12680 if (byte == 0)
12681 cacheline_size = 1024;
12682 else
12683 cacheline_size = (int) byte * 4;
12684
12685 /* On 5703 and later chips, the boundary bits have no
12686 * effect.
12687 */
12688 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12689 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12690 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12691 goto out;
12692
12693#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12694 goal = BOUNDARY_MULTI_CACHELINE;
12695#else
12696#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12697 goal = BOUNDARY_SINGLE_CACHELINE;
12698#else
12699 goal = 0;
12700#endif
12701#endif
12702
12703 if (!goal)
12704 goto out;
12705
12706 /* PCI controllers on most RISC systems tend to disconnect
12707 * when a device tries to burst across a cache-line boundary.
12708 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12709 *
12710 * Unfortunately, for PCI-E there are only limited
12711 * write-side controls for this, and thus for reads
12712 * we will still get the disconnects. We'll also waste
12713 * these PCI cycles for both read and write for chips
12714 * other than 5700 and 5701 which do not implement the
12715 * boundary bits.
12716 */
12717 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12718 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12719 switch (cacheline_size) {
12720 case 16:
12721 case 32:
12722 case 64:
12723 case 128:
12724 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12725 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12726 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12727 } else {
12728 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12729 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12730 }
12731 break;
12732
12733 case 256:
12734 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12735 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12736 break;
12737
12738 default:
12739 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12740 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12741 break;
855e1111 12742 }
59e6b434
DM		 12743 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12744 switch (cacheline_size) {
12745 case 16:
12746 case 32:
12747 case 64:
12748 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12749 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12750 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12751 break;
12752 }
12753 /* fallthrough */
12754 case 128:
12755 default:
12756 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12757 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12758 break;
855e1111 12759 }
59e6b434
DM		 12760 } else {
12761 switch (cacheline_size) {
12762 case 16:
12763 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12764 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12765 DMA_RWCTRL_WRITE_BNDRY_16);
12766 break;
12767 }
12768 /* fallthrough */
12769 case 32:
12770 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12771 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12772 DMA_RWCTRL_WRITE_BNDRY_32);
12773 break;
12774 }
12775 /* fallthrough */
12776 case 64:
12777 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12778 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12779 DMA_RWCTRL_WRITE_BNDRY_64);
12780 break;
12781 }
12782 /* fallthrough */
12783 case 128:
12784 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12785 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12786 DMA_RWCTRL_WRITE_BNDRY_128);
12787 break;
12788 }
12789 /* fallthrough */
12790 case 256:
12791 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12792 DMA_RWCTRL_WRITE_BNDRY_256);
12793 break;
12794 case 512:
12795 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12796 DMA_RWCTRL_WRITE_BNDRY_512);
12797 break;
12798 case 1024:
12799 default:
12800 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12801 DMA_RWCTRL_WRITE_BNDRY_1024);
12802 break;
855e1111 12803 }
59e6b434
DM		 12804 }
12805
12806out:
12807 return val;
12808}
12809
1da177e4
LT		 12810static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12811{
12812 struct tg3_internal_buffer_desc test_desc;
12813 u32 sram_dma_descs;
12814 int i, ret;
12815
12816 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12817
12818 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12819 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12820 tw32(RDMAC_STATUS, 0);
12821 tw32(WDMAC_STATUS, 0);
12822
12823 tw32(BUFMGR_MODE, 0);
12824 tw32(FTQ_RESET, 0);
12825
12826 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12827 test_desc.addr_lo = buf_dma & 0xffffffff;
12828 test_desc.nic_mbuf = 0x00002100;
12829 test_desc.len = size;
12830
12831 /*
12832 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12833 * the *second* time the tg3 driver was getting loaded after an
12834 * initial scan.
12835 *
12836 * Broadcom tells me:
12837 * ...the DMA engine is connected to the GRC block and a DMA
12838 * reset may affect the GRC block in some unpredictable way...
12839 * The behavior of resets to individual blocks has not been tested.
12840 *
12841 * Broadcom noted the GRC reset will also reset all sub-components.
12842 */
12843 if (to_device) {
12844 test_desc.cqid_sqid = (13 << 8) | 2;
12845
12846 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12847 udelay(40);
12848 } else {
12849 test_desc.cqid_sqid = (16 << 8) | 7;
12850
12851 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12852 udelay(40);
12853 }
12854 test_desc.flags = 0x00000005;
12855
12856 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12857 u32 val;
12858
12859 val = *(((u32 *)&test_desc) + i);
12860 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12861 sram_dma_descs + (i * sizeof(u32)));
12862 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12863 }
12864 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12865
12866 if (to_device) {
12867 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12868 } else {
12869 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12870 }
12871
12872 ret = -ENODEV;
12873 for (i = 0; i < 40; i++) {
12874 u32 val;
12875
12876 if (to_device)
12877 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12878 else
12879 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12880 if ((val & 0xffff) == sram_dma_descs) {
12881 ret = 0;
12882 break;
12883 }
12884
12885 udelay(100);
12886 }
12887
12888 return ret;
12889}
12890
ded7340d 12891#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12892
12893static int __devinit tg3_test_dma(struct tg3 *tp)
12894{
12895 dma_addr_t buf_dma;
59e6b434 12896 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12897 int ret;
12898
12899 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12900 if (!buf) {
12901 ret = -ENOMEM;
12902 goto out_nofree;
12903 }
12904
12905 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12906 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12907
59e6b434 12908 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12909
12910 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12911 /* DMA read watermark not used on PCIE */
12912 tp->dma_rwctrl |= 0x00180000;
12913 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12914 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12916 tp->dma_rwctrl |= 0x003f0000;
12917 else
12918 tp->dma_rwctrl |= 0x003f000f;
12919 } else {
12920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12922 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12923 u32 read_water = 0x7;
1da177e4 12924
4a29cc2e
MC		 12925 /* If the 5704 is behind the EPB bridge, we can
12926 * do the less restrictive ONE_DMA workaround for
12927 * better performance.
12928 */
12929 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12931 tp->dma_rwctrl |= 0x8000;
12932 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12933 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12934
49afdeb6
MC		 12935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12936 read_water = 4;
59e6b434 12937 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12938 tp->dma_rwctrl |=
12939 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12940 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12941 (1 << 23);
4cf78e4f
MC		 12942 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12943 /* 5780 always in PCIX mode */
12944 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12945 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12946 /* 5714 always in PCIX mode */
12947 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12948 } else {
12949 tp->dma_rwctrl |= 0x001b000f;
12950 }
12951 }
12952
12953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12955 tp->dma_rwctrl &= 0xfffffff0;
12956
12957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12959 /* Remove this if it causes problems for some boards. */
12960 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12961
12962 /* On 5700/5701 chips, we need to set this bit.
12963 * Otherwise the chip will issue cacheline transactions
12964 * to streamable DMA memory with not all the byte
12965 * enables turned on. This is an error on several
12966 * RISC PCI controllers, in particular sparc64.
12967 *
12968 * On 5703/5704 chips, this bit has been reassigned
12969 * a different meaning. In particular, it is used
12970 * on those chips to enable a PCI-X workaround.
12971 */
12972 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12973 }
12974
12975 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12976
12977#if 0
12978 /* Unneeded, already done by tg3_get_invariants. */
12979 tg3_switch_clocks(tp);
12980#endif
12981
12982 ret = 0;
12983 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12984 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12985 goto out;
12986
59e6b434
DM		 12987 /* It is best to perform DMA test with maximum write burst size
12988 * to expose the 5700/5701 write DMA bug.
12989 */
12990 saved_dma_rwctrl = tp->dma_rwctrl;
12991 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12992 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12993
1da177e4
LT		 12994 while (1) {
12995 u32 *p = buf, i;
12996
12997 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12998 p[i] = i;
12999
13000 /* Send the buffer to the chip. */
13001 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13002 if (ret) {
13003 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13004 break;
13005 }
13006
13007#if 0
13008 /* validate data reached card RAM correctly. */
13009 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13010 u32 val;
13011 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13012 if (le32_to_cpu(val) != p[i]) {
13013 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13014 /* ret = -ENODEV here? */
13015 }
13016 p[i] = 0;
13017 }
13018#endif
13019 /* Now read it back. */
13020 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13021 if (ret) {
13022 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13023
13024 break;
13025 }
13026
13027 /* Verify it. */
13028 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13029 if (p[i] == i)
13030 continue;
13031
59e6b434
DM		 13032 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13033 DMA_RWCTRL_WRITE_BNDRY_16) {
13034 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13035 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13036 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13037 break;
13038 } else {
13039 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13040 ret = -ENODEV;
13041 goto out;
13042 }
13043 }
13044
13045 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13046 /* Success. */
13047 ret = 0;
13048 break;
13049 }
13050 }
59e6b434
DM		 13051 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13052 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13053 static struct pci_device_id dma_wait_state_chipsets[] = {
13054 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13055 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13056 { },
13057 };
13058
59e6b434 13059 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13060 * now look for chipsets that are known to expose the
13061 * DMA bug without failing the test.
59e6b434 13062 */
6d1cfbab
MC		 13063 if (pci_dev_present(dma_wait_state_chipsets)) {
13064 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13065 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13066 }
13067 else
13068 /* Safe to use the calculated DMA boundary. */
13069 tp->dma_rwctrl = saved_dma_rwctrl;
13070
59e6b434
DM		 13071 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13072 }
1da177e4
LT		 13073
13074out:
13075 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13076out_nofree:
13077 return ret;
13078}
13079
13080static void __devinit tg3_init_link_config(struct tg3 *tp)
13081{
13082 tp->link_config.advertising =
13083 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13084 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13085 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13086 ADVERTISED_Autoneg | ADVERTISED_MII);
13087 tp->link_config.speed = SPEED_INVALID;
13088 tp->link_config.duplex = DUPLEX_INVALID;
13089 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13090 tp->link_config.active_speed = SPEED_INVALID;
13091 tp->link_config.active_duplex = DUPLEX_INVALID;
13092 tp->link_config.phy_is_low_power = 0;
13093 tp->link_config.orig_speed = SPEED_INVALID;
13094 tp->link_config.orig_duplex = DUPLEX_INVALID;
13095 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13096}
13097
13098static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13099{
fdfec172
MC		 13100 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13101 tp->bufmgr_config.mbuf_read_dma_low_water =
13102 DEFAULT_MB_RDMA_LOW_WATER_5705;
13103 tp->bufmgr_config.mbuf_mac_rx_low_water =
13104 DEFAULT_MB_MACRX_LOW_WATER_5705;
13105 tp->bufmgr_config.mbuf_high_water =
13106 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13108 tp->bufmgr_config.mbuf_mac_rx_low_water =
13109 DEFAULT_MB_MACRX_LOW_WATER_5906;
13110 tp->bufmgr_config.mbuf_high_water =
13111 DEFAULT_MB_HIGH_WATER_5906;
13112 }
fdfec172
MC		 13113
13114 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13115 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13116 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13117 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13118 tp->bufmgr_config.mbuf_high_water_jumbo =
13119 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13120 } else {
13121 tp->bufmgr_config.mbuf_read_dma_low_water =
13122 DEFAULT_MB_RDMA_LOW_WATER;
13123 tp->bufmgr_config.mbuf_mac_rx_low_water =
13124 DEFAULT_MB_MACRX_LOW_WATER;
13125 tp->bufmgr_config.mbuf_high_water =
13126 DEFAULT_MB_HIGH_WATER;
13127
13128 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13129 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13130 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13131 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13132 tp->bufmgr_config.mbuf_high_water_jumbo =
13133 DEFAULT_MB_HIGH_WATER_JUMBO;
13134 }
1da177e4
LT		 13135
13136 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13137 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13138}
13139
13140static char * __devinit tg3_phy_string(struct tg3 *tp)
13141{
13142 switch (tp->phy_id & PHY_ID_MASK) {
13143 case PHY_ID_BCM5400: return "5400";
13144 case PHY_ID_BCM5401: return "5401";
13145 case PHY_ID_BCM5411: return "5411";
13146 case PHY_ID_BCM5701: return "5701";
13147 case PHY_ID_BCM5703: return "5703";
13148 case PHY_ID_BCM5704: return "5704";
13149 case PHY_ID_BCM5705: return "5705";
13150 case PHY_ID_BCM5750: return "5750";
85e94ced 13151 case PHY_ID_BCM5752: return "5752";
a4e2b347 13152 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13153 case PHY_ID_BCM5780: return "5780";
af36e6b6 13154 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13155 case PHY_ID_BCM5787: return "5787";
d30cdd28 13156 case PHY_ID_BCM5784: return "5784";
126a3368 13157 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13158 case PHY_ID_BCM5906: return "5906";
9936bcf6 13159 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13160 case PHY_ID_BCM8002: return "8002/serdes";
13161 case 0: return "serdes";
13162 default: return "unknown";
855e1111 13163 }
1da177e4
LT		 13164}
13165
f9804ddb
MC		 13166static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13167{
13168 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13169 strcpy(str, "PCI Express");
13170 return str;
13171 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13172 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13173
13174 strcpy(str, "PCIX:");
13175
13176 if ((clock_ctrl == 7) ||
13177 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13178 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13179 strcat(str, "133MHz");
13180 else if (clock_ctrl == 0)
13181 strcat(str, "33MHz");
13182 else if (clock_ctrl == 2)
13183 strcat(str, "50MHz");
13184 else if (clock_ctrl == 4)
13185 strcat(str, "66MHz");
13186 else if (clock_ctrl == 6)
13187 strcat(str, "100MHz");
f9804ddb
MC		 13188 } else {
13189 strcpy(str, "PCI:");
13190 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13191 strcat(str, "66MHz");
13192 else
13193 strcat(str, "33MHz");
13194 }
13195 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13196 strcat(str, ":32-bit");
13197 else
13198 strcat(str, ":64-bit");
13199 return str;
13200}
13201
8c2dc7e1 13202static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13203{
13204 struct pci_dev *peer;
13205 unsigned int func, devnr = tp->pdev->devfn & ~7;
13206
13207 for (func = 0; func < 8; func++) {
13208 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13209 if (peer && peer != tp->pdev)
13210 break;
13211 pci_dev_put(peer);
13212 }
16fe9d74
MC		 13213 /* 5704 can be configured in single-port mode, set peer to
13214 * tp->pdev in that case.
13215 */
13216 if (!peer) {
13217 peer = tp->pdev;
13218 return peer;
13219 }
1da177e4
LT		 13220
13221 /*
13222 * We don't need to keep the refcount elevated; there's no way
13223 * to remove one half of this device without removing the other
13224 */
13225 pci_dev_put(peer);
13226
13227 return peer;
13228}
13229
15f9850d
DM		 13230static void __devinit tg3_init_coal(struct tg3 *tp)
13231{
13232 struct ethtool_coalesce *ec = &tp->coal;
13233
13234 memset(ec, 0, sizeof(*ec));
13235 ec->cmd = ETHTOOL_GCOALESCE;
13236 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13237 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13238 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13239 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13240 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13241 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13242 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13243 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13244 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13245
13246 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13247 HOSTCC_MODE_CLRTICK_TXBD)) {
13248 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13249 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13250 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13251 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13252 }
d244c892
MC		 13253
13254 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13255 ec->rx_coalesce_usecs_irq = 0;
13256 ec->tx_coalesce_usecs_irq = 0;
13257 ec->stats_block_coalesce_usecs = 0;
13258 }
15f9850d
DM		 13259}
13260
7c7d64b8
SH		 13261static const struct net_device_ops tg3_netdev_ops = {
13262 .ndo_open = tg3_open,
13263 .ndo_stop = tg3_close,
00829823
SH		 13264 .ndo_start_xmit = tg3_start_xmit,
13265 .ndo_get_stats = tg3_get_stats,
13266 .ndo_validate_addr = eth_validate_addr,
13267 .ndo_set_multicast_list = tg3_set_rx_mode,
13268 .ndo_set_mac_address = tg3_set_mac_addr,
13269 .ndo_do_ioctl = tg3_ioctl,
13270 .ndo_tx_timeout = tg3_tx_timeout,
13271 .ndo_change_mtu = tg3_change_mtu,
13272#if TG3_VLAN_TAG_USED
13273 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13274#endif
13275#ifdef CONFIG_NET_POLL_CONTROLLER
13276 .ndo_poll_controller = tg3_poll_controller,
13277#endif
13278};
13279
13280static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13281 .ndo_open = tg3_open,
13282 .ndo_stop = tg3_close,
13283 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13284 .ndo_get_stats = tg3_get_stats,
13285 .ndo_validate_addr = eth_validate_addr,
13286 .ndo_set_multicast_list = tg3_set_rx_mode,
13287 .ndo_set_mac_address = tg3_set_mac_addr,
13288 .ndo_do_ioctl = tg3_ioctl,
13289 .ndo_tx_timeout = tg3_tx_timeout,
13290 .ndo_change_mtu = tg3_change_mtu,
13291#if TG3_VLAN_TAG_USED
13292 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13293#endif
13294#ifdef CONFIG_NET_POLL_CONTROLLER
13295 .ndo_poll_controller = tg3_poll_controller,
13296#endif
13297};
13298
1da177e4
LT		 13299static int __devinit tg3_init_one(struct pci_dev *pdev,
13300 const struct pci_device_id *ent)
13301{
13302 static int tg3_version_printed = 0;
1da177e4
LT		 13303 struct net_device *dev;
13304 struct tg3 *tp;
d6645372 13305 int err, pm_cap;
f9804ddb 13306 char str[40];
72f2afb8 13307 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13308
13309 if (tg3_version_printed++ == 0)
13310 printk(KERN_INFO "%s", version);
13311
13312 err = pci_enable_device(pdev);
13313 if (err) {
13314 printk(KERN_ERR PFX "Cannot enable PCI device, "
13315 "aborting.\n");
13316 return err;
13317 }
13318
1da177e4
LT		 13319 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13320 if (err) {
13321 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13322 "aborting.\n");
13323 goto err_out_disable_pdev;
13324 }
13325
13326 pci_set_master(pdev);
13327
13328 /* Find power-management capability. */
13329 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13330 if (pm_cap == 0) {
13331 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13332 "aborting.\n");
13333 err = -EIO;
13334 goto err_out_free_res;
13335 }
13336
1da177e4
LT		 13337 dev = alloc_etherdev(sizeof(*tp));
13338 if (!dev) {
13339 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13340 err = -ENOMEM;
13341 goto err_out_free_res;
13342 }
13343
1da177e4
LT		 13344 SET_NETDEV_DEV(dev, &pdev->dev);
13345
1da177e4
LT		 13346#if TG3_VLAN_TAG_USED
13347 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13348#endif
13349
13350 tp = netdev_priv(dev);
13351 tp->pdev = pdev;
13352 tp->dev = dev;
13353 tp->pm_cap = pm_cap;
1da177e4
LT		 13354 tp->rx_mode = TG3_DEF_RX_MODE;
13355 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13356
1da177e4
LT		 13357 if (tg3_debug > 0)
13358 tp->msg_enable = tg3_debug;
13359 else
13360 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13361
13362 /* The word/byte swap controls here control register access byte
13363 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13364 * setting below.
13365 */
13366 tp->misc_host_ctrl =
13367 MISC_HOST_CTRL_MASK_PCI_INT |
13368 MISC_HOST_CTRL_WORD_SWAP |
13369 MISC_HOST_CTRL_INDIR_ACCESS |
13370 MISC_HOST_CTRL_PCISTATE_RW;
13371
13372 /* The NONFRM (non-frame) byte/word swap controls take effect
13373 * on descriptor entries, anything which isn't packet data.
13374 *
13375 * The StrongARM chips on the board (one for tx, one for rx)
13376 * are running in big-endian mode.
13377 */
13378 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13379 GRC_MODE_WSWAP_NONFRM_DATA);
13380#ifdef __BIG_ENDIAN
13381 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13382#endif
13383 spin_lock_init(&tp->lock);
1da177e4 13384 spin_lock_init(&tp->indirect_lock);
c4028958 13385 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13386
d5fe488a 13387 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13388 if (!tp->regs) {
1da177e4
LT		 13389 printk(KERN_ERR PFX "Cannot map device registers, "
13390 "aborting.\n");
13391 err = -ENOMEM;
13392 goto err_out_free_dev;
13393 }
13394
13395 tg3_init_link_config(tp);
13396
1da177e4
LT		 13397 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13398 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13399 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13400
bea3348e 13401 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13402 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13403 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13404 dev->irq = pdev->irq;
1da177e4
LT		 13405
13406 err = tg3_get_invariants(tp);
13407 if (err) {
13408 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13409 "aborting.\n");
13410 goto err_out_iounmap;
13411 }
13412
321d32a0 13413 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13414 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13415 dev->netdev_ops = &tg3_netdev_ops;
13416 else
13417 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13418
13419
4a29cc2e
MC		 13420 /* The EPB bridge inside 5714, 5715, and 5780 and any
13421 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13422 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13423 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13424 * do DMA address check in tg3_start_xmit().
13425 */
4a29cc2e 13426 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13427 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13428 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13429 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13430#ifdef CONFIG_HIGHMEM
6a35528a 13431 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13432#endif
4a29cc2e 13433 } else
6a35528a 13434 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13435
13436 /* Configure DMA attributes. */
284901a9 13437 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13438 err = pci_set_dma_mask(pdev, dma_mask);
13439 if (!err) {
13440 dev->features |= NETIF_F_HIGHDMA;
13441 err = pci_set_consistent_dma_mask(pdev,
13442 persist_dma_mask);
13443 if (err < 0) {
13444 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13445 "DMA for consistent allocations\n");
13446 goto err_out_iounmap;
13447 }
13448 }
13449 }
284901a9
YH		 13450 if (err || dma_mask == DMA_BIT_MASK(32)) {
13451 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13452 if (err) {
13453 printk(KERN_ERR PFX "No usable DMA configuration, "
13454 "aborting.\n");
13455 goto err_out_iounmap;
13456 }
13457 }
13458
fdfec172 13459 tg3_init_bufmgr_config(tp);
1da177e4 13460
077f849d 13461 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13462 tp->fw_needed = FIRMWARE_TG3;
077f849d 13463
1da177e4
LT		 13464 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13465 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13466 }
13467 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13468 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13469 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13470 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13471 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13472 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13473 } else {
7f62ad5d 13474 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13476 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13477 else
9e9fd12d 13478 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13479 }
1da177e4 13480
4e3a7aaa
MC		 13481 /* TSO is on by default on chips that support hardware TSO.
13482 * Firmware TSO on older chips gives lower performance, so it
13483 * is off by default, but can be enabled using ethtool.
13484 */
b0026624 13485 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13486 if (dev->features & NETIF_F_IP_CSUM)
13487 dev->features |= NETIF_F_TSO;
13488 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13489 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13490 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13492 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13493 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13495 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13496 dev->features |= NETIF_F_TSO_ECN;
b0026624 13497 }
1da177e4 13498
1da177e4
LT		 13499
13500 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13501 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13502 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13503 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13504 tp->rx_pending = 63;
13505 }
13506
1da177e4
LT		 13507 err = tg3_get_device_address(tp);
13508 if (err) {
13509 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13510 "aborting.\n");
077f849d 13511 goto err_out_fw;
1da177e4
LT		 13512 }
13513
c88864df 13514 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13515 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13516 if (!tp->aperegs) {
c88864df
MC		 13517 printk(KERN_ERR PFX "Cannot map APE registers, "
13518 "aborting.\n");
13519 err = -ENOMEM;
077f849d 13520 goto err_out_fw;
c88864df
MC		 13521 }
13522
13523 tg3_ape_lock_init(tp);
7fd76445
MC		 13524
13525 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13526 tg3_read_dash_ver(tp);
c88864df
MC		 13527 }
13528
1da177e4
LT		 13529 /*
13530 * Reset chip in case UNDI or EFI driver did not shutdown
13531 * DMA self test will enable WDMAC and we'll see (spurious)
13532 * pending DMA on the PCI bus at that point.
13533 */
13534 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13535 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13536 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13537 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13538 }
13539
13540 err = tg3_test_dma(tp);
13541 if (err) {
13542 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13543 goto err_out_apeunmap;
1da177e4
LT		 13544 }
13545
1da177e4
LT		 13546 /* flow control autonegotiation is default behavior */
13547 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13548 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13549
15f9850d
DM		 13550 tg3_init_coal(tp);
13551
c49a1561
MC		 13552 pci_set_drvdata(pdev, dev);
13553
1da177e4
LT		 13554 err = register_netdev(dev);
13555 if (err) {
13556 printk(KERN_ERR PFX "Cannot register net device, "
13557 "aborting.\n");
0d3031d9 13558 goto err_out_apeunmap;
1da177e4
LT		 13559 }
13560
df59c940 13561 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13562 dev->name,
13563 tp->board_part_number,
13564 tp->pci_chip_rev_id,
f9804ddb 13565 tg3_bus_string(tp, str),
e174961c 13566 dev->dev_addr);
1da177e4 13567
df59c940
MC		 13568 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13569 printk(KERN_INFO
13570 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13571 tp->dev->name,
13572 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13573 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13574 else
13575 printk(KERN_INFO
13576 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13577 tp->dev->name, tg3_phy_string(tp),
13578 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13579 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13580 "10/100/1000Base-T")),
13581 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13582
13583 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13584 dev->name,
13585 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13586 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13587 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13588 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13589 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13590 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13591 dev->name, tp->dma_rwctrl,
284901a9 13592 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13593 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13594
13595 return 0;
13596
0d3031d9
MC		 13597err_out_apeunmap:
13598 if (tp->aperegs) {
13599 iounmap(tp->aperegs);
13600 tp->aperegs = NULL;
13601 }
13602
077f849d
JSR		 13603err_out_fw:
13604 if (tp->fw)
13605 release_firmware(tp->fw);
13606
1da177e4 13607err_out_iounmap:
6892914f
MC		 13608 if (tp->regs) {
13609 iounmap(tp->regs);
22abe310 13610 tp->regs = NULL;
6892914f 13611 }
1da177e4
LT		 13612
13613err_out_free_dev:
13614 free_netdev(dev);
13615
13616err_out_free_res:
13617 pci_release_regions(pdev);
13618
13619err_out_disable_pdev:
13620 pci_disable_device(pdev);
13621 pci_set_drvdata(pdev, NULL);
13622 return err;
13623}
13624
13625static void __devexit tg3_remove_one(struct pci_dev *pdev)
13626{
13627 struct net_device *dev = pci_get_drvdata(pdev);
13628
13629 if (dev) {
13630 struct tg3 *tp = netdev_priv(dev);
13631
077f849d
JSR		 13632 if (tp->fw)
13633 release_firmware(tp->fw);
13634
7faa006f 13635 flush_scheduled_work();
158d7abd 13636
b02fd9e3
MC		 13637 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13638 tg3_phy_fini(tp);
158d7abd 13639 tg3_mdio_fini(tp);
b02fd9e3 13640 }
158d7abd 13641
1da177e4 13642 unregister_netdev(dev);
0d3031d9
MC		 13643 if (tp->aperegs) {
13644 iounmap(tp->aperegs);
13645 tp->aperegs = NULL;
13646 }
6892914f
MC		 13647 if (tp->regs) {
13648 iounmap(tp->regs);
22abe310 13649 tp->regs = NULL;
6892914f 13650 }
1da177e4
LT		 13651 free_netdev(dev);
13652 pci_release_regions(pdev);
13653 pci_disable_device(pdev);
13654 pci_set_drvdata(pdev, NULL);
13655 }
13656}
13657
13658static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13659{
13660 struct net_device *dev = pci_get_drvdata(pdev);
13661 struct tg3 *tp = netdev_priv(dev);
12dac075 13662 pci_power_t target_state;
1da177e4
LT		 13663 int err;
13664
3e0c95fd
MC		 13665 /* PCI register 4 needs to be saved whether netif_running() or not.
13666 * MSI address and data need to be saved if using MSI and
13667 * netif_running().
13668 */
13669 pci_save_state(pdev);
13670
1da177e4
LT		 13671 if (!netif_running(dev))
13672 return 0;
13673
7faa006f 13674 flush_scheduled_work();
b02fd9e3 13675 tg3_phy_stop(tp);
1da177e4
LT		 13676 tg3_netif_stop(tp);
13677
13678 del_timer_sync(&tp->timer);
13679
f47c11ee 13680 tg3_full_lock(tp, 1);
1da177e4 13681 tg3_disable_ints(tp);
f47c11ee 13682 tg3_full_unlock(tp);
1da177e4
LT		 13683
13684 netif_device_detach(dev);
13685
f47c11ee 13686 tg3_full_lock(tp, 0);
944d980e 13687 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13688 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13689 tg3_full_unlock(tp);
1da177e4 13690
12dac075
RW		 13691 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13692
13693 err = tg3_set_power_state(tp, target_state);
1da177e4 13694 if (err) {
b02fd9e3
MC		 13695 int err2;
13696
f47c11ee 13697 tg3_full_lock(tp, 0);
1da177e4 13698
6a9eba15 13699 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13700 err2 = tg3_restart_hw(tp, 1);
13701 if (err2)
b9ec6c1b 13702 goto out;
1da177e4
LT		 13703
13704 tp->timer.expires = jiffies + tp->timer_offset;
13705 add_timer(&tp->timer);
13706
13707 netif_device_attach(dev);
13708 tg3_netif_start(tp);
13709
b9ec6c1b 13710out:
f47c11ee 13711 tg3_full_unlock(tp);
b02fd9e3
MC		 13712
13713 if (!err2)
13714 tg3_phy_start(tp);
1da177e4
LT		 13715 }
13716
13717 return err;
13718}
13719
13720static int tg3_resume(struct pci_dev *pdev)
13721{
13722 struct net_device *dev = pci_get_drvdata(pdev);
13723 struct tg3 *tp = netdev_priv(dev);
13724 int err;
13725
3e0c95fd
MC		 13726 pci_restore_state(tp->pdev);
13727
1da177e4
LT		 13728 if (!netif_running(dev))
13729 return 0;
13730
bc1c7567 13731 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13732 if (err)
13733 return err;
13734
13735 netif_device_attach(dev);
13736
f47c11ee 13737 tg3_full_lock(tp, 0);
1da177e4 13738
6a9eba15 13739 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13740 err = tg3_restart_hw(tp, 1);
13741 if (err)
13742 goto out;
1da177e4
LT		 13743
13744 tp->timer.expires = jiffies + tp->timer_offset;
13745 add_timer(&tp->timer);
13746
1da177e4
LT		 13747 tg3_netif_start(tp);
13748
b9ec6c1b 13749out:
f47c11ee 13750 tg3_full_unlock(tp);
1da177e4 13751
b02fd9e3
MC		 13752 if (!err)
13753 tg3_phy_start(tp);
13754
b9ec6c1b 13755 return err;
1da177e4
LT		 13756}
13757
13758static struct pci_driver tg3_driver = {
13759 .name = DRV_MODULE_NAME,
13760 .id_table = tg3_pci_tbl,
13761 .probe = tg3_init_one,
13762 .remove = __devexit_p(tg3_remove_one),
13763 .suspend = tg3_suspend,
13764 .resume = tg3_resume
13765};
13766
13767static int __init tg3_init(void)
13768{
29917620 13769 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13770}
13771
13772static void __exit tg3_cleanup(void)
13773{
13774 pci_unregister_driver(&tg3_driver);
13775}
13776
13777module_init(tg3_init);
13778module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree