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tg3: Reformat NVRAM case statements
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
f656f398
MC		 71#define DRV_MODULE_VERSION "3.100"
72#define DRV_MODULE_RELDATE "August 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
233 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
234 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
235 {}
1da177e4
LT		 236};
237
238MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
239
50da859d 240static const struct {
1da177e4
LT		 241 const char string[ETH_GSTRING_LEN];
242} ethtool_stats_keys[TG3_NUM_STATS] = {
243 { "rx_octets" },
244 { "rx_fragments" },
245 { "rx_ucast_packets" },
246 { "rx_mcast_packets" },
247 { "rx_bcast_packets" },
248 { "rx_fcs_errors" },
249 { "rx_align_errors" },
250 { "rx_xon_pause_rcvd" },
251 { "rx_xoff_pause_rcvd" },
252 { "rx_mac_ctrl_rcvd" },
253 { "rx_xoff_entered" },
254 { "rx_frame_too_long_errors" },
255 { "rx_jabbers" },
256 { "rx_undersize_packets" },
257 { "rx_in_length_errors" },
258 { "rx_out_length_errors" },
259 { "rx_64_or_less_octet_packets" },
260 { "rx_65_to_127_octet_packets" },
261 { "rx_128_to_255_octet_packets" },
262 { "rx_256_to_511_octet_packets" },
263 { "rx_512_to_1023_octet_packets" },
264 { "rx_1024_to_1522_octet_packets" },
265 { "rx_1523_to_2047_octet_packets" },
266 { "rx_2048_to_4095_octet_packets" },
267 { "rx_4096_to_8191_octet_packets" },
268 { "rx_8192_to_9022_octet_packets" },
269
270 { "tx_octets" },
271 { "tx_collisions" },
272
273 { "tx_xon_sent" },
274 { "tx_xoff_sent" },
275 { "tx_flow_control" },
276 { "tx_mac_errors" },
277 { "tx_single_collisions" },
278 { "tx_mult_collisions" },
279 { "tx_deferred" },
280 { "tx_excessive_collisions" },
281 { "tx_late_collisions" },
282 { "tx_collide_2times" },
283 { "tx_collide_3times" },
284 { "tx_collide_4times" },
285 { "tx_collide_5times" },
286 { "tx_collide_6times" },
287 { "tx_collide_7times" },
288 { "tx_collide_8times" },
289 { "tx_collide_9times" },
290 { "tx_collide_10times" },
291 { "tx_collide_11times" },
292 { "tx_collide_12times" },
293 { "tx_collide_13times" },
294 { "tx_collide_14times" },
295 { "tx_collide_15times" },
296 { "tx_ucast_packets" },
297 { "tx_mcast_packets" },
298 { "tx_bcast_packets" },
299 { "tx_carrier_sense_errors" },
300 { "tx_discards" },
301 { "tx_errors" },
302
303 { "dma_writeq_full" },
304 { "dma_write_prioq_full" },
305 { "rxbds_empty" },
306 { "rx_discards" },
307 { "rx_errors" },
308 { "rx_threshold_hit" },
309
310 { "dma_readq_full" },
311 { "dma_read_prioq_full" },
312 { "tx_comp_queue_full" },
313
314 { "ring_set_send_prod_index" },
315 { "ring_status_update" },
316 { "nic_irqs" },
317 { "nic_avoided_irqs" },
318 { "nic_tx_threshold_hit" }
319};
320
50da859d 321static const struct {
4cafd3f5
MC		 322 const char string[ETH_GSTRING_LEN];
323} ethtool_test_keys[TG3_NUM_TEST] = {
324 { "nvram test (online) " },
325 { "link test (online) " },
326 { "register test (offline)" },
327 { "memory test (offline)" },
328 { "loopback test (offline)" },
329 { "interrupt test (offline)" },
330};
331
b401e9e2
MC		 332static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
333{
334 writel(val, tp->regs + off);
335}
336
337static u32 tg3_read32(struct tg3 *tp, u32 off)
338{
6aa20a22 339 return (readl(tp->regs + off));
b401e9e2
MC		 340}
341
0d3031d9
MC		 342static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->aperegs + off);
345}
346
347static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
348{
349 return (readl(tp->aperegs + off));
350}
351
1da177e4
LT		 352static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
353{
6892914f
MC		 354 unsigned long flags;
355
356 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 357 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
358 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 359 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 360}
361
362static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
363{
364 writel(val, tp->regs + off);
365 readl(tp->regs + off);
1da177e4
LT		 366}
367
6892914f 368static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 369{
6892914f
MC		 370 unsigned long flags;
371 u32 val;
372
373 spin_lock_irqsave(&tp->indirect_lock, flags);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
375 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
376 spin_unlock_irqrestore(&tp->indirect_lock, flags);
377 return val;
378}
379
380static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
381{
382 unsigned long flags;
383
384 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
385 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
386 TG3_64BIT_REG_LOW, val);
387 return;
388 }
389 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
390 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
391 TG3_64BIT_REG_LOW, val);
392 return;
1da177e4 393 }
6892914f
MC		 394
395 spin_lock_irqsave(&tp->indirect_lock, flags);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
397 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
398 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399
400 /* In indirect mode when disabling interrupts, we also need
401 * to clear the interrupt bit in the GRC local ctrl register.
402 */
403 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
404 (val == 0x1)) {
405 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
406 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
407 }
408}
409
410static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
411{
412 unsigned long flags;
413 u32 val;
414
415 spin_lock_irqsave(&tp->indirect_lock, flags);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
417 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
418 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 return val;
420}
421
b401e9e2
MC		 422/* usec_wait specifies the wait time in usec when writing to certain registers
423 * where it is unsafe to read back the register without some delay.
424 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
425 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
426 */
427static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 428{
b401e9e2
MC		 429 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
430 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
431 /* Non-posted methods */
432 tp->write32(tp, off, val);
433 else {
434 /* Posted method */
435 tg3_write32(tp, off, val);
436 if (usec_wait)
437 udelay(usec_wait);
438 tp->read32(tp, off);
439 }
440 /* Wait again after the read for the posted method to guarantee that
441 * the wait time is met.
442 */
443 if (usec_wait)
444 udelay(usec_wait);
1da177e4
LT		 445}
446
09ee929c
MC		 447static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
448{
449 tp->write32_mbox(tp, off, val);
6892914f
MC		 450 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
451 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
452 tp->read32_mbox(tp, off);
09ee929c
MC		 453}
454
20094930 455static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 456{
457 void __iomem *mbox = tp->regs + off;
458 writel(val, mbox);
459 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
460 writel(val, mbox);
461 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
462 readl(mbox);
463}
464
b5d3772c
MC		 465static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
466{
467 return (readl(tp->regs + off + GRCMBOX_BASE));
468}
469
470static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
471{
472 writel(val, tp->regs + off + GRCMBOX_BASE);
473}
474
20094930 475#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 476#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 477#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
478#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 479#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 480
481#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 482#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
483#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 484#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 485
486static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
487{
6892914f
MC		 488 unsigned long flags;
489
b5d3772c
MC		 490 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
491 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
492 return;
493
6892914f 494 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 495 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 498
bbadf503
MC		 499 /* Always leave this as zero. */
500 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
501 } else {
502 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
503 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 504
bbadf503
MC		 505 /* Always leave this as zero. */
506 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
507 }
508 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 509}
510
1da177e4
LT		 511static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
512{
6892914f
MC		 513 unsigned long flags;
514
b5d3772c
MC		 515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
516 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
517 *val = 0;
518 return;
519 }
520
6892914f 521 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 522 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
523 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
524 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 525
bbadf503
MC		 526 /* Always leave this as zero. */
527 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
528 } else {
529 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
530 *val = tr32(TG3PCI_MEM_WIN_DATA);
531
532 /* Always leave this as zero. */
533 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
534 }
6892914f 535 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 536}
537
0d3031d9
MC		 538static void tg3_ape_lock_init(struct tg3 *tp)
539{
540 int i;
541
542 /* Make sure the driver hasn't any stale locks. */
543 for (i = 0; i < 8; i++)
544 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
545 APE_LOCK_GRANT_DRIVER);
546}
547
548static int tg3_ape_lock(struct tg3 *tp, int locknum)
549{
550 int i, off;
551 int ret = 0;
552 u32 status;
553
554 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
555 return 0;
556
557 switch (locknum) {
77b483f1 558 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 559 case TG3_APE_LOCK_MEM:
560 break;
561 default:
562 return -EINVAL;
563 }
564
565 off = 4 * locknum;
566
567 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
568
569 /* Wait for up to 1 millisecond to acquire lock. */
570 for (i = 0; i < 100; i++) {
571 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
572 if (status == APE_LOCK_GRANT_DRIVER)
573 break;
574 udelay(10);
575 }
576
577 if (status != APE_LOCK_GRANT_DRIVER) {
578 /* Revoke the lock request. */
579 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
580 APE_LOCK_GRANT_DRIVER);
581
582 ret = -EBUSY;
583 }
584
585 return ret;
586}
587
588static void tg3_ape_unlock(struct tg3 *tp, int locknum)
589{
590 int off;
591
592 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
593 return;
594
595 switch (locknum) {
77b483f1 596 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 597 case TG3_APE_LOCK_MEM:
598 break;
599 default:
600 return;
601 }
602
603 off = 4 * locknum;
604 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
605}
606
1da177e4
LT		 607static void tg3_disable_ints(struct tg3 *tp)
608{
609 tw32(TG3PCI_MISC_HOST_CTRL,
610 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 611 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 612}
613
614static inline void tg3_cond_int(struct tg3 *tp)
615{
38f3843e
MC		 616 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
617 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 618 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 619 else
620 tw32(HOSTCC_MODE, tp->coalesce_mode |
621 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 622}
623
624static void tg3_enable_ints(struct tg3 *tp)
625{
bbe832c0
MC		 626 tp->irq_sync = 0;
627 wmb();
628
1da177e4
LT		 629 tw32(TG3PCI_MISC_HOST_CTRL,
630 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 631 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
632 (tp->last_tag << 24));
fcfa0a32
MC		 633 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
634 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
635 (tp->last_tag << 24));
1da177e4
LT		 636 tg3_cond_int(tp);
637}
638
04237ddd
MC		 639static inline unsigned int tg3_has_work(struct tg3 *tp)
640{
641 struct tg3_hw_status *sblk = tp->hw_status;
642 unsigned int work_exists = 0;
643
644 /* check for phy events */
645 if (!(tp->tg3_flags &
646 (TG3_FLAG_USE_LINKCHG_REG |
647 TG3_FLAG_POLL_SERDES))) {
648 if (sblk->status & SD_STATUS_LINK_CHG)
649 work_exists = 1;
650 }
651 /* check for RX/TX work to do */
652 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
653 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
654 work_exists = 1;
655
656 return work_exists;
657}
658
1da177e4 659/* tg3_restart_ints
04237ddd
MC		 660 * similar to tg3_enable_ints, but it accurately determines whether there
661 * is new work pending and can return without flushing the PIO write
6aa20a22 662 * which reenables interrupts
1da177e4
LT		 663 */
664static void tg3_restart_ints(struct tg3 *tp)
665{
fac9b83e
DM		 666 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
667 tp->last_tag << 24);
1da177e4
LT		 668 mmiowb();
669
fac9b83e
DM		 670 /* When doing tagged status, this work check is unnecessary.
671 * The last_tag we write above tells the chip which piece of
672 * work we've completed.
673 */
674 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
675 tg3_has_work(tp))
04237ddd
MC		 676 tw32(HOSTCC_MODE, tp->coalesce_mode |
677 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 678}
679
680static inline void tg3_netif_stop(struct tg3 *tp)
681{
bbe832c0 682 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 683 napi_disable(&tp->napi);
1da177e4
LT		 684 netif_tx_disable(tp->dev);
685}
686
687static inline void tg3_netif_start(struct tg3 *tp)
688{
689 netif_wake_queue(tp->dev);
690 /* NOTE: unconditional netif_wake_queue is only appropriate
691 * so long as all callers are assured to have free tx slots
692 * (such as after tg3_init_hw)
693 */
bea3348e 694 napi_enable(&tp->napi);
f47c11ee
DM		 695 tp->hw_status->status |= SD_STATUS_UPDATED;
696 tg3_enable_ints(tp);
1da177e4
LT		 697}
698
699static void tg3_switch_clocks(struct tg3 *tp)
700{
701 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
702 u32 orig_clock_ctrl;
703
795d01c5
MC		 704 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
705 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 706 return;
707
1da177e4
LT		 708 orig_clock_ctrl = clock_ctrl;
709 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
710 CLOCK_CTRL_CLKRUN_OENABLE |
711 0x1f);
712 tp->pci_clock_ctrl = clock_ctrl;
713
714 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
715 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 716 tw32_wait_f(TG3PCI_CLOCK_CTRL,
717 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 718 }
719 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 720 tw32_wait_f(TG3PCI_CLOCK_CTRL,
721 clock_ctrl |
722 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
723 40);
724 tw32_wait_f(TG3PCI_CLOCK_CTRL,
725 clock_ctrl | (CLOCK_CTRL_ALTCLK),
726 40);
1da177e4 727 }
b401e9e2 728 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 729}
730
731#define PHY_BUSY_LOOPS 5000
732
733static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
734{
735 u32 frame_val;
736 unsigned int loops;
737 int ret;
738
739 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
740 tw32_f(MAC_MI_MODE,
741 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
742 udelay(80);
743 }
744
745 *val = 0x0;
746
747 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
748 MI_COM_PHY_ADDR_MASK);
749 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
750 MI_COM_REG_ADDR_MASK);
751 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 752
1da177e4
LT		 753 tw32_f(MAC_MI_COM, frame_val);
754
755 loops = PHY_BUSY_LOOPS;
756 while (loops != 0) {
757 udelay(10);
758 frame_val = tr32(MAC_MI_COM);
759
760 if ((frame_val & MI_COM_BUSY) == 0) {
761 udelay(5);
762 frame_val = tr32(MAC_MI_COM);
763 break;
764 }
765 loops -= 1;
766 }
767
768 ret = -EBUSY;
769 if (loops != 0) {
770 *val = frame_val & MI_COM_DATA_MASK;
771 ret = 0;
772 }
773
774 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
775 tw32_f(MAC_MI_MODE, tp->mi_mode);
776 udelay(80);
777 }
778
779 return ret;
780}
781
782static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
783{
784 u32 frame_val;
785 unsigned int loops;
786 int ret;
787
7f97a4bd 788 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 789 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
790 return 0;
791
1da177e4
LT		 792 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793 tw32_f(MAC_MI_MODE,
794 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795 udelay(80);
796 }
797
798 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
799 MI_COM_PHY_ADDR_MASK);
800 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
801 MI_COM_REG_ADDR_MASK);
802 frame_val |= (val & MI_COM_DATA_MASK);
803 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 804
1da177e4
LT		 805 tw32_f(MAC_MI_COM, frame_val);
806
807 loops = PHY_BUSY_LOOPS;
808 while (loops != 0) {
809 udelay(10);
810 frame_val = tr32(MAC_MI_COM);
811 if ((frame_val & MI_COM_BUSY) == 0) {
812 udelay(5);
813 frame_val = tr32(MAC_MI_COM);
814 break;
815 }
816 loops -= 1;
817 }
818
819 ret = -EBUSY;
820 if (loops != 0)
821 ret = 0;
822
823 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
824 tw32_f(MAC_MI_MODE, tp->mi_mode);
825 udelay(80);
826 }
827
828 return ret;
829}
830
95e2869a
MC		 831static int tg3_bmcr_reset(struct tg3 *tp)
832{
833 u32 phy_control;
834 int limit, err;
835
836 /* OK, reset it, and poll the BMCR_RESET bit until it
837 * clears or we time out.
838 */
839 phy_control = BMCR_RESET;
840 err = tg3_writephy(tp, MII_BMCR, phy_control);
841 if (err != 0)
842 return -EBUSY;
843
844 limit = 5000;
845 while (limit--) {
846 err = tg3_readphy(tp, MII_BMCR, &phy_control);
847 if (err != 0)
848 return -EBUSY;
849
850 if ((phy_control & BMCR_RESET) == 0) {
851 udelay(40);
852 break;
853 }
854 udelay(10);
855 }
d4675b52 856 if (limit < 0)
95e2869a
MC		 857 return -EBUSY;
858
859 return 0;
860}
861
158d7abd
MC		 862static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
863{
3d16543d 864 struct tg3 *tp = bp->priv;
158d7abd
MC		 865 u32 val;
866
867 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
868 return -EAGAIN;
869
870 if (tg3_readphy(tp, reg, &val))
871 return -EIO;
872
873 return val;
874}
875
876static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
877{
3d16543d 878 struct tg3 *tp = bp->priv;
158d7abd
MC		 879
880 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
881 return -EAGAIN;
882
883 if (tg3_writephy(tp, reg, val))
884 return -EIO;
885
886 return 0;
887}
888
889static int tg3_mdio_reset(struct mii_bus *bp)
890{
891 return 0;
892}
893
9c61d6bc 894static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 895{
896 u32 val;
fcb389df 897 struct phy_device *phydev;
a9daf367 898
fcb389df
MC		 899 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
900 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
901 case TG3_PHY_ID_BCM50610:
902 val = MAC_PHYCFG2_50610_LED_MODES;
903 break;
904 case TG3_PHY_ID_BCMAC131:
905 val = MAC_PHYCFG2_AC131_LED_MODES;
906 break;
907 case TG3_PHY_ID_RTL8211C:
908 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
909 break;
910 case TG3_PHY_ID_RTL8201E:
911 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
912 break;
913 default:
a9daf367 914 return;
fcb389df
MC		 915 }
916
917 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
918 tw32(MAC_PHYCFG2, val);
919
920 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 921 val &= ~(MAC_PHYCFG1_RGMII_INT |
922 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
923 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 924 tw32(MAC_PHYCFG1, val);
925
926 return;
927 }
928
929 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
930 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
931 MAC_PHYCFG2_FMODE_MASK_MASK |
932 MAC_PHYCFG2_GMODE_MASK_MASK |
933 MAC_PHYCFG2_ACT_MASK_MASK |
934 MAC_PHYCFG2_QUAL_MASK_MASK |
935 MAC_PHYCFG2_INBAND_ENABLE;
936
937 tw32(MAC_PHYCFG2, val);
a9daf367 938
bb85fbb6
MC		 939 val = tr32(MAC_PHYCFG1);
940 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
941 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
942 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 943 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
944 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
945 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
946 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
947 }
bb85fbb6
MC		 948 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
949 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
950 tw32(MAC_PHYCFG1, val);
a9daf367 951
a9daf367
MC		 952 val = tr32(MAC_EXT_RGMII_MODE);
953 val &= ~(MAC_RGMII_MODE_RX_INT_B |
954 MAC_RGMII_MODE_RX_QUALITY |
955 MAC_RGMII_MODE_RX_ACTIVITY |
956 MAC_RGMII_MODE_RX_ENG_DET |
957 MAC_RGMII_MODE_TX_ENABLE |
958 MAC_RGMII_MODE_TX_LOWPWR |
959 MAC_RGMII_MODE_TX_RESET);
fcb389df 960 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 961 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
962 val |= MAC_RGMII_MODE_RX_INT_B |
963 MAC_RGMII_MODE_RX_QUALITY |
964 MAC_RGMII_MODE_RX_ACTIVITY |
965 MAC_RGMII_MODE_RX_ENG_DET;
966 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
967 val |= MAC_RGMII_MODE_TX_ENABLE |
968 MAC_RGMII_MODE_TX_LOWPWR |
969 MAC_RGMII_MODE_TX_RESET;
970 }
971 tw32(MAC_EXT_RGMII_MODE, val);
972}
973
158d7abd
MC		 974static void tg3_mdio_start(struct tg3 *tp)
975{
976 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 977 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 978 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 979 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 980 }
981
982 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
983 tw32_f(MAC_MI_MODE, tp->mi_mode);
984 udelay(80);
a9daf367 985
9c61d6bc
MC		 986 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
988 tg3_mdio_config_5785(tp);
158d7abd
MC		 989}
990
991static void tg3_mdio_stop(struct tg3 *tp)
992{
993 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 994 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 995 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 996 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 997 }
998}
999
1000static int tg3_mdio_init(struct tg3 *tp)
1001{
1002 int i;
1003 u32 reg;
a9daf367 1004 struct phy_device *phydev;
158d7abd
MC		 1005
1006 tg3_mdio_start(tp);
1007
1008 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1009 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1010 return 0;
1011
298cf9be
LB		 1012 tp->mdio_bus = mdiobus_alloc();
1013 if (tp->mdio_bus == NULL)
1014 return -ENOMEM;
158d7abd 1015
298cf9be
LB		 1016 tp->mdio_bus->name = "tg3 mdio bus";
1017 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1018 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1019 tp->mdio_bus->priv = tp;
1020 tp->mdio_bus->parent = &tp->pdev->dev;
1021 tp->mdio_bus->read = &tg3_mdio_read;
1022 tp->mdio_bus->write = &tg3_mdio_write;
1023 tp->mdio_bus->reset = &tg3_mdio_reset;
1024 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1025 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1026
1027 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1028 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1029
1030 /* The bus registration will look for all the PHYs on the mdio bus.
1031 * Unfortunately, it does not ensure the PHY is powered up before
1032 * accessing the PHY ID registers. A chip reset is the
1033 * quickest way to bring the device back to an operational state..
1034 */
1035 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1036 tg3_bmcr_reset(tp);
1037
298cf9be 1038 i = mdiobus_register(tp->mdio_bus);
a9daf367 1039 if (i) {
158d7abd
MC		 1040 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1041 tp->dev->name, i);
9c61d6bc 1042 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1043 return i;
1044 }
158d7abd 1045
298cf9be 1046 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1047
9c61d6bc
MC		 1048 if (!phydev || !phydev->drv) {
1049 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1050 mdiobus_unregister(tp->mdio_bus);
1051 mdiobus_free(tp->mdio_bus);
1052 return -ENODEV;
1053 }
1054
1055 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1056 case TG3_PHY_ID_BCM57780:
1057 phydev->interface = PHY_INTERFACE_MODE_GMII;
1058 break;
a9daf367 1059 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1060 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1061 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1062 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1063 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1064 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1066 /* fallthru */
1067 case TG3_PHY_ID_RTL8211C:
1068 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1069 break;
fcb389df 1070 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1071 case TG3_PHY_ID_BCMAC131:
1072 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1073 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1074 break;
1075 }
1076
9c61d6bc
MC		 1077 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1078
1079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080 tg3_mdio_config_5785(tp);
a9daf367
MC		 1081
1082 return 0;
158d7abd
MC		 1083}
1084
1085static void tg3_mdio_fini(struct tg3 *tp)
1086{
1087 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1088 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1089 mdiobus_unregister(tp->mdio_bus);
1090 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1091 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1092 }
1093}
1094
4ba526ce
MC		 1095/* tp->lock is held. */
1096static inline void tg3_generate_fw_event(struct tg3 *tp)
1097{
1098 u32 val;
1099
1100 val = tr32(GRC_RX_CPU_EVENT);
1101 val |= GRC_RX_CPU_DRIVER_EVENT;
1102 tw32_f(GRC_RX_CPU_EVENT, val);
1103
1104 tp->last_event_jiffies = jiffies;
1105}
1106
1107#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1108
95e2869a
MC		 1109/* tp->lock is held. */
1110static void tg3_wait_for_event_ack(struct tg3 *tp)
1111{
1112 int i;
4ba526ce
MC		 1113 unsigned int delay_cnt;
1114 long time_remain;
1115
1116 /* If enough time has passed, no wait is necessary. */
1117 time_remain = (long)(tp->last_event_jiffies + 1 +
1118 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1119 (long)jiffies;
1120 if (time_remain < 0)
1121 return;
1122
1123 /* Check if we can shorten the wait time. */
1124 delay_cnt = jiffies_to_usecs(time_remain);
1125 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1126 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1127 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1128
4ba526ce 1129 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1130 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1131 break;
4ba526ce 1132 udelay(8);
95e2869a
MC		 1133 }
1134}
1135
1136/* tp->lock is held. */
1137static void tg3_ump_link_report(struct tg3 *tp)
1138{
1139 u32 reg;
1140 u32 val;
1141
1142 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1143 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1144 return;
1145
1146 tg3_wait_for_event_ack(tp);
1147
1148 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1149
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_BMCR, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_BMSR, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1158
1159 val = 0;
1160 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1161 val = reg << 16;
1162 if (!tg3_readphy(tp, MII_LPA, &reg))
1163 val |= (reg & 0xffff);
1164 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1165
1166 val = 0;
1167 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1168 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1169 val = reg << 16;
1170 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1171 val |= (reg & 0xffff);
1172 }
1173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1174
1175 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1176 val = reg << 16;
1177 else
1178 val = 0;
1179 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1180
4ba526ce 1181 tg3_generate_fw_event(tp);
95e2869a
MC		 1182}
1183
1184static void tg3_link_report(struct tg3 *tp)
1185{
1186 if (!netif_carrier_ok(tp->dev)) {
1187 if (netif_msg_link(tp))
1188 printk(KERN_INFO PFX "%s: Link is down.\n",
1189 tp->dev->name);
1190 tg3_ump_link_report(tp);
1191 } else if (netif_msg_link(tp)) {
1192 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1193 tp->dev->name,
1194 (tp->link_config.active_speed == SPEED_1000 ?
1195 1000 :
1196 (tp->link_config.active_speed == SPEED_100 ?
1197 100 : 10)),
1198 (tp->link_config.active_duplex == DUPLEX_FULL ?
1199 "full" : "half"));
1200
1201 printk(KERN_INFO PFX
1202 "%s: Flow control is %s for TX and %s for RX.\n",
1203 tp->dev->name,
e18ce346 1204 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1205 "on" : "off",
e18ce346 1206 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1207 "on" : "off");
1208 tg3_ump_link_report(tp);
1209 }
1210}
1211
1212static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1213{
1214 u16 miireg;
1215
e18ce346 1216 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1217 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1218 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1219 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1220 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1221 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1222 else
1223 miireg = 0;
1224
1225 return miireg;
1226}
1227
1228static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1229{
1230 u16 miireg;
1231
e18ce346 1232 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1233 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1234 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1235 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1236 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1237 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1238 else
1239 miireg = 0;
1240
1241 return miireg;
1242}
1243
95e2869a
MC		 1244static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1245{
1246 u8 cap = 0;
1247
1248 if (lcladv & ADVERTISE_1000XPAUSE) {
1249 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1250 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1251 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1252 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1253 cap = FLOW_CTRL_RX;
95e2869a
MC		 1254 } else {
1255 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1256 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1257 }
1258 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1260 cap = FLOW_CTRL_TX;
95e2869a
MC		 1261 }
1262
1263 return cap;
1264}
1265
f51f3562 1266static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1267{
b02fd9e3 1268 u8 autoneg;
f51f3562 1269 u8 flowctrl = 0;
95e2869a
MC		 1270 u32 old_rx_mode = tp->rx_mode;
1271 u32 old_tx_mode = tp->tx_mode;
1272
b02fd9e3 1273 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1274 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1275 else
1276 autoneg = tp->link_config.autoneg;
1277
1278 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1279 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1280 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1281 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1282 else
bc02ff95 1283 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1284 } else
1285 flowctrl = tp->link_config.flowctrl;
95e2869a 1286
f51f3562 1287 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1288
e18ce346 1289 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1290 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1291 else
1292 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1293
f51f3562 1294 if (old_rx_mode != tp->rx_mode)
95e2869a 1295 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1296
e18ce346 1297 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1298 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1299 else
1300 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1301
f51f3562 1302 if (old_tx_mode != tp->tx_mode)
95e2869a 1303 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1304}
1305
b02fd9e3
MC		 1306static void tg3_adjust_link(struct net_device *dev)
1307{
1308 u8 oldflowctrl, linkmesg = 0;
1309 u32 mac_mode, lcl_adv, rmt_adv;
1310 struct tg3 *tp = netdev_priv(dev);
298cf9be 1311 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1312
1313 spin_lock(&tp->lock);
1314
1315 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1316 MAC_MODE_HALF_DUPLEX);
1317
1318 oldflowctrl = tp->link_config.active_flowctrl;
1319
1320 if (phydev->link) {
1321 lcl_adv = 0;
1322 rmt_adv = 0;
1323
1324 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1325 mac_mode |= MAC_MODE_PORT_MODE_MII;
1326 else
1327 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1328
1329 if (phydev->duplex == DUPLEX_HALF)
1330 mac_mode |= MAC_MODE_HALF_DUPLEX;
1331 else {
1332 lcl_adv = tg3_advert_flowctrl_1000T(
1333 tp->link_config.flowctrl);
1334
1335 if (phydev->pause)
1336 rmt_adv = LPA_PAUSE_CAP;
1337 if (phydev->asym_pause)
1338 rmt_adv |= LPA_PAUSE_ASYM;
1339 }
1340
1341 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1342 } else
1343 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1344
1345 if (mac_mode != tp->mac_mode) {
1346 tp->mac_mode = mac_mode;
1347 tw32_f(MAC_MODE, tp->mac_mode);
1348 udelay(40);
1349 }
1350
fcb389df
MC		 1351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1352 if (phydev->speed == SPEED_10)
1353 tw32(MAC_MI_STAT,
1354 MAC_MI_STAT_10MBPS_MODE |
1355 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1356 else
1357 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1358 }
1359
b02fd9e3
MC		 1360 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1361 tw32(MAC_TX_LENGTHS,
1362 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1363 (6 << TX_LENGTHS_IPG_SHIFT) |
1364 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1365 else
1366 tw32(MAC_TX_LENGTHS,
1367 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1368 (6 << TX_LENGTHS_IPG_SHIFT) |
1369 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1370
1371 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1372 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1373 phydev->speed != tp->link_config.active_speed ||
1374 phydev->duplex != tp->link_config.active_duplex ||
1375 oldflowctrl != tp->link_config.active_flowctrl)
1376 linkmesg = 1;
1377
1378 tp->link_config.active_speed = phydev->speed;
1379 tp->link_config.active_duplex = phydev->duplex;
1380
1381 spin_unlock(&tp->lock);
1382
1383 if (linkmesg)
1384 tg3_link_report(tp);
1385}
1386
1387static int tg3_phy_init(struct tg3 *tp)
1388{
1389 struct phy_device *phydev;
1390
1391 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1392 return 0;
1393
1394 /* Bring the PHY back to a known state. */
1395 tg3_bmcr_reset(tp);
1396
298cf9be 1397 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1398
1399 /* Attach the MAC to the PHY. */
fb28ad35 1400 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1401 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1402 if (IS_ERR(phydev)) {
1403 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1404 return PTR_ERR(phydev);
1405 }
1406
b02fd9e3 1407 /* Mask with MAC supported features. */
9c61d6bc
MC		 1408 switch (phydev->interface) {
1409 case PHY_INTERFACE_MODE_GMII:
1410 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1411 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1412 phydev->supported &= (PHY_GBIT_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 }
1417 /* fallthru */
9c61d6bc
MC		 1418 case PHY_INTERFACE_MODE_MII:
1419 phydev->supported &= (PHY_BASIC_FEATURES |
1420 SUPPORTED_Pause |
1421 SUPPORTED_Asym_Pause);
1422 break;
1423 default:
1424 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1425 return -EINVAL;
1426 }
1427
1428 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1429
1430 phydev->advertising = phydev->supported;
1431
b02fd9e3
MC		 1432 return 0;
1433}
1434
1435static void tg3_phy_start(struct tg3 *tp)
1436{
1437 struct phy_device *phydev;
1438
1439 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1440 return;
1441
298cf9be 1442 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1443
1444 if (tp->link_config.phy_is_low_power) {
1445 tp->link_config.phy_is_low_power = 0;
1446 phydev->speed = tp->link_config.orig_speed;
1447 phydev->duplex = tp->link_config.orig_duplex;
1448 phydev->autoneg = tp->link_config.orig_autoneg;
1449 phydev->advertising = tp->link_config.orig_advertising;
1450 }
1451
1452 phy_start(phydev);
1453
1454 phy_start_aneg(phydev);
1455}
1456
1457static void tg3_phy_stop(struct tg3 *tp)
1458{
1459 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1460 return;
1461
298cf9be 1462 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1463}
1464
1465static void tg3_phy_fini(struct tg3 *tp)
1466{
1467 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1468 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1469 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1470 }
1471}
1472
b2a5c19c
MC		 1473static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1474{
1475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1477}
1478
7f97a4bd
MC		 1479static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1480{
1481 u32 phytest;
1482
1483 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1484 u32 phy;
1485
1486 tg3_writephy(tp, MII_TG3_FET_TEST,
1487 phytest | MII_TG3_FET_SHADOW_EN);
1488 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1489 if (enable)
1490 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1491 else
1492 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1493 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1494 }
1495 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1496 }
1497}
1498
6833c043
MC		 1499static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1500{
1501 u32 reg;
1502
7f97a4bd 1503 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1504 return;
1505
7f97a4bd
MC		 1506 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1507 tg3_phy_fet_toggle_apd(tp, enable);
1508 return;
1509 }
1510
6833c043
MC		 1511 reg = MII_TG3_MISC_SHDW_WREN |
1512 MII_TG3_MISC_SHDW_SCR5_SEL |
1513 MII_TG3_MISC_SHDW_SCR5_LPED |
1514 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1515 MII_TG3_MISC_SHDW_SCR5_SDTL |
1516 MII_TG3_MISC_SHDW_SCR5_C125OE;
1517 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1518 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1519
1520 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1521
1522
1523 reg = MII_TG3_MISC_SHDW_WREN |
1524 MII_TG3_MISC_SHDW_APD_SEL |
1525 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1526 if (enable)
1527 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1528
1529 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1530}
1531
9ef8ca99
MC		 1532static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1533{
1534 u32 phy;
1535
1536 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1537 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1538 return;
1539
7f97a4bd 1540 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1541 u32 ephy;
1542
535ef6e1
MC		 1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1544 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1545
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 ephy | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1549 if (enable)
535ef6e1 1550 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1551 else
535ef6e1
MC		 1552 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1553 tg3_writephy(tp, reg, phy);
9ef8ca99 1554 }
535ef6e1 1555 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1556 }
1557 } else {
1558 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1559 MII_TG3_AUXCTL_SHDWSEL_MISC;
1560 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1561 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1562 if (enable)
1563 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1564 else
1565 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1566 phy |= MII_TG3_AUXCTL_MISC_WREN;
1567 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1568 }
1569 }
1570}
1571
1da177e4
LT		 1572static void tg3_phy_set_wirespeed(struct tg3 *tp)
1573{
1574 u32 val;
1575
1576 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1577 return;
1578
1579 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1580 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1581 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1582 (val | (1 << 15) | (1 << 4)));
1583}
1584
b2a5c19c
MC		 1585static void tg3_phy_apply_otp(struct tg3 *tp)
1586{
1587 u32 otp, phy;
1588
1589 if (!tp->phy_otp)
1590 return;
1591
1592 otp = tp->phy_otp;
1593
1594 /* Enable SM_DSP clock and tx 6dB coding. */
1595 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1596 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1597 MII_TG3_AUXCTL_ACTL_TX_6DB;
1598 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1599
1600 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1601 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1602 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1603
1604 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1605 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1606 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1607
1608 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1609 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1610 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1611
1612 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1613 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1614
1615 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1616 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1617
1618 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1619 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1620 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1621
1622 /* Turn off SM_DSP clock. */
1623 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1624 MII_TG3_AUXCTL_ACTL_TX_6DB;
1625 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1626}
1627
1da177e4
LT		 1628static int tg3_wait_macro_done(struct tg3 *tp)
1629{
1630 int limit = 100;
1631
1632 while (limit--) {
1633 u32 tmp32;
1634
1635 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1636 if ((tmp32 & 0x1000) == 0)
1637 break;
1638 }
1639 }
d4675b52 1640 if (limit < 0)
1da177e4
LT		 1641 return -EBUSY;
1642
1643 return 0;
1644}
1645
1646static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1647{
1648 static const u32 test_pat[4][6] = {
1649 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1650 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1651 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1652 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1653 };
1654 int chan;
1655
1656 for (chan = 0; chan < 4; chan++) {
1657 int i;
1658
1659 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1660 (chan * 0x2000) | 0x0200);
1661 tg3_writephy(tp, 0x16, 0x0002);
1662
1663 for (i = 0; i < 6; i++)
1664 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1665 test_pat[chan][i]);
1666
1667 tg3_writephy(tp, 0x16, 0x0202);
1668 if (tg3_wait_macro_done(tp)) {
1669 *resetp = 1;
1670 return -EBUSY;
1671 }
1672
1673 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1674 (chan * 0x2000) | 0x0200);
1675 tg3_writephy(tp, 0x16, 0x0082);
1676 if (tg3_wait_macro_done(tp)) {
1677 *resetp = 1;
1678 return -EBUSY;
1679 }
1680
1681 tg3_writephy(tp, 0x16, 0x0802);
1682 if (tg3_wait_macro_done(tp)) {
1683 *resetp = 1;
1684 return -EBUSY;
1685 }
1686
1687 for (i = 0; i < 6; i += 2) {
1688 u32 low, high;
1689
1690 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1691 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1692 tg3_wait_macro_done(tp)) {
1693 *resetp = 1;
1694 return -EBUSY;
1695 }
1696 low &= 0x7fff;
1697 high &= 0x000f;
1698 if (low != test_pat[chan][i] ||
1699 high != test_pat[chan][i+1]) {
1700 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1701 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1702 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1703
1704 return -EBUSY;
1705 }
1706 }
1707 }
1708
1709 return 0;
1710}
1711
1712static int tg3_phy_reset_chanpat(struct tg3 *tp)
1713{
1714 int chan;
1715
1716 for (chan = 0; chan < 4; chan++) {
1717 int i;
1718
1719 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720 (chan * 0x2000) | 0x0200);
1721 tg3_writephy(tp, 0x16, 0x0002);
1722 for (i = 0; i < 6; i++)
1723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1724 tg3_writephy(tp, 0x16, 0x0202);
1725 if (tg3_wait_macro_done(tp))
1726 return -EBUSY;
1727 }
1728
1729 return 0;
1730}
1731
1732static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1733{
1734 u32 reg32, phy9_orig;
1735 int retries, do_phy_reset, err;
1736
1737 retries = 10;
1738 do_phy_reset = 1;
1739 do {
1740 if (do_phy_reset) {
1741 err = tg3_bmcr_reset(tp);
1742 if (err)
1743 return err;
1744 do_phy_reset = 0;
1745 }
1746
1747 /* Disable transmitter and interrupt. */
1748 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1749 continue;
1750
1751 reg32 |= 0x3000;
1752 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1753
1754 /* Set full-duplex, 1000 mbps. */
1755 tg3_writephy(tp, MII_BMCR,
1756 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1757
1758 /* Set to master mode. */
1759 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1760 continue;
1761
1762 tg3_writephy(tp, MII_TG3_CTRL,
1763 (MII_TG3_CTRL_AS_MASTER |
1764 MII_TG3_CTRL_ENABLE_AS_MASTER));
1765
1766 /* Enable SM_DSP_CLOCK and 6dB. */
1767 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1768
1769 /* Block the PHY control access. */
1770 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1771 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1772
1773 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1774 if (!err)
1775 break;
1776 } while (--retries);
1777
1778 err = tg3_phy_reset_chanpat(tp);
1779 if (err)
1780 return err;
1781
1782 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1783 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1784
1785 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1786 tg3_writephy(tp, 0x16, 0x0000);
1787
1788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1790 /* Set Extended packet length bit for jumbo frames */
1791 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1792 }
1793 else {
1794 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1795 }
1796
1797 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1798
1799 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1800 reg32 &= ~0x3000;
1801 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1802 } else if (!err)
1803 err = -EBUSY;
1804
1805 return err;
1806}
1807
1808/* This will reset the tigon3 PHY if there is no valid
1809 * link unless the FORCE argument is non-zero.
1810 */
1811static int tg3_phy_reset(struct tg3 *tp)
1812{
b2a5c19c 1813 u32 cpmuctrl;
1da177e4
LT		 1814 u32 phy_status;
1815 int err;
1816
60189ddf
MC		 1817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1818 u32 val;
1819
1820 val = tr32(GRC_MISC_CFG);
1821 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1822 udelay(40);
1823 }
1da177e4
LT		 1824 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1825 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1826 if (err != 0)
1827 return -EBUSY;
1828
c8e1e82b
MC		 1829 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1830 netif_carrier_off(tp->dev);
1831 tg3_link_report(tp);
1832 }
1833
1da177e4
LT		 1834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1837 err = tg3_phy_reset_5703_4_5(tp);
1838 if (err)
1839 return err;
1840 goto out;
1841 }
1842
b2a5c19c
MC		 1843 cpmuctrl = 0;
1844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1845 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1846 cpmuctrl = tr32(TG3_CPMU_CTRL);
1847 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1848 tw32(TG3_CPMU_CTRL,
1849 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1850 }
1851
1da177e4
LT		 1852 err = tg3_bmcr_reset(tp);
1853 if (err)
1854 return err;
1855
b2a5c19c
MC		 1856 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1857 u32 phy;
1858
1859 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1860 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1861
1862 tw32(TG3_CPMU_CTRL, cpmuctrl);
1863 }
1864
bcb37f6c
MC		 1865 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1866 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1867 u32 val;
1868
1869 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1870 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1871 CPMU_LSPD_1000MB_MACCLK_12_5) {
1872 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1873 udelay(40);
1874 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1875 }
1876 }
1877
b2a5c19c
MC		 1878 tg3_phy_apply_otp(tp);
1879
6833c043
MC		 1880 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1881 tg3_phy_toggle_apd(tp, true);
1882 else
1883 tg3_phy_toggle_apd(tp, false);
1884
1da177e4
LT		 1885out:
1886 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1887 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1888 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1889 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1890 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1891 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1892 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1893 }
1894 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1895 tg3_writephy(tp, 0x1c, 0x8d68);
1896 tg3_writephy(tp, 0x1c, 0x8d68);
1897 }
1898 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1900 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1902 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1903 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1904 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1905 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1906 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1907 }
c424cb24
MC		 1908 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1909 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1911 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1913 tg3_writephy(tp, MII_TG3_TEST1,
1914 MII_TG3_TEST1_TRIM_EN | 0x4);
1915 } else
1916 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1917 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1918 }
1da177e4
LT		 1919 /* Set Extended packet length bit (bit 14) on all chips that */
1920 /* support jumbo frames */
1921 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1922 /* Cannot do read-modify-write on 5401 */
1923 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1924 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1925 u32 phy_reg;
1926
1927 /* Set bit 14 with read-modify-write to preserve other bits */
1928 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1929 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1930 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1931 }
1932
1933 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1934 * jumbo frames transmission.
1935 */
0f893dc6 1936 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1937 u32 phy_reg;
1938
1939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1940 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1941 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1942 }
1943
715116a1 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1945 /* adjust output voltage */
535ef6e1 1946 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1947 }
1948
9ef8ca99 1949 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1950 tg3_phy_set_wirespeed(tp);
1951 return 0;
1952}
1953
1954static void tg3_frob_aux_power(struct tg3 *tp)
1955{
1956 struct tg3 *tp_peer = tp;
1957
9d26e213 1958 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1959 return;
1960
8c2dc7e1
MC		 1961 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1962 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1963 struct net_device *dev_peer;
1964
1965 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1966 /* remove_one() may have been run on the peer. */
8c2dc7e1 1967 if (!dev_peer)
bc1c7567
MC		 1968 tp_peer = tp;
1969 else
1970 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1971 }
1972
1da177e4 1973 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1974 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1975 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1976 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1979 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1980 (GRC_LCLCTRL_GPIO_OE0 |
1981 GRC_LCLCTRL_GPIO_OE1 |
1982 GRC_LCLCTRL_GPIO_OE2 |
1983 GRC_LCLCTRL_GPIO_OUTPUT0 |
1984 GRC_LCLCTRL_GPIO_OUTPUT1),
1985 100);
8d519ab2
MC		 1986 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1987 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1988 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1989 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT0 |
1993 GRC_LCLCTRL_GPIO_OUTPUT1 |
1994 tp->grc_local_ctrl;
1995 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1996
1997 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1998 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1999
2000 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2001 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2002 } else {
2003 u32 no_gpio2;
dc56b7d4 2004 u32 grc_local_ctrl = 0;
1da177e4
LT		 2005
2006 if (tp_peer != tp &&
2007 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2008 return;
2009
dc56b7d4
MC		 2010 /* Workaround to prevent overdrawing Amps. */
2011 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2012 ASIC_REV_5714) {
2013 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2014 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2015 grc_local_ctrl, 100);
dc56b7d4
MC		 2016 }
2017
1da177e4
LT		 2018 /* On 5753 and variants, GPIO2 cannot be used. */
2019 no_gpio2 = tp->nic_sram_data_cfg &
2020 NIC_SRAM_DATA_CFG_NO_GPIO2;
2021
dc56b7d4 2022 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2023 GRC_LCLCTRL_GPIO_OE1 |
2024 GRC_LCLCTRL_GPIO_OE2 |
2025 GRC_LCLCTRL_GPIO_OUTPUT1 |
2026 GRC_LCLCTRL_GPIO_OUTPUT2;
2027 if (no_gpio2) {
2028 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2029 GRC_LCLCTRL_GPIO_OUTPUT2);
2030 }
b401e9e2
MC		 2031 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032 grc_local_ctrl, 100);
1da177e4
LT		 2033
2034 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2035
b401e9e2
MC		 2036 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2037 grc_local_ctrl, 100);
1da177e4
LT		 2038
2039 if (!no_gpio2) {
2040 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2041 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042 grc_local_ctrl, 100);
1da177e4
LT		 2043 }
2044 }
2045 } else {
2046 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2047 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2048 if (tp_peer != tp &&
2049 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2050 return;
2051
b401e9e2
MC		 2052 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2053 (GRC_LCLCTRL_GPIO_OE1 |
2054 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2055
b401e9e2
MC		 2056 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2057 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2058
b401e9e2
MC		 2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE1 |
2061 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2062 }
2063 }
2064}
2065
e8f3f6ca
MC		 2066static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2067{
2068 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2069 return 1;
2070 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2071 if (speed != SPEED_10)
2072 return 1;
2073 } else if (speed == SPEED_10)
2074 return 1;
2075
2076 return 0;
2077}
2078
1da177e4
LT		 2079static int tg3_setup_phy(struct tg3 *, int);
2080
2081#define RESET_KIND_SHUTDOWN 0
2082#define RESET_KIND_INIT 1
2083#define RESET_KIND_SUSPEND 2
2084
2085static void tg3_write_sig_post_reset(struct tg3 *, int);
2086static int tg3_halt_cpu(struct tg3 *, u32);
2087
0a459aac 2088static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2089{
ce057f01
MC		 2090 u32 val;
2091
5129724a
MC		 2092 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2094 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2095 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2096
2097 sg_dig_ctrl |=
2098 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2099 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2100 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2101 }
3f7045c1 2102 return;
5129724a 2103 }
3f7045c1 2104
60189ddf 2105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2106 tg3_bmcr_reset(tp);
2107 val = tr32(GRC_MISC_CFG);
2108 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2109 udelay(40);
2110 return;
0a459aac 2111 } else if (do_low_power) {
715116a1
MC		 2112 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2113 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2114
2115 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2116 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2117 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2118 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2119 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2120 }
3f7045c1 2121
15c3b696
MC		 2122 /* The PHY should not be powered down on some chips because
2123 * of bugs.
2124 */
2125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2128 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2129 return;
ce057f01 2130
bcb37f6c
MC		 2131 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2132 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2133 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2134 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2135 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2136 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2137 }
2138
15c3b696
MC		 2139 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2140}
2141
ffbcfed4
MC		 2142/* tp->lock is held. */
2143static int tg3_nvram_lock(struct tg3 *tp)
2144{
2145 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2146 int i;
2147
2148 if (tp->nvram_lock_cnt == 0) {
2149 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2150 for (i = 0; i < 8000; i++) {
2151 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2152 break;
2153 udelay(20);
2154 }
2155 if (i == 8000) {
2156 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2157 return -ENODEV;
2158 }
2159 }
2160 tp->nvram_lock_cnt++;
2161 }
2162 return 0;
2163}
2164
2165/* tp->lock is held. */
2166static void tg3_nvram_unlock(struct tg3 *tp)
2167{
2168 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2169 if (tp->nvram_lock_cnt > 0)
2170 tp->nvram_lock_cnt--;
2171 if (tp->nvram_lock_cnt == 0)
2172 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2173 }
2174}
2175
2176/* tp->lock is held. */
2177static void tg3_enable_nvram_access(struct tg3 *tp)
2178{
2179 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2180 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2181 u32 nvaccess = tr32(NVRAM_ACCESS);
2182
2183 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2184 }
2185}
2186
2187/* tp->lock is held. */
2188static void tg3_disable_nvram_access(struct tg3 *tp)
2189{
2190 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2191 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2192 u32 nvaccess = tr32(NVRAM_ACCESS);
2193
2194 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2195 }
2196}
2197
2198static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2199 u32 offset, u32 *val)
2200{
2201 u32 tmp;
2202 int i;
2203
2204 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2205 return -EINVAL;
2206
2207 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2208 EEPROM_ADDR_DEVID_MASK |
2209 EEPROM_ADDR_READ);
2210 tw32(GRC_EEPROM_ADDR,
2211 tmp |
2212 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2213 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2214 EEPROM_ADDR_ADDR_MASK) |
2215 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2216
2217 for (i = 0; i < 1000; i++) {
2218 tmp = tr32(GRC_EEPROM_ADDR);
2219
2220 if (tmp & EEPROM_ADDR_COMPLETE)
2221 break;
2222 msleep(1);
2223 }
2224 if (!(tmp & EEPROM_ADDR_COMPLETE))
2225 return -EBUSY;
2226
62cedd11
MC		 2227 tmp = tr32(GRC_EEPROM_DATA);
2228
2229 /*
2230 * The data will always be opposite the native endian
2231 * format. Perform a blind byteswap to compensate.
2232 */
2233 *val = swab32(tmp);
2234
ffbcfed4
MC		 2235 return 0;
2236}
2237
2238#define NVRAM_CMD_TIMEOUT 10000
2239
2240static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2241{
2242 int i;
2243
2244 tw32(NVRAM_CMD, nvram_cmd);
2245 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2246 udelay(10);
2247 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2248 udelay(10);
2249 break;
2250 }
2251 }
2252
2253 if (i == NVRAM_CMD_TIMEOUT)
2254 return -EBUSY;
2255
2256 return 0;
2257}
2258
2259static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2260{
2261 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2262 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2263 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2264 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2265 (tp->nvram_jedecnum == JEDEC_ATMEL))
2266
2267 addr = ((addr / tp->nvram_pagesize) <<
2268 ATMEL_AT45DB0X1B_PAGE_POS) +
2269 (addr % tp->nvram_pagesize);
2270
2271 return addr;
2272}
2273
2274static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2275{
2276 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2277 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2278 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2279 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2280 (tp->nvram_jedecnum == JEDEC_ATMEL))
2281
2282 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2283 tp->nvram_pagesize) +
2284 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2285
2286 return addr;
2287}
2288
e4f34110
MC		 2289/* NOTE: Data read in from NVRAM is byteswapped according to
2290 * the byteswapping settings for all other register accesses.
2291 * tg3 devices are BE devices, so on a BE machine, the data
2292 * returned will be exactly as it is seen in NVRAM. On a LE
2293 * machine, the 32-bit value will be byteswapped.
2294 */
ffbcfed4
MC		 2295static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2296{
2297 int ret;
2298
2299 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2300 return tg3_nvram_read_using_eeprom(tp, offset, val);
2301
2302 offset = tg3_nvram_phys_addr(tp, offset);
2303
2304 if (offset > NVRAM_ADDR_MSK)
2305 return -EINVAL;
2306
2307 ret = tg3_nvram_lock(tp);
2308 if (ret)
2309 return ret;
2310
2311 tg3_enable_nvram_access(tp);
2312
2313 tw32(NVRAM_ADDR, offset);
2314 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2315 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2316
2317 if (ret == 0)
e4f34110 2318 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2319
2320 tg3_disable_nvram_access(tp);
2321
2322 tg3_nvram_unlock(tp);
2323
2324 return ret;
2325}
2326
a9dc529d
MC		 2327/* Ensures NVRAM data is in bytestream format. */
2328static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2329{
2330 u32 v;
a9dc529d 2331 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2332 if (!res)
a9dc529d 2333 *val = cpu_to_be32(v);
ffbcfed4
MC		 2334 return res;
2335}
2336
3f007891
MC		 2337/* tp->lock is held. */
2338static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2339{
2340 u32 addr_high, addr_low;
2341 int i;
2342
2343 addr_high = ((tp->dev->dev_addr[0] << 8) |
2344 tp->dev->dev_addr[1]);
2345 addr_low = ((tp->dev->dev_addr[2] << 24) |
2346 (tp->dev->dev_addr[3] << 16) |
2347 (tp->dev->dev_addr[4] << 8) |
2348 (tp->dev->dev_addr[5] << 0));
2349 for (i = 0; i < 4; i++) {
2350 if (i == 1 && skip_mac_1)
2351 continue;
2352 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2353 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2354 }
2355
2356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2357 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2358 for (i = 0; i < 12; i++) {
2359 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2360 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2361 }
2362 }
2363
2364 addr_high = (tp->dev->dev_addr[0] +
2365 tp->dev->dev_addr[1] +
2366 tp->dev->dev_addr[2] +
2367 tp->dev->dev_addr[3] +
2368 tp->dev->dev_addr[4] +
2369 tp->dev->dev_addr[5]) &
2370 TX_BACKOFF_SEED_MASK;
2371 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2372}
2373
bc1c7567 2374static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2375{
2376 u32 misc_host_ctrl;
0a459aac 2377 bool device_should_wake, do_low_power;
1da177e4
LT		 2378
2379 /* Make sure register accesses (indirect or otherwise)
2380 * will function correctly.
2381 */
2382 pci_write_config_dword(tp->pdev,
2383 TG3PCI_MISC_HOST_CTRL,
2384 tp->misc_host_ctrl);
2385
1da177e4 2386 switch (state) {
bc1c7567 2387 case PCI_D0:
12dac075
RW		 2388 pci_enable_wake(tp->pdev, state, false);
2389 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2390
9d26e213
MC		 2391 /* Switch out of Vaux if it is a NIC */
2392 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2393 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2394
2395 return 0;
2396
bc1c7567 2397 case PCI_D1:
bc1c7567 2398 case PCI_D2:
bc1c7567 2399 case PCI_D3hot:
1da177e4
LT		 2400 break;
2401
2402 default:
12dac075
RW		 2403 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2404 tp->dev->name, state);
1da177e4 2405 return -EINVAL;
855e1111 2406 }
5e7dfd0f
MC		 2407
2408 /* Restore the CLKREQ setting. */
2409 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2410 u16 lnkctl;
2411
2412 pci_read_config_word(tp->pdev,
2413 tp->pcie_cap + PCI_EXP_LNKCTL,
2414 &lnkctl);
2415 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2416 pci_write_config_word(tp->pdev,
2417 tp->pcie_cap + PCI_EXP_LNKCTL,
2418 lnkctl);
2419 }
2420
1da177e4
LT		 2421 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2422 tw32(TG3PCI_MISC_HOST_CTRL,
2423 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2424
05ac4cb7
MC		 2425 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2426 device_may_wakeup(&tp->pdev->dev) &&
2427 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2428
dd477003 2429 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2430 do_low_power = false;
b02fd9e3
MC		 2431 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2432 !tp->link_config.phy_is_low_power) {
2433 struct phy_device *phydev;
0a459aac 2434 u32 phyid, advertising;
b02fd9e3 2435
298cf9be 2436 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2437
2438 tp->link_config.phy_is_low_power = 1;
2439
2440 tp->link_config.orig_speed = phydev->speed;
2441 tp->link_config.orig_duplex = phydev->duplex;
2442 tp->link_config.orig_autoneg = phydev->autoneg;
2443 tp->link_config.orig_advertising = phydev->advertising;
2444
2445 advertising = ADVERTISED_TP |
2446 ADVERTISED_Pause |
2447 ADVERTISED_Autoneg |
2448 ADVERTISED_10baseT_Half;
2449
2450 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2451 device_should_wake) {
b02fd9e3
MC		 2452 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2453 advertising |=
2454 ADVERTISED_100baseT_Half |
2455 ADVERTISED_100baseT_Full |
2456 ADVERTISED_10baseT_Full;
2457 else
2458 advertising |= ADVERTISED_10baseT_Full;
2459 }
2460
2461 phydev->advertising = advertising;
2462
2463 phy_start_aneg(phydev);
0a459aac
MC		 2464
2465 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2466 if (phyid != TG3_PHY_ID_BCMAC131) {
2467 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2468 if (phyid == TG3_PHY_OUI_1 ||
2469 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2470 phyid == TG3_PHY_OUI_3)
2471 do_low_power = true;
2472 }
b02fd9e3 2473 }
dd477003 2474 } else {
2023276e 2475 do_low_power = true;
0a459aac 2476
dd477003
MC		 2477 if (tp->link_config.phy_is_low_power == 0) {
2478 tp->link_config.phy_is_low_power = 1;
2479 tp->link_config.orig_speed = tp->link_config.speed;
2480 tp->link_config.orig_duplex = tp->link_config.duplex;
2481 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2482 }
1da177e4 2483
dd477003
MC		 2484 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2485 tp->link_config.speed = SPEED_10;
2486 tp->link_config.duplex = DUPLEX_HALF;
2487 tp->link_config.autoneg = AUTONEG_ENABLE;
2488 tg3_setup_phy(tp, 0);
2489 }
1da177e4
LT		 2490 }
2491
b5d3772c
MC		 2492 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2493 u32 val;
2494
2495 val = tr32(GRC_VCPU_EXT_CTRL);
2496 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2497 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2498 int i;
2499 u32 val;
2500
2501 for (i = 0; i < 200; i++) {
2502 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2503 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2504 break;
2505 msleep(1);
2506 }
2507 }
a85feb8c
GZ		 2508 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2509 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2510 WOL_DRV_STATE_SHUTDOWN |
2511 WOL_DRV_WOL |
2512 WOL_SET_MAGIC_PKT);
6921d201 2513
05ac4cb7 2514 if (device_should_wake) {
1da177e4
LT		 2515 u32 mac_mode;
2516
2517 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2518 if (do_low_power) {
dd477003
MC		 2519 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2520 udelay(40);
2521 }
1da177e4 2522
3f7045c1
MC		 2523 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2524 mac_mode = MAC_MODE_PORT_MODE_GMII;
2525 else
2526 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2527
e8f3f6ca
MC		 2528 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2529 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2530 ASIC_REV_5700) {
2531 u32 speed = (tp->tg3_flags &
2532 TG3_FLAG_WOL_SPEED_100MB) ?
2533 SPEED_100 : SPEED_10;
2534 if (tg3_5700_link_polarity(tp, speed))
2535 mac_mode |= MAC_MODE_LINK_POLARITY;
2536 else
2537 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2538 }
1da177e4
LT		 2539 } else {
2540 mac_mode = MAC_MODE_PORT_MODE_TBI;
2541 }
2542
cbf46853 2543 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2544 tw32(MAC_LED_CTRL, tp->led_ctrl);
2545
05ac4cb7
MC		 2546 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2547 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2548 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2549 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2550 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2551 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2552
3bda1258
MC		 2553 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2554 mac_mode |= tp->mac_mode &
2555 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2556 if (mac_mode & MAC_MODE_APE_TX_EN)
2557 mac_mode |= MAC_MODE_TDE_ENABLE;
2558 }
2559
1da177e4
LT		 2560 tw32_f(MAC_MODE, mac_mode);
2561 udelay(100);
2562
2563 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2564 udelay(10);
2565 }
2566
2567 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2568 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2570 u32 base_val;
2571
2572 base_val = tp->pci_clock_ctrl;
2573 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2574 CLOCK_CTRL_TXCLK_DISABLE);
2575
b401e9e2
MC		 2576 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2577 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2578 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2579 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2580 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2581 /* do nothing */
85e94ced 2582 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2583 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2584 u32 newbits1, newbits2;
2585
2586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2588 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2589 CLOCK_CTRL_TXCLK_DISABLE |
2590 CLOCK_CTRL_ALTCLK);
2591 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2592 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2593 newbits1 = CLOCK_CTRL_625_CORE;
2594 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2595 } else {
2596 newbits1 = CLOCK_CTRL_ALTCLK;
2597 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2598 }
2599
b401e9e2
MC		 2600 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2601 40);
1da177e4 2602
b401e9e2
MC		 2603 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2604 40);
1da177e4
LT		 2605
2606 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2607 u32 newbits3;
2608
2609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2611 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2612 CLOCK_CTRL_TXCLK_DISABLE |
2613 CLOCK_CTRL_44MHZ_CORE);
2614 } else {
2615 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2616 }
2617
b401e9e2
MC		 2618 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2619 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2620 }
2621 }
2622
05ac4cb7 2623 if (!(device_should_wake) &&
22435849 2624 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2625 tg3_power_down_phy(tp, do_low_power);
6921d201 2626
1da177e4
LT		 2627 tg3_frob_aux_power(tp);
2628
2629 /* Workaround for unstable PLL clock */
2630 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2631 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2632 u32 val = tr32(0x7d00);
2633
2634 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2635 tw32(0x7d00, val);
6921d201 2636 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2637 int err;
2638
2639 err = tg3_nvram_lock(tp);
1da177e4 2640 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2641 if (!err)
2642 tg3_nvram_unlock(tp);
6921d201 2643 }
1da177e4
LT		 2644 }
2645
bbadf503
MC		 2646 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2647
05ac4cb7 2648 if (device_should_wake)
12dac075
RW		 2649 pci_enable_wake(tp->pdev, state, true);
2650
1da177e4 2651 /* Finally, set the new power state. */
12dac075 2652 pci_set_power_state(tp->pdev, state);
1da177e4 2653
1da177e4
LT		 2654 return 0;
2655}
2656
1da177e4
LT		 2657static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2658{
2659 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2660 case MII_TG3_AUX_STAT_10HALF:
2661 *speed = SPEED_10;
2662 *duplex = DUPLEX_HALF;
2663 break;
2664
2665 case MII_TG3_AUX_STAT_10FULL:
2666 *speed = SPEED_10;
2667 *duplex = DUPLEX_FULL;
2668 break;
2669
2670 case MII_TG3_AUX_STAT_100HALF:
2671 *speed = SPEED_100;
2672 *duplex = DUPLEX_HALF;
2673 break;
2674
2675 case MII_TG3_AUX_STAT_100FULL:
2676 *speed = SPEED_100;
2677 *duplex = DUPLEX_FULL;
2678 break;
2679
2680 case MII_TG3_AUX_STAT_1000HALF:
2681 *speed = SPEED_1000;
2682 *duplex = DUPLEX_HALF;
2683 break;
2684
2685 case MII_TG3_AUX_STAT_1000FULL:
2686 *speed = SPEED_1000;
2687 *duplex = DUPLEX_FULL;
2688 break;
2689
2690 default:
7f97a4bd 2691 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2692 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2693 SPEED_10;
2694 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2695 DUPLEX_HALF;
2696 break;
2697 }
1da177e4
LT		 2698 *speed = SPEED_INVALID;
2699 *duplex = DUPLEX_INVALID;
2700 break;
855e1111 2701 }
1da177e4
LT		 2702}
2703
2704static void tg3_phy_copper_begin(struct tg3 *tp)
2705{
2706 u32 new_adv;
2707 int i;
2708
2709 if (tp->link_config.phy_is_low_power) {
2710 /* Entering low power mode. Disable gigabit and
2711 * 100baseT advertisements.
2712 */
2713 tg3_writephy(tp, MII_TG3_CTRL, 0);
2714
2715 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2716 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2717 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2718 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2719
2720 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2721 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2722 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2723 tp->link_config.advertising &=
2724 ~(ADVERTISED_1000baseT_Half |
2725 ADVERTISED_1000baseT_Full);
2726
ba4d07a8 2727 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2728 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2729 new_adv |= ADVERTISE_10HALF;
2730 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2731 new_adv |= ADVERTISE_10FULL;
2732 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2733 new_adv |= ADVERTISE_100HALF;
2734 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2735 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2736
2737 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2738
1da177e4
LT		 2739 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2740
2741 if (tp->link_config.advertising &
2742 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2743 new_adv = 0;
2744 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2745 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2746 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2747 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2748 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2749 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2750 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2751 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2752 MII_TG3_CTRL_ENABLE_AS_MASTER);
2753 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2754 } else {
2755 tg3_writephy(tp, MII_TG3_CTRL, 0);
2756 }
2757 } else {
ba4d07a8
MC		 2758 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2759 new_adv |= ADVERTISE_CSMA;
2760
1da177e4
LT		 2761 /* Asking for a specific link mode. */
2762 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2763 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2764
2765 if (tp->link_config.duplex == DUPLEX_FULL)
2766 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2767 else
2768 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2769 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2770 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2771 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2772 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2773 } else {
1da177e4
LT		 2774 if (tp->link_config.speed == SPEED_100) {
2775 if (tp->link_config.duplex == DUPLEX_FULL)
2776 new_adv |= ADVERTISE_100FULL;
2777 else
2778 new_adv |= ADVERTISE_100HALF;
2779 } else {
2780 if (tp->link_config.duplex == DUPLEX_FULL)
2781 new_adv |= ADVERTISE_10FULL;
2782 else
2783 new_adv |= ADVERTISE_10HALF;
2784 }
2785 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2786
2787 new_adv = 0;
1da177e4 2788 }
ba4d07a8
MC		 2789
2790 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2791 }
2792
2793 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2794 tp->link_config.speed != SPEED_INVALID) {
2795 u32 bmcr, orig_bmcr;
2796
2797 tp->link_config.active_speed = tp->link_config.speed;
2798 tp->link_config.active_duplex = tp->link_config.duplex;
2799
2800 bmcr = 0;
2801 switch (tp->link_config.speed) {
2802 default:
2803 case SPEED_10:
2804 break;
2805
2806 case SPEED_100:
2807 bmcr |= BMCR_SPEED100;
2808 break;
2809
2810 case SPEED_1000:
2811 bmcr |= TG3_BMCR_SPEED1000;
2812 break;
855e1111 2813 }
1da177e4
LT		 2814
2815 if (tp->link_config.duplex == DUPLEX_FULL)
2816 bmcr |= BMCR_FULLDPLX;
2817
2818 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2819 (bmcr != orig_bmcr)) {
2820 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2821 for (i = 0; i < 1500; i++) {
2822 u32 tmp;
2823
2824 udelay(10);
2825 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2826 tg3_readphy(tp, MII_BMSR, &tmp))
2827 continue;
2828 if (!(tmp & BMSR_LSTATUS)) {
2829 udelay(40);
2830 break;
2831 }
2832 }
2833 tg3_writephy(tp, MII_BMCR, bmcr);
2834 udelay(40);
2835 }
2836 } else {
2837 tg3_writephy(tp, MII_BMCR,
2838 BMCR_ANENABLE | BMCR_ANRESTART);
2839 }
2840}
2841
2842static int tg3_init_5401phy_dsp(struct tg3 *tp)
2843{
2844 int err;
2845
2846 /* Turn off tap power management. */
2847 /* Set Extended packet length bit */
2848 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2849
2850 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2851 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2852
2853 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2854 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2855
2856 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2857 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2858
2859 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2860 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2861
2862 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2863 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2864
2865 udelay(40);
2866
2867 return err;
2868}
2869
3600d918 2870static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2871{
3600d918
MC		 2872 u32 adv_reg, all_mask = 0;
2873
2874 if (mask & ADVERTISED_10baseT_Half)
2875 all_mask |= ADVERTISE_10HALF;
2876 if (mask & ADVERTISED_10baseT_Full)
2877 all_mask |= ADVERTISE_10FULL;
2878 if (mask & ADVERTISED_100baseT_Half)
2879 all_mask |= ADVERTISE_100HALF;
2880 if (mask & ADVERTISED_100baseT_Full)
2881 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2882
2883 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2884 return 0;
2885
1da177e4
LT		 2886 if ((adv_reg & all_mask) != all_mask)
2887 return 0;
2888 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2889 u32 tg3_ctrl;
2890
3600d918
MC		 2891 all_mask = 0;
2892 if (mask & ADVERTISED_1000baseT_Half)
2893 all_mask |= ADVERTISE_1000HALF;
2894 if (mask & ADVERTISED_1000baseT_Full)
2895 all_mask |= ADVERTISE_1000FULL;
2896
1da177e4
LT		 2897 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2898 return 0;
2899
1da177e4
LT		 2900 if ((tg3_ctrl & all_mask) != all_mask)
2901 return 0;
2902 }
2903 return 1;
2904}
2905
ef167e27
MC		 2906static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2907{
2908 u32 curadv, reqadv;
2909
2910 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2911 return 1;
2912
2913 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2914 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2915
2916 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2917 if (curadv != reqadv)
2918 return 0;
2919
2920 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2921 tg3_readphy(tp, MII_LPA, rmtadv);
2922 } else {
2923 /* Reprogram the advertisement register, even if it
2924 * does not affect the current link. If the link
2925 * gets renegotiated in the future, we can save an
2926 * additional renegotiation cycle by advertising
2927 * it correctly in the first place.
2928 */
2929 if (curadv != reqadv) {
2930 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2931 ADVERTISE_PAUSE_ASYM);
2932 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2933 }
2934 }
2935
2936 return 1;
2937}
2938
1da177e4
LT		 2939static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2940{
2941 int current_link_up;
2942 u32 bmsr, dummy;
ef167e27 2943 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2944 u16 current_speed;
2945 u8 current_duplex;
2946 int i, err;
2947
2948 tw32(MAC_EVENT, 0);
2949
2950 tw32_f(MAC_STATUS,
2951 (MAC_STATUS_SYNC_CHANGED |
2952 MAC_STATUS_CFG_CHANGED |
2953 MAC_STATUS_MI_COMPLETION |
2954 MAC_STATUS_LNKSTATE_CHANGED));
2955 udelay(40);
2956
8ef21428
MC		 2957 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2958 tw32_f(MAC_MI_MODE,
2959 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2960 udelay(80);
2961 }
1da177e4
LT		 2962
2963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2964
2965 /* Some third-party PHYs need to be reset on link going
2966 * down.
2967 */
2968 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2971 netif_carrier_ok(tp->dev)) {
2972 tg3_readphy(tp, MII_BMSR, &bmsr);
2973 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2974 !(bmsr & BMSR_LSTATUS))
2975 force_reset = 1;
2976 }
2977 if (force_reset)
2978 tg3_phy_reset(tp);
2979
2980 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2981 tg3_readphy(tp, MII_BMSR, &bmsr);
2982 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2983 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2984 bmsr = 0;
2985
2986 if (!(bmsr & BMSR_LSTATUS)) {
2987 err = tg3_init_5401phy_dsp(tp);
2988 if (err)
2989 return err;
2990
2991 tg3_readphy(tp, MII_BMSR, &bmsr);
2992 for (i = 0; i < 1000; i++) {
2993 udelay(10);
2994 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2995 (bmsr & BMSR_LSTATUS)) {
2996 udelay(40);
2997 break;
2998 }
2999 }
3000
3001 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3002 !(bmsr & BMSR_LSTATUS) &&
3003 tp->link_config.active_speed == SPEED_1000) {
3004 err = tg3_phy_reset(tp);
3005 if (!err)
3006 err = tg3_init_5401phy_dsp(tp);
3007 if (err)
3008 return err;
3009 }
3010 }
3011 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3012 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3013 /* 5701 {A0,B0} CRC bug workaround */
3014 tg3_writephy(tp, 0x15, 0x0a75);
3015 tg3_writephy(tp, 0x1c, 0x8c68);
3016 tg3_writephy(tp, 0x1c, 0x8d68);
3017 tg3_writephy(tp, 0x1c, 0x8c68);
3018 }
3019
3020 /* Clear pending interrupts... */
3021 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3022 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3023
3024 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3025 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3026 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3027 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3028
3029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3031 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3032 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3033 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3034 else
3035 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3036 }
3037
3038 current_link_up = 0;
3039 current_speed = SPEED_INVALID;
3040 current_duplex = DUPLEX_INVALID;
3041
3042 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3043 u32 val;
3044
3045 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3046 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3047 if (!(val & (1 << 10))) {
3048 val |= (1 << 10);
3049 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3050 goto relink;
3051 }
3052 }
3053
3054 bmsr = 0;
3055 for (i = 0; i < 100; i++) {
3056 tg3_readphy(tp, MII_BMSR, &bmsr);
3057 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3058 (bmsr & BMSR_LSTATUS))
3059 break;
3060 udelay(40);
3061 }
3062
3063 if (bmsr & BMSR_LSTATUS) {
3064 u32 aux_stat, bmcr;
3065
3066 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3067 for (i = 0; i < 2000; i++) {
3068 udelay(10);
3069 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3070 aux_stat)
3071 break;
3072 }
3073
3074 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3075 &current_speed,
3076 &current_duplex);
3077
3078 bmcr = 0;
3079 for (i = 0; i < 200; i++) {
3080 tg3_readphy(tp, MII_BMCR, &bmcr);
3081 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3082 continue;
3083 if (bmcr && bmcr != 0x7fff)
3084 break;
3085 udelay(10);
3086 }
3087
ef167e27
MC		 3088 lcl_adv = 0;
3089 rmt_adv = 0;
1da177e4 3090
ef167e27
MC		 3091 tp->link_config.active_speed = current_speed;
3092 tp->link_config.active_duplex = current_duplex;
3093
3094 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3095 if ((bmcr & BMCR_ANENABLE) &&
3096 tg3_copper_is_advertising_all(tp,
3097 tp->link_config.advertising)) {
3098 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3099 &rmt_adv))
3100 current_link_up = 1;
1da177e4
LT		 3101 }
3102 } else {
3103 if (!(bmcr & BMCR_ANENABLE) &&
3104 tp->link_config.speed == current_speed &&
ef167e27
MC		 3105 tp->link_config.duplex == current_duplex &&
3106 tp->link_config.flowctrl ==
3107 tp->link_config.active_flowctrl) {
1da177e4 3108 current_link_up = 1;
1da177e4
LT		 3109 }
3110 }
3111
ef167e27
MC		 3112 if (current_link_up == 1 &&
3113 tp->link_config.active_duplex == DUPLEX_FULL)
3114 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3115 }
3116
1da177e4 3117relink:
6921d201 3118 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3119 u32 tmp;
3120
3121 tg3_phy_copper_begin(tp);
3122
3123 tg3_readphy(tp, MII_BMSR, &tmp);
3124 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3125 (tmp & BMSR_LSTATUS))
3126 current_link_up = 1;
3127 }
3128
3129 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3130 if (current_link_up == 1) {
3131 if (tp->link_config.active_speed == SPEED_100 ||
3132 tp->link_config.active_speed == SPEED_10)
3133 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3134 else
3135 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3136 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3137 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3138 else
1da177e4
LT		 3139 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3140
3141 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3142 if (tp->link_config.active_duplex == DUPLEX_HALF)
3143 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3144
1da177e4 3145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3146 if (current_link_up == 1 &&
3147 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3148 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3149 else
3150 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3151 }
3152
3153 /* ??? Without this setting Netgear GA302T PHY does not
3154 * ??? send/receive packets...
3155 */
3156 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3157 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3158 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3159 tw32_f(MAC_MI_MODE, tp->mi_mode);
3160 udelay(80);
3161 }
3162
3163 tw32_f(MAC_MODE, tp->mac_mode);
3164 udelay(40);
3165
3166 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3167 /* Polled via timer. */
3168 tw32_f(MAC_EVENT, 0);
3169 } else {
3170 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3171 }
3172 udelay(40);
3173
3174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3175 current_link_up == 1 &&
3176 tp->link_config.active_speed == SPEED_1000 &&
3177 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3178 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3179 udelay(120);
3180 tw32_f(MAC_STATUS,
3181 (MAC_STATUS_SYNC_CHANGED |
3182 MAC_STATUS_CFG_CHANGED));
3183 udelay(40);
3184 tg3_write_mem(tp,
3185 NIC_SRAM_FIRMWARE_MBOX,
3186 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3187 }
3188
5e7dfd0f
MC		 3189 /* Prevent send BD corruption. */
3190 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3191 u16 oldlnkctl, newlnkctl;
3192
3193 pci_read_config_word(tp->pdev,
3194 tp->pcie_cap + PCI_EXP_LNKCTL,
3195 &oldlnkctl);
3196 if (tp->link_config.active_speed == SPEED_100 ||
3197 tp->link_config.active_speed == SPEED_10)
3198 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3199 else
3200 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3201 if (newlnkctl != oldlnkctl)
3202 pci_write_config_word(tp->pdev,
3203 tp->pcie_cap + PCI_EXP_LNKCTL,
3204 newlnkctl);
255ca311
MC		 3205 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3206 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3207 if (tp->link_config.active_speed == SPEED_100 ||
3208 tp->link_config.active_speed == SPEED_10)
3209 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3210 else
3211 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3212 if (newreg != oldreg)
3213 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3214 }
3215
1da177e4
LT		 3216 if (current_link_up != netif_carrier_ok(tp->dev)) {
3217 if (current_link_up)
3218 netif_carrier_on(tp->dev);
3219 else
3220 netif_carrier_off(tp->dev);
3221 tg3_link_report(tp);
3222 }
3223
3224 return 0;
3225}
3226
3227struct tg3_fiber_aneginfo {
3228 int state;
3229#define ANEG_STATE_UNKNOWN 0
3230#define ANEG_STATE_AN_ENABLE 1
3231#define ANEG_STATE_RESTART_INIT 2
3232#define ANEG_STATE_RESTART 3
3233#define ANEG_STATE_DISABLE_LINK_OK 4
3234#define ANEG_STATE_ABILITY_DETECT_INIT 5
3235#define ANEG_STATE_ABILITY_DETECT 6
3236#define ANEG_STATE_ACK_DETECT_INIT 7
3237#define ANEG_STATE_ACK_DETECT 8
3238#define ANEG_STATE_COMPLETE_ACK_INIT 9
3239#define ANEG_STATE_COMPLETE_ACK 10
3240#define ANEG_STATE_IDLE_DETECT_INIT 11
3241#define ANEG_STATE_IDLE_DETECT 12
3242#define ANEG_STATE_LINK_OK 13
3243#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3244#define ANEG_STATE_NEXT_PAGE_WAIT 15
3245
3246 u32 flags;
3247#define MR_AN_ENABLE 0x00000001
3248#define MR_RESTART_AN 0x00000002
3249#define MR_AN_COMPLETE 0x00000004
3250#define MR_PAGE_RX 0x00000008
3251#define MR_NP_LOADED 0x00000010
3252#define MR_TOGGLE_TX 0x00000020
3253#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3254#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3255#define MR_LP_ADV_SYM_PAUSE 0x00000100
3256#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3257#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3258#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3259#define MR_LP_ADV_NEXT_PAGE 0x00001000
3260#define MR_TOGGLE_RX 0x00002000
3261#define MR_NP_RX 0x00004000
3262
3263#define MR_LINK_OK 0x80000000
3264
3265 unsigned long link_time, cur_time;
3266
3267 u32 ability_match_cfg;
3268 int ability_match_count;
3269
3270 char ability_match, idle_match, ack_match;
3271
3272 u32 txconfig, rxconfig;
3273#define ANEG_CFG_NP 0x00000080
3274#define ANEG_CFG_ACK 0x00000040
3275#define ANEG_CFG_RF2 0x00000020
3276#define ANEG_CFG_RF1 0x00000010
3277#define ANEG_CFG_PS2 0x00000001
3278#define ANEG_CFG_PS1 0x00008000
3279#define ANEG_CFG_HD 0x00004000
3280#define ANEG_CFG_FD 0x00002000
3281#define ANEG_CFG_INVAL 0x00001f06
3282
3283};
3284#define ANEG_OK 0
3285#define ANEG_DONE 1
3286#define ANEG_TIMER_ENAB 2
3287#define ANEG_FAILED -1
3288
3289#define ANEG_STATE_SETTLE_TIME 10000
3290
3291static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3292 struct tg3_fiber_aneginfo *ap)
3293{
5be73b47 3294 u16 flowctrl;
1da177e4
LT		 3295 unsigned long delta;
3296 u32 rx_cfg_reg;
3297 int ret;
3298
3299 if (ap->state == ANEG_STATE_UNKNOWN) {
3300 ap->rxconfig = 0;
3301 ap->link_time = 0;
3302 ap->cur_time = 0;
3303 ap->ability_match_cfg = 0;
3304 ap->ability_match_count = 0;
3305 ap->ability_match = 0;
3306 ap->idle_match = 0;
3307 ap->ack_match = 0;
3308 }
3309 ap->cur_time++;
3310
3311 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3312 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3313
3314 if (rx_cfg_reg != ap->ability_match_cfg) {
3315 ap->ability_match_cfg = rx_cfg_reg;
3316 ap->ability_match = 0;
3317 ap->ability_match_count = 0;
3318 } else {
3319 if (++ap->ability_match_count > 1) {
3320 ap->ability_match = 1;
3321 ap->ability_match_cfg = rx_cfg_reg;
3322 }
3323 }
3324 if (rx_cfg_reg & ANEG_CFG_ACK)
3325 ap->ack_match = 1;
3326 else
3327 ap->ack_match = 0;
3328
3329 ap->idle_match = 0;
3330 } else {
3331 ap->idle_match = 1;
3332 ap->ability_match_cfg = 0;
3333 ap->ability_match_count = 0;
3334 ap->ability_match = 0;
3335 ap->ack_match = 0;
3336
3337 rx_cfg_reg = 0;
3338 }
3339
3340 ap->rxconfig = rx_cfg_reg;
3341 ret = ANEG_OK;
3342
3343 switch(ap->state) {
3344 case ANEG_STATE_UNKNOWN:
3345 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3346 ap->state = ANEG_STATE_AN_ENABLE;
3347
3348 /* fallthru */
3349 case ANEG_STATE_AN_ENABLE:
3350 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3351 if (ap->flags & MR_AN_ENABLE) {
3352 ap->link_time = 0;
3353 ap->cur_time = 0;
3354 ap->ability_match_cfg = 0;
3355 ap->ability_match_count = 0;
3356 ap->ability_match = 0;
3357 ap->idle_match = 0;
3358 ap->ack_match = 0;
3359
3360 ap->state = ANEG_STATE_RESTART_INIT;
3361 } else {
3362 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3363 }
3364 break;
3365
3366 case ANEG_STATE_RESTART_INIT:
3367 ap->link_time = ap->cur_time;
3368 ap->flags &= ~(MR_NP_LOADED);
3369 ap->txconfig = 0;
3370 tw32(MAC_TX_AUTO_NEG, 0);
3371 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3372 tw32_f(MAC_MODE, tp->mac_mode);
3373 udelay(40);
3374
3375 ret = ANEG_TIMER_ENAB;
3376 ap->state = ANEG_STATE_RESTART;
3377
3378 /* fallthru */
3379 case ANEG_STATE_RESTART:
3380 delta = ap->cur_time - ap->link_time;
3381 if (delta > ANEG_STATE_SETTLE_TIME) {
3382 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3383 } else {
3384 ret = ANEG_TIMER_ENAB;
3385 }
3386 break;
3387
3388 case ANEG_STATE_DISABLE_LINK_OK:
3389 ret = ANEG_DONE;
3390 break;
3391
3392 case ANEG_STATE_ABILITY_DETECT_INIT:
3393 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3394 ap->txconfig = ANEG_CFG_FD;
3395 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3396 if (flowctrl & ADVERTISE_1000XPAUSE)
3397 ap->txconfig |= ANEG_CFG_PS1;
3398 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3399 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3400 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3401 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3402 tw32_f(MAC_MODE, tp->mac_mode);
3403 udelay(40);
3404
3405 ap->state = ANEG_STATE_ABILITY_DETECT;
3406 break;
3407
3408 case ANEG_STATE_ABILITY_DETECT:
3409 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3410 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3411 }
3412 break;
3413
3414 case ANEG_STATE_ACK_DETECT_INIT:
3415 ap->txconfig |= ANEG_CFG_ACK;
3416 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3417 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3418 tw32_f(MAC_MODE, tp->mac_mode);
3419 udelay(40);
3420
3421 ap->state = ANEG_STATE_ACK_DETECT;
3422
3423 /* fallthru */
3424 case ANEG_STATE_ACK_DETECT:
3425 if (ap->ack_match != 0) {
3426 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3427 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3428 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3429 } else {
3430 ap->state = ANEG_STATE_AN_ENABLE;
3431 }
3432 } else if (ap->ability_match != 0 &&
3433 ap->rxconfig == 0) {
3434 ap->state = ANEG_STATE_AN_ENABLE;
3435 }
3436 break;
3437
3438 case ANEG_STATE_COMPLETE_ACK_INIT:
3439 if (ap->rxconfig & ANEG_CFG_INVAL) {
3440 ret = ANEG_FAILED;
3441 break;
3442 }
3443 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3444 MR_LP_ADV_HALF_DUPLEX |
3445 MR_LP_ADV_SYM_PAUSE |
3446 MR_LP_ADV_ASYM_PAUSE |
3447 MR_LP_ADV_REMOTE_FAULT1 |
3448 MR_LP_ADV_REMOTE_FAULT2 |
3449 MR_LP_ADV_NEXT_PAGE |
3450 MR_TOGGLE_RX |
3451 MR_NP_RX);
3452 if (ap->rxconfig & ANEG_CFG_FD)
3453 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3454 if (ap->rxconfig & ANEG_CFG_HD)
3455 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3456 if (ap->rxconfig & ANEG_CFG_PS1)
3457 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3458 if (ap->rxconfig & ANEG_CFG_PS2)
3459 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3460 if (ap->rxconfig & ANEG_CFG_RF1)
3461 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3462 if (ap->rxconfig & ANEG_CFG_RF2)
3463 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3464 if (ap->rxconfig & ANEG_CFG_NP)
3465 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3466
3467 ap->link_time = ap->cur_time;
3468
3469 ap->flags ^= (MR_TOGGLE_TX);
3470 if (ap->rxconfig & 0x0008)
3471 ap->flags |= MR_TOGGLE_RX;
3472 if (ap->rxconfig & ANEG_CFG_NP)
3473 ap->flags |= MR_NP_RX;
3474 ap->flags |= MR_PAGE_RX;
3475
3476 ap->state = ANEG_STATE_COMPLETE_ACK;
3477 ret = ANEG_TIMER_ENAB;
3478 break;
3479
3480 case ANEG_STATE_COMPLETE_ACK:
3481 if (ap->ability_match != 0 &&
3482 ap->rxconfig == 0) {
3483 ap->state = ANEG_STATE_AN_ENABLE;
3484 break;
3485 }
3486 delta = ap->cur_time - ap->link_time;
3487 if (delta > ANEG_STATE_SETTLE_TIME) {
3488 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3489 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3490 } else {
3491 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3492 !(ap->flags & MR_NP_RX)) {
3493 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3494 } else {
3495 ret = ANEG_FAILED;
3496 }
3497 }
3498 }
3499 break;
3500
3501 case ANEG_STATE_IDLE_DETECT_INIT:
3502 ap->link_time = ap->cur_time;
3503 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3504 tw32_f(MAC_MODE, tp->mac_mode);
3505 udelay(40);
3506
3507 ap->state = ANEG_STATE_IDLE_DETECT;
3508 ret = ANEG_TIMER_ENAB;
3509 break;
3510
3511 case ANEG_STATE_IDLE_DETECT:
3512 if (ap->ability_match != 0 &&
3513 ap->rxconfig == 0) {
3514 ap->state = ANEG_STATE_AN_ENABLE;
3515 break;
3516 }
3517 delta = ap->cur_time - ap->link_time;
3518 if (delta > ANEG_STATE_SETTLE_TIME) {
3519 /* XXX another gem from the Broadcom driver :( */
3520 ap->state = ANEG_STATE_LINK_OK;
3521 }
3522 break;
3523
3524 case ANEG_STATE_LINK_OK:
3525 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3526 ret = ANEG_DONE;
3527 break;
3528
3529 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3530 /* ??? unimplemented */
3531 break;
3532
3533 case ANEG_STATE_NEXT_PAGE_WAIT:
3534 /* ??? unimplemented */
3535 break;
3536
3537 default:
3538 ret = ANEG_FAILED;
3539 break;
855e1111 3540 }
1da177e4
LT		 3541
3542 return ret;
3543}
3544
5be73b47 3545static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3546{
3547 int res = 0;
3548 struct tg3_fiber_aneginfo aninfo;
3549 int status = ANEG_FAILED;
3550 unsigned int tick;
3551 u32 tmp;
3552
3553 tw32_f(MAC_TX_AUTO_NEG, 0);
3554
3555 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3556 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3557 udelay(40);
3558
3559 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3560 udelay(40);
3561
3562 memset(&aninfo, 0, sizeof(aninfo));
3563 aninfo.flags |= MR_AN_ENABLE;
3564 aninfo.state = ANEG_STATE_UNKNOWN;
3565 aninfo.cur_time = 0;
3566 tick = 0;
3567 while (++tick < 195000) {
3568 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3569 if (status == ANEG_DONE || status == ANEG_FAILED)
3570 break;
3571
3572 udelay(1);
3573 }
3574
3575 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576 tw32_f(MAC_MODE, tp->mac_mode);
3577 udelay(40);
3578
5be73b47
MC		 3579 *txflags = aninfo.txconfig;
3580 *rxflags = aninfo.flags;
1da177e4
LT		 3581
3582 if (status == ANEG_DONE &&
3583 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3584 MR_LP_ADV_FULL_DUPLEX)))
3585 res = 1;
3586
3587 return res;
3588}
3589
3590static void tg3_init_bcm8002(struct tg3 *tp)
3591{
3592 u32 mac_status = tr32(MAC_STATUS);
3593 int i;
3594
3595 /* Reset when initting first time or we have a link. */
3596 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3597 !(mac_status & MAC_STATUS_PCS_SYNCED))
3598 return;
3599
3600 /* Set PLL lock range. */
3601 tg3_writephy(tp, 0x16, 0x8007);
3602
3603 /* SW reset */
3604 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3605
3606 /* Wait for reset to complete. */
3607 /* XXX schedule_timeout() ... */
3608 for (i = 0; i < 500; i++)
3609 udelay(10);
3610
3611 /* Config mode; select PMA/Ch 1 regs. */
3612 tg3_writephy(tp, 0x10, 0x8411);
3613
3614 /* Enable auto-lock and comdet, select txclk for tx. */
3615 tg3_writephy(tp, 0x11, 0x0a10);
3616
3617 tg3_writephy(tp, 0x18, 0x00a0);
3618 tg3_writephy(tp, 0x16, 0x41ff);
3619
3620 /* Assert and deassert POR. */
3621 tg3_writephy(tp, 0x13, 0x0400);
3622 udelay(40);
3623 tg3_writephy(tp, 0x13, 0x0000);
3624
3625 tg3_writephy(tp, 0x11, 0x0a50);
3626 udelay(40);
3627 tg3_writephy(tp, 0x11, 0x0a10);
3628
3629 /* Wait for signal to stabilize */
3630 /* XXX schedule_timeout() ... */
3631 for (i = 0; i < 15000; i++)
3632 udelay(10);
3633
3634 /* Deselect the channel register so we can read the PHYID
3635 * later.
3636 */
3637 tg3_writephy(tp, 0x10, 0x8011);
3638}
3639
3640static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3641{
82cd3d11 3642 u16 flowctrl;
1da177e4
LT		 3643 u32 sg_dig_ctrl, sg_dig_status;
3644 u32 serdes_cfg, expected_sg_dig_ctrl;
3645 int workaround, port_a;
3646 int current_link_up;
3647
3648 serdes_cfg = 0;
3649 expected_sg_dig_ctrl = 0;
3650 workaround = 0;
3651 port_a = 1;
3652 current_link_up = 0;
3653
3654 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3655 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3656 workaround = 1;
3657 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3658 port_a = 0;
3659
3660 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3661 /* preserve bits 20-23 for voltage regulator */
3662 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3663 }
3664
3665 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3666
3667 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3668 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3669 if (workaround) {
3670 u32 val = serdes_cfg;
3671
3672 if (port_a)
3673 val |= 0xc010000;
3674 else
3675 val |= 0x4010000;
3676 tw32_f(MAC_SERDES_CFG, val);
3677 }
c98f6e3b
MC		 3678
3679 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3680 }
3681 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3682 tg3_setup_flow_control(tp, 0, 0);
3683 current_link_up = 1;
3684 }
3685 goto out;
3686 }
3687
3688 /* Want auto-negotiation. */
c98f6e3b 3689 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3690
82cd3d11
MC		 3691 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3692 if (flowctrl & ADVERTISE_1000XPAUSE)
3693 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3694 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3695 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3696
3697 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3698 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3699 tp->serdes_counter &&
3700 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3701 MAC_STATUS_RCVD_CFG)) ==
3702 MAC_STATUS_PCS_SYNCED)) {
3703 tp->serdes_counter--;
3704 current_link_up = 1;
3705 goto out;
3706 }
3707restart_autoneg:
1da177e4
LT		 3708 if (workaround)
3709 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3710 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3711 udelay(5);
3712 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3713
3d3ebe74
MC		 3714 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3715 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3716 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3717 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3718 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3719 mac_status = tr32(MAC_STATUS);
3720
c98f6e3b 3721 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3722 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3723 u32 local_adv = 0, remote_adv = 0;
3724
3725 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3726 local_adv |= ADVERTISE_1000XPAUSE;
3727 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3728 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3729
c98f6e3b 3730 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3731 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3732 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3733 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3734
3735 tg3_setup_flow_control(tp, local_adv, remote_adv);
3736 current_link_up = 1;
3d3ebe74
MC		 3737 tp->serdes_counter = 0;
3738 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3739 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3740 if (tp->serdes_counter)
3741 tp->serdes_counter--;
1da177e4
LT		 3742 else {
3743 if (workaround) {
3744 u32 val = serdes_cfg;
3745
3746 if (port_a)
3747 val |= 0xc010000;
3748 else
3749 val |= 0x4010000;
3750
3751 tw32_f(MAC_SERDES_CFG, val);
3752 }
3753
c98f6e3b 3754 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3755 udelay(40);
3756
3757 /* Link parallel detection - link is up */
3758 /* only if we have PCS_SYNC and not */
3759 /* receiving config code words */
3760 mac_status = tr32(MAC_STATUS);
3761 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3762 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3763 tg3_setup_flow_control(tp, 0, 0);
3764 current_link_up = 1;
3d3ebe74
MC		 3765 tp->tg3_flags2 |=
3766 TG3_FLG2_PARALLEL_DETECT;
3767 tp->serdes_counter =
3768 SERDES_PARALLEL_DET_TIMEOUT;
3769 } else
3770 goto restart_autoneg;
1da177e4
LT		 3771 }
3772 }
3d3ebe74
MC		 3773 } else {
3774 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3775 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3776 }
3777
3778out:
3779 return current_link_up;
3780}
3781
3782static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3783{
3784 int current_link_up = 0;
3785
5cf64b8a 3786 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3787 goto out;
1da177e4
LT		 3788
3789 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3790 u32 txflags, rxflags;
1da177e4 3791 int i;
6aa20a22 3792
5be73b47
MC		 3793 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3794 u32 local_adv = 0, remote_adv = 0;
1da177e4 3795
5be73b47
MC		 3796 if (txflags & ANEG_CFG_PS1)
3797 local_adv |= ADVERTISE_1000XPAUSE;
3798 if (txflags & ANEG_CFG_PS2)
3799 local_adv |= ADVERTISE_1000XPSE_ASYM;
3800
3801 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3802 remote_adv |= LPA_1000XPAUSE;
3803 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3804 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3805
3806 tg3_setup_flow_control(tp, local_adv, remote_adv);
3807
1da177e4
LT		 3808 current_link_up = 1;
3809 }
3810 for (i = 0; i < 30; i++) {
3811 udelay(20);
3812 tw32_f(MAC_STATUS,
3813 (MAC_STATUS_SYNC_CHANGED |
3814 MAC_STATUS_CFG_CHANGED));
3815 udelay(40);
3816 if ((tr32(MAC_STATUS) &
3817 (MAC_STATUS_SYNC_CHANGED |
3818 MAC_STATUS_CFG_CHANGED)) == 0)
3819 break;
3820 }
3821
3822 mac_status = tr32(MAC_STATUS);
3823 if (current_link_up == 0 &&
3824 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3825 !(mac_status & MAC_STATUS_RCVD_CFG))
3826 current_link_up = 1;
3827 } else {
5be73b47
MC		 3828 tg3_setup_flow_control(tp, 0, 0);
3829
1da177e4
LT		 3830 /* Forcing 1000FD link up. */
3831 current_link_up = 1;
1da177e4
LT		 3832
3833 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3834 udelay(40);
e8f3f6ca
MC		 3835
3836 tw32_f(MAC_MODE, tp->mac_mode);
3837 udelay(40);
1da177e4
LT		 3838 }
3839
3840out:
3841 return current_link_up;
3842}
3843
3844static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3845{
3846 u32 orig_pause_cfg;
3847 u16 orig_active_speed;
3848 u8 orig_active_duplex;
3849 u32 mac_status;
3850 int current_link_up;
3851 int i;
3852
8d018621 3853 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3854 orig_active_speed = tp->link_config.active_speed;
3855 orig_active_duplex = tp->link_config.active_duplex;
3856
3857 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3858 netif_carrier_ok(tp->dev) &&
3859 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3860 mac_status = tr32(MAC_STATUS);
3861 mac_status &= (MAC_STATUS_PCS_SYNCED |
3862 MAC_STATUS_SIGNAL_DET |
3863 MAC_STATUS_CFG_CHANGED |
3864 MAC_STATUS_RCVD_CFG);
3865 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3866 MAC_STATUS_SIGNAL_DET)) {
3867 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3868 MAC_STATUS_CFG_CHANGED));
3869 return 0;
3870 }
3871 }
3872
3873 tw32_f(MAC_TX_AUTO_NEG, 0);
3874
3875 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3876 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3877 tw32_f(MAC_MODE, tp->mac_mode);
3878 udelay(40);
3879
3880 if (tp->phy_id == PHY_ID_BCM8002)
3881 tg3_init_bcm8002(tp);
3882
3883 /* Enable link change event even when serdes polling. */
3884 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3885 udelay(40);
3886
3887 current_link_up = 0;
3888 mac_status = tr32(MAC_STATUS);
3889
3890 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3891 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3892 else
3893 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3894
1da177e4
LT		 3895 tp->hw_status->status =
3896 (SD_STATUS_UPDATED |
3897 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3898
3899 for (i = 0; i < 100; i++) {
3900 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3901 MAC_STATUS_CFG_CHANGED));
3902 udelay(5);
3903 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3904 MAC_STATUS_CFG_CHANGED |
3905 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3906 break;
3907 }
3908
3909 mac_status = tr32(MAC_STATUS);
3910 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3911 current_link_up = 0;
3d3ebe74
MC		 3912 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3913 tp->serdes_counter == 0) {
1da177e4
LT		 3914 tw32_f(MAC_MODE, (tp->mac_mode |
3915 MAC_MODE_SEND_CONFIGS));
3916 udelay(1);
3917 tw32_f(MAC_MODE, tp->mac_mode);
3918 }
3919 }
3920
3921 if (current_link_up == 1) {
3922 tp->link_config.active_speed = SPEED_1000;
3923 tp->link_config.active_duplex = DUPLEX_FULL;
3924 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3925 LED_CTRL_LNKLED_OVERRIDE |
3926 LED_CTRL_1000MBPS_ON));
3927 } else {
3928 tp->link_config.active_speed = SPEED_INVALID;
3929 tp->link_config.active_duplex = DUPLEX_INVALID;
3930 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3931 LED_CTRL_LNKLED_OVERRIDE |
3932 LED_CTRL_TRAFFIC_OVERRIDE));
3933 }
3934
3935 if (current_link_up != netif_carrier_ok(tp->dev)) {
3936 if (current_link_up)
3937 netif_carrier_on(tp->dev);
3938 else
3939 netif_carrier_off(tp->dev);
3940 tg3_link_report(tp);
3941 } else {
8d018621 3942 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3943 if (orig_pause_cfg != now_pause_cfg ||
3944 orig_active_speed != tp->link_config.active_speed ||
3945 orig_active_duplex != tp->link_config.active_duplex)
3946 tg3_link_report(tp);
3947 }
3948
3949 return 0;
3950}
3951
747e8f8b
MC		 3952static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3953{
3954 int current_link_up, err = 0;
3955 u32 bmsr, bmcr;
3956 u16 current_speed;
3957 u8 current_duplex;
ef167e27 3958 u32 local_adv, remote_adv;
747e8f8b
MC		 3959
3960 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3961 tw32_f(MAC_MODE, tp->mac_mode);
3962 udelay(40);
3963
3964 tw32(MAC_EVENT, 0);
3965
3966 tw32_f(MAC_STATUS,
3967 (MAC_STATUS_SYNC_CHANGED |
3968 MAC_STATUS_CFG_CHANGED |
3969 MAC_STATUS_MI_COMPLETION |
3970 MAC_STATUS_LNKSTATE_CHANGED));
3971 udelay(40);
3972
3973 if (force_reset)
3974 tg3_phy_reset(tp);
3975
3976 current_link_up = 0;
3977 current_speed = SPEED_INVALID;
3978 current_duplex = DUPLEX_INVALID;
3979
3980 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3981 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3983 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3984 bmsr |= BMSR_LSTATUS;
3985 else
3986 bmsr &= ~BMSR_LSTATUS;
3987 }
747e8f8b
MC		 3988
3989 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3990
3991 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3992 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3993 /* do nothing, just check for link up at the end */
3994 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3995 u32 adv, new_adv;
3996
3997 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3998 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3999 ADVERTISE_1000XPAUSE |
4000 ADVERTISE_1000XPSE_ASYM |
4001 ADVERTISE_SLCT);
4002
ba4d07a8 4003 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4004
4005 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4006 new_adv |= ADVERTISE_1000XHALF;
4007 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4008 new_adv |= ADVERTISE_1000XFULL;
4009
4010 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4011 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4012 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4013 tg3_writephy(tp, MII_BMCR, bmcr);
4014
4015 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4016 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4017 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4018
4019 return err;
4020 }
4021 } else {
4022 u32 new_bmcr;
4023
4024 bmcr &= ~BMCR_SPEED1000;
4025 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4026
4027 if (tp->link_config.duplex == DUPLEX_FULL)
4028 new_bmcr |= BMCR_FULLDPLX;
4029
4030 if (new_bmcr != bmcr) {
4031 /* BMCR_SPEED1000 is a reserved bit that needs
4032 * to be set on write.
4033 */
4034 new_bmcr |= BMCR_SPEED1000;
4035
4036 /* Force a linkdown */
4037 if (netif_carrier_ok(tp->dev)) {
4038 u32 adv;
4039
4040 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4041 adv &= ~(ADVERTISE_1000XFULL |
4042 ADVERTISE_1000XHALF |
4043 ADVERTISE_SLCT);
4044 tg3_writephy(tp, MII_ADVERTISE, adv);
4045 tg3_writephy(tp, MII_BMCR, bmcr |
4046 BMCR_ANRESTART |
4047 BMCR_ANENABLE);
4048 udelay(10);
4049 netif_carrier_off(tp->dev);
4050 }
4051 tg3_writephy(tp, MII_BMCR, new_bmcr);
4052 bmcr = new_bmcr;
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4055 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4056 ASIC_REV_5714) {
4057 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4058 bmsr |= BMSR_LSTATUS;
4059 else
4060 bmsr &= ~BMSR_LSTATUS;
4061 }
747e8f8b
MC		 4062 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4063 }
4064 }
4065
4066 if (bmsr & BMSR_LSTATUS) {
4067 current_speed = SPEED_1000;
4068 current_link_up = 1;
4069 if (bmcr & BMCR_FULLDPLX)
4070 current_duplex = DUPLEX_FULL;
4071 else
4072 current_duplex = DUPLEX_HALF;
4073
ef167e27
MC		 4074 local_adv = 0;
4075 remote_adv = 0;
4076
747e8f8b 4077 if (bmcr & BMCR_ANENABLE) {
ef167e27 4078 u32 common;
747e8f8b
MC		 4079
4080 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4081 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4082 common = local_adv & remote_adv;
4083 if (common & (ADVERTISE_1000XHALF |
4084 ADVERTISE_1000XFULL)) {
4085 if (common & ADVERTISE_1000XFULL)
4086 current_duplex = DUPLEX_FULL;
4087 else
4088 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4089 }
4090 else
4091 current_link_up = 0;
4092 }
4093 }
4094
ef167e27
MC		 4095 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4096 tg3_setup_flow_control(tp, local_adv, remote_adv);
4097
747e8f8b
MC		 4098 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4099 if (tp->link_config.active_duplex == DUPLEX_HALF)
4100 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4101
4102 tw32_f(MAC_MODE, tp->mac_mode);
4103 udelay(40);
4104
4105 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4106
4107 tp->link_config.active_speed = current_speed;
4108 tp->link_config.active_duplex = current_duplex;
4109
4110 if (current_link_up != netif_carrier_ok(tp->dev)) {
4111 if (current_link_up)
4112 netif_carrier_on(tp->dev);
4113 else {
4114 netif_carrier_off(tp->dev);
4115 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4116 }
4117 tg3_link_report(tp);
4118 }
4119 return err;
4120}
4121
4122static void tg3_serdes_parallel_detect(struct tg3 *tp)
4123{
3d3ebe74 4124 if (tp->serdes_counter) {
747e8f8b 4125 /* Give autoneg time to complete. */
3d3ebe74 4126 tp->serdes_counter--;
747e8f8b
MC		 4127 return;
4128 }
4129 if (!netif_carrier_ok(tp->dev) &&
4130 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4131 u32 bmcr;
4132
4133 tg3_readphy(tp, MII_BMCR, &bmcr);
4134 if (bmcr & BMCR_ANENABLE) {
4135 u32 phy1, phy2;
4136
4137 /* Select shadow register 0x1f */
4138 tg3_writephy(tp, 0x1c, 0x7c00);
4139 tg3_readphy(tp, 0x1c, &phy1);
4140
4141 /* Select expansion interrupt status register */
4142 tg3_writephy(tp, 0x17, 0x0f01);
4143 tg3_readphy(tp, 0x15, &phy2);
4144 tg3_readphy(tp, 0x15, &phy2);
4145
4146 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4147 /* We have signal detect and not receiving
4148 * config code words, link is up by parallel
4149 * detection.
4150 */
4151
4152 bmcr &= ~BMCR_ANENABLE;
4153 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4154 tg3_writephy(tp, MII_BMCR, bmcr);
4155 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4156 }
4157 }
4158 }
4159 else if (netif_carrier_ok(tp->dev) &&
4160 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4161 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4162 u32 phy2;
4163
4164 /* Select expansion interrupt status register */
4165 tg3_writephy(tp, 0x17, 0x0f01);
4166 tg3_readphy(tp, 0x15, &phy2);
4167 if (phy2 & 0x20) {
4168 u32 bmcr;
4169
4170 /* Config code words received, turn on autoneg. */
4171 tg3_readphy(tp, MII_BMCR, &bmcr);
4172 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4173
4174 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4175
4176 }
4177 }
4178}
4179
1da177e4
LT		 4180static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4181{
4182 int err;
4183
4184 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4185 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4186 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4187 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4188 } else {
4189 err = tg3_setup_copper_phy(tp, force_reset);
4190 }
4191
bcb37f6c 4192 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4193 u32 val, scale;
4194
4195 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4196 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4197 scale = 65;
4198 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4199 scale = 6;
4200 else
4201 scale = 12;
4202
4203 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4204 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4205 tw32(GRC_MISC_CFG, val);
4206 }
4207
1da177e4
LT		 4208 if (tp->link_config.active_speed == SPEED_1000 &&
4209 tp->link_config.active_duplex == DUPLEX_HALF)
4210 tw32(MAC_TX_LENGTHS,
4211 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4212 (6 << TX_LENGTHS_IPG_SHIFT) |
4213 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4214 else
4215 tw32(MAC_TX_LENGTHS,
4216 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4217 (6 << TX_LENGTHS_IPG_SHIFT) |
4218 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4219
4220 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4221 if (netif_carrier_ok(tp->dev)) {
4222 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4223 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4224 } else {
4225 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4226 }
4227 }
4228
8ed5d97e
MC		 4229 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4230 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4231 if (!netif_carrier_ok(tp->dev))
4232 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4233 tp->pwrmgmt_thresh;
4234 else
4235 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4236 tw32(PCIE_PWR_MGMT_THRESH, val);
4237 }
4238
1da177e4
LT		 4239 return err;
4240}
4241
df3e6548
MC		 4242/* This is called whenever we suspect that the system chipset is re-
4243 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4244 * is bogus tx completions. We try to recover by setting the
4245 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4246 * in the workqueue.
4247 */
4248static void tg3_tx_recover(struct tg3 *tp)
4249{
4250 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4251 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4252
4253 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4254 "mapped I/O cycles to the network device, attempting to "
4255 "recover. Please report the problem to the driver maintainer "
4256 "and include system chipset information.\n", tp->dev->name);
4257
4258 spin_lock(&tp->lock);
df3e6548 4259 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4260 spin_unlock(&tp->lock);
4261}
4262
1b2a7205
MC		 4263static inline u32 tg3_tx_avail(struct tg3 *tp)
4264{
4265 smp_mb();
4266 return (tp->tx_pending -
4267 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4268}
4269
1da177e4
LT		 4270/* Tigon3 never reports partial packet sends. So we do not
4271 * need special logic to handle SKBs that have not had all
4272 * of their frags sent yet, like SunGEM does.
4273 */
4274static void tg3_tx(struct tg3 *tp)
4275{
4276 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4277 u32 sw_idx = tp->tx_cons;
4278
4279 while (sw_idx != hw_idx) {
4280 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4281 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4282 int i, tx_bug = 0;
4283
4284 if (unlikely(skb == NULL)) {
4285 tg3_tx_recover(tp);
4286 return;
4287 }
1da177e4 4288
90079ce8 4289 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4290
4291 ri->skb = NULL;
4292
4293 sw_idx = NEXT_TX(sw_idx);
4294
4295 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4296 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4297 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4298 tx_bug = 1;
1da177e4
LT		 4299 sw_idx = NEXT_TX(sw_idx);
4300 }
4301
f47c11ee 4302 dev_kfree_skb(skb);
df3e6548
MC		 4303
4304 if (unlikely(tx_bug)) {
4305 tg3_tx_recover(tp);
4306 return;
4307 }
1da177e4
LT		 4308 }
4309
4310 tp->tx_cons = sw_idx;
4311
1b2a7205
MC		 4312 /* Need to make the tx_cons update visible to tg3_start_xmit()
4313 * before checking for netif_queue_stopped(). Without the
4314 * memory barrier, there is a small possibility that tg3_start_xmit()
4315 * will miss it and cause the queue to be stopped forever.
4316 */
4317 smp_mb();
4318
4319 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4320 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4321 netif_tx_lock(tp->dev);
51b91468 4322 if (netif_queue_stopped(tp->dev) &&
42952231 4323 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4324 netif_wake_queue(tp->dev);
1b2a7205 4325 netif_tx_unlock(tp->dev);
51b91468 4326 }
1da177e4
LT		 4327}
4328
4329/* Returns size of skb allocated or < 0 on error.
4330 *
4331 * We only need to fill in the address because the other members
4332 * of the RX descriptor are invariant, see tg3_init_rings.
4333 *
4334 * Note the purposeful assymetry of cpu vs. chip accesses. For
4335 * posting buffers we only dirty the first cache line of the RX
4336 * descriptor (containing the address). Whereas for the RX status
4337 * buffers the cpu only reads the last cacheline of the RX descriptor
4338 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4339 */
4340static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4341 int src_idx, u32 dest_idx_unmasked)
4342{
4343 struct tg3_rx_buffer_desc *desc;
4344 struct ring_info *map, *src_map;
4345 struct sk_buff *skb;
4346 dma_addr_t mapping;
4347 int skb_size, dest_idx;
4348
4349 src_map = NULL;
4350 switch (opaque_key) {
4351 case RXD_OPAQUE_RING_STD:
4352 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4353 desc = &tp->rx_std[dest_idx];
4354 map = &tp->rx_std_buffers[dest_idx];
4355 if (src_idx >= 0)
4356 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4357 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4358 break;
4359
4360 case RXD_OPAQUE_RING_JUMBO:
4361 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4362 desc = &tp->rx_jumbo[dest_idx];
4363 map = &tp->rx_jumbo_buffers[dest_idx];
4364 if (src_idx >= 0)
4365 src_map = &tp->rx_jumbo_buffers[src_idx];
4366 skb_size = RX_JUMBO_PKT_BUF_SZ;
4367 break;
4368
4369 default:
4370 return -EINVAL;
855e1111 4371 }
1da177e4
LT		 4372
4373 /* Do not overwrite any of the map or rp information
4374 * until we are sure we can commit to a new buffer.
4375 *
4376 * Callers depend upon this behavior and assume that
4377 * we leave everything unchanged if we fail.
4378 */
a20e9c62 4379 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4380 if (skb == NULL)
4381 return -ENOMEM;
4382
1da177e4
LT		 4383 skb_reserve(skb, tp->rx_offset);
4384
4385 mapping = pci_map_single(tp->pdev, skb->data,
4386 skb_size - tp->rx_offset,
4387 PCI_DMA_FROMDEVICE);
4388
4389 map->skb = skb;
4390 pci_unmap_addr_set(map, mapping, mapping);
4391
4392 if (src_map != NULL)
4393 src_map->skb = NULL;
4394
4395 desc->addr_hi = ((u64)mapping >> 32);
4396 desc->addr_lo = ((u64)mapping & 0xffffffff);
4397
4398 return skb_size;
4399}
4400
4401/* We only need to move over in the address because the other
4402 * members of the RX descriptor are invariant. See notes above
4403 * tg3_alloc_rx_skb for full details.
4404 */
4405static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4406 int src_idx, u32 dest_idx_unmasked)
4407{
4408 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4409 struct ring_info *src_map, *dest_map;
4410 int dest_idx;
4411
4412 switch (opaque_key) {
4413 case RXD_OPAQUE_RING_STD:
4414 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4415 dest_desc = &tp->rx_std[dest_idx];
4416 dest_map = &tp->rx_std_buffers[dest_idx];
4417 src_desc = &tp->rx_std[src_idx];
4418 src_map = &tp->rx_std_buffers[src_idx];
4419 break;
4420
4421 case RXD_OPAQUE_RING_JUMBO:
4422 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4423 dest_desc = &tp->rx_jumbo[dest_idx];
4424 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4425 src_desc = &tp->rx_jumbo[src_idx];
4426 src_map = &tp->rx_jumbo_buffers[src_idx];
4427 break;
4428
4429 default:
4430 return;
855e1111 4431 }
1da177e4
LT		 4432
4433 dest_map->skb = src_map->skb;
4434 pci_unmap_addr_set(dest_map, mapping,
4435 pci_unmap_addr(src_map, mapping));
4436 dest_desc->addr_hi = src_desc->addr_hi;
4437 dest_desc->addr_lo = src_desc->addr_lo;
4438
4439 src_map->skb = NULL;
4440}
4441
4442#if TG3_VLAN_TAG_USED
4443static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4444{
1383bdb9 4445 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
1da177e4
LT		 4446}
4447#endif
4448
4449/* The RX ring scheme is composed of multiple rings which post fresh
4450 * buffers to the chip, and one special ring the chip uses to report
4451 * status back to the host.
4452 *
4453 * The special ring reports the status of received packets to the
4454 * host. The chip does not write into the original descriptor the
4455 * RX buffer was obtained from. The chip simply takes the original
4456 * descriptor as provided by the host, updates the status and length
4457 * field, then writes this into the next status ring entry.
4458 *
4459 * Each ring the host uses to post buffers to the chip is described
4460 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4461 * it is first placed into the on-chip ram. When the packet's length
4462 * is known, it walks down the TG3_BDINFO entries to select the ring.
4463 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4464 * which is within the range of the new packet's length is chosen.
4465 *
4466 * The "separate ring for rx status" scheme may sound queer, but it makes
4467 * sense from a cache coherency perspective. If only the host writes
4468 * to the buffer post rings, and only the chip writes to the rx status
4469 * rings, then cache lines never move beyond shared-modified state.
4470 * If both the host and chip were to write into the same ring, cache line
4471 * eviction could occur since both entities want it in an exclusive state.
4472 */
4473static int tg3_rx(struct tg3 *tp, int budget)
4474{
f92905de 4475 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4476 u32 sw_idx = tp->rx_rcb_ptr;
4477 u16 hw_idx;
1da177e4
LT		 4478 int received;
4479
4480 hw_idx = tp->hw_status->idx[0].rx_producer;
4481 /*
4482 * We need to order the read of hw_idx and the read of
4483 * the opaque cookie.
4484 */
4485 rmb();
1da177e4
LT		 4486 work_mask = 0;
4487 received = 0;
4488 while (sw_idx != hw_idx && budget > 0) {
4489 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4490 unsigned int len;
4491 struct sk_buff *skb;
4492 dma_addr_t dma_addr;
4493 u32 opaque_key, desc_idx, *post_ptr;
4494
4495 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4496 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4497 if (opaque_key == RXD_OPAQUE_RING_STD) {
4498 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4499 mapping);
4500 skb = tp->rx_std_buffers[desc_idx].skb;
4501 post_ptr = &tp->rx_std_ptr;
f92905de 4502 rx_std_posted++;
1da177e4
LT		 4503 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4504 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4505 mapping);
4506 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4507 post_ptr = &tp->rx_jumbo_ptr;
4508 }
4509 else {
4510 goto next_pkt_nopost;
4511 }
4512
4513 work_mask |= opaque_key;
4514
4515 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4516 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4517 drop_it:
4518 tg3_recycle_rx(tp, opaque_key,
4519 desc_idx, *post_ptr);
4520 drop_it_no_recycle:
4521 /* Other statistics kept track of by card. */
4522 tp->net_stats.rx_dropped++;
4523 goto next_pkt;
4524 }
4525
ad829268
MC		 4526 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4527 ETH_FCS_LEN;
1da177e4 4528
6aa20a22 4529 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4530 && tp->rx_offset == NET_IP_ALIGN
4531 /* rx_offset will likely not equal NET_IP_ALIGN
4532 * if this is a 5701 card running in PCI-X mode
4533 * [see tg3_get_invariants()]
4534 */
1da177e4
LT		 4535 ) {
4536 int skb_size;
4537
4538 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4539 desc_idx, *post_ptr);
4540 if (skb_size < 0)
4541 goto drop_it;
4542
4543 pci_unmap_single(tp->pdev, dma_addr,
4544 skb_size - tp->rx_offset,
4545 PCI_DMA_FROMDEVICE);
4546
4547 skb_put(skb, len);
4548 } else {
4549 struct sk_buff *copy_skb;
4550
4551 tg3_recycle_rx(tp, opaque_key,
4552 desc_idx, *post_ptr);
4553
ad829268
MC		 4554 copy_skb = netdev_alloc_skb(tp->dev,
4555 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4556 if (copy_skb == NULL)
4557 goto drop_it_no_recycle;
4558
ad829268 4559 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4560 skb_put(copy_skb, len);
4561 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4562 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4563 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4564
4565 /* We'll reuse the original ring buffer. */
4566 skb = copy_skb;
4567 }
4568
4569 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4570 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4571 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4572 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4573 skb->ip_summed = CHECKSUM_UNNECESSARY;
4574 else
4575 skb->ip_summed = CHECKSUM_NONE;
4576
4577 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4578
4579 if (len > (tp->dev->mtu + ETH_HLEN) &&
4580 skb->protocol != htons(ETH_P_8021Q)) {
4581 dev_kfree_skb(skb);
4582 goto next_pkt;
4583 }
4584
1da177e4
LT		 4585#if TG3_VLAN_TAG_USED
4586 if (tp->vlgrp != NULL &&
4587 desc->type_flags & RXD_FLAG_VLAN) {
4588 tg3_vlan_rx(tp, skb,
4589 desc->err_vlan & RXD_VLAN_MASK);
4590 } else
4591#endif
1383bdb9 4592 napi_gro_receive(&tp->napi, skb);
1da177e4 4593
1da177e4
LT		 4594 received++;
4595 budget--;
4596
4597next_pkt:
4598 (*post_ptr)++;
f92905de
MC		 4599
4600 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4601 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4602
4603 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4604 TG3_64BIT_REG_LOW, idx);
4605 work_mask &= ~RXD_OPAQUE_RING_STD;
4606 rx_std_posted = 0;
4607 }
1da177e4 4608next_pkt_nopost:
483ba50b 4609 sw_idx++;
6b31a515 4610 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4611
4612 /* Refresh hw_idx to see if there is new work */
4613 if (sw_idx == hw_idx) {
4614 hw_idx = tp->hw_status->idx[0].rx_producer;
4615 rmb();
4616 }
1da177e4
LT		 4617 }
4618
4619 /* ACK the status ring. */
483ba50b
MC		 4620 tp->rx_rcb_ptr = sw_idx;
4621 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4622
4623 /* Refill RX ring(s). */
4624 if (work_mask & RXD_OPAQUE_RING_STD) {
4625 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4626 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4627 sw_idx);
4628 }
4629 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4630 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4631 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4632 sw_idx);
4633 }
4634 mmiowb();
4635
4636 return received;
4637}
4638
6f535763 4639static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4640{
1da177e4 4641 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4642
1da177e4
LT		 4643 /* handle link change and other phy events */
4644 if (!(tp->tg3_flags &
4645 (TG3_FLAG_USE_LINKCHG_REG |
4646 TG3_FLAG_POLL_SERDES))) {
4647 if (sblk->status & SD_STATUS_LINK_CHG) {
4648 sblk->status = SD_STATUS_UPDATED |
4649 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4650 spin_lock(&tp->lock);
dd477003
MC		 4651 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4652 tw32_f(MAC_STATUS,
4653 (MAC_STATUS_SYNC_CHANGED |
4654 MAC_STATUS_CFG_CHANGED |
4655 MAC_STATUS_MI_COMPLETION |
4656 MAC_STATUS_LNKSTATE_CHANGED));
4657 udelay(40);
4658 } else
4659 tg3_setup_phy(tp, 0);
f47c11ee 4660 spin_unlock(&tp->lock);
1da177e4
LT		 4661 }
4662 }
4663
4664 /* run TX completion thread */
4665 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4666 tg3_tx(tp);
6f535763 4667 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4668 return work_done;
1da177e4
LT		 4669 }
4670
1da177e4
LT		 4671 /* run RX thread, within the bounds set by NAPI.
4672 * All RX "locking" is done by ensuring outside
bea3348e 4673 * code synchronizes with tg3->napi.poll()
1da177e4 4674 */
bea3348e 4675 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4676 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4677
6f535763
DM		 4678 return work_done;
4679}
4680
4681static int tg3_poll(struct napi_struct *napi, int budget)
4682{
4683 struct tg3 *tp = container_of(napi, struct tg3, napi);
4684 int work_done = 0;
4fd7ab59 4685 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4686
4687 while (1) {
4688 work_done = tg3_poll_work(tp, work_done, budget);
4689
4690 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4691 goto tx_recovery;
4692
4693 if (unlikely(work_done >= budget))
4694 break;
4695
4fd7ab59
MC		 4696 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4697 /* tp->last_tag is used in tg3_restart_ints() below
4698 * to tell the hw how much work has been processed,
4699 * so we must read it before checking for more work.
4700 */
4701 tp->last_tag = sblk->status_tag;
624f8e50 4702 tp->last_irq_tag = tp->last_tag;
4fd7ab59
MC		 4703 rmb();
4704 } else
4705 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4706
4fd7ab59 4707 if (likely(!tg3_has_work(tp))) {
288379f0 4708 napi_complete(napi);
6f535763
DM		 4709 tg3_restart_ints(tp);
4710 break;
4711 }
1da177e4
LT		 4712 }
4713
bea3348e 4714 return work_done;
6f535763
DM		 4715
4716tx_recovery:
4fd7ab59 4717 /* work_done is guaranteed to be less than budget. */
288379f0 4718 napi_complete(napi);
6f535763 4719 schedule_work(&tp->reset_task);
4fd7ab59 4720 return work_done;
1da177e4
LT		 4721}
4722
f47c11ee
DM		 4723static void tg3_irq_quiesce(struct tg3 *tp)
4724{
4725 BUG_ON(tp->irq_sync);
4726
4727 tp->irq_sync = 1;
4728 smp_mb();
4729
4730 synchronize_irq(tp->pdev->irq);
4731}
4732
4733static inline int tg3_irq_sync(struct tg3 *tp)
4734{
4735 return tp->irq_sync;
4736}
4737
4738/* Fully shutdown all tg3 driver activity elsewhere in the system.
4739 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4740 * with as well. Most of the time, this is not necessary except when
4741 * shutting down the device.
4742 */
4743static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4744{
46966545 4745 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4746 if (irq_sync)
4747 tg3_irq_quiesce(tp);
f47c11ee
DM		 4748}
4749
4750static inline void tg3_full_unlock(struct tg3 *tp)
4751{
f47c11ee
DM		 4752 spin_unlock_bh(&tp->lock);
4753}
4754
fcfa0a32
MC		 4755/* One-shot MSI handler - Chip automatically disables interrupt
4756 * after sending MSI so driver doesn't have to do it.
4757 */
7d12e780 4758static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4759{
4760 struct net_device *dev = dev_id;
4761 struct tg3 *tp = netdev_priv(dev);
4762
4763 prefetch(tp->hw_status);
4764 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4765
4766 if (likely(!tg3_irq_sync(tp)))
288379f0 4767 napi_schedule(&tp->napi);
fcfa0a32
MC		 4768
4769 return IRQ_HANDLED;
4770}
4771
88b06bc2
MC		 4772/* MSI ISR - No need to check for interrupt sharing and no need to
4773 * flush status block and interrupt mailbox. PCI ordering rules
4774 * guarantee that MSI will arrive after the status block.
4775 */
7d12e780 4776static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4777{
4778 struct net_device *dev = dev_id;
4779 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4780
61487480
MC		 4781 prefetch(tp->hw_status);
4782 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4783 /*
fac9b83e 4784 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4785 * chip-internal interrupt pending events.
fac9b83e 4786 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4787 * NIC to stop sending us irqs, engaging "in-intr-handler"
4788 * event coalescing.
4789 */
4790 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4791 if (likely(!tg3_irq_sync(tp)))
288379f0 4792 napi_schedule(&tp->napi);
61487480 4793
88b06bc2
MC		 4794 return IRQ_RETVAL(1);
4795}
4796
7d12e780 4797static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4798{
4799 struct net_device *dev = dev_id;
4800 struct tg3 *tp = netdev_priv(dev);
4801 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4802 unsigned int handled = 1;
4803
1da177e4
LT		 4804 /* In INTx mode, it is possible for the interrupt to arrive at
4805 * the CPU before the status block posted prior to the interrupt.
4806 * Reading the PCI State register will confirm whether the
4807 * interrupt is ours and will flush the status block.
4808 */
d18edcb2
MC		 4809 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4810 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4811 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4812 handled = 0;
f47c11ee 4813 goto out;
fac9b83e 4814 }
d18edcb2
MC		 4815 }
4816
4817 /*
4818 * Writing any value to intr-mbox-0 clears PCI INTA# and
4819 * chip-internal interrupt pending events.
4820 * Writing non-zero to intr-mbox-0 additional tells the
4821 * NIC to stop sending us irqs, engaging "in-intr-handler"
4822 * event coalescing.
c04cb347
MC		 4823 *
4824 * Flush the mailbox to de-assert the IRQ immediately to prevent
4825 * spurious interrupts. The flush impacts performance but
4826 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4827 */
c04cb347 4828 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4829 if (tg3_irq_sync(tp))
4830 goto out;
4831 sblk->status &= ~SD_STATUS_UPDATED;
4832 if (likely(tg3_has_work(tp))) {
4833 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4834 napi_schedule(&tp->napi);
d18edcb2
MC		 4835 } else {
4836 /* No work, shared interrupt perhaps? re-enable
4837 * interrupts, and flush that PCI write
4838 */
4839 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4840 0x00000000);
fac9b83e 4841 }
f47c11ee 4842out:
fac9b83e
DM		 4843 return IRQ_RETVAL(handled);
4844}
4845
7d12e780 4846static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4847{
4848 struct net_device *dev = dev_id;
4849 struct tg3 *tp = netdev_priv(dev);
4850 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4851 unsigned int handled = 1;
4852
fac9b83e
DM		 4853 /* In INTx mode, it is possible for the interrupt to arrive at
4854 * the CPU before the status block posted prior to the interrupt.
4855 * Reading the PCI State register will confirm whether the
4856 * interrupt is ours and will flush the status block.
4857 */
624f8e50 4858 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
d18edcb2
MC		 4859 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4860 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4861 handled = 0;
f47c11ee 4862 goto out;
1da177e4 4863 }
d18edcb2
MC		 4864 }
4865
4866 /*
4867 * writing any value to intr-mbox-0 clears PCI INTA# and
4868 * chip-internal interrupt pending events.
4869 * writing non-zero to intr-mbox-0 additional tells the
4870 * NIC to stop sending us irqs, engaging "in-intr-handler"
4871 * event coalescing.
c04cb347
MC		 4872 *
4873 * Flush the mailbox to de-assert the IRQ immediately to prevent
4874 * spurious interrupts. The flush impacts performance but
4875 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4876 */
c04cb347 4877 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4878
4879 /*
4880 * In a shared interrupt configuration, sometimes other devices'
4881 * interrupts will scream. We record the current status tag here
4882 * so that the above check can report that the screaming interrupts
4883 * are unhandled. Eventually they will be silenced.
4884 */
4885 tp->last_irq_tag = sblk->status_tag;
4886
d18edcb2
MC		 4887 if (tg3_irq_sync(tp))
4888 goto out;
624f8e50
MC		 4889
4890 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4891
4892 napi_schedule(&tp->napi);
4893
f47c11ee 4894out:
1da177e4
LT		 4895 return IRQ_RETVAL(handled);
4896}
4897
7938109f 4898/* ISR for interrupt test */
7d12e780 4899static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4900{
4901 struct net_device *dev = dev_id;
4902 struct tg3 *tp = netdev_priv(dev);
4903 struct tg3_hw_status *sblk = tp->hw_status;
4904
f9804ddb
MC		 4905 if ((sblk->status & SD_STATUS_UPDATED) ||
4906 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4907 tg3_disable_ints(tp);
7938109f
MC		 4908 return IRQ_RETVAL(1);
4909 }
4910 return IRQ_RETVAL(0);
4911}
4912
8e7a22e3 4913static int tg3_init_hw(struct tg3 *, int);
944d980e 4914static int tg3_halt(struct tg3 *, int, int);
1da177e4 4915
b9ec6c1b
MC		 4916/* Restart hardware after configuration changes, self-test, etc.
4917 * Invoked with tp->lock held.
4918 */
4919static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4920 __releases(tp->lock)
4921 __acquires(tp->lock)
b9ec6c1b
MC		 4922{
4923 int err;
4924
4925 err = tg3_init_hw(tp, reset_phy);
4926 if (err) {
4927 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4928 "aborting.\n", tp->dev->name);
4929 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4930 tg3_full_unlock(tp);
4931 del_timer_sync(&tp->timer);
4932 tp->irq_sync = 0;
bea3348e 4933 napi_enable(&tp->napi);
b9ec6c1b
MC		 4934 dev_close(tp->dev);
4935 tg3_full_lock(tp, 0);
4936 }
4937 return err;
4938}
4939
1da177e4
LT		 4940#ifdef CONFIG_NET_POLL_CONTROLLER
4941static void tg3_poll_controller(struct net_device *dev)
4942{
88b06bc2
MC		 4943 struct tg3 *tp = netdev_priv(dev);
4944
7d12e780 4945 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4946}
4947#endif
4948
c4028958 4949static void tg3_reset_task(struct work_struct *work)
1da177e4 4950{
c4028958 4951 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4952 int err;
1da177e4
LT		 4953 unsigned int restart_timer;
4954
7faa006f 4955 tg3_full_lock(tp, 0);
7faa006f
MC		 4956
4957 if (!netif_running(tp->dev)) {
7faa006f
MC		 4958 tg3_full_unlock(tp);
4959 return;
4960 }
4961
4962 tg3_full_unlock(tp);
4963
b02fd9e3
MC		 4964 tg3_phy_stop(tp);
4965
1da177e4
LT		 4966 tg3_netif_stop(tp);
4967
f47c11ee 4968 tg3_full_lock(tp, 1);
1da177e4
LT		 4969
4970 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4971 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4972
df3e6548
MC		 4973 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4974 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4975 tp->write32_rx_mbox = tg3_write_flush_reg32;
4976 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4977 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4978 }
4979
944d980e 4980 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4981 err = tg3_init_hw(tp, 1);
4982 if (err)
b9ec6c1b 4983 goto out;
1da177e4
LT		 4984
4985 tg3_netif_start(tp);
4986
1da177e4
LT		 4987 if (restart_timer)
4988 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4989
b9ec6c1b 4990out:
7faa006f 4991 tg3_full_unlock(tp);
b02fd9e3
MC		 4992
4993 if (!err)
4994 tg3_phy_start(tp);
1da177e4
LT		 4995}
4996
b0408751
MC		 4997static void tg3_dump_short_state(struct tg3 *tp)
4998{
4999 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5000 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5001 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5002 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5003}
5004
1da177e4
LT		 5005static void tg3_tx_timeout(struct net_device *dev)
5006{
5007 struct tg3 *tp = netdev_priv(dev);
5008
b0408751 5009 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5010 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5011 dev->name);
b0408751
MC		 5012 tg3_dump_short_state(tp);
5013 }
1da177e4
LT		 5014
5015 schedule_work(&tp->reset_task);
5016}
5017
c58ec932
MC		 5018/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5019static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5020{
5021 u32 base = (u32) mapping & 0xffffffff;
5022
5023 return ((base > 0xffffdcc0) &&
5024 (base + len + 8 < base));
5025}
5026
72f2afb8
MC		 5027/* Test for DMA addresses > 40-bit */
5028static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5029 int len)
5030{
5031#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5032 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5033 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5034 return 0;
5035#else
5036 return 0;
5037#endif
5038}
5039
1da177e4
LT		 5040static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5041
72f2afb8
MC		 5042/* Workaround 4GB and 40-bit hardware DMA bugs. */
5043static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5044 u32 last_plus_one, u32 *start,
5045 u32 base_flags, u32 mss)
1da177e4 5046{
41588ba1 5047 struct sk_buff *new_skb;
c58ec932 5048 dma_addr_t new_addr = 0;
1da177e4 5049 u32 entry = *start;
c58ec932 5050 int i, ret = 0;
1da177e4 5051
41588ba1
MC		 5052 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5053 new_skb = skb_copy(skb, GFP_ATOMIC);
5054 else {
5055 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5056
5057 new_skb = skb_copy_expand(skb,
5058 skb_headroom(skb) + more_headroom,
5059 skb_tailroom(skb), GFP_ATOMIC);
5060 }
5061
1da177e4 5062 if (!new_skb) {
c58ec932
MC		 5063 ret = -1;
5064 } else {
5065 /* New SKB is guaranteed to be linear. */
5066 entry = *start;
90079ce8 5067 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5068 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5069
c58ec932
MC		 5070 /* Make sure new skb does not cross any 4G boundaries.
5071 * Drop the packet if it does.
5072 */
90079ce8 5073 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5074 if (!ret)
5075 skb_dma_unmap(&tp->pdev->dev, new_skb,
5076 DMA_TO_DEVICE);
c58ec932
MC		 5077 ret = -1;
5078 dev_kfree_skb(new_skb);
5079 new_skb = NULL;
5080 } else {
5081 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5082 base_flags, 1 | (mss << 1));
5083 *start = NEXT_TX(entry);
5084 }
1da177e4
LT		 5085 }
5086
1da177e4
LT		 5087 /* Now clean up the sw ring entries. */
5088 i = 0;
5089 while (entry != last_plus_one) {
1da177e4
LT		 5090 if (i == 0) {
5091 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5092 } else {
5093 tp->tx_buffers[entry].skb = NULL;
5094 }
5095 entry = NEXT_TX(entry);
5096 i++;
5097 }
5098
90079ce8 5099 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5100 dev_kfree_skb(skb);
5101
c58ec932 5102 return ret;
1da177e4
LT		 5103}
5104
5105static void tg3_set_txd(struct tg3 *tp, int entry,
5106 dma_addr_t mapping, int len, u32 flags,
5107 u32 mss_and_is_end)
5108{
5109 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5110 int is_end = (mss_and_is_end & 0x1);
5111 u32 mss = (mss_and_is_end >> 1);
5112 u32 vlan_tag = 0;
5113
5114 if (is_end)
5115 flags |= TXD_FLAG_END;
5116 if (flags & TXD_FLAG_VLAN) {
5117 vlan_tag = flags >> 16;
5118 flags &= 0xffff;
5119 }
5120 vlan_tag |= (mss << TXD_MSS_SHIFT);
5121
5122 txd->addr_hi = ((u64) mapping >> 32);
5123 txd->addr_lo = ((u64) mapping & 0xffffffff);
5124 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5125 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5126}
5127
5a6f3074
MC		 5128/* hard_start_xmit for devices that don't have any bugs and
5129 * support TG3_FLG2_HW_TSO_2 only.
5130 */
1da177e4 5131static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5132{
5133 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5134 u32 len, entry, base_flags, mss;
90079ce8
DM		 5135 struct skb_shared_info *sp;
5136 dma_addr_t mapping;
5a6f3074
MC		 5137
5138 len = skb_headlen(skb);
5139
00b70504 5140 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5141 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5142 * interrupt. Furthermore, IRQ processing runs lockless so we have
5143 * no IRQ context deadlocks to worry about either. Rejoice!
5144 */
1b2a7205 5145 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5146 if (!netif_queue_stopped(dev)) {
5147 netif_stop_queue(dev);
5148
5149 /* This is a hard error, log it. */
5150 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5151 "queue awake!\n", dev->name);
5152 }
5a6f3074
MC		 5153 return NETDEV_TX_BUSY;
5154 }
5155
5156 entry = tp->tx_prod;
5157 base_flags = 0;
5a6f3074 5158 mss = 0;
c13e3713 5159 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5160 int tcp_opt_len, ip_tcp_len;
5161
5162 if (skb_header_cloned(skb) &&
5163 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5164 dev_kfree_skb(skb);
5165 goto out_unlock;
5166 }
5167
b0026624
MC		 5168 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5169 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5170 else {
eddc9ec5
ACM		 5171 struct iphdr *iph = ip_hdr(skb);
5172
ab6a5bb6 5173 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5174 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5175
eddc9ec5
ACM		 5176 iph->check = 0;
5177 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5178 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5179 }
5a6f3074
MC		 5180
5181 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5182 TXD_FLAG_CPU_POST_DMA);
5183
aa8223c7 5184 tcp_hdr(skb)->check = 0;
5a6f3074 5185
5a6f3074 5186 }
84fa7933 5187 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5188 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5189#if TG3_VLAN_TAG_USED
5190 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5191 base_flags |= (TXD_FLAG_VLAN |
5192 (vlan_tx_tag_get(skb) << 16));
5193#endif
5194
90079ce8
DM		 5195 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5196 dev_kfree_skb(skb);
5197 goto out_unlock;
5198 }
5199
5200 sp = skb_shinfo(skb);
5201
042a53a9 5202 mapping = sp->dma_head;
5a6f3074
MC		 5203
5204 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5205
5206 tg3_set_txd(tp, entry, mapping, len, base_flags,
5207 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5208
5209 entry = NEXT_TX(entry);
5210
5211 /* Now loop through additional data fragments, and queue them. */
5212 if (skb_shinfo(skb)->nr_frags > 0) {
5213 unsigned int i, last;
5214
5215 last = skb_shinfo(skb)->nr_frags - 1;
5216 for (i = 0; i <= last; i++) {
5217 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5218
5219 len = frag->size;
042a53a9 5220 mapping = sp->dma_maps[i];
5a6f3074 5221 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5222
5223 tg3_set_txd(tp, entry, mapping, len,
5224 base_flags, (i == last) | (mss << 1));
5225
5226 entry = NEXT_TX(entry);
5227 }
5228 }
5229
5230 /* Packets are ready, update Tx producer idx local and on card. */
5231 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5232
5233 tp->tx_prod = entry;
1b2a7205 5234 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5235 netif_stop_queue(dev);
42952231 5236 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5237 netif_wake_queue(tp->dev);
5238 }
5239
5240out_unlock:
cdd0db05 5241 mmiowb();
5a6f3074
MC		 5242
5243 return NETDEV_TX_OK;
5244}
5245
52c0fd83
MC		 5246static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5247
5248/* Use GSO to workaround a rare TSO bug that may be triggered when the
5249 * TSO header is greater than 80 bytes.
5250 */
5251static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5252{
5253 struct sk_buff *segs, *nskb;
5254
5255 /* Estimate the number of fragments in the worst case */
1b2a7205 5256 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5257 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5258 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5259 return NETDEV_TX_BUSY;
5260
5261 netif_wake_queue(tp->dev);
52c0fd83
MC		 5262 }
5263
5264 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5265 if (IS_ERR(segs))
52c0fd83
MC		 5266 goto tg3_tso_bug_end;
5267
5268 do {
5269 nskb = segs;
5270 segs = segs->next;
5271 nskb->next = NULL;
5272 tg3_start_xmit_dma_bug(nskb, tp->dev);
5273 } while (segs);
5274
5275tg3_tso_bug_end:
5276 dev_kfree_skb(skb);
5277
5278 return NETDEV_TX_OK;
5279}
52c0fd83 5280
5a6f3074
MC		 5281/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5282 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5283 */
5284static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5285{
5286 struct tg3 *tp = netdev_priv(dev);
1da177e4 5287 u32 len, entry, base_flags, mss;
90079ce8 5288 struct skb_shared_info *sp;
1da177e4 5289 int would_hit_hwbug;
90079ce8 5290 dma_addr_t mapping;
1da177e4
LT		 5291
5292 len = skb_headlen(skb);
5293
00b70504 5294 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5295 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5296 * interrupt. Furthermore, IRQ processing runs lockless so we have
5297 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5298 */
1b2a7205 5299 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5300 if (!netif_queue_stopped(dev)) {
5301 netif_stop_queue(dev);
5302
5303 /* This is a hard error, log it. */
5304 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5305 "queue awake!\n", dev->name);
5306 }
1da177e4
LT		 5307 return NETDEV_TX_BUSY;
5308 }
5309
5310 entry = tp->tx_prod;
5311 base_flags = 0;
84fa7933 5312 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5313 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5314 mss = 0;
c13e3713 5315 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5316 struct iphdr *iph;
52c0fd83 5317 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5318
5319 if (skb_header_cloned(skb) &&
5320 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5321 dev_kfree_skb(skb);
5322 goto out_unlock;
5323 }
5324
ab6a5bb6 5325 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5326 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5327
52c0fd83
MC		 5328 hdr_len = ip_tcp_len + tcp_opt_len;
5329 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5330 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5331 return (tg3_tso_bug(tp, skb));
5332
1da177e4
LT		 5333 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5334 TXD_FLAG_CPU_POST_DMA);
5335
eddc9ec5
ACM		 5336 iph = ip_hdr(skb);
5337 iph->check = 0;
5338 iph->tot_len = htons(mss + hdr_len);
1da177e4 5339 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5340 tcp_hdr(skb)->check = 0;
1da177e4 5341 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5342 } else
5343 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5344 iph->daddr, 0,
5345 IPPROTO_TCP,
5346 0);
1da177e4
LT		 5347
5348 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5349 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5350 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5351 int tsflags;
5352
eddc9ec5 5353 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5354 mss |= (tsflags << 11);
5355 }
5356 } else {
eddc9ec5 5357 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5358 int tsflags;
5359
eddc9ec5 5360 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5361 base_flags |= tsflags << 12;
5362 }
5363 }
5364 }
1da177e4
LT		 5365#if TG3_VLAN_TAG_USED
5366 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5367 base_flags |= (TXD_FLAG_VLAN |
5368 (vlan_tx_tag_get(skb) << 16));
5369#endif
5370
90079ce8
DM		 5371 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5372 dev_kfree_skb(skb);
5373 goto out_unlock;
5374 }
5375
5376 sp = skb_shinfo(skb);
5377
042a53a9 5378 mapping = sp->dma_head;
1da177e4
LT		 5379
5380 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5381
5382 would_hit_hwbug = 0;
5383
41588ba1
MC		 5384 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5385 would_hit_hwbug = 1;
5386 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5387 would_hit_hwbug = 1;
1da177e4
LT		 5388
5389 tg3_set_txd(tp, entry, mapping, len, base_flags,
5390 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5391
5392 entry = NEXT_TX(entry);
5393
5394 /* Now loop through additional data fragments, and queue them. */
5395 if (skb_shinfo(skb)->nr_frags > 0) {
5396 unsigned int i, last;
5397
5398 last = skb_shinfo(skb)->nr_frags - 1;
5399 for (i = 0; i <= last; i++) {
5400 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5401
5402 len = frag->size;
042a53a9 5403 mapping = sp->dma_maps[i];
1da177e4
LT		 5404
5405 tp->tx_buffers[entry].skb = NULL;
1da177e4 5406
c58ec932
MC		 5407 if (tg3_4g_overflow_test(mapping, len))
5408 would_hit_hwbug = 1;
1da177e4 5409
72f2afb8
MC		 5410 if (tg3_40bit_overflow_test(tp, mapping, len))
5411 would_hit_hwbug = 1;
5412
1da177e4
LT		 5413 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5414 tg3_set_txd(tp, entry, mapping, len,
5415 base_flags, (i == last)|(mss << 1));
5416 else
5417 tg3_set_txd(tp, entry, mapping, len,
5418 base_flags, (i == last));
5419
5420 entry = NEXT_TX(entry);
5421 }
5422 }
5423
5424 if (would_hit_hwbug) {
5425 u32 last_plus_one = entry;
5426 u32 start;
1da177e4 5427
c58ec932
MC		 5428 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5429 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5430
5431 /* If the workaround fails due to memory/mapping
5432 * failure, silently drop this packet.
5433 */
72f2afb8 5434 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5435 &start, base_flags, mss))
1da177e4
LT		 5436 goto out_unlock;
5437
5438 entry = start;
5439 }
5440
5441 /* Packets are ready, update Tx producer idx local and on card. */
5442 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5443
5444 tp->tx_prod = entry;
1b2a7205 5445 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5446 netif_stop_queue(dev);
42952231 5447 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5448 netif_wake_queue(tp->dev);
5449 }
1da177e4
LT		 5450
5451out_unlock:
cdd0db05 5452 mmiowb();
1da177e4
LT		 5453
5454 return NETDEV_TX_OK;
5455}
5456
5457static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5458 int new_mtu)
5459{
5460 dev->mtu = new_mtu;
5461
ef7f5ec0 5462 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5463 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5464 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5465 ethtool_op_set_tso(dev, 0);
5466 }
5467 else
5468 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5469 } else {
a4e2b347 5470 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5471 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5472 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5473 }
1da177e4
LT		 5474}
5475
5476static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5477{
5478 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5479 int err;
1da177e4
LT		 5480
5481 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5482 return -EINVAL;
5483
5484 if (!netif_running(dev)) {
5485 /* We'll just catch it later when the
5486 * device is up'd.
5487 */
5488 tg3_set_mtu(dev, tp, new_mtu);
5489 return 0;
5490 }
5491
b02fd9e3
MC		 5492 tg3_phy_stop(tp);
5493
1da177e4 5494 tg3_netif_stop(tp);
f47c11ee
DM		 5495
5496 tg3_full_lock(tp, 1);
1da177e4 5497
944d980e 5498 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5499
5500 tg3_set_mtu(dev, tp, new_mtu);
5501
b9ec6c1b 5502 err = tg3_restart_hw(tp, 0);
1da177e4 5503
b9ec6c1b
MC		 5504 if (!err)
5505 tg3_netif_start(tp);
1da177e4 5506
f47c11ee 5507 tg3_full_unlock(tp);
1da177e4 5508
b02fd9e3
MC		 5509 if (!err)
5510 tg3_phy_start(tp);
5511
b9ec6c1b 5512 return err;
1da177e4
LT		 5513}
5514
5515/* Free up pending packets in all rx/tx rings.
5516 *
5517 * The chip has been shut down and the driver detached from
5518 * the networking, so no interrupts or new tx packets will
5519 * end up in the driver. tp->{tx,}lock is not held and we are not
5520 * in an interrupt context and thus may sleep.
5521 */
5522static void tg3_free_rings(struct tg3 *tp)
5523{
5524 struct ring_info *rxp;
5525 int i;
5526
5527 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5528 rxp = &tp->rx_std_buffers[i];
5529
5530 if (rxp->skb == NULL)
5531 continue;
5532 pci_unmap_single(tp->pdev,
5533 pci_unmap_addr(rxp, mapping),
7e72aad4 5534 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5535 PCI_DMA_FROMDEVICE);
5536 dev_kfree_skb_any(rxp->skb);
5537 rxp->skb = NULL;
5538 }
5539
5540 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5541 rxp = &tp->rx_jumbo_buffers[i];
5542
5543 if (rxp->skb == NULL)
5544 continue;
5545 pci_unmap_single(tp->pdev,
5546 pci_unmap_addr(rxp, mapping),
5547 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5548 PCI_DMA_FROMDEVICE);
5549 dev_kfree_skb_any(rxp->skb);
5550 rxp->skb = NULL;
5551 }
5552
5553 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5554 struct tx_ring_info *txp;
5555 struct sk_buff *skb;
1da177e4
LT		 5556
5557 txp = &tp->tx_buffers[i];
5558 skb = txp->skb;
5559
5560 if (skb == NULL) {
5561 i++;
5562 continue;
5563 }
5564
90079ce8 5565 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5566
90079ce8 5567 txp->skb = NULL;
1da177e4 5568
90079ce8 5569 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5570
5571 dev_kfree_skb_any(skb);
5572 }
5573}
5574
5575/* Initialize tx/rx rings for packet processing.
5576 *
5577 * The chip has been shut down and the driver detached from
5578 * the networking, so no interrupts or new tx packets will
5579 * end up in the driver. tp->{tx,}lock are held and thus
5580 * we may not sleep.
5581 */
32d8c572 5582static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5583{
5584 u32 i;
5585
5586 /* Free up all the SKBs. */
5587 tg3_free_rings(tp);
5588
5589 /* Zero out all descriptors. */
5590 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5591 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5592 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5593 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5594
7e72aad4 5595 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5596 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5597 (tp->dev->mtu > ETH_DATA_LEN))
5598 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5599
1da177e4
LT		 5600 /* Initialize invariants of the rings, we only set this
5601 * stuff once. This works because the card does not
5602 * write into the rx buffer posting rings.
5603 */
5604 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5605 struct tg3_rx_buffer_desc *rxd;
5606
5607 rxd = &tp->rx_std[i];
7e72aad4 5608 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5609 << RXD_LEN_SHIFT;
5610 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5611 rxd->opaque = (RXD_OPAQUE_RING_STD |
5612 (i << RXD_OPAQUE_INDEX_SHIFT));
5613 }
5614
0f893dc6 5615 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5616 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5617 struct tg3_rx_buffer_desc *rxd;
5618
5619 rxd = &tp->rx_jumbo[i];
5620 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5621 << RXD_LEN_SHIFT;
5622 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5623 RXD_FLAG_JUMBO;
5624 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5625 (i << RXD_OPAQUE_INDEX_SHIFT));
5626 }
5627 }
5628
5629 /* Now allocate fresh SKBs for each rx ring. */
5630 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5631 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5632 printk(KERN_WARNING PFX
5633 "%s: Using a smaller RX standard ring, "
5634 "only %d out of %d buffers were allocated "
5635 "successfully.\n",
5636 tp->dev->name, i, tp->rx_pending);
5637 if (i == 0)
5638 return -ENOMEM;
5639 tp->rx_pending = i;
1da177e4 5640 break;
32d8c572 5641 }
1da177e4
LT		 5642 }
5643
0f893dc6 5644 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5645 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5646 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5647 -1, i) < 0) {
5648 printk(KERN_WARNING PFX
5649 "%s: Using a smaller RX jumbo ring, "
5650 "only %d out of %d buffers were "
5651 "allocated successfully.\n",
5652 tp->dev->name, i, tp->rx_jumbo_pending);
5653 if (i == 0) {
5654 tg3_free_rings(tp);
5655 return -ENOMEM;
5656 }
5657 tp->rx_jumbo_pending = i;
1da177e4 5658 break;
32d8c572 5659 }
1da177e4
LT		 5660 }
5661 }
32d8c572 5662 return 0;
1da177e4
LT		 5663}
5664
5665/*
5666 * Must not be invoked with interrupt sources disabled and
5667 * the hardware shutdown down.
5668 */
5669static void tg3_free_consistent(struct tg3 *tp)
5670{
b4558ea9
JJ		 5671 kfree(tp->rx_std_buffers);
5672 tp->rx_std_buffers = NULL;
1da177e4
LT		 5673 if (tp->rx_std) {
5674 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5675 tp->rx_std, tp->rx_std_mapping);
5676 tp->rx_std = NULL;
5677 }
5678 if (tp->rx_jumbo) {
5679 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5680 tp->rx_jumbo, tp->rx_jumbo_mapping);
5681 tp->rx_jumbo = NULL;
5682 }
5683 if (tp->rx_rcb) {
5684 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5685 tp->rx_rcb, tp->rx_rcb_mapping);
5686 tp->rx_rcb = NULL;
5687 }
5688 if (tp->tx_ring) {
5689 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5690 tp->tx_ring, tp->tx_desc_mapping);
5691 tp->tx_ring = NULL;
5692 }
5693 if (tp->hw_status) {
5694 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5695 tp->hw_status, tp->status_mapping);
5696 tp->hw_status = NULL;
5697 }
5698 if (tp->hw_stats) {
5699 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5700 tp->hw_stats, tp->stats_mapping);
5701 tp->hw_stats = NULL;
5702 }
5703}
5704
5705/*
5706 * Must not be invoked with interrupt sources disabled and
5707 * the hardware shutdown down. Can sleep.
5708 */
5709static int tg3_alloc_consistent(struct tg3 *tp)
5710{
bd2b3343 5711 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5712 (TG3_RX_RING_SIZE +
5713 TG3_RX_JUMBO_RING_SIZE)) +
5714 (sizeof(struct tx_ring_info) *
5715 TG3_TX_RING_SIZE),
5716 GFP_KERNEL);
5717 if (!tp->rx_std_buffers)
5718 return -ENOMEM;
5719
1da177e4
LT		 5720 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5721 tp->tx_buffers = (struct tx_ring_info *)
5722 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5723
5724 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5725 &tp->rx_std_mapping);
5726 if (!tp->rx_std)
5727 goto err_out;
5728
5729 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5730 &tp->rx_jumbo_mapping);
5731
5732 if (!tp->rx_jumbo)
5733 goto err_out;
5734
5735 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5736 &tp->rx_rcb_mapping);
5737 if (!tp->rx_rcb)
5738 goto err_out;
5739
5740 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5741 &tp->tx_desc_mapping);
5742 if (!tp->tx_ring)
5743 goto err_out;
5744
5745 tp->hw_status = pci_alloc_consistent(tp->pdev,
5746 TG3_HW_STATUS_SIZE,
5747 &tp->status_mapping);
5748 if (!tp->hw_status)
5749 goto err_out;
5750
5751 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5752 sizeof(struct tg3_hw_stats),
5753 &tp->stats_mapping);
5754 if (!tp->hw_stats)
5755 goto err_out;
5756
5757 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5758 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5759
5760 return 0;
5761
5762err_out:
5763 tg3_free_consistent(tp);
5764 return -ENOMEM;
5765}
5766
5767#define MAX_WAIT_CNT 1000
5768
5769/* To stop a block, clear the enable bit and poll till it
5770 * clears. tp->lock is held.
5771 */
b3b7d6be 5772static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5773{
5774 unsigned int i;
5775 u32 val;
5776
5777 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5778 switch (ofs) {
5779 case RCVLSC_MODE:
5780 case DMAC_MODE:
5781 case MBFREE_MODE:
5782 case BUFMGR_MODE:
5783 case MEMARB_MODE:
5784 /* We can't enable/disable these bits of the
5785 * 5705/5750, just say success.
5786 */
5787 return 0;
5788
5789 default:
5790 break;
855e1111 5791 }
1da177e4
LT		 5792 }
5793
5794 val = tr32(ofs);
5795 val &= ~enable_bit;
5796 tw32_f(ofs, val);
5797
5798 for (i = 0; i < MAX_WAIT_CNT; i++) {
5799 udelay(100);
5800 val = tr32(ofs);
5801 if ((val & enable_bit) == 0)
5802 break;
5803 }
5804
b3b7d6be 5805 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5806 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5807 "ofs=%lx enable_bit=%x\n",
5808 ofs, enable_bit);
5809 return -ENODEV;
5810 }
5811
5812 return 0;
5813}
5814
5815/* tp->lock is held. */
b3b7d6be 5816static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5817{
5818 int i, err;
5819
5820 tg3_disable_ints(tp);
5821
5822 tp->rx_mode &= ~RX_MODE_ENABLE;
5823 tw32_f(MAC_RX_MODE, tp->rx_mode);
5824 udelay(10);
5825
b3b7d6be
DM		 5826 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5827 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5828 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5829 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5830 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5831 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5832
5833 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5834 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5835 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5836 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5837 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5838 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5839 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5840
5841 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5842 tw32_f(MAC_MODE, tp->mac_mode);
5843 udelay(40);
5844
5845 tp->tx_mode &= ~TX_MODE_ENABLE;
5846 tw32_f(MAC_TX_MODE, tp->tx_mode);
5847
5848 for (i = 0; i < MAX_WAIT_CNT; i++) {
5849 udelay(100);
5850 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5851 break;
5852 }
5853 if (i >= MAX_WAIT_CNT) {
5854 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5855 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5856 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5857 err |= -ENODEV;
1da177e4
LT		 5858 }
5859
e6de8ad1 5860 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5861 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5862 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5863
5864 tw32(FTQ_RESET, 0xffffffff);
5865 tw32(FTQ_RESET, 0x00000000);
5866
b3b7d6be
DM		 5867 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5868 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5869
5870 if (tp->hw_status)
5871 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5872 if (tp->hw_stats)
5873 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5874
1da177e4
LT		 5875 return err;
5876}
5877
0d3031d9
MC		 5878static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5879{
5880 int i;
5881 u32 apedata;
5882
5883 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5884 if (apedata != APE_SEG_SIG_MAGIC)
5885 return;
5886
5887 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5888 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5889 return;
5890
5891 /* Wait for up to 1 millisecond for APE to service previous event. */
5892 for (i = 0; i < 10; i++) {
5893 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5894 return;
5895
5896 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5897
5898 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5899 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5900 event | APE_EVENT_STATUS_EVENT_PENDING);
5901
5902 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5903
5904 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5905 break;
5906
5907 udelay(100);
5908 }
5909
5910 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5911 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5912}
5913
5914static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5915{
5916 u32 event;
5917 u32 apedata;
5918
5919 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5920 return;
5921
5922 switch (kind) {
5923 case RESET_KIND_INIT:
5924 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5925 APE_HOST_SEG_SIG_MAGIC);
5926 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5927 APE_HOST_SEG_LEN_MAGIC);
5928 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5929 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5930 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5931 APE_HOST_DRIVER_ID_MAGIC);
5932 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5933 APE_HOST_BEHAV_NO_PHYLOCK);
5934
5935 event = APE_EVENT_STATUS_STATE_START;
5936 break;
5937 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5938 /* With the interface we are currently using,
5939 * APE does not track driver state. Wiping
5940 * out the HOST SEGMENT SIGNATURE forces
5941 * the APE to assume OS absent status.
5942 */
5943 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5944
0d3031d9
MC		 5945 event = APE_EVENT_STATUS_STATE_UNLOAD;
5946 break;
5947 case RESET_KIND_SUSPEND:
5948 event = APE_EVENT_STATUS_STATE_SUSPEND;
5949 break;
5950 default:
5951 return;
5952 }
5953
5954 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5955
5956 tg3_ape_send_event(tp, event);
5957}
5958
1da177e4
LT		 5959/* tp->lock is held. */
5960static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5961{
f49639e6
DM		 5962 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5963 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5964
5965 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5966 switch (kind) {
5967 case RESET_KIND_INIT:
5968 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5969 DRV_STATE_START);
5970 break;
5971
5972 case RESET_KIND_SHUTDOWN:
5973 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5974 DRV_STATE_UNLOAD);
5975 break;
5976
5977 case RESET_KIND_SUSPEND:
5978 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5979 DRV_STATE_SUSPEND);
5980 break;
5981
5982 default:
5983 break;
855e1111 5984 }
1da177e4 5985 }
0d3031d9
MC		 5986
5987 if (kind == RESET_KIND_INIT ||
5988 kind == RESET_KIND_SUSPEND)
5989 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5990}
5991
5992/* tp->lock is held. */
5993static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5994{
5995 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5996 switch (kind) {
5997 case RESET_KIND_INIT:
5998 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5999 DRV_STATE_START_DONE);
6000 break;
6001
6002 case RESET_KIND_SHUTDOWN:
6003 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6004 DRV_STATE_UNLOAD_DONE);
6005 break;
6006
6007 default:
6008 break;
855e1111 6009 }
1da177e4 6010 }
0d3031d9
MC		 6011
6012 if (kind == RESET_KIND_SHUTDOWN)
6013 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6014}
6015
6016/* tp->lock is held. */
6017static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6018{
6019 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6020 switch (kind) {
6021 case RESET_KIND_INIT:
6022 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6023 DRV_STATE_START);
6024 break;
6025
6026 case RESET_KIND_SHUTDOWN:
6027 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6028 DRV_STATE_UNLOAD);
6029 break;
6030
6031 case RESET_KIND_SUSPEND:
6032 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6033 DRV_STATE_SUSPEND);
6034 break;
6035
6036 default:
6037 break;
855e1111 6038 }
1da177e4
LT		 6039 }
6040}
6041
7a6f4369
MC		 6042static int tg3_poll_fw(struct tg3 *tp)
6043{
6044 int i;
6045 u32 val;
6046
b5d3772c 6047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6048 /* Wait up to 20ms for init done. */
6049 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6050 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6051 return 0;
0ccead18 6052 udelay(100);
b5d3772c
MC		 6053 }
6054 return -ENODEV;
6055 }
6056
7a6f4369
MC		 6057 /* Wait for firmware initialization to complete. */
6058 for (i = 0; i < 100000; i++) {
6059 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6060 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6061 break;
6062 udelay(10);
6063 }
6064
6065 /* Chip might not be fitted with firmware. Some Sun onboard
6066 * parts are configured like that. So don't signal the timeout
6067 * of the above loop as an error, but do report the lack of
6068 * running firmware once.
6069 */
6070 if (i >= 100000 &&
6071 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6072 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6073
6074 printk(KERN_INFO PFX "%s: No firmware running.\n",
6075 tp->dev->name);
6076 }
6077
6078 return 0;
6079}
6080
ee6a99b5
MC		 6081/* Save PCI command register before chip reset */
6082static void tg3_save_pci_state(struct tg3 *tp)
6083{
8a6eac90 6084 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6085}
6086
6087/* Restore PCI state after chip reset */
6088static void tg3_restore_pci_state(struct tg3 *tp)
6089{
6090 u32 val;
6091
6092 /* Re-enable indirect register accesses. */
6093 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6094 tp->misc_host_ctrl);
6095
6096 /* Set MAX PCI retry to zero. */
6097 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6098 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6099 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6100 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6101 /* Allow reads and writes to the APE register and memory space. */
6102 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6103 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6104 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6105 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6106
8a6eac90 6107 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6108
fcb389df
MC		 6109 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6110 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6111 pcie_set_readrq(tp->pdev, 4096);
6112 else {
6113 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6114 tp->pci_cacheline_sz);
6115 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6116 tp->pci_lat_timer);
6117 }
114342f2 6118 }
5f5c51e3 6119
ee6a99b5 6120 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6121 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6122 u16 pcix_cmd;
6123
6124 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6125 &pcix_cmd);
6126 pcix_cmd &= ~PCI_X_CMD_ERO;
6127 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6128 pcix_cmd);
6129 }
ee6a99b5
MC		 6130
6131 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6132
6133 /* Chip reset on 5780 will reset MSI enable bit,
6134 * so need to restore it.
6135 */
6136 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6137 u16 ctrl;
6138
6139 pci_read_config_word(tp->pdev,
6140 tp->msi_cap + PCI_MSI_FLAGS,
6141 &ctrl);
6142 pci_write_config_word(tp->pdev,
6143 tp->msi_cap + PCI_MSI_FLAGS,
6144 ctrl | PCI_MSI_FLAGS_ENABLE);
6145 val = tr32(MSGINT_MODE);
6146 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6147 }
6148 }
6149}
6150
1da177e4
LT		 6151static void tg3_stop_fw(struct tg3 *);
6152
6153/* tp->lock is held. */
6154static int tg3_chip_reset(struct tg3 *tp)
6155{
6156 u32 val;
1ee582d8 6157 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6158 int err;
1da177e4 6159
f49639e6
DM		 6160 tg3_nvram_lock(tp);
6161
158d7abd
MC		 6162 tg3_mdio_stop(tp);
6163
77b483f1
MC		 6164 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6165
f49639e6
DM		 6166 /* No matching tg3_nvram_unlock() after this because
6167 * chip reset below will undo the nvram lock.
6168 */
6169 tp->nvram_lock_cnt = 0;
1da177e4 6170
ee6a99b5
MC		 6171 /* GRC_MISC_CFG core clock reset will clear the memory
6172 * enable bit in PCI register 4 and the MSI enable bit
6173 * on some chips, so we save relevant registers here.
6174 */
6175 tg3_save_pci_state(tp);
6176
d9ab5ad1 6177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6178 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6179 tw32(GRC_FASTBOOT_PC, 0);
6180
1da177e4
LT		 6181 /*
6182 * We must avoid the readl() that normally takes place.
6183 * It locks machines, causes machine checks, and other
6184 * fun things. So, temporarily disable the 5701
6185 * hardware workaround, while we do the reset.
6186 */
1ee582d8
MC		 6187 write_op = tp->write32;
6188 if (write_op == tg3_write_flush_reg32)
6189 tp->write32 = tg3_write32;
1da177e4 6190
d18edcb2
MC		 6191 /* Prevent the irq handler from reading or writing PCI registers
6192 * during chip reset when the memory enable bit in the PCI command
6193 * register may be cleared. The chip does not generate interrupt
6194 * at this time, but the irq handler may still be called due to irq
6195 * sharing or irqpoll.
6196 */
6197 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6198 if (tp->hw_status) {
6199 tp->hw_status->status = 0;
6200 tp->hw_status->status_tag = 0;
6201 }
d18edcb2 6202 tp->last_tag = 0;
624f8e50 6203 tp->last_irq_tag = 0;
d18edcb2
MC		 6204 smp_mb();
6205 synchronize_irq(tp->pdev->irq);
6206
255ca311
MC		 6207 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6208 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6209 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6210 }
6211
1da177e4
LT		 6212 /* do the reset */
6213 val = GRC_MISC_CFG_CORECLK_RESET;
6214
6215 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6216 if (tr32(0x7e2c) == 0x60) {
6217 tw32(0x7e2c, 0x20);
6218 }
6219 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6220 tw32(GRC_MISC_CFG, (1 << 29));
6221 val |= (1 << 29);
6222 }
6223 }
6224
b5d3772c
MC		 6225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6226 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6227 tw32(GRC_VCPU_EXT_CTRL,
6228 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6229 }
6230
1da177e4
LT		 6231 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6232 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6233 tw32(GRC_MISC_CFG, val);
6234
1ee582d8
MC		 6235 /* restore 5701 hardware bug workaround write method */
6236 tp->write32 = write_op;
1da177e4
LT		 6237
6238 /* Unfortunately, we have to delay before the PCI read back.
6239 * Some 575X chips even will not respond to a PCI cfg access
6240 * when the reset command is given to the chip.
6241 *
6242 * How do these hardware designers expect things to work
6243 * properly if the PCI write is posted for a long period
6244 * of time? It is always necessary to have some method by
6245 * which a register read back can occur to push the write
6246 * out which does the reset.
6247 *
6248 * For most tg3 variants the trick below was working.
6249 * Ho hum...
6250 */
6251 udelay(120);
6252
6253 /* Flush PCI posted writes. The normal MMIO registers
6254 * are inaccessible at this time so this is the only
6255 * way to make this reliably (actually, this is no longer
6256 * the case, see above). I tried to use indirect
6257 * register read/write but this upset some 5701 variants.
6258 */
6259 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6260
6261 udelay(120);
6262
5e7dfd0f 6263 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6264 u16 val16;
6265
1da177e4
LT		 6266 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6267 int i;
6268 u32 cfg_val;
6269
6270 /* Wait for link training to complete. */
6271 for (i = 0; i < 5000; i++)
6272 udelay(100);
6273
6274 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6275 pci_write_config_dword(tp->pdev, 0xc4,
6276 cfg_val | (1 << 15));
6277 }
5e7dfd0f 6278
e7126997
MC		 6279 /* Clear the "no snoop" and "relaxed ordering" bits. */
6280 pci_read_config_word(tp->pdev,
6281 tp->pcie_cap + PCI_EXP_DEVCTL,
6282 &val16);
6283 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6284 PCI_EXP_DEVCTL_NOSNOOP_EN);
6285 /*
6286 * Older PCIe devices only support the 128 byte
6287 * MPS setting. Enforce the restriction.
5e7dfd0f 6288 */
e7126997
MC		 6289 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6290 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6291 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6292 pci_write_config_word(tp->pdev,
6293 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6294 val16);
5e7dfd0f
MC		 6295
6296 pcie_set_readrq(tp->pdev, 4096);
6297
6298 /* Clear error status */
6299 pci_write_config_word(tp->pdev,
6300 tp->pcie_cap + PCI_EXP_DEVSTA,
6301 PCI_EXP_DEVSTA_CED |
6302 PCI_EXP_DEVSTA_NFED |
6303 PCI_EXP_DEVSTA_FED |
6304 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6305 }
6306
ee6a99b5 6307 tg3_restore_pci_state(tp);
1da177e4 6308
d18edcb2
MC		 6309 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6310
ee6a99b5
MC		 6311 val = 0;
6312 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6313 val = tr32(MEMARB_MODE);
ee6a99b5 6314 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6315
6316 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6317 tg3_stop_fw(tp);
6318 tw32(0x5000, 0x400);
6319 }
6320
6321 tw32(GRC_MODE, tp->grc_mode);
6322
6323 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6324 val = tr32(0xc4);
1da177e4
LT		 6325
6326 tw32(0xc4, val | (1 << 15));
6327 }
6328
6329 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6330 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6331 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6332 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6333 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6334 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6335 }
6336
6337 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6338 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6339 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6340 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6341 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6342 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6343 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6344 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6345 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6346 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6347 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6348 } else
6349 tw32_f(MAC_MODE, 0);
6350 udelay(40);
6351
77b483f1
MC		 6352 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6353
7a6f4369
MC		 6354 err = tg3_poll_fw(tp);
6355 if (err)
6356 return err;
1da177e4 6357
0a9140cf
MC		 6358 tg3_mdio_start(tp);
6359
1da177e4
LT		 6360 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6361 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6362 val = tr32(0x7c00);
1da177e4
LT		 6363
6364 tw32(0x7c00, val | (1 << 25));
6365 }
6366
6367 /* Reprobe ASF enable state. */
6368 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6369 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6370 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6371 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6372 u32 nic_cfg;
6373
6374 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6375 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6376 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6377 tp->last_event_jiffies = jiffies;
cbf46853 6378 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6379 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6380 }
6381 }
6382
6383 return 0;
6384}
6385
6386/* tp->lock is held. */
6387static void tg3_stop_fw(struct tg3 *tp)
6388{
0d3031d9
MC		 6389 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6390 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6391 /* Wait for RX cpu to ACK the previous event. */
6392 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6393
6394 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6395
6396 tg3_generate_fw_event(tp);
1da177e4 6397
7c5026aa
MC		 6398 /* Wait for RX cpu to ACK this event. */
6399 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6400 }
6401}
6402
6403/* tp->lock is held. */
944d980e 6404static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6405{
6406 int err;
6407
6408 tg3_stop_fw(tp);
6409
944d980e 6410 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6411
b3b7d6be 6412 tg3_abort_hw(tp, silent);
1da177e4
LT		 6413 err = tg3_chip_reset(tp);
6414
daba2a63
MC		 6415 __tg3_set_mac_addr(tp, 0);
6416
944d980e
MC		 6417 tg3_write_sig_legacy(tp, kind);
6418 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6419
6420 if (err)
6421 return err;
6422
6423 return 0;
6424}
6425
1da177e4
LT		 6426#define RX_CPU_SCRATCH_BASE 0x30000
6427#define RX_CPU_SCRATCH_SIZE 0x04000
6428#define TX_CPU_SCRATCH_BASE 0x34000
6429#define TX_CPU_SCRATCH_SIZE 0x04000
6430
6431/* tp->lock is held. */
6432static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6433{
6434 int i;
6435
5d9428de
ES		 6436 BUG_ON(offset == TX_CPU_BASE &&
6437 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6438
b5d3772c
MC		 6439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6440 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6441
6442 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6443 return 0;
6444 }
1da177e4
LT		 6445 if (offset == RX_CPU_BASE) {
6446 for (i = 0; i < 10000; i++) {
6447 tw32(offset + CPU_STATE, 0xffffffff);
6448 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6449 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6450 break;
6451 }
6452
6453 tw32(offset + CPU_STATE, 0xffffffff);
6454 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6455 udelay(10);
6456 } else {
6457 for (i = 0; i < 10000; i++) {
6458 tw32(offset + CPU_STATE, 0xffffffff);
6459 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6460 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6461 break;
6462 }
6463 }
6464
6465 if (i >= 10000) {
6466 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6467 "and %s CPU\n",
6468 tp->dev->name,
6469 (offset == RX_CPU_BASE ? "RX" : "TX"));
6470 return -ENODEV;
6471 }
ec41c7df
MC		 6472
6473 /* Clear firmware's nvram arbitration. */
6474 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6475 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6476 return 0;
6477}
6478
6479struct fw_info {
077f849d
JSR		 6480 unsigned int fw_base;
6481 unsigned int fw_len;
6482 const __be32 *fw_data;
1da177e4
LT		 6483};
6484
6485/* tp->lock is held. */
6486static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6487 int cpu_scratch_size, struct fw_info *info)
6488{
ec41c7df 6489 int err, lock_err, i;
1da177e4
LT		 6490 void (*write_op)(struct tg3 *, u32, u32);
6491
6492 if (cpu_base == TX_CPU_BASE &&
6493 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6494 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6495 "TX cpu firmware on %s which is 5705.\n",
6496 tp->dev->name);
6497 return -EINVAL;
6498 }
6499
6500 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6501 write_op = tg3_write_mem;
6502 else
6503 write_op = tg3_write_indirect_reg32;
6504
1b628151
MC		 6505 /* It is possible that bootcode is still loading at this point.
6506 * Get the nvram lock first before halting the cpu.
6507 */
ec41c7df 6508 lock_err = tg3_nvram_lock(tp);
1da177e4 6509 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6510 if (!lock_err)
6511 tg3_nvram_unlock(tp);
1da177e4
LT		 6512 if (err)
6513 goto out;
6514
6515 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6516 write_op(tp, cpu_scratch_base + i, 0);
6517 tw32(cpu_base + CPU_STATE, 0xffffffff);
6518 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6519 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6520 write_op(tp, (cpu_scratch_base +
077f849d 6521 (info->fw_base & 0xffff) +
1da177e4 6522 (i * sizeof(u32))),
077f849d 6523 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6524
6525 err = 0;
6526
6527out:
1da177e4
LT		 6528 return err;
6529}
6530
6531/* tp->lock is held. */
6532static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6533{
6534 struct fw_info info;
077f849d 6535 const __be32 *fw_data;
1da177e4
LT		 6536 int err, i;
6537
077f849d
JSR		 6538 fw_data = (void *)tp->fw->data;
6539
6540 /* Firmware blob starts with version numbers, followed by
6541 start address and length. We are setting complete length.
6542 length = end_address_of_bss - start_address_of_text.
6543 Remainder is the blob to be loaded contiguously
6544 from start address. */
6545
6546 info.fw_base = be32_to_cpu(fw_data[1]);
6547 info.fw_len = tp->fw->size - 12;
6548 info.fw_data = &fw_data[3];
1da177e4
LT		 6549
6550 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6551 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6552 &info);
6553 if (err)
6554 return err;
6555
6556 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6557 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6558 &info);
6559 if (err)
6560 return err;
6561
6562 /* Now startup only the RX cpu. */
6563 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6564 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6565
6566 for (i = 0; i < 5; i++) {
077f849d 6567 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6568 break;
6569 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6570 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6571 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6572 udelay(1000);
6573 }
6574 if (i >= 5) {
6575 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6576 "to set RX CPU PC, is %08x should be %08x\n",
6577 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6578 info.fw_base);
1da177e4
LT		 6579 return -ENODEV;
6580 }
6581 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6582 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6583
6584 return 0;
6585}
6586
1da177e4 6587/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6588
6589/* tp->lock is held. */
6590static int tg3_load_tso_firmware(struct tg3 *tp)
6591{
6592 struct fw_info info;
077f849d 6593 const __be32 *fw_data;
1da177e4
LT		 6594 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6595 int err, i;
6596
6597 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6598 return 0;
6599
077f849d
JSR		 6600 fw_data = (void *)tp->fw->data;
6601
6602 /* Firmware blob starts with version numbers, followed by
6603 start address and length. We are setting complete length.
6604 length = end_address_of_bss - start_address_of_text.
6605 Remainder is the blob to be loaded contiguously
6606 from start address. */
6607
6608 info.fw_base = be32_to_cpu(fw_data[1]);
6609 cpu_scratch_size = tp->fw_len;
6610 info.fw_len = tp->fw->size - 12;
6611 info.fw_data = &fw_data[3];
6612
1da177e4 6613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6614 cpu_base = RX_CPU_BASE;
6615 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6616 } else {
1da177e4
LT		 6617 cpu_base = TX_CPU_BASE;
6618 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6619 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6620 }
6621
6622 err = tg3_load_firmware_cpu(tp, cpu_base,
6623 cpu_scratch_base, cpu_scratch_size,
6624 &info);
6625 if (err)
6626 return err;
6627
6628 /* Now startup the cpu. */
6629 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6630 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6631
6632 for (i = 0; i < 5; i++) {
077f849d 6633 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6634 break;
6635 tw32(cpu_base + CPU_STATE, 0xffffffff);
6636 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6637 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6638 udelay(1000);
6639 }
6640 if (i >= 5) {
6641 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6642 "to set CPU PC, is %08x should be %08x\n",
6643 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6644 info.fw_base);
1da177e4
LT		 6645 return -ENODEV;
6646 }
6647 tw32(cpu_base + CPU_STATE, 0xffffffff);
6648 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6649 return 0;
6650}
6651
1da177e4 6652
1da177e4
LT		 6653static int tg3_set_mac_addr(struct net_device *dev, void *p)
6654{
6655 struct tg3 *tp = netdev_priv(dev);
6656 struct sockaddr *addr = p;
986e0aeb 6657 int err = 0, skip_mac_1 = 0;
1da177e4 6658
f9804ddb
MC		 6659 if (!is_valid_ether_addr(addr->sa_data))
6660 return -EINVAL;
6661
1da177e4
LT		 6662 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6663
e75f7c90
MC		 6664 if (!netif_running(dev))
6665 return 0;
6666
58712ef9 6667 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6668 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6669
986e0aeb
MC		 6670 addr0_high = tr32(MAC_ADDR_0_HIGH);
6671 addr0_low = tr32(MAC_ADDR_0_LOW);
6672 addr1_high = tr32(MAC_ADDR_1_HIGH);
6673 addr1_low = tr32(MAC_ADDR_1_LOW);
6674
6675 /* Skip MAC addr 1 if ASF is using it. */
6676 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6677 !(addr1_high == 0 && addr1_low == 0))
6678 skip_mac_1 = 1;
58712ef9 6679 }
986e0aeb
MC		 6680 spin_lock_bh(&tp->lock);
6681 __tg3_set_mac_addr(tp, skip_mac_1);
6682 spin_unlock_bh(&tp->lock);
1da177e4 6683
b9ec6c1b 6684 return err;
1da177e4
LT		 6685}
6686
6687/* tp->lock is held. */
6688static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6689 dma_addr_t mapping, u32 maxlen_flags,
6690 u32 nic_addr)
6691{
6692 tg3_write_mem(tp,
6693 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6694 ((u64) mapping >> 32));
6695 tg3_write_mem(tp,
6696 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6697 ((u64) mapping & 0xffffffff));
6698 tg3_write_mem(tp,
6699 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6700 maxlen_flags);
6701
6702 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6703 tg3_write_mem(tp,
6704 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6705 nic_addr);
6706}
6707
6708static void __tg3_set_rx_mode(struct net_device *);
d244c892 6709static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6710{
6711 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6712 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6713 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6714 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6715 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6716 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6717 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6718 }
6719 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6720 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6721 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6722 u32 val = ec->stats_block_coalesce_usecs;
6723
6724 if (!netif_carrier_ok(tp->dev))
6725 val = 0;
6726
6727 tw32(HOSTCC_STAT_COAL_TICKS, val);
6728 }
6729}
1da177e4
LT		 6730
6731/* tp->lock is held. */
8e7a22e3 6732static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6733{
6734 u32 val, rdmac_mode;
6735 int i, err, limit;
6736
6737 tg3_disable_ints(tp);
6738
6739 tg3_stop_fw(tp);
6740
6741 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6742
6743 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6744 tg3_abort_hw(tp, 1);
1da177e4
LT		 6745 }
6746
dd477003
MC		 6747 if (reset_phy &&
6748 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6749 tg3_phy_reset(tp);
6750
1da177e4
LT		 6751 err = tg3_chip_reset(tp);
6752 if (err)
6753 return err;
6754
6755 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6756
bcb37f6c 6757 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6758 val = tr32(TG3_CPMU_CTRL);
6759 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6760 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6761
6762 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6763 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6764 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6765 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6766
6767 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6768 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6769 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6770 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6771
6772 val = tr32(TG3_CPMU_HST_ACC);
6773 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6774 val |= CPMU_HST_ACC_MACCLK_6_25;
6775 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6776 }
6777
33466d93
MC		 6778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6779 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6780 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6781 PCIE_PWR_MGMT_L1_THRESH_4MS;
6782 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6783
6784 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6785 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6786
6787 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6788 }
6789
255ca311
MC		 6790 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6791 val = tr32(TG3_PCIE_LNKCTL);
6792 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6793 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6794 else
6795 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6796 tw32(TG3_PCIE_LNKCTL, val);
6797 }
6798
1da177e4
LT		 6799 /* This works around an issue with Athlon chipsets on
6800 * B3 tigon3 silicon. This bit has no effect on any
6801 * other revision. But do not set this on PCI Express
795d01c5 6802 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6803 */
795d01c5
MC		 6804 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6805 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6806 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6807 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6808 }
1da177e4
LT		 6809
6810 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6811 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6812 val = tr32(TG3PCI_PCISTATE);
6813 val |= PCISTATE_RETRY_SAME_DMA;
6814 tw32(TG3PCI_PCISTATE, val);
6815 }
6816
0d3031d9
MC		 6817 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6818 /* Allow reads and writes to the
6819 * APE register and memory space.
6820 */
6821 val = tr32(TG3PCI_PCISTATE);
6822 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6823 PCISTATE_ALLOW_APE_SHMEM_WR;
6824 tw32(TG3PCI_PCISTATE, val);
6825 }
6826
1da177e4
LT		 6827 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6828 /* Enable some hw fixes. */
6829 val = tr32(TG3PCI_MSI_DATA);
6830 val |= (1 << 26) | (1 << 28) | (1 << 29);
6831 tw32(TG3PCI_MSI_DATA, val);
6832 }
6833
6834 /* Descriptor ring init may make accesses to the
6835 * NIC SRAM area to setup the TX descriptors, so we
6836 * can only do this after the hardware has been
6837 * successfully reset.
6838 */
32d8c572
MC		 6839 err = tg3_init_rings(tp);
6840 if (err)
6841 return err;
1da177e4 6842
9936bcf6 6843 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6844 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6845 /* This value is determined during the probe time DMA
6846 * engine test, tg3_test_dma.
6847 */
6848 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6849 }
1da177e4
LT		 6850
6851 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6852 GRC_MODE_4X_NIC_SEND_RINGS |
6853 GRC_MODE_NO_TX_PHDR_CSUM |
6854 GRC_MODE_NO_RX_PHDR_CSUM);
6855 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6856
6857 /* Pseudo-header checksum is done by hardware logic and not
6858 * the offload processers, so make the chip do the pseudo-
6859 * header checksums on receive. For transmit it is more
6860 * convenient to do the pseudo-header checksum in software
6861 * as Linux does that on transmit for us in all cases.
6862 */
6863 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6864
6865 tw32(GRC_MODE,
6866 tp->grc_mode |
6867 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6868
6869 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6870 val = tr32(GRC_MISC_CFG);
6871 val &= ~0xff;
6872 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6873 tw32(GRC_MISC_CFG, val);
6874
6875 /* Initialize MBUF/DESC pool. */
cbf46853 6876 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6877 /* Do nothing. */
6878 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6879 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6880 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6881 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6882 else
6883 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6884 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6885 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6886 }
1da177e4
LT		 6887 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6888 int fw_len;
6889
077f849d 6890 fw_len = tp->fw_len;
1da177e4
LT		 6891 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6892 tw32(BUFMGR_MB_POOL_ADDR,
6893 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6894 tw32(BUFMGR_MB_POOL_SIZE,
6895 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6896 }
1da177e4 6897
0f893dc6 6898 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6899 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6900 tp->bufmgr_config.mbuf_read_dma_low_water);
6901 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6902 tp->bufmgr_config.mbuf_mac_rx_low_water);
6903 tw32(BUFMGR_MB_HIGH_WATER,
6904 tp->bufmgr_config.mbuf_high_water);
6905 } else {
6906 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6907 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6908 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6909 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6910 tw32(BUFMGR_MB_HIGH_WATER,
6911 tp->bufmgr_config.mbuf_high_water_jumbo);
6912 }
6913 tw32(BUFMGR_DMA_LOW_WATER,
6914 tp->bufmgr_config.dma_low_water);
6915 tw32(BUFMGR_DMA_HIGH_WATER,
6916 tp->bufmgr_config.dma_high_water);
6917
6918 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6919 for (i = 0; i < 2000; i++) {
6920 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6921 break;
6922 udelay(10);
6923 }
6924 if (i >= 2000) {
6925 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6926 tp->dev->name);
6927 return -ENODEV;
6928 }
6929
6930 /* Setup replenish threshold. */
f92905de
MC		 6931 val = tp->rx_pending / 8;
6932 if (val == 0)
6933 val = 1;
6934 else if (val > tp->rx_std_max_post)
6935 val = tp->rx_std_max_post;
b5d3772c
MC		 6936 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6937 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6938 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6939
6940 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6941 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6942 }
f92905de
MC		 6943
6944 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6945
6946 /* Initialize TG3_BDINFO's at:
6947 * RCVDBDI_STD_BD: standard eth size rx ring
6948 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6949 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6950 *
6951 * like so:
6952 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6953 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6954 * ring attribute flags
6955 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6956 *
6957 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6958 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6959 *
6960 * The size of each ring is fixed in the firmware, but the location is
6961 * configurable.
6962 */
6963 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6964 ((u64) tp->rx_std_mapping >> 32));
6965 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6966 ((u64) tp->rx_std_mapping & 0xffffffff));
6967 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6968 NIC_SRAM_RX_BUFFER_DESC);
6969
6970 /* Don't even try to program the JUMBO/MINI buffer descriptor
6971 * configs on 5705.
6972 */
6973 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6974 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6975 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6976 } else {
6977 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6978 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6979
6980 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6981 BDINFO_FLAGS_DISABLED);
6982
6983 /* Setup replenish threshold. */
6984 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6985
0f893dc6 6986 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6987 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6988 ((u64) tp->rx_jumbo_mapping >> 32));
6989 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6990 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6991 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6992 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6993 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6994 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6995 } else {
6996 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6997 BDINFO_FLAGS_DISABLED);
6998 }
6999
7000 }
7001
7002 /* There is only one send ring on 5705/5750, no need to explicitly
7003 * disable the others.
7004 */
7005 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7006 /* Clear out send RCB ring in SRAM. */
7007 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7008 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7009 BDINFO_FLAGS_DISABLED);
7010 }
7011
7012 tp->tx_prod = 0;
7013 tp->tx_cons = 0;
7014 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7015 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7016
7017 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7018 tp->tx_desc_mapping,
7019 (TG3_TX_RING_SIZE <<
7020 BDINFO_FLAGS_MAXLEN_SHIFT),
7021 NIC_SRAM_TX_BUFFER_DESC);
7022
7023 /* There is only one receive return ring on 5705/5750, no need
7024 * to explicitly disable the others.
7025 */
7026 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7027 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7028 i += TG3_BDINFO_SIZE) {
7029 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7030 BDINFO_FLAGS_DISABLED);
7031 }
7032 }
7033
7034 tp->rx_rcb_ptr = 0;
7035 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7036
7037 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7038 tp->rx_rcb_mapping,
7039 (TG3_RX_RCB_RING_SIZE(tp) <<
7040 BDINFO_FLAGS_MAXLEN_SHIFT),
7041 0);
7042
7043 tp->rx_std_ptr = tp->rx_pending;
7044 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7045 tp->rx_std_ptr);
7046
0f893dc6 7047 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 7048 tp->rx_jumbo_pending : 0;
7049 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7050 tp->rx_jumbo_ptr);
7051
7052 /* Initialize MAC address and backoff seed. */
986e0aeb 7053 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7054
7055 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7056 tw32(MAC_RX_MTU_SIZE,
7057 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7058
7059 /* The slot time is changed by tg3_setup_phy if we
7060 * run at gigabit with half duplex.
7061 */
7062 tw32(MAC_TX_LENGTHS,
7063 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7064 (6 << TX_LENGTHS_IPG_SHIFT) |
7065 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7066
7067 /* Receive rules. */
7068 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7069 tw32(RCVLPC_CONFIG, 0x0181);
7070
7071 /* Calculate RDMAC_MODE setting early, we need it to determine
7072 * the RCVLPC_STATE_ENABLE mask.
7073 */
7074 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7075 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7076 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7077 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7078 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7079
57e6983c 7080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7082 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7083 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7084 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7085 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7086
85e94ced
MC		 7087 /* If statement applies to 5705 and 5750 PCI devices only */
7088 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7089 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7090 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7091 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7093 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7094 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7095 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7096 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7097 }
7098 }
7099
85e94ced
MC		 7100 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7101 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7102
1da177e4 7103 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7104 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7105
7106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7108 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7109
7110 /* Receive/send statistics. */
1661394e
MC		 7111 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7112 val = tr32(RCVLPC_STATS_ENABLE);
7113 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7114 tw32(RCVLPC_STATS_ENABLE, val);
7115 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7116 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7117 val = tr32(RCVLPC_STATS_ENABLE);
7118 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7119 tw32(RCVLPC_STATS_ENABLE, val);
7120 } else {
7121 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7122 }
7123 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7124 tw32(SNDDATAI_STATSENAB, 0xffffff);
7125 tw32(SNDDATAI_STATSCTRL,
7126 (SNDDATAI_SCTRL_ENABLE |
7127 SNDDATAI_SCTRL_FASTUPD));
7128
7129 /* Setup host coalescing engine. */
7130 tw32(HOSTCC_MODE, 0);
7131 for (i = 0; i < 2000; i++) {
7132 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7133 break;
7134 udelay(10);
7135 }
7136
d244c892 7137 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7138
7139 /* set status block DMA address */
7140 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7141 ((u64) tp->status_mapping >> 32));
7142 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7143 ((u64) tp->status_mapping & 0xffffffff));
7144
7145 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7146 /* Status/statistics block address. See tg3_timer,
7147 * the tg3_periodic_fetch_stats call there, and
7148 * tg3_get_stats to see how this works for 5705/5750 chips.
7149 */
1da177e4
LT		 7150 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7151 ((u64) tp->stats_mapping >> 32));
7152 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7153 ((u64) tp->stats_mapping & 0xffffffff));
7154 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7155 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7156 }
7157
7158 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7159
7160 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7161 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7162 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7163 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7164
7165 /* Clear statistics/status block in chip, and status block in ram. */
7166 for (i = NIC_SRAM_STATS_BLK;
7167 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7168 i += sizeof(u32)) {
7169 tg3_write_mem(tp, i, 0);
7170 udelay(40);
7171 }
7172 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7173
c94e3941
MC		 7174 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7175 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7176 /* reset to prevent losing 1st rx packet intermittently */
7177 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7178 udelay(10);
7179 }
7180
3bda1258
MC		 7181 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7182 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7183 else
7184 tp->mac_mode = 0;
7185 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7186 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7187 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7188 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7189 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7190 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7191 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7192 udelay(40);
7193
314fba34 7194 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7195 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7196 * register to preserve the GPIO settings for LOMs. The GPIOs,
7197 * whether used as inputs or outputs, are set by boot code after
7198 * reset.
7199 */
9d26e213 7200 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7201 u32 gpio_mask;
7202
9d26e213
MC		 7203 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7204 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7205 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7206
7207 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7208 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7209 GRC_LCLCTRL_GPIO_OUTPUT3;
7210
af36e6b6
MC		 7211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7212 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7213
aaf84465 7214 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7215 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7216
7217 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7218 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7219 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7220 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7221 }
1da177e4
LT		 7222 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7223 udelay(100);
7224
09ee929c 7225 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
1da177e4
LT		 7226
7227 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7228 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7229 udelay(40);
7230 }
7231
7232 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7233 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7234 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7235 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7236 WDMAC_MODE_LNGREAD_ENAB);
7237
85e94ced
MC		 7238 /* If statement applies to 5705 and 5750 PCI devices only */
7239 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7240 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7242 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7243 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7244 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7245 /* nothing */
7246 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7247 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7248 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7249 val |= WDMAC_MODE_RX_ACCEL;
7250 }
7251 }
7252
d9ab5ad1 7253 /* Enable host coalescing bug fix */
321d32a0 7254 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7255 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7256
1da177e4
LT		 7257 tw32_f(WDMAC_MODE, val);
7258 udelay(40);
7259
9974a356
MC		 7260 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7261 u16 pcix_cmd;
7262
7263 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7264 &pcix_cmd);
1da177e4 7265 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7266 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7267 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7268 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7269 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7270 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7271 }
9974a356
MC		 7272 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7273 pcix_cmd);
1da177e4
LT		 7274 }
7275
7276 tw32_f(RDMAC_MODE, rdmac_mode);
7277 udelay(40);
7278
7279 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7280 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7281 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7282
7283 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7284 tw32(SNDDATAC_MODE,
7285 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7286 else
7287 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7288
1da177e4
LT		 7289 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7290 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7291 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7292 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7293 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7294 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7295 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7296 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7297
7298 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7299 err = tg3_load_5701_a0_firmware_fix(tp);
7300 if (err)
7301 return err;
7302 }
7303
1da177e4
LT		 7304 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7305 err = tg3_load_tso_firmware(tp);
7306 if (err)
7307 return err;
7308 }
1da177e4
LT		 7309
7310 tp->tx_mode = TX_MODE_ENABLE;
7311 tw32_f(MAC_TX_MODE, tp->tx_mode);
7312 udelay(100);
7313
7314 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7315 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7316 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7317
1da177e4
LT		 7318 tw32_f(MAC_RX_MODE, tp->rx_mode);
7319 udelay(10);
7320
1da177e4
LT		 7321 tw32(MAC_LED_CTRL, tp->led_ctrl);
7322
7323 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7324 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7325 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7326 udelay(10);
7327 }
7328 tw32_f(MAC_RX_MODE, tp->rx_mode);
7329 udelay(10);
7330
7331 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7332 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7333 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7334 /* Set drive transmission level to 1.2V */
7335 /* only if the signal pre-emphasis bit is not set */
7336 val = tr32(MAC_SERDES_CFG);
7337 val &= 0xfffff000;
7338 val |= 0x880;
7339 tw32(MAC_SERDES_CFG, val);
7340 }
7341 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7342 tw32(MAC_SERDES_CFG, 0x616000);
7343 }
7344
7345 /* Prevent chip from dropping frames when flow control
7346 * is enabled.
7347 */
7348 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7349
7350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7351 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7352 /* Use hardware link auto-negotiation */
7353 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7354 }
7355
d4d2c558
MC		 7356 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7357 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7358 u32 tmp;
7359
7360 tmp = tr32(SERDES_RX_CTRL);
7361 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7362 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7363 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7364 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7365 }
7366
dd477003
MC		 7367 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7368 if (tp->link_config.phy_is_low_power) {
7369 tp->link_config.phy_is_low_power = 0;
7370 tp->link_config.speed = tp->link_config.orig_speed;
7371 tp->link_config.duplex = tp->link_config.orig_duplex;
7372 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7373 }
1da177e4 7374
dd477003
MC		 7375 err = tg3_setup_phy(tp, 0);
7376 if (err)
7377 return err;
1da177e4 7378
dd477003 7379 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7380 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7381 u32 tmp;
7382
7383 /* Clear CRC stats. */
7384 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7385 tg3_writephy(tp, MII_TG3_TEST1,
7386 tmp | MII_TG3_TEST1_CRC_EN);
7387 tg3_readphy(tp, 0x14, &tmp);
7388 }
1da177e4
LT		 7389 }
7390 }
7391
7392 __tg3_set_rx_mode(tp->dev);
7393
7394 /* Initialize receive rules. */
7395 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7396 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7397 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7398 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7399
4cf78e4f 7400 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7401 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7402 limit = 8;
7403 else
7404 limit = 16;
7405 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7406 limit -= 4;
7407 switch (limit) {
7408 case 16:
7409 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7410 case 15:
7411 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7412 case 14:
7413 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7414 case 13:
7415 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7416 case 12:
7417 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7418 case 11:
7419 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7420 case 10:
7421 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7422 case 9:
7423 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7424 case 8:
7425 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7426 case 7:
7427 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7428 case 6:
7429 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7430 case 5:
7431 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7432 case 4:
7433 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7434 case 3:
7435 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7436 case 2:
7437 case 1:
7438
7439 default:
7440 break;
855e1111 7441 }
1da177e4 7442
9ce768ea
MC		 7443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7444 /* Write our heartbeat update interval to APE. */
7445 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7446 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7447
1da177e4
LT		 7448 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7449
1da177e4
LT		 7450 return 0;
7451}
7452
7453/* Called at device open time to get the chip ready for
7454 * packet processing. Invoked with tp->lock held.
7455 */
8e7a22e3 7456static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7457{
1da177e4
LT		 7458 tg3_switch_clocks(tp);
7459
7460 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7461
2f751b67 7462 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7463}
7464
7465#define TG3_STAT_ADD32(PSTAT, REG) \
7466do { u32 __val = tr32(REG); \
7467 (PSTAT)->low += __val; \
7468 if ((PSTAT)->low < __val) \
7469 (PSTAT)->high += 1; \
7470} while (0)
7471
7472static void tg3_periodic_fetch_stats(struct tg3 *tp)
7473{
7474 struct tg3_hw_stats *sp = tp->hw_stats;
7475
7476 if (!netif_carrier_ok(tp->dev))
7477 return;
7478
7479 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7480 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7481 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7482 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7483 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7484 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7485 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7486 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7487 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7488 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7489 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7490 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7491 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7492
7493 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7494 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7495 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7496 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7497 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7498 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7499 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7500 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7501 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7502 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7503 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7504 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7505 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7506 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7507
7508 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7509 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7510 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7511}
7512
7513static void tg3_timer(unsigned long __opaque)
7514{
7515 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7516
f475f163
MC		 7517 if (tp->irq_sync)
7518 goto restart_timer;
7519
f47c11ee 7520 spin_lock(&tp->lock);
1da177e4 7521
fac9b83e
DM		 7522 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7523 /* All of this garbage is because when using non-tagged
7524 * IRQ status the mailbox/status_block protocol the chip
7525 * uses with the cpu is race prone.
7526 */
7527 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7528 tw32(GRC_LOCAL_CTRL,
7529 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7530 } else {
7531 tw32(HOSTCC_MODE, tp->coalesce_mode |
7532 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7533 }
1da177e4 7534
fac9b83e
DM		 7535 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7536 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7537 spin_unlock(&tp->lock);
fac9b83e
DM		 7538 schedule_work(&tp->reset_task);
7539 return;
7540 }
1da177e4
LT		 7541 }
7542
1da177e4
LT		 7543 /* This part only runs once per second. */
7544 if (!--tp->timer_counter) {
fac9b83e
DM		 7545 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7546 tg3_periodic_fetch_stats(tp);
7547
1da177e4
LT		 7548 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7549 u32 mac_stat;
7550 int phy_event;
7551
7552 mac_stat = tr32(MAC_STATUS);
7553
7554 phy_event = 0;
7555 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7556 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7557 phy_event = 1;
7558 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7559 phy_event = 1;
7560
7561 if (phy_event)
7562 tg3_setup_phy(tp, 0);
7563 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7564 u32 mac_stat = tr32(MAC_STATUS);
7565 int need_setup = 0;
7566
7567 if (netif_carrier_ok(tp->dev) &&
7568 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7569 need_setup = 1;
7570 }
7571 if (! netif_carrier_ok(tp->dev) &&
7572 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7573 MAC_STATUS_SIGNAL_DET))) {
7574 need_setup = 1;
7575 }
7576 if (need_setup) {
3d3ebe74
MC		 7577 if (!tp->serdes_counter) {
7578 tw32_f(MAC_MODE,
7579 (tp->mac_mode &
7580 ~MAC_MODE_PORT_MODE_MASK));
7581 udelay(40);
7582 tw32_f(MAC_MODE, tp->mac_mode);
7583 udelay(40);
7584 }
1da177e4
LT		 7585 tg3_setup_phy(tp, 0);
7586 }
747e8f8b
MC		 7587 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7588 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7589
7590 tp->timer_counter = tp->timer_multiplier;
7591 }
7592
130b8e4d
MC		 7593 /* Heartbeat is only sent once every 2 seconds.
7594 *
7595 * The heartbeat is to tell the ASF firmware that the host
7596 * driver is still alive. In the event that the OS crashes,
7597 * ASF needs to reset the hardware to free up the FIFO space
7598 * that may be filled with rx packets destined for the host.
7599 * If the FIFO is full, ASF will no longer function properly.
7600 *
7601 * Unintended resets have been reported on real time kernels
7602 * where the timer doesn't run on time. Netpoll will also have
7603 * same problem.
7604 *
7605 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7606 * to check the ring condition when the heartbeat is expiring
7607 * before doing the reset. This will prevent most unintended
7608 * resets.
7609 */
1da177e4 7610 if (!--tp->asf_counter) {
bc7959b2
MC		 7611 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7612 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7613 tg3_wait_for_event_ack(tp);
7614
bbadf503 7615 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7616 FWCMD_NICDRV_ALIVE3);
bbadf503 7617 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7618 /* 5 seconds timeout */
bbadf503 7619 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7620
7621 tg3_generate_fw_event(tp);
1da177e4
LT		 7622 }
7623 tp->asf_counter = tp->asf_multiplier;
7624 }
7625
f47c11ee 7626 spin_unlock(&tp->lock);
1da177e4 7627
f475f163 7628restart_timer:
1da177e4
LT		 7629 tp->timer.expires = jiffies + tp->timer_offset;
7630 add_timer(&tp->timer);
7631}
7632
81789ef5 7633static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7634{
7d12e780 7635 irq_handler_t fn;
fcfa0a32
MC		 7636 unsigned long flags;
7637 struct net_device *dev = tp->dev;
7638
7639 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7640 fn = tg3_msi;
7641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7642 fn = tg3_msi_1shot;
1fb9df5d 7643 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7644 } else {
7645 fn = tg3_interrupt;
7646 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7647 fn = tg3_interrupt_tagged;
1fb9df5d 7648 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7649 }
7650 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7651}
7652
7938109f
MC		 7653static int tg3_test_interrupt(struct tg3 *tp)
7654{
7655 struct net_device *dev = tp->dev;
b16250e3 7656 int err, i, intr_ok = 0;
7938109f 7657
d4bc3927
MC		 7658 if (!netif_running(dev))
7659 return -ENODEV;
7660
7938109f
MC		 7661 tg3_disable_ints(tp);
7662
7663 free_irq(tp->pdev->irq, dev);
7664
7665 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7666 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7667 if (err)
7668 return err;
7669
38f3843e 7670 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7671 tg3_enable_ints(tp);
7672
7673 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7674 HOSTCC_MODE_NOW);
7675
7676 for (i = 0; i < 5; i++) {
b16250e3
MC		 7677 u32 int_mbox, misc_host_ctrl;
7678
09ee929c
MC		 7679 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7680 TG3_64BIT_REG_LOW);
b16250e3
MC		 7681 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7682
7683 if ((int_mbox != 0) ||
7684 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7685 intr_ok = 1;
7938109f 7686 break;
b16250e3
MC		 7687 }
7688
7938109f
MC		 7689 msleep(10);
7690 }
7691
7692 tg3_disable_ints(tp);
7693
7694 free_irq(tp->pdev->irq, dev);
6aa20a22 7695
fcfa0a32 7696 err = tg3_request_irq(tp);
7938109f
MC		 7697
7698 if (err)
7699 return err;
7700
b16250e3 7701 if (intr_ok)
7938109f
MC		 7702 return 0;
7703
7704 return -EIO;
7705}
7706
7707/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7708 * successfully restored
7709 */
7710static int tg3_test_msi(struct tg3 *tp)
7711{
7712 struct net_device *dev = tp->dev;
7713 int err;
7714 u16 pci_cmd;
7715
7716 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7717 return 0;
7718
7719 /* Turn off SERR reporting in case MSI terminates with Master
7720 * Abort.
7721 */
7722 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7723 pci_write_config_word(tp->pdev, PCI_COMMAND,
7724 pci_cmd & ~PCI_COMMAND_SERR);
7725
7726 err = tg3_test_interrupt(tp);
7727
7728 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7729
7730 if (!err)
7731 return 0;
7732
7733 /* other failures */
7734 if (err != -EIO)
7735 return err;
7736
7737 /* MSI test failed, go back to INTx mode */
7738 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7739 "switching to INTx mode. Please report this failure to "
7740 "the PCI maintainer and include system chipset information.\n",
7741 tp->dev->name);
7742
7743 free_irq(tp->pdev->irq, dev);
7744 pci_disable_msi(tp->pdev);
7745
7746 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7747
fcfa0a32 7748 err = tg3_request_irq(tp);
7938109f
MC		 7749 if (err)
7750 return err;
7751
7752 /* Need to reset the chip because the MSI cycle may have terminated
7753 * with Master Abort.
7754 */
f47c11ee 7755 tg3_full_lock(tp, 1);
7938109f 7756
944d980e 7757 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7758 err = tg3_init_hw(tp, 1);
7938109f 7759
f47c11ee 7760 tg3_full_unlock(tp);
7938109f
MC		 7761
7762 if (err)
7763 free_irq(tp->pdev->irq, dev);
7764
7765 return err;
7766}
7767
9e9fd12d
MC		 7768static int tg3_request_firmware(struct tg3 *tp)
7769{
7770 const __be32 *fw_data;
7771
7772 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7773 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7774 tp->dev->name, tp->fw_needed);
7775 return -ENOENT;
7776 }
7777
7778 fw_data = (void *)tp->fw->data;
7779
7780 /* Firmware blob starts with version numbers, followed by
7781 * start address and _full_ length including BSS sections
7782 * (which must be longer than the actual data, of course
7783 */
7784
7785 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7786 if (tp->fw_len < (tp->fw->size - 12)) {
7787 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7788 tp->dev->name, tp->fw_len, tp->fw_needed);
7789 release_firmware(tp->fw);
7790 tp->fw = NULL;
7791 return -EINVAL;
7792 }
7793
7794 /* We no longer need firmware; we have it. */
7795 tp->fw_needed = NULL;
7796 return 0;
7797}
7798
1da177e4
LT		 7799static int tg3_open(struct net_device *dev)
7800{
7801 struct tg3 *tp = netdev_priv(dev);
7802 int err;
7803
9e9fd12d
MC		 7804 if (tp->fw_needed) {
7805 err = tg3_request_firmware(tp);
7806 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7807 if (err)
7808 return err;
7809 } else if (err) {
7810 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7811 tp->dev->name);
7812 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7813 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7814 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7815 tp->dev->name);
7816 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7817 }
7818 }
7819
c49a1561
MC		 7820 netif_carrier_off(tp->dev);
7821
bc1c7567 7822 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7823 if (err)
bc1c7567 7824 return err;
2f751b67
MC		 7825
7826 tg3_full_lock(tp, 0);
bc1c7567 7827
1da177e4
LT		 7828 tg3_disable_ints(tp);
7829 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7830
f47c11ee 7831 tg3_full_unlock(tp);
1da177e4
LT		 7832
7833 /* The placement of this call is tied
7834 * to the setup and use of Host TX descriptors.
7835 */
7836 err = tg3_alloc_consistent(tp);
7837 if (err)
7838 return err;
7839
7544b097 7840 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7841 /* All MSI supporting chips should support tagged
7842 * status. Assert that this is the case.
7843 */
7844 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7845 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7846 "Not using MSI.\n", tp->dev->name);
7847 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7848 u32 msi_mode;
7849
7850 msi_mode = tr32(MSGINT_MODE);
7851 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7852 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7853 }
7854 }
fcfa0a32 7855 err = tg3_request_irq(tp);
1da177e4
LT		 7856
7857 if (err) {
88b06bc2
MC		 7858 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7859 pci_disable_msi(tp->pdev);
7860 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7861 }
1da177e4
LT		 7862 tg3_free_consistent(tp);
7863 return err;
7864 }
7865
bea3348e
SH		 7866 napi_enable(&tp->napi);
7867
f47c11ee 7868 tg3_full_lock(tp, 0);
1da177e4 7869
8e7a22e3 7870 err = tg3_init_hw(tp, 1);
1da177e4 7871 if (err) {
944d980e 7872 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7873 tg3_free_rings(tp);
7874 } else {
fac9b83e
DM		 7875 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7876 tp->timer_offset = HZ;
7877 else
7878 tp->timer_offset = HZ / 10;
7879
7880 BUG_ON(tp->timer_offset > HZ);
7881 tp->timer_counter = tp->timer_multiplier =
7882 (HZ / tp->timer_offset);
7883 tp->asf_counter = tp->asf_multiplier =
28fbef78 7884 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7885
7886 init_timer(&tp->timer);
7887 tp->timer.expires = jiffies + tp->timer_offset;
7888 tp->timer.data = (unsigned long) tp;
7889 tp->timer.function = tg3_timer;
1da177e4
LT		 7890 }
7891
f47c11ee 7892 tg3_full_unlock(tp);
1da177e4
LT		 7893
7894 if (err) {
bea3348e 7895 napi_disable(&tp->napi);
88b06bc2
MC		 7896 free_irq(tp->pdev->irq, dev);
7897 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7898 pci_disable_msi(tp->pdev);
7899 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7900 }
1da177e4
LT		 7901 tg3_free_consistent(tp);
7902 return err;
7903 }
7904
7938109f
MC		 7905 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7906 err = tg3_test_msi(tp);
fac9b83e 7907
7938109f 7908 if (err) {
f47c11ee 7909 tg3_full_lock(tp, 0);
7938109f
MC		 7910
7911 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7912 pci_disable_msi(tp->pdev);
7913 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7914 }
944d980e 7915 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7916 tg3_free_rings(tp);
7917 tg3_free_consistent(tp);
7918
f47c11ee 7919 tg3_full_unlock(tp);
7938109f 7920
bea3348e
SH		 7921 napi_disable(&tp->napi);
7922
7938109f
MC		 7923 return err;
7924 }
fcfa0a32
MC		 7925
7926 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7927 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7928 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7929
b5d3772c
MC		 7930 tw32(PCIE_TRANSACTION_CFG,
7931 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7932 }
7933 }
7938109f
MC		 7934 }
7935
b02fd9e3
MC		 7936 tg3_phy_start(tp);
7937
f47c11ee 7938 tg3_full_lock(tp, 0);
1da177e4 7939
7938109f
MC		 7940 add_timer(&tp->timer);
7941 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7942 tg3_enable_ints(tp);
7943
f47c11ee 7944 tg3_full_unlock(tp);
1da177e4
LT		 7945
7946 netif_start_queue(dev);
7947
7948 return 0;
7949}
7950
7951#if 0
7952/*static*/ void tg3_dump_state(struct tg3 *tp)
7953{
7954 u32 val32, val32_2, val32_3, val32_4, val32_5;
7955 u16 val16;
7956 int i;
7957
7958 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7959 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7960 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7961 val16, val32);
7962
7963 /* MAC block */
7964 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7965 tr32(MAC_MODE), tr32(MAC_STATUS));
7966 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7967 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7968 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7969 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7970 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7971 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7972
7973 /* Send data initiator control block */
7974 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7975 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7976 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7977 tr32(SNDDATAI_STATSCTRL));
7978
7979 /* Send data completion control block */
7980 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7981
7982 /* Send BD ring selector block */
7983 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7984 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7985
7986 /* Send BD initiator control block */
7987 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7988 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7989
7990 /* Send BD completion control block */
7991 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7992
7993 /* Receive list placement control block */
7994 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7995 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7996 printk(" RCVLPC_STATSCTRL[%08x]\n",
7997 tr32(RCVLPC_STATSCTRL));
7998
7999 /* Receive data and receive BD initiator control block */
8000 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8001 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8002
8003 /* Receive data completion control block */
8004 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8005 tr32(RCVDCC_MODE));
8006
8007 /* Receive BD initiator control block */
8008 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8009 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8010
8011 /* Receive BD completion control block */
8012 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8013 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8014
8015 /* Receive list selector control block */
8016 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8017 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8018
8019 /* Mbuf cluster free block */
8020 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8021 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8022
8023 /* Host coalescing control block */
8024 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8025 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8026 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8027 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8028 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8029 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8030 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8031 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8032 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8033 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8034 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8035 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8036
8037 /* Memory arbiter control block */
8038 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8039 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8040
8041 /* Buffer manager control block */
8042 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8043 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8044 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8045 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8046 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8047 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8048 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8049 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8050
8051 /* Read DMA control block */
8052 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8053 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8054
8055 /* Write DMA control block */
8056 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8057 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8058
8059 /* DMA completion block */
8060 printk("DEBUG: DMAC_MODE[%08x]\n",
8061 tr32(DMAC_MODE));
8062
8063 /* GRC block */
8064 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8065 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8066 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8067 tr32(GRC_LOCAL_CTRL));
8068
8069 /* TG3_BDINFOs */
8070 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8071 tr32(RCVDBDI_JUMBO_BD + 0x0),
8072 tr32(RCVDBDI_JUMBO_BD + 0x4),
8073 tr32(RCVDBDI_JUMBO_BD + 0x8),
8074 tr32(RCVDBDI_JUMBO_BD + 0xc));
8075 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8076 tr32(RCVDBDI_STD_BD + 0x0),
8077 tr32(RCVDBDI_STD_BD + 0x4),
8078 tr32(RCVDBDI_STD_BD + 0x8),
8079 tr32(RCVDBDI_STD_BD + 0xc));
8080 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8081 tr32(RCVDBDI_MINI_BD + 0x0),
8082 tr32(RCVDBDI_MINI_BD + 0x4),
8083 tr32(RCVDBDI_MINI_BD + 0x8),
8084 tr32(RCVDBDI_MINI_BD + 0xc));
8085
8086 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8087 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8088 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8089 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8090 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8091 val32, val32_2, val32_3, val32_4);
8092
8093 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8094 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8095 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8096 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8097 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8098 val32, val32_2, val32_3, val32_4);
8099
8100 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8101 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8102 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8103 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8104 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8105 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8106 val32, val32_2, val32_3, val32_4, val32_5);
8107
8108 /* SW status block */
8109 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8110 tp->hw_status->status,
8111 tp->hw_status->status_tag,
8112 tp->hw_status->rx_jumbo_consumer,
8113 tp->hw_status->rx_consumer,
8114 tp->hw_status->rx_mini_consumer,
8115 tp->hw_status->idx[0].rx_producer,
8116 tp->hw_status->idx[0].tx_consumer);
8117
8118 /* SW statistics block */
8119 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8120 ((u32 *)tp->hw_stats)[0],
8121 ((u32 *)tp->hw_stats)[1],
8122 ((u32 *)tp->hw_stats)[2],
8123 ((u32 *)tp->hw_stats)[3]);
8124
8125 /* Mailboxes */
8126 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8127 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8128 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8129 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8130 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8131
8132 /* NIC side send descriptors. */
8133 for (i = 0; i < 6; i++) {
8134 unsigned long txd;
8135
8136 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8137 + (i * sizeof(struct tg3_tx_buffer_desc));
8138 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8139 i,
8140 readl(txd + 0x0), readl(txd + 0x4),
8141 readl(txd + 0x8), readl(txd + 0xc));
8142 }
8143
8144 /* NIC side RX descriptors. */
8145 for (i = 0; i < 6; i++) {
8146 unsigned long rxd;
8147
8148 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8149 + (i * sizeof(struct tg3_rx_buffer_desc));
8150 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8151 i,
8152 readl(rxd + 0x0), readl(rxd + 0x4),
8153 readl(rxd + 0x8), readl(rxd + 0xc));
8154 rxd += (4 * sizeof(u32));
8155 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8156 i,
8157 readl(rxd + 0x0), readl(rxd + 0x4),
8158 readl(rxd + 0x8), readl(rxd + 0xc));
8159 }
8160
8161 for (i = 0; i < 6; i++) {
8162 unsigned long rxd;
8163
8164 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8165 + (i * sizeof(struct tg3_rx_buffer_desc));
8166 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8167 i,
8168 readl(rxd + 0x0), readl(rxd + 0x4),
8169 readl(rxd + 0x8), readl(rxd + 0xc));
8170 rxd += (4 * sizeof(u32));
8171 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8172 i,
8173 readl(rxd + 0x0), readl(rxd + 0x4),
8174 readl(rxd + 0x8), readl(rxd + 0xc));
8175 }
8176}
8177#endif
8178
8179static struct net_device_stats *tg3_get_stats(struct net_device *);
8180static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8181
8182static int tg3_close(struct net_device *dev)
8183{
8184 struct tg3 *tp = netdev_priv(dev);
8185
bea3348e 8186 napi_disable(&tp->napi);
28e53bdd 8187 cancel_work_sync(&tp->reset_task);
7faa006f 8188
1da177e4
LT		 8189 netif_stop_queue(dev);
8190
8191 del_timer_sync(&tp->timer);
8192
f47c11ee 8193 tg3_full_lock(tp, 1);
1da177e4
LT		 8194#if 0
8195 tg3_dump_state(tp);
8196#endif
8197
8198 tg3_disable_ints(tp);
8199
944d980e 8200 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8201 tg3_free_rings(tp);
5cf64b8a 8202 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8203
f47c11ee 8204 tg3_full_unlock(tp);
1da177e4 8205
88b06bc2
MC		 8206 free_irq(tp->pdev->irq, dev);
8207 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8208 pci_disable_msi(tp->pdev);
8209 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8210 }
1da177e4
LT		 8211
8212 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8213 sizeof(tp->net_stats_prev));
8214 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8215 sizeof(tp->estats_prev));
8216
8217 tg3_free_consistent(tp);
8218
bc1c7567
MC		 8219 tg3_set_power_state(tp, PCI_D3hot);
8220
8221 netif_carrier_off(tp->dev);
8222
1da177e4
LT		 8223 return 0;
8224}
8225
8226static inline unsigned long get_stat64(tg3_stat64_t *val)
8227{
8228 unsigned long ret;
8229
8230#if (BITS_PER_LONG == 32)
8231 ret = val->low;
8232#else
8233 ret = ((u64)val->high << 32) | ((u64)val->low);
8234#endif
8235 return ret;
8236}
8237
816f8b86
SB		 8238static inline u64 get_estat64(tg3_stat64_t *val)
8239{
8240 return ((u64)val->high << 32) | ((u64)val->low);
8241}
8242
1da177e4
LT		 8243static unsigned long calc_crc_errors(struct tg3 *tp)
8244{
8245 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8246
8247 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8248 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8250 u32 val;
8251
f47c11ee 8252 spin_lock_bh(&tp->lock);
569a5df8
MC		 8253 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8254 tg3_writephy(tp, MII_TG3_TEST1,
8255 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8256 tg3_readphy(tp, 0x14, &val);
8257 } else
8258 val = 0;
f47c11ee 8259 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8260
8261 tp->phy_crc_errors += val;
8262
8263 return tp->phy_crc_errors;
8264 }
8265
8266 return get_stat64(&hw_stats->rx_fcs_errors);
8267}
8268
8269#define ESTAT_ADD(member) \
8270 estats->member = old_estats->member + \
816f8b86 8271 get_estat64(&hw_stats->member)
1da177e4
LT		 8272
8273static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8274{
8275 struct tg3_ethtool_stats *estats = &tp->estats;
8276 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8277 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8278
8279 if (!hw_stats)
8280 return old_estats;
8281
8282 ESTAT_ADD(rx_octets);
8283 ESTAT_ADD(rx_fragments);
8284 ESTAT_ADD(rx_ucast_packets);
8285 ESTAT_ADD(rx_mcast_packets);
8286 ESTAT_ADD(rx_bcast_packets);
8287 ESTAT_ADD(rx_fcs_errors);
8288 ESTAT_ADD(rx_align_errors);
8289 ESTAT_ADD(rx_xon_pause_rcvd);
8290 ESTAT_ADD(rx_xoff_pause_rcvd);
8291 ESTAT_ADD(rx_mac_ctrl_rcvd);
8292 ESTAT_ADD(rx_xoff_entered);
8293 ESTAT_ADD(rx_frame_too_long_errors);
8294 ESTAT_ADD(rx_jabbers);
8295 ESTAT_ADD(rx_undersize_packets);
8296 ESTAT_ADD(rx_in_length_errors);
8297 ESTAT_ADD(rx_out_length_errors);
8298 ESTAT_ADD(rx_64_or_less_octet_packets);
8299 ESTAT_ADD(rx_65_to_127_octet_packets);
8300 ESTAT_ADD(rx_128_to_255_octet_packets);
8301 ESTAT_ADD(rx_256_to_511_octet_packets);
8302 ESTAT_ADD(rx_512_to_1023_octet_packets);
8303 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8304 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8305 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8306 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8307 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8308
8309 ESTAT_ADD(tx_octets);
8310 ESTAT_ADD(tx_collisions);
8311 ESTAT_ADD(tx_xon_sent);
8312 ESTAT_ADD(tx_xoff_sent);
8313 ESTAT_ADD(tx_flow_control);
8314 ESTAT_ADD(tx_mac_errors);
8315 ESTAT_ADD(tx_single_collisions);
8316 ESTAT_ADD(tx_mult_collisions);
8317 ESTAT_ADD(tx_deferred);
8318 ESTAT_ADD(tx_excessive_collisions);
8319 ESTAT_ADD(tx_late_collisions);
8320 ESTAT_ADD(tx_collide_2times);
8321 ESTAT_ADD(tx_collide_3times);
8322 ESTAT_ADD(tx_collide_4times);
8323 ESTAT_ADD(tx_collide_5times);
8324 ESTAT_ADD(tx_collide_6times);
8325 ESTAT_ADD(tx_collide_7times);
8326 ESTAT_ADD(tx_collide_8times);
8327 ESTAT_ADD(tx_collide_9times);
8328 ESTAT_ADD(tx_collide_10times);
8329 ESTAT_ADD(tx_collide_11times);
8330 ESTAT_ADD(tx_collide_12times);
8331 ESTAT_ADD(tx_collide_13times);
8332 ESTAT_ADD(tx_collide_14times);
8333 ESTAT_ADD(tx_collide_15times);
8334 ESTAT_ADD(tx_ucast_packets);
8335 ESTAT_ADD(tx_mcast_packets);
8336 ESTAT_ADD(tx_bcast_packets);
8337 ESTAT_ADD(tx_carrier_sense_errors);
8338 ESTAT_ADD(tx_discards);
8339 ESTAT_ADD(tx_errors);
8340
8341 ESTAT_ADD(dma_writeq_full);
8342 ESTAT_ADD(dma_write_prioq_full);
8343 ESTAT_ADD(rxbds_empty);
8344 ESTAT_ADD(rx_discards);
8345 ESTAT_ADD(rx_errors);
8346 ESTAT_ADD(rx_threshold_hit);
8347
8348 ESTAT_ADD(dma_readq_full);
8349 ESTAT_ADD(dma_read_prioq_full);
8350 ESTAT_ADD(tx_comp_queue_full);
8351
8352 ESTAT_ADD(ring_set_send_prod_index);
8353 ESTAT_ADD(ring_status_update);
8354 ESTAT_ADD(nic_irqs);
8355 ESTAT_ADD(nic_avoided_irqs);
8356 ESTAT_ADD(nic_tx_threshold_hit);
8357
8358 return estats;
8359}
8360
8361static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8362{
8363 struct tg3 *tp = netdev_priv(dev);
8364 struct net_device_stats *stats = &tp->net_stats;
8365 struct net_device_stats *old_stats = &tp->net_stats_prev;
8366 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8367
8368 if (!hw_stats)
8369 return old_stats;
8370
8371 stats->rx_packets = old_stats->rx_packets +
8372 get_stat64(&hw_stats->rx_ucast_packets) +
8373 get_stat64(&hw_stats->rx_mcast_packets) +
8374 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8375
1da177e4
LT		 8376 stats->tx_packets = old_stats->tx_packets +
8377 get_stat64(&hw_stats->tx_ucast_packets) +
8378 get_stat64(&hw_stats->tx_mcast_packets) +
8379 get_stat64(&hw_stats->tx_bcast_packets);
8380
8381 stats->rx_bytes = old_stats->rx_bytes +
8382 get_stat64(&hw_stats->rx_octets);
8383 stats->tx_bytes = old_stats->tx_bytes +
8384 get_stat64(&hw_stats->tx_octets);
8385
8386 stats->rx_errors = old_stats->rx_errors +
4f63b877 8387 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8388 stats->tx_errors = old_stats->tx_errors +
8389 get_stat64(&hw_stats->tx_errors) +
8390 get_stat64(&hw_stats->tx_mac_errors) +
8391 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8392 get_stat64(&hw_stats->tx_discards);
8393
8394 stats->multicast = old_stats->multicast +
8395 get_stat64(&hw_stats->rx_mcast_packets);
8396 stats->collisions = old_stats->collisions +
8397 get_stat64(&hw_stats->tx_collisions);
8398
8399 stats->rx_length_errors = old_stats->rx_length_errors +
8400 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8401 get_stat64(&hw_stats->rx_undersize_packets);
8402
8403 stats->rx_over_errors = old_stats->rx_over_errors +
8404 get_stat64(&hw_stats->rxbds_empty);
8405 stats->rx_frame_errors = old_stats->rx_frame_errors +
8406 get_stat64(&hw_stats->rx_align_errors);
8407 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8408 get_stat64(&hw_stats->tx_discards);
8409 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8410 get_stat64(&hw_stats->tx_carrier_sense_errors);
8411
8412 stats->rx_crc_errors = old_stats->rx_crc_errors +
8413 calc_crc_errors(tp);
8414
4f63b877
JL		 8415 stats->rx_missed_errors = old_stats->rx_missed_errors +
8416 get_stat64(&hw_stats->rx_discards);
8417
1da177e4
LT		 8418 return stats;
8419}
8420
8421static inline u32 calc_crc(unsigned char *buf, int len)
8422{
8423 u32 reg;
8424 u32 tmp;
8425 int j, k;
8426
8427 reg = 0xffffffff;
8428
8429 for (j = 0; j < len; j++) {
8430 reg ^= buf[j];
8431
8432 for (k = 0; k < 8; k++) {
8433 tmp = reg & 0x01;
8434
8435 reg >>= 1;
8436
8437 if (tmp) {
8438 reg ^= 0xedb88320;
8439 }
8440 }
8441 }
8442
8443 return ~reg;
8444}
8445
8446static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8447{
8448 /* accept or reject all multicast frames */
8449 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8450 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8451 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8452 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8453}
8454
8455static void __tg3_set_rx_mode(struct net_device *dev)
8456{
8457 struct tg3 *tp = netdev_priv(dev);
8458 u32 rx_mode;
8459
8460 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8461 RX_MODE_KEEP_VLAN_TAG);
8462
8463 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8464 * flag clear.
8465 */
8466#if TG3_VLAN_TAG_USED
8467 if (!tp->vlgrp &&
8468 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8469 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8470#else
8471 /* By definition, VLAN is disabled always in this
8472 * case.
8473 */
8474 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8475 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8476#endif
8477
8478 if (dev->flags & IFF_PROMISC) {
8479 /* Promiscuous mode. */
8480 rx_mode |= RX_MODE_PROMISC;
8481 } else if (dev->flags & IFF_ALLMULTI) {
8482 /* Accept all multicast. */
8483 tg3_set_multi (tp, 1);
8484 } else if (dev->mc_count < 1) {
8485 /* Reject all multicast. */
8486 tg3_set_multi (tp, 0);
8487 } else {
8488 /* Accept one or more multicast(s). */
8489 struct dev_mc_list *mclist;
8490 unsigned int i;
8491 u32 mc_filter[4] = { 0, };
8492 u32 regidx;
8493 u32 bit;
8494 u32 crc;
8495
8496 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8497 i++, mclist = mclist->next) {
8498
8499 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8500 bit = ~crc & 0x7f;
8501 regidx = (bit & 0x60) >> 5;
8502 bit &= 0x1f;
8503 mc_filter[regidx] |= (1 << bit);
8504 }
8505
8506 tw32(MAC_HASH_REG_0, mc_filter[0]);
8507 tw32(MAC_HASH_REG_1, mc_filter[1]);
8508 tw32(MAC_HASH_REG_2, mc_filter[2]);
8509 tw32(MAC_HASH_REG_3, mc_filter[3]);
8510 }
8511
8512 if (rx_mode != tp->rx_mode) {
8513 tp->rx_mode = rx_mode;
8514 tw32_f(MAC_RX_MODE, rx_mode);
8515 udelay(10);
8516 }
8517}
8518
8519static void tg3_set_rx_mode(struct net_device *dev)
8520{
8521 struct tg3 *tp = netdev_priv(dev);
8522
e75f7c90
MC		 8523 if (!netif_running(dev))
8524 return;
8525
f47c11ee 8526 tg3_full_lock(tp, 0);
1da177e4 8527 __tg3_set_rx_mode(dev);
f47c11ee 8528 tg3_full_unlock(tp);
1da177e4
LT		 8529}
8530
8531#define TG3_REGDUMP_LEN (32 * 1024)
8532
8533static int tg3_get_regs_len(struct net_device *dev)
8534{
8535 return TG3_REGDUMP_LEN;
8536}
8537
8538static void tg3_get_regs(struct net_device *dev,
8539 struct ethtool_regs *regs, void *_p)
8540{
8541 u32 *p = _p;
8542 struct tg3 *tp = netdev_priv(dev);
8543 u8 *orig_p = _p;
8544 int i;
8545
8546 regs->version = 0;
8547
8548 memset(p, 0, TG3_REGDUMP_LEN);
8549
bc1c7567
MC		 8550 if (tp->link_config.phy_is_low_power)
8551 return;
8552
f47c11ee 8553 tg3_full_lock(tp, 0);
1da177e4
LT		 8554
8555#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8556#define GET_REG32_LOOP(base,len) \
8557do { p = (u32 *)(orig_p + (base)); \
8558 for (i = 0; i < len; i += 4) \
8559 __GET_REG32((base) + i); \
8560} while (0)
8561#define GET_REG32_1(reg) \
8562do { p = (u32 *)(orig_p + (reg)); \
8563 __GET_REG32((reg)); \
8564} while (0)
8565
8566 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8567 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8568 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8569 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8570 GET_REG32_1(SNDDATAC_MODE);
8571 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8572 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8573 GET_REG32_1(SNDBDC_MODE);
8574 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8575 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8576 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8577 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8578 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8579 GET_REG32_1(RCVDCC_MODE);
8580 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8581 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8582 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8583 GET_REG32_1(MBFREE_MODE);
8584 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8585 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8586 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8587 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8588 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8589 GET_REG32_1(RX_CPU_MODE);
8590 GET_REG32_1(RX_CPU_STATE);
8591 GET_REG32_1(RX_CPU_PGMCTR);
8592 GET_REG32_1(RX_CPU_HWBKPT);
8593 GET_REG32_1(TX_CPU_MODE);
8594 GET_REG32_1(TX_CPU_STATE);
8595 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8596 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8597 GET_REG32_LOOP(FTQ_RESET, 0x120);
8598 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8599 GET_REG32_1(DMAC_MODE);
8600 GET_REG32_LOOP(GRC_MODE, 0x4c);
8601 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8602 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8603
8604#undef __GET_REG32
8605#undef GET_REG32_LOOP
8606#undef GET_REG32_1
8607
f47c11ee 8608 tg3_full_unlock(tp);
1da177e4
LT		 8609}
8610
8611static int tg3_get_eeprom_len(struct net_device *dev)
8612{
8613 struct tg3 *tp = netdev_priv(dev);
8614
8615 return tp->nvram_size;
8616}
8617
1da177e4
LT		 8618static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8619{
8620 struct tg3 *tp = netdev_priv(dev);
8621 int ret;
8622 u8 *pd;
b9fc7dc5 8623 u32 i, offset, len, b_offset, b_count;
a9dc529d 8624 __be32 val;
1da177e4 8625
df259d8c
MC		 8626 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8627 return -EINVAL;
8628
bc1c7567
MC		 8629 if (tp->link_config.phy_is_low_power)
8630 return -EAGAIN;
8631
1da177e4
LT		 8632 offset = eeprom->offset;
8633 len = eeprom->len;
8634 eeprom->len = 0;
8635
8636 eeprom->magic = TG3_EEPROM_MAGIC;
8637
8638 if (offset & 3) {
8639 /* adjustments to start on required 4 byte boundary */
8640 b_offset = offset & 3;
8641 b_count = 4 - b_offset;
8642 if (b_count > len) {
8643 /* i.e. offset=1 len=2 */
8644 b_count = len;
8645 }
a9dc529d 8646 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8647 if (ret)
8648 return ret;
1da177e4
LT		 8649 memcpy(data, ((char*)&val) + b_offset, b_count);
8650 len -= b_count;
8651 offset += b_count;
8652 eeprom->len += b_count;
8653 }
8654
8655 /* read bytes upto the last 4 byte boundary */
8656 pd = &data[eeprom->len];
8657 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8658 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8659 if (ret) {
8660 eeprom->len += i;
8661 return ret;
8662 }
1da177e4
LT		 8663 memcpy(pd + i, &val, 4);
8664 }
8665 eeprom->len += i;
8666
8667 if (len & 3) {
8668 /* read last bytes not ending on 4 byte boundary */
8669 pd = &data[eeprom->len];
8670 b_count = len & 3;
8671 b_offset = offset + len - b_count;
a9dc529d 8672 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8673 if (ret)
8674 return ret;
b9fc7dc5 8675 memcpy(pd, &val, b_count);
1da177e4
LT		 8676 eeprom->len += b_count;
8677 }
8678 return 0;
8679}
8680
6aa20a22 8681static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8682
8683static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8684{
8685 struct tg3 *tp = netdev_priv(dev);
8686 int ret;
b9fc7dc5 8687 u32 offset, len, b_offset, odd_len;
1da177e4 8688 u8 *buf;
a9dc529d 8689 __be32 start, end;
1da177e4 8690
bc1c7567
MC		 8691 if (tp->link_config.phy_is_low_power)
8692 return -EAGAIN;
8693
df259d8c
MC		 8694 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8695 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8696 return -EINVAL;
8697
8698 offset = eeprom->offset;
8699 len = eeprom->len;
8700
8701 if ((b_offset = (offset & 3))) {
8702 /* adjustments to start on required 4 byte boundary */
a9dc529d 8703 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8704 if (ret)
8705 return ret;
1da177e4
LT		 8706 len += b_offset;
8707 offset &= ~3;
1c8594b4
MC		 8708 if (len < 4)
8709 len = 4;
1da177e4
LT		 8710 }
8711
8712 odd_len = 0;
1c8594b4 8713 if (len & 3) {
1da177e4
LT		 8714 /* adjustments to end on required 4 byte boundary */
8715 odd_len = 1;
8716 len = (len + 3) & ~3;
a9dc529d 8717 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8718 if (ret)
8719 return ret;
1da177e4
LT		 8720 }
8721
8722 buf = data;
8723 if (b_offset || odd_len) {
8724 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8725 if (!buf)
1da177e4
LT		 8726 return -ENOMEM;
8727 if (b_offset)
8728 memcpy(buf, &start, 4);
8729 if (odd_len)
8730 memcpy(buf+len-4, &end, 4);
8731 memcpy(buf + b_offset, data, eeprom->len);
8732 }
8733
8734 ret = tg3_nvram_write_block(tp, offset, len, buf);
8735
8736 if (buf != data)
8737 kfree(buf);
8738
8739 return ret;
8740}
8741
8742static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8743{
b02fd9e3
MC		 8744 struct tg3 *tp = netdev_priv(dev);
8745
8746 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8747 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8748 return -EAGAIN;
298cf9be 8749 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8750 }
6aa20a22 8751
1da177e4
LT		 8752 cmd->supported = (SUPPORTED_Autoneg);
8753
8754 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8755 cmd->supported |= (SUPPORTED_1000baseT_Half |
8756 SUPPORTED_1000baseT_Full);
8757
ef348144 8758 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8759 cmd->supported |= (SUPPORTED_100baseT_Half |
8760 SUPPORTED_100baseT_Full |
8761 SUPPORTED_10baseT_Half |
8762 SUPPORTED_10baseT_Full |
3bebab59 8763 SUPPORTED_TP);
ef348144
KK		 8764 cmd->port = PORT_TP;
8765 } else {
1da177e4 8766 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8767 cmd->port = PORT_FIBRE;
8768 }
6aa20a22 8769
1da177e4
LT		 8770 cmd->advertising = tp->link_config.advertising;
8771 if (netif_running(dev)) {
8772 cmd->speed = tp->link_config.active_speed;
8773 cmd->duplex = tp->link_config.active_duplex;
8774 }
1da177e4 8775 cmd->phy_address = PHY_ADDR;
7e5856bd 8776 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8777 cmd->autoneg = tp->link_config.autoneg;
8778 cmd->maxtxpkt = 0;
8779 cmd->maxrxpkt = 0;
8780 return 0;
8781}
6aa20a22 8782
1da177e4
LT		 8783static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8784{
8785 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8786
b02fd9e3
MC		 8787 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8788 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8789 return -EAGAIN;
298cf9be 8790 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8791 }
8792
7e5856bd
MC		 8793 if (cmd->autoneg != AUTONEG_ENABLE &&
8794 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8795 return -EINVAL;
7e5856bd
MC		 8796
8797 if (cmd->autoneg == AUTONEG_DISABLE &&
8798 cmd->duplex != DUPLEX_FULL &&
8799 cmd->duplex != DUPLEX_HALF)
37ff238d 8800 return -EINVAL;
1da177e4 8801
7e5856bd
MC		 8802 if (cmd->autoneg == AUTONEG_ENABLE) {
8803 u32 mask = ADVERTISED_Autoneg |
8804 ADVERTISED_Pause |
8805 ADVERTISED_Asym_Pause;
8806
8807 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8808 mask |= ADVERTISED_1000baseT_Half |
8809 ADVERTISED_1000baseT_Full;
8810
8811 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8812 mask |= ADVERTISED_100baseT_Half |
8813 ADVERTISED_100baseT_Full |
8814 ADVERTISED_10baseT_Half |
8815 ADVERTISED_10baseT_Full |
8816 ADVERTISED_TP;
8817 else
8818 mask |= ADVERTISED_FIBRE;
8819
8820 if (cmd->advertising & ~mask)
8821 return -EINVAL;
8822
8823 mask &= (ADVERTISED_1000baseT_Half |
8824 ADVERTISED_1000baseT_Full |
8825 ADVERTISED_100baseT_Half |
8826 ADVERTISED_100baseT_Full |
8827 ADVERTISED_10baseT_Half |
8828 ADVERTISED_10baseT_Full);
8829
8830 cmd->advertising &= mask;
8831 } else {
8832 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8833 if (cmd->speed != SPEED_1000)
8834 return -EINVAL;
8835
8836 if (cmd->duplex != DUPLEX_FULL)
8837 return -EINVAL;
8838 } else {
8839 if (cmd->speed != SPEED_100 &&
8840 cmd->speed != SPEED_10)
8841 return -EINVAL;
8842 }
8843 }
8844
f47c11ee 8845 tg3_full_lock(tp, 0);
1da177e4
LT		 8846
8847 tp->link_config.autoneg = cmd->autoneg;
8848 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8849 tp->link_config.advertising = (cmd->advertising |
8850 ADVERTISED_Autoneg);
1da177e4
LT		 8851 tp->link_config.speed = SPEED_INVALID;
8852 tp->link_config.duplex = DUPLEX_INVALID;
8853 } else {
8854 tp->link_config.advertising = 0;
8855 tp->link_config.speed = cmd->speed;
8856 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8857 }
6aa20a22 8858
24fcad6b
MC		 8859 tp->link_config.orig_speed = tp->link_config.speed;
8860 tp->link_config.orig_duplex = tp->link_config.duplex;
8861 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8862
1da177e4
LT		 8863 if (netif_running(dev))
8864 tg3_setup_phy(tp, 1);
8865
f47c11ee 8866 tg3_full_unlock(tp);
6aa20a22 8867
1da177e4
LT		 8868 return 0;
8869}
6aa20a22 8870
1da177e4
LT		 8871static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8872{
8873 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8874
1da177e4
LT		 8875 strcpy(info->driver, DRV_MODULE_NAME);
8876 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8877 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8878 strcpy(info->bus_info, pci_name(tp->pdev));
8879}
6aa20a22 8880
1da177e4
LT		 8881static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8882{
8883 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8884
12dac075
RW		 8885 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8886 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8887 wol->supported = WAKE_MAGIC;
8888 else
8889 wol->supported = 0;
1da177e4 8890 wol->wolopts = 0;
05ac4cb7
MC		 8891 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8892 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8893 wol->wolopts = WAKE_MAGIC;
8894 memset(&wol->sopass, 0, sizeof(wol->sopass));
8895}
6aa20a22 8896
1da177e4
LT		 8897static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8898{
8899 struct tg3 *tp = netdev_priv(dev);
12dac075 8900 struct device *dp = &tp->pdev->dev;
6aa20a22 8901
1da177e4
LT		 8902 if (wol->wolopts & ~WAKE_MAGIC)
8903 return -EINVAL;
8904 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8905 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8906 return -EINVAL;
6aa20a22 8907
f47c11ee 8908 spin_lock_bh(&tp->lock);
12dac075 8909 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8910 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8911 device_set_wakeup_enable(dp, true);
8912 } else {
1da177e4 8913 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8914 device_set_wakeup_enable(dp, false);
8915 }
f47c11ee 8916 spin_unlock_bh(&tp->lock);
6aa20a22 8917
1da177e4
LT		 8918 return 0;
8919}
6aa20a22 8920
1da177e4
LT		 8921static u32 tg3_get_msglevel(struct net_device *dev)
8922{
8923 struct tg3 *tp = netdev_priv(dev);
8924 return tp->msg_enable;
8925}
6aa20a22 8926
1da177e4
LT		 8927static void tg3_set_msglevel(struct net_device *dev, u32 value)
8928{
8929 struct tg3 *tp = netdev_priv(dev);
8930 tp->msg_enable = value;
8931}
6aa20a22 8932
1da177e4
LT		 8933static int tg3_set_tso(struct net_device *dev, u32 value)
8934{
8935 struct tg3 *tp = netdev_priv(dev);
8936
8937 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8938 if (value)
8939 return -EINVAL;
8940 return 0;
8941 }
027455ad
MC		 8942 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8943 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8944 if (value) {
b0026624 8945 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8947 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8948 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8951 dev->features |= NETIF_F_TSO_ECN;
8952 } else
8953 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8954 }
1da177e4
LT		 8955 return ethtool_op_set_tso(dev, value);
8956}
6aa20a22 8957
1da177e4
LT		 8958static int tg3_nway_reset(struct net_device *dev)
8959{
8960 struct tg3 *tp = netdev_priv(dev);
1da177e4 8961 int r;
6aa20a22 8962
1da177e4
LT		 8963 if (!netif_running(dev))
8964 return -EAGAIN;
8965
c94e3941
MC		 8966 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8967 return -EINVAL;
8968
b02fd9e3
MC		 8969 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8970 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8971 return -EAGAIN;
298cf9be 8972 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8973 } else {
8974 u32 bmcr;
8975
8976 spin_lock_bh(&tp->lock);
8977 r = -EINVAL;
8978 tg3_readphy(tp, MII_BMCR, &bmcr);
8979 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8980 ((bmcr & BMCR_ANENABLE) ||
8981 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8982 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8983 BMCR_ANENABLE);
8984 r = 0;
8985 }
8986 spin_unlock_bh(&tp->lock);
1da177e4 8987 }
6aa20a22 8988
1da177e4
LT		 8989 return r;
8990}
6aa20a22 8991
1da177e4
LT		 8992static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8993{
8994 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8995
1da177e4
LT		 8996 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8997 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8998 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8999 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9000 else
9001 ering->rx_jumbo_max_pending = 0;
9002
9003 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9004
9005 ering->rx_pending = tp->rx_pending;
9006 ering->rx_mini_pending = 0;
4f81c32b
MC		 9007 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9008 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9009 else
9010 ering->rx_jumbo_pending = 0;
9011
1da177e4
LT		 9012 ering->tx_pending = tp->tx_pending;
9013}
6aa20a22 9014
1da177e4
LT		 9015static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9016{
9017 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9018 int irq_sync = 0, err = 0;
6aa20a22 9019
1da177e4
LT		 9020 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9021 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9022 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9023 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9024 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9025 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9026 return -EINVAL;
6aa20a22 9027
bbe832c0 9028 if (netif_running(dev)) {
b02fd9e3 9029 tg3_phy_stop(tp);
1da177e4 9030 tg3_netif_stop(tp);
bbe832c0
MC		 9031 irq_sync = 1;
9032 }
1da177e4 9033
bbe832c0 9034 tg3_full_lock(tp, irq_sync);
6aa20a22 9035
1da177e4
LT		 9036 tp->rx_pending = ering->rx_pending;
9037
9038 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9039 tp->rx_pending > 63)
9040 tp->rx_pending = 63;
9041 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9042 tp->tx_pending = ering->tx_pending;
9043
9044 if (netif_running(dev)) {
944d980e 9045 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9046 err = tg3_restart_hw(tp, 1);
9047 if (!err)
9048 tg3_netif_start(tp);
1da177e4
LT		 9049 }
9050
f47c11ee 9051 tg3_full_unlock(tp);
6aa20a22 9052
b02fd9e3
MC		 9053 if (irq_sync && !err)
9054 tg3_phy_start(tp);
9055
b9ec6c1b 9056 return err;
1da177e4 9057}
6aa20a22 9058
1da177e4
LT		 9059static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9060{
9061 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9062
1da177e4 9063 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9064
e18ce346 9065 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9066 epause->rx_pause = 1;
9067 else
9068 epause->rx_pause = 0;
9069
e18ce346 9070 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9071 epause->tx_pause = 1;
9072 else
9073 epause->tx_pause = 0;
1da177e4 9074}
6aa20a22 9075
1da177e4
LT		 9076static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9077{
9078 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9079 int err = 0;
6aa20a22 9080
b02fd9e3
MC		 9081 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9082 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9083 return -EAGAIN;
1da177e4 9084
b02fd9e3
MC		 9085 if (epause->autoneg) {
9086 u32 newadv;
9087 struct phy_device *phydev;
f47c11ee 9088
298cf9be 9089 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9090
b02fd9e3
MC		 9091 if (epause->rx_pause) {
9092 if (epause->tx_pause)
9093 newadv = ADVERTISED_Pause;
9094 else
9095 newadv = ADVERTISED_Pause |
9096 ADVERTISED_Asym_Pause;
9097 } else if (epause->tx_pause) {
9098 newadv = ADVERTISED_Asym_Pause;
9099 } else
9100 newadv = 0;
9101
9102 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9103 u32 oldadv = phydev->advertising &
9104 (ADVERTISED_Pause |
9105 ADVERTISED_Asym_Pause);
9106 if (oldadv != newadv) {
9107 phydev->advertising &=
9108 ~(ADVERTISED_Pause |
9109 ADVERTISED_Asym_Pause);
9110 phydev->advertising |= newadv;
9111 err = phy_start_aneg(phydev);
9112 }
9113 } else {
9114 tp->link_config.advertising &=
9115 ~(ADVERTISED_Pause |
9116 ADVERTISED_Asym_Pause);
9117 tp->link_config.advertising |= newadv;
9118 }
9119 } else {
9120 if (epause->rx_pause)
e18ce346 9121 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9122 else
e18ce346 9123 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9124
b02fd9e3 9125 if (epause->tx_pause)
e18ce346 9126 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9127 else
e18ce346 9128 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9129
9130 if (netif_running(dev))
9131 tg3_setup_flow_control(tp, 0, 0);
9132 }
9133 } else {
9134 int irq_sync = 0;
9135
9136 if (netif_running(dev)) {
9137 tg3_netif_stop(tp);
9138 irq_sync = 1;
9139 }
9140
9141 tg3_full_lock(tp, irq_sync);
9142
9143 if (epause->autoneg)
9144 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9145 else
9146 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9147 if (epause->rx_pause)
e18ce346 9148 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9149 else
e18ce346 9150 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9151 if (epause->tx_pause)
e18ce346 9152 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9153 else
e18ce346 9154 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9155
9156 if (netif_running(dev)) {
9157 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9158 err = tg3_restart_hw(tp, 1);
9159 if (!err)
9160 tg3_netif_start(tp);
9161 }
9162
9163 tg3_full_unlock(tp);
9164 }
6aa20a22 9165
b9ec6c1b 9166 return err;
1da177e4 9167}
6aa20a22 9168
1da177e4
LT		 9169static u32 tg3_get_rx_csum(struct net_device *dev)
9170{
9171 struct tg3 *tp = netdev_priv(dev);
9172 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9173}
6aa20a22 9174
1da177e4
LT		 9175static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9176{
9177 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9178
1da177e4
LT		 9179 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9180 if (data != 0)
9181 return -EINVAL;
9182 return 0;
9183 }
6aa20a22 9184
f47c11ee 9185 spin_lock_bh(&tp->lock);
1da177e4
LT		 9186 if (data)
9187 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9188 else
9189 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9190 spin_unlock_bh(&tp->lock);
6aa20a22 9191
1da177e4
LT		 9192 return 0;
9193}
6aa20a22 9194
1da177e4
LT		 9195static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9196{
9197 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9198
1da177e4
LT		 9199 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9200 if (data != 0)
9201 return -EINVAL;
9202 return 0;
9203 }
6aa20a22 9204
321d32a0 9205 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9206 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9207 else
9c27dbdf 9208 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9209
9210 return 0;
9211}
9212
b9f2c044 9213static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9214{
b9f2c044
JG		 9215 switch (sset) {
9216 case ETH_SS_TEST:
9217 return TG3_NUM_TEST;
9218 case ETH_SS_STATS:
9219 return TG3_NUM_STATS;
9220 default:
9221 return -EOPNOTSUPP;
9222 }
4cafd3f5
MC		 9223}
9224
1da177e4
LT		 9225static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9226{
9227 switch (stringset) {
9228 case ETH_SS_STATS:
9229 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9230 break;
4cafd3f5
MC		 9231 case ETH_SS_TEST:
9232 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9233 break;
1da177e4
LT		 9234 default:
9235 WARN_ON(1); /* we need a WARN() */
9236 break;
9237 }
9238}
9239
4009a93d
MC		 9240static int tg3_phys_id(struct net_device *dev, u32 data)
9241{
9242 struct tg3 *tp = netdev_priv(dev);
9243 int i;
9244
9245 if (!netif_running(tp->dev))
9246 return -EAGAIN;
9247
9248 if (data == 0)
759afc31 9249 data = UINT_MAX / 2;
4009a93d
MC		 9250
9251 for (i = 0; i < (data * 2); i++) {
9252 if ((i % 2) == 0)
9253 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9254 LED_CTRL_1000MBPS_ON |
9255 LED_CTRL_100MBPS_ON |
9256 LED_CTRL_10MBPS_ON |
9257 LED_CTRL_TRAFFIC_OVERRIDE |
9258 LED_CTRL_TRAFFIC_BLINK |
9259 LED_CTRL_TRAFFIC_LED);
6aa20a22 9260
4009a93d
MC		 9261 else
9262 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9263 LED_CTRL_TRAFFIC_OVERRIDE);
9264
9265 if (msleep_interruptible(500))
9266 break;
9267 }
9268 tw32(MAC_LED_CTRL, tp->led_ctrl);
9269 return 0;
9270}
9271
1da177e4
LT		 9272static void tg3_get_ethtool_stats (struct net_device *dev,
9273 struct ethtool_stats *estats, u64 *tmp_stats)
9274{
9275 struct tg3 *tp = netdev_priv(dev);
9276 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9277}
9278
566f86ad 9279#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9280#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9281#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9282#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9283#define NVRAM_SELFBOOT_HW_SIZE 0x20
9284#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9285
9286static int tg3_test_nvram(struct tg3 *tp)
9287{
b9fc7dc5 9288 u32 csum, magic;
a9dc529d 9289 __be32 *buf;
ab0049b4 9290 int i, j, k, err = 0, size;
566f86ad 9291
df259d8c
MC		 9292 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9293 return 0;
9294
e4f34110 9295 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9296 return -EIO;
9297
1b27777a
MC		 9298 if (magic == TG3_EEPROM_MAGIC)
9299 size = NVRAM_TEST_SIZE;
b16250e3 9300 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9301 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9302 TG3_EEPROM_SB_FORMAT_1) {
9303 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9304 case TG3_EEPROM_SB_REVISION_0:
9305 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9306 break;
9307 case TG3_EEPROM_SB_REVISION_2:
9308 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9309 break;
9310 case TG3_EEPROM_SB_REVISION_3:
9311 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9312 break;
9313 default:
9314 return 0;
9315 }
9316 } else
1b27777a 9317 return 0;
b16250e3
MC		 9318 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9319 size = NVRAM_SELFBOOT_HW_SIZE;
9320 else
1b27777a
MC		 9321 return -EIO;
9322
9323 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9324 if (buf == NULL)
9325 return -ENOMEM;
9326
1b27777a
MC		 9327 err = -EIO;
9328 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9329 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9330 if (err)
566f86ad 9331 break;
566f86ad 9332 }
1b27777a 9333 if (i < size)
566f86ad
MC		 9334 goto out;
9335
1b27777a 9336 /* Selfboot format */
a9dc529d 9337 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9338 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9339 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9340 u8 *buf8 = (u8 *) buf, csum8 = 0;
9341
b9fc7dc5 9342 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9343 TG3_EEPROM_SB_REVISION_2) {
9344 /* For rev 2, the csum doesn't include the MBA. */
9345 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9346 csum8 += buf8[i];
9347 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9348 csum8 += buf8[i];
9349 } else {
9350 for (i = 0; i < size; i++)
9351 csum8 += buf8[i];
9352 }
1b27777a 9353
ad96b485
AB		 9354 if (csum8 == 0) {
9355 err = 0;
9356 goto out;
9357 }
9358
9359 err = -EIO;
9360 goto out;
1b27777a 9361 }
566f86ad 9362
b9fc7dc5 9363 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9364 TG3_EEPROM_MAGIC_HW) {
9365 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9366 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9367 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9368
9369 /* Separate the parity bits and the data bytes. */
9370 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9371 if ((i == 0) || (i == 8)) {
9372 int l;
9373 u8 msk;
9374
9375 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9376 parity[k++] = buf8[i] & msk;
9377 i++;
9378 }
9379 else if (i == 16) {
9380 int l;
9381 u8 msk;
9382
9383 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9384 parity[k++] = buf8[i] & msk;
9385 i++;
9386
9387 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9388 parity[k++] = buf8[i] & msk;
9389 i++;
9390 }
9391 data[j++] = buf8[i];
9392 }
9393
9394 err = -EIO;
9395 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9396 u8 hw8 = hweight8(data[i]);
9397
9398 if ((hw8 & 0x1) && parity[i])
9399 goto out;
9400 else if (!(hw8 & 0x1) && !parity[i])
9401 goto out;
9402 }
9403 err = 0;
9404 goto out;
9405 }
9406
566f86ad
MC		 9407 /* Bootstrap checksum at offset 0x10 */
9408 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9409 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9410 goto out;
9411
9412 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9413 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9414 if (csum != be32_to_cpu(buf[0xfc/4]))
9415 goto out;
566f86ad
MC		 9416
9417 err = 0;
9418
9419out:
9420 kfree(buf);
9421 return err;
9422}
9423
ca43007a
MC		 9424#define TG3_SERDES_TIMEOUT_SEC 2
9425#define TG3_COPPER_TIMEOUT_SEC 6
9426
9427static int tg3_test_link(struct tg3 *tp)
9428{
9429 int i, max;
9430
9431 if (!netif_running(tp->dev))
9432 return -ENODEV;
9433
4c987487 9434 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9435 max = TG3_SERDES_TIMEOUT_SEC;
9436 else
9437 max = TG3_COPPER_TIMEOUT_SEC;
9438
9439 for (i = 0; i < max; i++) {
9440 if (netif_carrier_ok(tp->dev))
9441 return 0;
9442
9443 if (msleep_interruptible(1000))
9444 break;
9445 }
9446
9447 return -EIO;
9448}
9449
a71116d1 9450/* Only test the commonly used registers */
30ca3e37 9451static int tg3_test_registers(struct tg3 *tp)
a71116d1 9452{
b16250e3 9453 int i, is_5705, is_5750;
a71116d1
MC		 9454 u32 offset, read_mask, write_mask, val, save_val, read_val;
9455 static struct {
9456 u16 offset;
9457 u16 flags;
9458#define TG3_FL_5705 0x1
9459#define TG3_FL_NOT_5705 0x2
9460#define TG3_FL_NOT_5788 0x4
b16250e3 9461#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9462 u32 read_mask;
9463 u32 write_mask;
9464 } reg_tbl[] = {
9465 /* MAC Control Registers */
9466 { MAC_MODE, TG3_FL_NOT_5705,
9467 0x00000000, 0x00ef6f8c },
9468 { MAC_MODE, TG3_FL_5705,
9469 0x00000000, 0x01ef6b8c },
9470 { MAC_STATUS, TG3_FL_NOT_5705,
9471 0x03800107, 0x00000000 },
9472 { MAC_STATUS, TG3_FL_5705,
9473 0x03800100, 0x00000000 },
9474 { MAC_ADDR_0_HIGH, 0x0000,
9475 0x00000000, 0x0000ffff },
9476 { MAC_ADDR_0_LOW, 0x0000,
9477 0x00000000, 0xffffffff },
9478 { MAC_RX_MTU_SIZE, 0x0000,
9479 0x00000000, 0x0000ffff },
9480 { MAC_TX_MODE, 0x0000,
9481 0x00000000, 0x00000070 },
9482 { MAC_TX_LENGTHS, 0x0000,
9483 0x00000000, 0x00003fff },
9484 { MAC_RX_MODE, TG3_FL_NOT_5705,
9485 0x00000000, 0x000007fc },
9486 { MAC_RX_MODE, TG3_FL_5705,
9487 0x00000000, 0x000007dc },
9488 { MAC_HASH_REG_0, 0x0000,
9489 0x00000000, 0xffffffff },
9490 { MAC_HASH_REG_1, 0x0000,
9491 0x00000000, 0xffffffff },
9492 { MAC_HASH_REG_2, 0x0000,
9493 0x00000000, 0xffffffff },
9494 { MAC_HASH_REG_3, 0x0000,
9495 0x00000000, 0xffffffff },
9496
9497 /* Receive Data and Receive BD Initiator Control Registers. */
9498 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9499 0x00000000, 0xffffffff },
9500 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9501 0x00000000, 0xffffffff },
9502 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9503 0x00000000, 0x00000003 },
9504 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9505 0x00000000, 0xffffffff },
9506 { RCVDBDI_STD_BD+0, 0x0000,
9507 0x00000000, 0xffffffff },
9508 { RCVDBDI_STD_BD+4, 0x0000,
9509 0x00000000, 0xffffffff },
9510 { RCVDBDI_STD_BD+8, 0x0000,
9511 0x00000000, 0xffff0002 },
9512 { RCVDBDI_STD_BD+0xc, 0x0000,
9513 0x00000000, 0xffffffff },
6aa20a22 9514
a71116d1
MC		 9515 /* Receive BD Initiator Control Registers. */
9516 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9517 0x00000000, 0xffffffff },
9518 { RCVBDI_STD_THRESH, TG3_FL_5705,
9519 0x00000000, 0x000003ff },
9520 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9521 0x00000000, 0xffffffff },
6aa20a22 9522
a71116d1
MC		 9523 /* Host Coalescing Control Registers. */
9524 { HOSTCC_MODE, TG3_FL_NOT_5705,
9525 0x00000000, 0x00000004 },
9526 { HOSTCC_MODE, TG3_FL_5705,
9527 0x00000000, 0x000000f6 },
9528 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9529 0x00000000, 0xffffffff },
9530 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9531 0x00000000, 0x000003ff },
9532 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9533 0x00000000, 0xffffffff },
9534 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9535 0x00000000, 0x000003ff },
9536 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9537 0x00000000, 0xffffffff },
9538 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9539 0x00000000, 0x000000ff },
9540 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9541 0x00000000, 0xffffffff },
9542 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9543 0x00000000, 0x000000ff },
9544 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9545 0x00000000, 0xffffffff },
9546 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9547 0x00000000, 0xffffffff },
9548 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9549 0x00000000, 0xffffffff },
9550 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9551 0x00000000, 0x000000ff },
9552 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9553 0x00000000, 0xffffffff },
9554 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9555 0x00000000, 0x000000ff },
9556 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9557 0x00000000, 0xffffffff },
9558 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9559 0x00000000, 0xffffffff },
9560 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9561 0x00000000, 0xffffffff },
9562 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9563 0x00000000, 0xffffffff },
9564 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9565 0x00000000, 0xffffffff },
9566 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9567 0xffffffff, 0x00000000 },
9568 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9569 0xffffffff, 0x00000000 },
9570
9571 /* Buffer Manager Control Registers. */
b16250e3 9572 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9573 0x00000000, 0x007fff80 },
b16250e3 9574 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9575 0x00000000, 0x007fffff },
9576 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9577 0x00000000, 0x0000003f },
9578 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9579 0x00000000, 0x000001ff },
9580 { BUFMGR_MB_HIGH_WATER, 0x0000,
9581 0x00000000, 0x000001ff },
9582 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9583 0xffffffff, 0x00000000 },
9584 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9585 0xffffffff, 0x00000000 },
6aa20a22 9586
a71116d1
MC		 9587 /* Mailbox Registers */
9588 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9589 0x00000000, 0x000001ff },
9590 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9591 0x00000000, 0x000001ff },
9592 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9593 0x00000000, 0x000007ff },
9594 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9595 0x00000000, 0x000001ff },
9596
9597 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9598 };
9599
b16250e3
MC		 9600 is_5705 = is_5750 = 0;
9601 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9602 is_5705 = 1;
b16250e3
MC		 9603 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9604 is_5750 = 1;
9605 }
a71116d1
MC		 9606
9607 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9608 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9609 continue;
9610
9611 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9612 continue;
9613
9614 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9615 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9616 continue;
9617
b16250e3
MC		 9618 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9619 continue;
9620
a71116d1
MC		 9621 offset = (u32) reg_tbl[i].offset;
9622 read_mask = reg_tbl[i].read_mask;
9623 write_mask = reg_tbl[i].write_mask;
9624
9625 /* Save the original register content */
9626 save_val = tr32(offset);
9627
9628 /* Determine the read-only value. */
9629 read_val = save_val & read_mask;
9630
9631 /* Write zero to the register, then make sure the read-only bits
9632 * are not changed and the read/write bits are all zeros.
9633 */
9634 tw32(offset, 0);
9635
9636 val = tr32(offset);
9637
9638 /* Test the read-only and read/write bits. */
9639 if (((val & read_mask) != read_val) || (val & write_mask))
9640 goto out;
9641
9642 /* Write ones to all the bits defined by RdMask and WrMask, then
9643 * make sure the read-only bits are not changed and the
9644 * read/write bits are all ones.
9645 */
9646 tw32(offset, read_mask | write_mask);
9647
9648 val = tr32(offset);
9649
9650 /* Test the read-only bits. */
9651 if ((val & read_mask) != read_val)
9652 goto out;
9653
9654 /* Test the read/write bits. */
9655 if ((val & write_mask) != write_mask)
9656 goto out;
9657
9658 tw32(offset, save_val);
9659 }
9660
9661 return 0;
9662
9663out:
9f88f29f
MC		 9664 if (netif_msg_hw(tp))
9665 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9666 offset);
a71116d1
MC		 9667 tw32(offset, save_val);
9668 return -EIO;
9669}
9670
7942e1db
MC		 9671static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9672{
f71e1309 9673 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9674 int i;
9675 u32 j;
9676
e9edda69 9677 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9678 for (j = 0; j < len; j += 4) {
9679 u32 val;
9680
9681 tg3_write_mem(tp, offset + j, test_pattern[i]);
9682 tg3_read_mem(tp, offset + j, &val);
9683 if (val != test_pattern[i])
9684 return -EIO;
9685 }
9686 }
9687 return 0;
9688}
9689
9690static int tg3_test_memory(struct tg3 *tp)
9691{
9692 static struct mem_entry {
9693 u32 offset;
9694 u32 len;
9695 } mem_tbl_570x[] = {
38690194 9696 { 0x00000000, 0x00b50},
7942e1db
MC		 9697 { 0x00002000, 0x1c000},
9698 { 0xffffffff, 0x00000}
9699 }, mem_tbl_5705[] = {
9700 { 0x00000100, 0x0000c},
9701 { 0x00000200, 0x00008},
7942e1db
MC		 9702 { 0x00004000, 0x00800},
9703 { 0x00006000, 0x01000},
9704 { 0x00008000, 0x02000},
9705 { 0x00010000, 0x0e000},
9706 { 0xffffffff, 0x00000}
79f4d13a
MC		 9707 }, mem_tbl_5755[] = {
9708 { 0x00000200, 0x00008},
9709 { 0x00004000, 0x00800},
9710 { 0x00006000, 0x00800},
9711 { 0x00008000, 0x02000},
9712 { 0x00010000, 0x0c000},
9713 { 0xffffffff, 0x00000}
b16250e3
MC		 9714 }, mem_tbl_5906[] = {
9715 { 0x00000200, 0x00008},
9716 { 0x00004000, 0x00400},
9717 { 0x00006000, 0x00400},
9718 { 0x00008000, 0x01000},
9719 { 0x00010000, 0x01000},
9720 { 0xffffffff, 0x00000}
7942e1db
MC		 9721 };
9722 struct mem_entry *mem_tbl;
9723 int err = 0;
9724 int i;
9725
321d32a0
MC		 9726 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9727 mem_tbl = mem_tbl_5755;
9728 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9729 mem_tbl = mem_tbl_5906;
9730 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9731 mem_tbl = mem_tbl_5705;
9732 else
7942e1db
MC		 9733 mem_tbl = mem_tbl_570x;
9734
9735 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9736 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9737 mem_tbl[i].len)) != 0)
9738 break;
9739 }
6aa20a22 9740
7942e1db
MC		 9741 return err;
9742}
9743
9f40dead
MC		 9744#define TG3_MAC_LOOPBACK 0
9745#define TG3_PHY_LOOPBACK 1
9746
9747static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9748{
9f40dead 9749 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9750 u32 desc_idx;
9751 struct sk_buff *skb, *rx_skb;
9752 u8 *tx_data;
9753 dma_addr_t map;
9754 int num_pkts, tx_len, rx_len, i, err;
9755 struct tg3_rx_buffer_desc *desc;
9756
9f40dead 9757 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9758 /* HW errata - mac loopback fails in some cases on 5780.
9759 * Normal traffic and PHY loopback are not affected by
9760 * errata.
9761 */
9762 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9763 return 0;
9764
9f40dead 9765 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9766 MAC_MODE_PORT_INT_LPBACK;
9767 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9768 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9769 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9770 mac_mode |= MAC_MODE_PORT_MODE_MII;
9771 else
9772 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9773 tw32(MAC_MODE, mac_mode);
9774 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9775 u32 val;
9776
7f97a4bd
MC		 9777 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9778 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9779 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9780 } else
9781 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9782
9ef8ca99
MC		 9783 tg3_phy_toggle_automdix(tp, 0);
9784
3f7045c1 9785 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9786 udelay(40);
5d64ad34 9787
e8f3f6ca 9788 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 9789 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9791 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 9792 mac_mode |= MAC_MODE_PORT_MODE_MII;
9793 } else
9794 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9795
c94e3941
MC		 9796 /* reset to prevent losing 1st rx packet intermittently */
9797 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9798 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9799 udelay(10);
9800 tw32_f(MAC_RX_MODE, tp->rx_mode);
9801 }
e8f3f6ca
MC		 9802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9803 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9804 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9805 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9806 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9807 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9808 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9809 }
9f40dead 9810 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9811 }
9812 else
9813 return -EINVAL;
c76949a6
MC		 9814
9815 err = -EIO;
9816
c76949a6 9817 tx_len = 1514;
a20e9c62 9818 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9819 if (!skb)
9820 return -ENOMEM;
9821
c76949a6
MC		 9822 tx_data = skb_put(skb, tx_len);
9823 memcpy(tx_data, tp->dev->dev_addr, 6);
9824 memset(tx_data + 6, 0x0, 8);
9825
9826 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9827
9828 for (i = 14; i < tx_len; i++)
9829 tx_data[i] = (u8) (i & 0xff);
9830
9831 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9832
9833 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9834 HOSTCC_MODE_NOW);
9835
9836 udelay(10);
9837
9838 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9839
c76949a6
MC		 9840 num_pkts = 0;
9841
9f40dead 9842 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9843
9f40dead 9844 tp->tx_prod++;
c76949a6
MC		 9845 num_pkts++;
9846
9f40dead
MC		 9847 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9848 tp->tx_prod);
09ee929c 9849 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9850
9851 udelay(10);
9852
3f7045c1
MC		 9853 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9854 for (i = 0; i < 25; i++) {
c76949a6
MC		 9855 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9856 HOSTCC_MODE_NOW);
9857
9858 udelay(10);
9859
9860 tx_idx = tp->hw_status->idx[0].tx_consumer;
9861 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9862 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9863 (rx_idx == (rx_start_idx + num_pkts)))
9864 break;
9865 }
9866
9867 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9868 dev_kfree_skb(skb);
9869
9f40dead 9870 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9871 goto out;
9872
9873 if (rx_idx != rx_start_idx + num_pkts)
9874 goto out;
9875
9876 desc = &tp->rx_rcb[rx_start_idx];
9877 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9878 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9879 if (opaque_key != RXD_OPAQUE_RING_STD)
9880 goto out;
9881
9882 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9883 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9884 goto out;
9885
9886 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9887 if (rx_len != tx_len)
9888 goto out;
9889
9890 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9891
9892 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9893 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9894
9895 for (i = 14; i < tx_len; i++) {
9896 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9897 goto out;
9898 }
9899 err = 0;
6aa20a22 9900
c76949a6
MC		 9901 /* tg3_free_rings will unmap and free the rx_skb */
9902out:
9903 return err;
9904}
9905
9f40dead
MC		 9906#define TG3_MAC_LOOPBACK_FAILED 1
9907#define TG3_PHY_LOOPBACK_FAILED 2
9908#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9909 TG3_PHY_LOOPBACK_FAILED)
9910
9911static int tg3_test_loopback(struct tg3 *tp)
9912{
9913 int err = 0;
9936bcf6 9914 u32 cpmuctrl = 0;
9f40dead
MC		 9915
9916 if (!netif_running(tp->dev))
9917 return TG3_LOOPBACK_FAILED;
9918
b9ec6c1b
MC		 9919 err = tg3_reset_hw(tp, 1);
9920 if (err)
9921 return TG3_LOOPBACK_FAILED;
9f40dead 9922
6833c043
MC		 9923 /* Turn off gphy autopowerdown. */
9924 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9925 tg3_phy_toggle_apd(tp, false);
9926
321d32a0 9927 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9928 int i;
9929 u32 status;
9930
9931 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9932
9933 /* Wait for up to 40 microseconds to acquire lock. */
9934 for (i = 0; i < 4; i++) {
9935 status = tr32(TG3_CPMU_MUTEX_GNT);
9936 if (status == CPMU_MUTEX_GNT_DRIVER)
9937 break;
9938 udelay(10);
9939 }
9940
9941 if (status != CPMU_MUTEX_GNT_DRIVER)
9942 return TG3_LOOPBACK_FAILED;
9943
b2a5c19c 9944 /* Turn off link-based power management. */
e875093c 9945 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9946 tw32(TG3_CPMU_CTRL,
9947 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9948 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9949 }
9950
9f40dead
MC		 9951 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9952 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9953
321d32a0 9954 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9955 tw32(TG3_CPMU_CTRL, cpmuctrl);
9956
9957 /* Release the mutex */
9958 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9959 }
9960
dd477003
MC		 9961 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9962 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9963 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9964 err |= TG3_PHY_LOOPBACK_FAILED;
9965 }
9966
6833c043
MC		 9967 /* Re-enable gphy autopowerdown. */
9968 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9969 tg3_phy_toggle_apd(tp, true);
9970
9f40dead
MC		 9971 return err;
9972}
9973
4cafd3f5
MC		 9974static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9975 u64 *data)
9976{
566f86ad
MC		 9977 struct tg3 *tp = netdev_priv(dev);
9978
bc1c7567
MC		 9979 if (tp->link_config.phy_is_low_power)
9980 tg3_set_power_state(tp, PCI_D0);
9981
566f86ad
MC		 9982 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9983
9984 if (tg3_test_nvram(tp) != 0) {
9985 etest->flags |= ETH_TEST_FL_FAILED;
9986 data[0] = 1;
9987 }
ca43007a
MC		 9988 if (tg3_test_link(tp) != 0) {
9989 etest->flags |= ETH_TEST_FL_FAILED;
9990 data[1] = 1;
9991 }
a71116d1 9992 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9993 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9994
9995 if (netif_running(dev)) {
b02fd9e3 9996 tg3_phy_stop(tp);
a71116d1 9997 tg3_netif_stop(tp);
bbe832c0
MC		 9998 irq_sync = 1;
9999 }
a71116d1 10000
bbe832c0 10001 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10002
10003 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10004 err = tg3_nvram_lock(tp);
a71116d1
MC		 10005 tg3_halt_cpu(tp, RX_CPU_BASE);
10006 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10007 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10008 if (!err)
10009 tg3_nvram_unlock(tp);
a71116d1 10010
d9ab5ad1
MC		 10011 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10012 tg3_phy_reset(tp);
10013
a71116d1
MC		 10014 if (tg3_test_registers(tp) != 0) {
10015 etest->flags |= ETH_TEST_FL_FAILED;
10016 data[2] = 1;
10017 }
7942e1db
MC		 10018 if (tg3_test_memory(tp) != 0) {
10019 etest->flags |= ETH_TEST_FL_FAILED;
10020 data[3] = 1;
10021 }
9f40dead 10022 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10023 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10024
f47c11ee
DM		 10025 tg3_full_unlock(tp);
10026
d4bc3927
MC		 10027 if (tg3_test_interrupt(tp) != 0) {
10028 etest->flags |= ETH_TEST_FL_FAILED;
10029 data[5] = 1;
10030 }
f47c11ee
DM		 10031
10032 tg3_full_lock(tp, 0);
d4bc3927 10033
a71116d1
MC		 10034 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10035 if (netif_running(dev)) {
10036 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10037 err2 = tg3_restart_hw(tp, 1);
10038 if (!err2)
b9ec6c1b 10039 tg3_netif_start(tp);
a71116d1 10040 }
f47c11ee
DM		 10041
10042 tg3_full_unlock(tp);
b02fd9e3
MC		 10043
10044 if (irq_sync && !err2)
10045 tg3_phy_start(tp);
a71116d1 10046 }
bc1c7567
MC		 10047 if (tp->link_config.phy_is_low_power)
10048 tg3_set_power_state(tp, PCI_D3hot);
10049
4cafd3f5
MC		 10050}
10051
1da177e4
LT		 10052static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10053{
10054 struct mii_ioctl_data *data = if_mii(ifr);
10055 struct tg3 *tp = netdev_priv(dev);
10056 int err;
10057
b02fd9e3
MC		 10058 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10059 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10060 return -EAGAIN;
298cf9be 10061 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10062 }
10063
1da177e4
LT		 10064 switch(cmd) {
10065 case SIOCGMIIPHY:
10066 data->phy_id = PHY_ADDR;
10067
10068 /* fallthru */
10069 case SIOCGMIIREG: {
10070 u32 mii_regval;
10071
10072 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10073 break; /* We have no PHY */
10074
bc1c7567
MC		 10075 if (tp->link_config.phy_is_low_power)
10076 return -EAGAIN;
10077
f47c11ee 10078 spin_lock_bh(&tp->lock);
1da177e4 10079 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10080 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10081
10082 data->val_out = mii_regval;
10083
10084 return err;
10085 }
10086
10087 case SIOCSMIIREG:
10088 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10089 break; /* We have no PHY */
10090
10091 if (!capable(CAP_NET_ADMIN))
10092 return -EPERM;
10093
bc1c7567
MC		 10094 if (tp->link_config.phy_is_low_power)
10095 return -EAGAIN;
10096
f47c11ee 10097 spin_lock_bh(&tp->lock);
1da177e4 10098 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10099 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10100
10101 return err;
10102
10103 default:
10104 /* do nothing */
10105 break;
10106 }
10107 return -EOPNOTSUPP;
10108}
10109
10110#if TG3_VLAN_TAG_USED
10111static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10112{
10113 struct tg3 *tp = netdev_priv(dev);
10114
844b3eed
MC		 10115 if (!netif_running(dev)) {
10116 tp->vlgrp = grp;
10117 return;
10118 }
10119
10120 tg3_netif_stop(tp);
29315e87 10121
f47c11ee 10122 tg3_full_lock(tp, 0);
1da177e4
LT		 10123
10124 tp->vlgrp = grp;
10125
10126 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10127 __tg3_set_rx_mode(dev);
10128
844b3eed 10129 tg3_netif_start(tp);
46966545
MC		 10130
10131 tg3_full_unlock(tp);
1da177e4 10132}
1da177e4
LT		 10133#endif
10134
15f9850d
DM		 10135static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10136{
10137 struct tg3 *tp = netdev_priv(dev);
10138
10139 memcpy(ec, &tp->coal, sizeof(*ec));
10140 return 0;
10141}
10142
d244c892
MC		 10143static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10144{
10145 struct tg3 *tp = netdev_priv(dev);
10146 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10147 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10148
10149 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10150 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10151 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10152 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10153 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10154 }
10155
10156 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10157 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10158 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10159 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10160 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10161 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10162 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10163 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10164 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10165 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10166 return -EINVAL;
10167
10168 /* No rx interrupts will be generated if both are zero */
10169 if ((ec->rx_coalesce_usecs == 0) &&
10170 (ec->rx_max_coalesced_frames == 0))
10171 return -EINVAL;
10172
10173 /* No tx interrupts will be generated if both are zero */
10174 if ((ec->tx_coalesce_usecs == 0) &&
10175 (ec->tx_max_coalesced_frames == 0))
10176 return -EINVAL;
10177
10178 /* Only copy relevant parameters, ignore all others. */
10179 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10180 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10181 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10182 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10183 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10184 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10185 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10186 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10187 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10188
10189 if (netif_running(dev)) {
10190 tg3_full_lock(tp, 0);
10191 __tg3_set_coalesce(tp, &tp->coal);
10192 tg3_full_unlock(tp);
10193 }
10194 return 0;
10195}
10196
7282d491 10197static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10198 .get_settings = tg3_get_settings,
10199 .set_settings = tg3_set_settings,
10200 .get_drvinfo = tg3_get_drvinfo,
10201 .get_regs_len = tg3_get_regs_len,
10202 .get_regs = tg3_get_regs,
10203 .get_wol = tg3_get_wol,
10204 .set_wol = tg3_set_wol,
10205 .get_msglevel = tg3_get_msglevel,
10206 .set_msglevel = tg3_set_msglevel,
10207 .nway_reset = tg3_nway_reset,
10208 .get_link = ethtool_op_get_link,
10209 .get_eeprom_len = tg3_get_eeprom_len,
10210 .get_eeprom = tg3_get_eeprom,
10211 .set_eeprom = tg3_set_eeprom,
10212 .get_ringparam = tg3_get_ringparam,
10213 .set_ringparam = tg3_set_ringparam,
10214 .get_pauseparam = tg3_get_pauseparam,
10215 .set_pauseparam = tg3_set_pauseparam,
10216 .get_rx_csum = tg3_get_rx_csum,
10217 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10218 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10219 .set_sg = ethtool_op_set_sg,
1da177e4 10220 .set_tso = tg3_set_tso,
4cafd3f5 10221 .self_test = tg3_self_test,
1da177e4 10222 .get_strings = tg3_get_strings,
4009a93d 10223 .phys_id = tg3_phys_id,
1da177e4 10224 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10225 .get_coalesce = tg3_get_coalesce,
d244c892 10226 .set_coalesce = tg3_set_coalesce,
b9f2c044 10227 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10228};
10229
10230static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10231{
1b27777a 10232 u32 cursize, val, magic;
1da177e4
LT		 10233
10234 tp->nvram_size = EEPROM_CHIP_SIZE;
10235
e4f34110 10236 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10237 return;
10238
b16250e3
MC		 10239 if ((magic != TG3_EEPROM_MAGIC) &&
10240 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10241 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10242 return;
10243
10244 /*
10245 * Size the chip by reading offsets at increasing powers of two.
10246 * When we encounter our validation signature, we know the addressing
10247 * has wrapped around, and thus have our chip size.
10248 */
1b27777a 10249 cursize = 0x10;
1da177e4
LT		 10250
10251 while (cursize < tp->nvram_size) {
e4f34110 10252 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10253 return;
10254
1820180b 10255 if (val == magic)
1da177e4
LT		 10256 break;
10257
10258 cursize <<= 1;
10259 }
10260
10261 tp->nvram_size = cursize;
10262}
6aa20a22 10263
1da177e4
LT		 10264static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10265{
10266 u32 val;
10267
df259d8c
MC		 10268 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10269 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10270 return;
10271
10272 /* Selfboot format */
1820180b 10273 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10274 tg3_get_eeprom_size(tp);
10275 return;
10276 }
10277
6d348f2c 10278 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10279 if (val != 0) {
6d348f2c
MC		 10280 /* This is confusing. We want to operate on the
10281 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10282 * call will read from NVRAM and byteswap the data
10283 * according to the byteswapping settings for all
10284 * other register accesses. This ensures the data we
10285 * want will always reside in the lower 16-bits.
10286 * However, the data in NVRAM is in LE format, which
10287 * means the data from the NVRAM read will always be
10288 * opposite the endianness of the CPU. The 16-bit
10289 * byteswap then brings the data to CPU endianness.
10290 */
10291 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10292 return;
10293 }
10294 }
fd1122a2 10295 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10296}
10297
10298static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10299{
10300 u32 nvcfg1;
10301
10302 nvcfg1 = tr32(NVRAM_CFG1);
10303 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10304 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10305 } else {
1da177e4
LT		 10306 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10307 tw32(NVRAM_CFG1, nvcfg1);
10308 }
10309
4c987487 10310 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10311 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10312 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10313 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10314 tp->nvram_jedecnum = JEDEC_ATMEL;
10315 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10316 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10317 break;
10318 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10319 tp->nvram_jedecnum = JEDEC_ATMEL;
10320 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10321 break;
10322 case FLASH_VENDOR_ATMEL_EEPROM:
10323 tp->nvram_jedecnum = JEDEC_ATMEL;
10324 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10325 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10326 break;
10327 case FLASH_VENDOR_ST:
10328 tp->nvram_jedecnum = JEDEC_ST;
10329 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10330 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10331 break;
10332 case FLASH_VENDOR_SAIFUN:
10333 tp->nvram_jedecnum = JEDEC_SAIFUN;
10334 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10335 break;
10336 case FLASH_VENDOR_SST_SMALL:
10337 case FLASH_VENDOR_SST_LARGE:
10338 tp->nvram_jedecnum = JEDEC_SST;
10339 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10340 break;
1da177e4 10341 }
8590a603 10342 } else {
1da177e4
LT		 10343 tp->nvram_jedecnum = JEDEC_ATMEL;
10344 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10345 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10346 }
10347}
10348
361b4ac2
MC		 10349static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10350{
10351 u32 nvcfg1;
10352
10353 nvcfg1 = tr32(NVRAM_CFG1);
10354
e6af301b
MC		 10355 /* NVRAM protection for TPM */
10356 if (nvcfg1 & (1 << 27))
10357 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10358
361b4ac2 10359 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10360 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10361 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10362 tp->nvram_jedecnum = JEDEC_ATMEL;
10363 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10364 break;
10365 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10366 tp->nvram_jedecnum = JEDEC_ATMEL;
10367 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10368 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10369 break;
10370 case FLASH_5752VENDOR_ST_M45PE10:
10371 case FLASH_5752VENDOR_ST_M45PE20:
10372 case FLASH_5752VENDOR_ST_M45PE40:
10373 tp->nvram_jedecnum = JEDEC_ST;
10374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10375 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10376 break;
361b4ac2
MC		 10377 }
10378
10379 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10380 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10381 case FLASH_5752PAGE_SIZE_256:
10382 tp->nvram_pagesize = 256;
10383 break;
10384 case FLASH_5752PAGE_SIZE_512:
10385 tp->nvram_pagesize = 512;
10386 break;
10387 case FLASH_5752PAGE_SIZE_1K:
10388 tp->nvram_pagesize = 1024;
10389 break;
10390 case FLASH_5752PAGE_SIZE_2K:
10391 tp->nvram_pagesize = 2048;
10392 break;
10393 case FLASH_5752PAGE_SIZE_4K:
10394 tp->nvram_pagesize = 4096;
10395 break;
10396 case FLASH_5752PAGE_SIZE_264:
10397 tp->nvram_pagesize = 264;
10398 break;
361b4ac2 10399 }
8590a603 10400 } else {
361b4ac2
MC		 10401 /* For eeprom, set pagesize to maximum eeprom size */
10402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10403
10404 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10405 tw32(NVRAM_CFG1, nvcfg1);
10406 }
10407}
10408
d3c7b886
MC		 10409static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10410{
989a9d23 10411 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10412
10413 nvcfg1 = tr32(NVRAM_CFG1);
10414
10415 /* NVRAM protection for TPM */
989a9d23 10416 if (nvcfg1 & (1 << 27)) {
d3c7b886 10417 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10418 protect = 1;
10419 }
d3c7b886 10420
989a9d23
MC		 10421 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10422 switch (nvcfg1) {
8590a603
MC		 10423 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10424 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10425 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10426 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10427 tp->nvram_jedecnum = JEDEC_ATMEL;
10428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10429 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10430 tp->nvram_pagesize = 264;
10431 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10432 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10433 tp->nvram_size = (protect ? 0x3e200 :
10434 TG3_NVRAM_SIZE_512KB);
10435 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10436 tp->nvram_size = (protect ? 0x1f200 :
10437 TG3_NVRAM_SIZE_256KB);
10438 else
10439 tp->nvram_size = (protect ? 0x1f200 :
10440 TG3_NVRAM_SIZE_128KB);
10441 break;
10442 case FLASH_5752VENDOR_ST_M45PE10:
10443 case FLASH_5752VENDOR_ST_M45PE20:
10444 case FLASH_5752VENDOR_ST_M45PE40:
10445 tp->nvram_jedecnum = JEDEC_ST;
10446 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10447 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10448 tp->nvram_pagesize = 256;
10449 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10450 tp->nvram_size = (protect ?
10451 TG3_NVRAM_SIZE_64KB :
10452 TG3_NVRAM_SIZE_128KB);
10453 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10454 tp->nvram_size = (protect ?
10455 TG3_NVRAM_SIZE_64KB :
10456 TG3_NVRAM_SIZE_256KB);
10457 else
10458 tp->nvram_size = (protect ?
10459 TG3_NVRAM_SIZE_128KB :
10460 TG3_NVRAM_SIZE_512KB);
10461 break;
d3c7b886
MC		 10462 }
10463}
10464
1b27777a
MC		 10465static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10466{
10467 u32 nvcfg1;
10468
10469 nvcfg1 = tr32(NVRAM_CFG1);
10470
10471 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10472 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10473 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10474 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10475 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10476 tp->nvram_jedecnum = JEDEC_ATMEL;
10477 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10478 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10479
8590a603
MC		 10480 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10481 tw32(NVRAM_CFG1, nvcfg1);
10482 break;
10483 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10484 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10485 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10486 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10487 tp->nvram_jedecnum = JEDEC_ATMEL;
10488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10489 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10490 tp->nvram_pagesize = 264;
10491 break;
10492 case FLASH_5752VENDOR_ST_M45PE10:
10493 case FLASH_5752VENDOR_ST_M45PE20:
10494 case FLASH_5752VENDOR_ST_M45PE40:
10495 tp->nvram_jedecnum = JEDEC_ST;
10496 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10497 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10498 tp->nvram_pagesize = 256;
10499 break;
1b27777a
MC		 10500 }
10501}
10502
6b91fa02
MC		 10503static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10504{
10505 u32 nvcfg1, protect = 0;
10506
10507 nvcfg1 = tr32(NVRAM_CFG1);
10508
10509 /* NVRAM protection for TPM */
10510 if (nvcfg1 & (1 << 27)) {
10511 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10512 protect = 1;
10513 }
10514
10515 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10516 switch (nvcfg1) {
8590a603
MC		 10517 case FLASH_5761VENDOR_ATMEL_ADB021D:
10518 case FLASH_5761VENDOR_ATMEL_ADB041D:
10519 case FLASH_5761VENDOR_ATMEL_ADB081D:
10520 case FLASH_5761VENDOR_ATMEL_ADB161D:
10521 case FLASH_5761VENDOR_ATMEL_MDB021D:
10522 case FLASH_5761VENDOR_ATMEL_MDB041D:
10523 case FLASH_5761VENDOR_ATMEL_MDB081D:
10524 case FLASH_5761VENDOR_ATMEL_MDB161D:
10525 tp->nvram_jedecnum = JEDEC_ATMEL;
10526 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10527 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10528 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10529 tp->nvram_pagesize = 256;
10530 break;
10531 case FLASH_5761VENDOR_ST_A_M45PE20:
10532 case FLASH_5761VENDOR_ST_A_M45PE40:
10533 case FLASH_5761VENDOR_ST_A_M45PE80:
10534 case FLASH_5761VENDOR_ST_A_M45PE16:
10535 case FLASH_5761VENDOR_ST_M_M45PE20:
10536 case FLASH_5761VENDOR_ST_M_M45PE40:
10537 case FLASH_5761VENDOR_ST_M_M45PE80:
10538 case FLASH_5761VENDOR_ST_M_M45PE16:
10539 tp->nvram_jedecnum = JEDEC_ST;
10540 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10541 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10542 tp->nvram_pagesize = 256;
10543 break;
6b91fa02
MC		 10544 }
10545
10546 if (protect) {
10547 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10548 } else {
10549 switch (nvcfg1) {
8590a603
MC		 10550 case FLASH_5761VENDOR_ATMEL_ADB161D:
10551 case FLASH_5761VENDOR_ATMEL_MDB161D:
10552 case FLASH_5761VENDOR_ST_A_M45PE16:
10553 case FLASH_5761VENDOR_ST_M_M45PE16:
10554 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10555 break;
10556 case FLASH_5761VENDOR_ATMEL_ADB081D:
10557 case FLASH_5761VENDOR_ATMEL_MDB081D:
10558 case FLASH_5761VENDOR_ST_A_M45PE80:
10559 case FLASH_5761VENDOR_ST_M_M45PE80:
10560 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10561 break;
10562 case FLASH_5761VENDOR_ATMEL_ADB041D:
10563 case FLASH_5761VENDOR_ATMEL_MDB041D:
10564 case FLASH_5761VENDOR_ST_A_M45PE40:
10565 case FLASH_5761VENDOR_ST_M_M45PE40:
10566 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10567 break;
10568 case FLASH_5761VENDOR_ATMEL_ADB021D:
10569 case FLASH_5761VENDOR_ATMEL_MDB021D:
10570 case FLASH_5761VENDOR_ST_A_M45PE20:
10571 case FLASH_5761VENDOR_ST_M_M45PE20:
10572 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10573 break;
6b91fa02
MC		 10574 }
10575 }
10576}
10577
b5d3772c
MC		 10578static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10579{
10580 tp->nvram_jedecnum = JEDEC_ATMEL;
10581 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10582 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10583}
10584
321d32a0
MC		 10585static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10586{
10587 u32 nvcfg1;
10588
10589 nvcfg1 = tr32(NVRAM_CFG1);
10590
10591 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10592 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10593 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10594 tp->nvram_jedecnum = JEDEC_ATMEL;
10595 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10596 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10597
10598 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10599 tw32(NVRAM_CFG1, nvcfg1);
10600 return;
10601 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10602 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10603 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10604 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10605 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10606 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10607 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10608 tp->nvram_jedecnum = JEDEC_ATMEL;
10609 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10610 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10611
10612 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10613 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10614 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10615 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10616 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10617 break;
10618 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10619 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10620 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10621 break;
10622 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10623 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10624 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10625 break;
10626 }
10627 break;
10628 case FLASH_5752VENDOR_ST_M45PE10:
10629 case FLASH_5752VENDOR_ST_M45PE20:
10630 case FLASH_5752VENDOR_ST_M45PE40:
10631 tp->nvram_jedecnum = JEDEC_ST;
10632 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10633 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10634
10635 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10636 case FLASH_5752VENDOR_ST_M45PE10:
10637 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10638 break;
10639 case FLASH_5752VENDOR_ST_M45PE20:
10640 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10641 break;
10642 case FLASH_5752VENDOR_ST_M45PE40:
10643 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10644 break;
10645 }
10646 break;
10647 default:
df259d8c 10648 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10649 return;
10650 }
10651
10652 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10653 case FLASH_5752PAGE_SIZE_256:
10654 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10655 tp->nvram_pagesize = 256;
10656 break;
10657 case FLASH_5752PAGE_SIZE_512:
10658 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10659 tp->nvram_pagesize = 512;
10660 break;
10661 case FLASH_5752PAGE_SIZE_1K:
10662 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10663 tp->nvram_pagesize = 1024;
10664 break;
10665 case FLASH_5752PAGE_SIZE_2K:
10666 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10667 tp->nvram_pagesize = 2048;
10668 break;
10669 case FLASH_5752PAGE_SIZE_4K:
10670 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10671 tp->nvram_pagesize = 4096;
10672 break;
10673 case FLASH_5752PAGE_SIZE_264:
10674 tp->nvram_pagesize = 264;
10675 break;
10676 case FLASH_5752PAGE_SIZE_528:
10677 tp->nvram_pagesize = 528;
10678 break;
10679 }
10680}
10681
1da177e4
LT		 10682/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10683static void __devinit tg3_nvram_init(struct tg3 *tp)
10684{
1da177e4
LT		 10685 tw32_f(GRC_EEPROM_ADDR,
10686 (EEPROM_ADDR_FSM_RESET |
10687 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10688 EEPROM_ADDR_CLKPERD_SHIFT)));
10689
9d57f01c 10690 msleep(1);
1da177e4
LT		 10691
10692 /* Enable seeprom accesses. */
10693 tw32_f(GRC_LOCAL_CTRL,
10694 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10695 udelay(100);
10696
10697 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10698 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10699 tp->tg3_flags |= TG3_FLAG_NVRAM;
10700
ec41c7df
MC		 10701 if (tg3_nvram_lock(tp)) {
10702 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10703 "tg3_nvram_init failed.\n", tp->dev->name);
10704 return;
10705 }
e6af301b 10706 tg3_enable_nvram_access(tp);
1da177e4 10707
989a9d23
MC		 10708 tp->nvram_size = 0;
10709
361b4ac2
MC		 10710 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10711 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10712 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10713 tg3_get_5755_nvram_info(tp);
d30cdd28 10714 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10717 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10718 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10719 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10720 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10721 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10722 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10723 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10724 else
10725 tg3_get_nvram_info(tp);
10726
989a9d23
MC		 10727 if (tp->nvram_size == 0)
10728 tg3_get_nvram_size(tp);
1da177e4 10729
e6af301b 10730 tg3_disable_nvram_access(tp);
381291b7 10731 tg3_nvram_unlock(tp);
1da177e4
LT		 10732
10733 } else {
10734 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10735
10736 tg3_get_eeprom_size(tp);
10737 }
10738}
10739
1da177e4
LT		 10740static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10741 u32 offset, u32 len, u8 *buf)
10742{
10743 int i, j, rc = 0;
10744 u32 val;
10745
10746 for (i = 0; i < len; i += 4) {
b9fc7dc5 10747 u32 addr;
a9dc529d 10748 __be32 data;
1da177e4
LT		 10749
10750 addr = offset + i;
10751
10752 memcpy(&data, buf + i, 4);
10753
62cedd11
MC		 10754 /*
10755 * The SEEPROM interface expects the data to always be opposite
10756 * the native endian format. We accomplish this by reversing
10757 * all the operations that would have been performed on the
10758 * data from a call to tg3_nvram_read_be32().
10759 */
10760 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10761
10762 val = tr32(GRC_EEPROM_ADDR);
10763 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10764
10765 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10766 EEPROM_ADDR_READ);
10767 tw32(GRC_EEPROM_ADDR, val |
10768 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10769 (addr & EEPROM_ADDR_ADDR_MASK) |
10770 EEPROM_ADDR_START |
10771 EEPROM_ADDR_WRITE);
6aa20a22 10772
9d57f01c 10773 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10774 val = tr32(GRC_EEPROM_ADDR);
10775
10776 if (val & EEPROM_ADDR_COMPLETE)
10777 break;
9d57f01c 10778 msleep(1);
1da177e4
LT		 10779 }
10780 if (!(val & EEPROM_ADDR_COMPLETE)) {
10781 rc = -EBUSY;
10782 break;
10783 }
10784 }
10785
10786 return rc;
10787}
10788
10789/* offset and length are dword aligned */
10790static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10791 u8 *buf)
10792{
10793 int ret = 0;
10794 u32 pagesize = tp->nvram_pagesize;
10795 u32 pagemask = pagesize - 1;
10796 u32 nvram_cmd;
10797 u8 *tmp;
10798
10799 tmp = kmalloc(pagesize, GFP_KERNEL);
10800 if (tmp == NULL)
10801 return -ENOMEM;
10802
10803 while (len) {
10804 int j;
e6af301b 10805 u32 phy_addr, page_off, size;
1da177e4
LT		 10806
10807 phy_addr = offset & ~pagemask;
6aa20a22 10808
1da177e4 10809 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10810 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10811 (__be32 *) (tmp + j));
10812 if (ret)
1da177e4
LT		 10813 break;
10814 }
10815 if (ret)
10816 break;
10817
10818 page_off = offset & pagemask;
10819 size = pagesize;
10820 if (len < size)
10821 size = len;
10822
10823 len -= size;
10824
10825 memcpy(tmp + page_off, buf, size);
10826
10827 offset = offset + (pagesize - page_off);
10828
e6af301b 10829 tg3_enable_nvram_access(tp);
1da177e4
LT		 10830
10831 /*
10832 * Before we can erase the flash page, we need
10833 * to issue a special "write enable" command.
10834 */
10835 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10836
10837 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10838 break;
10839
10840 /* Erase the target page */
10841 tw32(NVRAM_ADDR, phy_addr);
10842
10843 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10844 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10845
10846 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10847 break;
10848
10849 /* Issue another write enable to start the write. */
10850 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10851
10852 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10853 break;
10854
10855 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10856 __be32 data;
1da177e4 10857
b9fc7dc5 10858 data = *((__be32 *) (tmp + j));
a9dc529d 10859
b9fc7dc5 10860 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10861
10862 tw32(NVRAM_ADDR, phy_addr + j);
10863
10864 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10865 NVRAM_CMD_WR;
10866
10867 if (j == 0)
10868 nvram_cmd |= NVRAM_CMD_FIRST;
10869 else if (j == (pagesize - 4))
10870 nvram_cmd |= NVRAM_CMD_LAST;
10871
10872 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10873 break;
10874 }
10875 if (ret)
10876 break;
10877 }
10878
10879 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10880 tg3_nvram_exec_cmd(tp, nvram_cmd);
10881
10882 kfree(tmp);
10883
10884 return ret;
10885}
10886
10887/* offset and length are dword aligned */
10888static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10889 u8 *buf)
10890{
10891 int i, ret = 0;
10892
10893 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10894 u32 page_off, phy_addr, nvram_cmd;
10895 __be32 data;
1da177e4
LT		 10896
10897 memcpy(&data, buf + i, 4);
b9fc7dc5 10898 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10899
10900 page_off = offset % tp->nvram_pagesize;
10901
1820180b 10902 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10903
10904 tw32(NVRAM_ADDR, phy_addr);
10905
10906 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10907
10908 if ((page_off == 0) || (i == 0))
10909 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10910 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10911 nvram_cmd |= NVRAM_CMD_LAST;
10912
10913 if (i == (len - 4))
10914 nvram_cmd |= NVRAM_CMD_LAST;
10915
321d32a0
MC		 10916 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10917 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10918 (tp->nvram_jedecnum == JEDEC_ST) &&
10919 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10920
10921 if ((ret = tg3_nvram_exec_cmd(tp,
10922 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10923 NVRAM_CMD_DONE)))
10924
10925 break;
10926 }
10927 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10928 /* We always do complete word writes to eeprom. */
10929 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10930 }
10931
10932 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10933 break;
10934 }
10935 return ret;
10936}
10937
10938/* offset and length are dword aligned */
10939static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10940{
10941 int ret;
10942
1da177e4 10943 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10944 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10945 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10946 udelay(40);
10947 }
10948
10949 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10950 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10951 }
10952 else {
10953 u32 grc_mode;
10954
ec41c7df
MC		 10955 ret = tg3_nvram_lock(tp);
10956 if (ret)
10957 return ret;
1da177e4 10958
e6af301b
MC		 10959 tg3_enable_nvram_access(tp);
10960 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10961 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10962 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10963
10964 grc_mode = tr32(GRC_MODE);
10965 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10966
10967 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10968 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10969
10970 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10971 buf);
10972 }
10973 else {
10974 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10975 buf);
10976 }
10977
10978 grc_mode = tr32(GRC_MODE);
10979 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10980
e6af301b 10981 tg3_disable_nvram_access(tp);
1da177e4
LT		 10982 tg3_nvram_unlock(tp);
10983 }
10984
10985 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10986 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10987 udelay(40);
10988 }
10989
10990 return ret;
10991}
10992
10993struct subsys_tbl_ent {
10994 u16 subsys_vendor, subsys_devid;
10995 u32 phy_id;
10996};
10997
10998static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10999 /* Broadcom boards. */
11000 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11001 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11002 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11003 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11004 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11005 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11006 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11007 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11008 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11009 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11010 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11011
11012 /* 3com boards. */
11013 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11014 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11015 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11016 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11017 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11018
11019 /* DELL boards. */
11020 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11021 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11022 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11023 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11024
11025 /* Compaq boards. */
11026 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11027 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11028 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11029 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11030 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11031
11032 /* IBM boards. */
11033 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11034};
11035
11036static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11037{
11038 int i;
11039
11040 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11041 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11042 tp->pdev->subsystem_vendor) &&
11043 (subsys_id_to_phy_id[i].subsys_devid ==
11044 tp->pdev->subsystem_device))
11045 return &subsys_id_to_phy_id[i];
11046 }
11047 return NULL;
11048}
11049
7d0c41ef 11050static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11051{
1da177e4 11052 u32 val;
caf636c7
MC		 11053 u16 pmcsr;
11054
11055 /* On some early chips the SRAM cannot be accessed in D3hot state,
11056 * so need make sure we're in D0.
11057 */
11058 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11059 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11060 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11061 msleep(1);
7d0c41ef
MC		 11062
11063 /* Make sure register accesses (indirect or otherwise)
11064 * will function correctly.
11065 */
11066 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11067 tp->misc_host_ctrl);
1da177e4 11068
f49639e6
DM		 11069 /* The memory arbiter has to be enabled in order for SRAM accesses
11070 * to succeed. Normally on powerup the tg3 chip firmware will make
11071 * sure it is enabled, but other entities such as system netboot
11072 * code might disable it.
11073 */
11074 val = tr32(MEMARB_MODE);
11075 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11076
1da177e4 11077 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11078 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11079
a85feb8c
GZ		 11080 /* Assume an onboard device and WOL capable by default. */
11081 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11082
b5d3772c 11083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11084 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11085 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11086 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11087 }
0527ba35
MC		 11088 val = tr32(VCPU_CFGSHDW);
11089 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11090 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11091 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11092 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11093 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11094 goto done;
b5d3772c
MC		 11095 }
11096
1da177e4
LT		 11097 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11098 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11099 u32 nic_cfg, led_cfg;
a9daf367 11100 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11101 int eeprom_phy_serdes = 0;
1da177e4
LT		 11102
11103 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11104 tp->nic_sram_data_cfg = nic_cfg;
11105
11106 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11107 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11108 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11109 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11110 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11111 (ver > 0) && (ver < 0x100))
11112 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11113
a9daf367
MC		 11114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11115 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11116
1da177e4
LT		 11117 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11118 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11119 eeprom_phy_serdes = 1;
11120
11121 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11122 if (nic_phy_id != 0) {
11123 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11124 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11125
11126 eeprom_phy_id = (id1 >> 16) << 10;
11127 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11128 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11129 } else
11130 eeprom_phy_id = 0;
11131
7d0c41ef 11132 tp->phy_id = eeprom_phy_id;
747e8f8b 11133 if (eeprom_phy_serdes) {
a4e2b347 11134 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11135 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11136 else
11137 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11138 }
7d0c41ef 11139
cbf46853 11140 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11141 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11142 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11143 else
1da177e4
LT		 11144 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11145
11146 switch (led_cfg) {
11147 default:
11148 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11149 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11150 break;
11151
11152 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11153 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11154 break;
11155
11156 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11157 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11158
11159 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11160 * read on some older 5700/5701 bootcode.
11161 */
11162 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11163 ASIC_REV_5700 ||
11164 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11165 ASIC_REV_5701)
11166 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11167
1da177e4
LT		 11168 break;
11169
11170 case SHASTA_EXT_LED_SHARED:
11171 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11172 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11173 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11174 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11175 LED_CTRL_MODE_PHY_2);
11176 break;
11177
11178 case SHASTA_EXT_LED_MAC:
11179 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11180 break;
11181
11182 case SHASTA_EXT_LED_COMBO:
11183 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11184 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11185 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11186 LED_CTRL_MODE_PHY_2);
11187 break;
11188
855e1111 11189 }
1da177e4
LT		 11190
11191 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11193 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11194 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11195
b2a5c19c
MC		 11196 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11197 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11198
9d26e213 11199 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11200 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11201 if ((tp->pdev->subsystem_vendor ==
11202 PCI_VENDOR_ID_ARIMA) &&
11203 (tp->pdev->subsystem_device == 0x205a ||
11204 tp->pdev->subsystem_device == 0x2063))
11205 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11206 } else {
f49639e6 11207 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11208 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11209 }
1da177e4
LT		 11210
11211 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11212 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11213 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11214 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11215 }
b2b98d4a
MC		 11216
11217 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11218 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11219 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11220
a85feb8c
GZ		 11221 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11222 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11223 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11224
12dac075 11225 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11226 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11227 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11228
1da177e4
LT		 11229 if (cfg2 & (1 << 17))
11230 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11231
11232 /* serdes signal pre-emphasis in register 0x590 set by */
11233 /* bootcode if bit 18 is set */
11234 if (cfg2 & (1 << 18))
11235 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11236
321d32a0
MC		 11237 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11238 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11239 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11240 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11241
8ed5d97e
MC		 11242 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11243 u32 cfg3;
11244
11245 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11246 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11247 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11248 }
a9daf367
MC		 11249
11250 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11251 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11252 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11253 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11254 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11255 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11256 }
05ac4cb7
MC		 11257done:
11258 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11259 device_set_wakeup_enable(&tp->pdev->dev,
11260 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11261}
11262
b2a5c19c
MC		 11263static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11264{
11265 int i;
11266 u32 val;
11267
11268 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11269 tw32(OTP_CTRL, cmd);
11270
11271 /* Wait for up to 1 ms for command to execute. */
11272 for (i = 0; i < 100; i++) {
11273 val = tr32(OTP_STATUS);
11274 if (val & OTP_STATUS_CMD_DONE)
11275 break;
11276 udelay(10);
11277 }
11278
11279 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11280}
11281
11282/* Read the gphy configuration from the OTP region of the chip. The gphy
11283 * configuration is a 32-bit value that straddles the alignment boundary.
11284 * We do two 32-bit reads and then shift and merge the results.
11285 */
11286static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11287{
11288 u32 bhalf_otp, thalf_otp;
11289
11290 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11291
11292 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11293 return 0;
11294
11295 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11296
11297 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11298 return 0;
11299
11300 thalf_otp = tr32(OTP_READ_DATA);
11301
11302 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11303
11304 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11305 return 0;
11306
11307 bhalf_otp = tr32(OTP_READ_DATA);
11308
11309 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11310}
11311
7d0c41ef
MC		 11312static int __devinit tg3_phy_probe(struct tg3 *tp)
11313{
11314 u32 hw_phy_id_1, hw_phy_id_2;
11315 u32 hw_phy_id, hw_phy_id_masked;
11316 int err;
1da177e4 11317
b02fd9e3
MC		 11318 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11319 return tg3_phy_init(tp);
11320
1da177e4 11321 /* Reading the PHY ID register can conflict with ASF
877d0310 11322 * firmware access to the PHY hardware.
1da177e4
LT		 11323 */
11324 err = 0;
0d3031d9
MC		 11325 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11326 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11327 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11328 } else {
11329 /* Now read the physical PHY_ID from the chip and verify
11330 * that it is sane. If it doesn't look good, we fall back
11331 * to either the hard-coded table based PHY_ID and failing
11332 * that the value found in the eeprom area.
11333 */
11334 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11335 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11336
11337 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11338 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11339 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11340
11341 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11342 }
11343
11344 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11345 tp->phy_id = hw_phy_id;
11346 if (hw_phy_id_masked == PHY_ID_BCM8002)
11347 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11348 else
11349 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11350 } else {
7d0c41ef
MC		 11351 if (tp->phy_id != PHY_ID_INVALID) {
11352 /* Do nothing, phy ID already set up in
11353 * tg3_get_eeprom_hw_cfg().
11354 */
1da177e4
LT		 11355 } else {
11356 struct subsys_tbl_ent *p;
11357
11358 /* No eeprom signature? Try the hardcoded
11359 * subsys device table.
11360 */
11361 p = lookup_by_subsys(tp);
11362 if (!p)
11363 return -ENODEV;
11364
11365 tp->phy_id = p->phy_id;
11366 if (!tp->phy_id ||
11367 tp->phy_id == PHY_ID_BCM8002)
11368 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11369 }
11370 }
11371
747e8f8b 11372 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11373 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11374 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11375 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11376
11377 tg3_readphy(tp, MII_BMSR, &bmsr);
11378 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11379 (bmsr & BMSR_LSTATUS))
11380 goto skip_phy_reset;
6aa20a22 11381
1da177e4
LT		 11382 err = tg3_phy_reset(tp);
11383 if (err)
11384 return err;
11385
11386 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11387 ADVERTISE_100HALF | ADVERTISE_100FULL |
11388 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11389 tg3_ctrl = 0;
11390 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11391 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11392 MII_TG3_CTRL_ADV_1000_FULL);
11393 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11394 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11395 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11396 MII_TG3_CTRL_ENABLE_AS_MASTER);
11397 }
11398
3600d918
MC		 11399 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11400 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11401 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11402 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11403 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11404
11405 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11406 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11407
11408 tg3_writephy(tp, MII_BMCR,
11409 BMCR_ANENABLE | BMCR_ANRESTART);
11410 }
11411 tg3_phy_set_wirespeed(tp);
11412
11413 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11414 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11415 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11416 }
11417
11418skip_phy_reset:
11419 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11420 err = tg3_init_5401phy_dsp(tp);
11421 if (err)
11422 return err;
11423 }
11424
11425 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11426 err = tg3_init_5401phy_dsp(tp);
11427 }
11428
747e8f8b 11429 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11430 tp->link_config.advertising =
11431 (ADVERTISED_1000baseT_Half |
11432 ADVERTISED_1000baseT_Full |
11433 ADVERTISED_Autoneg |
11434 ADVERTISED_FIBRE);
11435 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11436 tp->link_config.advertising &=
11437 ~(ADVERTISED_1000baseT_Half |
11438 ADVERTISED_1000baseT_Full);
11439
11440 return err;
11441}
11442
11443static void __devinit tg3_read_partno(struct tg3 *tp)
11444{
6d348f2c 11445 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11446 unsigned int i;
1b27777a 11447 u32 magic;
1da177e4 11448
df259d8c
MC		 11449 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11450 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11451 goto out_not_found;
1da177e4 11452
1820180b 11453 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11454 for (i = 0; i < 256; i += 4) {
11455 u32 tmp;
1da177e4 11456
6d348f2c
MC		 11457 /* The data is in little-endian format in NVRAM.
11458 * Use the big-endian read routines to preserve
11459 * the byte order as it exists in NVRAM.
11460 */
11461 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11462 goto out_not_found;
11463
6d348f2c 11464 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11465 }
11466 } else {
11467 int vpd_cap;
11468
11469 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11470 for (i = 0; i < 256; i += 4) {
11471 u32 tmp, j = 0;
b9fc7dc5 11472 __le32 v;
1b27777a
MC		 11473 u16 tmp16;
11474
11475 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11476 i);
11477 while (j++ < 100) {
11478 pci_read_config_word(tp->pdev, vpd_cap +
11479 PCI_VPD_ADDR, &tmp16);
11480 if (tmp16 & 0x8000)
11481 break;
11482 msleep(1);
11483 }
f49639e6
DM		 11484 if (!(tmp16 & 0x8000))
11485 goto out_not_found;
11486
1b27777a
MC		 11487 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11488 &tmp);
b9fc7dc5 11489 v = cpu_to_le32(tmp);
6d348f2c 11490 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11491 }
1da177e4
LT		 11492 }
11493
11494 /* Now parse and find the part number. */
af2c6a4a 11495 for (i = 0; i < 254; ) {
1da177e4 11496 unsigned char val = vpd_data[i];
af2c6a4a 11497 unsigned int block_end;
1da177e4
LT		 11498
11499 if (val == 0x82 || val == 0x91) {
11500 i = (i + 3 +
11501 (vpd_data[i + 1] +
11502 (vpd_data[i + 2] << 8)));
11503 continue;
11504 }
11505
11506 if (val != 0x90)
11507 goto out_not_found;
11508
11509 block_end = (i + 3 +
11510 (vpd_data[i + 1] +
11511 (vpd_data[i + 2] << 8)));
11512 i += 3;
af2c6a4a
MC		 11513
11514 if (block_end > 256)
11515 goto out_not_found;
11516
11517 while (i < (block_end - 2)) {
1da177e4
LT		 11518 if (vpd_data[i + 0] == 'P' &&
11519 vpd_data[i + 1] == 'N') {
11520 int partno_len = vpd_data[i + 2];
11521
af2c6a4a
MC		 11522 i += 3;
11523 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11524 goto out_not_found;
11525
11526 memcpy(tp->board_part_number,
af2c6a4a 11527 &vpd_data[i], partno_len);
1da177e4
LT		 11528
11529 /* Success. */
11530 return;
11531 }
af2c6a4a 11532 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11533 }
11534
11535 /* Part number not found. */
11536 goto out_not_found;
11537 }
11538
11539out_not_found:
b5d3772c
MC		 11540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11541 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11542 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11543 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11544 strcpy(tp->board_part_number, "BCM57780");
11545 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11546 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11547 strcpy(tp->board_part_number, "BCM57760");
11548 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11549 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11550 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11551 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11552 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11553 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11554 else
11555 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11556}
11557
9c8a620e
MC		 11558static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11559{
11560 u32 val;
11561
e4f34110 11562 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11563 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11564 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11565 val != 0)
11566 return 0;
11567
11568 return 1;
11569}
11570
acd9c119
MC		 11571static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11572{
ff3a7cb2 11573 u32 val, offset, start, ver_offset;
acd9c119 11574 int i;
ff3a7cb2 11575 bool newver = false;
acd9c119
MC		 11576
11577 if (tg3_nvram_read(tp, 0xc, &offset) ||
11578 tg3_nvram_read(tp, 0x4, &start))
11579 return;
11580
11581 offset = tg3_nvram_logical_addr(tp, offset);
11582
ff3a7cb2 11583 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11584 return;
11585
ff3a7cb2
MC		 11586 if ((val & 0xfc000000) == 0x0c000000) {
11587 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11588 return;
11589
ff3a7cb2
MC		 11590 if (val == 0)
11591 newver = true;
11592 }
11593
11594 if (newver) {
11595 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11596 return;
11597
11598 offset = offset + ver_offset - start;
11599 for (i = 0; i < 16; i += 4) {
11600 __be32 v;
11601 if (tg3_nvram_read_be32(tp, offset + i, &v))
11602 return;
11603
11604 memcpy(tp->fw_ver + i, &v, sizeof(v));
11605 }
11606 } else {
11607 u32 major, minor;
11608
11609 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11610 return;
11611
11612 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11613 TG3_NVM_BCVER_MAJSFT;
11614 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11615 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11616 }
11617}
11618
a6f6cb1c
MC		 11619static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11620{
11621 u32 val, major, minor;
11622
11623 /* Use native endian representation */
11624 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11625 return;
11626
11627 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11628 TG3_NVM_HWSB_CFG1_MAJSFT;
11629 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11630 TG3_NVM_HWSB_CFG1_MINSFT;
11631
11632 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11633}
11634
dfe00d7d
MC		 11635static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11636{
11637 u32 offset, major, minor, build;
11638
11639 tp->fw_ver[0] = 's';
11640 tp->fw_ver[1] = 'b';
11641 tp->fw_ver[2] = '\0';
11642
11643 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11644 return;
11645
11646 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11647 case TG3_EEPROM_SB_REVISION_0:
11648 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11649 break;
11650 case TG3_EEPROM_SB_REVISION_2:
11651 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11652 break;
11653 case TG3_EEPROM_SB_REVISION_3:
11654 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11655 break;
11656 default:
11657 return;
11658 }
11659
e4f34110 11660 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11661 return;
11662
11663 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11664 TG3_EEPROM_SB_EDH_BLD_SHFT;
11665 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11666 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11667 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11668
11669 if (minor > 99 || build > 26)
11670 return;
11671
11672 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11673
11674 if (build > 0) {
11675 tp->fw_ver[8] = 'a' + build - 1;
11676 tp->fw_ver[9] = '\0';
11677 }
11678}
11679
acd9c119 11680static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11681{
11682 u32 val, offset, start;
acd9c119 11683 int i, vlen;
9c8a620e
MC		 11684
11685 for (offset = TG3_NVM_DIR_START;
11686 offset < TG3_NVM_DIR_END;
11687 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11688 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11689 return;
11690
9c8a620e
MC		 11691 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11692 break;
11693 }
11694
11695 if (offset == TG3_NVM_DIR_END)
11696 return;
11697
11698 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11699 start = 0x08000000;
e4f34110 11700 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11701 return;
11702
e4f34110 11703 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11704 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11705 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11706 return;
11707
11708 offset += val - start;
11709
acd9c119 11710 vlen = strlen(tp->fw_ver);
9c8a620e 11711
acd9c119
MC		 11712 tp->fw_ver[vlen++] = ',';
11713 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11714
11715 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11716 __be32 v;
11717 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11718 return;
11719
b9fc7dc5 11720 offset += sizeof(v);
c4e6575c 11721
acd9c119
MC		 11722 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11723 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11724 break;
c4e6575c 11725 }
9c8a620e 11726
acd9c119
MC		 11727 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11728 vlen += sizeof(v);
c4e6575c 11729 }
acd9c119
MC		 11730}
11731
7fd76445
MC		 11732static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11733{
11734 int vlen;
11735 u32 apedata;
11736
11737 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11738 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11739 return;
11740
11741 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11742 if (apedata != APE_SEG_SIG_MAGIC)
11743 return;
11744
11745 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11746 if (!(apedata & APE_FW_STATUS_READY))
11747 return;
11748
11749 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11750
11751 vlen = strlen(tp->fw_ver);
11752
11753 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11754 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11755 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11756 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11757 (apedata & APE_FW_VERSION_BLDMSK));
11758}
11759
acd9c119
MC		 11760static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11761{
11762 u32 val;
11763
df259d8c
MC		 11764 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11765 tp->fw_ver[0] = 's';
11766 tp->fw_ver[1] = 'b';
11767 tp->fw_ver[2] = '\0';
11768
11769 return;
11770 }
11771
acd9c119
MC		 11772 if (tg3_nvram_read(tp, 0, &val))
11773 return;
11774
11775 if (val == TG3_EEPROM_MAGIC)
11776 tg3_read_bc_ver(tp);
11777 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11778 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11779 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11780 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11781 else
11782 return;
11783
11784 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11785 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11786 return;
11787
11788 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11789
11790 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11791}
11792
7544b097
MC		 11793static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11794
1da177e4
LT		 11795static int __devinit tg3_get_invariants(struct tg3 *tp)
11796{
11797 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11798 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11799 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11800 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11801 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11802 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11803 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11804 { },
11805 };
11806 u32 misc_ctrl_reg;
1da177e4
LT		 11807 u32 pci_state_reg, grc_misc_cfg;
11808 u32 val;
11809 u16 pci_cmd;
5e7dfd0f 11810 int err;
1da177e4 11811
1da177e4
LT		 11812 /* Force memory write invalidate off. If we leave it on,
11813 * then on 5700_BX chips we have to enable a workaround.
11814 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11815 * to match the cacheline size. The Broadcom driver have this
11816 * workaround but turns MWI off all the times so never uses
11817 * it. This seems to suggest that the workaround is insufficient.
11818 */
11819 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11820 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11821 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11822
11823 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11824 * has the register indirect write enable bit set before
11825 * we try to access any of the MMIO registers. It is also
11826 * critical that the PCI-X hw workaround situation is decided
11827 * before that as well.
11828 */
11829 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11830 &misc_ctrl_reg);
11831
11832 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11833 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11835 u32 prod_id_asic_rev;
11836
11837 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11838 &prod_id_asic_rev);
321d32a0 11839 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11840 }
1da177e4 11841
ff645bec
MC		 11842 /* Wrong chip ID in 5752 A0. This code can be removed later
11843 * as A0 is not in production.
11844 */
11845 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11846 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11847
6892914f
MC		 11848 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11849 * we need to disable memory and use config. cycles
11850 * only to access all registers. The 5702/03 chips
11851 * can mistakenly decode the special cycles from the
11852 * ICH chipsets as memory write cycles, causing corruption
11853 * of register and memory space. Only certain ICH bridges
11854 * will drive special cycles with non-zero data during the
11855 * address phase which can fall within the 5703's address
11856 * range. This is not an ICH bug as the PCI spec allows
11857 * non-zero address during special cycles. However, only
11858 * these ICH bridges are known to drive non-zero addresses
11859 * during special cycles.
11860 *
11861 * Since special cycles do not cross PCI bridges, we only
11862 * enable this workaround if the 5703 is on the secondary
11863 * bus of these ICH bridges.
11864 */
11865 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11866 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11867 static struct tg3_dev_id {
11868 u32 vendor;
11869 u32 device;
11870 u32 rev;
11871 } ich_chipsets[] = {
11872 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11873 PCI_ANY_ID },
11874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11875 PCI_ANY_ID },
11876 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11877 0xa },
11878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11879 PCI_ANY_ID },
11880 { },
11881 };
11882 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11883 struct pci_dev *bridge = NULL;
11884
11885 while (pci_id->vendor != 0) {
11886 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11887 bridge);
11888 if (!bridge) {
11889 pci_id++;
11890 continue;
11891 }
11892 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11893 if (bridge->revision > pci_id->rev)
6892914f
MC		 11894 continue;
11895 }
11896 if (bridge->subordinate &&
11897 (bridge->subordinate->number ==
11898 tp->pdev->bus->number)) {
11899
11900 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11901 pci_dev_put(bridge);
11902 break;
11903 }
11904 }
11905 }
11906
41588ba1
MC		 11907 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11908 static struct tg3_dev_id {
11909 u32 vendor;
11910 u32 device;
11911 } bridge_chipsets[] = {
11912 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11913 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11914 { },
11915 };
11916 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11917 struct pci_dev *bridge = NULL;
11918
11919 while (pci_id->vendor != 0) {
11920 bridge = pci_get_device(pci_id->vendor,
11921 pci_id->device,
11922 bridge);
11923 if (!bridge) {
11924 pci_id++;
11925 continue;
11926 }
11927 if (bridge->subordinate &&
11928 (bridge->subordinate->number <=
11929 tp->pdev->bus->number) &&
11930 (bridge->subordinate->subordinate >=
11931 tp->pdev->bus->number)) {
11932 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11933 pci_dev_put(bridge);
11934 break;
11935 }
11936 }
11937 }
11938
4a29cc2e
MC		 11939 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11940 * DMA addresses > 40-bit. This bridge may have other additional
11941 * 57xx devices behind it in some 4-port NIC designs for example.
11942 * Any tg3 device found behind the bridge will also need the 40-bit
11943 * DMA workaround.
11944 */
a4e2b347
MC		 11945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11947 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11948 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11949 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11950 }
4a29cc2e
MC		 11951 else {
11952 struct pci_dev *bridge = NULL;
11953
11954 do {
11955 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11956 PCI_DEVICE_ID_SERVERWORKS_EPB,
11957 bridge);
11958 if (bridge && bridge->subordinate &&
11959 (bridge->subordinate->number <=
11960 tp->pdev->bus->number) &&
11961 (bridge->subordinate->subordinate >=
11962 tp->pdev->bus->number)) {
11963 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11964 pci_dev_put(bridge);
11965 break;
11966 }
11967 } while (bridge);
11968 }
4cf78e4f 11969
1da177e4
LT		 11970 /* Initialize misc host control in PCI block. */
11971 tp->misc_host_ctrl |= (misc_ctrl_reg &
11972 MISC_HOST_CTRL_CHIPREV);
11973 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11974 tp->misc_host_ctrl);
11975
7544b097
MC		 11976 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11977 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11978 tp->pdev_peer = tg3_find_peer(tp);
11979
321d32a0
MC		 11980 /* Intentionally exclude ASIC_REV_5906 */
11981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11982 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11983 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11987 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11988
11989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11992 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11993 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11994 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11995
1b440c56
JL		 11996 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11997 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11998 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11999
027455ad
MC		 12000 /* 5700 B0 chips do not support checksumming correctly due
12001 * to hardware bugs.
12002 */
12003 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12004 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12005 else {
12006 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12007 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12008 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12009 tp->dev->features |= NETIF_F_IPV6_CSUM;
12010 }
12011
5a6f3074 12012 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12013 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12014 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12015 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12016 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12017 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12018 tp->pdev_peer == tp->pdev))
12019 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12020
321d32a0 12021 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12023 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12024 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12025 } else {
7f62ad5d 12026 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12027 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12028 ASIC_REV_5750 &&
12029 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12030 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12031 }
5a6f3074 12032 }
1da177e4 12033
f51f3562
MC		 12034 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12035 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 12036 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12037
52f4490c
MC		 12038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12039 &pci_state_reg);
12040
5e7dfd0f
MC		 12041 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12042 if (tp->pcie_cap != 0) {
12043 u16 lnkctl;
12044
1da177e4 12045 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12046
12047 pcie_set_readrq(tp->pdev, 4096);
12048
5e7dfd0f
MC		 12049 pci_read_config_word(tp->pdev,
12050 tp->pcie_cap + PCI_EXP_LNKCTL,
12051 &lnkctl);
12052 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12054 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12057 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12058 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12059 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12060 }
52f4490c 12061 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12062 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12063 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12064 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12065 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12066 if (!tp->pcix_cap) {
12067 printk(KERN_ERR PFX "Cannot find PCI-X "
12068 "capability, aborting.\n");
12069 return -EIO;
12070 }
12071
12072 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12073 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12074 }
1da177e4 12075
399de50b
MC		 12076 /* If we have an AMD 762 or VIA K8T800 chipset, write
12077 * reordering to the mailbox registers done by the host
12078 * controller can cause major troubles. We read back from
12079 * every mailbox register write to force the writes to be
12080 * posted to the chip in order.
12081 */
12082 if (pci_dev_present(write_reorder_chipsets) &&
12083 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12084 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12085
69fc4053
MC		 12086 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12087 &tp->pci_cacheline_sz);
12088 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12089 &tp->pci_lat_timer);
1da177e4
LT		 12090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12091 tp->pci_lat_timer < 64) {
12092 tp->pci_lat_timer = 64;
69fc4053
MC		 12093 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12094 tp->pci_lat_timer);
1da177e4
LT		 12095 }
12096
52f4490c
MC		 12097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12098 /* 5700 BX chips need to have their TX producer index
12099 * mailboxes written twice to workaround a bug.
12100 */
12101 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12102
52f4490c 12103 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12104 *
12105 * The workaround is to use indirect register accesses
12106 * for all chip writes not to mailbox registers.
12107 */
52f4490c 12108 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12109 u32 pm_reg;
1da177e4
LT		 12110
12111 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12112
12113 /* The chip can have it's power management PCI config
12114 * space registers clobbered due to this bug.
12115 * So explicitly force the chip into D0 here.
12116 */
9974a356
MC		 12117 pci_read_config_dword(tp->pdev,
12118 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12119 &pm_reg);
12120 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12121 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12122 pci_write_config_dword(tp->pdev,
12123 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12124 pm_reg);
12125
12126 /* Also, force SERR#/PERR# in PCI command. */
12127 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12128 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12129 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12130 }
12131 }
12132
1da177e4
LT		 12133 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12134 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12135 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12136 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12137
12138 /* Chip-specific fixup from Broadcom driver */
12139 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12140 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12141 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12142 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12143 }
12144
1ee582d8 12145 /* Default fast path register access methods */
20094930 12146 tp->read32 = tg3_read32;
1ee582d8 12147 tp->write32 = tg3_write32;
09ee929c 12148 tp->read32_mbox = tg3_read32;
20094930 12149 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12150 tp->write32_tx_mbox = tg3_write32;
12151 tp->write32_rx_mbox = tg3_write32;
12152
12153 /* Various workaround register access methods */
12154 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12155 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12156 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12157 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12158 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12159 /*
12160 * Back to back register writes can cause problems on these
12161 * chips, the workaround is to read back all reg writes
12162 * except those to mailbox regs.
12163 *
12164 * See tg3_write_indirect_reg32().
12165 */
1ee582d8 12166 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12167 }
12168
1ee582d8
MC		 12169
12170 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12171 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12172 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12173 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12174 tp->write32_rx_mbox = tg3_write_flush_reg32;
12175 }
20094930 12176
6892914f
MC		 12177 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12178 tp->read32 = tg3_read_indirect_reg32;
12179 tp->write32 = tg3_write_indirect_reg32;
12180 tp->read32_mbox = tg3_read_indirect_mbox;
12181 tp->write32_mbox = tg3_write_indirect_mbox;
12182 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12183 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12184
12185 iounmap(tp->regs);
22abe310 12186 tp->regs = NULL;
6892914f
MC		 12187
12188 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12189 pci_cmd &= ~PCI_COMMAND_MEMORY;
12190 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12191 }
b5d3772c
MC		 12192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12193 tp->read32_mbox = tg3_read32_mbox_5906;
12194 tp->write32_mbox = tg3_write32_mbox_5906;
12195 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12196 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12197 }
6892914f 12198
bbadf503
MC		 12199 if (tp->write32 == tg3_write_indirect_reg32 ||
12200 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12201 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12203 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12204
7d0c41ef 12205 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12206 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12207 * determined before calling tg3_set_power_state() so that
12208 * we know whether or not to switch out of Vaux power.
12209 * When the flag is set, it means that GPIO1 is used for eeprom
12210 * write protect and also implies that it is a LOM where GPIOs
12211 * are not used to switch power.
6aa20a22 12212 */
7d0c41ef
MC		 12213 tg3_get_eeprom_hw_cfg(tp);
12214
0d3031d9
MC		 12215 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12216 /* Allow reads and writes to the
12217 * APE register and memory space.
12218 */
12219 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12220 PCISTATE_ALLOW_APE_SHMEM_WR;
12221 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12222 pci_state_reg);
12223 }
12224
9936bcf6 12225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12229 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12230
314fba34
MC		 12231 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12232 * GPIO1 driven high will bring 5700's external PHY out of reset.
12233 * It is also used as eeprom write protect on LOMs.
12234 */
12235 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12236 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12237 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12238 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12239 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12240 /* Unused GPIO3 must be driven as output on 5752 because there
12241 * are no pull-up resistors on unused GPIO pins.
12242 */
12243 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12244 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12245
321d32a0
MC		 12246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12248 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12249
8d519ab2
MC		 12250 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12251 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12252 /* Turn off the debug UART. */
12253 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12254 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12255 /* Keep VMain power. */
12256 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12257 GRC_LCLCTRL_GPIO_OUTPUT0;
12258 }
12259
1da177e4 12260 /* Force the chip into D0. */
bc1c7567 12261 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12262 if (err) {
12263 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12264 pci_name(tp->pdev));
12265 return err;
12266 }
12267
1da177e4
LT		 12268 /* Derive initial jumbo mode from MTU assigned in
12269 * ether_setup() via the alloc_etherdev() call
12270 */
0f893dc6 12271 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12272 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12273 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12274
12275 /* Determine WakeOnLan speed to use. */
12276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12277 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12278 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12279 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12280 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12281 } else {
12282 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12283 }
12284
7f97a4bd
MC		 12285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12286 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12287
1da177e4
LT		 12288 /* A few boards don't want Ethernet@WireSpeed phy feature */
12289 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12290 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12291 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12292 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12293 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12294 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12295 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12296
12297 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12298 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12299 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12300 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12301 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12302
321d32a0 12303 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12304 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12305 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12311 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12312 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12313 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12314 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12315 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12316 } else
c424cb24
MC		 12317 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12318 }
1da177e4 12319
b2a5c19c
MC		 12320 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12321 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12322 tp->phy_otp = tg3_read_otp_phycfg(tp);
12323 if (tp->phy_otp == 0)
12324 tp->phy_otp = TG3_OTP_DEFAULT;
12325 }
12326
f51f3562 12327 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12328 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12329 else
12330 tp->mi_mode = MAC_MI_MODE_BASE;
12331
1da177e4 12332 tp->coalesce_mode = 0;
1da177e4
LT		 12333 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12334 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12335 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12336
321d32a0
MC		 12337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12338 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12339 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12340
255ca311
MC		 12341 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12342 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12343 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12344 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12345
158d7abd
MC		 12346 err = tg3_mdio_init(tp);
12347 if (err)
12348 return err;
1da177e4
LT		 12349
12350 /* Initialize data/descriptor byte/word swapping. */
12351 val = tr32(GRC_MODE);
12352 val &= GRC_MODE_HOST_STACKUP;
12353 tw32(GRC_MODE, val | tp->grc_mode);
12354
12355 tg3_switch_clocks(tp);
12356
12357 /* Clear this out for sanity. */
12358 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12359
12360 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12361 &pci_state_reg);
12362 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12363 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12364 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12365
12366 if (chiprevid == CHIPREV_ID_5701_A0 ||
12367 chiprevid == CHIPREV_ID_5701_B0 ||
12368 chiprevid == CHIPREV_ID_5701_B2 ||
12369 chiprevid == CHIPREV_ID_5701_B5) {
12370 void __iomem *sram_base;
12371
12372 /* Write some dummy words into the SRAM status block
12373 * area, see if it reads back correctly. If the return
12374 * value is bad, force enable the PCIX workaround.
12375 */
12376 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12377
12378 writel(0x00000000, sram_base);
12379 writel(0x00000000, sram_base + 4);
12380 writel(0xffffffff, sram_base + 4);
12381 if (readl(sram_base) != 0x00000000)
12382 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12383 }
12384 }
12385
12386 udelay(50);
12387 tg3_nvram_init(tp);
12388
12389 grc_misc_cfg = tr32(GRC_MISC_CFG);
12390 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12391
1da177e4
LT		 12392 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12393 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12394 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12395 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12396
fac9b83e
DM		 12397 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12398 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12399 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12400 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12401 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12402 HOSTCC_MODE_CLRTICK_TXBD);
12403
12404 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12405 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12406 tp->misc_host_ctrl);
12407 }
12408
3bda1258
MC		 12409 /* Preserve the APE MAC_MODE bits */
12410 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12411 tp->mac_mode = tr32(MAC_MODE) |
12412 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12413 else
12414 tp->mac_mode = TG3_DEF_MAC_MODE;
12415
1da177e4
LT		 12416 /* these are limited to 10/100 only */
12417 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12418 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12419 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12420 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12421 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12422 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12423 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12424 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12425 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12426 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12427 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12428 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12429 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12430 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12431
12432 err = tg3_phy_probe(tp);
12433 if (err) {
12434 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12435 pci_name(tp->pdev), err);
12436 /* ... but do not return immediately ... */
b02fd9e3 12437 tg3_mdio_fini(tp);
1da177e4
LT		 12438 }
12439
12440 tg3_read_partno(tp);
c4e6575c 12441 tg3_read_fw_ver(tp);
1da177e4
LT		 12442
12443 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12444 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12445 } else {
12446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12447 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12448 else
12449 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12450 }
12451
12452 /* 5700 {AX,BX} chips have a broken status block link
12453 * change bit implementation, so we must use the
12454 * status register in those cases.
12455 */
12456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12457 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12458 else
12459 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12460
12461 /* The led_ctrl is set during tg3_phy_probe, here we might
12462 * have to force the link status polling mechanism based
12463 * upon subsystem IDs.
12464 */
12465 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12467 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12468 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12469 TG3_FLAG_USE_LINKCHG_REG);
12470 }
12471
12472 /* For all SERDES we poll the MAC status register. */
12473 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12474 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12475 else
12476 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12477
ad829268 12478 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12480 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12481 tp->rx_offset = 0;
12482
f92905de
MC		 12483 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12484
12485 /* Increment the rx prod index on the rx std ring by at most
12486 * 8 for these chips to workaround hw errata.
12487 */
12488 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12489 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12491 tp->rx_std_max_post = 8;
12492
8ed5d97e
MC		 12493 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12494 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12495 PCIE_PWR_MGMT_L1_THRESH_MSK;
12496
1da177e4
LT		 12497 return err;
12498}
12499
49b6e95f 12500#ifdef CONFIG_SPARC
1da177e4
LT		 12501static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12502{
12503 struct net_device *dev = tp->dev;
12504 struct pci_dev *pdev = tp->pdev;
49b6e95f 12505 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12506 const unsigned char *addr;
49b6e95f
DM		 12507 int len;
12508
12509 addr = of_get_property(dp, "local-mac-address", &len);
12510 if (addr && len == 6) {
12511 memcpy(dev->dev_addr, addr, 6);
12512 memcpy(dev->perm_addr, dev->dev_addr, 6);
12513 return 0;
1da177e4
LT		 12514 }
12515 return -ENODEV;
12516}
12517
12518static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12519{
12520 struct net_device *dev = tp->dev;
12521
12522 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12523 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12524 return 0;
12525}
12526#endif
12527
12528static int __devinit tg3_get_device_address(struct tg3 *tp)
12529{
12530 struct net_device *dev = tp->dev;
12531 u32 hi, lo, mac_offset;
008652b3 12532 int addr_ok = 0;
1da177e4 12533
49b6e95f 12534#ifdef CONFIG_SPARC
1da177e4
LT		 12535 if (!tg3_get_macaddr_sparc(tp))
12536 return 0;
12537#endif
12538
12539 mac_offset = 0x7c;
f49639e6 12540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12541 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12542 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12543 mac_offset = 0xcc;
12544 if (tg3_nvram_lock(tp))
12545 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12546 else
12547 tg3_nvram_unlock(tp);
12548 }
b5d3772c
MC		 12549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12550 mac_offset = 0x10;
1da177e4
LT		 12551
12552 /* First try to get it from MAC address mailbox. */
12553 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12554 if ((hi >> 16) == 0x484b) {
12555 dev->dev_addr[0] = (hi >> 8) & 0xff;
12556 dev->dev_addr[1] = (hi >> 0) & 0xff;
12557
12558 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12559 dev->dev_addr[2] = (lo >> 24) & 0xff;
12560 dev->dev_addr[3] = (lo >> 16) & 0xff;
12561 dev->dev_addr[4] = (lo >> 8) & 0xff;
12562 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12563
008652b3
MC		 12564 /* Some old bootcode may report a 0 MAC address in SRAM */
12565 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12566 }
12567 if (!addr_ok) {
12568 /* Next, try NVRAM. */
df259d8c
MC		 12569 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12570 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12571 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12572 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12573 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12574 }
12575 /* Finally just fetch it out of the MAC control regs. */
12576 else {
12577 hi = tr32(MAC_ADDR_0_HIGH);
12578 lo = tr32(MAC_ADDR_0_LOW);
12579
12580 dev->dev_addr[5] = lo & 0xff;
12581 dev->dev_addr[4] = (lo >> 8) & 0xff;
12582 dev->dev_addr[3] = (lo >> 16) & 0xff;
12583 dev->dev_addr[2] = (lo >> 24) & 0xff;
12584 dev->dev_addr[1] = hi & 0xff;
12585 dev->dev_addr[0] = (hi >> 8) & 0xff;
12586 }
1da177e4
LT		 12587 }
12588
12589 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12590#ifdef CONFIG_SPARC
1da177e4
LT		 12591 if (!tg3_get_default_macaddr_sparc(tp))
12592 return 0;
12593#endif
12594 return -EINVAL;
12595 }
2ff43697 12596 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12597 return 0;
12598}
12599
59e6b434
DM		 12600#define BOUNDARY_SINGLE_CACHELINE 1
12601#define BOUNDARY_MULTI_CACHELINE 2
12602
12603static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12604{
12605 int cacheline_size;
12606 u8 byte;
12607 int goal;
12608
12609 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12610 if (byte == 0)
12611 cacheline_size = 1024;
12612 else
12613 cacheline_size = (int) byte * 4;
12614
12615 /* On 5703 and later chips, the boundary bits have no
12616 * effect.
12617 */
12618 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12619 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12620 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12621 goto out;
12622
12623#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12624 goal = BOUNDARY_MULTI_CACHELINE;
12625#else
12626#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12627 goal = BOUNDARY_SINGLE_CACHELINE;
12628#else
12629 goal = 0;
12630#endif
12631#endif
12632
12633 if (!goal)
12634 goto out;
12635
12636 /* PCI controllers on most RISC systems tend to disconnect
12637 * when a device tries to burst across a cache-line boundary.
12638 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12639 *
12640 * Unfortunately, for PCI-E there are only limited
12641 * write-side controls for this, and thus for reads
12642 * we will still get the disconnects. We'll also waste
12643 * these PCI cycles for both read and write for chips
12644 * other than 5700 and 5701 which do not implement the
12645 * boundary bits.
12646 */
12647 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12648 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12649 switch (cacheline_size) {
12650 case 16:
12651 case 32:
12652 case 64:
12653 case 128:
12654 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12655 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12656 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12657 } else {
12658 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12659 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12660 }
12661 break;
12662
12663 case 256:
12664 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12665 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12666 break;
12667
12668 default:
12669 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12670 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12671 break;
855e1111 12672 }
59e6b434
DM		 12673 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12674 switch (cacheline_size) {
12675 case 16:
12676 case 32:
12677 case 64:
12678 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12679 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12680 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12681 break;
12682 }
12683 /* fallthrough */
12684 case 128:
12685 default:
12686 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12687 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12688 break;
855e1111 12689 }
59e6b434
DM		 12690 } else {
12691 switch (cacheline_size) {
12692 case 16:
12693 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12694 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12695 DMA_RWCTRL_WRITE_BNDRY_16);
12696 break;
12697 }
12698 /* fallthrough */
12699 case 32:
12700 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12701 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12702 DMA_RWCTRL_WRITE_BNDRY_32);
12703 break;
12704 }
12705 /* fallthrough */
12706 case 64:
12707 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12708 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12709 DMA_RWCTRL_WRITE_BNDRY_64);
12710 break;
12711 }
12712 /* fallthrough */
12713 case 128:
12714 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12715 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12716 DMA_RWCTRL_WRITE_BNDRY_128);
12717 break;
12718 }
12719 /* fallthrough */
12720 case 256:
12721 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12722 DMA_RWCTRL_WRITE_BNDRY_256);
12723 break;
12724 case 512:
12725 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12726 DMA_RWCTRL_WRITE_BNDRY_512);
12727 break;
12728 case 1024:
12729 default:
12730 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12731 DMA_RWCTRL_WRITE_BNDRY_1024);
12732 break;
855e1111 12733 }
59e6b434
DM		 12734 }
12735
12736out:
12737 return val;
12738}
12739
1da177e4
LT		 12740static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12741{
12742 struct tg3_internal_buffer_desc test_desc;
12743 u32 sram_dma_descs;
12744 int i, ret;
12745
12746 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12747
12748 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12749 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12750 tw32(RDMAC_STATUS, 0);
12751 tw32(WDMAC_STATUS, 0);
12752
12753 tw32(BUFMGR_MODE, 0);
12754 tw32(FTQ_RESET, 0);
12755
12756 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12757 test_desc.addr_lo = buf_dma & 0xffffffff;
12758 test_desc.nic_mbuf = 0x00002100;
12759 test_desc.len = size;
12760
12761 /*
12762 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12763 * the *second* time the tg3 driver was getting loaded after an
12764 * initial scan.
12765 *
12766 * Broadcom tells me:
12767 * ...the DMA engine is connected to the GRC block and a DMA
12768 * reset may affect the GRC block in some unpredictable way...
12769 * The behavior of resets to individual blocks has not been tested.
12770 *
12771 * Broadcom noted the GRC reset will also reset all sub-components.
12772 */
12773 if (to_device) {
12774 test_desc.cqid_sqid = (13 << 8) | 2;
12775
12776 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12777 udelay(40);
12778 } else {
12779 test_desc.cqid_sqid = (16 << 8) | 7;
12780
12781 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12782 udelay(40);
12783 }
12784 test_desc.flags = 0x00000005;
12785
12786 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12787 u32 val;
12788
12789 val = *(((u32 *)&test_desc) + i);
12790 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12791 sram_dma_descs + (i * sizeof(u32)));
12792 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12793 }
12794 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12795
12796 if (to_device) {
12797 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12798 } else {
12799 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12800 }
12801
12802 ret = -ENODEV;
12803 for (i = 0; i < 40; i++) {
12804 u32 val;
12805
12806 if (to_device)
12807 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12808 else
12809 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12810 if ((val & 0xffff) == sram_dma_descs) {
12811 ret = 0;
12812 break;
12813 }
12814
12815 udelay(100);
12816 }
12817
12818 return ret;
12819}
12820
ded7340d 12821#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12822
12823static int __devinit tg3_test_dma(struct tg3 *tp)
12824{
12825 dma_addr_t buf_dma;
59e6b434 12826 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12827 int ret;
12828
12829 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12830 if (!buf) {
12831 ret = -ENOMEM;
12832 goto out_nofree;
12833 }
12834
12835 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12836 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12837
59e6b434 12838 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12839
12840 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12841 /* DMA read watermark not used on PCIE */
12842 tp->dma_rwctrl |= 0x00180000;
12843 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12846 tp->dma_rwctrl |= 0x003f0000;
12847 else
12848 tp->dma_rwctrl |= 0x003f000f;
12849 } else {
12850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12852 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12853 u32 read_water = 0x7;
1da177e4 12854
4a29cc2e
MC		 12855 /* If the 5704 is behind the EPB bridge, we can
12856 * do the less restrictive ONE_DMA workaround for
12857 * better performance.
12858 */
12859 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12860 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12861 tp->dma_rwctrl |= 0x8000;
12862 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12863 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12864
49afdeb6
MC		 12865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12866 read_water = 4;
59e6b434 12867 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12868 tp->dma_rwctrl |=
12869 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12870 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12871 (1 << 23);
4cf78e4f
MC		 12872 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12873 /* 5780 always in PCIX mode */
12874 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12875 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12876 /* 5714 always in PCIX mode */
12877 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12878 } else {
12879 tp->dma_rwctrl |= 0x001b000f;
12880 }
12881 }
12882
12883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12885 tp->dma_rwctrl &= 0xfffffff0;
12886
12887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12889 /* Remove this if it causes problems for some boards. */
12890 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12891
12892 /* On 5700/5701 chips, we need to set this bit.
12893 * Otherwise the chip will issue cacheline transactions
12894 * to streamable DMA memory with not all the byte
12895 * enables turned on. This is an error on several
12896 * RISC PCI controllers, in particular sparc64.
12897 *
12898 * On 5703/5704 chips, this bit has been reassigned
12899 * a different meaning. In particular, it is used
12900 * on those chips to enable a PCI-X workaround.
12901 */
12902 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12903 }
12904
12905 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12906
12907#if 0
12908 /* Unneeded, already done by tg3_get_invariants. */
12909 tg3_switch_clocks(tp);
12910#endif
12911
12912 ret = 0;
12913 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12914 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12915 goto out;
12916
59e6b434
DM		 12917 /* It is best to perform DMA test with maximum write burst size
12918 * to expose the 5700/5701 write DMA bug.
12919 */
12920 saved_dma_rwctrl = tp->dma_rwctrl;
12921 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12922 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12923
1da177e4
LT		 12924 while (1) {
12925 u32 *p = buf, i;
12926
12927 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12928 p[i] = i;
12929
12930 /* Send the buffer to the chip. */
12931 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12932 if (ret) {
12933 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12934 break;
12935 }
12936
12937#if 0
12938 /* validate data reached card RAM correctly. */
12939 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12940 u32 val;
12941 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12942 if (le32_to_cpu(val) != p[i]) {
12943 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12944 /* ret = -ENODEV here? */
12945 }
12946 p[i] = 0;
12947 }
12948#endif
12949 /* Now read it back. */
12950 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12951 if (ret) {
12952 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12953
12954 break;
12955 }
12956
12957 /* Verify it. */
12958 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12959 if (p[i] == i)
12960 continue;
12961
59e6b434
DM		 12962 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12963 DMA_RWCTRL_WRITE_BNDRY_16) {
12964 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12965 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12966 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12967 break;
12968 } else {
12969 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12970 ret = -ENODEV;
12971 goto out;
12972 }
12973 }
12974
12975 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12976 /* Success. */
12977 ret = 0;
12978 break;
12979 }
12980 }
59e6b434
DM		 12981 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12982 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12983 static struct pci_device_id dma_wait_state_chipsets[] = {
12984 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12985 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12986 { },
12987 };
12988
59e6b434 12989 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12990 * now look for chipsets that are known to expose the
12991 * DMA bug without failing the test.
59e6b434 12992 */
6d1cfbab
MC		 12993 if (pci_dev_present(dma_wait_state_chipsets)) {
12994 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12995 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12996 }
12997 else
12998 /* Safe to use the calculated DMA boundary. */
12999 tp->dma_rwctrl = saved_dma_rwctrl;
13000
59e6b434
DM		 13001 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13002 }
1da177e4
LT		 13003
13004out:
13005 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13006out_nofree:
13007 return ret;
13008}
13009
13010static void __devinit tg3_init_link_config(struct tg3 *tp)
13011{
13012 tp->link_config.advertising =
13013 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13014 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13015 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13016 ADVERTISED_Autoneg | ADVERTISED_MII);
13017 tp->link_config.speed = SPEED_INVALID;
13018 tp->link_config.duplex = DUPLEX_INVALID;
13019 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13020 tp->link_config.active_speed = SPEED_INVALID;
13021 tp->link_config.active_duplex = DUPLEX_INVALID;
13022 tp->link_config.phy_is_low_power = 0;
13023 tp->link_config.orig_speed = SPEED_INVALID;
13024 tp->link_config.orig_duplex = DUPLEX_INVALID;
13025 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13026}
13027
13028static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13029{
fdfec172
MC		 13030 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13031 tp->bufmgr_config.mbuf_read_dma_low_water =
13032 DEFAULT_MB_RDMA_LOW_WATER_5705;
13033 tp->bufmgr_config.mbuf_mac_rx_low_water =
13034 DEFAULT_MB_MACRX_LOW_WATER_5705;
13035 tp->bufmgr_config.mbuf_high_water =
13036 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13038 tp->bufmgr_config.mbuf_mac_rx_low_water =
13039 DEFAULT_MB_MACRX_LOW_WATER_5906;
13040 tp->bufmgr_config.mbuf_high_water =
13041 DEFAULT_MB_HIGH_WATER_5906;
13042 }
fdfec172
MC		 13043
13044 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13045 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13046 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13047 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13048 tp->bufmgr_config.mbuf_high_water_jumbo =
13049 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13050 } else {
13051 tp->bufmgr_config.mbuf_read_dma_low_water =
13052 DEFAULT_MB_RDMA_LOW_WATER;
13053 tp->bufmgr_config.mbuf_mac_rx_low_water =
13054 DEFAULT_MB_MACRX_LOW_WATER;
13055 tp->bufmgr_config.mbuf_high_water =
13056 DEFAULT_MB_HIGH_WATER;
13057
13058 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13059 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13060 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13061 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13062 tp->bufmgr_config.mbuf_high_water_jumbo =
13063 DEFAULT_MB_HIGH_WATER_JUMBO;
13064 }
1da177e4
LT		 13065
13066 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13067 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13068}
13069
13070static char * __devinit tg3_phy_string(struct tg3 *tp)
13071{
13072 switch (tp->phy_id & PHY_ID_MASK) {
13073 case PHY_ID_BCM5400: return "5400";
13074 case PHY_ID_BCM5401: return "5401";
13075 case PHY_ID_BCM5411: return "5411";
13076 case PHY_ID_BCM5701: return "5701";
13077 case PHY_ID_BCM5703: return "5703";
13078 case PHY_ID_BCM5704: return "5704";
13079 case PHY_ID_BCM5705: return "5705";
13080 case PHY_ID_BCM5750: return "5750";
85e94ced 13081 case PHY_ID_BCM5752: return "5752";
a4e2b347 13082 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13083 case PHY_ID_BCM5780: return "5780";
af36e6b6 13084 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13085 case PHY_ID_BCM5787: return "5787";
d30cdd28 13086 case PHY_ID_BCM5784: return "5784";
126a3368 13087 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13088 case PHY_ID_BCM5906: return "5906";
9936bcf6 13089 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13090 case PHY_ID_BCM8002: return "8002/serdes";
13091 case 0: return "serdes";
13092 default: return "unknown";
855e1111 13093 }
1da177e4
LT		 13094}
13095
f9804ddb
MC		 13096static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13097{
13098 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13099 strcpy(str, "PCI Express");
13100 return str;
13101 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13102 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13103
13104 strcpy(str, "PCIX:");
13105
13106 if ((clock_ctrl == 7) ||
13107 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13108 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13109 strcat(str, "133MHz");
13110 else if (clock_ctrl == 0)
13111 strcat(str, "33MHz");
13112 else if (clock_ctrl == 2)
13113 strcat(str, "50MHz");
13114 else if (clock_ctrl == 4)
13115 strcat(str, "66MHz");
13116 else if (clock_ctrl == 6)
13117 strcat(str, "100MHz");
f9804ddb
MC		 13118 } else {
13119 strcpy(str, "PCI:");
13120 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13121 strcat(str, "66MHz");
13122 else
13123 strcat(str, "33MHz");
13124 }
13125 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13126 strcat(str, ":32-bit");
13127 else
13128 strcat(str, ":64-bit");
13129 return str;
13130}
13131
8c2dc7e1 13132static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13133{
13134 struct pci_dev *peer;
13135 unsigned int func, devnr = tp->pdev->devfn & ~7;
13136
13137 for (func = 0; func < 8; func++) {
13138 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13139 if (peer && peer != tp->pdev)
13140 break;
13141 pci_dev_put(peer);
13142 }
16fe9d74
MC		 13143 /* 5704 can be configured in single-port mode, set peer to
13144 * tp->pdev in that case.
13145 */
13146 if (!peer) {
13147 peer = tp->pdev;
13148 return peer;
13149 }
1da177e4
LT		 13150
13151 /*
13152 * We don't need to keep the refcount elevated; there's no way
13153 * to remove one half of this device without removing the other
13154 */
13155 pci_dev_put(peer);
13156
13157 return peer;
13158}
13159
15f9850d
DM		 13160static void __devinit tg3_init_coal(struct tg3 *tp)
13161{
13162 struct ethtool_coalesce *ec = &tp->coal;
13163
13164 memset(ec, 0, sizeof(*ec));
13165 ec->cmd = ETHTOOL_GCOALESCE;
13166 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13167 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13168 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13169 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13170 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13171 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13172 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13173 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13174 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13175
13176 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13177 HOSTCC_MODE_CLRTICK_TXBD)) {
13178 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13179 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13180 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13181 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13182 }
d244c892
MC		 13183
13184 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13185 ec->rx_coalesce_usecs_irq = 0;
13186 ec->tx_coalesce_usecs_irq = 0;
13187 ec->stats_block_coalesce_usecs = 0;
13188 }
15f9850d
DM		 13189}
13190
7c7d64b8
SH		 13191static const struct net_device_ops tg3_netdev_ops = {
13192 .ndo_open = tg3_open,
13193 .ndo_stop = tg3_close,
00829823
SH		 13194 .ndo_start_xmit = tg3_start_xmit,
13195 .ndo_get_stats = tg3_get_stats,
13196 .ndo_validate_addr = eth_validate_addr,
13197 .ndo_set_multicast_list = tg3_set_rx_mode,
13198 .ndo_set_mac_address = tg3_set_mac_addr,
13199 .ndo_do_ioctl = tg3_ioctl,
13200 .ndo_tx_timeout = tg3_tx_timeout,
13201 .ndo_change_mtu = tg3_change_mtu,
13202#if TG3_VLAN_TAG_USED
13203 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13204#endif
13205#ifdef CONFIG_NET_POLL_CONTROLLER
13206 .ndo_poll_controller = tg3_poll_controller,
13207#endif
13208};
13209
13210static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13211 .ndo_open = tg3_open,
13212 .ndo_stop = tg3_close,
13213 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13214 .ndo_get_stats = tg3_get_stats,
13215 .ndo_validate_addr = eth_validate_addr,
13216 .ndo_set_multicast_list = tg3_set_rx_mode,
13217 .ndo_set_mac_address = tg3_set_mac_addr,
13218 .ndo_do_ioctl = tg3_ioctl,
13219 .ndo_tx_timeout = tg3_tx_timeout,
13220 .ndo_change_mtu = tg3_change_mtu,
13221#if TG3_VLAN_TAG_USED
13222 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13223#endif
13224#ifdef CONFIG_NET_POLL_CONTROLLER
13225 .ndo_poll_controller = tg3_poll_controller,
13226#endif
13227};
13228
1da177e4
LT		 13229static int __devinit tg3_init_one(struct pci_dev *pdev,
13230 const struct pci_device_id *ent)
13231{
13232 static int tg3_version_printed = 0;
1da177e4
LT		 13233 struct net_device *dev;
13234 struct tg3 *tp;
d6645372 13235 int err, pm_cap;
f9804ddb 13236 char str[40];
72f2afb8 13237 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13238
13239 if (tg3_version_printed++ == 0)
13240 printk(KERN_INFO "%s", version);
13241
13242 err = pci_enable_device(pdev);
13243 if (err) {
13244 printk(KERN_ERR PFX "Cannot enable PCI device, "
13245 "aborting.\n");
13246 return err;
13247 }
13248
1da177e4
LT		 13249 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13250 if (err) {
13251 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13252 "aborting.\n");
13253 goto err_out_disable_pdev;
13254 }
13255
13256 pci_set_master(pdev);
13257
13258 /* Find power-management capability. */
13259 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13260 if (pm_cap == 0) {
13261 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13262 "aborting.\n");
13263 err = -EIO;
13264 goto err_out_free_res;
13265 }
13266
1da177e4
LT		 13267 dev = alloc_etherdev(sizeof(*tp));
13268 if (!dev) {
13269 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13270 err = -ENOMEM;
13271 goto err_out_free_res;
13272 }
13273
1da177e4
LT		 13274 SET_NETDEV_DEV(dev, &pdev->dev);
13275
1da177e4
LT		 13276#if TG3_VLAN_TAG_USED
13277 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13278#endif
13279
13280 tp = netdev_priv(dev);
13281 tp->pdev = pdev;
13282 tp->dev = dev;
13283 tp->pm_cap = pm_cap;
1da177e4
LT		 13284 tp->rx_mode = TG3_DEF_RX_MODE;
13285 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13286
1da177e4
LT		 13287 if (tg3_debug > 0)
13288 tp->msg_enable = tg3_debug;
13289 else
13290 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13291
13292 /* The word/byte swap controls here control register access byte
13293 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13294 * setting below.
13295 */
13296 tp->misc_host_ctrl =
13297 MISC_HOST_CTRL_MASK_PCI_INT |
13298 MISC_HOST_CTRL_WORD_SWAP |
13299 MISC_HOST_CTRL_INDIR_ACCESS |
13300 MISC_HOST_CTRL_PCISTATE_RW;
13301
13302 /* The NONFRM (non-frame) byte/word swap controls take effect
13303 * on descriptor entries, anything which isn't packet data.
13304 *
13305 * The StrongARM chips on the board (one for tx, one for rx)
13306 * are running in big-endian mode.
13307 */
13308 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13309 GRC_MODE_WSWAP_NONFRM_DATA);
13310#ifdef __BIG_ENDIAN
13311 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13312#endif
13313 spin_lock_init(&tp->lock);
1da177e4 13314 spin_lock_init(&tp->indirect_lock);
c4028958 13315 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13316
d5fe488a 13317 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13318 if (!tp->regs) {
1da177e4
LT		 13319 printk(KERN_ERR PFX "Cannot map device registers, "
13320 "aborting.\n");
13321 err = -ENOMEM;
13322 goto err_out_free_dev;
13323 }
13324
13325 tg3_init_link_config(tp);
13326
1da177e4
LT		 13327 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13328 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13329 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13330
bea3348e 13331 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13332 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13333 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13334 dev->irq = pdev->irq;
1da177e4
LT		 13335
13336 err = tg3_get_invariants(tp);
13337 if (err) {
13338 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13339 "aborting.\n");
13340 goto err_out_iounmap;
13341 }
13342
321d32a0 13343 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13345 dev->netdev_ops = &tg3_netdev_ops;
13346 else
13347 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13348
13349
4a29cc2e
MC		 13350 /* The EPB bridge inside 5714, 5715, and 5780 and any
13351 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13352 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13353 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13354 * do DMA address check in tg3_start_xmit().
13355 */
4a29cc2e 13356 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13357 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13358 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13359 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13360#ifdef CONFIG_HIGHMEM
6a35528a 13361 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13362#endif
4a29cc2e 13363 } else
6a35528a 13364 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13365
13366 /* Configure DMA attributes. */
284901a9 13367 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13368 err = pci_set_dma_mask(pdev, dma_mask);
13369 if (!err) {
13370 dev->features |= NETIF_F_HIGHDMA;
13371 err = pci_set_consistent_dma_mask(pdev,
13372 persist_dma_mask);
13373 if (err < 0) {
13374 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13375 "DMA for consistent allocations\n");
13376 goto err_out_iounmap;
13377 }
13378 }
13379 }
284901a9
YH		 13380 if (err || dma_mask == DMA_BIT_MASK(32)) {
13381 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13382 if (err) {
13383 printk(KERN_ERR PFX "No usable DMA configuration, "
13384 "aborting.\n");
13385 goto err_out_iounmap;
13386 }
13387 }
13388
fdfec172 13389 tg3_init_bufmgr_config(tp);
1da177e4 13390
077f849d 13391 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13392 tp->fw_needed = FIRMWARE_TG3;
077f849d 13393
1da177e4
LT		 13394 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13395 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13396 }
13397 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13399 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13400 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13401 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13402 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13403 } else {
7f62ad5d 13404 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13406 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13407 else
9e9fd12d 13408 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13409 }
1da177e4 13410
4e3a7aaa
MC		 13411 /* TSO is on by default on chips that support hardware TSO.
13412 * Firmware TSO on older chips gives lower performance, so it
13413 * is off by default, but can be enabled using ethtool.
13414 */
b0026624 13415 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13416 if (dev->features & NETIF_F_IP_CSUM)
13417 dev->features |= NETIF_F_TSO;
13418 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13419 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13420 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13422 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13423 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13426 dev->features |= NETIF_F_TSO_ECN;
b0026624 13427 }
1da177e4 13428
1da177e4
LT		 13429
13430 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13431 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13432 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13433 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13434 tp->rx_pending = 63;
13435 }
13436
1da177e4
LT		 13437 err = tg3_get_device_address(tp);
13438 if (err) {
13439 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13440 "aborting.\n");
077f849d 13441 goto err_out_fw;
1da177e4
LT		 13442 }
13443
c88864df 13444 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13445 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13446 if (!tp->aperegs) {
c88864df
MC		 13447 printk(KERN_ERR PFX "Cannot map APE registers, "
13448 "aborting.\n");
13449 err = -ENOMEM;
077f849d 13450 goto err_out_fw;
c88864df
MC		 13451 }
13452
13453 tg3_ape_lock_init(tp);
7fd76445
MC		 13454
13455 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13456 tg3_read_dash_ver(tp);
c88864df
MC		 13457 }
13458
1da177e4
LT		 13459 /*
13460 * Reset chip in case UNDI or EFI driver did not shutdown
13461 * DMA self test will enable WDMAC and we'll see (spurious)
13462 * pending DMA on the PCI bus at that point.
13463 */
13464 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13465 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13466 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13467 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13468 }
13469
13470 err = tg3_test_dma(tp);
13471 if (err) {
13472 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13473 goto err_out_apeunmap;
1da177e4
LT		 13474 }
13475
1da177e4
LT		 13476 /* flow control autonegotiation is default behavior */
13477 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13478 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13479
15f9850d
DM		 13480 tg3_init_coal(tp);
13481
c49a1561
MC		 13482 pci_set_drvdata(pdev, dev);
13483
1da177e4
LT		 13484 err = register_netdev(dev);
13485 if (err) {
13486 printk(KERN_ERR PFX "Cannot register net device, "
13487 "aborting.\n");
0d3031d9 13488 goto err_out_apeunmap;
1da177e4
LT		 13489 }
13490
df59c940 13491 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13492 dev->name,
13493 tp->board_part_number,
13494 tp->pci_chip_rev_id,
f9804ddb 13495 tg3_bus_string(tp, str),
e174961c 13496 dev->dev_addr);
1da177e4 13497
df59c940
MC		 13498 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13499 printk(KERN_INFO
13500 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13501 tp->dev->name,
13502 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13503 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13504 else
13505 printk(KERN_INFO
13506 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13507 tp->dev->name, tg3_phy_string(tp),
13508 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13509 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13510 "10/100/1000Base-T")),
13511 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13512
13513 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13514 dev->name,
13515 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13516 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13517 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13518 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13519 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13520 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13521 dev->name, tp->dma_rwctrl,
284901a9 13522 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13523 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13524
13525 return 0;
13526
0d3031d9
MC		 13527err_out_apeunmap:
13528 if (tp->aperegs) {
13529 iounmap(tp->aperegs);
13530 tp->aperegs = NULL;
13531 }
13532
077f849d
JSR		 13533err_out_fw:
13534 if (tp->fw)
13535 release_firmware(tp->fw);
13536
1da177e4 13537err_out_iounmap:
6892914f
MC		 13538 if (tp->regs) {
13539 iounmap(tp->regs);
22abe310 13540 tp->regs = NULL;
6892914f 13541 }
1da177e4
LT		 13542
13543err_out_free_dev:
13544 free_netdev(dev);
13545
13546err_out_free_res:
13547 pci_release_regions(pdev);
13548
13549err_out_disable_pdev:
13550 pci_disable_device(pdev);
13551 pci_set_drvdata(pdev, NULL);
13552 return err;
13553}
13554
13555static void __devexit tg3_remove_one(struct pci_dev *pdev)
13556{
13557 struct net_device *dev = pci_get_drvdata(pdev);
13558
13559 if (dev) {
13560 struct tg3 *tp = netdev_priv(dev);
13561
077f849d
JSR		 13562 if (tp->fw)
13563 release_firmware(tp->fw);
13564
7faa006f 13565 flush_scheduled_work();
158d7abd 13566
b02fd9e3
MC		 13567 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13568 tg3_phy_fini(tp);
158d7abd 13569 tg3_mdio_fini(tp);
b02fd9e3 13570 }
158d7abd 13571
1da177e4 13572 unregister_netdev(dev);
0d3031d9
MC		 13573 if (tp->aperegs) {
13574 iounmap(tp->aperegs);
13575 tp->aperegs = NULL;
13576 }
6892914f
MC		 13577 if (tp->regs) {
13578 iounmap(tp->regs);
22abe310 13579 tp->regs = NULL;
6892914f 13580 }
1da177e4
LT		 13581 free_netdev(dev);
13582 pci_release_regions(pdev);
13583 pci_disable_device(pdev);
13584 pci_set_drvdata(pdev, NULL);
13585 }
13586}
13587
13588static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13589{
13590 struct net_device *dev = pci_get_drvdata(pdev);
13591 struct tg3 *tp = netdev_priv(dev);
12dac075 13592 pci_power_t target_state;
1da177e4
LT		 13593 int err;
13594
3e0c95fd
MC		 13595 /* PCI register 4 needs to be saved whether netif_running() or not.
13596 * MSI address and data need to be saved if using MSI and
13597 * netif_running().
13598 */
13599 pci_save_state(pdev);
13600
1da177e4
LT		 13601 if (!netif_running(dev))
13602 return 0;
13603
7faa006f 13604 flush_scheduled_work();
b02fd9e3 13605 tg3_phy_stop(tp);
1da177e4
LT		 13606 tg3_netif_stop(tp);
13607
13608 del_timer_sync(&tp->timer);
13609
f47c11ee 13610 tg3_full_lock(tp, 1);
1da177e4 13611 tg3_disable_ints(tp);
f47c11ee 13612 tg3_full_unlock(tp);
1da177e4
LT		 13613
13614 netif_device_detach(dev);
13615
f47c11ee 13616 tg3_full_lock(tp, 0);
944d980e 13617 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13618 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13619 tg3_full_unlock(tp);
1da177e4 13620
12dac075
RW		 13621 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13622
13623 err = tg3_set_power_state(tp, target_state);
1da177e4 13624 if (err) {
b02fd9e3
MC		 13625 int err2;
13626
f47c11ee 13627 tg3_full_lock(tp, 0);
1da177e4 13628
6a9eba15 13629 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13630 err2 = tg3_restart_hw(tp, 1);
13631 if (err2)
b9ec6c1b 13632 goto out;
1da177e4
LT		 13633
13634 tp->timer.expires = jiffies + tp->timer_offset;
13635 add_timer(&tp->timer);
13636
13637 netif_device_attach(dev);
13638 tg3_netif_start(tp);
13639
b9ec6c1b 13640out:
f47c11ee 13641 tg3_full_unlock(tp);
b02fd9e3
MC		 13642
13643 if (!err2)
13644 tg3_phy_start(tp);
1da177e4
LT		 13645 }
13646
13647 return err;
13648}
13649
13650static int tg3_resume(struct pci_dev *pdev)
13651{
13652 struct net_device *dev = pci_get_drvdata(pdev);
13653 struct tg3 *tp = netdev_priv(dev);
13654 int err;
13655
3e0c95fd
MC		 13656 pci_restore_state(tp->pdev);
13657
1da177e4
LT		 13658 if (!netif_running(dev))
13659 return 0;
13660
bc1c7567 13661 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13662 if (err)
13663 return err;
13664
13665 netif_device_attach(dev);
13666
f47c11ee 13667 tg3_full_lock(tp, 0);
1da177e4 13668
6a9eba15 13669 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13670 err = tg3_restart_hw(tp, 1);
13671 if (err)
13672 goto out;
1da177e4
LT		 13673
13674 tp->timer.expires = jiffies + tp->timer_offset;
13675 add_timer(&tp->timer);
13676
1da177e4
LT		 13677 tg3_netif_start(tp);
13678
b9ec6c1b 13679out:
f47c11ee 13680 tg3_full_unlock(tp);
1da177e4 13681
b02fd9e3
MC		 13682 if (!err)
13683 tg3_phy_start(tp);
13684
b9ec6c1b 13685 return err;
1da177e4
LT		 13686}
13687
13688static struct pci_driver tg3_driver = {
13689 .name = DRV_MODULE_NAME,
13690 .id_table = tg3_pci_tbl,
13691 .probe = tg3_init_one,
13692 .remove = __devexit_p(tg3_remove_one),
13693 .suspend = tg3_suspend,
13694 .resume = tg3_resume
13695};
13696
13697static int __init tg3_init(void)
13698{
29917620 13699 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13700}
13701
13702static void __exit tg3_cleanup(void)
13703{
13704 pci_unregister_driver(&tg3_driver);
13705}
13706
13707module_init(tg3_init);
13708module_exit(tg3_cleanup);
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