]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
tg3: Move general int members to a per-int struct
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT
1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT
8 *
9 * Firmware is:
49cabf49
MC
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT
16 */
17
1da177e4
LT
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT
37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT
44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT
47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT
56#endif
57
63532394
MC
58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT
61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT
67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
f656f398
MC
71#define DRV_MODULE_VERSION "3.100"
72#define DRV_MODULE_RELDATE "August 25, 2009"
1da177e4
LT
73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT
96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
79ed5ac7
MC
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
1da177e4 122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 123 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT
126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC
128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT
137
138/* minimum number of free TX descriptors required to wake up TX process */
42952231 139#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 140
ad829268
MC
141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT
143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC
146#define TG3_NUM_TEST 6
147
077f849d
JSR
148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT
152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR
159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
1da177e4
LT
163
164static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165module_param(tg3_debug, int, 0);
166MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK
235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
1da177e4
LT
243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
50da859d 247static const struct {
1da177e4
LT
248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
50da859d 328static const struct {
4cafd3f5
MC
329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
b401e9e2
MC
339static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342}
343
344static u32 tg3_read32(struct tg3 *tp, u32 off)
345{
6aa20a22 346 return (readl(tp->regs + off));
b401e9e2
MC
347}
348
0d3031d9
MC
349static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->aperegs + off);
352}
353
354static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355{
356 return (readl(tp->aperegs + off));
357}
358
1da177e4
LT
359static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360{
6892914f
MC
361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC
364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC
367}
368
369static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370{
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
1da177e4
LT
373}
374
6892914f 375static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 376{
6892914f
MC
377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385}
386
387static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388{
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
1da177e4 400 }
6892914f
MC
401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415}
416
417static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418{
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427}
428
b401e9e2
MC
429/* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 435{
b401e9e2
MC
436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
1da177e4
LT
452}
453
09ee929c
MC
454static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455{
456 tp->write32_mbox(tp, off, val);
6892914f
MC
457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
09ee929c
MC
460}
461
20094930 462static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT
463{
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470}
471
b5d3772c
MC
472static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473{
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475}
476
477static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478{
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480}
481
20094930 482#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 483#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC
484#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 486#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC
487
488#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC
489#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 491#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT
492
493static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494{
6892914f
MC
495 unsigned long flags;
496
b5d3772c
MC
497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
6892914f 501 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC
502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 505
bbadf503
MC
506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 511
bbadf503
MC
512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM
516}
517
1da177e4
LT
518static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519{
6892914f
MC
520 unsigned long flags;
521
b5d3772c
MC
522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
6892914f 528 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC
529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 532
bbadf503
MC
533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
6892914f 542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT
543}
544
0d3031d9
MC
545static void tg3_ape_lock_init(struct tg3 *tp)
546{
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553}
554
555static int tg3_ape_lock(struct tg3 *tp, int locknum)
556{
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
77b483f1 565 case TG3_APE_LOCK_GRC:
0d3031d9
MC
566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593}
594
595static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596{
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
77b483f1 603 case TG3_APE_LOCK_GRC:
0d3031d9
MC
604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612}
613
1da177e4
LT
614static void tg3_disable_ints(struct tg3 *tp)
615{
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 618 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
1da177e4
LT
619}
620
621static inline void tg3_cond_int(struct tg3 *tp)
622{
38f3843e 623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
898a56f8 624 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1da177e4 625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC
626 else
627 tw32(HOSTCC_MODE, tp->coalesce_mode |
628 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT
629}
630
631static void tg3_enable_ints(struct tg3 *tp)
632{
898a56f8 633 struct tg3_napi *tnapi = &tp->napi[0];
bbe832c0
MC
634 tp->irq_sync = 0;
635 wmb();
636
1da177e4
LT
637 tw32(TG3PCI_MISC_HOST_CTRL,
638 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 639 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
fcfa0a32 640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
898a56f8 641 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT
642 tg3_cond_int(tp);
643}
644
17375d25 645static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 646{
17375d25 647 struct tg3 *tp = tnapi->tp;
898a56f8 648 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC
649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
659 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
660 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
661 work_exists = 1;
662
663 return work_exists;
664}
665
17375d25 666/* tg3_int_reenable
04237ddd
MC
667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
6aa20a22 669 * which reenables interrupts
1da177e4 670 */
17375d25 671static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 672{
17375d25
MC
673 struct tg3 *tp = tnapi->tp;
674
898a56f8 675 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT
676 mmiowb();
677
fac9b83e
DM
678 /* When doing tagged status, this work check is unnecessary.
679 * The last_tag we write above tells the chip which piece of
680 * work we've completed.
681 */
682 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 683 tg3_has_work(tnapi))
04237ddd
MC
684 tw32(HOSTCC_MODE, tp->coalesce_mode |
685 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT
686}
687
688static inline void tg3_netif_stop(struct tg3 *tp)
689{
bbe832c0 690 tp->dev->trans_start = jiffies; /* prevent tx timeout */
8ef0442f 691 napi_disable(&tp->napi[0].napi);
1da177e4
LT
692 netif_tx_disable(tp->dev);
693}
694
695static inline void tg3_netif_start(struct tg3 *tp)
696{
898a56f8 697 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT
698 netif_wake_queue(tp->dev);
699 /* NOTE: unconditional netif_wake_queue is only appropriate
700 * so long as all callers are assured to have free tx slots
701 * (such as after tg3_init_hw)
702 */
898a56f8
MC
703 napi_enable(&tnapi->napi);
704 tnapi->hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 705 tg3_enable_ints(tp);
1da177e4
LT
706}
707
708static void tg3_switch_clocks(struct tg3 *tp)
709{
710 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
711 u32 orig_clock_ctrl;
712
795d01c5
MC
713 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
714 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC
715 return;
716
1da177e4
LT
717 orig_clock_ctrl = clock_ctrl;
718 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
719 CLOCK_CTRL_CLKRUN_OENABLE |
720 0x1f);
721 tp->pci_clock_ctrl = clock_ctrl;
722
723 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
724 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC
725 tw32_wait_f(TG3PCI_CLOCK_CTRL,
726 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT
727 }
728 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC
729 tw32_wait_f(TG3PCI_CLOCK_CTRL,
730 clock_ctrl |
731 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
732 40);
733 tw32_wait_f(TG3PCI_CLOCK_CTRL,
734 clock_ctrl | (CLOCK_CTRL_ALTCLK),
735 40);
1da177e4 736 }
b401e9e2 737 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT
738}
739
740#define PHY_BUSY_LOOPS 5000
741
742static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
743{
744 u32 frame_val;
745 unsigned int loops;
746 int ret;
747
748 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
749 tw32_f(MAC_MI_MODE,
750 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
751 udelay(80);
752 }
753
754 *val = 0x0;
755
756 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
757 MI_COM_PHY_ADDR_MASK);
758 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
759 MI_COM_REG_ADDR_MASK);
760 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 761
1da177e4
LT
762 tw32_f(MAC_MI_COM, frame_val);
763
764 loops = PHY_BUSY_LOOPS;
765 while (loops != 0) {
766 udelay(10);
767 frame_val = tr32(MAC_MI_COM);
768
769 if ((frame_val & MI_COM_BUSY) == 0) {
770 udelay(5);
771 frame_val = tr32(MAC_MI_COM);
772 break;
773 }
774 loops -= 1;
775 }
776
777 ret = -EBUSY;
778 if (loops != 0) {
779 *val = frame_val & MI_COM_DATA_MASK;
780 ret = 0;
781 }
782
783 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
784 tw32_f(MAC_MI_MODE, tp->mi_mode);
785 udelay(80);
786 }
787
788 return ret;
789}
790
791static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
792{
793 u32 frame_val;
794 unsigned int loops;
795 int ret;
796
7f97a4bd 797 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC
798 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
799 return 0;
800
1da177e4
LT
801 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802 tw32_f(MAC_MI_MODE,
803 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
804 udelay(80);
805 }
806
807 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (val & MI_COM_DATA_MASK);
812 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 813
1da177e4
LT
814 tw32_f(MAC_MI_COM, frame_val);
815
816 loops = PHY_BUSY_LOOPS;
817 while (loops != 0) {
818 udelay(10);
819 frame_val = tr32(MAC_MI_COM);
820 if ((frame_val & MI_COM_BUSY) == 0) {
821 udelay(5);
822 frame_val = tr32(MAC_MI_COM);
823 break;
824 }
825 loops -= 1;
826 }
827
828 ret = -EBUSY;
829 if (loops != 0)
830 ret = 0;
831
832 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
833 tw32_f(MAC_MI_MODE, tp->mi_mode);
834 udelay(80);
835 }
836
837 return ret;
838}
839
95e2869a
MC
840static int tg3_bmcr_reset(struct tg3 *tp)
841{
842 u32 phy_control;
843 int limit, err;
844
845 /* OK, reset it, and poll the BMCR_RESET bit until it
846 * clears or we time out.
847 */
848 phy_control = BMCR_RESET;
849 err = tg3_writephy(tp, MII_BMCR, phy_control);
850 if (err != 0)
851 return -EBUSY;
852
853 limit = 5000;
854 while (limit--) {
855 err = tg3_readphy(tp, MII_BMCR, &phy_control);
856 if (err != 0)
857 return -EBUSY;
858
859 if ((phy_control & BMCR_RESET) == 0) {
860 udelay(40);
861 break;
862 }
863 udelay(10);
864 }
d4675b52 865 if (limit < 0)
95e2869a
MC
866 return -EBUSY;
867
868 return 0;
869}
870
158d7abd
MC
871static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
872{
3d16543d 873 struct tg3 *tp = bp->priv;
158d7abd
MC
874 u32 val;
875
876 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
877 return -EAGAIN;
878
879 if (tg3_readphy(tp, reg, &val))
880 return -EIO;
881
882 return val;
883}
884
885static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
886{
3d16543d 887 struct tg3 *tp = bp->priv;
158d7abd
MC
888
889 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
890 return -EAGAIN;
891
892 if (tg3_writephy(tp, reg, val))
893 return -EIO;
894
895 return 0;
896}
897
898static int tg3_mdio_reset(struct mii_bus *bp)
899{
900 return 0;
901}
902
9c61d6bc 903static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC
904{
905 u32 val;
fcb389df 906 struct phy_device *phydev;
a9daf367 907
fcb389df
MC
908 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
909 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
910 case TG3_PHY_ID_BCM50610:
911 val = MAC_PHYCFG2_50610_LED_MODES;
912 break;
913 case TG3_PHY_ID_BCMAC131:
914 val = MAC_PHYCFG2_AC131_LED_MODES;
915 break;
916 case TG3_PHY_ID_RTL8211C:
917 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
918 break;
919 case TG3_PHY_ID_RTL8201E:
920 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
921 break;
922 default:
a9daf367 923 return;
fcb389df
MC
924 }
925
926 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
927 tw32(MAC_PHYCFG2, val);
928
929 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC
930 val &= ~(MAC_PHYCFG1_RGMII_INT |
931 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
932 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC
933 tw32(MAC_PHYCFG1, val);
934
935 return;
936 }
937
938 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
939 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
940 MAC_PHYCFG2_FMODE_MASK_MASK |
941 MAC_PHYCFG2_GMODE_MASK_MASK |
942 MAC_PHYCFG2_ACT_MASK_MASK |
943 MAC_PHYCFG2_QUAL_MASK_MASK |
944 MAC_PHYCFG2_INBAND_ENABLE;
945
946 tw32(MAC_PHYCFG2, val);
a9daf367 947
bb85fbb6
MC
948 val = tr32(MAC_PHYCFG1);
949 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
950 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
951 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC
952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
953 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
954 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
955 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
956 }
bb85fbb6
MC
957 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
958 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
959 tw32(MAC_PHYCFG1, val);
a9daf367 960
a9daf367
MC
961 val = tr32(MAC_EXT_RGMII_MODE);
962 val &= ~(MAC_RGMII_MODE_RX_INT_B |
963 MAC_RGMII_MODE_RX_QUALITY |
964 MAC_RGMII_MODE_RX_ACTIVITY |
965 MAC_RGMII_MODE_RX_ENG_DET |
966 MAC_RGMII_MODE_TX_ENABLE |
967 MAC_RGMII_MODE_TX_LOWPWR |
968 MAC_RGMII_MODE_TX_RESET);
fcb389df 969 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC
970 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
971 val |= MAC_RGMII_MODE_RX_INT_B |
972 MAC_RGMII_MODE_RX_QUALITY |
973 MAC_RGMII_MODE_RX_ACTIVITY |
974 MAC_RGMII_MODE_RX_ENG_DET;
975 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
976 val |= MAC_RGMII_MODE_TX_ENABLE |
977 MAC_RGMII_MODE_TX_LOWPWR |
978 MAC_RGMII_MODE_TX_RESET;
979 }
980 tw32(MAC_EXT_RGMII_MODE, val);
981}
982
158d7abd
MC
983static void tg3_mdio_start(struct tg3 *tp)
984{
985 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 986 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 987 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 988 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC
989 }
990
991 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
992 tw32_f(MAC_MI_MODE, tp->mi_mode);
993 udelay(80);
a9daf367 994
9c61d6bc
MC
995 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
997 tg3_mdio_config_5785(tp);
158d7abd
MC
998}
999
1000static void tg3_mdio_stop(struct tg3 *tp)
1001{
1002 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1003 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1004 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1005 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC
1006 }
1007}
1008
1009static int tg3_mdio_init(struct tg3 *tp)
1010{
1011 int i;
1012 u32 reg;
a9daf367 1013 struct phy_device *phydev;
158d7abd
MC
1014
1015 tg3_mdio_start(tp);
1016
1017 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1018 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1019 return 0;
1020
298cf9be
LB
1021 tp->mdio_bus = mdiobus_alloc();
1022 if (tp->mdio_bus == NULL)
1023 return -ENOMEM;
158d7abd 1024
298cf9be
LB
1025 tp->mdio_bus->name = "tg3 mdio bus";
1026 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1027 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB
1028 tp->mdio_bus->priv = tp;
1029 tp->mdio_bus->parent = &tp->pdev->dev;
1030 tp->mdio_bus->read = &tg3_mdio_read;
1031 tp->mdio_bus->write = &tg3_mdio_write;
1032 tp->mdio_bus->reset = &tg3_mdio_reset;
1033 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1034 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC
1035
1036 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1037 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC
1038
1039 /* The bus registration will look for all the PHYs on the mdio bus.
1040 * Unfortunately, it does not ensure the PHY is powered up before
1041 * accessing the PHY ID registers. A chip reset is the
1042 * quickest way to bring the device back to an operational state..
1043 */
1044 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1045 tg3_bmcr_reset(tp);
1046
298cf9be 1047 i = mdiobus_register(tp->mdio_bus);
a9daf367 1048 if (i) {
158d7abd
MC
1049 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1050 tp->dev->name, i);
9c61d6bc 1051 mdiobus_free(tp->mdio_bus);
a9daf367
MC
1052 return i;
1053 }
158d7abd 1054
298cf9be 1055 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1056
9c61d6bc
MC
1057 if (!phydev || !phydev->drv) {
1058 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1059 mdiobus_unregister(tp->mdio_bus);
1060 mdiobus_free(tp->mdio_bus);
1061 return -ENODEV;
1062 }
1063
1064 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC
1065 case TG3_PHY_ID_BCM57780:
1066 phydev->interface = PHY_INTERFACE_MODE_GMII;
1067 break;
a9daf367 1068 case TG3_PHY_ID_BCM50610:
a9daf367
MC
1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1070 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1073 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1074 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC
1075 /* fallthru */
1076 case TG3_PHY_ID_RTL8211C:
1077 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1078 break;
fcb389df 1079 case TG3_PHY_ID_RTL8201E:
a9daf367
MC
1080 case TG3_PHY_ID_BCMAC131:
1081 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1082 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC
1083 break;
1084 }
1085
9c61d6bc
MC
1086 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1087
1088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1089 tg3_mdio_config_5785(tp);
a9daf367
MC
1090
1091 return 0;
158d7abd
MC
1092}
1093
1094static void tg3_mdio_fini(struct tg3 *tp)
1095{
1096 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1097 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB
1098 mdiobus_unregister(tp->mdio_bus);
1099 mdiobus_free(tp->mdio_bus);
158d7abd
MC
1100 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1101 }
1102}
1103
4ba526ce
MC
1104/* tp->lock is held. */
1105static inline void tg3_generate_fw_event(struct tg3 *tp)
1106{
1107 u32 val;
1108
1109 val = tr32(GRC_RX_CPU_EVENT);
1110 val |= GRC_RX_CPU_DRIVER_EVENT;
1111 tw32_f(GRC_RX_CPU_EVENT, val);
1112
1113 tp->last_event_jiffies = jiffies;
1114}
1115
1116#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1117
95e2869a
MC
1118/* tp->lock is held. */
1119static void tg3_wait_for_event_ack(struct tg3 *tp)
1120{
1121 int i;
4ba526ce
MC
1122 unsigned int delay_cnt;
1123 long time_remain;
1124
1125 /* If enough time has passed, no wait is necessary. */
1126 time_remain = (long)(tp->last_event_jiffies + 1 +
1127 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1128 (long)jiffies;
1129 if (time_remain < 0)
1130 return;
1131
1132 /* Check if we can shorten the wait time. */
1133 delay_cnt = jiffies_to_usecs(time_remain);
1134 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1135 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1136 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1137
4ba526ce 1138 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC
1139 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1140 break;
4ba526ce 1141 udelay(8);
95e2869a
MC
1142 }
1143}
1144
1145/* tp->lock is held. */
1146static void tg3_ump_link_report(struct tg3 *tp)
1147{
1148 u32 reg;
1149 u32 val;
1150
1151 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1152 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1153 return;
1154
1155 tg3_wait_for_event_ack(tp);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1158
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1160
1161 val = 0;
1162 if (!tg3_readphy(tp, MII_BMCR, &reg))
1163 val = reg << 16;
1164 if (!tg3_readphy(tp, MII_BMSR, &reg))
1165 val |= (reg & 0xffff);
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1167
1168 val = 0;
1169 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1170 val = reg << 16;
1171 if (!tg3_readphy(tp, MII_LPA, &reg))
1172 val |= (reg & 0xffff);
1173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1174
1175 val = 0;
1176 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1177 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1178 val = reg << 16;
1179 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1180 val |= (reg & 0xffff);
1181 }
1182 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1183
1184 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1185 val = reg << 16;
1186 else
1187 val = 0;
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1189
4ba526ce 1190 tg3_generate_fw_event(tp);
95e2869a
MC
1191}
1192
1193static void tg3_link_report(struct tg3 *tp)
1194{
1195 if (!netif_carrier_ok(tp->dev)) {
1196 if (netif_msg_link(tp))
1197 printk(KERN_INFO PFX "%s: Link is down.\n",
1198 tp->dev->name);
1199 tg3_ump_link_report(tp);
1200 } else if (netif_msg_link(tp)) {
1201 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1202 tp->dev->name,
1203 (tp->link_config.active_speed == SPEED_1000 ?
1204 1000 :
1205 (tp->link_config.active_speed == SPEED_100 ?
1206 100 : 10)),
1207 (tp->link_config.active_duplex == DUPLEX_FULL ?
1208 "full" : "half"));
1209
1210 printk(KERN_INFO PFX
1211 "%s: Flow control is %s for TX and %s for RX.\n",
1212 tp->dev->name,
e18ce346 1213 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1214 "on" : "off",
e18ce346 1215 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC
1216 "on" : "off");
1217 tg3_ump_link_report(tp);
1218 }
1219}
1220
1221static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC
1230 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
1237static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1238{
1239 u16 miireg;
1240
e18ce346 1241 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1242 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1243 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1244 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1245 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC
1246 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1247 else
1248 miireg = 0;
1249
1250 return miireg;
1251}
1252
95e2869a
MC
1253static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1254{
1255 u8 cap = 0;
1256
1257 if (lcladv & ADVERTISE_1000XPAUSE) {
1258 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1260 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1261 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1262 cap = FLOW_CTRL_RX;
95e2869a
MC
1263 } else {
1264 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1265 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC
1266 }
1267 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1268 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1269 cap = FLOW_CTRL_TX;
95e2869a
MC
1270 }
1271
1272 return cap;
1273}
1274
f51f3562 1275static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1276{
b02fd9e3 1277 u8 autoneg;
f51f3562 1278 u8 flowctrl = 0;
95e2869a
MC
1279 u32 old_rx_mode = tp->rx_mode;
1280 u32 old_tx_mode = tp->tx_mode;
1281
b02fd9e3 1282 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1283 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC
1284 else
1285 autoneg = tp->link_config.autoneg;
1286
1287 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC
1288 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1289 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1290 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1291 else
bc02ff95 1292 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC
1293 } else
1294 flowctrl = tp->link_config.flowctrl;
95e2869a 1295
f51f3562 1296 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1297
e18ce346 1298 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC
1299 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1300 else
1301 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1302
f51f3562 1303 if (old_rx_mode != tp->rx_mode)
95e2869a 1304 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1305
e18ce346 1306 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC
1307 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1308 else
1309 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1310
f51f3562 1311 if (old_tx_mode != tp->tx_mode)
95e2869a 1312 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC
1313}
1314
b02fd9e3
MC
1315static void tg3_adjust_link(struct net_device *dev)
1316{
1317 u8 oldflowctrl, linkmesg = 0;
1318 u32 mac_mode, lcl_adv, rmt_adv;
1319 struct tg3 *tp = netdev_priv(dev);
298cf9be 1320 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC
1321
1322 spin_lock(&tp->lock);
1323
1324 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1325 MAC_MODE_HALF_DUPLEX);
1326
1327 oldflowctrl = tp->link_config.active_flowctrl;
1328
1329 if (phydev->link) {
1330 lcl_adv = 0;
1331 rmt_adv = 0;
1332
1333 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1334 mac_mode |= MAC_MODE_PORT_MODE_MII;
1335 else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (phydev->duplex == DUPLEX_HALF)
1339 mac_mode |= MAC_MODE_HALF_DUPLEX;
1340 else {
1341 lcl_adv = tg3_advert_flowctrl_1000T(
1342 tp->link_config.flowctrl);
1343
1344 if (phydev->pause)
1345 rmt_adv = LPA_PAUSE_CAP;
1346 if (phydev->asym_pause)
1347 rmt_adv |= LPA_PAUSE_ASYM;
1348 }
1349
1350 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1351 } else
1352 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1353
1354 if (mac_mode != tp->mac_mode) {
1355 tp->mac_mode = mac_mode;
1356 tw32_f(MAC_MODE, tp->mac_mode);
1357 udelay(40);
1358 }
1359
fcb389df
MC
1360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1361 if (phydev->speed == SPEED_10)
1362 tw32(MAC_MI_STAT,
1363 MAC_MI_STAT_10MBPS_MODE |
1364 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 else
1366 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1367 }
1368
b02fd9e3
MC
1369 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1370 tw32(MAC_TX_LENGTHS,
1371 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1372 (6 << TX_LENGTHS_IPG_SHIFT) |
1373 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1374 else
1375 tw32(MAC_TX_LENGTHS,
1376 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1377 (6 << TX_LENGTHS_IPG_SHIFT) |
1378 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1379
1380 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1381 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1382 phydev->speed != tp->link_config.active_speed ||
1383 phydev->duplex != tp->link_config.active_duplex ||
1384 oldflowctrl != tp->link_config.active_flowctrl)
1385 linkmesg = 1;
1386
1387 tp->link_config.active_speed = phydev->speed;
1388 tp->link_config.active_duplex = phydev->duplex;
1389
1390 spin_unlock(&tp->lock);
1391
1392 if (linkmesg)
1393 tg3_link_report(tp);
1394}
1395
1396static int tg3_phy_init(struct tg3 *tp)
1397{
1398 struct phy_device *phydev;
1399
1400 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1401 return 0;
1402
1403 /* Bring the PHY back to a known state. */
1404 tg3_bmcr_reset(tp);
1405
298cf9be 1406 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC
1407
1408 /* Attach the MAC to the PHY. */
fb28ad35 1409 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1410 phydev->dev_flags, phydev->interface);
b02fd9e3
MC
1411 if (IS_ERR(phydev)) {
1412 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1413 return PTR_ERR(phydev);
1414 }
1415
b02fd9e3 1416 /* Mask with MAC supported features. */
9c61d6bc
MC
1417 switch (phydev->interface) {
1418 case PHY_INTERFACE_MODE_GMII:
1419 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC
1420 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1421 phydev->supported &= (PHY_GBIT_FEATURES |
1422 SUPPORTED_Pause |
1423 SUPPORTED_Asym_Pause);
1424 break;
1425 }
1426 /* fallthru */
9c61d6bc
MC
1427 case PHY_INTERFACE_MODE_MII:
1428 phydev->supported &= (PHY_BASIC_FEATURES |
1429 SUPPORTED_Pause |
1430 SUPPORTED_Asym_Pause);
1431 break;
1432 default:
1433 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1434 return -EINVAL;
1435 }
1436
1437 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC
1438
1439 phydev->advertising = phydev->supported;
1440
b02fd9e3
MC
1441 return 0;
1442}
1443
1444static void tg3_phy_start(struct tg3 *tp)
1445{
1446 struct phy_device *phydev;
1447
1448 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1449 return;
1450
298cf9be 1451 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC
1452
1453 if (tp->link_config.phy_is_low_power) {
1454 tp->link_config.phy_is_low_power = 0;
1455 phydev->speed = tp->link_config.orig_speed;
1456 phydev->duplex = tp->link_config.orig_duplex;
1457 phydev->autoneg = tp->link_config.orig_autoneg;
1458 phydev->advertising = tp->link_config.orig_advertising;
1459 }
1460
1461 phy_start(phydev);
1462
1463 phy_start_aneg(phydev);
1464}
1465
1466static void tg3_phy_stop(struct tg3 *tp)
1467{
1468 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1469 return;
1470
298cf9be 1471 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC
1472}
1473
1474static void tg3_phy_fini(struct tg3 *tp)
1475{
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1477 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC
1478 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1479 }
1480}
1481
b2a5c19c
MC
1482static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1483{
1484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1485 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1486}
1487
7f97a4bd
MC
1488static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1489{
1490 u32 phytest;
1491
1492 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1493 u32 phy;
1494
1495 tg3_writephy(tp, MII_TG3_FET_TEST,
1496 phytest | MII_TG3_FET_SHADOW_EN);
1497 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1498 if (enable)
1499 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 else
1501 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1502 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1503 }
1504 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1505 }
1506}
1507
6833c043
MC
1508static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1509{
1510 u32 reg;
1511
7f97a4bd 1512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC
1513 return;
1514
7f97a4bd
MC
1515 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1516 tg3_phy_fet_toggle_apd(tp, enable);
1517 return;
1518 }
1519
6833c043
MC
1520 reg = MII_TG3_MISC_SHDW_WREN |
1521 MII_TG3_MISC_SHDW_SCR5_SEL |
1522 MII_TG3_MISC_SHDW_SCR5_LPED |
1523 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1524 MII_TG3_MISC_SHDW_SCR5_SDTL |
1525 MII_TG3_MISC_SHDW_SCR5_C125OE;
1526 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1527 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1528
1529 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1530
1531
1532 reg = MII_TG3_MISC_SHDW_WREN |
1533 MII_TG3_MISC_SHDW_APD_SEL |
1534 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1535 if (enable)
1536 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1537
1538 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1539}
1540
9ef8ca99
MC
1541static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1542{
1543 u32 phy;
1544
1545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1546 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1547 return;
1548
7f97a4bd 1549 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC
1550 u32 ephy;
1551
535ef6e1
MC
1552 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1553 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1554
1555 tg3_writephy(tp, MII_TG3_FET_TEST,
1556 ephy | MII_TG3_FET_SHADOW_EN);
1557 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1558 if (enable)
535ef6e1 1559 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1560 else
535ef6e1
MC
1561 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1562 tg3_writephy(tp, reg, phy);
9ef8ca99 1563 }
535ef6e1 1564 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC
1565 }
1566 } else {
1567 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1568 MII_TG3_AUXCTL_SHDWSEL_MISC;
1569 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1570 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1571 if (enable)
1572 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 else
1574 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1575 phy |= MII_TG3_AUXCTL_MISC_WREN;
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1577 }
1578 }
1579}
1580
1da177e4
LT
1581static void tg3_phy_set_wirespeed(struct tg3 *tp)
1582{
1583 u32 val;
1584
1585 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1586 return;
1587
1588 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1589 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1590 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1591 (val | (1 << 15) | (1 << 4)));
1592}
1593
b2a5c19c
MC
1594static void tg3_phy_apply_otp(struct tg3 *tp)
1595{
1596 u32 otp, phy;
1597
1598 if (!tp->phy_otp)
1599 return;
1600
1601 otp = tp->phy_otp;
1602
1603 /* Enable SM_DSP clock and tx 6dB coding. */
1604 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1605 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1606 MII_TG3_AUXCTL_ACTL_TX_6DB;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608
1609 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1610 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1611 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1612
1613 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1614 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1615 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1616
1617 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1618 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1619 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1620
1621 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1622 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1623
1624 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1625 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1626
1627 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1628 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1629 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1630
1631 /* Turn off SM_DSP clock. */
1632 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1633 MII_TG3_AUXCTL_ACTL_TX_6DB;
1634 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1635}
1636
1da177e4
LT
1637static int tg3_wait_macro_done(struct tg3 *tp)
1638{
1639 int limit = 100;
1640
1641 while (limit--) {
1642 u32 tmp32;
1643
1644 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1645 if ((tmp32 & 0x1000) == 0)
1646 break;
1647 }
1648 }
d4675b52 1649 if (limit < 0)
1da177e4
LT
1650 return -EBUSY;
1651
1652 return 0;
1653}
1654
1655static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1656{
1657 static const u32 test_pat[4][6] = {
1658 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1659 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1660 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1661 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1662 };
1663 int chan;
1664
1665 for (chan = 0; chan < 4; chan++) {
1666 int i;
1667
1668 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1669 (chan * 0x2000) | 0x0200);
1670 tg3_writephy(tp, 0x16, 0x0002);
1671
1672 for (i = 0; i < 6; i++)
1673 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1674 test_pat[chan][i]);
1675
1676 tg3_writephy(tp, 0x16, 0x0202);
1677 if (tg3_wait_macro_done(tp)) {
1678 *resetp = 1;
1679 return -EBUSY;
1680 }
1681
1682 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1683 (chan * 0x2000) | 0x0200);
1684 tg3_writephy(tp, 0x16, 0x0082);
1685 if (tg3_wait_macro_done(tp)) {
1686 *resetp = 1;
1687 return -EBUSY;
1688 }
1689
1690 tg3_writephy(tp, 0x16, 0x0802);
1691 if (tg3_wait_macro_done(tp)) {
1692 *resetp = 1;
1693 return -EBUSY;
1694 }
1695
1696 for (i = 0; i < 6; i += 2) {
1697 u32 low, high;
1698
1699 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1700 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1701 tg3_wait_macro_done(tp)) {
1702 *resetp = 1;
1703 return -EBUSY;
1704 }
1705 low &= 0x7fff;
1706 high &= 0x000f;
1707 if (low != test_pat[chan][i] ||
1708 high != test_pat[chan][i+1]) {
1709 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1710 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1712
1713 return -EBUSY;
1714 }
1715 }
1716 }
1717
1718 return 0;
1719}
1720
1721static int tg3_phy_reset_chanpat(struct tg3 *tp)
1722{
1723 int chan;
1724
1725 for (chan = 0; chan < 4; chan++) {
1726 int i;
1727
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731 for (i = 0; i < 6; i++)
1732 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp))
1735 return -EBUSY;
1736 }
1737
1738 return 0;
1739}
1740
1741static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1742{
1743 u32 reg32, phy9_orig;
1744 int retries, do_phy_reset, err;
1745
1746 retries = 10;
1747 do_phy_reset = 1;
1748 do {
1749 if (do_phy_reset) {
1750 err = tg3_bmcr_reset(tp);
1751 if (err)
1752 return err;
1753 do_phy_reset = 0;
1754 }
1755
1756 /* Disable transmitter and interrupt. */
1757 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1758 continue;
1759
1760 reg32 |= 0x3000;
1761 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1762
1763 /* Set full-duplex, 1000 mbps. */
1764 tg3_writephy(tp, MII_BMCR,
1765 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1766
1767 /* Set to master mode. */
1768 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1769 continue;
1770
1771 tg3_writephy(tp, MII_TG3_CTRL,
1772 (MII_TG3_CTRL_AS_MASTER |
1773 MII_TG3_CTRL_ENABLE_AS_MASTER));
1774
1775 /* Enable SM_DSP_CLOCK and 6dB. */
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1777
1778 /* Block the PHY control access. */
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1781
1782 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1783 if (!err)
1784 break;
1785 } while (--retries);
1786
1787 err = tg3_phy_reset_chanpat(tp);
1788 if (err)
1789 return err;
1790
1791 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1793
1794 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1795 tg3_writephy(tp, 0x16, 0x0000);
1796
1797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1799 /* Set Extended packet length bit for jumbo frames */
1800 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1801 }
1802 else {
1803 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1804 }
1805
1806 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1807
1808 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1809 reg32 &= ~0x3000;
1810 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1811 } else if (!err)
1812 err = -EBUSY;
1813
1814 return err;
1815}
1816
1817/* This will reset the tigon3 PHY if there is no valid
1818 * link unless the FORCE argument is non-zero.
1819 */
1820static int tg3_phy_reset(struct tg3 *tp)
1821{
b2a5c19c 1822 u32 cpmuctrl;
1da177e4
LT
1823 u32 phy_status;
1824 int err;
1825
60189ddf
MC
1826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1827 u32 val;
1828
1829 val = tr32(GRC_MISC_CFG);
1830 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1831 udelay(40);
1832 }
1da177e4
LT
1833 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1834 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1835 if (err != 0)
1836 return -EBUSY;
1837
c8e1e82b
MC
1838 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1839 netif_carrier_off(tp->dev);
1840 tg3_link_report(tp);
1841 }
1842
1da177e4
LT
1843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1846 err = tg3_phy_reset_5703_4_5(tp);
1847 if (err)
1848 return err;
1849 goto out;
1850 }
1851
b2a5c19c
MC
1852 cpmuctrl = 0;
1853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1854 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1855 cpmuctrl = tr32(TG3_CPMU_CTRL);
1856 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1857 tw32(TG3_CPMU_CTRL,
1858 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1859 }
1860
1da177e4
LT
1861 err = tg3_bmcr_reset(tp);
1862 if (err)
1863 return err;
1864
b2a5c19c
MC
1865 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1866 u32 phy;
1867
1868 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1869 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1870
1871 tw32(TG3_CPMU_CTRL, cpmuctrl);
1872 }
1873
bcb37f6c
MC
1874 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1875 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC
1876 u32 val;
1877
1878 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1879 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1880 CPMU_LSPD_1000MB_MACCLK_12_5) {
1881 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1882 udelay(40);
1883 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1884 }
1885 }
1886
b2a5c19c
MC
1887 tg3_phy_apply_otp(tp);
1888
6833c043
MC
1889 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1890 tg3_phy_toggle_apd(tp, true);
1891 else
1892 tg3_phy_toggle_apd(tp, false);
1893
1da177e4
LT
1894out:
1895 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1896 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1900 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902 }
1903 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1904 tg3_writephy(tp, 0x1c, 0x8d68);
1905 tg3_writephy(tp, 0x1c, 0x8d68);
1906 }
1907 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1915 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1916 }
c424cb24
MC
1917 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1918 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1919 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC
1920 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1921 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1922 tg3_writephy(tp, MII_TG3_TEST1,
1923 MII_TG3_TEST1_TRIM_EN | 0x4);
1924 } else
1925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC
1926 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1927 }
1da177e4
LT
1928 /* Set Extended packet length bit (bit 14) on all chips that */
1929 /* support jumbo frames */
1930 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1931 /* Cannot do read-modify-write on 5401 */
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1933 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT
1934 u32 phy_reg;
1935
1936 /* Set bit 14 with read-modify-write to preserve other bits */
1937 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1938 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1940 }
1941
1942 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1943 * jumbo frames transmission.
1944 */
8f666b07 1945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT
1946 u32 phy_reg;
1947
1948 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1949 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1950 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1951 }
1952
715116a1 1953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1954 /* adjust output voltage */
535ef6e1 1955 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC
1956 }
1957
9ef8ca99 1958 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT
1959 tg3_phy_set_wirespeed(tp);
1960 return 0;
1961}
1962
1963static void tg3_frob_aux_power(struct tg3 *tp)
1964{
1965 struct tg3 *tp_peer = tp;
1966
9d26e213 1967 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT
1968 return;
1969
8c2dc7e1
MC
1970 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1971 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1972 struct net_device *dev_peer;
1973
1974 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1975 /* remove_one() may have been run on the peer. */
8c2dc7e1 1976 if (!dev_peer)
bc1c7567
MC
1977 tp_peer = tp;
1978 else
1979 tp_peer = netdev_priv(dev_peer);
1da177e4
LT
1980 }
1981
1da177e4 1982 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC
1983 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1984 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1985 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT
1986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC
1988 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1989 (GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT0 |
1993 GRC_LCLCTRL_GPIO_OUTPUT1),
1994 100);
8d519ab2
MC
1995 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC
1997 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1998 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1999 GRC_LCLCTRL_GPIO_OE1 |
2000 GRC_LCLCTRL_GPIO_OE2 |
2001 GRC_LCLCTRL_GPIO_OUTPUT0 |
2002 GRC_LCLCTRL_GPIO_OUTPUT1 |
2003 tp->grc_local_ctrl;
2004 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2005
2006 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2007 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2008
2009 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2010 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT
2011 } else {
2012 u32 no_gpio2;
dc56b7d4 2013 u32 grc_local_ctrl = 0;
1da177e4
LT
2014
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017 return;
2018
dc56b7d4
MC
2019 /* Workaround to prevent overdrawing Amps. */
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2021 ASIC_REV_5714) {
2022 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC
2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 grc_local_ctrl, 100);
dc56b7d4
MC
2025 }
2026
1da177e4
LT
2027 /* On 5753 and variants, GPIO2 cannot be used. */
2028 no_gpio2 = tp->nic_sram_data_cfg &
2029 NIC_SRAM_DATA_CFG_NO_GPIO2;
2030
dc56b7d4 2031 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT
2032 GRC_LCLCTRL_GPIO_OE1 |
2033 GRC_LCLCTRL_GPIO_OE2 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 GRC_LCLCTRL_GPIO_OUTPUT2;
2036 if (no_gpio2) {
2037 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2038 GRC_LCLCTRL_GPIO_OUTPUT2);
2039 }
b401e9e2
MC
2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 grc_local_ctrl, 100);
1da177e4
LT
2042
2043 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2044
b401e9e2
MC
2045 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2046 grc_local_ctrl, 100);
1da177e4
LT
2047
2048 if (!no_gpio2) {
2049 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC
2050 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2051 grc_local_ctrl, 100);
1da177e4
LT
2052 }
2053 }
2054 } else {
2055 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2056 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2057 if (tp_peer != tp &&
2058 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2059 return;
2060
b401e9e2
MC
2061 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062 (GRC_LCLCTRL_GPIO_OE1 |
2063 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2064
b401e9e2
MC
2065 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2066 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2067
b401e9e2
MC
2068 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2069 (GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT
2071 }
2072 }
2073}
2074
e8f3f6ca
MC
2075static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2076{
2077 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2078 return 1;
2079 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2080 if (speed != SPEED_10)
2081 return 1;
2082 } else if (speed == SPEED_10)
2083 return 1;
2084
2085 return 0;
2086}
2087
1da177e4
LT
2088static int tg3_setup_phy(struct tg3 *, int);
2089
2090#define RESET_KIND_SHUTDOWN 0
2091#define RESET_KIND_INIT 1
2092#define RESET_KIND_SUSPEND 2
2093
2094static void tg3_write_sig_post_reset(struct tg3 *, int);
2095static int tg3_halt_cpu(struct tg3 *, u32);
2096
0a459aac 2097static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2098{
ce057f01
MC
2099 u32 val;
2100
5129724a
MC
2101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2103 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2104 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2105
2106 sg_dig_ctrl |=
2107 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2108 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2109 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2110 }
3f7045c1 2111 return;
5129724a 2112 }
3f7045c1 2113
60189ddf 2114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC
2115 tg3_bmcr_reset(tp);
2116 val = tr32(GRC_MISC_CFG);
2117 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2118 udelay(40);
2119 return;
0a459aac 2120 } else if (do_low_power) {
715116a1
MC
2121 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2122 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC
2123
2124 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2126 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2127 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2128 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2129 }
3f7045c1 2130
15c3b696
MC
2131 /* The PHY should not be powered down on some chips because
2132 * of bugs.
2133 */
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2137 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2138 return;
ce057f01 2139
bcb37f6c
MC
2140 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2141 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC
2142 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2143 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2144 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2145 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2146 }
2147
15c3b696
MC
2148 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2149}
2150
ffbcfed4
MC
2151/* tp->lock is held. */
2152static int tg3_nvram_lock(struct tg3 *tp)
2153{
2154 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2155 int i;
2156
2157 if (tp->nvram_lock_cnt == 0) {
2158 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2159 for (i = 0; i < 8000; i++) {
2160 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2161 break;
2162 udelay(20);
2163 }
2164 if (i == 8000) {
2165 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2166 return -ENODEV;
2167 }
2168 }
2169 tp->nvram_lock_cnt++;
2170 }
2171 return 0;
2172}
2173
2174/* tp->lock is held. */
2175static void tg3_nvram_unlock(struct tg3 *tp)
2176{
2177 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2178 if (tp->nvram_lock_cnt > 0)
2179 tp->nvram_lock_cnt--;
2180 if (tp->nvram_lock_cnt == 0)
2181 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2182 }
2183}
2184
2185/* tp->lock is held. */
2186static void tg3_enable_nvram_access(struct tg3 *tp)
2187{
2188 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2189 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2190 u32 nvaccess = tr32(NVRAM_ACCESS);
2191
2192 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2193 }
2194}
2195
2196/* tp->lock is held. */
2197static void tg3_disable_nvram_access(struct tg3 *tp)
2198{
2199 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2200 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2201 u32 nvaccess = tr32(NVRAM_ACCESS);
2202
2203 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2204 }
2205}
2206
2207static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2208 u32 offset, u32 *val)
2209{
2210 u32 tmp;
2211 int i;
2212
2213 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2214 return -EINVAL;
2215
2216 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2217 EEPROM_ADDR_DEVID_MASK |
2218 EEPROM_ADDR_READ);
2219 tw32(GRC_EEPROM_ADDR,
2220 tmp |
2221 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2222 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2223 EEPROM_ADDR_ADDR_MASK) |
2224 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2225
2226 for (i = 0; i < 1000; i++) {
2227 tmp = tr32(GRC_EEPROM_ADDR);
2228
2229 if (tmp & EEPROM_ADDR_COMPLETE)
2230 break;
2231 msleep(1);
2232 }
2233 if (!(tmp & EEPROM_ADDR_COMPLETE))
2234 return -EBUSY;
2235
62cedd11
MC
2236 tmp = tr32(GRC_EEPROM_DATA);
2237
2238 /*
2239 * The data will always be opposite the native endian
2240 * format. Perform a blind byteswap to compensate.
2241 */
2242 *val = swab32(tmp);
2243
ffbcfed4
MC
2244 return 0;
2245}
2246
2247#define NVRAM_CMD_TIMEOUT 10000
2248
2249static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2250{
2251 int i;
2252
2253 tw32(NVRAM_CMD, nvram_cmd);
2254 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2255 udelay(10);
2256 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2257 udelay(10);
2258 break;
2259 }
2260 }
2261
2262 if (i == NVRAM_CMD_TIMEOUT)
2263 return -EBUSY;
2264
2265 return 0;
2266}
2267
2268static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2269{
2270 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2271 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2272 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2274 (tp->nvram_jedecnum == JEDEC_ATMEL))
2275
2276 addr = ((addr / tp->nvram_pagesize) <<
2277 ATMEL_AT45DB0X1B_PAGE_POS) +
2278 (addr % tp->nvram_pagesize);
2279
2280 return addr;
2281}
2282
2283static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2284{
2285 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2286 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2287 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2288 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2289 (tp->nvram_jedecnum == JEDEC_ATMEL))
2290
2291 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2292 tp->nvram_pagesize) +
2293 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2294
2295 return addr;
2296}
2297
e4f34110
MC
2298/* NOTE: Data read in from NVRAM is byteswapped according to
2299 * the byteswapping settings for all other register accesses.
2300 * tg3 devices are BE devices, so on a BE machine, the data
2301 * returned will be exactly as it is seen in NVRAM. On a LE
2302 * machine, the 32-bit value will be byteswapped.
2303 */
ffbcfed4
MC
2304static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2305{
2306 int ret;
2307
2308 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2309 return tg3_nvram_read_using_eeprom(tp, offset, val);
2310
2311 offset = tg3_nvram_phys_addr(tp, offset);
2312
2313 if (offset > NVRAM_ADDR_MSK)
2314 return -EINVAL;
2315
2316 ret = tg3_nvram_lock(tp);
2317 if (ret)
2318 return ret;
2319
2320 tg3_enable_nvram_access(tp);
2321
2322 tw32(NVRAM_ADDR, offset);
2323 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2324 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2325
2326 if (ret == 0)
e4f34110 2327 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC
2328
2329 tg3_disable_nvram_access(tp);
2330
2331 tg3_nvram_unlock(tp);
2332
2333 return ret;
2334}
2335
a9dc529d
MC
2336/* Ensures NVRAM data is in bytestream format. */
2337static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC
2338{
2339 u32 v;
a9dc529d 2340 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2341 if (!res)
a9dc529d 2342 *val = cpu_to_be32(v);
ffbcfed4
MC
2343 return res;
2344}
2345
3f007891
MC
2346/* tp->lock is held. */
2347static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2348{
2349 u32 addr_high, addr_low;
2350 int i;
2351
2352 addr_high = ((tp->dev->dev_addr[0] << 8) |
2353 tp->dev->dev_addr[1]);
2354 addr_low = ((tp->dev->dev_addr[2] << 24) |
2355 (tp->dev->dev_addr[3] << 16) |
2356 (tp->dev->dev_addr[4] << 8) |
2357 (tp->dev->dev_addr[5] << 0));
2358 for (i = 0; i < 4; i++) {
2359 if (i == 1 && skip_mac_1)
2360 continue;
2361 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2362 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2363 }
2364
2365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2367 for (i = 0; i < 12; i++) {
2368 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2369 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2370 }
2371 }
2372
2373 addr_high = (tp->dev->dev_addr[0] +
2374 tp->dev->dev_addr[1] +
2375 tp->dev->dev_addr[2] +
2376 tp->dev->dev_addr[3] +
2377 tp->dev->dev_addr[4] +
2378 tp->dev->dev_addr[5]) &
2379 TX_BACKOFF_SEED_MASK;
2380 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2381}
2382
bc1c7567 2383static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT
2384{
2385 u32 misc_host_ctrl;
0a459aac 2386 bool device_should_wake, do_low_power;
1da177e4
LT
2387
2388 /* Make sure register accesses (indirect or otherwise)
2389 * will function correctly.
2390 */
2391 pci_write_config_dword(tp->pdev,
2392 TG3PCI_MISC_HOST_CTRL,
2393 tp->misc_host_ctrl);
2394
1da177e4 2395 switch (state) {
bc1c7567 2396 case PCI_D0:
12dac075
RW
2397 pci_enable_wake(tp->pdev, state, false);
2398 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2399
9d26e213
MC
2400 /* Switch out of Vaux if it is a NIC */
2401 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2402 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT
2403
2404 return 0;
2405
bc1c7567 2406 case PCI_D1:
bc1c7567 2407 case PCI_D2:
bc1c7567 2408 case PCI_D3hot:
1da177e4
LT
2409 break;
2410
2411 default:
12dac075
RW
2412 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2413 tp->dev->name, state);
1da177e4 2414 return -EINVAL;
855e1111 2415 }
5e7dfd0f
MC
2416
2417 /* Restore the CLKREQ setting. */
2418 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2419 u16 lnkctl;
2420
2421 pci_read_config_word(tp->pdev,
2422 tp->pcie_cap + PCI_EXP_LNKCTL,
2423 &lnkctl);
2424 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2425 pci_write_config_word(tp->pdev,
2426 tp->pcie_cap + PCI_EXP_LNKCTL,
2427 lnkctl);
2428 }
2429
1da177e4
LT
2430 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2431 tw32(TG3PCI_MISC_HOST_CTRL,
2432 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2433
05ac4cb7
MC
2434 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2435 device_may_wakeup(&tp->pdev->dev) &&
2436 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2437
dd477003 2438 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2439 do_low_power = false;
b02fd9e3
MC
2440 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2441 !tp->link_config.phy_is_low_power) {
2442 struct phy_device *phydev;
0a459aac 2443 u32 phyid, advertising;
b02fd9e3 2444
298cf9be 2445 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC
2446
2447 tp->link_config.phy_is_low_power = 1;
2448
2449 tp->link_config.orig_speed = phydev->speed;
2450 tp->link_config.orig_duplex = phydev->duplex;
2451 tp->link_config.orig_autoneg = phydev->autoneg;
2452 tp->link_config.orig_advertising = phydev->advertising;
2453
2454 advertising = ADVERTISED_TP |
2455 ADVERTISED_Pause |
2456 ADVERTISED_Autoneg |
2457 ADVERTISED_10baseT_Half;
2458
2459 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2460 device_should_wake) {
b02fd9e3
MC
2461 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2462 advertising |=
2463 ADVERTISED_100baseT_Half |
2464 ADVERTISED_100baseT_Full |
2465 ADVERTISED_10baseT_Full;
2466 else
2467 advertising |= ADVERTISED_10baseT_Full;
2468 }
2469
2470 phydev->advertising = advertising;
2471
2472 phy_start_aneg(phydev);
0a459aac
MC
2473
2474 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2475 if (phyid != TG3_PHY_ID_BCMAC131) {
2476 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK
2477 if (phyid == TG3_PHY_OUI_1 ||
2478 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC
2479 phyid == TG3_PHY_OUI_3)
2480 do_low_power = true;
2481 }
b02fd9e3 2482 }
dd477003 2483 } else {
2023276e 2484 do_low_power = true;
0a459aac 2485
dd477003
MC
2486 if (tp->link_config.phy_is_low_power == 0) {
2487 tp->link_config.phy_is_low_power = 1;
2488 tp->link_config.orig_speed = tp->link_config.speed;
2489 tp->link_config.orig_duplex = tp->link_config.duplex;
2490 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2491 }
1da177e4 2492
dd477003
MC
2493 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2494 tp->link_config.speed = SPEED_10;
2495 tp->link_config.duplex = DUPLEX_HALF;
2496 tp->link_config.autoneg = AUTONEG_ENABLE;
2497 tg3_setup_phy(tp, 0);
2498 }
1da177e4
LT
2499 }
2500
b5d3772c
MC
2501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2502 u32 val;
2503
2504 val = tr32(GRC_VCPU_EXT_CTRL);
2505 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2506 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC
2507 int i;
2508 u32 val;
2509
2510 for (i = 0; i < 200; i++) {
2511 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2512 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2513 break;
2514 msleep(1);
2515 }
2516 }
a85feb8c
GZ
2517 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2518 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2519 WOL_DRV_STATE_SHUTDOWN |
2520 WOL_DRV_WOL |
2521 WOL_SET_MAGIC_PKT);
6921d201 2522
05ac4cb7 2523 if (device_should_wake) {
1da177e4
LT
2524 u32 mac_mode;
2525
2526 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2527 if (do_low_power) {
dd477003
MC
2528 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2529 udelay(40);
2530 }
1da177e4 2531
3f7045c1
MC
2532 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2533 mac_mode = MAC_MODE_PORT_MODE_GMII;
2534 else
2535 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2536
e8f3f6ca
MC
2537 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2538 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2539 ASIC_REV_5700) {
2540 u32 speed = (tp->tg3_flags &
2541 TG3_FLAG_WOL_SPEED_100MB) ?
2542 SPEED_100 : SPEED_10;
2543 if (tg3_5700_link_polarity(tp, speed))
2544 mac_mode |= MAC_MODE_LINK_POLARITY;
2545 else
2546 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2547 }
1da177e4
LT
2548 } else {
2549 mac_mode = MAC_MODE_PORT_MODE_TBI;
2550 }
2551
cbf46853 2552 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT
2553 tw32(MAC_LED_CTRL, tp->led_ctrl);
2554
05ac4cb7
MC
2555 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2556 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2557 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2558 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2559 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2560 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2561
3bda1258
MC
2562 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2563 mac_mode |= tp->mac_mode &
2564 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2565 if (mac_mode & MAC_MODE_APE_TX_EN)
2566 mac_mode |= MAC_MODE_TDE_ENABLE;
2567 }
2568
1da177e4
LT
2569 tw32_f(MAC_MODE, mac_mode);
2570 udelay(100);
2571
2572 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2573 udelay(10);
2574 }
2575
2576 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2577 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2579 u32 base_val;
2580
2581 base_val = tp->pci_clock_ctrl;
2582 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2583 CLOCK_CTRL_TXCLK_DISABLE);
2584
b401e9e2
MC
2585 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2586 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2587 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2588 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2590 /* do nothing */
85e94ced 2591 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT
2592 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2593 u32 newbits1, newbits2;
2594
2595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2597 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2598 CLOCK_CTRL_TXCLK_DISABLE |
2599 CLOCK_CTRL_ALTCLK);
2600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2601 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2602 newbits1 = CLOCK_CTRL_625_CORE;
2603 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2604 } else {
2605 newbits1 = CLOCK_CTRL_ALTCLK;
2606 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2607 }
2608
b401e9e2
MC
2609 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2610 40);
1da177e4 2611
b401e9e2
MC
2612 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2613 40);
1da177e4
LT
2614
2615 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2616 u32 newbits3;
2617
2618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2620 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2621 CLOCK_CTRL_TXCLK_DISABLE |
2622 CLOCK_CTRL_44MHZ_CORE);
2623 } else {
2624 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2625 }
2626
b401e9e2
MC
2627 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2628 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT
2629 }
2630 }
2631
05ac4cb7 2632 if (!(device_should_wake) &&
22435849 2633 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2634 tg3_power_down_phy(tp, do_low_power);
6921d201 2635
1da177e4
LT
2636 tg3_frob_aux_power(tp);
2637
2638 /* Workaround for unstable PLL clock */
2639 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2640 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2641 u32 val = tr32(0x7d00);
2642
2643 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2644 tw32(0x7d00, val);
6921d201 2645 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC
2646 int err;
2647
2648 err = tg3_nvram_lock(tp);
1da177e4 2649 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC
2650 if (!err)
2651 tg3_nvram_unlock(tp);
6921d201 2652 }
1da177e4
LT
2653 }
2654
bbadf503
MC
2655 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2656
05ac4cb7 2657 if (device_should_wake)
12dac075
RW
2658 pci_enable_wake(tp->pdev, state, true);
2659
1da177e4 2660 /* Finally, set the new power state. */
12dac075 2661 pci_set_power_state(tp->pdev, state);
1da177e4 2662
1da177e4
LT
2663 return 0;
2664}
2665
1da177e4
LT
2666static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2667{
2668 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2669 case MII_TG3_AUX_STAT_10HALF:
2670 *speed = SPEED_10;
2671 *duplex = DUPLEX_HALF;
2672 break;
2673
2674 case MII_TG3_AUX_STAT_10FULL:
2675 *speed = SPEED_10;
2676 *duplex = DUPLEX_FULL;
2677 break;
2678
2679 case MII_TG3_AUX_STAT_100HALF:
2680 *speed = SPEED_100;
2681 *duplex = DUPLEX_HALF;
2682 break;
2683
2684 case MII_TG3_AUX_STAT_100FULL:
2685 *speed = SPEED_100;
2686 *duplex = DUPLEX_FULL;
2687 break;
2688
2689 case MII_TG3_AUX_STAT_1000HALF:
2690 *speed = SPEED_1000;
2691 *duplex = DUPLEX_HALF;
2692 break;
2693
2694 case MII_TG3_AUX_STAT_1000FULL:
2695 *speed = SPEED_1000;
2696 *duplex = DUPLEX_FULL;
2697 break;
2698
2699 default:
7f97a4bd 2700 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC
2701 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2702 SPEED_10;
2703 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2704 DUPLEX_HALF;
2705 break;
2706 }
1da177e4
LT
2707 *speed = SPEED_INVALID;
2708 *duplex = DUPLEX_INVALID;
2709 break;
855e1111 2710 }
1da177e4
LT
2711}
2712
2713static void tg3_phy_copper_begin(struct tg3 *tp)
2714{
2715 u32 new_adv;
2716 int i;
2717
2718 if (tp->link_config.phy_is_low_power) {
2719 /* Entering low power mode. Disable gigabit and
2720 * 100baseT advertisements.
2721 */
2722 tg3_writephy(tp, MII_TG3_CTRL, 0);
2723
2724 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2725 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2726 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2727 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2728
2729 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2730 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT
2731 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2732 tp->link_config.advertising &=
2733 ~(ADVERTISED_1000baseT_Half |
2734 ADVERTISED_1000baseT_Full);
2735
ba4d07a8 2736 new_adv = ADVERTISE_CSMA;
1da177e4
LT
2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2738 new_adv |= ADVERTISE_10HALF;
2739 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2740 new_adv |= ADVERTISE_10FULL;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2742 new_adv |= ADVERTISE_100HALF;
2743 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2744 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC
2745
2746 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2747
1da177e4
LT
2748 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2749
2750 if (tp->link_config.advertising &
2751 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2752 new_adv = 0;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2755 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2756 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2757 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2758 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2760 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2761 MII_TG3_CTRL_ENABLE_AS_MASTER);
2762 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2763 } else {
2764 tg3_writephy(tp, MII_TG3_CTRL, 0);
2765 }
2766 } else {
ba4d07a8
MC
2767 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2768 new_adv |= ADVERTISE_CSMA;
2769
1da177e4
LT
2770 /* Asking for a specific link mode. */
2771 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT
2772 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2773
2774 if (tp->link_config.duplex == DUPLEX_FULL)
2775 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2776 else
2777 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2778 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2780 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2781 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2782 } else {
1da177e4
LT
2783 if (tp->link_config.speed == SPEED_100) {
2784 if (tp->link_config.duplex == DUPLEX_FULL)
2785 new_adv |= ADVERTISE_100FULL;
2786 else
2787 new_adv |= ADVERTISE_100HALF;
2788 } else {
2789 if (tp->link_config.duplex == DUPLEX_FULL)
2790 new_adv |= ADVERTISE_10FULL;
2791 else
2792 new_adv |= ADVERTISE_10HALF;
2793 }
2794 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC
2795
2796 new_adv = 0;
1da177e4 2797 }
ba4d07a8
MC
2798
2799 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT
2800 }
2801
2802 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2803 tp->link_config.speed != SPEED_INVALID) {
2804 u32 bmcr, orig_bmcr;
2805
2806 tp->link_config.active_speed = tp->link_config.speed;
2807 tp->link_config.active_duplex = tp->link_config.duplex;
2808
2809 bmcr = 0;
2810 switch (tp->link_config.speed) {
2811 default:
2812 case SPEED_10:
2813 break;
2814
2815 case SPEED_100:
2816 bmcr |= BMCR_SPEED100;
2817 break;
2818
2819 case SPEED_1000:
2820 bmcr |= TG3_BMCR_SPEED1000;
2821 break;
855e1111 2822 }
1da177e4
LT
2823
2824 if (tp->link_config.duplex == DUPLEX_FULL)
2825 bmcr |= BMCR_FULLDPLX;
2826
2827 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2828 (bmcr != orig_bmcr)) {
2829 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2830 for (i = 0; i < 1500; i++) {
2831 u32 tmp;
2832
2833 udelay(10);
2834 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2835 tg3_readphy(tp, MII_BMSR, &tmp))
2836 continue;
2837 if (!(tmp & BMSR_LSTATUS)) {
2838 udelay(40);
2839 break;
2840 }
2841 }
2842 tg3_writephy(tp, MII_BMCR, bmcr);
2843 udelay(40);
2844 }
2845 } else {
2846 tg3_writephy(tp, MII_BMCR,
2847 BMCR_ANENABLE | BMCR_ANRESTART);
2848 }
2849}
2850
2851static int tg3_init_5401phy_dsp(struct tg3 *tp)
2852{
2853 int err;
2854
2855 /* Turn off tap power management. */
2856 /* Set Extended packet length bit */
2857 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2858
2859 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2860 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2861
2862 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2863 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2864
2865 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2866 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2867
2868 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2869 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2870
2871 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2872 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2873
2874 udelay(40);
2875
2876 return err;
2877}
2878
3600d918 2879static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2880{
3600d918
MC
2881 u32 adv_reg, all_mask = 0;
2882
2883 if (mask & ADVERTISED_10baseT_Half)
2884 all_mask |= ADVERTISE_10HALF;
2885 if (mask & ADVERTISED_10baseT_Full)
2886 all_mask |= ADVERTISE_10FULL;
2887 if (mask & ADVERTISED_100baseT_Half)
2888 all_mask |= ADVERTISE_100HALF;
2889 if (mask & ADVERTISED_100baseT_Full)
2890 all_mask |= ADVERTISE_100FULL;
1da177e4
LT
2891
2892 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2893 return 0;
2894
1da177e4
LT
2895 if ((adv_reg & all_mask) != all_mask)
2896 return 0;
2897 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2898 u32 tg3_ctrl;
2899
3600d918
MC
2900 all_mask = 0;
2901 if (mask & ADVERTISED_1000baseT_Half)
2902 all_mask |= ADVERTISE_1000HALF;
2903 if (mask & ADVERTISED_1000baseT_Full)
2904 all_mask |= ADVERTISE_1000FULL;
2905
1da177e4
LT
2906 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2907 return 0;
2908
1da177e4
LT
2909 if ((tg3_ctrl & all_mask) != all_mask)
2910 return 0;
2911 }
2912 return 1;
2913}
2914
ef167e27
MC
2915static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2916{
2917 u32 curadv, reqadv;
2918
2919 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2920 return 1;
2921
2922 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2923 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2924
2925 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2926 if (curadv != reqadv)
2927 return 0;
2928
2929 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2930 tg3_readphy(tp, MII_LPA, rmtadv);
2931 } else {
2932 /* Reprogram the advertisement register, even if it
2933 * does not affect the current link. If the link
2934 * gets renegotiated in the future, we can save an
2935 * additional renegotiation cycle by advertising
2936 * it correctly in the first place.
2937 */
2938 if (curadv != reqadv) {
2939 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2940 ADVERTISE_PAUSE_ASYM);
2941 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2942 }
2943 }
2944
2945 return 1;
2946}
2947
1da177e4
LT
2948static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2949{
2950 int current_link_up;
2951 u32 bmsr, dummy;
ef167e27 2952 u32 lcl_adv, rmt_adv;
1da177e4
LT
2953 u16 current_speed;
2954 u8 current_duplex;
2955 int i, err;
2956
2957 tw32(MAC_EVENT, 0);
2958
2959 tw32_f(MAC_STATUS,
2960 (MAC_STATUS_SYNC_CHANGED |
2961 MAC_STATUS_CFG_CHANGED |
2962 MAC_STATUS_MI_COMPLETION |
2963 MAC_STATUS_LNKSTATE_CHANGED));
2964 udelay(40);
2965
8ef21428
MC
2966 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2967 tw32_f(MAC_MI_MODE,
2968 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2969 udelay(80);
2970 }
1da177e4
LT
2971
2972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2973
2974 /* Some third-party PHYs need to be reset on link going
2975 * down.
2976 */
2977 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2980 netif_carrier_ok(tp->dev)) {
2981 tg3_readphy(tp, MII_BMSR, &bmsr);
2982 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2983 !(bmsr & BMSR_LSTATUS))
2984 force_reset = 1;
2985 }
2986 if (force_reset)
2987 tg3_phy_reset(tp);
2988
2989 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2990 tg3_readphy(tp, MII_BMSR, &bmsr);
2991 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2992 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2993 bmsr = 0;
2994
2995 if (!(bmsr & BMSR_LSTATUS)) {
2996 err = tg3_init_5401phy_dsp(tp);
2997 if (err)
2998 return err;
2999
3000 tg3_readphy(tp, MII_BMSR, &bmsr);
3001 for (i = 0; i < 1000; i++) {
3002 udelay(10);
3003 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3004 (bmsr & BMSR_LSTATUS)) {
3005 udelay(40);
3006 break;
3007 }
3008 }
3009
3010 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3011 !(bmsr & BMSR_LSTATUS) &&
3012 tp->link_config.active_speed == SPEED_1000) {
3013 err = tg3_phy_reset(tp);
3014 if (!err)
3015 err = tg3_init_5401phy_dsp(tp);
3016 if (err)
3017 return err;
3018 }
3019 }
3020 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3021 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3022 /* 5701 {A0,B0} CRC bug workaround */
3023 tg3_writephy(tp, 0x15, 0x0a75);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 tg3_writephy(tp, 0x1c, 0x8d68);
3026 tg3_writephy(tp, 0x1c, 0x8c68);
3027 }
3028
3029 /* Clear pending interrupts... */
3030 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3031 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3032
3033 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3034 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3035 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT
3036 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3037
3038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3040 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3041 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3042 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3043 else
3044 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3045 }
3046
3047 current_link_up = 0;
3048 current_speed = SPEED_INVALID;
3049 current_duplex = DUPLEX_INVALID;
3050
3051 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3052 u32 val;
3053
3054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3055 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3056 if (!(val & (1 << 10))) {
3057 val |= (1 << 10);
3058 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3059 goto relink;
3060 }
3061 }
3062
3063 bmsr = 0;
3064 for (i = 0; i < 100; i++) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS))
3068 break;
3069 udelay(40);
3070 }
3071
3072 if (bmsr & BMSR_LSTATUS) {
3073 u32 aux_stat, bmcr;
3074
3075 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3076 for (i = 0; i < 2000; i++) {
3077 udelay(10);
3078 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3079 aux_stat)
3080 break;
3081 }
3082
3083 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3084 &current_speed,
3085 &current_duplex);
3086
3087 bmcr = 0;
3088 for (i = 0; i < 200; i++) {
3089 tg3_readphy(tp, MII_BMCR, &bmcr);
3090 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3091 continue;
3092 if (bmcr && bmcr != 0x7fff)
3093 break;
3094 udelay(10);
3095 }
3096
ef167e27
MC
3097 lcl_adv = 0;
3098 rmt_adv = 0;
1da177e4 3099
ef167e27
MC
3100 tp->link_config.active_speed = current_speed;
3101 tp->link_config.active_duplex = current_duplex;
3102
3103 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3104 if ((bmcr & BMCR_ANENABLE) &&
3105 tg3_copper_is_advertising_all(tp,
3106 tp->link_config.advertising)) {
3107 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3108 &rmt_adv))
3109 current_link_up = 1;
1da177e4
LT
3110 }
3111 } else {
3112 if (!(bmcr & BMCR_ANENABLE) &&
3113 tp->link_config.speed == current_speed &&
ef167e27
MC
3114 tp->link_config.duplex == current_duplex &&
3115 tp->link_config.flowctrl ==
3116 tp->link_config.active_flowctrl) {
1da177e4 3117 current_link_up = 1;
1da177e4
LT
3118 }
3119 }
3120
ef167e27
MC
3121 if (current_link_up == 1 &&
3122 tp->link_config.active_duplex == DUPLEX_FULL)
3123 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT
3124 }
3125
1da177e4 3126relink:
6921d201 3127 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT
3128 u32 tmp;
3129
3130 tg3_phy_copper_begin(tp);
3131
3132 tg3_readphy(tp, MII_BMSR, &tmp);
3133 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3134 (tmp & BMSR_LSTATUS))
3135 current_link_up = 1;
3136 }
3137
3138 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3139 if (current_link_up == 1) {
3140 if (tp->link_config.active_speed == SPEED_100 ||
3141 tp->link_config.active_speed == SPEED_10)
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3143 else
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC
3145 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3147 else
1da177e4
LT
3148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3149
3150 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3151 if (tp->link_config.active_duplex == DUPLEX_HALF)
3152 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3153
1da177e4 3154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC
3155 if (current_link_up == 1 &&
3156 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3157 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC
3158 else
3159 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT
3160 }
3161
3162 /* ??? Without this setting Netgear GA302T PHY does not
3163 * ??? send/receive packets...
3164 */
3165 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3166 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3167 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3168 tw32_f(MAC_MI_MODE, tp->mi_mode);
3169 udelay(80);
3170 }
3171
3172 tw32_f(MAC_MODE, tp->mac_mode);
3173 udelay(40);
3174
3175 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3176 /* Polled via timer. */
3177 tw32_f(MAC_EVENT, 0);
3178 } else {
3179 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3180 }
3181 udelay(40);
3182
3183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3184 current_link_up == 1 &&
3185 tp->link_config.active_speed == SPEED_1000 &&
3186 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3187 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3188 udelay(120);
3189 tw32_f(MAC_STATUS,
3190 (MAC_STATUS_SYNC_CHANGED |
3191 MAC_STATUS_CFG_CHANGED));
3192 udelay(40);
3193 tg3_write_mem(tp,
3194 NIC_SRAM_FIRMWARE_MBOX,
3195 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3196 }
3197
5e7dfd0f
MC
3198 /* Prevent send BD corruption. */
3199 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3200 u16 oldlnkctl, newlnkctl;
3201
3202 pci_read_config_word(tp->pdev,
3203 tp->pcie_cap + PCI_EXP_LNKCTL,
3204 &oldlnkctl);
3205 if (tp->link_config.active_speed == SPEED_100 ||
3206 tp->link_config.active_speed == SPEED_10)
3207 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3208 else
3209 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3210 if (newlnkctl != oldlnkctl)
3211 pci_write_config_word(tp->pdev,
3212 tp->pcie_cap + PCI_EXP_LNKCTL,
3213 newlnkctl);
255ca311
MC
3214 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3215 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3216 if (tp->link_config.active_speed == SPEED_100 ||
3217 tp->link_config.active_speed == SPEED_10)
3218 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 else
3220 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3221 if (newreg != oldreg)
3222 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC
3223 }
3224
1da177e4
LT
3225 if (current_link_up != netif_carrier_ok(tp->dev)) {
3226 if (current_link_up)
3227 netif_carrier_on(tp->dev);
3228 else
3229 netif_carrier_off(tp->dev);
3230 tg3_link_report(tp);
3231 }
3232
3233 return 0;
3234}
3235
3236struct tg3_fiber_aneginfo {
3237 int state;
3238#define ANEG_STATE_UNKNOWN 0
3239#define ANEG_STATE_AN_ENABLE 1
3240#define ANEG_STATE_RESTART_INIT 2
3241#define ANEG_STATE_RESTART 3
3242#define ANEG_STATE_DISABLE_LINK_OK 4
3243#define ANEG_STATE_ABILITY_DETECT_INIT 5
3244#define ANEG_STATE_ABILITY_DETECT 6
3245#define ANEG_STATE_ACK_DETECT_INIT 7
3246#define ANEG_STATE_ACK_DETECT 8
3247#define ANEG_STATE_COMPLETE_ACK_INIT 9
3248#define ANEG_STATE_COMPLETE_ACK 10
3249#define ANEG_STATE_IDLE_DETECT_INIT 11
3250#define ANEG_STATE_IDLE_DETECT 12
3251#define ANEG_STATE_LINK_OK 13
3252#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3253#define ANEG_STATE_NEXT_PAGE_WAIT 15
3254
3255 u32 flags;
3256#define MR_AN_ENABLE 0x00000001
3257#define MR_RESTART_AN 0x00000002
3258#define MR_AN_COMPLETE 0x00000004
3259#define MR_PAGE_RX 0x00000008
3260#define MR_NP_LOADED 0x00000010
3261#define MR_TOGGLE_TX 0x00000020
3262#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3263#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3264#define MR_LP_ADV_SYM_PAUSE 0x00000100
3265#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3266#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3267#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3268#define MR_LP_ADV_NEXT_PAGE 0x00001000
3269#define MR_TOGGLE_RX 0x00002000
3270#define MR_NP_RX 0x00004000
3271
3272#define MR_LINK_OK 0x80000000
3273
3274 unsigned long link_time, cur_time;
3275
3276 u32 ability_match_cfg;
3277 int ability_match_count;
3278
3279 char ability_match, idle_match, ack_match;
3280
3281 u32 txconfig, rxconfig;
3282#define ANEG_CFG_NP 0x00000080
3283#define ANEG_CFG_ACK 0x00000040
3284#define ANEG_CFG_RF2 0x00000020
3285#define ANEG_CFG_RF1 0x00000010
3286#define ANEG_CFG_PS2 0x00000001
3287#define ANEG_CFG_PS1 0x00008000
3288#define ANEG_CFG_HD 0x00004000
3289#define ANEG_CFG_FD 0x00002000
3290#define ANEG_CFG_INVAL 0x00001f06
3291
3292};
3293#define ANEG_OK 0
3294#define ANEG_DONE 1
3295#define ANEG_TIMER_ENAB 2
3296#define ANEG_FAILED -1
3297
3298#define ANEG_STATE_SETTLE_TIME 10000
3299
3300static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3301 struct tg3_fiber_aneginfo *ap)
3302{
5be73b47 3303 u16 flowctrl;
1da177e4
LT
3304 unsigned long delta;
3305 u32 rx_cfg_reg;
3306 int ret;
3307
3308 if (ap->state == ANEG_STATE_UNKNOWN) {
3309 ap->rxconfig = 0;
3310 ap->link_time = 0;
3311 ap->cur_time = 0;
3312 ap->ability_match_cfg = 0;
3313 ap->ability_match_count = 0;
3314 ap->ability_match = 0;
3315 ap->idle_match = 0;
3316 ap->ack_match = 0;
3317 }
3318 ap->cur_time++;
3319
3320 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3321 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3322
3323 if (rx_cfg_reg != ap->ability_match_cfg) {
3324 ap->ability_match_cfg = rx_cfg_reg;
3325 ap->ability_match = 0;
3326 ap->ability_match_count = 0;
3327 } else {
3328 if (++ap->ability_match_count > 1) {
3329 ap->ability_match = 1;
3330 ap->ability_match_cfg = rx_cfg_reg;
3331 }
3332 }
3333 if (rx_cfg_reg & ANEG_CFG_ACK)
3334 ap->ack_match = 1;
3335 else
3336 ap->ack_match = 0;
3337
3338 ap->idle_match = 0;
3339 } else {
3340 ap->idle_match = 1;
3341 ap->ability_match_cfg = 0;
3342 ap->ability_match_count = 0;
3343 ap->ability_match = 0;
3344 ap->ack_match = 0;
3345
3346 rx_cfg_reg = 0;
3347 }
3348
3349 ap->rxconfig = rx_cfg_reg;
3350 ret = ANEG_OK;
3351
3352 switch(ap->state) {
3353 case ANEG_STATE_UNKNOWN:
3354 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3355 ap->state = ANEG_STATE_AN_ENABLE;
3356
3357 /* fallthru */
3358 case ANEG_STATE_AN_ENABLE:
3359 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3360 if (ap->flags & MR_AN_ENABLE) {
3361 ap->link_time = 0;
3362 ap->cur_time = 0;
3363 ap->ability_match_cfg = 0;
3364 ap->ability_match_count = 0;
3365 ap->ability_match = 0;
3366 ap->idle_match = 0;
3367 ap->ack_match = 0;
3368
3369 ap->state = ANEG_STATE_RESTART_INIT;
3370 } else {
3371 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3372 }
3373 break;
3374
3375 case ANEG_STATE_RESTART_INIT:
3376 ap->link_time = ap->cur_time;
3377 ap->flags &= ~(MR_NP_LOADED);
3378 ap->txconfig = 0;
3379 tw32(MAC_TX_AUTO_NEG, 0);
3380 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3381 tw32_f(MAC_MODE, tp->mac_mode);
3382 udelay(40);
3383
3384 ret = ANEG_TIMER_ENAB;
3385 ap->state = ANEG_STATE_RESTART;
3386
3387 /* fallthru */
3388 case ANEG_STATE_RESTART:
3389 delta = ap->cur_time - ap->link_time;
3390 if (delta > ANEG_STATE_SETTLE_TIME) {
3391 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3392 } else {
3393 ret = ANEG_TIMER_ENAB;
3394 }
3395 break;
3396
3397 case ANEG_STATE_DISABLE_LINK_OK:
3398 ret = ANEG_DONE;
3399 break;
3400
3401 case ANEG_STATE_ABILITY_DETECT_INIT:
3402 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC
3403 ap->txconfig = ANEG_CFG_FD;
3404 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3405 if (flowctrl & ADVERTISE_1000XPAUSE)
3406 ap->txconfig |= ANEG_CFG_PS1;
3407 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3408 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT
3409 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3410 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3411 tw32_f(MAC_MODE, tp->mac_mode);
3412 udelay(40);
3413
3414 ap->state = ANEG_STATE_ABILITY_DETECT;
3415 break;
3416
3417 case ANEG_STATE_ABILITY_DETECT:
3418 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3419 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3420 }
3421 break;
3422
3423 case ANEG_STATE_ACK_DETECT_INIT:
3424 ap->txconfig |= ANEG_CFG_ACK;
3425 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3426 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3427 tw32_f(MAC_MODE, tp->mac_mode);
3428 udelay(40);
3429
3430 ap->state = ANEG_STATE_ACK_DETECT;
3431
3432 /* fallthru */
3433 case ANEG_STATE_ACK_DETECT:
3434 if (ap->ack_match != 0) {
3435 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3436 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3437 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3438 } else {
3439 ap->state = ANEG_STATE_AN_ENABLE;
3440 }
3441 } else if (ap->ability_match != 0 &&
3442 ap->rxconfig == 0) {
3443 ap->state = ANEG_STATE_AN_ENABLE;
3444 }
3445 break;
3446
3447 case ANEG_STATE_COMPLETE_ACK_INIT:
3448 if (ap->rxconfig & ANEG_CFG_INVAL) {
3449 ret = ANEG_FAILED;
3450 break;
3451 }
3452 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3453 MR_LP_ADV_HALF_DUPLEX |
3454 MR_LP_ADV_SYM_PAUSE |
3455 MR_LP_ADV_ASYM_PAUSE |
3456 MR_LP_ADV_REMOTE_FAULT1 |
3457 MR_LP_ADV_REMOTE_FAULT2 |
3458 MR_LP_ADV_NEXT_PAGE |
3459 MR_TOGGLE_RX |
3460 MR_NP_RX);
3461 if (ap->rxconfig & ANEG_CFG_FD)
3462 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_HD)
3464 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3465 if (ap->rxconfig & ANEG_CFG_PS1)
3466 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_PS2)
3468 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3469 if (ap->rxconfig & ANEG_CFG_RF1)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3471 if (ap->rxconfig & ANEG_CFG_RF2)
3472 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3473 if (ap->rxconfig & ANEG_CFG_NP)
3474 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3475
3476 ap->link_time = ap->cur_time;
3477
3478 ap->flags ^= (MR_TOGGLE_TX);
3479 if (ap->rxconfig & 0x0008)
3480 ap->flags |= MR_TOGGLE_RX;
3481 if (ap->rxconfig & ANEG_CFG_NP)
3482 ap->flags |= MR_NP_RX;
3483 ap->flags |= MR_PAGE_RX;
3484
3485 ap->state = ANEG_STATE_COMPLETE_ACK;
3486 ret = ANEG_TIMER_ENAB;
3487 break;
3488
3489 case ANEG_STATE_COMPLETE_ACK:
3490 if (ap->ability_match != 0 &&
3491 ap->rxconfig == 0) {
3492 ap->state = ANEG_STATE_AN_ENABLE;
3493 break;
3494 }
3495 delta = ap->cur_time - ap->link_time;
3496 if (delta > ANEG_STATE_SETTLE_TIME) {
3497 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3498 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3499 } else {
3500 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3501 !(ap->flags & MR_NP_RX)) {
3502 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3503 } else {
3504 ret = ANEG_FAILED;
3505 }
3506 }
3507 }
3508 break;
3509
3510 case ANEG_STATE_IDLE_DETECT_INIT:
3511 ap->link_time = ap->cur_time;
3512 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3513 tw32_f(MAC_MODE, tp->mac_mode);
3514 udelay(40);
3515
3516 ap->state = ANEG_STATE_IDLE_DETECT;
3517 ret = ANEG_TIMER_ENAB;
3518 break;
3519
3520 case ANEG_STATE_IDLE_DETECT:
3521 if (ap->ability_match != 0 &&
3522 ap->rxconfig == 0) {
3523 ap->state = ANEG_STATE_AN_ENABLE;
3524 break;
3525 }
3526 delta = ap->cur_time - ap->link_time;
3527 if (delta > ANEG_STATE_SETTLE_TIME) {
3528 /* XXX another gem from the Broadcom driver :( */
3529 ap->state = ANEG_STATE_LINK_OK;
3530 }
3531 break;
3532
3533 case ANEG_STATE_LINK_OK:
3534 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3535 ret = ANEG_DONE;
3536 break;
3537
3538 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3539 /* ??? unimplemented */
3540 break;
3541
3542 case ANEG_STATE_NEXT_PAGE_WAIT:
3543 /* ??? unimplemented */
3544 break;
3545
3546 default:
3547 ret = ANEG_FAILED;
3548 break;
855e1111 3549 }
1da177e4
LT
3550
3551 return ret;
3552}
3553
5be73b47 3554static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT
3555{
3556 int res = 0;
3557 struct tg3_fiber_aneginfo aninfo;
3558 int status = ANEG_FAILED;
3559 unsigned int tick;
3560 u32 tmp;
3561
3562 tw32_f(MAC_TX_AUTO_NEG, 0);
3563
3564 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3565 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3566 udelay(40);
3567
3568 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3569 udelay(40);
3570
3571 memset(&aninfo, 0, sizeof(aninfo));
3572 aninfo.flags |= MR_AN_ENABLE;
3573 aninfo.state = ANEG_STATE_UNKNOWN;
3574 aninfo.cur_time = 0;
3575 tick = 0;
3576 while (++tick < 195000) {
3577 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3578 if (status == ANEG_DONE || status == ANEG_FAILED)
3579 break;
3580
3581 udelay(1);
3582 }
3583
3584 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3585 tw32_f(MAC_MODE, tp->mac_mode);
3586 udelay(40);
3587
5be73b47
MC
3588 *txflags = aninfo.txconfig;
3589 *rxflags = aninfo.flags;
1da177e4
LT
3590
3591 if (status == ANEG_DONE &&
3592 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3593 MR_LP_ADV_FULL_DUPLEX)))
3594 res = 1;
3595
3596 return res;
3597}
3598
3599static void tg3_init_bcm8002(struct tg3 *tp)
3600{
3601 u32 mac_status = tr32(MAC_STATUS);
3602 int i;
3603
3604 /* Reset when initting first time or we have a link. */
3605 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3606 !(mac_status & MAC_STATUS_PCS_SYNCED))
3607 return;
3608
3609 /* Set PLL lock range. */
3610 tg3_writephy(tp, 0x16, 0x8007);
3611
3612 /* SW reset */
3613 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3614
3615 /* Wait for reset to complete. */
3616 /* XXX schedule_timeout() ... */
3617 for (i = 0; i < 500; i++)
3618 udelay(10);
3619
3620 /* Config mode; select PMA/Ch 1 regs. */
3621 tg3_writephy(tp, 0x10, 0x8411);
3622
3623 /* Enable auto-lock and comdet, select txclk for tx. */
3624 tg3_writephy(tp, 0x11, 0x0a10);
3625
3626 tg3_writephy(tp, 0x18, 0x00a0);
3627 tg3_writephy(tp, 0x16, 0x41ff);
3628
3629 /* Assert and deassert POR. */
3630 tg3_writephy(tp, 0x13, 0x0400);
3631 udelay(40);
3632 tg3_writephy(tp, 0x13, 0x0000);
3633
3634 tg3_writephy(tp, 0x11, 0x0a50);
3635 udelay(40);
3636 tg3_writephy(tp, 0x11, 0x0a10);
3637
3638 /* Wait for signal to stabilize */
3639 /* XXX schedule_timeout() ... */
3640 for (i = 0; i < 15000; i++)
3641 udelay(10);
3642
3643 /* Deselect the channel register so we can read the PHYID
3644 * later.
3645 */
3646 tg3_writephy(tp, 0x10, 0x8011);
3647}
3648
3649static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3650{
82cd3d11 3651 u16 flowctrl;
1da177e4
LT
3652 u32 sg_dig_ctrl, sg_dig_status;
3653 u32 serdes_cfg, expected_sg_dig_ctrl;
3654 int workaround, port_a;
3655 int current_link_up;
3656
3657 serdes_cfg = 0;
3658 expected_sg_dig_ctrl = 0;
3659 workaround = 0;
3660 port_a = 1;
3661 current_link_up = 0;
3662
3663 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3664 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3665 workaround = 1;
3666 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3667 port_a = 0;
3668
3669 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3670 /* preserve bits 20-23 for voltage regulator */
3671 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3672 }
3673
3674 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3675
3676 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3677 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT
3678 if (workaround) {
3679 u32 val = serdes_cfg;
3680
3681 if (port_a)
3682 val |= 0xc010000;
3683 else
3684 val |= 0x4010000;
3685 tw32_f(MAC_SERDES_CFG, val);
3686 }
c98f6e3b
MC
3687
3688 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT
3689 }
3690 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3691 tg3_setup_flow_control(tp, 0, 0);
3692 current_link_up = 1;
3693 }
3694 goto out;
3695 }
3696
3697 /* Want auto-negotiation. */
c98f6e3b 3698 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3699
82cd3d11
MC
3700 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3701 if (flowctrl & ADVERTISE_1000XPAUSE)
3702 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3703 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3704 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT
3705
3706 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC
3707 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3708 tp->serdes_counter &&
3709 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3710 MAC_STATUS_RCVD_CFG)) ==
3711 MAC_STATUS_PCS_SYNCED)) {
3712 tp->serdes_counter--;
3713 current_link_up = 1;
3714 goto out;
3715 }
3716restart_autoneg:
1da177e4
LT
3717 if (workaround)
3718 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT
3720 udelay(5);
3721 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3722
3d3ebe74
MC
3723 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3724 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT
3725 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3726 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3727 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT
3728 mac_status = tr32(MAC_STATUS);
3729
c98f6e3b 3730 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3731 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC
3732 u32 local_adv = 0, remote_adv = 0;
3733
3734 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3735 local_adv |= ADVERTISE_1000XPAUSE;
3736 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3737 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3738
c98f6e3b 3739 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3740 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3741 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3742 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT
3743
3744 tg3_setup_flow_control(tp, local_adv, remote_adv);
3745 current_link_up = 1;
3d3ebe74
MC
3746 tp->serdes_counter = 0;
3747 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3748 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC
3749 if (tp->serdes_counter)
3750 tp->serdes_counter--;
1da177e4
LT
3751 else {
3752 if (workaround) {
3753 u32 val = serdes_cfg;
3754
3755 if (port_a)
3756 val |= 0xc010000;
3757 else
3758 val |= 0x4010000;
3759
3760 tw32_f(MAC_SERDES_CFG, val);
3761 }
3762
c98f6e3b 3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT
3764 udelay(40);
3765
3766 /* Link parallel detection - link is up */
3767 /* only if we have PCS_SYNC and not */
3768 /* receiving config code words */
3769 mac_status = tr32(MAC_STATUS);
3770 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3771 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3772 tg3_setup_flow_control(tp, 0, 0);
3773 current_link_up = 1;
3d3ebe74
MC
3774 tp->tg3_flags2 |=
3775 TG3_FLG2_PARALLEL_DETECT;
3776 tp->serdes_counter =
3777 SERDES_PARALLEL_DET_TIMEOUT;
3778 } else
3779 goto restart_autoneg;
1da177e4
LT
3780 }
3781 }
3d3ebe74
MC
3782 } else {
3783 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT
3785 }
3786
3787out:
3788 return current_link_up;
3789}
3790
3791static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3792{
3793 int current_link_up = 0;
3794
5cf64b8a 3795 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3796 goto out;
1da177e4
LT
3797
3798 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3799 u32 txflags, rxflags;
1da177e4 3800 int i;
6aa20a22 3801
5be73b47
MC
3802 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3803 u32 local_adv = 0, remote_adv = 0;
1da177e4 3804
5be73b47
MC
3805 if (txflags & ANEG_CFG_PS1)
3806 local_adv |= ADVERTISE_1000XPAUSE;
3807 if (txflags & ANEG_CFG_PS2)
3808 local_adv |= ADVERTISE_1000XPSE_ASYM;
3809
3810 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE;
3812 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3813 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT
3814
3815 tg3_setup_flow_control(tp, local_adv, remote_adv);
3816
1da177e4
LT
3817 current_link_up = 1;
3818 }
3819 for (i = 0; i < 30; i++) {
3820 udelay(20);
3821 tw32_f(MAC_STATUS,
3822 (MAC_STATUS_SYNC_CHANGED |
3823 MAC_STATUS_CFG_CHANGED));
3824 udelay(40);
3825 if ((tr32(MAC_STATUS) &
3826 (MAC_STATUS_SYNC_CHANGED |
3827 MAC_STATUS_CFG_CHANGED)) == 0)
3828 break;
3829 }
3830
3831 mac_status = tr32(MAC_STATUS);
3832 if (current_link_up == 0 &&
3833 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG))
3835 current_link_up = 1;
3836 } else {
5be73b47
MC
3837 tg3_setup_flow_control(tp, 0, 0);
3838
1da177e4
LT
3839 /* Forcing 1000FD link up. */
3840 current_link_up = 1;
1da177e4
LT
3841
3842 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3843 udelay(40);
e8f3f6ca
MC
3844
3845 tw32_f(MAC_MODE, tp->mac_mode);
3846 udelay(40);
1da177e4
LT
3847 }
3848
3849out:
3850 return current_link_up;
3851}
3852
3853static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3854{
3855 u32 orig_pause_cfg;
3856 u16 orig_active_speed;
3857 u8 orig_active_duplex;
3858 u32 mac_status;
3859 int current_link_up;
3860 int i;
3861
8d018621 3862 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT
3863 orig_active_speed = tp->link_config.active_speed;
3864 orig_active_duplex = tp->link_config.active_duplex;
3865
3866 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3867 netif_carrier_ok(tp->dev) &&
3868 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3869 mac_status = tr32(MAC_STATUS);
3870 mac_status &= (MAC_STATUS_PCS_SYNCED |
3871 MAC_STATUS_SIGNAL_DET |
3872 MAC_STATUS_CFG_CHANGED |
3873 MAC_STATUS_RCVD_CFG);
3874 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3875 MAC_STATUS_SIGNAL_DET)) {
3876 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 return 0;
3879 }
3880 }
3881
3882 tw32_f(MAC_TX_AUTO_NEG, 0);
3883
3884 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3885 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3886 tw32_f(MAC_MODE, tp->mac_mode);
3887 udelay(40);
3888
3889 if (tp->phy_id == PHY_ID_BCM8002)
3890 tg3_init_bcm8002(tp);
3891
3892 /* Enable link change event even when serdes polling. */
3893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3894 udelay(40);
3895
3896 current_link_up = 0;
3897 mac_status = tr32(MAC_STATUS);
3898
3899 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3900 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3901 else
3902 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3903
898a56f8 3904 tp->napi[0].hw_status->status =
1da177e4 3905 (SD_STATUS_UPDATED |
898a56f8 3906 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT
3907
3908 for (i = 0; i < 100; i++) {
3909 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3910 MAC_STATUS_CFG_CHANGED));
3911 udelay(5);
3912 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC
3913 MAC_STATUS_CFG_CHANGED |
3914 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT
3915 break;
3916 }
3917
3918 mac_status = tr32(MAC_STATUS);
3919 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3920 current_link_up = 0;
3d3ebe74
MC
3921 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3922 tp->serdes_counter == 0) {
1da177e4
LT
3923 tw32_f(MAC_MODE, (tp->mac_mode |
3924 MAC_MODE_SEND_CONFIGS));
3925 udelay(1);
3926 tw32_f(MAC_MODE, tp->mac_mode);
3927 }
3928 }
3929
3930 if (current_link_up == 1) {
3931 tp->link_config.active_speed = SPEED_1000;
3932 tp->link_config.active_duplex = DUPLEX_FULL;
3933 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3934 LED_CTRL_LNKLED_OVERRIDE |
3935 LED_CTRL_1000MBPS_ON));
3936 } else {
3937 tp->link_config.active_speed = SPEED_INVALID;
3938 tp->link_config.active_duplex = DUPLEX_INVALID;
3939 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3940 LED_CTRL_LNKLED_OVERRIDE |
3941 LED_CTRL_TRAFFIC_OVERRIDE));
3942 }
3943
3944 if (current_link_up != netif_carrier_ok(tp->dev)) {
3945 if (current_link_up)
3946 netif_carrier_on(tp->dev);
3947 else
3948 netif_carrier_off(tp->dev);
3949 tg3_link_report(tp);
3950 } else {
8d018621 3951 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT
3952 if (orig_pause_cfg != now_pause_cfg ||
3953 orig_active_speed != tp->link_config.active_speed ||
3954 orig_active_duplex != tp->link_config.active_duplex)
3955 tg3_link_report(tp);
3956 }
3957
3958 return 0;
3959}
3960
747e8f8b
MC
3961static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3962{
3963 int current_link_up, err = 0;
3964 u32 bmsr, bmcr;
3965 u16 current_speed;
3966 u8 current_duplex;
ef167e27 3967 u32 local_adv, remote_adv;
747e8f8b
MC
3968
3969 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3970 tw32_f(MAC_MODE, tp->mac_mode);
3971 udelay(40);
3972
3973 tw32(MAC_EVENT, 0);
3974
3975 tw32_f(MAC_STATUS,
3976 (MAC_STATUS_SYNC_CHANGED |
3977 MAC_STATUS_CFG_CHANGED |
3978 MAC_STATUS_MI_COMPLETION |
3979 MAC_STATUS_LNKSTATE_CHANGED));
3980 udelay(40);
3981
3982 if (force_reset)
3983 tg3_phy_reset(tp);
3984
3985 current_link_up = 0;
3986 current_speed = SPEED_INVALID;
3987 current_duplex = DUPLEX_INVALID;
3988
3989 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3990 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC
3991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3992 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3993 bmsr |= BMSR_LSTATUS;
3994 else
3995 bmsr &= ~BMSR_LSTATUS;
3996 }
747e8f8b
MC
3997
3998 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3999
4000 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4001 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC
4002 /* do nothing, just check for link up at the end */
4003 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4004 u32 adv, new_adv;
4005
4006 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4007 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4008 ADVERTISE_1000XPAUSE |
4009 ADVERTISE_1000XPSE_ASYM |
4010 ADVERTISE_SLCT);
4011
ba4d07a8 4012 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC
4013
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4015 new_adv |= ADVERTISE_1000XHALF;
4016 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4017 new_adv |= ADVERTISE_1000XFULL;
4018
4019 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4020 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4021 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4022 tg3_writephy(tp, MII_BMCR, bmcr);
4023
4024 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4025 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC
4026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4027
4028 return err;
4029 }
4030 } else {
4031 u32 new_bmcr;
4032
4033 bmcr &= ~BMCR_SPEED1000;
4034 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4035
4036 if (tp->link_config.duplex == DUPLEX_FULL)
4037 new_bmcr |= BMCR_FULLDPLX;
4038
4039 if (new_bmcr != bmcr) {
4040 /* BMCR_SPEED1000 is a reserved bit that needs
4041 * to be set on write.
4042 */
4043 new_bmcr |= BMCR_SPEED1000;
4044
4045 /* Force a linkdown */
4046 if (netif_carrier_ok(tp->dev)) {
4047 u32 adv;
4048
4049 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4050 adv &= ~(ADVERTISE_1000XFULL |
4051 ADVERTISE_1000XHALF |
4052 ADVERTISE_SLCT);
4053 tg3_writephy(tp, MII_ADVERTISE, adv);
4054 tg3_writephy(tp, MII_BMCR, bmcr |
4055 BMCR_ANRESTART |
4056 BMCR_ANENABLE);
4057 udelay(10);
4058 netif_carrier_off(tp->dev);
4059 }
4060 tg3_writephy(tp, MII_BMCR, new_bmcr);
4061 bmcr = new_bmcr;
4062 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4063 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC
4064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4065 ASIC_REV_5714) {
4066 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4067 bmsr |= BMSR_LSTATUS;
4068 else
4069 bmsr &= ~BMSR_LSTATUS;
4070 }
747e8f8b
MC
4071 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4072 }
4073 }
4074
4075 if (bmsr & BMSR_LSTATUS) {
4076 current_speed = SPEED_1000;
4077 current_link_up = 1;
4078 if (bmcr & BMCR_FULLDPLX)
4079 current_duplex = DUPLEX_FULL;
4080 else
4081 current_duplex = DUPLEX_HALF;
4082
ef167e27
MC
4083 local_adv = 0;
4084 remote_adv = 0;
4085
747e8f8b 4086 if (bmcr & BMCR_ANENABLE) {
ef167e27 4087 u32 common;
747e8f8b
MC
4088
4089 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4090 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4091 common = local_adv & remote_adv;
4092 if (common & (ADVERTISE_1000XHALF |
4093 ADVERTISE_1000XFULL)) {
4094 if (common & ADVERTISE_1000XFULL)
4095 current_duplex = DUPLEX_FULL;
4096 else
4097 current_duplex = DUPLEX_HALF;
747e8f8b
MC
4098 }
4099 else
4100 current_link_up = 0;
4101 }
4102 }
4103
ef167e27
MC
4104 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4105 tg3_setup_flow_control(tp, local_adv, remote_adv);
4106
747e8f8b
MC
4107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4108 if (tp->link_config.active_duplex == DUPLEX_HALF)
4109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4110
4111 tw32_f(MAC_MODE, tp->mac_mode);
4112 udelay(40);
4113
4114 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4115
4116 tp->link_config.active_speed = current_speed;
4117 tp->link_config.active_duplex = current_duplex;
4118
4119 if (current_link_up != netif_carrier_ok(tp->dev)) {
4120 if (current_link_up)
4121 netif_carrier_on(tp->dev);
4122 else {
4123 netif_carrier_off(tp->dev);
4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4125 }
4126 tg3_link_report(tp);
4127 }
4128 return err;
4129}
4130
4131static void tg3_serdes_parallel_detect(struct tg3 *tp)
4132{
3d3ebe74 4133 if (tp->serdes_counter) {
747e8f8b 4134 /* Give autoneg time to complete. */
3d3ebe74 4135 tp->serdes_counter--;
747e8f8b
MC
4136 return;
4137 }
4138 if (!netif_carrier_ok(tp->dev) &&
4139 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4140 u32 bmcr;
4141
4142 tg3_readphy(tp, MII_BMCR, &bmcr);
4143 if (bmcr & BMCR_ANENABLE) {
4144 u32 phy1, phy2;
4145
4146 /* Select shadow register 0x1f */
4147 tg3_writephy(tp, 0x1c, 0x7c00);
4148 tg3_readphy(tp, 0x1c, &phy1);
4149
4150 /* Select expansion interrupt status register */
4151 tg3_writephy(tp, 0x17, 0x0f01);
4152 tg3_readphy(tp, 0x15, &phy2);
4153 tg3_readphy(tp, 0x15, &phy2);
4154
4155 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4156 /* We have signal detect and not receiving
4157 * config code words, link is up by parallel
4158 * detection.
4159 */
4160
4161 bmcr &= ~BMCR_ANENABLE;
4162 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4163 tg3_writephy(tp, MII_BMCR, bmcr);
4164 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4165 }
4166 }
4167 }
4168 else if (netif_carrier_ok(tp->dev) &&
4169 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4170 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4171 u32 phy2;
4172
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp, 0x17, 0x0f01);
4175 tg3_readphy(tp, 0x15, &phy2);
4176 if (phy2 & 0x20) {
4177 u32 bmcr;
4178
4179 /* Config code words received, turn on autoneg. */
4180 tg3_readphy(tp, MII_BMCR, &bmcr);
4181 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4182
4183 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4184
4185 }
4186 }
4187}
4188
1da177e4
LT
4189static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4190{
4191 int err;
4192
4193 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4194 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC
4195 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4196 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT
4197 } else {
4198 err = tg3_setup_copper_phy(tp, force_reset);
4199 }
4200
bcb37f6c 4201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC
4202 u32 val, scale;
4203
4204 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4205 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4206 scale = 65;
4207 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4208 scale = 6;
4209 else
4210 scale = 12;
4211
4212 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4213 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4214 tw32(GRC_MISC_CFG, val);
4215 }
4216
1da177e4
LT
4217 if (tp->link_config.active_speed == SPEED_1000 &&
4218 tp->link_config.active_duplex == DUPLEX_HALF)
4219 tw32(MAC_TX_LENGTHS,
4220 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4221 (6 << TX_LENGTHS_IPG_SHIFT) |
4222 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4223 else
4224 tw32(MAC_TX_LENGTHS,
4225 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4226 (6 << TX_LENGTHS_IPG_SHIFT) |
4227 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4228
4229 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4230 if (netif_carrier_ok(tp->dev)) {
4231 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4232 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT
4233 } else {
4234 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4235 }
4236 }
4237
8ed5d97e
MC
4238 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4239 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4240 if (!netif_carrier_ok(tp->dev))
4241 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4242 tp->pwrmgmt_thresh;
4243 else
4244 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4245 tw32(PCIE_PWR_MGMT_THRESH, val);
4246 }
4247
1da177e4
LT
4248 return err;
4249}
4250
df3e6548
MC
4251/* This is called whenever we suspect that the system chipset is re-
4252 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4253 * is bogus tx completions. We try to recover by setting the
4254 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4255 * in the workqueue.
4256 */
4257static void tg3_tx_recover(struct tg3 *tp)
4258{
4259 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4260 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4261
4262 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4263 "mapped I/O cycles to the network device, attempting to "
4264 "recover. Please report the problem to the driver maintainer "
4265 "and include system chipset information.\n", tp->dev->name);
4266
4267 spin_lock(&tp->lock);
df3e6548 4268 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC
4269 spin_unlock(&tp->lock);
4270}
4271
1b2a7205
MC
4272static inline u32 tg3_tx_avail(struct tg3 *tp)
4273{
4274 smp_mb();
4275 return (tp->tx_pending -
4276 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4277}
4278
1da177e4
LT
4279/* Tigon3 never reports partial packet sends. So we do not
4280 * need special logic to handle SKBs that have not had all
4281 * of their frags sent yet, like SunGEM does.
4282 */
17375d25 4283static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4284{
17375d25 4285 struct tg3 *tp = tnapi->tp;
898a56f8 4286 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
1da177e4
LT
4287 u32 sw_idx = tp->tx_cons;
4288
4289 while (sw_idx != hw_idx) {
4290 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4291 struct sk_buff *skb = ri->skb;
df3e6548
MC
4292 int i, tx_bug = 0;
4293
4294 if (unlikely(skb == NULL)) {
4295 tg3_tx_recover(tp);
4296 return;
4297 }
1da177e4 4298
90079ce8 4299 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT
4300
4301 ri->skb = NULL;
4302
4303 sw_idx = NEXT_TX(sw_idx);
4304
4305 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4306 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC
4307 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4308 tx_bug = 1;
1da177e4
LT
4309 sw_idx = NEXT_TX(sw_idx);
4310 }
4311
f47c11ee 4312 dev_kfree_skb(skb);
df3e6548
MC
4313
4314 if (unlikely(tx_bug)) {
4315 tg3_tx_recover(tp);
4316 return;
4317 }
1da177e4
LT
4318 }
4319
4320 tp->tx_cons = sw_idx;
4321
1b2a7205
MC
4322 /* Need to make the tx_cons update visible to tg3_start_xmit()
4323 * before checking for netif_queue_stopped(). Without the
4324 * memory barrier, there is a small possibility that tg3_start_xmit()
4325 * will miss it and cause the queue to be stopped forever.
4326 */
4327 smp_mb();
4328
4329 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4330 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4331 netif_tx_lock(tp->dev);
51b91468 4332 if (netif_queue_stopped(tp->dev) &&
42952231 4333 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4334 netif_wake_queue(tp->dev);
1b2a7205 4335 netif_tx_unlock(tp->dev);
51b91468 4336 }
1da177e4
LT
4337}
4338
4339/* Returns size of skb allocated or < 0 on error.
4340 *
4341 * We only need to fill in the address because the other members
4342 * of the RX descriptor are invariant, see tg3_init_rings.
4343 *
4344 * Note the purposeful assymetry of cpu vs. chip accesses. For
4345 * posting buffers we only dirty the first cache line of the RX
4346 * descriptor (containing the address). Whereas for the RX status
4347 * buffers the cpu only reads the last cacheline of the RX descriptor
4348 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4349 */
17375d25 4350static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT
4351 int src_idx, u32 dest_idx_unmasked)
4352{
17375d25 4353 struct tg3 *tp = tnapi->tp;
1da177e4
LT
4354 struct tg3_rx_buffer_desc *desc;
4355 struct ring_info *map, *src_map;
4356 struct sk_buff *skb;
4357 dma_addr_t mapping;
4358 int skb_size, dest_idx;
21f581a5 4359 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT
4360
4361 src_map = NULL;
4362 switch (opaque_key) {
4363 case RXD_OPAQUE_RING_STD:
4364 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC
4365 desc = &tpr->rx_std[dest_idx];
4366 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4367 if (src_idx >= 0)
21f581a5 4368 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4369 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT
4370 break;
4371
4372 case RXD_OPAQUE_RING_JUMBO:
4373 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4374 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4375 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4376 if (src_idx >= 0)
21f581a5 4377 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4378 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT
4379 break;
4380
4381 default:
4382 return -EINVAL;
855e1111 4383 }
1da177e4
LT
4384
4385 /* Do not overwrite any of the map or rp information
4386 * until we are sure we can commit to a new buffer.
4387 *
4388 * Callers depend upon this behavior and assume that
4389 * we leave everything unchanged if we fail.
4390 */
287be12e 4391 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT
4392 if (skb == NULL)
4393 return -ENOMEM;
4394
1da177e4
LT
4395 skb_reserve(skb, tp->rx_offset);
4396
287be12e 4397 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT
4398 PCI_DMA_FROMDEVICE);
4399
4400 map->skb = skb;
4401 pci_unmap_addr_set(map, mapping, mapping);
4402
4403 if (src_map != NULL)
4404 src_map->skb = NULL;
4405
4406 desc->addr_hi = ((u64)mapping >> 32);
4407 desc->addr_lo = ((u64)mapping & 0xffffffff);
4408
4409 return skb_size;
4410}
4411
4412/* We only need to move over in the address because the other
4413 * members of the RX descriptor are invariant. See notes above
4414 * tg3_alloc_rx_skb for full details.
4415 */
17375d25 4416static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT
4417 int src_idx, u32 dest_idx_unmasked)
4418{
17375d25 4419 struct tg3 *tp = tnapi->tp;
1da177e4
LT
4420 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4421 struct ring_info *src_map, *dest_map;
4422 int dest_idx;
21f581a5 4423 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT
4424
4425 switch (opaque_key) {
4426 case RXD_OPAQUE_RING_STD:
4427 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC
4428 dest_desc = &tpr->rx_std[dest_idx];
4429 dest_map = &tpr->rx_std_buffers[dest_idx];
4430 src_desc = &tpr->rx_std[src_idx];
4431 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT
4432 break;
4433
4434 case RXD_OPAQUE_RING_JUMBO:
4435 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4436 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4437 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4438 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4439 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT
4440 break;
4441
4442 default:
4443 return;
855e1111 4444 }
1da177e4
LT
4445
4446 dest_map->skb = src_map->skb;
4447 pci_unmap_addr_set(dest_map, mapping,
4448 pci_unmap_addr(src_map, mapping));
4449 dest_desc->addr_hi = src_desc->addr_hi;
4450 dest_desc->addr_lo = src_desc->addr_lo;
4451
4452 src_map->skb = NULL;
4453}
4454
1da177e4
LT
4455/* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4458 *
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4464 *
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4471 *
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4478 */
17375d25 4479static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4480{
17375d25 4481 struct tg3 *tp = tnapi->tp;
f92905de 4482 u32 work_mask, rx_std_posted = 0;
483ba50b
MC
4483 u32 sw_idx = tp->rx_rcb_ptr;
4484 u16 hw_idx;
1da177e4 4485 int received;
21f581a5 4486 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4487
898a56f8 4488 hw_idx = tnapi->hw_status->idx[0].rx_producer;
1da177e4
LT
4489 /*
4490 * We need to order the read of hw_idx and the read of
4491 * the opaque cookie.
4492 */
4493 rmb();
1da177e4
LT
4494 work_mask = 0;
4495 received = 0;
4496 while (sw_idx != hw_idx && budget > 0) {
4497 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4498 unsigned int len;
4499 struct sk_buff *skb;
4500 dma_addr_t dma_addr;
4501 u32 opaque_key, desc_idx, *post_ptr;
4502
4503 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4504 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4505 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC
4506 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4507 dma_addr = pci_unmap_addr(ri, mapping);
4508 skb = ri->skb;
4509 post_ptr = &tpr->rx_std_ptr;
f92905de 4510 rx_std_posted++;
1da177e4 4511 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC
4512 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4513 dma_addr = pci_unmap_addr(ri, mapping);
4514 skb = ri->skb;
4515 post_ptr = &tpr->rx_jmb_ptr;
4516 } else
1da177e4 4517 goto next_pkt_nopost;
1da177e4
LT
4518
4519 work_mask |= opaque_key;
4520
4521 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4522 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4523 drop_it:
17375d25 4524 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT
4525 desc_idx, *post_ptr);
4526 drop_it_no_recycle:
4527 /* Other statistics kept track of by card. */
4528 tp->net_stats.rx_dropped++;
4529 goto next_pkt;
4530 }
4531
ad829268
MC
4532 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4533 ETH_FCS_LEN;
1da177e4 4534
6aa20a22 4535 if (len > RX_COPY_THRESHOLD
ad829268
MC
4536 && tp->rx_offset == NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4540 */
1da177e4
LT
4541 ) {
4542 int skb_size;
4543
17375d25 4544 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT
4545 desc_idx, *post_ptr);
4546 if (skb_size < 0)
4547 goto drop_it;
4548
287be12e 4549 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT
4550 PCI_DMA_FROMDEVICE);
4551
4552 skb_put(skb, len);
4553 } else {
4554 struct sk_buff *copy_skb;
4555
17375d25 4556 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT
4557 desc_idx, *post_ptr);
4558
ad829268
MC
4559 copy_skb = netdev_alloc_skb(tp->dev,
4560 len + TG3_RAW_IP_ALIGN);
1da177e4
LT
4561 if (copy_skb == NULL)
4562 goto drop_it_no_recycle;
4563
ad829268 4564 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT
4565 skb_put(copy_skb, len);
4566 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4567 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT
4568 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4569
4570 /* We'll reuse the original ring buffer. */
4571 skb = copy_skb;
4572 }
4573
4574 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4575 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4576 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4577 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4578 skb->ip_summed = CHECKSUM_UNNECESSARY;
4579 else
4580 skb->ip_summed = CHECKSUM_NONE;
4581
4582 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC
4583
4584 if (len > (tp->dev->mtu + ETH_HLEN) &&
4585 skb->protocol != htons(ETH_P_8021Q)) {
4586 dev_kfree_skb(skb);
4587 goto next_pkt;
4588 }
4589
1da177e4
LT
4590#if TG3_VLAN_TAG_USED
4591 if (tp->vlgrp != NULL &&
4592 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4593 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4594 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT
4595 } else
4596#endif
17375d25 4597 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4598
1da177e4
LT
4599 received++;
4600 budget--;
4601
4602next_pkt:
4603 (*post_ptr)++;
f92905de
MC
4604
4605 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4606 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4607
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4609 TG3_64BIT_REG_LOW, idx);
4610 work_mask &= ~RXD_OPAQUE_RING_STD;
4611 rx_std_posted = 0;
4612 }
1da177e4 4613next_pkt_nopost:
483ba50b 4614 sw_idx++;
6b31a515 4615 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC
4616
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx == hw_idx) {
898a56f8 4619 hw_idx = tnapi->hw_status->idx[0].rx_producer;
52f6d697
MC
4620 rmb();
4621 }
1da177e4
LT
4622 }
4623
4624 /* ACK the status ring. */
483ba50b
MC
4625 tp->rx_rcb_ptr = sw_idx;
4626 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT
4627
4628 /* Refill RX ring(s). */
4629 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4630 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT
4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4632 sw_idx);
4633 }
4634 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4635 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT
4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4637 sw_idx);
4638 }
4639 mmiowb();
4640
4641 return received;
4642}
4643
17375d25 4644static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4645{
17375d25 4646 struct tg3 *tp = tnapi->tp;
898a56f8 4647 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4648
1da177e4
LT
4649 /* handle link change and other phy events */
4650 if (!(tp->tg3_flags &
4651 (TG3_FLAG_USE_LINKCHG_REG |
4652 TG3_FLAG_POLL_SERDES))) {
4653 if (sblk->status & SD_STATUS_LINK_CHG) {
4654 sblk->status = SD_STATUS_UPDATED |
4655 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4656 spin_lock(&tp->lock);
dd477003
MC
4657 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4658 tw32_f(MAC_STATUS,
4659 (MAC_STATUS_SYNC_CHANGED |
4660 MAC_STATUS_CFG_CHANGED |
4661 MAC_STATUS_MI_COMPLETION |
4662 MAC_STATUS_LNKSTATE_CHANGED));
4663 udelay(40);
4664 } else
4665 tg3_setup_phy(tp, 0);
f47c11ee 4666 spin_unlock(&tp->lock);
1da177e4
LT
4667 }
4668 }
4669
4670 /* run TX completion thread */
4671 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
17375d25 4672 tg3_tx(tnapi);
6f535763 4673 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4674 return work_done;
1da177e4
LT
4675 }
4676
1da177e4
LT
4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
bea3348e 4679 * code synchronizes with tg3->napi.poll()
1da177e4 4680 */
bea3348e 4681 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
17375d25 4682 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4683
6f535763
DM
4684 return work_done;
4685}
4686
4687static int tg3_poll(struct napi_struct *napi, int budget)
4688{
8ef0442f
MC
4689 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4690 struct tg3 *tp = tnapi->tp;
6f535763 4691 int work_done = 0;
898a56f8 4692 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM
4693
4694 while (1) {
17375d25 4695 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM
4696
4697 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4698 goto tx_recovery;
4699
4700 if (unlikely(work_done >= budget))
4701 break;
4702
4fd7ab59 4703 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4704 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC
4705 * to tell the hw how much work has been processed,
4706 * so we must read it before checking for more work.
4707 */
898a56f8
MC
4708 tnapi->last_tag = sblk->status_tag;
4709 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC
4710 rmb();
4711 } else
4712 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4713
17375d25 4714 if (likely(!tg3_has_work(tnapi))) {
288379f0 4715 napi_complete(napi);
17375d25 4716 tg3_int_reenable(tnapi);
6f535763
DM
4717 break;
4718 }
1da177e4
LT
4719 }
4720
bea3348e 4721 return work_done;
6f535763
DM
4722
4723tx_recovery:
4fd7ab59 4724 /* work_done is guaranteed to be less than budget. */
288379f0 4725 napi_complete(napi);
6f535763 4726 schedule_work(&tp->reset_task);
4fd7ab59 4727 return work_done;
1da177e4
LT
4728}
4729
f47c11ee
DM
4730static void tg3_irq_quiesce(struct tg3 *tp)
4731{
4732 BUG_ON(tp->irq_sync);
4733
4734 tp->irq_sync = 1;
4735 smp_mb();
4736
4737 synchronize_irq(tp->pdev->irq);
4738}
4739
4740static inline int tg3_irq_sync(struct tg3 *tp)
4741{
4742 return tp->irq_sync;
4743}
4744
4745/* Fully shutdown all tg3 driver activity elsewhere in the system.
4746 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4747 * with as well. Most of the time, this is not necessary except when
4748 * shutting down the device.
4749 */
4750static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4751{
46966545 4752 spin_lock_bh(&tp->lock);
f47c11ee
DM
4753 if (irq_sync)
4754 tg3_irq_quiesce(tp);
f47c11ee
DM
4755}
4756
4757static inline void tg3_full_unlock(struct tg3 *tp)
4758{
f47c11ee
DM
4759 spin_unlock_bh(&tp->lock);
4760}
4761
fcfa0a32
MC
4762/* One-shot MSI handler - Chip automatically disables interrupt
4763 * after sending MSI so driver doesn't have to do it.
4764 */
7d12e780 4765static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4766{
09943a18
MC
4767 struct tg3_napi *tnapi = dev_id;
4768 struct tg3 *tp = tnapi->tp;
fcfa0a32 4769
898a56f8 4770 prefetch(tnapi->hw_status);
fcfa0a32
MC
4771 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4772
4773 if (likely(!tg3_irq_sync(tp)))
09943a18 4774 napi_schedule(&tnapi->napi);
fcfa0a32
MC
4775
4776 return IRQ_HANDLED;
4777}
4778
88b06bc2
MC
4779/* MSI ISR - No need to check for interrupt sharing and no need to
4780 * flush status block and interrupt mailbox. PCI ordering rules
4781 * guarantee that MSI will arrive after the status block.
4782 */
7d12e780 4783static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4784{
09943a18
MC
4785 struct tg3_napi *tnapi = dev_id;
4786 struct tg3 *tp = tnapi->tp;
88b06bc2 4787
898a56f8 4788 prefetch(tnapi->hw_status);
61487480 4789 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4790 /*
fac9b83e 4791 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4792 * chip-internal interrupt pending events.
fac9b83e 4793 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC
4794 * NIC to stop sending us irqs, engaging "in-intr-handler"
4795 * event coalescing.
4796 */
4797 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4798 if (likely(!tg3_irq_sync(tp)))
09943a18 4799 napi_schedule(&tnapi->napi);
61487480 4800
88b06bc2
MC
4801 return IRQ_RETVAL(1);
4802}
4803
7d12e780 4804static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4805{
09943a18
MC
4806 struct tg3_napi *tnapi = dev_id;
4807 struct tg3 *tp = tnapi->tp;
898a56f8 4808 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT
4809 unsigned int handled = 1;
4810
1da177e4
LT
4811 /* In INTx mode, it is possible for the interrupt to arrive at
4812 * the CPU before the status block posted prior to the interrupt.
4813 * Reading the PCI State register will confirm whether the
4814 * interrupt is ours and will flush the status block.
4815 */
d18edcb2
MC
4816 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4817 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4818 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4819 handled = 0;
f47c11ee 4820 goto out;
fac9b83e 4821 }
d18edcb2
MC
4822 }
4823
4824 /*
4825 * Writing any value to intr-mbox-0 clears PCI INTA# and
4826 * chip-internal interrupt pending events.
4827 * Writing non-zero to intr-mbox-0 additional tells the
4828 * NIC to stop sending us irqs, engaging "in-intr-handler"
4829 * event coalescing.
c04cb347
MC
4830 *
4831 * Flush the mailbox to de-assert the IRQ immediately to prevent
4832 * spurious interrupts. The flush impacts performance but
4833 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4834 */
c04cb347 4835 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC
4836 if (tg3_irq_sync(tp))
4837 goto out;
4838 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4839 if (likely(tg3_has_work(tnapi))) {
d18edcb2 4840 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
09943a18 4841 napi_schedule(&tnapi->napi);
d18edcb2
MC
4842 } else {
4843 /* No work, shared interrupt perhaps? re-enable
4844 * interrupts, and flush that PCI write
4845 */
4846 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4847 0x00000000);
fac9b83e 4848 }
f47c11ee 4849out:
fac9b83e
DM
4850 return IRQ_RETVAL(handled);
4851}
4852
7d12e780 4853static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4854{
09943a18
MC
4855 struct tg3_napi *tnapi = dev_id;
4856 struct tg3 *tp = tnapi->tp;
898a56f8 4857 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM
4858 unsigned int handled = 1;
4859
fac9b83e
DM
4860 /* In INTx mode, it is possible for the interrupt to arrive at
4861 * the CPU before the status block posted prior to the interrupt.
4862 * Reading the PCI State register will confirm whether the
4863 * interrupt is ours and will flush the status block.
4864 */
898a56f8 4865 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC
4866 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4867 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4868 handled = 0;
f47c11ee 4869 goto out;
1da177e4 4870 }
d18edcb2
MC
4871 }
4872
4873 /*
4874 * writing any value to intr-mbox-0 clears PCI INTA# and
4875 * chip-internal interrupt pending events.
4876 * writing non-zero to intr-mbox-0 additional tells the
4877 * NIC to stop sending us irqs, engaging "in-intr-handler"
4878 * event coalescing.
c04cb347
MC
4879 *
4880 * Flush the mailbox to de-assert the IRQ immediately to prevent
4881 * spurious interrupts. The flush impacts performance but
4882 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4883 */
c04cb347 4884 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC
4885
4886 /*
4887 * In a shared interrupt configuration, sometimes other devices'
4888 * interrupts will scream. We record the current status tag here
4889 * so that the above check can report that the screaming interrupts
4890 * are unhandled. Eventually they will be silenced.
4891 */
898a56f8 4892 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4893
d18edcb2
MC
4894 if (tg3_irq_sync(tp))
4895 goto out;
624f8e50
MC
4896
4897 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4898
09943a18 4899 napi_schedule(&tnapi->napi);
624f8e50 4900
f47c11ee 4901out:
1da177e4
LT
4902 return IRQ_RETVAL(handled);
4903}
4904
7938109f 4905/* ISR for interrupt test */
7d12e780 4906static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4907{
09943a18
MC
4908 struct tg3_napi *tnapi = dev_id;
4909 struct tg3 *tp = tnapi->tp;
898a56f8 4910 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4911
f9804ddb
MC
4912 if ((sblk->status & SD_STATUS_UPDATED) ||
4913 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4914 tg3_disable_ints(tp);
7938109f
MC
4915 return IRQ_RETVAL(1);
4916 }
4917 return IRQ_RETVAL(0);
4918}
4919
8e7a22e3 4920static int tg3_init_hw(struct tg3 *, int);
944d980e 4921static int tg3_halt(struct tg3 *, int, int);
1da177e4 4922
b9ec6c1b
MC
4923/* Restart hardware after configuration changes, self-test, etc.
4924 * Invoked with tp->lock held.
4925 */
4926static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED
4927 __releases(tp->lock)
4928 __acquires(tp->lock)
b9ec6c1b
MC
4929{
4930 int err;
4931
4932 err = tg3_init_hw(tp, reset_phy);
4933 if (err) {
4934 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4935 "aborting.\n", tp->dev->name);
4936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4937 tg3_full_unlock(tp);
4938 del_timer_sync(&tp->timer);
4939 tp->irq_sync = 0;
8ef0442f 4940 napi_enable(&tp->napi[0].napi);
b9ec6c1b
MC
4941 dev_close(tp->dev);
4942 tg3_full_lock(tp, 0);
4943 }
4944 return err;
4945}
4946
1da177e4
LT
4947#ifdef CONFIG_NET_POLL_CONTROLLER
4948static void tg3_poll_controller(struct net_device *dev)
4949{
88b06bc2
MC
4950 struct tg3 *tp = netdev_priv(dev);
4951
7d12e780 4952 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT
4953}
4954#endif
4955
c4028958 4956static void tg3_reset_task(struct work_struct *work)
1da177e4 4957{
c4028958 4958 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4959 int err;
1da177e4
LT
4960 unsigned int restart_timer;
4961
7faa006f 4962 tg3_full_lock(tp, 0);
7faa006f
MC
4963
4964 if (!netif_running(tp->dev)) {
7faa006f
MC
4965 tg3_full_unlock(tp);
4966 return;
4967 }
4968
4969 tg3_full_unlock(tp);
4970
b02fd9e3
MC
4971 tg3_phy_stop(tp);
4972
1da177e4
LT
4973 tg3_netif_stop(tp);
4974
f47c11ee 4975 tg3_full_lock(tp, 1);
1da177e4
LT
4976
4977 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4978 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4979
df3e6548
MC
4980 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4981 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4982 tp->write32_rx_mbox = tg3_write_flush_reg32;
4983 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4984 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4985 }
4986
944d980e 4987 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC
4988 err = tg3_init_hw(tp, 1);
4989 if (err)
b9ec6c1b 4990 goto out;
1da177e4
LT
4991
4992 tg3_netif_start(tp);
4993
1da177e4
LT
4994 if (restart_timer)
4995 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4996
b9ec6c1b 4997out:
7faa006f 4998 tg3_full_unlock(tp);
b02fd9e3
MC
4999
5000 if (!err)
5001 tg3_phy_start(tp);
1da177e4
LT
5002}
5003
b0408751
MC
5004static void tg3_dump_short_state(struct tg3 *tp)
5005{
5006 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5007 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5008 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5009 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5010}
5011
1da177e4
LT
5012static void tg3_tx_timeout(struct net_device *dev)
5013{
5014 struct tg3 *tp = netdev_priv(dev);
5015
b0408751 5016 if (netif_msg_tx_err(tp)) {
9f88f29f
MC
5017 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5018 dev->name);
b0408751
MC
5019 tg3_dump_short_state(tp);
5020 }
1da177e4
LT
5021
5022 schedule_work(&tp->reset_task);
5023}
5024
c58ec932
MC
5025/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5026static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5027{
5028 u32 base = (u32) mapping & 0xffffffff;
5029
5030 return ((base > 0xffffdcc0) &&
5031 (base + len + 8 < base));
5032}
5033
72f2afb8
MC
5034/* Test for DMA addresses > 40-bit */
5035static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5036 int len)
5037{
5038#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5039 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5040 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC
5041 return 0;
5042#else
5043 return 0;
5044#endif
5045}
5046
1da177e4
LT
5047static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5048
72f2afb8
MC
5049/* Workaround 4GB and 40-bit hardware DMA bugs. */
5050static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC
5051 u32 last_plus_one, u32 *start,
5052 u32 base_flags, u32 mss)
1da177e4 5053{
41588ba1 5054 struct sk_buff *new_skb;
c58ec932 5055 dma_addr_t new_addr = 0;
1da177e4 5056 u32 entry = *start;
c58ec932 5057 int i, ret = 0;
1da177e4 5058
41588ba1
MC
5059 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5060 new_skb = skb_copy(skb, GFP_ATOMIC);
5061 else {
5062 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5063
5064 new_skb = skb_copy_expand(skb,
5065 skb_headroom(skb) + more_headroom,
5066 skb_tailroom(skb), GFP_ATOMIC);
5067 }
5068
1da177e4 5069 if (!new_skb) {
c58ec932
MC
5070 ret = -1;
5071 } else {
5072 /* New SKB is guaranteed to be linear. */
5073 entry = *start;
90079ce8 5074 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5075 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5076
c58ec932
MC
5077 /* Make sure new skb does not cross any 4G boundaries.
5078 * Drop the packet if it does.
5079 */
90079ce8 5080 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM
5081 if (!ret)
5082 skb_dma_unmap(&tp->pdev->dev, new_skb,
5083 DMA_TO_DEVICE);
c58ec932
MC
5084 ret = -1;
5085 dev_kfree_skb(new_skb);
5086 new_skb = NULL;
5087 } else {
5088 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5089 base_flags, 1 | (mss << 1));
5090 *start = NEXT_TX(entry);
5091 }
1da177e4
LT
5092 }
5093
1da177e4
LT
5094 /* Now clean up the sw ring entries. */
5095 i = 0;
5096 while (entry != last_plus_one) {
1da177e4
LT
5097 if (i == 0) {
5098 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT
5099 } else {
5100 tp->tx_buffers[entry].skb = NULL;
5101 }
5102 entry = NEXT_TX(entry);
5103 i++;
5104 }
5105
90079ce8 5106 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT
5107 dev_kfree_skb(skb);
5108
c58ec932 5109 return ret;
1da177e4
LT
5110}
5111
5112static void tg3_set_txd(struct tg3 *tp, int entry,
5113 dma_addr_t mapping, int len, u32 flags,
5114 u32 mss_and_is_end)
5115{
5116 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5117 int is_end = (mss_and_is_end & 0x1);
5118 u32 mss = (mss_and_is_end >> 1);
5119 u32 vlan_tag = 0;
5120
5121 if (is_end)
5122 flags |= TXD_FLAG_END;
5123 if (flags & TXD_FLAG_VLAN) {
5124 vlan_tag = flags >> 16;
5125 flags &= 0xffff;
5126 }
5127 vlan_tag |= (mss << TXD_MSS_SHIFT);
5128
5129 txd->addr_hi = ((u64) mapping >> 32);
5130 txd->addr_lo = ((u64) mapping & 0xffffffff);
5131 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5132 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5133}
5134
5a6f3074
MC
5135/* hard_start_xmit for devices that don't have any bugs and
5136 * support TG3_FLG2_HW_TSO_2 only.
5137 */
1da177e4 5138static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC
5139{
5140 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5141 u32 len, entry, base_flags, mss;
90079ce8
DM
5142 struct skb_shared_info *sp;
5143 dma_addr_t mapping;
5a6f3074
MC
5144
5145 len = skb_headlen(skb);
5146
00b70504 5147 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5148 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC
5149 * interrupt. Furthermore, IRQ processing runs lockless so we have
5150 * no IRQ context deadlocks to worry about either. Rejoice!
5151 */
1b2a7205 5152 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC
5153 if (!netif_queue_stopped(dev)) {
5154 netif_stop_queue(dev);
5155
5156 /* This is a hard error, log it. */
5157 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5158 "queue awake!\n", dev->name);
5159 }
5a6f3074
MC
5160 return NETDEV_TX_BUSY;
5161 }
5162
5163 entry = tp->tx_prod;
5164 base_flags = 0;
5a6f3074 5165 mss = 0;
c13e3713 5166 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC
5167 int tcp_opt_len, ip_tcp_len;
5168
5169 if (skb_header_cloned(skb) &&
5170 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5171 dev_kfree_skb(skb);
5172 goto out_unlock;
5173 }
5174
b0026624
MC
5175 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5176 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5177 else {
eddc9ec5
ACM
5178 struct iphdr *iph = ip_hdr(skb);
5179
ab6a5bb6 5180 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5181 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5182
eddc9ec5
ACM
5183 iph->check = 0;
5184 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC
5185 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5186 }
5a6f3074
MC
5187
5188 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5189 TXD_FLAG_CPU_POST_DMA);
5190
aa8223c7 5191 tcp_hdr(skb)->check = 0;
5a6f3074 5192
5a6f3074 5193 }
84fa7933 5194 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5195 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC
5196#if TG3_VLAN_TAG_USED
5197 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5198 base_flags |= (TXD_FLAG_VLAN |
5199 (vlan_tx_tag_get(skb) << 16));
5200#endif
5201
90079ce8
DM
5202 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5203 dev_kfree_skb(skb);
5204 goto out_unlock;
5205 }
5206
5207 sp = skb_shinfo(skb);
5208
042a53a9 5209 mapping = sp->dma_head;
5a6f3074
MC
5210
5211 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC
5212
5213 tg3_set_txd(tp, entry, mapping, len, base_flags,
5214 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5215
5216 entry = NEXT_TX(entry);
5217
5218 /* Now loop through additional data fragments, and queue them. */
5219 if (skb_shinfo(skb)->nr_frags > 0) {
5220 unsigned int i, last;
5221
5222 last = skb_shinfo(skb)->nr_frags - 1;
5223 for (i = 0; i <= last; i++) {
5224 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5225
5226 len = frag->size;
042a53a9 5227 mapping = sp->dma_maps[i];
5a6f3074 5228 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC
5229
5230 tg3_set_txd(tp, entry, mapping, len,
5231 base_flags, (i == last) | (mss << 1));
5232
5233 entry = NEXT_TX(entry);
5234 }
5235 }
5236
5237 /* Packets are ready, update Tx producer idx local and on card. */
5238 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5239
5240 tp->tx_prod = entry;
1b2a7205 5241 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5242 netif_stop_queue(dev);
42952231 5243 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC
5244 netif_wake_queue(tp->dev);
5245 }
5246
5247out_unlock:
cdd0db05 5248 mmiowb();
5a6f3074
MC
5249
5250 return NETDEV_TX_OK;
5251}
5252
52c0fd83
MC
5253static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5254
5255/* Use GSO to workaround a rare TSO bug that may be triggered when the
5256 * TSO header is greater than 80 bytes.
5257 */
5258static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5259{
5260 struct sk_buff *segs, *nskb;
5261
5262 /* Estimate the number of fragments in the worst case */
1b2a7205 5263 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5264 netif_stop_queue(tp->dev);
7f62ad5d
MC
5265 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5266 return NETDEV_TX_BUSY;
5267
5268 netif_wake_queue(tp->dev);
52c0fd83
MC
5269 }
5270
5271 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5272 if (IS_ERR(segs))
52c0fd83
MC
5273 goto tg3_tso_bug_end;
5274
5275 do {
5276 nskb = segs;
5277 segs = segs->next;
5278 nskb->next = NULL;
5279 tg3_start_xmit_dma_bug(nskb, tp->dev);
5280 } while (segs);
5281
5282tg3_tso_bug_end:
5283 dev_kfree_skb(skb);
5284
5285 return NETDEV_TX_OK;
5286}
52c0fd83 5287
5a6f3074
MC
5288/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5289 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5290 */
5291static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT
5292{
5293 struct tg3 *tp = netdev_priv(dev);
1da177e4 5294 u32 len, entry, base_flags, mss;
90079ce8 5295 struct skb_shared_info *sp;
1da177e4 5296 int would_hit_hwbug;
90079ce8 5297 dma_addr_t mapping;
1da177e4
LT
5298
5299 len = skb_headlen(skb);
5300
00b70504 5301 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5302 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM
5303 * interrupt. Furthermore, IRQ processing runs lockless so we have
5304 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5305 */
1b2a7205 5306 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH
5307 if (!netif_queue_stopped(dev)) {
5308 netif_stop_queue(dev);
5309
5310 /* This is a hard error, log it. */
5311 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5312 "queue awake!\n", dev->name);
5313 }
1da177e4
LT
5314 return NETDEV_TX_BUSY;
5315 }
5316
5317 entry = tp->tx_prod;
5318 base_flags = 0;
84fa7933 5319 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5320 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5321 mss = 0;
c13e3713 5322 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5323 struct iphdr *iph;
52c0fd83 5324 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT
5325
5326 if (skb_header_cloned(skb) &&
5327 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5328 dev_kfree_skb(skb);
5329 goto out_unlock;
5330 }
5331
ab6a5bb6 5332 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5333 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5334
52c0fd83
MC
5335 hdr_len = ip_tcp_len + tcp_opt_len;
5336 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5337 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC
5338 return (tg3_tso_bug(tp, skb));
5339
1da177e4
LT
5340 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5341 TXD_FLAG_CPU_POST_DMA);
5342
eddc9ec5
ACM
5343 iph = ip_hdr(skb);
5344 iph->check = 0;
5345 iph->tot_len = htons(mss + hdr_len);
1da177e4 5346 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5347 tcp_hdr(skb)->check = 0;
1da177e4 5348 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM
5349 } else
5350 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5351 iph->daddr, 0,
5352 IPPROTO_TCP,
5353 0);
1da177e4
LT
5354
5355 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5357 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT
5358 int tsflags;
5359
eddc9ec5 5360 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT
5361 mss |= (tsflags << 11);
5362 }
5363 } else {
eddc9ec5 5364 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT
5365 int tsflags;
5366
eddc9ec5 5367 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT
5368 base_flags |= tsflags << 12;
5369 }
5370 }
5371 }
1da177e4
LT
5372#if TG3_VLAN_TAG_USED
5373 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5374 base_flags |= (TXD_FLAG_VLAN |
5375 (vlan_tx_tag_get(skb) << 16));
5376#endif
5377
90079ce8
DM
5378 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5379 dev_kfree_skb(skb);
5380 goto out_unlock;
5381 }
5382
5383 sp = skb_shinfo(skb);
5384
042a53a9 5385 mapping = sp->dma_head;
1da177e4
LT
5386
5387 tp->tx_buffers[entry].skb = skb;
1da177e4
LT
5388
5389 would_hit_hwbug = 0;
5390
41588ba1
MC
5391 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5392 would_hit_hwbug = 1;
5393 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5394 would_hit_hwbug = 1;
1da177e4
LT
5395
5396 tg3_set_txd(tp, entry, mapping, len, base_flags,
5397 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5398
5399 entry = NEXT_TX(entry);
5400
5401 /* Now loop through additional data fragments, and queue them. */
5402 if (skb_shinfo(skb)->nr_frags > 0) {
5403 unsigned int i, last;
5404
5405 last = skb_shinfo(skb)->nr_frags - 1;
5406 for (i = 0; i <= last; i++) {
5407 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5408
5409 len = frag->size;
042a53a9 5410 mapping = sp->dma_maps[i];
1da177e4
LT
5411
5412 tp->tx_buffers[entry].skb = NULL;
1da177e4 5413
c58ec932
MC
5414 if (tg3_4g_overflow_test(mapping, len))
5415 would_hit_hwbug = 1;
1da177e4 5416
72f2afb8
MC
5417 if (tg3_40bit_overflow_test(tp, mapping, len))
5418 would_hit_hwbug = 1;
5419
1da177e4
LT
5420 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5421 tg3_set_txd(tp, entry, mapping, len,
5422 base_flags, (i == last)|(mss << 1));
5423 else
5424 tg3_set_txd(tp, entry, mapping, len,
5425 base_flags, (i == last));
5426
5427 entry = NEXT_TX(entry);
5428 }
5429 }
5430
5431 if (would_hit_hwbug) {
5432 u32 last_plus_one = entry;
5433 u32 start;
1da177e4 5434
c58ec932
MC
5435 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5436 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT
5437
5438 /* If the workaround fails due to memory/mapping
5439 * failure, silently drop this packet.
5440 */
72f2afb8 5441 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5442 &start, base_flags, mss))
1da177e4
LT
5443 goto out_unlock;
5444
5445 entry = start;
5446 }
5447
5448 /* Packets are ready, update Tx producer idx local and on card. */
5449 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5450
5451 tp->tx_prod = entry;
1b2a7205 5452 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5453 netif_stop_queue(dev);
42952231 5454 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC
5455 netif_wake_queue(tp->dev);
5456 }
1da177e4
LT
5457
5458out_unlock:
cdd0db05 5459 mmiowb();
1da177e4
LT
5460
5461 return NETDEV_TX_OK;
5462}
5463
5464static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5465 int new_mtu)
5466{
5467 dev->mtu = new_mtu;
5468
ef7f5ec0 5469 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5470 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC
5471 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5472 ethtool_op_set_tso(dev, 0);
5473 }
5474 else
5475 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5476 } else {
a4e2b347 5477 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5478 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5479 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5480 }
1da177e4
LT
5481}
5482
5483static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5484{
5485 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5486 int err;
1da177e4
LT
5487
5488 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5489 return -EINVAL;
5490
5491 if (!netif_running(dev)) {
5492 /* We'll just catch it later when the
5493 * device is up'd.
5494 */
5495 tg3_set_mtu(dev, tp, new_mtu);
5496 return 0;
5497 }
5498
b02fd9e3
MC
5499 tg3_phy_stop(tp);
5500
1da177e4 5501 tg3_netif_stop(tp);
f47c11ee
DM
5502
5503 tg3_full_lock(tp, 1);
1da177e4 5504
944d980e 5505 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT
5506
5507 tg3_set_mtu(dev, tp, new_mtu);
5508
b9ec6c1b 5509 err = tg3_restart_hw(tp, 0);
1da177e4 5510
b9ec6c1b
MC
5511 if (!err)
5512 tg3_netif_start(tp);
1da177e4 5513
f47c11ee 5514 tg3_full_unlock(tp);
1da177e4 5515
b02fd9e3
MC
5516 if (!err)
5517 tg3_phy_start(tp);
5518
b9ec6c1b 5519 return err;
1da177e4
LT
5520}
5521
21f581a5
MC
5522static void tg3_rx_prodring_free(struct tg3 *tp,
5523 struct tg3_rx_prodring_set *tpr)
1da177e4
LT
5524{
5525 struct ring_info *rxp;
5526 int i;
5527
5528 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5529 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT
5530
5531 if (rxp->skb == NULL)
5532 continue;
1da177e4 5533
1da177e4
LT
5534 pci_unmap_single(tp->pdev,
5535 pci_unmap_addr(rxp, mapping),
cf7a7298 5536 tp->rx_pkt_map_sz,
1da177e4
LT
5537 PCI_DMA_FROMDEVICE);
5538 dev_kfree_skb_any(rxp->skb);
5539 rxp->skb = NULL;
5540 }
5541
cf7a7298
MC
5542 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5543 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5544 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5545
cf7a7298
MC
5546 if (rxp->skb == NULL)
5547 continue;
1da177e4 5548
cf7a7298
MC
5549 pci_unmap_single(tp->pdev,
5550 pci_unmap_addr(rxp, mapping),
5551 TG3_RX_JMB_MAP_SZ,
5552 PCI_DMA_FROMDEVICE);
5553 dev_kfree_skb_any(rxp->skb);
5554 rxp->skb = NULL;
1da177e4 5555 }
1da177e4
LT
5556 }
5557}
5558
5559/* Initialize tx/rx rings for packet processing.
5560 *
5561 * The chip has been shut down and the driver detached from
5562 * the networking, so no interrupts or new tx packets will
5563 * end up in the driver. tp->{tx,}lock are held and thus
5564 * we may not sleep.
5565 */
21f581a5
MC
5566static int tg3_rx_prodring_alloc(struct tg3 *tp,
5567 struct tg3_rx_prodring_set *tpr)
1da177e4 5568{
287be12e 5569 u32 i, rx_pkt_dma_sz;
17375d25 5570 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5571
1da177e4 5572 /* Zero out all descriptors. */
21f581a5 5573 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5574
287be12e 5575 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5576 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC
5577 tp->dev->mtu > ETH_DATA_LEN)
5578 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5579 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5580
1da177e4
LT
5581 /* Initialize invariants of the rings, we only set this
5582 * stuff once. This works because the card does not
5583 * write into the rx buffer posting rings.
5584 */
5585 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5586 struct tg3_rx_buffer_desc *rxd;
5587
21f581a5 5588 rxd = &tpr->rx_std[i];
287be12e 5589 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT
5590 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5591 rxd->opaque = (RXD_OPAQUE_RING_STD |
5592 (i << RXD_OPAQUE_INDEX_SHIFT));
5593 }
5594
1da177e4
LT
5595 /* Now allocate fresh SKBs for each rx ring. */
5596 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5597 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC
5598 printk(KERN_WARNING PFX
5599 "%s: Using a smaller RX standard ring, "
5600 "only %d out of %d buffers were allocated "
5601 "successfully.\n",
5602 tp->dev->name, i, tp->rx_pending);
5603 if (i == 0)
cf7a7298 5604 goto initfail;
32d8c572 5605 tp->rx_pending = i;
1da177e4 5606 break;
32d8c572 5607 }
1da177e4
LT
5608 }
5609
cf7a7298
MC
5610 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5611 goto done;
5612
21f581a5 5613 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5614
0f893dc6 5615 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC
5616 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5617 struct tg3_rx_buffer_desc *rxd;
5618
79ed5ac7 5619 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC
5620 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5621 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5622 RXD_FLAG_JUMBO;
5623 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5624 (i << RXD_OPAQUE_INDEX_SHIFT));
5625 }
5626
1da177e4 5627 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5628 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC
5629 -1, i) < 0) {
5630 printk(KERN_WARNING PFX
5631 "%s: Using a smaller RX jumbo ring, "
5632 "only %d out of %d buffers were "
5633 "allocated successfully.\n",
5634 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC
5635 if (i == 0)
5636 goto initfail;
32d8c572 5637 tp->rx_jumbo_pending = i;
1da177e4 5638 break;
32d8c572 5639 }
1da177e4
LT
5640 }
5641 }
cf7a7298
MC
5642
5643done:
32d8c572 5644 return 0;
cf7a7298
MC
5645
5646initfail:
21f581a5 5647 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5648 return -ENOMEM;
1da177e4
LT
5649}
5650
21f581a5
MC
5651static void tg3_rx_prodring_fini(struct tg3 *tp,
5652 struct tg3_rx_prodring_set *tpr)
1da177e4 5653{
21f581a5
MC
5654 kfree(tpr->rx_std_buffers);
5655 tpr->rx_std_buffers = NULL;
5656 kfree(tpr->rx_jmb_buffers);
5657 tpr->rx_jmb_buffers = NULL;
5658 if (tpr->rx_std) {
1da177e4 5659 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC
5660 tpr->rx_std, tpr->rx_std_mapping);
5661 tpr->rx_std = NULL;
1da177e4 5662 }
21f581a5 5663 if (tpr->rx_jmb) {
1da177e4 5664 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC
5665 tpr->rx_jmb, tpr->rx_jmb_mapping);
5666 tpr->rx_jmb = NULL;
1da177e4 5667 }
cf7a7298
MC
5668}
5669
21f581a5
MC
5670static int tg3_rx_prodring_init(struct tg3 *tp,
5671 struct tg3_rx_prodring_set *tpr)
cf7a7298 5672{
21f581a5
MC
5673 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5674 TG3_RX_RING_SIZE, GFP_KERNEL);
5675 if (!tpr->rx_std_buffers)
cf7a7298
MC
5676 return -ENOMEM;
5677
21f581a5
MC
5678 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5679 &tpr->rx_std_mapping);
5680 if (!tpr->rx_std)
cf7a7298
MC
5681 goto err_out;
5682
5683 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC
5684 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5685 TG3_RX_JUMBO_RING_SIZE,
5686 GFP_KERNEL);
5687 if (!tpr->rx_jmb_buffers)
cf7a7298
MC
5688 goto err_out;
5689
21f581a5
MC
5690 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5691 TG3_RX_JUMBO_RING_BYTES,
5692 &tpr->rx_jmb_mapping);
5693 if (!tpr->rx_jmb)
cf7a7298
MC
5694 goto err_out;
5695 }
5696
5697 return 0;
5698
5699err_out:
21f581a5 5700 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC
5701 return -ENOMEM;
5702}
5703
5704/* Free up pending packets in all rx/tx rings.
5705 *
5706 * The chip has been shut down and the driver detached from
5707 * the networking, so no interrupts or new tx packets will
5708 * end up in the driver. tp->{tx,}lock is not held and we are not
5709 * in an interrupt context and thus may sleep.
5710 */
5711static void tg3_free_rings(struct tg3 *tp)
5712{
5713 int i;
5714
5715 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5716 struct tx_ring_info *txp;
5717 struct sk_buff *skb;
5718
5719 txp = &tp->tx_buffers[i];
5720 skb = txp->skb;
5721
5722 if (skb == NULL) {
5723 i++;
5724 continue;
5725 }
5726
5727 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5728
5729 txp->skb = NULL;
5730
5731 i += skb_shinfo(skb)->nr_frags + 1;
5732
5733 dev_kfree_skb_any(skb);
5734 }
5735
21f581a5 5736 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC
5737}
5738
5739/* Initialize tx/rx rings for packet processing.
5740 *
5741 * The chip has been shut down and the driver detached from
5742 * the networking, so no interrupts or new tx packets will
5743 * end up in the driver. tp->{tx,}lock are held and thus
5744 * we may not sleep.
5745 */
5746static int tg3_init_rings(struct tg3 *tp)
5747{
5748 /* Free up all the SKBs. */
5749 tg3_free_rings(tp);
5750
5751 /* Zero out all descriptors. */
5752 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5753 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5754
21f581a5 5755 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC
5756}
5757
5758/*
5759 * Must not be invoked with interrupt sources disabled and
5760 * the hardware shutdown down.
5761 */
5762static void tg3_free_consistent(struct tg3 *tp)
5763{
898a56f8
MC
5764 struct tg3_napi *tnapi = &tp->napi[0];
5765
cf7a7298
MC
5766 kfree(tp->tx_buffers);
5767 tp->tx_buffers = NULL;
1da177e4
LT
5768 if (tp->rx_rcb) {
5769 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5770 tp->rx_rcb, tp->rx_rcb_mapping);
5771 tp->rx_rcb = NULL;
5772 }
5773 if (tp->tx_ring) {
5774 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5775 tp->tx_ring, tp->tx_desc_mapping);
5776 tp->tx_ring = NULL;
5777 }
898a56f8 5778 if (tnapi->hw_status) {
1da177e4 5779 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
898a56f8
MC
5780 tnapi->hw_status,
5781 tnapi->status_mapping);
5782 tnapi->hw_status = NULL;
1da177e4
LT
5783 }
5784 if (tp->hw_stats) {
5785 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5786 tp->hw_stats, tp->stats_mapping);
5787 tp->hw_stats = NULL;
5788 }
21f581a5 5789 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT
5790}
5791
5792/*
5793 * Must not be invoked with interrupt sources disabled and
5794 * the hardware shutdown down. Can sleep.
5795 */
5796static int tg3_alloc_consistent(struct tg3 *tp)
5797{
898a56f8
MC
5798 struct tg3_napi *tnapi = &tp->napi[0];
5799
21f581a5 5800 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT
5801 return -ENOMEM;
5802
cf7a7298
MC
5803 tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5804 TG3_TX_RING_SIZE, GFP_KERNEL);
5805 if (!tp->tx_buffers)
1da177e4
LT
5806 goto err_out;
5807
5808 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5809 &tp->rx_rcb_mapping);
5810 if (!tp->rx_rcb)
5811 goto err_out;
5812
5813 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5814 &tp->tx_desc_mapping);
5815 if (!tp->tx_ring)
5816 goto err_out;
5817
898a56f8
MC
5818 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5819 TG3_HW_STATUS_SIZE,
5820 &tnapi->status_mapping);
5821 if (!tnapi->hw_status)
1da177e4
LT
5822 goto err_out;
5823
898a56f8
MC
5824 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5825
1da177e4
LT
5826 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5827 sizeof(struct tg3_hw_stats),
5828 &tp->stats_mapping);
5829 if (!tp->hw_stats)
5830 goto err_out;
5831
1da177e4
LT
5832 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5833
5834 return 0;
5835
5836err_out:
5837 tg3_free_consistent(tp);
5838 return -ENOMEM;
5839}
5840
5841#define MAX_WAIT_CNT 1000
5842
5843/* To stop a block, clear the enable bit and poll till it
5844 * clears. tp->lock is held.
5845 */
b3b7d6be 5846static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT
5847{
5848 unsigned int i;
5849 u32 val;
5850
5851 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5852 switch (ofs) {
5853 case RCVLSC_MODE:
5854 case DMAC_MODE:
5855 case MBFREE_MODE:
5856 case BUFMGR_MODE:
5857 case MEMARB_MODE:
5858 /* We can't enable/disable these bits of the
5859 * 5705/5750, just say success.
5860 */
5861 return 0;
5862
5863 default:
5864 break;
855e1111 5865 }
1da177e4
LT
5866 }
5867
5868 val = tr32(ofs);
5869 val &= ~enable_bit;
5870 tw32_f(ofs, val);
5871
5872 for (i = 0; i < MAX_WAIT_CNT; i++) {
5873 udelay(100);
5874 val = tr32(ofs);
5875 if ((val & enable_bit) == 0)
5876 break;
5877 }
5878
b3b7d6be 5879 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT
5880 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5881 "ofs=%lx enable_bit=%x\n",
5882 ofs, enable_bit);
5883 return -ENODEV;
5884 }
5885
5886 return 0;
5887}
5888
5889/* tp->lock is held. */
b3b7d6be 5890static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT
5891{
5892 int i, err;
898a56f8 5893 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT
5894
5895 tg3_disable_ints(tp);
5896
5897 tp->rx_mode &= ~RX_MODE_ENABLE;
5898 tw32_f(MAC_RX_MODE, tp->rx_mode);
5899 udelay(10);
5900
b3b7d6be
DM
5901 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5902 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5903 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5904 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5905 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5906 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5907
5908 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5909 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5910 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5911 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5912 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5913 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5914 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT
5915
5916 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5917 tw32_f(MAC_MODE, tp->mac_mode);
5918 udelay(40);
5919
5920 tp->tx_mode &= ~TX_MODE_ENABLE;
5921 tw32_f(MAC_TX_MODE, tp->tx_mode);
5922
5923 for (i = 0; i < MAX_WAIT_CNT; i++) {
5924 udelay(100);
5925 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5926 break;
5927 }
5928 if (i >= MAX_WAIT_CNT) {
5929 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5930 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5931 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5932 err |= -ENODEV;
1da177e4
LT
5933 }
5934
e6de8ad1 5935 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM
5936 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5937 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT
5938
5939 tw32(FTQ_RESET, 0xffffffff);
5940 tw32(FTQ_RESET, 0x00000000);
5941
b3b7d6be
DM
5942 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5943 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 5944
898a56f8
MC
5945 if (tnapi->hw_status)
5946 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
1da177e4
LT
5947 if (tp->hw_stats)
5948 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5949
1da177e4
LT
5950 return err;
5951}
5952
0d3031d9
MC
5953static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5954{
5955 int i;
5956 u32 apedata;
5957
5958 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5959 if (apedata != APE_SEG_SIG_MAGIC)
5960 return;
5961
5962 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5963 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC
5964 return;
5965
5966 /* Wait for up to 1 millisecond for APE to service previous event. */
5967 for (i = 0; i < 10; i++) {
5968 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5969 return;
5970
5971 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5972
5973 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5974 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5975 event | APE_EVENT_STATUS_EVENT_PENDING);
5976
5977 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5978
5979 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5980 break;
5981
5982 udelay(100);
5983 }
5984
5985 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5986 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5987}
5988
5989static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5990{
5991 u32 event;
5992 u32 apedata;
5993
5994 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5995 return;
5996
5997 switch (kind) {
5998 case RESET_KIND_INIT:
5999 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6000 APE_HOST_SEG_SIG_MAGIC);
6001 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6002 APE_HOST_SEG_LEN_MAGIC);
6003 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6004 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6005 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6006 APE_HOST_DRIVER_ID_MAGIC);
6007 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6008 APE_HOST_BEHAV_NO_PHYLOCK);
6009
6010 event = APE_EVENT_STATUS_STATE_START;
6011 break;
6012 case RESET_KIND_SHUTDOWN:
b2aee154
MC
6013 /* With the interface we are currently using,
6014 * APE does not track driver state. Wiping
6015 * out the HOST SEGMENT SIGNATURE forces
6016 * the APE to assume OS absent status.
6017 */
6018 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6019
0d3031d9
MC
6020 event = APE_EVENT_STATUS_STATE_UNLOAD;
6021 break;
6022 case RESET_KIND_SUSPEND:
6023 event = APE_EVENT_STATUS_STATE_SUSPEND;
6024 break;
6025 default:
6026 return;
6027 }
6028
6029 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6030
6031 tg3_ape_send_event(tp, event);
6032}
6033
1da177e4
LT
6034/* tp->lock is held. */
6035static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6036{
f49639e6
DM
6037 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6038 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT
6039
6040 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6041 switch (kind) {
6042 case RESET_KIND_INIT:
6043 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6044 DRV_STATE_START);
6045 break;
6046
6047 case RESET_KIND_SHUTDOWN:
6048 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6049 DRV_STATE_UNLOAD);
6050 break;
6051
6052 case RESET_KIND_SUSPEND:
6053 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6054 DRV_STATE_SUSPEND);
6055 break;
6056
6057 default:
6058 break;
855e1111 6059 }
1da177e4 6060 }
0d3031d9
MC
6061
6062 if (kind == RESET_KIND_INIT ||
6063 kind == RESET_KIND_SUSPEND)
6064 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT
6065}
6066
6067/* tp->lock is held. */
6068static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6069{
6070 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6071 switch (kind) {
6072 case RESET_KIND_INIT:
6073 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6074 DRV_STATE_START_DONE);
6075 break;
6076
6077 case RESET_KIND_SHUTDOWN:
6078 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6079 DRV_STATE_UNLOAD_DONE);
6080 break;
6081
6082 default:
6083 break;
855e1111 6084 }
1da177e4 6085 }
0d3031d9
MC
6086
6087 if (kind == RESET_KIND_SHUTDOWN)
6088 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT
6089}
6090
6091/* tp->lock is held. */
6092static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6093{
6094 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6095 switch (kind) {
6096 case RESET_KIND_INIT:
6097 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6098 DRV_STATE_START);
6099 break;
6100
6101 case RESET_KIND_SHUTDOWN:
6102 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6103 DRV_STATE_UNLOAD);
6104 break;
6105
6106 case RESET_KIND_SUSPEND:
6107 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6108 DRV_STATE_SUSPEND);
6109 break;
6110
6111 default:
6112 break;
855e1111 6113 }
1da177e4
LT
6114 }
6115}
6116
7a6f4369
MC
6117static int tg3_poll_fw(struct tg3 *tp)
6118{
6119 int i;
6120 u32 val;
6121
b5d3772c 6122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ
6123 /* Wait up to 20ms for init done. */
6124 for (i = 0; i < 200; i++) {
b5d3772c
MC
6125 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6126 return 0;
0ccead18 6127 udelay(100);
b5d3772c
MC
6128 }
6129 return -ENODEV;
6130 }
6131
7a6f4369
MC
6132 /* Wait for firmware initialization to complete. */
6133 for (i = 0; i < 100000; i++) {
6134 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6135 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6136 break;
6137 udelay(10);
6138 }
6139
6140 /* Chip might not be fitted with firmware. Some Sun onboard
6141 * parts are configured like that. So don't signal the timeout
6142 * of the above loop as an error, but do report the lack of
6143 * running firmware once.
6144 */
6145 if (i >= 100000 &&
6146 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6147 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6148
6149 printk(KERN_INFO PFX "%s: No firmware running.\n",
6150 tp->dev->name);
6151 }
6152
6153 return 0;
6154}
6155
ee6a99b5
MC
6156/* Save PCI command register before chip reset */
6157static void tg3_save_pci_state(struct tg3 *tp)
6158{
8a6eac90 6159 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC
6160}
6161
6162/* Restore PCI state after chip reset */
6163static void tg3_restore_pci_state(struct tg3 *tp)
6164{
6165 u32 val;
6166
6167 /* Re-enable indirect register accesses. */
6168 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6169 tp->misc_host_ctrl);
6170
6171 /* Set MAX PCI retry to zero. */
6172 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6173 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6174 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6175 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC
6176 /* Allow reads and writes to the APE register and memory space. */
6177 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6178 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6179 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC
6180 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6181
8a6eac90 6182 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6183
fcb389df
MC
6184 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6185 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6186 pcie_set_readrq(tp->pdev, 4096);
6187 else {
6188 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6189 tp->pci_cacheline_sz);
6190 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6191 tp->pci_lat_timer);
6192 }
114342f2 6193 }
5f5c51e3 6194
ee6a99b5 6195 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6196 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC
6197 u16 pcix_cmd;
6198
6199 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6200 &pcix_cmd);
6201 pcix_cmd &= ~PCI_X_CMD_ERO;
6202 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6203 pcix_cmd);
6204 }
ee6a99b5
MC
6205
6206 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC
6207
6208 /* Chip reset on 5780 will reset MSI enable bit,
6209 * so need to restore it.
6210 */
6211 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6212 u16 ctrl;
6213
6214 pci_read_config_word(tp->pdev,
6215 tp->msi_cap + PCI_MSI_FLAGS,
6216 &ctrl);
6217 pci_write_config_word(tp->pdev,
6218 tp->msi_cap + PCI_MSI_FLAGS,
6219 ctrl | PCI_MSI_FLAGS_ENABLE);
6220 val = tr32(MSGINT_MODE);
6221 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6222 }
6223 }
6224}
6225
1da177e4
LT
6226static void tg3_stop_fw(struct tg3 *);
6227
6228/* tp->lock is held. */
6229static int tg3_chip_reset(struct tg3 *tp)
6230{
6231 u32 val;
1ee582d8 6232 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6233 int err;
1da177e4 6234
f49639e6
DM
6235 tg3_nvram_lock(tp);
6236
158d7abd
MC
6237 tg3_mdio_stop(tp);
6238
77b483f1
MC
6239 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6240
f49639e6
DM
6241 /* No matching tg3_nvram_unlock() after this because
6242 * chip reset below will undo the nvram lock.
6243 */
6244 tp->nvram_lock_cnt = 0;
1da177e4 6245
ee6a99b5
MC
6246 /* GRC_MISC_CFG core clock reset will clear the memory
6247 * enable bit in PCI register 4 and the MSI enable bit
6248 * on some chips, so we save relevant registers here.
6249 */
6250 tg3_save_pci_state(tp);
6251
d9ab5ad1 6252 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6253 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC
6254 tw32(GRC_FASTBOOT_PC, 0);
6255
1da177e4
LT
6256 /*
6257 * We must avoid the readl() that normally takes place.
6258 * It locks machines, causes machine checks, and other
6259 * fun things. So, temporarily disable the 5701
6260 * hardware workaround, while we do the reset.
6261 */
1ee582d8
MC
6262 write_op = tp->write32;
6263 if (write_op == tg3_write_flush_reg32)
6264 tp->write32 = tg3_write32;
1da177e4 6265
d18edcb2
MC
6266 /* Prevent the irq handler from reading or writing PCI registers
6267 * during chip reset when the memory enable bit in the PCI command
6268 * register may be cleared. The chip does not generate interrupt
6269 * at this time, but the irq handler may still be called due to irq
6270 * sharing or irqpoll.
6271 */
6272 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
898a56f8
MC
6273 if (tp->napi[0].hw_status) {
6274 tp->napi[0].hw_status->status = 0;
6275 tp->napi[0].hw_status->status_tag = 0;
b8fa2f3a 6276 }
898a56f8
MC
6277 tp->napi[0].last_tag = 0;
6278 tp->napi[0].last_irq_tag = 0;
d18edcb2
MC
6279 smp_mb();
6280 synchronize_irq(tp->pdev->irq);
6281
255ca311
MC
6282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6283 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6284 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6285 }
6286
1da177e4
LT
6287 /* do the reset */
6288 val = GRC_MISC_CFG_CORECLK_RESET;
6289
6290 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6291 if (tr32(0x7e2c) == 0x60) {
6292 tw32(0x7e2c, 0x20);
6293 }
6294 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6295 tw32(GRC_MISC_CFG, (1 << 29));
6296 val |= (1 << 29);
6297 }
6298 }
6299
b5d3772c
MC
6300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6301 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6302 tw32(GRC_VCPU_EXT_CTRL,
6303 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6304 }
6305
1da177e4
LT
6306 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6307 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6308 tw32(GRC_MISC_CFG, val);
6309
1ee582d8
MC
6310 /* restore 5701 hardware bug workaround write method */
6311 tp->write32 = write_op;
1da177e4
LT
6312
6313 /* Unfortunately, we have to delay before the PCI read back.
6314 * Some 575X chips even will not respond to a PCI cfg access
6315 * when the reset command is given to the chip.
6316 *
6317 * How do these hardware designers expect things to work
6318 * properly if the PCI write is posted for a long period
6319 * of time? It is always necessary to have some method by
6320 * which a register read back can occur to push the write
6321 * out which does the reset.
6322 *
6323 * For most tg3 variants the trick below was working.
6324 * Ho hum...
6325 */
6326 udelay(120);
6327
6328 /* Flush PCI posted writes. The normal MMIO registers
6329 * are inaccessible at this time so this is the only
6330 * way to make this reliably (actually, this is no longer
6331 * the case, see above). I tried to use indirect
6332 * register read/write but this upset some 5701 variants.
6333 */
6334 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6335
6336 udelay(120);
6337
5e7dfd0f 6338 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC
6339 u16 val16;
6340
1da177e4
LT
6341 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6342 int i;
6343 u32 cfg_val;
6344
6345 /* Wait for link training to complete. */
6346 for (i = 0; i < 5000; i++)
6347 udelay(100);
6348
6349 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6350 pci_write_config_dword(tp->pdev, 0xc4,
6351 cfg_val | (1 << 15));
6352 }
5e7dfd0f 6353
e7126997
MC
6354 /* Clear the "no snoop" and "relaxed ordering" bits. */
6355 pci_read_config_word(tp->pdev,
6356 tp->pcie_cap + PCI_EXP_DEVCTL,
6357 &val16);
6358 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6359 PCI_EXP_DEVCTL_NOSNOOP_EN);
6360 /*
6361 * Older PCIe devices only support the 128 byte
6362 * MPS setting. Enforce the restriction.
5e7dfd0f 6363 */
e7126997
MC
6364 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6365 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6366 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC
6367 pci_write_config_word(tp->pdev,
6368 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6369 val16);
5e7dfd0f
MC
6370
6371 pcie_set_readrq(tp->pdev, 4096);
6372
6373 /* Clear error status */
6374 pci_write_config_word(tp->pdev,
6375 tp->pcie_cap + PCI_EXP_DEVSTA,
6376 PCI_EXP_DEVSTA_CED |
6377 PCI_EXP_DEVSTA_NFED |
6378 PCI_EXP_DEVSTA_FED |
6379 PCI_EXP_DEVSTA_URD);
1da177e4
LT
6380 }
6381
ee6a99b5 6382 tg3_restore_pci_state(tp);
1da177e4 6383
d18edcb2
MC
6384 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6385
ee6a99b5
MC
6386 val = 0;
6387 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6388 val = tr32(MEMARB_MODE);
ee6a99b5 6389 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT
6390
6391 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6392 tg3_stop_fw(tp);
6393 tw32(0x5000, 0x400);
6394 }
6395
6396 tw32(GRC_MODE, tp->grc_mode);
6397
6398 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6399 val = tr32(0xc4);
1da177e4
LT
6400
6401 tw32(0xc4, val | (1 << 15));
6402 }
6403
6404 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6405 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6406 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6407 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6408 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6409 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6410 }
6411
6412 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6413 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6414 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC
6415 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6416 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6417 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC
6418 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6419 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6420 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6421 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6422 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT
6423 } else
6424 tw32_f(MAC_MODE, 0);
6425 udelay(40);
6426
77b483f1
MC
6427 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6428
7a6f4369
MC
6429 err = tg3_poll_fw(tp);
6430 if (err)
6431 return err;
1da177e4 6432
0a9140cf
MC
6433 tg3_mdio_start(tp);
6434
1da177e4
LT
6435 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6436 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6437 val = tr32(0x7c00);
1da177e4
LT
6438
6439 tw32(0x7c00, val | (1 << 25));
6440 }
6441
6442 /* Reprobe ASF enable state. */
6443 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6444 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6445 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6446 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6447 u32 nic_cfg;
6448
6449 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6450 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6451 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6452 tp->last_event_jiffies = jiffies;
cbf46853 6453 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT
6454 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6455 }
6456 }
6457
6458 return 0;
6459}
6460
6461/* tp->lock is held. */
6462static void tg3_stop_fw(struct tg3 *tp)
6463{
0d3031d9
MC
6464 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6465 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC
6466 /* Wait for RX cpu to ACK the previous event. */
6467 tg3_wait_for_event_ack(tp);
1da177e4
LT
6468
6469 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC
6470
6471 tg3_generate_fw_event(tp);
1da177e4 6472
7c5026aa
MC
6473 /* Wait for RX cpu to ACK this event. */
6474 tg3_wait_for_event_ack(tp);
1da177e4
LT
6475 }
6476}
6477
6478/* tp->lock is held. */
944d980e 6479static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT
6480{
6481 int err;
6482
6483 tg3_stop_fw(tp);
6484
944d980e 6485 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6486
b3b7d6be 6487 tg3_abort_hw(tp, silent);
1da177e4
LT
6488 err = tg3_chip_reset(tp);
6489
daba2a63
MC
6490 __tg3_set_mac_addr(tp, 0);
6491
944d980e
MC
6492 tg3_write_sig_legacy(tp, kind);
6493 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT
6494
6495 if (err)
6496 return err;
6497
6498 return 0;
6499}
6500
1da177e4
LT
6501#define RX_CPU_SCRATCH_BASE 0x30000
6502#define RX_CPU_SCRATCH_SIZE 0x04000
6503#define TX_CPU_SCRATCH_BASE 0x34000
6504#define TX_CPU_SCRATCH_SIZE 0x04000
6505
6506/* tp->lock is held. */
6507static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6508{
6509 int i;
6510
5d9428de
ES
6511 BUG_ON(offset == TX_CPU_BASE &&
6512 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6513
b5d3772c
MC
6514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6515 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6516
6517 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6518 return 0;
6519 }
1da177e4
LT
6520 if (offset == RX_CPU_BASE) {
6521 for (i = 0; i < 10000; i++) {
6522 tw32(offset + CPU_STATE, 0xffffffff);
6523 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6524 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6525 break;
6526 }
6527
6528 tw32(offset + CPU_STATE, 0xffffffff);
6529 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6530 udelay(10);
6531 } else {
6532 for (i = 0; i < 10000; i++) {
6533 tw32(offset + CPU_STATE, 0xffffffff);
6534 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6535 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6536 break;
6537 }
6538 }
6539
6540 if (i >= 10000) {
6541 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6542 "and %s CPU\n",
6543 tp->dev->name,
6544 (offset == RX_CPU_BASE ? "RX" : "TX"));
6545 return -ENODEV;
6546 }
ec41c7df
MC
6547
6548 /* Clear firmware's nvram arbitration. */
6549 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6550 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT
6551 return 0;
6552}
6553
6554struct fw_info {
077f849d
JSR
6555 unsigned int fw_base;
6556 unsigned int fw_len;
6557 const __be32 *fw_data;
1da177e4
LT
6558};
6559
6560/* tp->lock is held. */
6561static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6562 int cpu_scratch_size, struct fw_info *info)
6563{
ec41c7df 6564 int err, lock_err, i;
1da177e4
LT
6565 void (*write_op)(struct tg3 *, u32, u32);
6566
6567 if (cpu_base == TX_CPU_BASE &&
6568 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6569 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6570 "TX cpu firmware on %s which is 5705.\n",
6571 tp->dev->name);
6572 return -EINVAL;
6573 }
6574
6575 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6576 write_op = tg3_write_mem;
6577 else
6578 write_op = tg3_write_indirect_reg32;
6579
1b628151
MC
6580 /* It is possible that bootcode is still loading at this point.
6581 * Get the nvram lock first before halting the cpu.
6582 */
ec41c7df 6583 lock_err = tg3_nvram_lock(tp);
1da177e4 6584 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC
6585 if (!lock_err)
6586 tg3_nvram_unlock(tp);
1da177e4
LT
6587 if (err)
6588 goto out;
6589
6590 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6591 write_op(tp, cpu_scratch_base + i, 0);
6592 tw32(cpu_base + CPU_STATE, 0xffffffff);
6593 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6594 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6595 write_op(tp, (cpu_scratch_base +
077f849d 6596 (info->fw_base & 0xffff) +
1da177e4 6597 (i * sizeof(u32))),
077f849d 6598 be32_to_cpu(info->fw_data[i]));
1da177e4
LT
6599
6600 err = 0;
6601
6602out:
1da177e4
LT
6603 return err;
6604}
6605
6606/* tp->lock is held. */
6607static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6608{
6609 struct fw_info info;
077f849d 6610 const __be32 *fw_data;
1da177e4
LT
6611 int err, i;
6612
077f849d
JSR
6613 fw_data = (void *)tp->fw->data;
6614
6615 /* Firmware blob starts with version numbers, followed by
6616 start address and length. We are setting complete length.
6617 length = end_address_of_bss - start_address_of_text.
6618 Remainder is the blob to be loaded contiguously
6619 from start address. */
6620
6621 info.fw_base = be32_to_cpu(fw_data[1]);
6622 info.fw_len = tp->fw->size - 12;
6623 info.fw_data = &fw_data[3];
1da177e4
LT
6624
6625 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6626 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6627 &info);
6628 if (err)
6629 return err;
6630
6631 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6632 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6633 &info);
6634 if (err)
6635 return err;
6636
6637 /* Now startup only the RX cpu. */
6638 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6639 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT
6640
6641 for (i = 0; i < 5; i++) {
077f849d 6642 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT
6643 break;
6644 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6645 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6646 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT
6647 udelay(1000);
6648 }
6649 if (i >= 5) {
6650 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6651 "to set RX CPU PC, is %08x should be %08x\n",
6652 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6653 info.fw_base);
1da177e4
LT
6654 return -ENODEV;
6655 }
6656 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6657 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6658
6659 return 0;
6660}
6661
1da177e4 6662/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT
6663
6664/* tp->lock is held. */
6665static int tg3_load_tso_firmware(struct tg3 *tp)
6666{
6667 struct fw_info info;
077f849d 6668 const __be32 *fw_data;
1da177e4
LT
6669 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6670 int err, i;
6671
6672 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6673 return 0;
6674
077f849d
JSR
6675 fw_data = (void *)tp->fw->data;
6676
6677 /* Firmware blob starts with version numbers, followed by
6678 start address and length. We are setting complete length.
6679 length = end_address_of_bss - start_address_of_text.
6680 Remainder is the blob to be loaded contiguously
6681 from start address. */
6682
6683 info.fw_base = be32_to_cpu(fw_data[1]);
6684 cpu_scratch_size = tp->fw_len;
6685 info.fw_len = tp->fw->size - 12;
6686 info.fw_data = &fw_data[3];
6687
1da177e4 6688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT
6689 cpu_base = RX_CPU_BASE;
6690 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6691 } else {
1da177e4
LT
6692 cpu_base = TX_CPU_BASE;
6693 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6694 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6695 }
6696
6697 err = tg3_load_firmware_cpu(tp, cpu_base,
6698 cpu_scratch_base, cpu_scratch_size,
6699 &info);
6700 if (err)
6701 return err;
6702
6703 /* Now startup the cpu. */
6704 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6705 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT
6706
6707 for (i = 0; i < 5; i++) {
077f849d 6708 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT
6709 break;
6710 tw32(cpu_base + CPU_STATE, 0xffffffff);
6711 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6712 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT
6713 udelay(1000);
6714 }
6715 if (i >= 5) {
6716 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6717 "to set CPU PC, is %08x should be %08x\n",
6718 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6719 info.fw_base);
1da177e4
LT
6720 return -ENODEV;
6721 }
6722 tw32(cpu_base + CPU_STATE, 0xffffffff);
6723 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6724 return 0;
6725}
6726
1da177e4 6727
1da177e4
LT
6728static int tg3_set_mac_addr(struct net_device *dev, void *p)
6729{
6730 struct tg3 *tp = netdev_priv(dev);
6731 struct sockaddr *addr = p;
986e0aeb 6732 int err = 0, skip_mac_1 = 0;
1da177e4 6733
f9804ddb
MC
6734 if (!is_valid_ether_addr(addr->sa_data))
6735 return -EINVAL;
6736
1da177e4
LT
6737 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6738
e75f7c90
MC
6739 if (!netif_running(dev))
6740 return 0;
6741
58712ef9 6742 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6743 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6744
986e0aeb
MC
6745 addr0_high = tr32(MAC_ADDR_0_HIGH);
6746 addr0_low = tr32(MAC_ADDR_0_LOW);
6747 addr1_high = tr32(MAC_ADDR_1_HIGH);
6748 addr1_low = tr32(MAC_ADDR_1_LOW);
6749
6750 /* Skip MAC addr 1 if ASF is using it. */
6751 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6752 !(addr1_high == 0 && addr1_low == 0))
6753 skip_mac_1 = 1;
58712ef9 6754 }
986e0aeb
MC
6755 spin_lock_bh(&tp->lock);
6756 __tg3_set_mac_addr(tp, skip_mac_1);
6757 spin_unlock_bh(&tp->lock);
1da177e4 6758
b9ec6c1b 6759 return err;
1da177e4
LT
6760}
6761
6762/* tp->lock is held. */
6763static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6764 dma_addr_t mapping, u32 maxlen_flags,
6765 u32 nic_addr)
6766{
6767 tg3_write_mem(tp,
6768 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6769 ((u64) mapping >> 32));
6770 tg3_write_mem(tp,
6771 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6772 ((u64) mapping & 0xffffffff));
6773 tg3_write_mem(tp,
6774 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6775 maxlen_flags);
6776
6777 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6778 tg3_write_mem(tp,
6779 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6780 nic_addr);
6781}
6782
6783static void __tg3_set_rx_mode(struct net_device *);
d244c892 6784static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM
6785{
6786 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6787 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6788 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6789 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6790 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6791 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6792 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6793 }
6794 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6795 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6796 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6797 u32 val = ec->stats_block_coalesce_usecs;
6798
6799 if (!netif_carrier_ok(tp->dev))
6800 val = 0;
6801
6802 tw32(HOSTCC_STAT_COAL_TICKS, val);
6803 }
6804}
1da177e4
LT
6805
6806/* tp->lock is held. */
8e7a22e3 6807static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT
6808{
6809 u32 val, rdmac_mode;
6810 int i, err, limit;
21f581a5 6811 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT
6812
6813 tg3_disable_ints(tp);
6814
6815 tg3_stop_fw(tp);
6816
6817 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6818
6819 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6820 tg3_abort_hw(tp, 1);
1da177e4
LT
6821 }
6822
dd477003
MC
6823 if (reset_phy &&
6824 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC
6825 tg3_phy_reset(tp);
6826
1da177e4
LT
6827 err = tg3_chip_reset(tp);
6828 if (err)
6829 return err;
6830
6831 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6832
bcb37f6c 6833 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC
6834 val = tr32(TG3_CPMU_CTRL);
6835 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6836 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC
6837
6838 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6839 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6840 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6841 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6842
6843 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6844 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6845 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6846 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6847
6848 val = tr32(TG3_CPMU_HST_ACC);
6849 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6850 val |= CPMU_HST_ACC_MACCLK_6_25;
6851 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC
6852 }
6853
33466d93
MC
6854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6855 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6856 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6857 PCIE_PWR_MGMT_L1_THRESH_4MS;
6858 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC
6859
6860 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6861 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6862
6863 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC
6864 }
6865
255ca311
MC
6866 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6867 val = tr32(TG3_PCIE_LNKCTL);
6868 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6869 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6870 else
6871 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6872 tw32(TG3_PCIE_LNKCTL, val);
6873 }
6874
1da177e4
LT
6875 /* This works around an issue with Athlon chipsets on
6876 * B3 tigon3 silicon. This bit has no effect on any
6877 * other revision. But do not set this on PCI Express
795d01c5 6878 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6879 */
795d01c5
MC
6880 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6881 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6882 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6883 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6884 }
1da177e4
LT
6885
6886 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6887 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6888 val = tr32(TG3PCI_PCISTATE);
6889 val |= PCISTATE_RETRY_SAME_DMA;
6890 tw32(TG3PCI_PCISTATE, val);
6891 }
6892
0d3031d9
MC
6893 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6894 /* Allow reads and writes to the
6895 * APE register and memory space.
6896 */
6897 val = tr32(TG3PCI_PCISTATE);
6898 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6899 PCISTATE_ALLOW_APE_SHMEM_WR;
6900 tw32(TG3PCI_PCISTATE, val);
6901 }
6902
1da177e4
LT
6903 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6904 /* Enable some hw fixes. */
6905 val = tr32(TG3PCI_MSI_DATA);
6906 val |= (1 << 26) | (1 << 28) | (1 << 29);
6907 tw32(TG3PCI_MSI_DATA, val);
6908 }
6909
6910 /* Descriptor ring init may make accesses to the
6911 * NIC SRAM area to setup the TX descriptors, so we
6912 * can only do this after the hardware has been
6913 * successfully reset.
6914 */
32d8c572
MC
6915 err = tg3_init_rings(tp);
6916 if (err)
6917 return err;
1da177e4 6918
9936bcf6 6919 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6920 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC
6921 /* This value is determined during the probe time DMA
6922 * engine test, tg3_test_dma.
6923 */
6924 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6925 }
1da177e4
LT
6926
6927 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6928 GRC_MODE_4X_NIC_SEND_RINGS |
6929 GRC_MODE_NO_TX_PHDR_CSUM |
6930 GRC_MODE_NO_RX_PHDR_CSUM);
6931 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC
6932
6933 /* Pseudo-header checksum is done by hardware logic and not
6934 * the offload processers, so make the chip do the pseudo-
6935 * header checksums on receive. For transmit it is more
6936 * convenient to do the pseudo-header checksum in software
6937 * as Linux does that on transmit for us in all cases.
6938 */
6939 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT
6940
6941 tw32(GRC_MODE,
6942 tp->grc_mode |
6943 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6944
6945 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6946 val = tr32(GRC_MISC_CFG);
6947 val &= ~0xff;
6948 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6949 tw32(GRC_MISC_CFG, val);
6950
6951 /* Initialize MBUF/DESC pool. */
cbf46853 6952 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT
6953 /* Do nothing. */
6954 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6955 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6957 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6958 else
6959 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6960 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6961 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6962 }
1da177e4
LT
6963 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6964 int fw_len;
6965
077f849d 6966 fw_len = tp->fw_len;
1da177e4
LT
6967 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6968 tw32(BUFMGR_MB_POOL_ADDR,
6969 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6970 tw32(BUFMGR_MB_POOL_SIZE,
6971 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6972 }
1da177e4 6973
0f893dc6 6974 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT
6975 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6976 tp->bufmgr_config.mbuf_read_dma_low_water);
6977 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6978 tp->bufmgr_config.mbuf_mac_rx_low_water);
6979 tw32(BUFMGR_MB_HIGH_WATER,
6980 tp->bufmgr_config.mbuf_high_water);
6981 } else {
6982 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6983 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6984 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6985 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6986 tw32(BUFMGR_MB_HIGH_WATER,
6987 tp->bufmgr_config.mbuf_high_water_jumbo);
6988 }
6989 tw32(BUFMGR_DMA_LOW_WATER,
6990 tp->bufmgr_config.dma_low_water);
6991 tw32(BUFMGR_DMA_HIGH_WATER,
6992 tp->bufmgr_config.dma_high_water);
6993
6994 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6995 for (i = 0; i < 2000; i++) {
6996 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6997 break;
6998 udelay(10);
6999 }
7000 if (i >= 2000) {
7001 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7002 tp->dev->name);
7003 return -ENODEV;
7004 }
7005
7006 /* Setup replenish threshold. */
f92905de
MC
7007 val = tp->rx_pending / 8;
7008 if (val == 0)
7009 val = 1;
7010 else if (val > tp->rx_std_max_post)
7011 val = tp->rx_std_max_post;
b5d3772c
MC
7012 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7013 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7014 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7015
7016 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7017 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7018 }
f92905de
MC
7019
7020 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT
7021
7022 /* Initialize TG3_BDINFO's at:
7023 * RCVDBDI_STD_BD: standard eth size rx ring
7024 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7025 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7026 *
7027 * like so:
7028 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7029 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7030 * ring attribute flags
7031 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7032 *
7033 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7034 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7035 *
7036 * The size of each ring is fixed in the firmware, but the location is
7037 * configurable.
7038 */
7039 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7040 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7041 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7042 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT
7043 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7044 NIC_SRAM_RX_BUFFER_DESC);
7045
fdb72b38
MC
7046 /* Disable the mini ring */
7047 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT
7048 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7049 BDINFO_FLAGS_DISABLED);
7050
fdb72b38
MC
7051 /* Program the jumbo buffer descriptor ring control
7052 * blocks on those devices that have them.
7053 */
8f666b07 7054 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7055 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT
7056 /* Setup replenish threshold. */
7057 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7058
0f893dc6 7059 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7060 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7061 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7062 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7063 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7064 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC
7065 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7066 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT
7067 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7068 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7069 } else {
7070 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7071 BDINFO_FLAGS_DISABLED);
7072 }
7073
fdb72b38
MC
7074 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7075 } else
7076 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7077
7078 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4
LT
7079
7080 /* There is only one send ring on 5705/5750, no need to explicitly
7081 * disable the others.
7082 */
7083 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7084 /* Clear out send RCB ring in SRAM. */
7085 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7086 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7087 BDINFO_FLAGS_DISABLED);
7088 }
7089
7090 tp->tx_prod = 0;
7091 tp->tx_cons = 0;
7092 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7093 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7094
7095 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7096 tp->tx_desc_mapping,
7097 (TG3_TX_RING_SIZE <<
7098 BDINFO_FLAGS_MAXLEN_SHIFT),
7099 NIC_SRAM_TX_BUFFER_DESC);
7100
7101 /* There is only one receive return ring on 5705/5750, no need
7102 * to explicitly disable the others.
7103 */
7104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7105 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7106 i += TG3_BDINFO_SIZE) {
7107 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7108 BDINFO_FLAGS_DISABLED);
7109 }
7110 }
7111
7112 tp->rx_rcb_ptr = 0;
7113 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7114
7115 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7116 tp->rx_rcb_mapping,
7117 (TG3_RX_RCB_RING_SIZE(tp) <<
7118 BDINFO_FLAGS_MAXLEN_SHIFT),
7119 0);
7120
21f581a5 7121 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7122 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7123 tpr->rx_std_ptr);
1da177e4 7124
21f581a5
MC
7125 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7126 tp->rx_jumbo_pending : 0;
1da177e4 7127 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7128 tpr->rx_jmb_ptr);
1da177e4
LT
7129
7130 /* Initialize MAC address and backoff seed. */
986e0aeb 7131 __tg3_set_mac_addr(tp, 0);
1da177e4
LT
7132
7133 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC
7134 tw32(MAC_RX_MTU_SIZE,
7135 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT
7136
7137 /* The slot time is changed by tg3_setup_phy if we
7138 * run at gigabit with half duplex.
7139 */
7140 tw32(MAC_TX_LENGTHS,
7141 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7142 (6 << TX_LENGTHS_IPG_SHIFT) |
7143 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7144
7145 /* Receive rules. */
7146 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7147 tw32(RCVLPC_CONFIG, 0x0181);
7148
7149 /* Calculate RDMAC_MODE setting early, we need it to determine
7150 * the RCVLPC_STATE_ENABLE mask.
7151 */
7152 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7153 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7154 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7155 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7156 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7157
57e6983c 7158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC
7159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC
7161 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7162 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7163 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7164
85e94ced
MC
7165 /* If statement applies to 5705 and 5750 PCI devices only */
7166 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7167 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7168 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7169 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT
7171 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7172 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7173 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7174 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7175 }
7176 }
7177
85e94ced
MC
7178 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7179 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7180
1da177e4 7181 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC
7182 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7183
7184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7186 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT
7187
7188 /* Receive/send statistics. */
1661394e
MC
7189 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7190 val = tr32(RCVLPC_STATS_ENABLE);
7191 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7192 tw32(RCVLPC_STATS_ENABLE, val);
7193 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7194 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT
7195 val = tr32(RCVLPC_STATS_ENABLE);
7196 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7197 tw32(RCVLPC_STATS_ENABLE, val);
7198 } else {
7199 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7200 }
7201 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7202 tw32(SNDDATAI_STATSENAB, 0xffffff);
7203 tw32(SNDDATAI_STATSCTRL,
7204 (SNDDATAI_SCTRL_ENABLE |
7205 SNDDATAI_SCTRL_FASTUPD));
7206
7207 /* Setup host coalescing engine. */
7208 tw32(HOSTCC_MODE, 0);
7209 for (i = 0; i < 2000; i++) {
7210 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7211 break;
7212 udelay(10);
7213 }
7214
d244c892 7215 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT
7216
7217 /* set status block DMA address */
7218 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
898a56f8 7219 ((u64) tp->napi[0].status_mapping >> 32));
1da177e4 7220 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
898a56f8 7221 ((u64) tp->napi[0].status_mapping & 0xffffffff));
1da177e4
LT
7222
7223 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7224 /* Status/statistics block address. See tg3_timer,
7225 * the tg3_periodic_fetch_stats call there, and
7226 * tg3_get_stats to see how this works for 5705/5750 chips.
7227 */
1da177e4
LT
7228 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7229 ((u64) tp->stats_mapping >> 32));
7230 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7231 ((u64) tp->stats_mapping & 0xffffffff));
7232 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7233 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7234 }
7235
7236 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7237
7238 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7239 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7240 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7241 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7242
7243 /* Clear statistics/status block in chip, and status block in ram. */
7244 for (i = NIC_SRAM_STATS_BLK;
7245 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7246 i += sizeof(u32)) {
7247 tg3_write_mem(tp, i, 0);
7248 udelay(40);
7249 }
898a56f8 7250 memset(tp->napi[0].hw_status, 0, TG3_HW_STATUS_SIZE);
1da177e4 7251
c94e3941
MC
7252 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7253 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7254 /* reset to prevent losing 1st rx packet intermittently */
7255 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7256 udelay(10);
7257 }
7258
3bda1258
MC
7259 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7260 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7261 else
7262 tp->mac_mode = 0;
7263 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7264 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC
7265 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7266 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7267 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7268 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT
7269 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7270 udelay(40);
7271
314fba34 7272 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7273 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC
7274 * register to preserve the GPIO settings for LOMs. The GPIOs,
7275 * whether used as inputs or outputs, are set by boot code after
7276 * reset.
7277 */
9d26e213 7278 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC
7279 u32 gpio_mask;
7280
9d26e213
MC
7281 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7282 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7283 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC
7284
7285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7286 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7287 GRC_LCLCTRL_GPIO_OUTPUT3;
7288
af36e6b6
MC
7289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7290 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7291
aaf84465 7292 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC
7293 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7294
7295 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC
7296 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7297 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7298 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7299 }
1da177e4
LT
7300 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7301 udelay(100);
7302
898a56f8 7303 tw32_mailbox_f(tp->napi[0].int_mbox, 0);
1da177e4
LT
7304
7305 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7306 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7307 udelay(40);
7308 }
7309
7310 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7311 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7312 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7313 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7314 WDMAC_MODE_LNGREAD_ENAB);
7315
85e94ced
MC
7316 /* If statement applies to 5705 and 5750 PCI devices only */
7317 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7318 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7320 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT
7321 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7322 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7323 /* nothing */
7324 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7325 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7326 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7327 val |= WDMAC_MODE_RX_ACCEL;
7328 }
7329 }
7330
d9ab5ad1 7331 /* Enable host coalescing bug fix */
321d32a0 7332 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7333 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7334
1da177e4
LT
7335 tw32_f(WDMAC_MODE, val);
7336 udelay(40);
7337
9974a356
MC
7338 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7339 u16 pcix_cmd;
7340
7341 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7342 &pcix_cmd);
1da177e4 7343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC
7344 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7345 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7346 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC
7347 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7348 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7349 }
9974a356
MC
7350 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7351 pcix_cmd);
1da177e4
LT
7352 }
7353
7354 tw32_f(RDMAC_MODE, rdmac_mode);
7355 udelay(40);
7356
7357 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7358 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7359 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC
7360
7361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7362 tw32(SNDDATAC_MODE,
7363 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7364 else
7365 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7366
1da177e4
LT
7367 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7368 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7369 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7370 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT
7371 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7372 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT
7373 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7374 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7375
7376 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7377 err = tg3_load_5701_a0_firmware_fix(tp);
7378 if (err)
7379 return err;
7380 }
7381
1da177e4
LT
7382 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7383 err = tg3_load_tso_firmware(tp);
7384 if (err)
7385 return err;
7386 }
1da177e4
LT
7387
7388 tp->tx_mode = TX_MODE_ENABLE;
7389 tw32_f(MAC_TX_MODE, tp->tx_mode);
7390 udelay(100);
7391
7392 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7393 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC
7394 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7395
1da177e4
LT
7396 tw32_f(MAC_RX_MODE, tp->rx_mode);
7397 udelay(10);
7398
1da177e4
LT
7399 tw32(MAC_LED_CTRL, tp->led_ctrl);
7400
7401 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7402 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT
7403 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7404 udelay(10);
7405 }
7406 tw32_f(MAC_RX_MODE, tp->rx_mode);
7407 udelay(10);
7408
7409 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7410 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7411 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7412 /* Set drive transmission level to 1.2V */
7413 /* only if the signal pre-emphasis bit is not set */
7414 val = tr32(MAC_SERDES_CFG);
7415 val &= 0xfffff000;
7416 val |= 0x880;
7417 tw32(MAC_SERDES_CFG, val);
7418 }
7419 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7420 tw32(MAC_SERDES_CFG, 0x616000);
7421 }
7422
7423 /* Prevent chip from dropping frames when flow control
7424 * is enabled.
7425 */
7426 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7427
7428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7429 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7430 /* Use hardware link auto-negotiation */
7431 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7432 }
7433
d4d2c558
MC
7434 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7435 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7436 u32 tmp;
7437
7438 tmp = tr32(SERDES_RX_CTRL);
7439 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7440 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7441 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7442 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7443 }
7444
dd477003
MC
7445 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7446 if (tp->link_config.phy_is_low_power) {
7447 tp->link_config.phy_is_low_power = 0;
7448 tp->link_config.speed = tp->link_config.orig_speed;
7449 tp->link_config.duplex = tp->link_config.orig_duplex;
7450 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7451 }
1da177e4 7452
dd477003
MC
7453 err = tg3_setup_phy(tp, 0);
7454 if (err)
7455 return err;
1da177e4 7456
dd477003 7457 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7458 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC
7459 u32 tmp;
7460
7461 /* Clear CRC stats. */
7462 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7463 tg3_writephy(tp, MII_TG3_TEST1,
7464 tmp | MII_TG3_TEST1_CRC_EN);
7465 tg3_readphy(tp, 0x14, &tmp);
7466 }
1da177e4
LT
7467 }
7468 }
7469
7470 __tg3_set_rx_mode(tp->dev);
7471
7472 /* Initialize receive rules. */
7473 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7474 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7475 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7476 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7477
4cf78e4f 7478 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7479 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT
7480 limit = 8;
7481 else
7482 limit = 16;
7483 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7484 limit -= 4;
7485 switch (limit) {
7486 case 16:
7487 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7488 case 15:
7489 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7490 case 14:
7491 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7492 case 13:
7493 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7494 case 12:
7495 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7496 case 11:
7497 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7498 case 10:
7499 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7500 case 9:
7501 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7502 case 8:
7503 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7504 case 7:
7505 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7506 case 6:
7507 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7508 case 5:
7509 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7510 case 4:
7511 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7512 case 3:
7513 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7514 case 2:
7515 case 1:
7516
7517 default:
7518 break;
855e1111 7519 }
1da177e4 7520
9ce768ea
MC
7521 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7522 /* Write our heartbeat update interval to APE. */
7523 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7524 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7525
1da177e4
LT
7526 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7527
1da177e4
LT
7528 return 0;
7529}
7530
7531/* Called at device open time to get the chip ready for
7532 * packet processing. Invoked with tp->lock held.
7533 */
8e7a22e3 7534static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7535{
1da177e4
LT
7536 tg3_switch_clocks(tp);
7537
7538 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7539
2f751b67 7540 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT
7541}
7542
7543#define TG3_STAT_ADD32(PSTAT, REG) \
7544do { u32 __val = tr32(REG); \
7545 (PSTAT)->low += __val; \
7546 if ((PSTAT)->low < __val) \
7547 (PSTAT)->high += 1; \
7548} while (0)
7549
7550static void tg3_periodic_fetch_stats(struct tg3 *tp)
7551{
7552 struct tg3_hw_stats *sp = tp->hw_stats;
7553
7554 if (!netif_carrier_ok(tp->dev))
7555 return;
7556
7557 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7558 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7559 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7560 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7561 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7562 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7563 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7564 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7565 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7566 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7567 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7568 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7569 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7570
7571 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7572 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7573 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7574 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7575 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7576 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7577 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7578 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7579 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7580 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7581 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7582 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7583 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7584 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC
7585
7586 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7587 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7588 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT
7589}
7590
7591static void tg3_timer(unsigned long __opaque)
7592{
7593 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7594
f475f163
MC
7595 if (tp->irq_sync)
7596 goto restart_timer;
7597
f47c11ee 7598 spin_lock(&tp->lock);
1da177e4 7599
fac9b83e
DM
7600 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7601 /* All of this garbage is because when using non-tagged
7602 * IRQ status the mailbox/status_block protocol the chip
7603 * uses with the cpu is race prone.
7604 */
898a56f8 7605 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM
7606 tw32(GRC_LOCAL_CTRL,
7607 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7608 } else {
7609 tw32(HOSTCC_MODE, tp->coalesce_mode |
7610 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7611 }
1da177e4 7612
fac9b83e
DM
7613 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7614 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7615 spin_unlock(&tp->lock);
fac9b83e
DM
7616 schedule_work(&tp->reset_task);
7617 return;
7618 }
1da177e4
LT
7619 }
7620
1da177e4
LT
7621 /* This part only runs once per second. */
7622 if (!--tp->timer_counter) {
fac9b83e
DM
7623 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7624 tg3_periodic_fetch_stats(tp);
7625
1da177e4
LT
7626 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7627 u32 mac_stat;
7628 int phy_event;
7629
7630 mac_stat = tr32(MAC_STATUS);
7631
7632 phy_event = 0;
7633 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7634 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7635 phy_event = 1;
7636 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7637 phy_event = 1;
7638
7639 if (phy_event)
7640 tg3_setup_phy(tp, 0);
7641 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7642 u32 mac_stat = tr32(MAC_STATUS);
7643 int need_setup = 0;
7644
7645 if (netif_carrier_ok(tp->dev) &&
7646 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7647 need_setup = 1;
7648 }
7649 if (! netif_carrier_ok(tp->dev) &&
7650 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7651 MAC_STATUS_SIGNAL_DET))) {
7652 need_setup = 1;
7653 }
7654 if (need_setup) {
3d3ebe74
MC
7655 if (!tp->serdes_counter) {
7656 tw32_f(MAC_MODE,
7657 (tp->mac_mode &
7658 ~MAC_MODE_PORT_MODE_MASK));
7659 udelay(40);
7660 tw32_f(MAC_MODE, tp->mac_mode);
7661 udelay(40);
7662 }
1da177e4
LT
7663 tg3_setup_phy(tp, 0);
7664 }
747e8f8b
MC
7665 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7666 tg3_serdes_parallel_detect(tp);
1da177e4
LT
7667
7668 tp->timer_counter = tp->timer_multiplier;
7669 }
7670
130b8e4d
MC
7671 /* Heartbeat is only sent once every 2 seconds.
7672 *
7673 * The heartbeat is to tell the ASF firmware that the host
7674 * driver is still alive. In the event that the OS crashes,
7675 * ASF needs to reset the hardware to free up the FIFO space
7676 * that may be filled with rx packets destined for the host.
7677 * If the FIFO is full, ASF will no longer function properly.
7678 *
7679 * Unintended resets have been reported on real time kernels
7680 * where the timer doesn't run on time. Netpoll will also have
7681 * same problem.
7682 *
7683 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7684 * to check the ring condition when the heartbeat is expiring
7685 * before doing the reset. This will prevent most unintended
7686 * resets.
7687 */
1da177e4 7688 if (!--tp->asf_counter) {
bc7959b2
MC
7689 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7690 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC
7691 tg3_wait_for_event_ack(tp);
7692
bbadf503 7693 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7694 FWCMD_NICDRV_ALIVE3);
bbadf503 7695 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7696 /* 5 seconds timeout */
bbadf503 7697 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC
7698
7699 tg3_generate_fw_event(tp);
1da177e4
LT
7700 }
7701 tp->asf_counter = tp->asf_multiplier;
7702 }
7703
f47c11ee 7704 spin_unlock(&tp->lock);
1da177e4 7705
f475f163 7706restart_timer:
1da177e4
LT
7707 tp->timer.expires = jiffies + tp->timer_offset;
7708 add_timer(&tp->timer);
7709}
7710
81789ef5 7711static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7712{
7d12e780 7713 irq_handler_t fn;
fcfa0a32 7714 unsigned long flags;
09943a18 7715 char *name = tp->dev->name;
fcfa0a32
MC
7716
7717 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7718 fn = tg3_msi;
7719 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7720 fn = tg3_msi_1shot;
1fb9df5d 7721 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC
7722 } else {
7723 fn = tg3_interrupt;
7724 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7725 fn = tg3_interrupt_tagged;
1fb9df5d 7726 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 7727 }
09943a18 7728 return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]);
fcfa0a32
MC
7729}
7730
7938109f
MC
7731static int tg3_test_interrupt(struct tg3 *tp)
7732{
09943a18 7733 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 7734 struct net_device *dev = tp->dev;
b16250e3 7735 int err, i, intr_ok = 0;
7938109f 7736
d4bc3927
MC
7737 if (!netif_running(dev))
7738 return -ENODEV;
7739
7938109f
MC
7740 tg3_disable_ints(tp);
7741
09943a18 7742 free_irq(tp->pdev->irq, tnapi);
7938109f
MC
7743
7744 err = request_irq(tp->pdev->irq, tg3_test_isr,
09943a18 7745 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC
7746 if (err)
7747 return err;
7748
898a56f8 7749 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC
7750 tg3_enable_ints(tp);
7751
7752 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7753 HOSTCC_MODE_NOW);
7754
7755 for (i = 0; i < 5; i++) {
b16250e3
MC
7756 u32 int_mbox, misc_host_ctrl;
7757
898a56f8 7758 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC
7759 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7760
7761 if ((int_mbox != 0) ||
7762 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7763 intr_ok = 1;
7938109f 7764 break;
b16250e3
MC
7765 }
7766
7938109f
MC
7767 msleep(10);
7768 }
7769
7770 tg3_disable_ints(tp);
7771
09943a18 7772 free_irq(tp->pdev->irq, tnapi);
6aa20a22 7773
fcfa0a32 7774 err = tg3_request_irq(tp);
7938109f
MC
7775
7776 if (err)
7777 return err;
7778
b16250e3 7779 if (intr_ok)
7938109f
MC
7780 return 0;
7781
7782 return -EIO;
7783}
7784
7785/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7786 * successfully restored
7787 */
7788static int tg3_test_msi(struct tg3 *tp)
7789{
7938109f
MC
7790 int err;
7791 u16 pci_cmd;
7792
7793 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7794 return 0;
7795
7796 /* Turn off SERR reporting in case MSI terminates with Master
7797 * Abort.
7798 */
7799 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7800 pci_write_config_word(tp->pdev, PCI_COMMAND,
7801 pci_cmd & ~PCI_COMMAND_SERR);
7802
7803 err = tg3_test_interrupt(tp);
7804
7805 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7806
7807 if (!err)
7808 return 0;
7809
7810 /* other failures */
7811 if (err != -EIO)
7812 return err;
7813
7814 /* MSI test failed, go back to INTx mode */
7815 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7816 "switching to INTx mode. Please report this failure to "
7817 "the PCI maintainer and include system chipset information.\n",
7818 tp->dev->name);
7819
09943a18
MC
7820 free_irq(tp->pdev->irq, &tp->napi[0]);
7821
7938109f
MC
7822 pci_disable_msi(tp->pdev);
7823
7824 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7825
fcfa0a32 7826 err = tg3_request_irq(tp);
7938109f
MC
7827 if (err)
7828 return err;
7829
7830 /* Need to reset the chip because the MSI cycle may have terminated
7831 * with Master Abort.
7832 */
f47c11ee 7833 tg3_full_lock(tp, 1);
7938109f 7834
944d980e 7835 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7836 err = tg3_init_hw(tp, 1);
7938109f 7837
f47c11ee 7838 tg3_full_unlock(tp);
7938109f
MC
7839
7840 if (err)
09943a18 7841 free_irq(tp->pdev->irq, &tp->napi[0]);
7938109f
MC
7842
7843 return err;
7844}
7845
9e9fd12d
MC
7846static int tg3_request_firmware(struct tg3 *tp)
7847{
7848 const __be32 *fw_data;
7849
7850 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7851 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7852 tp->dev->name, tp->fw_needed);
7853 return -ENOENT;
7854 }
7855
7856 fw_data = (void *)tp->fw->data;
7857
7858 /* Firmware blob starts with version numbers, followed by
7859 * start address and _full_ length including BSS sections
7860 * (which must be longer than the actual data, of course
7861 */
7862
7863 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7864 if (tp->fw_len < (tp->fw->size - 12)) {
7865 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7866 tp->dev->name, tp->fw_len, tp->fw_needed);
7867 release_firmware(tp->fw);
7868 tp->fw = NULL;
7869 return -EINVAL;
7870 }
7871
7872 /* We no longer need firmware; we have it. */
7873 tp->fw_needed = NULL;
7874 return 0;
7875}
7876
07b0173c
MC
7877static void tg3_ints_init(struct tg3 *tp)
7878{
7879 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7880 /* All MSI supporting chips should support tagged
7881 * status. Assert that this is the case.
7882 */
7883 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7884 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7885 "Not using MSI.\n", tp->dev->name);
7886 } else if (pci_enable_msi(tp->pdev) == 0) {
7887 u32 msi_mode;
7888
7889 msi_mode = tr32(MSGINT_MODE);
7890 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7891 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7892 }
7893 }
7894}
7895
7896static void tg3_ints_fini(struct tg3 *tp)
7897{
7898 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7899 pci_disable_msi(tp->pdev);
7900 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7901 }
7902}
7903
1da177e4
LT
7904static int tg3_open(struct net_device *dev)
7905{
7906 struct tg3 *tp = netdev_priv(dev);
7907 int err;
7908
9e9fd12d
MC
7909 if (tp->fw_needed) {
7910 err = tg3_request_firmware(tp);
7911 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7912 if (err)
7913 return err;
7914 } else if (err) {
7915 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7916 tp->dev->name);
7917 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7918 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7919 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7920 tp->dev->name);
7921 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7922 }
7923 }
7924
c49a1561
MC
7925 netif_carrier_off(tp->dev);
7926
bc1c7567 7927 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7928 if (err)
bc1c7567 7929 return err;
2f751b67
MC
7930
7931 tg3_full_lock(tp, 0);
bc1c7567 7932
1da177e4
LT
7933 tg3_disable_ints(tp);
7934 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7935
f47c11ee 7936 tg3_full_unlock(tp);
1da177e4
LT
7937
7938 /* The placement of this call is tied
7939 * to the setup and use of Host TX descriptors.
7940 */
7941 err = tg3_alloc_consistent(tp);
7942 if (err)
7943 return err;
7944
07b0173c 7945 tg3_ints_init(tp);
88b06bc2 7946
8ef0442f 7947 napi_enable(&tp->napi[0].napi);
1da177e4 7948
07b0173c 7949 err = tg3_request_irq(tp);
1da177e4 7950
07b0173c
MC
7951 if (err)
7952 goto err_out1;
bea3348e 7953
f47c11ee 7954 tg3_full_lock(tp, 0);
1da177e4 7955
8e7a22e3 7956 err = tg3_init_hw(tp, 1);
1da177e4 7957 if (err) {
944d980e 7958 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT
7959 tg3_free_rings(tp);
7960 } else {
fac9b83e
DM
7961 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7962 tp->timer_offset = HZ;
7963 else
7964 tp->timer_offset = HZ / 10;
7965
7966 BUG_ON(tp->timer_offset > HZ);
7967 tp->timer_counter = tp->timer_multiplier =
7968 (HZ / tp->timer_offset);
7969 tp->asf_counter = tp->asf_multiplier =
28fbef78 7970 ((HZ / tp->timer_offset) * 2);
1da177e4
LT
7971
7972 init_timer(&tp->timer);
7973 tp->timer.expires = jiffies + tp->timer_offset;
7974 tp->timer.data = (unsigned long) tp;
7975 tp->timer.function = tg3_timer;
1da177e4
LT
7976 }
7977
f47c11ee 7978 tg3_full_unlock(tp);
1da177e4 7979
07b0173c
MC
7980 if (err)
7981 goto err_out2;
1da177e4 7982
7938109f
MC
7983 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7984 err = tg3_test_msi(tp);
fac9b83e 7985
7938109f 7986 if (err) {
f47c11ee 7987 tg3_full_lock(tp, 0);
944d980e 7988 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 7989 tg3_free_rings(tp);
f47c11ee 7990 tg3_full_unlock(tp);
7938109f 7991
07b0173c 7992 goto err_out1;
7938109f 7993 }
fcfa0a32
MC
7994
7995 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7996 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7997 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7998
b5d3772c
MC
7999 tw32(PCIE_TRANSACTION_CFG,
8000 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC
8001 }
8002 }
7938109f
MC
8003 }
8004
b02fd9e3
MC
8005 tg3_phy_start(tp);
8006
f47c11ee 8007 tg3_full_lock(tp, 0);
1da177e4 8008
7938109f
MC
8009 add_timer(&tp->timer);
8010 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT
8011 tg3_enable_ints(tp);
8012
f47c11ee 8013 tg3_full_unlock(tp);
1da177e4
LT
8014
8015 netif_start_queue(dev);
8016
8017 return 0;
07b0173c
MC
8018
8019err_out2:
09943a18 8020 free_irq(tp->pdev->irq, &tp->napi[0]);
07b0173c
MC
8021
8022err_out1:
8ef0442f 8023 napi_disable(&tp->napi[0].napi);
07b0173c
MC
8024 tg3_ints_fini(tp);
8025 tg3_free_consistent(tp);
8026 return err;
1da177e4
LT
8027}
8028
8029#if 0
8030/*static*/ void tg3_dump_state(struct tg3 *tp)
8031{
8032 u32 val32, val32_2, val32_3, val32_4, val32_5;
8033 u16 val16;
8034 int i;
898a56f8 8035 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT
8036
8037 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8039 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8040 val16, val32);
8041
8042 /* MAC block */
8043 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8044 tr32(MAC_MODE), tr32(MAC_STATUS));
8045 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8046 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8047 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8048 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8049 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8050 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8051
8052 /* Send data initiator control block */
8053 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8054 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8055 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8056 tr32(SNDDATAI_STATSCTRL));
8057
8058 /* Send data completion control block */
8059 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8060
8061 /* Send BD ring selector block */
8062 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8063 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8064
8065 /* Send BD initiator control block */
8066 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8067 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8068
8069 /* Send BD completion control block */
8070 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8071
8072 /* Receive list placement control block */
8073 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8074 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8075 printk(" RCVLPC_STATSCTRL[%08x]\n",
8076 tr32(RCVLPC_STATSCTRL));
8077
8078 /* Receive data and receive BD initiator control block */
8079 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8080 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8081
8082 /* Receive data completion control block */
8083 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8084 tr32(RCVDCC_MODE));
8085
8086 /* Receive BD initiator control block */
8087 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8088 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8089
8090 /* Receive BD completion control block */
8091 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8092 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8093
8094 /* Receive list selector control block */
8095 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8096 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8097
8098 /* Mbuf cluster free block */
8099 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8100 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8101
8102 /* Host coalescing control block */
8103 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8104 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8105 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8106 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8107 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8108 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8109 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8110 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8111 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8112 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8113 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8114 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8115
8116 /* Memory arbiter control block */
8117 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8118 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8119
8120 /* Buffer manager control block */
8121 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8122 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8123 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8124 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8125 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8126 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8127 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8128 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8129
8130 /* Read DMA control block */
8131 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8132 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8133
8134 /* Write DMA control block */
8135 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8136 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8137
8138 /* DMA completion block */
8139 printk("DEBUG: DMAC_MODE[%08x]\n",
8140 tr32(DMAC_MODE));
8141
8142 /* GRC block */
8143 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8144 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8145 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8146 tr32(GRC_LOCAL_CTRL));
8147
8148 /* TG3_BDINFOs */
8149 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8150 tr32(RCVDBDI_JUMBO_BD + 0x0),
8151 tr32(RCVDBDI_JUMBO_BD + 0x4),
8152 tr32(RCVDBDI_JUMBO_BD + 0x8),
8153 tr32(RCVDBDI_JUMBO_BD + 0xc));
8154 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8155 tr32(RCVDBDI_STD_BD + 0x0),
8156 tr32(RCVDBDI_STD_BD + 0x4),
8157 tr32(RCVDBDI_STD_BD + 0x8),
8158 tr32(RCVDBDI_STD_BD + 0xc));
8159 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8160 tr32(RCVDBDI_MINI_BD + 0x0),
8161 tr32(RCVDBDI_MINI_BD + 0x4),
8162 tr32(RCVDBDI_MINI_BD + 0x8),
8163 tr32(RCVDBDI_MINI_BD + 0xc));
8164
8165 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8166 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8167 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8168 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8169 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8170 val32, val32_2, val32_3, val32_4);
8171
8172 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8173 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8174 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8175 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8176 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8177 val32, val32_2, val32_3, val32_4);
8178
8179 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8180 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8181 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8182 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8183 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8184 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8185 val32, val32_2, val32_3, val32_4, val32_5);
8186
8187 /* SW status block */
898a56f8
MC
8188 printk(KERN_DEBUG
8189 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8190 sblk->status,
8191 sblk->status_tag,
8192 sblk->rx_jumbo_consumer,
8193 sblk->rx_consumer,
8194 sblk->rx_mini_consumer,
8195 sblk->idx[0].rx_producer,
8196 sblk->idx[0].tx_consumer);
1da177e4
LT
8197
8198 /* SW statistics block */
8199 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8200 ((u32 *)tp->hw_stats)[0],
8201 ((u32 *)tp->hw_stats)[1],
8202 ((u32 *)tp->hw_stats)[2],
8203 ((u32 *)tp->hw_stats)[3]);
8204
8205 /* Mailboxes */
8206 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC
8207 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8208 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8209 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8210 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT
8211
8212 /* NIC side send descriptors. */
8213 for (i = 0; i < 6; i++) {
8214 unsigned long txd;
8215
8216 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8217 + (i * sizeof(struct tg3_tx_buffer_desc));
8218 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8219 i,
8220 readl(txd + 0x0), readl(txd + 0x4),
8221 readl(txd + 0x8), readl(txd + 0xc));
8222 }
8223
8224 /* NIC side RX descriptors. */
8225 for (i = 0; i < 6; i++) {
8226 unsigned long rxd;
8227
8228 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8229 + (i * sizeof(struct tg3_rx_buffer_desc));
8230 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8231 i,
8232 readl(rxd + 0x0), readl(rxd + 0x4),
8233 readl(rxd + 0x8), readl(rxd + 0xc));
8234 rxd += (4 * sizeof(u32));
8235 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8236 i,
8237 readl(rxd + 0x0), readl(rxd + 0x4),
8238 readl(rxd + 0x8), readl(rxd + 0xc));
8239 }
8240
8241 for (i = 0; i < 6; i++) {
8242 unsigned long rxd;
8243
8244 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8245 + (i * sizeof(struct tg3_rx_buffer_desc));
8246 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8247 i,
8248 readl(rxd + 0x0), readl(rxd + 0x4),
8249 readl(rxd + 0x8), readl(rxd + 0xc));
8250 rxd += (4 * sizeof(u32));
8251 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8252 i,
8253 readl(rxd + 0x0), readl(rxd + 0x4),
8254 readl(rxd + 0x8), readl(rxd + 0xc));
8255 }
8256}
8257#endif
8258
8259static struct net_device_stats *tg3_get_stats(struct net_device *);
8260static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8261
8262static int tg3_close(struct net_device *dev)
8263{
8264 struct tg3 *tp = netdev_priv(dev);
8265
8ef0442f 8266 napi_disable(&tp->napi[0].napi);
28e53bdd 8267 cancel_work_sync(&tp->reset_task);
7faa006f 8268
1da177e4
LT
8269 netif_stop_queue(dev);
8270
8271 del_timer_sync(&tp->timer);
8272
f47c11ee 8273 tg3_full_lock(tp, 1);
1da177e4
LT
8274#if 0
8275 tg3_dump_state(tp);
8276#endif
8277
8278 tg3_disable_ints(tp);
8279
944d980e 8280 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8281 tg3_free_rings(tp);
5cf64b8a 8282 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8283
f47c11ee 8284 tg3_full_unlock(tp);
1da177e4 8285
09943a18 8286 free_irq(tp->pdev->irq, &tp->napi[0]);
07b0173c
MC
8287
8288 tg3_ints_fini(tp);
1da177e4
LT
8289
8290 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8291 sizeof(tp->net_stats_prev));
8292 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8293 sizeof(tp->estats_prev));
8294
8295 tg3_free_consistent(tp);
8296
bc1c7567
MC
8297 tg3_set_power_state(tp, PCI_D3hot);
8298
8299 netif_carrier_off(tp->dev);
8300
1da177e4
LT
8301 return 0;
8302}
8303
8304static inline unsigned long get_stat64(tg3_stat64_t *val)
8305{
8306 unsigned long ret;
8307
8308#if (BITS_PER_LONG == 32)
8309 ret = val->low;
8310#else
8311 ret = ((u64)val->high << 32) | ((u64)val->low);
8312#endif
8313 return ret;
8314}
8315
816f8b86
SB
8316static inline u64 get_estat64(tg3_stat64_t *val)
8317{
8318 return ((u64)val->high << 32) | ((u64)val->low);
8319}
8320
1da177e4
LT
8321static unsigned long calc_crc_errors(struct tg3 *tp)
8322{
8323 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8324
8325 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8326 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8327 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT
8328 u32 val;
8329
f47c11ee 8330 spin_lock_bh(&tp->lock);
569a5df8
MC
8331 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8332 tg3_writephy(tp, MII_TG3_TEST1,
8333 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT
8334 tg3_readphy(tp, 0x14, &val);
8335 } else
8336 val = 0;
f47c11ee 8337 spin_unlock_bh(&tp->lock);
1da177e4
LT
8338
8339 tp->phy_crc_errors += val;
8340
8341 return tp->phy_crc_errors;
8342 }
8343
8344 return get_stat64(&hw_stats->rx_fcs_errors);
8345}
8346
8347#define ESTAT_ADD(member) \
8348 estats->member = old_estats->member + \
816f8b86 8349 get_estat64(&hw_stats->member)
1da177e4
LT
8350
8351static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8352{
8353 struct tg3_ethtool_stats *estats = &tp->estats;
8354 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8355 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8356
8357 if (!hw_stats)
8358 return old_estats;
8359
8360 ESTAT_ADD(rx_octets);
8361 ESTAT_ADD(rx_fragments);
8362 ESTAT_ADD(rx_ucast_packets);
8363 ESTAT_ADD(rx_mcast_packets);
8364 ESTAT_ADD(rx_bcast_packets);
8365 ESTAT_ADD(rx_fcs_errors);
8366 ESTAT_ADD(rx_align_errors);
8367 ESTAT_ADD(rx_xon_pause_rcvd);
8368 ESTAT_ADD(rx_xoff_pause_rcvd);
8369 ESTAT_ADD(rx_mac_ctrl_rcvd);
8370 ESTAT_ADD(rx_xoff_entered);
8371 ESTAT_ADD(rx_frame_too_long_errors);
8372 ESTAT_ADD(rx_jabbers);
8373 ESTAT_ADD(rx_undersize_packets);
8374 ESTAT_ADD(rx_in_length_errors);
8375 ESTAT_ADD(rx_out_length_errors);
8376 ESTAT_ADD(rx_64_or_less_octet_packets);
8377 ESTAT_ADD(rx_65_to_127_octet_packets);
8378 ESTAT_ADD(rx_128_to_255_octet_packets);
8379 ESTAT_ADD(rx_256_to_511_octet_packets);
8380 ESTAT_ADD(rx_512_to_1023_octet_packets);
8381 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8382 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8383 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8384 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8385 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8386
8387 ESTAT_ADD(tx_octets);
8388 ESTAT_ADD(tx_collisions);
8389 ESTAT_ADD(tx_xon_sent);
8390 ESTAT_ADD(tx_xoff_sent);
8391 ESTAT_ADD(tx_flow_control);
8392 ESTAT_ADD(tx_mac_errors);
8393 ESTAT_ADD(tx_single_collisions);
8394 ESTAT_ADD(tx_mult_collisions);
8395 ESTAT_ADD(tx_deferred);
8396 ESTAT_ADD(tx_excessive_collisions);
8397 ESTAT_ADD(tx_late_collisions);
8398 ESTAT_ADD(tx_collide_2times);
8399 ESTAT_ADD(tx_collide_3times);
8400 ESTAT_ADD(tx_collide_4times);
8401 ESTAT_ADD(tx_collide_5times);
8402 ESTAT_ADD(tx_collide_6times);
8403 ESTAT_ADD(tx_collide_7times);
8404 ESTAT_ADD(tx_collide_8times);
8405 ESTAT_ADD(tx_collide_9times);
8406 ESTAT_ADD(tx_collide_10times);
8407 ESTAT_ADD(tx_collide_11times);
8408 ESTAT_ADD(tx_collide_12times);
8409 ESTAT_ADD(tx_collide_13times);
8410 ESTAT_ADD(tx_collide_14times);
8411 ESTAT_ADD(tx_collide_15times);
8412 ESTAT_ADD(tx_ucast_packets);
8413 ESTAT_ADD(tx_mcast_packets);
8414 ESTAT_ADD(tx_bcast_packets);
8415 ESTAT_ADD(tx_carrier_sense_errors);
8416 ESTAT_ADD(tx_discards);
8417 ESTAT_ADD(tx_errors);
8418
8419 ESTAT_ADD(dma_writeq_full);
8420 ESTAT_ADD(dma_write_prioq_full);
8421 ESTAT_ADD(rxbds_empty);
8422 ESTAT_ADD(rx_discards);
8423 ESTAT_ADD(rx_errors);
8424 ESTAT_ADD(rx_threshold_hit);
8425
8426 ESTAT_ADD(dma_readq_full);
8427 ESTAT_ADD(dma_read_prioq_full);
8428 ESTAT_ADD(tx_comp_queue_full);
8429
8430 ESTAT_ADD(ring_set_send_prod_index);
8431 ESTAT_ADD(ring_status_update);
8432 ESTAT_ADD(nic_irqs);
8433 ESTAT_ADD(nic_avoided_irqs);
8434 ESTAT_ADD(nic_tx_threshold_hit);
8435
8436 return estats;
8437}
8438
8439static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8440{
8441 struct tg3 *tp = netdev_priv(dev);
8442 struct net_device_stats *stats = &tp->net_stats;
8443 struct net_device_stats *old_stats = &tp->net_stats_prev;
8444 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8445
8446 if (!hw_stats)
8447 return old_stats;
8448
8449 stats->rx_packets = old_stats->rx_packets +
8450 get_stat64(&hw_stats->rx_ucast_packets) +
8451 get_stat64(&hw_stats->rx_mcast_packets) +
8452 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8453
1da177e4
LT
8454 stats->tx_packets = old_stats->tx_packets +
8455 get_stat64(&hw_stats->tx_ucast_packets) +
8456 get_stat64(&hw_stats->tx_mcast_packets) +
8457 get_stat64(&hw_stats->tx_bcast_packets);
8458
8459 stats->rx_bytes = old_stats->rx_bytes +
8460 get_stat64(&hw_stats->rx_octets);
8461 stats->tx_bytes = old_stats->tx_bytes +
8462 get_stat64(&hw_stats->tx_octets);
8463
8464 stats->rx_errors = old_stats->rx_errors +
4f63b877 8465 get_stat64(&hw_stats->rx_errors);
1da177e4
LT
8466 stats->tx_errors = old_stats->tx_errors +
8467 get_stat64(&hw_stats->tx_errors) +
8468 get_stat64(&hw_stats->tx_mac_errors) +
8469 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8470 get_stat64(&hw_stats->tx_discards);
8471
8472 stats->multicast = old_stats->multicast +
8473 get_stat64(&hw_stats->rx_mcast_packets);
8474 stats->collisions = old_stats->collisions +
8475 get_stat64(&hw_stats->tx_collisions);
8476
8477 stats->rx_length_errors = old_stats->rx_length_errors +
8478 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8479 get_stat64(&hw_stats->rx_undersize_packets);
8480
8481 stats->rx_over_errors = old_stats->rx_over_errors +
8482 get_stat64(&hw_stats->rxbds_empty);
8483 stats->rx_frame_errors = old_stats->rx_frame_errors +
8484 get_stat64(&hw_stats->rx_align_errors);
8485 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8486 get_stat64(&hw_stats->tx_discards);
8487 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8488 get_stat64(&hw_stats->tx_carrier_sense_errors);
8489
8490 stats->rx_crc_errors = old_stats->rx_crc_errors +
8491 calc_crc_errors(tp);
8492
4f63b877
JL
8493 stats->rx_missed_errors = old_stats->rx_missed_errors +
8494 get_stat64(&hw_stats->rx_discards);
8495
1da177e4
LT
8496 return stats;
8497}
8498
8499static inline u32 calc_crc(unsigned char *buf, int len)
8500{
8501 u32 reg;
8502 u32 tmp;
8503 int j, k;
8504
8505 reg = 0xffffffff;
8506
8507 for (j = 0; j < len; j++) {
8508 reg ^= buf[j];
8509
8510 for (k = 0; k < 8; k++) {
8511 tmp = reg & 0x01;
8512
8513 reg >>= 1;
8514
8515 if (tmp) {
8516 reg ^= 0xedb88320;
8517 }
8518 }
8519 }
8520
8521 return ~reg;
8522}
8523
8524static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8525{
8526 /* accept or reject all multicast frames */
8527 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8528 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8529 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8530 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8531}
8532
8533static void __tg3_set_rx_mode(struct net_device *dev)
8534{
8535 struct tg3 *tp = netdev_priv(dev);
8536 u32 rx_mode;
8537
8538 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8539 RX_MODE_KEEP_VLAN_TAG);
8540
8541 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8542 * flag clear.
8543 */
8544#if TG3_VLAN_TAG_USED
8545 if (!tp->vlgrp &&
8546 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8547 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8548#else
8549 /* By definition, VLAN is disabled always in this
8550 * case.
8551 */
8552 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8553 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8554#endif
8555
8556 if (dev->flags & IFF_PROMISC) {
8557 /* Promiscuous mode. */
8558 rx_mode |= RX_MODE_PROMISC;
8559 } else if (dev->flags & IFF_ALLMULTI) {
8560 /* Accept all multicast. */
8561 tg3_set_multi (tp, 1);
8562 } else if (dev->mc_count < 1) {
8563 /* Reject all multicast. */
8564 tg3_set_multi (tp, 0);
8565 } else {
8566 /* Accept one or more multicast(s). */
8567 struct dev_mc_list *mclist;
8568 unsigned int i;
8569 u32 mc_filter[4] = { 0, };
8570 u32 regidx;
8571 u32 bit;
8572 u32 crc;
8573
8574 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8575 i++, mclist = mclist->next) {
8576
8577 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8578 bit = ~crc & 0x7f;
8579 regidx = (bit & 0x60) >> 5;
8580 bit &= 0x1f;
8581 mc_filter[regidx] |= (1 << bit);
8582 }
8583
8584 tw32(MAC_HASH_REG_0, mc_filter[0]);
8585 tw32(MAC_HASH_REG_1, mc_filter[1]);
8586 tw32(MAC_HASH_REG_2, mc_filter[2]);
8587 tw32(MAC_HASH_REG_3, mc_filter[3]);
8588 }
8589
8590 if (rx_mode != tp->rx_mode) {
8591 tp->rx_mode = rx_mode;
8592 tw32_f(MAC_RX_MODE, rx_mode);
8593 udelay(10);
8594 }
8595}
8596
8597static void tg3_set_rx_mode(struct net_device *dev)
8598{
8599 struct tg3 *tp = netdev_priv(dev);
8600
e75f7c90
MC
8601 if (!netif_running(dev))
8602 return;
8603
f47c11ee 8604 tg3_full_lock(tp, 0);
1da177e4 8605 __tg3_set_rx_mode(dev);
f47c11ee 8606 tg3_full_unlock(tp);
1da177e4
LT
8607}
8608
8609#define TG3_REGDUMP_LEN (32 * 1024)
8610
8611static int tg3_get_regs_len(struct net_device *dev)
8612{
8613 return TG3_REGDUMP_LEN;
8614}
8615
8616static void tg3_get_regs(struct net_device *dev,
8617 struct ethtool_regs *regs, void *_p)
8618{
8619 u32 *p = _p;
8620 struct tg3 *tp = netdev_priv(dev);
8621 u8 *orig_p = _p;
8622 int i;
8623
8624 regs->version = 0;
8625
8626 memset(p, 0, TG3_REGDUMP_LEN);
8627
bc1c7567
MC
8628 if (tp->link_config.phy_is_low_power)
8629 return;
8630
f47c11ee 8631 tg3_full_lock(tp, 0);
1da177e4
LT
8632
8633#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8634#define GET_REG32_LOOP(base,len) \
8635do { p = (u32 *)(orig_p + (base)); \
8636 for (i = 0; i < len; i += 4) \
8637 __GET_REG32((base) + i); \
8638} while (0)
8639#define GET_REG32_1(reg) \
8640do { p = (u32 *)(orig_p + (reg)); \
8641 __GET_REG32((reg)); \
8642} while (0)
8643
8644 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8645 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8646 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8647 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8648 GET_REG32_1(SNDDATAC_MODE);
8649 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8650 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8651 GET_REG32_1(SNDBDC_MODE);
8652 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8653 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8654 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8655 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8656 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8657 GET_REG32_1(RCVDCC_MODE);
8658 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8659 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8660 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8661 GET_REG32_1(MBFREE_MODE);
8662 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8663 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8664 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8665 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8666 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE
8667 GET_REG32_1(RX_CPU_MODE);
8668 GET_REG32_1(RX_CPU_STATE);
8669 GET_REG32_1(RX_CPU_PGMCTR);
8670 GET_REG32_1(RX_CPU_HWBKPT);
8671 GET_REG32_1(TX_CPU_MODE);
8672 GET_REG32_1(TX_CPU_STATE);
8673 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT
8674 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8675 GET_REG32_LOOP(FTQ_RESET, 0x120);
8676 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8677 GET_REG32_1(DMAC_MODE);
8678 GET_REG32_LOOP(GRC_MODE, 0x4c);
8679 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8680 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8681
8682#undef __GET_REG32
8683#undef GET_REG32_LOOP
8684#undef GET_REG32_1
8685
f47c11ee 8686 tg3_full_unlock(tp);
1da177e4
LT
8687}
8688
8689static int tg3_get_eeprom_len(struct net_device *dev)
8690{
8691 struct tg3 *tp = netdev_priv(dev);
8692
8693 return tp->nvram_size;
8694}
8695
1da177e4
LT
8696static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8697{
8698 struct tg3 *tp = netdev_priv(dev);
8699 int ret;
8700 u8 *pd;
b9fc7dc5 8701 u32 i, offset, len, b_offset, b_count;
a9dc529d 8702 __be32 val;
1da177e4 8703
df259d8c
MC
8704 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8705 return -EINVAL;
8706
bc1c7567
MC
8707 if (tp->link_config.phy_is_low_power)
8708 return -EAGAIN;
8709
1da177e4
LT
8710 offset = eeprom->offset;
8711 len = eeprom->len;
8712 eeprom->len = 0;
8713
8714 eeprom->magic = TG3_EEPROM_MAGIC;
8715
8716 if (offset & 3) {
8717 /* adjustments to start on required 4 byte boundary */
8718 b_offset = offset & 3;
8719 b_count = 4 - b_offset;
8720 if (b_count > len) {
8721 /* i.e. offset=1 len=2 */
8722 b_count = len;
8723 }
a9dc529d 8724 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT
8725 if (ret)
8726 return ret;
1da177e4
LT
8727 memcpy(data, ((char*)&val) + b_offset, b_count);
8728 len -= b_count;
8729 offset += b_count;
8730 eeprom->len += b_count;
8731 }
8732
8733 /* read bytes upto the last 4 byte boundary */
8734 pd = &data[eeprom->len];
8735 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8736 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT
8737 if (ret) {
8738 eeprom->len += i;
8739 return ret;
8740 }
1da177e4
LT
8741 memcpy(pd + i, &val, 4);
8742 }
8743 eeprom->len += i;
8744
8745 if (len & 3) {
8746 /* read last bytes not ending on 4 byte boundary */
8747 pd = &data[eeprom->len];
8748 b_count = len & 3;
8749 b_offset = offset + len - b_count;
a9dc529d 8750 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT
8751 if (ret)
8752 return ret;
b9fc7dc5 8753 memcpy(pd, &val, b_count);
1da177e4
LT
8754 eeprom->len += b_count;
8755 }
8756 return 0;
8757}
8758
6aa20a22 8759static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT
8760
8761static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8762{
8763 struct tg3 *tp = netdev_priv(dev);
8764 int ret;
b9fc7dc5 8765 u32 offset, len, b_offset, odd_len;
1da177e4 8766 u8 *buf;
a9dc529d 8767 __be32 start, end;
1da177e4 8768
bc1c7567
MC
8769 if (tp->link_config.phy_is_low_power)
8770 return -EAGAIN;
8771
df259d8c
MC
8772 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8773 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT
8774 return -EINVAL;
8775
8776 offset = eeprom->offset;
8777 len = eeprom->len;
8778
8779 if ((b_offset = (offset & 3))) {
8780 /* adjustments to start on required 4 byte boundary */
a9dc529d 8781 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT
8782 if (ret)
8783 return ret;
1da177e4
LT
8784 len += b_offset;
8785 offset &= ~3;
1c8594b4
MC
8786 if (len < 4)
8787 len = 4;
1da177e4
LT
8788 }
8789
8790 odd_len = 0;
1c8594b4 8791 if (len & 3) {
1da177e4
LT
8792 /* adjustments to end on required 4 byte boundary */
8793 odd_len = 1;
8794 len = (len + 3) & ~3;
a9dc529d 8795 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT
8796 if (ret)
8797 return ret;
1da177e4
LT
8798 }
8799
8800 buf = data;
8801 if (b_offset || odd_len) {
8802 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8803 if (!buf)
1da177e4
LT
8804 return -ENOMEM;
8805 if (b_offset)
8806 memcpy(buf, &start, 4);
8807 if (odd_len)
8808 memcpy(buf+len-4, &end, 4);
8809 memcpy(buf + b_offset, data, eeprom->len);
8810 }
8811
8812 ret = tg3_nvram_write_block(tp, offset, len, buf);
8813
8814 if (buf != data)
8815 kfree(buf);
8816
8817 return ret;
8818}
8819
8820static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8821{
b02fd9e3
MC
8822 struct tg3 *tp = netdev_priv(dev);
8823
8824 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8825 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8826 return -EAGAIN;
298cf9be 8827 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8828 }
6aa20a22 8829
1da177e4
LT
8830 cmd->supported = (SUPPORTED_Autoneg);
8831
8832 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8833 cmd->supported |= (SUPPORTED_1000baseT_Half |
8834 SUPPORTED_1000baseT_Full);
8835
ef348144 8836 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT
8837 cmd->supported |= (SUPPORTED_100baseT_Half |
8838 SUPPORTED_100baseT_Full |
8839 SUPPORTED_10baseT_Half |
8840 SUPPORTED_10baseT_Full |
3bebab59 8841 SUPPORTED_TP);
ef348144
KK
8842 cmd->port = PORT_TP;
8843 } else {
1da177e4 8844 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK
8845 cmd->port = PORT_FIBRE;
8846 }
6aa20a22 8847
1da177e4
LT
8848 cmd->advertising = tp->link_config.advertising;
8849 if (netif_running(dev)) {
8850 cmd->speed = tp->link_config.active_speed;
8851 cmd->duplex = tp->link_config.active_duplex;
8852 }
1da177e4 8853 cmd->phy_address = PHY_ADDR;
7e5856bd 8854 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT
8855 cmd->autoneg = tp->link_config.autoneg;
8856 cmd->maxtxpkt = 0;
8857 cmd->maxrxpkt = 0;
8858 return 0;
8859}
6aa20a22 8860
1da177e4
LT
8861static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8862{
8863 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8864
b02fd9e3
MC
8865 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8866 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8867 return -EAGAIN;
298cf9be 8868 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC
8869 }
8870
7e5856bd
MC
8871 if (cmd->autoneg != AUTONEG_ENABLE &&
8872 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8873 return -EINVAL;
7e5856bd
MC
8874
8875 if (cmd->autoneg == AUTONEG_DISABLE &&
8876 cmd->duplex != DUPLEX_FULL &&
8877 cmd->duplex != DUPLEX_HALF)
37ff238d 8878 return -EINVAL;
1da177e4 8879
7e5856bd
MC
8880 if (cmd->autoneg == AUTONEG_ENABLE) {
8881 u32 mask = ADVERTISED_Autoneg |
8882 ADVERTISED_Pause |
8883 ADVERTISED_Asym_Pause;
8884
8885 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8886 mask |= ADVERTISED_1000baseT_Half |
8887 ADVERTISED_1000baseT_Full;
8888
8889 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8890 mask |= ADVERTISED_100baseT_Half |
8891 ADVERTISED_100baseT_Full |
8892 ADVERTISED_10baseT_Half |
8893 ADVERTISED_10baseT_Full |
8894 ADVERTISED_TP;
8895 else
8896 mask |= ADVERTISED_FIBRE;
8897
8898 if (cmd->advertising & ~mask)
8899 return -EINVAL;
8900
8901 mask &= (ADVERTISED_1000baseT_Half |
8902 ADVERTISED_1000baseT_Full |
8903 ADVERTISED_100baseT_Half |
8904 ADVERTISED_100baseT_Full |
8905 ADVERTISED_10baseT_Half |
8906 ADVERTISED_10baseT_Full);
8907
8908 cmd->advertising &= mask;
8909 } else {
8910 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8911 if (cmd->speed != SPEED_1000)
8912 return -EINVAL;
8913
8914 if (cmd->duplex != DUPLEX_FULL)
8915 return -EINVAL;
8916 } else {
8917 if (cmd->speed != SPEED_100 &&
8918 cmd->speed != SPEED_10)
8919 return -EINVAL;
8920 }
8921 }
8922
f47c11ee 8923 tg3_full_lock(tp, 0);
1da177e4
LT
8924
8925 tp->link_config.autoneg = cmd->autoneg;
8926 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG
8927 tp->link_config.advertising = (cmd->advertising |
8928 ADVERTISED_Autoneg);
1da177e4
LT
8929 tp->link_config.speed = SPEED_INVALID;
8930 tp->link_config.duplex = DUPLEX_INVALID;
8931 } else {
8932 tp->link_config.advertising = 0;
8933 tp->link_config.speed = cmd->speed;
8934 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8935 }
6aa20a22 8936
24fcad6b
MC
8937 tp->link_config.orig_speed = tp->link_config.speed;
8938 tp->link_config.orig_duplex = tp->link_config.duplex;
8939 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8940
1da177e4
LT
8941 if (netif_running(dev))
8942 tg3_setup_phy(tp, 1);
8943
f47c11ee 8944 tg3_full_unlock(tp);
6aa20a22 8945
1da177e4
LT
8946 return 0;
8947}
6aa20a22 8948
1da177e4
LT
8949static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8950{
8951 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8952
1da177e4
LT
8953 strcpy(info->driver, DRV_MODULE_NAME);
8954 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8955 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT
8956 strcpy(info->bus_info, pci_name(tp->pdev));
8957}
6aa20a22 8958
1da177e4
LT
8959static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8960{
8961 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8962
12dac075
RW
8963 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8964 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ
8965 wol->supported = WAKE_MAGIC;
8966 else
8967 wol->supported = 0;
1da177e4 8968 wol->wolopts = 0;
05ac4cb7
MC
8969 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8970 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT
8971 wol->wolopts = WAKE_MAGIC;
8972 memset(&wol->sopass, 0, sizeof(wol->sopass));
8973}
6aa20a22 8974
1da177e4
LT
8975static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8976{
8977 struct tg3 *tp = netdev_priv(dev);
12dac075 8978 struct device *dp = &tp->pdev->dev;
6aa20a22 8979
1da177e4
LT
8980 if (wol->wolopts & ~WAKE_MAGIC)
8981 return -EINVAL;
8982 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8983 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8984 return -EINVAL;
6aa20a22 8985
f47c11ee 8986 spin_lock_bh(&tp->lock);
12dac075 8987 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8988 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW
8989 device_set_wakeup_enable(dp, true);
8990 } else {
1da177e4 8991 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW
8992 device_set_wakeup_enable(dp, false);
8993 }
f47c11ee 8994 spin_unlock_bh(&tp->lock);
6aa20a22 8995
1da177e4
LT
8996 return 0;
8997}
6aa20a22 8998
1da177e4
LT
8999static u32 tg3_get_msglevel(struct net_device *dev)
9000{
9001 struct tg3 *tp = netdev_priv(dev);
9002 return tp->msg_enable;
9003}
6aa20a22 9004
1da177e4
LT
9005static void tg3_set_msglevel(struct net_device *dev, u32 value)
9006{
9007 struct tg3 *tp = netdev_priv(dev);
9008 tp->msg_enable = value;
9009}
6aa20a22 9010
1da177e4
LT
9011static int tg3_set_tso(struct net_device *dev, u32 value)
9012{
9013 struct tg3 *tp = netdev_priv(dev);
9014
9015 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9016 if (value)
9017 return -EINVAL;
9018 return 0;
9019 }
027455ad
MC
9020 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9021 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9022 if (value) {
b0026624 9023 dev->features |= NETIF_F_TSO6;
57e6983c
MC
9024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9025 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9026 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC
9027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC
9029 dev->features |= NETIF_F_TSO_ECN;
9030 } else
9031 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9032 }
1da177e4
LT
9033 return ethtool_op_set_tso(dev, value);
9034}
6aa20a22 9035
1da177e4
LT
9036static int tg3_nway_reset(struct net_device *dev)
9037{
9038 struct tg3 *tp = netdev_priv(dev);
1da177e4 9039 int r;
6aa20a22 9040
1da177e4
LT
9041 if (!netif_running(dev))
9042 return -EAGAIN;
9043
c94e3941
MC
9044 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9045 return -EINVAL;
9046
b02fd9e3
MC
9047 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9048 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9049 return -EAGAIN;
298cf9be 9050 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC
9051 } else {
9052 u32 bmcr;
9053
9054 spin_lock_bh(&tp->lock);
9055 r = -EINVAL;
9056 tg3_readphy(tp, MII_BMCR, &bmcr);
9057 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9058 ((bmcr & BMCR_ANENABLE) ||
9059 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9060 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9061 BMCR_ANENABLE);
9062 r = 0;
9063 }
9064 spin_unlock_bh(&tp->lock);
1da177e4 9065 }
6aa20a22 9066
1da177e4
LT
9067 return r;
9068}
6aa20a22 9069
1da177e4
LT
9070static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9071{
9072 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9073
1da177e4
LT
9074 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9075 ering->rx_mini_max_pending = 0;
4f81c32b
MC
9076 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9077 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9078 else
9079 ering->rx_jumbo_max_pending = 0;
9080
9081 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT
9082
9083 ering->rx_pending = tp->rx_pending;
9084 ering->rx_mini_pending = 0;
4f81c32b
MC
9085 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9086 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9087 else
9088 ering->rx_jumbo_pending = 0;
9089
1da177e4
LT
9090 ering->tx_pending = tp->tx_pending;
9091}
6aa20a22 9092
1da177e4
LT
9093static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9094{
9095 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9096 int irq_sync = 0, err = 0;
6aa20a22 9097
1da177e4
LT
9098 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9099 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC
9100 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9101 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9102 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9103 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9104 return -EINVAL;
6aa20a22 9105
bbe832c0 9106 if (netif_running(dev)) {
b02fd9e3 9107 tg3_phy_stop(tp);
1da177e4 9108 tg3_netif_stop(tp);
bbe832c0
MC
9109 irq_sync = 1;
9110 }
1da177e4 9111
bbe832c0 9112 tg3_full_lock(tp, irq_sync);
6aa20a22 9113
1da177e4
LT
9114 tp->rx_pending = ering->rx_pending;
9115
9116 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9117 tp->rx_pending > 63)
9118 tp->rx_pending = 63;
9119 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9120 tp->tx_pending = ering->tx_pending;
9121
9122 if (netif_running(dev)) {
944d980e 9123 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC
9124 err = tg3_restart_hw(tp, 1);
9125 if (!err)
9126 tg3_netif_start(tp);
1da177e4
LT
9127 }
9128
f47c11ee 9129 tg3_full_unlock(tp);
6aa20a22 9130
b02fd9e3
MC
9131 if (irq_sync && !err)
9132 tg3_phy_start(tp);
9133
b9ec6c1b 9134 return err;
1da177e4 9135}
6aa20a22 9136
1da177e4
LT
9137static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9138{
9139 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9140
1da177e4 9141 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9142
e18ce346 9143 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC
9144 epause->rx_pause = 1;
9145 else
9146 epause->rx_pause = 0;
9147
e18ce346 9148 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC
9149 epause->tx_pause = 1;
9150 else
9151 epause->tx_pause = 0;
1da177e4 9152}
6aa20a22 9153
1da177e4
LT
9154static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9155{
9156 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9157 int err = 0;
6aa20a22 9158
b02fd9e3
MC
9159 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9160 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9161 return -EAGAIN;
1da177e4 9162
b02fd9e3
MC
9163 if (epause->autoneg) {
9164 u32 newadv;
9165 struct phy_device *phydev;
f47c11ee 9166
298cf9be 9167 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9168
b02fd9e3
MC
9169 if (epause->rx_pause) {
9170 if (epause->tx_pause)
9171 newadv = ADVERTISED_Pause;
9172 else
9173 newadv = ADVERTISED_Pause |
9174 ADVERTISED_Asym_Pause;
9175 } else if (epause->tx_pause) {
9176 newadv = ADVERTISED_Asym_Pause;
9177 } else
9178 newadv = 0;
9179
9180 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9181 u32 oldadv = phydev->advertising &
9182 (ADVERTISED_Pause |
9183 ADVERTISED_Asym_Pause);
9184 if (oldadv != newadv) {
9185 phydev->advertising &=
9186 ~(ADVERTISED_Pause |
9187 ADVERTISED_Asym_Pause);
9188 phydev->advertising |= newadv;
9189 err = phy_start_aneg(phydev);
9190 }
9191 } else {
9192 tp->link_config.advertising &=
9193 ~(ADVERTISED_Pause |
9194 ADVERTISED_Asym_Pause);
9195 tp->link_config.advertising |= newadv;
9196 }
9197 } else {
9198 if (epause->rx_pause)
e18ce346 9199 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9200 else
e18ce346 9201 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9202
b02fd9e3 9203 if (epause->tx_pause)
e18ce346 9204 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9205 else
e18ce346 9206 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC
9207
9208 if (netif_running(dev))
9209 tg3_setup_flow_control(tp, 0, 0);
9210 }
9211 } else {
9212 int irq_sync = 0;
9213
9214 if (netif_running(dev)) {
9215 tg3_netif_stop(tp);
9216 irq_sync = 1;
9217 }
9218
9219 tg3_full_lock(tp, irq_sync);
9220
9221 if (epause->autoneg)
9222 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9223 else
9224 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9225 if (epause->rx_pause)
e18ce346 9226 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9227 else
e18ce346 9228 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9229 if (epause->tx_pause)
e18ce346 9230 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9231 else
e18ce346 9232 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC
9233
9234 if (netif_running(dev)) {
9235 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9236 err = tg3_restart_hw(tp, 1);
9237 if (!err)
9238 tg3_netif_start(tp);
9239 }
9240
9241 tg3_full_unlock(tp);
9242 }
6aa20a22 9243
b9ec6c1b 9244 return err;
1da177e4 9245}
6aa20a22 9246
1da177e4
LT
9247static u32 tg3_get_rx_csum(struct net_device *dev)
9248{
9249 struct tg3 *tp = netdev_priv(dev);
9250 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9251}
6aa20a22 9252
1da177e4
LT
9253static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9254{
9255 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9256
1da177e4
LT
9257 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9258 if (data != 0)
9259 return -EINVAL;
9260 return 0;
9261 }
6aa20a22 9262
f47c11ee 9263 spin_lock_bh(&tp->lock);
1da177e4
LT
9264 if (data)
9265 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9266 else
9267 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9268 spin_unlock_bh(&tp->lock);
6aa20a22 9269
1da177e4
LT
9270 return 0;
9271}
6aa20a22 9272
1da177e4
LT
9273static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9274{
9275 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9276
1da177e4
LT
9277 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9278 if (data != 0)
9279 return -EINVAL;
9280 return 0;
9281 }
6aa20a22 9282
321d32a0 9283 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9284 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9285 else
9c27dbdf 9286 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT
9287
9288 return 0;
9289}
9290
b9f2c044 9291static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9292{
b9f2c044
JG
9293 switch (sset) {
9294 case ETH_SS_TEST:
9295 return TG3_NUM_TEST;
9296 case ETH_SS_STATS:
9297 return TG3_NUM_STATS;
9298 default:
9299 return -EOPNOTSUPP;
9300 }
4cafd3f5
MC
9301}
9302
1da177e4
LT
9303static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9304{
9305 switch (stringset) {
9306 case ETH_SS_STATS:
9307 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9308 break;
4cafd3f5
MC
9309 case ETH_SS_TEST:
9310 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9311 break;
1da177e4
LT
9312 default:
9313 WARN_ON(1); /* we need a WARN() */
9314 break;
9315 }
9316}
9317
4009a93d
MC
9318static int tg3_phys_id(struct net_device *dev, u32 data)
9319{
9320 struct tg3 *tp = netdev_priv(dev);
9321 int i;
9322
9323 if (!netif_running(tp->dev))
9324 return -EAGAIN;
9325
9326 if (data == 0)
759afc31 9327 data = UINT_MAX / 2;
4009a93d
MC
9328
9329 for (i = 0; i < (data * 2); i++) {
9330 if ((i % 2) == 0)
9331 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9332 LED_CTRL_1000MBPS_ON |
9333 LED_CTRL_100MBPS_ON |
9334 LED_CTRL_10MBPS_ON |
9335 LED_CTRL_TRAFFIC_OVERRIDE |
9336 LED_CTRL_TRAFFIC_BLINK |
9337 LED_CTRL_TRAFFIC_LED);
6aa20a22 9338
4009a93d
MC
9339 else
9340 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9341 LED_CTRL_TRAFFIC_OVERRIDE);
9342
9343 if (msleep_interruptible(500))
9344 break;
9345 }
9346 tw32(MAC_LED_CTRL, tp->led_ctrl);
9347 return 0;
9348}
9349
1da177e4
LT
9350static void tg3_get_ethtool_stats (struct net_device *dev,
9351 struct ethtool_stats *estats, u64 *tmp_stats)
9352{
9353 struct tg3 *tp = netdev_priv(dev);
9354 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9355}
9356
566f86ad 9357#define NVRAM_TEST_SIZE 0x100
a5767dec
MC
9358#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9359#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9360#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC
9361#define NVRAM_SELFBOOT_HW_SIZE 0x20
9362#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC
9363
9364static int tg3_test_nvram(struct tg3 *tp)
9365{
b9fc7dc5 9366 u32 csum, magic;
a9dc529d 9367 __be32 *buf;
ab0049b4 9368 int i, j, k, err = 0, size;
566f86ad 9369
df259d8c
MC
9370 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9371 return 0;
9372
e4f34110 9373 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC
9374 return -EIO;
9375
1b27777a
MC
9376 if (magic == TG3_EEPROM_MAGIC)
9377 size = NVRAM_TEST_SIZE;
b16250e3 9378 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC
9379 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9380 TG3_EEPROM_SB_FORMAT_1) {
9381 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9382 case TG3_EEPROM_SB_REVISION_0:
9383 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9384 break;
9385 case TG3_EEPROM_SB_REVISION_2:
9386 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9387 break;
9388 case TG3_EEPROM_SB_REVISION_3:
9389 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9390 break;
9391 default:
9392 return 0;
9393 }
9394 } else
1b27777a 9395 return 0;
b16250e3
MC
9396 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9397 size = NVRAM_SELFBOOT_HW_SIZE;
9398 else
1b27777a
MC
9399 return -EIO;
9400
9401 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC
9402 if (buf == NULL)
9403 return -ENOMEM;
9404
1b27777a
MC
9405 err = -EIO;
9406 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC
9407 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9408 if (err)
566f86ad 9409 break;
566f86ad 9410 }
1b27777a 9411 if (i < size)
566f86ad
MC
9412 goto out;
9413
1b27777a 9414 /* Selfboot format */
a9dc529d 9415 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9416 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9417 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC
9418 u8 *buf8 = (u8 *) buf, csum8 = 0;
9419
b9fc7dc5 9420 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC
9421 TG3_EEPROM_SB_REVISION_2) {
9422 /* For rev 2, the csum doesn't include the MBA. */
9423 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9424 csum8 += buf8[i];
9425 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9426 csum8 += buf8[i];
9427 } else {
9428 for (i = 0; i < size; i++)
9429 csum8 += buf8[i];
9430 }
1b27777a 9431
ad96b485
AB
9432 if (csum8 == 0) {
9433 err = 0;
9434 goto out;
9435 }
9436
9437 err = -EIO;
9438 goto out;
1b27777a 9439 }
566f86ad 9440
b9fc7dc5 9441 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC
9442 TG3_EEPROM_MAGIC_HW) {
9443 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9444 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9445 u8 *buf8 = (u8 *) buf;
b16250e3
MC
9446
9447 /* Separate the parity bits and the data bytes. */
9448 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9449 if ((i == 0) || (i == 8)) {
9450 int l;
9451 u8 msk;
9452
9453 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9454 parity[k++] = buf8[i] & msk;
9455 i++;
9456 }
9457 else if (i == 16) {
9458 int l;
9459 u8 msk;
9460
9461 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9462 parity[k++] = buf8[i] & msk;
9463 i++;
9464
9465 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9466 parity[k++] = buf8[i] & msk;
9467 i++;
9468 }
9469 data[j++] = buf8[i];
9470 }
9471
9472 err = -EIO;
9473 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9474 u8 hw8 = hweight8(data[i]);
9475
9476 if ((hw8 & 0x1) && parity[i])
9477 goto out;
9478 else if (!(hw8 & 0x1) && !parity[i])
9479 goto out;
9480 }
9481 err = 0;
9482 goto out;
9483 }
9484
566f86ad
MC
9485 /* Bootstrap checksum at offset 0x10 */
9486 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9487 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC
9488 goto out;
9489
9490 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9491 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC
9492 if (csum != be32_to_cpu(buf[0xfc/4]))
9493 goto out;
566f86ad
MC
9494
9495 err = 0;
9496
9497out:
9498 kfree(buf);
9499 return err;
9500}
9501
ca43007a
MC
9502#define TG3_SERDES_TIMEOUT_SEC 2
9503#define TG3_COPPER_TIMEOUT_SEC 6
9504
9505static int tg3_test_link(struct tg3 *tp)
9506{
9507 int i, max;
9508
9509 if (!netif_running(tp->dev))
9510 return -ENODEV;
9511
4c987487 9512 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC
9513 max = TG3_SERDES_TIMEOUT_SEC;
9514 else
9515 max = TG3_COPPER_TIMEOUT_SEC;
9516
9517 for (i = 0; i < max; i++) {
9518 if (netif_carrier_ok(tp->dev))
9519 return 0;
9520
9521 if (msleep_interruptible(1000))
9522 break;
9523 }
9524
9525 return -EIO;
9526}
9527
a71116d1 9528/* Only test the commonly used registers */
30ca3e37 9529static int tg3_test_registers(struct tg3 *tp)
a71116d1 9530{
b16250e3 9531 int i, is_5705, is_5750;
a71116d1
MC
9532 u32 offset, read_mask, write_mask, val, save_val, read_val;
9533 static struct {
9534 u16 offset;
9535 u16 flags;
9536#define TG3_FL_5705 0x1
9537#define TG3_FL_NOT_5705 0x2
9538#define TG3_FL_NOT_5788 0x4
b16250e3 9539#define TG3_FL_NOT_5750 0x8
a71116d1
MC
9540 u32 read_mask;
9541 u32 write_mask;
9542 } reg_tbl[] = {
9543 /* MAC Control Registers */
9544 { MAC_MODE, TG3_FL_NOT_5705,
9545 0x00000000, 0x00ef6f8c },
9546 { MAC_MODE, TG3_FL_5705,
9547 0x00000000, 0x01ef6b8c },
9548 { MAC_STATUS, TG3_FL_NOT_5705,
9549 0x03800107, 0x00000000 },
9550 { MAC_STATUS, TG3_FL_5705,
9551 0x03800100, 0x00000000 },
9552 { MAC_ADDR_0_HIGH, 0x0000,
9553 0x00000000, 0x0000ffff },
9554 { MAC_ADDR_0_LOW, 0x0000,
9555 0x00000000, 0xffffffff },
9556 { MAC_RX_MTU_SIZE, 0x0000,
9557 0x00000000, 0x0000ffff },
9558 { MAC_TX_MODE, 0x0000,
9559 0x00000000, 0x00000070 },
9560 { MAC_TX_LENGTHS, 0x0000,
9561 0x00000000, 0x00003fff },
9562 { MAC_RX_MODE, TG3_FL_NOT_5705,
9563 0x00000000, 0x000007fc },
9564 { MAC_RX_MODE, TG3_FL_5705,
9565 0x00000000, 0x000007dc },
9566 { MAC_HASH_REG_0, 0x0000,
9567 0x00000000, 0xffffffff },
9568 { MAC_HASH_REG_1, 0x0000,
9569 0x00000000, 0xffffffff },
9570 { MAC_HASH_REG_2, 0x0000,
9571 0x00000000, 0xffffffff },
9572 { MAC_HASH_REG_3, 0x0000,
9573 0x00000000, 0xffffffff },
9574
9575 /* Receive Data and Receive BD Initiator Control Registers. */
9576 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9577 0x00000000, 0xffffffff },
9578 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9579 0x00000000, 0xffffffff },
9580 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9581 0x00000000, 0x00000003 },
9582 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9583 0x00000000, 0xffffffff },
9584 { RCVDBDI_STD_BD+0, 0x0000,
9585 0x00000000, 0xffffffff },
9586 { RCVDBDI_STD_BD+4, 0x0000,
9587 0x00000000, 0xffffffff },
9588 { RCVDBDI_STD_BD+8, 0x0000,
9589 0x00000000, 0xffff0002 },
9590 { RCVDBDI_STD_BD+0xc, 0x0000,
9591 0x00000000, 0xffffffff },
6aa20a22 9592
a71116d1
MC
9593 /* Receive BD Initiator Control Registers. */
9594 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9595 0x00000000, 0xffffffff },
9596 { RCVBDI_STD_THRESH, TG3_FL_5705,
9597 0x00000000, 0x000003ff },
9598 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9599 0x00000000, 0xffffffff },
6aa20a22 9600
a71116d1
MC
9601 /* Host Coalescing Control Registers. */
9602 { HOSTCC_MODE, TG3_FL_NOT_5705,
9603 0x00000000, 0x00000004 },
9604 { HOSTCC_MODE, TG3_FL_5705,
9605 0x00000000, 0x000000f6 },
9606 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9607 0x00000000, 0xffffffff },
9608 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9609 0x00000000, 0x000003ff },
9610 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9611 0x00000000, 0xffffffff },
9612 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9613 0x00000000, 0x000003ff },
9614 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9615 0x00000000, 0xffffffff },
9616 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9617 0x00000000, 0x000000ff },
9618 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9619 0x00000000, 0xffffffff },
9620 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9621 0x00000000, 0x000000ff },
9622 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9623 0x00000000, 0xffffffff },
9624 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9625 0x00000000, 0xffffffff },
9626 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9627 0x00000000, 0xffffffff },
9628 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9629 0x00000000, 0x000000ff },
9630 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9631 0x00000000, 0xffffffff },
9632 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9633 0x00000000, 0x000000ff },
9634 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9635 0x00000000, 0xffffffff },
9636 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9637 0x00000000, 0xffffffff },
9638 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9639 0x00000000, 0xffffffff },
9640 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9641 0x00000000, 0xffffffff },
9642 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9643 0x00000000, 0xffffffff },
9644 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9645 0xffffffff, 0x00000000 },
9646 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9647 0xffffffff, 0x00000000 },
9648
9649 /* Buffer Manager Control Registers. */
b16250e3 9650 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9651 0x00000000, 0x007fff80 },
b16250e3 9652 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC
9653 0x00000000, 0x007fffff },
9654 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9655 0x00000000, 0x0000003f },
9656 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9657 0x00000000, 0x000001ff },
9658 { BUFMGR_MB_HIGH_WATER, 0x0000,
9659 0x00000000, 0x000001ff },
9660 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9661 0xffffffff, 0x00000000 },
9662 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9663 0xffffffff, 0x00000000 },
6aa20a22 9664
a71116d1
MC
9665 /* Mailbox Registers */
9666 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9667 0x00000000, 0x000001ff },
9668 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9669 0x00000000, 0x000001ff },
9670 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9671 0x00000000, 0x000007ff },
9672 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9673 0x00000000, 0x000001ff },
9674
9675 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9676 };
9677
b16250e3
MC
9678 is_5705 = is_5750 = 0;
9679 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9680 is_5705 = 1;
b16250e3
MC
9681 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9682 is_5750 = 1;
9683 }
a71116d1
MC
9684
9685 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9686 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9687 continue;
9688
9689 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9690 continue;
9691
9692 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9693 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9694 continue;
9695
b16250e3
MC
9696 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9697 continue;
9698
a71116d1
MC
9699 offset = (u32) reg_tbl[i].offset;
9700 read_mask = reg_tbl[i].read_mask;
9701 write_mask = reg_tbl[i].write_mask;
9702
9703 /* Save the original register content */
9704 save_val = tr32(offset);
9705
9706 /* Determine the read-only value. */
9707 read_val = save_val & read_mask;
9708
9709 /* Write zero to the register, then make sure the read-only bits
9710 * are not changed and the read/write bits are all zeros.
9711 */
9712 tw32(offset, 0);
9713
9714 val = tr32(offset);
9715
9716 /* Test the read-only and read/write bits. */
9717 if (((val & read_mask) != read_val) || (val & write_mask))
9718 goto out;
9719
9720 /* Write ones to all the bits defined by RdMask and WrMask, then
9721 * make sure the read-only bits are not changed and the
9722 * read/write bits are all ones.
9723 */
9724 tw32(offset, read_mask | write_mask);
9725
9726 val = tr32(offset);
9727
9728 /* Test the read-only bits. */
9729 if ((val & read_mask) != read_val)
9730 goto out;
9731
9732 /* Test the read/write bits. */
9733 if ((val & write_mask) != write_mask)
9734 goto out;
9735
9736 tw32(offset, save_val);
9737 }
9738
9739 return 0;
9740
9741out:
9f88f29f
MC
9742 if (netif_msg_hw(tp))
9743 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9744 offset);
a71116d1
MC
9745 tw32(offset, save_val);
9746 return -EIO;
9747}
9748
7942e1db
MC
9749static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9750{
f71e1309 9751 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC
9752 int i;
9753 u32 j;
9754
e9edda69 9755 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC
9756 for (j = 0; j < len; j += 4) {
9757 u32 val;
9758
9759 tg3_write_mem(tp, offset + j, test_pattern[i]);
9760 tg3_read_mem(tp, offset + j, &val);
9761 if (val != test_pattern[i])
9762 return -EIO;
9763 }
9764 }
9765 return 0;
9766}
9767
9768static int tg3_test_memory(struct tg3 *tp)
9769{
9770 static struct mem_entry {
9771 u32 offset;
9772 u32 len;
9773 } mem_tbl_570x[] = {
38690194 9774 { 0x00000000, 0x00b50},
7942e1db
MC
9775 { 0x00002000, 0x1c000},
9776 { 0xffffffff, 0x00000}
9777 }, mem_tbl_5705[] = {
9778 { 0x00000100, 0x0000c},
9779 { 0x00000200, 0x00008},
7942e1db
MC
9780 { 0x00004000, 0x00800},
9781 { 0x00006000, 0x01000},
9782 { 0x00008000, 0x02000},
9783 { 0x00010000, 0x0e000},
9784 { 0xffffffff, 0x00000}
79f4d13a
MC
9785 }, mem_tbl_5755[] = {
9786 { 0x00000200, 0x00008},
9787 { 0x00004000, 0x00800},
9788 { 0x00006000, 0x00800},
9789 { 0x00008000, 0x02000},
9790 { 0x00010000, 0x0c000},
9791 { 0xffffffff, 0x00000}
b16250e3
MC
9792 }, mem_tbl_5906[] = {
9793 { 0x00000200, 0x00008},
9794 { 0x00004000, 0x00400},
9795 { 0x00006000, 0x00400},
9796 { 0x00008000, 0x01000},
9797 { 0x00010000, 0x01000},
9798 { 0xffffffff, 0x00000}
7942e1db
MC
9799 };
9800 struct mem_entry *mem_tbl;
9801 int err = 0;
9802 int i;
9803
321d32a0
MC
9804 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9805 mem_tbl = mem_tbl_5755;
9806 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9807 mem_tbl = mem_tbl_5906;
9808 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9809 mem_tbl = mem_tbl_5705;
9810 else
7942e1db
MC
9811 mem_tbl = mem_tbl_570x;
9812
9813 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9814 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9815 mem_tbl[i].len)) != 0)
9816 break;
9817 }
6aa20a22 9818
7942e1db
MC
9819 return err;
9820}
9821
9f40dead
MC
9822#define TG3_MAC_LOOPBACK 0
9823#define TG3_PHY_LOOPBACK 1
9824
9825static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9826{
9f40dead 9827 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC
9828 u32 desc_idx;
9829 struct sk_buff *skb, *rx_skb;
9830 u8 *tx_data;
9831 dma_addr_t map;
9832 int num_pkts, tx_len, rx_len, i, err;
9833 struct tg3_rx_buffer_desc *desc;
898a56f8 9834 struct tg3_napi *tnapi, *rnapi;
21f581a5 9835 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 9836
898a56f8
MC
9837 tnapi = &tp->napi[0];
9838 rnapi = &tp->napi[0];
9839
9f40dead 9840 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC
9841 /* HW errata - mac loopback fails in some cases on 5780.
9842 * Normal traffic and PHY loopback are not affected by
9843 * errata.
9844 */
9845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9846 return 0;
9847
9f40dead 9848 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC
9849 MAC_MODE_PORT_INT_LPBACK;
9850 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9851 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC
9852 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9853 mac_mode |= MAC_MODE_PORT_MODE_MII;
9854 else
9855 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC
9856 tw32(MAC_MODE, mac_mode);
9857 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC
9858 u32 val;
9859
7f97a4bd
MC
9860 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9861 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC
9862 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9863 } else
9864 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9865
9ef8ca99
MC
9866 tg3_phy_toggle_automdix(tp, 0);
9867
3f7045c1 9868 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9869 udelay(40);
5d64ad34 9870
e8f3f6ca 9871 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC
9872 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9873 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9874 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC
9875 mac_mode |= MAC_MODE_PORT_MODE_MII;
9876 } else
9877 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9878
c94e3941
MC
9879 /* reset to prevent losing 1st rx packet intermittently */
9880 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9881 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9882 udelay(10);
9883 tw32_f(MAC_RX_MODE, tp->rx_mode);
9884 }
e8f3f6ca
MC
9885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9886 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9887 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9888 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9889 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC
9890 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9891 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9892 }
9f40dead 9893 tw32(MAC_MODE, mac_mode);
9f40dead
MC
9894 }
9895 else
9896 return -EINVAL;
c76949a6
MC
9897
9898 err = -EIO;
9899
c76949a6 9900 tx_len = 1514;
a20e9c62 9901 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ
9902 if (!skb)
9903 return -ENOMEM;
9904
c76949a6
MC
9905 tx_data = skb_put(skb, tx_len);
9906 memcpy(tx_data, tp->dev->dev_addr, 6);
9907 memset(tx_data + 6, 0x0, 8);
9908
9909 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9910
9911 for (i = 14; i < tx_len; i++)
9912 tx_data[i] = (u8) (i & 0xff);
9913
9914 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9915
9916 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9917 HOSTCC_MODE_NOW);
9918
9919 udelay(10);
9920
898a56f8 9921 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 9922
c76949a6
MC
9923 num_pkts = 0;
9924
9f40dead 9925 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9926
9f40dead 9927 tp->tx_prod++;
c76949a6
MC
9928 num_pkts++;
9929
9f40dead
MC
9930 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9931 tp->tx_prod);
09ee929c 9932 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC
9933
9934 udelay(10);
9935
3f7045c1
MC
9936 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9937 for (i = 0; i < 25; i++) {
c76949a6
MC
9938 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9939 HOSTCC_MODE_NOW);
9940
9941 udelay(10);
9942
898a56f8
MC
9943 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
9944 rx_idx = rnapi->hw_status->idx[0].rx_producer;
9f40dead 9945 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC
9946 (rx_idx == (rx_start_idx + num_pkts)))
9947 break;
9948 }
9949
9950 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9951 dev_kfree_skb(skb);
9952
9f40dead 9953 if (tx_idx != tp->tx_prod)
c76949a6
MC
9954 goto out;
9955
9956 if (rx_idx != rx_start_idx + num_pkts)
9957 goto out;
9958
9959 desc = &tp->rx_rcb[rx_start_idx];
9960 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9961 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9962 if (opaque_key != RXD_OPAQUE_RING_STD)
9963 goto out;
9964
9965 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9966 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9967 goto out;
9968
9969 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9970 if (rx_len != tx_len)
9971 goto out;
9972
21f581a5 9973 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 9974
21f581a5 9975 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC
9976 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9977
9978 for (i = 14; i < tx_len; i++) {
9979 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9980 goto out;
9981 }
9982 err = 0;
6aa20a22 9983
c76949a6
MC
9984 /* tg3_free_rings will unmap and free the rx_skb */
9985out:
9986 return err;
9987}
9988
9f40dead
MC
9989#define TG3_MAC_LOOPBACK_FAILED 1
9990#define TG3_PHY_LOOPBACK_FAILED 2
9991#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9992 TG3_PHY_LOOPBACK_FAILED)
9993
9994static int tg3_test_loopback(struct tg3 *tp)
9995{
9996 int err = 0;
9936bcf6 9997 u32 cpmuctrl = 0;
9f40dead
MC
9998
9999 if (!netif_running(tp->dev))
10000 return TG3_LOOPBACK_FAILED;
10001
b9ec6c1b
MC
10002 err = tg3_reset_hw(tp, 1);
10003 if (err)
10004 return TG3_LOOPBACK_FAILED;
9f40dead 10005
6833c043
MC
10006 /* Turn off gphy autopowerdown. */
10007 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10008 tg3_phy_toggle_apd(tp, false);
10009
321d32a0 10010 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC
10011 int i;
10012 u32 status;
10013
10014 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10015
10016 /* Wait for up to 40 microseconds to acquire lock. */
10017 for (i = 0; i < 4; i++) {
10018 status = tr32(TG3_CPMU_MUTEX_GNT);
10019 if (status == CPMU_MUTEX_GNT_DRIVER)
10020 break;
10021 udelay(10);
10022 }
10023
10024 if (status != CPMU_MUTEX_GNT_DRIVER)
10025 return TG3_LOOPBACK_FAILED;
10026
b2a5c19c 10027 /* Turn off link-based power management. */
e875093c 10028 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC
10029 tw32(TG3_CPMU_CTRL,
10030 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10031 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC
10032 }
10033
9f40dead
MC
10034 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10035 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10036
321d32a0 10037 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC
10038 tw32(TG3_CPMU_CTRL, cpmuctrl);
10039
10040 /* Release the mutex */
10041 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10042 }
10043
dd477003
MC
10044 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10045 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC
10046 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10047 err |= TG3_PHY_LOOPBACK_FAILED;
10048 }
10049
6833c043
MC
10050 /* Re-enable gphy autopowerdown. */
10051 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10052 tg3_phy_toggle_apd(tp, true);
10053
9f40dead
MC
10054 return err;
10055}
10056
4cafd3f5
MC
10057static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10058 u64 *data)
10059{
566f86ad
MC
10060 struct tg3 *tp = netdev_priv(dev);
10061
bc1c7567
MC
10062 if (tp->link_config.phy_is_low_power)
10063 tg3_set_power_state(tp, PCI_D0);
10064
566f86ad
MC
10065 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10066
10067 if (tg3_test_nvram(tp) != 0) {
10068 etest->flags |= ETH_TEST_FL_FAILED;
10069 data[0] = 1;
10070 }
ca43007a
MC
10071 if (tg3_test_link(tp) != 0) {
10072 etest->flags |= ETH_TEST_FL_FAILED;
10073 data[1] = 1;
10074 }
a71116d1 10075 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10076 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC
10077
10078 if (netif_running(dev)) {
b02fd9e3 10079 tg3_phy_stop(tp);
a71116d1 10080 tg3_netif_stop(tp);
bbe832c0
MC
10081 irq_sync = 1;
10082 }
a71116d1 10083
bbe832c0 10084 tg3_full_lock(tp, irq_sync);
a71116d1
MC
10085
10086 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10087 err = tg3_nvram_lock(tp);
a71116d1
MC
10088 tg3_halt_cpu(tp, RX_CPU_BASE);
10089 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10090 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC
10091 if (!err)
10092 tg3_nvram_unlock(tp);
a71116d1 10093
d9ab5ad1
MC
10094 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10095 tg3_phy_reset(tp);
10096
a71116d1
MC
10097 if (tg3_test_registers(tp) != 0) {
10098 etest->flags |= ETH_TEST_FL_FAILED;
10099 data[2] = 1;
10100 }
7942e1db
MC
10101 if (tg3_test_memory(tp) != 0) {
10102 etest->flags |= ETH_TEST_FL_FAILED;
10103 data[3] = 1;
10104 }
9f40dead 10105 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10106 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10107
f47c11ee
DM
10108 tg3_full_unlock(tp);
10109
d4bc3927
MC
10110 if (tg3_test_interrupt(tp) != 0) {
10111 etest->flags |= ETH_TEST_FL_FAILED;
10112 data[5] = 1;
10113 }
f47c11ee
DM
10114
10115 tg3_full_lock(tp, 0);
d4bc3927 10116
a71116d1
MC
10117 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10118 if (netif_running(dev)) {
10119 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC
10120 err2 = tg3_restart_hw(tp, 1);
10121 if (!err2)
b9ec6c1b 10122 tg3_netif_start(tp);
a71116d1 10123 }
f47c11ee
DM
10124
10125 tg3_full_unlock(tp);
b02fd9e3
MC
10126
10127 if (irq_sync && !err2)
10128 tg3_phy_start(tp);
a71116d1 10129 }
bc1c7567
MC
10130 if (tp->link_config.phy_is_low_power)
10131 tg3_set_power_state(tp, PCI_D3hot);
10132
4cafd3f5
MC
10133}
10134
1da177e4
LT
10135static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10136{
10137 struct mii_ioctl_data *data = if_mii(ifr);
10138 struct tg3 *tp = netdev_priv(dev);
10139 int err;
10140
b02fd9e3
MC
10141 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10142 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10143 return -EAGAIN;
298cf9be 10144 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC
10145 }
10146
1da177e4
LT
10147 switch(cmd) {
10148 case SIOCGMIIPHY:
10149 data->phy_id = PHY_ADDR;
10150
10151 /* fallthru */
10152 case SIOCGMIIREG: {
10153 u32 mii_regval;
10154
10155 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10156 break; /* We have no PHY */
10157
bc1c7567
MC
10158 if (tp->link_config.phy_is_low_power)
10159 return -EAGAIN;
10160
f47c11ee 10161 spin_lock_bh(&tp->lock);
1da177e4 10162 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10163 spin_unlock_bh(&tp->lock);
1da177e4
LT
10164
10165 data->val_out = mii_regval;
10166
10167 return err;
10168 }
10169
10170 case SIOCSMIIREG:
10171 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10172 break; /* We have no PHY */
10173
10174 if (!capable(CAP_NET_ADMIN))
10175 return -EPERM;
10176
bc1c7567
MC
10177 if (tp->link_config.phy_is_low_power)
10178 return -EAGAIN;
10179
f47c11ee 10180 spin_lock_bh(&tp->lock);
1da177e4 10181 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10182 spin_unlock_bh(&tp->lock);
1da177e4
LT
10183
10184 return err;
10185
10186 default:
10187 /* do nothing */
10188 break;
10189 }
10190 return -EOPNOTSUPP;
10191}
10192
10193#if TG3_VLAN_TAG_USED
10194static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10195{
10196 struct tg3 *tp = netdev_priv(dev);
10197
844b3eed
MC
10198 if (!netif_running(dev)) {
10199 tp->vlgrp = grp;
10200 return;
10201 }
10202
10203 tg3_netif_stop(tp);
29315e87 10204
f47c11ee 10205 tg3_full_lock(tp, 0);
1da177e4
LT
10206
10207 tp->vlgrp = grp;
10208
10209 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10210 __tg3_set_rx_mode(dev);
10211
844b3eed 10212 tg3_netif_start(tp);
46966545
MC
10213
10214 tg3_full_unlock(tp);
1da177e4 10215}
1da177e4
LT
10216#endif
10217
15f9850d
DM
10218static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10219{
10220 struct tg3 *tp = netdev_priv(dev);
10221
10222 memcpy(ec, &tp->coal, sizeof(*ec));
10223 return 0;
10224}
10225
d244c892
MC
10226static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10227{
10228 struct tg3 *tp = netdev_priv(dev);
10229 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10230 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10231
10232 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10233 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10234 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10235 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10236 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10237 }
10238
10239 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10240 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10241 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10242 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10243 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10244 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10245 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10246 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10247 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10248 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10249 return -EINVAL;
10250
10251 /* No rx interrupts will be generated if both are zero */
10252 if ((ec->rx_coalesce_usecs == 0) &&
10253 (ec->rx_max_coalesced_frames == 0))
10254 return -EINVAL;
10255
10256 /* No tx interrupts will be generated if both are zero */
10257 if ((ec->tx_coalesce_usecs == 0) &&
10258 (ec->tx_max_coalesced_frames == 0))
10259 return -EINVAL;
10260
10261 /* Only copy relevant parameters, ignore all others. */
10262 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10263 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10264 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10265 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10266 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10267 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10268 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10269 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10270 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10271
10272 if (netif_running(dev)) {
10273 tg3_full_lock(tp, 0);
10274 __tg3_set_coalesce(tp, &tp->coal);
10275 tg3_full_unlock(tp);
10276 }
10277 return 0;
10278}
10279
7282d491 10280static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT
10281 .get_settings = tg3_get_settings,
10282 .set_settings = tg3_set_settings,
10283 .get_drvinfo = tg3_get_drvinfo,
10284 .get_regs_len = tg3_get_regs_len,
10285 .get_regs = tg3_get_regs,
10286 .get_wol = tg3_get_wol,
10287 .set_wol = tg3_set_wol,
10288 .get_msglevel = tg3_get_msglevel,
10289 .set_msglevel = tg3_set_msglevel,
10290 .nway_reset = tg3_nway_reset,
10291 .get_link = ethtool_op_get_link,
10292 .get_eeprom_len = tg3_get_eeprom_len,
10293 .get_eeprom = tg3_get_eeprom,
10294 .set_eeprom = tg3_set_eeprom,
10295 .get_ringparam = tg3_get_ringparam,
10296 .set_ringparam = tg3_set_ringparam,
10297 .get_pauseparam = tg3_get_pauseparam,
10298 .set_pauseparam = tg3_set_pauseparam,
10299 .get_rx_csum = tg3_get_rx_csum,
10300 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10301 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10302 .set_sg = ethtool_op_set_sg,
1da177e4 10303 .set_tso = tg3_set_tso,
4cafd3f5 10304 .self_test = tg3_self_test,
1da177e4 10305 .get_strings = tg3_get_strings,
4009a93d 10306 .phys_id = tg3_phys_id,
1da177e4 10307 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10308 .get_coalesce = tg3_get_coalesce,
d244c892 10309 .set_coalesce = tg3_set_coalesce,
b9f2c044 10310 .get_sset_count = tg3_get_sset_count,
1da177e4
LT
10311};
10312
10313static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10314{
1b27777a 10315 u32 cursize, val, magic;
1da177e4
LT
10316
10317 tp->nvram_size = EEPROM_CHIP_SIZE;
10318
e4f34110 10319 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT
10320 return;
10321
b16250e3
MC
10322 if ((magic != TG3_EEPROM_MAGIC) &&
10323 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10324 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT
10325 return;
10326
10327 /*
10328 * Size the chip by reading offsets at increasing powers of two.
10329 * When we encounter our validation signature, we know the addressing
10330 * has wrapped around, and thus have our chip size.
10331 */
1b27777a 10332 cursize = 0x10;
1da177e4
LT
10333
10334 while (cursize < tp->nvram_size) {
e4f34110 10335 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT
10336 return;
10337
1820180b 10338 if (val == magic)
1da177e4
LT
10339 break;
10340
10341 cursize <<= 1;
10342 }
10343
10344 tp->nvram_size = cursize;
10345}
6aa20a22 10346
1da177e4
LT
10347static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10348{
10349 u32 val;
10350
df259d8c
MC
10351 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10352 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC
10353 return;
10354
10355 /* Selfboot format */
1820180b 10356 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC
10357 tg3_get_eeprom_size(tp);
10358 return;
10359 }
10360
6d348f2c 10361 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10362 if (val != 0) {
6d348f2c
MC
10363 /* This is confusing. We want to operate on the
10364 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10365 * call will read from NVRAM and byteswap the data
10366 * according to the byteswapping settings for all
10367 * other register accesses. This ensures the data we
10368 * want will always reside in the lower 16-bits.
10369 * However, the data in NVRAM is in LE format, which
10370 * means the data from the NVRAM read will always be
10371 * opposite the endianness of the CPU. The 16-bit
10372 * byteswap then brings the data to CPU endianness.
10373 */
10374 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT
10375 return;
10376 }
10377 }
fd1122a2 10378 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT
10379}
10380
10381static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10382{
10383 u32 nvcfg1;
10384
10385 nvcfg1 = tr32(NVRAM_CFG1);
10386 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10387 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10388 } else {
1da177e4
LT
10389 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10390 tw32(NVRAM_CFG1, nvcfg1);
10391 }
10392
4c987487 10393 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10394 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10395 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC
10396 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10397 tp->nvram_jedecnum = JEDEC_ATMEL;
10398 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10399 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10400 break;
10401 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10402 tp->nvram_jedecnum = JEDEC_ATMEL;
10403 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10404 break;
10405 case FLASH_VENDOR_ATMEL_EEPROM:
10406 tp->nvram_jedecnum = JEDEC_ATMEL;
10407 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10408 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10409 break;
10410 case FLASH_VENDOR_ST:
10411 tp->nvram_jedecnum = JEDEC_ST;
10412 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10413 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10414 break;
10415 case FLASH_VENDOR_SAIFUN:
10416 tp->nvram_jedecnum = JEDEC_SAIFUN;
10417 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10418 break;
10419 case FLASH_VENDOR_SST_SMALL:
10420 case FLASH_VENDOR_SST_LARGE:
10421 tp->nvram_jedecnum = JEDEC_SST;
10422 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10423 break;
1da177e4 10424 }
8590a603 10425 } else {
1da177e4
LT
10426 tp->nvram_jedecnum = JEDEC_ATMEL;
10427 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10429 }
10430}
10431
361b4ac2
MC
10432static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10433{
10434 u32 nvcfg1;
10435
10436 nvcfg1 = tr32(NVRAM_CFG1);
10437
e6af301b
MC
10438 /* NVRAM protection for TPM */
10439 if (nvcfg1 & (1 << 27))
10440 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10441
361b4ac2 10442 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC
10443 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10444 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10445 tp->nvram_jedecnum = JEDEC_ATMEL;
10446 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10447 break;
10448 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10449 tp->nvram_jedecnum = JEDEC_ATMEL;
10450 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10451 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10452 break;
10453 case FLASH_5752VENDOR_ST_M45PE10:
10454 case FLASH_5752VENDOR_ST_M45PE20:
10455 case FLASH_5752VENDOR_ST_M45PE40:
10456 tp->nvram_jedecnum = JEDEC_ST;
10457 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10458 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10459 break;
361b4ac2
MC
10460 }
10461
10462 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10463 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC
10464 case FLASH_5752PAGE_SIZE_256:
10465 tp->nvram_pagesize = 256;
10466 break;
10467 case FLASH_5752PAGE_SIZE_512:
10468 tp->nvram_pagesize = 512;
10469 break;
10470 case FLASH_5752PAGE_SIZE_1K:
10471 tp->nvram_pagesize = 1024;
10472 break;
10473 case FLASH_5752PAGE_SIZE_2K:
10474 tp->nvram_pagesize = 2048;
10475 break;
10476 case FLASH_5752PAGE_SIZE_4K:
10477 tp->nvram_pagesize = 4096;
10478 break;
10479 case FLASH_5752PAGE_SIZE_264:
10480 tp->nvram_pagesize = 264;
10481 break;
361b4ac2 10482 }
8590a603 10483 } else {
361b4ac2
MC
10484 /* For eeprom, set pagesize to maximum eeprom size */
10485 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10486
10487 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10488 tw32(NVRAM_CFG1, nvcfg1);
10489 }
10490}
10491
d3c7b886
MC
10492static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10493{
989a9d23 10494 u32 nvcfg1, protect = 0;
d3c7b886
MC
10495
10496 nvcfg1 = tr32(NVRAM_CFG1);
10497
10498 /* NVRAM protection for TPM */
989a9d23 10499 if (nvcfg1 & (1 << 27)) {
d3c7b886 10500 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC
10501 protect = 1;
10502 }
d3c7b886 10503
989a9d23
MC
10504 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10505 switch (nvcfg1) {
8590a603
MC
10506 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10507 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10508 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10509 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10510 tp->nvram_jedecnum = JEDEC_ATMEL;
10511 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10512 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10513 tp->nvram_pagesize = 264;
10514 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10515 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10516 tp->nvram_size = (protect ? 0x3e200 :
10517 TG3_NVRAM_SIZE_512KB);
10518 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10519 tp->nvram_size = (protect ? 0x1f200 :
10520 TG3_NVRAM_SIZE_256KB);
10521 else
10522 tp->nvram_size = (protect ? 0x1f200 :
10523 TG3_NVRAM_SIZE_128KB);
10524 break;
10525 case FLASH_5752VENDOR_ST_M45PE10:
10526 case FLASH_5752VENDOR_ST_M45PE20:
10527 case FLASH_5752VENDOR_ST_M45PE40:
10528 tp->nvram_jedecnum = JEDEC_ST;
10529 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10530 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10531 tp->nvram_pagesize = 256;
10532 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10533 tp->nvram_size = (protect ?
10534 TG3_NVRAM_SIZE_64KB :
10535 TG3_NVRAM_SIZE_128KB);
10536 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10537 tp->nvram_size = (protect ?
10538 TG3_NVRAM_SIZE_64KB :
10539 TG3_NVRAM_SIZE_256KB);
10540 else
10541 tp->nvram_size = (protect ?
10542 TG3_NVRAM_SIZE_128KB :
10543 TG3_NVRAM_SIZE_512KB);
10544 break;
d3c7b886
MC
10545 }
10546}
10547
1b27777a
MC
10548static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10549{
10550 u32 nvcfg1;
10551
10552 nvcfg1 = tr32(NVRAM_CFG1);
10553
10554 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC
10555 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10556 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10557 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10558 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10559 tp->nvram_jedecnum = JEDEC_ATMEL;
10560 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10561 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10562
8590a603
MC
10563 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10564 tw32(NVRAM_CFG1, nvcfg1);
10565 break;
10566 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10567 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10568 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10569 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10570 tp->nvram_jedecnum = JEDEC_ATMEL;
10571 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10572 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10573 tp->nvram_pagesize = 264;
10574 break;
10575 case FLASH_5752VENDOR_ST_M45PE10:
10576 case FLASH_5752VENDOR_ST_M45PE20:
10577 case FLASH_5752VENDOR_ST_M45PE40:
10578 tp->nvram_jedecnum = JEDEC_ST;
10579 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10580 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10581 tp->nvram_pagesize = 256;
10582 break;
1b27777a
MC
10583 }
10584}
10585
6b91fa02
MC
10586static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10587{
10588 u32 nvcfg1, protect = 0;
10589
10590 nvcfg1 = tr32(NVRAM_CFG1);
10591
10592 /* NVRAM protection for TPM */
10593 if (nvcfg1 & (1 << 27)) {
10594 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10595 protect = 1;
10596 }
10597
10598 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10599 switch (nvcfg1) {
8590a603
MC
10600 case FLASH_5761VENDOR_ATMEL_ADB021D:
10601 case FLASH_5761VENDOR_ATMEL_ADB041D:
10602 case FLASH_5761VENDOR_ATMEL_ADB081D:
10603 case FLASH_5761VENDOR_ATMEL_ADB161D:
10604 case FLASH_5761VENDOR_ATMEL_MDB021D:
10605 case FLASH_5761VENDOR_ATMEL_MDB041D:
10606 case FLASH_5761VENDOR_ATMEL_MDB081D:
10607 case FLASH_5761VENDOR_ATMEL_MDB161D:
10608 tp->nvram_jedecnum = JEDEC_ATMEL;
10609 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10610 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10611 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10612 tp->nvram_pagesize = 256;
10613 break;
10614 case FLASH_5761VENDOR_ST_A_M45PE20:
10615 case FLASH_5761VENDOR_ST_A_M45PE40:
10616 case FLASH_5761VENDOR_ST_A_M45PE80:
10617 case FLASH_5761VENDOR_ST_A_M45PE16:
10618 case FLASH_5761VENDOR_ST_M_M45PE20:
10619 case FLASH_5761VENDOR_ST_M_M45PE40:
10620 case FLASH_5761VENDOR_ST_M_M45PE80:
10621 case FLASH_5761VENDOR_ST_M_M45PE16:
10622 tp->nvram_jedecnum = JEDEC_ST;
10623 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10624 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10625 tp->nvram_pagesize = 256;
10626 break;
6b91fa02
MC
10627 }
10628
10629 if (protect) {
10630 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10631 } else {
10632 switch (nvcfg1) {
8590a603
MC
10633 case FLASH_5761VENDOR_ATMEL_ADB161D:
10634 case FLASH_5761VENDOR_ATMEL_MDB161D:
10635 case FLASH_5761VENDOR_ST_A_M45PE16:
10636 case FLASH_5761VENDOR_ST_M_M45PE16:
10637 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10638 break;
10639 case FLASH_5761VENDOR_ATMEL_ADB081D:
10640 case FLASH_5761VENDOR_ATMEL_MDB081D:
10641 case FLASH_5761VENDOR_ST_A_M45PE80:
10642 case FLASH_5761VENDOR_ST_M_M45PE80:
10643 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10644 break;
10645 case FLASH_5761VENDOR_ATMEL_ADB041D:
10646 case FLASH_5761VENDOR_ATMEL_MDB041D:
10647 case FLASH_5761VENDOR_ST_A_M45PE40:
10648 case FLASH_5761VENDOR_ST_M_M45PE40:
10649 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10650 break;
10651 case FLASH_5761VENDOR_ATMEL_ADB021D:
10652 case FLASH_5761VENDOR_ATMEL_MDB021D:
10653 case FLASH_5761VENDOR_ST_A_M45PE20:
10654 case FLASH_5761VENDOR_ST_M_M45PE20:
10655 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10656 break;
6b91fa02
MC
10657 }
10658 }
10659}
10660
b5d3772c
MC
10661static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10662{
10663 tp->nvram_jedecnum = JEDEC_ATMEL;
10664 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10665 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10666}
10667
321d32a0
MC
10668static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10669{
10670 u32 nvcfg1;
10671
10672 nvcfg1 = tr32(NVRAM_CFG1);
10673
10674 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10675 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10676 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10677 tp->nvram_jedecnum = JEDEC_ATMEL;
10678 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10679 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10680
10681 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10682 tw32(NVRAM_CFG1, nvcfg1);
10683 return;
10684 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10685 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10686 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10687 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10688 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10689 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10690 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10691 tp->nvram_jedecnum = JEDEC_ATMEL;
10692 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10693 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10694
10695 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10696 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10697 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10698 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10699 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10700 break;
10701 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10702 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10703 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10704 break;
10705 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10706 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10707 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10708 break;
10709 }
10710 break;
10711 case FLASH_5752VENDOR_ST_M45PE10:
10712 case FLASH_5752VENDOR_ST_M45PE20:
10713 case FLASH_5752VENDOR_ST_M45PE40:
10714 tp->nvram_jedecnum = JEDEC_ST;
10715 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10716 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10717
10718 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10719 case FLASH_5752VENDOR_ST_M45PE10:
10720 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10721 break;
10722 case FLASH_5752VENDOR_ST_M45PE20:
10723 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10724 break;
10725 case FLASH_5752VENDOR_ST_M45PE40:
10726 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10727 break;
10728 }
10729 break;
10730 default:
df259d8c 10731 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC
10732 return;
10733 }
10734
10735 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10736 case FLASH_5752PAGE_SIZE_256:
10737 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10738 tp->nvram_pagesize = 256;
10739 break;
10740 case FLASH_5752PAGE_SIZE_512:
10741 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10742 tp->nvram_pagesize = 512;
10743 break;
10744 case FLASH_5752PAGE_SIZE_1K:
10745 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10746 tp->nvram_pagesize = 1024;
10747 break;
10748 case FLASH_5752PAGE_SIZE_2K:
10749 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10750 tp->nvram_pagesize = 2048;
10751 break;
10752 case FLASH_5752PAGE_SIZE_4K:
10753 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10754 tp->nvram_pagesize = 4096;
10755 break;
10756 case FLASH_5752PAGE_SIZE_264:
10757 tp->nvram_pagesize = 264;
10758 break;
10759 case FLASH_5752PAGE_SIZE_528:
10760 tp->nvram_pagesize = 528;
10761 break;
10762 }
10763}
10764
1da177e4
LT
10765/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10766static void __devinit tg3_nvram_init(struct tg3 *tp)
10767{
1da177e4
LT
10768 tw32_f(GRC_EEPROM_ADDR,
10769 (EEPROM_ADDR_FSM_RESET |
10770 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10771 EEPROM_ADDR_CLKPERD_SHIFT)));
10772
9d57f01c 10773 msleep(1);
1da177e4
LT
10774
10775 /* Enable seeprom accesses. */
10776 tw32_f(GRC_LOCAL_CTRL,
10777 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10778 udelay(100);
10779
10780 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10781 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10782 tp->tg3_flags |= TG3_FLAG_NVRAM;
10783
ec41c7df
MC
10784 if (tg3_nvram_lock(tp)) {
10785 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10786 "tg3_nvram_init failed.\n", tp->dev->name);
10787 return;
10788 }
e6af301b 10789 tg3_enable_nvram_access(tp);
1da177e4 10790
989a9d23
MC
10791 tp->nvram_size = 0;
10792
361b4ac2
MC
10793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10794 tg3_get_5752_nvram_info(tp);
d3c7b886
MC
10795 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10796 tg3_get_5755_nvram_info(tp);
d30cdd28 10797 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC
10798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10800 tg3_get_5787_nvram_info(tp);
6b91fa02
MC
10801 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10802 tg3_get_5761_nvram_info(tp);
b5d3772c
MC
10803 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10804 tg3_get_5906_nvram_info(tp);
321d32a0
MC
10805 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10806 tg3_get_57780_nvram_info(tp);
361b4ac2
MC
10807 else
10808 tg3_get_nvram_info(tp);
10809
989a9d23
MC
10810 if (tp->nvram_size == 0)
10811 tg3_get_nvram_size(tp);
1da177e4 10812
e6af301b 10813 tg3_disable_nvram_access(tp);
381291b7 10814 tg3_nvram_unlock(tp);
1da177e4
LT
10815
10816 } else {
10817 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10818
10819 tg3_get_eeprom_size(tp);
10820 }
10821}
10822
1da177e4
LT
10823static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10824 u32 offset, u32 len, u8 *buf)
10825{
10826 int i, j, rc = 0;
10827 u32 val;
10828
10829 for (i = 0; i < len; i += 4) {
b9fc7dc5 10830 u32 addr;
a9dc529d 10831 __be32 data;
1da177e4
LT
10832
10833 addr = offset + i;
10834
10835 memcpy(&data, buf + i, 4);
10836
62cedd11
MC
10837 /*
10838 * The SEEPROM interface expects the data to always be opposite
10839 * the native endian format. We accomplish this by reversing
10840 * all the operations that would have been performed on the
10841 * data from a call to tg3_nvram_read_be32().
10842 */
10843 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT
10844
10845 val = tr32(GRC_EEPROM_ADDR);
10846 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10847
10848 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10849 EEPROM_ADDR_READ);
10850 tw32(GRC_EEPROM_ADDR, val |
10851 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10852 (addr & EEPROM_ADDR_ADDR_MASK) |
10853 EEPROM_ADDR_START |
10854 EEPROM_ADDR_WRITE);
6aa20a22 10855
9d57f01c 10856 for (j = 0; j < 1000; j++) {
1da177e4
LT
10857 val = tr32(GRC_EEPROM_ADDR);
10858
10859 if (val & EEPROM_ADDR_COMPLETE)
10860 break;
9d57f01c 10861 msleep(1);
1da177e4
LT
10862 }
10863 if (!(val & EEPROM_ADDR_COMPLETE)) {
10864 rc = -EBUSY;
10865 break;
10866 }
10867 }
10868
10869 return rc;
10870}
10871
10872/* offset and length are dword aligned */
10873static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10874 u8 *buf)
10875{
10876 int ret = 0;
10877 u32 pagesize = tp->nvram_pagesize;
10878 u32 pagemask = pagesize - 1;
10879 u32 nvram_cmd;
10880 u8 *tmp;
10881
10882 tmp = kmalloc(pagesize, GFP_KERNEL);
10883 if (tmp == NULL)
10884 return -ENOMEM;
10885
10886 while (len) {
10887 int j;
e6af301b 10888 u32 phy_addr, page_off, size;
1da177e4
LT
10889
10890 phy_addr = offset & ~pagemask;
6aa20a22 10891
1da177e4 10892 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC
10893 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10894 (__be32 *) (tmp + j));
10895 if (ret)
1da177e4
LT
10896 break;
10897 }
10898 if (ret)
10899 break;
10900
10901 page_off = offset & pagemask;
10902 size = pagesize;
10903 if (len < size)
10904 size = len;
10905
10906 len -= size;
10907
10908 memcpy(tmp + page_off, buf, size);
10909
10910 offset = offset + (pagesize - page_off);
10911
e6af301b 10912 tg3_enable_nvram_access(tp);
1da177e4
LT
10913
10914 /*
10915 * Before we can erase the flash page, we need
10916 * to issue a special "write enable" command.
10917 */
10918 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10919
10920 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10921 break;
10922
10923 /* Erase the target page */
10924 tw32(NVRAM_ADDR, phy_addr);
10925
10926 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10927 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10928
10929 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10930 break;
10931
10932 /* Issue another write enable to start the write. */
10933 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10934
10935 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10936 break;
10937
10938 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10939 __be32 data;
1da177e4 10940
b9fc7dc5 10941 data = *((__be32 *) (tmp + j));
a9dc529d 10942
b9fc7dc5 10943 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT
10944
10945 tw32(NVRAM_ADDR, phy_addr + j);
10946
10947 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10948 NVRAM_CMD_WR;
10949
10950 if (j == 0)
10951 nvram_cmd |= NVRAM_CMD_FIRST;
10952 else if (j == (pagesize - 4))
10953 nvram_cmd |= NVRAM_CMD_LAST;
10954
10955 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10956 break;
10957 }
10958 if (ret)
10959 break;
10960 }
10961
10962 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10963 tg3_nvram_exec_cmd(tp, nvram_cmd);
10964
10965 kfree(tmp);
10966
10967 return ret;
10968}
10969
10970/* offset and length are dword aligned */
10971static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10972 u8 *buf)
10973{
10974 int i, ret = 0;
10975
10976 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV
10977 u32 page_off, phy_addr, nvram_cmd;
10978 __be32 data;
1da177e4
LT
10979
10980 memcpy(&data, buf + i, 4);
b9fc7dc5 10981 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT
10982
10983 page_off = offset % tp->nvram_pagesize;
10984
1820180b 10985 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT
10986
10987 tw32(NVRAM_ADDR, phy_addr);
10988
10989 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10990
10991 if ((page_off == 0) || (i == 0))
10992 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10993 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT
10994 nvram_cmd |= NVRAM_CMD_LAST;
10995
10996 if (i == (len - 4))
10997 nvram_cmd |= NVRAM_CMD_LAST;
10998
321d32a0
MC
10999 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11000 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC
11001 (tp->nvram_jedecnum == JEDEC_ST) &&
11002 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT
11003
11004 if ((ret = tg3_nvram_exec_cmd(tp,
11005 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11006 NVRAM_CMD_DONE)))
11007
11008 break;
11009 }
11010 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11011 /* We always do complete word writes to eeprom. */
11012 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11013 }
11014
11015 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11016 break;
11017 }
11018 return ret;
11019}
11020
11021/* offset and length are dword aligned */
11022static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11023{
11024 int ret;
11025
1da177e4 11026 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC
11027 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11028 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT
11029 udelay(40);
11030 }
11031
11032 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11033 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11034 }
11035 else {
11036 u32 grc_mode;
11037
ec41c7df
MC
11038 ret = tg3_nvram_lock(tp);
11039 if (ret)
11040 return ret;
1da177e4 11041
e6af301b
MC
11042 tg3_enable_nvram_access(tp);
11043 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11044 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11045 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT
11046
11047 grc_mode = tr32(GRC_MODE);
11048 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11049
11050 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11051 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11052
11053 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11054 buf);
11055 }
11056 else {
11057 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11058 buf);
11059 }
11060
11061 grc_mode = tr32(GRC_MODE);
11062 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11063
e6af301b 11064 tg3_disable_nvram_access(tp);
1da177e4
LT
11065 tg3_nvram_unlock(tp);
11066 }
11067
11068 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11069 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT
11070 udelay(40);
11071 }
11072
11073 return ret;
11074}
11075
11076struct subsys_tbl_ent {
11077 u16 subsys_vendor, subsys_devid;
11078 u32 phy_id;
11079};
11080
11081static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11082 /* Broadcom boards. */
11083 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11084 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11085 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11086 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11087 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11088 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11089 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11090 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11091 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11092 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11093 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11094
11095 /* 3com boards. */
11096 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11097 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11098 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11099 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11100 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11101
11102 /* DELL boards. */
11103 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11104 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11105 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11106 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11107
11108 /* Compaq boards. */
11109 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11110 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11111 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11112 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11113 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11114
11115 /* IBM boards. */
11116 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11117};
11118
11119static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11120{
11121 int i;
11122
11123 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11124 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11125 tp->pdev->subsystem_vendor) &&
11126 (subsys_id_to_phy_id[i].subsys_devid ==
11127 tp->pdev->subsystem_device))
11128 return &subsys_id_to_phy_id[i];
11129 }
11130 return NULL;
11131}
11132
7d0c41ef 11133static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11134{
1da177e4 11135 u32 val;
caf636c7
MC
11136 u16 pmcsr;
11137
11138 /* On some early chips the SRAM cannot be accessed in D3hot state,
11139 * so need make sure we're in D0.
11140 */
11141 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11142 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11143 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11144 msleep(1);
7d0c41ef
MC
11145
11146 /* Make sure register accesses (indirect or otherwise)
11147 * will function correctly.
11148 */
11149 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11150 tp->misc_host_ctrl);
1da177e4 11151
f49639e6
DM
11152 /* The memory arbiter has to be enabled in order for SRAM accesses
11153 * to succeed. Normally on powerup the tg3 chip firmware will make
11154 * sure it is enabled, but other entities such as system netboot
11155 * code might disable it.
11156 */
11157 val = tr32(MEMARB_MODE);
11158 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11159
1da177e4 11160 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC
11161 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11162
a85feb8c
GZ
11163 /* Assume an onboard device and WOL capable by default. */
11164 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11165
b5d3772c 11166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11167 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11168 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC
11169 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11170 }
0527ba35
MC
11171 val = tr32(VCPU_CFGSHDW);
11172 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11173 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11174 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11175 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11176 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11177 goto done;
b5d3772c
MC
11178 }
11179
1da177e4
LT
11180 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11181 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11182 u32 nic_cfg, led_cfg;
a9daf367 11183 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11184 int eeprom_phy_serdes = 0;
1da177e4
LT
11185
11186 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11187 tp->nic_sram_data_cfg = nic_cfg;
11188
11189 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11190 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11191 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11192 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11193 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11194 (ver > 0) && (ver < 0x100))
11195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11196
a9daf367
MC
11197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11198 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11199
1da177e4
LT
11200 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11201 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11202 eeprom_phy_serdes = 1;
11203
11204 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11205 if (nic_phy_id != 0) {
11206 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11207 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11208
11209 eeprom_phy_id = (id1 >> 16) << 10;
11210 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11211 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11212 } else
11213 eeprom_phy_id = 0;
11214
7d0c41ef 11215 tp->phy_id = eeprom_phy_id;
747e8f8b 11216 if (eeprom_phy_serdes) {
a4e2b347 11217 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC
11218 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11219 else
11220 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11221 }
7d0c41ef 11222
cbf46853 11223 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT
11224 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11225 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11226 else
1da177e4
LT
11227 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11228
11229 switch (led_cfg) {
11230 default:
11231 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11232 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11233 break;
11234
11235 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11236 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11237 break;
11238
11239 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11240 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC
11241
11242 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11243 * read on some older 5700/5701 bootcode.
11244 */
11245 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11246 ASIC_REV_5700 ||
11247 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11248 ASIC_REV_5701)
11249 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11250
1da177e4
LT
11251 break;
11252
11253 case SHASTA_EXT_LED_SHARED:
11254 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11255 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11256 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11257 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11258 LED_CTRL_MODE_PHY_2);
11259 break;
11260
11261 case SHASTA_EXT_LED_MAC:
11262 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11263 break;
11264
11265 case SHASTA_EXT_LED_COMBO:
11266 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11267 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11268 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11269 LED_CTRL_MODE_PHY_2);
11270 break;
11271
855e1111 11272 }
1da177e4
LT
11273
11274 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11275 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11276 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11277 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11278
b2a5c19c
MC
11279 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11280 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11281
9d26e213 11282 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11283 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC
11284 if ((tp->pdev->subsystem_vendor ==
11285 PCI_VENDOR_ID_ARIMA) &&
11286 (tp->pdev->subsystem_device == 0x205a ||
11287 tp->pdev->subsystem_device == 0x2063))
11288 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11289 } else {
f49639e6 11290 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC
11291 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11292 }
1da177e4
LT
11293
11294 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11295 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11296 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT
11297 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11298 }
b2b98d4a
MC
11299
11300 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11301 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11302 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11303
a85feb8c
GZ
11304 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11305 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11306 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11307
12dac075 11308 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11309 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC
11310 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11311
1da177e4
LT
11312 if (cfg2 & (1 << 17))
11313 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11314
11315 /* serdes signal pre-emphasis in register 0x590 set by */
11316 /* bootcode if bit 18 is set */
11317 if (cfg2 & (1 << 18))
11318 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11319
321d32a0
MC
11320 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11321 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC
11322 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11323 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11324
8ed5d97e
MC
11325 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11326 u32 cfg3;
11327
11328 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11329 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11330 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11331 }
a9daf367
MC
11332
11333 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11334 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11335 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11336 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11337 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11338 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11339 }
05ac4cb7
MC
11340done:
11341 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11342 device_set_wakeup_enable(&tp->pdev->dev,
11343 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC
11344}
11345
b2a5c19c
MC
11346static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11347{
11348 int i;
11349 u32 val;
11350
11351 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11352 tw32(OTP_CTRL, cmd);
11353
11354 /* Wait for up to 1 ms for command to execute. */
11355 for (i = 0; i < 100; i++) {
11356 val = tr32(OTP_STATUS);
11357 if (val & OTP_STATUS_CMD_DONE)
11358 break;
11359 udelay(10);
11360 }
11361
11362 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11363}
11364
11365/* Read the gphy configuration from the OTP region of the chip. The gphy
11366 * configuration is a 32-bit value that straddles the alignment boundary.
11367 * We do two 32-bit reads and then shift and merge the results.
11368 */
11369static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11370{
11371 u32 bhalf_otp, thalf_otp;
11372
11373 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11374
11375 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11376 return 0;
11377
11378 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11379
11380 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11381 return 0;
11382
11383 thalf_otp = tr32(OTP_READ_DATA);
11384
11385 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11386
11387 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11388 return 0;
11389
11390 bhalf_otp = tr32(OTP_READ_DATA);
11391
11392 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11393}
11394
7d0c41ef
MC
11395static int __devinit tg3_phy_probe(struct tg3 *tp)
11396{
11397 u32 hw_phy_id_1, hw_phy_id_2;
11398 u32 hw_phy_id, hw_phy_id_masked;
11399 int err;
1da177e4 11400
b02fd9e3
MC
11401 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11402 return tg3_phy_init(tp);
11403
1da177e4 11404 /* Reading the PHY ID register can conflict with ASF
877d0310 11405 * firmware access to the PHY hardware.
1da177e4
LT
11406 */
11407 err = 0;
0d3031d9
MC
11408 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11409 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT
11410 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11411 } else {
11412 /* Now read the physical PHY_ID from the chip and verify
11413 * that it is sane. If it doesn't look good, we fall back
11414 * to either the hard-coded table based PHY_ID and failing
11415 * that the value found in the eeprom area.
11416 */
11417 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11418 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11419
11420 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11421 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11422 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11423
11424 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11425 }
11426
11427 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11428 tp->phy_id = hw_phy_id;
11429 if (hw_phy_id_masked == PHY_ID_BCM8002)
11430 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC
11431 else
11432 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11433 } else {
7d0c41ef
MC
11434 if (tp->phy_id != PHY_ID_INVALID) {
11435 /* Do nothing, phy ID already set up in
11436 * tg3_get_eeprom_hw_cfg().
11437 */
1da177e4
LT
11438 } else {
11439 struct subsys_tbl_ent *p;
11440
11441 /* No eeprom signature? Try the hardcoded
11442 * subsys device table.
11443 */
11444 p = lookup_by_subsys(tp);
11445 if (!p)
11446 return -ENODEV;
11447
11448 tp->phy_id = p->phy_id;
11449 if (!tp->phy_id ||
11450 tp->phy_id == PHY_ID_BCM8002)
11451 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11452 }
11453 }
11454
747e8f8b 11455 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11456 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11457 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11458 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT
11459
11460 tg3_readphy(tp, MII_BMSR, &bmsr);
11461 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11462 (bmsr & BMSR_LSTATUS))
11463 goto skip_phy_reset;
6aa20a22 11464
1da177e4
LT
11465 err = tg3_phy_reset(tp);
11466 if (err)
11467 return err;
11468
11469 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11470 ADVERTISE_100HALF | ADVERTISE_100FULL |
11471 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11472 tg3_ctrl = 0;
11473 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11474 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11475 MII_TG3_CTRL_ADV_1000_FULL);
11476 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11477 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11478 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11479 MII_TG3_CTRL_ENABLE_AS_MASTER);
11480 }
11481
3600d918
MC
11482 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11483 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11484 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11485 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT
11486 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11487
11488 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11489 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11490
11491 tg3_writephy(tp, MII_BMCR,
11492 BMCR_ANENABLE | BMCR_ANRESTART);
11493 }
11494 tg3_phy_set_wirespeed(tp);
11495
11496 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11497 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11498 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11499 }
11500
11501skip_phy_reset:
11502 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11503 err = tg3_init_5401phy_dsp(tp);
11504 if (err)
11505 return err;
11506 }
11507
11508 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11509 err = tg3_init_5401phy_dsp(tp);
11510 }
11511
747e8f8b 11512 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT
11513 tp->link_config.advertising =
11514 (ADVERTISED_1000baseT_Half |
11515 ADVERTISED_1000baseT_Full |
11516 ADVERTISED_Autoneg |
11517 ADVERTISED_FIBRE);
11518 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11519 tp->link_config.advertising &=
11520 ~(ADVERTISED_1000baseT_Half |
11521 ADVERTISED_1000baseT_Full);
11522
11523 return err;
11524}
11525
11526static void __devinit tg3_read_partno(struct tg3 *tp)
11527{
6d348f2c 11528 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11529 unsigned int i;
1b27777a 11530 u32 magic;
1da177e4 11531
df259d8c
MC
11532 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11533 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11534 goto out_not_found;
1da177e4 11535
1820180b 11536 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC
11537 for (i = 0; i < 256; i += 4) {
11538 u32 tmp;
1da177e4 11539
6d348f2c
MC
11540 /* The data is in little-endian format in NVRAM.
11541 * Use the big-endian read routines to preserve
11542 * the byte order as it exists in NVRAM.
11543 */
11544 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC
11545 goto out_not_found;
11546
6d348f2c 11547 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC
11548 }
11549 } else {
11550 int vpd_cap;
11551
11552 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11553 for (i = 0; i < 256; i += 4) {
11554 u32 tmp, j = 0;
b9fc7dc5 11555 __le32 v;
1b27777a
MC
11556 u16 tmp16;
11557
11558 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11559 i);
11560 while (j++ < 100) {
11561 pci_read_config_word(tp->pdev, vpd_cap +
11562 PCI_VPD_ADDR, &tmp16);
11563 if (tmp16 & 0x8000)
11564 break;
11565 msleep(1);
11566 }
f49639e6
DM
11567 if (!(tmp16 & 0x8000))
11568 goto out_not_found;
11569
1b27777a
MC
11570 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11571 &tmp);
b9fc7dc5 11572 v = cpu_to_le32(tmp);
6d348f2c 11573 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11574 }
1da177e4
LT
11575 }
11576
11577 /* Now parse and find the part number. */
af2c6a4a 11578 for (i = 0; i < 254; ) {
1da177e4 11579 unsigned char val = vpd_data[i];
af2c6a4a 11580 unsigned int block_end;
1da177e4
LT
11581
11582 if (val == 0x82 || val == 0x91) {
11583 i = (i + 3 +
11584 (vpd_data[i + 1] +
11585 (vpd_data[i + 2] << 8)));
11586 continue;
11587 }
11588
11589 if (val != 0x90)
11590 goto out_not_found;
11591
11592 block_end = (i + 3 +
11593 (vpd_data[i + 1] +
11594 (vpd_data[i + 2] << 8)));
11595 i += 3;
af2c6a4a
MC
11596
11597 if (block_end > 256)
11598 goto out_not_found;
11599
11600 while (i < (block_end - 2)) {
1da177e4
LT
11601 if (vpd_data[i + 0] == 'P' &&
11602 vpd_data[i + 1] == 'N') {
11603 int partno_len = vpd_data[i + 2];
11604
af2c6a4a
MC
11605 i += 3;
11606 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT
11607 goto out_not_found;
11608
11609 memcpy(tp->board_part_number,
af2c6a4a 11610 &vpd_data[i], partno_len);
1da177e4
LT
11611
11612 /* Success. */
11613 return;
11614 }
af2c6a4a 11615 i += 3 + vpd_data[i + 2];
1da177e4
LT
11616 }
11617
11618 /* Part number not found. */
11619 goto out_not_found;
11620 }
11621
11622out_not_found:
b5d3772c
MC
11623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11624 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC
11625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11626 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11627 strcpy(tp->board_part_number, "BCM57780");
11628 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11629 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11630 strcpy(tp->board_part_number, "BCM57760");
11631 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11632 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11633 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC
11634 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11635 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11636 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC
11637 else
11638 strcpy(tp->board_part_number, "none");
1da177e4
LT
11639}
11640
9c8a620e
MC
11641static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11642{
11643 u32 val;
11644
e4f34110 11645 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11646 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11647 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC
11648 val != 0)
11649 return 0;
11650
11651 return 1;
11652}
11653
acd9c119
MC
11654static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11655{
ff3a7cb2 11656 u32 val, offset, start, ver_offset;
acd9c119 11657 int i;
ff3a7cb2 11658 bool newver = false;
acd9c119
MC
11659
11660 if (tg3_nvram_read(tp, 0xc, &offset) ||
11661 tg3_nvram_read(tp, 0x4, &start))
11662 return;
11663
11664 offset = tg3_nvram_logical_addr(tp, offset);
11665
ff3a7cb2 11666 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC
11667 return;
11668
ff3a7cb2
MC
11669 if ((val & 0xfc000000) == 0x0c000000) {
11670 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC
11671 return;
11672
ff3a7cb2
MC
11673 if (val == 0)
11674 newver = true;
11675 }
11676
11677 if (newver) {
11678 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11679 return;
11680
11681 offset = offset + ver_offset - start;
11682 for (i = 0; i < 16; i += 4) {
11683 __be32 v;
11684 if (tg3_nvram_read_be32(tp, offset + i, &v))
11685 return;
11686
11687 memcpy(tp->fw_ver + i, &v, sizeof(v));
11688 }
11689 } else {
11690 u32 major, minor;
11691
11692 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11693 return;
11694
11695 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11696 TG3_NVM_BCVER_MAJSFT;
11697 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11698 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC
11699 }
11700}
11701
a6f6cb1c
MC
11702static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11703{
11704 u32 val, major, minor;
11705
11706 /* Use native endian representation */
11707 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11708 return;
11709
11710 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11711 TG3_NVM_HWSB_CFG1_MAJSFT;
11712 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11713 TG3_NVM_HWSB_CFG1_MINSFT;
11714
11715 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11716}
11717
dfe00d7d
MC
11718static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11719{
11720 u32 offset, major, minor, build;
11721
11722 tp->fw_ver[0] = 's';
11723 tp->fw_ver[1] = 'b';
11724 tp->fw_ver[2] = '\0';
11725
11726 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11727 return;
11728
11729 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11730 case TG3_EEPROM_SB_REVISION_0:
11731 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11732 break;
11733 case TG3_EEPROM_SB_REVISION_2:
11734 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11735 break;
11736 case TG3_EEPROM_SB_REVISION_3:
11737 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11738 break;
11739 default:
11740 return;
11741 }
11742
e4f34110 11743 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC
11744 return;
11745
11746 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11747 TG3_EEPROM_SB_EDH_BLD_SHFT;
11748 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11749 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11750 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11751
11752 if (minor > 99 || build > 26)
11753 return;
11754
11755 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11756
11757 if (build > 0) {
11758 tp->fw_ver[8] = 'a' + build - 1;
11759 tp->fw_ver[9] = '\0';
11760 }
11761}
11762
acd9c119 11763static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC
11764{
11765 u32 val, offset, start;
acd9c119 11766 int i, vlen;
9c8a620e
MC
11767
11768 for (offset = TG3_NVM_DIR_START;
11769 offset < TG3_NVM_DIR_END;
11770 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11771 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC
11772 return;
11773
9c8a620e
MC
11774 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11775 break;
11776 }
11777
11778 if (offset == TG3_NVM_DIR_END)
11779 return;
11780
11781 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11782 start = 0x08000000;
e4f34110 11783 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC
11784 return;
11785
e4f34110 11786 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11787 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11788 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC
11789 return;
11790
11791 offset += val - start;
11792
acd9c119 11793 vlen = strlen(tp->fw_ver);
9c8a620e 11794
acd9c119
MC
11795 tp->fw_ver[vlen++] = ',';
11796 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC
11797
11798 for (i = 0; i < 4; i++) {
a9dc529d
MC
11799 __be32 v;
11800 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC
11801 return;
11802
b9fc7dc5 11803 offset += sizeof(v);
c4e6575c 11804
acd9c119
MC
11805 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11806 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11807 break;
c4e6575c 11808 }
9c8a620e 11809
acd9c119
MC
11810 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11811 vlen += sizeof(v);
c4e6575c 11812 }
acd9c119
MC
11813}
11814
7fd76445
MC
11815static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11816{
11817 int vlen;
11818 u32 apedata;
11819
11820 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11821 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11822 return;
11823
11824 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11825 if (apedata != APE_SEG_SIG_MAGIC)
11826 return;
11827
11828 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11829 if (!(apedata & APE_FW_STATUS_READY))
11830 return;
11831
11832 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11833
11834 vlen = strlen(tp->fw_ver);
11835
11836 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11837 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11838 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11839 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11840 (apedata & APE_FW_VERSION_BLDMSK));
11841}
11842
acd9c119
MC
11843static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11844{
11845 u32 val;
11846
df259d8c
MC
11847 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11848 tp->fw_ver[0] = 's';
11849 tp->fw_ver[1] = 'b';
11850 tp->fw_ver[2] = '\0';
11851
11852 return;
11853 }
11854
acd9c119
MC
11855 if (tg3_nvram_read(tp, 0, &val))
11856 return;
11857
11858 if (val == TG3_EEPROM_MAGIC)
11859 tg3_read_bc_ver(tp);
11860 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11861 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC
11862 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11863 tg3_read_hwsb_ver(tp);
acd9c119
MC
11864 else
11865 return;
11866
11867 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11868 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11869 return;
11870
11871 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC
11872
11873 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC
11874}
11875
7544b097
MC
11876static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11877
1da177e4
LT
11878static int __devinit tg3_get_invariants(struct tg3 *tp)
11879{
11880 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT
11881 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11882 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL
11883 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11884 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC
11885 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11886 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT
11887 { },
11888 };
11889 u32 misc_ctrl_reg;
1da177e4
LT
11890 u32 pci_state_reg, grc_misc_cfg;
11891 u32 val;
11892 u16 pci_cmd;
5e7dfd0f 11893 int err;
1da177e4 11894
1da177e4
LT
11895 /* Force memory write invalidate off. If we leave it on,
11896 * then on 5700_BX chips we have to enable a workaround.
11897 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11898 * to match the cacheline size. The Broadcom driver have this
11899 * workaround but turns MWI off all the times so never uses
11900 * it. This seems to suggest that the workaround is insufficient.
11901 */
11902 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11903 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11904 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11905
11906 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11907 * has the register indirect write enable bit set before
11908 * we try to access any of the MMIO registers. It is also
11909 * critical that the PCI-X hw workaround situation is decided
11910 * before that as well.
11911 */
11912 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11913 &misc_ctrl_reg);
11914
11915 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11916 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC
11917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11918 u32 prod_id_asic_rev;
11919
11920 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11921 &prod_id_asic_rev);
321d32a0 11922 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11923 }
1da177e4 11924
ff645bec
MC
11925 /* Wrong chip ID in 5752 A0. This code can be removed later
11926 * as A0 is not in production.
11927 */
11928 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11929 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11930
6892914f
MC
11931 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11932 * we need to disable memory and use config. cycles
11933 * only to access all registers. The 5702/03 chips
11934 * can mistakenly decode the special cycles from the
11935 * ICH chipsets as memory write cycles, causing corruption
11936 * of register and memory space. Only certain ICH bridges
11937 * will drive special cycles with non-zero data during the
11938 * address phase which can fall within the 5703's address
11939 * range. This is not an ICH bug as the PCI spec allows
11940 * non-zero address during special cycles. However, only
11941 * these ICH bridges are known to drive non-zero addresses
11942 * during special cycles.
11943 *
11944 * Since special cycles do not cross PCI bridges, we only
11945 * enable this workaround if the 5703 is on the secondary
11946 * bus of these ICH bridges.
11947 */
11948 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11949 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11950 static struct tg3_dev_id {
11951 u32 vendor;
11952 u32 device;
11953 u32 rev;
11954 } ich_chipsets[] = {
11955 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11956 PCI_ANY_ID },
11957 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11958 PCI_ANY_ID },
11959 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11960 0xa },
11961 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11962 PCI_ANY_ID },
11963 { },
11964 };
11965 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11966 struct pci_dev *bridge = NULL;
11967
11968 while (pci_id->vendor != 0) {
11969 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11970 bridge);
11971 if (!bridge) {
11972 pci_id++;
11973 continue;
11974 }
11975 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11976 if (bridge->revision > pci_id->rev)
6892914f
MC
11977 continue;
11978 }
11979 if (bridge->subordinate &&
11980 (bridge->subordinate->number ==
11981 tp->pdev->bus->number)) {
11982
11983 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11984 pci_dev_put(bridge);
11985 break;
11986 }
11987 }
11988 }
11989
41588ba1
MC
11990 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11991 static struct tg3_dev_id {
11992 u32 vendor;
11993 u32 device;
11994 } bridge_chipsets[] = {
11995 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11996 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11997 { },
11998 };
11999 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12000 struct pci_dev *bridge = NULL;
12001
12002 while (pci_id->vendor != 0) {
12003 bridge = pci_get_device(pci_id->vendor,
12004 pci_id->device,
12005 bridge);
12006 if (!bridge) {
12007 pci_id++;
12008 continue;
12009 }
12010 if (bridge->subordinate &&
12011 (bridge->subordinate->number <=
12012 tp->pdev->bus->number) &&
12013 (bridge->subordinate->subordinate >=
12014 tp->pdev->bus->number)) {
12015 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12016 pci_dev_put(bridge);
12017 break;
12018 }
12019 }
12020 }
12021
4a29cc2e
MC
12022 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12023 * DMA addresses > 40-bit. This bridge may have other additional
12024 * 57xx devices behind it in some 4-port NIC designs for example.
12025 * Any tg3 device found behind the bridge will also need the 40-bit
12026 * DMA workaround.
12027 */
a4e2b347
MC
12028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12030 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12031 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12032 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12033 }
4a29cc2e
MC
12034 else {
12035 struct pci_dev *bridge = NULL;
12036
12037 do {
12038 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12039 PCI_DEVICE_ID_SERVERWORKS_EPB,
12040 bridge);
12041 if (bridge && bridge->subordinate &&
12042 (bridge->subordinate->number <=
12043 tp->pdev->bus->number) &&
12044 (bridge->subordinate->subordinate >=
12045 tp->pdev->bus->number)) {
12046 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12047 pci_dev_put(bridge);
12048 break;
12049 }
12050 } while (bridge);
12051 }
4cf78e4f 12052
1da177e4
LT
12053 /* Initialize misc host control in PCI block. */
12054 tp->misc_host_ctrl |= (misc_ctrl_reg &
12055 MISC_HOST_CTRL_CHIPREV);
12056 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12057 tp->misc_host_ctrl);
12058
7544b097
MC
12059 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12060 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12061 tp->pdev_peer = tg3_find_peer(tp);
12062
321d32a0
MC
12063 /* Intentionally exclude ASIC_REV_5906 */
12064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12065 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC
12069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12070 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12071
12072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12075 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12076 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL
12077 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12078
1b440c56
JL
12079 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12080 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12081 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12082
027455ad
MC
12083 /* 5700 B0 chips do not support checksumming correctly due
12084 * to hardware bugs.
12085 */
12086 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12087 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12088 else {
12089 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12090 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12091 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12092 tp->dev->features |= NETIF_F_IPV6_CSUM;
12093 }
12094
5a6f3074 12095 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC
12096 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12098 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12099 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12100 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12101 tp->pdev_peer == tp->pdev))
12102 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12103
321d32a0 12104 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12106 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12107 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12108 } else {
7f62ad5d 12109 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC
12110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12111 ASIC_REV_5750 &&
12112 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12113 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12114 }
5a6f3074 12115 }
1da177e4 12116
f51f3562
MC
12117 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12118 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12119 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12120
52f4490c
MC
12121 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12122 &pci_state_reg);
12123
5e7dfd0f
MC
12124 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12125 if (tp->pcie_cap != 0) {
12126 u16 lnkctl;
12127
1da177e4 12128 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC
12129
12130 pcie_set_readrq(tp->pdev, 4096);
12131
5e7dfd0f
MC
12132 pci_read_config_word(tp->pdev,
12133 tp->pcie_cap + PCI_EXP_LNKCTL,
12134 &lnkctl);
12135 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12137 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC
12140 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12141 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12142 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12143 }
52f4490c 12144 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12145 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC
12146 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12147 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12148 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12149 if (!tp->pcix_cap) {
12150 printk(KERN_ERR PFX "Cannot find PCI-X "
12151 "capability, aborting.\n");
12152 return -EIO;
12153 }
12154
12155 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12156 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12157 }
1da177e4 12158
399de50b
MC
12159 /* If we have an AMD 762 or VIA K8T800 chipset, write
12160 * reordering to the mailbox registers done by the host
12161 * controller can cause major troubles. We read back from
12162 * every mailbox register write to force the writes to be
12163 * posted to the chip in order.
12164 */
12165 if (pci_dev_present(write_reorder_chipsets) &&
12166 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12167 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12168
69fc4053
MC
12169 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12170 &tp->pci_cacheline_sz);
12171 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12172 &tp->pci_lat_timer);
1da177e4
LT
12173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12174 tp->pci_lat_timer < 64) {
12175 tp->pci_lat_timer = 64;
69fc4053
MC
12176 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12177 tp->pci_lat_timer);
1da177e4
LT
12178 }
12179
52f4490c
MC
12180 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12181 /* 5700 BX chips need to have their TX producer index
12182 * mailboxes written twice to workaround a bug.
12183 */
12184 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12185
52f4490c 12186 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT
12187 *
12188 * The workaround is to use indirect register accesses
12189 * for all chip writes not to mailbox registers.
12190 */
52f4490c 12191 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12192 u32 pm_reg;
1da177e4
LT
12193
12194 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12195
12196 /* The chip can have it's power management PCI config
12197 * space registers clobbered due to this bug.
12198 * So explicitly force the chip into D0 here.
12199 */
9974a356
MC
12200 pci_read_config_dword(tp->pdev,
12201 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT
12202 &pm_reg);
12203 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12204 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC
12205 pci_write_config_dword(tp->pdev,
12206 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT
12207 pm_reg);
12208
12209 /* Also, force SERR#/PERR# in PCI command. */
12210 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12211 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12212 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12213 }
12214 }
12215
1da177e4
LT
12216 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12217 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12218 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12219 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12220
12221 /* Chip-specific fixup from Broadcom driver */
12222 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12223 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12224 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12225 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12226 }
12227
1ee582d8 12228 /* Default fast path register access methods */
20094930 12229 tp->read32 = tg3_read32;
1ee582d8 12230 tp->write32 = tg3_write32;
09ee929c 12231 tp->read32_mbox = tg3_read32;
20094930 12232 tp->write32_mbox = tg3_write32;
1ee582d8
MC
12233 tp->write32_tx_mbox = tg3_write32;
12234 tp->write32_rx_mbox = tg3_write32;
12235
12236 /* Various workaround register access methods */
12237 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12238 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC
12239 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12240 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12241 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12242 /*
12243 * Back to back register writes can cause problems on these
12244 * chips, the workaround is to read back all reg writes
12245 * except those to mailbox regs.
12246 *
12247 * See tg3_write_indirect_reg32().
12248 */
1ee582d8 12249 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC
12250 }
12251
1ee582d8
MC
12252
12253 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12254 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12255 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12256 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12257 tp->write32_rx_mbox = tg3_write_flush_reg32;
12258 }
20094930 12259
6892914f
MC
12260 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12261 tp->read32 = tg3_read_indirect_reg32;
12262 tp->write32 = tg3_write_indirect_reg32;
12263 tp->read32_mbox = tg3_read_indirect_mbox;
12264 tp->write32_mbox = tg3_write_indirect_mbox;
12265 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12266 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12267
12268 iounmap(tp->regs);
22abe310 12269 tp->regs = NULL;
6892914f
MC
12270
12271 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12272 pci_cmd &= ~PCI_COMMAND_MEMORY;
12273 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12274 }
b5d3772c
MC
12275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12276 tp->read32_mbox = tg3_read32_mbox_5906;
12277 tp->write32_mbox = tg3_write32_mbox_5906;
12278 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12279 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12280 }
6892914f 12281
bbadf503
MC
12282 if (tp->write32 == tg3_write_indirect_reg32 ||
12283 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12284 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC
12286 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12287
7d0c41ef 12288 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12289 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC
12290 * determined before calling tg3_set_power_state() so that
12291 * we know whether or not to switch out of Vaux power.
12292 * When the flag is set, it means that GPIO1 is used for eeprom
12293 * write protect and also implies that it is a LOM where GPIOs
12294 * are not used to switch power.
6aa20a22 12295 */
7d0c41ef
MC
12296 tg3_get_eeprom_hw_cfg(tp);
12297
0d3031d9
MC
12298 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12299 /* Allow reads and writes to the
12300 * APE register and memory space.
12301 */
12302 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12303 PCISTATE_ALLOW_APE_SHMEM_WR;
12304 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12305 pci_state_reg);
12306 }
12307
9936bcf6 12308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC
12310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC
12312 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12313
314fba34
MC
12314 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12315 * GPIO1 driven high will bring 5700's external PHY out of reset.
12316 * It is also used as eeprom write protect on LOMs.
12317 */
12318 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12319 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12320 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12321 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12322 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC
12323 /* Unused GPIO3 must be driven as output on 5752 because there
12324 * are no pull-up resistors on unused GPIO pins.
12325 */
12326 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12327 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12328
321d32a0
MC
12329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12330 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC
12331 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12332
8d519ab2
MC
12333 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12334 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC
12335 /* Turn off the debug UART. */
12336 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12337 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12338 /* Keep VMain power. */
12339 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12340 GRC_LCLCTRL_GPIO_OUTPUT0;
12341 }
12342
1da177e4 12343 /* Force the chip into D0. */
bc1c7567 12344 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT
12345 if (err) {
12346 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12347 pci_name(tp->pdev));
12348 return err;
12349 }
12350
1da177e4
LT
12351 /* Derive initial jumbo mode from MTU assigned in
12352 * ether_setup() via the alloc_etherdev() call
12353 */
0f893dc6 12354 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12355 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12356 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT
12357
12358 /* Determine WakeOnLan speed to use. */
12359 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12360 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12361 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12362 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12363 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12364 } else {
12365 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12366 }
12367
7f97a4bd
MC
12368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12369 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12370
1da177e4
LT
12371 /* A few boards don't want Ethernet@WireSpeed phy feature */
12372 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12373 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12374 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12375 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12376 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12377 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT
12378 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12379
12380 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12381 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12382 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12383 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12384 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12385
321d32a0 12386 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12387 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC
12388 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12389 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC
12392 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC
12394 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12395 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12396 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC
12397 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12398 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12399 } else
c424cb24
MC
12400 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12401 }
1da177e4 12402
b2a5c19c
MC
12403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12404 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12405 tp->phy_otp = tg3_read_otp_phycfg(tp);
12406 if (tp->phy_otp == 0)
12407 tp->phy_otp = TG3_OTP_DEFAULT;
12408 }
12409
f51f3562 12410 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC
12411 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12412 else
12413 tp->mi_mode = MAC_MI_MODE_BASE;
12414
1da177e4 12415 tp->coalesce_mode = 0;
1da177e4
LT
12416 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12417 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12418 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12419
321d32a0
MC
12420 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC
12422 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12423
255ca311
MC
12424 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12425 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12426 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12427 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12428
158d7abd
MC
12429 err = tg3_mdio_init(tp);
12430 if (err)
12431 return err;
1da177e4
LT
12432
12433 /* Initialize data/descriptor byte/word swapping. */
12434 val = tr32(GRC_MODE);
12435 val &= GRC_MODE_HOST_STACKUP;
12436 tw32(GRC_MODE, val | tp->grc_mode);
12437
12438 tg3_switch_clocks(tp);
12439
12440 /* Clear this out for sanity. */
12441 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12442
12443 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12444 &pci_state_reg);
12445 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12446 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12447 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12448
12449 if (chiprevid == CHIPREV_ID_5701_A0 ||
12450 chiprevid == CHIPREV_ID_5701_B0 ||
12451 chiprevid == CHIPREV_ID_5701_B2 ||
12452 chiprevid == CHIPREV_ID_5701_B5) {
12453 void __iomem *sram_base;
12454
12455 /* Write some dummy words into the SRAM status block
12456 * area, see if it reads back correctly. If the return
12457 * value is bad, force enable the PCIX workaround.
12458 */
12459 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12460
12461 writel(0x00000000, sram_base);
12462 writel(0x00000000, sram_base + 4);
12463 writel(0xffffffff, sram_base + 4);
12464 if (readl(sram_base) != 0x00000000)
12465 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12466 }
12467 }
12468
12469 udelay(50);
12470 tg3_nvram_init(tp);
12471
12472 grc_misc_cfg = tr32(GRC_MISC_CFG);
12473 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12474
1da177e4
LT
12475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12476 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12477 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12478 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12479
fac9b83e
DM
12480 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12481 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12482 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12483 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12484 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12485 HOSTCC_MODE_CLRTICK_TXBD);
12486
12487 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12488 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12489 tp->misc_host_ctrl);
12490 }
12491
3bda1258
MC
12492 /* Preserve the APE MAC_MODE bits */
12493 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12494 tp->mac_mode = tr32(MAC_MODE) |
12495 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12496 else
12497 tp->mac_mode = TG3_DEF_MAC_MODE;
12498
1da177e4
LT
12499 /* these are limited to 10/100 only */
12500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12501 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12502 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12503 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12504 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12505 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12506 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12507 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12508 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC
12509 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12510 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12511 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12512 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT
12513 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12514
12515 err = tg3_phy_probe(tp);
12516 if (err) {
12517 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12518 pci_name(tp->pdev), err);
12519 /* ... but do not return immediately ... */
b02fd9e3 12520 tg3_mdio_fini(tp);
1da177e4
LT
12521 }
12522
12523 tg3_read_partno(tp);
c4e6575c 12524 tg3_read_fw_ver(tp);
1da177e4
LT
12525
12526 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12527 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12528 } else {
12529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12530 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12531 else
12532 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12533 }
12534
12535 /* 5700 {AX,BX} chips have a broken status block link
12536 * change bit implementation, so we must use the
12537 * status register in those cases.
12538 */
12539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12540 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12541 else
12542 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12543
12544 /* The led_ctrl is set during tg3_phy_probe, here we might
12545 * have to force the link status polling mechanism based
12546 * upon subsystem IDs.
12547 */
12548 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT
12550 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12551 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12552 TG3_FLAG_USE_LINKCHG_REG);
12553 }
12554
12555 /* For all SERDES we poll the MAC status register. */
12556 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12557 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12558 else
12559 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12560
ad829268 12561 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT
12562 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12563 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12564 tp->rx_offset = 0;
12565
f92905de
MC
12566 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12567
12568 /* Increment the rx prod index on the rx std ring by at most
12569 * 8 for these chips to workaround hw errata.
12570 */
12571 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12574 tp->rx_std_max_post = 8;
12575
8ed5d97e
MC
12576 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12577 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12578 PCIE_PWR_MGMT_L1_THRESH_MSK;
12579
1da177e4
LT
12580 return err;
12581}
12582
49b6e95f 12583#ifdef CONFIG_SPARC
1da177e4
LT
12584static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12585{
12586 struct net_device *dev = tp->dev;
12587 struct pci_dev *pdev = tp->pdev;
49b6e95f 12588 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12589 const unsigned char *addr;
49b6e95f
DM
12590 int len;
12591
12592 addr = of_get_property(dp, "local-mac-address", &len);
12593 if (addr && len == 6) {
12594 memcpy(dev->dev_addr, addr, 6);
12595 memcpy(dev->perm_addr, dev->dev_addr, 6);
12596 return 0;
1da177e4
LT
12597 }
12598 return -ENODEV;
12599}
12600
12601static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12602{
12603 struct net_device *dev = tp->dev;
12604
12605 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12606 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT
12607 return 0;
12608}
12609#endif
12610
12611static int __devinit tg3_get_device_address(struct tg3 *tp)
12612{
12613 struct net_device *dev = tp->dev;
12614 u32 hi, lo, mac_offset;
008652b3 12615 int addr_ok = 0;
1da177e4 12616
49b6e95f 12617#ifdef CONFIG_SPARC
1da177e4
LT
12618 if (!tg3_get_macaddr_sparc(tp))
12619 return 0;
12620#endif
12621
12622 mac_offset = 0x7c;
f49639e6 12623 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12624 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT
12625 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12626 mac_offset = 0xcc;
12627 if (tg3_nvram_lock(tp))
12628 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12629 else
12630 tg3_nvram_unlock(tp);
12631 }
b5d3772c
MC
12632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12633 mac_offset = 0x10;
1da177e4
LT
12634
12635 /* First try to get it from MAC address mailbox. */
12636 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12637 if ((hi >> 16) == 0x484b) {
12638 dev->dev_addr[0] = (hi >> 8) & 0xff;
12639 dev->dev_addr[1] = (hi >> 0) & 0xff;
12640
12641 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12642 dev->dev_addr[2] = (lo >> 24) & 0xff;
12643 dev->dev_addr[3] = (lo >> 16) & 0xff;
12644 dev->dev_addr[4] = (lo >> 8) & 0xff;
12645 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12646
008652b3
MC
12647 /* Some old bootcode may report a 0 MAC address in SRAM */
12648 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12649 }
12650 if (!addr_ok) {
12651 /* Next, try NVRAM. */
df259d8c
MC
12652 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12653 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12654 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC
12655 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12656 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC
12657 }
12658 /* Finally just fetch it out of the MAC control regs. */
12659 else {
12660 hi = tr32(MAC_ADDR_0_HIGH);
12661 lo = tr32(MAC_ADDR_0_LOW);
12662
12663 dev->dev_addr[5] = lo & 0xff;
12664 dev->dev_addr[4] = (lo >> 8) & 0xff;
12665 dev->dev_addr[3] = (lo >> 16) & 0xff;
12666 dev->dev_addr[2] = (lo >> 24) & 0xff;
12667 dev->dev_addr[1] = hi & 0xff;
12668 dev->dev_addr[0] = (hi >> 8) & 0xff;
12669 }
1da177e4
LT
12670 }
12671
12672 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12673#ifdef CONFIG_SPARC
1da177e4
LT
12674 if (!tg3_get_default_macaddr_sparc(tp))
12675 return 0;
12676#endif
12677 return -EINVAL;
12678 }
2ff43697 12679 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT
12680 return 0;
12681}
12682
59e6b434
DM
12683#define BOUNDARY_SINGLE_CACHELINE 1
12684#define BOUNDARY_MULTI_CACHELINE 2
12685
12686static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12687{
12688 int cacheline_size;
12689 u8 byte;
12690 int goal;
12691
12692 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12693 if (byte == 0)
12694 cacheline_size = 1024;
12695 else
12696 cacheline_size = (int) byte * 4;
12697
12698 /* On 5703 and later chips, the boundary bits have no
12699 * effect.
12700 */
12701 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12702 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12703 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12704 goto out;
12705
12706#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12707 goal = BOUNDARY_MULTI_CACHELINE;
12708#else
12709#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12710 goal = BOUNDARY_SINGLE_CACHELINE;
12711#else
12712 goal = 0;
12713#endif
12714#endif
12715
12716 if (!goal)
12717 goto out;
12718
12719 /* PCI controllers on most RISC systems tend to disconnect
12720 * when a device tries to burst across a cache-line boundary.
12721 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12722 *
12723 * Unfortunately, for PCI-E there are only limited
12724 * write-side controls for this, and thus for reads
12725 * we will still get the disconnects. We'll also waste
12726 * these PCI cycles for both read and write for chips
12727 * other than 5700 and 5701 which do not implement the
12728 * boundary bits.
12729 */
12730 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12731 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12732 switch (cacheline_size) {
12733 case 16:
12734 case 32:
12735 case 64:
12736 case 128:
12737 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12738 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12739 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12740 } else {
12741 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12742 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12743 }
12744 break;
12745
12746 case 256:
12747 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12748 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12749 break;
12750
12751 default:
12752 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12753 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12754 break;
855e1111 12755 }
59e6b434
DM
12756 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12757 switch (cacheline_size) {
12758 case 16:
12759 case 32:
12760 case 64:
12761 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12762 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12763 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12764 break;
12765 }
12766 /* fallthrough */
12767 case 128:
12768 default:
12769 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12770 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12771 break;
855e1111 12772 }
59e6b434
DM
12773 } else {
12774 switch (cacheline_size) {
12775 case 16:
12776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12777 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12778 DMA_RWCTRL_WRITE_BNDRY_16);
12779 break;
12780 }
12781 /* fallthrough */
12782 case 32:
12783 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12784 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12785 DMA_RWCTRL_WRITE_BNDRY_32);
12786 break;
12787 }
12788 /* fallthrough */
12789 case 64:
12790 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12791 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12792 DMA_RWCTRL_WRITE_BNDRY_64);
12793 break;
12794 }
12795 /* fallthrough */
12796 case 128:
12797 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12798 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12799 DMA_RWCTRL_WRITE_BNDRY_128);
12800 break;
12801 }
12802 /* fallthrough */
12803 case 256:
12804 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12805 DMA_RWCTRL_WRITE_BNDRY_256);
12806 break;
12807 case 512:
12808 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12809 DMA_RWCTRL_WRITE_BNDRY_512);
12810 break;
12811 case 1024:
12812 default:
12813 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12814 DMA_RWCTRL_WRITE_BNDRY_1024);
12815 break;
855e1111 12816 }
59e6b434
DM
12817 }
12818
12819out:
12820 return val;
12821}
12822
1da177e4
LT
12823static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12824{
12825 struct tg3_internal_buffer_desc test_desc;
12826 u32 sram_dma_descs;
12827 int i, ret;
12828
12829 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12830
12831 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12832 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12833 tw32(RDMAC_STATUS, 0);
12834 tw32(WDMAC_STATUS, 0);
12835
12836 tw32(BUFMGR_MODE, 0);
12837 tw32(FTQ_RESET, 0);
12838
12839 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12840 test_desc.addr_lo = buf_dma & 0xffffffff;
12841 test_desc.nic_mbuf = 0x00002100;
12842 test_desc.len = size;
12843
12844 /*
12845 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12846 * the *second* time the tg3 driver was getting loaded after an
12847 * initial scan.
12848 *
12849 * Broadcom tells me:
12850 * ...the DMA engine is connected to the GRC block and a DMA
12851 * reset may affect the GRC block in some unpredictable way...
12852 * The behavior of resets to individual blocks has not been tested.
12853 *
12854 * Broadcom noted the GRC reset will also reset all sub-components.
12855 */
12856 if (to_device) {
12857 test_desc.cqid_sqid = (13 << 8) | 2;
12858
12859 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12860 udelay(40);
12861 } else {
12862 test_desc.cqid_sqid = (16 << 8) | 7;
12863
12864 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12865 udelay(40);
12866 }
12867 test_desc.flags = 0x00000005;
12868
12869 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12870 u32 val;
12871
12872 val = *(((u32 *)&test_desc) + i);
12873 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12874 sram_dma_descs + (i * sizeof(u32)));
12875 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12876 }
12877 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12878
12879 if (to_device) {
12880 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12881 } else {
12882 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12883 }
12884
12885 ret = -ENODEV;
12886 for (i = 0; i < 40; i++) {
12887 u32 val;
12888
12889 if (to_device)
12890 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12891 else
12892 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12893 if ((val & 0xffff) == sram_dma_descs) {
12894 ret = 0;
12895 break;
12896 }
12897
12898 udelay(100);
12899 }
12900
12901 return ret;
12902}
12903
ded7340d 12904#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT
12905
12906static int __devinit tg3_test_dma(struct tg3 *tp)
12907{
12908 dma_addr_t buf_dma;
59e6b434 12909 u32 *buf, saved_dma_rwctrl;
1da177e4
LT
12910 int ret;
12911
12912 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12913 if (!buf) {
12914 ret = -ENOMEM;
12915 goto out_nofree;
12916 }
12917
12918 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12919 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12920
59e6b434 12921 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT
12922
12923 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12924 /* DMA read watermark not used on PCIE */
12925 tp->dma_rwctrl |= 0x00180000;
12926 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC
12927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT
12929 tp->dma_rwctrl |= 0x003f0000;
12930 else
12931 tp->dma_rwctrl |= 0x003f000f;
12932 } else {
12933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12935 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12936 u32 read_water = 0x7;
1da177e4 12937
4a29cc2e
MC
12938 /* If the 5704 is behind the EPB bridge, we can
12939 * do the less restrictive ONE_DMA workaround for
12940 * better performance.
12941 */
12942 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12944 tp->dma_rwctrl |= 0x8000;
12945 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT
12946 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12947
49afdeb6
MC
12948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12949 read_water = 4;
59e6b434 12950 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC
12951 tp->dma_rwctrl |=
12952 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12953 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12954 (1 << 23);
4cf78e4f
MC
12955 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12956 /* 5780 always in PCIX mode */
12957 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC
12958 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12959 /* 5714 always in PCIX mode */
12960 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT
12961 } else {
12962 tp->dma_rwctrl |= 0x001b000f;
12963 }
12964 }
12965
12966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12968 tp->dma_rwctrl &= 0xfffffff0;
12969
12970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12972 /* Remove this if it causes problems for some boards. */
12973 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12974
12975 /* On 5700/5701 chips, we need to set this bit.
12976 * Otherwise the chip will issue cacheline transactions
12977 * to streamable DMA memory with not all the byte
12978 * enables turned on. This is an error on several
12979 * RISC PCI controllers, in particular sparc64.
12980 *
12981 * On 5703/5704 chips, this bit has been reassigned
12982 * a different meaning. In particular, it is used
12983 * on those chips to enable a PCI-X workaround.
12984 */
12985 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12986 }
12987
12988 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12989
12990#if 0
12991 /* Unneeded, already done by tg3_get_invariants. */
12992 tg3_switch_clocks(tp);
12993#endif
12994
12995 ret = 0;
12996 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12997 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12998 goto out;
12999
59e6b434
DM
13000 /* It is best to perform DMA test with maximum write burst size
13001 * to expose the 5700/5701 write DMA bug.
13002 */
13003 saved_dma_rwctrl = tp->dma_rwctrl;
13004 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13005 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13006
1da177e4
LT
13007 while (1) {
13008 u32 *p = buf, i;
13009
13010 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13011 p[i] = i;
13012
13013 /* Send the buffer to the chip. */
13014 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13015 if (ret) {
13016 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13017 break;
13018 }
13019
13020#if 0
13021 /* validate data reached card RAM correctly. */
13022 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13023 u32 val;
13024 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13025 if (le32_to_cpu(val) != p[i]) {
13026 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13027 /* ret = -ENODEV here? */
13028 }
13029 p[i] = 0;
13030 }
13031#endif
13032 /* Now read it back. */
13033 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13034 if (ret) {
13035 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13036
13037 break;
13038 }
13039
13040 /* Verify it. */
13041 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13042 if (p[i] == i)
13043 continue;
13044
59e6b434
DM
13045 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13046 DMA_RWCTRL_WRITE_BNDRY_16) {
13047 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT
13048 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13049 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13050 break;
13051 } else {
13052 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13053 ret = -ENODEV;
13054 goto out;
13055 }
13056 }
13057
13058 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13059 /* Success. */
13060 ret = 0;
13061 break;
13062 }
13063 }
59e6b434
DM
13064 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13065 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC
13066 static struct pci_device_id dma_wait_state_chipsets[] = {
13067 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13068 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13069 { },
13070 };
13071
59e6b434 13072 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC
13073 * now look for chipsets that are known to expose the
13074 * DMA bug without failing the test.
59e6b434 13075 */
6d1cfbab
MC
13076 if (pci_dev_present(dma_wait_state_chipsets)) {
13077 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13078 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13079 }
13080 else
13081 /* Safe to use the calculated DMA boundary. */
13082 tp->dma_rwctrl = saved_dma_rwctrl;
13083
59e6b434
DM
13084 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13085 }
1da177e4
LT
13086
13087out:
13088 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13089out_nofree:
13090 return ret;
13091}
13092
13093static void __devinit tg3_init_link_config(struct tg3 *tp)
13094{
13095 tp->link_config.advertising =
13096 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13097 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13098 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13099 ADVERTISED_Autoneg | ADVERTISED_MII);
13100 tp->link_config.speed = SPEED_INVALID;
13101 tp->link_config.duplex = DUPLEX_INVALID;
13102 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT
13103 tp->link_config.active_speed = SPEED_INVALID;
13104 tp->link_config.active_duplex = DUPLEX_INVALID;
13105 tp->link_config.phy_is_low_power = 0;
13106 tp->link_config.orig_speed = SPEED_INVALID;
13107 tp->link_config.orig_duplex = DUPLEX_INVALID;
13108 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13109}
13110
13111static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13112{
fdfec172
MC
13113 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13114 tp->bufmgr_config.mbuf_read_dma_low_water =
13115 DEFAULT_MB_RDMA_LOW_WATER_5705;
13116 tp->bufmgr_config.mbuf_mac_rx_low_water =
13117 DEFAULT_MB_MACRX_LOW_WATER_5705;
13118 tp->bufmgr_config.mbuf_high_water =
13119 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC
13120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13121 tp->bufmgr_config.mbuf_mac_rx_low_water =
13122 DEFAULT_MB_MACRX_LOW_WATER_5906;
13123 tp->bufmgr_config.mbuf_high_water =
13124 DEFAULT_MB_HIGH_WATER_5906;
13125 }
fdfec172
MC
13126
13127 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13128 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13129 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13130 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13131 tp->bufmgr_config.mbuf_high_water_jumbo =
13132 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13133 } else {
13134 tp->bufmgr_config.mbuf_read_dma_low_water =
13135 DEFAULT_MB_RDMA_LOW_WATER;
13136 tp->bufmgr_config.mbuf_mac_rx_low_water =
13137 DEFAULT_MB_MACRX_LOW_WATER;
13138 tp->bufmgr_config.mbuf_high_water =
13139 DEFAULT_MB_HIGH_WATER;
13140
13141 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13142 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13143 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13144 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13145 tp->bufmgr_config.mbuf_high_water_jumbo =
13146 DEFAULT_MB_HIGH_WATER_JUMBO;
13147 }
1da177e4
LT
13148
13149 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13150 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13151}
13152
13153static char * __devinit tg3_phy_string(struct tg3 *tp)
13154{
13155 switch (tp->phy_id & PHY_ID_MASK) {
13156 case PHY_ID_BCM5400: return "5400";
13157 case PHY_ID_BCM5401: return "5401";
13158 case PHY_ID_BCM5411: return "5411";
13159 case PHY_ID_BCM5701: return "5701";
13160 case PHY_ID_BCM5703: return "5703";
13161 case PHY_ID_BCM5704: return "5704";
13162 case PHY_ID_BCM5705: return "5705";
13163 case PHY_ID_BCM5750: return "5750";
85e94ced 13164 case PHY_ID_BCM5752: return "5752";
a4e2b347 13165 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13166 case PHY_ID_BCM5780: return "5780";
af36e6b6 13167 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13168 case PHY_ID_BCM5787: return "5787";
d30cdd28 13169 case PHY_ID_BCM5784: return "5784";
126a3368 13170 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13171 case PHY_ID_BCM5906: return "5906";
9936bcf6 13172 case PHY_ID_BCM5761: return "5761";
1da177e4
LT
13173 case PHY_ID_BCM8002: return "8002/serdes";
13174 case 0: return "serdes";
13175 default: return "unknown";
855e1111 13176 }
1da177e4
LT
13177}
13178
f9804ddb
MC
13179static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13180{
13181 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13182 strcpy(str, "PCI Express");
13183 return str;
13184 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13185 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13186
13187 strcpy(str, "PCIX:");
13188
13189 if ((clock_ctrl == 7) ||
13190 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13191 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13192 strcat(str, "133MHz");
13193 else if (clock_ctrl == 0)
13194 strcat(str, "33MHz");
13195 else if (clock_ctrl == 2)
13196 strcat(str, "50MHz");
13197 else if (clock_ctrl == 4)
13198 strcat(str, "66MHz");
13199 else if (clock_ctrl == 6)
13200 strcat(str, "100MHz");
f9804ddb
MC
13201 } else {
13202 strcpy(str, "PCI:");
13203 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13204 strcat(str, "66MHz");
13205 else
13206 strcat(str, "33MHz");
13207 }
13208 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13209 strcat(str, ":32-bit");
13210 else
13211 strcat(str, ":64-bit");
13212 return str;
13213}
13214
8c2dc7e1 13215static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT
13216{
13217 struct pci_dev *peer;
13218 unsigned int func, devnr = tp->pdev->devfn & ~7;
13219
13220 for (func = 0; func < 8; func++) {
13221 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13222 if (peer && peer != tp->pdev)
13223 break;
13224 pci_dev_put(peer);
13225 }
16fe9d74
MC
13226 /* 5704 can be configured in single-port mode, set peer to
13227 * tp->pdev in that case.
13228 */
13229 if (!peer) {
13230 peer = tp->pdev;
13231 return peer;
13232 }
1da177e4
LT
13233
13234 /*
13235 * We don't need to keep the refcount elevated; there's no way
13236 * to remove one half of this device without removing the other
13237 */
13238 pci_dev_put(peer);
13239
13240 return peer;
13241}
13242
15f9850d
DM
13243static void __devinit tg3_init_coal(struct tg3 *tp)
13244{
13245 struct ethtool_coalesce *ec = &tp->coal;
13246
13247 memset(ec, 0, sizeof(*ec));
13248 ec->cmd = ETHTOOL_GCOALESCE;
13249 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13250 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13251 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13252 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13253 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13254 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13255 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13256 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13257 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13258
13259 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13260 HOSTCC_MODE_CLRTICK_TXBD)) {
13261 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13262 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13263 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13264 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13265 }
d244c892
MC
13266
13267 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13268 ec->rx_coalesce_usecs_irq = 0;
13269 ec->tx_coalesce_usecs_irq = 0;
13270 ec->stats_block_coalesce_usecs = 0;
13271 }
15f9850d
DM
13272}
13273
7c7d64b8
SH
13274static const struct net_device_ops tg3_netdev_ops = {
13275 .ndo_open = tg3_open,
13276 .ndo_stop = tg3_close,
00829823
SH
13277 .ndo_start_xmit = tg3_start_xmit,
13278 .ndo_get_stats = tg3_get_stats,
13279 .ndo_validate_addr = eth_validate_addr,
13280 .ndo_set_multicast_list = tg3_set_rx_mode,
13281 .ndo_set_mac_address = tg3_set_mac_addr,
13282 .ndo_do_ioctl = tg3_ioctl,
13283 .ndo_tx_timeout = tg3_tx_timeout,
13284 .ndo_change_mtu = tg3_change_mtu,
13285#if TG3_VLAN_TAG_USED
13286 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13287#endif
13288#ifdef CONFIG_NET_POLL_CONTROLLER
13289 .ndo_poll_controller = tg3_poll_controller,
13290#endif
13291};
13292
13293static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13294 .ndo_open = tg3_open,
13295 .ndo_stop = tg3_close,
13296 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH
13297 .ndo_get_stats = tg3_get_stats,
13298 .ndo_validate_addr = eth_validate_addr,
13299 .ndo_set_multicast_list = tg3_set_rx_mode,
13300 .ndo_set_mac_address = tg3_set_mac_addr,
13301 .ndo_do_ioctl = tg3_ioctl,
13302 .ndo_tx_timeout = tg3_tx_timeout,
13303 .ndo_change_mtu = tg3_change_mtu,
13304#if TG3_VLAN_TAG_USED
13305 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13306#endif
13307#ifdef CONFIG_NET_POLL_CONTROLLER
13308 .ndo_poll_controller = tg3_poll_controller,
13309#endif
13310};
13311
1da177e4
LT
13312static int __devinit tg3_init_one(struct pci_dev *pdev,
13313 const struct pci_device_id *ent)
13314{
13315 static int tg3_version_printed = 0;
1da177e4
LT
13316 struct net_device *dev;
13317 struct tg3 *tp;
d6645372 13318 int err, pm_cap;
f9804ddb 13319 char str[40];
72f2afb8 13320 u64 dma_mask, persist_dma_mask;
1da177e4
LT
13321
13322 if (tg3_version_printed++ == 0)
13323 printk(KERN_INFO "%s", version);
13324
13325 err = pci_enable_device(pdev);
13326 if (err) {
13327 printk(KERN_ERR PFX "Cannot enable PCI device, "
13328 "aborting.\n");
13329 return err;
13330 }
13331
1da177e4
LT
13332 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13333 if (err) {
13334 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13335 "aborting.\n");
13336 goto err_out_disable_pdev;
13337 }
13338
13339 pci_set_master(pdev);
13340
13341 /* Find power-management capability. */
13342 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13343 if (pm_cap == 0) {
13344 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13345 "aborting.\n");
13346 err = -EIO;
13347 goto err_out_free_res;
13348 }
13349
1da177e4
LT
13350 dev = alloc_etherdev(sizeof(*tp));
13351 if (!dev) {
13352 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13353 err = -ENOMEM;
13354 goto err_out_free_res;
13355 }
13356
1da177e4
LT
13357 SET_NETDEV_DEV(dev, &pdev->dev);
13358
1da177e4
LT
13359#if TG3_VLAN_TAG_USED
13360 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT
13361#endif
13362
13363 tp = netdev_priv(dev);
13364 tp->pdev = pdev;
13365 tp->dev = dev;
13366 tp->pm_cap = pm_cap;
1da177e4
LT
13367 tp->rx_mode = TG3_DEF_RX_MODE;
13368 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13369
1da177e4
LT
13370 if (tg3_debug > 0)
13371 tp->msg_enable = tg3_debug;
13372 else
13373 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13374
13375 /* The word/byte swap controls here control register access byte
13376 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13377 * setting below.
13378 */
13379 tp->misc_host_ctrl =
13380 MISC_HOST_CTRL_MASK_PCI_INT |
13381 MISC_HOST_CTRL_WORD_SWAP |
13382 MISC_HOST_CTRL_INDIR_ACCESS |
13383 MISC_HOST_CTRL_PCISTATE_RW;
13384
13385 /* The NONFRM (non-frame) byte/word swap controls take effect
13386 * on descriptor entries, anything which isn't packet data.
13387 *
13388 * The StrongARM chips on the board (one for tx, one for rx)
13389 * are running in big-endian mode.
13390 */
13391 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13392 GRC_MODE_WSWAP_NONFRM_DATA);
13393#ifdef __BIG_ENDIAN
13394 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13395#endif
13396 spin_lock_init(&tp->lock);
1da177e4 13397 spin_lock_init(&tp->indirect_lock);
c4028958 13398 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13399
d5fe488a 13400 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13401 if (!tp->regs) {
1da177e4
LT
13402 printk(KERN_ERR PFX "Cannot map device registers, "
13403 "aborting.\n");
13404 err = -ENOMEM;
13405 goto err_out_free_dev;
13406 }
13407
13408 tg3_init_link_config(tp);
13409
1da177e4
LT
13410 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13411 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13412 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13413
8ef0442f 13414 tp->napi[0].tp = tp;
898a56f8 13415 tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
8ef0442f 13416 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 13417 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13418 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13419 dev->irq = pdev->irq;
1da177e4
LT
13420
13421 err = tg3_get_invariants(tp);
13422 if (err) {
13423 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13424 "aborting.\n");
13425 goto err_out_iounmap;
13426 }
13427
321d32a0 13428 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH
13429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13430 dev->netdev_ops = &tg3_netdev_ops;
13431 else
13432 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13433
13434
4a29cc2e
MC
13435 /* The EPB bridge inside 5714, 5715, and 5780 and any
13436 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC
13437 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13438 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13439 * do DMA address check in tg3_start_xmit().
13440 */
4a29cc2e 13441 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13442 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13443 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13444 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13445#ifdef CONFIG_HIGHMEM
6a35528a 13446 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13447#endif
4a29cc2e 13448 } else
6a35528a 13449 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC
13450
13451 /* Configure DMA attributes. */
284901a9 13452 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC
13453 err = pci_set_dma_mask(pdev, dma_mask);
13454 if (!err) {
13455 dev->features |= NETIF_F_HIGHDMA;
13456 err = pci_set_consistent_dma_mask(pdev,
13457 persist_dma_mask);
13458 if (err < 0) {
13459 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13460 "DMA for consistent allocations\n");
13461 goto err_out_iounmap;
13462 }
13463 }
13464 }
284901a9
YH
13465 if (err || dma_mask == DMA_BIT_MASK(32)) {
13466 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC
13467 if (err) {
13468 printk(KERN_ERR PFX "No usable DMA configuration, "
13469 "aborting.\n");
13470 goto err_out_iounmap;
13471 }
13472 }
13473
fdfec172 13474 tg3_init_bufmgr_config(tp);
1da177e4 13475
077f849d 13476 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13477 tp->fw_needed = FIRMWARE_TG3;
077f849d 13478
1da177e4
LT
13479 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13480 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13481 }
13482 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13483 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13484 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT
13486 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13487 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13488 } else {
7f62ad5d 13489 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13491 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13492 else
9e9fd12d 13493 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13494 }
1da177e4 13495
4e3a7aaa
MC
13496 /* TSO is on by default on chips that support hardware TSO.
13497 * Firmware TSO on older chips gives lower performance, so it
13498 * is off by default, but can be enabled using ethtool.
13499 */
b0026624 13500 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC
13501 if (dev->features & NETIF_F_IP_CSUM)
13502 dev->features |= NETIF_F_TSO;
13503 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13504 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13505 dev->features |= NETIF_F_TSO6;
57e6983c
MC
13506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13507 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13508 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC
13509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13511 dev->features |= NETIF_F_TSO_ECN;
b0026624 13512 }
1da177e4 13513
1da177e4
LT
13514
13515 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13516 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13517 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13518 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13519 tp->rx_pending = 63;
13520 }
13521
1da177e4
LT
13522 err = tg3_get_device_address(tp);
13523 if (err) {
13524 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13525 "aborting.\n");
077f849d 13526 goto err_out_fw;
1da177e4
LT
13527 }
13528
c88864df 13529 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13530 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13531 if (!tp->aperegs) {
c88864df
MC
13532 printk(KERN_ERR PFX "Cannot map APE registers, "
13533 "aborting.\n");
13534 err = -ENOMEM;
077f849d 13535 goto err_out_fw;
c88864df
MC
13536 }
13537
13538 tg3_ape_lock_init(tp);
7fd76445
MC
13539
13540 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13541 tg3_read_dash_ver(tp);
c88864df
MC
13542 }
13543
1da177e4
LT
13544 /*
13545 * Reset chip in case UNDI or EFI driver did not shutdown
13546 * DMA self test will enable WDMAC and we'll see (spurious)
13547 * pending DMA on the PCI bus at that point.
13548 */
13549 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13550 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13551 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13552 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT
13553 }
13554
13555 err = tg3_test_dma(tp);
13556 if (err) {
13557 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13558 goto err_out_apeunmap;
1da177e4
LT
13559 }
13560
1da177e4
LT
13561 /* flow control autonegotiation is default behavior */
13562 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13563 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13564
15f9850d
DM
13565 tg3_init_coal(tp);
13566
c49a1561
MC
13567 pci_set_drvdata(pdev, dev);
13568
1da177e4
LT
13569 err = register_netdev(dev);
13570 if (err) {
13571 printk(KERN_ERR PFX "Cannot register net device, "
13572 "aborting.\n");
0d3031d9 13573 goto err_out_apeunmap;
1da177e4
LT
13574 }
13575
df59c940 13576 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT
13577 dev->name,
13578 tp->board_part_number,
13579 tp->pci_chip_rev_id,
f9804ddb 13580 tg3_bus_string(tp, str),
e174961c 13581 dev->dev_addr);
1da177e4 13582
df59c940
MC
13583 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13584 printk(KERN_INFO
13585 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13586 tp->dev->name,
13587 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13588 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC
13589 else
13590 printk(KERN_INFO
13591 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13592 tp->dev->name, tg3_phy_string(tp),
13593 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13594 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13595 "10/100/1000Base-T")),
13596 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13597
13598 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT
13599 dev->name,
13600 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13601 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13602 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13603 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13604 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC
13605 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13606 dev->name, tp->dma_rwctrl,
284901a9 13607 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13608 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT
13609
13610 return 0;
13611
0d3031d9
MC
13612err_out_apeunmap:
13613 if (tp->aperegs) {
13614 iounmap(tp->aperegs);
13615 tp->aperegs = NULL;
13616 }
13617
077f849d
JSR
13618err_out_fw:
13619 if (tp->fw)
13620 release_firmware(tp->fw);
13621
1da177e4 13622err_out_iounmap:
6892914f
MC
13623 if (tp->regs) {
13624 iounmap(tp->regs);
22abe310 13625 tp->regs = NULL;
6892914f 13626 }
1da177e4
LT
13627
13628err_out_free_dev:
13629 free_netdev(dev);
13630
13631err_out_free_res:
13632 pci_release_regions(pdev);
13633
13634err_out_disable_pdev:
13635 pci_disable_device(pdev);
13636 pci_set_drvdata(pdev, NULL);
13637 return err;
13638}
13639
13640static void __devexit tg3_remove_one(struct pci_dev *pdev)
13641{
13642 struct net_device *dev = pci_get_drvdata(pdev);
13643
13644 if (dev) {
13645 struct tg3 *tp = netdev_priv(dev);
13646
077f849d
JSR
13647 if (tp->fw)
13648 release_firmware(tp->fw);
13649
7faa006f 13650 flush_scheduled_work();
158d7abd 13651
b02fd9e3
MC
13652 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13653 tg3_phy_fini(tp);
158d7abd 13654 tg3_mdio_fini(tp);
b02fd9e3 13655 }
158d7abd 13656
1da177e4 13657 unregister_netdev(dev);
0d3031d9
MC
13658 if (tp->aperegs) {
13659 iounmap(tp->aperegs);
13660 tp->aperegs = NULL;
13661 }
6892914f
MC
13662 if (tp->regs) {
13663 iounmap(tp->regs);
22abe310 13664 tp->regs = NULL;
6892914f 13665 }
1da177e4
LT
13666 free_netdev(dev);
13667 pci_release_regions(pdev);
13668 pci_disable_device(pdev);
13669 pci_set_drvdata(pdev, NULL);
13670 }
13671}
13672
13673static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13674{
13675 struct net_device *dev = pci_get_drvdata(pdev);
13676 struct tg3 *tp = netdev_priv(dev);
12dac075 13677 pci_power_t target_state;
1da177e4
LT
13678 int err;
13679
3e0c95fd
MC
13680 /* PCI register 4 needs to be saved whether netif_running() or not.
13681 * MSI address and data need to be saved if using MSI and
13682 * netif_running().
13683 */
13684 pci_save_state(pdev);
13685
1da177e4
LT
13686 if (!netif_running(dev))
13687 return 0;
13688
7faa006f 13689 flush_scheduled_work();
b02fd9e3 13690 tg3_phy_stop(tp);
1da177e4
LT
13691 tg3_netif_stop(tp);
13692
13693 del_timer_sync(&tp->timer);
13694
f47c11ee 13695 tg3_full_lock(tp, 1);
1da177e4 13696 tg3_disable_ints(tp);
f47c11ee 13697 tg3_full_unlock(tp);
1da177e4
LT
13698
13699 netif_device_detach(dev);
13700
f47c11ee 13701 tg3_full_lock(tp, 0);
944d980e 13702 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13703 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13704 tg3_full_unlock(tp);
1da177e4 13705
12dac075
RW
13706 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13707
13708 err = tg3_set_power_state(tp, target_state);
1da177e4 13709 if (err) {
b02fd9e3
MC
13710 int err2;
13711
f47c11ee 13712 tg3_full_lock(tp, 0);
1da177e4 13713
6a9eba15 13714 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC
13715 err2 = tg3_restart_hw(tp, 1);
13716 if (err2)
b9ec6c1b 13717 goto out;
1da177e4
LT
13718
13719 tp->timer.expires = jiffies + tp->timer_offset;
13720 add_timer(&tp->timer);
13721
13722 netif_device_attach(dev);
13723 tg3_netif_start(tp);
13724
b9ec6c1b 13725out:
f47c11ee 13726 tg3_full_unlock(tp);
b02fd9e3
MC
13727
13728 if (!err2)
13729 tg3_phy_start(tp);
1da177e4
LT
13730 }
13731
13732 return err;
13733}
13734
13735static int tg3_resume(struct pci_dev *pdev)
13736{
13737 struct net_device *dev = pci_get_drvdata(pdev);
13738 struct tg3 *tp = netdev_priv(dev);
13739 int err;
13740
3e0c95fd
MC
13741 pci_restore_state(tp->pdev);
13742
1da177e4
LT
13743 if (!netif_running(dev))
13744 return 0;
13745
bc1c7567 13746 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT
13747 if (err)
13748 return err;
13749
13750 netif_device_attach(dev);
13751
f47c11ee 13752 tg3_full_lock(tp, 0);
1da177e4 13753
6a9eba15 13754 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC
13755 err = tg3_restart_hw(tp, 1);
13756 if (err)
13757 goto out;
1da177e4
LT
13758
13759 tp->timer.expires = jiffies + tp->timer_offset;
13760 add_timer(&tp->timer);
13761
1da177e4
LT
13762 tg3_netif_start(tp);
13763
b9ec6c1b 13764out:
f47c11ee 13765 tg3_full_unlock(tp);
1da177e4 13766
b02fd9e3
MC
13767 if (!err)
13768 tg3_phy_start(tp);
13769
b9ec6c1b 13770 return err;
1da177e4
LT
13771}
13772
13773static struct pci_driver tg3_driver = {
13774 .name = DRV_MODULE_NAME,
13775 .id_table = tg3_pci_tbl,
13776 .probe = tg3_init_one,
13777 .remove = __devexit_p(tg3_remove_one),
13778 .suspend = tg3_suspend,
13779 .resume = tg3_resume
13780};
13781
13782static int __init tg3_init(void)
13783{
29917620 13784 return pci_register_driver(&tg3_driver);
1da177e4
LT
13785}
13786
13787static void __exit tg3_cleanup(void)
13788{
13789 pci_unregister_driver(&tg3_driver);
13790}
13791
13792module_init(tg3_init);
13793module_exit(tg3_cleanup);