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tg3 / broadcom: Refine AC131 APD support
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
daf09de8
MC		 71#define DRV_MODULE_VERSION "3.102"
72#define DRV_MODULE_RELDATE "September 1, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
c73430d0 943 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
a9daf367 956 return;
fcb389df
MC		 957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
a9daf367 980
bb85fbb6
MC		 981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
bb85fbb6
MC		 990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
a9daf367 993
a9daf367
MC		 994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
fcb389df 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014}
1015
158d7abd
MC		 1016static void tg3_mdio_start(struct tg3 *tp)
1017{
158d7abd
MC		 1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
a9daf367 1021
882e9793
MC		 1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
3f0e3ad7 1035 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1036
9c61d6bc
MC		 1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
158d7abd
MC		 1040}
1041
158d7abd
MC		 1042static int tg3_mdio_init(struct tg3 *tp)
1043{
1044 int i;
1045 u32 reg;
a9daf367 1046 struct phy_device *phydev;
158d7abd
MC		 1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
298cf9be
LB		 1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
158d7abd 1057
298cf9be
LB		 1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1070 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
298cf9be 1080 i = mdiobus_register(tp->mdio_bus);
a9daf367 1081 if (i) {
158d7abd
MC		 1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
9c61d6bc 1084 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1085 return i;
1086 }
158d7abd 1087
3f0e3ad7 1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1089
9c61d6bc
MC		 1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100 break;
a9daf367 1101 case TG3_PHY_ID_BCM50610:
c73430d0 1102 case TG3_PHY_ID_BCM50610M:
63a14ce4 1103 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE;
a9daf367
MC		 1104 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1105 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1106 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1107 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1108 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1109 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1110 /* fallthru */
1111 case TG3_PHY_ID_RTL8211C:
1112 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1113 break;
fcb389df 1114 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1115 case TG3_PHY_ID_BCMAC131:
1116 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1117 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1118 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1119 break;
1120 }
1121
9c61d6bc
MC		 1122 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1123
1124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1125 tg3_mdio_config_5785(tp);
a9daf367
MC		 1126
1127 return 0;
158d7abd
MC		 1128}
1129
1130static void tg3_mdio_fini(struct tg3 *tp)
1131{
1132 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1133 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1134 mdiobus_unregister(tp->mdio_bus);
1135 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1136 }
1137}
1138
4ba526ce
MC		 1139/* tp->lock is held. */
1140static inline void tg3_generate_fw_event(struct tg3 *tp)
1141{
1142 u32 val;
1143
1144 val = tr32(GRC_RX_CPU_EVENT);
1145 val |= GRC_RX_CPU_DRIVER_EVENT;
1146 tw32_f(GRC_RX_CPU_EVENT, val);
1147
1148 tp->last_event_jiffies = jiffies;
1149}
1150
1151#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1152
95e2869a
MC		 1153/* tp->lock is held. */
1154static void tg3_wait_for_event_ack(struct tg3 *tp)
1155{
1156 int i;
4ba526ce
MC		 1157 unsigned int delay_cnt;
1158 long time_remain;
1159
1160 /* If enough time has passed, no wait is necessary. */
1161 time_remain = (long)(tp->last_event_jiffies + 1 +
1162 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1163 (long)jiffies;
1164 if (time_remain < 0)
1165 return;
1166
1167 /* Check if we can shorten the wait time. */
1168 delay_cnt = jiffies_to_usecs(time_remain);
1169 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1170 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1171 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1172
4ba526ce 1173 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1174 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1175 break;
4ba526ce 1176 udelay(8);
95e2869a
MC		 1177 }
1178}
1179
1180/* tp->lock is held. */
1181static void tg3_ump_link_report(struct tg3 *tp)
1182{
1183 u32 reg;
1184 u32 val;
1185
1186 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1187 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1188 return;
1189
1190 tg3_wait_for_event_ack(tp);
1191
1192 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1193
1194 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1195
1196 val = 0;
1197 if (!tg3_readphy(tp, MII_BMCR, &reg))
1198 val = reg << 16;
1199 if (!tg3_readphy(tp, MII_BMSR, &reg))
1200 val |= (reg & 0xffff);
1201 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1202
1203 val = 0;
1204 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1205 val = reg << 16;
1206 if (!tg3_readphy(tp, MII_LPA, &reg))
1207 val |= (reg & 0xffff);
1208 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1209
1210 val = 0;
1211 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1212 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1213 val = reg << 16;
1214 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1215 val |= (reg & 0xffff);
1216 }
1217 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1218
1219 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1220 val = reg << 16;
1221 else
1222 val = 0;
1223 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1224
4ba526ce 1225 tg3_generate_fw_event(tp);
95e2869a
MC		 1226}
1227
1228static void tg3_link_report(struct tg3 *tp)
1229{
1230 if (!netif_carrier_ok(tp->dev)) {
1231 if (netif_msg_link(tp))
1232 printk(KERN_INFO PFX "%s: Link is down.\n",
1233 tp->dev->name);
1234 tg3_ump_link_report(tp);
1235 } else if (netif_msg_link(tp)) {
1236 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1237 tp->dev->name,
1238 (tp->link_config.active_speed == SPEED_1000 ?
1239 1000 :
1240 (tp->link_config.active_speed == SPEED_100 ?
1241 100 : 10)),
1242 (tp->link_config.active_duplex == DUPLEX_FULL ?
1243 "full" : "half"));
1244
1245 printk(KERN_INFO PFX
1246 "%s: Flow control is %s for TX and %s for RX.\n",
1247 tp->dev->name,
e18ce346 1248 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1249 "on" : "off",
e18ce346 1250 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1251 "on" : "off");
1252 tg3_ump_link_report(tp);
1253 }
1254}
1255
1256static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1257{
1258 u16 miireg;
1259
e18ce346 1260 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1261 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1262 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1263 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1264 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1265 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1266 else
1267 miireg = 0;
1268
1269 return miireg;
1270}
1271
1272static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1273{
1274 u16 miireg;
1275
e18ce346 1276 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1277 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1278 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1279 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1280 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1281 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1282 else
1283 miireg = 0;
1284
1285 return miireg;
1286}
1287
95e2869a
MC		 1288static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1289{
1290 u8 cap = 0;
1291
1292 if (lcladv & ADVERTISE_1000XPAUSE) {
1293 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1294 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1295 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1296 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1297 cap = FLOW_CTRL_RX;
95e2869a
MC		 1298 } else {
1299 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1300 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1301 }
1302 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1303 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1304 cap = FLOW_CTRL_TX;
95e2869a
MC		 1305 }
1306
1307 return cap;
1308}
1309
f51f3562 1310static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1311{
b02fd9e3 1312 u8 autoneg;
f51f3562 1313 u8 flowctrl = 0;
95e2869a
MC		 1314 u32 old_rx_mode = tp->rx_mode;
1315 u32 old_tx_mode = tp->tx_mode;
1316
b02fd9e3 1317 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1318 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1319 else
1320 autoneg = tp->link_config.autoneg;
1321
1322 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1323 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1324 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1325 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1326 else
bc02ff95 1327 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1328 } else
1329 flowctrl = tp->link_config.flowctrl;
95e2869a 1330
f51f3562 1331 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1332
e18ce346 1333 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1334 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1335 else
1336 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1337
f51f3562 1338 if (old_rx_mode != tp->rx_mode)
95e2869a 1339 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1340
e18ce346 1341 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1342 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1343 else
1344 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1345
f51f3562 1346 if (old_tx_mode != tp->tx_mode)
95e2869a 1347 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1348}
1349
b02fd9e3
MC		 1350static void tg3_adjust_link(struct net_device *dev)
1351{
1352 u8 oldflowctrl, linkmesg = 0;
1353 u32 mac_mode, lcl_adv, rmt_adv;
1354 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1355 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1356
24bb4fb6 1357 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1358
1359 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1360 MAC_MODE_HALF_DUPLEX);
1361
1362 oldflowctrl = tp->link_config.active_flowctrl;
1363
1364 if (phydev->link) {
1365 lcl_adv = 0;
1366 rmt_adv = 0;
1367
1368 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1369 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1370 else if (phydev->speed == SPEED_1000 ||
1371 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1372 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1373 else
1374 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1375
1376 if (phydev->duplex == DUPLEX_HALF)
1377 mac_mode |= MAC_MODE_HALF_DUPLEX;
1378 else {
1379 lcl_adv = tg3_advert_flowctrl_1000T(
1380 tp->link_config.flowctrl);
1381
1382 if (phydev->pause)
1383 rmt_adv = LPA_PAUSE_CAP;
1384 if (phydev->asym_pause)
1385 rmt_adv |= LPA_PAUSE_ASYM;
1386 }
1387
1388 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1389 } else
1390 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1391
1392 if (mac_mode != tp->mac_mode) {
1393 tp->mac_mode = mac_mode;
1394 tw32_f(MAC_MODE, tp->mac_mode);
1395 udelay(40);
1396 }
1397
fcb389df
MC		 1398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1399 if (phydev->speed == SPEED_10)
1400 tw32(MAC_MI_STAT,
1401 MAC_MI_STAT_10MBPS_MODE |
1402 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1403 else
1404 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1405 }
1406
b02fd9e3
MC		 1407 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1408 tw32(MAC_TX_LENGTHS,
1409 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1410 (6 << TX_LENGTHS_IPG_SHIFT) |
1411 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1412 else
1413 tw32(MAC_TX_LENGTHS,
1414 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1415 (6 << TX_LENGTHS_IPG_SHIFT) |
1416 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1417
1418 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1419 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1420 phydev->speed != tp->link_config.active_speed ||
1421 phydev->duplex != tp->link_config.active_duplex ||
1422 oldflowctrl != tp->link_config.active_flowctrl)
1423 linkmesg = 1;
1424
1425 tp->link_config.active_speed = phydev->speed;
1426 tp->link_config.active_duplex = phydev->duplex;
1427
24bb4fb6 1428 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1429
1430 if (linkmesg)
1431 tg3_link_report(tp);
1432}
1433
1434static int tg3_phy_init(struct tg3 *tp)
1435{
1436 struct phy_device *phydev;
1437
1438 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1439 return 0;
1440
1441 /* Bring the PHY back to a known state. */
1442 tg3_bmcr_reset(tp);
1443
3f0e3ad7 1444 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1445
1446 /* Attach the MAC to the PHY. */
fb28ad35 1447 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1448 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1449 if (IS_ERR(phydev)) {
1450 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1451 return PTR_ERR(phydev);
1452 }
1453
b02fd9e3 1454 /* Mask with MAC supported features. */
9c61d6bc
MC		 1455 switch (phydev->interface) {
1456 case PHY_INTERFACE_MODE_GMII:
1457 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1458 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1459 phydev->supported &= (PHY_GBIT_FEATURES |
1460 SUPPORTED_Pause |
1461 SUPPORTED_Asym_Pause);
1462 break;
1463 }
1464 /* fallthru */
9c61d6bc
MC		 1465 case PHY_INTERFACE_MODE_MII:
1466 phydev->supported &= (PHY_BASIC_FEATURES |
1467 SUPPORTED_Pause |
1468 SUPPORTED_Asym_Pause);
1469 break;
1470 default:
3f0e3ad7 1471 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1472 return -EINVAL;
1473 }
1474
1475 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1476
1477 phydev->advertising = phydev->supported;
1478
b02fd9e3
MC		 1479 return 0;
1480}
1481
1482static void tg3_phy_start(struct tg3 *tp)
1483{
1484 struct phy_device *phydev;
1485
1486 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1487 return;
1488
3f0e3ad7 1489 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1490
1491 if (tp->link_config.phy_is_low_power) {
1492 tp->link_config.phy_is_low_power = 0;
1493 phydev->speed = tp->link_config.orig_speed;
1494 phydev->duplex = tp->link_config.orig_duplex;
1495 phydev->autoneg = tp->link_config.orig_autoneg;
1496 phydev->advertising = tp->link_config.orig_advertising;
1497 }
1498
1499 phy_start(phydev);
1500
1501 phy_start_aneg(phydev);
1502}
1503
1504static void tg3_phy_stop(struct tg3 *tp)
1505{
1506 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1507 return;
1508
3f0e3ad7 1509 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1510}
1511
1512static void tg3_phy_fini(struct tg3 *tp)
1513{
1514 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1515 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1516 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1517 }
1518}
1519
b2a5c19c
MC		 1520static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1521{
1522 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1523 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1524}
1525
7f97a4bd
MC		 1526static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1527{
1528 u32 phytest;
1529
1530 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1531 u32 phy;
1532
1533 tg3_writephy(tp, MII_TG3_FET_TEST,
1534 phytest | MII_TG3_FET_SHADOW_EN);
1535 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1536 if (enable)
1537 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1538 else
1539 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1540 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1541 }
1542 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1543 }
1544}
1545
6833c043
MC		 1546static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1547{
1548 u32 reg;
1549
7f97a4bd 1550 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1551 return;
1552
7f97a4bd
MC		 1553 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1554 tg3_phy_fet_toggle_apd(tp, enable);
1555 return;
1556 }
1557
6833c043
MC		 1558 reg = MII_TG3_MISC_SHDW_WREN |
1559 MII_TG3_MISC_SHDW_SCR5_SEL |
1560 MII_TG3_MISC_SHDW_SCR5_LPED |
1561 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1562 MII_TG3_MISC_SHDW_SCR5_SDTL |
1563 MII_TG3_MISC_SHDW_SCR5_C125OE;
1564 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1565 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1566
1567 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1568
1569
1570 reg = MII_TG3_MISC_SHDW_WREN |
1571 MII_TG3_MISC_SHDW_APD_SEL |
1572 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1573 if (enable)
1574 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1575
1576 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1577}
1578
9ef8ca99
MC		 1579static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1580{
1581 u32 phy;
1582
1583 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1584 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1585 return;
1586
7f97a4bd 1587 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1588 u32 ephy;
1589
535ef6e1
MC		 1590 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1591 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1592
1593 tg3_writephy(tp, MII_TG3_FET_TEST,
1594 ephy | MII_TG3_FET_SHADOW_EN);
1595 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1596 if (enable)
535ef6e1 1597 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1598 else
535ef6e1
MC		 1599 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1600 tg3_writephy(tp, reg, phy);
9ef8ca99 1601 }
535ef6e1 1602 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1603 }
1604 } else {
1605 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1606 MII_TG3_AUXCTL_SHDWSEL_MISC;
1607 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1608 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1609 if (enable)
1610 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1611 else
1612 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1613 phy |= MII_TG3_AUXCTL_MISC_WREN;
1614 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1615 }
1616 }
1617}
1618
1da177e4
LT		 1619static void tg3_phy_set_wirespeed(struct tg3 *tp)
1620{
1621 u32 val;
1622
1623 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1624 return;
1625
1626 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1627 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1628 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1629 (val | (1 << 15) | (1 << 4)));
1630}
1631
b2a5c19c
MC		 1632static void tg3_phy_apply_otp(struct tg3 *tp)
1633{
1634 u32 otp, phy;
1635
1636 if (!tp->phy_otp)
1637 return;
1638
1639 otp = tp->phy_otp;
1640
1641 /* Enable SM_DSP clock and tx 6dB coding. */
1642 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1643 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1644 MII_TG3_AUXCTL_ACTL_TX_6DB;
1645 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1646
1647 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1648 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1649 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1650
1651 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1652 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1653 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1654
1655 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1656 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1657 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1658
1659 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1660 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1661
1662 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1663 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1664
1665 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1666 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1667 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1668
1669 /* Turn off SM_DSP clock. */
1670 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1671 MII_TG3_AUXCTL_ACTL_TX_6DB;
1672 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673}
1674
1da177e4
LT		 1675static int tg3_wait_macro_done(struct tg3 *tp)
1676{
1677 int limit = 100;
1678
1679 while (limit--) {
1680 u32 tmp32;
1681
1682 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1683 if ((tmp32 & 0x1000) == 0)
1684 break;
1685 }
1686 }
d4675b52 1687 if (limit < 0)
1da177e4
LT		 1688 return -EBUSY;
1689
1690 return 0;
1691}
1692
1693static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1694{
1695 static const u32 test_pat[4][6] = {
1696 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1697 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1698 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1699 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1700 };
1701 int chan;
1702
1703 for (chan = 0; chan < 4; chan++) {
1704 int i;
1705
1706 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1707 (chan * 0x2000) | 0x0200);
1708 tg3_writephy(tp, 0x16, 0x0002);
1709
1710 for (i = 0; i < 6; i++)
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1712 test_pat[chan][i]);
1713
1714 tg3_writephy(tp, 0x16, 0x0202);
1715 if (tg3_wait_macro_done(tp)) {
1716 *resetp = 1;
1717 return -EBUSY;
1718 }
1719
1720 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1721 (chan * 0x2000) | 0x0200);
1722 tg3_writephy(tp, 0x16, 0x0082);
1723 if (tg3_wait_macro_done(tp)) {
1724 *resetp = 1;
1725 return -EBUSY;
1726 }
1727
1728 tg3_writephy(tp, 0x16, 0x0802);
1729 if (tg3_wait_macro_done(tp)) {
1730 *resetp = 1;
1731 return -EBUSY;
1732 }
1733
1734 for (i = 0; i < 6; i += 2) {
1735 u32 low, high;
1736
1737 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1738 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1739 tg3_wait_macro_done(tp)) {
1740 *resetp = 1;
1741 return -EBUSY;
1742 }
1743 low &= 0x7fff;
1744 high &= 0x000f;
1745 if (low != test_pat[chan][i] ||
1746 high != test_pat[chan][i+1]) {
1747 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1748 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1749 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1750
1751 return -EBUSY;
1752 }
1753 }
1754 }
1755
1756 return 0;
1757}
1758
1759static int tg3_phy_reset_chanpat(struct tg3 *tp)
1760{
1761 int chan;
1762
1763 for (chan = 0; chan < 4; chan++) {
1764 int i;
1765
1766 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1767 (chan * 0x2000) | 0x0200);
1768 tg3_writephy(tp, 0x16, 0x0002);
1769 for (i = 0; i < 6; i++)
1770 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1771 tg3_writephy(tp, 0x16, 0x0202);
1772 if (tg3_wait_macro_done(tp))
1773 return -EBUSY;
1774 }
1775
1776 return 0;
1777}
1778
1779static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1780{
1781 u32 reg32, phy9_orig;
1782 int retries, do_phy_reset, err;
1783
1784 retries = 10;
1785 do_phy_reset = 1;
1786 do {
1787 if (do_phy_reset) {
1788 err = tg3_bmcr_reset(tp);
1789 if (err)
1790 return err;
1791 do_phy_reset = 0;
1792 }
1793
1794 /* Disable transmitter and interrupt. */
1795 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1796 continue;
1797
1798 reg32 |= 0x3000;
1799 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1800
1801 /* Set full-duplex, 1000 mbps. */
1802 tg3_writephy(tp, MII_BMCR,
1803 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1804
1805 /* Set to master mode. */
1806 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1807 continue;
1808
1809 tg3_writephy(tp, MII_TG3_CTRL,
1810 (MII_TG3_CTRL_AS_MASTER |
1811 MII_TG3_CTRL_ENABLE_AS_MASTER));
1812
1813 /* Enable SM_DSP_CLOCK and 6dB. */
1814 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1815
1816 /* Block the PHY control access. */
1817 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1818 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1819
1820 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1821 if (!err)
1822 break;
1823 } while (--retries);
1824
1825 err = tg3_phy_reset_chanpat(tp);
1826 if (err)
1827 return err;
1828
1829 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1830 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1831
1832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1833 tg3_writephy(tp, 0x16, 0x0000);
1834
1835 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1837 /* Set Extended packet length bit for jumbo frames */
1838 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1839 }
1840 else {
1841 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1842 }
1843
1844 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1845
1846 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1847 reg32 &= ~0x3000;
1848 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1849 } else if (!err)
1850 err = -EBUSY;
1851
1852 return err;
1853}
1854
1855/* This will reset the tigon3 PHY if there is no valid
1856 * link unless the FORCE argument is non-zero.
1857 */
1858static int tg3_phy_reset(struct tg3 *tp)
1859{
b2a5c19c 1860 u32 cpmuctrl;
1da177e4
LT		 1861 u32 phy_status;
1862 int err;
1863
60189ddf
MC		 1864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1865 u32 val;
1866
1867 val = tr32(GRC_MISC_CFG);
1868 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1869 udelay(40);
1870 }
1da177e4
LT		 1871 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1872 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1873 if (err != 0)
1874 return -EBUSY;
1875
c8e1e82b
MC		 1876 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1877 netif_carrier_off(tp->dev);
1878 tg3_link_report(tp);
1879 }
1880
1da177e4
LT		 1881 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1884 err = tg3_phy_reset_5703_4_5(tp);
1885 if (err)
1886 return err;
1887 goto out;
1888 }
1889
b2a5c19c
MC		 1890 cpmuctrl = 0;
1891 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1892 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1893 cpmuctrl = tr32(TG3_CPMU_CTRL);
1894 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1895 tw32(TG3_CPMU_CTRL,
1896 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1897 }
1898
1da177e4
LT		 1899 err = tg3_bmcr_reset(tp);
1900 if (err)
1901 return err;
1902
b2a5c19c
MC		 1903 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1904 u32 phy;
1905
1906 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1907 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1908
1909 tw32(TG3_CPMU_CTRL, cpmuctrl);
1910 }
1911
bcb37f6c
MC		 1912 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1913 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1914 u32 val;
1915
1916 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1917 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1918 CPMU_LSPD_1000MB_MACCLK_12_5) {
1919 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1920 udelay(40);
1921 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1922 }
1923 }
1924
b2a5c19c
MC		 1925 tg3_phy_apply_otp(tp);
1926
6833c043
MC		 1927 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1928 tg3_phy_toggle_apd(tp, true);
1929 else
1930 tg3_phy_toggle_apd(tp, false);
1931
1da177e4
LT		 1932out:
1933 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1935 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1936 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1937 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1938 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1940 }
1941 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1942 tg3_writephy(tp, 0x1c, 0x8d68);
1943 tg3_writephy(tp, 0x1c, 0x8d68);
1944 }
1945 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1946 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1947 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1948 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1949 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1950 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1951 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1953 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1954 }
c424cb24
MC		 1955 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1956 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1957 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1959 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1960 tg3_writephy(tp, MII_TG3_TEST1,
1961 MII_TG3_TEST1_TRIM_EN | 0x4);
1962 } else
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1965 }
1da177e4
LT		 1966 /* Set Extended packet length bit (bit 14) on all chips that */
1967 /* support jumbo frames */
1968 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1969 /* Cannot do read-modify-write on 5401 */
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1971 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1972 u32 phy_reg;
1973
1974 /* Set bit 14 with read-modify-write to preserve other bits */
1975 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1976 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1978 }
1979
1980 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1981 * jumbo frames transmission.
1982 */
8f666b07 1983 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1984 u32 phy_reg;
1985
1986 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1987 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1988 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1989 }
1990
715116a1 1991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1992 /* adjust output voltage */
535ef6e1 1993 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1994 }
1995
9ef8ca99 1996 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1997 tg3_phy_set_wirespeed(tp);
1998 return 0;
1999}
2000
2001static void tg3_frob_aux_power(struct tg3 *tp)
2002{
2003 struct tg3 *tp_peer = tp;
2004
9d26e213 2005 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2006 return;
2007
f6eb9b1f
MC		 2008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2011 struct net_device *dev_peer;
2012
2013 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2014 /* remove_one() may have been run on the peer. */
8c2dc7e1 2015 if (!dev_peer)
bc1c7567
MC		 2016 tp_peer = tp;
2017 else
2018 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2019 }
2020
1da177e4 2021 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2022 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2023 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2024 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2027 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2028 (GRC_LCLCTRL_GPIO_OE0 |
2029 GRC_LCLCTRL_GPIO_OE1 |
2030 GRC_LCLCTRL_GPIO_OE2 |
2031 GRC_LCLCTRL_GPIO_OUTPUT0 |
2032 GRC_LCLCTRL_GPIO_OUTPUT1),
2033 100);
8d519ab2
MC		 2034 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2035 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2036 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2037 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2038 GRC_LCLCTRL_GPIO_OE1 |
2039 GRC_LCLCTRL_GPIO_OE2 |
2040 GRC_LCLCTRL_GPIO_OUTPUT0 |
2041 GRC_LCLCTRL_GPIO_OUTPUT1 |
2042 tp->grc_local_ctrl;
2043 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2044
2045 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2046 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2047
2048 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2049 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2050 } else {
2051 u32 no_gpio2;
dc56b7d4 2052 u32 grc_local_ctrl = 0;
1da177e4
LT		 2053
2054 if (tp_peer != tp &&
2055 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2056 return;
2057
dc56b7d4
MC		 2058 /* Workaround to prevent overdrawing Amps. */
2059 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2060 ASIC_REV_5714) {
2061 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2062 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2063 grc_local_ctrl, 100);
dc56b7d4
MC		 2064 }
2065
1da177e4
LT		 2066 /* On 5753 and variants, GPIO2 cannot be used. */
2067 no_gpio2 = tp->nic_sram_data_cfg &
2068 NIC_SRAM_DATA_CFG_NO_GPIO2;
2069
dc56b7d4 2070 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2071 GRC_LCLCTRL_GPIO_OE1 |
2072 GRC_LCLCTRL_GPIO_OE2 |
2073 GRC_LCLCTRL_GPIO_OUTPUT1 |
2074 GRC_LCLCTRL_GPIO_OUTPUT2;
2075 if (no_gpio2) {
2076 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2077 GRC_LCLCTRL_GPIO_OUTPUT2);
2078 }
b401e9e2
MC		 2079 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2080 grc_local_ctrl, 100);
1da177e4
LT		 2081
2082 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2083
b401e9e2
MC		 2084 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2085 grc_local_ctrl, 100);
1da177e4
LT		 2086
2087 if (!no_gpio2) {
2088 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2089 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090 grc_local_ctrl, 100);
1da177e4
LT		 2091 }
2092 }
2093 } else {
2094 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2096 if (tp_peer != tp &&
2097 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2098 return;
2099
b401e9e2
MC		 2100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101 (GRC_LCLCTRL_GPIO_OE1 |
2102 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2103
b401e9e2
MC		 2104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2106
b401e9e2
MC		 2107 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2108 (GRC_LCLCTRL_GPIO_OE1 |
2109 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2110 }
2111 }
2112}
2113
e8f3f6ca
MC		 2114static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2115{
2116 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2117 return 1;
2118 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2119 if (speed != SPEED_10)
2120 return 1;
2121 } else if (speed == SPEED_10)
2122 return 1;
2123
2124 return 0;
2125}
2126
1da177e4
LT		 2127static int tg3_setup_phy(struct tg3 *, int);
2128
2129#define RESET_KIND_SHUTDOWN 0
2130#define RESET_KIND_INIT 1
2131#define RESET_KIND_SUSPEND 2
2132
2133static void tg3_write_sig_post_reset(struct tg3 *, int);
2134static int tg3_halt_cpu(struct tg3 *, u32);
2135
0a459aac 2136static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2137{
ce057f01
MC		 2138 u32 val;
2139
5129724a
MC		 2140 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2142 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2143 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2144
2145 sg_dig_ctrl |=
2146 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2147 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2148 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2149 }
3f7045c1 2150 return;
5129724a 2151 }
3f7045c1 2152
60189ddf 2153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2154 tg3_bmcr_reset(tp);
2155 val = tr32(GRC_MISC_CFG);
2156 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2157 udelay(40);
2158 return;
0e5f784c
MC		 2159 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2160 u32 phytest;
2161 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2162 u32 phy;
2163
2164 tg3_writephy(tp, MII_ADVERTISE, 0);
2165 tg3_writephy(tp, MII_BMCR,
2166 BMCR_ANENABLE | BMCR_ANRESTART);
2167
2168 tg3_writephy(tp, MII_TG3_FET_TEST,
2169 phytest | MII_TG3_FET_SHADOW_EN);
2170 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2171 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2172 tg3_writephy(tp,
2173 MII_TG3_FET_SHDW_AUXMODE4,
2174 phy);
2175 }
2176 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2177 }
2178 return;
0a459aac 2179 } else if (do_low_power) {
715116a1
MC		 2180 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2181 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2182
2183 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2184 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2185 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2186 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2187 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2188 }
3f7045c1 2189
15c3b696
MC		 2190 /* The PHY should not be powered down on some chips because
2191 * of bugs.
2192 */
2193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2195 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2196 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2197 return;
ce057f01 2198
bcb37f6c
MC		 2199 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2200 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2201 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2202 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2203 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2204 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2205 }
2206
15c3b696
MC		 2207 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2208}
2209
ffbcfed4
MC		 2210/* tp->lock is held. */
2211static int tg3_nvram_lock(struct tg3 *tp)
2212{
2213 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2214 int i;
2215
2216 if (tp->nvram_lock_cnt == 0) {
2217 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2218 for (i = 0; i < 8000; i++) {
2219 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2220 break;
2221 udelay(20);
2222 }
2223 if (i == 8000) {
2224 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2225 return -ENODEV;
2226 }
2227 }
2228 tp->nvram_lock_cnt++;
2229 }
2230 return 0;
2231}
2232
2233/* tp->lock is held. */
2234static void tg3_nvram_unlock(struct tg3 *tp)
2235{
2236 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2237 if (tp->nvram_lock_cnt > 0)
2238 tp->nvram_lock_cnt--;
2239 if (tp->nvram_lock_cnt == 0)
2240 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2241 }
2242}
2243
2244/* tp->lock is held. */
2245static void tg3_enable_nvram_access(struct tg3 *tp)
2246{
2247 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2248 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2249 u32 nvaccess = tr32(NVRAM_ACCESS);
2250
2251 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2252 }
2253}
2254
2255/* tp->lock is held. */
2256static void tg3_disable_nvram_access(struct tg3 *tp)
2257{
2258 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2259 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2260 u32 nvaccess = tr32(NVRAM_ACCESS);
2261
2262 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2263 }
2264}
2265
2266static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2267 u32 offset, u32 *val)
2268{
2269 u32 tmp;
2270 int i;
2271
2272 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2273 return -EINVAL;
2274
2275 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2276 EEPROM_ADDR_DEVID_MASK |
2277 EEPROM_ADDR_READ);
2278 tw32(GRC_EEPROM_ADDR,
2279 tmp |
2280 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2281 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2282 EEPROM_ADDR_ADDR_MASK) |
2283 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2284
2285 for (i = 0; i < 1000; i++) {
2286 tmp = tr32(GRC_EEPROM_ADDR);
2287
2288 if (tmp & EEPROM_ADDR_COMPLETE)
2289 break;
2290 msleep(1);
2291 }
2292 if (!(tmp & EEPROM_ADDR_COMPLETE))
2293 return -EBUSY;
2294
62cedd11
MC		 2295 tmp = tr32(GRC_EEPROM_DATA);
2296
2297 /*
2298 * The data will always be opposite the native endian
2299 * format. Perform a blind byteswap to compensate.
2300 */
2301 *val = swab32(tmp);
2302
ffbcfed4
MC		 2303 return 0;
2304}
2305
2306#define NVRAM_CMD_TIMEOUT 10000
2307
2308static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2309{
2310 int i;
2311
2312 tw32(NVRAM_CMD, nvram_cmd);
2313 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2314 udelay(10);
2315 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2316 udelay(10);
2317 break;
2318 }
2319 }
2320
2321 if (i == NVRAM_CMD_TIMEOUT)
2322 return -EBUSY;
2323
2324 return 0;
2325}
2326
2327static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2328{
2329 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2330 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2331 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2332 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2333 (tp->nvram_jedecnum == JEDEC_ATMEL))
2334
2335 addr = ((addr / tp->nvram_pagesize) <<
2336 ATMEL_AT45DB0X1B_PAGE_POS) +
2337 (addr % tp->nvram_pagesize);
2338
2339 return addr;
2340}
2341
2342static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2343{
2344 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2345 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2346 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2347 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2348 (tp->nvram_jedecnum == JEDEC_ATMEL))
2349
2350 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2351 tp->nvram_pagesize) +
2352 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2353
2354 return addr;
2355}
2356
e4f34110
MC		 2357/* NOTE: Data read in from NVRAM is byteswapped according to
2358 * the byteswapping settings for all other register accesses.
2359 * tg3 devices are BE devices, so on a BE machine, the data
2360 * returned will be exactly as it is seen in NVRAM. On a LE
2361 * machine, the 32-bit value will be byteswapped.
2362 */
ffbcfed4
MC		 2363static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2364{
2365 int ret;
2366
2367 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2368 return tg3_nvram_read_using_eeprom(tp, offset, val);
2369
2370 offset = tg3_nvram_phys_addr(tp, offset);
2371
2372 if (offset > NVRAM_ADDR_MSK)
2373 return -EINVAL;
2374
2375 ret = tg3_nvram_lock(tp);
2376 if (ret)
2377 return ret;
2378
2379 tg3_enable_nvram_access(tp);
2380
2381 tw32(NVRAM_ADDR, offset);
2382 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2383 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2384
2385 if (ret == 0)
e4f34110 2386 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2387
2388 tg3_disable_nvram_access(tp);
2389
2390 tg3_nvram_unlock(tp);
2391
2392 return ret;
2393}
2394
a9dc529d
MC		 2395/* Ensures NVRAM data is in bytestream format. */
2396static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2397{
2398 u32 v;
a9dc529d 2399 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2400 if (!res)
a9dc529d 2401 *val = cpu_to_be32(v);
ffbcfed4
MC		 2402 return res;
2403}
2404
3f007891
MC		 2405/* tp->lock is held. */
2406static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2407{
2408 u32 addr_high, addr_low;
2409 int i;
2410
2411 addr_high = ((tp->dev->dev_addr[0] << 8) |
2412 tp->dev->dev_addr[1]);
2413 addr_low = ((tp->dev->dev_addr[2] << 24) |
2414 (tp->dev->dev_addr[3] << 16) |
2415 (tp->dev->dev_addr[4] << 8) |
2416 (tp->dev->dev_addr[5] << 0));
2417 for (i = 0; i < 4; i++) {
2418 if (i == 1 && skip_mac_1)
2419 continue;
2420 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2421 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2422 }
2423
2424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2426 for (i = 0; i < 12; i++) {
2427 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2428 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2429 }
2430 }
2431
2432 addr_high = (tp->dev->dev_addr[0] +
2433 tp->dev->dev_addr[1] +
2434 tp->dev->dev_addr[2] +
2435 tp->dev->dev_addr[3] +
2436 tp->dev->dev_addr[4] +
2437 tp->dev->dev_addr[5]) &
2438 TX_BACKOFF_SEED_MASK;
2439 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2440}
2441
bc1c7567 2442static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2443{
2444 u32 misc_host_ctrl;
0a459aac 2445 bool device_should_wake, do_low_power;
1da177e4
LT		 2446
2447 /* Make sure register accesses (indirect or otherwise)
2448 * will function correctly.
2449 */
2450 pci_write_config_dword(tp->pdev,
2451 TG3PCI_MISC_HOST_CTRL,
2452 tp->misc_host_ctrl);
2453
1da177e4 2454 switch (state) {
bc1c7567 2455 case PCI_D0:
12dac075
RW		 2456 pci_enable_wake(tp->pdev, state, false);
2457 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2458
9d26e213
MC		 2459 /* Switch out of Vaux if it is a NIC */
2460 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2461 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2462
2463 return 0;
2464
bc1c7567 2465 case PCI_D1:
bc1c7567 2466 case PCI_D2:
bc1c7567 2467 case PCI_D3hot:
1da177e4
LT		 2468 break;
2469
2470 default:
12dac075
RW		 2471 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2472 tp->dev->name, state);
1da177e4 2473 return -EINVAL;
855e1111 2474 }
5e7dfd0f
MC		 2475
2476 /* Restore the CLKREQ setting. */
2477 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2478 u16 lnkctl;
2479
2480 pci_read_config_word(tp->pdev,
2481 tp->pcie_cap + PCI_EXP_LNKCTL,
2482 &lnkctl);
2483 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2484 pci_write_config_word(tp->pdev,
2485 tp->pcie_cap + PCI_EXP_LNKCTL,
2486 lnkctl);
2487 }
2488
1da177e4
LT		 2489 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2490 tw32(TG3PCI_MISC_HOST_CTRL,
2491 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2492
05ac4cb7
MC		 2493 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2494 device_may_wakeup(&tp->pdev->dev) &&
2495 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2496
dd477003 2497 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2498 do_low_power = false;
b02fd9e3
MC		 2499 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2500 !tp->link_config.phy_is_low_power) {
2501 struct phy_device *phydev;
0a459aac 2502 u32 phyid, advertising;
b02fd9e3 2503
3f0e3ad7 2504 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2505
2506 tp->link_config.phy_is_low_power = 1;
2507
2508 tp->link_config.orig_speed = phydev->speed;
2509 tp->link_config.orig_duplex = phydev->duplex;
2510 tp->link_config.orig_autoneg = phydev->autoneg;
2511 tp->link_config.orig_advertising = phydev->advertising;
2512
2513 advertising = ADVERTISED_TP |
2514 ADVERTISED_Pause |
2515 ADVERTISED_Autoneg |
2516 ADVERTISED_10baseT_Half;
2517
2518 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2519 device_should_wake) {
b02fd9e3
MC		 2520 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2521 advertising |=
2522 ADVERTISED_100baseT_Half |
2523 ADVERTISED_100baseT_Full |
2524 ADVERTISED_10baseT_Full;
2525 else
2526 advertising |= ADVERTISED_10baseT_Full;
2527 }
2528
2529 phydev->advertising = advertising;
2530
2531 phy_start_aneg(phydev);
0a459aac
MC		 2532
2533 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2534 if (phyid != TG3_PHY_ID_BCMAC131) {
2535 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2536 if (phyid == TG3_PHY_OUI_1 ||
2537 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2538 phyid == TG3_PHY_OUI_3)
2539 do_low_power = true;
2540 }
b02fd9e3 2541 }
dd477003 2542 } else {
2023276e 2543 do_low_power = true;
0a459aac 2544
dd477003
MC		 2545 if (tp->link_config.phy_is_low_power == 0) {
2546 tp->link_config.phy_is_low_power = 1;
2547 tp->link_config.orig_speed = tp->link_config.speed;
2548 tp->link_config.orig_duplex = tp->link_config.duplex;
2549 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2550 }
1da177e4 2551
dd477003
MC		 2552 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2553 tp->link_config.speed = SPEED_10;
2554 tp->link_config.duplex = DUPLEX_HALF;
2555 tp->link_config.autoneg = AUTONEG_ENABLE;
2556 tg3_setup_phy(tp, 0);
2557 }
1da177e4
LT		 2558 }
2559
b5d3772c
MC		 2560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2561 u32 val;
2562
2563 val = tr32(GRC_VCPU_EXT_CTRL);
2564 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2565 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2566 int i;
2567 u32 val;
2568
2569 for (i = 0; i < 200; i++) {
2570 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2571 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2572 break;
2573 msleep(1);
2574 }
2575 }
a85feb8c
GZ		 2576 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2577 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2578 WOL_DRV_STATE_SHUTDOWN |
2579 WOL_DRV_WOL |
2580 WOL_SET_MAGIC_PKT);
6921d201 2581
05ac4cb7 2582 if (device_should_wake) {
1da177e4
LT		 2583 u32 mac_mode;
2584
2585 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2586 if (do_low_power) {
dd477003
MC		 2587 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2588 udelay(40);
2589 }
1da177e4 2590
3f7045c1
MC		 2591 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2592 mac_mode = MAC_MODE_PORT_MODE_GMII;
2593 else
2594 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2595
e8f3f6ca
MC		 2596 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2597 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2598 ASIC_REV_5700) {
2599 u32 speed = (tp->tg3_flags &
2600 TG3_FLAG_WOL_SPEED_100MB) ?
2601 SPEED_100 : SPEED_10;
2602 if (tg3_5700_link_polarity(tp, speed))
2603 mac_mode |= MAC_MODE_LINK_POLARITY;
2604 else
2605 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2606 }
1da177e4
LT		 2607 } else {
2608 mac_mode = MAC_MODE_PORT_MODE_TBI;
2609 }
2610
cbf46853 2611 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2612 tw32(MAC_LED_CTRL, tp->led_ctrl);
2613
05ac4cb7
MC		 2614 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2615 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2616 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2617 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2618 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2619 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2620
3bda1258
MC		 2621 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2622 mac_mode |= tp->mac_mode &
2623 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2624 if (mac_mode & MAC_MODE_APE_TX_EN)
2625 mac_mode |= MAC_MODE_TDE_ENABLE;
2626 }
2627
1da177e4
LT		 2628 tw32_f(MAC_MODE, mac_mode);
2629 udelay(100);
2630
2631 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2632 udelay(10);
2633 }
2634
2635 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2636 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2638 u32 base_val;
2639
2640 base_val = tp->pci_clock_ctrl;
2641 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2642 CLOCK_CTRL_TXCLK_DISABLE);
2643
b401e9e2
MC		 2644 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2645 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2646 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2647 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2648 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2649 /* do nothing */
85e94ced 2650 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2651 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2652 u32 newbits1, newbits2;
2653
2654 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2656 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2657 CLOCK_CTRL_TXCLK_DISABLE |
2658 CLOCK_CTRL_ALTCLK);
2659 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2660 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2661 newbits1 = CLOCK_CTRL_625_CORE;
2662 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2663 } else {
2664 newbits1 = CLOCK_CTRL_ALTCLK;
2665 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2666 }
2667
b401e9e2
MC		 2668 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2669 40);
1da177e4 2670
b401e9e2
MC		 2671 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2672 40);
1da177e4
LT		 2673
2674 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2675 u32 newbits3;
2676
2677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2678 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2679 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2680 CLOCK_CTRL_TXCLK_DISABLE |
2681 CLOCK_CTRL_44MHZ_CORE);
2682 } else {
2683 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2684 }
2685
b401e9e2
MC		 2686 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2687 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2688 }
2689 }
2690
05ac4cb7 2691 if (!(device_should_wake) &&
22435849 2692 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2693 tg3_power_down_phy(tp, do_low_power);
6921d201 2694
1da177e4
LT		 2695 tg3_frob_aux_power(tp);
2696
2697 /* Workaround for unstable PLL clock */
2698 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2699 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2700 u32 val = tr32(0x7d00);
2701
2702 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2703 tw32(0x7d00, val);
6921d201 2704 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2705 int err;
2706
2707 err = tg3_nvram_lock(tp);
1da177e4 2708 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2709 if (!err)
2710 tg3_nvram_unlock(tp);
6921d201 2711 }
1da177e4
LT		 2712 }
2713
bbadf503
MC		 2714 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2715
05ac4cb7 2716 if (device_should_wake)
12dac075
RW		 2717 pci_enable_wake(tp->pdev, state, true);
2718
1da177e4 2719 /* Finally, set the new power state. */
12dac075 2720 pci_set_power_state(tp->pdev, state);
1da177e4 2721
1da177e4
LT		 2722 return 0;
2723}
2724
1da177e4
LT		 2725static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2726{
2727 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2728 case MII_TG3_AUX_STAT_10HALF:
2729 *speed = SPEED_10;
2730 *duplex = DUPLEX_HALF;
2731 break;
2732
2733 case MII_TG3_AUX_STAT_10FULL:
2734 *speed = SPEED_10;
2735 *duplex = DUPLEX_FULL;
2736 break;
2737
2738 case MII_TG3_AUX_STAT_100HALF:
2739 *speed = SPEED_100;
2740 *duplex = DUPLEX_HALF;
2741 break;
2742
2743 case MII_TG3_AUX_STAT_100FULL:
2744 *speed = SPEED_100;
2745 *duplex = DUPLEX_FULL;
2746 break;
2747
2748 case MII_TG3_AUX_STAT_1000HALF:
2749 *speed = SPEED_1000;
2750 *duplex = DUPLEX_HALF;
2751 break;
2752
2753 case MII_TG3_AUX_STAT_1000FULL:
2754 *speed = SPEED_1000;
2755 *duplex = DUPLEX_FULL;
2756 break;
2757
2758 default:
7f97a4bd 2759 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2760 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2761 SPEED_10;
2762 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2763 DUPLEX_HALF;
2764 break;
2765 }
1da177e4
LT		 2766 *speed = SPEED_INVALID;
2767 *duplex = DUPLEX_INVALID;
2768 break;
855e1111 2769 }
1da177e4
LT		 2770}
2771
2772static void tg3_phy_copper_begin(struct tg3 *tp)
2773{
2774 u32 new_adv;
2775 int i;
2776
2777 if (tp->link_config.phy_is_low_power) {
2778 /* Entering low power mode. Disable gigabit and
2779 * 100baseT advertisements.
2780 */
2781 tg3_writephy(tp, MII_TG3_CTRL, 0);
2782
2783 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2784 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2785 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2786 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2787
2788 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2789 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2790 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2791 tp->link_config.advertising &=
2792 ~(ADVERTISED_1000baseT_Half |
2793 ADVERTISED_1000baseT_Full);
2794
ba4d07a8 2795 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2796 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2797 new_adv |= ADVERTISE_10HALF;
2798 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2799 new_adv |= ADVERTISE_10FULL;
2800 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2801 new_adv |= ADVERTISE_100HALF;
2802 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2803 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2804
2805 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2806
1da177e4
LT		 2807 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2808
2809 if (tp->link_config.advertising &
2810 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2811 new_adv = 0;
2812 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2813 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2814 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2815 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2816 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2817 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2818 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2819 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2820 MII_TG3_CTRL_ENABLE_AS_MASTER);
2821 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2822 } else {
2823 tg3_writephy(tp, MII_TG3_CTRL, 0);
2824 }
2825 } else {
ba4d07a8
MC		 2826 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2827 new_adv |= ADVERTISE_CSMA;
2828
1da177e4
LT		 2829 /* Asking for a specific link mode. */
2830 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2831 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2832
2833 if (tp->link_config.duplex == DUPLEX_FULL)
2834 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2835 else
2836 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2837 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2838 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2839 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2840 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2841 } else {
1da177e4
LT		 2842 if (tp->link_config.speed == SPEED_100) {
2843 if (tp->link_config.duplex == DUPLEX_FULL)
2844 new_adv |= ADVERTISE_100FULL;
2845 else
2846 new_adv |= ADVERTISE_100HALF;
2847 } else {
2848 if (tp->link_config.duplex == DUPLEX_FULL)
2849 new_adv |= ADVERTISE_10FULL;
2850 else
2851 new_adv |= ADVERTISE_10HALF;
2852 }
2853 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2854
2855 new_adv = 0;
1da177e4 2856 }
ba4d07a8
MC		 2857
2858 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2859 }
2860
2861 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2862 tp->link_config.speed != SPEED_INVALID) {
2863 u32 bmcr, orig_bmcr;
2864
2865 tp->link_config.active_speed = tp->link_config.speed;
2866 tp->link_config.active_duplex = tp->link_config.duplex;
2867
2868 bmcr = 0;
2869 switch (tp->link_config.speed) {
2870 default:
2871 case SPEED_10:
2872 break;
2873
2874 case SPEED_100:
2875 bmcr |= BMCR_SPEED100;
2876 break;
2877
2878 case SPEED_1000:
2879 bmcr |= TG3_BMCR_SPEED1000;
2880 break;
855e1111 2881 }
1da177e4
LT		 2882
2883 if (tp->link_config.duplex == DUPLEX_FULL)
2884 bmcr |= BMCR_FULLDPLX;
2885
2886 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2887 (bmcr != orig_bmcr)) {
2888 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2889 for (i = 0; i < 1500; i++) {
2890 u32 tmp;
2891
2892 udelay(10);
2893 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2894 tg3_readphy(tp, MII_BMSR, &tmp))
2895 continue;
2896 if (!(tmp & BMSR_LSTATUS)) {
2897 udelay(40);
2898 break;
2899 }
2900 }
2901 tg3_writephy(tp, MII_BMCR, bmcr);
2902 udelay(40);
2903 }
2904 } else {
2905 tg3_writephy(tp, MII_BMCR,
2906 BMCR_ANENABLE | BMCR_ANRESTART);
2907 }
2908}
2909
2910static int tg3_init_5401phy_dsp(struct tg3 *tp)
2911{
2912 int err;
2913
2914 /* Turn off tap power management. */
2915 /* Set Extended packet length bit */
2916 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2917
2918 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2919 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2920
2921 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2922 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2923
2924 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2925 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2926
2927 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2928 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2929
2930 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2931 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2932
2933 udelay(40);
2934
2935 return err;
2936}
2937
3600d918 2938static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2939{
3600d918
MC		 2940 u32 adv_reg, all_mask = 0;
2941
2942 if (mask & ADVERTISED_10baseT_Half)
2943 all_mask |= ADVERTISE_10HALF;
2944 if (mask & ADVERTISED_10baseT_Full)
2945 all_mask |= ADVERTISE_10FULL;
2946 if (mask & ADVERTISED_100baseT_Half)
2947 all_mask |= ADVERTISE_100HALF;
2948 if (mask & ADVERTISED_100baseT_Full)
2949 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2950
2951 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2952 return 0;
2953
1da177e4
LT		 2954 if ((adv_reg & all_mask) != all_mask)
2955 return 0;
2956 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2957 u32 tg3_ctrl;
2958
3600d918
MC		 2959 all_mask = 0;
2960 if (mask & ADVERTISED_1000baseT_Half)
2961 all_mask |= ADVERTISE_1000HALF;
2962 if (mask & ADVERTISED_1000baseT_Full)
2963 all_mask |= ADVERTISE_1000FULL;
2964
1da177e4
LT		 2965 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2966 return 0;
2967
1da177e4
LT		 2968 if ((tg3_ctrl & all_mask) != all_mask)
2969 return 0;
2970 }
2971 return 1;
2972}
2973
ef167e27
MC		 2974static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2975{
2976 u32 curadv, reqadv;
2977
2978 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2979 return 1;
2980
2981 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2982 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2983
2984 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2985 if (curadv != reqadv)
2986 return 0;
2987
2988 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2989 tg3_readphy(tp, MII_LPA, rmtadv);
2990 } else {
2991 /* Reprogram the advertisement register, even if it
2992 * does not affect the current link. If the link
2993 * gets renegotiated in the future, we can save an
2994 * additional renegotiation cycle by advertising
2995 * it correctly in the first place.
2996 */
2997 if (curadv != reqadv) {
2998 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2999 ADVERTISE_PAUSE_ASYM);
3000 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3001 }
3002 }
3003
3004 return 1;
3005}
3006
1da177e4
LT		 3007static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3008{
3009 int current_link_up;
3010 u32 bmsr, dummy;
ef167e27 3011 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3012 u16 current_speed;
3013 u8 current_duplex;
3014 int i, err;
3015
3016 tw32(MAC_EVENT, 0);
3017
3018 tw32_f(MAC_STATUS,
3019 (MAC_STATUS_SYNC_CHANGED |
3020 MAC_STATUS_CFG_CHANGED |
3021 MAC_STATUS_MI_COMPLETION |
3022 MAC_STATUS_LNKSTATE_CHANGED));
3023 udelay(40);
3024
8ef21428
MC		 3025 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3026 tw32_f(MAC_MI_MODE,
3027 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3028 udelay(80);
3029 }
1da177e4
LT		 3030
3031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3032
3033 /* Some third-party PHYs need to be reset on link going
3034 * down.
3035 */
3036 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3039 netif_carrier_ok(tp->dev)) {
3040 tg3_readphy(tp, MII_BMSR, &bmsr);
3041 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3042 !(bmsr & BMSR_LSTATUS))
3043 force_reset = 1;
3044 }
3045 if (force_reset)
3046 tg3_phy_reset(tp);
3047
3048 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3049 tg3_readphy(tp, MII_BMSR, &bmsr);
3050 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3051 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3052 bmsr = 0;
3053
3054 if (!(bmsr & BMSR_LSTATUS)) {
3055 err = tg3_init_5401phy_dsp(tp);
3056 if (err)
3057 return err;
3058
3059 tg3_readphy(tp, MII_BMSR, &bmsr);
3060 for (i = 0; i < 1000; i++) {
3061 udelay(10);
3062 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3063 (bmsr & BMSR_LSTATUS)) {
3064 udelay(40);
3065 break;
3066 }
3067 }
3068
3069 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3070 !(bmsr & BMSR_LSTATUS) &&
3071 tp->link_config.active_speed == SPEED_1000) {
3072 err = tg3_phy_reset(tp);
3073 if (!err)
3074 err = tg3_init_5401phy_dsp(tp);
3075 if (err)
3076 return err;
3077 }
3078 }
3079 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3080 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3081 /* 5701 {A0,B0} CRC bug workaround */
3082 tg3_writephy(tp, 0x15, 0x0a75);
3083 tg3_writephy(tp, 0x1c, 0x8c68);
3084 tg3_writephy(tp, 0x1c, 0x8d68);
3085 tg3_writephy(tp, 0x1c, 0x8c68);
3086 }
3087
3088 /* Clear pending interrupts... */
3089 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3090 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3091
3092 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3093 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3094 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3095 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3096
3097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3099 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3100 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3101 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3102 else
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3104 }
3105
3106 current_link_up = 0;
3107 current_speed = SPEED_INVALID;
3108 current_duplex = DUPLEX_INVALID;
3109
3110 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3111 u32 val;
3112
3113 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3114 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3115 if (!(val & (1 << 10))) {
3116 val |= (1 << 10);
3117 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3118 goto relink;
3119 }
3120 }
3121
3122 bmsr = 0;
3123 for (i = 0; i < 100; i++) {
3124 tg3_readphy(tp, MII_BMSR, &bmsr);
3125 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3126 (bmsr & BMSR_LSTATUS))
3127 break;
3128 udelay(40);
3129 }
3130
3131 if (bmsr & BMSR_LSTATUS) {
3132 u32 aux_stat, bmcr;
3133
3134 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3135 for (i = 0; i < 2000; i++) {
3136 udelay(10);
3137 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3138 aux_stat)
3139 break;
3140 }
3141
3142 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3143 &current_speed,
3144 &current_duplex);
3145
3146 bmcr = 0;
3147 for (i = 0; i < 200; i++) {
3148 tg3_readphy(tp, MII_BMCR, &bmcr);
3149 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3150 continue;
3151 if (bmcr && bmcr != 0x7fff)
3152 break;
3153 udelay(10);
3154 }
3155
ef167e27
MC		 3156 lcl_adv = 0;
3157 rmt_adv = 0;
1da177e4 3158
ef167e27
MC		 3159 tp->link_config.active_speed = current_speed;
3160 tp->link_config.active_duplex = current_duplex;
3161
3162 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3163 if ((bmcr & BMCR_ANENABLE) &&
3164 tg3_copper_is_advertising_all(tp,
3165 tp->link_config.advertising)) {
3166 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3167 &rmt_adv))
3168 current_link_up = 1;
1da177e4
LT		 3169 }
3170 } else {
3171 if (!(bmcr & BMCR_ANENABLE) &&
3172 tp->link_config.speed == current_speed &&
ef167e27
MC		 3173 tp->link_config.duplex == current_duplex &&
3174 tp->link_config.flowctrl ==
3175 tp->link_config.active_flowctrl) {
1da177e4 3176 current_link_up = 1;
1da177e4
LT		 3177 }
3178 }
3179
ef167e27
MC		 3180 if (current_link_up == 1 &&
3181 tp->link_config.active_duplex == DUPLEX_FULL)
3182 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3183 }
3184
1da177e4 3185relink:
6921d201 3186 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3187 u32 tmp;
3188
3189 tg3_phy_copper_begin(tp);
3190
3191 tg3_readphy(tp, MII_BMSR, &tmp);
3192 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3193 (tmp & BMSR_LSTATUS))
3194 current_link_up = 1;
3195 }
3196
3197 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3198 if (current_link_up == 1) {
3199 if (tp->link_config.active_speed == SPEED_100 ||
3200 tp->link_config.active_speed == SPEED_10)
3201 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3202 else
3203 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3204 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3205 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206 else
1da177e4
LT		 3207 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3208
3209 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3210 if (tp->link_config.active_duplex == DUPLEX_HALF)
3211 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3212
1da177e4 3213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3214 if (current_link_up == 1 &&
3215 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3216 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3217 else
3218 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3219 }
3220
3221 /* ??? Without this setting Netgear GA302T PHY does not
3222 * ??? send/receive packets...
3223 */
3224 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3225 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3226 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3227 tw32_f(MAC_MI_MODE, tp->mi_mode);
3228 udelay(80);
3229 }
3230
3231 tw32_f(MAC_MODE, tp->mac_mode);
3232 udelay(40);
3233
3234 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3235 /* Polled via timer. */
3236 tw32_f(MAC_EVENT, 0);
3237 } else {
3238 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3239 }
3240 udelay(40);
3241
3242 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3243 current_link_up == 1 &&
3244 tp->link_config.active_speed == SPEED_1000 &&
3245 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3246 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3247 udelay(120);
3248 tw32_f(MAC_STATUS,
3249 (MAC_STATUS_SYNC_CHANGED |
3250 MAC_STATUS_CFG_CHANGED));
3251 udelay(40);
3252 tg3_write_mem(tp,
3253 NIC_SRAM_FIRMWARE_MBOX,
3254 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3255 }
3256
5e7dfd0f
MC		 3257 /* Prevent send BD corruption. */
3258 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3259 u16 oldlnkctl, newlnkctl;
3260
3261 pci_read_config_word(tp->pdev,
3262 tp->pcie_cap + PCI_EXP_LNKCTL,
3263 &oldlnkctl);
3264 if (tp->link_config.active_speed == SPEED_100 ||
3265 tp->link_config.active_speed == SPEED_10)
3266 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3267 else
3268 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3269 if (newlnkctl != oldlnkctl)
3270 pci_write_config_word(tp->pdev,
3271 tp->pcie_cap + PCI_EXP_LNKCTL,
3272 newlnkctl);
3273 }
3274
1da177e4
LT		 3275 if (current_link_up != netif_carrier_ok(tp->dev)) {
3276 if (current_link_up)
3277 netif_carrier_on(tp->dev);
3278 else
3279 netif_carrier_off(tp->dev);
3280 tg3_link_report(tp);
3281 }
3282
3283 return 0;
3284}
3285
3286struct tg3_fiber_aneginfo {
3287 int state;
3288#define ANEG_STATE_UNKNOWN 0
3289#define ANEG_STATE_AN_ENABLE 1
3290#define ANEG_STATE_RESTART_INIT 2
3291#define ANEG_STATE_RESTART 3
3292#define ANEG_STATE_DISABLE_LINK_OK 4
3293#define ANEG_STATE_ABILITY_DETECT_INIT 5
3294#define ANEG_STATE_ABILITY_DETECT 6
3295#define ANEG_STATE_ACK_DETECT_INIT 7
3296#define ANEG_STATE_ACK_DETECT 8
3297#define ANEG_STATE_COMPLETE_ACK_INIT 9
3298#define ANEG_STATE_COMPLETE_ACK 10
3299#define ANEG_STATE_IDLE_DETECT_INIT 11
3300#define ANEG_STATE_IDLE_DETECT 12
3301#define ANEG_STATE_LINK_OK 13
3302#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3303#define ANEG_STATE_NEXT_PAGE_WAIT 15
3304
3305 u32 flags;
3306#define MR_AN_ENABLE 0x00000001
3307#define MR_RESTART_AN 0x00000002
3308#define MR_AN_COMPLETE 0x00000004
3309#define MR_PAGE_RX 0x00000008
3310#define MR_NP_LOADED 0x00000010
3311#define MR_TOGGLE_TX 0x00000020
3312#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3313#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3314#define MR_LP_ADV_SYM_PAUSE 0x00000100
3315#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3316#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3317#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3318#define MR_LP_ADV_NEXT_PAGE 0x00001000
3319#define MR_TOGGLE_RX 0x00002000
3320#define MR_NP_RX 0x00004000
3321
3322#define MR_LINK_OK 0x80000000
3323
3324 unsigned long link_time, cur_time;
3325
3326 u32 ability_match_cfg;
3327 int ability_match_count;
3328
3329 char ability_match, idle_match, ack_match;
3330
3331 u32 txconfig, rxconfig;
3332#define ANEG_CFG_NP 0x00000080
3333#define ANEG_CFG_ACK 0x00000040
3334#define ANEG_CFG_RF2 0x00000020
3335#define ANEG_CFG_RF1 0x00000010
3336#define ANEG_CFG_PS2 0x00000001
3337#define ANEG_CFG_PS1 0x00008000
3338#define ANEG_CFG_HD 0x00004000
3339#define ANEG_CFG_FD 0x00002000
3340#define ANEG_CFG_INVAL 0x00001f06
3341
3342};
3343#define ANEG_OK 0
3344#define ANEG_DONE 1
3345#define ANEG_TIMER_ENAB 2
3346#define ANEG_FAILED -1
3347
3348#define ANEG_STATE_SETTLE_TIME 10000
3349
3350static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3351 struct tg3_fiber_aneginfo *ap)
3352{
5be73b47 3353 u16 flowctrl;
1da177e4
LT		 3354 unsigned long delta;
3355 u32 rx_cfg_reg;
3356 int ret;
3357
3358 if (ap->state == ANEG_STATE_UNKNOWN) {
3359 ap->rxconfig = 0;
3360 ap->link_time = 0;
3361 ap->cur_time = 0;
3362 ap->ability_match_cfg = 0;
3363 ap->ability_match_count = 0;
3364 ap->ability_match = 0;
3365 ap->idle_match = 0;
3366 ap->ack_match = 0;
3367 }
3368 ap->cur_time++;
3369
3370 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3371 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3372
3373 if (rx_cfg_reg != ap->ability_match_cfg) {
3374 ap->ability_match_cfg = rx_cfg_reg;
3375 ap->ability_match = 0;
3376 ap->ability_match_count = 0;
3377 } else {
3378 if (++ap->ability_match_count > 1) {
3379 ap->ability_match = 1;
3380 ap->ability_match_cfg = rx_cfg_reg;
3381 }
3382 }
3383 if (rx_cfg_reg & ANEG_CFG_ACK)
3384 ap->ack_match = 1;
3385 else
3386 ap->ack_match = 0;
3387
3388 ap->idle_match = 0;
3389 } else {
3390 ap->idle_match = 1;
3391 ap->ability_match_cfg = 0;
3392 ap->ability_match_count = 0;
3393 ap->ability_match = 0;
3394 ap->ack_match = 0;
3395
3396 rx_cfg_reg = 0;
3397 }
3398
3399 ap->rxconfig = rx_cfg_reg;
3400 ret = ANEG_OK;
3401
3402 switch(ap->state) {
3403 case ANEG_STATE_UNKNOWN:
3404 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3405 ap->state = ANEG_STATE_AN_ENABLE;
3406
3407 /* fallthru */
3408 case ANEG_STATE_AN_ENABLE:
3409 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3410 if (ap->flags & MR_AN_ENABLE) {
3411 ap->link_time = 0;
3412 ap->cur_time = 0;
3413 ap->ability_match_cfg = 0;
3414 ap->ability_match_count = 0;
3415 ap->ability_match = 0;
3416 ap->idle_match = 0;
3417 ap->ack_match = 0;
3418
3419 ap->state = ANEG_STATE_RESTART_INIT;
3420 } else {
3421 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3422 }
3423 break;
3424
3425 case ANEG_STATE_RESTART_INIT:
3426 ap->link_time = ap->cur_time;
3427 ap->flags &= ~(MR_NP_LOADED);
3428 ap->txconfig = 0;
3429 tw32(MAC_TX_AUTO_NEG, 0);
3430 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3431 tw32_f(MAC_MODE, tp->mac_mode);
3432 udelay(40);
3433
3434 ret = ANEG_TIMER_ENAB;
3435 ap->state = ANEG_STATE_RESTART;
3436
3437 /* fallthru */
3438 case ANEG_STATE_RESTART:
3439 delta = ap->cur_time - ap->link_time;
3440 if (delta > ANEG_STATE_SETTLE_TIME) {
3441 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3442 } else {
3443 ret = ANEG_TIMER_ENAB;
3444 }
3445 break;
3446
3447 case ANEG_STATE_DISABLE_LINK_OK:
3448 ret = ANEG_DONE;
3449 break;
3450
3451 case ANEG_STATE_ABILITY_DETECT_INIT:
3452 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3453 ap->txconfig = ANEG_CFG_FD;
3454 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3455 if (flowctrl & ADVERTISE_1000XPAUSE)
3456 ap->txconfig |= ANEG_CFG_PS1;
3457 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3458 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3459 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3460 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3461 tw32_f(MAC_MODE, tp->mac_mode);
3462 udelay(40);
3463
3464 ap->state = ANEG_STATE_ABILITY_DETECT;
3465 break;
3466
3467 case ANEG_STATE_ABILITY_DETECT:
3468 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3469 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3470 }
3471 break;
3472
3473 case ANEG_STATE_ACK_DETECT_INIT:
3474 ap->txconfig |= ANEG_CFG_ACK;
3475 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3476 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3477 tw32_f(MAC_MODE, tp->mac_mode);
3478 udelay(40);
3479
3480 ap->state = ANEG_STATE_ACK_DETECT;
3481
3482 /* fallthru */
3483 case ANEG_STATE_ACK_DETECT:
3484 if (ap->ack_match != 0) {
3485 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3486 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3487 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3488 } else {
3489 ap->state = ANEG_STATE_AN_ENABLE;
3490 }
3491 } else if (ap->ability_match != 0 &&
3492 ap->rxconfig == 0) {
3493 ap->state = ANEG_STATE_AN_ENABLE;
3494 }
3495 break;
3496
3497 case ANEG_STATE_COMPLETE_ACK_INIT:
3498 if (ap->rxconfig & ANEG_CFG_INVAL) {
3499 ret = ANEG_FAILED;
3500 break;
3501 }
3502 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3503 MR_LP_ADV_HALF_DUPLEX |
3504 MR_LP_ADV_SYM_PAUSE |
3505 MR_LP_ADV_ASYM_PAUSE |
3506 MR_LP_ADV_REMOTE_FAULT1 |
3507 MR_LP_ADV_REMOTE_FAULT2 |
3508 MR_LP_ADV_NEXT_PAGE |
3509 MR_TOGGLE_RX |
3510 MR_NP_RX);
3511 if (ap->rxconfig & ANEG_CFG_FD)
3512 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3513 if (ap->rxconfig & ANEG_CFG_HD)
3514 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3515 if (ap->rxconfig & ANEG_CFG_PS1)
3516 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3517 if (ap->rxconfig & ANEG_CFG_PS2)
3518 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3519 if (ap->rxconfig & ANEG_CFG_RF1)
3520 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3521 if (ap->rxconfig & ANEG_CFG_RF2)
3522 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3523 if (ap->rxconfig & ANEG_CFG_NP)
3524 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3525
3526 ap->link_time = ap->cur_time;
3527
3528 ap->flags ^= (MR_TOGGLE_TX);
3529 if (ap->rxconfig & 0x0008)
3530 ap->flags |= MR_TOGGLE_RX;
3531 if (ap->rxconfig & ANEG_CFG_NP)
3532 ap->flags |= MR_NP_RX;
3533 ap->flags |= MR_PAGE_RX;
3534
3535 ap->state = ANEG_STATE_COMPLETE_ACK;
3536 ret = ANEG_TIMER_ENAB;
3537 break;
3538
3539 case ANEG_STATE_COMPLETE_ACK:
3540 if (ap->ability_match != 0 &&
3541 ap->rxconfig == 0) {
3542 ap->state = ANEG_STATE_AN_ENABLE;
3543 break;
3544 }
3545 delta = ap->cur_time - ap->link_time;
3546 if (delta > ANEG_STATE_SETTLE_TIME) {
3547 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3548 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3549 } else {
3550 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3551 !(ap->flags & MR_NP_RX)) {
3552 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553 } else {
3554 ret = ANEG_FAILED;
3555 }
3556 }
3557 }
3558 break;
3559
3560 case ANEG_STATE_IDLE_DETECT_INIT:
3561 ap->link_time = ap->cur_time;
3562 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3563 tw32_f(MAC_MODE, tp->mac_mode);
3564 udelay(40);
3565
3566 ap->state = ANEG_STATE_IDLE_DETECT;
3567 ret = ANEG_TIMER_ENAB;
3568 break;
3569
3570 case ANEG_STATE_IDLE_DETECT:
3571 if (ap->ability_match != 0 &&
3572 ap->rxconfig == 0) {
3573 ap->state = ANEG_STATE_AN_ENABLE;
3574 break;
3575 }
3576 delta = ap->cur_time - ap->link_time;
3577 if (delta > ANEG_STATE_SETTLE_TIME) {
3578 /* XXX another gem from the Broadcom driver :( */
3579 ap->state = ANEG_STATE_LINK_OK;
3580 }
3581 break;
3582
3583 case ANEG_STATE_LINK_OK:
3584 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3585 ret = ANEG_DONE;
3586 break;
3587
3588 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3589 /* ??? unimplemented */
3590 break;
3591
3592 case ANEG_STATE_NEXT_PAGE_WAIT:
3593 /* ??? unimplemented */
3594 break;
3595
3596 default:
3597 ret = ANEG_FAILED;
3598 break;
855e1111 3599 }
1da177e4
LT		 3600
3601 return ret;
3602}
3603
5be73b47 3604static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3605{
3606 int res = 0;
3607 struct tg3_fiber_aneginfo aninfo;
3608 int status = ANEG_FAILED;
3609 unsigned int tick;
3610 u32 tmp;
3611
3612 tw32_f(MAC_TX_AUTO_NEG, 0);
3613
3614 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3615 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3616 udelay(40);
3617
3618 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3619 udelay(40);
3620
3621 memset(&aninfo, 0, sizeof(aninfo));
3622 aninfo.flags |= MR_AN_ENABLE;
3623 aninfo.state = ANEG_STATE_UNKNOWN;
3624 aninfo.cur_time = 0;
3625 tick = 0;
3626 while (++tick < 195000) {
3627 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3628 if (status == ANEG_DONE || status == ANEG_FAILED)
3629 break;
3630
3631 udelay(1);
3632 }
3633
3634 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3635 tw32_f(MAC_MODE, tp->mac_mode);
3636 udelay(40);
3637
5be73b47
MC		 3638 *txflags = aninfo.txconfig;
3639 *rxflags = aninfo.flags;
1da177e4
LT		 3640
3641 if (status == ANEG_DONE &&
3642 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3643 MR_LP_ADV_FULL_DUPLEX)))
3644 res = 1;
3645
3646 return res;
3647}
3648
3649static void tg3_init_bcm8002(struct tg3 *tp)
3650{
3651 u32 mac_status = tr32(MAC_STATUS);
3652 int i;
3653
3654 /* Reset when initting first time or we have a link. */
3655 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3656 !(mac_status & MAC_STATUS_PCS_SYNCED))
3657 return;
3658
3659 /* Set PLL lock range. */
3660 tg3_writephy(tp, 0x16, 0x8007);
3661
3662 /* SW reset */
3663 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3664
3665 /* Wait for reset to complete. */
3666 /* XXX schedule_timeout() ... */
3667 for (i = 0; i < 500; i++)
3668 udelay(10);
3669
3670 /* Config mode; select PMA/Ch 1 regs. */
3671 tg3_writephy(tp, 0x10, 0x8411);
3672
3673 /* Enable auto-lock and comdet, select txclk for tx. */
3674 tg3_writephy(tp, 0x11, 0x0a10);
3675
3676 tg3_writephy(tp, 0x18, 0x00a0);
3677 tg3_writephy(tp, 0x16, 0x41ff);
3678
3679 /* Assert and deassert POR. */
3680 tg3_writephy(tp, 0x13, 0x0400);
3681 udelay(40);
3682 tg3_writephy(tp, 0x13, 0x0000);
3683
3684 tg3_writephy(tp, 0x11, 0x0a50);
3685 udelay(40);
3686 tg3_writephy(tp, 0x11, 0x0a10);
3687
3688 /* Wait for signal to stabilize */
3689 /* XXX schedule_timeout() ... */
3690 for (i = 0; i < 15000; i++)
3691 udelay(10);
3692
3693 /* Deselect the channel register so we can read the PHYID
3694 * later.
3695 */
3696 tg3_writephy(tp, 0x10, 0x8011);
3697}
3698
3699static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3700{
82cd3d11 3701 u16 flowctrl;
1da177e4
LT		 3702 u32 sg_dig_ctrl, sg_dig_status;
3703 u32 serdes_cfg, expected_sg_dig_ctrl;
3704 int workaround, port_a;
3705 int current_link_up;
3706
3707 serdes_cfg = 0;
3708 expected_sg_dig_ctrl = 0;
3709 workaround = 0;
3710 port_a = 1;
3711 current_link_up = 0;
3712
3713 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3714 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3715 workaround = 1;
3716 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3717 port_a = 0;
3718
3719 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3720 /* preserve bits 20-23 for voltage regulator */
3721 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3722 }
3723
3724 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3725
3726 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3727 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3728 if (workaround) {
3729 u32 val = serdes_cfg;
3730
3731 if (port_a)
3732 val |= 0xc010000;
3733 else
3734 val |= 0x4010000;
3735 tw32_f(MAC_SERDES_CFG, val);
3736 }
c98f6e3b
MC		 3737
3738 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3739 }
3740 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3741 tg3_setup_flow_control(tp, 0, 0);
3742 current_link_up = 1;
3743 }
3744 goto out;
3745 }
3746
3747 /* Want auto-negotiation. */
c98f6e3b 3748 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3749
82cd3d11
MC		 3750 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3751 if (flowctrl & ADVERTISE_1000XPAUSE)
3752 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3753 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3754 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3755
3756 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3757 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3758 tp->serdes_counter &&
3759 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3760 MAC_STATUS_RCVD_CFG)) ==
3761 MAC_STATUS_PCS_SYNCED)) {
3762 tp->serdes_counter--;
3763 current_link_up = 1;
3764 goto out;
3765 }
3766restart_autoneg:
1da177e4
LT		 3767 if (workaround)
3768 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3769 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3770 udelay(5);
3771 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3772
3d3ebe74
MC		 3773 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3774 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3775 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3776 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3777 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3778 mac_status = tr32(MAC_STATUS);
3779
c98f6e3b 3780 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3781 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3782 u32 local_adv = 0, remote_adv = 0;
3783
3784 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3785 local_adv |= ADVERTISE_1000XPAUSE;
3786 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3787 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3788
c98f6e3b 3789 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3790 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3791 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3792 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3793
3794 tg3_setup_flow_control(tp, local_adv, remote_adv);
3795 current_link_up = 1;
3d3ebe74
MC		 3796 tp->serdes_counter = 0;
3797 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3798 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3799 if (tp->serdes_counter)
3800 tp->serdes_counter--;
1da177e4
LT		 3801 else {
3802 if (workaround) {
3803 u32 val = serdes_cfg;
3804
3805 if (port_a)
3806 val |= 0xc010000;
3807 else
3808 val |= 0x4010000;
3809
3810 tw32_f(MAC_SERDES_CFG, val);
3811 }
3812
c98f6e3b 3813 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3814 udelay(40);
3815
3816 /* Link parallel detection - link is up */
3817 /* only if we have PCS_SYNC and not */
3818 /* receiving config code words */
3819 mac_status = tr32(MAC_STATUS);
3820 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3821 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3822 tg3_setup_flow_control(tp, 0, 0);
3823 current_link_up = 1;
3d3ebe74
MC		 3824 tp->tg3_flags2 |=
3825 TG3_FLG2_PARALLEL_DETECT;
3826 tp->serdes_counter =
3827 SERDES_PARALLEL_DET_TIMEOUT;
3828 } else
3829 goto restart_autoneg;
1da177e4
LT		 3830 }
3831 }
3d3ebe74
MC		 3832 } else {
3833 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3834 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3835 }
3836
3837out:
3838 return current_link_up;
3839}
3840
3841static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3842{
3843 int current_link_up = 0;
3844
5cf64b8a 3845 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3846 goto out;
1da177e4
LT		 3847
3848 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3849 u32 txflags, rxflags;
1da177e4 3850 int i;
6aa20a22 3851
5be73b47
MC		 3852 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3853 u32 local_adv = 0, remote_adv = 0;
1da177e4 3854
5be73b47
MC		 3855 if (txflags & ANEG_CFG_PS1)
3856 local_adv |= ADVERTISE_1000XPAUSE;
3857 if (txflags & ANEG_CFG_PS2)
3858 local_adv |= ADVERTISE_1000XPSE_ASYM;
3859
3860 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3861 remote_adv |= LPA_1000XPAUSE;
3862 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3863 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3864
3865 tg3_setup_flow_control(tp, local_adv, remote_adv);
3866
1da177e4
LT		 3867 current_link_up = 1;
3868 }
3869 for (i = 0; i < 30; i++) {
3870 udelay(20);
3871 tw32_f(MAC_STATUS,
3872 (MAC_STATUS_SYNC_CHANGED |
3873 MAC_STATUS_CFG_CHANGED));
3874 udelay(40);
3875 if ((tr32(MAC_STATUS) &
3876 (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED)) == 0)
3878 break;
3879 }
3880
3881 mac_status = tr32(MAC_STATUS);
3882 if (current_link_up == 0 &&
3883 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3884 !(mac_status & MAC_STATUS_RCVD_CFG))
3885 current_link_up = 1;
3886 } else {
5be73b47
MC		 3887 tg3_setup_flow_control(tp, 0, 0);
3888
1da177e4
LT		 3889 /* Forcing 1000FD link up. */
3890 current_link_up = 1;
1da177e4
LT		 3891
3892 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3893 udelay(40);
e8f3f6ca
MC		 3894
3895 tw32_f(MAC_MODE, tp->mac_mode);
3896 udelay(40);
1da177e4
LT		 3897 }
3898
3899out:
3900 return current_link_up;
3901}
3902
3903static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3904{
3905 u32 orig_pause_cfg;
3906 u16 orig_active_speed;
3907 u8 orig_active_duplex;
3908 u32 mac_status;
3909 int current_link_up;
3910 int i;
3911
8d018621 3912 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3913 orig_active_speed = tp->link_config.active_speed;
3914 orig_active_duplex = tp->link_config.active_duplex;
3915
3916 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3917 netif_carrier_ok(tp->dev) &&
3918 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3919 mac_status = tr32(MAC_STATUS);
3920 mac_status &= (MAC_STATUS_PCS_SYNCED |
3921 MAC_STATUS_SIGNAL_DET |
3922 MAC_STATUS_CFG_CHANGED |
3923 MAC_STATUS_RCVD_CFG);
3924 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3925 MAC_STATUS_SIGNAL_DET)) {
3926 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3927 MAC_STATUS_CFG_CHANGED));
3928 return 0;
3929 }
3930 }
3931
3932 tw32_f(MAC_TX_AUTO_NEG, 0);
3933
3934 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3935 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3936 tw32_f(MAC_MODE, tp->mac_mode);
3937 udelay(40);
3938
3939 if (tp->phy_id == PHY_ID_BCM8002)
3940 tg3_init_bcm8002(tp);
3941
3942 /* Enable link change event even when serdes polling. */
3943 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3944 udelay(40);
3945
3946 current_link_up = 0;
3947 mac_status = tr32(MAC_STATUS);
3948
3949 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3950 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3951 else
3952 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3953
898a56f8 3954 tp->napi[0].hw_status->status =
1da177e4 3955 (SD_STATUS_UPDATED |
898a56f8 3956 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3957
3958 for (i = 0; i < 100; i++) {
3959 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3960 MAC_STATUS_CFG_CHANGED));
3961 udelay(5);
3962 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3963 MAC_STATUS_CFG_CHANGED |
3964 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3965 break;
3966 }
3967
3968 mac_status = tr32(MAC_STATUS);
3969 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3970 current_link_up = 0;
3d3ebe74
MC		 3971 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3972 tp->serdes_counter == 0) {
1da177e4
LT		 3973 tw32_f(MAC_MODE, (tp->mac_mode |
3974 MAC_MODE_SEND_CONFIGS));
3975 udelay(1);
3976 tw32_f(MAC_MODE, tp->mac_mode);
3977 }
3978 }
3979
3980 if (current_link_up == 1) {
3981 tp->link_config.active_speed = SPEED_1000;
3982 tp->link_config.active_duplex = DUPLEX_FULL;
3983 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3984 LED_CTRL_LNKLED_OVERRIDE |
3985 LED_CTRL_1000MBPS_ON));
3986 } else {
3987 tp->link_config.active_speed = SPEED_INVALID;
3988 tp->link_config.active_duplex = DUPLEX_INVALID;
3989 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3990 LED_CTRL_LNKLED_OVERRIDE |
3991 LED_CTRL_TRAFFIC_OVERRIDE));
3992 }
3993
3994 if (current_link_up != netif_carrier_ok(tp->dev)) {
3995 if (current_link_up)
3996 netif_carrier_on(tp->dev);
3997 else
3998 netif_carrier_off(tp->dev);
3999 tg3_link_report(tp);
4000 } else {
8d018621 4001 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4002 if (orig_pause_cfg != now_pause_cfg ||
4003 orig_active_speed != tp->link_config.active_speed ||
4004 orig_active_duplex != tp->link_config.active_duplex)
4005 tg3_link_report(tp);
4006 }
4007
4008 return 0;
4009}
4010
747e8f8b
MC		 4011static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4012{
4013 int current_link_up, err = 0;
4014 u32 bmsr, bmcr;
4015 u16 current_speed;
4016 u8 current_duplex;
ef167e27 4017 u32 local_adv, remote_adv;
747e8f8b
MC		 4018
4019 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020 tw32_f(MAC_MODE, tp->mac_mode);
4021 udelay(40);
4022
4023 tw32(MAC_EVENT, 0);
4024
4025 tw32_f(MAC_STATUS,
4026 (MAC_STATUS_SYNC_CHANGED |
4027 MAC_STATUS_CFG_CHANGED |
4028 MAC_STATUS_MI_COMPLETION |
4029 MAC_STATUS_LNKSTATE_CHANGED));
4030 udelay(40);
4031
4032 if (force_reset)
4033 tg3_phy_reset(tp);
4034
4035 current_link_up = 0;
4036 current_speed = SPEED_INVALID;
4037 current_duplex = DUPLEX_INVALID;
4038
4039 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4041 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4042 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4043 bmsr |= BMSR_LSTATUS;
4044 else
4045 bmsr &= ~BMSR_LSTATUS;
4046 }
747e8f8b
MC		 4047
4048 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4049
4050 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4051 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4052 /* do nothing, just check for link up at the end */
4053 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4054 u32 adv, new_adv;
4055
4056 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4057 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4058 ADVERTISE_1000XPAUSE |
4059 ADVERTISE_1000XPSE_ASYM |
4060 ADVERTISE_SLCT);
4061
ba4d07a8 4062 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4063
4064 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4065 new_adv |= ADVERTISE_1000XHALF;
4066 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4067 new_adv |= ADVERTISE_1000XFULL;
4068
4069 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4070 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4071 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4072 tg3_writephy(tp, MII_BMCR, bmcr);
4073
4074 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4075 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4076 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4077
4078 return err;
4079 }
4080 } else {
4081 u32 new_bmcr;
4082
4083 bmcr &= ~BMCR_SPEED1000;
4084 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4085
4086 if (tp->link_config.duplex == DUPLEX_FULL)
4087 new_bmcr |= BMCR_FULLDPLX;
4088
4089 if (new_bmcr != bmcr) {
4090 /* BMCR_SPEED1000 is a reserved bit that needs
4091 * to be set on write.
4092 */
4093 new_bmcr |= BMCR_SPEED1000;
4094
4095 /* Force a linkdown */
4096 if (netif_carrier_ok(tp->dev)) {
4097 u32 adv;
4098
4099 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100 adv &= ~(ADVERTISE_1000XFULL |
4101 ADVERTISE_1000XHALF |
4102 ADVERTISE_SLCT);
4103 tg3_writephy(tp, MII_ADVERTISE, adv);
4104 tg3_writephy(tp, MII_BMCR, bmcr |
4105 BMCR_ANRESTART |
4106 BMCR_ANENABLE);
4107 udelay(10);
4108 netif_carrier_off(tp->dev);
4109 }
4110 tg3_writephy(tp, MII_BMCR, new_bmcr);
4111 bmcr = new_bmcr;
4112 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4114 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4115 ASIC_REV_5714) {
4116 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4117 bmsr |= BMSR_LSTATUS;
4118 else
4119 bmsr &= ~BMSR_LSTATUS;
4120 }
747e8f8b
MC		 4121 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4122 }
4123 }
4124
4125 if (bmsr & BMSR_LSTATUS) {
4126 current_speed = SPEED_1000;
4127 current_link_up = 1;
4128 if (bmcr & BMCR_FULLDPLX)
4129 current_duplex = DUPLEX_FULL;
4130 else
4131 current_duplex = DUPLEX_HALF;
4132
ef167e27
MC		 4133 local_adv = 0;
4134 remote_adv = 0;
4135
747e8f8b 4136 if (bmcr & BMCR_ANENABLE) {
ef167e27 4137 u32 common;
747e8f8b
MC		 4138
4139 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4140 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4141 common = local_adv & remote_adv;
4142 if (common & (ADVERTISE_1000XHALF |
4143 ADVERTISE_1000XFULL)) {
4144 if (common & ADVERTISE_1000XFULL)
4145 current_duplex = DUPLEX_FULL;
4146 else
4147 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4148 }
4149 else
4150 current_link_up = 0;
4151 }
4152 }
4153
ef167e27
MC		 4154 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4155 tg3_setup_flow_control(tp, local_adv, remote_adv);
4156
747e8f8b
MC		 4157 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4158 if (tp->link_config.active_duplex == DUPLEX_HALF)
4159 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4160
4161 tw32_f(MAC_MODE, tp->mac_mode);
4162 udelay(40);
4163
4164 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4165
4166 tp->link_config.active_speed = current_speed;
4167 tp->link_config.active_duplex = current_duplex;
4168
4169 if (current_link_up != netif_carrier_ok(tp->dev)) {
4170 if (current_link_up)
4171 netif_carrier_on(tp->dev);
4172 else {
4173 netif_carrier_off(tp->dev);
4174 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4175 }
4176 tg3_link_report(tp);
4177 }
4178 return err;
4179}
4180
4181static void tg3_serdes_parallel_detect(struct tg3 *tp)
4182{
3d3ebe74 4183 if (tp->serdes_counter) {
747e8f8b 4184 /* Give autoneg time to complete. */
3d3ebe74 4185 tp->serdes_counter--;
747e8f8b
MC		 4186 return;
4187 }
4188 if (!netif_carrier_ok(tp->dev) &&
4189 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4190 u32 bmcr;
4191
4192 tg3_readphy(tp, MII_BMCR, &bmcr);
4193 if (bmcr & BMCR_ANENABLE) {
4194 u32 phy1, phy2;
4195
4196 /* Select shadow register 0x1f */
4197 tg3_writephy(tp, 0x1c, 0x7c00);
4198 tg3_readphy(tp, 0x1c, &phy1);
4199
4200 /* Select expansion interrupt status register */
4201 tg3_writephy(tp, 0x17, 0x0f01);
4202 tg3_readphy(tp, 0x15, &phy2);
4203 tg3_readphy(tp, 0x15, &phy2);
4204
4205 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4206 /* We have signal detect and not receiving
4207 * config code words, link is up by parallel
4208 * detection.
4209 */
4210
4211 bmcr &= ~BMCR_ANENABLE;
4212 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4213 tg3_writephy(tp, MII_BMCR, bmcr);
4214 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4215 }
4216 }
4217 }
4218 else if (netif_carrier_ok(tp->dev) &&
4219 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4220 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4221 u32 phy2;
4222
4223 /* Select expansion interrupt status register */
4224 tg3_writephy(tp, 0x17, 0x0f01);
4225 tg3_readphy(tp, 0x15, &phy2);
4226 if (phy2 & 0x20) {
4227 u32 bmcr;
4228
4229 /* Config code words received, turn on autoneg. */
4230 tg3_readphy(tp, MII_BMCR, &bmcr);
4231 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4232
4233 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4234
4235 }
4236 }
4237}
4238
1da177e4
LT		 4239static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4240{
4241 int err;
4242
4243 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4244 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4245 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4246 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4247 } else {
4248 err = tg3_setup_copper_phy(tp, force_reset);
4249 }
4250
bcb37f6c 4251 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4252 u32 val, scale;
4253
4254 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4255 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4256 scale = 65;
4257 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4258 scale = 6;
4259 else
4260 scale = 12;
4261
4262 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4263 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4264 tw32(GRC_MISC_CFG, val);
4265 }
4266
1da177e4
LT		 4267 if (tp->link_config.active_speed == SPEED_1000 &&
4268 tp->link_config.active_duplex == DUPLEX_HALF)
4269 tw32(MAC_TX_LENGTHS,
4270 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4271 (6 << TX_LENGTHS_IPG_SHIFT) |
4272 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4273 else
4274 tw32(MAC_TX_LENGTHS,
4275 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4276 (6 << TX_LENGTHS_IPG_SHIFT) |
4277 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4278
4279 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4280 if (netif_carrier_ok(tp->dev)) {
4281 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4282 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4283 } else {
4284 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4285 }
4286 }
4287
8ed5d97e
MC		 4288 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4289 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4290 if (!netif_carrier_ok(tp->dev))
4291 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4292 tp->pwrmgmt_thresh;
4293 else
4294 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4295 tw32(PCIE_PWR_MGMT_THRESH, val);
4296 }
4297
1da177e4
LT		 4298 return err;
4299}
4300
df3e6548
MC		 4301/* This is called whenever we suspect that the system chipset is re-
4302 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4303 * is bogus tx completions. We try to recover by setting the
4304 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4305 * in the workqueue.
4306 */
4307static void tg3_tx_recover(struct tg3 *tp)
4308{
4309 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4310 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4311
4312 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4313 "mapped I/O cycles to the network device, attempting to "
4314 "recover. Please report the problem to the driver maintainer "
4315 "and include system chipset information.\n", tp->dev->name);
4316
4317 spin_lock(&tp->lock);
df3e6548 4318 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4319 spin_unlock(&tp->lock);
4320}
4321
f3f3f27e 4322static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4323{
4324 smp_mb();
f3f3f27e
MC		 4325 return tnapi->tx_pending -
4326 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4327}
4328
1da177e4
LT		 4329/* Tigon3 never reports partial packet sends. So we do not
4330 * need special logic to handle SKBs that have not had all
4331 * of their frags sent yet, like SunGEM does.
4332 */
17375d25 4333static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4334{
17375d25 4335 struct tg3 *tp = tnapi->tp;
898a56f8 4336 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4337 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4338 struct netdev_queue *txq;
4339 int index = tnapi - tp->napi;
4340
4341 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4342 index--;
4343
4344 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4345
4346 while (sw_idx != hw_idx) {
f3f3f27e 4347 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4348 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4349 int i, tx_bug = 0;
4350
4351 if (unlikely(skb == NULL)) {
4352 tg3_tx_recover(tp);
4353 return;
4354 }
1da177e4 4355
90079ce8 4356 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4357
4358 ri->skb = NULL;
4359
4360 sw_idx = NEXT_TX(sw_idx);
4361
4362 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4363 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4364 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4365 tx_bug = 1;
1da177e4
LT		 4366 sw_idx = NEXT_TX(sw_idx);
4367 }
4368
f47c11ee 4369 dev_kfree_skb(skb);
df3e6548
MC		 4370
4371 if (unlikely(tx_bug)) {
4372 tg3_tx_recover(tp);
4373 return;
4374 }
1da177e4
LT		 4375 }
4376
f3f3f27e 4377 tnapi->tx_cons = sw_idx;
1da177e4 4378
1b2a7205
MC		 4379 /* Need to make the tx_cons update visible to tg3_start_xmit()
4380 * before checking for netif_queue_stopped(). Without the
4381 * memory barrier, there is a small possibility that tg3_start_xmit()
4382 * will miss it and cause the queue to be stopped forever.
4383 */
4384 smp_mb();
4385
fe5f5787 4386 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4387 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4388 __netif_tx_lock(txq, smp_processor_id());
4389 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4390 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4391 netif_tx_wake_queue(txq);
4392 __netif_tx_unlock(txq);
51b91468 4393 }
1da177e4
LT		 4394}
4395
4396/* Returns size of skb allocated or < 0 on error.
4397 *
4398 * We only need to fill in the address because the other members
4399 * of the RX descriptor are invariant, see tg3_init_rings.
4400 *
4401 * Note the purposeful assymetry of cpu vs. chip accesses. For
4402 * posting buffers we only dirty the first cache line of the RX
4403 * descriptor (containing the address). Whereas for the RX status
4404 * buffers the cpu only reads the last cacheline of the RX descriptor
4405 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4406 */
17375d25 4407static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4408 int src_idx, u32 dest_idx_unmasked)
4409{
17375d25 4410 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4411 struct tg3_rx_buffer_desc *desc;
4412 struct ring_info *map, *src_map;
4413 struct sk_buff *skb;
4414 dma_addr_t mapping;
4415 int skb_size, dest_idx;
21f581a5 4416 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4417
4418 src_map = NULL;
4419 switch (opaque_key) {
4420 case RXD_OPAQUE_RING_STD:
4421 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4422 desc = &tpr->rx_std[dest_idx];
4423 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4424 if (src_idx >= 0)
21f581a5 4425 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4426 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4427 break;
4428
4429 case RXD_OPAQUE_RING_JUMBO:
4430 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4431 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4432 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4433 if (src_idx >= 0)
21f581a5 4434 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4435 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4436 break;
4437
4438 default:
4439 return -EINVAL;
855e1111 4440 }
1da177e4
LT		 4441
4442 /* Do not overwrite any of the map or rp information
4443 * until we are sure we can commit to a new buffer.
4444 *
4445 * Callers depend upon this behavior and assume that
4446 * we leave everything unchanged if we fail.
4447 */
287be12e 4448 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4449 if (skb == NULL)
4450 return -ENOMEM;
4451
1da177e4
LT		 4452 skb_reserve(skb, tp->rx_offset);
4453
287be12e 4454 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4455 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4456 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4457 dev_kfree_skb(skb);
4458 return -EIO;
4459 }
1da177e4
LT		 4460
4461 map->skb = skb;
4462 pci_unmap_addr_set(map, mapping, mapping);
4463
4464 if (src_map != NULL)
4465 src_map->skb = NULL;
4466
4467 desc->addr_hi = ((u64)mapping >> 32);
4468 desc->addr_lo = ((u64)mapping & 0xffffffff);
4469
4470 return skb_size;
4471}
4472
4473/* We only need to move over in the address because the other
4474 * members of the RX descriptor are invariant. See notes above
4475 * tg3_alloc_rx_skb for full details.
4476 */
17375d25 4477static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4478 int src_idx, u32 dest_idx_unmasked)
4479{
17375d25 4480 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4481 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4482 struct ring_info *src_map, *dest_map;
4483 int dest_idx;
21f581a5 4484 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4485
4486 switch (opaque_key) {
4487 case RXD_OPAQUE_RING_STD:
4488 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4489 dest_desc = &tpr->rx_std[dest_idx];
4490 dest_map = &tpr->rx_std_buffers[dest_idx];
4491 src_desc = &tpr->rx_std[src_idx];
4492 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4493 break;
4494
4495 case RXD_OPAQUE_RING_JUMBO:
4496 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4497 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4498 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4499 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4500 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4501 break;
4502
4503 default:
4504 return;
855e1111 4505 }
1da177e4
LT		 4506
4507 dest_map->skb = src_map->skb;
4508 pci_unmap_addr_set(dest_map, mapping,
4509 pci_unmap_addr(src_map, mapping));
4510 dest_desc->addr_hi = src_desc->addr_hi;
4511 dest_desc->addr_lo = src_desc->addr_lo;
4512
4513 src_map->skb = NULL;
4514}
4515
1da177e4
LT		 4516/* The RX ring scheme is composed of multiple rings which post fresh
4517 * buffers to the chip, and one special ring the chip uses to report
4518 * status back to the host.
4519 *
4520 * The special ring reports the status of received packets to the
4521 * host. The chip does not write into the original descriptor the
4522 * RX buffer was obtained from. The chip simply takes the original
4523 * descriptor as provided by the host, updates the status and length
4524 * field, then writes this into the next status ring entry.
4525 *
4526 * Each ring the host uses to post buffers to the chip is described
4527 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4528 * it is first placed into the on-chip ram. When the packet's length
4529 * is known, it walks down the TG3_BDINFO entries to select the ring.
4530 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4531 * which is within the range of the new packet's length is chosen.
4532 *
4533 * The "separate ring for rx status" scheme may sound queer, but it makes
4534 * sense from a cache coherency perspective. If only the host writes
4535 * to the buffer post rings, and only the chip writes to the rx status
4536 * rings, then cache lines never move beyond shared-modified state.
4537 * If both the host and chip were to write into the same ring, cache line
4538 * eviction could occur since both entities want it in an exclusive state.
4539 */
17375d25 4540static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4541{
17375d25 4542 struct tg3 *tp = tnapi->tp;
f92905de 4543 u32 work_mask, rx_std_posted = 0;
72334482 4544 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4545 u16 hw_idx;
1da177e4 4546 int received;
21f581a5 4547 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4548
8d9d7cfc 4549 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4550 /*
4551 * We need to order the read of hw_idx and the read of
4552 * the opaque cookie.
4553 */
4554 rmb();
1da177e4
LT		 4555 work_mask = 0;
4556 received = 0;
4557 while (sw_idx != hw_idx && budget > 0) {
72334482 4558 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4559 unsigned int len;
4560 struct sk_buff *skb;
4561 dma_addr_t dma_addr;
4562 u32 opaque_key, desc_idx, *post_ptr;
4563
4564 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4565 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4566 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4567 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4568 dma_addr = pci_unmap_addr(ri, mapping);
4569 skb = ri->skb;
4570 post_ptr = &tpr->rx_std_ptr;
f92905de 4571 rx_std_posted++;
1da177e4 4572 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4573 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4574 dma_addr = pci_unmap_addr(ri, mapping);
4575 skb = ri->skb;
4576 post_ptr = &tpr->rx_jmb_ptr;
4577 } else
1da177e4 4578 goto next_pkt_nopost;
1da177e4
LT		 4579
4580 work_mask |= opaque_key;
4581
4582 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4583 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4584 drop_it:
17375d25 4585 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4586 desc_idx, *post_ptr);
4587 drop_it_no_recycle:
4588 /* Other statistics kept track of by card. */
4589 tp->net_stats.rx_dropped++;
4590 goto next_pkt;
4591 }
4592
ad829268
MC		 4593 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4594 ETH_FCS_LEN;
1da177e4 4595
6aa20a22 4596 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4597 && tp->rx_offset == NET_IP_ALIGN
4598 /* rx_offset will likely not equal NET_IP_ALIGN
4599 * if this is a 5701 card running in PCI-X mode
4600 * [see tg3_get_invariants()]
4601 */
1da177e4
LT		 4602 ) {
4603 int skb_size;
4604
17375d25 4605 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4606 desc_idx, *post_ptr);
4607 if (skb_size < 0)
4608 goto drop_it;
4609
287be12e 4610 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4611 PCI_DMA_FROMDEVICE);
4612
4613 skb_put(skb, len);
4614 } else {
4615 struct sk_buff *copy_skb;
4616
17375d25 4617 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4618 desc_idx, *post_ptr);
4619
ad829268
MC		 4620 copy_skb = netdev_alloc_skb(tp->dev,
4621 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4622 if (copy_skb == NULL)
4623 goto drop_it_no_recycle;
4624
ad829268 4625 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4626 skb_put(copy_skb, len);
4627 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4628 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4629 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4630
4631 /* We'll reuse the original ring buffer. */
4632 skb = copy_skb;
4633 }
4634
4635 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4636 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4637 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4638 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4639 skb->ip_summed = CHECKSUM_UNNECESSARY;
4640 else
4641 skb->ip_summed = CHECKSUM_NONE;
4642
4643 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4644
4645 if (len > (tp->dev->mtu + ETH_HLEN) &&
4646 skb->protocol != htons(ETH_P_8021Q)) {
4647 dev_kfree_skb(skb);
4648 goto next_pkt;
4649 }
4650
1da177e4
LT		 4651#if TG3_VLAN_TAG_USED
4652 if (tp->vlgrp != NULL &&
4653 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4654 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4655 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4656 } else
4657#endif
17375d25 4658 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4659
1da177e4
LT		 4660 received++;
4661 budget--;
4662
4663next_pkt:
4664 (*post_ptr)++;
f92905de
MC		 4665
4666 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4667 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4668
4669 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4670 TG3_64BIT_REG_LOW, idx);
4671 work_mask &= ~RXD_OPAQUE_RING_STD;
4672 rx_std_posted = 0;
4673 }
1da177e4 4674next_pkt_nopost:
483ba50b 4675 sw_idx++;
6b31a515 4676 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4677
4678 /* Refresh hw_idx to see if there is new work */
4679 if (sw_idx == hw_idx) {
8d9d7cfc 4680 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4681 rmb();
4682 }
1da177e4
LT		 4683 }
4684
4685 /* ACK the status ring. */
72334482
MC		 4686 tnapi->rx_rcb_ptr = sw_idx;
4687 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4688
4689 /* Refill RX ring(s). */
4690 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4691 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4692 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4693 sw_idx);
4694 }
4695 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4696 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4697 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4698 sw_idx);
4699 }
4700 mmiowb();
4701
4702 return received;
4703}
4704
17375d25 4705static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4706{
17375d25 4707 struct tg3 *tp = tnapi->tp;
898a56f8 4708 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4709
1da177e4
LT		 4710 /* handle link change and other phy events */
4711 if (!(tp->tg3_flags &
4712 (TG3_FLAG_USE_LINKCHG_REG |
4713 TG3_FLAG_POLL_SERDES))) {
4714 if (sblk->status & SD_STATUS_LINK_CHG) {
4715 sblk->status = SD_STATUS_UPDATED |
4716 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4717 spin_lock(&tp->lock);
dd477003
MC		 4718 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4719 tw32_f(MAC_STATUS,
4720 (MAC_STATUS_SYNC_CHANGED |
4721 MAC_STATUS_CFG_CHANGED |
4722 MAC_STATUS_MI_COMPLETION |
4723 MAC_STATUS_LNKSTATE_CHANGED));
4724 udelay(40);
4725 } else
4726 tg3_setup_phy(tp, 0);
f47c11ee 4727 spin_unlock(&tp->lock);
1da177e4
LT		 4728 }
4729 }
4730
4731 /* run TX completion thread */
f3f3f27e 4732 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4733 tg3_tx(tnapi);
6f535763 4734 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4735 return work_done;
1da177e4
LT		 4736 }
4737
1da177e4
LT		 4738 /* run RX thread, within the bounds set by NAPI.
4739 * All RX "locking" is done by ensuring outside
bea3348e 4740 * code synchronizes with tg3->napi.poll()
1da177e4 4741 */
8d9d7cfc 4742 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4743 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4744
6f535763
DM		 4745 return work_done;
4746}
4747
4748static int tg3_poll(struct napi_struct *napi, int budget)
4749{
8ef0442f
MC		 4750 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4751 struct tg3 *tp = tnapi->tp;
6f535763 4752 int work_done = 0;
898a56f8 4753 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4754
4755 while (1) {
17375d25 4756 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4757
4758 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4759 goto tx_recovery;
4760
4761 if (unlikely(work_done >= budget))
4762 break;
4763
4fd7ab59 4764 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4765 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4766 * to tell the hw how much work has been processed,
4767 * so we must read it before checking for more work.
4768 */
898a56f8
MC		 4769 tnapi->last_tag = sblk->status_tag;
4770 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4771 rmb();
4772 } else
4773 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4774
17375d25 4775 if (likely(!tg3_has_work(tnapi))) {
288379f0 4776 napi_complete(napi);
17375d25 4777 tg3_int_reenable(tnapi);
6f535763
DM		 4778 break;
4779 }
1da177e4
LT		 4780 }
4781
bea3348e 4782 return work_done;
6f535763
DM		 4783
4784tx_recovery:
4fd7ab59 4785 /* work_done is guaranteed to be less than budget. */
288379f0 4786 napi_complete(napi);
6f535763 4787 schedule_work(&tp->reset_task);
4fd7ab59 4788 return work_done;
1da177e4
LT		 4789}
4790
f47c11ee
DM		 4791static void tg3_irq_quiesce(struct tg3 *tp)
4792{
4f125f42
MC		 4793 int i;
4794
f47c11ee
DM		 4795 BUG_ON(tp->irq_sync);
4796
4797 tp->irq_sync = 1;
4798 smp_mb();
4799
4f125f42
MC		 4800 for (i = 0; i < tp->irq_cnt; i++)
4801 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4802}
4803
4804static inline int tg3_irq_sync(struct tg3 *tp)
4805{
4806 return tp->irq_sync;
4807}
4808
4809/* Fully shutdown all tg3 driver activity elsewhere in the system.
4810 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4811 * with as well. Most of the time, this is not necessary except when
4812 * shutting down the device.
4813 */
4814static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4815{
46966545 4816 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4817 if (irq_sync)
4818 tg3_irq_quiesce(tp);
f47c11ee
DM		 4819}
4820
4821static inline void tg3_full_unlock(struct tg3 *tp)
4822{
f47c11ee
DM		 4823 spin_unlock_bh(&tp->lock);
4824}
4825
fcfa0a32
MC		 4826/* One-shot MSI handler - Chip automatically disables interrupt
4827 * after sending MSI so driver doesn't have to do it.
4828 */
7d12e780 4829static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4830{
09943a18
MC		 4831 struct tg3_napi *tnapi = dev_id;
4832 struct tg3 *tp = tnapi->tp;
fcfa0a32 4833
898a56f8 4834 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4835 if (tnapi->rx_rcb)
4836 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4837
4838 if (likely(!tg3_irq_sync(tp)))
09943a18 4839 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4840
4841 return IRQ_HANDLED;
4842}
4843
88b06bc2
MC		 4844/* MSI ISR - No need to check for interrupt sharing and no need to
4845 * flush status block and interrupt mailbox. PCI ordering rules
4846 * guarantee that MSI will arrive after the status block.
4847 */
7d12e780 4848static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4849{
09943a18
MC		 4850 struct tg3_napi *tnapi = dev_id;
4851 struct tg3 *tp = tnapi->tp;
88b06bc2 4852
898a56f8 4853 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4854 if (tnapi->rx_rcb)
4855 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4856 /*
fac9b83e 4857 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4858 * chip-internal interrupt pending events.
fac9b83e 4859 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4860 * NIC to stop sending us irqs, engaging "in-intr-handler"
4861 * event coalescing.
4862 */
4863 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4864 if (likely(!tg3_irq_sync(tp)))
09943a18 4865 napi_schedule(&tnapi->napi);
61487480 4866
88b06bc2
MC		 4867 return IRQ_RETVAL(1);
4868}
4869
7d12e780 4870static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4871{
09943a18
MC		 4872 struct tg3_napi *tnapi = dev_id;
4873 struct tg3 *tp = tnapi->tp;
898a56f8 4874 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4875 unsigned int handled = 1;
4876
1da177e4
LT		 4877 /* In INTx mode, it is possible for the interrupt to arrive at
4878 * the CPU before the status block posted prior to the interrupt.
4879 * Reading the PCI State register will confirm whether the
4880 * interrupt is ours and will flush the status block.
4881 */
d18edcb2
MC		 4882 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4883 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4884 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4885 handled = 0;
f47c11ee 4886 goto out;
fac9b83e 4887 }
d18edcb2
MC		 4888 }
4889
4890 /*
4891 * Writing any value to intr-mbox-0 clears PCI INTA# and
4892 * chip-internal interrupt pending events.
4893 * Writing non-zero to intr-mbox-0 additional tells the
4894 * NIC to stop sending us irqs, engaging "in-intr-handler"
4895 * event coalescing.
c04cb347
MC		 4896 *
4897 * Flush the mailbox to de-assert the IRQ immediately to prevent
4898 * spurious interrupts. The flush impacts performance but
4899 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4900 */
c04cb347 4901 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4902 if (tg3_irq_sync(tp))
4903 goto out;
4904 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4905 if (likely(tg3_has_work(tnapi))) {
72334482 4906 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4907 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4908 } else {
4909 /* No work, shared interrupt perhaps? re-enable
4910 * interrupts, and flush that PCI write
4911 */
4912 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4913 0x00000000);
fac9b83e 4914 }
f47c11ee 4915out:
fac9b83e
DM		 4916 return IRQ_RETVAL(handled);
4917}
4918
7d12e780 4919static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4920{
09943a18
MC		 4921 struct tg3_napi *tnapi = dev_id;
4922 struct tg3 *tp = tnapi->tp;
898a56f8 4923 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4924 unsigned int handled = 1;
4925
fac9b83e
DM		 4926 /* In INTx mode, it is possible for the interrupt to arrive at
4927 * the CPU before the status block posted prior to the interrupt.
4928 * Reading the PCI State register will confirm whether the
4929 * interrupt is ours and will flush the status block.
4930 */
898a56f8 4931 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4932 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4933 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4934 handled = 0;
f47c11ee 4935 goto out;
1da177e4 4936 }
d18edcb2
MC		 4937 }
4938
4939 /*
4940 * writing any value to intr-mbox-0 clears PCI INTA# and
4941 * chip-internal interrupt pending events.
4942 * writing non-zero to intr-mbox-0 additional tells the
4943 * NIC to stop sending us irqs, engaging "in-intr-handler"
4944 * event coalescing.
c04cb347
MC		 4945 *
4946 * Flush the mailbox to de-assert the IRQ immediately to prevent
4947 * spurious interrupts. The flush impacts performance but
4948 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4949 */
c04cb347 4950 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4951
4952 /*
4953 * In a shared interrupt configuration, sometimes other devices'
4954 * interrupts will scream. We record the current status tag here
4955 * so that the above check can report that the screaming interrupts
4956 * are unhandled. Eventually they will be silenced.
4957 */
898a56f8 4958 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4959
d18edcb2
MC		 4960 if (tg3_irq_sync(tp))
4961 goto out;
624f8e50 4962
72334482 4963 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4964
09943a18 4965 napi_schedule(&tnapi->napi);
624f8e50 4966
f47c11ee 4967out:
1da177e4
LT		 4968 return IRQ_RETVAL(handled);
4969}
4970
7938109f 4971/* ISR for interrupt test */
7d12e780 4972static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4973{
09943a18
MC		 4974 struct tg3_napi *tnapi = dev_id;
4975 struct tg3 *tp = tnapi->tp;
898a56f8 4976 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4977
f9804ddb
MC		 4978 if ((sblk->status & SD_STATUS_UPDATED) ||
4979 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4980 tg3_disable_ints(tp);
7938109f
MC		 4981 return IRQ_RETVAL(1);
4982 }
4983 return IRQ_RETVAL(0);
4984}
4985
8e7a22e3 4986static int tg3_init_hw(struct tg3 *, int);
944d980e 4987static int tg3_halt(struct tg3 *, int, int);
1da177e4 4988
b9ec6c1b
MC		 4989/* Restart hardware after configuration changes, self-test, etc.
4990 * Invoked with tp->lock held.
4991 */
4992static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4993 __releases(tp->lock)
4994 __acquires(tp->lock)
b9ec6c1b
MC		 4995{
4996 int err;
4997
4998 err = tg3_init_hw(tp, reset_phy);
4999 if (err) {
5000 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5001 "aborting.\n", tp->dev->name);
5002 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5003 tg3_full_unlock(tp);
5004 del_timer_sync(&tp->timer);
5005 tp->irq_sync = 0;
fed97810 5006 tg3_napi_enable(tp);
b9ec6c1b
MC		 5007 dev_close(tp->dev);
5008 tg3_full_lock(tp, 0);
5009 }
5010 return err;
5011}
5012
1da177e4
LT		 5013#ifdef CONFIG_NET_POLL_CONTROLLER
5014static void tg3_poll_controller(struct net_device *dev)
5015{
4f125f42 5016 int i;
88b06bc2
MC		 5017 struct tg3 *tp = netdev_priv(dev);
5018
4f125f42
MC		 5019 for (i = 0; i < tp->irq_cnt; i++)
5020 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5021}
5022#endif
5023
c4028958 5024static void tg3_reset_task(struct work_struct *work)
1da177e4 5025{
c4028958 5026 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5027 int err;
1da177e4
LT		 5028 unsigned int restart_timer;
5029
7faa006f 5030 tg3_full_lock(tp, 0);
7faa006f
MC		 5031
5032 if (!netif_running(tp->dev)) {
7faa006f
MC		 5033 tg3_full_unlock(tp);
5034 return;
5035 }
5036
5037 tg3_full_unlock(tp);
5038
b02fd9e3
MC		 5039 tg3_phy_stop(tp);
5040
1da177e4
LT		 5041 tg3_netif_stop(tp);
5042
f47c11ee 5043 tg3_full_lock(tp, 1);
1da177e4
LT		 5044
5045 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5046 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5047
df3e6548
MC		 5048 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5049 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5050 tp->write32_rx_mbox = tg3_write_flush_reg32;
5051 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5052 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5053 }
5054
944d980e 5055 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5056 err = tg3_init_hw(tp, 1);
5057 if (err)
b9ec6c1b 5058 goto out;
1da177e4
LT		 5059
5060 tg3_netif_start(tp);
5061
1da177e4
LT		 5062 if (restart_timer)
5063 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5064
b9ec6c1b 5065out:
7faa006f 5066 tg3_full_unlock(tp);
b02fd9e3
MC		 5067
5068 if (!err)
5069 tg3_phy_start(tp);
1da177e4
LT		 5070}
5071
b0408751
MC		 5072static void tg3_dump_short_state(struct tg3 *tp)
5073{
5074 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5075 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5076 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5077 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5078}
5079
1da177e4
LT		 5080static void tg3_tx_timeout(struct net_device *dev)
5081{
5082 struct tg3 *tp = netdev_priv(dev);
5083
b0408751 5084 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5085 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5086 dev->name);
b0408751
MC		 5087 tg3_dump_short_state(tp);
5088 }
1da177e4
LT		 5089
5090 schedule_work(&tp->reset_task);
5091}
5092
c58ec932
MC		 5093/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5094static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5095{
5096 u32 base = (u32) mapping & 0xffffffff;
5097
5098 return ((base > 0xffffdcc0) &&
5099 (base + len + 8 < base));
5100}
5101
72f2afb8
MC		 5102/* Test for DMA addresses > 40-bit */
5103static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5104 int len)
5105{
5106#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5107 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5108 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5109 return 0;
5110#else
5111 return 0;
5112#endif
5113}
5114
f3f3f27e 5115static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5116
72f2afb8
MC		 5117/* Workaround 4GB and 40-bit hardware DMA bugs. */
5118static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5119 u32 last_plus_one, u32 *start,
5120 u32 base_flags, u32 mss)
1da177e4 5121{
f3f3f27e 5122 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5123 struct sk_buff *new_skb;
c58ec932 5124 dma_addr_t new_addr = 0;
1da177e4 5125 u32 entry = *start;
c58ec932 5126 int i, ret = 0;
1da177e4 5127
41588ba1
MC		 5128 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5129 new_skb = skb_copy(skb, GFP_ATOMIC);
5130 else {
5131 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5132
5133 new_skb = skb_copy_expand(skb,
5134 skb_headroom(skb) + more_headroom,
5135 skb_tailroom(skb), GFP_ATOMIC);
5136 }
5137
1da177e4 5138 if (!new_skb) {
c58ec932
MC		 5139 ret = -1;
5140 } else {
5141 /* New SKB is guaranteed to be linear. */
5142 entry = *start;
90079ce8 5143 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5144 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5145
c58ec932
MC		 5146 /* Make sure new skb does not cross any 4G boundaries.
5147 * Drop the packet if it does.
5148 */
0e1406dd
MC		 5149 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5150 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5151 if (!ret)
5152 skb_dma_unmap(&tp->pdev->dev, new_skb,
5153 DMA_TO_DEVICE);
c58ec932
MC		 5154 ret = -1;
5155 dev_kfree_skb(new_skb);
5156 new_skb = NULL;
5157 } else {
f3f3f27e 5158 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5159 base_flags, 1 | (mss << 1));
5160 *start = NEXT_TX(entry);
5161 }
1da177e4
LT		 5162 }
5163
1da177e4
LT		 5164 /* Now clean up the sw ring entries. */
5165 i = 0;
5166 while (entry != last_plus_one) {
f3f3f27e
MC		 5167 if (i == 0)
5168 tnapi->tx_buffers[entry].skb = new_skb;
5169 else
5170 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5171 entry = NEXT_TX(entry);
5172 i++;
5173 }
5174
90079ce8 5175 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5176 dev_kfree_skb(skb);
5177
c58ec932 5178 return ret;
1da177e4
LT		 5179}
5180
f3f3f27e 5181static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5182 dma_addr_t mapping, int len, u32 flags,
5183 u32 mss_and_is_end)
5184{
f3f3f27e 5185 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5186 int is_end = (mss_and_is_end & 0x1);
5187 u32 mss = (mss_and_is_end >> 1);
5188 u32 vlan_tag = 0;
5189
5190 if (is_end)
5191 flags |= TXD_FLAG_END;
5192 if (flags & TXD_FLAG_VLAN) {
5193 vlan_tag = flags >> 16;
5194 flags &= 0xffff;
5195 }
5196 vlan_tag |= (mss << TXD_MSS_SHIFT);
5197
5198 txd->addr_hi = ((u64) mapping >> 32);
5199 txd->addr_lo = ((u64) mapping & 0xffffffff);
5200 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5201 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5202}
5203
5a6f3074
MC		 5204/* hard_start_xmit for devices that don't have any bugs and
5205 * support TG3_FLG2_HW_TSO_2 only.
5206 */
61357325
SH		 5207static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5208 struct net_device *dev)
5a6f3074
MC		 5209{
5210 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5211 u32 len, entry, base_flags, mss;
90079ce8
DM		 5212 struct skb_shared_info *sp;
5213 dma_addr_t mapping;
fe5f5787
MC		 5214 struct tg3_napi *tnapi;
5215 struct netdev_queue *txq;
5a6f3074 5216
fe5f5787
MC		 5217 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5218 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5219 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5220 tnapi++;
5a6f3074 5221
00b70504 5222 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5223 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5224 * interrupt. Furthermore, IRQ processing runs lockless so we have
5225 * no IRQ context deadlocks to worry about either. Rejoice!
5226 */
f3f3f27e 5227 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5228 if (!netif_tx_queue_stopped(txq)) {
5229 netif_tx_stop_queue(txq);
5a6f3074
MC		 5230
5231 /* This is a hard error, log it. */
5232 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5233 "queue awake!\n", dev->name);
5234 }
5a6f3074
MC		 5235 return NETDEV_TX_BUSY;
5236 }
5237
f3f3f27e 5238 entry = tnapi->tx_prod;
5a6f3074 5239 base_flags = 0;
5a6f3074 5240 mss = 0;
c13e3713 5241 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5242 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5243 u32 hdrlen;
5a6f3074
MC		 5244
5245 if (skb_header_cloned(skb) &&
5246 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5247 dev_kfree_skb(skb);
5248 goto out_unlock;
5249 }
5250
b0026624 5251 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5252 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5253 else {
eddc9ec5
ACM		 5254 struct iphdr *iph = ip_hdr(skb);
5255
ab6a5bb6 5256 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5257 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5258
eddc9ec5
ACM		 5259 iph->check = 0;
5260 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5261 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5262 }
5a6f3074 5263
f6eb9b1f
MC		 5264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5265 mss |= (hdrlen & 0xc) << 12;
5266 if (hdrlen & 0x10)
5267 base_flags |= 0x00000010;
5268 base_flags |= (hdrlen & 0x3e0) << 5;
5269 } else
5270 mss |= hdrlen << 9;
5271
5a6f3074
MC		 5272 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5273 TXD_FLAG_CPU_POST_DMA);
5274
aa8223c7 5275 tcp_hdr(skb)->check = 0;
5a6f3074 5276
5a6f3074 5277 }
84fa7933 5278 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5279 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5280#if TG3_VLAN_TAG_USED
5281 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5282 base_flags |= (TXD_FLAG_VLAN |
5283 (vlan_tx_tag_get(skb) << 16));
5284#endif
5285
90079ce8
DM		 5286 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5287 dev_kfree_skb(skb);
5288 goto out_unlock;
5289 }
5290
5291 sp = skb_shinfo(skb);
5292
042a53a9 5293 mapping = sp->dma_head;
5a6f3074 5294
f3f3f27e 5295 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5296
fe5f5787
MC		 5297 len = skb_headlen(skb);
5298
f6eb9b1f
MC		 5299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5300 !mss && skb->len > ETH_DATA_LEN)
5301 base_flags |= TXD_FLAG_JMB_PKT;
5302
f3f3f27e 5303 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5304 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5305
5306 entry = NEXT_TX(entry);
5307
5308 /* Now loop through additional data fragments, and queue them. */
5309 if (skb_shinfo(skb)->nr_frags > 0) {
5310 unsigned int i, last;
5311
5312 last = skb_shinfo(skb)->nr_frags - 1;
5313 for (i = 0; i <= last; i++) {
5314 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5315
5316 len = frag->size;
042a53a9 5317 mapping = sp->dma_maps[i];
f3f3f27e 5318 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5319
f3f3f27e 5320 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5321 base_flags, (i == last) | (mss << 1));
5322
5323 entry = NEXT_TX(entry);
5324 }
5325 }
5326
5327 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5328 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5329
f3f3f27e
MC		 5330 tnapi->tx_prod = entry;
5331 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5332 netif_tx_stop_queue(txq);
f3f3f27e 5333 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5334 netif_tx_wake_queue(txq);
5a6f3074
MC		 5335 }
5336
5337out_unlock:
cdd0db05 5338 mmiowb();
5a6f3074
MC		 5339
5340 return NETDEV_TX_OK;
5341}
5342
61357325
SH		 5343static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5344 struct net_device *);
52c0fd83
MC		 5345
5346/* Use GSO to workaround a rare TSO bug that may be triggered when the
5347 * TSO header is greater than 80 bytes.
5348 */
5349static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5350{
5351 struct sk_buff *segs, *nskb;
f3f3f27e 5352 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5353
5354 /* Estimate the number of fragments in the worst case */
f3f3f27e 5355 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5356 netif_stop_queue(tp->dev);
f3f3f27e 5357 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5358 return NETDEV_TX_BUSY;
5359
5360 netif_wake_queue(tp->dev);
52c0fd83
MC		 5361 }
5362
5363 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5364 if (IS_ERR(segs))
52c0fd83
MC		 5365 goto tg3_tso_bug_end;
5366
5367 do {
5368 nskb = segs;
5369 segs = segs->next;
5370 nskb->next = NULL;
5371 tg3_start_xmit_dma_bug(nskb, tp->dev);
5372 } while (segs);
5373
5374tg3_tso_bug_end:
5375 dev_kfree_skb(skb);
5376
5377 return NETDEV_TX_OK;
5378}
52c0fd83 5379
5a6f3074
MC		 5380/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5381 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5382 */
61357325
SH		 5383static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5384 struct net_device *dev)
1da177e4
LT		 5385{
5386 struct tg3 *tp = netdev_priv(dev);
1da177e4 5387 u32 len, entry, base_flags, mss;
90079ce8 5388 struct skb_shared_info *sp;
1da177e4 5389 int would_hit_hwbug;
90079ce8 5390 dma_addr_t mapping;
f3f3f27e 5391 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5392
5393 len = skb_headlen(skb);
5394
00b70504 5395 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5396 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5397 * interrupt. Furthermore, IRQ processing runs lockless so we have
5398 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5399 */
f3f3f27e 5400 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5401 if (!netif_queue_stopped(dev)) {
5402 netif_stop_queue(dev);
5403
5404 /* This is a hard error, log it. */
5405 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5406 "queue awake!\n", dev->name);
5407 }
1da177e4
LT		 5408 return NETDEV_TX_BUSY;
5409 }
5410
f3f3f27e 5411 entry = tnapi->tx_prod;
1da177e4 5412 base_flags = 0;
84fa7933 5413 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5414 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5415 mss = 0;
c13e3713 5416 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5417 struct iphdr *iph;
92c6b8d1 5418 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5419
5420 if (skb_header_cloned(skb) &&
5421 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5422 dev_kfree_skb(skb);
5423 goto out_unlock;
5424 }
5425
ab6a5bb6 5426 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5427 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5428
52c0fd83
MC		 5429 hdr_len = ip_tcp_len + tcp_opt_len;
5430 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5431 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5432 return (tg3_tso_bug(tp, skb));
5433
1da177e4
LT		 5434 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5435 TXD_FLAG_CPU_POST_DMA);
5436
eddc9ec5
ACM		 5437 iph = ip_hdr(skb);
5438 iph->check = 0;
5439 iph->tot_len = htons(mss + hdr_len);
1da177e4 5440 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5441 tcp_hdr(skb)->check = 0;
1da177e4 5442 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5443 } else
5444 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5445 iph->daddr, 0,
5446 IPPROTO_TCP,
5447 0);
1da177e4 5448
92c6b8d1
MC		 5449 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5450 mss |= hdr_len << 9;
5451 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5452 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5453 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5454 int tsflags;
5455
eddc9ec5 5456 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5457 mss |= (tsflags << 11);
5458 }
5459 } else {
eddc9ec5 5460 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5461 int tsflags;
5462
eddc9ec5 5463 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5464 base_flags |= tsflags << 12;
5465 }
5466 }
5467 }
1da177e4
LT		 5468#if TG3_VLAN_TAG_USED
5469 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5470 base_flags |= (TXD_FLAG_VLAN |
5471 (vlan_tx_tag_get(skb) << 16));
5472#endif
5473
90079ce8
DM		 5474 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5475 dev_kfree_skb(skb);
5476 goto out_unlock;
5477 }
5478
5479 sp = skb_shinfo(skb);
5480
042a53a9 5481 mapping = sp->dma_head;
1da177e4 5482
f3f3f27e 5483 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5484
5485 would_hit_hwbug = 0;
5486
92c6b8d1
MC		 5487 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5488 would_hit_hwbug = 1;
5489
0e1406dd
MC		 5490 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5491 tg3_4g_overflow_test(mapping, len))
5492 would_hit_hwbug = 1;
5493
5494 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5495 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5496 would_hit_hwbug = 1;
0e1406dd
MC		 5497
5498 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5499 would_hit_hwbug = 1;
1da177e4 5500
f3f3f27e 5501 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5502 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5503
5504 entry = NEXT_TX(entry);
5505
5506 /* Now loop through additional data fragments, and queue them. */
5507 if (skb_shinfo(skb)->nr_frags > 0) {
5508 unsigned int i, last;
5509
5510 last = skb_shinfo(skb)->nr_frags - 1;
5511 for (i = 0; i <= last; i++) {
5512 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5513
5514 len = frag->size;
042a53a9 5515 mapping = sp->dma_maps[i];
1da177e4 5516
f3f3f27e 5517 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5518
92c6b8d1
MC		 5519 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5520 len <= 8)
5521 would_hit_hwbug = 1;
5522
0e1406dd
MC		 5523 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5524 tg3_4g_overflow_test(mapping, len))
c58ec932 5525 would_hit_hwbug = 1;
1da177e4 5526
0e1406dd
MC		 5527 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5528 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5529 would_hit_hwbug = 1;
5530
1da177e4 5531 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5532 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5533 base_flags, (i == last)|(mss << 1));
5534 else
f3f3f27e 5535 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5536 base_flags, (i == last));
5537
5538 entry = NEXT_TX(entry);
5539 }
5540 }
5541
5542 if (would_hit_hwbug) {
5543 u32 last_plus_one = entry;
5544 u32 start;
1da177e4 5545
c58ec932
MC		 5546 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5547 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5548
5549 /* If the workaround fails due to memory/mapping
5550 * failure, silently drop this packet.
5551 */
72f2afb8 5552 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5553 &start, base_flags, mss))
1da177e4
LT		 5554 goto out_unlock;
5555
5556 entry = start;
5557 }
5558
5559 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5560 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5561
f3f3f27e
MC		 5562 tnapi->tx_prod = entry;
5563 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5564 netif_stop_queue(dev);
f3f3f27e 5565 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5566 netif_wake_queue(tp->dev);
5567 }
1da177e4
LT		 5568
5569out_unlock:
cdd0db05 5570 mmiowb();
1da177e4
LT		 5571
5572 return NETDEV_TX_OK;
5573}
5574
5575static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5576 int new_mtu)
5577{
5578 dev->mtu = new_mtu;
5579
ef7f5ec0 5580 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5581 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5582 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5583 ethtool_op_set_tso(dev, 0);
5584 }
5585 else
5586 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5587 } else {
a4e2b347 5588 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5589 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5590 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5591 }
1da177e4
LT		 5592}
5593
5594static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5595{
5596 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5597 int err;
1da177e4
LT		 5598
5599 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5600 return -EINVAL;
5601
5602 if (!netif_running(dev)) {
5603 /* We'll just catch it later when the
5604 * device is up'd.
5605 */
5606 tg3_set_mtu(dev, tp, new_mtu);
5607 return 0;
5608 }
5609
b02fd9e3
MC		 5610 tg3_phy_stop(tp);
5611
1da177e4 5612 tg3_netif_stop(tp);
f47c11ee
DM		 5613
5614 tg3_full_lock(tp, 1);
1da177e4 5615
944d980e 5616 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5617
5618 tg3_set_mtu(dev, tp, new_mtu);
5619
b9ec6c1b 5620 err = tg3_restart_hw(tp, 0);
1da177e4 5621
b9ec6c1b
MC		 5622 if (!err)
5623 tg3_netif_start(tp);
1da177e4 5624
f47c11ee 5625 tg3_full_unlock(tp);
1da177e4 5626
b02fd9e3
MC		 5627 if (!err)
5628 tg3_phy_start(tp);
5629
b9ec6c1b 5630 return err;
1da177e4
LT		 5631}
5632
21f581a5
MC		 5633static void tg3_rx_prodring_free(struct tg3 *tp,
5634 struct tg3_rx_prodring_set *tpr)
1da177e4 5635{
1da177e4 5636 int i;
f3f3f27e 5637 struct ring_info *rxp;
1da177e4
LT		 5638
5639 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5640 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5641
5642 if (rxp->skb == NULL)
5643 continue;
1da177e4 5644
1da177e4
LT		 5645 pci_unmap_single(tp->pdev,
5646 pci_unmap_addr(rxp, mapping),
cf7a7298 5647 tp->rx_pkt_map_sz,
1da177e4
LT		 5648 PCI_DMA_FROMDEVICE);
5649 dev_kfree_skb_any(rxp->skb);
5650 rxp->skb = NULL;
5651 }
5652
cf7a7298
MC		 5653 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5654 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5655 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5656
cf7a7298
MC		 5657 if (rxp->skb == NULL)
5658 continue;
1da177e4 5659
cf7a7298
MC		 5660 pci_unmap_single(tp->pdev,
5661 pci_unmap_addr(rxp, mapping),
5662 TG3_RX_JMB_MAP_SZ,
5663 PCI_DMA_FROMDEVICE);
5664 dev_kfree_skb_any(rxp->skb);
5665 rxp->skb = NULL;
1da177e4 5666 }
1da177e4
LT		 5667 }
5668}
5669
5670/* Initialize tx/rx rings for packet processing.
5671 *
5672 * The chip has been shut down and the driver detached from
5673 * the networking, so no interrupts or new tx packets will
5674 * end up in the driver. tp->{tx,}lock are held and thus
5675 * we may not sleep.
5676 */
21f581a5
MC		 5677static int tg3_rx_prodring_alloc(struct tg3 *tp,
5678 struct tg3_rx_prodring_set *tpr)
1da177e4 5679{
287be12e 5680 u32 i, rx_pkt_dma_sz;
17375d25 5681 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5682
1da177e4 5683 /* Zero out all descriptors. */
21f581a5 5684 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5685
287be12e 5686 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5687 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5688 tp->dev->mtu > ETH_DATA_LEN)
5689 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5690 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5691
1da177e4
LT		 5692 /* Initialize invariants of the rings, we only set this
5693 * stuff once. This works because the card does not
5694 * write into the rx buffer posting rings.
5695 */
5696 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5697 struct tg3_rx_buffer_desc *rxd;
5698
21f581a5 5699 rxd = &tpr->rx_std[i];
287be12e 5700 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5701 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5702 rxd->opaque = (RXD_OPAQUE_RING_STD |
5703 (i << RXD_OPAQUE_INDEX_SHIFT));
5704 }
5705
1da177e4
LT		 5706 /* Now allocate fresh SKBs for each rx ring. */
5707 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5708 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5709 printk(KERN_WARNING PFX
5710 "%s: Using a smaller RX standard ring, "
5711 "only %d out of %d buffers were allocated "
5712 "successfully.\n",
5713 tp->dev->name, i, tp->rx_pending);
5714 if (i == 0)
cf7a7298 5715 goto initfail;
32d8c572 5716 tp->rx_pending = i;
1da177e4 5717 break;
32d8c572 5718 }
1da177e4
LT		 5719 }
5720
cf7a7298
MC		 5721 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5722 goto done;
5723
21f581a5 5724 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5725
0f893dc6 5726 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5727 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5728 struct tg3_rx_buffer_desc *rxd;
5729
79ed5ac7 5730 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5731 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5732 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5733 RXD_FLAG_JUMBO;
5734 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5735 (i << RXD_OPAQUE_INDEX_SHIFT));
5736 }
5737
1da177e4 5738 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5739 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5740 -1, i) < 0) {
5741 printk(KERN_WARNING PFX
5742 "%s: Using a smaller RX jumbo ring, "
5743 "only %d out of %d buffers were "
5744 "allocated successfully.\n",
5745 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5746 if (i == 0)
5747 goto initfail;
32d8c572 5748 tp->rx_jumbo_pending = i;
1da177e4 5749 break;
32d8c572 5750 }
1da177e4
LT		 5751 }
5752 }
cf7a7298
MC		 5753
5754done:
32d8c572 5755 return 0;
cf7a7298
MC		 5756
5757initfail:
21f581a5 5758 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5759 return -ENOMEM;
1da177e4
LT		 5760}
5761
21f581a5
MC		 5762static void tg3_rx_prodring_fini(struct tg3 *tp,
5763 struct tg3_rx_prodring_set *tpr)
1da177e4 5764{
21f581a5
MC		 5765 kfree(tpr->rx_std_buffers);
5766 tpr->rx_std_buffers = NULL;
5767 kfree(tpr->rx_jmb_buffers);
5768 tpr->rx_jmb_buffers = NULL;
5769 if (tpr->rx_std) {
1da177e4 5770 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5771 tpr->rx_std, tpr->rx_std_mapping);
5772 tpr->rx_std = NULL;
1da177e4 5773 }
21f581a5 5774 if (tpr->rx_jmb) {
1da177e4 5775 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5776 tpr->rx_jmb, tpr->rx_jmb_mapping);
5777 tpr->rx_jmb = NULL;
1da177e4 5778 }
cf7a7298
MC		 5779}
5780
21f581a5
MC		 5781static int tg3_rx_prodring_init(struct tg3 *tp,
5782 struct tg3_rx_prodring_set *tpr)
cf7a7298 5783{
21f581a5
MC		 5784 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5785 TG3_RX_RING_SIZE, GFP_KERNEL);
5786 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5787 return -ENOMEM;
5788
21f581a5
MC		 5789 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5790 &tpr->rx_std_mapping);
5791 if (!tpr->rx_std)
cf7a7298
MC		 5792 goto err_out;
5793
5794 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5795 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5796 TG3_RX_JUMBO_RING_SIZE,
5797 GFP_KERNEL);
5798 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5799 goto err_out;
5800
21f581a5
MC		 5801 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5802 TG3_RX_JUMBO_RING_BYTES,
5803 &tpr->rx_jmb_mapping);
5804 if (!tpr->rx_jmb)
cf7a7298
MC		 5805 goto err_out;
5806 }
5807
5808 return 0;
5809
5810err_out:
21f581a5 5811 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5812 return -ENOMEM;
5813}
5814
5815/* Free up pending packets in all rx/tx rings.
5816 *
5817 * The chip has been shut down and the driver detached from
5818 * the networking, so no interrupts or new tx packets will
5819 * end up in the driver. tp->{tx,}lock is not held and we are not
5820 * in an interrupt context and thus may sleep.
5821 */
5822static void tg3_free_rings(struct tg3 *tp)
5823{
f77a6a8e 5824 int i, j;
cf7a7298 5825
f77a6a8e
MC		 5826 for (j = 0; j < tp->irq_cnt; j++) {
5827 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5828
0c1d0e2b
MC		 5829 if (!tnapi->tx_buffers)
5830 continue;
5831
f77a6a8e
MC		 5832 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5833 struct tx_ring_info *txp;
5834 struct sk_buff *skb;
cf7a7298 5835
f77a6a8e
MC		 5836 txp = &tnapi->tx_buffers[i];
5837 skb = txp->skb;
cf7a7298 5838
f77a6a8e
MC		 5839 if (skb == NULL) {
5840 i++;
5841 continue;
5842 }
cf7a7298 5843
f77a6a8e 5844 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5845
f77a6a8e 5846 txp->skb = NULL;
cf7a7298 5847
f77a6a8e
MC		 5848 i += skb_shinfo(skb)->nr_frags + 1;
5849
5850 dev_kfree_skb_any(skb);
5851 }
cf7a7298
MC		 5852 }
5853
21f581a5 5854 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5855}
5856
5857/* Initialize tx/rx rings for packet processing.
5858 *
5859 * The chip has been shut down and the driver detached from
5860 * the networking, so no interrupts or new tx packets will
5861 * end up in the driver. tp->{tx,}lock are held and thus
5862 * we may not sleep.
5863 */
5864static int tg3_init_rings(struct tg3 *tp)
5865{
f77a6a8e 5866 int i;
72334482 5867
cf7a7298
MC		 5868 /* Free up all the SKBs. */
5869 tg3_free_rings(tp);
5870
f77a6a8e
MC		 5871 for (i = 0; i < tp->irq_cnt; i++) {
5872 struct tg3_napi *tnapi = &tp->napi[i];
5873
5874 tnapi->last_tag = 0;
5875 tnapi->last_irq_tag = 0;
5876 tnapi->hw_status->status = 0;
5877 tnapi->hw_status->status_tag = 0;
5878 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5879
f77a6a8e
MC		 5880 tnapi->tx_prod = 0;
5881 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5882 if (tnapi->tx_ring)
5883 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5884
5885 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5886 if (tnapi->rx_rcb)
5887 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5888 }
72334482 5889
21f581a5 5890 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5891}
5892
5893/*
5894 * Must not be invoked with interrupt sources disabled and
5895 * the hardware shutdown down.
5896 */
5897static void tg3_free_consistent(struct tg3 *tp)
5898{
f77a6a8e 5899 int i;
898a56f8 5900
f77a6a8e
MC		 5901 for (i = 0; i < tp->irq_cnt; i++) {
5902 struct tg3_napi *tnapi = &tp->napi[i];
5903
5904 if (tnapi->tx_ring) {
5905 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5906 tnapi->tx_ring, tnapi->tx_desc_mapping);
5907 tnapi->tx_ring = NULL;
5908 }
5909
5910 kfree(tnapi->tx_buffers);
5911 tnapi->tx_buffers = NULL;
5912
5913 if (tnapi->rx_rcb) {
5914 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5915 tnapi->rx_rcb,
5916 tnapi->rx_rcb_mapping);
5917 tnapi->rx_rcb = NULL;
5918 }
5919
5920 if (tnapi->hw_status) {
5921 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5922 tnapi->hw_status,
5923 tnapi->status_mapping);
5924 tnapi->hw_status = NULL;
5925 }
1da177e4 5926 }
f77a6a8e 5927
1da177e4
LT		 5928 if (tp->hw_stats) {
5929 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5930 tp->hw_stats, tp->stats_mapping);
5931 tp->hw_stats = NULL;
5932 }
f77a6a8e 5933
21f581a5 5934 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5935}
5936
5937/*
5938 * Must not be invoked with interrupt sources disabled and
5939 * the hardware shutdown down. Can sleep.
5940 */
5941static int tg3_alloc_consistent(struct tg3 *tp)
5942{
f77a6a8e 5943 int i;
898a56f8 5944
21f581a5 5945 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5946 return -ENOMEM;
5947
f77a6a8e
MC		 5948 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5949 sizeof(struct tg3_hw_stats),
5950 &tp->stats_mapping);
5951 if (!tp->hw_stats)
1da177e4
LT		 5952 goto err_out;
5953
f77a6a8e 5954 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 5955
f77a6a8e
MC		 5956 for (i = 0; i < tp->irq_cnt; i++) {
5957 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 5958 struct tg3_hw_status *sblk;
1da177e4 5959
f77a6a8e
MC		 5960 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5961 TG3_HW_STATUS_SIZE,
5962 &tnapi->status_mapping);
5963 if (!tnapi->hw_status)
5964 goto err_out;
898a56f8 5965
f77a6a8e 5966 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 5967 sblk = tnapi->hw_status;
5968
5969 /*
5970 * When RSS is enabled, the status block format changes
5971 * slightly. The "rx_jumbo_consumer", "reserved",
5972 * and "rx_mini_consumer" members get mapped to the
5973 * other three rx return ring producer indexes.
5974 */
5975 switch (i) {
5976 default:
5977 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5978 break;
5979 case 2:
5980 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5981 break;
5982 case 3:
5983 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5984 break;
5985 case 4:
5986 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5987 break;
5988 }
72334482 5989
0c1d0e2b
MC		 5990 /*
5991 * If multivector RSS is enabled, vector 0 does not handle
5992 * rx or tx interrupts. Don't allocate any resources for it.
5993 */
5994 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5995 continue;
5996
f77a6a8e
MC		 5997 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5998 TG3_RX_RCB_RING_BYTES(tp),
5999 &tnapi->rx_rcb_mapping);
6000 if (!tnapi->rx_rcb)
6001 goto err_out;
72334482 6002
f77a6a8e 6003 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6004
f77a6a8e
MC		 6005 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6006 TG3_TX_RING_SIZE, GFP_KERNEL);
6007 if (!tnapi->tx_buffers)
6008 goto err_out;
6009
6010 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6011 TG3_TX_RING_BYTES,
6012 &tnapi->tx_desc_mapping);
6013 if (!tnapi->tx_ring)
6014 goto err_out;
6015 }
1da177e4
LT		 6016
6017 return 0;
6018
6019err_out:
6020 tg3_free_consistent(tp);
6021 return -ENOMEM;
6022}
6023
6024#define MAX_WAIT_CNT 1000
6025
6026/* To stop a block, clear the enable bit and poll till it
6027 * clears. tp->lock is held.
6028 */
b3b7d6be 6029static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6030{
6031 unsigned int i;
6032 u32 val;
6033
6034 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6035 switch (ofs) {
6036 case RCVLSC_MODE:
6037 case DMAC_MODE:
6038 case MBFREE_MODE:
6039 case BUFMGR_MODE:
6040 case MEMARB_MODE:
6041 /* We can't enable/disable these bits of the
6042 * 5705/5750, just say success.
6043 */
6044 return 0;
6045
6046 default:
6047 break;
855e1111 6048 }
1da177e4
LT		 6049 }
6050
6051 val = tr32(ofs);
6052 val &= ~enable_bit;
6053 tw32_f(ofs, val);
6054
6055 for (i = 0; i < MAX_WAIT_CNT; i++) {
6056 udelay(100);
6057 val = tr32(ofs);
6058 if ((val & enable_bit) == 0)
6059 break;
6060 }
6061
b3b7d6be 6062 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6063 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6064 "ofs=%lx enable_bit=%x\n",
6065 ofs, enable_bit);
6066 return -ENODEV;
6067 }
6068
6069 return 0;
6070}
6071
6072/* tp->lock is held. */
b3b7d6be 6073static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6074{
6075 int i, err;
6076
6077 tg3_disable_ints(tp);
6078
6079 tp->rx_mode &= ~RX_MODE_ENABLE;
6080 tw32_f(MAC_RX_MODE, tp->rx_mode);
6081 udelay(10);
6082
b3b7d6be
DM		 6083 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6084 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6085 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6086 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6087 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6088 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6089
6090 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6091 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6092 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6093 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6094 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6095 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6096 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6097
6098 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6099 tw32_f(MAC_MODE, tp->mac_mode);
6100 udelay(40);
6101
6102 tp->tx_mode &= ~TX_MODE_ENABLE;
6103 tw32_f(MAC_TX_MODE, tp->tx_mode);
6104
6105 for (i = 0; i < MAX_WAIT_CNT; i++) {
6106 udelay(100);
6107 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6108 break;
6109 }
6110 if (i >= MAX_WAIT_CNT) {
6111 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6112 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6113 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6114 err |= -ENODEV;
1da177e4
LT		 6115 }
6116
e6de8ad1 6117 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6118 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6119 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6120
6121 tw32(FTQ_RESET, 0xffffffff);
6122 tw32(FTQ_RESET, 0x00000000);
6123
b3b7d6be
DM		 6124 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6125 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6126
f77a6a8e
MC		 6127 for (i = 0; i < tp->irq_cnt; i++) {
6128 struct tg3_napi *tnapi = &tp->napi[i];
6129 if (tnapi->hw_status)
6130 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6131 }
1da177e4
LT		 6132 if (tp->hw_stats)
6133 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6134
1da177e4
LT		 6135 return err;
6136}
6137
0d3031d9
MC		 6138static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6139{
6140 int i;
6141 u32 apedata;
6142
6143 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6144 if (apedata != APE_SEG_SIG_MAGIC)
6145 return;
6146
6147 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6148 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6149 return;
6150
6151 /* Wait for up to 1 millisecond for APE to service previous event. */
6152 for (i = 0; i < 10; i++) {
6153 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6154 return;
6155
6156 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6157
6158 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6159 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6160 event | APE_EVENT_STATUS_EVENT_PENDING);
6161
6162 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6163
6164 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6165 break;
6166
6167 udelay(100);
6168 }
6169
6170 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6171 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6172}
6173
6174static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6175{
6176 u32 event;
6177 u32 apedata;
6178
6179 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6180 return;
6181
6182 switch (kind) {
6183 case RESET_KIND_INIT:
6184 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6185 APE_HOST_SEG_SIG_MAGIC);
6186 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6187 APE_HOST_SEG_LEN_MAGIC);
6188 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6189 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6190 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6191 APE_HOST_DRIVER_ID_MAGIC);
6192 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6193 APE_HOST_BEHAV_NO_PHYLOCK);
6194
6195 event = APE_EVENT_STATUS_STATE_START;
6196 break;
6197 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6198 /* With the interface we are currently using,
6199 * APE does not track driver state. Wiping
6200 * out the HOST SEGMENT SIGNATURE forces
6201 * the APE to assume OS absent status.
6202 */
6203 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6204
0d3031d9
MC		 6205 event = APE_EVENT_STATUS_STATE_UNLOAD;
6206 break;
6207 case RESET_KIND_SUSPEND:
6208 event = APE_EVENT_STATUS_STATE_SUSPEND;
6209 break;
6210 default:
6211 return;
6212 }
6213
6214 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6215
6216 tg3_ape_send_event(tp, event);
6217}
6218
1da177e4
LT		 6219/* tp->lock is held. */
6220static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6221{
f49639e6
DM		 6222 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6223 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6224
6225 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6226 switch (kind) {
6227 case RESET_KIND_INIT:
6228 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6229 DRV_STATE_START);
6230 break;
6231
6232 case RESET_KIND_SHUTDOWN:
6233 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6234 DRV_STATE_UNLOAD);
6235 break;
6236
6237 case RESET_KIND_SUSPEND:
6238 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6239 DRV_STATE_SUSPEND);
6240 break;
6241
6242 default:
6243 break;
855e1111 6244 }
1da177e4 6245 }
0d3031d9
MC		 6246
6247 if (kind == RESET_KIND_INIT ||
6248 kind == RESET_KIND_SUSPEND)
6249 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6250}
6251
6252/* tp->lock is held. */
6253static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6254{
6255 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6256 switch (kind) {
6257 case RESET_KIND_INIT:
6258 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6259 DRV_STATE_START_DONE);
6260 break;
6261
6262 case RESET_KIND_SHUTDOWN:
6263 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6264 DRV_STATE_UNLOAD_DONE);
6265 break;
6266
6267 default:
6268 break;
855e1111 6269 }
1da177e4 6270 }
0d3031d9
MC		 6271
6272 if (kind == RESET_KIND_SHUTDOWN)
6273 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6274}
6275
6276/* tp->lock is held. */
6277static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6278{
6279 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6280 switch (kind) {
6281 case RESET_KIND_INIT:
6282 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6283 DRV_STATE_START);
6284 break;
6285
6286 case RESET_KIND_SHUTDOWN:
6287 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6288 DRV_STATE_UNLOAD);
6289 break;
6290
6291 case RESET_KIND_SUSPEND:
6292 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6293 DRV_STATE_SUSPEND);
6294 break;
6295
6296 default:
6297 break;
855e1111 6298 }
1da177e4
LT		 6299 }
6300}
6301
7a6f4369
MC		 6302static int tg3_poll_fw(struct tg3 *tp)
6303{
6304 int i;
6305 u32 val;
6306
b5d3772c 6307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6308 /* Wait up to 20ms for init done. */
6309 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6310 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6311 return 0;
0ccead18 6312 udelay(100);
b5d3772c
MC		 6313 }
6314 return -ENODEV;
6315 }
6316
7a6f4369
MC		 6317 /* Wait for firmware initialization to complete. */
6318 for (i = 0; i < 100000; i++) {
6319 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6320 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6321 break;
6322 udelay(10);
6323 }
6324
6325 /* Chip might not be fitted with firmware. Some Sun onboard
6326 * parts are configured like that. So don't signal the timeout
6327 * of the above loop as an error, but do report the lack of
6328 * running firmware once.
6329 */
6330 if (i >= 100000 &&
6331 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6332 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6333
6334 printk(KERN_INFO PFX "%s: No firmware running.\n",
6335 tp->dev->name);
6336 }
6337
6338 return 0;
6339}
6340
ee6a99b5
MC		 6341/* Save PCI command register before chip reset */
6342static void tg3_save_pci_state(struct tg3 *tp)
6343{
8a6eac90 6344 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6345}
6346
6347/* Restore PCI state after chip reset */
6348static void tg3_restore_pci_state(struct tg3 *tp)
6349{
6350 u32 val;
6351
6352 /* Re-enable indirect register accesses. */
6353 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6354 tp->misc_host_ctrl);
6355
6356 /* Set MAX PCI retry to zero. */
6357 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6358 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6359 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6360 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6361 /* Allow reads and writes to the APE register and memory space. */
6362 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6363 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6364 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6365 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6366
8a6eac90 6367 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6368
fcb389df
MC		 6369 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6370 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6371 pcie_set_readrq(tp->pdev, 4096);
6372 else {
6373 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6374 tp->pci_cacheline_sz);
6375 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6376 tp->pci_lat_timer);
6377 }
114342f2 6378 }
5f5c51e3 6379
ee6a99b5 6380 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6381 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6382 u16 pcix_cmd;
6383
6384 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6385 &pcix_cmd);
6386 pcix_cmd &= ~PCI_X_CMD_ERO;
6387 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6388 pcix_cmd);
6389 }
ee6a99b5
MC		 6390
6391 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6392
6393 /* Chip reset on 5780 will reset MSI enable bit,
6394 * so need to restore it.
6395 */
6396 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6397 u16 ctrl;
6398
6399 pci_read_config_word(tp->pdev,
6400 tp->msi_cap + PCI_MSI_FLAGS,
6401 &ctrl);
6402 pci_write_config_word(tp->pdev,
6403 tp->msi_cap + PCI_MSI_FLAGS,
6404 ctrl | PCI_MSI_FLAGS_ENABLE);
6405 val = tr32(MSGINT_MODE);
6406 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6407 }
6408 }
6409}
6410
1da177e4
LT		 6411static void tg3_stop_fw(struct tg3 *);
6412
6413/* tp->lock is held. */
6414static int tg3_chip_reset(struct tg3 *tp)
6415{
6416 u32 val;
1ee582d8 6417 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6418 int i, err;
1da177e4 6419
f49639e6
DM		 6420 tg3_nvram_lock(tp);
6421
77b483f1
MC		 6422 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6423
f49639e6
DM		 6424 /* No matching tg3_nvram_unlock() after this because
6425 * chip reset below will undo the nvram lock.
6426 */
6427 tp->nvram_lock_cnt = 0;
1da177e4 6428
ee6a99b5
MC		 6429 /* GRC_MISC_CFG core clock reset will clear the memory
6430 * enable bit in PCI register 4 and the MSI enable bit
6431 * on some chips, so we save relevant registers here.
6432 */
6433 tg3_save_pci_state(tp);
6434
d9ab5ad1 6435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6436 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6437 tw32(GRC_FASTBOOT_PC, 0);
6438
1da177e4
LT		 6439 /*
6440 * We must avoid the readl() that normally takes place.
6441 * It locks machines, causes machine checks, and other
6442 * fun things. So, temporarily disable the 5701
6443 * hardware workaround, while we do the reset.
6444 */
1ee582d8
MC		 6445 write_op = tp->write32;
6446 if (write_op == tg3_write_flush_reg32)
6447 tp->write32 = tg3_write32;
1da177e4 6448
d18edcb2
MC		 6449 /* Prevent the irq handler from reading or writing PCI registers
6450 * during chip reset when the memory enable bit in the PCI command
6451 * register may be cleared. The chip does not generate interrupt
6452 * at this time, but the irq handler may still be called due to irq
6453 * sharing or irqpoll.
6454 */
6455 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6456 for (i = 0; i < tp->irq_cnt; i++) {
6457 struct tg3_napi *tnapi = &tp->napi[i];
6458 if (tnapi->hw_status) {
6459 tnapi->hw_status->status = 0;
6460 tnapi->hw_status->status_tag = 0;
6461 }
6462 tnapi->last_tag = 0;
6463 tnapi->last_irq_tag = 0;
b8fa2f3a 6464 }
d18edcb2 6465 smp_mb();
4f125f42
MC		 6466
6467 for (i = 0; i < tp->irq_cnt; i++)
6468 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6469
255ca311
MC		 6470 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6471 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6472 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6473 }
6474
1da177e4
LT		 6475 /* do the reset */
6476 val = GRC_MISC_CFG_CORECLK_RESET;
6477
6478 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6479 if (tr32(0x7e2c) == 0x60) {
6480 tw32(0x7e2c, 0x20);
6481 }
6482 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6483 tw32(GRC_MISC_CFG, (1 << 29));
6484 val |= (1 << 29);
6485 }
6486 }
6487
b5d3772c
MC		 6488 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6489 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6490 tw32(GRC_VCPU_EXT_CTRL,
6491 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6492 }
6493
1da177e4
LT		 6494 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6495 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6496 tw32(GRC_MISC_CFG, val);
6497
1ee582d8
MC		 6498 /* restore 5701 hardware bug workaround write method */
6499 tp->write32 = write_op;
1da177e4
LT		 6500
6501 /* Unfortunately, we have to delay before the PCI read back.
6502 * Some 575X chips even will not respond to a PCI cfg access
6503 * when the reset command is given to the chip.
6504 *
6505 * How do these hardware designers expect things to work
6506 * properly if the PCI write is posted for a long period
6507 * of time? It is always necessary to have some method by
6508 * which a register read back can occur to push the write
6509 * out which does the reset.
6510 *
6511 * For most tg3 variants the trick below was working.
6512 * Ho hum...
6513 */
6514 udelay(120);
6515
6516 /* Flush PCI posted writes. The normal MMIO registers
6517 * are inaccessible at this time so this is the only
6518 * way to make this reliably (actually, this is no longer
6519 * the case, see above). I tried to use indirect
6520 * register read/write but this upset some 5701 variants.
6521 */
6522 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6523
6524 udelay(120);
6525
5e7dfd0f 6526 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6527 u16 val16;
6528
1da177e4
LT		 6529 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6530 int i;
6531 u32 cfg_val;
6532
6533 /* Wait for link training to complete. */
6534 for (i = 0; i < 5000; i++)
6535 udelay(100);
6536
6537 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6538 pci_write_config_dword(tp->pdev, 0xc4,
6539 cfg_val | (1 << 15));
6540 }
5e7dfd0f 6541
e7126997
MC		 6542 /* Clear the "no snoop" and "relaxed ordering" bits. */
6543 pci_read_config_word(tp->pdev,
6544 tp->pcie_cap + PCI_EXP_DEVCTL,
6545 &val16);
6546 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6547 PCI_EXP_DEVCTL_NOSNOOP_EN);
6548 /*
6549 * Older PCIe devices only support the 128 byte
6550 * MPS setting. Enforce the restriction.
5e7dfd0f 6551 */
e7126997
MC		 6552 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6553 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6554 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6555 pci_write_config_word(tp->pdev,
6556 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6557 val16);
5e7dfd0f
MC		 6558
6559 pcie_set_readrq(tp->pdev, 4096);
6560
6561 /* Clear error status */
6562 pci_write_config_word(tp->pdev,
6563 tp->pcie_cap + PCI_EXP_DEVSTA,
6564 PCI_EXP_DEVSTA_CED |
6565 PCI_EXP_DEVSTA_NFED |
6566 PCI_EXP_DEVSTA_FED |
6567 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6568 }
6569
ee6a99b5 6570 tg3_restore_pci_state(tp);
1da177e4 6571
d18edcb2
MC		 6572 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6573
ee6a99b5
MC		 6574 val = 0;
6575 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6576 val = tr32(MEMARB_MODE);
ee6a99b5 6577 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6578
6579 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6580 tg3_stop_fw(tp);
6581 tw32(0x5000, 0x400);
6582 }
6583
6584 tw32(GRC_MODE, tp->grc_mode);
6585
6586 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6587 val = tr32(0xc4);
1da177e4
LT		 6588
6589 tw32(0xc4, val | (1 << 15));
6590 }
6591
6592 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6594 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6595 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6596 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6597 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6598 }
6599
6600 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6601 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6602 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6603 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6604 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6605 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6606 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6607 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6608 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6609 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6610 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6611 } else
6612 tw32_f(MAC_MODE, 0);
6613 udelay(40);
6614
77b483f1
MC		 6615 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6616
7a6f4369
MC		 6617 err = tg3_poll_fw(tp);
6618 if (err)
6619 return err;
1da177e4 6620
0a9140cf
MC		 6621 tg3_mdio_start(tp);
6622
52cdf852
MC		 6623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6624 u8 phy_addr;
6625
6626 phy_addr = tp->phy_addr;
6627 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6628
6629 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6630 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6631 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6632 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6633 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6634 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6635 udelay(10);
6636
6637 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6638 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6639 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6640 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6641 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6642 udelay(10);
6643
6644 tp->phy_addr = phy_addr;
6645 }
6646
1da177e4 6647 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6648 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6649 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6650 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6651 val = tr32(0x7c00);
1da177e4
LT		 6652
6653 tw32(0x7c00, val | (1 << 25));
6654 }
6655
6656 /* Reprobe ASF enable state. */
6657 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6658 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6659 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6660 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6661 u32 nic_cfg;
6662
6663 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6664 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6665 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6666 tp->last_event_jiffies = jiffies;
cbf46853 6667 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6668 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6669 }
6670 }
6671
6672 return 0;
6673}
6674
6675/* tp->lock is held. */
6676static void tg3_stop_fw(struct tg3 *tp)
6677{
0d3031d9
MC		 6678 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6679 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6680 /* Wait for RX cpu to ACK the previous event. */
6681 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6682
6683 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6684
6685 tg3_generate_fw_event(tp);
1da177e4 6686
7c5026aa
MC		 6687 /* Wait for RX cpu to ACK this event. */
6688 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6689 }
6690}
6691
6692/* tp->lock is held. */
944d980e 6693static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6694{
6695 int err;
6696
6697 tg3_stop_fw(tp);
6698
944d980e 6699 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6700
b3b7d6be 6701 tg3_abort_hw(tp, silent);
1da177e4
LT		 6702 err = tg3_chip_reset(tp);
6703
daba2a63
MC		 6704 __tg3_set_mac_addr(tp, 0);
6705
944d980e
MC		 6706 tg3_write_sig_legacy(tp, kind);
6707 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6708
6709 if (err)
6710 return err;
6711
6712 return 0;
6713}
6714
1da177e4
LT		 6715#define RX_CPU_SCRATCH_BASE 0x30000
6716#define RX_CPU_SCRATCH_SIZE 0x04000
6717#define TX_CPU_SCRATCH_BASE 0x34000
6718#define TX_CPU_SCRATCH_SIZE 0x04000
6719
6720/* tp->lock is held. */
6721static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6722{
6723 int i;
6724
5d9428de
ES		 6725 BUG_ON(offset == TX_CPU_BASE &&
6726 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6727
b5d3772c
MC		 6728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6729 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6730
6731 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6732 return 0;
6733 }
1da177e4
LT		 6734 if (offset == RX_CPU_BASE) {
6735 for (i = 0; i < 10000; i++) {
6736 tw32(offset + CPU_STATE, 0xffffffff);
6737 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6738 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6739 break;
6740 }
6741
6742 tw32(offset + CPU_STATE, 0xffffffff);
6743 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6744 udelay(10);
6745 } else {
6746 for (i = 0; i < 10000; i++) {
6747 tw32(offset + CPU_STATE, 0xffffffff);
6748 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6749 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6750 break;
6751 }
6752 }
6753
6754 if (i >= 10000) {
6755 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6756 "and %s CPU\n",
6757 tp->dev->name,
6758 (offset == RX_CPU_BASE ? "RX" : "TX"));
6759 return -ENODEV;
6760 }
ec41c7df
MC		 6761
6762 /* Clear firmware's nvram arbitration. */
6763 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6764 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6765 return 0;
6766}
6767
6768struct fw_info {
077f849d
JSR		 6769 unsigned int fw_base;
6770 unsigned int fw_len;
6771 const __be32 *fw_data;
1da177e4
LT		 6772};
6773
6774/* tp->lock is held. */
6775static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6776 int cpu_scratch_size, struct fw_info *info)
6777{
ec41c7df 6778 int err, lock_err, i;
1da177e4
LT		 6779 void (*write_op)(struct tg3 *, u32, u32);
6780
6781 if (cpu_base == TX_CPU_BASE &&
6782 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6783 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6784 "TX cpu firmware on %s which is 5705.\n",
6785 tp->dev->name);
6786 return -EINVAL;
6787 }
6788
6789 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6790 write_op = tg3_write_mem;
6791 else
6792 write_op = tg3_write_indirect_reg32;
6793
1b628151
MC		 6794 /* It is possible that bootcode is still loading at this point.
6795 * Get the nvram lock first before halting the cpu.
6796 */
ec41c7df 6797 lock_err = tg3_nvram_lock(tp);
1da177e4 6798 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6799 if (!lock_err)
6800 tg3_nvram_unlock(tp);
1da177e4
LT		 6801 if (err)
6802 goto out;
6803
6804 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6805 write_op(tp, cpu_scratch_base + i, 0);
6806 tw32(cpu_base + CPU_STATE, 0xffffffff);
6807 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6808 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6809 write_op(tp, (cpu_scratch_base +
077f849d 6810 (info->fw_base & 0xffff) +
1da177e4 6811 (i * sizeof(u32))),
077f849d 6812 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6813
6814 err = 0;
6815
6816out:
1da177e4
LT		 6817 return err;
6818}
6819
6820/* tp->lock is held. */
6821static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6822{
6823 struct fw_info info;
077f849d 6824 const __be32 *fw_data;
1da177e4
LT		 6825 int err, i;
6826
077f849d
JSR		 6827 fw_data = (void *)tp->fw->data;
6828
6829 /* Firmware blob starts with version numbers, followed by
6830 start address and length. We are setting complete length.
6831 length = end_address_of_bss - start_address_of_text.
6832 Remainder is the blob to be loaded contiguously
6833 from start address. */
6834
6835 info.fw_base = be32_to_cpu(fw_data[1]);
6836 info.fw_len = tp->fw->size - 12;
6837 info.fw_data = &fw_data[3];
1da177e4
LT		 6838
6839 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6840 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6841 &info);
6842 if (err)
6843 return err;
6844
6845 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6846 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6847 &info);
6848 if (err)
6849 return err;
6850
6851 /* Now startup only the RX cpu. */
6852 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6853 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6854
6855 for (i = 0; i < 5; i++) {
077f849d 6856 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6857 break;
6858 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6859 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6860 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6861 udelay(1000);
6862 }
6863 if (i >= 5) {
6864 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6865 "to set RX CPU PC, is %08x should be %08x\n",
6866 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6867 info.fw_base);
1da177e4
LT		 6868 return -ENODEV;
6869 }
6870 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6871 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6872
6873 return 0;
6874}
6875
1da177e4 6876/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6877
6878/* tp->lock is held. */
6879static int tg3_load_tso_firmware(struct tg3 *tp)
6880{
6881 struct fw_info info;
077f849d 6882 const __be32 *fw_data;
1da177e4
LT		 6883 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6884 int err, i;
6885
6886 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6887 return 0;
6888
077f849d
JSR		 6889 fw_data = (void *)tp->fw->data;
6890
6891 /* Firmware blob starts with version numbers, followed by
6892 start address and length. We are setting complete length.
6893 length = end_address_of_bss - start_address_of_text.
6894 Remainder is the blob to be loaded contiguously
6895 from start address. */
6896
6897 info.fw_base = be32_to_cpu(fw_data[1]);
6898 cpu_scratch_size = tp->fw_len;
6899 info.fw_len = tp->fw->size - 12;
6900 info.fw_data = &fw_data[3];
6901
1da177e4 6902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6903 cpu_base = RX_CPU_BASE;
6904 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6905 } else {
1da177e4
LT		 6906 cpu_base = TX_CPU_BASE;
6907 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6908 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6909 }
6910
6911 err = tg3_load_firmware_cpu(tp, cpu_base,
6912 cpu_scratch_base, cpu_scratch_size,
6913 &info);
6914 if (err)
6915 return err;
6916
6917 /* Now startup the cpu. */
6918 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6919 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6920
6921 for (i = 0; i < 5; i++) {
077f849d 6922 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6923 break;
6924 tw32(cpu_base + CPU_STATE, 0xffffffff);
6925 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6926 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6927 udelay(1000);
6928 }
6929 if (i >= 5) {
6930 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6931 "to set CPU PC, is %08x should be %08x\n",
6932 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6933 info.fw_base);
1da177e4
LT		 6934 return -ENODEV;
6935 }
6936 tw32(cpu_base + CPU_STATE, 0xffffffff);
6937 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6938 return 0;
6939}
6940
1da177e4 6941
1da177e4
LT		 6942static int tg3_set_mac_addr(struct net_device *dev, void *p)
6943{
6944 struct tg3 *tp = netdev_priv(dev);
6945 struct sockaddr *addr = p;
986e0aeb 6946 int err = 0, skip_mac_1 = 0;
1da177e4 6947
f9804ddb
MC		 6948 if (!is_valid_ether_addr(addr->sa_data))
6949 return -EINVAL;
6950
1da177e4
LT		 6951 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6952
e75f7c90
MC		 6953 if (!netif_running(dev))
6954 return 0;
6955
58712ef9 6956 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6957 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6958
986e0aeb
MC		 6959 addr0_high = tr32(MAC_ADDR_0_HIGH);
6960 addr0_low = tr32(MAC_ADDR_0_LOW);
6961 addr1_high = tr32(MAC_ADDR_1_HIGH);
6962 addr1_low = tr32(MAC_ADDR_1_LOW);
6963
6964 /* Skip MAC addr 1 if ASF is using it. */
6965 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6966 !(addr1_high == 0 && addr1_low == 0))
6967 skip_mac_1 = 1;
58712ef9 6968 }
986e0aeb
MC		 6969 spin_lock_bh(&tp->lock);
6970 __tg3_set_mac_addr(tp, skip_mac_1);
6971 spin_unlock_bh(&tp->lock);
1da177e4 6972
b9ec6c1b 6973 return err;
1da177e4
LT		 6974}
6975
6976/* tp->lock is held. */
6977static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6978 dma_addr_t mapping, u32 maxlen_flags,
6979 u32 nic_addr)
6980{
6981 tg3_write_mem(tp,
6982 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6983 ((u64) mapping >> 32));
6984 tg3_write_mem(tp,
6985 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6986 ((u64) mapping & 0xffffffff));
6987 tg3_write_mem(tp,
6988 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6989 maxlen_flags);
6990
6991 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6992 tg3_write_mem(tp,
6993 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6994 nic_addr);
6995}
6996
6997static void __tg3_set_rx_mode(struct net_device *);
d244c892 6998static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 6999{
b6080e12
MC		 7000 int i;
7001
7002 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7003 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7004 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7005 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7006
7007 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7008 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7009 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7010 } else {
7011 tw32(HOSTCC_TXCOL_TICKS, 0);
7012 tw32(HOSTCC_TXMAX_FRAMES, 0);
7013 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7014
7015 tw32(HOSTCC_RXCOL_TICKS, 0);
7016 tw32(HOSTCC_RXMAX_FRAMES, 0);
7017 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7018 }
b6080e12 7019
15f9850d
DM		 7020 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7021 u32 val = ec->stats_block_coalesce_usecs;
7022
b6080e12
MC		 7023 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7024 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7025
15f9850d
DM		 7026 if (!netif_carrier_ok(tp->dev))
7027 val = 0;
7028
7029 tw32(HOSTCC_STAT_COAL_TICKS, val);
7030 }
b6080e12
MC		 7031
7032 for (i = 0; i < tp->irq_cnt - 1; i++) {
7033 u32 reg;
7034
7035 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7036 tw32(reg, ec->rx_coalesce_usecs);
7037 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7038 tw32(reg, ec->tx_coalesce_usecs);
7039 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7040 tw32(reg, ec->rx_max_coalesced_frames);
7041 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7042 tw32(reg, ec->tx_max_coalesced_frames);
7043 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7044 tw32(reg, ec->rx_max_coalesced_frames_irq);
7045 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7046 tw32(reg, ec->tx_max_coalesced_frames_irq);
7047 }
7048
7049 for (; i < tp->irq_max - 1; i++) {
7050 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7051 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7052 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7053 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7054 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7055 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7056 }
15f9850d 7057}
1da177e4 7058
2d31ecaf
MC		 7059/* tp->lock is held. */
7060static void tg3_rings_reset(struct tg3 *tp)
7061{
7062 int i;
f77a6a8e 7063 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7064 struct tg3_napi *tnapi = &tp->napi[0];
7065
7066 /* Disable all transmit rings but the first. */
7067 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7068 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7069 else
7070 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7071
7072 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7073 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7074 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7075 BDINFO_FLAGS_DISABLED);
7076
7077
7078 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7080 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7081 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7082 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7083 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7084 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7085 else
7086 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7087
7088 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7089 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7090 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7091 BDINFO_FLAGS_DISABLED);
7092
7093 /* Disable interrupts */
7094 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7095
7096 /* Zero mailbox registers. */
f77a6a8e
MC		 7097 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7098 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7099 tp->napi[i].tx_prod = 0;
7100 tp->napi[i].tx_cons = 0;
7101 tw32_mailbox(tp->napi[i].prodmbox, 0);
7102 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7103 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7104 }
7105 } else {
7106 tp->napi[0].tx_prod = 0;
7107 tp->napi[0].tx_cons = 0;
7108 tw32_mailbox(tp->napi[0].prodmbox, 0);
7109 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7110 }
2d31ecaf
MC		 7111
7112 /* Make sure the NIC-based send BD rings are disabled. */
7113 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7114 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7115 for (i = 0; i < 16; i++)
7116 tw32_tx_mbox(mbox + i * 8, 0);
7117 }
7118
7119 txrcb = NIC_SRAM_SEND_RCB;
7120 rxrcb = NIC_SRAM_RCV_RET_RCB;
7121
7122 /* Clear status block in ram. */
7123 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7124
7125 /* Set status block DMA address */
7126 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7127 ((u64) tnapi->status_mapping >> 32));
7128 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7129 ((u64) tnapi->status_mapping & 0xffffffff));
7130
f77a6a8e
MC		 7131 if (tnapi->tx_ring) {
7132 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7133 (TG3_TX_RING_SIZE <<
7134 BDINFO_FLAGS_MAXLEN_SHIFT),
7135 NIC_SRAM_TX_BUFFER_DESC);
7136 txrcb += TG3_BDINFO_SIZE;
7137 }
7138
7139 if (tnapi->rx_rcb) {
7140 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7141 (TG3_RX_RCB_RING_SIZE(tp) <<
7142 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7143 rxrcb += TG3_BDINFO_SIZE;
7144 }
7145
7146 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7147
f77a6a8e
MC		 7148 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7149 u64 mapping = (u64)tnapi->status_mapping;
7150 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7151 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7152
7153 /* Clear status block in ram. */
7154 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7155
7156 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7157 (TG3_TX_RING_SIZE <<
7158 BDINFO_FLAGS_MAXLEN_SHIFT),
7159 NIC_SRAM_TX_BUFFER_DESC);
7160
7161 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7162 (TG3_RX_RCB_RING_SIZE(tp) <<
7163 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7164
7165 stblk += 8;
7166 txrcb += TG3_BDINFO_SIZE;
7167 rxrcb += TG3_BDINFO_SIZE;
7168 }
2d31ecaf
MC		 7169}
7170
1da177e4 7171/* tp->lock is held. */
8e7a22e3 7172static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7173{
7174 u32 val, rdmac_mode;
7175 int i, err, limit;
21f581a5 7176 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7177
7178 tg3_disable_ints(tp);
7179
7180 tg3_stop_fw(tp);
7181
7182 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7183
7184 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7185 tg3_abort_hw(tp, 1);
1da177e4
LT		 7186 }
7187
dd477003
MC		 7188 if (reset_phy &&
7189 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7190 tg3_phy_reset(tp);
7191
1da177e4
LT		 7192 err = tg3_chip_reset(tp);
7193 if (err)
7194 return err;
7195
7196 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7197
bcb37f6c 7198 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7199 val = tr32(TG3_CPMU_CTRL);
7200 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7201 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7202
7203 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7204 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7205 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7206 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7207
7208 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7209 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7210 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7211 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7212
7213 val = tr32(TG3_CPMU_HST_ACC);
7214 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7215 val |= CPMU_HST_ACC_MACCLK_6_25;
7216 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7217 }
7218
33466d93
MC		 7219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7220 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7221 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7222 PCIE_PWR_MGMT_L1_THRESH_4MS;
7223 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7224
7225 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7226 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7227
7228 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7229
f40386c8
MC		 7230 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7231 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7232 }
7233
1da177e4
LT		 7234 /* This works around an issue with Athlon chipsets on
7235 * B3 tigon3 silicon. This bit has no effect on any
7236 * other revision. But do not set this on PCI Express
795d01c5 7237 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7238 */
795d01c5
MC		 7239 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7240 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7241 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7242 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7243 }
1da177e4
LT		 7244
7245 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7246 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7247 val = tr32(TG3PCI_PCISTATE);
7248 val |= PCISTATE_RETRY_SAME_DMA;
7249 tw32(TG3PCI_PCISTATE, val);
7250 }
7251
0d3031d9
MC		 7252 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7253 /* Allow reads and writes to the
7254 * APE register and memory space.
7255 */
7256 val = tr32(TG3PCI_PCISTATE);
7257 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7258 PCISTATE_ALLOW_APE_SHMEM_WR;
7259 tw32(TG3PCI_PCISTATE, val);
7260 }
7261
1da177e4
LT		 7262 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7263 /* Enable some hw fixes. */
7264 val = tr32(TG3PCI_MSI_DATA);
7265 val |= (1 << 26) | (1 << 28) | (1 << 29);
7266 tw32(TG3PCI_MSI_DATA, val);
7267 }
7268
7269 /* Descriptor ring init may make accesses to the
7270 * NIC SRAM area to setup the TX descriptors, so we
7271 * can only do this after the hardware has been
7272 * successfully reset.
7273 */
32d8c572
MC		 7274 err = tg3_init_rings(tp);
7275 if (err)
7276 return err;
1da177e4 7277
9936bcf6 7278 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
f6eb9b1f
MC		 7279 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7280 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
d30cdd28
MC		 7281 /* This value is determined during the probe time DMA
7282 * engine test, tg3_test_dma.
7283 */
7284 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7285 }
1da177e4
LT		 7286
7287 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7288 GRC_MODE_4X_NIC_SEND_RINGS |
7289 GRC_MODE_NO_TX_PHDR_CSUM |
7290 GRC_MODE_NO_RX_PHDR_CSUM);
7291 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7292
7293 /* Pseudo-header checksum is done by hardware logic and not
7294 * the offload processers, so make the chip do the pseudo-
7295 * header checksums on receive. For transmit it is more
7296 * convenient to do the pseudo-header checksum in software
7297 * as Linux does that on transmit for us in all cases.
7298 */
7299 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7300
7301 tw32(GRC_MODE,
7302 tp->grc_mode |
7303 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7304
7305 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7306 val = tr32(GRC_MISC_CFG);
7307 val &= ~0xff;
7308 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7309 tw32(GRC_MISC_CFG, val);
7310
7311 /* Initialize MBUF/DESC pool. */
cbf46853 7312 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7313 /* Do nothing. */
7314 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7315 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7317 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7318 else
7319 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7320 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7321 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7322 }
1da177e4
LT		 7323 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7324 int fw_len;
7325
077f849d 7326 fw_len = tp->fw_len;
1da177e4
LT		 7327 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7328 tw32(BUFMGR_MB_POOL_ADDR,
7329 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7330 tw32(BUFMGR_MB_POOL_SIZE,
7331 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7332 }
1da177e4 7333
0f893dc6 7334 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7335 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7336 tp->bufmgr_config.mbuf_read_dma_low_water);
7337 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7338 tp->bufmgr_config.mbuf_mac_rx_low_water);
7339 tw32(BUFMGR_MB_HIGH_WATER,
7340 tp->bufmgr_config.mbuf_high_water);
7341 } else {
7342 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7343 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7344 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7345 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7346 tw32(BUFMGR_MB_HIGH_WATER,
7347 tp->bufmgr_config.mbuf_high_water_jumbo);
7348 }
7349 tw32(BUFMGR_DMA_LOW_WATER,
7350 tp->bufmgr_config.dma_low_water);
7351 tw32(BUFMGR_DMA_HIGH_WATER,
7352 tp->bufmgr_config.dma_high_water);
7353
7354 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7355 for (i = 0; i < 2000; i++) {
7356 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7357 break;
7358 udelay(10);
7359 }
7360 if (i >= 2000) {
7361 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7362 tp->dev->name);
7363 return -ENODEV;
7364 }
7365
7366 /* Setup replenish threshold. */
f92905de
MC		 7367 val = tp->rx_pending / 8;
7368 if (val == 0)
7369 val = 1;
7370 else if (val > tp->rx_std_max_post)
7371 val = tp->rx_std_max_post;
b5d3772c
MC		 7372 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7373 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7374 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7375
7376 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7377 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7378 }
f92905de
MC		 7379
7380 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7381
7382 /* Initialize TG3_BDINFO's at:
7383 * RCVDBDI_STD_BD: standard eth size rx ring
7384 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7385 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7386 *
7387 * like so:
7388 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7389 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7390 * ring attribute flags
7391 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7392 *
7393 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7394 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7395 *
7396 * The size of each ring is fixed in the firmware, but the location is
7397 * configurable.
7398 */
7399 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7400 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7401 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7402 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7403 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7404 NIC_SRAM_RX_BUFFER_DESC);
7405
fdb72b38
MC		 7406 /* Disable the mini ring */
7407 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7408 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7409 BDINFO_FLAGS_DISABLED);
7410
fdb72b38
MC		 7411 /* Program the jumbo buffer descriptor ring control
7412 * blocks on those devices that have them.
7413 */
8f666b07 7414 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7415 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7416 /* Setup replenish threshold. */
7417 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7418
0f893dc6 7419 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7420 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7421 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7422 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7423 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7424 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7425 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7426 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7427 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7428 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7429 } else {
7430 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7431 BDINFO_FLAGS_DISABLED);
7432 }
7433
f6eb9b1f
MC		 7434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7435 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7436 (RX_STD_MAX_SIZE << 2);
7437 else
7438 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7439 } else
7440 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7441
7442 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7443
21f581a5 7444 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7445 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7446 tpr->rx_std_ptr);
1da177e4 7447
21f581a5
MC		 7448 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7449 tp->rx_jumbo_pending : 0;
1da177e4 7450 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7451 tpr->rx_jmb_ptr);
1da177e4 7452
f6eb9b1f
MC		 7453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7454 tw32(STD_REPLENISH_LWM, 32);
7455 tw32(JMB_REPLENISH_LWM, 16);
7456 }
7457
2d31ecaf
MC		 7458 tg3_rings_reset(tp);
7459
1da177e4 7460 /* Initialize MAC address and backoff seed. */
986e0aeb 7461 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7462
7463 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7464 tw32(MAC_RX_MTU_SIZE,
7465 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7466
7467 /* The slot time is changed by tg3_setup_phy if we
7468 * run at gigabit with half duplex.
7469 */
7470 tw32(MAC_TX_LENGTHS,
7471 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7472 (6 << TX_LENGTHS_IPG_SHIFT) |
7473 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7474
7475 /* Receive rules. */
7476 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7477 tw32(RCVLPC_CONFIG, 0x0181);
7478
7479 /* Calculate RDMAC_MODE setting early, we need it to determine
7480 * the RCVLPC_STATE_ENABLE mask.
7481 */
7482 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7483 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7484 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7485 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7486 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7487
57e6983c 7488 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7489 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7491 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7492 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7493 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7494
85e94ced
MC		 7495 /* If statement applies to 5705 and 5750 PCI devices only */
7496 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7497 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7498 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7499 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7501 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7502 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7503 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7504 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7505 }
7506 }
7507
85e94ced
MC		 7508 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7509 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7510
1da177e4 7511 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7512 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7513
7514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7516 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7517
7518 /* Receive/send statistics. */
1661394e
MC		 7519 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7520 val = tr32(RCVLPC_STATS_ENABLE);
7521 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7522 tw32(RCVLPC_STATS_ENABLE, val);
7523 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7524 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7525 val = tr32(RCVLPC_STATS_ENABLE);
7526 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7527 tw32(RCVLPC_STATS_ENABLE, val);
7528 } else {
7529 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7530 }
7531 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7532 tw32(SNDDATAI_STATSENAB, 0xffffff);
7533 tw32(SNDDATAI_STATSCTRL,
7534 (SNDDATAI_SCTRL_ENABLE |
7535 SNDDATAI_SCTRL_FASTUPD));
7536
7537 /* Setup host coalescing engine. */
7538 tw32(HOSTCC_MODE, 0);
7539 for (i = 0; i < 2000; i++) {
7540 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7541 break;
7542 udelay(10);
7543 }
7544
d244c892 7545 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7546
1da177e4
LT		 7547 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7548 /* Status/statistics block address. See tg3_timer,
7549 * the tg3_periodic_fetch_stats call there, and
7550 * tg3_get_stats to see how this works for 5705/5750 chips.
7551 */
1da177e4
LT		 7552 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7553 ((u64) tp->stats_mapping >> 32));
7554 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7555 ((u64) tp->stats_mapping & 0xffffffff));
7556 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7557
1da177e4 7558 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7559
7560 /* Clear statistics and status block memory areas */
7561 for (i = NIC_SRAM_STATS_BLK;
7562 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7563 i += sizeof(u32)) {
7564 tg3_write_mem(tp, i, 0);
7565 udelay(40);
7566 }
1da177e4
LT		 7567 }
7568
7569 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7570
7571 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7572 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7573 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7574 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7575
c94e3941
MC		 7576 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7577 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7578 /* reset to prevent losing 1st rx packet intermittently */
7579 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7580 udelay(10);
7581 }
7582
3bda1258
MC		 7583 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7584 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7585 else
7586 tp->mac_mode = 0;
7587 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7588 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7589 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7590 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7591 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7592 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7593 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7594 udelay(40);
7595
314fba34 7596 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7597 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7598 * register to preserve the GPIO settings for LOMs. The GPIOs,
7599 * whether used as inputs or outputs, are set by boot code after
7600 * reset.
7601 */
9d26e213 7602 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7603 u32 gpio_mask;
7604
9d26e213
MC		 7605 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7606 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7607 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7608
7609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7610 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7611 GRC_LCLCTRL_GPIO_OUTPUT3;
7612
af36e6b6
MC		 7613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7614 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7615
aaf84465 7616 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7617 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7618
7619 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7620 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7621 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7622 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7623 }
1da177e4
LT		 7624 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7625 udelay(100);
7626
baf8a94a
MC		 7627 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7628 val = tr32(MSGINT_MODE);
7629 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7630 tw32(MSGINT_MODE, val);
7631 }
7632
1da177e4
LT		 7633 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7634 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7635 udelay(40);
7636 }
7637
7638 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7639 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7640 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7641 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7642 WDMAC_MODE_LNGREAD_ENAB);
7643
85e94ced
MC		 7644 /* If statement applies to 5705 and 5750 PCI devices only */
7645 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7646 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7648 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7649 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7650 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7651 /* nothing */
7652 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7653 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7654 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7655 val |= WDMAC_MODE_RX_ACCEL;
7656 }
7657 }
7658
d9ab5ad1 7659 /* Enable host coalescing bug fix */
321d32a0 7660 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7661 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7662
788a035e
MC		 7663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7664 val |= WDMAC_MODE_BURST_ALL_DATA;
7665
1da177e4
LT		 7666 tw32_f(WDMAC_MODE, val);
7667 udelay(40);
7668
9974a356
MC		 7669 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7670 u16 pcix_cmd;
7671
7672 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7673 &pcix_cmd);
1da177e4 7674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7675 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7676 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7677 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7678 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7679 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7680 }
9974a356
MC		 7681 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7682 pcix_cmd);
1da177e4
LT		 7683 }
7684
7685 tw32_f(RDMAC_MODE, rdmac_mode);
7686 udelay(40);
7687
7688 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7689 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7690 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7691
7692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7693 tw32(SNDDATAC_MODE,
7694 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7695 else
7696 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7697
1da177e4
LT		 7698 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7699 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7700 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7701 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7702 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7703 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7704 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7705 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7706 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7707 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7708 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7709
7710 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7711 err = tg3_load_5701_a0_firmware_fix(tp);
7712 if (err)
7713 return err;
7714 }
7715
1da177e4
LT		 7716 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7717 err = tg3_load_tso_firmware(tp);
7718 if (err)
7719 return err;
7720 }
1da177e4
LT		 7721
7722 tp->tx_mode = TX_MODE_ENABLE;
7723 tw32_f(MAC_TX_MODE, tp->tx_mode);
7724 udelay(100);
7725
baf8a94a
MC		 7726 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7727 u32 reg = MAC_RSS_INDIR_TBL_0;
7728 u8 *ent = (u8 *)&val;
7729
7730 /* Setup the indirection table */
7731 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7732 int idx = i % sizeof(val);
7733
7734 ent[idx] = i % (tp->irq_cnt - 1);
7735 if (idx == sizeof(val) - 1) {
7736 tw32(reg, val);
7737 reg += 4;
7738 }
7739 }
7740
7741 /* Setup the "secret" hash key. */
7742 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7743 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7744 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7745 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7746 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7747 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7748 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7749 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7750 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7751 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7752 }
7753
1da177e4 7754 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7755 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7756 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7757
baf8a94a
MC		 7758 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7759 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7760 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7761 RX_MODE_RSS_IPV6_HASH_EN |
7762 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7763 RX_MODE_RSS_IPV4_HASH_EN |
7764 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7765
1da177e4
LT		 7766 tw32_f(MAC_RX_MODE, tp->rx_mode);
7767 udelay(10);
7768
1da177e4
LT		 7769 tw32(MAC_LED_CTRL, tp->led_ctrl);
7770
7771 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7772 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7773 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7774 udelay(10);
7775 }
7776 tw32_f(MAC_RX_MODE, tp->rx_mode);
7777 udelay(10);
7778
7779 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7780 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7781 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7782 /* Set drive transmission level to 1.2V */
7783 /* only if the signal pre-emphasis bit is not set */
7784 val = tr32(MAC_SERDES_CFG);
7785 val &= 0xfffff000;
7786 val |= 0x880;
7787 tw32(MAC_SERDES_CFG, val);
7788 }
7789 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7790 tw32(MAC_SERDES_CFG, 0x616000);
7791 }
7792
7793 /* Prevent chip from dropping frames when flow control
7794 * is enabled.
7795 */
7796 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7797
7798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7799 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7800 /* Use hardware link auto-negotiation */
7801 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7802 }
7803
d4d2c558
MC		 7804 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7805 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7806 u32 tmp;
7807
7808 tmp = tr32(SERDES_RX_CTRL);
7809 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7810 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7811 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7812 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7813 }
7814
dd477003
MC		 7815 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7816 if (tp->link_config.phy_is_low_power) {
7817 tp->link_config.phy_is_low_power = 0;
7818 tp->link_config.speed = tp->link_config.orig_speed;
7819 tp->link_config.duplex = tp->link_config.orig_duplex;
7820 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7821 }
1da177e4 7822
dd477003
MC		 7823 err = tg3_setup_phy(tp, 0);
7824 if (err)
7825 return err;
1da177e4 7826
dd477003 7827 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7828 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7829 u32 tmp;
7830
7831 /* Clear CRC stats. */
7832 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7833 tg3_writephy(tp, MII_TG3_TEST1,
7834 tmp | MII_TG3_TEST1_CRC_EN);
7835 tg3_readphy(tp, 0x14, &tmp);
7836 }
1da177e4
LT		 7837 }
7838 }
7839
7840 __tg3_set_rx_mode(tp->dev);
7841
7842 /* Initialize receive rules. */
7843 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7844 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7845 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7846 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7847
4cf78e4f 7848 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7849 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7850 limit = 8;
7851 else
7852 limit = 16;
7853 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7854 limit -= 4;
7855 switch (limit) {
7856 case 16:
7857 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7858 case 15:
7859 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7860 case 14:
7861 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7862 case 13:
7863 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7864 case 12:
7865 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7866 case 11:
7867 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7868 case 10:
7869 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7870 case 9:
7871 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7872 case 8:
7873 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7874 case 7:
7875 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7876 case 6:
7877 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7878 case 5:
7879 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7880 case 4:
7881 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7882 case 3:
7883 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7884 case 2:
7885 case 1:
7886
7887 default:
7888 break;
855e1111 7889 }
1da177e4 7890
9ce768ea
MC		 7891 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7892 /* Write our heartbeat update interval to APE. */
7893 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7894 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7895
1da177e4
LT		 7896 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7897
1da177e4
LT		 7898 return 0;
7899}
7900
7901/* Called at device open time to get the chip ready for
7902 * packet processing. Invoked with tp->lock held.
7903 */
8e7a22e3 7904static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7905{
1da177e4
LT		 7906 tg3_switch_clocks(tp);
7907
7908 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7909
2f751b67 7910 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7911}
7912
7913#define TG3_STAT_ADD32(PSTAT, REG) \
7914do { u32 __val = tr32(REG); \
7915 (PSTAT)->low += __val; \
7916 if ((PSTAT)->low < __val) \
7917 (PSTAT)->high += 1; \
7918} while (0)
7919
7920static void tg3_periodic_fetch_stats(struct tg3 *tp)
7921{
7922 struct tg3_hw_stats *sp = tp->hw_stats;
7923
7924 if (!netif_carrier_ok(tp->dev))
7925 return;
7926
7927 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7928 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7929 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7930 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7931 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7932 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7933 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7934 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7935 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7936 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7937 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7938 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7939 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7940
7941 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7942 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7943 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7944 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7945 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7946 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7947 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7948 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7949 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7950 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7951 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7952 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7953 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7954 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7955
7956 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7957 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7958 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7959}
7960
7961static void tg3_timer(unsigned long __opaque)
7962{
7963 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7964
f475f163
MC		 7965 if (tp->irq_sync)
7966 goto restart_timer;
7967
f47c11ee 7968 spin_lock(&tp->lock);
1da177e4 7969
fac9b83e
DM		 7970 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7971 /* All of this garbage is because when using non-tagged
7972 * IRQ status the mailbox/status_block protocol the chip
7973 * uses with the cpu is race prone.
7974 */
898a56f8 7975 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7976 tw32(GRC_LOCAL_CTRL,
7977 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7978 } else {
7979 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7980 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7981 }
1da177e4 7982
fac9b83e
DM		 7983 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7984 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7985 spin_unlock(&tp->lock);
fac9b83e
DM		 7986 schedule_work(&tp->reset_task);
7987 return;
7988 }
1da177e4
LT		 7989 }
7990
1da177e4
LT		 7991 /* This part only runs once per second. */
7992 if (!--tp->timer_counter) {
fac9b83e
DM		 7993 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7994 tg3_periodic_fetch_stats(tp);
7995
1da177e4
LT		 7996 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7997 u32 mac_stat;
7998 int phy_event;
7999
8000 mac_stat = tr32(MAC_STATUS);
8001
8002 phy_event = 0;
8003 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8004 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8005 phy_event = 1;
8006 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8007 phy_event = 1;
8008
8009 if (phy_event)
8010 tg3_setup_phy(tp, 0);
8011 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8012 u32 mac_stat = tr32(MAC_STATUS);
8013 int need_setup = 0;
8014
8015 if (netif_carrier_ok(tp->dev) &&
8016 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8017 need_setup = 1;
8018 }
8019 if (! netif_carrier_ok(tp->dev) &&
8020 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8021 MAC_STATUS_SIGNAL_DET))) {
8022 need_setup = 1;
8023 }
8024 if (need_setup) {
3d3ebe74
MC		 8025 if (!tp->serdes_counter) {
8026 tw32_f(MAC_MODE,
8027 (tp->mac_mode &
8028 ~MAC_MODE_PORT_MODE_MASK));
8029 udelay(40);
8030 tw32_f(MAC_MODE, tp->mac_mode);
8031 udelay(40);
8032 }
1da177e4
LT		 8033 tg3_setup_phy(tp, 0);
8034 }
747e8f8b
MC		 8035 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8036 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8037
8038 tp->timer_counter = tp->timer_multiplier;
8039 }
8040
130b8e4d
MC		 8041 /* Heartbeat is only sent once every 2 seconds.
8042 *
8043 * The heartbeat is to tell the ASF firmware that the host
8044 * driver is still alive. In the event that the OS crashes,
8045 * ASF needs to reset the hardware to free up the FIFO space
8046 * that may be filled with rx packets destined for the host.
8047 * If the FIFO is full, ASF will no longer function properly.
8048 *
8049 * Unintended resets have been reported on real time kernels
8050 * where the timer doesn't run on time. Netpoll will also have
8051 * same problem.
8052 *
8053 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8054 * to check the ring condition when the heartbeat is expiring
8055 * before doing the reset. This will prevent most unintended
8056 * resets.
8057 */
1da177e4 8058 if (!--tp->asf_counter) {
bc7959b2
MC		 8059 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8060 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8061 tg3_wait_for_event_ack(tp);
8062
bbadf503 8063 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8064 FWCMD_NICDRV_ALIVE3);
bbadf503 8065 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8066 /* 5 seconds timeout */
bbadf503 8067 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8068
8069 tg3_generate_fw_event(tp);
1da177e4
LT		 8070 }
8071 tp->asf_counter = tp->asf_multiplier;
8072 }
8073
f47c11ee 8074 spin_unlock(&tp->lock);
1da177e4 8075
f475f163 8076restart_timer:
1da177e4
LT		 8077 tp->timer.expires = jiffies + tp->timer_offset;
8078 add_timer(&tp->timer);
8079}
8080
4f125f42 8081static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8082{
7d12e780 8083 irq_handler_t fn;
fcfa0a32 8084 unsigned long flags;
4f125f42
MC		 8085 char *name;
8086 struct tg3_napi *tnapi = &tp->napi[irq_num];
8087
8088 if (tp->irq_cnt == 1)
8089 name = tp->dev->name;
8090 else {
8091 name = &tnapi->irq_lbl[0];
8092 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8093 name[IFNAMSIZ-1] = 0;
8094 }
fcfa0a32 8095
679563f4 8096 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8097 fn = tg3_msi;
8098 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8099 fn = tg3_msi_1shot;
1fb9df5d 8100 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8101 } else {
8102 fn = tg3_interrupt;
8103 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8104 fn = tg3_interrupt_tagged;
1fb9df5d 8105 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8106 }
4f125f42
MC		 8107
8108 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8109}
8110
7938109f
MC		 8111static int tg3_test_interrupt(struct tg3 *tp)
8112{
09943a18 8113 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8114 struct net_device *dev = tp->dev;
b16250e3 8115 int err, i, intr_ok = 0;
f6eb9b1f 8116 u32 val;
7938109f 8117
d4bc3927
MC		 8118 if (!netif_running(dev))
8119 return -ENODEV;
8120
7938109f
MC		 8121 tg3_disable_ints(tp);
8122
4f125f42 8123 free_irq(tnapi->irq_vec, tnapi);
7938109f 8124
f6eb9b1f
MC		 8125 /*
8126 * Turn off MSI one shot mode. Otherwise this test has no
8127 * observable way to know whether the interrupt was delivered.
8128 */
8129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8130 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8131 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8132 tw32(MSGINT_MODE, val);
8133 }
8134
4f125f42 8135 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8136 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8137 if (err)
8138 return err;
8139
898a56f8 8140 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8141 tg3_enable_ints(tp);
8142
8143 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8144 tnapi->coal_now);
7938109f
MC		 8145
8146 for (i = 0; i < 5; i++) {
b16250e3
MC		 8147 u32 int_mbox, misc_host_ctrl;
8148
898a56f8 8149 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8150 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8151
8152 if ((int_mbox != 0) ||
8153 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8154 intr_ok = 1;
7938109f 8155 break;
b16250e3
MC		 8156 }
8157
7938109f
MC		 8158 msleep(10);
8159 }
8160
8161 tg3_disable_ints(tp);
8162
4f125f42 8163 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8164
4f125f42 8165 err = tg3_request_irq(tp, 0);
7938109f
MC		 8166
8167 if (err)
8168 return err;
8169
f6eb9b1f
MC		 8170 if (intr_ok) {
8171 /* Reenable MSI one shot mode. */
8172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8173 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8174 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8175 tw32(MSGINT_MODE, val);
8176 }
7938109f 8177 return 0;
f6eb9b1f 8178 }
7938109f
MC		 8179
8180 return -EIO;
8181}
8182
8183/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8184 * successfully restored
8185 */
8186static int tg3_test_msi(struct tg3 *tp)
8187{
7938109f
MC		 8188 int err;
8189 u16 pci_cmd;
8190
8191 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8192 return 0;
8193
8194 /* Turn off SERR reporting in case MSI terminates with Master
8195 * Abort.
8196 */
8197 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8198 pci_write_config_word(tp->pdev, PCI_COMMAND,
8199 pci_cmd & ~PCI_COMMAND_SERR);
8200
8201 err = tg3_test_interrupt(tp);
8202
8203 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8204
8205 if (!err)
8206 return 0;
8207
8208 /* other failures */
8209 if (err != -EIO)
8210 return err;
8211
8212 /* MSI test failed, go back to INTx mode */
8213 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8214 "switching to INTx mode. Please report this failure to "
8215 "the PCI maintainer and include system chipset information.\n",
8216 tp->dev->name);
8217
4f125f42 8218 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8219
7938109f
MC		 8220 pci_disable_msi(tp->pdev);
8221
8222 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8223
4f125f42 8224 err = tg3_request_irq(tp, 0);
7938109f
MC		 8225 if (err)
8226 return err;
8227
8228 /* Need to reset the chip because the MSI cycle may have terminated
8229 * with Master Abort.
8230 */
f47c11ee 8231 tg3_full_lock(tp, 1);
7938109f 8232
944d980e 8233 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8234 err = tg3_init_hw(tp, 1);
7938109f 8235
f47c11ee 8236 tg3_full_unlock(tp);
7938109f
MC		 8237
8238 if (err)
4f125f42 8239 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8240
8241 return err;
8242}
8243
9e9fd12d
MC		 8244static int tg3_request_firmware(struct tg3 *tp)
8245{
8246 const __be32 *fw_data;
8247
8248 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8249 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8250 tp->dev->name, tp->fw_needed);
8251 return -ENOENT;
8252 }
8253
8254 fw_data = (void *)tp->fw->data;
8255
8256 /* Firmware blob starts with version numbers, followed by
8257 * start address and _full_ length including BSS sections
8258 * (which must be longer than the actual data, of course
8259 */
8260
8261 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8262 if (tp->fw_len < (tp->fw->size - 12)) {
8263 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8264 tp->dev->name, tp->fw_len, tp->fw_needed);
8265 release_firmware(tp->fw);
8266 tp->fw = NULL;
8267 return -EINVAL;
8268 }
8269
8270 /* We no longer need firmware; we have it. */
8271 tp->fw_needed = NULL;
8272 return 0;
8273}
8274
679563f4
MC		 8275static bool tg3_enable_msix(struct tg3 *tp)
8276{
8277 int i, rc, cpus = num_online_cpus();
8278 struct msix_entry msix_ent[tp->irq_max];
8279
8280 if (cpus == 1)
8281 /* Just fallback to the simpler MSI mode. */
8282 return false;
8283
8284 /*
8285 * We want as many rx rings enabled as there are cpus.
8286 * The first MSIX vector only deals with link interrupts, etc,
8287 * so we add one to the number of vectors we are requesting.
8288 */
8289 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8290
8291 for (i = 0; i < tp->irq_max; i++) {
8292 msix_ent[i].entry = i;
8293 msix_ent[i].vector = 0;
8294 }
8295
8296 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8297 if (rc != 0) {
8298 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8299 return false;
8300 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8301 return false;
8302 printk(KERN_NOTICE
8303 "%s: Requested %d MSI-X vectors, received %d\n",
8304 tp->dev->name, tp->irq_cnt, rc);
8305 tp->irq_cnt = rc;
8306 }
8307
baf8a94a
MC		 8308 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8309
679563f4
MC		 8310 for (i = 0; i < tp->irq_max; i++)
8311 tp->napi[i].irq_vec = msix_ent[i].vector;
8312
fe5f5787
MC		 8313 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8314
679563f4
MC		 8315 return true;
8316}
8317
07b0173c
MC		 8318static void tg3_ints_init(struct tg3 *tp)
8319{
679563f4
MC		 8320 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8321 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8322 /* All MSI supporting chips should support tagged
8323 * status. Assert that this is the case.
8324 */
679563f4
MC		 8325 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8326 "Not using MSI.\n", tp->dev->name);
8327 goto defcfg;
07b0173c 8328 }
4f125f42 8329
679563f4
MC		 8330 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8331 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8332 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8333 pci_enable_msi(tp->pdev) == 0)
8334 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8335
8336 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8337 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8338 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8339 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8340 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8341 }
8342defcfg:
8343 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8344 tp->irq_cnt = 1;
8345 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8346 tp->dev->real_num_tx_queues = 1;
679563f4 8347 }
07b0173c
MC		 8348}
8349
8350static void tg3_ints_fini(struct tg3 *tp)
8351{
679563f4
MC		 8352 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8353 pci_disable_msix(tp->pdev);
8354 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8355 pci_disable_msi(tp->pdev);
8356 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8357 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8358}
8359
1da177e4
LT		 8360static int tg3_open(struct net_device *dev)
8361{
8362 struct tg3 *tp = netdev_priv(dev);
4f125f42 8363 int i, err;
1da177e4 8364
9e9fd12d
MC		 8365 if (tp->fw_needed) {
8366 err = tg3_request_firmware(tp);
8367 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8368 if (err)
8369 return err;
8370 } else if (err) {
8371 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8372 tp->dev->name);
8373 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8374 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8375 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8376 tp->dev->name);
8377 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8378 }
8379 }
8380
c49a1561
MC		 8381 netif_carrier_off(tp->dev);
8382
bc1c7567 8383 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8384 if (err)
bc1c7567 8385 return err;
2f751b67
MC		 8386
8387 tg3_full_lock(tp, 0);
bc1c7567 8388
1da177e4
LT		 8389 tg3_disable_ints(tp);
8390 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8391
f47c11ee 8392 tg3_full_unlock(tp);
1da177e4 8393
679563f4
MC		 8394 /*
8395 * Setup interrupts first so we know how
8396 * many NAPI resources to allocate
8397 */
8398 tg3_ints_init(tp);
8399
1da177e4
LT		 8400 /* The placement of this call is tied
8401 * to the setup and use of Host TX descriptors.
8402 */
8403 err = tg3_alloc_consistent(tp);
8404 if (err)
679563f4 8405 goto err_out1;
88b06bc2 8406
fed97810 8407 tg3_napi_enable(tp);
1da177e4 8408
4f125f42
MC		 8409 for (i = 0; i < tp->irq_cnt; i++) {
8410 struct tg3_napi *tnapi = &tp->napi[i];
8411 err = tg3_request_irq(tp, i);
8412 if (err) {
8413 for (i--; i >= 0; i--)
8414 free_irq(tnapi->irq_vec, tnapi);
8415 break;
8416 }
8417 }
1da177e4 8418
07b0173c 8419 if (err)
679563f4 8420 goto err_out2;
bea3348e 8421
f47c11ee 8422 tg3_full_lock(tp, 0);
1da177e4 8423
8e7a22e3 8424 err = tg3_init_hw(tp, 1);
1da177e4 8425 if (err) {
944d980e 8426 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8427 tg3_free_rings(tp);
8428 } else {
fac9b83e
DM		 8429 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8430 tp->timer_offset = HZ;
8431 else
8432 tp->timer_offset = HZ / 10;
8433
8434 BUG_ON(tp->timer_offset > HZ);
8435 tp->timer_counter = tp->timer_multiplier =
8436 (HZ / tp->timer_offset);
8437 tp->asf_counter = tp->asf_multiplier =
28fbef78 8438 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8439
8440 init_timer(&tp->timer);
8441 tp->timer.expires = jiffies + tp->timer_offset;
8442 tp->timer.data = (unsigned long) tp;
8443 tp->timer.function = tg3_timer;
1da177e4
LT		 8444 }
8445
f47c11ee 8446 tg3_full_unlock(tp);
1da177e4 8447
07b0173c 8448 if (err)
679563f4 8449 goto err_out3;
1da177e4 8450
7938109f
MC		 8451 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8452 err = tg3_test_msi(tp);
fac9b83e 8453
7938109f 8454 if (err) {
f47c11ee 8455 tg3_full_lock(tp, 0);
944d980e 8456 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8457 tg3_free_rings(tp);
f47c11ee 8458 tg3_full_unlock(tp);
7938109f 8459
679563f4 8460 goto err_out2;
7938109f 8461 }
fcfa0a32 8462
f6eb9b1f
MC		 8463 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8464 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8465 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8466 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8467
f6eb9b1f
MC		 8468 tw32(PCIE_TRANSACTION_CFG,
8469 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8470 }
7938109f
MC		 8471 }
8472
b02fd9e3
MC		 8473 tg3_phy_start(tp);
8474
f47c11ee 8475 tg3_full_lock(tp, 0);
1da177e4 8476
7938109f
MC		 8477 add_timer(&tp->timer);
8478 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8479 tg3_enable_ints(tp);
8480
f47c11ee 8481 tg3_full_unlock(tp);
1da177e4 8482
fe5f5787 8483 netif_tx_start_all_queues(dev);
1da177e4
LT		 8484
8485 return 0;
07b0173c 8486
679563f4 8487err_out3:
4f125f42
MC		 8488 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8489 struct tg3_napi *tnapi = &tp->napi[i];
8490 free_irq(tnapi->irq_vec, tnapi);
8491 }
07b0173c 8492
679563f4 8493err_out2:
fed97810 8494 tg3_napi_disable(tp);
07b0173c 8495 tg3_free_consistent(tp);
679563f4
MC		 8496
8497err_out1:
8498 tg3_ints_fini(tp);
07b0173c 8499 return err;
1da177e4
LT		 8500}
8501
8502#if 0
8503/*static*/ void tg3_dump_state(struct tg3 *tp)
8504{
8505 u32 val32, val32_2, val32_3, val32_4, val32_5;
8506 u16 val16;
8507 int i;
898a56f8 8508 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8509
8510 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8511 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8512 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8513 val16, val32);
8514
8515 /* MAC block */
8516 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8517 tr32(MAC_MODE), tr32(MAC_STATUS));
8518 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8519 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8520 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8521 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8522 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8523 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8524
8525 /* Send data initiator control block */
8526 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8527 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8528 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8529 tr32(SNDDATAI_STATSCTRL));
8530
8531 /* Send data completion control block */
8532 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8533
8534 /* Send BD ring selector block */
8535 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8536 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8537
8538 /* Send BD initiator control block */
8539 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8540 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8541
8542 /* Send BD completion control block */
8543 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8544
8545 /* Receive list placement control block */
8546 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8547 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8548 printk(" RCVLPC_STATSCTRL[%08x]\n",
8549 tr32(RCVLPC_STATSCTRL));
8550
8551 /* Receive data and receive BD initiator control block */
8552 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8553 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8554
8555 /* Receive data completion control block */
8556 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8557 tr32(RCVDCC_MODE));
8558
8559 /* Receive BD initiator control block */
8560 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8561 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8562
8563 /* Receive BD completion control block */
8564 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8565 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8566
8567 /* Receive list selector control block */
8568 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8569 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8570
8571 /* Mbuf cluster free block */
8572 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8573 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8574
8575 /* Host coalescing control block */
8576 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8577 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8578 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8579 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8580 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8581 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8582 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8583 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8584 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8585 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8586 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8587 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8588
8589 /* Memory arbiter control block */
8590 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8591 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8592
8593 /* Buffer manager control block */
8594 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8595 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8596 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8597 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8598 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8599 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8600 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8601 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8602
8603 /* Read DMA control block */
8604 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8605 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8606
8607 /* Write DMA control block */
8608 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8609 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8610
8611 /* DMA completion block */
8612 printk("DEBUG: DMAC_MODE[%08x]\n",
8613 tr32(DMAC_MODE));
8614
8615 /* GRC block */
8616 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8617 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8618 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8619 tr32(GRC_LOCAL_CTRL));
8620
8621 /* TG3_BDINFOs */
8622 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8623 tr32(RCVDBDI_JUMBO_BD + 0x0),
8624 tr32(RCVDBDI_JUMBO_BD + 0x4),
8625 tr32(RCVDBDI_JUMBO_BD + 0x8),
8626 tr32(RCVDBDI_JUMBO_BD + 0xc));
8627 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8628 tr32(RCVDBDI_STD_BD + 0x0),
8629 tr32(RCVDBDI_STD_BD + 0x4),
8630 tr32(RCVDBDI_STD_BD + 0x8),
8631 tr32(RCVDBDI_STD_BD + 0xc));
8632 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8633 tr32(RCVDBDI_MINI_BD + 0x0),
8634 tr32(RCVDBDI_MINI_BD + 0x4),
8635 tr32(RCVDBDI_MINI_BD + 0x8),
8636 tr32(RCVDBDI_MINI_BD + 0xc));
8637
8638 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8639 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8640 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8641 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8642 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8643 val32, val32_2, val32_3, val32_4);
8644
8645 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8646 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8647 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8648 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8649 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8650 val32, val32_2, val32_3, val32_4);
8651
8652 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8653 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8654 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8655 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8656 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8657 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8658 val32, val32_2, val32_3, val32_4, val32_5);
8659
8660 /* SW status block */
898a56f8
MC		 8661 printk(KERN_DEBUG
8662 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8663 sblk->status,
8664 sblk->status_tag,
8665 sblk->rx_jumbo_consumer,
8666 sblk->rx_consumer,
8667 sblk->rx_mini_consumer,
8668 sblk->idx[0].rx_producer,
8669 sblk->idx[0].tx_consumer);
1da177e4
LT		 8670
8671 /* SW statistics block */
8672 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8673 ((u32 *)tp->hw_stats)[0],
8674 ((u32 *)tp->hw_stats)[1],
8675 ((u32 *)tp->hw_stats)[2],
8676 ((u32 *)tp->hw_stats)[3]);
8677
8678 /* Mailboxes */
8679 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8680 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8681 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8682 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8683 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8684
8685 /* NIC side send descriptors. */
8686 for (i = 0; i < 6; i++) {
8687 unsigned long txd;
8688
8689 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8690 + (i * sizeof(struct tg3_tx_buffer_desc));
8691 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8692 i,
8693 readl(txd + 0x0), readl(txd + 0x4),
8694 readl(txd + 0x8), readl(txd + 0xc));
8695 }
8696
8697 /* NIC side RX descriptors. */
8698 for (i = 0; i < 6; i++) {
8699 unsigned long rxd;
8700
8701 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8702 + (i * sizeof(struct tg3_rx_buffer_desc));
8703 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8704 i,
8705 readl(rxd + 0x0), readl(rxd + 0x4),
8706 readl(rxd + 0x8), readl(rxd + 0xc));
8707 rxd += (4 * sizeof(u32));
8708 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8709 i,
8710 readl(rxd + 0x0), readl(rxd + 0x4),
8711 readl(rxd + 0x8), readl(rxd + 0xc));
8712 }
8713
8714 for (i = 0; i < 6; i++) {
8715 unsigned long rxd;
8716
8717 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8718 + (i * sizeof(struct tg3_rx_buffer_desc));
8719 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8720 i,
8721 readl(rxd + 0x0), readl(rxd + 0x4),
8722 readl(rxd + 0x8), readl(rxd + 0xc));
8723 rxd += (4 * sizeof(u32));
8724 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8725 i,
8726 readl(rxd + 0x0), readl(rxd + 0x4),
8727 readl(rxd + 0x8), readl(rxd + 0xc));
8728 }
8729}
8730#endif
8731
8732static struct net_device_stats *tg3_get_stats(struct net_device *);
8733static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8734
8735static int tg3_close(struct net_device *dev)
8736{
4f125f42 8737 int i;
1da177e4
LT		 8738 struct tg3 *tp = netdev_priv(dev);
8739
fed97810 8740 tg3_napi_disable(tp);
28e53bdd 8741 cancel_work_sync(&tp->reset_task);
7faa006f 8742
fe5f5787 8743 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8744
8745 del_timer_sync(&tp->timer);
8746
24bb4fb6
MC		 8747 tg3_phy_stop(tp);
8748
f47c11ee 8749 tg3_full_lock(tp, 1);
1da177e4
LT		 8750#if 0
8751 tg3_dump_state(tp);
8752#endif
8753
8754 tg3_disable_ints(tp);
8755
944d980e 8756 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8757 tg3_free_rings(tp);
5cf64b8a 8758 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8759
f47c11ee 8760 tg3_full_unlock(tp);
1da177e4 8761
4f125f42
MC		 8762 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8763 struct tg3_napi *tnapi = &tp->napi[i];
8764 free_irq(tnapi->irq_vec, tnapi);
8765 }
07b0173c
MC		 8766
8767 tg3_ints_fini(tp);
1da177e4
LT		 8768
8769 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8770 sizeof(tp->net_stats_prev));
8771 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8772 sizeof(tp->estats_prev));
8773
8774 tg3_free_consistent(tp);
8775
bc1c7567
MC		 8776 tg3_set_power_state(tp, PCI_D3hot);
8777
8778 netif_carrier_off(tp->dev);
8779
1da177e4
LT		 8780 return 0;
8781}
8782
8783static inline unsigned long get_stat64(tg3_stat64_t *val)
8784{
8785 unsigned long ret;
8786
8787#if (BITS_PER_LONG == 32)
8788 ret = val->low;
8789#else
8790 ret = ((u64)val->high << 32) | ((u64)val->low);
8791#endif
8792 return ret;
8793}
8794
816f8b86
SB		 8795static inline u64 get_estat64(tg3_stat64_t *val)
8796{
8797 return ((u64)val->high << 32) | ((u64)val->low);
8798}
8799
1da177e4
LT		 8800static unsigned long calc_crc_errors(struct tg3 *tp)
8801{
8802 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8803
8804 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8805 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8807 u32 val;
8808
f47c11ee 8809 spin_lock_bh(&tp->lock);
569a5df8
MC		 8810 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8811 tg3_writephy(tp, MII_TG3_TEST1,
8812 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8813 tg3_readphy(tp, 0x14, &val);
8814 } else
8815 val = 0;
f47c11ee 8816 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8817
8818 tp->phy_crc_errors += val;
8819
8820 return tp->phy_crc_errors;
8821 }
8822
8823 return get_stat64(&hw_stats->rx_fcs_errors);
8824}
8825
8826#define ESTAT_ADD(member) \
8827 estats->member = old_estats->member + \
816f8b86 8828 get_estat64(&hw_stats->member)
1da177e4
LT		 8829
8830static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8831{
8832 struct tg3_ethtool_stats *estats = &tp->estats;
8833 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8834 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8835
8836 if (!hw_stats)
8837 return old_estats;
8838
8839 ESTAT_ADD(rx_octets);
8840 ESTAT_ADD(rx_fragments);
8841 ESTAT_ADD(rx_ucast_packets);
8842 ESTAT_ADD(rx_mcast_packets);
8843 ESTAT_ADD(rx_bcast_packets);
8844 ESTAT_ADD(rx_fcs_errors);
8845 ESTAT_ADD(rx_align_errors);
8846 ESTAT_ADD(rx_xon_pause_rcvd);
8847 ESTAT_ADD(rx_xoff_pause_rcvd);
8848 ESTAT_ADD(rx_mac_ctrl_rcvd);
8849 ESTAT_ADD(rx_xoff_entered);
8850 ESTAT_ADD(rx_frame_too_long_errors);
8851 ESTAT_ADD(rx_jabbers);
8852 ESTAT_ADD(rx_undersize_packets);
8853 ESTAT_ADD(rx_in_length_errors);
8854 ESTAT_ADD(rx_out_length_errors);
8855 ESTAT_ADD(rx_64_or_less_octet_packets);
8856 ESTAT_ADD(rx_65_to_127_octet_packets);
8857 ESTAT_ADD(rx_128_to_255_octet_packets);
8858 ESTAT_ADD(rx_256_to_511_octet_packets);
8859 ESTAT_ADD(rx_512_to_1023_octet_packets);
8860 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8861 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8862 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8863 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8864 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8865
8866 ESTAT_ADD(tx_octets);
8867 ESTAT_ADD(tx_collisions);
8868 ESTAT_ADD(tx_xon_sent);
8869 ESTAT_ADD(tx_xoff_sent);
8870 ESTAT_ADD(tx_flow_control);
8871 ESTAT_ADD(tx_mac_errors);
8872 ESTAT_ADD(tx_single_collisions);
8873 ESTAT_ADD(tx_mult_collisions);
8874 ESTAT_ADD(tx_deferred);
8875 ESTAT_ADD(tx_excessive_collisions);
8876 ESTAT_ADD(tx_late_collisions);
8877 ESTAT_ADD(tx_collide_2times);
8878 ESTAT_ADD(tx_collide_3times);
8879 ESTAT_ADD(tx_collide_4times);
8880 ESTAT_ADD(tx_collide_5times);
8881 ESTAT_ADD(tx_collide_6times);
8882 ESTAT_ADD(tx_collide_7times);
8883 ESTAT_ADD(tx_collide_8times);
8884 ESTAT_ADD(tx_collide_9times);
8885 ESTAT_ADD(tx_collide_10times);
8886 ESTAT_ADD(tx_collide_11times);
8887 ESTAT_ADD(tx_collide_12times);
8888 ESTAT_ADD(tx_collide_13times);
8889 ESTAT_ADD(tx_collide_14times);
8890 ESTAT_ADD(tx_collide_15times);
8891 ESTAT_ADD(tx_ucast_packets);
8892 ESTAT_ADD(tx_mcast_packets);
8893 ESTAT_ADD(tx_bcast_packets);
8894 ESTAT_ADD(tx_carrier_sense_errors);
8895 ESTAT_ADD(tx_discards);
8896 ESTAT_ADD(tx_errors);
8897
8898 ESTAT_ADD(dma_writeq_full);
8899 ESTAT_ADD(dma_write_prioq_full);
8900 ESTAT_ADD(rxbds_empty);
8901 ESTAT_ADD(rx_discards);
8902 ESTAT_ADD(rx_errors);
8903 ESTAT_ADD(rx_threshold_hit);
8904
8905 ESTAT_ADD(dma_readq_full);
8906 ESTAT_ADD(dma_read_prioq_full);
8907 ESTAT_ADD(tx_comp_queue_full);
8908
8909 ESTAT_ADD(ring_set_send_prod_index);
8910 ESTAT_ADD(ring_status_update);
8911 ESTAT_ADD(nic_irqs);
8912 ESTAT_ADD(nic_avoided_irqs);
8913 ESTAT_ADD(nic_tx_threshold_hit);
8914
8915 return estats;
8916}
8917
8918static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8919{
8920 struct tg3 *tp = netdev_priv(dev);
8921 struct net_device_stats *stats = &tp->net_stats;
8922 struct net_device_stats *old_stats = &tp->net_stats_prev;
8923 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8924
8925 if (!hw_stats)
8926 return old_stats;
8927
8928 stats->rx_packets = old_stats->rx_packets +
8929 get_stat64(&hw_stats->rx_ucast_packets) +
8930 get_stat64(&hw_stats->rx_mcast_packets) +
8931 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8932
1da177e4
LT		 8933 stats->tx_packets = old_stats->tx_packets +
8934 get_stat64(&hw_stats->tx_ucast_packets) +
8935 get_stat64(&hw_stats->tx_mcast_packets) +
8936 get_stat64(&hw_stats->tx_bcast_packets);
8937
8938 stats->rx_bytes = old_stats->rx_bytes +
8939 get_stat64(&hw_stats->rx_octets);
8940 stats->tx_bytes = old_stats->tx_bytes +
8941 get_stat64(&hw_stats->tx_octets);
8942
8943 stats->rx_errors = old_stats->rx_errors +
4f63b877 8944 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8945 stats->tx_errors = old_stats->tx_errors +
8946 get_stat64(&hw_stats->tx_errors) +
8947 get_stat64(&hw_stats->tx_mac_errors) +
8948 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8949 get_stat64(&hw_stats->tx_discards);
8950
8951 stats->multicast = old_stats->multicast +
8952 get_stat64(&hw_stats->rx_mcast_packets);
8953 stats->collisions = old_stats->collisions +
8954 get_stat64(&hw_stats->tx_collisions);
8955
8956 stats->rx_length_errors = old_stats->rx_length_errors +
8957 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8958 get_stat64(&hw_stats->rx_undersize_packets);
8959
8960 stats->rx_over_errors = old_stats->rx_over_errors +
8961 get_stat64(&hw_stats->rxbds_empty);
8962 stats->rx_frame_errors = old_stats->rx_frame_errors +
8963 get_stat64(&hw_stats->rx_align_errors);
8964 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8965 get_stat64(&hw_stats->tx_discards);
8966 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8967 get_stat64(&hw_stats->tx_carrier_sense_errors);
8968
8969 stats->rx_crc_errors = old_stats->rx_crc_errors +
8970 calc_crc_errors(tp);
8971
4f63b877
JL		 8972 stats->rx_missed_errors = old_stats->rx_missed_errors +
8973 get_stat64(&hw_stats->rx_discards);
8974
1da177e4
LT		 8975 return stats;
8976}
8977
8978static inline u32 calc_crc(unsigned char *buf, int len)
8979{
8980 u32 reg;
8981 u32 tmp;
8982 int j, k;
8983
8984 reg = 0xffffffff;
8985
8986 for (j = 0; j < len; j++) {
8987 reg ^= buf[j];
8988
8989 for (k = 0; k < 8; k++) {
8990 tmp = reg & 0x01;
8991
8992 reg >>= 1;
8993
8994 if (tmp) {
8995 reg ^= 0xedb88320;
8996 }
8997 }
8998 }
8999
9000 return ~reg;
9001}
9002
9003static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9004{
9005 /* accept or reject all multicast frames */
9006 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9007 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9008 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9009 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9010}
9011
9012static void __tg3_set_rx_mode(struct net_device *dev)
9013{
9014 struct tg3 *tp = netdev_priv(dev);
9015 u32 rx_mode;
9016
9017 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9018 RX_MODE_KEEP_VLAN_TAG);
9019
9020 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9021 * flag clear.
9022 */
9023#if TG3_VLAN_TAG_USED
9024 if (!tp->vlgrp &&
9025 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9026 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9027#else
9028 /* By definition, VLAN is disabled always in this
9029 * case.
9030 */
9031 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9032 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9033#endif
9034
9035 if (dev->flags & IFF_PROMISC) {
9036 /* Promiscuous mode. */
9037 rx_mode |= RX_MODE_PROMISC;
9038 } else if (dev->flags & IFF_ALLMULTI) {
9039 /* Accept all multicast. */
9040 tg3_set_multi (tp, 1);
9041 } else if (dev->mc_count < 1) {
9042 /* Reject all multicast. */
9043 tg3_set_multi (tp, 0);
9044 } else {
9045 /* Accept one or more multicast(s). */
9046 struct dev_mc_list *mclist;
9047 unsigned int i;
9048 u32 mc_filter[4] = { 0, };
9049 u32 regidx;
9050 u32 bit;
9051 u32 crc;
9052
9053 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9054 i++, mclist = mclist->next) {
9055
9056 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9057 bit = ~crc & 0x7f;
9058 regidx = (bit & 0x60) >> 5;
9059 bit &= 0x1f;
9060 mc_filter[regidx] |= (1 << bit);
9061 }
9062
9063 tw32(MAC_HASH_REG_0, mc_filter[0]);
9064 tw32(MAC_HASH_REG_1, mc_filter[1]);
9065 tw32(MAC_HASH_REG_2, mc_filter[2]);
9066 tw32(MAC_HASH_REG_3, mc_filter[3]);
9067 }
9068
9069 if (rx_mode != tp->rx_mode) {
9070 tp->rx_mode = rx_mode;
9071 tw32_f(MAC_RX_MODE, rx_mode);
9072 udelay(10);
9073 }
9074}
9075
9076static void tg3_set_rx_mode(struct net_device *dev)
9077{
9078 struct tg3 *tp = netdev_priv(dev);
9079
e75f7c90
MC		 9080 if (!netif_running(dev))
9081 return;
9082
f47c11ee 9083 tg3_full_lock(tp, 0);
1da177e4 9084 __tg3_set_rx_mode(dev);
f47c11ee 9085 tg3_full_unlock(tp);
1da177e4
LT		 9086}
9087
9088#define TG3_REGDUMP_LEN (32 * 1024)
9089
9090static int tg3_get_regs_len(struct net_device *dev)
9091{
9092 return TG3_REGDUMP_LEN;
9093}
9094
9095static void tg3_get_regs(struct net_device *dev,
9096 struct ethtool_regs *regs, void *_p)
9097{
9098 u32 *p = _p;
9099 struct tg3 *tp = netdev_priv(dev);
9100 u8 *orig_p = _p;
9101 int i;
9102
9103 regs->version = 0;
9104
9105 memset(p, 0, TG3_REGDUMP_LEN);
9106
bc1c7567
MC		 9107 if (tp->link_config.phy_is_low_power)
9108 return;
9109
f47c11ee 9110 tg3_full_lock(tp, 0);
1da177e4
LT		 9111
9112#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9113#define GET_REG32_LOOP(base,len) \
9114do { p = (u32 *)(orig_p + (base)); \
9115 for (i = 0; i < len; i += 4) \
9116 __GET_REG32((base) + i); \
9117} while (0)
9118#define GET_REG32_1(reg) \
9119do { p = (u32 *)(orig_p + (reg)); \
9120 __GET_REG32((reg)); \
9121} while (0)
9122
9123 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9124 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9125 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9126 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9127 GET_REG32_1(SNDDATAC_MODE);
9128 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9129 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9130 GET_REG32_1(SNDBDC_MODE);
9131 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9132 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9133 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9134 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9135 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9136 GET_REG32_1(RCVDCC_MODE);
9137 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9138 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9139 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9140 GET_REG32_1(MBFREE_MODE);
9141 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9142 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9143 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9144 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9145 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9146 GET_REG32_1(RX_CPU_MODE);
9147 GET_REG32_1(RX_CPU_STATE);
9148 GET_REG32_1(RX_CPU_PGMCTR);
9149 GET_REG32_1(RX_CPU_HWBKPT);
9150 GET_REG32_1(TX_CPU_MODE);
9151 GET_REG32_1(TX_CPU_STATE);
9152 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9153 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9154 GET_REG32_LOOP(FTQ_RESET, 0x120);
9155 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9156 GET_REG32_1(DMAC_MODE);
9157 GET_REG32_LOOP(GRC_MODE, 0x4c);
9158 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9159 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9160
9161#undef __GET_REG32
9162#undef GET_REG32_LOOP
9163#undef GET_REG32_1
9164
f47c11ee 9165 tg3_full_unlock(tp);
1da177e4
LT		 9166}
9167
9168static int tg3_get_eeprom_len(struct net_device *dev)
9169{
9170 struct tg3 *tp = netdev_priv(dev);
9171
9172 return tp->nvram_size;
9173}
9174
1da177e4
LT		 9175static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9176{
9177 struct tg3 *tp = netdev_priv(dev);
9178 int ret;
9179 u8 *pd;
b9fc7dc5 9180 u32 i, offset, len, b_offset, b_count;
a9dc529d 9181 __be32 val;
1da177e4 9182
df259d8c
MC		 9183 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9184 return -EINVAL;
9185
bc1c7567
MC		 9186 if (tp->link_config.phy_is_low_power)
9187 return -EAGAIN;
9188
1da177e4
LT		 9189 offset = eeprom->offset;
9190 len = eeprom->len;
9191 eeprom->len = 0;
9192
9193 eeprom->magic = TG3_EEPROM_MAGIC;
9194
9195 if (offset & 3) {
9196 /* adjustments to start on required 4 byte boundary */
9197 b_offset = offset & 3;
9198 b_count = 4 - b_offset;
9199 if (b_count > len) {
9200 /* i.e. offset=1 len=2 */
9201 b_count = len;
9202 }
a9dc529d 9203 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9204 if (ret)
9205 return ret;
1da177e4
LT		 9206 memcpy(data, ((char*)&val) + b_offset, b_count);
9207 len -= b_count;
9208 offset += b_count;
9209 eeprom->len += b_count;
9210 }
9211
9212 /* read bytes upto the last 4 byte boundary */
9213 pd = &data[eeprom->len];
9214 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9215 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9216 if (ret) {
9217 eeprom->len += i;
9218 return ret;
9219 }
1da177e4
LT		 9220 memcpy(pd + i, &val, 4);
9221 }
9222 eeprom->len += i;
9223
9224 if (len & 3) {
9225 /* read last bytes not ending on 4 byte boundary */
9226 pd = &data[eeprom->len];
9227 b_count = len & 3;
9228 b_offset = offset + len - b_count;
a9dc529d 9229 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9230 if (ret)
9231 return ret;
b9fc7dc5 9232 memcpy(pd, &val, b_count);
1da177e4
LT		 9233 eeprom->len += b_count;
9234 }
9235 return 0;
9236}
9237
6aa20a22 9238static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9239
9240static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9241{
9242 struct tg3 *tp = netdev_priv(dev);
9243 int ret;
b9fc7dc5 9244 u32 offset, len, b_offset, odd_len;
1da177e4 9245 u8 *buf;
a9dc529d 9246 __be32 start, end;
1da177e4 9247
bc1c7567
MC		 9248 if (tp->link_config.phy_is_low_power)
9249 return -EAGAIN;
9250
df259d8c
MC		 9251 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9252 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9253 return -EINVAL;
9254
9255 offset = eeprom->offset;
9256 len = eeprom->len;
9257
9258 if ((b_offset = (offset & 3))) {
9259 /* adjustments to start on required 4 byte boundary */
a9dc529d 9260 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9261 if (ret)
9262 return ret;
1da177e4
LT		 9263 len += b_offset;
9264 offset &= ~3;
1c8594b4
MC		 9265 if (len < 4)
9266 len = 4;
1da177e4
LT		 9267 }
9268
9269 odd_len = 0;
1c8594b4 9270 if (len & 3) {
1da177e4
LT		 9271 /* adjustments to end on required 4 byte boundary */
9272 odd_len = 1;
9273 len = (len + 3) & ~3;
a9dc529d 9274 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9275 if (ret)
9276 return ret;
1da177e4
LT		 9277 }
9278
9279 buf = data;
9280 if (b_offset || odd_len) {
9281 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9282 if (!buf)
1da177e4
LT		 9283 return -ENOMEM;
9284 if (b_offset)
9285 memcpy(buf, &start, 4);
9286 if (odd_len)
9287 memcpy(buf+len-4, &end, 4);
9288 memcpy(buf + b_offset, data, eeprom->len);
9289 }
9290
9291 ret = tg3_nvram_write_block(tp, offset, len, buf);
9292
9293 if (buf != data)
9294 kfree(buf);
9295
9296 return ret;
9297}
9298
9299static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9300{
b02fd9e3
MC		 9301 struct tg3 *tp = netdev_priv(dev);
9302
9303 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9304 struct phy_device *phydev;
b02fd9e3
MC		 9305 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9306 return -EAGAIN;
3f0e3ad7
MC		 9307 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9308 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9309 }
6aa20a22 9310
1da177e4
LT		 9311 cmd->supported = (SUPPORTED_Autoneg);
9312
9313 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9314 cmd->supported |= (SUPPORTED_1000baseT_Half |
9315 SUPPORTED_1000baseT_Full);
9316
ef348144 9317 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9318 cmd->supported |= (SUPPORTED_100baseT_Half |
9319 SUPPORTED_100baseT_Full |
9320 SUPPORTED_10baseT_Half |
9321 SUPPORTED_10baseT_Full |
3bebab59 9322 SUPPORTED_TP);
ef348144
KK		 9323 cmd->port = PORT_TP;
9324 } else {
1da177e4 9325 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9326 cmd->port = PORT_FIBRE;
9327 }
6aa20a22 9328
1da177e4
LT		 9329 cmd->advertising = tp->link_config.advertising;
9330 if (netif_running(dev)) {
9331 cmd->speed = tp->link_config.active_speed;
9332 cmd->duplex = tp->link_config.active_duplex;
9333 }
882e9793 9334 cmd->phy_address = tp->phy_addr;
7e5856bd 9335 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9336 cmd->autoneg = tp->link_config.autoneg;
9337 cmd->maxtxpkt = 0;
9338 cmd->maxrxpkt = 0;
9339 return 0;
9340}
6aa20a22 9341
1da177e4
LT		 9342static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9343{
9344 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9345
b02fd9e3 9346 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9347 struct phy_device *phydev;
b02fd9e3
MC		 9348 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9349 return -EAGAIN;
3f0e3ad7
MC		 9350 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9351 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9352 }
9353
7e5856bd
MC		 9354 if (cmd->autoneg != AUTONEG_ENABLE &&
9355 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9356 return -EINVAL;
7e5856bd
MC		 9357
9358 if (cmd->autoneg == AUTONEG_DISABLE &&
9359 cmd->duplex != DUPLEX_FULL &&
9360 cmd->duplex != DUPLEX_HALF)
37ff238d 9361 return -EINVAL;
1da177e4 9362
7e5856bd
MC		 9363 if (cmd->autoneg == AUTONEG_ENABLE) {
9364 u32 mask = ADVERTISED_Autoneg |
9365 ADVERTISED_Pause |
9366 ADVERTISED_Asym_Pause;
9367
9368 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9369 mask |= ADVERTISED_1000baseT_Half |
9370 ADVERTISED_1000baseT_Full;
9371
9372 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9373 mask |= ADVERTISED_100baseT_Half |
9374 ADVERTISED_100baseT_Full |
9375 ADVERTISED_10baseT_Half |
9376 ADVERTISED_10baseT_Full |
9377 ADVERTISED_TP;
9378 else
9379 mask |= ADVERTISED_FIBRE;
9380
9381 if (cmd->advertising & ~mask)
9382 return -EINVAL;
9383
9384 mask &= (ADVERTISED_1000baseT_Half |
9385 ADVERTISED_1000baseT_Full |
9386 ADVERTISED_100baseT_Half |
9387 ADVERTISED_100baseT_Full |
9388 ADVERTISED_10baseT_Half |
9389 ADVERTISED_10baseT_Full);
9390
9391 cmd->advertising &= mask;
9392 } else {
9393 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9394 if (cmd->speed != SPEED_1000)
9395 return -EINVAL;
9396
9397 if (cmd->duplex != DUPLEX_FULL)
9398 return -EINVAL;
9399 } else {
9400 if (cmd->speed != SPEED_100 &&
9401 cmd->speed != SPEED_10)
9402 return -EINVAL;
9403 }
9404 }
9405
f47c11ee 9406 tg3_full_lock(tp, 0);
1da177e4
LT		 9407
9408 tp->link_config.autoneg = cmd->autoneg;
9409 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9410 tp->link_config.advertising = (cmd->advertising |
9411 ADVERTISED_Autoneg);
1da177e4
LT		 9412 tp->link_config.speed = SPEED_INVALID;
9413 tp->link_config.duplex = DUPLEX_INVALID;
9414 } else {
9415 tp->link_config.advertising = 0;
9416 tp->link_config.speed = cmd->speed;
9417 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9418 }
6aa20a22 9419
24fcad6b
MC		 9420 tp->link_config.orig_speed = tp->link_config.speed;
9421 tp->link_config.orig_duplex = tp->link_config.duplex;
9422 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9423
1da177e4
LT		 9424 if (netif_running(dev))
9425 tg3_setup_phy(tp, 1);
9426
f47c11ee 9427 tg3_full_unlock(tp);
6aa20a22 9428
1da177e4
LT		 9429 return 0;
9430}
6aa20a22 9431
1da177e4
LT		 9432static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9433{
9434 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9435
1da177e4
LT		 9436 strcpy(info->driver, DRV_MODULE_NAME);
9437 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9438 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9439 strcpy(info->bus_info, pci_name(tp->pdev));
9440}
6aa20a22 9441
1da177e4
LT		 9442static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9443{
9444 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9445
12dac075
RW		 9446 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9447 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9448 wol->supported = WAKE_MAGIC;
9449 else
9450 wol->supported = 0;
1da177e4 9451 wol->wolopts = 0;
05ac4cb7
MC		 9452 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9453 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9454 wol->wolopts = WAKE_MAGIC;
9455 memset(&wol->sopass, 0, sizeof(wol->sopass));
9456}
6aa20a22 9457
1da177e4
LT		 9458static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9459{
9460 struct tg3 *tp = netdev_priv(dev);
12dac075 9461 struct device *dp = &tp->pdev->dev;
6aa20a22 9462
1da177e4
LT		 9463 if (wol->wolopts & ~WAKE_MAGIC)
9464 return -EINVAL;
9465 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9466 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9467 return -EINVAL;
6aa20a22 9468
f47c11ee 9469 spin_lock_bh(&tp->lock);
12dac075 9470 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9471 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9472 device_set_wakeup_enable(dp, true);
9473 } else {
1da177e4 9474 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9475 device_set_wakeup_enable(dp, false);
9476 }
f47c11ee 9477 spin_unlock_bh(&tp->lock);
6aa20a22 9478
1da177e4
LT		 9479 return 0;
9480}
6aa20a22 9481
1da177e4
LT		 9482static u32 tg3_get_msglevel(struct net_device *dev)
9483{
9484 struct tg3 *tp = netdev_priv(dev);
9485 return tp->msg_enable;
9486}
6aa20a22 9487
1da177e4
LT		 9488static void tg3_set_msglevel(struct net_device *dev, u32 value)
9489{
9490 struct tg3 *tp = netdev_priv(dev);
9491 tp->msg_enable = value;
9492}
6aa20a22 9493
1da177e4
LT		 9494static int tg3_set_tso(struct net_device *dev, u32 value)
9495{
9496 struct tg3 *tp = netdev_priv(dev);
9497
9498 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9499 if (value)
9500 return -EINVAL;
9501 return 0;
9502 }
027455ad
MC		 9503 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9504 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9505 if (value) {
b0026624 9506 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9508 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9509 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 9511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6
MC		 9513 dev->features |= NETIF_F_TSO_ECN;
9514 } else
9515 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9516 }
1da177e4
LT		 9517 return ethtool_op_set_tso(dev, value);
9518}
6aa20a22 9519
1da177e4
LT		 9520static int tg3_nway_reset(struct net_device *dev)
9521{
9522 struct tg3 *tp = netdev_priv(dev);
1da177e4 9523 int r;
6aa20a22 9524
1da177e4
LT		 9525 if (!netif_running(dev))
9526 return -EAGAIN;
9527
c94e3941
MC		 9528 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9529 return -EINVAL;
9530
b02fd9e3
MC		 9531 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9532 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9533 return -EAGAIN;
3f0e3ad7 9534 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9535 } else {
9536 u32 bmcr;
9537
9538 spin_lock_bh(&tp->lock);
9539 r = -EINVAL;
9540 tg3_readphy(tp, MII_BMCR, &bmcr);
9541 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9542 ((bmcr & BMCR_ANENABLE) ||
9543 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9544 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9545 BMCR_ANENABLE);
9546 r = 0;
9547 }
9548 spin_unlock_bh(&tp->lock);
1da177e4 9549 }
6aa20a22 9550
1da177e4
LT		 9551 return r;
9552}
6aa20a22 9553
1da177e4
LT		 9554static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9555{
9556 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9557
1da177e4
LT		 9558 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9559 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9560 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9561 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9562 else
9563 ering->rx_jumbo_max_pending = 0;
9564
9565 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9566
9567 ering->rx_pending = tp->rx_pending;
9568 ering->rx_mini_pending = 0;
4f81c32b
MC		 9569 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9570 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9571 else
9572 ering->rx_jumbo_pending = 0;
9573
f3f3f27e 9574 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9575}
6aa20a22 9576
1da177e4
LT		 9577static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9578{
9579 struct tg3 *tp = netdev_priv(dev);
646c9edd 9580 int i, irq_sync = 0, err = 0;
6aa20a22 9581
1da177e4
LT		 9582 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9583 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9584 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9585 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9586 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9587 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9588 return -EINVAL;
6aa20a22 9589
bbe832c0 9590 if (netif_running(dev)) {
b02fd9e3 9591 tg3_phy_stop(tp);
1da177e4 9592 tg3_netif_stop(tp);
bbe832c0
MC		 9593 irq_sync = 1;
9594 }
1da177e4 9595
bbe832c0 9596 tg3_full_lock(tp, irq_sync);
6aa20a22 9597
1da177e4
LT		 9598 tp->rx_pending = ering->rx_pending;
9599
9600 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9601 tp->rx_pending > 63)
9602 tp->rx_pending = 63;
9603 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9604
9605 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9606 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9607
9608 if (netif_running(dev)) {
944d980e 9609 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9610 err = tg3_restart_hw(tp, 1);
9611 if (!err)
9612 tg3_netif_start(tp);
1da177e4
LT		 9613 }
9614
f47c11ee 9615 tg3_full_unlock(tp);
6aa20a22 9616
b02fd9e3
MC		 9617 if (irq_sync && !err)
9618 tg3_phy_start(tp);
9619
b9ec6c1b 9620 return err;
1da177e4 9621}
6aa20a22 9622
1da177e4
LT		 9623static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9624{
9625 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9626
1da177e4 9627 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9628
e18ce346 9629 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9630 epause->rx_pause = 1;
9631 else
9632 epause->rx_pause = 0;
9633
e18ce346 9634 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9635 epause->tx_pause = 1;
9636 else
9637 epause->tx_pause = 0;
1da177e4 9638}
6aa20a22 9639
1da177e4
LT		 9640static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9641{
9642 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9643 int err = 0;
6aa20a22 9644
b02fd9e3
MC		 9645 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9646 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9647 return -EAGAIN;
1da177e4 9648
b02fd9e3
MC		 9649 if (epause->autoneg) {
9650 u32 newadv;
9651 struct phy_device *phydev;
f47c11ee 9652
3f0e3ad7 9653 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9654
b02fd9e3
MC		 9655 if (epause->rx_pause) {
9656 if (epause->tx_pause)
9657 newadv = ADVERTISED_Pause;
9658 else
9659 newadv = ADVERTISED_Pause |
9660 ADVERTISED_Asym_Pause;
9661 } else if (epause->tx_pause) {
9662 newadv = ADVERTISED_Asym_Pause;
9663 } else
9664 newadv = 0;
9665
9666 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9667 u32 oldadv = phydev->advertising &
9668 (ADVERTISED_Pause |
9669 ADVERTISED_Asym_Pause);
9670 if (oldadv != newadv) {
9671 phydev->advertising &=
9672 ~(ADVERTISED_Pause |
9673 ADVERTISED_Asym_Pause);
9674 phydev->advertising |= newadv;
9675 err = phy_start_aneg(phydev);
9676 }
9677 } else {
9678 tp->link_config.advertising &=
9679 ~(ADVERTISED_Pause |
9680 ADVERTISED_Asym_Pause);
9681 tp->link_config.advertising |= newadv;
9682 }
9683 } else {
9684 if (epause->rx_pause)
e18ce346 9685 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9686 else
e18ce346 9687 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9688
b02fd9e3 9689 if (epause->tx_pause)
e18ce346 9690 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9691 else
e18ce346 9692 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9693
9694 if (netif_running(dev))
9695 tg3_setup_flow_control(tp, 0, 0);
9696 }
9697 } else {
9698 int irq_sync = 0;
9699
9700 if (netif_running(dev)) {
9701 tg3_netif_stop(tp);
9702 irq_sync = 1;
9703 }
9704
9705 tg3_full_lock(tp, irq_sync);
9706
9707 if (epause->autoneg)
9708 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9709 else
9710 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9711 if (epause->rx_pause)
e18ce346 9712 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9713 else
e18ce346 9714 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9715 if (epause->tx_pause)
e18ce346 9716 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9717 else
e18ce346 9718 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9719
9720 if (netif_running(dev)) {
9721 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9722 err = tg3_restart_hw(tp, 1);
9723 if (!err)
9724 tg3_netif_start(tp);
9725 }
9726
9727 tg3_full_unlock(tp);
9728 }
6aa20a22 9729
b9ec6c1b 9730 return err;
1da177e4 9731}
6aa20a22 9732
1da177e4
LT		 9733static u32 tg3_get_rx_csum(struct net_device *dev)
9734{
9735 struct tg3 *tp = netdev_priv(dev);
9736 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9737}
6aa20a22 9738
1da177e4
LT		 9739static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9740{
9741 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9742
1da177e4
LT		 9743 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9744 if (data != 0)
9745 return -EINVAL;
9746 return 0;
9747 }
6aa20a22 9748
f47c11ee 9749 spin_lock_bh(&tp->lock);
1da177e4
LT		 9750 if (data)
9751 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9752 else
9753 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9754 spin_unlock_bh(&tp->lock);
6aa20a22 9755
1da177e4
LT		 9756 return 0;
9757}
6aa20a22 9758
1da177e4
LT		 9759static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9760{
9761 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9762
1da177e4
LT		 9763 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9764 if (data != 0)
9765 return -EINVAL;
9766 return 0;
9767 }
6aa20a22 9768
321d32a0 9769 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9770 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9771 else
9c27dbdf 9772 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9773
9774 return 0;
9775}
9776
b9f2c044 9777static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9778{
b9f2c044
JG		 9779 switch (sset) {
9780 case ETH_SS_TEST:
9781 return TG3_NUM_TEST;
9782 case ETH_SS_STATS:
9783 return TG3_NUM_STATS;
9784 default:
9785 return -EOPNOTSUPP;
9786 }
4cafd3f5
MC		 9787}
9788
1da177e4
LT		 9789static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9790{
9791 switch (stringset) {
9792 case ETH_SS_STATS:
9793 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9794 break;
4cafd3f5
MC		 9795 case ETH_SS_TEST:
9796 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9797 break;
1da177e4
LT		 9798 default:
9799 WARN_ON(1); /* we need a WARN() */
9800 break;
9801 }
9802}
9803
4009a93d
MC		 9804static int tg3_phys_id(struct net_device *dev, u32 data)
9805{
9806 struct tg3 *tp = netdev_priv(dev);
9807 int i;
9808
9809 if (!netif_running(tp->dev))
9810 return -EAGAIN;
9811
9812 if (data == 0)
759afc31 9813 data = UINT_MAX / 2;
4009a93d
MC		 9814
9815 for (i = 0; i < (data * 2); i++) {
9816 if ((i % 2) == 0)
9817 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9818 LED_CTRL_1000MBPS_ON |
9819 LED_CTRL_100MBPS_ON |
9820 LED_CTRL_10MBPS_ON |
9821 LED_CTRL_TRAFFIC_OVERRIDE |
9822 LED_CTRL_TRAFFIC_BLINK |
9823 LED_CTRL_TRAFFIC_LED);
6aa20a22 9824
4009a93d
MC		 9825 else
9826 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9827 LED_CTRL_TRAFFIC_OVERRIDE);
9828
9829 if (msleep_interruptible(500))
9830 break;
9831 }
9832 tw32(MAC_LED_CTRL, tp->led_ctrl);
9833 return 0;
9834}
9835
1da177e4
LT		 9836static void tg3_get_ethtool_stats (struct net_device *dev,
9837 struct ethtool_stats *estats, u64 *tmp_stats)
9838{
9839 struct tg3 *tp = netdev_priv(dev);
9840 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9841}
9842
566f86ad 9843#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9844#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9845#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9846#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9847#define NVRAM_SELFBOOT_HW_SIZE 0x20
9848#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9849
9850static int tg3_test_nvram(struct tg3 *tp)
9851{
b9fc7dc5 9852 u32 csum, magic;
a9dc529d 9853 __be32 *buf;
ab0049b4 9854 int i, j, k, err = 0, size;
566f86ad 9855
df259d8c
MC		 9856 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9857 return 0;
9858
e4f34110 9859 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9860 return -EIO;
9861
1b27777a
MC		 9862 if (magic == TG3_EEPROM_MAGIC)
9863 size = NVRAM_TEST_SIZE;
b16250e3 9864 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9865 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9866 TG3_EEPROM_SB_FORMAT_1) {
9867 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9868 case TG3_EEPROM_SB_REVISION_0:
9869 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9870 break;
9871 case TG3_EEPROM_SB_REVISION_2:
9872 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9873 break;
9874 case TG3_EEPROM_SB_REVISION_3:
9875 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9876 break;
9877 default:
9878 return 0;
9879 }
9880 } else
1b27777a 9881 return 0;
b16250e3
MC		 9882 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9883 size = NVRAM_SELFBOOT_HW_SIZE;
9884 else
1b27777a
MC		 9885 return -EIO;
9886
9887 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9888 if (buf == NULL)
9889 return -ENOMEM;
9890
1b27777a
MC		 9891 err = -EIO;
9892 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9893 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9894 if (err)
566f86ad 9895 break;
566f86ad 9896 }
1b27777a 9897 if (i < size)
566f86ad
MC		 9898 goto out;
9899
1b27777a 9900 /* Selfboot format */
a9dc529d 9901 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9902 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9903 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9904 u8 *buf8 = (u8 *) buf, csum8 = 0;
9905
b9fc7dc5 9906 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9907 TG3_EEPROM_SB_REVISION_2) {
9908 /* For rev 2, the csum doesn't include the MBA. */
9909 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9910 csum8 += buf8[i];
9911 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9912 csum8 += buf8[i];
9913 } else {
9914 for (i = 0; i < size; i++)
9915 csum8 += buf8[i];
9916 }
1b27777a 9917
ad96b485
AB		 9918 if (csum8 == 0) {
9919 err = 0;
9920 goto out;
9921 }
9922
9923 err = -EIO;
9924 goto out;
1b27777a 9925 }
566f86ad 9926
b9fc7dc5 9927 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9928 TG3_EEPROM_MAGIC_HW) {
9929 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9930 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9931 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9932
9933 /* Separate the parity bits and the data bytes. */
9934 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9935 if ((i == 0) || (i == 8)) {
9936 int l;
9937 u8 msk;
9938
9939 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9940 parity[k++] = buf8[i] & msk;
9941 i++;
9942 }
9943 else if (i == 16) {
9944 int l;
9945 u8 msk;
9946
9947 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9948 parity[k++] = buf8[i] & msk;
9949 i++;
9950
9951 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9952 parity[k++] = buf8[i] & msk;
9953 i++;
9954 }
9955 data[j++] = buf8[i];
9956 }
9957
9958 err = -EIO;
9959 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9960 u8 hw8 = hweight8(data[i]);
9961
9962 if ((hw8 & 0x1) && parity[i])
9963 goto out;
9964 else if (!(hw8 & 0x1) && !parity[i])
9965 goto out;
9966 }
9967 err = 0;
9968 goto out;
9969 }
9970
566f86ad
MC		 9971 /* Bootstrap checksum at offset 0x10 */
9972 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9973 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9974 goto out;
9975
9976 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9977 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9978 if (csum != be32_to_cpu(buf[0xfc/4]))
9979 goto out;
566f86ad
MC		 9980
9981 err = 0;
9982
9983out:
9984 kfree(buf);
9985 return err;
9986}
9987
ca43007a
MC		 9988#define TG3_SERDES_TIMEOUT_SEC 2
9989#define TG3_COPPER_TIMEOUT_SEC 6
9990
9991static int tg3_test_link(struct tg3 *tp)
9992{
9993 int i, max;
9994
9995 if (!netif_running(tp->dev))
9996 return -ENODEV;
9997
4c987487 9998 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9999 max = TG3_SERDES_TIMEOUT_SEC;
10000 else
10001 max = TG3_COPPER_TIMEOUT_SEC;
10002
10003 for (i = 0; i < max; i++) {
10004 if (netif_carrier_ok(tp->dev))
10005 return 0;
10006
10007 if (msleep_interruptible(1000))
10008 break;
10009 }
10010
10011 return -EIO;
10012}
10013
a71116d1 10014/* Only test the commonly used registers */
30ca3e37 10015static int tg3_test_registers(struct tg3 *tp)
a71116d1 10016{
b16250e3 10017 int i, is_5705, is_5750;
a71116d1
MC		 10018 u32 offset, read_mask, write_mask, val, save_val, read_val;
10019 static struct {
10020 u16 offset;
10021 u16 flags;
10022#define TG3_FL_5705 0x1
10023#define TG3_FL_NOT_5705 0x2
10024#define TG3_FL_NOT_5788 0x4
b16250e3 10025#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10026 u32 read_mask;
10027 u32 write_mask;
10028 } reg_tbl[] = {
10029 /* MAC Control Registers */
10030 { MAC_MODE, TG3_FL_NOT_5705,
10031 0x00000000, 0x00ef6f8c },
10032 { MAC_MODE, TG3_FL_5705,
10033 0x00000000, 0x01ef6b8c },
10034 { MAC_STATUS, TG3_FL_NOT_5705,
10035 0x03800107, 0x00000000 },
10036 { MAC_STATUS, TG3_FL_5705,
10037 0x03800100, 0x00000000 },
10038 { MAC_ADDR_0_HIGH, 0x0000,
10039 0x00000000, 0x0000ffff },
10040 { MAC_ADDR_0_LOW, 0x0000,
10041 0x00000000, 0xffffffff },
10042 { MAC_RX_MTU_SIZE, 0x0000,
10043 0x00000000, 0x0000ffff },
10044 { MAC_TX_MODE, 0x0000,
10045 0x00000000, 0x00000070 },
10046 { MAC_TX_LENGTHS, 0x0000,
10047 0x00000000, 0x00003fff },
10048 { MAC_RX_MODE, TG3_FL_NOT_5705,
10049 0x00000000, 0x000007fc },
10050 { MAC_RX_MODE, TG3_FL_5705,
10051 0x00000000, 0x000007dc },
10052 { MAC_HASH_REG_0, 0x0000,
10053 0x00000000, 0xffffffff },
10054 { MAC_HASH_REG_1, 0x0000,
10055 0x00000000, 0xffffffff },
10056 { MAC_HASH_REG_2, 0x0000,
10057 0x00000000, 0xffffffff },
10058 { MAC_HASH_REG_3, 0x0000,
10059 0x00000000, 0xffffffff },
10060
10061 /* Receive Data and Receive BD Initiator Control Registers. */
10062 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10063 0x00000000, 0xffffffff },
10064 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10065 0x00000000, 0xffffffff },
10066 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10067 0x00000000, 0x00000003 },
10068 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10069 0x00000000, 0xffffffff },
10070 { RCVDBDI_STD_BD+0, 0x0000,
10071 0x00000000, 0xffffffff },
10072 { RCVDBDI_STD_BD+4, 0x0000,
10073 0x00000000, 0xffffffff },
10074 { RCVDBDI_STD_BD+8, 0x0000,
10075 0x00000000, 0xffff0002 },
10076 { RCVDBDI_STD_BD+0xc, 0x0000,
10077 0x00000000, 0xffffffff },
6aa20a22 10078
a71116d1
MC		 10079 /* Receive BD Initiator Control Registers. */
10080 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10081 0x00000000, 0xffffffff },
10082 { RCVBDI_STD_THRESH, TG3_FL_5705,
10083 0x00000000, 0x000003ff },
10084 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10085 0x00000000, 0xffffffff },
6aa20a22 10086
a71116d1
MC		 10087 /* Host Coalescing Control Registers. */
10088 { HOSTCC_MODE, TG3_FL_NOT_5705,
10089 0x00000000, 0x00000004 },
10090 { HOSTCC_MODE, TG3_FL_5705,
10091 0x00000000, 0x000000f6 },
10092 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10093 0x00000000, 0xffffffff },
10094 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10095 0x00000000, 0x000003ff },
10096 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10097 0x00000000, 0xffffffff },
10098 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10099 0x00000000, 0x000003ff },
10100 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10101 0x00000000, 0xffffffff },
10102 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10103 0x00000000, 0x000000ff },
10104 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10105 0x00000000, 0xffffffff },
10106 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10107 0x00000000, 0x000000ff },
10108 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10109 0x00000000, 0xffffffff },
10110 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10111 0x00000000, 0xffffffff },
10112 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10113 0x00000000, 0xffffffff },
10114 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10115 0x00000000, 0x000000ff },
10116 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10117 0x00000000, 0xffffffff },
10118 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10119 0x00000000, 0x000000ff },
10120 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10121 0x00000000, 0xffffffff },
10122 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10123 0x00000000, 0xffffffff },
10124 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10125 0x00000000, 0xffffffff },
10126 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10127 0x00000000, 0xffffffff },
10128 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10129 0x00000000, 0xffffffff },
10130 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10131 0xffffffff, 0x00000000 },
10132 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10133 0xffffffff, 0x00000000 },
10134
10135 /* Buffer Manager Control Registers. */
b16250e3 10136 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10137 0x00000000, 0x007fff80 },
b16250e3 10138 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10139 0x00000000, 0x007fffff },
10140 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10141 0x00000000, 0x0000003f },
10142 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10143 0x00000000, 0x000001ff },
10144 { BUFMGR_MB_HIGH_WATER, 0x0000,
10145 0x00000000, 0x000001ff },
10146 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10147 0xffffffff, 0x00000000 },
10148 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10149 0xffffffff, 0x00000000 },
6aa20a22 10150
a71116d1
MC		 10151 /* Mailbox Registers */
10152 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10153 0x00000000, 0x000001ff },
10154 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10155 0x00000000, 0x000001ff },
10156 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10157 0x00000000, 0x000007ff },
10158 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10159 0x00000000, 0x000001ff },
10160
10161 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10162 };
10163
b16250e3
MC		 10164 is_5705 = is_5750 = 0;
10165 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10166 is_5705 = 1;
b16250e3
MC		 10167 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10168 is_5750 = 1;
10169 }
a71116d1
MC		 10170
10171 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10172 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10173 continue;
10174
10175 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10176 continue;
10177
10178 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10179 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10180 continue;
10181
b16250e3
MC		 10182 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10183 continue;
10184
a71116d1
MC		 10185 offset = (u32) reg_tbl[i].offset;
10186 read_mask = reg_tbl[i].read_mask;
10187 write_mask = reg_tbl[i].write_mask;
10188
10189 /* Save the original register content */
10190 save_val = tr32(offset);
10191
10192 /* Determine the read-only value. */
10193 read_val = save_val & read_mask;
10194
10195 /* Write zero to the register, then make sure the read-only bits
10196 * are not changed and the read/write bits are all zeros.
10197 */
10198 tw32(offset, 0);
10199
10200 val = tr32(offset);
10201
10202 /* Test the read-only and read/write bits. */
10203 if (((val & read_mask) != read_val) || (val & write_mask))
10204 goto out;
10205
10206 /* Write ones to all the bits defined by RdMask and WrMask, then
10207 * make sure the read-only bits are not changed and the
10208 * read/write bits are all ones.
10209 */
10210 tw32(offset, read_mask | write_mask);
10211
10212 val = tr32(offset);
10213
10214 /* Test the read-only bits. */
10215 if ((val & read_mask) != read_val)
10216 goto out;
10217
10218 /* Test the read/write bits. */
10219 if ((val & write_mask) != write_mask)
10220 goto out;
10221
10222 tw32(offset, save_val);
10223 }
10224
10225 return 0;
10226
10227out:
9f88f29f
MC		 10228 if (netif_msg_hw(tp))
10229 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10230 offset);
a71116d1
MC		 10231 tw32(offset, save_val);
10232 return -EIO;
10233}
10234
7942e1db
MC		 10235static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10236{
f71e1309 10237 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10238 int i;
10239 u32 j;
10240
e9edda69 10241 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10242 for (j = 0; j < len; j += 4) {
10243 u32 val;
10244
10245 tg3_write_mem(tp, offset + j, test_pattern[i]);
10246 tg3_read_mem(tp, offset + j, &val);
10247 if (val != test_pattern[i])
10248 return -EIO;
10249 }
10250 }
10251 return 0;
10252}
10253
10254static int tg3_test_memory(struct tg3 *tp)
10255{
10256 static struct mem_entry {
10257 u32 offset;
10258 u32 len;
10259 } mem_tbl_570x[] = {
38690194 10260 { 0x00000000, 0x00b50},
7942e1db
MC		 10261 { 0x00002000, 0x1c000},
10262 { 0xffffffff, 0x00000}
10263 }, mem_tbl_5705[] = {
10264 { 0x00000100, 0x0000c},
10265 { 0x00000200, 0x00008},
7942e1db
MC		 10266 { 0x00004000, 0x00800},
10267 { 0x00006000, 0x01000},
10268 { 0x00008000, 0x02000},
10269 { 0x00010000, 0x0e000},
10270 { 0xffffffff, 0x00000}
79f4d13a
MC		 10271 }, mem_tbl_5755[] = {
10272 { 0x00000200, 0x00008},
10273 { 0x00004000, 0x00800},
10274 { 0x00006000, 0x00800},
10275 { 0x00008000, 0x02000},
10276 { 0x00010000, 0x0c000},
10277 { 0xffffffff, 0x00000}
b16250e3
MC		 10278 }, mem_tbl_5906[] = {
10279 { 0x00000200, 0x00008},
10280 { 0x00004000, 0x00400},
10281 { 0x00006000, 0x00400},
10282 { 0x00008000, 0x01000},
10283 { 0x00010000, 0x01000},
10284 { 0xffffffff, 0x00000}
7942e1db
MC		 10285 };
10286 struct mem_entry *mem_tbl;
10287 int err = 0;
10288 int i;
10289
321d32a0
MC		 10290 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10291 mem_tbl = mem_tbl_5755;
10292 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10293 mem_tbl = mem_tbl_5906;
10294 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10295 mem_tbl = mem_tbl_5705;
10296 else
7942e1db
MC		 10297 mem_tbl = mem_tbl_570x;
10298
10299 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10300 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10301 mem_tbl[i].len)) != 0)
10302 break;
10303 }
6aa20a22 10304
7942e1db
MC		 10305 return err;
10306}
10307
9f40dead
MC		 10308#define TG3_MAC_LOOPBACK 0
10309#define TG3_PHY_LOOPBACK 1
10310
10311static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10312{
9f40dead 10313 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10314 u32 desc_idx, coal_now;
c76949a6
MC		 10315 struct sk_buff *skb, *rx_skb;
10316 u8 *tx_data;
10317 dma_addr_t map;
10318 int num_pkts, tx_len, rx_len, i, err;
10319 struct tg3_rx_buffer_desc *desc;
898a56f8 10320 struct tg3_napi *tnapi, *rnapi;
21f581a5 10321 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10322
0c1d0e2b
MC		 10323 if (tp->irq_cnt > 1) {
10324 tnapi = &tp->napi[1];
10325 rnapi = &tp->napi[1];
10326 } else {
10327 tnapi = &tp->napi[0];
10328 rnapi = &tp->napi[0];
10329 }
fd2ce37f 10330 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10331
9f40dead 10332 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10333 /* HW errata - mac loopback fails in some cases on 5780.
10334 * Normal traffic and PHY loopback are not affected by
10335 * errata.
10336 */
10337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10338 return 0;
10339
9f40dead 10340 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10341 MAC_MODE_PORT_INT_LPBACK;
10342 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10343 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10344 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10345 mac_mode |= MAC_MODE_PORT_MODE_MII;
10346 else
10347 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10348 tw32(MAC_MODE, mac_mode);
10349 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10350 u32 val;
10351
7f97a4bd
MC		 10352 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10353 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10354 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10355 } else
10356 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10357
9ef8ca99
MC		 10358 tg3_phy_toggle_automdix(tp, 0);
10359
3f7045c1 10360 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10361 udelay(40);
5d64ad34 10362
e8f3f6ca 10363 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10364 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10366 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10367 mac_mode |= MAC_MODE_PORT_MODE_MII;
10368 } else
10369 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10370
c94e3941
MC		 10371 /* reset to prevent losing 1st rx packet intermittently */
10372 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10373 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10374 udelay(10);
10375 tw32_f(MAC_RX_MODE, tp->rx_mode);
10376 }
e8f3f6ca
MC		 10377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10378 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10379 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10380 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10381 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10382 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10383 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10384 }
9f40dead 10385 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10386 }
10387 else
10388 return -EINVAL;
c76949a6
MC		 10389
10390 err = -EIO;
10391
c76949a6 10392 tx_len = 1514;
a20e9c62 10393 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10394 if (!skb)
10395 return -ENOMEM;
10396
c76949a6
MC		 10397 tx_data = skb_put(skb, tx_len);
10398 memcpy(tx_data, tp->dev->dev_addr, 6);
10399 memset(tx_data + 6, 0x0, 8);
10400
10401 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10402
10403 for (i = 14; i < tx_len; i++)
10404 tx_data[i] = (u8) (i & 0xff);
10405
a21771dd
MC		 10406 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10407 dev_kfree_skb(skb);
10408 return -EIO;
10409 }
c76949a6
MC		 10410
10411 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10412 rnapi->coal_now);
c76949a6
MC		 10413
10414 udelay(10);
10415
898a56f8 10416 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10417
c76949a6
MC		 10418 num_pkts = 0;
10419
a21771dd
MC		 10420 tg3_set_txd(tnapi, tnapi->tx_prod,
10421 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10422
f3f3f27e 10423 tnapi->tx_prod++;
c76949a6
MC		 10424 num_pkts++;
10425
f3f3f27e
MC		 10426 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10427 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10428
10429 udelay(10);
10430
303fc921
MC		 10431 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10432 for (i = 0; i < 35; i++) {
c76949a6 10433 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10434 coal_now);
c76949a6
MC		 10435
10436 udelay(10);
10437
898a56f8
MC		 10438 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10439 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10440 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10441 (rx_idx == (rx_start_idx + num_pkts)))
10442 break;
10443 }
10444
a21771dd 10445 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10446 dev_kfree_skb(skb);
10447
f3f3f27e 10448 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10449 goto out;
10450
10451 if (rx_idx != rx_start_idx + num_pkts)
10452 goto out;
10453
72334482 10454 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10455 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10456 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10457 if (opaque_key != RXD_OPAQUE_RING_STD)
10458 goto out;
10459
10460 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10461 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10462 goto out;
10463
10464 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10465 if (rx_len != tx_len)
10466 goto out;
10467
21f581a5 10468 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10469
21f581a5 10470 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10471 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10472
10473 for (i = 14; i < tx_len; i++) {
10474 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10475 goto out;
10476 }
10477 err = 0;
6aa20a22 10478
c76949a6
MC		 10479 /* tg3_free_rings will unmap and free the rx_skb */
10480out:
10481 return err;
10482}
10483
9f40dead
MC		 10484#define TG3_MAC_LOOPBACK_FAILED 1
10485#define TG3_PHY_LOOPBACK_FAILED 2
10486#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10487 TG3_PHY_LOOPBACK_FAILED)
10488
10489static int tg3_test_loopback(struct tg3 *tp)
10490{
10491 int err = 0;
9936bcf6 10492 u32 cpmuctrl = 0;
9f40dead
MC		 10493
10494 if (!netif_running(tp->dev))
10495 return TG3_LOOPBACK_FAILED;
10496
b9ec6c1b
MC		 10497 err = tg3_reset_hw(tp, 1);
10498 if (err)
10499 return TG3_LOOPBACK_FAILED;
9f40dead 10500
6833c043
MC		 10501 /* Turn off gphy autopowerdown. */
10502 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10503 tg3_phy_toggle_apd(tp, false);
10504
321d32a0 10505 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10506 int i;
10507 u32 status;
10508
10509 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10510
10511 /* Wait for up to 40 microseconds to acquire lock. */
10512 for (i = 0; i < 4; i++) {
10513 status = tr32(TG3_CPMU_MUTEX_GNT);
10514 if (status == CPMU_MUTEX_GNT_DRIVER)
10515 break;
10516 udelay(10);
10517 }
10518
10519 if (status != CPMU_MUTEX_GNT_DRIVER)
10520 return TG3_LOOPBACK_FAILED;
10521
b2a5c19c 10522 /* Turn off link-based power management. */
e875093c 10523 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10524 tw32(TG3_CPMU_CTRL,
10525 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10526 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10527 }
10528
9f40dead
MC		 10529 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10530 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10531
321d32a0 10532 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10533 tw32(TG3_CPMU_CTRL, cpmuctrl);
10534
10535 /* Release the mutex */
10536 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10537 }
10538
dd477003
MC		 10539 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10540 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10541 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10542 err |= TG3_PHY_LOOPBACK_FAILED;
10543 }
10544
6833c043
MC		 10545 /* Re-enable gphy autopowerdown. */
10546 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10547 tg3_phy_toggle_apd(tp, true);
10548
9f40dead
MC		 10549 return err;
10550}
10551
4cafd3f5
MC		 10552static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10553 u64 *data)
10554{
566f86ad
MC		 10555 struct tg3 *tp = netdev_priv(dev);
10556
bc1c7567
MC		 10557 if (tp->link_config.phy_is_low_power)
10558 tg3_set_power_state(tp, PCI_D0);
10559
566f86ad
MC		 10560 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10561
10562 if (tg3_test_nvram(tp) != 0) {
10563 etest->flags |= ETH_TEST_FL_FAILED;
10564 data[0] = 1;
10565 }
ca43007a
MC		 10566 if (tg3_test_link(tp) != 0) {
10567 etest->flags |= ETH_TEST_FL_FAILED;
10568 data[1] = 1;
10569 }
a71116d1 10570 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10571 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10572
10573 if (netif_running(dev)) {
b02fd9e3 10574 tg3_phy_stop(tp);
a71116d1 10575 tg3_netif_stop(tp);
bbe832c0
MC		 10576 irq_sync = 1;
10577 }
a71116d1 10578
bbe832c0 10579 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10580
10581 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10582 err = tg3_nvram_lock(tp);
a71116d1
MC		 10583 tg3_halt_cpu(tp, RX_CPU_BASE);
10584 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10585 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10586 if (!err)
10587 tg3_nvram_unlock(tp);
a71116d1 10588
d9ab5ad1
MC		 10589 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10590 tg3_phy_reset(tp);
10591
a71116d1
MC		 10592 if (tg3_test_registers(tp) != 0) {
10593 etest->flags |= ETH_TEST_FL_FAILED;
10594 data[2] = 1;
10595 }
7942e1db
MC		 10596 if (tg3_test_memory(tp) != 0) {
10597 etest->flags |= ETH_TEST_FL_FAILED;
10598 data[3] = 1;
10599 }
9f40dead 10600 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10601 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10602
f47c11ee
DM		 10603 tg3_full_unlock(tp);
10604
d4bc3927
MC		 10605 if (tg3_test_interrupt(tp) != 0) {
10606 etest->flags |= ETH_TEST_FL_FAILED;
10607 data[5] = 1;
10608 }
f47c11ee
DM		 10609
10610 tg3_full_lock(tp, 0);
d4bc3927 10611
a71116d1
MC		 10612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10613 if (netif_running(dev)) {
10614 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10615 err2 = tg3_restart_hw(tp, 1);
10616 if (!err2)
b9ec6c1b 10617 tg3_netif_start(tp);
a71116d1 10618 }
f47c11ee
DM		 10619
10620 tg3_full_unlock(tp);
b02fd9e3
MC		 10621
10622 if (irq_sync && !err2)
10623 tg3_phy_start(tp);
a71116d1 10624 }
bc1c7567
MC		 10625 if (tp->link_config.phy_is_low_power)
10626 tg3_set_power_state(tp, PCI_D3hot);
10627
4cafd3f5
MC		 10628}
10629
1da177e4
LT		 10630static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10631{
10632 struct mii_ioctl_data *data = if_mii(ifr);
10633 struct tg3 *tp = netdev_priv(dev);
10634 int err;
10635
b02fd9e3 10636 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10637 struct phy_device *phydev;
b02fd9e3
MC		 10638 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10639 return -EAGAIN;
3f0e3ad7
MC		 10640 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10641 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10642 }
10643
1da177e4
LT		 10644 switch(cmd) {
10645 case SIOCGMIIPHY:
882e9793 10646 data->phy_id = tp->phy_addr;
1da177e4
LT		 10647
10648 /* fallthru */
10649 case SIOCGMIIREG: {
10650 u32 mii_regval;
10651
10652 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10653 break; /* We have no PHY */
10654
bc1c7567
MC		 10655 if (tp->link_config.phy_is_low_power)
10656 return -EAGAIN;
10657
f47c11ee 10658 spin_lock_bh(&tp->lock);
1da177e4 10659 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10660 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10661
10662 data->val_out = mii_regval;
10663
10664 return err;
10665 }
10666
10667 case SIOCSMIIREG:
10668 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10669 break; /* We have no PHY */
10670
bc1c7567
MC		 10671 if (tp->link_config.phy_is_low_power)
10672 return -EAGAIN;
10673
f47c11ee 10674 spin_lock_bh(&tp->lock);
1da177e4 10675 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10676 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10677
10678 return err;
10679
10680 default:
10681 /* do nothing */
10682 break;
10683 }
10684 return -EOPNOTSUPP;
10685}
10686
10687#if TG3_VLAN_TAG_USED
10688static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10689{
10690 struct tg3 *tp = netdev_priv(dev);
10691
844b3eed
MC		 10692 if (!netif_running(dev)) {
10693 tp->vlgrp = grp;
10694 return;
10695 }
10696
10697 tg3_netif_stop(tp);
29315e87 10698
f47c11ee 10699 tg3_full_lock(tp, 0);
1da177e4
LT		 10700
10701 tp->vlgrp = grp;
10702
10703 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10704 __tg3_set_rx_mode(dev);
10705
844b3eed 10706 tg3_netif_start(tp);
46966545
MC		 10707
10708 tg3_full_unlock(tp);
1da177e4 10709}
1da177e4
LT		 10710#endif
10711
15f9850d
DM		 10712static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10713{
10714 struct tg3 *tp = netdev_priv(dev);
10715
10716 memcpy(ec, &tp->coal, sizeof(*ec));
10717 return 0;
10718}
10719
d244c892
MC		 10720static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10721{
10722 struct tg3 *tp = netdev_priv(dev);
10723 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10724 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10725
10726 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10727 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10728 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10729 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10730 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10731 }
10732
10733 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10734 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10735 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10736 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10737 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10738 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10739 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10740 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10741 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10742 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10743 return -EINVAL;
10744
10745 /* No rx interrupts will be generated if both are zero */
10746 if ((ec->rx_coalesce_usecs == 0) &&
10747 (ec->rx_max_coalesced_frames == 0))
10748 return -EINVAL;
10749
10750 /* No tx interrupts will be generated if both are zero */
10751 if ((ec->tx_coalesce_usecs == 0) &&
10752 (ec->tx_max_coalesced_frames == 0))
10753 return -EINVAL;
10754
10755 /* Only copy relevant parameters, ignore all others. */
10756 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10757 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10758 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10759 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10760 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10761 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10762 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10763 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10764 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10765
10766 if (netif_running(dev)) {
10767 tg3_full_lock(tp, 0);
10768 __tg3_set_coalesce(tp, &tp->coal);
10769 tg3_full_unlock(tp);
10770 }
10771 return 0;
10772}
10773
7282d491 10774static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10775 .get_settings = tg3_get_settings,
10776 .set_settings = tg3_set_settings,
10777 .get_drvinfo = tg3_get_drvinfo,
10778 .get_regs_len = tg3_get_regs_len,
10779 .get_regs = tg3_get_regs,
10780 .get_wol = tg3_get_wol,
10781 .set_wol = tg3_set_wol,
10782 .get_msglevel = tg3_get_msglevel,
10783 .set_msglevel = tg3_set_msglevel,
10784 .nway_reset = tg3_nway_reset,
10785 .get_link = ethtool_op_get_link,
10786 .get_eeprom_len = tg3_get_eeprom_len,
10787 .get_eeprom = tg3_get_eeprom,
10788 .set_eeprom = tg3_set_eeprom,
10789 .get_ringparam = tg3_get_ringparam,
10790 .set_ringparam = tg3_set_ringparam,
10791 .get_pauseparam = tg3_get_pauseparam,
10792 .set_pauseparam = tg3_set_pauseparam,
10793 .get_rx_csum = tg3_get_rx_csum,
10794 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10795 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10796 .set_sg = ethtool_op_set_sg,
1da177e4 10797 .set_tso = tg3_set_tso,
4cafd3f5 10798 .self_test = tg3_self_test,
1da177e4 10799 .get_strings = tg3_get_strings,
4009a93d 10800 .phys_id = tg3_phys_id,
1da177e4 10801 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10802 .get_coalesce = tg3_get_coalesce,
d244c892 10803 .set_coalesce = tg3_set_coalesce,
b9f2c044 10804 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10805};
10806
10807static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10808{
1b27777a 10809 u32 cursize, val, magic;
1da177e4
LT		 10810
10811 tp->nvram_size = EEPROM_CHIP_SIZE;
10812
e4f34110 10813 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10814 return;
10815
b16250e3
MC		 10816 if ((magic != TG3_EEPROM_MAGIC) &&
10817 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10818 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10819 return;
10820
10821 /*
10822 * Size the chip by reading offsets at increasing powers of two.
10823 * When we encounter our validation signature, we know the addressing
10824 * has wrapped around, and thus have our chip size.
10825 */
1b27777a 10826 cursize = 0x10;
1da177e4
LT		 10827
10828 while (cursize < tp->nvram_size) {
e4f34110 10829 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10830 return;
10831
1820180b 10832 if (val == magic)
1da177e4
LT		 10833 break;
10834
10835 cursize <<= 1;
10836 }
10837
10838 tp->nvram_size = cursize;
10839}
6aa20a22 10840
1da177e4
LT		 10841static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10842{
10843 u32 val;
10844
df259d8c
MC		 10845 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10846 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10847 return;
10848
10849 /* Selfboot format */
1820180b 10850 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10851 tg3_get_eeprom_size(tp);
10852 return;
10853 }
10854
6d348f2c 10855 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10856 if (val != 0) {
6d348f2c
MC		 10857 /* This is confusing. We want to operate on the
10858 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10859 * call will read from NVRAM and byteswap the data
10860 * according to the byteswapping settings for all
10861 * other register accesses. This ensures the data we
10862 * want will always reside in the lower 16-bits.
10863 * However, the data in NVRAM is in LE format, which
10864 * means the data from the NVRAM read will always be
10865 * opposite the endianness of the CPU. The 16-bit
10866 * byteswap then brings the data to CPU endianness.
10867 */
10868 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10869 return;
10870 }
10871 }
fd1122a2 10872 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10873}
10874
10875static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10876{
10877 u32 nvcfg1;
10878
10879 nvcfg1 = tr32(NVRAM_CFG1);
10880 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10881 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10882 } else {
1da177e4
LT		 10883 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10884 tw32(NVRAM_CFG1, nvcfg1);
10885 }
10886
4c987487 10887 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10888 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10889 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10890 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10891 tp->nvram_jedecnum = JEDEC_ATMEL;
10892 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10893 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10894 break;
10895 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10896 tp->nvram_jedecnum = JEDEC_ATMEL;
10897 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10898 break;
10899 case FLASH_VENDOR_ATMEL_EEPROM:
10900 tp->nvram_jedecnum = JEDEC_ATMEL;
10901 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10902 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10903 break;
10904 case FLASH_VENDOR_ST:
10905 tp->nvram_jedecnum = JEDEC_ST;
10906 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10907 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10908 break;
10909 case FLASH_VENDOR_SAIFUN:
10910 tp->nvram_jedecnum = JEDEC_SAIFUN;
10911 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10912 break;
10913 case FLASH_VENDOR_SST_SMALL:
10914 case FLASH_VENDOR_SST_LARGE:
10915 tp->nvram_jedecnum = JEDEC_SST;
10916 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10917 break;
1da177e4 10918 }
8590a603 10919 } else {
1da177e4
LT		 10920 tp->nvram_jedecnum = JEDEC_ATMEL;
10921 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10922 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10923 }
10924}
10925
a1b950d5
MC		 10926static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10927{
10928 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10929 case FLASH_5752PAGE_SIZE_256:
10930 tp->nvram_pagesize = 256;
10931 break;
10932 case FLASH_5752PAGE_SIZE_512:
10933 tp->nvram_pagesize = 512;
10934 break;
10935 case FLASH_5752PAGE_SIZE_1K:
10936 tp->nvram_pagesize = 1024;
10937 break;
10938 case FLASH_5752PAGE_SIZE_2K:
10939 tp->nvram_pagesize = 2048;
10940 break;
10941 case FLASH_5752PAGE_SIZE_4K:
10942 tp->nvram_pagesize = 4096;
10943 break;
10944 case FLASH_5752PAGE_SIZE_264:
10945 tp->nvram_pagesize = 264;
10946 break;
10947 case FLASH_5752PAGE_SIZE_528:
10948 tp->nvram_pagesize = 528;
10949 break;
10950 }
10951}
10952
361b4ac2
MC		 10953static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10954{
10955 u32 nvcfg1;
10956
10957 nvcfg1 = tr32(NVRAM_CFG1);
10958
e6af301b
MC		 10959 /* NVRAM protection for TPM */
10960 if (nvcfg1 & (1 << 27))
10961 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10962
361b4ac2 10963 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10964 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10965 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10966 tp->nvram_jedecnum = JEDEC_ATMEL;
10967 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10968 break;
10969 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10970 tp->nvram_jedecnum = JEDEC_ATMEL;
10971 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10972 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10973 break;
10974 case FLASH_5752VENDOR_ST_M45PE10:
10975 case FLASH_5752VENDOR_ST_M45PE20:
10976 case FLASH_5752VENDOR_ST_M45PE40:
10977 tp->nvram_jedecnum = JEDEC_ST;
10978 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10979 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10980 break;
361b4ac2
MC		 10981 }
10982
10983 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 10984 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 10985 } else {
361b4ac2
MC		 10986 /* For eeprom, set pagesize to maximum eeprom size */
10987 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10988
10989 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10990 tw32(NVRAM_CFG1, nvcfg1);
10991 }
10992}
10993
d3c7b886
MC		 10994static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10995{
989a9d23 10996 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10997
10998 nvcfg1 = tr32(NVRAM_CFG1);
10999
11000 /* NVRAM protection for TPM */
989a9d23 11001 if (nvcfg1 & (1 << 27)) {
d3c7b886 11002 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 11003 protect = 1;
11004 }
d3c7b886 11005
989a9d23
MC		 11006 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11007 switch (nvcfg1) {
8590a603
MC		 11008 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11009 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11010 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11011 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11012 tp->nvram_jedecnum = JEDEC_ATMEL;
11013 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11014 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11015 tp->nvram_pagesize = 264;
11016 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11017 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11018 tp->nvram_size = (protect ? 0x3e200 :
11019 TG3_NVRAM_SIZE_512KB);
11020 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11021 tp->nvram_size = (protect ? 0x1f200 :
11022 TG3_NVRAM_SIZE_256KB);
11023 else
11024 tp->nvram_size = (protect ? 0x1f200 :
11025 TG3_NVRAM_SIZE_128KB);
11026 break;
11027 case FLASH_5752VENDOR_ST_M45PE10:
11028 case FLASH_5752VENDOR_ST_M45PE20:
11029 case FLASH_5752VENDOR_ST_M45PE40:
11030 tp->nvram_jedecnum = JEDEC_ST;
11031 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11032 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11033 tp->nvram_pagesize = 256;
11034 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11035 tp->nvram_size = (protect ?
11036 TG3_NVRAM_SIZE_64KB :
11037 TG3_NVRAM_SIZE_128KB);
11038 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11039 tp->nvram_size = (protect ?
11040 TG3_NVRAM_SIZE_64KB :
11041 TG3_NVRAM_SIZE_256KB);
11042 else
11043 tp->nvram_size = (protect ?
11044 TG3_NVRAM_SIZE_128KB :
11045 TG3_NVRAM_SIZE_512KB);
11046 break;
d3c7b886
MC		 11047 }
11048}
11049
1b27777a
MC		 11050static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11051{
11052 u32 nvcfg1;
11053
11054 nvcfg1 = tr32(NVRAM_CFG1);
11055
11056 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11057 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11058 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11059 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11060 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11061 tp->nvram_jedecnum = JEDEC_ATMEL;
11062 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11063 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11064
8590a603
MC		 11065 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11066 tw32(NVRAM_CFG1, nvcfg1);
11067 break;
11068 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11069 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11070 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11071 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11072 tp->nvram_jedecnum = JEDEC_ATMEL;
11073 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11074 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11075 tp->nvram_pagesize = 264;
11076 break;
11077 case FLASH_5752VENDOR_ST_M45PE10:
11078 case FLASH_5752VENDOR_ST_M45PE20:
11079 case FLASH_5752VENDOR_ST_M45PE40:
11080 tp->nvram_jedecnum = JEDEC_ST;
11081 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11082 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11083 tp->nvram_pagesize = 256;
11084 break;
1b27777a
MC		 11085 }
11086}
11087
6b91fa02
MC		 11088static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11089{
11090 u32 nvcfg1, protect = 0;
11091
11092 nvcfg1 = tr32(NVRAM_CFG1);
11093
11094 /* NVRAM protection for TPM */
11095 if (nvcfg1 & (1 << 27)) {
11096 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11097 protect = 1;
11098 }
11099
11100 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11101 switch (nvcfg1) {
8590a603
MC		 11102 case FLASH_5761VENDOR_ATMEL_ADB021D:
11103 case FLASH_5761VENDOR_ATMEL_ADB041D:
11104 case FLASH_5761VENDOR_ATMEL_ADB081D:
11105 case FLASH_5761VENDOR_ATMEL_ADB161D:
11106 case FLASH_5761VENDOR_ATMEL_MDB021D:
11107 case FLASH_5761VENDOR_ATMEL_MDB041D:
11108 case FLASH_5761VENDOR_ATMEL_MDB081D:
11109 case FLASH_5761VENDOR_ATMEL_MDB161D:
11110 tp->nvram_jedecnum = JEDEC_ATMEL;
11111 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11112 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11113 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11114 tp->nvram_pagesize = 256;
11115 break;
11116 case FLASH_5761VENDOR_ST_A_M45PE20:
11117 case FLASH_5761VENDOR_ST_A_M45PE40:
11118 case FLASH_5761VENDOR_ST_A_M45PE80:
11119 case FLASH_5761VENDOR_ST_A_M45PE16:
11120 case FLASH_5761VENDOR_ST_M_M45PE20:
11121 case FLASH_5761VENDOR_ST_M_M45PE40:
11122 case FLASH_5761VENDOR_ST_M_M45PE80:
11123 case FLASH_5761VENDOR_ST_M_M45PE16:
11124 tp->nvram_jedecnum = JEDEC_ST;
11125 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11126 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11127 tp->nvram_pagesize = 256;
11128 break;
6b91fa02
MC		 11129 }
11130
11131 if (protect) {
11132 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11133 } else {
11134 switch (nvcfg1) {
8590a603
MC		 11135 case FLASH_5761VENDOR_ATMEL_ADB161D:
11136 case FLASH_5761VENDOR_ATMEL_MDB161D:
11137 case FLASH_5761VENDOR_ST_A_M45PE16:
11138 case FLASH_5761VENDOR_ST_M_M45PE16:
11139 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11140 break;
11141 case FLASH_5761VENDOR_ATMEL_ADB081D:
11142 case FLASH_5761VENDOR_ATMEL_MDB081D:
11143 case FLASH_5761VENDOR_ST_A_M45PE80:
11144 case FLASH_5761VENDOR_ST_M_M45PE80:
11145 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11146 break;
11147 case FLASH_5761VENDOR_ATMEL_ADB041D:
11148 case FLASH_5761VENDOR_ATMEL_MDB041D:
11149 case FLASH_5761VENDOR_ST_A_M45PE40:
11150 case FLASH_5761VENDOR_ST_M_M45PE40:
11151 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11152 break;
11153 case FLASH_5761VENDOR_ATMEL_ADB021D:
11154 case FLASH_5761VENDOR_ATMEL_MDB021D:
11155 case FLASH_5761VENDOR_ST_A_M45PE20:
11156 case FLASH_5761VENDOR_ST_M_M45PE20:
11157 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11158 break;
6b91fa02
MC		 11159 }
11160 }
11161}
11162
b5d3772c
MC		 11163static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11164{
11165 tp->nvram_jedecnum = JEDEC_ATMEL;
11166 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11167 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11168}
11169
321d32a0
MC		 11170static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11171{
11172 u32 nvcfg1;
11173
11174 nvcfg1 = tr32(NVRAM_CFG1);
11175
11176 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11177 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11178 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11179 tp->nvram_jedecnum = JEDEC_ATMEL;
11180 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11181 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11182
11183 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11184 tw32(NVRAM_CFG1, nvcfg1);
11185 return;
11186 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11187 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11188 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11189 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11190 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11191 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11192 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11193 tp->nvram_jedecnum = JEDEC_ATMEL;
11194 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11195 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11196
11197 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11198 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11199 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11200 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11201 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11202 break;
11203 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11204 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11205 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11206 break;
11207 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11208 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11209 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11210 break;
11211 }
11212 break;
11213 case FLASH_5752VENDOR_ST_M45PE10:
11214 case FLASH_5752VENDOR_ST_M45PE20:
11215 case FLASH_5752VENDOR_ST_M45PE40:
11216 tp->nvram_jedecnum = JEDEC_ST;
11217 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11218 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11219
11220 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11221 case FLASH_5752VENDOR_ST_M45PE10:
11222 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11223 break;
11224 case FLASH_5752VENDOR_ST_M45PE20:
11225 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11226 break;
11227 case FLASH_5752VENDOR_ST_M45PE40:
11228 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11229 break;
11230 }
11231 break;
11232 default:
df259d8c 11233 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11234 return;
11235 }
11236
a1b950d5
MC		 11237 tg3_nvram_get_pagesize(tp, nvcfg1);
11238 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11239 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11240}
11241
11242
11243static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11244{
11245 u32 nvcfg1;
11246
11247 nvcfg1 = tr32(NVRAM_CFG1);
11248
11249 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11250 case FLASH_5717VENDOR_ATMEL_EEPROM:
11251 case FLASH_5717VENDOR_MICRO_EEPROM:
11252 tp->nvram_jedecnum = JEDEC_ATMEL;
11253 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11254 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11255
11256 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11257 tw32(NVRAM_CFG1, nvcfg1);
11258 return;
11259 case FLASH_5717VENDOR_ATMEL_MDB011D:
11260 case FLASH_5717VENDOR_ATMEL_ADB011B:
11261 case FLASH_5717VENDOR_ATMEL_ADB011D:
11262 case FLASH_5717VENDOR_ATMEL_MDB021D:
11263 case FLASH_5717VENDOR_ATMEL_ADB021B:
11264 case FLASH_5717VENDOR_ATMEL_ADB021D:
11265 case FLASH_5717VENDOR_ATMEL_45USPT:
11266 tp->nvram_jedecnum = JEDEC_ATMEL;
11267 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11268 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11269
11270 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11271 case FLASH_5717VENDOR_ATMEL_MDB021D:
11272 case FLASH_5717VENDOR_ATMEL_ADB021B:
11273 case FLASH_5717VENDOR_ATMEL_ADB021D:
11274 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11275 break;
11276 default:
11277 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11278 break;
11279 }
321d32a0 11280 break;
a1b950d5
MC		 11281 case FLASH_5717VENDOR_ST_M_M25PE10:
11282 case FLASH_5717VENDOR_ST_A_M25PE10:
11283 case FLASH_5717VENDOR_ST_M_M45PE10:
11284 case FLASH_5717VENDOR_ST_A_M45PE10:
11285 case FLASH_5717VENDOR_ST_M_M25PE20:
11286 case FLASH_5717VENDOR_ST_A_M25PE20:
11287 case FLASH_5717VENDOR_ST_M_M45PE20:
11288 case FLASH_5717VENDOR_ST_A_M45PE20:
11289 case FLASH_5717VENDOR_ST_25USPT:
11290 case FLASH_5717VENDOR_ST_45USPT:
11291 tp->nvram_jedecnum = JEDEC_ST;
11292 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11293 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11294
11295 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11296 case FLASH_5717VENDOR_ST_M_M25PE20:
11297 case FLASH_5717VENDOR_ST_A_M25PE20:
11298 case FLASH_5717VENDOR_ST_M_M45PE20:
11299 case FLASH_5717VENDOR_ST_A_M45PE20:
11300 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11301 break;
11302 default:
11303 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11304 break;
11305 }
321d32a0 11306 break;
a1b950d5
MC		 11307 default:
11308 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11309 return;
321d32a0 11310 }
a1b950d5
MC		 11311
11312 tg3_nvram_get_pagesize(tp, nvcfg1);
11313 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11314 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11315}
11316
1da177e4
LT		 11317/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11318static void __devinit tg3_nvram_init(struct tg3 *tp)
11319{
1da177e4
LT		 11320 tw32_f(GRC_EEPROM_ADDR,
11321 (EEPROM_ADDR_FSM_RESET |
11322 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11323 EEPROM_ADDR_CLKPERD_SHIFT)));
11324
9d57f01c 11325 msleep(1);
1da177e4
LT		 11326
11327 /* Enable seeprom accesses. */
11328 tw32_f(GRC_LOCAL_CTRL,
11329 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11330 udelay(100);
11331
11332 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11333 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11334 tp->tg3_flags |= TG3_FLAG_NVRAM;
11335
ec41c7df
MC		 11336 if (tg3_nvram_lock(tp)) {
11337 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11338 "tg3_nvram_init failed.\n", tp->dev->name);
11339 return;
11340 }
e6af301b 11341 tg3_enable_nvram_access(tp);
1da177e4 11342
989a9d23
MC		 11343 tp->nvram_size = 0;
11344
361b4ac2
MC		 11345 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11346 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11347 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11348 tg3_get_5755_nvram_info(tp);
d30cdd28 11349 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11352 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11353 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11354 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11355 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11356 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11357 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11358 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11359 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11360 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11361 else
11362 tg3_get_nvram_info(tp);
11363
989a9d23
MC		 11364 if (tp->nvram_size == 0)
11365 tg3_get_nvram_size(tp);
1da177e4 11366
e6af301b 11367 tg3_disable_nvram_access(tp);
381291b7 11368 tg3_nvram_unlock(tp);
1da177e4
LT		 11369
11370 } else {
11371 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11372
11373 tg3_get_eeprom_size(tp);
11374 }
11375}
11376
1da177e4
LT		 11377static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11378 u32 offset, u32 len, u8 *buf)
11379{
11380 int i, j, rc = 0;
11381 u32 val;
11382
11383 for (i = 0; i < len; i += 4) {
b9fc7dc5 11384 u32 addr;
a9dc529d 11385 __be32 data;
1da177e4
LT		 11386
11387 addr = offset + i;
11388
11389 memcpy(&data, buf + i, 4);
11390
62cedd11
MC		 11391 /*
11392 * The SEEPROM interface expects the data to always be opposite
11393 * the native endian format. We accomplish this by reversing
11394 * all the operations that would have been performed on the
11395 * data from a call to tg3_nvram_read_be32().
11396 */
11397 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11398
11399 val = tr32(GRC_EEPROM_ADDR);
11400 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11401
11402 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11403 EEPROM_ADDR_READ);
11404 tw32(GRC_EEPROM_ADDR, val |
11405 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11406 (addr & EEPROM_ADDR_ADDR_MASK) |
11407 EEPROM_ADDR_START |
11408 EEPROM_ADDR_WRITE);
6aa20a22 11409
9d57f01c 11410 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11411 val = tr32(GRC_EEPROM_ADDR);
11412
11413 if (val & EEPROM_ADDR_COMPLETE)
11414 break;
9d57f01c 11415 msleep(1);
1da177e4
LT		 11416 }
11417 if (!(val & EEPROM_ADDR_COMPLETE)) {
11418 rc = -EBUSY;
11419 break;
11420 }
11421 }
11422
11423 return rc;
11424}
11425
11426/* offset and length are dword aligned */
11427static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11428 u8 *buf)
11429{
11430 int ret = 0;
11431 u32 pagesize = tp->nvram_pagesize;
11432 u32 pagemask = pagesize - 1;
11433 u32 nvram_cmd;
11434 u8 *tmp;
11435
11436 tmp = kmalloc(pagesize, GFP_KERNEL);
11437 if (tmp == NULL)
11438 return -ENOMEM;
11439
11440 while (len) {
11441 int j;
e6af301b 11442 u32 phy_addr, page_off, size;
1da177e4
LT		 11443
11444 phy_addr = offset & ~pagemask;
6aa20a22 11445
1da177e4 11446 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11447 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11448 (__be32 *) (tmp + j));
11449 if (ret)
1da177e4
LT		 11450 break;
11451 }
11452 if (ret)
11453 break;
11454
11455 page_off = offset & pagemask;
11456 size = pagesize;
11457 if (len < size)
11458 size = len;
11459
11460 len -= size;
11461
11462 memcpy(tmp + page_off, buf, size);
11463
11464 offset = offset + (pagesize - page_off);
11465
e6af301b 11466 tg3_enable_nvram_access(tp);
1da177e4
LT		 11467
11468 /*
11469 * Before we can erase the flash page, we need
11470 * to issue a special "write enable" command.
11471 */
11472 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11473
11474 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11475 break;
11476
11477 /* Erase the target page */
11478 tw32(NVRAM_ADDR, phy_addr);
11479
11480 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11481 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11482
11483 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11484 break;
11485
11486 /* Issue another write enable to start the write. */
11487 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11488
11489 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11490 break;
11491
11492 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11493 __be32 data;
1da177e4 11494
b9fc7dc5 11495 data = *((__be32 *) (tmp + j));
a9dc529d 11496
b9fc7dc5 11497 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11498
11499 tw32(NVRAM_ADDR, phy_addr + j);
11500
11501 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11502 NVRAM_CMD_WR;
11503
11504 if (j == 0)
11505 nvram_cmd |= NVRAM_CMD_FIRST;
11506 else if (j == (pagesize - 4))
11507 nvram_cmd |= NVRAM_CMD_LAST;
11508
11509 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11510 break;
11511 }
11512 if (ret)
11513 break;
11514 }
11515
11516 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11517 tg3_nvram_exec_cmd(tp, nvram_cmd);
11518
11519 kfree(tmp);
11520
11521 return ret;
11522}
11523
11524/* offset and length are dword aligned */
11525static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11526 u8 *buf)
11527{
11528 int i, ret = 0;
11529
11530 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11531 u32 page_off, phy_addr, nvram_cmd;
11532 __be32 data;
1da177e4
LT		 11533
11534 memcpy(&data, buf + i, 4);
b9fc7dc5 11535 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11536
11537 page_off = offset % tp->nvram_pagesize;
11538
1820180b 11539 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11540
11541 tw32(NVRAM_ADDR, phy_addr);
11542
11543 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11544
11545 if ((page_off == 0) || (i == 0))
11546 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11547 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11548 nvram_cmd |= NVRAM_CMD_LAST;
11549
11550 if (i == (len - 4))
11551 nvram_cmd |= NVRAM_CMD_LAST;
11552
321d32a0
MC		 11553 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11554 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11555 (tp->nvram_jedecnum == JEDEC_ST) &&
11556 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11557
11558 if ((ret = tg3_nvram_exec_cmd(tp,
11559 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11560 NVRAM_CMD_DONE)))
11561
11562 break;
11563 }
11564 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11565 /* We always do complete word writes to eeprom. */
11566 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11567 }
11568
11569 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11570 break;
11571 }
11572 return ret;
11573}
11574
11575/* offset and length are dword aligned */
11576static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11577{
11578 int ret;
11579
1da177e4 11580 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11581 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11582 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11583 udelay(40);
11584 }
11585
11586 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11587 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11588 }
11589 else {
11590 u32 grc_mode;
11591
ec41c7df
MC		 11592 ret = tg3_nvram_lock(tp);
11593 if (ret)
11594 return ret;
1da177e4 11595
e6af301b
MC		 11596 tg3_enable_nvram_access(tp);
11597 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11598 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11599 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11600
11601 grc_mode = tr32(GRC_MODE);
11602 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11603
11604 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11605 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11606
11607 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11608 buf);
11609 }
11610 else {
11611 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11612 buf);
11613 }
11614
11615 grc_mode = tr32(GRC_MODE);
11616 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11617
e6af301b 11618 tg3_disable_nvram_access(tp);
1da177e4
LT		 11619 tg3_nvram_unlock(tp);
11620 }
11621
11622 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11623 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11624 udelay(40);
11625 }
11626
11627 return ret;
11628}
11629
11630struct subsys_tbl_ent {
11631 u16 subsys_vendor, subsys_devid;
11632 u32 phy_id;
11633};
11634
11635static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11636 /* Broadcom boards. */
11637 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11638 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11639 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11640 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11641 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11642 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11643 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11644 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11645 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11646 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11647 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11648
11649 /* 3com boards. */
11650 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11651 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11652 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11653 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11654 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11655
11656 /* DELL boards. */
11657 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11658 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11659 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11660 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11661
11662 /* Compaq boards. */
11663 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11664 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11665 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11666 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11667 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11668
11669 /* IBM boards. */
11670 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11671};
11672
11673static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11674{
11675 int i;
11676
11677 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11678 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11679 tp->pdev->subsystem_vendor) &&
11680 (subsys_id_to_phy_id[i].subsys_devid ==
11681 tp->pdev->subsystem_device))
11682 return &subsys_id_to_phy_id[i];
11683 }
11684 return NULL;
11685}
11686
7d0c41ef 11687static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11688{
1da177e4 11689 u32 val;
caf636c7
MC		 11690 u16 pmcsr;
11691
11692 /* On some early chips the SRAM cannot be accessed in D3hot state,
11693 * so need make sure we're in D0.
11694 */
11695 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11696 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11697 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11698 msleep(1);
7d0c41ef
MC		 11699
11700 /* Make sure register accesses (indirect or otherwise)
11701 * will function correctly.
11702 */
11703 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11704 tp->misc_host_ctrl);
1da177e4 11705
f49639e6
DM		 11706 /* The memory arbiter has to be enabled in order for SRAM accesses
11707 * to succeed. Normally on powerup the tg3 chip firmware will make
11708 * sure it is enabled, but other entities such as system netboot
11709 * code might disable it.
11710 */
11711 val = tr32(MEMARB_MODE);
11712 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11713
1da177e4 11714 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11715 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11716
a85feb8c
GZ		 11717 /* Assume an onboard device and WOL capable by default. */
11718 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11719
b5d3772c 11720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11721 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11722 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11723 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11724 }
0527ba35
MC		 11725 val = tr32(VCPU_CFGSHDW);
11726 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11727 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11728 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11729 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11730 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11731 goto done;
b5d3772c
MC		 11732 }
11733
1da177e4
LT		 11734 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11735 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11736 u32 nic_cfg, led_cfg;
a9daf367 11737 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11738 int eeprom_phy_serdes = 0;
1da177e4
LT		 11739
11740 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11741 tp->nic_sram_data_cfg = nic_cfg;
11742
11743 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11744 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11745 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11746 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11747 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11748 (ver > 0) && (ver < 0x100))
11749 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11750
a9daf367
MC		 11751 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11752 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11753
1da177e4
LT		 11754 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11755 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11756 eeprom_phy_serdes = 1;
11757
11758 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11759 if (nic_phy_id != 0) {
11760 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11761 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11762
11763 eeprom_phy_id = (id1 >> 16) << 10;
11764 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11765 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11766 } else
11767 eeprom_phy_id = 0;
11768
7d0c41ef 11769 tp->phy_id = eeprom_phy_id;
747e8f8b 11770 if (eeprom_phy_serdes) {
a4e2b347 11771 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11772 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11773 else
11774 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11775 }
7d0c41ef 11776
cbf46853 11777 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11778 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11779 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11780 else
1da177e4
LT		 11781 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11782
11783 switch (led_cfg) {
11784 default:
11785 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11786 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11787 break;
11788
11789 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11790 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11791 break;
11792
11793 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11794 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11795
11796 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11797 * read on some older 5700/5701 bootcode.
11798 */
11799 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11800 ASIC_REV_5700 ||
11801 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11802 ASIC_REV_5701)
11803 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11804
1da177e4
LT		 11805 break;
11806
11807 case SHASTA_EXT_LED_SHARED:
11808 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11809 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11810 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11811 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11812 LED_CTRL_MODE_PHY_2);
11813 break;
11814
11815 case SHASTA_EXT_LED_MAC:
11816 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11817 break;
11818
11819 case SHASTA_EXT_LED_COMBO:
11820 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11821 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11822 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11823 LED_CTRL_MODE_PHY_2);
11824 break;
11825
855e1111 11826 }
1da177e4
LT		 11827
11828 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11830 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11831 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11832
b2a5c19c
MC		 11833 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11834 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11835
9d26e213 11836 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11837 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11838 if ((tp->pdev->subsystem_vendor ==
11839 PCI_VENDOR_ID_ARIMA) &&
11840 (tp->pdev->subsystem_device == 0x205a ||
11841 tp->pdev->subsystem_device == 0x2063))
11842 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11843 } else {
f49639e6 11844 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11845 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11846 }
1da177e4
LT		 11847
11848 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11849 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11850 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11851 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11852 }
b2b98d4a
MC		 11853
11854 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11855 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11856 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11857
a85feb8c
GZ		 11858 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11859 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11860 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11861
12dac075 11862 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11863 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11864 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11865
1da177e4
LT		 11866 if (cfg2 & (1 << 17))
11867 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11868
11869 /* serdes signal pre-emphasis in register 0x590 set by */
11870 /* bootcode if bit 18 is set */
11871 if (cfg2 & (1 << 18))
11872 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11873
321d32a0
MC		 11874 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11875 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11876 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11877 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11878
8ed5d97e
MC		 11879 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11880 u32 cfg3;
11881
11882 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11883 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11884 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11885 }
a9daf367
MC		 11886
11887 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11888 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11889 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11890 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11891 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11892 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11893 }
05ac4cb7
MC		 11894done:
11895 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11896 device_set_wakeup_enable(&tp->pdev->dev,
11897 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11898}
11899
b2a5c19c
MC		 11900static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11901{
11902 int i;
11903 u32 val;
11904
11905 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11906 tw32(OTP_CTRL, cmd);
11907
11908 /* Wait for up to 1 ms for command to execute. */
11909 for (i = 0; i < 100; i++) {
11910 val = tr32(OTP_STATUS);
11911 if (val & OTP_STATUS_CMD_DONE)
11912 break;
11913 udelay(10);
11914 }
11915
11916 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11917}
11918
11919/* Read the gphy configuration from the OTP region of the chip. The gphy
11920 * configuration is a 32-bit value that straddles the alignment boundary.
11921 * We do two 32-bit reads and then shift and merge the results.
11922 */
11923static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11924{
11925 u32 bhalf_otp, thalf_otp;
11926
11927 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11928
11929 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11930 return 0;
11931
11932 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11933
11934 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11935 return 0;
11936
11937 thalf_otp = tr32(OTP_READ_DATA);
11938
11939 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11940
11941 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11942 return 0;
11943
11944 bhalf_otp = tr32(OTP_READ_DATA);
11945
11946 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11947}
11948
7d0c41ef
MC		 11949static int __devinit tg3_phy_probe(struct tg3 *tp)
11950{
11951 u32 hw_phy_id_1, hw_phy_id_2;
11952 u32 hw_phy_id, hw_phy_id_masked;
11953 int err;
1da177e4 11954
b02fd9e3
MC		 11955 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11956 return tg3_phy_init(tp);
11957
1da177e4 11958 /* Reading the PHY ID register can conflict with ASF
877d0310 11959 * firmware access to the PHY hardware.
1da177e4
LT		 11960 */
11961 err = 0;
0d3031d9
MC		 11962 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11963 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11964 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11965 } else {
11966 /* Now read the physical PHY_ID from the chip and verify
11967 * that it is sane. If it doesn't look good, we fall back
11968 * to either the hard-coded table based PHY_ID and failing
11969 * that the value found in the eeprom area.
11970 */
11971 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11972 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11973
11974 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11975 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11976 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11977
11978 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11979 }
11980
11981 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11982 tp->phy_id = hw_phy_id;
11983 if (hw_phy_id_masked == PHY_ID_BCM8002)
11984 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11985 else
11986 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11987 } else {
7d0c41ef
MC		 11988 if (tp->phy_id != PHY_ID_INVALID) {
11989 /* Do nothing, phy ID already set up in
11990 * tg3_get_eeprom_hw_cfg().
11991 */
1da177e4
LT		 11992 } else {
11993 struct subsys_tbl_ent *p;
11994
11995 /* No eeprom signature? Try the hardcoded
11996 * subsys device table.
11997 */
11998 p = lookup_by_subsys(tp);
11999 if (!p)
12000 return -ENODEV;
12001
12002 tp->phy_id = p->phy_id;
12003 if (!tp->phy_id ||
12004 tp->phy_id == PHY_ID_BCM8002)
12005 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12006 }
12007 }
12008
747e8f8b 12009 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12010 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12011 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12012 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12013
12014 tg3_readphy(tp, MII_BMSR, &bmsr);
12015 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12016 (bmsr & BMSR_LSTATUS))
12017 goto skip_phy_reset;
6aa20a22 12018
1da177e4
LT		 12019 err = tg3_phy_reset(tp);
12020 if (err)
12021 return err;
12022
12023 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12024 ADVERTISE_100HALF | ADVERTISE_100FULL |
12025 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12026 tg3_ctrl = 0;
12027 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12028 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12029 MII_TG3_CTRL_ADV_1000_FULL);
12030 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12031 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12032 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12033 MII_TG3_CTRL_ENABLE_AS_MASTER);
12034 }
12035
3600d918
MC		 12036 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12037 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12038 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12039 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12040 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12041
12042 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12043 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12044
12045 tg3_writephy(tp, MII_BMCR,
12046 BMCR_ANENABLE | BMCR_ANRESTART);
12047 }
12048 tg3_phy_set_wirespeed(tp);
12049
12050 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12051 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12052 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12053 }
12054
12055skip_phy_reset:
12056 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12057 err = tg3_init_5401phy_dsp(tp);
12058 if (err)
12059 return err;
12060 }
12061
12062 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12063 err = tg3_init_5401phy_dsp(tp);
12064 }
12065
747e8f8b 12066 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12067 tp->link_config.advertising =
12068 (ADVERTISED_1000baseT_Half |
12069 ADVERTISED_1000baseT_Full |
12070 ADVERTISED_Autoneg |
12071 ADVERTISED_FIBRE);
12072 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12073 tp->link_config.advertising &=
12074 ~(ADVERTISED_1000baseT_Half |
12075 ADVERTISED_1000baseT_Full);
12076
12077 return err;
12078}
12079
12080static void __devinit tg3_read_partno(struct tg3 *tp)
12081{
6d348f2c 12082 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12083 unsigned int i;
1b27777a 12084 u32 magic;
1da177e4 12085
df259d8c
MC		 12086 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12087 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12088 goto out_not_found;
1da177e4 12089
1820180b 12090 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12091 for (i = 0; i < 256; i += 4) {
12092 u32 tmp;
1da177e4 12093
6d348f2c
MC		 12094 /* The data is in little-endian format in NVRAM.
12095 * Use the big-endian read routines to preserve
12096 * the byte order as it exists in NVRAM.
12097 */
12098 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12099 goto out_not_found;
12100
6d348f2c 12101 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12102 }
12103 } else {
12104 int vpd_cap;
12105
12106 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12107 for (i = 0; i < 256; i += 4) {
12108 u32 tmp, j = 0;
b9fc7dc5 12109 __le32 v;
1b27777a
MC		 12110 u16 tmp16;
12111
12112 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12113 i);
12114 while (j++ < 100) {
12115 pci_read_config_word(tp->pdev, vpd_cap +
12116 PCI_VPD_ADDR, &tmp16);
12117 if (tmp16 & 0x8000)
12118 break;
12119 msleep(1);
12120 }
f49639e6
DM		 12121 if (!(tmp16 & 0x8000))
12122 goto out_not_found;
12123
1b27777a
MC		 12124 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12125 &tmp);
b9fc7dc5 12126 v = cpu_to_le32(tmp);
6d348f2c 12127 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12128 }
1da177e4
LT		 12129 }
12130
12131 /* Now parse and find the part number. */
af2c6a4a 12132 for (i = 0; i < 254; ) {
1da177e4 12133 unsigned char val = vpd_data[i];
af2c6a4a 12134 unsigned int block_end;
1da177e4
LT		 12135
12136 if (val == 0x82 || val == 0x91) {
12137 i = (i + 3 +
12138 (vpd_data[i + 1] +
12139 (vpd_data[i + 2] << 8)));
12140 continue;
12141 }
12142
12143 if (val != 0x90)
12144 goto out_not_found;
12145
12146 block_end = (i + 3 +
12147 (vpd_data[i + 1] +
12148 (vpd_data[i + 2] << 8)));
12149 i += 3;
af2c6a4a
MC		 12150
12151 if (block_end > 256)
12152 goto out_not_found;
12153
12154 while (i < (block_end - 2)) {
1da177e4
LT		 12155 if (vpd_data[i + 0] == 'P' &&
12156 vpd_data[i + 1] == 'N') {
12157 int partno_len = vpd_data[i + 2];
12158
af2c6a4a
MC		 12159 i += 3;
12160 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12161 goto out_not_found;
12162
12163 memcpy(tp->board_part_number,
af2c6a4a 12164 &vpd_data[i], partno_len);
1da177e4
LT		 12165
12166 /* Success. */
12167 return;
12168 }
af2c6a4a 12169 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12170 }
12171
12172 /* Part number not found. */
12173 goto out_not_found;
12174 }
12175
12176out_not_found:
b5d3772c
MC		 12177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12178 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12179 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12180 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12181 strcpy(tp->board_part_number, "BCM57780");
12182 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12183 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12184 strcpy(tp->board_part_number, "BCM57760");
12185 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12187 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12188 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12189 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12190 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12191 else
12192 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12193}
12194
9c8a620e
MC		 12195static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12196{
12197 u32 val;
12198
e4f34110 12199 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12200 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12201 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12202 val != 0)
12203 return 0;
12204
12205 return 1;
12206}
12207
acd9c119
MC		 12208static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12209{
ff3a7cb2 12210 u32 val, offset, start, ver_offset;
acd9c119 12211 int i;
ff3a7cb2 12212 bool newver = false;
acd9c119
MC		 12213
12214 if (tg3_nvram_read(tp, 0xc, &offset) ||
12215 tg3_nvram_read(tp, 0x4, &start))
12216 return;
12217
12218 offset = tg3_nvram_logical_addr(tp, offset);
12219
ff3a7cb2 12220 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12221 return;
12222
ff3a7cb2
MC		 12223 if ((val & 0xfc000000) == 0x0c000000) {
12224 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12225 return;
12226
ff3a7cb2
MC		 12227 if (val == 0)
12228 newver = true;
12229 }
12230
12231 if (newver) {
12232 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12233 return;
12234
12235 offset = offset + ver_offset - start;
12236 for (i = 0; i < 16; i += 4) {
12237 __be32 v;
12238 if (tg3_nvram_read_be32(tp, offset + i, &v))
12239 return;
12240
12241 memcpy(tp->fw_ver + i, &v, sizeof(v));
12242 }
12243 } else {
12244 u32 major, minor;
12245
12246 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12247 return;
12248
12249 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12250 TG3_NVM_BCVER_MAJSFT;
12251 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12252 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12253 }
12254}
12255
a6f6cb1c
MC		 12256static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12257{
12258 u32 val, major, minor;
12259
12260 /* Use native endian representation */
12261 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12262 return;
12263
12264 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12265 TG3_NVM_HWSB_CFG1_MAJSFT;
12266 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12267 TG3_NVM_HWSB_CFG1_MINSFT;
12268
12269 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12270}
12271
dfe00d7d
MC		 12272static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12273{
12274 u32 offset, major, minor, build;
12275
12276 tp->fw_ver[0] = 's';
12277 tp->fw_ver[1] = 'b';
12278 tp->fw_ver[2] = '\0';
12279
12280 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12281 return;
12282
12283 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12284 case TG3_EEPROM_SB_REVISION_0:
12285 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12286 break;
12287 case TG3_EEPROM_SB_REVISION_2:
12288 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12289 break;
12290 case TG3_EEPROM_SB_REVISION_3:
12291 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12292 break;
12293 default:
12294 return;
12295 }
12296
e4f34110 12297 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12298 return;
12299
12300 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12301 TG3_EEPROM_SB_EDH_BLD_SHFT;
12302 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12303 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12304 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12305
12306 if (minor > 99 || build > 26)
12307 return;
12308
12309 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12310
12311 if (build > 0) {
12312 tp->fw_ver[8] = 'a' + build - 1;
12313 tp->fw_ver[9] = '\0';
12314 }
12315}
12316
acd9c119 12317static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12318{
12319 u32 val, offset, start;
acd9c119 12320 int i, vlen;
9c8a620e
MC		 12321
12322 for (offset = TG3_NVM_DIR_START;
12323 offset < TG3_NVM_DIR_END;
12324 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12325 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12326 return;
12327
9c8a620e
MC		 12328 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12329 break;
12330 }
12331
12332 if (offset == TG3_NVM_DIR_END)
12333 return;
12334
12335 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12336 start = 0x08000000;
e4f34110 12337 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12338 return;
12339
e4f34110 12340 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12341 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12342 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12343 return;
12344
12345 offset += val - start;
12346
acd9c119 12347 vlen = strlen(tp->fw_ver);
9c8a620e 12348
acd9c119
MC		 12349 tp->fw_ver[vlen++] = ',';
12350 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12351
12352 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12353 __be32 v;
12354 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12355 return;
12356
b9fc7dc5 12357 offset += sizeof(v);
c4e6575c 12358
acd9c119
MC		 12359 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12360 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12361 break;
c4e6575c 12362 }
9c8a620e 12363
acd9c119
MC		 12364 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12365 vlen += sizeof(v);
c4e6575c 12366 }
acd9c119
MC		 12367}
12368
7fd76445
MC		 12369static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12370{
12371 int vlen;
12372 u32 apedata;
12373
12374 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12375 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12376 return;
12377
12378 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12379 if (apedata != APE_SEG_SIG_MAGIC)
12380 return;
12381
12382 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12383 if (!(apedata & APE_FW_STATUS_READY))
12384 return;
12385
12386 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12387
12388 vlen = strlen(tp->fw_ver);
12389
12390 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12391 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12392 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12393 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12394 (apedata & APE_FW_VERSION_BLDMSK));
12395}
12396
acd9c119
MC		 12397static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12398{
12399 u32 val;
12400
df259d8c
MC		 12401 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12402 tp->fw_ver[0] = 's';
12403 tp->fw_ver[1] = 'b';
12404 tp->fw_ver[2] = '\0';
12405
12406 return;
12407 }
12408
acd9c119
MC		 12409 if (tg3_nvram_read(tp, 0, &val))
12410 return;
12411
12412 if (val == TG3_EEPROM_MAGIC)
12413 tg3_read_bc_ver(tp);
12414 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12415 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12416 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12417 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12418 else
12419 return;
12420
12421 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12422 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12423 return;
12424
12425 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12426
12427 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12428}
12429
7544b097
MC		 12430static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12431
1da177e4
LT		 12432static int __devinit tg3_get_invariants(struct tg3 *tp)
12433{
12434 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12435 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12436 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12437 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12438 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12439 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12440 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12441 { },
12442 };
12443 u32 misc_ctrl_reg;
1da177e4
LT		 12444 u32 pci_state_reg, grc_misc_cfg;
12445 u32 val;
12446 u16 pci_cmd;
5e7dfd0f 12447 int err;
1da177e4 12448
1da177e4
LT		 12449 /* Force memory write invalidate off. If we leave it on,
12450 * then on 5700_BX chips we have to enable a workaround.
12451 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12452 * to match the cacheline size. The Broadcom driver have this
12453 * workaround but turns MWI off all the times so never uses
12454 * it. This seems to suggest that the workaround is insufficient.
12455 */
12456 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12457 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12458 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12459
12460 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12461 * has the register indirect write enable bit set before
12462 * we try to access any of the MMIO registers. It is also
12463 * critical that the PCI-X hw workaround situation is decided
12464 * before that as well.
12465 */
12466 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12467 &misc_ctrl_reg);
12468
12469 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12470 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12472 u32 prod_id_asic_rev;
12473
f6eb9b1f
MC		 12474 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12476 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12477 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12478 pci_read_config_dword(tp->pdev,
12479 TG3PCI_GEN2_PRODID_ASICREV,
12480 &prod_id_asic_rev);
12481 else
12482 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12483 &prod_id_asic_rev);
12484
321d32a0 12485 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12486 }
1da177e4 12487
ff645bec
MC		 12488 /* Wrong chip ID in 5752 A0. This code can be removed later
12489 * as A0 is not in production.
12490 */
12491 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12492 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12493
6892914f
MC		 12494 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12495 * we need to disable memory and use config. cycles
12496 * only to access all registers. The 5702/03 chips
12497 * can mistakenly decode the special cycles from the
12498 * ICH chipsets as memory write cycles, causing corruption
12499 * of register and memory space. Only certain ICH bridges
12500 * will drive special cycles with non-zero data during the
12501 * address phase which can fall within the 5703's address
12502 * range. This is not an ICH bug as the PCI spec allows
12503 * non-zero address during special cycles. However, only
12504 * these ICH bridges are known to drive non-zero addresses
12505 * during special cycles.
12506 *
12507 * Since special cycles do not cross PCI bridges, we only
12508 * enable this workaround if the 5703 is on the secondary
12509 * bus of these ICH bridges.
12510 */
12511 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12512 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12513 static struct tg3_dev_id {
12514 u32 vendor;
12515 u32 device;
12516 u32 rev;
12517 } ich_chipsets[] = {
12518 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12519 PCI_ANY_ID },
12520 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12521 PCI_ANY_ID },
12522 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12523 0xa },
12524 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12525 PCI_ANY_ID },
12526 { },
12527 };
12528 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12529 struct pci_dev *bridge = NULL;
12530
12531 while (pci_id->vendor != 0) {
12532 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12533 bridge);
12534 if (!bridge) {
12535 pci_id++;
12536 continue;
12537 }
12538 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12539 if (bridge->revision > pci_id->rev)
6892914f
MC		 12540 continue;
12541 }
12542 if (bridge->subordinate &&
12543 (bridge->subordinate->number ==
12544 tp->pdev->bus->number)) {
12545
12546 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12547 pci_dev_put(bridge);
12548 break;
12549 }
12550 }
12551 }
12552
41588ba1
MC		 12553 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12554 static struct tg3_dev_id {
12555 u32 vendor;
12556 u32 device;
12557 } bridge_chipsets[] = {
12558 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12559 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12560 { },
12561 };
12562 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12563 struct pci_dev *bridge = NULL;
12564
12565 while (pci_id->vendor != 0) {
12566 bridge = pci_get_device(pci_id->vendor,
12567 pci_id->device,
12568 bridge);
12569 if (!bridge) {
12570 pci_id++;
12571 continue;
12572 }
12573 if (bridge->subordinate &&
12574 (bridge->subordinate->number <=
12575 tp->pdev->bus->number) &&
12576 (bridge->subordinate->subordinate >=
12577 tp->pdev->bus->number)) {
12578 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12579 pci_dev_put(bridge);
12580 break;
12581 }
12582 }
12583 }
12584
4a29cc2e
MC		 12585 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12586 * DMA addresses > 40-bit. This bridge may have other additional
12587 * 57xx devices behind it in some 4-port NIC designs for example.
12588 * Any tg3 device found behind the bridge will also need the 40-bit
12589 * DMA workaround.
12590 */
a4e2b347
MC		 12591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12592 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12593 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12594 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12595 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12596 }
4a29cc2e
MC		 12597 else {
12598 struct pci_dev *bridge = NULL;
12599
12600 do {
12601 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12602 PCI_DEVICE_ID_SERVERWORKS_EPB,
12603 bridge);
12604 if (bridge && bridge->subordinate &&
12605 (bridge->subordinate->number <=
12606 tp->pdev->bus->number) &&
12607 (bridge->subordinate->subordinate >=
12608 tp->pdev->bus->number)) {
12609 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12610 pci_dev_put(bridge);
12611 break;
12612 }
12613 } while (bridge);
12614 }
4cf78e4f 12615
1da177e4
LT		 12616 /* Initialize misc host control in PCI block. */
12617 tp->misc_host_ctrl |= (misc_ctrl_reg &
12618 MISC_HOST_CTRL_CHIPREV);
12619 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12620 tp->misc_host_ctrl);
12621
f6eb9b1f
MC		 12622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12624 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12625 tp->pdev_peer = tg3_find_peer(tp);
12626
321d32a0
MC		 12627 /* Intentionally exclude ASIC_REV_5906 */
12628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12635 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12636
12637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12640 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12641 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12642 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12643
1b440c56
JL		 12644 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12645 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12646 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12647
027455ad
MC		 12648 /* 5700 B0 chips do not support checksumming correctly due
12649 * to hardware bugs.
12650 */
12651 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12652 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12653 else {
12654 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12655 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12656 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12657 tp->dev->features |= NETIF_F_IPV6_CSUM;
12658 }
12659
5a6f3074 12660 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12661 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12662 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12663 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12664 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12665 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12666 tp->pdev_peer == tp->pdev))
12667 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12668
321d32a0 12669 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12670 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12671 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12672 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12673 } else {
7f62ad5d 12674 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12675 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12676 ASIC_REV_5750 &&
12677 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12678 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12679 }
5a6f3074 12680 }
1da177e4 12681
4f125f42
MC		 12682 tp->irq_max = 1;
12683
f6eb9b1f
MC		 12684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12685 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12686 tp->irq_max = TG3_IRQ_MAX_VECS;
12687 }
0e1406dd
MC		 12688
12689 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
92c6b8d1
MC		 12690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12691 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12692 else {
12693 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12694 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12695 }
0e1406dd 12696 }
f6eb9b1f 12697
f51f3562 12698 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12699 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12701 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12702
52f4490c
MC		 12703 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12704 &pci_state_reg);
12705
5e7dfd0f
MC		 12706 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12707 if (tp->pcie_cap != 0) {
12708 u16 lnkctl;
12709
1da177e4 12710 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12711
12712 pcie_set_readrq(tp->pdev, 4096);
12713
5e7dfd0f
MC		 12714 pci_read_config_word(tp->pdev,
12715 tp->pcie_cap + PCI_EXP_LNKCTL,
12716 &lnkctl);
12717 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12719 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12721 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12722 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12723 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12724 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12725 }
52f4490c 12726 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12727 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12728 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12729 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12730 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12731 if (!tp->pcix_cap) {
12732 printk(KERN_ERR PFX "Cannot find PCI-X "
12733 "capability, aborting.\n");
12734 return -EIO;
12735 }
12736
12737 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12738 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12739 }
1da177e4 12740
399de50b
MC		 12741 /* If we have an AMD 762 or VIA K8T800 chipset, write
12742 * reordering to the mailbox registers done by the host
12743 * controller can cause major troubles. We read back from
12744 * every mailbox register write to force the writes to be
12745 * posted to the chip in order.
12746 */
12747 if (pci_dev_present(write_reorder_chipsets) &&
12748 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12749 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12750
69fc4053
MC		 12751 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12752 &tp->pci_cacheline_sz);
12753 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12754 &tp->pci_lat_timer);
1da177e4
LT		 12755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12756 tp->pci_lat_timer < 64) {
12757 tp->pci_lat_timer = 64;
69fc4053
MC		 12758 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12759 tp->pci_lat_timer);
1da177e4
LT		 12760 }
12761
52f4490c
MC		 12762 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12763 /* 5700 BX chips need to have their TX producer index
12764 * mailboxes written twice to workaround a bug.
12765 */
12766 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12767
52f4490c 12768 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12769 *
12770 * The workaround is to use indirect register accesses
12771 * for all chip writes not to mailbox registers.
12772 */
52f4490c 12773 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12774 u32 pm_reg;
1da177e4
LT		 12775
12776 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12777
12778 /* The chip can have it's power management PCI config
12779 * space registers clobbered due to this bug.
12780 * So explicitly force the chip into D0 here.
12781 */
9974a356
MC		 12782 pci_read_config_dword(tp->pdev,
12783 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12784 &pm_reg);
12785 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12786 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12787 pci_write_config_dword(tp->pdev,
12788 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12789 pm_reg);
12790
12791 /* Also, force SERR#/PERR# in PCI command. */
12792 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12793 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12794 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12795 }
12796 }
12797
1da177e4
LT		 12798 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12799 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12800 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12801 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12802
12803 /* Chip-specific fixup from Broadcom driver */
12804 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12805 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12806 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12807 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12808 }
12809
1ee582d8 12810 /* Default fast path register access methods */
20094930 12811 tp->read32 = tg3_read32;
1ee582d8 12812 tp->write32 = tg3_write32;
09ee929c 12813 tp->read32_mbox = tg3_read32;
20094930 12814 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12815 tp->write32_tx_mbox = tg3_write32;
12816 tp->write32_rx_mbox = tg3_write32;
12817
12818 /* Various workaround register access methods */
12819 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12820 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12821 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12822 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12823 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12824 /*
12825 * Back to back register writes can cause problems on these
12826 * chips, the workaround is to read back all reg writes
12827 * except those to mailbox regs.
12828 *
12829 * See tg3_write_indirect_reg32().
12830 */
1ee582d8 12831 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12832 }
12833
1ee582d8
MC		 12834 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12835 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12836 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12837 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12838 tp->write32_rx_mbox = tg3_write_flush_reg32;
12839 }
20094930 12840
6892914f
MC		 12841 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12842 tp->read32 = tg3_read_indirect_reg32;
12843 tp->write32 = tg3_write_indirect_reg32;
12844 tp->read32_mbox = tg3_read_indirect_mbox;
12845 tp->write32_mbox = tg3_write_indirect_mbox;
12846 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12847 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12848
12849 iounmap(tp->regs);
22abe310 12850 tp->regs = NULL;
6892914f
MC		 12851
12852 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12853 pci_cmd &= ~PCI_COMMAND_MEMORY;
12854 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12855 }
b5d3772c
MC		 12856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12857 tp->read32_mbox = tg3_read32_mbox_5906;
12858 tp->write32_mbox = tg3_write32_mbox_5906;
12859 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12860 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12861 }
6892914f 12862
bbadf503
MC		 12863 if (tp->write32 == tg3_write_indirect_reg32 ||
12864 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12865 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12867 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12868
7d0c41ef 12869 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12870 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12871 * determined before calling tg3_set_power_state() so that
12872 * we know whether or not to switch out of Vaux power.
12873 * When the flag is set, it means that GPIO1 is used for eeprom
12874 * write protect and also implies that it is a LOM where GPIOs
12875 * are not used to switch power.
6aa20a22 12876 */
7d0c41ef
MC		 12877 tg3_get_eeprom_hw_cfg(tp);
12878
0d3031d9
MC		 12879 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12880 /* Allow reads and writes to the
12881 * APE register and memory space.
12882 */
12883 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12884 PCISTATE_ALLOW_APE_SHMEM_WR;
12885 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12886 pci_state_reg);
12887 }
12888
9936bcf6 12889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12894 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12895
314fba34
MC		 12896 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12897 * GPIO1 driven high will bring 5700's external PHY out of reset.
12898 * It is also used as eeprom write protect on LOMs.
12899 */
12900 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12901 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12902 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12903 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12904 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12905 /* Unused GPIO3 must be driven as output on 5752 because there
12906 * are no pull-up resistors on unused GPIO pins.
12907 */
12908 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12909 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12910
321d32a0
MC		 12911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12912 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12913 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12914
8d519ab2
MC		 12915 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12916 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12917 /* Turn off the debug UART. */
12918 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12919 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12920 /* Keep VMain power. */
12921 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12922 GRC_LCLCTRL_GPIO_OUTPUT0;
12923 }
12924
1da177e4 12925 /* Force the chip into D0. */
bc1c7567 12926 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12927 if (err) {
12928 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12929 pci_name(tp->pdev));
12930 return err;
12931 }
12932
1da177e4
LT		 12933 /* Derive initial jumbo mode from MTU assigned in
12934 * ether_setup() via the alloc_etherdev() call
12935 */
0f893dc6 12936 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12937 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12938 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12939
12940 /* Determine WakeOnLan speed to use. */
12941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12942 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12943 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12944 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12945 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12946 } else {
12947 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12948 }
12949
7f97a4bd
MC		 12950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12951 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12952
1da177e4
LT		 12953 /* A few boards don't want Ethernet@WireSpeed phy feature */
12954 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12955 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12956 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12957 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12958 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12959 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12960 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12961
12962 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12963 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12964 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12965 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12966 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12967
321d32a0 12968 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12969 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 12970 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 12971 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12972 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 12973 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12977 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12978 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12979 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12980 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12981 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12982 } else
c424cb24
MC		 12983 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12984 }
1da177e4 12985
b2a5c19c
MC		 12986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12987 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12988 tp->phy_otp = tg3_read_otp_phycfg(tp);
12989 if (tp->phy_otp == 0)
12990 tp->phy_otp = TG3_OTP_DEFAULT;
12991 }
12992
f51f3562 12993 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12994 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12995 else
12996 tp->mi_mode = MAC_MI_MODE_BASE;
12997
1da177e4 12998 tp->coalesce_mode = 0;
1da177e4
LT		 12999 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13000 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13001 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13002
321d32a0
MC		 13003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13004 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13005 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13006
158d7abd
MC		 13007 err = tg3_mdio_init(tp);
13008 if (err)
13009 return err;
1da177e4
LT		 13010
13011 /* Initialize data/descriptor byte/word swapping. */
13012 val = tr32(GRC_MODE);
13013 val &= GRC_MODE_HOST_STACKUP;
13014 tw32(GRC_MODE, val | tp->grc_mode);
13015
13016 tg3_switch_clocks(tp);
13017
13018 /* Clear this out for sanity. */
13019 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13020
13021 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13022 &pci_state_reg);
13023 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13024 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13025 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13026
13027 if (chiprevid == CHIPREV_ID_5701_A0 ||
13028 chiprevid == CHIPREV_ID_5701_B0 ||
13029 chiprevid == CHIPREV_ID_5701_B2 ||
13030 chiprevid == CHIPREV_ID_5701_B5) {
13031 void __iomem *sram_base;
13032
13033 /* Write some dummy words into the SRAM status block
13034 * area, see if it reads back correctly. If the return
13035 * value is bad, force enable the PCIX workaround.
13036 */
13037 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13038
13039 writel(0x00000000, sram_base);
13040 writel(0x00000000, sram_base + 4);
13041 writel(0xffffffff, sram_base + 4);
13042 if (readl(sram_base) != 0x00000000)
13043 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13044 }
13045 }
13046
13047 udelay(50);
13048 tg3_nvram_init(tp);
13049
13050 grc_misc_cfg = tr32(GRC_MISC_CFG);
13051 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13052
1da177e4
LT		 13053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13054 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13055 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13056 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13057
fac9b83e
DM		 13058 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13059 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13060 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13061 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13062 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13063 HOSTCC_MODE_CLRTICK_TXBD);
13064
13065 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13066 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13067 tp->misc_host_ctrl);
13068 }
13069
3bda1258
MC		 13070 /* Preserve the APE MAC_MODE bits */
13071 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13072 tp->mac_mode = tr32(MAC_MODE) |
13073 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13074 else
13075 tp->mac_mode = TG3_DEF_MAC_MODE;
13076
1da177e4
LT		 13077 /* these are limited to 10/100 only */
13078 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13079 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13080 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13081 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13082 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13083 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13084 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13085 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13086 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13087 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13088 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13089 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13090 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13091 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13092
13093 err = tg3_phy_probe(tp);
13094 if (err) {
13095 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13096 pci_name(tp->pdev), err);
13097 /* ... but do not return immediately ... */
b02fd9e3 13098 tg3_mdio_fini(tp);
1da177e4
LT		 13099 }
13100
13101 tg3_read_partno(tp);
c4e6575c 13102 tg3_read_fw_ver(tp);
1da177e4
LT		 13103
13104 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13105 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13106 } else {
13107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13108 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13109 else
13110 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13111 }
13112
13113 /* 5700 {AX,BX} chips have a broken status block link
13114 * change bit implementation, so we must use the
13115 * status register in those cases.
13116 */
13117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13118 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13119 else
13120 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13121
13122 /* The led_ctrl is set during tg3_phy_probe, here we might
13123 * have to force the link status polling mechanism based
13124 * upon subsystem IDs.
13125 */
13126 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13128 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13129 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13130 TG3_FLAG_USE_LINKCHG_REG);
13131 }
13132
13133 /* For all SERDES we poll the MAC status register. */
13134 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13135 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13136 else
13137 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13138
ad829268 13139 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13141 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13142 tp->rx_offset = 0;
13143
f92905de
MC		 13144 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13145
13146 /* Increment the rx prod index on the rx std ring by at most
13147 * 8 for these chips to workaround hw errata.
13148 */
13149 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13152 tp->rx_std_max_post = 8;
13153
8ed5d97e
MC		 13154 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13155 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13156 PCIE_PWR_MGMT_L1_THRESH_MSK;
13157
1da177e4
LT		 13158 return err;
13159}
13160
49b6e95f 13161#ifdef CONFIG_SPARC
1da177e4
LT		 13162static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13163{
13164 struct net_device *dev = tp->dev;
13165 struct pci_dev *pdev = tp->pdev;
49b6e95f 13166 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13167 const unsigned char *addr;
49b6e95f
DM		 13168 int len;
13169
13170 addr = of_get_property(dp, "local-mac-address", &len);
13171 if (addr && len == 6) {
13172 memcpy(dev->dev_addr, addr, 6);
13173 memcpy(dev->perm_addr, dev->dev_addr, 6);
13174 return 0;
1da177e4
LT		 13175 }
13176 return -ENODEV;
13177}
13178
13179static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13180{
13181 struct net_device *dev = tp->dev;
13182
13183 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13184 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13185 return 0;
13186}
13187#endif
13188
13189static int __devinit tg3_get_device_address(struct tg3 *tp)
13190{
13191 struct net_device *dev = tp->dev;
13192 u32 hi, lo, mac_offset;
008652b3 13193 int addr_ok = 0;
1da177e4 13194
49b6e95f 13195#ifdef CONFIG_SPARC
1da177e4
LT		 13196 if (!tg3_get_macaddr_sparc(tp))
13197 return 0;
13198#endif
13199
13200 mac_offset = 0x7c;
f49639e6 13201 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13202 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13203 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13204 mac_offset = 0xcc;
13205 if (tg3_nvram_lock(tp))
13206 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13207 else
13208 tg3_nvram_unlock(tp);
a1b950d5
MC		 13209 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13210 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13211 mac_offset = 0xcc;
13212 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13213 mac_offset = 0x10;
1da177e4
LT		 13214
13215 /* First try to get it from MAC address mailbox. */
13216 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13217 if ((hi >> 16) == 0x484b) {
13218 dev->dev_addr[0] = (hi >> 8) & 0xff;
13219 dev->dev_addr[1] = (hi >> 0) & 0xff;
13220
13221 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13222 dev->dev_addr[2] = (lo >> 24) & 0xff;
13223 dev->dev_addr[3] = (lo >> 16) & 0xff;
13224 dev->dev_addr[4] = (lo >> 8) & 0xff;
13225 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13226
008652b3
MC		 13227 /* Some old bootcode may report a 0 MAC address in SRAM */
13228 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13229 }
13230 if (!addr_ok) {
13231 /* Next, try NVRAM. */
df259d8c
MC		 13232 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13233 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13234 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13235 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13236 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13237 }
13238 /* Finally just fetch it out of the MAC control regs. */
13239 else {
13240 hi = tr32(MAC_ADDR_0_HIGH);
13241 lo = tr32(MAC_ADDR_0_LOW);
13242
13243 dev->dev_addr[5] = lo & 0xff;
13244 dev->dev_addr[4] = (lo >> 8) & 0xff;
13245 dev->dev_addr[3] = (lo >> 16) & 0xff;
13246 dev->dev_addr[2] = (lo >> 24) & 0xff;
13247 dev->dev_addr[1] = hi & 0xff;
13248 dev->dev_addr[0] = (hi >> 8) & 0xff;
13249 }
1da177e4
LT		 13250 }
13251
13252 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13253#ifdef CONFIG_SPARC
1da177e4
LT		 13254 if (!tg3_get_default_macaddr_sparc(tp))
13255 return 0;
13256#endif
13257 return -EINVAL;
13258 }
2ff43697 13259 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13260 return 0;
13261}
13262
59e6b434
DM		 13263#define BOUNDARY_SINGLE_CACHELINE 1
13264#define BOUNDARY_MULTI_CACHELINE 2
13265
13266static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13267{
13268 int cacheline_size;
13269 u8 byte;
13270 int goal;
13271
13272 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13273 if (byte == 0)
13274 cacheline_size = 1024;
13275 else
13276 cacheline_size = (int) byte * 4;
13277
13278 /* On 5703 and later chips, the boundary bits have no
13279 * effect.
13280 */
13281 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13282 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13283 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13284 goto out;
13285
13286#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13287 goal = BOUNDARY_MULTI_CACHELINE;
13288#else
13289#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13290 goal = BOUNDARY_SINGLE_CACHELINE;
13291#else
13292 goal = 0;
13293#endif
13294#endif
13295
13296 if (!goal)
13297 goto out;
13298
13299 /* PCI controllers on most RISC systems tend to disconnect
13300 * when a device tries to burst across a cache-line boundary.
13301 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13302 *
13303 * Unfortunately, for PCI-E there are only limited
13304 * write-side controls for this, and thus for reads
13305 * we will still get the disconnects. We'll also waste
13306 * these PCI cycles for both read and write for chips
13307 * other than 5700 and 5701 which do not implement the
13308 * boundary bits.
13309 */
13310 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13311 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13312 switch (cacheline_size) {
13313 case 16:
13314 case 32:
13315 case 64:
13316 case 128:
13317 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13318 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13319 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13320 } else {
13321 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13322 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13323 }
13324 break;
13325
13326 case 256:
13327 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13328 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13329 break;
13330
13331 default:
13332 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13333 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13334 break;
855e1111 13335 }
59e6b434
DM		 13336 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13337 switch (cacheline_size) {
13338 case 16:
13339 case 32:
13340 case 64:
13341 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13342 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13343 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13344 break;
13345 }
13346 /* fallthrough */
13347 case 128:
13348 default:
13349 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13350 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13351 break;
855e1111 13352 }
59e6b434
DM		 13353 } else {
13354 switch (cacheline_size) {
13355 case 16:
13356 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13357 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13358 DMA_RWCTRL_WRITE_BNDRY_16);
13359 break;
13360 }
13361 /* fallthrough */
13362 case 32:
13363 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13364 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13365 DMA_RWCTRL_WRITE_BNDRY_32);
13366 break;
13367 }
13368 /* fallthrough */
13369 case 64:
13370 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13371 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13372 DMA_RWCTRL_WRITE_BNDRY_64);
13373 break;
13374 }
13375 /* fallthrough */
13376 case 128:
13377 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13378 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13379 DMA_RWCTRL_WRITE_BNDRY_128);
13380 break;
13381 }
13382 /* fallthrough */
13383 case 256:
13384 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13385 DMA_RWCTRL_WRITE_BNDRY_256);
13386 break;
13387 case 512:
13388 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13389 DMA_RWCTRL_WRITE_BNDRY_512);
13390 break;
13391 case 1024:
13392 default:
13393 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13394 DMA_RWCTRL_WRITE_BNDRY_1024);
13395 break;
855e1111 13396 }
59e6b434
DM		 13397 }
13398
13399out:
13400 return val;
13401}
13402
1da177e4
LT		 13403static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13404{
13405 struct tg3_internal_buffer_desc test_desc;
13406 u32 sram_dma_descs;
13407 int i, ret;
13408
13409 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13410
13411 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13412 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13413 tw32(RDMAC_STATUS, 0);
13414 tw32(WDMAC_STATUS, 0);
13415
13416 tw32(BUFMGR_MODE, 0);
13417 tw32(FTQ_RESET, 0);
13418
13419 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13420 test_desc.addr_lo = buf_dma & 0xffffffff;
13421 test_desc.nic_mbuf = 0x00002100;
13422 test_desc.len = size;
13423
13424 /*
13425 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13426 * the *second* time the tg3 driver was getting loaded after an
13427 * initial scan.
13428 *
13429 * Broadcom tells me:
13430 * ...the DMA engine is connected to the GRC block and a DMA
13431 * reset may affect the GRC block in some unpredictable way...
13432 * The behavior of resets to individual blocks has not been tested.
13433 *
13434 * Broadcom noted the GRC reset will also reset all sub-components.
13435 */
13436 if (to_device) {
13437 test_desc.cqid_sqid = (13 << 8) | 2;
13438
13439 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13440 udelay(40);
13441 } else {
13442 test_desc.cqid_sqid = (16 << 8) | 7;
13443
13444 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13445 udelay(40);
13446 }
13447 test_desc.flags = 0x00000005;
13448
13449 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13450 u32 val;
13451
13452 val = *(((u32 *)&test_desc) + i);
13453 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13454 sram_dma_descs + (i * sizeof(u32)));
13455 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13456 }
13457 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13458
13459 if (to_device) {
13460 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13461 } else {
13462 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13463 }
13464
13465 ret = -ENODEV;
13466 for (i = 0; i < 40; i++) {
13467 u32 val;
13468
13469 if (to_device)
13470 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13471 else
13472 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13473 if ((val & 0xffff) == sram_dma_descs) {
13474 ret = 0;
13475 break;
13476 }
13477
13478 udelay(100);
13479 }
13480
13481 return ret;
13482}
13483
ded7340d 13484#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13485
13486static int __devinit tg3_test_dma(struct tg3 *tp)
13487{
13488 dma_addr_t buf_dma;
59e6b434 13489 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13490 int ret;
13491
13492 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13493 if (!buf) {
13494 ret = -ENOMEM;
13495 goto out_nofree;
13496 }
13497
13498 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13499 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13500
59e6b434 13501 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13502
13503 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13504 /* DMA read watermark not used on PCIE */
13505 tp->dma_rwctrl |= 0x00180000;
13506 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13509 tp->dma_rwctrl |= 0x003f0000;
13510 else
13511 tp->dma_rwctrl |= 0x003f000f;
13512 } else {
13513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13515 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13516 u32 read_water = 0x7;
1da177e4 13517
4a29cc2e
MC		 13518 /* If the 5704 is behind the EPB bridge, we can
13519 * do the less restrictive ONE_DMA workaround for
13520 * better performance.
13521 */
13522 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13524 tp->dma_rwctrl |= 0x8000;
13525 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13526 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13527
49afdeb6
MC		 13528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13529 read_water = 4;
59e6b434 13530 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13531 tp->dma_rwctrl |=
13532 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13533 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13534 (1 << 23);
4cf78e4f
MC		 13535 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13536 /* 5780 always in PCIX mode */
13537 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13538 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13539 /* 5714 always in PCIX mode */
13540 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13541 } else {
13542 tp->dma_rwctrl |= 0x001b000f;
13543 }
13544 }
13545
13546 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13548 tp->dma_rwctrl &= 0xfffffff0;
13549
13550 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13552 /* Remove this if it causes problems for some boards. */
13553 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13554
13555 /* On 5700/5701 chips, we need to set this bit.
13556 * Otherwise the chip will issue cacheline transactions
13557 * to streamable DMA memory with not all the byte
13558 * enables turned on. This is an error on several
13559 * RISC PCI controllers, in particular sparc64.
13560 *
13561 * On 5703/5704 chips, this bit has been reassigned
13562 * a different meaning. In particular, it is used
13563 * on those chips to enable a PCI-X workaround.
13564 */
13565 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13566 }
13567
13568 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13569
13570#if 0
13571 /* Unneeded, already done by tg3_get_invariants. */
13572 tg3_switch_clocks(tp);
13573#endif
13574
13575 ret = 0;
13576 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13577 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13578 goto out;
13579
59e6b434
DM		 13580 /* It is best to perform DMA test with maximum write burst size
13581 * to expose the 5700/5701 write DMA bug.
13582 */
13583 saved_dma_rwctrl = tp->dma_rwctrl;
13584 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13585 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13586
1da177e4
LT		 13587 while (1) {
13588 u32 *p = buf, i;
13589
13590 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13591 p[i] = i;
13592
13593 /* Send the buffer to the chip. */
13594 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13595 if (ret) {
13596 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13597 break;
13598 }
13599
13600#if 0
13601 /* validate data reached card RAM correctly. */
13602 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13603 u32 val;
13604 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13605 if (le32_to_cpu(val) != p[i]) {
13606 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13607 /* ret = -ENODEV here? */
13608 }
13609 p[i] = 0;
13610 }
13611#endif
13612 /* Now read it back. */
13613 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13614 if (ret) {
13615 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13616
13617 break;
13618 }
13619
13620 /* Verify it. */
13621 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13622 if (p[i] == i)
13623 continue;
13624
59e6b434
DM		 13625 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13626 DMA_RWCTRL_WRITE_BNDRY_16) {
13627 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13628 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13629 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13630 break;
13631 } else {
13632 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13633 ret = -ENODEV;
13634 goto out;
13635 }
13636 }
13637
13638 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13639 /* Success. */
13640 ret = 0;
13641 break;
13642 }
13643 }
59e6b434
DM		 13644 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13645 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13646 static struct pci_device_id dma_wait_state_chipsets[] = {
13647 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13648 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13649 { },
13650 };
13651
59e6b434 13652 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13653 * now look for chipsets that are known to expose the
13654 * DMA bug without failing the test.
59e6b434 13655 */
6d1cfbab
MC		 13656 if (pci_dev_present(dma_wait_state_chipsets)) {
13657 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13658 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13659 }
13660 else
13661 /* Safe to use the calculated DMA boundary. */
13662 tp->dma_rwctrl = saved_dma_rwctrl;
13663
59e6b434
DM		 13664 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13665 }
1da177e4
LT		 13666
13667out:
13668 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13669out_nofree:
13670 return ret;
13671}
13672
13673static void __devinit tg3_init_link_config(struct tg3 *tp)
13674{
13675 tp->link_config.advertising =
13676 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13677 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13678 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13679 ADVERTISED_Autoneg | ADVERTISED_MII);
13680 tp->link_config.speed = SPEED_INVALID;
13681 tp->link_config.duplex = DUPLEX_INVALID;
13682 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13683 tp->link_config.active_speed = SPEED_INVALID;
13684 tp->link_config.active_duplex = DUPLEX_INVALID;
13685 tp->link_config.phy_is_low_power = 0;
13686 tp->link_config.orig_speed = SPEED_INVALID;
13687 tp->link_config.orig_duplex = DUPLEX_INVALID;
13688 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13689}
13690
13691static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13692{
f6eb9b1f
MC		 13693 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13694 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13695 tp->bufmgr_config.mbuf_read_dma_low_water =
13696 DEFAULT_MB_RDMA_LOW_WATER_5705;
13697 tp->bufmgr_config.mbuf_mac_rx_low_water =
13698 DEFAULT_MB_MACRX_LOW_WATER_5705;
13699 tp->bufmgr_config.mbuf_high_water =
13700 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13702 tp->bufmgr_config.mbuf_mac_rx_low_water =
13703 DEFAULT_MB_MACRX_LOW_WATER_5906;
13704 tp->bufmgr_config.mbuf_high_water =
13705 DEFAULT_MB_HIGH_WATER_5906;
13706 }
fdfec172
MC		 13707
13708 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13709 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13710 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13711 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13712 tp->bufmgr_config.mbuf_high_water_jumbo =
13713 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13714 } else {
13715 tp->bufmgr_config.mbuf_read_dma_low_water =
13716 DEFAULT_MB_RDMA_LOW_WATER;
13717 tp->bufmgr_config.mbuf_mac_rx_low_water =
13718 DEFAULT_MB_MACRX_LOW_WATER;
13719 tp->bufmgr_config.mbuf_high_water =
13720 DEFAULT_MB_HIGH_WATER;
13721
13722 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13723 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13724 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13725 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13726 tp->bufmgr_config.mbuf_high_water_jumbo =
13727 DEFAULT_MB_HIGH_WATER_JUMBO;
13728 }
1da177e4
LT		 13729
13730 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13731 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13732}
13733
13734static char * __devinit tg3_phy_string(struct tg3 *tp)
13735{
13736 switch (tp->phy_id & PHY_ID_MASK) {
13737 case PHY_ID_BCM5400: return "5400";
13738 case PHY_ID_BCM5401: return "5401";
13739 case PHY_ID_BCM5411: return "5411";
13740 case PHY_ID_BCM5701: return "5701";
13741 case PHY_ID_BCM5703: return "5703";
13742 case PHY_ID_BCM5704: return "5704";
13743 case PHY_ID_BCM5705: return "5705";
13744 case PHY_ID_BCM5750: return "5750";
85e94ced 13745 case PHY_ID_BCM5752: return "5752";
a4e2b347 13746 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13747 case PHY_ID_BCM5780: return "5780";
af36e6b6 13748 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13749 case PHY_ID_BCM5787: return "5787";
d30cdd28 13750 case PHY_ID_BCM5784: return "5784";
126a3368 13751 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13752 case PHY_ID_BCM5906: return "5906";
9936bcf6 13753 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13754 case PHY_ID_BCM8002: return "8002/serdes";
13755 case 0: return "serdes";
13756 default: return "unknown";
855e1111 13757 }
1da177e4
LT		 13758}
13759
f9804ddb
MC		 13760static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13761{
13762 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13763 strcpy(str, "PCI Express");
13764 return str;
13765 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13766 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13767
13768 strcpy(str, "PCIX:");
13769
13770 if ((clock_ctrl == 7) ||
13771 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13772 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13773 strcat(str, "133MHz");
13774 else if (clock_ctrl == 0)
13775 strcat(str, "33MHz");
13776 else if (clock_ctrl == 2)
13777 strcat(str, "50MHz");
13778 else if (clock_ctrl == 4)
13779 strcat(str, "66MHz");
13780 else if (clock_ctrl == 6)
13781 strcat(str, "100MHz");
f9804ddb
MC		 13782 } else {
13783 strcpy(str, "PCI:");
13784 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13785 strcat(str, "66MHz");
13786 else
13787 strcat(str, "33MHz");
13788 }
13789 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13790 strcat(str, ":32-bit");
13791 else
13792 strcat(str, ":64-bit");
13793 return str;
13794}
13795
8c2dc7e1 13796static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13797{
13798 struct pci_dev *peer;
13799 unsigned int func, devnr = tp->pdev->devfn & ~7;
13800
13801 for (func = 0; func < 8; func++) {
13802 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13803 if (peer && peer != tp->pdev)
13804 break;
13805 pci_dev_put(peer);
13806 }
16fe9d74
MC		 13807 /* 5704 can be configured in single-port mode, set peer to
13808 * tp->pdev in that case.
13809 */
13810 if (!peer) {
13811 peer = tp->pdev;
13812 return peer;
13813 }
1da177e4
LT		 13814
13815 /*
13816 * We don't need to keep the refcount elevated; there's no way
13817 * to remove one half of this device without removing the other
13818 */
13819 pci_dev_put(peer);
13820
13821 return peer;
13822}
13823
15f9850d
DM		 13824static void __devinit tg3_init_coal(struct tg3 *tp)
13825{
13826 struct ethtool_coalesce *ec = &tp->coal;
13827
13828 memset(ec, 0, sizeof(*ec));
13829 ec->cmd = ETHTOOL_GCOALESCE;
13830 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13831 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13832 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13833 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13834 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13835 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13836 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13837 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13838 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13839
13840 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13841 HOSTCC_MODE_CLRTICK_TXBD)) {
13842 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13843 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13844 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13845 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13846 }
d244c892
MC		 13847
13848 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13849 ec->rx_coalesce_usecs_irq = 0;
13850 ec->tx_coalesce_usecs_irq = 0;
13851 ec->stats_block_coalesce_usecs = 0;
13852 }
15f9850d
DM		 13853}
13854
7c7d64b8
SH		 13855static const struct net_device_ops tg3_netdev_ops = {
13856 .ndo_open = tg3_open,
13857 .ndo_stop = tg3_close,
00829823
SH		 13858 .ndo_start_xmit = tg3_start_xmit,
13859 .ndo_get_stats = tg3_get_stats,
13860 .ndo_validate_addr = eth_validate_addr,
13861 .ndo_set_multicast_list = tg3_set_rx_mode,
13862 .ndo_set_mac_address = tg3_set_mac_addr,
13863 .ndo_do_ioctl = tg3_ioctl,
13864 .ndo_tx_timeout = tg3_tx_timeout,
13865 .ndo_change_mtu = tg3_change_mtu,
13866#if TG3_VLAN_TAG_USED
13867 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13868#endif
13869#ifdef CONFIG_NET_POLL_CONTROLLER
13870 .ndo_poll_controller = tg3_poll_controller,
13871#endif
13872};
13873
13874static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13875 .ndo_open = tg3_open,
13876 .ndo_stop = tg3_close,
13877 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13878 .ndo_get_stats = tg3_get_stats,
13879 .ndo_validate_addr = eth_validate_addr,
13880 .ndo_set_multicast_list = tg3_set_rx_mode,
13881 .ndo_set_mac_address = tg3_set_mac_addr,
13882 .ndo_do_ioctl = tg3_ioctl,
13883 .ndo_tx_timeout = tg3_tx_timeout,
13884 .ndo_change_mtu = tg3_change_mtu,
13885#if TG3_VLAN_TAG_USED
13886 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13887#endif
13888#ifdef CONFIG_NET_POLL_CONTROLLER
13889 .ndo_poll_controller = tg3_poll_controller,
13890#endif
13891};
13892
1da177e4
LT		 13893static int __devinit tg3_init_one(struct pci_dev *pdev,
13894 const struct pci_device_id *ent)
13895{
13896 static int tg3_version_printed = 0;
1da177e4
LT		 13897 struct net_device *dev;
13898 struct tg3 *tp;
646c9edd
MC		 13899 int i, err, pm_cap;
13900 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13901 char str[40];
72f2afb8 13902 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13903
13904 if (tg3_version_printed++ == 0)
13905 printk(KERN_INFO "%s", version);
13906
13907 err = pci_enable_device(pdev);
13908 if (err) {
13909 printk(KERN_ERR PFX "Cannot enable PCI device, "
13910 "aborting.\n");
13911 return err;
13912 }
13913
1da177e4
LT		 13914 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13915 if (err) {
13916 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13917 "aborting.\n");
13918 goto err_out_disable_pdev;
13919 }
13920
13921 pci_set_master(pdev);
13922
13923 /* Find power-management capability. */
13924 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13925 if (pm_cap == 0) {
13926 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13927 "aborting.\n");
13928 err = -EIO;
13929 goto err_out_free_res;
13930 }
13931
fe5f5787 13932 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 13933 if (!dev) {
13934 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13935 err = -ENOMEM;
13936 goto err_out_free_res;
13937 }
13938
1da177e4
LT		 13939 SET_NETDEV_DEV(dev, &pdev->dev);
13940
1da177e4
LT		 13941#if TG3_VLAN_TAG_USED
13942 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13943#endif
13944
13945 tp = netdev_priv(dev);
13946 tp->pdev = pdev;
13947 tp->dev = dev;
13948 tp->pm_cap = pm_cap;
1da177e4
LT		 13949 tp->rx_mode = TG3_DEF_RX_MODE;
13950 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13951
1da177e4
LT		 13952 if (tg3_debug > 0)
13953 tp->msg_enable = tg3_debug;
13954 else
13955 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13956
13957 /* The word/byte swap controls here control register access byte
13958 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13959 * setting below.
13960 */
13961 tp->misc_host_ctrl =
13962 MISC_HOST_CTRL_MASK_PCI_INT |
13963 MISC_HOST_CTRL_WORD_SWAP |
13964 MISC_HOST_CTRL_INDIR_ACCESS |
13965 MISC_HOST_CTRL_PCISTATE_RW;
13966
13967 /* The NONFRM (non-frame) byte/word swap controls take effect
13968 * on descriptor entries, anything which isn't packet data.
13969 *
13970 * The StrongARM chips on the board (one for tx, one for rx)
13971 * are running in big-endian mode.
13972 */
13973 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13974 GRC_MODE_WSWAP_NONFRM_DATA);
13975#ifdef __BIG_ENDIAN
13976 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13977#endif
13978 spin_lock_init(&tp->lock);
1da177e4 13979 spin_lock_init(&tp->indirect_lock);
c4028958 13980 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13981
d5fe488a 13982 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13983 if (!tp->regs) {
1da177e4
LT		 13984 printk(KERN_ERR PFX "Cannot map device registers, "
13985 "aborting.\n");
13986 err = -ENOMEM;
13987 goto err_out_free_dev;
13988 }
13989
13990 tg3_init_link_config(tp);
13991
1da177e4
LT		 13992 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13993 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13994
646c9edd
MC		 13995 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13996 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13997 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13998 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13999 struct tg3_napi *tnapi = &tp->napi[i];
14000
14001 tnapi->tp = tp;
14002 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14003
14004 tnapi->int_mbox = intmbx;
14005 if (i < 4)
14006 intmbx += 0x8;
14007 else
14008 intmbx += 0x4;
14009
14010 tnapi->consmbox = rcvmbx;
14011 tnapi->prodmbox = sndmbx;
14012
14013 if (i)
14014 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14015 else
14016 tnapi->coal_now = HOSTCC_MODE_NOW;
14017
14018 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14019 break;
14020
14021 /*
14022 * If we support MSIX, we'll be using RSS. If we're using
14023 * RSS, the first vector only handles link interrupts and the
14024 * remaining vectors handle rx and tx interrupts. Reuse the
14025 * mailbox values for the next iteration. The values we setup
14026 * above are still useful for the single vectored mode.
14027 */
14028 if (!i)
14029 continue;
14030
14031 rcvmbx += 0x8;
14032
14033 if (sndmbx & 0x4)
14034 sndmbx -= 0x4;
14035 else
14036 sndmbx += 0xc;
14037 }
14038
8ef0442f 14039 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 14040 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14041 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14042 dev->irq = pdev->irq;
1da177e4
LT		 14043
14044 err = tg3_get_invariants(tp);
14045 if (err) {
14046 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14047 "aborting.\n");
14048 goto err_out_iounmap;
14049 }
14050
92c6b8d1 14051 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
00829823
SH		 14052 dev->netdev_ops = &tg3_netdev_ops;
14053 else
14054 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14055
14056
4a29cc2e
MC		 14057 /* The EPB bridge inside 5714, 5715, and 5780 and any
14058 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14059 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14060 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14061 * do DMA address check in tg3_start_xmit().
14062 */
4a29cc2e 14063 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14064 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14065 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14066 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14067#ifdef CONFIG_HIGHMEM
6a35528a 14068 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14069#endif
4a29cc2e 14070 } else
6a35528a 14071 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14072
14073 /* Configure DMA attributes. */
284901a9 14074 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14075 err = pci_set_dma_mask(pdev, dma_mask);
14076 if (!err) {
14077 dev->features |= NETIF_F_HIGHDMA;
14078 err = pci_set_consistent_dma_mask(pdev,
14079 persist_dma_mask);
14080 if (err < 0) {
14081 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14082 "DMA for consistent allocations\n");
14083 goto err_out_iounmap;
14084 }
14085 }
14086 }
284901a9
YH		 14087 if (err || dma_mask == DMA_BIT_MASK(32)) {
14088 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14089 if (err) {
14090 printk(KERN_ERR PFX "No usable DMA configuration, "
14091 "aborting.\n");
14092 goto err_out_iounmap;
14093 }
14094 }
14095
fdfec172 14096 tg3_init_bufmgr_config(tp);
1da177e4 14097
077f849d 14098 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 14099 tp->fw_needed = FIRMWARE_TG3;
077f849d 14100
1da177e4
LT		 14101 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14102 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14103 }
14104 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14106 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 14107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 14108 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14109 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14110 } else {
7f62ad5d 14111 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 14112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 14113 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 14114 else
9e9fd12d 14115 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 14116 }
1da177e4 14117
4e3a7aaa
MC		 14118 /* TSO is on by default on chips that support hardware TSO.
14119 * Firmware TSO on older chips gives lower performance, so it
14120 * is off by default, but can be enabled using ethtool.
14121 */
b0026624 14122 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 14123 if (dev->features & NETIF_F_IP_CSUM)
14124 dev->features |= NETIF_F_TSO;
14125 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14126 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 14127 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 14128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14129 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14130 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 14132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6 14134 dev->features |= NETIF_F_TSO_ECN;
b0026624 14135 }
1da177e4 14136
1da177e4
LT		 14137
14138 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14139 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14140 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14141 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14142 tp->rx_pending = 63;
14143 }
14144
1da177e4
LT		 14145 err = tg3_get_device_address(tp);
14146 if (err) {
14147 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14148 "aborting.\n");
077f849d 14149 goto err_out_fw;
1da177e4
LT		 14150 }
14151
c88864df 14152 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14153 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14154 if (!tp->aperegs) {
c88864df
MC		 14155 printk(KERN_ERR PFX "Cannot map APE registers, "
14156 "aborting.\n");
14157 err = -ENOMEM;
077f849d 14158 goto err_out_fw;
c88864df
MC		 14159 }
14160
14161 tg3_ape_lock_init(tp);
7fd76445
MC		 14162
14163 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14164 tg3_read_dash_ver(tp);
c88864df
MC		 14165 }
14166
1da177e4
LT		 14167 /*
14168 * Reset chip in case UNDI or EFI driver did not shutdown
14169 * DMA self test will enable WDMAC and we'll see (spurious)
14170 * pending DMA on the PCI bus at that point.
14171 */
14172 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14173 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14174 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14175 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14176 }
14177
14178 err = tg3_test_dma(tp);
14179 if (err) {
14180 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14181 goto err_out_apeunmap;
1da177e4
LT		 14182 }
14183
1da177e4
LT		 14184 /* flow control autonegotiation is default behavior */
14185 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14186 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14187
15f9850d
DM		 14188 tg3_init_coal(tp);
14189
c49a1561
MC		 14190 pci_set_drvdata(pdev, dev);
14191
1da177e4
LT		 14192 err = register_netdev(dev);
14193 if (err) {
14194 printk(KERN_ERR PFX "Cannot register net device, "
14195 "aborting.\n");
0d3031d9 14196 goto err_out_apeunmap;
1da177e4
LT		 14197 }
14198
df59c940 14199 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14200 dev->name,
14201 tp->board_part_number,
14202 tp->pci_chip_rev_id,
f9804ddb 14203 tg3_bus_string(tp, str),
e174961c 14204 dev->dev_addr);
1da177e4 14205
3f0e3ad7
MC		 14206 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14207 struct phy_device *phydev;
14208 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14209 printk(KERN_INFO
14210 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14211 tp->dev->name, phydev->drv->name,
14212 dev_name(&phydev->dev));
14213 } else
df59c940
MC		 14214 printk(KERN_INFO
14215 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14216 tp->dev->name, tg3_phy_string(tp),
14217 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14218 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14219 "10/100/1000Base-T")),
14220 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14221
14222 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14223 dev->name,
14224 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14225 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14226 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14227 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14228 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14229 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14230 dev->name, tp->dma_rwctrl,
284901a9 14231 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14232 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14233
14234 return 0;
14235
0d3031d9
MC		 14236err_out_apeunmap:
14237 if (tp->aperegs) {
14238 iounmap(tp->aperegs);
14239 tp->aperegs = NULL;
14240 }
14241
077f849d
JSR		 14242err_out_fw:
14243 if (tp->fw)
14244 release_firmware(tp->fw);
14245
1da177e4 14246err_out_iounmap:
6892914f
MC		 14247 if (tp->regs) {
14248 iounmap(tp->regs);
22abe310 14249 tp->regs = NULL;
6892914f 14250 }
1da177e4
LT		 14251
14252err_out_free_dev:
14253 free_netdev(dev);
14254
14255err_out_free_res:
14256 pci_release_regions(pdev);
14257
14258err_out_disable_pdev:
14259 pci_disable_device(pdev);
14260 pci_set_drvdata(pdev, NULL);
14261 return err;
14262}
14263
14264static void __devexit tg3_remove_one(struct pci_dev *pdev)
14265{
14266 struct net_device *dev = pci_get_drvdata(pdev);
14267
14268 if (dev) {
14269 struct tg3 *tp = netdev_priv(dev);
14270
077f849d
JSR		 14271 if (tp->fw)
14272 release_firmware(tp->fw);
14273
7faa006f 14274 flush_scheduled_work();
158d7abd 14275
b02fd9e3
MC		 14276 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14277 tg3_phy_fini(tp);
158d7abd 14278 tg3_mdio_fini(tp);
b02fd9e3 14279 }
158d7abd 14280
1da177e4 14281 unregister_netdev(dev);
0d3031d9
MC		 14282 if (tp->aperegs) {
14283 iounmap(tp->aperegs);
14284 tp->aperegs = NULL;
14285 }
6892914f
MC		 14286 if (tp->regs) {
14287 iounmap(tp->regs);
22abe310 14288 tp->regs = NULL;
6892914f 14289 }
1da177e4
LT		 14290 free_netdev(dev);
14291 pci_release_regions(pdev);
14292 pci_disable_device(pdev);
14293 pci_set_drvdata(pdev, NULL);
14294 }
14295}
14296
14297static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14298{
14299 struct net_device *dev = pci_get_drvdata(pdev);
14300 struct tg3 *tp = netdev_priv(dev);
12dac075 14301 pci_power_t target_state;
1da177e4
LT		 14302 int err;
14303
3e0c95fd
MC		 14304 /* PCI register 4 needs to be saved whether netif_running() or not.
14305 * MSI address and data need to be saved if using MSI and
14306 * netif_running().
14307 */
14308 pci_save_state(pdev);
14309
1da177e4
LT		 14310 if (!netif_running(dev))
14311 return 0;
14312
7faa006f 14313 flush_scheduled_work();
b02fd9e3 14314 tg3_phy_stop(tp);
1da177e4
LT		 14315 tg3_netif_stop(tp);
14316
14317 del_timer_sync(&tp->timer);
14318
f47c11ee 14319 tg3_full_lock(tp, 1);
1da177e4 14320 tg3_disable_ints(tp);
f47c11ee 14321 tg3_full_unlock(tp);
1da177e4
LT		 14322
14323 netif_device_detach(dev);
14324
f47c11ee 14325 tg3_full_lock(tp, 0);
944d980e 14326 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14327 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14328 tg3_full_unlock(tp);
1da177e4 14329
12dac075
RW		 14330 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14331
14332 err = tg3_set_power_state(tp, target_state);
1da177e4 14333 if (err) {
b02fd9e3
MC		 14334 int err2;
14335
f47c11ee 14336 tg3_full_lock(tp, 0);
1da177e4 14337
6a9eba15 14338 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14339 err2 = tg3_restart_hw(tp, 1);
14340 if (err2)
b9ec6c1b 14341 goto out;
1da177e4
LT		 14342
14343 tp->timer.expires = jiffies + tp->timer_offset;
14344 add_timer(&tp->timer);
14345
14346 netif_device_attach(dev);
14347 tg3_netif_start(tp);
14348
b9ec6c1b 14349out:
f47c11ee 14350 tg3_full_unlock(tp);
b02fd9e3
MC		 14351
14352 if (!err2)
14353 tg3_phy_start(tp);
1da177e4
LT		 14354 }
14355
14356 return err;
14357}
14358
14359static int tg3_resume(struct pci_dev *pdev)
14360{
14361 struct net_device *dev = pci_get_drvdata(pdev);
14362 struct tg3 *tp = netdev_priv(dev);
14363 int err;
14364
3e0c95fd
MC		 14365 pci_restore_state(tp->pdev);
14366
1da177e4
LT		 14367 if (!netif_running(dev))
14368 return 0;
14369
bc1c7567 14370 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14371 if (err)
14372 return err;
14373
14374 netif_device_attach(dev);
14375
f47c11ee 14376 tg3_full_lock(tp, 0);
1da177e4 14377
6a9eba15 14378 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14379 err = tg3_restart_hw(tp, 1);
14380 if (err)
14381 goto out;
1da177e4
LT		 14382
14383 tp->timer.expires = jiffies + tp->timer_offset;
14384 add_timer(&tp->timer);
14385
1da177e4
LT		 14386 tg3_netif_start(tp);
14387
b9ec6c1b 14388out:
f47c11ee 14389 tg3_full_unlock(tp);
1da177e4 14390
b02fd9e3
MC		 14391 if (!err)
14392 tg3_phy_start(tp);
14393
b9ec6c1b 14394 return err;
1da177e4
LT		 14395}
14396
14397static struct pci_driver tg3_driver = {
14398 .name = DRV_MODULE_NAME,
14399 .id_table = tg3_pci_tbl,
14400 .probe = tg3_init_one,
14401 .remove = __devexit_p(tg3_remove_one),
14402 .suspend = tg3_suspend,
14403 .resume = tg3_resume
14404};
14405
14406static int __init tg3_init(void)
14407{
29917620 14408 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14409}
14410
14411static void __exit tg3_cleanup(void)
14412{
14413 pci_unregister_driver(&tg3_driver);
14414}
14415
14416module_init(tg3_init);
14417module_exit(tg3_cleanup);
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